From maarten@treewalker.org Mon May 2 11:48:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 May 2011 11:48:10 +0200 (CEST) Received: from smtp-vbr10.xs4all.nl ([194.109.24.30]:4318 "EHLO smtp-vbr10.xs4all.nl" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491062Ab1EBJsE (ORCPT ); Mon, 2 May 2011 11:48:04 +0200 Received: from starbug-2.trinair2002 (c74072.upc-c.chello.nl [212.187.74.72]) (authenticated bits=0) by smtp-vbr10.xs4all.nl (8.13.8/8.13.8) with ESMTP id p429lnRx064895; Mon, 2 May 2011 11:47:53 +0200 (CEST) (envelope-from maarten@treewalker.org) Received: from hyperion.trinair2002 (hyperion.trinair2002 [192.168.0.43]) by starbug-2.trinair2002 (Postfix) with ESMTP id 9853D44960; Mon, 2 May 2011 11:47:49 +0200 (CEST) From: Maarten ter Huurne To: Ralf Baechle Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Lars-Peter Clausen , Maarten ter Huurne Subject: [PATCH] MIPS: JZ4740: setup: Autodetect physical memory. Date: Mon, 2 May 2011 11:47:00 +0200 Message-Id: <1304329620-17659-1-git-send-email-maarten@treewalker.org> X-Mailer: git-send-email 1.7.3.4 X-Virus-Scanned: by XS4ALL Virus Scanner Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29803 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maarten@treewalker.org Precedence: bulk X-list: linux-mips Assume that the boot loader knows the physical memory of the system and deduce that information from the contents of the SDRAM control register. It is still possible to override with with the "mem=" parameter, but we have a sensible default now. Signed-off-by: Maarten ter Huurne Acked-by: Lars-Peter Clausen --- arch/mips/jz4740/setup.c | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+), 0 deletions(-) diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c index 6a9e14d..d97cfbf 100644 --- a/arch/mips/jz4740/setup.c +++ b/arch/mips/jz4740/setup.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2009-2010, Lars-Peter Clausen + * Copyright (C) 2011, Maarten ter Huurne * JZ4740 setup code * * This program is free software; you can redistribute it and/or modify it @@ -14,13 +15,44 @@ */ #include +#include #include +#include + +#include + #include "reset.h" + +#define JZ4740_EMC_SDRAM_CTRL 0x80 + + +static void __init jz4740_detect_mem(void) +{ + void __iomem *jz_emc_base; + u32 ctrl, bus, bank, rows, cols; + phys_t size; + + jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100); + ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL); + bus = 2 - ((ctrl >> 31) & 1); + bank = 1 + ((ctrl >> 19) & 1); + cols = 8 + ((ctrl >> 26) & 7); + rows = 11 + ((ctrl >> 20) & 3); + printk(KERN_DEBUG + "SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n", + bus, bank, rows, cols); + iounmap(jz_emc_base); + + size = 1 << (bus + bank + cols + rows); + add_memory_region(0, size, BOOT_MEM_RAM); +} + void __init plat_mem_setup(void) { jz4740_reset_init(); + jz4740_detect_mem(); } const char *get_system_type(void) -- 1.7.3.4 From sven@narfation.org Tue May 3 23:31:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 May 2011 23:31:14 +0200 (CEST) Received: from narfation.org ([79.140.41.39]:36705 "EHLO v3-1039.vlinux.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491204Ab1ECVbI (ORCPT ); Tue, 3 May 2011 23:31:08 +0200 Received: from sven-desktop.home.narfation.org (i59F6A5DC.versanet.de [89.246.165.220]) by v3-1039.vlinux.de (Postfix) with ESMTPSA id 65E1B940CF; Tue, 3 May 2011 23:31:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=narfation.org; s=mail; t=1304458277; bh=sQDHl932+uNRI2Fh874hEtx7gcOULgLxW0VHF1muM+0=; h=From:To:Cc:Subject:Date:Message-Id; b=i78kmfj1ByW7IWbIc5ahEgz4ipVHPFLXOnbpGFnVKhS0zx+ZiytLvQslqv1eSHViw mpHtdncePG4Rj+DHvtj8EdEkBsIFM387bkgvSYgCZkzl+5VRkKFzxG1W3sNO4SsdiU h59UuEqv7Rx40otDqQvihycRk0kyLuGesvnmFQ7M= From: Sven Eckelmann To: linux-kernel@vger.kernel.org Cc: Sven Eckelmann , David Howells , Chris Metcalf , x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org Subject: [PATCH] atomic: add *_dec_not_zero Date: Tue, 3 May 2011 23:30:35 +0200 Message-Id: <1304458235-28473-1-git-send-email-sven@narfation.org> X-Mailer: git-send-email 1.7.4.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29804 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sven@narfation.org Precedence: bulk X-list: linux-mips Introduce an *_dec_not_zero operation. Make this a special case of *_add_unless because batman-adv uses atomic_dec_not_zero in different places like re-broadcast queue or aggregation queue management. There are other non-final patches which may also want to use this macro. Reported-by: David S. Miller Signed-off-by: Sven Eckelmann Cc: David Howells Cc: Chris Metcalf Cc: x86@kernel.org Cc: linux-alpha@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: uclinux-dist-devel@blackfin.uclinux.org Cc: linux-cris-kernel@axis.com Cc: linux-ia64@vger.kernel.org Cc: linux-m32r@ml.linux-m32r.org Cc: linux-m68k@lists.linux-m68k.org Cc: linux-mips@linux-mips.org Cc: linux-am33-list@redhat.com Cc: linux-parisc@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-s390@vger.kernel.org Cc: linux-sh@vger.kernel.org Cc: sparclinux@vger.kernel.org Cc: linux-arch@vger.kernel.org --- David S. Miller recommended this change in https://lists.open-mesh.org/pipermail/b.a.t.m.a.n/2011-May/004560.html arch/alpha/include/asm/atomic.h | 2 ++ arch/alpha/include/asm/local.h | 1 + arch/arm/include/asm/atomic.h | 2 ++ arch/avr32/include/asm/atomic.h | 1 + arch/blackfin/include/asm/atomic.h | 1 + arch/cris/include/asm/atomic.h | 1 + arch/frv/include/asm/atomic.h | 1 + arch/h8300/include/asm/atomic.h | 1 + arch/ia64/include/asm/atomic.h | 2 ++ arch/m32r/include/asm/atomic.h | 1 + arch/m32r/include/asm/local.h | 1 + arch/m68k/include/asm/atomic.h | 1 + arch/mips/include/asm/atomic.h | 2 ++ arch/mips/include/asm/local.h | 1 + arch/mn10300/include/asm/atomic.h | 1 + arch/parisc/include/asm/atomic.h | 2 ++ arch/powerpc/include/asm/atomic.h | 2 ++ arch/powerpc/include/asm/local.h | 1 + arch/s390/include/asm/atomic.h | 2 ++ arch/sh/include/asm/atomic.h | 1 + arch/sparc/include/asm/atomic_32.h | 1 + arch/sparc/include/asm/atomic_64.h | 2 ++ arch/tile/include/asm/atomic.h | 9 +++++++++ arch/tile/include/asm/atomic_32.h | 1 + arch/x86/include/asm/atomic.h | 1 + arch/x86/include/asm/atomic64_64.h | 1 + arch/xtensa/include/asm/atomic.h | 1 + include/asm-generic/atomic-long.h | 2 ++ include/asm-generic/atomic.h | 1 + include/asm-generic/atomic64.h | 1 + include/asm-generic/local.h | 1 + include/asm-generic/local64.h | 2 ++ 32 files changed, 50 insertions(+), 0 deletions(-) diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h index e756d04..7e9434e 100644 --- a/arch/alpha/include/asm/atomic.h +++ b/arch/alpha/include/asm/atomic.h @@ -200,6 +200,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) /** * atomic64_add_unless - add unless the number is a given value @@ -226,6 +227,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) } #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0) diff --git a/arch/alpha/include/asm/local.h b/arch/alpha/include/asm/local.h index b9e3e33..09fb327 100644 --- a/arch/alpha/include/asm/local.h +++ b/arch/alpha/include/asm/local.h @@ -79,6 +79,7 @@ static __inline__ long local_sub_return(long i, local_t * l) c != (u); \ }) #define local_inc_not_zero(l) local_add_unless((l), 1, 0) +#define local_dec_not_zero(l) local_add_unless((l), -1, 0) #define local_add_negative(a, l) (local_add_return((a), (l)) < 0) diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 7e79503..a005265 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -218,6 +218,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) return c != u; } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #define atomic_inc(v) atomic_add(1, v) #define atomic_dec(v) atomic_sub(1, v) @@ -459,6 +460,7 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u) #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v)) #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1LL, 0LL) #else /* !CONFIG_GENERIC_ATOMIC64 */ #include diff --git a/arch/avr32/include/asm/atomic.h b/arch/avr32/include/asm/atomic.h index bbce6a1..e6f39c1 100644 --- a/arch/avr32/include/asm/atomic.h +++ b/arch/avr32/include/asm/atomic.h @@ -189,6 +189,7 @@ static inline int atomic_sub_if_positive(int i, atomic_t *v) #define atomic_add_negative(i, v) (atomic_add_return(i, v) < 0) #define atomic_inc_not_zero(v) atomic_add_unless(v, 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v) #define smp_mb__before_atomic_dec() barrier() diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h index e485089..900682e 100644 --- a/arch/blackfin/include/asm/atomic.h +++ b/arch/blackfin/include/asm/atomic.h @@ -103,6 +103,7 @@ static inline int atomic_test_mask(int mask, atomic_t *v) c != (u); \ }) #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) /* * atomic_inc_and_test - increment and test diff --git a/arch/cris/include/asm/atomic.h b/arch/cris/include/asm/atomic.h index 88dc9b9..9db2767 100644 --- a/arch/cris/include/asm/atomic.h +++ b/arch/cris/include/asm/atomic.h @@ -151,6 +151,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) return ret != u; } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) /* Atomic operations are already serializing */ #define smp_mb__before_atomic_dec() barrier() diff --git a/arch/frv/include/asm/atomic.h b/arch/frv/include/asm/atomic.h index fae32c7..90f12a8 100644 --- a/arch/frv/include/asm/atomic.h +++ b/arch/frv/include/asm/atomic.h @@ -257,6 +257,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #include #endif /* _ASM_ATOMIC_H */ diff --git a/arch/h8300/include/asm/atomic.h b/arch/h8300/include/asm/atomic.h index 984221a..eda4c8a 100644 --- a/arch/h8300/include/asm/atomic.h +++ b/arch/h8300/include/asm/atomic.h @@ -117,6 +117,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) return ret != u; } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v) { diff --git a/arch/ia64/include/asm/atomic.h b/arch/ia64/include/asm/atomic.h index 4468814..e2777a9 100644 --- a/arch/ia64/include/asm/atomic.h +++ b/arch/ia64/include/asm/atomic.h @@ -106,6 +106,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) static __inline__ long atomic64_add_unless(atomic64_t *v, long a, long u) { @@ -123,6 +124,7 @@ static __inline__ long atomic64_add_unless(atomic64_t *v, long a, long u) } #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) #define atomic_add_return(i,v) \ ({ \ diff --git a/arch/m32r/include/asm/atomic.h b/arch/m32r/include/asm/atomic.h index d44a51e..4e0b4ec 100644 --- a/arch/m32r/include/asm/atomic.h +++ b/arch/m32r/include/asm/atomic.h @@ -263,6 +263,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) static __inline__ void atomic_clear_mask(unsigned long mask, atomic_t *addr) { diff --git a/arch/m32r/include/asm/local.h b/arch/m32r/include/asm/local.h index 734bca8..d536082 100644 --- a/arch/m32r/include/asm/local.h +++ b/arch/m32r/include/asm/local.h @@ -272,6 +272,7 @@ static inline int local_add_unless(local_t *l, long a, long u) } #define local_inc_not_zero(l) local_add_unless((l), 1, 0) +#define local_dec_not_zero(l) local_add_unless((l), -1, 0) static inline void local_clear_mask(unsigned long mask, local_t *addr) { diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h index 03ae3d1..187a33f 100644 --- a/arch/m68k/include/asm/atomic.h +++ b/arch/m68k/include/asm/atomic.h @@ -199,6 +199,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) /* Atomic operations are already serializing */ #define smp_mb__before_atomic_dec() barrier() diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 4a02fe8..8c4109e 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -326,6 +326,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) return c != (u); } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #define atomic_dec_return(v) atomic_sub_return(1, (v)) #define atomic_inc_return(v) atomic_add_return(1, (v)) @@ -698,6 +699,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) } #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) #define atomic64_dec_return(v) atomic64_sub_return(1, (v)) #define atomic64_inc_return(v) atomic64_add_return(1, (v)) diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h index fffc830..c34d3ca 100644 --- a/arch/mips/include/asm/local.h +++ b/arch/mips/include/asm/local.h @@ -137,6 +137,7 @@ static __inline__ long local_sub_return(long i, local_t * l) c != (u); \ }) #define local_inc_not_zero(l) local_add_unless((l), 1, 0) +#define local_dec_not_zero(l) local_add_unless((l), -1, 0) #define local_dec_return(l) local_sub_return(1, (l)) #define local_inc_return(l) local_add_return(1, (l)) diff --git a/arch/mn10300/include/asm/atomic.h b/arch/mn10300/include/asm/atomic.h index 9d773a6..bcad5d1 100644 --- a/arch/mn10300/include/asm/atomic.h +++ b/arch/mn10300/include/asm/atomic.h @@ -270,6 +270,7 @@ static inline void atomic_dec(atomic_t *v) }) #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) /** * atomic_clear_mask - Atomically clear bits in memory diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h index f819559..c2353cf 100644 --- a/arch/parisc/include/asm/atomic.h +++ b/arch/parisc/include/asm/atomic.h @@ -221,6 +221,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #define atomic_add(i,v) ((void)(__atomic_add_return( (i),(v)))) #define atomic_sub(i,v) ((void)(__atomic_add_return(-(i),(v)))) @@ -335,6 +336,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) } #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) #else /* CONFIG_64BIT */ diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h index b8f152e..906f49a 100644 --- a/arch/powerpc/include/asm/atomic.h +++ b/arch/powerpc/include/asm/atomic.h @@ -213,6 +213,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0) #define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0) @@ -469,6 +470,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) } #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) #else /* __powerpc64__ */ #include diff --git a/arch/powerpc/include/asm/local.h b/arch/powerpc/include/asm/local.h index c2410af..3d4c58a 100644 --- a/arch/powerpc/include/asm/local.h +++ b/arch/powerpc/include/asm/local.h @@ -134,6 +134,7 @@ static __inline__ int local_add_unless(local_t *l, long a, long u) } #define local_inc_not_zero(l) local_add_unless((l), 1, 0) +#define local_dec_not_zero(l) local_add_unless((l), -1, 0) #define local_sub_and_test(a, l) (local_sub_return((a), (l)) == 0) #define local_dec_and_test(l) (local_dec_return((l)) == 0) diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h index d9db138..09972c3 100644 --- a/arch/s390/include/asm/atomic.h +++ b/arch/s390/include/asm/atomic.h @@ -109,6 +109,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #undef __CS_LOOP @@ -326,6 +327,7 @@ static inline long long atomic64_dec_if_positive(atomic64_t *v) #define atomic64_dec_return(_v) atomic64_sub_return(1, _v) #define atomic64_dec_and_test(_v) (atomic64_sub_return(1, _v) == 0) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) #define smp_mb__before_atomic_dec() smp_mb() #define smp_mb__after_atomic_dec() smp_mb() diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h index c798312..848849e 100644 --- a/arch/sh/include/asm/atomic.h +++ b/arch/sh/include/asm/atomic.h @@ -31,6 +31,7 @@ #define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #define atomic_inc(v) atomic_add(1, (v)) #define atomic_dec(v) atomic_sub(1, (v)) diff --git a/arch/sparc/include/asm/atomic_32.h b/arch/sparc/include/asm/atomic_32.h index 7ae128b..c7da1e5 100644 --- a/arch/sparc/include/asm/atomic_32.h +++ b/arch/sparc/include/asm/atomic_32.h @@ -53,6 +53,7 @@ extern void atomic_set(atomic_t *, int); #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0) #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) /* This is the old 24-bit implementation. It's still used internally * by some sparc-specific code, notably the semaphore implementation. diff --git a/arch/sparc/include/asm/atomic_64.h b/arch/sparc/include/asm/atomic_64.h index bdb2ff8..23ad7cf 100644 --- a/arch/sparc/include/asm/atomic_64.h +++ b/arch/sparc/include/asm/atomic_64.h @@ -86,6 +86,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) #define atomic64_cmpxchg(v, o, n) \ ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n))) @@ -107,6 +108,7 @@ static inline long atomic64_add_unless(atomic64_t *v, long a, long u) } #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) /* Atomic operations are already serializing */ #define smp_mb__before_atomic_dec() barrier() diff --git a/arch/tile/include/asm/atomic.h b/arch/tile/include/asm/atomic.h index 75a1602..7fd7be2 100644 --- a/arch/tile/include/asm/atomic.h +++ b/arch/tile/include/asm/atomic.h @@ -130,6 +130,15 @@ static inline int atomic_read(const atomic_t *v) */ #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +/** + * atomic_dec_not_zero - decrement unless the number is zero + * @v: pointer of type atomic_t + * + * Atomically decrement @v by 1, so long as @v is non-zero. + * Returns non-zero if @v was non-zero, and zero otherwise. + */ +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) + /* * We define xchg() and cmpxchg() in the included headers. diff --git a/arch/tile/include/asm/atomic_32.h b/arch/tile/include/asm/atomic_32.h index ed359aee..43137bd 100644 --- a/arch/tile/include/asm/atomic_32.h +++ b/arch/tile/include/asm/atomic_32.h @@ -243,6 +243,7 @@ static inline void atomic64_set(atomic64_t *v, u64 n) #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v)) #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1LL, 0LL) /* * We need to barrier before modifying the word, since the _atomic_xxx() diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h index 952a826..7102a0b 100644 --- a/arch/x86/include/asm/atomic.h +++ b/arch/x86/include/asm/atomic.h @@ -245,6 +245,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) /* * atomic_dec_if_positive - decrement by 1 if old value positive diff --git a/arch/x86/include/asm/atomic64_64.h b/arch/x86/include/asm/atomic64_64.h index 49fd1ea..2cb37f4 100644 --- a/arch/x86/include/asm/atomic64_64.h +++ b/arch/x86/include/asm/atomic64_64.h @@ -220,6 +220,7 @@ static inline int atomic64_add_unless(atomic64_t *v, long a, long u) } #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) /* * atomic64_dec_if_positive - decrement by 1 if old value positive diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h index a96a061..3b2a7b3 100644 --- a/arch/xtensa/include/asm/atomic.h +++ b/arch/xtensa/include/asm/atomic.h @@ -249,6 +249,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) { diff --git a/include/asm-generic/atomic-long.h b/include/asm-generic/atomic-long.h index b7babf0..0fe75ab 100644 --- a/include/asm-generic/atomic-long.h +++ b/include/asm-generic/atomic-long.h @@ -130,6 +130,7 @@ static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) } #define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l)) +#define atomic_long_dec_not_zero(l) atomic64_dec_not_zero((atomic64_t *)(l)) #define atomic_long_cmpxchg(l, old, new) \ (atomic64_cmpxchg((atomic64_t *)(l), (old), (new))) @@ -247,6 +248,7 @@ static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) } #define atomic_long_inc_not_zero(l) atomic_inc_not_zero((atomic_t *)(l)) +#define atomic_long_dec_not_zero(l) atomic_dec_not_zero((atomic_t *)(l)) #define atomic_long_cmpxchg(l, old, new) \ (atomic_cmpxchg((atomic_t *)(l), (old), (new))) diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h index e994197..4e1d3ef 100644 --- a/include/asm-generic/atomic.h +++ b/include/asm-generic/atomic.h @@ -139,6 +139,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) { diff --git a/include/asm-generic/atomic64.h b/include/asm-generic/atomic64.h index b18ce4f..f301c46 100644 --- a/include/asm-generic/atomic64.h +++ b/include/asm-generic/atomic64.h @@ -38,5 +38,6 @@ extern int atomic64_add_unless(atomic64_t *v, long long a, long long u); #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v)) #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL) +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1LL, 0LL) #endif /* _ASM_GENERIC_ATOMIC64_H */ diff --git a/include/asm-generic/local.h b/include/asm-generic/local.h index c8a5d68..82ef01f 100644 --- a/include/asm-generic/local.h +++ b/include/asm-generic/local.h @@ -44,6 +44,7 @@ typedef struct #define local_xchg(l, n) atomic_long_xchg((&(l)->a), (n)) #define local_add_unless(l, _a, u) atomic_long_add_unless((&(l)->a), (_a), (u)) #define local_inc_not_zero(l) atomic_long_inc_not_zero(&(l)->a) +#define local_dec_not_zero(l) atomic_long_dec_not_zero(&(l)->a) /* Non-atomic variants, ie. preemption disabled and won't be touched * in interrupt, etc. Some archs can optimize this case well. */ diff --git a/include/asm-generic/local64.h b/include/asm-generic/local64.h index 02ac760..aa3a841 100644 --- a/include/asm-generic/local64.h +++ b/include/asm-generic/local64.h @@ -45,6 +45,7 @@ typedef struct { #define local64_xchg(l, n) local_xchg((&(l)->a), (n)) #define local64_add_unless(l, _a, u) local_add_unless((&(l)->a), (_a), (u)) #define local64_inc_not_zero(l) local_inc_not_zero(&(l)->a) +#define local64_dec_not_zero(l) local_dec_not_zero(&(l)->a) /* Non-atomic variants, ie. preemption disabled and won't be touched * in interrupt, etc. Some archs can optimize this case well. */ @@ -83,6 +84,7 @@ typedef struct { #define local64_xchg(l, n) atomic64_xchg((&(l)->a), (n)) #define local64_add_unless(l, _a, u) atomic64_add_unless((&(l)->a), (_a), (u)) #define local64_inc_not_zero(l) atomic64_inc_not_zero(&(l)->a) +#define local64_dec_not_zero(l) atomic64_dec_not_zero(&(l)->a) /* Non-atomic variants, ie. preemption disabled and won't be touched * in interrupt, etc. Some archs can optimize this case well. */ -- 1.7.4.4 From vapier.adi@gmail.com Wed May 4 06:45:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 06:45:20 +0200 (CEST) Received: from mail-gx0-f177.google.com ([209.85.161.177]:41101 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490954Ab1EDEpN convert rfc822-to-8bit (ORCPT ); Wed, 4 May 2011 06:45:13 +0200 Received: by gxk2 with SMTP id 2so326882gxk.36 for ; Tue, 03 May 2011 21:45:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type:content-transfer-encoding; bh=SiHOHYPZplxYzEe1LV2HgbIkftjZmwJhiWkX9LoI13U=; b=SNmqV5qgB2uXNQyKPzcXfz+LFZEGWu4nQ0EyWbUhb7jpmMlcQFmt0aJcpDVzBh1q1e oKji0WXKLGALASK9TVCwnvoZapnFfducKJenfPgED4DIs9JT7Tvw0qXzvirkzDjv/S0G IhE7KtTHEFIPOYtsekS9WC3lCgt7DDliN1h5I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=P3q/LtiLXRDW5M9apfXqtpa0o1NGigAbH1bVHFdu+pPiKJ2tRE+akDw5nhKqNVQehj zft90B72mafT9ujrLEIfKmtWkWc6dWOiPnf3AFNPO1vEq5mJfSeBAWo76EfKYtror2gd mx3OZe9TRn8uRvt37KE3JCv8K0um3Iwr6Ghg0= Received: by 10.91.24.4 with SMTP id b4mr699396agj.34.1304484307079; Tue, 03 May 2011 21:45:07 -0700 (PDT) MIME-Version: 1.0 Received: by 10.91.19.32 with HTTP; Tue, 3 May 2011 21:44:46 -0700 (PDT) In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> From: Mike Frysinger Date: Wed, 4 May 2011 00:44:46 -0400 Message-ID: Subject: Re: [PATCH] atomic: add *_dec_not_zero To: Sven Eckelmann Cc: linux-kernel@vger.kernel.org, David Howells , Chris Metcalf , x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29805 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vapier.adi@gmail.com Precedence: bulk X-list: linux-mips On Tue, May 3, 2011 at 17:30, Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation.  Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. > > Cc: uclinux-dist-devel@blackfin.uclinux.org > > --- a/arch/blackfin/include/asm/atomic.h > +++ b/arch/blackfin/include/asm/atomic.h > @@ -103,6 +103,7 @@ static inline int atomic_test_mask(int mask, atomic_t *v) > c != (u); \ > }) > #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) > +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) > > /* > * atomic_inc_and_test - increment and test no opinion on the actual idea, but for the Blackfin pieces: Acked-by: Mike Frysinger -mike From davem@davemloft.net Wed May 4 08:13:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 08:13:33 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:51079 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490953Ab1EDGNa (ORCPT ); Wed, 4 May 2011 08:13:30 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 7D0A024C089; Tue, 3 May 2011 23:12:55 -0700 (PDT) Date: Tue, 03 May 2011 23:12:55 -0700 (PDT) Message-Id: <20110503.231255.115931602.davem@davemloft.net> To: sven@narfation.org Cc: linux-kernel@vger.kernel.org, dhowells@redhat.com, cmetcalf@tilera.com, x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH] atomic: add *_dec_not_zero From: David Miller In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29806 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Sven Eckelmann Date: Tue, 3 May 2011 23:30:35 +0200 > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. > > Reported-by: David S. Miller > Signed-off-by: Sven Eckelmann Acked-by: David S. Miller From mingo@elte.hu Wed May 4 09:03:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 09:03:42 +0200 (CEST) Received: from mx2.mail.elte.hu ([157.181.151.9]:52107 "EHLO mx2.mail.elte.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490954Ab1EDHDk (ORCPT ); Wed, 4 May 2011 09:03:40 +0200 Received: from elvis.elte.hu ([157.181.1.14]) by mx2.mail.elte.hu with esmtp (Exim) id 1QHW7D-0005sK-Eh from ; Wed, 04 May 2011 09:03:25 +0200 Received: by elvis.elte.hu (Postfix, from userid 1004) id 76EEA3E2510; Wed, 4 May 2011 09:03:11 +0200 (CEST) Date: Wed, 4 May 2011 09:03:12 +0200 From: Ingo Molnar To: Sven Eckelmann Cc: linux-kernel@vger.kernel.org, David Howells , Chris Metcalf , x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH] atomic: add *_dec_not_zero Message-ID: <20110504070312.GD20828@elte.hu> References: <1304458235-28473-1-git-send-email-sven@narfation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> User-Agent: Mutt/1.5.20 (2009-08-17) Received-SPF: neutral (mx2.mail.elte.hu: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-SpamScore: -2.0 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=-2.0 required=5.9 tests=BAYES_00 autolearn=no SpamAssassin version=3.3.1 -2.0 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29807 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips * Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. > arch/x86/include/asm/atomic.h | 1 + > arch/x86/include/asm/atomic64_64.h | 1 + Acked-by: Ingo Molnar Thanks, Ingo From David.Laight@ACULAB.COM Wed May 4 10:06:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 10:07:00 +0200 (CEST) Received: from mx0.aculab.com ([213.249.233.131]:36997 "HELO mx0.aculab.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1490983Ab1EDIG4 convert rfc822-to-8bit (ORCPT ); Wed, 4 May 2011 10:06:56 +0200 Received: (qmail 2805 invoked from network); 4 May 2011 08:06:45 -0000 Received: from localhost (127.0.0.1) by mx0.aculab.com with SMTP; 4 May 2011 08:06:45 -0000 Received: from mx0.aculab.com ([127.0.0.1]) by localhost (mx0.aculab.com [127.0.0.1]) (amavisd-new, port 10024) with SMTP id 00592-02 for ; Wed, 4 May 2011 09:06:44 +0100 (BST) Received: (qmail 2712 invoked by uid 599); 4 May 2011 08:06:43 -0000 Received: from unknown (HELO saturn3.Aculab.com) (10.202.163.5) by mx0.aculab.com (qpsmtpd/0.28) with ESMTP; Wed, 04 May 2011 09:06:43 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH] atomic: add *_dec_not_zero Date: Wed, 4 May 2011 09:05:53 +0100 Message-ID: In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] atomic: add *_dec_not_zero Thread-Index: AcwJ3EAltH6AZTKdQ3qO9QnukRcgpAAVa6Mw From: "David Laight" To: "Sven Eckelmann" , Cc: , , , , , , , , , "Chris Metcalf" , "David Howells" , , , , , , , X-Virus-Scanned: by iCritical at mx0.aculab.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29808 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: David.Laight@ACULAB.COM Precedence: bulk X-list: linux-mips > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. Isn't there a place where a default definition of this can be defined? Instead of adding it separately to every architecture. David From sven@narfation.org Wed May 4 10:21:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 10:21:43 +0200 (CEST) Received: from narfation.org ([79.140.41.39]:33695 "EHLO v3-1039.vlinux.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490984Ab1EDIVj (ORCPT ); Wed, 4 May 2011 10:21:39 +0200 Received: from sven-laptop.home.narfation.org (bathseba.informatik.tu-chemnitz.de [134.109.192.185]) by v3-1039.vlinux.de (Postfix) with ESMTPSA id 2E300940CF; Wed, 4 May 2011 10:21:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=narfation.org; s=mail; t=1304497298; bh=8KC/VAUU532yNdFbGxPYeuJANlG8AfOjjawVUtjP0rs=; h=From:To:Subject:Date:Cc:References:In-Reply-To:MIME-Version: Content-Type:Content-Transfer-Encoding:Message-Id; b=NsSunp2Mfpofv5VUKaQUK7rWXK3J92ip8xpFeDvZbhcyptSDVpa+doQoWFVdCUqrM gscCgcXf7UIpcMmBaiE0nUxvcPMaD8/vRWL942MKxyy8XS27AAj55C0Wc4Mnl9lh9r ZPv82XsaqDx+84OOvGT/o1M5WBCwKapSJgkfx0gE= From: Sven Eckelmann To: "David Laight" Subject: Re: [PATCH] atomic: add *_dec_not_zero Date: Wed, 4 May 2011 10:21:16 +0200 User-Agent: KMail/1.13.5 (Linux/2.6.38-2-686; KDE/4.4.5; i686; ; ) Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mips@linux-mips.org, linux-m32r@ml.linux-m32r.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org, linux-cris-kernel@axis.com, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, x86@kernel.org, "Chris Metcalf" , "David Howells" , linux-m68k@lists.linux-m68k.org, linux-am33-list@redhat.com, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org References: In-Reply-To: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart2868987.P04i5ibDgT"; protocol="application/pgp-signature"; micalg=pgp-sha512 Content-Transfer-Encoding: 7bit Message-Id: <201105041021.22082.sven@narfation.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29809 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sven@narfation.org Precedence: bulk X-list: linux-mips --nextPart2868987.P04i5ibDgT Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable On Wednesday 04 May 2011 10:05:53 David Laight wrote: > > Introduce an *_dec_not_zero operation. Make this a special case of > > *_add_unless because batman-adv uses atomic_dec_not_zero in different > > places like re-broadcast queue or aggregation queue management. There > > are other non-final patches which may also want to use this macro. >=20 > Isn't there a place where a default definition of this can be > defined? Instead of adding it separately to every architecture. Not that I would know about such a place - and all other atomic* macro=20 definitions also suggest that there is no such place. Kind regards, Sven --nextPart2868987.P04i5ibDgT Content-Type: application/pgp-signature; name=signature.asc Content-Description: This is a digitally signed message part. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCgAGBQJNwQx+AAoJEF2HCgfBJntGRUwQAKpZ3vas4MhN1cUHPC7peYuT VyMmy/osbr9OqHAvxVB80ZjA8lwG2OjOeB5RbJFfHIcfdC/VLAyWF0o1i8jYBYLf qlkDuM1jRBLK7NJSmHBoTIm+zKVjQJm1cJW1qjhWqDr+tmbeHReJxmHX7uewO6bH 98rXwt2tqdZk621b1Z6pZCbLZZODQwLTejS10FDs5rT4wZztimpXGQRSjdoc0ENP k4TX9Y8Uwac6yLA9jlgXhHzAe0iu+x9l89x1euq6Uerkax2HB0Y6YpdH97/SfxpD eHSIgOFN8+o6WWblKOSTbDJqz0kjdvi/Wcj5mfs2YpScxE1UbEhK04Q918TWScyG ysiycLfHrmBl+zQ6hTGveXd96M85XNlYkSIQZR48e2vSHUycF8Busv7UUTF0xnmW 2hl1svdX6p3IXMEUtYDBX7iSlEtmDe+V8bG0Ftw1nJ4cqNn4Xbp3WUSQn1qUwo1H FwbQfFOTkzy02nWJvYpARHgTKnztbgGvC2XKWY4AtAF2WRBxmBbUTtzau9VqACzH 5I/9X63DnNo+V/yTIKps03+CyXIys/QdrsN2NaP/iEUEwz/8wVyRT4HgdYQO1nTs e7amjs4tEW+oduDnRsPbnczSwy0lOHkVPuwiPgEA8S+WRbU5miS56u+nLDB+y/kh u3hzuBSc64RKiJMEccmv =JUtM -----END PGP SIGNATURE----- --nextPart2868987.P04i5ibDgT-- From vapier.adi@gmail.com Wed May 4 10:33:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 10:33:58 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:48127 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490984Ab1EDIdu convert rfc822-to-8bit (ORCPT ); Wed, 4 May 2011 10:33:50 +0200 Received: by gwb1 with SMTP id 1so360704gwb.36 for ; Wed, 04 May 2011 01:33:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type:content-transfer-encoding; bh=ZjYSQ3FUv2Mh+C2C8y6rq/DkVU0IKBkQeY8EgZl9N+E=; b=JmKIltEPoJoMs5Ywot7vURXXM+ZorhWQ8uB+yucxRNvkd/WAnP7MOjR+NOo76BHiy9 +ipOg425jJhQfQr5pCXWyB4r9XRaRuk24Vyah/jrRdDmqnHbomG/2C+yYEBt7R9G0TaI FAQuLqzfOJ2G24RMUlqrZy8UIkGDpfXvfEHQg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=uanrApxMmwvwo06Bya8A+hoAytG/7rvDHGRTiJ6gM4NcPb8GrRCxxCEZVqV+NefZIh tMZ3nZfZ9IOygsVFM54NwGXSo2KoH5M6K3Cvb+Yamq0UsiAVit+ph/jS2/zWs5iSvWVY tPDc/6Npmb8IBen8P0+4SZf8JgHA179qhyxqY= Received: by 10.90.188.16 with SMTP id l16mr789544agf.88.1304498024192; Wed, 04 May 2011 01:33:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.91.19.32 with HTTP; Wed, 4 May 2011 01:33:24 -0700 (PDT) In-Reply-To: References: <1304458235-28473-1-git-send-email-sven@narfation.org> From: Mike Frysinger Date: Wed, 4 May 2011 04:33:24 -0400 Message-ID: Subject: Re: [PATCH] atomic: add *_dec_not_zero To: David Laight Cc: Sven Eckelmann , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mips@linux-mips.org, linux-m32r@ml.linux-m32r.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org, linux-cris-kernel@axis.com, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, x86@kernel.org, Chris Metcalf , David Howells , linux-m68k@lists.linux-m68k.org, linux-am33-list@redhat.com, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29810 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vapier.adi@gmail.com Precedence: bulk X-list: linux-mips On Wed, May 4, 2011 at 04:05, David Laight wrote: >> Introduce an *_dec_not_zero operation.  Make this a special case of >> *_add_unless because batman-adv uses atomic_dec_not_zero in different >> places like re-broadcast queue or aggregation queue management. There >> are other non-final patches which may also want to use this macro. > > Isn't there a place where a default definition of this can be > defined? Instead of adding it separately to every architecture. that's what asm-generic is for. if the arch isnt using it, it's either because the arch needs to convert to it, or they're using SMP and asm-generic doesnt yet support that for atomic.h. for example, the Blackfin port only needed updating for the SMP case. in the non-SMP case, we're getting the def from asm-generic/atomic.h. -mike From jesper.nilsson@axis.com Wed May 4 12:48:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 12:48:57 +0200 (CEST) Received: from anubis.se.axis.com ([195.60.68.12]:46258 "EHLO anubis.se.axis.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490984Ab1EDKsy (ORCPT ); Wed, 4 May 2011 12:48:54 +0200 Received: from localhost (localhost [127.0.0.1]) by anubis.se.axis.com (Postfix) with ESMTP id E9AD819DC6; Wed, 4 May 2011 12:48:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at anubis.se.axis.com Received: from anubis.se.axis.com ([127.0.0.1]) by localhost (anubis.se.axis.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id tgeP7vRDzl5S; Wed, 4 May 2011 12:48:47 +0200 (CEST) Received: from seth.se.axis.com (seth.se.axis.com [10.0.2.172]) by anubis.se.axis.com (Postfix) with ESMTP id 2D0C919D9A; Wed, 4 May 2011 12:48:45 +0200 (CEST) Received: from silver.se.axis.com (silver.se.axis.com [10.88.4.3]) by seth.se.axis.com (Postfix) with ESMTP id EF5EF3E13C; Wed, 4 May 2011 12:48:45 +0200 (CEST) Received: from silver.se.axis.com (localhost [127.0.0.1]) by silver.se.axis.com (8.14.3/8.14.3/Debian-5+lenny1) with ESMTP id p44AmjRg024638; Wed, 4 May 2011 12:48:45 +0200 Received: (from jespern@localhost) by silver.se.axis.com (8.14.3/8.14.3/Submit) id p44AmfPQ024637; Wed, 4 May 2011 12:48:41 +0200 Date: Wed, 4 May 2011 12:48:41 +0200 From: Jesper Nilsson To: Sven Eckelmann Cc: "linux-kernel@vger.kernel.org" , "linux-arch@vger.kernel.org" , "linux-mips@linux-mips.org" , "linux-m32r@ml.linux-m32r.org" , "linux-ia64@vger.kernel.org" , "linux-parisc@vger.kernel.org" , linux-cris-kernel , "linux-s390@vger.kernel.org" , "linux-sh@vger.kernel.org" , "x86@kernel.org" , Chris Metcalf , David Howells , "linux-m68k@lists.linux-m68k.org" , "linux-am33-list@redhat.com" , "linux-alpha@vger.kernel.org" , "sparclinux@vger.kernel.org" , "uclinux-dist-devel@blackfin.uclinux.org" , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH] atomic: add *_dec_not_zero Message-ID: <20110504104841.GE16179@axis.com> References: <1304458235-28473-1-git-send-email-sven@narfation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29811 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jesper.nilsson@axis.com Precedence: bulk X-list: linux-mips On Tue, May 03, 2011 at 11:30:35PM +0200, Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. For the CRIS-part: Acked-by: Jesper Nilsson /^JN - Jesper Nilsson -- Jesper Nilsson -- jesper.nilsson@axis.com From ralf@linux-mips.org Wed May 4 13:06:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 13:06:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:39130 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491102Ab1EDLF7 (ORCPT ); Wed, 4 May 2011 13:05:59 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p44B2BXU005150; Wed, 4 May 2011 12:02:12 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p44B27JV005143; Wed, 4 May 2011 12:02:07 +0100 Date: Wed, 4 May 2011 12:02:07 +0100 From: Ralf Baechle To: Sven Eckelmann Cc: linux-kernel@vger.kernel.org, David Howells , Chris Metcalf , x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH] atomic: add *_dec_not_zero Message-ID: <20110504110207.GA4243@linux-mips.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, May 03, 2011 at 11:30:35PM +0200, Sven Eckelmann wrote: > arch/mips/include/asm/atomic.h | 2 ++ > arch/mips/include/asm/local.h | 1 + Acked-by: Ralf Baechle Ralf From dhowells@redhat.com Wed May 4 13:54:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 13:54:26 +0200 (CEST) Received: from mx1.redhat.com ([209.132.183.28]:25485 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490998Ab1EDLyW (ORCPT ); Wed, 4 May 2011 13:54:22 +0200 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p44BrZVY020695 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 4 May 2011 07:53:35 -0400 Received: from redhat.com ([10.3.112.17]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p44BrKwt021393; Wed, 4 May 2011 07:53:21 -0400 Organization: Red Hat UK Ltd. Registered Address: Red Hat UK Ltd, Amberley Place, 107-111 Peascod Street, Windsor, Berkshire, SI4 1TE, United Kingdom. Registered in England and Wales under Company Registration No. 3798903 From: David Howells In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> To: Sven Eckelmann Cc: dhowells@redhat.com, linux-kernel@vger.kernel.org, Chris Metcalf , x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH] atomic: add *_dec_not_zero Date: Wed, 04 May 2011 12:53:19 +0100 Message-ID: <20684.1304509999@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhowells@redhat.com Precedence: bulk X-list: linux-mips Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. > > Reported-by: David S. Miller > Signed-off-by: Sven Eckelmann Acked-by: David Howells [MN10300 and FRV] From cmetcalf@tilera.com Wed May 4 14:09:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 14:09:32 +0200 (CEST) Received: from usmamail.tilera.com ([206.83.70.75]:62377 "EHLO USMAMAIL.TILERA.COM" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490998Ab1EDMJ3 (ORCPT ); Wed, 4 May 2011 14:09:29 +0200 Received: from [127.0.0.1] (24.34.76.130) by USMAExch2.tad.internal.tilera.com (10.3.0.33) with Microsoft SMTP Server id 14.0.694.0; Wed, 4 May 2011 08:09:20 -0400 Message-ID: <4DC141EC.5050406@tilera.com> Date: Wed, 4 May 2011 08:09:16 -0400 From: Chris Metcalf User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 To: Sven Eckelmann CC: , David Howells , , , , , , , , , , , , , , , , Subject: Re: [PATCH] atomic: add *_dec_not_zero References: <1304458235-28473-1-git-send-email-sven@narfation.org> In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cmetcalf@tilera.com Precedence: bulk X-list: linux-mips On 5/3/2011 5:30 PM, Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. > > Reported-by: David S. Miller > Signed-off-by: Sven Eckelmann > [...] > arch/tile/include/asm/atomic.h | 9 +++++++++ > arch/tile/include/asm/atomic_32.h | 1 + Acked-by: Chris Metcalf -- Chris Metcalf, Tilera Corp. http://www.tilera.com From geert.uytterhoeven@gmail.com Wed May 4 14:17:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 14:18:02 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:61436 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491051Ab1EDMR5 convert rfc822-to-8bit (ORCPT ); Wed, 4 May 2011 14:17:57 +0200 Received: by bwz1 with SMTP id 1so1179861bwz.36 for ; Wed, 04 May 2011 05:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=3ERi4Yv6QUYVc9R1ygD5GOUKWvs/8X1wolS/oEDmci8=; b=rWTmL+qKC4a25Wby1kavCPeOcCVKBrRxXfruVvrbhM0WbjKQEJr8suEL3oJd9CI4UN C1VBQchDRocSM98CXvhG8cXSI0pNApuOzFUcd2zth2iSdh906QIiqzjVlCFkQbT22ah9 olopGzojadjlBa+DpwOwDi+Da8mISa3qcH1zc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=f51yaEtpSAU1uXzB0uFikDTsnRzdJs5qeoBFJ5G46lBryxBVESllgxJ3ZNW0Tan/30 1dmZ9s/ahKafyMpm9XKTENrhqMALkR6UFzVX28gXJnkjoy7fqlHCrm2AjpBDIgygAIss gHankU5bqAHPFjeMQJXbuN2/GnUfHN4qWjxyk= MIME-Version: 1.0 Received: by 10.204.0.82 with SMTP id 18mr1025272bka.100.1304511471362; Wed, 04 May 2011 05:17:51 -0700 (PDT) Received: by 10.204.126.154 with HTTP; Wed, 4 May 2011 05:17:51 -0700 (PDT) In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> Date: Wed, 4 May 2011 14:17:51 +0200 X-Google-Sender-Auth: 52Q_K_1bwIVJ1s18yumwIOjW098 Message-ID: Subject: Re: [PATCH] atomic: add *_dec_not_zero From: Geert Uytterhoeven To: Sven Eckelmann Cc: linux-kernel@vger.kernel.org, David Howells , Chris Metcalf , x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Tue, May 3, 2011 at 23:30, Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation.  Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. >  arch/m68k/include/asm/atomic.h     |    1 + Acked-by: Geert Uytterhoeven Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds From James.Bottomley@HansenPartnership.com Wed May 4 17:04:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 17:04:18 +0200 (CEST) Received: from bedivere.hansenpartnership.com ([66.63.167.143]:35979 "EHLO bedivere.hansenpartnership.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491040Ab1EDPEP (ORCPT ); Wed, 4 May 2011 17:04:15 +0200 Received: from localhost (localhost [127.0.0.1]) by bedivere.hansenpartnership.com (Postfix) with ESMTP id 549738EE11E; Wed, 4 May 2011 08:04:07 -0700 (PDT) Received: from bedivere.hansenpartnership.com ([127.0.0.1]) by localhost (bedivere.hansenpartnership.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 73FMpYj8FZQo; Wed, 4 May 2011 08:04:07 -0700 (PDT) Received: from [192.168.2.10] (dagonet.hansenpartnership.com [76.243.235.53]) by bedivere.hansenpartnership.com (Postfix) with ESMTPSA id 988D58EE0BE; Wed, 4 May 2011 08:04:05 -0700 (PDT) Subject: Re: [PATCH] atomic: add *_dec_not_zero From: James Bottomley To: Mike Frysinger Cc: Sven Eckelmann , linux-kernel@vger.kernel.org, David Howells , Chris Metcalf , x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org In-Reply-To: References: <1304458235-28473-1-git-send-email-sven@narfation.org> Content-Type: text/plain; charset="UTF-8" Date: Wed, 04 May 2011 10:04:04 -0500 Message-ID: <1304521444.2810.23.camel@mulgrave.site> Mime-Version: 1.0 X-Mailer: Evolution 2.32.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: James.Bottomley@HansenPartnership.com Precedence: bulk X-list: linux-mips On Wed, 2011-05-04 at 00:44 -0400, Mike Frysinger wrote: > On Tue, May 3, 2011 at 17:30, Sven Eckelmann wrote: > > Introduce an *_dec_not_zero operation. Make this a special case of > > *_add_unless because batman-adv uses atomic_dec_not_zero in different > > places like re-broadcast queue or aggregation queue management. There > > are other non-final patches which may also want to use this macro. > > > > Cc: uclinux-dist-devel@blackfin.uclinux.org > > > > --- a/arch/blackfin/include/asm/atomic.h > > +++ b/arch/blackfin/include/asm/atomic.h > > @@ -103,6 +103,7 @@ static inline int atomic_test_mask(int mask, atomic_t *v) > > c != (u); \ > > }) > > #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) > > +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) > > > > /* > > * atomic_inc_and_test - increment and test > > no opinion on the actual idea, but for the Blackfin pieces: > Acked-by: Mike Frysinger This goes for parisc as well. Acked-by: James Bottomley James From will.deacon@arm.com Wed May 4 19:39:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 19:39:18 +0200 (CEST) Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:50387 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491005Ab1EDRjP (ORCPT ); Wed, 4 May 2011 19:39:15 +0200 Received: from [10.37.7.18] ([10.37.7.18]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id p44HK3F9001742; Wed, 4 May 2011 18:20:03 +0100 (BST) Subject: Re: [PATCH] atomic: add *_dec_not_zero From: Will Deacon To: Sven Eckelmann Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mips@linux-mips.org, linux-m32r@ml.linux-m32r.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org, linux-cris-kernel@axis.com, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, x86@kernel.org, Chris Metcalf , David Howells , linux-m68k@vger.kernel.org, linux-am33-list@redhat.com, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> Content-Type: text/plain; charset="UTF-8" Date: Wed, 04 May 2011 18:27:36 +0100 Message-ID: <1304530056.2296.1.camel@craptop> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29817 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: will.deacon@arm.com Precedence: bulk X-list: linux-mips On Tue, 2011-05-03 at 22:30 +0100, Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. > For the ARM changes: Acked-by: Will Deacon Cheers, Will From mattst88@gmail.com Wed May 4 20:13:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 May 2011 20:13:59 +0200 (CEST) Received: from mail-qy0-f177.google.com ([209.85.216.177]:63315 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491051Ab1EDSN4 convert rfc822-to-8bit (ORCPT ); Wed, 4 May 2011 20:13:56 +0200 Received: by qyl38 with SMTP id 38so1194685qyl.15 for ; Wed, 04 May 2011 11:13:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type:content-transfer-encoding; bh=iV5A6Hdagp0QOu9qzGkatnLVdEWa9xEERC805YIbK2g=; b=ARiNNEFBeZg9hyzUoHdP0qpgjkYWjaSWQMaIpSuOEU7Ng4l7K4+UNxbRFpz5xVYmlr SS1GzoNEMgMriacfqq/3Y7eYm3yx1wMs1NrgDno6vwKjioE9NL7TwgOkTHH9ioGNTZjm axP5fVnpgOk5HzPbAQCD/IPxh8/fyojzipjxA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=cYOJce8VpG868iJ0yzmRyAszW2Fl48ey7hvbXiW1SagCtjGsRA/MsLC5sr2D1GrN6v lY33gIN+ZbD4ljGMpWkvClkczjGlXLdRGW1Dtor7c1IGCIIYb1PQCYhK740p+hMGXtpC Ui6Z6P0EW941i+Z0I0Bn1ZACrUf7hqyjuNYuQ= Received: by 10.229.73.35 with SMTP id o35mr1127247qcj.13.1304532829087; Wed, 04 May 2011 11:13:49 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.18.3 with HTTP; Wed, 4 May 2011 11:13:29 -0700 (PDT) In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> From: Matt Turner Date: Wed, 4 May 2011 14:13:29 -0400 Message-ID: Subject: Re: [PATCH] atomic: add *_dec_not_zero To: Sven Eckelmann Cc: linux-kernel@vger.kernel.org, David Howells , Chris Metcalf , x86@kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips On Tue, May 3, 2011 at 5:30 PM, Sven Eckelmann wrote: > diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h > index e756d04..7e9434e 100644 > --- a/arch/alpha/include/asm/atomic.h > +++ b/arch/alpha/include/asm/atomic.h > @@ -200,6 +200,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) >  } > >  #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) > +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) > >  /** >  * atomic64_add_unless - add unless the number is a given value > @@ -226,6 +227,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) >  } > >  #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) > +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) > >  #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) >  #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0) > diff --git a/arch/alpha/include/asm/local.h b/arch/alpha/include/asm/local.h > index b9e3e33..09fb327 100644 > --- a/arch/alpha/include/asm/local.h > +++ b/arch/alpha/include/asm/local.h > @@ -79,6 +79,7 @@ static __inline__ long local_sub_return(long i, local_t * l) >        c != (u);                                               \ >  }) >  #define local_inc_not_zero(l) local_add_unless((l), 1, 0) > +#define local_dec_not_zero(l) local_add_unless((l), -1, 0) > >  #define local_add_negative(a, l) (local_add_return((a), (l)) < 0) > Acked-by: Matt Turner [alpha] From ralf@linux-mips.org Thu May 5 13:04:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 13:04:26 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49024 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490992Ab1EELET (ORCPT ); Thu, 5 May 2011 13:04:19 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p45B5Ig1029503; Thu, 5 May 2011 12:05:18 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p45B5Giv029498; Thu, 5 May 2011 12:05:16 +0100 Date: Thu, 5 May 2011 12:05:16 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Hibernation: Fixes for PAGE_SIZE >= 64kb Message-ID: <20110505110515.GA29437@linux-mips.org> References: <1303595819-19299-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1303595819-19299-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied! Ralf From ralf@linux-mips.org Thu May 5 13:32:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 13:32:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54174 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490982Ab1EELcI (ORCPT ); Thu, 5 May 2011 13:32:08 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p45BXAkK031737; Thu, 5 May 2011 12:33:10 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p45BX998031735; Thu, 5 May 2011 12:33:09 +0100 Date: Thu, 5 May 2011 12:33:09 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Invalidate old TLB mappings when updating huge page PTEs. Message-ID: <20110505113309.GA30067@linux-mips.org> References: <1303947568-29874-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1303947568-29874-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From David.Daney@caviumnetworks.com Thu May 5 19:02:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:02:52 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14434 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491023Ab1EERCq (ORCPT ); Thu, 5 May 2011 19:02:46 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 05 May 2011 10:03:43 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:42 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:41 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p45H2Y0R030499; Thu, 5 May 2011 10:02:34 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p45H2VhZ030498; Thu, 5 May 2011 10:02:31 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v3 0/6] MIPS: Octeon: Use Device Tree. Date: Thu, 5 May 2011 10:02:23 -0700 Message-Id: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 05 May 2011 17:02:41.0976 (UTC) FILETIME=[3F043B80:01CC0B46] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips After several weeks of fire fighting, I am back to my Octeon device tree patches. New in v3: More updates to device tree bindings, and perhaps more importantly descriptions/definitions of the bindings libfdt building moved to devices/of/libfdt. Cleanup and style improvements as suggested by Grant Likley. Omitted all the driver changes, as they are unchanged from the last set, and at this stage the patches are just an RFC. New in v2: Changed many device tree bindings. They should be closer to the standard naming scheme now. Editing of the template device tree is done in the flattened form using libfdt. Standard platform driver functions used in preference to the of_platform variety. v1: Background: The Octeon family of SOCs has a variety of on-chip controllers for Ethernet, MDIO, I2C, and several other I/O devices. These chips are used on boards with a great variety of different configurations. To date, the configuration and bus topology information has been hard coded in the drivers and support code. To facilitate supporting new chips and boards, we would like to make use use the Device Tree to encode the configuration information. I would like to get some feedback on the current code I am working with. The migration approach is as follows: o Several device tree templates are statically linked into the kernel image. Based on SOC type and board type one of these is selected in early boot. Legacy configuration probing code is used to prune and patch the device tree template. o New SOCs and boards will directly use a device tree passed by the bootloader (This patch set doesn't actually implement this, but it is trivial to add). 1/6 - Infrastructure to allow scripts/dtc/libfdt to be used in the kernel. 2/6 - OF patch to simplify of_find_node_by_path(). 3/6 - Add the statically linked Device Tree templates and bindings descriptions. 4/6 - Remove unused arch/mips/prom.c code that conflicts with following patches. 5/6 - irq_create_of_mapping() function. 6/6 - Fix up Device Tree template for current environment. David Daney (6): of: Allow scripts/dtc/libfdt to be used from kernel code of: Make of_find_node_by_path() traverse /aliases for relative paths. MIPS: Octeon: Add device tree source files. MIPS: Prune some target specific code out of prom.c MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts. MIPS: Octeon: Initialize and fixup device tree. .../devicetree/bindings/mips/cavium/bootbus.txt | 37 ++ .../devicetree/bindings/mips/cavium/ciu.txt | 26 ++ .../devicetree/bindings/mips/cavium/gpio.txt | 48 +++ .../devicetree/bindings/mips/cavium/mdio.txt | 27 ++ .../devicetree/bindings/mips/cavium/mix.txt | 40 ++ .../devicetree/bindings/mips/cavium/pip.txt | 98 +++++ .../devicetree/bindings/mips/cavium/twsi.txt | 34 ++ .../devicetree/bindings/mips/cavium/uart.txt | 19 + .../devicetree/bindings/mips/cavium/uctl.txt | 47 +++ arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 15 + arch/mips/cavium-octeon/octeon-irq.c | 183 ++++++++- arch/mips/cavium-octeon/octeon-platform.c | 295 +++++++++++++ arch/mips/cavium-octeon/octeon_3xxx.dts | 431 ++++++++++++++++++++ arch/mips/cavium-octeon/setup.c | 17 + arch/mips/kernel/prom.c | 49 --- drivers/of/Kconfig | 3 + drivers/of/Makefile | 2 + drivers/of/base.c | 41 ++- drivers/of/libfdt/Makefile | 8 + include/linux/libfdt.h | 8 + include/linux/libfdt_env.h | 13 + 23 files changed, 1393 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/gpio.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/mdio.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/mix.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/pip.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/twsi.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uart.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 drivers/of/libfdt/Makefile create mode 100644 include/linux/libfdt.h create mode 100644 include/linux/libfdt_env.h -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu May 5 19:03:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:03:18 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14440 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491041Ab1EERCq (ORCPT ); Thu, 5 May 2011 19:02:46 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 05 May 2011 10:03:46 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:44 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:44 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p45H2dqX030507; Thu, 5 May 2011 10:02:39 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p45H2b4V030506; Thu, 5 May 2011 10:02:37 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v3 1/6] of: Allow scripts/dtc/libfdt to be used from kernel code Date: Thu, 5 May 2011 10:02:24 -0700 Message-Id: <1304614949-30460-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 05 May 2011 17:02:44.0382 (UTC) FILETIME=[40735BE0:01CC0B46] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips To use it you need to do this in your Kconfig: select LIBFDT And in the Makefile of the code using libfdt something like: ccflags-y := -include linux/libfdt_env.h -I$(src)/../../../scripts/dtc/libfdt Signed-off-by: David Daney --- drivers/of/Kconfig | 3 +++ drivers/of/Makefile | 2 ++ drivers/of/libfdt/Makefile | 8 ++++++++ include/linux/libfdt.h | 8 ++++++++ include/linux/libfdt_env.h | 13 +++++++++++++ 5 files changed, 34 insertions(+), 0 deletions(-) create mode 100644 drivers/of/libfdt/Makefile create mode 100644 include/linux/libfdt.h create mode 100644 include/linux/libfdt_env.h diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index d06a637..9b0474e 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -4,6 +4,9 @@ config DTC config OF bool +config LIBFDT + bool + menu "Device Tree and Open Firmware support" depends on OF diff --git a/drivers/of/Makefile b/drivers/of/Makefile index f7861ed..a8dec2f 100644 --- a/drivers/of/Makefile +++ b/drivers/of/Makefile @@ -10,3 +10,5 @@ obj-$(CONFIG_OF_NET) += of_net.o obj-$(CONFIG_OF_SPI) += of_spi.o obj-$(CONFIG_OF_MDIO) += of_mdio.o obj-$(CONFIG_OF_PCI) += of_pci.o + +obj-$(CONFIG_LIBFDT) += libfdt/ diff --git a/drivers/of/libfdt/Makefile b/drivers/of/libfdt/Makefile new file mode 100644 index 0000000..bda11fe --- /dev/null +++ b/drivers/of/libfdt/Makefile @@ -0,0 +1,8 @@ +ccflags-y := -include linux/libfdt_env.h -I$(src)/../../../scripts/dtc/libfdt + +obj-y = fdt.o fdt_wip.o fdt_ro.o + + +$(obj)/%.o: $(src)/../../../scripts/dtc/libfdt/%.c FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h new file mode 100644 index 0000000..4c0306c --- /dev/null +++ b/include/linux/libfdt.h @@ -0,0 +1,8 @@ +#ifndef _INCLUDE_LIBFDT_H_ +#define _INCLUDE_LIBFDT_H_ + +#include +#include "../../scripts/dtc/libfdt/fdt.h" +#include "../../scripts/dtc/libfdt/libfdt.h" + +#endif /* _INCLUDE_LIBFDT_H_ */ diff --git a/include/linux/libfdt_env.h b/include/linux/libfdt_env.h new file mode 100644 index 0000000..01508c7 --- /dev/null +++ b/include/linux/libfdt_env.h @@ -0,0 +1,13 @@ +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H + +#include + +#include + +#define fdt32_to_cpu(x) be32_to_cpu(x) +#define cpu_to_fdt32(x) cpu_to_be32(x) +#define fdt64_to_cpu(x) be64_to_cpu(x) +#define cpu_to_fdt64(x) cpu_to_be64(x) + +#endif /* _LIBFDT_ENV_H */ -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu May 5 19:03:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:03:43 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14452 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491052Ab1EERCt (ORCPT ); Thu, 5 May 2011 19:02:49 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 05 May 2011 10:03:48 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:47 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:47 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p45H2eKF030512; Thu, 5 May 2011 10:02:41 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p45H2ePj030510; Thu, 5 May 2011 10:02:40 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v3 2/6] of: Make of_find_node_by_path() traverse /aliases for relative paths. Date: Thu, 5 May 2011 10:02:25 -0700 Message-Id: <1304614949-30460-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 05 May 2011 17:02:47.0194 (UTC) FILETIME=[42206FA0:01CC0B46] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Currently all paths passed to of_find_node_by_path() must begin with a '/', indicating a full path to the desired node. Augment the look-up code so that if a path does *not* begin with '/', the path is used as the name of an /aliases property. The value of this alias is then used as the full node path to be found. Signed-off-by: David Daney --- drivers/of/base.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 files changed, 40 insertions(+), 1 deletions(-) diff --git a/drivers/of/base.c b/drivers/of/base.c index 632ebae..1a0a83e 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -340,7 +340,10 @@ EXPORT_SYMBOL(of_get_next_child); /** * of_find_node_by_path - Find a node matching a full OF path - * @path: The full path to match + * @path: Either the full path to match, or if the path does not + * start with '/', the name of a property of the /aliases + * node (an alias). In the case of an alias, the node + * matching the alias' value will be returned. * * Returns a node pointer with refcount incremented, use * of_node_put() on it when done. @@ -348,14 +351,50 @@ EXPORT_SYMBOL(of_get_next_child); struct device_node *of_find_node_by_path(const char *path) { struct device_node *np = allnodes; + struct device_node *aliases = NULL; + char *alias = NULL; + char *new_path = NULL; read_lock(&devtree_lock); + + if (path[0] != '/') { + const char *ps; + aliases = of_find_node_by_path("/aliases"); + if (!aliases) + goto out; + + ps = strchr(path, '/'); + if (ps) { + size_t len = ps - path; + alias = kmalloc(len + 1, GFP_KERNEL); + strncpy(alias, path, len); + alias[len] = 0; + path = of_get_property(aliases, alias, NULL); + if (!path) + goto out; + len = strlen(path) + strlen(ps) + 1; + new_path = kmalloc(len, GFP_KERNEL); + strcpy(new_path, path); + strcat(new_path, ps); + path = new_path; + } else { + path = of_get_property(aliases, path, NULL); + } + if (!path) + goto out; + } + for (; np; np = np->allnext) { if (np->full_name && (of_node_cmp(np->full_name, path) == 0) && of_node_get(np)) break; } +out: + if (aliases) + of_node_put(aliases); read_unlock(&devtree_lock); + kfree(alias); + kfree(new_path); return np; } EXPORT_SYMBOL(of_find_node_by_path); -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu May 5 19:04:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:04:08 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14448 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491756Ab1EERCt (ORCPT ); Thu, 5 May 2011 19:02:49 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 05 May 2011 10:03:48 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:47 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:47 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p45H2iXv030520; Thu, 5 May 2011 10:02:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p45H2hM1030519; Thu, 5 May 2011 10:02:43 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v3 3/6] MIPS: Octeon: Add device tree source files. Date: Thu, 5 May 2011 10:02:26 -0700 Message-Id: <1304614949-30460-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 05 May 2011 17:02:47.0194 (UTC) FILETIME=[42206FA0:01CC0B46] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- .../devicetree/bindings/mips/cavium/bootbus.txt | 37 ++ .../devicetree/bindings/mips/cavium/ciu.txt | 26 ++ .../devicetree/bindings/mips/cavium/gpio.txt | 48 +++ .../devicetree/bindings/mips/cavium/mdio.txt | 27 ++ .../devicetree/bindings/mips/cavium/mix.txt | 40 ++ .../devicetree/bindings/mips/cavium/pip.txt | 98 +++++ .../devicetree/bindings/mips/cavium/twsi.txt | 34 ++ .../devicetree/bindings/mips/cavium/uart.txt | 19 + .../devicetree/bindings/mips/cavium/uctl.txt | 47 +++ arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 13 + arch/mips/cavium-octeon/octeon_3xxx.dts | 431 ++++++++++++++++++++ 12 files changed, 822 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/gpio.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/mdio.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/mix.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/pip.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/twsi.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uart.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt new file mode 100644 index 0000000..221c118 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt @@ -0,0 +1,37 @@ +* Boot Bus + +Properties: +- compatible: "cavium,octeon-3860-bootbus" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the CIU's register bank. + +- #address-cells: Must be <2>. The first cell is the chip select + within the bootbus. The second cell is the offset from the chip select. + +- #size-cells: Must be <1>. + +- ranges: There must be one one triplet of (child-bus-address, + parent-bus-address, length) for each active chip select. + +Example: + bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0x1000000>, + <1 0 0x1 0x30000000 0x10000000>, + <2 0 0x1 0x40000000 0x10000000>, + <3 0 0x1 0x50000000 0x10000000>, + <4 0 0x1 0x60000000 0x10000000>, + <5 0 0x1 0x70000000 0x10000000>, + <6 0 0x1 0x80000000 0x10000000>, + <7 0 0x1 0x90000000 0x10000000>; + . + . + . + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt new file mode 100644 index 0000000..c8ff212 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu.txt @@ -0,0 +1,26 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-3860-ciu" + + Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value of 0 or 1. The second cell is the bit + within the bank and may have a value between 0 and 63. + +Example: + interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/gpio.txt b/Documentation/devicetree/bindings/mips/cavium/gpio.txt new file mode 100644 index 0000000..72853d4 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/gpio.txt @@ -0,0 +1,48 @@ +* General Purpose Input Output (GPIO) bus. + +Properties: +- compatible: "cavium,octeon-3860-gpio" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the GPIO unit's register bank. + +- gpio-controller: This is a GPIO controller. + +- #gpio-cells: Must be <2>. The first cell is the GPIO pin. + +- interrupt-controller: The GPIO controller is also an interrupt + controller, any of its pins may be configured as an interrupt + source. + +- #interrupt-cells: Must be <2>. The first cell is the GPIO pin + connected to the interrupt source. The second cell is the interrupt + triggering protocol and may have one of four values: + 0 - level triggered active high. + 1 - level triggered active low + 2 - edge triggered on the rising edge. + 3 - edge triggered on the falling edge. + +- interrupts: Interrupt routing for pin 0. The remaining pins are + also routed, but in a manner that can be derived from the pin0 + routing, so they are not specified. + +Example: + + gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (0 - level active high + * 1 - level active low + * 2 - edge rising + * 3 - edge falling + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/mdio.txt b/Documentation/devicetree/bindings/mips/cavium/mdio.txt new file mode 100644 index 0000000..6253c3b --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/mdio.txt @@ -0,0 +1,27 @@ +* System Management Interface (SMI) / MDIO + +Properties: +- compatible: "cavium,octeon-3860-mdio" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the MDIO bus controller register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. MDIO addresses have no size component. + +Typically an MDIO bus might have several children. + +Example: + mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + ethernet-phy@0 { + ... + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/mix.txt b/Documentation/devicetree/bindings/mips/cavium/mix.txt new file mode 100644 index 0000000..2a91a33 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/mix.txt @@ -0,0 +1,40 @@ +* MIX Ethernet controller. + +Properties: +- compatible: "cavium,octeon-5750-mix" + + Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX + devices. + +- reg: The base addresses of four seperate register banks. The first + bank contains the MIX registers. The second bank the corresponding + AGL registers. The third bank are the AGL registers shared by all + MIX devices present. The fourth bank is the AGL_PRT_CTL shared by + all MIX devices present. + +- cell-index: A single cell specifying which portion of the shared + register banks corresponds to this MIX device. + +- interrupts: Two interrupt specifiers. The first is the MIX + interrupt routing and the second the routing for the AGL interrupts. + +- mac-address: Optional, the MAC address to assign to the device. + +- local-mac-address: Optional, the MAC address to assign to the device + if mac-address is not specified. + +- phy-handle: Optional, a phandle for the PHY device connected to this device. + +Example: + ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 0f b7 10 63 54 ]; + phy-handle = <&phy1>; + }; + diff --git a/Documentation/devicetree/bindings/mips/cavium/pip.txt b/Documentation/devicetree/bindings/mips/cavium/pip.txt new file mode 100644 index 0000000..d4c53ba --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/pip.txt @@ -0,0 +1,98 @@ +* PIP Ethernet nexus. + +The PIP Ethernet nexus can control several data packet input/output +devices. The devices have a two level grouping scheme. There may be +several interfaces, and each interface may have several ports. These +ports might be an individual Ethernet PHY. + + +Properties for the PIP nexus: +- compatible: "cavium,octeon-3860-pip" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the PIP's register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. + +Properties for PIP interfaces which is a child the PIP nexus: +- compatible: "cavium,octeon-3860-pip-interface" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The interface number. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. + +Properties for PIP port which is a child the PIP interface: +- compatible: "cavium,octeon-3860-pip-port" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The port number within the interface group. + +- mac-address: Optional, the MAC address to assign to the device. + +- local-mac-address: Optional, the MAC address to assign to the device + if mac-address is not specified. + +- phy-handle: Optional, a phandle for the PHY device connected to this device. + +Example: + + pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 60 ]; + phy-handle = <&phy2>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 61 ]; + phy-handle = <&phy3>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 62 ]; + phy-handle = <&phy4>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 63 ]; + phy-handle = <&phy5>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 64 ]; + phy-handle = <&phy6>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/twsi.txt b/Documentation/devicetree/bindings/mips/cavium/twsi.txt new file mode 100644 index 0000000..6e57155 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/twsi.txt @@ -0,0 +1,34 @@ +* Two Wire Serial Interface (TWSI) / I2C + +- compatible: "cavium,octeon-3860-twsi" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the TWSI/I2C bus controller register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. I2C addresses have no size component. + +- interrupts: A single interrupt specifier. + +- clock-rate: The I2C bus clock rate in Hz. + +Example: + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-rate = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/uart.txt b/Documentation/devicetree/bindings/mips/cavium/uart.txt new file mode 100644 index 0000000..87a6c37 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/uart.txt @@ -0,0 +1,19 @@ +* Universal Asynchronous Receiver/Transmitter (UART) + +- compatible: "cavium,octeon-3860-uart" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the UART register bank. + +- interrupts: A single interrupt specifier. + +- current-speed: Optional, the current bit rate in bits per second. + +Example: + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + current-speed = <115200>; + interrupts = <0 35>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt new file mode 100644 index 0000000..5dabe02 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/uctl.txt @@ -0,0 +1,47 @@ +* UCTL USB controller glue + +Properties: +- compatible: "cavium,octeon-6335-uctl" + + Compatibility with all cn6XXX SOCs. + +- reg: The base address of the UCTL register bank. + +- #address-cells: Must be <2>. + +- #size-cells: Must be <2>. + +- ranges: Empty to signify direct mapping of the children. + +- refclk-frequency: A single cell containing the reference clock + frequency in Hz. + +- refclk-type: A string describing the reference clock connection + either "crystal" or "external". + +Example: + uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <24000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore new file mode 100644 index 0000000..39c9686 --- /dev/null +++ b/arch/mips/cavium-octeon/.gitignore @@ -0,0 +1,2 @@ +*.dtb.S +*.dtb diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 19eb043..b8d4f63 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -15,3 +15,16 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o + +DTS_FILES = octeon_3xxx.dts +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) + +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) + +$(obj)/%.dtb: $(src)/%.dts + $(call cmd,dtc) + +# Let's keep the .dtb files around in case we want to look at them. +.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) + +clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts new file mode 100644 index 0000000..8c1d3d4 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_3xxx.dts @@ -0,0 +1,431 @@ +/dts-v1/; +/* + * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-3860"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (0 - level active high + * 1 - level active low + * 2 - edge rising + * 3 - edge falling + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>; /* <0 17> <0 18> <0 19> + <0 20> <0 21> <0 22> <0 23> + <0 24> <0 25> <0 26> <0 27> + <0 28> <0 29> <0 30> <0 31>; */ + }; + + smi0: mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + phy0: ethernet-phy@0 { + compatible = "broadcom,bcm5241"; + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "broadcom,bcm5241"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <5 1>; /* Pin 5, active low */ + }; + phy3: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <5 1>; /* Pin 5, active low */ + }; + phy4: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <5 1>; /* Pin 5, active low */ + }; + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <5 1>; /* Pin 5, active low */ + }; + + phy6: ethernet-phy@6 { + reg = <6>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000001900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <0 62>, <1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + mix1: ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy5>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy6>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy7>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy8>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy9>; + }; + }; + + interface@2 { /* DPI interface. */ + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@3 { /* Loop interface. */ + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-rate = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <0 59>; + clock-rate = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 34>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 35>; + }; + + uart2: serial@1180000000400 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000400 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <1 16>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0x1000000>, + <1 0 0x1 0x30000000 0x10000000>, + <2 0 0x1 0x40000000 0x10000000>, + <3 0 0x1 0x50000000 0x10000000>, + <4 0 0x1 0x60000000 0x10000000>, + <5 0 0x1 0x70000000 0x10000000>, + <6 0 0x1 0x80000000 0x10000000>, + <7 0 0x1 0x90000000 0x10000000>; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware"; + reg = <0x0 0x400000>; + read-only; + }; + + partition@400000 { + label = "data"; + reg = <0x400000 0x400000>; + read-only; + }; + }; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <24000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + }; + + aliases { + mix0 = &mix0; + mix1 = &mix1; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + flash0 = &flash0; + }; + }; -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu May 5 19:04:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:04:35 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14465 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491761Ab1EERCy (ORCPT ); Thu, 5 May 2011 19:02:54 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 05 May 2011 10:03:54 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:52 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:52 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p45H2mi5030528; Thu, 5 May 2011 10:02:49 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p45H2mYA030527; Thu, 5 May 2011 10:02:48 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v3 5/6] MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts. Date: Thu, 5 May 2011 10:02:28 -0700 Message-Id: <1304614949-30460-6-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 05 May 2011 17:02:52.0647 (UTC) FILETIME=[45607F70:01CC0B46] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is needed for Octeon to use the Device Tree. The GPIO interrupts are configured based on Device Tree properties Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 183 +++++++++++++++++++++++++++++++++- 1 files changed, 182 insertions(+), 1 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index ffd4ae6..68b711c 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -8,11 +8,14 @@ #include #include +#include #include +#include #include #include #include +#include static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); @@ -58,6 +61,90 @@ static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, octeon_irq_ciu_to_irq[line][bit] = irq; } +static unsigned int octeon_irq_gpio_mapping(struct device_node *controller, + const u32 *intspec, + unsigned int intsize) +{ + struct of_irq oirq; + int i; + unsigned int irq = 0; + unsigned int type; + unsigned int ciu = 0, bit = 0; + unsigned int pin = be32_to_cpup(intspec); + unsigned int trigger = be32_to_cpup(intspec + 1); + bool set_edge_handler = false; + + if (pin >= 16) + goto err; + i = of_irq_map_one(controller, 0, &oirq); + if (i) + goto err; + if (oirq.size != 2) + goto err_put; + + ciu = oirq.specifier[0]; + bit = oirq.specifier[1] + pin; + + if (ciu >= 8 || bit >= 64) + goto err_put; + + irq = octeon_irq_ciu_to_irq[ciu][bit]; + if (!irq) + goto err_put; + + switch (trigger & 3) { + case 0: + type = IRQ_TYPE_LEVEL_HIGH; + break; + case 1: + type = IRQ_TYPE_LEVEL_LOW; + break; + case 2: + type = IRQ_TYPE_EDGE_RISING; + set_edge_handler = true; + break; + case 3: + type = IRQ_TYPE_EDGE_FALLING; + set_edge_handler = true; + break; + } + + irq_set_irq_type(irq, type); + + if (set_edge_handler) + __irq_set_handler(irq, handle_edge_irq, 0, NULL); + +err_put: + of_node_put(oirq.controller); +err: + return irq; +} + +/* + * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# + * + * Octeon irq maps are a pair of indexes. The first selects either + * ciu0 or ciu1, the second is the bit within the ciu register. + */ +unsigned int irq_create_of_mapping(struct device_node *controller, + const u32 *intspec, unsigned int intsize) +{ + unsigned int irq = 0; + unsigned int ciu, bit; + + if (of_device_is_compatible(controller, "cavium,octeon-3860-gpio")) + return octeon_irq_gpio_mapping(controller, intspec, intsize); + + ciu = be32_to_cpup(intspec); + bit = be32_to_cpup(intspec + 1); + + if (ciu < 8 && bit < 64) + irq = octeon_irq_ciu_to_irq[ciu][bit]; + + return irq; +} +EXPORT_SYMBOL_GPL(irq_create_of_mapping); + static int octeon_coreid_for_cpu(int cpu) { #ifdef CONFIG_SMP @@ -505,6 +592,72 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) } } +static void octeon_irq_gpio_setup(struct irq_data *data) +{ + union cvmx_gpio_bit_cfgx cfg; + int bit = data->irq - OCTEON_IRQ_GPIO0; + u32 t = irqd_get_trigger_type(data); + + cfg.u64 = 0; + cfg.s.int_en = 1; + cfg.s.int_type = (t & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) != 0; + cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0; + + /* 1 uS glitch filter*/ + cfg.s.fil_cnt = 7; + cfg.s.fil_sel = 3; + + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), cfg.u64); +} + +static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu_enable_v2(data); +} + +static void octeon_irq_ciu_enable_gpio(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu_enable(data); +} + +static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t) +{ + u32 current_type = irqd_get_trigger_type(data); + + /* If the type has been set, don't change it */ + if (current_type && current_type != t) + return -EINVAL; + + irqd_set_trigger_type(data, t); + return IRQ_SET_MASK_OK; +} + +static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0); + + octeon_irq_ciu_disable_all_v2(data); +} + +static void octeon_irq_ciu_disable_gpio(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0); + + octeon_irq_ciu_disable_all(data); +} + +static void octeon_irq_ciu_gpio_ack(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + u64 mask = 1ull << bit; + + cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); +} + #ifdef CONFIG_SMP static void octeon_irq_cpu_offline_ciu(struct irq_data *data) @@ -717,6 +870,31 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = { .flags = IRQCHIP_ONOFFLINE_ENABLED, }; +static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu_enable_gpio_v2, + .irq_disable = octeon_irq_ciu_disable_gpio_v2, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, +#endif +}; + +static struct irq_chip octeon_irq_chip_ciu_gpio = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu_enable_gpio, + .irq_disable = octeon_irq_ciu_disable_gpio, + .irq_mask = octeon_irq_dummy_mask, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, +#endif +}; + /* * Watchdog interrupts are special. They are associated with a single * core, so we hardwire the affinity to that core. @@ -890,6 +1068,7 @@ static void __init octeon_irq_init_ciu(void) struct irq_chip *chip_edge; struct irq_chip *chip_mbox; struct irq_chip *chip_wd; + struct irq_chip *chip_gpio; octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; @@ -904,6 +1083,7 @@ static void __init octeon_irq_init_ciu(void) chip_edge = &octeon_irq_chip_ciu_edge_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; + chip_gpio = &octeon_irq_chip_ciu_gpio_v2; } else { octeon_irq_ip2 = octeon_irq_ip2_v1; octeon_irq_ip3 = octeon_irq_ip3_v1; @@ -911,6 +1091,7 @@ static void __init octeon_irq_init_ciu(void) chip_edge = &octeon_irq_chip_ciu_edge; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; + chip_gpio = &octeon_irq_chip_ciu_gpio; } octeon_irq_ip4 = octeon_irq_ip4_mask; @@ -921,7 +1102,7 @@ static void __init octeon_irq_init_ciu(void) for (i = 0; i < 16; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu May 5 19:04:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:05:00 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14470 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491763Ab1EERCy (ORCPT ); Thu, 5 May 2011 19:02:54 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 05 May 2011 10:03:54 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:52 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:52 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p45H2o9E030532; Thu, 5 May 2011 10:02:50 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p45H2nUw030531; Thu, 5 May 2011 10:02:49 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v3 6/6] MIPS: Octeon: Initialize and fixup device tree. Date: Thu, 5 May 2011 10:02:29 -0700 Message-Id: <1304614949-30460-7-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 05 May 2011 17:02:52.0647 (UTC) FILETIME=[45607F70:01CC0B46] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/Makefile | 2 + arch/mips/cavium-octeon/octeon-platform.c | 295 +++++++++++++++++++++++++++++ arch/mips/cavium-octeon/setup.c | 17 ++ 4 files changed, 315 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 12b6a07..6767176 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1382,6 +1382,7 @@ config CPU_CAVIUM_OCTEON select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select LIBFDT help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index b8d4f63..602eadf 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -9,6 +9,8 @@ # Copyright (C) 2005-2009 Cavium Networks # +ccflags-y := -include linux/libfdt_env.h -I$(src)/../../../scripts/dtc/libfdt + obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o obj-y += dma-octeon.o flash_setup.o obj-y += octeon-memcpy.o diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index cd61d72..e595a81 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -13,10 +13,16 @@ #include #include #include +#include #include +#include +#include +#include #include #include +#include +#include static struct octeon_cf_data octeon_cf_data; @@ -440,6 +446,295 @@ device_initcall(octeon_ohci_device_init); #endif /* CONFIG_USB */ +static struct of_device_id __initdata octeon_ids[] = { + { .compatible = "simple-bus", }, + { .compatible = "cavium,octeon-6335-uctl", }, + { .compatible = "cavium,octeon-3860-bootbus", }, + {}, +}; + +static void __init octeon_fdt_set_phy(int eth, int phy_addr) +{ + const __be32 *phy_handle; + const __be32 *reg; + struct fdt_node_header *raw_node; + u32 phandle; + int phy; + int available_len, addr_len, len; + char new_address[3]; + char *cp; + + phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); + if (!phy_handle) + return; + + phandle = be32_to_cpup(phy_handle); + phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); + if (phy_addr < 0 || phy < 0) { + /* Delete the PHY things */ + if (phy >= 0) + fdt_nop_node(initial_boot_params, phy); + fdt_nop_property(initial_boot_params, eth, "phy-handle"); + return; + } + + reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); + if (phy_addr == be32_to_cpup(reg)) + return; + + fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); + + snprintf(new_address, sizeof(new_address), "%x", phy_addr); + /* + * All PHYs in the template have a name like 'ethernet-phy@0', + * that is 14 characters, which allows us to replace the + * address portion with up to two characters without + * clobbering things past a multiple of 4 boundry. + */ + raw_node = (void *)fdt_offset_ptr(initial_boot_params, phy, 0); + cp = strchr(raw_node->name, '@'); + if (!cp) + return; + + available_len = (strlen(raw_node->name) + 4) & ~3; + len = cp - raw_node->name + 1; + addr_len = strlen(new_address); + + if (len + addr_len + 1 > available_len) { + pr_err("ERROR: cannot edit PHY address <%s>\n", raw_node->name); + return; + } + + cp++; + strcpy(cp, new_address); +} + +static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) +{ + u8 new_mac[6]; + u64 mac = *pmac; + int r; + + new_mac[0] = (mac >> 40) & 0xff; + new_mac[1] = (mac >> 32) & 0xff; + new_mac[2] = (mac >> 24) & 0xff; + new_mac[3] = (mac >> 16) & 0xff; + new_mac[4] = (mac >> 8) & 0xff; + new_mac[5] = mac & 0xff; + + r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", + new_mac, sizeof(new_mac)); + + if (r) { + pr_err("Setting \"local-mac-address\" failed %d", r); + return; + } + *pmac = mac + 1; +} + +static void __init octeon_fdt_rm_ethernet(int node) +{ + const __be32 *phy_handle; + + phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); + if (phy_handle) { + u32 ph = be32_to_cpup(phy_handle); + int p = fdt_node_offset_by_phandle(initial_boot_params, ph); + if (p >= 0) + fdt_nop_node(initial_boot_params, p); + } + fdt_nop_node(initial_boot_params, node); +} + +static void __init octeon_fdt_pip_port(int iface, int i, int p, u64 *pmac) +{ + char name_buffer[20]; + int eth; + int phy_addr; + + snprintf(name_buffer, sizeof(name_buffer), "ethernet@%d", p); + eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); + if (eth < 0) + return; + if (p >= cvmx_helper_ports_on_interface(i)) { + pr_notice("Deleting port %x:%x\n", i, p); + octeon_fdt_rm_ethernet(eth); + return; + } + + phy_addr = cvmx_helper_board_get_mii_address(16 * i + p); + octeon_fdt_set_phy(eth, phy_addr); + octeon_fdt_set_mac_addr(eth, pmac); +} + +static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) +{ + char name_buffer[20]; + int iface; + int p; + + cvmx_helper_interface_enumerate(idx); + snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); + iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); + if (iface < 0) + return; + + for (p = 0; p < 4; p++) + octeon_fdt_pip_port(iface, idx, p, pmac); +} + +int __init octeon_prune_device_tree(void) +{ + int i, max_port, uart_mask; + const char *pip_path; + char name_buffer[20]; + int aliases; + u64 mac_addr_base; + + if (fdt_check_header(initial_boot_params)) + panic("Corrupt Device Tree."); + + aliases = fdt_path_offset(initial_boot_params, "/aliases"); + if (aliases < 0) { + pr_err("Error: No /aliases node in device tree."); + return -EINVAL; + } + + + mac_addr_base = + ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | + ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | + ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | + ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | + ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | + (octeon_bootinfo->mac_addr_base[5] & 0xffull); + + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) + max_port = 2; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 1; + else + max_port = 0; + + for (i = 0; i < 2; i++) { + const char *alias_prop; + int mgmt; + snprintf(name_buffer, sizeof(name_buffer), + "mix%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + if (alias_prop) { + mgmt = fdt_path_offset(initial_boot_params, alias_prop); + if (mgmt < 0) + continue; + if (i >= max_port) { + pr_notice("Deleting mix%d\n", i); + octeon_fdt_rm_ethernet(mgmt); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } else { + octeon_fdt_set_phy(mgmt, i); + octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); + } + } + } + + pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); + if (pip_path) { + int pip = fdt_path_offset(initial_boot_params, pip_path); + if (pip >= 0) + for (i = 0; i < 4; i++) + octeon_fdt_pip_iface(pip, i, &mac_addr_base); + } + + /* I2C */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + const char *alias_prop; + int i2c; + snprintf(name_buffer, sizeof(name_buffer), + "twsi%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + i2c = fdt_path_offset(initial_boot_params, alias_prop); + if (i2c < 0) + continue; + if (i >= max_port) { + pr_notice("Deleting twsi%d\n", i); + fdt_nop_node(initial_boot_params, i2c); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + } + + /* Serial */ + uart_mask = 0; + +#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL + /* + * If we are configured to run as the second of two kernels, + * disable uart0 and enable uart1. Uart0 is owned by the first + * kernel + */ + uart_mask |= 2; /* uart1 */ +#else + /* + * We are configured for the first kernel. We'll enable uart0 + * if the bootloader told us to use 0, otherwise will enable + * uart 1. + */ + if (octeon_get_boot_uart() == 0) + uart_mask |= 1; /* uart0 */ + if (octeon_get_boot_uart() == 1) + uart_mask |= 2; /* uart1 */ + +#ifdef CONFIG_KGDB + uart_mask |= 2; /* uart1 */ +#endif +#endif + + /* Right now CN52XX is the only chip with a third uart */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) + uart_mask |= 4; /* uart2 */ + + for (i = 0; i < 3; i++) { + const char *alias_prop; + int uart; + snprintf(name_buffer, sizeof(name_buffer), + "uart%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + uart = fdt_path_offset(initial_boot_params, alias_prop); + if (uart_mask & (1 << i)) + continue; + pr_notice("Deleting uart%d\n", i); + fdt_nop_node(initial_boot_params, uart); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + + return 0; +} + +static int __init octeon_publish_devices(void) +{ + return of_platform_bus_probe(NULL, octeon_ids, NULL); +} +device_initcall(octeon_publish_devices); + + MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 36221b3..91431a6 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #ifdef CONFIG_BLK_DEV_INITRD #include #endif @@ -797,3 +798,19 @@ void prom_free_prom_memory(void) } #endif } + +int octeon_prune_device_tree(void); + +extern const char __dtb_octeon_3xxx_begin; +extern const char __dtb_octeon_3xxx_end; +void __init device_tree_init(void) +{ + int dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; + /* Copy the default tree from init memory. */ + initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); + if (initial_boot_params == NULL) + panic("Could not allocate initial_boot_params\n"); + memcpy(initial_boot_params, &__dtb_octeon_3xxx_begin, dt_size); + octeon_prune_device_tree(); + unflatten_device_tree(); +} -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu May 5 19:05:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:05:23 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14478 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491766Ab1EERC4 (ORCPT ); Thu, 5 May 2011 19:02:56 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 05 May 2011 10:03:56 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:54 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:02:54 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p45H2kVu030524; Thu, 5 May 2011 10:02:47 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p45H2j9X030523; Thu, 5 May 2011 10:02:45 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v3 4/6] MIPS: Prune some target specific code out of prom.c Date: Thu, 5 May 2011 10:02:27 -0700 Message-Id: <1304614949-30460-5-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 05 May 2011 17:02:54.0710 (UTC) FILETIME=[469B4960:01CC0B46] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29827 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This code is not common enough to be in a shared file. It is also not used by any existing boards, so just remove it. Signed-off-by: David Daney --- arch/mips/kernel/prom.c | 49 ----------------------------------------------- 1 files changed, 0 insertions(+), 49 deletions(-) diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index a19811e9..a07b6f1 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -59,52 +59,3 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start, initrd_below_start_ok = 1; } #endif - -/* - * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# - * - * Currently the mapping mechanism is trivial; simple flat hwirq numbers are - * mapped 1:1 onto Linux irq numbers. Cascaded irq controllers are not - * supported. - */ -unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) -{ - return intspec[0]; -} -EXPORT_SYMBOL_GPL(irq_create_of_mapping); - -void __init early_init_devtree(void *params) -{ - /* Setup flat device-tree pointer */ - initial_boot_params = params; - - /* Retrieve various informations from the /chosen node of the - * device-tree, including the platform type, initrd location and - * size, and more ... - */ - of_scan_flat_dt(early_init_dt_scan_chosen, NULL); - - /* Scan memory nodes */ - of_scan_flat_dt(early_init_dt_scan_root, NULL); - of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL); -} - -void __init device_tree_init(void) -{ - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_mem_mach(base, size); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_mem_mach(base, size); -} -- 1.7.2.3 From glikely@secretlab.ca Thu May 5 19:40:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:40:44 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:45967 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491766Ab1EERkk convert rfc822-to-8bit (ORCPT ); Thu, 5 May 2011 19:40:40 +0200 Received: by iyb39 with SMTP id 39so2502389iyb.36 for ; Thu, 05 May 2011 10:40:34 -0700 (PDT) Received: by 10.42.131.65 with SMTP id y1mr1377161ics.172.1304617234061; Thu, 05 May 2011 10:40:34 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.155.1 with HTTP; Thu, 5 May 2011 10:40:14 -0700 (PDT) In-Reply-To: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> From: Grant Likely Date: Thu, 5 May 2011 11:40:14 -0600 X-Google-Sender-Auth: f3ThH4wbhym7hMbqmD6_pfY6gg8 Message-ID: Subject: Re: [RFC PATCH v3 0/6] MIPS: Octeon: Use Device Tree. To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Thu, May 5, 2011 at 11:02 AM, David Daney wrote: > After several weeks of fire fighting, I am back to my Octeon device > tree patches. > > New in v3: > > More updates to device tree bindings, and perhaps more importantly > descriptions/definitions of the bindings > > libfdt building moved to devices/of/libfdt. > > Cleanup and style improvements as suggested by Grant Likley. > > Omitted all the driver changes, as they are unchanged from the last > set, and at this stage the patches are just an RFC. > > New in v2: > > Changed many device tree bindings.  They should be closer to the > standard naming scheme now. > > Editing of the template device tree is done in the flattened form > using libfdt. > > Standard platform driver functions used in preference to the > of_platform variety. > > v1: > > Background: The Octeon family of SOCs has a variety of on-chip > controllers for Ethernet, MDIO, I2C, and several other I/O devices. > These chips are used on boards with a great variety of different > configurations.  To date, the configuration and bus topology > information has been hard coded in the drivers and support code. > > To facilitate supporting new chips and boards, we would like to make > use use the Device Tree to encode the configuration information. > > I would like to get some feedback on the current code I am working > with.  The migration approach is as follows: > > o Several device tree templates are statically linked into the kernel >  image.  Based on SOC type and board type one of these is selected in >  early boot.  Legacy configuration probing code is used to prune and >  patch the device tree template. > > o New SOCs and boards will directly use a device tree passed by the >  bootloader (This patch set doesn't actually implement this, but it >  is trivial to add). > > > > 1/6 -  Infrastructure to allow scripts/dtc/libfdt to be used in the >       kernel. > > 2/6 - OF patch to simplify of_find_node_by_path(). > > 3/6 - Add the statically linked Device Tree templates and bindings >      descriptions. > > 4/6 - Remove unused arch/mips/prom.c code that conflicts with >      following patches. > > 5/6 - irq_create_of_mapping() function. > > 6/6 - Fix up Device Tree template for current environment. > > > David Daney (6): >  of: Allow scripts/dtc/libfdt to be used from kernel code >  of: Make of_find_node_by_path() traverse /aliases for relative paths. >  MIPS: Octeon: Add device tree source files. >  MIPS: Prune some target specific code out of prom.c >  MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts. >  MIPS: Octeon: Initialize and fixup device tree. > >  .../devicetree/bindings/mips/cavium/bootbus.txt    |   37 ++ >  .../devicetree/bindings/mips/cavium/ciu.txt        |   26 ++ >  .../devicetree/bindings/mips/cavium/gpio.txt       |   48 +++ >  .../devicetree/bindings/mips/cavium/mdio.txt       |   27 ++ >  .../devicetree/bindings/mips/cavium/mix.txt        |   40 ++ >  .../devicetree/bindings/mips/cavium/pip.txt        |   98 +++++ >  .../devicetree/bindings/mips/cavium/twsi.txt       |   34 ++ >  .../devicetree/bindings/mips/cavium/uart.txt       |   19 + >  .../devicetree/bindings/mips/cavium/uctl.txt       |   47 +++ >  arch/mips/Kconfig                                  |    1 + >  arch/mips/cavium-octeon/.gitignore                 |    2 + >  arch/mips/cavium-octeon/Makefile                   |   15 + >  arch/mips/cavium-octeon/octeon-irq.c               |  183 ++++++++- >  arch/mips/cavium-octeon/octeon-platform.c          |  295 +++++++++++++ >  arch/mips/cavium-octeon/octeon_3xxx.dts            |  431 ++++++++++++++++++++ >  arch/mips/cavium-octeon/setup.c                    |   17 + >  arch/mips/kernel/prom.c                            |   49 --- >  drivers/of/Kconfig                                 |    3 + >  drivers/of/Makefile                                |    2 + >  drivers/of/base.c                                  |   41 ++- >  drivers/of/libfdt/Makefile                         |    8 + Out of curiosity, how big are the compiled libfdt object files? >  include/linux/libfdt.h                             |    8 + >  include/linux/libfdt_env.h                         |   13 + >  23 files changed, 1393 insertions(+), 51 deletions(-) >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/gpio.txt >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/mdio.txt >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/mix.txt >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/pip.txt >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/twsi.txt >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/uart.txt >  create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt >  create mode 100644 arch/mips/cavium-octeon/.gitignore >  create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts >  create mode 100644 drivers/of/libfdt/Makefile >  create mode 100644 include/linux/libfdt.h >  create mode 100644 include/linux/libfdt_env.h > > -- > 1.7.2.3 > > -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. From David.Daney@caviumnetworks.com Thu May 5 19:48:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 19:48:29 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16461 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491763Ab1EERsZ (ORCPT ); Thu, 5 May 2011 19:48:25 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 05 May 2011 10:49:13 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:48:12 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 May 2011 10:48:12 -0700 Message-ID: <4DC2E2D6.1040502@caviumnetworks.com> Date: Thu, 05 May 2011 10:48:06 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Grant Likely CC: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v3 0/6] MIPS: Octeon: Use Device Tree. References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 May 2011 17:48:12.0284 (UTC) FILETIME=[9A682BC0:01CC0B4C] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 05/05/2011 10:40 AM, Grant Likely wrote: > On Thu, May 5, 2011 at 11:02 AM, David Daney wrote: [...] >> drivers/of/libfdt/Makefile | 8 + > > Out of curiosity, how big are the compiled libfdt object files? > For my 64-bit mips64 kernel: [ddaney@dd1 libfdt]$ mips64-linux-size *.o text data bss dec hex filename 7024 0 0 7024 1b70 built-in.o 1792 0 0 1792 700 fdt.o 4328 0 0 4328 10e8 fdt_ro.o 904 0 0 904 388 fdt_wip.o David Daney From blogic@openwrt.org Thu May 5 22:59:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 May 2011 22:59:03 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:44575 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490992Ab1EEU7A (ORCPT ); Thu, 5 May 2011 22:59:00 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: [PATCH V6] MIPS: lantiq: add watchdog support Date: Thu, 5 May 2011 23:00:23 +0200 Message-Id: <1304629223-30537-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29830 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the watchdog found inside the Lantiq SoC family. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: Wim Van Sebroeck Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org --- Changes in V2 * add comments to explain register access * cleanup resource allocation * cleanup clock handling * whitespace fixes Changes in V3 * whitespace * change __iomem void to void __iomem * typo fixes * comment style * fix exit path in init function Changes in V4 * fixes register offsets (we use a smaller memory window) * typo in the comments * add __init to probe function Changes in V5 * add support for WDIOC_GETBOOTSTATUS and WDIOC_GETSTATUS * remove ifdefs and add a module parameter for the nowayout feature * add a remove function * fix typos Changes in V6 * WDIOC_SETTIMEOUT should return ltq_wdt_timeout aswell as applying it drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/lantiq_wdt.c | 261 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+), 0 deletions(-) create mode 100644 drivers/watchdog/lantiq_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 1b0f98b..022f9eb 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -990,6 +990,12 @@ config BCM63XX_WDT To compile this driver as a loadable module, choose M here. The module will be called bcm63xx_wdt. +config LANTIQ_WDT + tristate "Lantiq SoC watchdog" + depends on LANTIQ + help + Hardware driver for the Lantiq SoC Watchdog Timer. + # PARISC Architecture # POWERPC Architecture diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 3f8608b..ed26f70 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o obj-$(CONFIG_TXX9_WDT) += txx9wdt.o obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o # PARISC Architecture diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c new file mode 100644 index 0000000..ba1618f --- /dev/null +++ b/drivers/watchdog/lantiq_wdt.c @@ -0,0 +1,261 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + * Based on EP93xx wdt driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Section 3.4 of the datasheet + * The password sequence protects the WDT control register from unintended + * write actions, which might cause malfunction of the WDT. + * + * essentially the following two magic passwords need to be written to allow + * IO access to the WDT core + */ +#define LTQ_WDT_PW1 0x00BE0000 +#define LTQ_WDT_PW2 0x00DC0000 + +#define LTQ_WDT_CR 0x0 /* watchdog control register */ +#define LTQ_WDT_SR 0x8 /* watchdog status register */ + +#define LTQ_WDT_SR_EN (0x1 << 31) /* enable bit */ +#define LTQ_WDT_SR_PWD (0x3 << 26) /* turn on power */ +#define LTQ_WDT_SR_CLKDIV (0x3 << 24) /* turn on clock and set */ + /* divider to 0x40000 */ +#define LTQ_WDT_DIVIDER 0x40000 +#define LTQ_MAX_TIMEOUT ((1 << 16) - 1) /* the reload field is 16 bit */ + +static int nowayout = WATCHDOG_NOWAYOUT; + +static void __iomem *ltq_wdt_membase; +static unsigned long ltq_io_region_clk_rate; + +static unsigned long ltq_wdt_bootstatus; +static int ltq_wdt_timeout = 30; +static int ltq_wdt_ok_to_close; +static int ltq_wdt_in_use; + +static void +ltq_wdt_enable(void) +{ + ltq_wdt_timeout = ltq_wdt_timeout * + (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER) + 0x1000; + if (ltq_wdt_timeout > LTQ_MAX_TIMEOUT) + ltq_wdt_timeout = LTQ_MAX_TIMEOUT; + + /* write the first password magic */ + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); + /* write the second magic plus the configuration and new timeout */ + ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV | + LTQ_WDT_PW2 | ltq_wdt_timeout, ltq_wdt_membase + LTQ_WDT_CR); +} + +static void +ltq_wdt_disable(void) +{ + /* write the first password magic */ + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); + /* write the second password magic with no config + * this turns the watchdog off + */ + ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR); +} + +static ssize_t +ltq_wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) +{ + if (len) { + if (!nowayout) { + size_t i; + + ltq_wdt_ok_to_close = 0; + for (i = 0; i != len; i++) { + char c; + + if (get_user(c, data + i)) + return -EFAULT; + if (c == 'V') + ltq_wdt_ok_to_close = 1; + else + ltq_wdt_ok_to_close = 0; + } + } + ltq_wdt_enable(); + } + + return len; +} + +static struct watchdog_info ident = { + .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | + WDIOF_CARDRESET, + .identity = "ltq_wdt", +}; + +static long +ltq_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = -ENOTTY; + + switch (cmd) { + case WDIOC_GETSUPPORT: + ret = copy_to_user((struct watchdog_info __user *)arg, &ident, + sizeof(ident)) ? -EFAULT : 0; + break; + + case WDIOC_GETBOOTSTATUS: + ret = put_user(ltq_wdt_bootstatus, (int __user *)arg); + break; + + case WDIOC_GETSTATUS: + ret = put_user(0, (int __user *)arg); + break; + + case WDIOC_SETTIMEOUT: + ret = get_user(ltq_wdt_timeout, (int __user *)arg); + if (!ret) + ltq_wdt_enable(); + /* intentional drop through */ + case WDIOC_GETTIMEOUT: + ret = put_user(ltq_wdt_timeout, (int __user *)arg); + break; + + case WDIOC_KEEPALIVE: + ltq_wdt_enable(); + ret = 0; + break; + } + return ret; +} + +static int +ltq_wdt_open(struct inode *inode, struct file *file) +{ + if (ltq_wdt_in_use) + return -EBUSY; + ltq_wdt_in_use = 1; + ltq_wdt_enable(); + + return nonseekable_open(inode, file); +} + +static int +ltq_wdt_release(struct inode *inode, struct file *file) +{ + if (ltq_wdt_ok_to_close) + ltq_wdt_disable(); + else + pr_err("ltq_wdt: watchdog closed without warning\n"); + ltq_wdt_ok_to_close = 0; + ltq_wdt_in_use = 0; + + return 0; +} + +static const struct file_operations ltq_wdt_fops = { + .owner = THIS_MODULE, + .write = ltq_wdt_write, + .unlocked_ioctl = ltq_wdt_ioctl, + .open = ltq_wdt_open, + .release = ltq_wdt_release, + .llseek = no_llseek, +}; + +static struct miscdevice ltq_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = <q_wdt_fops, +}; + +static int __init +ltq_wdt_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk *clk; + + if (!res) { + dev_err(&pdev->dev, "cannot obtain I/O memory region"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "cannot request I/O memory region"); + return -EBUSY; + } + ltq_wdt_membase = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ltq_wdt_membase) { + dev_err(&pdev->dev, "cannot remap I/O memory region\n"); + return -ENOMEM; + } + + /* we do not need to enable the clock as it is always running */ + clk = clk_get(&pdev->dev, "io"); + WARN_ON(!clk); + ltq_io_region_clk_rate = clk_get_rate(clk); + clk_put(clk); + + if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST) + ltq_wdt_bootstatus = WDIOF_CARDRESET; + + return misc_register(<q_wdt_miscdev); +} + +static int __devexit +ltq_wdt_remove(struct platform_device *pdev) +{ + misc_deregister(<q_wdt_miscdev); + + if (ltq_wdt_membase) + iounmap(ltq_wdt_membase); + + return 0; +} + + +static struct platform_driver ltq_wdt_driver = { + .remove = __devexit_p(ltq_wdt_remove), + .driver = { + .name = "ltq_wdt", + .owner = THIS_MODULE, + }, +}; + +static int __init +init_ltq_wdt(void) +{ + return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); +} + +static void __exit +exit_ltq_wdt(void) +{ + return platform_driver_unregister(<q_wdt_driver); +} + +module_init(init_ltq_wdt); +module_exit(exit_ltq_wdt); + +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); + +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC Watchdog"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- 1.7.2.3 From blogic@openwrt.org Fri May 6 00:08:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 00:09:01 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:40661 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490996Ab1EEWI6 (ORCPT ); Fri, 6 May 2011 00:08:58 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 1/3] MIPS: lantiq: add DMA support Date: Fri, 6 May 2011 00:10:00 +0200 Message-Id: <1304633402-24161-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304633402-24161-1-git-send-email-blogic@openwrt.org> References: <1304633402-24161-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29831 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for the DMA engine found inside the XWAY family of SoCs. The engine has 5 ports and 20 channels. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- Changes in V2 * use spinlocks .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +- arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 60 +++++ arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/dma.c | 272 ++++++++++++++++++++ 4 files changed, 335 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h create mode 100644 arch/mips/lantiq/xway/dma.c diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 34bc993..95f1882 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -85,7 +85,8 @@ #define LTQ_PPE32_SIZE 0x40000 /* DMA */ -#define LTQ_DMA_BASE_ADDR 0xBE104100 +#define LTQ_DMA_BASE_ADDR 0x1E104100 +#define LTQ_DMA_SIZE 0x800 /* PCI */ #define PCI_CR_BASE_ADDR 0x1E105400 diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h new file mode 100644 index 0000000..872943a --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h @@ -0,0 +1,60 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#ifndef LTQ_DMA_H__ +#define LTQ_DMA_H__ + +#define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ +#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */ + +#define LTQ_DMA_OWN BIT(31) /* owner bit */ +#define LTQ_DMA_C BIT(30) /* complete bit */ +#define LTQ_DMA_SOP BIT(29) /* start of packet */ +#define LTQ_DMA_EOP BIT(28) /* end of packet */ +#define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */ +#define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */ +#define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */ + +struct ltq_dma_desc { + u32 ctl; + u32 addr; +}; + +struct ltq_dma_channel { + int nr; /* the channel number */ + int irq; /* the mapped irq */ + int desc; /* the current descriptor */ + struct ltq_dma_desc *desc_base; /* the descriptor base */ + int phys; /* physical addr */ +}; + +enum { + DMA_PORT_ETOP = 0, + DMA_PORT_DEU, +}; + +extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_open(struct ltq_dma_channel *ch); +extern void ltq_dma_close(struct ltq_dma_channel *ch); +extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch); +extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch); +extern void ltq_dma_free(struct ltq_dma_channel *ch); +extern void ltq_dma_init_port(int p); + +#endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index a021def..d88a3e8 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o +obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c new file mode 100644 index 0000000..485d5bf --- /dev/null +++ b/arch/mips/lantiq/xway/dma.c @@ -0,0 +1,272 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include + +#include +#include + +#define LTQ_DMA_CTRL 0x10 +#define LTQ_DMA_CPOLL 0x14 +#define LTQ_DMA_CS 0x18 +#define LTQ_DMA_CCTRL 0x1C +#define LTQ_DMA_CDBA 0x20 +#define LTQ_DMA_CDLEN 0x24 +#define LTQ_DMA_CIS 0x28 +#define LTQ_DMA_CIE 0x2C +#define LTQ_DMA_PS 0x40 +#define LTQ_DMA_PCTRL 0x44 +#define LTQ_DMA_IRNEN 0xf4 + +#define DMA_DESCPT BIT(3) /* descriptor complete irq */ +#define DMA_TX BIT(8) /* TX channel direction */ +#define DMA_CHAN_ON BIT(0) /* channel on / off bit */ +#define DMA_PDEN BIT(6) /* enable packet drop */ +#define DMA_CHAN_RST BIT(1) /* channel on / off bit */ +#define DMA_RESET BIT(0) /* channel on / off bit */ +#define DMA_IRQ_ACK 0x7e /* IRQ status register */ +#define DMA_POLL BIT(31) /* turn on channel polling */ +#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ +#define DMA_2W_BURST BIT(1) /* 2 word burst length */ +#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ +#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */ +#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ + +#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) +#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y)) +#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ + ltq_dma_membase + (z)) + +static void __iomem *ltq_dma_membase; + +void +ltq_dma_enable_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_enable_irq); + +void +ltq_dma_disable_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_disable_irq); + +void +ltq_dma_ack_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_ack_irq); + +void +ltq_dma_open(struct ltq_dma_channel *ch) +{ + unsigned long flag; + + local_irq_save(flag); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL); + ltq_dma_enable_irq(ch); + local_irq_restore(flag); +} +EXPORT_SYMBOL_GPL(ltq_dma_open); + +void +ltq_dma_close(struct ltq_dma_channel *ch) +{ + unsigned long flag; + + local_irq_save(flag); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + ltq_dma_disable_irq(ch); + local_irq_restore(flag); +} +EXPORT_SYMBOL_GPL(ltq_dma_close); + +static void +ltq_dma_alloc(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ch->desc = 0; + ch->desc_base = dma_alloc_coherent(NULL, + LTQ_DESC_NUM * LTQ_DESC_SIZE, + &ch->phys, GFP_ATOMIC); + memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE); + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32(ch->phys, LTQ_DMA_CDBA); + ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + wmb(); + ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL); + while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST) + ; + local_irq_restore(flags); +} + +void +ltq_dma_alloc_tx(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ltq_dma_alloc(ch); + + local_irq_save(flags); + ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx); + +void +ltq_dma_alloc_rx(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ltq_dma_alloc(ch); + + local_irq_save(flags); + ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx); + +void +ltq_dma_free(struct ltq_dma_channel *ch) +{ + if (!ch->desc_base) + return; + ltq_dma_close(ch); + dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE, + ch->desc_base, ch->phys); +} +EXPORT_SYMBOL_GPL(ltq_dma_free); + +void +ltq_dma_init_port(int p) +{ + ltq_dma_w32(p, LTQ_DMA_PS); + switch (p) { + case DMA_PORT_ETOP: + /* + * Tell the DMA engine to swap the endianess of data frames and + * drop packets if the channel arbitration fails. + */ + ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN, + LTQ_DMA_PCTRL); + break; + + case DMA_PORT_DEU: + ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2), + LTQ_DMA_PCTRL); + break; + + default: + break; + } +} +EXPORT_SYMBOL_GPL(ltq_dma_init_port); + +static int +ltq_dma_probe(struct platform_device *pdev) +{ + struct resource *res; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get dma resource\n"); + return -ENOENT; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request dma resource\n"); + return -EBUSY; + } + + ltq_dma_membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_dma_membase) { + dev_err(&pdev->dev, "failed to remap dma engine %d\n", + pdev->id); + return -ENOMEM; + } + + /* power up and reset the dma engine */ + ltq_pmu_enable(PMU_DMA); + ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); + + /* disable all interrupts */ + ltq_dma_w32(0, LTQ_DMA_IRNEN); + + /* reset/configure each channel */ + for (i = 0; i < DMA_MAX_CHANNEL; i++) { + ltq_dma_w32(i, LTQ_DMA_CS); + ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); + ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + } + return 0; +} + +static struct platform_driver ltq_dma_driver = { + .probe = ltq_dma_probe, + .driver = { + .name = "ltq_dma", + .owner = THIS_MODULE, + }, +}; + +int __init +ltq_dma_init(void) +{ + int ret = platform_driver_register(<q_dma_driver); + + if (ret) + pr_info("ltq_dma : Error registering platfom driver!"); + return ret; +} + +postcore_initcall(ltq_dma_init); -- 1.7.2.3 From blogic@openwrt.org Fri May 6 00:09:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 00:09:28 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:40664 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490997Ab1EEWI6 (ORCPT ); Fri, 6 May 2011 00:08:58 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 3/3] MIPS: lantiq: add dma/etop board support Date: Fri, 6 May 2011 00:10:02 +0200 Message-Id: <1304633402-24161-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304633402-24161-1-git-send-email-blogic@openwrt.org> References: <1304633402-24161-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29832 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds functions to register the etop and dma platform devices and calls them from the board specific setup code. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/devices.c | 13 +++++++++++++ arch/mips/lantiq/devices.h | 1 + arch/mips/lantiq/xway/devices.c | 27 +++++++++++++++++++++++++++ arch/mips/lantiq/xway/devices.h | 2 ++ arch/mips/lantiq/xway/mach-easy50712.c | 6 ++++++ 5 files changed, 49 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c index e758863..a10244e 100644 --- a/arch/mips/lantiq/devices.c +++ b/arch/mips/lantiq/devices.c @@ -31,6 +31,19 @@ #define IRQ_RES(resname, irq) \ {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} +/* dma engine */ +static struct resource ltq_dma_resource = { + .name = "dma", + .start = LTQ_DMA_BASE_ADDR, + .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +void __init ltq_register_dma(void) +{ + platform_device_register_simple("ltq_dma", 0, <q_dma_resource, 1); +} + /* nor flash */ static struct resource ltq_nor_resource = { .name = "nor", diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h index 069006c..d339963 100644 --- a/arch/mips/lantiq/devices.h +++ b/arch/mips/lantiq/devices.h @@ -12,6 +12,7 @@ #include #include +extern void ltq_register_dma(void); extern void ltq_register_nor(struct physmap_flash_data *data); extern void ltq_register_wdt(void); extern void ltq_register_asc(int port); diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c index 7d58ae5..99ff2ef 100644 --- a/arch/mips/lantiq/xway/devices.c +++ b/arch/mips/lantiq/xway/devices.c @@ -75,3 +75,30 @@ void __init ltq_register_gpio_stp(void) { platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1); } + +/* ethernet */ +static struct resource ltq_ethernet_resources = { + .name = "etop", + .start = LTQ_ETOP_BASE_ADDR, + .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ltq_ethernet = { + .name = "ltq_etop", + .resource = <q_ethernet_resources, + .num_resources = 1, +}; + +void __init +ltq_register_ethernet(struct ltq_eth_data *eth) +{ + if (!eth) + return; + if (!is_valid_ether_addr(eth->mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + random_ether_addr(eth->mac.sa_data); + } + ltq_ethernet.dev.platform_data = eth; + platform_device_register(<q_ethernet); +} diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h index 87ba61e..29d831b 100644 --- a/arch/mips/lantiq/xway/devices.h +++ b/arch/mips/lantiq/xway/devices.h @@ -10,8 +10,10 @@ #define _LTQ_DEVICES_XWAY_H__ #include "../devices.h" +#include extern void ltq_register_gpio(void); extern void ltq_register_gpio_stp(void); +extern void ltq_register_ethernet(struct ltq_eth_data *eth); #endif diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c index 5242a27..a001761 100644 --- a/arch/mips/lantiq/xway/mach-easy50712.c +++ b/arch/mips/lantiq/xway/mach-easy50712.c @@ -59,13 +59,19 @@ static struct ltq_pci_data ltq_pci_data = { }, }; +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_MII, +}; + static void __init easy50712_init(void) { + ltq_register_dma(); ltq_register_gpio(); ltq_register_gpio_stp(); ltq_register_nor(&easy50712_flash_data); ltq_register_wdt(); ltq_register_pci(<q_pci_data); + ltq_register_ethernet(<q_eth_data); } MIPS_MACHINE(LTQ_MACH_EASY50712, -- 1.7.2.3 From blogic@openwrt.org Fri May 6 00:09:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 00:09:58 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:40665 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491007Ab1EEWI6 (ORCPT ); Fri, 6 May 2011 00:08:58 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: [PATCH V2 2/3] MIPS: lantiq: add ethernet driver Date: Fri, 6 May 2011 00:10:01 +0200 Message-Id: <1304633402-24161-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304633402-24161-1-git-send-email-blogic@openwrt.org> References: <1304633402-24161-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29833 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet work. Support for all 8 dma channels, gbit and the embedded switch found on the ar9/vr9 still needs to be implemented. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org --- Changes in V2: * use spinlocks * use NAPI * remove duplicate stats counter .../mips/include/asm/mach-lantiq/lantiq_platform.h | 7 + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/lantiq_etop.c | 794 ++++++++++++++++++++ 5 files changed, 811 insertions(+), 2 deletions(-) create mode 100644 drivers/net/lantiq_etop.c diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h index 1f1dba6..a305f1d 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h @@ -10,6 +10,7 @@ #define _LANTIQ_PLATFORM_H__ #include +#include /* struct used to pass info to the pci core */ enum { @@ -43,4 +44,10 @@ struct ltq_pci_data { int irq[16]; }; +/* struct used to pass info to network drivers */ +struct ltq_eth_data { + struct sockaddr mac; + int mii_mode; +}; + #endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 95f1882..0213601 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -81,8 +81,8 @@ #define PMU_SWITCH 0x10000000 /* ETOP - ethernet */ -#define LTQ_PPE32_BASE_ADDR 0xBE180000 -#define LTQ_PPE32_SIZE 0x40000 +#define LTQ_ETOP_BASE_ADDR 0x1E180000 +#define LTQ_ETOP_SIZE 0x40000 /* DMA */ #define LTQ_DMA_BASE_ADDR 0x1E104100 diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b30c688..4878587 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2017,6 +2017,13 @@ config FTMAC100 from Faraday. It is used on Faraday A320, Andes AG101 and some other ARM/NDS32 SoC's. +config LANTIQ_ETOP + tristate "Lantiq SoC ETOP driver" + depends on SOC_TYPE_XWAY + help + Support for the MII0 inside the Lantiq SoC + + source "drivers/net/fs_enet/Kconfig" source "drivers/net/octeon/Kconfig" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fbfca11..df71da7 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -261,6 +261,7 @@ obj-$(CONFIG_MLX4_CORE) += mlx4/ obj-$(CONFIG_ENC28J60) += enc28j60.o obj-$(CONFIG_ETHOC) += ethoc.o obj-$(CONFIG_GRETH) += greth.o +obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o diff --git a/drivers/net/lantiq_etop.c b/drivers/net/lantiq_etop.c new file mode 100644 index 0000000..3c9d34f --- /dev/null +++ b/drivers/net/lantiq_etop.c @@ -0,0 +1,794 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define LTQ_ETOP_MDIO 0x11804 +#define MDIO_REQUEST 0x80000000 +#define MDIO_READ 0x40000000 +#define MDIO_ADDR_MASK 0x1f +#define MDIO_ADDR_OFFSET 0x15 +#define MDIO_REG_MASK 0x1f +#define MDIO_REG_OFFSET 0x10 +#define MDIO_VAL_MASK 0xffff + +#define PPE32_CGEN 0x800 +#define LQ_PPE32_ENET_MAC_CFG 0x1840 + +#define LTQ_ETOP_ENETS0 0x11850 +#define LTQ_ETOP_MAC_DA0 0x1186C +#define LTQ_ETOP_MAC_DA1 0x11870 +#define LTQ_ETOP_CFG 0x16020 +#define LTQ_ETOP_IGPLEN 0x16080 + +#define MAX_DMA_CHAN 0x8 +#define MAX_DMA_CRC_LEN 0x4 +#define MAX_DMA_DATA_LEN 0x600 + +#define ETOP_FTCU BIT(28) +#define ETOP_MII_MASK 0xf +#define ETOP_MII_NORMAL 0xd +#define ETOP_MII_REVERSE 0xe +#define ETOP_PLEN_UNDER 0x40 +#define ETOP_CGEN 0x800 + +/* use 2 static channels for TX/RX */ +#define LTQ_ETOP_TX_CHANNEL 1 +#define LTQ_ETOP_RX_CHANNEL 6 +#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) + +#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) +#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) +#define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +#define DRV_VERSION "1.0" + +static void __iomem *ltq_etop_membase; + +struct ltq_etop_chan { + int idx; + int tx_free; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; + struct sk_buff *skb[LTQ_DESC_NUM]; +}; + +struct ltq_etop_priv { + struct net_device *netdev; + struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + struct phy_device *phydev; + + struct ltq_etop_chan ch[MAX_DMA_CHAN]; + int tx_free[MAX_DMA_CHAN >> 1]; + + spinlock_t lock; +}; + +static int +ltq_etop_alloc_skb(struct ltq_etop_chan *ch) +{ + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, + ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, DMA_FROM_DEVICE); + ch->dma.desc_base[ch->dma.desc].addr = + CPHYSADDR(ch->skb[ch->dma.desc]->data); + ch->dma.desc_base[ch->dma.desc].ctl = + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | MAX_DMA_DATA_LEN; + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); + return 0; +} + +static void +ltq_etop_hw_receive(struct ltq_etop_chan *ch) +{ + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + struct sk_buff *skb = ch->skb[ch->dma.desc]; + int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + if (ltq_etop_alloc_skb(ch)) { + netdev_err(ch->netdev, + "failed to allocate new rx buffer, stopping DMA\n"); + ltq_dma_close(&ch->dma); + } + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); + skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); +} + +static int +ltq_etop_poll_rx(struct napi_struct *napi, int budget) +{ + struct ltq_etop_chan *ch = container_of(napi, struct ltq_etop_chan, napi); + int rx = 0; + int complete = 0; + + while ((rx < budget) && !complete) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + ltq_etop_hw_receive(ch); + rx++; + } else { + complete = 1; + } + } + if (complete || !rx) { + napi_complete(&ch->napi); + ltq_dma_ack_irq(&ch->dma); + } + return rx; +} + +static int +ltq_etop_poll_tx(struct napi_struct *napi, int budget) +{ + struct ltq_etop_chan *ch = + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = + netdev_get_tx_queue(ch->netdev, ch->idx >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, + sizeof(struct ltq_dma_desc)); + ch->tx_free++; + ch->tx_free %= LTQ_DESC_NUM; + } + spin_unlock_irqrestore(&priv->lock, flags); + + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); + ltq_dma_ack_irq(&ch->dma); + return 1; +} + +static irqreturn_t +ltq_etop_dma_irq(int irq, void *_priv) +{ + struct ltq_etop_priv *priv = _priv; + int ch = irq - LTQ_DMA_CH0_INT; + + napi_schedule(&priv->ch[ch].napi); + return IRQ_HANDLED; +} + +static void +ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); + if (IS_RX(ch->idx)) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); + } +} + +static void +ltq_etop_hw_exit(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + + ltq_pmu_disable(PMU_PPE); + for (i = 0; i < MAX_DMA_CHAN; i++) + if (IS_TX(i) || IS_RX(i)) + ltq_etop_free_channel(dev, &priv->ch[i]); +} + +static int +ltq_etop_hw_init(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + + ltq_pmu_enable(PMU_PPE); + + switch (priv->pldata->mii_mode) { + case PHY_INTERFACE_MODE_RMII: + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_REVERSE, LTQ_ETOP_CFG); + break; + + case PHY_INTERFACE_MODE_MII: + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_NORMAL, LTQ_ETOP_CFG); + break; + + default: + netdev_err(dev, "unknown mii mode %d\n", + priv->pldata->mii_mode); + return -ENOTSUPP; + } + + /* enable crc generation */ + ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); + + ltq_dma_init_port(DMA_PORT_ETOP); + + for (i = 0; i < MAX_DMA_CHAN; i++) { + int irq = LTQ_DMA_CH0_INT + i; + struct ltq_etop_chan *ch = &priv->ch[i]; + + ch->idx = ch->dma.nr = i; + + if (IS_TX(i)) { + ltq_dma_alloc_tx(&ch->dma); + request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, + "etop_tx", priv); + } else if (IS_RX(i)) { + ltq_dma_alloc_rx(&ch->dma); + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; + ch->dma.desc++) + if (ltq_etop_alloc_skb(ch)) + return -ENOMEM; + ch->dma.desc = 0; + request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, + "etop_rx", priv); + } + ch->dma.irq = irq; + } + return 0; +} + +static void +ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) +{ + strcpy(info->driver, "Lantiq ETOP"); + strcpy(info->bus_info, "internal"); + strcpy(info->version, DRV_VERSION); +} + +static int +ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + return phy_ethtool_gset(priv->phydev, cmd); +} + +static int +ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + return phy_ethtool_sset(priv->phydev, cmd); +} + +static int +ltq_etop_nway_reset(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + return phy_start_aneg(priv->phydev); +} + +static const struct ethtool_ops ltq_etop_ethtool_ops = { + .get_drvinfo = ltq_etop_get_drvinfo, + .get_settings = ltq_etop_get_settings, + .set_settings = ltq_etop_set_settings, + .nway_reset = ltq_etop_nway_reset, +}; + +static int +ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) +{ + u32 val = MDIO_REQUEST | + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + ltq_etop_w32(val, LTQ_ETOP_MDIO); + return 0; +} + +static int +ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) +{ + u32 val = MDIO_REQUEST | MDIO_READ | + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + ltq_etop_w32(val, LTQ_ETOP_MDIO); + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; + return val; +} + +static void +ltq_etop_mdio_link(struct net_device *dev) +{ + /* nothing to do */ +} + +static int +ltq_etop_mdio_probe(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; + int phy_addr; + + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (priv->mii_bus->phy_map[phy_addr]) { + phydev = priv->mii_bus->phy_map[phy_addr]; + break; + } + } + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); + return -ENODEV; + } + + phydev = phy_connect(dev, dev_name(&phydev->dev), <q_etop_mdio_link, + 0, priv->pldata->mii_mode); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + + phydev->supported &= (SUPPORTED_10baseT_Half + | SUPPORTED_10baseT_Full + | SUPPORTED_100baseT_Half + | SUPPORTED_100baseT_Full + | SUPPORTED_Autoneg + | SUPPORTED_MII + | SUPPORTED_TP); + + phydev->advertising = phydev->supported; + priv->phydev = phydev; + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", + dev->name, phydev->drv->name, + dev_name(&phydev->dev), phydev->irq); + + return 0; +} + +static int +ltq_etop_mdio_init(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + int err; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { + netdev_err(dev, "failed to allocate mii bus\n"); + err = -ENOMEM; + goto err_out; + } + + priv->mii_bus->priv = dev; + priv->mii_bus->read = ltq_etop_mdio_rd; + priv->mii_bus->write = ltq_etop_mdio_wr; + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); + priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); + if (!priv->mii_bus->irq) { + err = -ENOMEM; + goto err_out_free_mdiobus; + } + + for (i = 0; i < PHY_MAX_ADDR; ++i) + priv->mii_bus->irq[i] = PHY_POLL; + + if (mdiobus_register(priv->mii_bus)) { + err = -ENXIO; + goto err_out_free_mdio_irq; + } + + if (ltq_etop_mdio_probe(dev)) { + err = -ENXIO; + goto err_out_unregister_bus; + } + return 0; + +err_out_unregister_bus: + mdiobus_unregister(priv->mii_bus); +err_out_free_mdio_irq: + kfree(priv->mii_bus->irq); +err_out_free_mdiobus: + mdiobus_free(priv->mii_bus); +err_out: + return err; +} + +static void +ltq_etop_mdio_cleanup(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + phy_disconnect(priv->phydev); + mdiobus_unregister(priv->mii_bus); + kfree(priv->mii_bus->irq); + mdiobus_free(priv->mii_bus); +} + +static int +ltq_etop_open(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + + for (i = 0; i < MAX_DMA_CHAN; i++) { + struct ltq_etop_chan *ch = &priv->ch[i]; + + if (!IS_TX(i) && (!IS_RX(i))) + continue; + ltq_dma_open(&ch->dma); + napi_enable(&ch->napi); + } + phy_start(priv->phydev); + netif_tx_start_all_queues(dev); + return 0; +} + +static int +ltq_etop_stop(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + + netif_tx_stop_all_queues(dev); + phy_stop(priv->phydev); + for (i = 0; i < MAX_DMA_CHAN; i++) { + struct ltq_etop_chan *ch = &priv->ch[i]; + + if (!IS_RX(i) && !IS_TX(i)) + continue; + napi_disable(&ch->napi); + ltq_dma_close(&ch->dma); + } + return 0; +} + +static int +ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) +{ + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); + struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + int len; + unsigned long flags; + u32 byte_offset; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { + dev_kfree_skb_any(skb); + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; + } + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; + ch->skb[ch->dma.desc] = skb; + + dev->trans_start = jiffies; + + spin_lock_irqsave(&priv->lock, flags); + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, + DMA_TO_DEVICE)) - byte_offset; + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + + if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +} + +static int +ltq_etop_change_mtu(struct net_device *dev, int new_mtu) +{ + int ret = eth_change_mtu(dev, new_mtu); + + if (!ret) { + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, + LTQ_ETOP_IGPLEN); + spin_unlock_irqrestore(&priv->lock, flags); + } + return ret; +} + +static int +ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ + return phy_mii_ioctl(priv->phydev, rq, cmd); +} + +static int +ltq_etop_set_mac_address(struct net_device *dev, void *p) +{ + int ret = eth_mac_addr(dev, p); + + if (!ret) { + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; + + /* store the mac for the unicast filter */ + spin_lock_irqsave(&priv->lock, flags); + ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); + ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, + LTQ_ETOP_MAC_DA1); + spin_unlock_irqrestore(&priv->lock, flags); + } + return ret; +} + +static void +ltq_etop_set_multicast_list(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; + + /* ensure that the unicast filter is not enabled in promiscious mode */ + spin_lock_irqsave(&priv->lock, flags); + if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) + ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); + else + ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static u16 +ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb) +{ + /* we are currently only using the first queue */ + return 0; +} + +static int +ltq_etop_init(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int err; + + ether_setup(dev); + dev->watchdog_timeo = 10 * HZ; + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); + err = ltq_etop_set_mac_address(dev, &priv->pldata->mac); + if (err) + goto err_netdev; + ltq_etop_set_multicast_list(dev); + err = ltq_etop_mdio_init(dev); + if (err) + goto err_netdev; + return 0; + +err_netdev: + unregister_netdev(dev); + free_netdev(dev); +err_hw: + ltq_etop_hw_exit(dev); + return err; +} + +static void +ltq_etop_tx_timeout(struct net_device *dev) +{ + int err; + + ltq_etop_hw_exit(dev); + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; + dev->trans_start = jiffies; + netif_wake_queue(dev); + return; + +err_hw: + ltq_etop_hw_exit(dev); + netdev_err(dev, "failed to restart etop after TX timeout\n"); +} + +static const struct net_device_ops ltq_eth_netdev_ops = { + .ndo_open = ltq_etop_open, + .ndo_stop = ltq_etop_stop, + .ndo_start_xmit = ltq_etop_tx, + .ndo_change_mtu = ltq_etop_change_mtu, + .ndo_do_ioctl = ltq_etop_ioctl, + .ndo_set_mac_address = ltq_etop_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_multicast_list = ltq_etop_set_multicast_list, + .ndo_select_queue = ltq_etop_select_queue, + .ndo_init = ltq_etop_init, + .ndo_tx_timeout = ltq_etop_tx_timeout, +}; + +static int __init +ltq_etop_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct ltq_etop_priv *priv; + struct resource *res; + int err; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get etop resource\n"); + err = -ENOENT; + goto err_out; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request etop resource\n"); + err = -EBUSY; + goto err_out; + } + + ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_etop_membase) { + dev_err(&pdev->dev, "failed to remap etop engine %d\n", + pdev->id); + err = -ENOMEM; + goto err_out; + } + + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; + dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; + spin_lock_init(&priv->lock); + + for (i = 0; i < MAX_DMA_CHAN; i++) { + if (IS_TX(i)) + netif_napi_add(dev, &priv->ch[i].napi, + ltq_etop_poll_tx, 8); + else if (IS_RX(i)) + netif_napi_add(dev, &priv->ch[i].napi, + ltq_etop_poll_rx, 32); + priv->ch[i].netdev = dev; + } + + err = register_netdev(dev); + if (err) + goto err_free; + + platform_set_drvdata(pdev, dev); + return 0; + +err_free: + kfree(dev); +err_out: + return err; +} + +static int __devexit +ltq_etop_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (dev) { + netif_tx_stop_all_queues(dev); + ltq_etop_hw_exit(dev); + ltq_etop_mdio_cleanup(dev); + unregister_netdev(dev); + } + return 0; +} + +static struct platform_driver ltq_mii_driver = { + .remove = __devexit_p(ltq_etop_remove), + .driver = { + .name = "ltq_etop", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_etop(void) +{ + int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); + + if (ret) + pr_err("ltq_etop: Error registering platfom driver!"); + return ret; +} + +static void __exit +exit_ltq_etop(void) +{ + platform_driver_unregister(<q_mii_driver); +} + +module_init(init_ltq_etop); +module_exit(exit_ltq_etop); + +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC ETOP"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 From davem@davemloft.net Fri May 6 00:11:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 00:11:30 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:38137 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490992Ab1EEWLY (ORCPT ); Fri, 6 May 2011 00:11:24 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 3AF0824C088; Thu, 5 May 2011 15:10:50 -0700 (PDT) Date: Thu, 05 May 2011 15:10:49 -0700 (PDT) Message-Id: <20110505.151049.35056363.davem@davemloft.net> To: blogic@openwrt.org Cc: ralf@linux-mips.org, ralph.hempel@lantiq.com, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH V2 2/3] MIPS: lantiq: add ethernet driver From: David Miller In-Reply-To: <1304633402-24161-3-git-send-email-blogic@openwrt.org> References: <1304633402-24161-1-git-send-email-blogic@openwrt.org> <1304633402-24161-3-git-send-email-blogic@openwrt.org> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29834 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: John Crispin Date: Fri, 6 May 2011 00:10:01 +0200 > This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found > inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet > work. Support for all 8 dma channels, gbit and the embedded switch found on > the ar9/vr9 still needs to be implemented. > > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel No objections from me and this can go via the MIPS tree: Acked-by: David S. Miller From blogic@openwrt.org Fri May 6 00:15:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 00:15:08 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:41187 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490992Ab1EEWPD (ORCPT ); Fri, 6 May 2011 00:15:03 +0200 Message-ID: <4DC321C7.8060600@openwrt.org> Date: Fri, 06 May 2011 00:16:39 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: David Miller CC: ralf@linux-mips.org, ralph.hempel@lantiq.com, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH V2 2/3] MIPS: lantiq: add ethernet driver References: <1304633402-24161-1-git-send-email-blogic@openwrt.org> <1304633402-24161-3-git-send-email-blogic@openwrt.org> <20110505.151049.35056363.davem@davemloft.net> In-Reply-To: <20110505.151049.35056363.davem@davemloft.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29835 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips On 06/05/11 00:10, David Miller wrote: > From: John Crispin > Date: Fri, 6 May 2011 00:10:01 +0200 > > >> This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found >> inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet >> work. Support for all 8 dma channels, gbit and the embedded switch found on >> the ar9/vr9 still needs to be implemented. >> >> Signed-off-by: John Crispin >> Signed-off-by: Ralph Hempel >> > No objections from me and this can go via the MIPS tree: > > Acked-by: David S. Miller > > Thank you ! From aoliva@redhat.com Fri May 6 10:30:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 10:30:57 +0200 (CEST) Received: from mx1.redhat.com ([209.132.183.28]:29474 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491015Ab1EFIay (ORCPT ); Fri, 6 May 2011 10:30:54 +0200 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p468UTux029351 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 6 May 2011 04:30:29 -0400 Received: from freie.oliva.athome.lsd.ic.unicamp.br (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p468UQ4Q009687 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 May 2011 04:30:28 -0400 Received: from livre.localdomain (livre-to-gw.oliva.athome.lsd.ic.unicamp.br [172.31.160.19]) by freie.oliva.athome.lsd.ic.unicamp.br (8.14.4/8.14.4) with ESMTP id p468UPAO017491; Fri, 6 May 2011 05:30:25 -0300 Received: from livre.localdomain (aoliva@localhost.localdomain [127.0.0.1]) by livre.localdomain (8.14.3/8.14.3/Debian-5+lenny1) with ESMTP id p468TJ8S006941; Fri, 6 May 2011 05:29:19 -0300 Received: (from aoliva@localhost) by livre.localdomain (8.14.3/8.14.3/Submit) id p468TGfq006939; Fri, 6 May 2011 05:29:16 -0300 X-Authentication-Warning: livre.localdomain: aoliva set sender to aoliva@redhat.com using -f From: Alexandre Oliva To: David Daney Cc: linux-mips , GCC , binutils , Prasun Kapoor Subject: Re: RFC: A new MIPS64 ABI Organization: Free thinker, does not speak for Red Hat or its Operating System Tools Group References: <4D5990A4.2050308@caviumnetworks.com> <4D5AC12D.3080108@caviumnetworks.com> Date: Fri, 06 May 2011 05:29:16 -0300 In-Reply-To: <4D5AC12D.3080108@caviumnetworks.com> (David Daney's message of "Tue, 15 Feb 2011 10:08:45 -0800") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29836 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aoliva@redhat.com Precedence: bulk X-list: linux-mips On Feb 15, 2011, David Daney wrote: > On 02/15/2011 09:56 AM, Alexandre Oliva wrote: >> On Feb 14, 2011, David Daney wrote: >> So, sorry if this is a dumb question, but wouldn't it be much easier to >> keep on using sign-extended addresses, and just make sure the kernel >> never allocates a virtual memory range that crosses a sign-bit change, > No, it is not possible. The MIPS (and MIPS64) hardware architecture > does not allow userspace access to addresses with the high bit (two > bits for mips64) set. Interesting. I guess this makes it far easier to transition to the u32 ABI: n32 addresses all have the 32-bit MSB bit clear, so n32 binaries can be used within u32 environments, as long as the environment refrains from using addresses that have the MSB bit set. So we could switch lib32 to u32, have a machine-specific bit set for u32 binaries, and if the kernel starts an executable or interpreter that has that bit clear, it will refrain from allocating any n32-invalid address for that process. Furthermore, libc, upon loading a library, should be able to notify the kernel when an n32 library is to be loaded, to which the kernel would respond either with failure (if that process already uses u32-valid but n32-invalid addresses) or success (switching to n32 mode if not in it already). Am I missing any other issues? -- Alexandre Oliva, freedom fighter http://FSFLA.org/~lxoliva/ You must be the change you wish to see in the world. -- Gandhi Be Free! -- http://FSFLA.org/ FSF Latin America board member Free Software Evangelist Red Hat Brazil Compiler Engineer From sshtylyov@mvista.com Fri May 6 12:07:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 12:07:41 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:37477 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491019Ab1EFKHi (ORCPT ); Fri, 6 May 2011 12:07:38 +0200 Received: by ewy3 with SMTP id 3so1028628ewy.36 for ; Fri, 06 May 2011 03:07:31 -0700 (PDT) Received: by 10.213.110.18 with SMTP id l18mr780567ebp.57.1304676451616; Fri, 06 May 2011 03:07:31 -0700 (PDT) Received: from [192.168.2.2] ([91.79.96.47]) by mx.google.com with ESMTPS id 46sm1196579ees.11.2011.05.06.03.07.26 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 06 May 2011 03:07:27 -0700 (PDT) Message-ID: <4DC3C7FC.9050807@mvista.com> Date: Fri, 06 May 2011 14:05:48 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v3 2/6] of: Make of_find_node_by_path() traverse /aliases for relative paths. References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> <1304614949-30460-3-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1304614949-30460-3-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29837 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 05-05-2011 21:02, David Daney wrote: > Currently all paths passed to of_find_node_by_path() must begin with a > '/', indicating a full path to the desired node. > Augment the look-up code so that if a path does *not* begin with '/', > the path is used as the name of an /aliases property. The value of > this alias is then used as the full node path to be found. > Signed-off-by: David Daney > --- > drivers/of/base.c | 41 ++++++++++++++++++++++++++++++++++++++++- > 1 files changed, 40 insertions(+), 1 deletions(-) > diff --git a/drivers/of/base.c b/drivers/of/base.c > index 632ebae..1a0a83e 100644 > --- a/drivers/of/base.c > +++ b/drivers/of/base.c [...] > @@ -348,14 +351,50 @@ EXPORT_SYMBOL(of_get_next_child); > struct device_node *of_find_node_by_path(const char *path) > { > struct device_node *np = allnodes; > + struct device_node *aliases = NULL; > + char *alias = NULL; > + char *new_path = NULL; > > read_lock(&devtree_lock); > + > + if (path[0] != '/') { > + const char *ps; > + aliases = of_find_node_by_path("/aliases"); > + if (!aliases) > + goto out; > + > + ps = strchr(path, '/'); > + if (ps) { > + size_t len = ps - path; > + alias = kmalloc(len + 1, GFP_KERNEL); How about error handling? > + strncpy(alias, path, len); > + alias[len] = 0; > + path = of_get_property(aliases, alias, NULL); > + if (!path) > + goto out; > + len = strlen(path) + strlen(ps) + 1; > + new_path = kmalloc(len, GFP_KERNEL); Here too... WBR, Sergei From sshtylyov@mvista.com Fri May 6 12:18:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 12:19:01 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:36139 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491015Ab1EFKS6 (ORCPT ); Fri, 6 May 2011 12:18:58 +0200 Received: by ewy3 with SMTP id 3so1031894ewy.36 for ; Fri, 06 May 2011 03:18:53 -0700 (PDT) Received: by 10.213.2.208 with SMTP id 16mr87239ebk.32.1304677132840; Fri, 06 May 2011 03:18:52 -0700 (PDT) Received: from [192.168.2.2] ([91.79.96.47]) by mx.google.com with ESMTPS id s1sm1215963ees.3.2011.05.06.03.18.50 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 06 May 2011 03:18:51 -0700 (PDT) Message-ID: <4DC3CAA9.5040203@mvista.com> Date: Fri, 06 May 2011 14:17:13 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v3 2/6] of: Make of_find_node_by_path() traverse /aliases for relative paths. References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> <1304614949-30460-3-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1304614949-30460-3-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29838 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 05-05-2011 21:02, David Daney wrote: > Currently all paths passed to of_find_node_by_path() must begin with a > '/', indicating a full path to the desired node. > Augment the look-up code so that if a path does *not* begin with '/', > the path is used as the name of an /aliases property. The value of > this alias is then used as the full node path to be found. > Signed-off-by: David Daney > --- > drivers/of/base.c | 41 ++++++++++++++++++++++++++++++++++++++++- > 1 files changed, 40 insertions(+), 1 deletions(-) > diff --git a/drivers/of/base.c b/drivers/of/base.c > index 632ebae..1a0a83e 100644 > --- a/drivers/of/base.c > +++ b/drivers/of/base.c [...] > @@ -348,14 +351,50 @@ EXPORT_SYMBOL(of_get_next_child); > struct device_node *of_find_node_by_path(const char *path) > { > struct device_node *np = allnodes; > + struct device_node *aliases = NULL; > + char *alias = NULL; > + char *new_path = NULL; > > read_lock(&devtree_lock); > + > + if (path[0] != '/') { > + const char *ps; > + aliases = of_find_node_by_path("/aliases"); > + if (!aliases) > + goto out; > + > + ps = strchr(path, '/'); > + if (ps) { > + size_t len = ps - path; > + alias = kmalloc(len + 1, GFP_KERNEL); > + strncpy(alias, path, len); > + alias[len] = 0; BTW, you could use kstrndup() (from mm/util.c) instead of the above 3 lines. WBR, Sergei From sshtylyov@mvista.com Fri May 6 12:28:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 12:28:12 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:56015 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491015Ab1EFK2H (ORCPT ); Fri, 6 May 2011 12:28:07 +0200 Received: by ewy3 with SMTP id 3so1034226ewy.36 for ; Fri, 06 May 2011 03:28:02 -0700 (PDT) Received: by 10.14.17.6 with SMTP id i6mr1673015eei.51.1304677682110; Fri, 06 May 2011 03:28:02 -0700 (PDT) Received: from [192.168.2.2] ([91.79.96.47]) by mx.google.com with ESMTPS id e32sm1195003eee.5.2011.05.06.03.27.55 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 06 May 2011 03:27:57 -0700 (PDT) Message-ID: <4DC3CCC9.4040002@mvista.com> Date: Fri, 06 May 2011 14:26:17 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , Ralph Hempel , linux-mips@linux-mips.org Subject: Re: [PATCH V2 3/3] MIPS: lantiq: add dma/etop board support References: <1304633402-24161-1-git-send-email-blogic@openwrt.org> <1304633402-24161-4-git-send-email-blogic@openwrt.org> In-Reply-To: <1304633402-24161-4-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29839 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 06-05-2011 2:10, John Crispin wrote: > This patch adds functions to register the etop and dma platform devices and > calls them from the board specific setup code. > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel > Cc: linux-mips@linux-mips.org [...] > diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c > index e758863..a10244e 100644 > --- a/arch/mips/lantiq/devices.c > +++ b/arch/mips/lantiq/devices.c > @@ -31,6 +31,19 @@ > #define IRQ_RES(resname, irq) \ > {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} > > +/* dma engine */ > +static struct resource ltq_dma_resource = { > + .name = "dma", > + .start = LTQ_DMA_BASE_ADDR, > + .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, > + .flags = IORESOURCE_MEM, Spaces before = instead of tab here. > diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c > index 7d58ae5..99ff2ef 100644 > --- a/arch/mips/lantiq/xway/devices.c > +++ b/arch/mips/lantiq/xway/devices.c > @@ -75,3 +75,30 @@ void __init ltq_register_gpio_stp(void) > { > platform_device_register_simple("ltq_stp", 0,<q_stp_resource, 1); > } > + > +/* ethernet */ > +static struct resource ltq_ethernet_resources = { > + .name = "etop", > + .start = LTQ_ETOP_BASE_ADDR, > + .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, > + .flags = IORESOURCE_MEM, It's better to use tabs, not spaces between the filed names and =, like above... > +}; > + > +static struct platform_device ltq_ethernet = { > + .name = "ltq_etop", > + .resource =<q_ethernet_resources, > + .num_resources = 1, Too many spaces? > +}; > + > +void __init > +ltq_register_ethernet(struct ltq_eth_data *eth) > +{ > + if (!eth) > + return; > + if (!is_valid_ether_addr(eth->mac.sa_data)) { > + pr_warn("etop: invalid MAC, using random\n"); > + random_ether_addr(eth->mac.sa_data); > + } Why not do it in the driver? > + ltq_ethernet.dev.platform_data = eth; > + platform_device_register(<q_ethernet); > +} [...] > diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c > index 5242a27..a001761 100644 > --- a/arch/mips/lantiq/xway/mach-easy50712.c > +++ b/arch/mips/lantiq/xway/mach-easy50712.c > @@ -59,13 +59,19 @@ static struct ltq_pci_data ltq_pci_data = { > }, > }; > > +static struct ltq_eth_data ltq_eth_data = { > + .mii_mode = PHY_INTERFACE_MODE_MII, > +}; > + > static void __init easy50712_init(void) > { > + ltq_register_dma(); > ltq_register_gpio(); > ltq_register_gpio_stp(); > ltq_register_nor(&easy50712_flash_data); > ltq_register_wdt(); > ltq_register_pci(<q_pci_data); > + ltq_register_ethernet(<q_eth_data); > } > > MIPS_MACHINE(LTQ_MACH_EASY50712, I'd put the board code in a sperate patch... WBR, Sergei From mmarek@suse.cz Fri May 6 12:56:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 12:56:30 +0200 (CEST) Received: from cantor.suse.de ([195.135.220.2]:56711 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491056Ab1EFK41 (ORCPT ); Fri, 6 May 2011 12:56:27 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 9F74A94746; Fri, 6 May 2011 12:56:22 +0200 (CEST) Message-ID: <4DC3D3D5.6060007@suse.cz> Date: Fri, 06 May 2011 12:56:21 +0200 From: Michal Marek User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.14) Gecko/20110221 SUSE/3.1.8 Thunderbird/3.1.8 MIME-Version: 1.0 To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v3 1/6] of: Allow scripts/dtc/libfdt to be used from kernel code References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> <1304614949-30460-2-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1304614949-30460-2-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29840 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mmarek@suse.cz Precedence: bulk X-list: linux-mips On 5.5.2011 19:02, David Daney wrote: > --- /dev/null > +++ b/drivers/of/libfdt/Makefile > @@ -0,0 +1,8 @@ > +ccflags-y := -include linux/libfdt_env.h -I$(src)/../../../scripts/dtc/libfdt > + > +obj-y = fdt.o fdt_wip.o fdt_ro.o > + > + > +$(obj)/%.o: $(src)/../../../scripts/dtc/libfdt/%.c FORCE > + $(call cmd,force_checksrc) > + $(call if_changed_rule,cc_o_c) It's just three source files, so you could use three one-line wrappers that #include ../../../scripts/dtc/libfdt/.c instead of copying the %.c -> %.o rule here. Michal From David.Daney@caviumnetworks.com Fri May 6 19:00:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 19:00:27 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15577 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491069Ab1EFRAT (ORCPT ); Fri, 6 May 2011 19:00:19 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 06 May 2011 10:01:16 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 6 May 2011 10:00:15 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 6 May 2011 10:00:15 -0700 Message-ID: <4DC42919.5030403@caviumnetworks.com> Date: Fri, 06 May 2011 10:00:09 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Alexandre Oliva CC: linux-mips , GCC , binutils , Prasun Kapoor , Ralf Baechle Subject: Re: RFC: A new MIPS64 ABI References: <4D5990A4.2050308@caviumnetworks.com> <4D5AC12D.3080108@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 May 2011 17:00:15.0147 (UTC) FILETIME=[11E9A7B0:01CC0C0F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29841 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 05/06/2011 01:29 AM, Alexandre Oliva wrote: > On Feb 15, 2011, David Daney wrote: > >> On 02/15/2011 09:56 AM, Alexandre Oliva wrote: >>> On Feb 14, 2011, David Daney wrote: > >>> So, sorry if this is a dumb question, but wouldn't it be much easier to >>> keep on using sign-extended addresses, and just make sure the kernel >>> never allocates a virtual memory range that crosses a sign-bit change, > >> No, it is not possible. The MIPS (and MIPS64) hardware architecture >> does not allow userspace access to addresses with the high bit (two >> bits for mips64) set. > > Interesting. I guess this makes it far easier to transition to the u32 > ABI: n32 addresses all have the 32-bit MSB bit clear, so n32 binaries > can be used within u32 environments, as long as the environment refrains > from using addresses that have the MSB bit set. > Correct. > So we could switch lib32 to u32, have a machine-specific bit set for u32 > binaries, and if the kernel starts an executable or interpreter that has > that bit clear, it will refrain from allocating any n32-invalid address > for that process. Furthermore, libc, upon loading a library, should be > able to notify the kernel when an n32 library is to be loaded, to which > the kernel would respond either with failure (if that process already > uses u32-valid but n32-invalid addresses) or success (switching to n32 > mode if not in it already). > > Am I missing any other issues? No, this is pretty much what Ralf and I came up with on IRC. We tag u32 objects (in a similar manner to how non-executable stack is done). The linker will propagate the u32 tag as it links things together. u32 shared libraries are compatible with legacy n32 binaries as long as the OS doesn't map any memory where the address has bit 31 set. When the OS loads an n32 executable it would check the u32 tag (both of the executable and ld.so) and adjust its memory allocation strategy. The OS will continue to map the VDSO at the 2GB point. This will cause the maximum size of any object to be compatible with the 32-bit n32 ptrdiff_t. I think once the OS puts a process into u32 mode, there is no going back. We would just have ld.so refuse to load any shared objects that were not compatible with the current mode. We would continue to place libraries in /lib32, /usr/lib32, /usr/local/lib32, etc. David Daney From David.Daney@caviumnetworks.com Fri May 6 19:14:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 19:14:38 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16053 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491069Ab1EFROe (ORCPT ); Fri, 6 May 2011 19:14:34 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 06 May 2011 10:15:33 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 6 May 2011 10:14:31 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 6 May 2011 10:14:31 -0700 Message-ID: <4DC42C72.1010306@caviumnetworks.com> Date: Fri, 06 May 2011 10:14:26 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Michal Marek CC: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v3 1/6] of: Allow scripts/dtc/libfdt to be used from kernel code References: <1304614949-30460-1-git-send-email-ddaney@caviumnetworks.com> <1304614949-30460-2-git-send-email-ddaney@caviumnetworks.com> <4DC3D3D5.6060007@suse.cz> In-Reply-To: <4DC3D3D5.6060007@suse.cz> Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 May 2011 17:14:31.0901 (UTC) FILETIME=[1093F0D0:01CC0C11] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29842 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 05/06/2011 03:56 AM, Michal Marek wrote: > On 5.5.2011 19:02, David Daney wrote: >> --- /dev/null >> +++ b/drivers/of/libfdt/Makefile >> @@ -0,0 +1,8 @@ >> +ccflags-y := -include linux/libfdt_env.h >> -I$(src)/../../../scripts/dtc/libfdt >> + >> +obj-y = fdt.o fdt_wip.o fdt_ro.o >> + >> + >> +$(obj)/%.o: $(src)/../../../scripts/dtc/libfdt/%.c FORCE >> + $(call cmd,force_checksrc) >> + $(call if_changed_rule,cc_o_c) > > It's just three source files, so you could use three one-line wrappers > that #include ../../../scripts/dtc/libfdt/.c instead of copying > the %.c -> %.o rule here. > Good idea, that does seem cleaner. I will adjust the patch. David Daney From jayachandranc@netlogicmicro.com Fri May 6 22:05:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:05:05 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:2780 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491100Ab1EFUFA (ORCPT ); Fri, 6 May 2011 22:05:00 +0200 X-TM-IMSS-Message-ID: <2cf41b740003a93c@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf41b740003a93c ; Fri, 6 May 2011 13:04:29 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:05:54 -0700 Date: Sat, 7 May 2011 01:36:05 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 2/8] mach-netlogic include directory and files. Message-ID: <9718c3f12f279f43876be5b266fcf6d35ec87306.1304712046.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:05:55.0134 (UTC) FILETIME=[01DCC5E0:01CC0C29] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29843 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add war.h and irq.h with XLR/XLS definitions. Add feature overrides for XLR/XLS. Signed-off-by: Jayachandran C --- .../asm/mach-netlogic/cpu-feature-overrides.h | 47 ++++++++++++++++++++ arch/mips/include/asm/mach-netlogic/irq.h | 14 ++++++ arch/mips/include/asm/mach-netlogic/war.h | 26 +++++++++++ 3 files changed, 87 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h new file mode 100644 index 0000000..3b72827 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_counter 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_icache_snoops_remote_store 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h new file mode 100644 index 0000000..b590245 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/irq.h @@ -0,0 +1,14 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + */ +#ifndef __ASM_NETLOGIC_IRQ_H +#define __ASM_NETLOGIC_IRQ_H + +#define NR_IRQS 64 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* __ASM_NETLOGIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h new file mode 100644 index 0000000..22da893 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/war.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_NLM_WAR_H +#define __ASM_MIPS_MACH_NLM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_NLM_WAR_H */ -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri May 6 22:05:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:05:32 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:2782 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491099Ab1EFUFA (ORCPT ); Fri, 6 May 2011 22:05:00 +0200 X-TM-IMSS-Message-ID: <2cf41b160003a93b@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf41b160003a93b ; Fri, 6 May 2011 13:04:29 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:05:37 -0700 Date: Sat, 7 May 2011 01:35:48 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 1/8] Netlogic XLR/XLS processor IDs. Message-ID: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:05:37.0900 (UTC) FILETIME=[F79712C0:01CC0C28] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29844 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add Netlogic Microsystems company ID and processor IDs for XLR and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. Signed-off-by: Jayachandran C --- arch/mips/include/asm/cpu.h | 27 ++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..34c0d3c 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 @@ -142,6 +143,31 @@ #define PRID_IMP_JZRISC 0x0200 /* + * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC + */ +#define PRID_IMP_NETLOGIC_XLR732 0x0000 +#define PRID_IMP_NETLOGIC_XLR716 0x0200 +#define PRID_IMP_NETLOGIC_XLR532 0x0900 +#define PRID_IMP_NETLOGIC_XLR308 0x0600 +#define PRID_IMP_NETLOGIC_XLR532C 0x0800 +#define PRID_IMP_NETLOGIC_XLR516C 0x0a00 +#define PRID_IMP_NETLOGIC_XLR508C 0x0b00 +#define PRID_IMP_NETLOGIC_XLR308C 0x0f00 +#define PRID_IMP_NETLOGIC_XLS608 0x8000 +#define PRID_IMP_NETLOGIC_XLS408 0x8800 +#define PRID_IMP_NETLOGIC_XLS404 0x8c00 +#define PRID_IMP_NETLOGIC_XLS208 0x8e00 +#define PRID_IMP_NETLOGIC_XLS204 0x8f00 +#define PRID_IMP_NETLOGIC_XLS108 0xce00 +#define PRID_IMP_NETLOGIC_XLS104 0xcf00 +#define PRID_IMP_NETLOGIC_XLS616B 0x4000 +#define PRID_IMP_NETLOGIC_XLS608B 0x4a00 +#define PRID_IMP_NETLOGIC_XLS416B 0x4400 +#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 +#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 +#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 + +/* * Definitions for 7:0 on legacy processors */ @@ -234,6 +260,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, + CPU_XLR, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..130aa7a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + c->options = (MIPS_CPU_TLB | + MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | + MIPS_CPU_WATCH | + MIPS_CPU_EJTAG | + MIPS_CPU_LLSC); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_NETLOGIC_XLR732: + case PRID_IMP_NETLOGIC_XLR716: + case PRID_IMP_NETLOGIC_XLR532: + case PRID_IMP_NETLOGIC_XLR308: + case PRID_IMP_NETLOGIC_XLR532C: + case PRID_IMP_NETLOGIC_XLR516C: + case PRID_IMP_NETLOGIC_XLR508C: + case PRID_IMP_NETLOGIC_XLR308C: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLR"; + break; + + case PRID_IMP_NETLOGIC_XLS608: + case PRID_IMP_NETLOGIC_XLS408: + case PRID_IMP_NETLOGIC_XLS404: + case PRID_IMP_NETLOGIC_XLS208: + case PRID_IMP_NETLOGIC_XLS204: + case PRID_IMP_NETLOGIC_XLS108: + case PRID_IMP_NETLOGIC_XLS104: + case PRID_IMP_NETLOGIC_XLS616B: + case PRID_IMP_NETLOGIC_XLS608B: + case PRID_IMP_NETLOGIC_XLS416B: + case PRID_IMP_NETLOGIC_XLS412B: + case PRID_IMP_NETLOGIC_XLS408B: + case PRID_IMP_NETLOGIC_XLS404B: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLS"; + break; + + default: + printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", + c->processor_id); + c->cputype = CPU_XLR; + break; + } + + c->isa_level = MIPS_CPU_ISA_M64R1; + c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; +} + #ifdef CONFIG_64BIT /* For use by uaccess.h */ u64 __ua_limit; @@ -1034,6 +1087,8 @@ __cpuinit void cpu_probe(void) break; case PRID_COMP_INGENIC: cpu_probe_ingenic(c, cpu); + case PRID_COMP_NETLOGIC: + cpu_probe_netlogic(c, cpu); break; } -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri May 6 22:05:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:05:57 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:2781 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491098Ab1EFUFA (ORCPT ); Fri, 6 May 2011 22:05:00 +0200 X-TM-IMSS-Message-ID: <2cf41ab80003a93a@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf41ab80003a93a ; Fri, 6 May 2011 13:04:29 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:05:19 -0700 Date: Sat, 7 May 2011 01:35:30 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 0/8] Support for Netlogic XLR/XLS processors. Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:05:20.0150 (UTC) FILETIME=[ED02A360:01CC0C28] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29845 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Reposting this again. I also have the initial XLP patchset ready, but I will wait for this to be queued before posting the rest. As always, please let me know if you have any comments on the code or license. Thanks, JC. Jayachandran C (8): Netlogic XLR/XLS processor IDs. mach-netlogic include directory and files. Cache support, TLB support, asm/module.h entry Platform files for XLR/XLS processor support. Kconfig and Makefile update for Netlogic XLR/XLS Add default configuration for XLR/XLS processors PCI support for XLR/XLS USB support for XLS platforms. arch/mips/Kconfig | 44 + arch/mips/Makefile | 12 + arch/mips/configs/nlm_xlr_defconfig | 1705 ++++++++++++++++++++ arch/mips/include/asm/cpu.h | 27 + .../asm/mach-netlogic/cpu-feature-overrides.h | 47 + arch/mips/include/asm/mach-netlogic/irq.h | 14 + arch/mips/include/asm/mach-netlogic/war.h | 26 + arch/mips/include/asm/module.h | 2 + arch/mips/include/asm/netlogic/interrupt.h | 45 + arch/mips/include/asm/netlogic/mips-extns.h | 76 + arch/mips/include/asm/netlogic/psb-bootinfo.h | 109 ++ arch/mips/include/asm/netlogic/xlr/gpio.h | 73 + arch/mips/include/asm/netlogic/xlr/iomap.h | 131 ++ arch/mips/include/asm/netlogic/xlr/pic.h | 231 +++ arch/mips/include/asm/netlogic/xlr/xlr.h | 75 + arch/mips/kernel/Makefile | 1 + arch/mips/kernel/cpu-probe.c | 55 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + arch/mips/netlogic/Kconfig | 5 + arch/mips/netlogic/xlr/Makefile | 5 + arch/mips/netlogic/xlr/irq.c | 300 ++++ arch/mips/netlogic/xlr/platform.c | 187 +++ arch/mips/netlogic/xlr/setup.c | 188 +++ arch/mips/netlogic/xlr/smp.c | 225 +++ arch/mips/netlogic/xlr/smpboot.S | 94 ++ arch/mips/netlogic/xlr/time.c | 51 + arch/mips/netlogic/xlr/xlr_console.c | 46 + arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlr.c | 214 +++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-xls.c | 161 ++ drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-xls.c | 151 ++ 36 files changed, 4315 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c create mode 100644 arch/mips/pci/pci-xlr.c create mode 100644 drivers/usb/host/ehci-xls.c create mode 100644 drivers/usb/host/ohci-xls.c -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri May 6 22:06:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:06:20 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:3883 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491104Ab1EFUF7 (ORCPT ); Fri, 6 May 2011 22:05:59 +0200 X-TM-IMSS-Message-ID: <2cf508060003a948@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf508060003a948 ; Fri, 6 May 2011 13:05:30 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:06:12 -0700 Date: Sat, 7 May 2011 01:36:21 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 3/8] Cache support, TLB support, asm/module.h entry Message-ID: <07e3b598b08cb1f1f31b4c6e461f3c06e8711c47.1304712046.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:06:12.0494 (UTC) FILETIME=[0C35B2E0:01CC0C29] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips CPU_XLR case added to mm/tlbex.c CPU_XLR case added to mm/c-r4k.c for PINDEX attribute Add XLR to asm/module.h Signed-off-by: Jayachandran C --- arch/mips/include/asm/module.h | 2 ++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 3 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index d94085a..bc01a02 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON2 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " +#elif defined CONFIG_CPU_XLR +#define MODULE_PROC_FAMILY "XLR " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 71bddf8..d9bc5d3 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1006,6 +1006,7 @@ static void __cpuinit probe_pcache(void) case CPU_25KF: case CPU_SB1: case CPU_SB1A: + case CPU_XLR: c->dcache.flags |= MIPS_CACHE_PINDEX; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index f5734c2..424ed4b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: + case CPU_XLR: uasm_i_nop(p); tlbw(p); break; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri May 6 22:06:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:06:46 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:3882 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491105Ab1EFUGA (ORCPT ); Fri, 6 May 2011 22:06:00 +0200 X-TM-IMSS-Message-ID: <2cf5092f0003a94a@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf5092f0003a94a ; Fri, 6 May 2011 13:05:30 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:06:47 -0700 Date: Sat, 7 May 2011 01:36:57 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 5/8] Kconfig and Makefile update for Netlogic XLR/XLS Message-ID: <88b9f2509f086d61c6621ae04a0e41f2353387e6.1304712046.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:06:47.0291 (UTC) FILETIME=[20F34CB0:01CC0C29] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add NLM_XLR_BOARD, CPU_XLR and other config options Makefile updates, mostly based on r4k Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 42 +++++++++++++++++++++++++++++++++++++++ arch/mips/Makefile | 12 +++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/netlogic/Kconfig | 5 ++++ arch/mips/netlogic/xlr/Makefile | 5 ++++ 7 files changed, 67 insertions(+), 0 deletions(-) create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 351c80f..5016caa 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -736,6 +736,33 @@ config CAVIUM_OCTEON_REFERENCE_BOARD Hikari Say Y here for most Octeon reference boards. +config NLM_XLR_BOARD + bool "Netlogic XLR/XLS based systems" + depends on EXPERIMENTAL + select BOOT_ELF32 + select NLM_COMMON + select NLM_XLR + select SYS_HAS_CPU_XLR + select SYS_SUPPORTS_SMP + select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select 64BIT_PHYS_ADDR + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select DMA_COHERENT + select NR_CPUS_DEFAULT_32 + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select ZONE_DMA if 64BIT + select SYNC_R4K + select SYS_HAS_EARLY_PRINTK + help + Support for systems based on Netlogic XLR and XLS processors. + Say Y here if you have a XLR or XLS based board. + endchoice source "arch/mips/alchemy/Kconfig" @@ -752,6 +779,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/netlogic/Kconfig" endmenu @@ -1420,6 +1448,17 @@ config CPU_BMIPS5000 help Broadcom BMIPS5000 processors. +config CPU_XLR + bool "Netlogic XLR SoC" + depends on SYS_HAS_CPU_XLR + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select CPU_SUPPORTS_HUGEPAGES + help + Netlogic Microsystems XLR/XLS processors. endchoice if CPU_LOONGSON2F @@ -1550,6 +1589,9 @@ config SYS_HAS_CPU_BMIPS4380 config SYS_HAS_CPU_BMIPS5000 bool +config SYS_HAS_CPU_XLR + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 53e3514..884819c 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -191,6 +191,18 @@ endif # include $(srctree)/arch/mips/Kbuild.platforms +# +# NETLOGIC SOC Common (common) +# +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic + +# +# NETLOGIC XLR/XLS SoC, Simulator and boards +# +core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ +load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 + cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cedee2b..83bba33 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o +obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 2adead5..b2cad4f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o +obj-$(CONFIG_CPU_XLR) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index d679c77..eb44636 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o +obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig new file mode 100644 index 0000000..a5ca743 --- /dev/null +++ b/arch/mips/netlogic/Kconfig @@ -0,0 +1,5 @@ +config NLM_COMMON + bool + +config NLM_XLR + bool diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile new file mode 100644 index 0000000..9bd3f73 --- /dev/null +++ b/arch/mips/netlogic/xlr/Makefile @@ -0,0 +1,5 @@ +obj-y += setup.o platform.o irq.o setup.o time.o +obj-$(CONFIG_SMP) += smp.o smpboot.o +obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o + +EXTRA_CFLAGS += -Werror -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri May 6 22:07:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:07:11 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:3881 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491099Ab1EFUGA (ORCPT ); Fri, 6 May 2011 22:06:00 +0200 X-TM-IMSS-Message-ID: <2cf508640003a949@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf508640003a949 ; Fri, 6 May 2011 13:05:30 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:06:30 -0700 Date: Sat, 7 May 2011 01:36:40 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 4/8] Platform files for XLR/XLS processor support. Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:06:30.0478 (UTC) FILETIME=[16EDD6E0:01CC0C29] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips * include/asm/netlogic added with files common for all Netlogic processors (common with XLP which will be added later) * include/asm/netlogic/xlr for XLR/XLS chip specific files * netlogic/xlr for XLR/XLS platform files Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/interrupt.h | 45 +++++ arch/mips/include/asm/netlogic/mips-extns.h | 76 ++++++++ arch/mips/include/asm/netlogic/psb-bootinfo.h | 109 ++++++++++++ arch/mips/include/asm/netlogic/xlr/gpio.h | 73 ++++++++ arch/mips/include/asm/netlogic/xlr/iomap.h | 131 ++++++++++++++ arch/mips/include/asm/netlogic/xlr/pic.h | 231 +++++++++++++++++++++++++ arch/mips/include/asm/netlogic/xlr/xlr.h | 54 ++++++ arch/mips/netlogic/xlr/irq.c | 216 +++++++++++++++++++++++ arch/mips/netlogic/xlr/platform.c | 98 +++++++++++ arch/mips/netlogic/xlr/setup.c | 188 ++++++++++++++++++++ arch/mips/netlogic/xlr/smp.c | 225 ++++++++++++++++++++++++ arch/mips/netlogic/xlr/smpboot.S | 94 ++++++++++ arch/mips/netlogic/xlr/time.c | 51 ++++++ arch/mips/netlogic/xlr/xlr_console.c | 46 +++++ 14 files changed, 1637 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h new file mode 100644 index 0000000..a85aadb --- /dev/null +++ b/arch/mips/include/asm/netlogic/interrupt.h @@ -0,0 +1,45 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_INTERRUPT_H +#define _ASM_NLM_INTERRUPT_H + +/* Defines for the IRQ numbers */ + +#define IRQ_IPI_SMP_FUNCTION 3 +#define IRQ_IPI_SMP_RESCHEDULE 4 +#define IRQ_MSGRING 6 +#define IRQ_TIMER 7 + +#endif diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h new file mode 100644 index 0000000..8c53d0b --- /dev/null +++ b/arch/mips/include/asm/netlogic/mips-extns.h @@ -0,0 +1,76 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_MIPS_EXTS_H +#define _ASM_NLM_MIPS_EXTS_H + +/* + * XLR and XLP interrupt request and interrupt mask registers + */ +#define read_c0_eirr() __read_64bit_c0_register($9, 6) +#define read_c0_eimr() __read_64bit_c0_register($9, 7) +#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val) + +/* + * Writing EIMR in 32 bit is a special case, the lower 8 bit of the + * EIMR is shadowed in the status register, so we cannot save and + * restore status register for split read. + */ +#define write_c0_eimr(val) \ +do { \ + if (sizeof(unsigned long) == 4) { \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, $9, 7\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\ + local_irq_restore(__flags); \ + } else \ + __write_64bit_c0_register($9, 7, (val)); \ +} while (0) + +static inline int hard_smp_processor_id(void) +{ + return __read_32bit_c0_register($15, 1) & 0x3ff; +} + +#endif /*_ASM_NLM_MIPS_EXTS_H */ diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h new file mode 100644 index 0000000..6878307 --- /dev/null +++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h @@ -0,0 +1,109 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NETLOGIC_BOOTINFO_H +#define _ASM_NETLOGIC_BOOTINFO_H + +struct psb_info { + uint64_t boot_level; + uint64_t io_base; + uint64_t output_device; + uint64_t uart_print; + uint64_t led_output; + uint64_t init; + uint64_t exit; + uint64_t warm_reset; + uint64_t wakeup; + uint64_t online_cpu_map; + uint64_t master_reentry_sp; + uint64_t master_reentry_gp; + uint64_t master_reentry_fn; + uint64_t slave_reentry_fn; + uint64_t magic_dword; + uint64_t uart_putchar; + uint64_t size; + uint64_t uart_getchar; + uint64_t nmi_handler; + uint64_t psb_version; + uint64_t mac_addr; + uint64_t cpu_frequency; + uint64_t board_version; + uint64_t malloc; + uint64_t free; + uint64_t global_shmem_addr; + uint64_t global_shmem_size; + uint64_t psb_os_cpu_map; + uint64_t userapp_cpu_map; + uint64_t wakeup_os; + uint64_t psb_mem_map; + uint64_t board_major_version; + uint64_t board_minor_version; + uint64_t board_manf_revision; + uint64_t board_serial_number; + uint64_t psb_physaddr_map; + uint64_t xlr_loaderip_config; + uint64_t bldr_envp; + uint64_t avail_mem_map; +}; + +enum { + NETLOGIC_IO_SPACE = 0x10, + PCIX_IO_SPACE, + PCIX_CFG_SPACE, + PCIX_MEMORY_SPACE, + HT_IO_SPACE, + HT_CFG_SPACE, + HT_MEMORY_SPACE, + SRAM_SPACE, + FLASH_CONTROLLER_SPACE +}; + +#define NLM_MAX_ARGS 64 +#define NLM_MAX_ENVS 32 + +/* This is what netlboot passes and linux boot_mem_map is subtly different */ +#define NLM_BOOT_MEM_MAP_MAX 32 +struct nlm_boot_mem_map { + int nr_map; + struct nlm_boot_mem_map_entry { + uint64_t addr; /* start of memory segment */ + uint64_t size; /* size of memory segment */ + uint32_t type; /* type of memory segment */ + } map[NLM_BOOT_MEM_MAP_MAX]; +}; + +/* Pointer to saved boot loader info */ +extern struct psb_info nlm_prom_info; + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h new file mode 100644 index 0000000..51f6ad4 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/gpio.h @@ -0,0 +1,73 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_GPIO_H +#define _ASM_NLM_GPIO_H + +#define NETLOGIC_GPIO_INT_EN_REG 0 +#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 +#define NETLOGIC_GPIO_IO_DIR_REG 2 +#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 +#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 + +#define NETLOGIC_GPIO_SWRESET_REG 8 +#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 +#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 +#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 +#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 +#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 +#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 +#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 +#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 + +#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 +#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 +#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 +#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 + +#define NETLOGIC_GPIO_FUSE_BANK_REG 35 +#define NETLOGIC_GPIO_CPU_RESET_REG 40 +#define NETLOGIC_GPIO_RNG_REG 43 + +#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 +#define NETLOGIC_GPIO_LED_BITMAP 0x1700000 +#define NETLOGIC_GPIO_LED_0_SHIFT 20 +#define NETLOGIC_GPIO_LED_1_SHIFT 24 + +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h new file mode 100644 index 0000000..2e3a4dd --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/iomap.h @@ -0,0 +1,131 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_IOMAP_H +#define _ASM_NLM_IOMAP_H + +#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000) +#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 +#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 +#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 +#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 +#define NETLOGIC_IO_PIC_OFFSET 0x08000 +#define NETLOGIC_IO_UART_0_OFFSET 0x14000 +#define NETLOGIC_IO_UART_1_OFFSET 0x15100 + +#define NETLOGIC_IO_SIZE 0x1000 + +#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 + +#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 +#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 + +#define NETLOGIC_IO_SRAM_OFFSET 0x07000 + +#define NETLOGIC_IO_PCIX_OFFSET 0x09000 +#define NETLOGIC_IO_HT_OFFSET 0x0A000 + +#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 + +#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 +#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 +#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 +#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 + +/* XLS devices */ +#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 +#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 +#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 +#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 + +#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 +#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 +#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 +#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 + +#define NETLOGIC_IO_USB_0_OFFSET 0x24000 +#define NETLOGIC_IO_USB_1_OFFSET 0x25000 + +#define NETLOGIC_IO_COMP_OFFSET 0x1D000 +/* end XLS devices */ + +/* XLR devices */ +#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 +#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 +#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 +#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 +/* end XLR devices */ + +#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 +#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 + +#define NETLOGIC_IO_GPIO_OFFSET 0x18000 +#define NETLOGIC_IO_FLASH_OFFSET 0x19000 +#define NETLOGIC_IO_TB_OFFSET 0x1C000 + +#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) + +/* + * Base Address (Virtual) of the PCI Config address space + * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28) + * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes + * ie 1<<24 = 16M + */ +#define DEFAULT_PCI_CONFIG_BASE 0x18000000 +#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 +#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 + +#ifndef __ASSEMBLY__ +#include +#include + +typedef volatile __u32 nlm_reg_t; +extern unsigned long netlogic_io_base; + +/* FIXME read once in write_reg */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define netlogic_read_reg(base, offset) ((base)[(offset)]) +#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value)) +#else +#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)])) +#define netlogic_write_reg(base, offset, value) \ + ((base)[(offset)] = cpu_to_be32((value))) +#endif + +#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)])) +#define netlogic_write_reg_le32(base, offset, value) \ + ((base)[(offset)] = cpu_to_le32((value))) +#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset))) +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h new file mode 100644 index 0000000..5cceb74 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -0,0 +1,231 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_XLR_PIC_H +#define _ASM_NLM_XLR_PIC_H + +#define PIC_CLKS_PER_SEC 66666666ULL +/* PIC hardware interrupt numbers */ +#define PIC_IRT_WD_INDEX 0 +#define PIC_IRT_TIMER_0_INDEX 1 +#define PIC_IRT_TIMER_1_INDEX 2 +#define PIC_IRT_TIMER_2_INDEX 3 +#define PIC_IRT_TIMER_3_INDEX 4 +#define PIC_IRT_TIMER_4_INDEX 5 +#define PIC_IRT_TIMER_5_INDEX 6 +#define PIC_IRT_TIMER_6_INDEX 7 +#define PIC_IRT_TIMER_7_INDEX 8 +#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX +#define PIC_IRT_UART_0_INDEX 9 +#define PIC_IRT_UART_1_INDEX 10 +#define PIC_IRT_I2C_0_INDEX 11 +#define PIC_IRT_I2C_1_INDEX 12 +#define PIC_IRT_PCMCIA_INDEX 13 +#define PIC_IRT_GPIO_INDEX 14 +#define PIC_IRT_HYPER_INDEX 15 +#define PIC_IRT_PCIX_INDEX 16 +/* XLS */ +#define PIC_IRT_CDE_INDEX 15 +#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16 +/* XLS */ +#define PIC_IRT_GMAC0_INDEX 17 +#define PIC_IRT_GMAC1_INDEX 18 +#define PIC_IRT_GMAC2_INDEX 19 +#define PIC_IRT_GMAC3_INDEX 20 +#define PIC_IRT_XGS0_INDEX 21 +#define PIC_IRT_XGS1_INDEX 22 +#define PIC_IRT_HYPER_FATAL_INDEX 23 +#define PIC_IRT_PCIX_FATAL_INDEX 24 +#define PIC_IRT_BRIDGE_AERR_INDEX 25 +#define PIC_IRT_BRIDGE_BERR_INDEX 26 +#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27 +#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28 +/* XLS */ +#define PIC_IRT_GMAC4_INDEX 21 +#define PIC_IRT_GMAC5_INDEX 22 +#define PIC_IRT_GMAC6_INDEX 23 +#define PIC_IRT_GMAC7_INDEX 24 +#define PIC_IRT_BRIDGE_ERR_INDEX 25 +#define PIC_IRT_PCIE_LINK0_INDEX 26 +#define PIC_IRT_PCIE_LINK1_INDEX 27 +#define PIC_IRT_PCIE_LINK2_INDEX 23 +#define PIC_IRT_PCIE_LINK3_INDEX 24 +#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28 +#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29 +#define PIC_IRT_SRIO_LINK0_INDEX 26 +#define PIC_IRT_SRIO_LINK1_INDEX 27 +#define PIC_IRT_SRIO_LINK2_INDEX 28 +#define PIC_IRT_SRIO_LINK3_INDEX 29 +#define PIC_IRT_PCIE_INT_INDEX 28 +#define PIC_IRT_PCIE_FATAL_INDEX 29 +#define PIC_IRT_GPIO_B_INDEX 30 +#define PIC_IRT_USB_INDEX 31 +/* XLS */ +#define PIC_NUM_IRTS 32 + + +#define PIC_CLOCK_TIMER 7 + +/* PIC Registers */ +#define PIC_CTRL 0x00 +#define PIC_IPI 0x04 +#define PIC_INT_ACK 0x06 + +#define WD_MAX_VAL_0 0x08 +#define WD_MAX_VAL_1 0x09 +#define WD_MASK_0 0x0a +#define WD_MASK_1 0x0b +#define WD_HEARBEAT_0 0x0c +#define WD_HEARBEAT_1 0x0d + +#define PIC_IRT_0_BASE 0x40 +#define PIC_IRT_1_BASE 0x80 +#define PIC_TIMER_MAXVAL_0_BASE 0x100 +#define PIC_TIMER_MAXVAL_1_BASE 0x110 +#define PIC_TIMER_COUNT_0_BASE 0x120 +#define PIC_TIMER_COUNT_1_BASE 0x130 + +#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) +#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) + +#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) +#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i)) +#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i)) +#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i)) + +/* + * Mapping between hardware interrupt numbers and IRQs on CPU + * we use a simple scheme to map PIC interrupts 0-31 to IRQs + * 8-39. This leaves the IRQ 0-7 for cpu interrupts like + * count/compare and FMN + */ +#define PIC_IRQ_BASE 8 +#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) +#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) + +#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE +#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) +#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX) +#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX) +#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX) +#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX) +#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX) +#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX) +#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX) +#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX) +#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ) +#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX) +#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX) +#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX) +#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX) +#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX) +#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX) +#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX) +#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX) +/* XLS */ +#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX) +#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX) +/* end XLS */ +#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX) +#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX) +#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX) +#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX) +#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX) +#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX) +#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX) +#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX) +#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) +#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) +#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) +#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) +/* XLS defines */ +#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) +#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) +#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX) +#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX) +#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX) +#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX) +#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX) +#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX) +#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX) +#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX) +#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX) +#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX) +#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX) +#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX) +#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX) +#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX) +#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX) +#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX) +#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX) +#define PIC_IRT_LAST_IRQ PIC_USB_IRQ +/* end XLS */ + +#ifndef __ASSEMBLY__ +static inline void pic_send_ipi(u32 ipi) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_IPI, ipi); +} + +static inline u32 pic_read_control(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + return netlogic_read_reg(mmio, PIC_CTRL); +} + +static inline void pic_write_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, control); +} + +static inline void pic_update_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, + (control | netlogic_read_reg(mmio, PIC_CTRL))); +} + +#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ + ((irq) <= PIC_TIMER_7_IRQ)) +#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ + ((irq) <= PIC_IRT_LAST_IRQ)) +#endif + +#endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h new file mode 100644 index 0000000..454c236 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -0,0 +1,54 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_XLR_H +#define _ASM_NLM_XLR_H + +/* Platform UART functions */ +struct uart_port; +unsigned int nlm_xlr_uart_in(struct uart_port *, int); +void nlm_xlr_uart_out(struct uart_port *, int, int); + +/* SMP support functions */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); +int nlm_wakeup_secondary_cpus(u32 wakeup_mask); +void nlm_smp_irq_init(void); +void nlm_boot_smp_nmi(void); +void prom_pre_boot_secondary_cpus(void); + +extern struct plat_smp_ops nlm_smp_ops; +extern unsigned long nlm_common_ebase; + +#endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c new file mode 100644 index 0000000..2033f56 --- /dev/null +++ b/arch/mips/netlogic/xlr/irq.c @@ -0,0 +1,216 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +static u64 nlm_irq_mask; +static DEFINE_SPINLOCK(nlm_pic_lock); + +static void xlr_pic_enable(struct irq_data *d) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + unsigned long flags; + nlm_reg_t reg; + int irq = d->irq; + + WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + reg | (1 << 6) | (1 << 30) | (1 << 31)); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static void xlr_pic_mask(struct irq_data *d) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + unsigned long flags; + nlm_reg_t reg; + int irq = d->irq; + + WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + reg | (1 << 6) | (1 << 30) | (0 << 31)); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static void xlr_pic_ack(struct irq_data *d) +{ + unsigned long flags; + nlm_reg_t *mmio; + int irq = d->irq; + + WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +/* + * This chip definition handles interrupts routed thru the XLR + * hardware PIC, currently IRQs 8-39 are mapped to hardware intr + * 0-31 wired the XLR PIC + */ +static struct irq_chip xlr_pic = { + .name = "XLR-PIC", + .irq_enable = xlr_pic_enable, + .irq_mask = xlr_pic_mask, + .irq_ack = xlr_pic_ack, +}; + +static void rsvd_irq_handler(struct irq_data *d) +{ + WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq); +} + +/* + * Chip definition for CPU originated interrupts(timer, msg) and + * IPIs + */ +struct irq_chip nlm_cpu_intr = { + .name = "XLR-CPU-INTR", + .irq_enable = rsvd_irq_handler, + .irq_mask = rsvd_irq_handler, + .irq_ack = rsvd_irq_handler, +}; + +void __init init_xlr_irqs(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + uint32_t thread_mask = 1; + int level, i; + + pr_info("Interrupt thread mask [%x]\n", thread_mask); + for (i = 0; i < PIC_NUM_IRTS; i++) { + level = PIC_IRQ_IS_EDGE_TRIGGERED(i); + + /* Bind all PIC irqs to boot cpu */ + netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask); + + /* + * Use local scheduling and high polarity for all IRTs + * Invalidate all IRTs, by default + */ + netlogic_write_reg(mmio, PIC_IRT_1_BASE + i, + (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i)); + } + + /* Make all IRQs as level triggered by default */ + for (i = 0; i < NR_IRQS; i++) { + if (PIC_IRQ_IS_IRT(i)) + irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq); + else + irq_set_chip_and_handler(i, &nlm_cpu_intr, + handle_level_irq); + } +#ifdef CONFIG_SMP + irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr, + nlm_smp_function_ipi_handler); + irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr, + nlm_smp_resched_ipi_handler); + nlm_irq_mask |= + ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); +#endif + /* unmask all PIC related interrupts. If no handler is installed by the + * drivers, it'll just ack the interrupt and return + */ + for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) + nlm_irq_mask |= (1ULL << i); + + nlm_irq_mask |= (1ULL << IRQ_TIMER); +} + +void __init arch_init_irq(void) +{ + /* Initialize the irq descriptors */ + init_xlr_irqs(); + write_c0_eimr(nlm_irq_mask); +} + +void __cpuinit nlm_smp_irq_init(void) +{ + /* set interrupt mask for non-zero cpus */ + write_c0_eimr(nlm_irq_mask); +} + +asmlinkage void plat_irq_dispatch(void) +{ + uint64_t eirr; + int i; + + eirr = read_c0_eirr() & read_c0_eimr(); + if (!eirr) + return; + + /* no need of EIRR here, writing compare clears interrupt */ + if (eirr & (1 << IRQ_TIMER)) { + do_IRQ(IRQ_TIMER); + return; + } + + /* TODO use dcltz: optimize below code */ + for (i = 63; i != -1; i--) { + if (eirr & (1ULL << i)) + break; + } + if (i == -1) { + pr_err("no interrupt !!\n"); + return; + } + + /* Ack eirr */ + write_c0_eirr(1ULL << i); + + do_IRQ(i); +} diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c new file mode 100644 index 0000000..609ec25 --- /dev/null +++ b/arch/mips/netlogic/xlr/platform.c @@ -0,0 +1,98 @@ +/* + * Copyright 2011, Netlogic Microsystems. + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) +{ + nlm_reg_t *mmio; + unsigned int value; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + value = netlogic_read_reg(mmio, 0); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + return value; +} + +void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) +{ + nlm_reg_t *mmio; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + netlogic_write_reg(mmio, 0, value); +} + +#define PORT(_irq) \ + { \ + .irq = _irq, \ + .regshift = 2, \ + .iotype = UPIO_MEM32, \ + .flags = (UPF_SKIP_TEST | \ + UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\ + .uartclk = PIC_CLKS_PER_SEC, \ + .type = PORT_16550A, \ + .serial_in = nlm_xlr_uart_in, \ + .serial_out = nlm_xlr_uart_out, \ + } + +static struct plat_serial8250_port xlr_uart_data[] = { + PORT(PIC_UART_0_IRQ), + PORT(PIC_UART_1_IRQ), + {}, +}; + +static struct platform_device uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = xlr_uart_data, + }, +}; + +static int __init nlm_uart_init(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + xlr_uart_data[0].membase = (void __iomem *)mmio; + xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio); + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); + xlr_uart_data[1].membase = (void __iomem *)mmio; + xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio); + + return platform_device_register(&uart_device); +} + +arch_initcall(nlm_uart_init); diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c new file mode 100644 index 0000000..4828025 --- /dev/null +++ b/arch/mips/netlogic/xlr/setup.c @@ -0,0 +1,188 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); +unsigned long nlm_common_ebase = 0x0; +struct psb_info nlm_prom_info; + +static void nlm_early_serial_setup(void) +{ + struct uart_port s; + nlm_reg_t *uart_base; + + uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + memset(&s, 0, sizeof(s)); + s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + s.iotype = UPIO_MEM32; + s.regshift = 2; + s.irq = PIC_UART_0_IRQ; + s.uartclk = PIC_CLKS_PER_SEC; + s.serial_in = nlm_xlr_uart_in; + s.serial_out = nlm_xlr_uart_out; + s.mapbase = (unsigned long)uart_base; + s.membase = (unsigned char __iomem *)uart_base; + early_serial_setup(&s); +} + +static void nlm_linux_exit(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); + /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ + netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); + for ( ; ; ) + cpu_wait(); +} + +void __init plat_mem_setup(void) +{ + panic_timeout = 5; + _machine_restart = (void (*)(char *))nlm_linux_exit; + _machine_halt = nlm_linux_exit; + pm_power_off = nlm_linux_exit; +} + +const char *get_system_type(void) +{ + return "Netlogic XLR/XLS Series"; +} + +void __init prom_free_prom_memory(void) +{ + /* Nothing yet */ +} + +static void build_arcs_cmdline(int *argv) +{ + int i, remain, len; + char *arg; + + remain = sizeof(arcs_cmdline) - 1; + arcs_cmdline[0] = '\0'; + for (i = 0; argv[i] != 0; i++) { + arg = (char *)(long)argv[i]; + len = strlen(arg); + if (len + 1 > remain) + break; + strcat(arcs_cmdline, arg); + strcat(arcs_cmdline, " "); + remain -= len + 1; + } + + /* Add the default options here */ + if ((strstr(arcs_cmdline, "console=")) == NULL) { + arg = "console=ttyS0,38400 "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#ifdef CONFIG_BLK_DEV_INITRD + if ((strstr(arcs_cmdline, "rdinit=")) == NULL) { + arg = "rdinit=/sbin/init "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#endif + return; +fail: + panic("Cannot add %s, command line too big!", arg); +} + +static void prom_add_memory(void) +{ + struct nlm_boot_mem_map *bootm; + u64 start, size; + u64 pref_backup = 512; /* avoid pref walking beyond end */ + int i; + + bootm = (void *)(long)nlm_prom_info.psb_mem_map; + for (i = 0; i < bootm->nr_map; i++) { + if (bootm->map[i].type != BOOT_MEM_RAM) + continue; + start = bootm->map[i].addr; + size = bootm->map[i].size; + + /* Work around for using bootloader mem */ + if (i == 0 && start == 0 && size == 0x0c000000) + size = 0x0ff00000; + + add_memory_region(start, size - pref_backup, BOOT_MEM_RAM); + } +} + +void __init prom_init(void) +{ + int *argv, *envp; /* passed as 32 bit ptrs */ + struct psb_info *prom_infop; + + /* truncate to 32 bit and sign extend all args */ + argv = (int *)(long)(int)fw_arg1; + envp = (int *)(long)(int)fw_arg2; + prom_infop = (struct psb_info *)(long)(int)fw_arg3; + + nlm_prom_info = *prom_infop; + + nlm_early_serial_setup(); + build_arcs_cmdline(argv); + nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); + prom_add_memory(); + +#ifdef CONFIG_SMP + nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map); + register_smp_ops(&nlm_smp_ops); +#endif +} diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c new file mode 100644 index 0000000..b495a7f --- /dev/null +++ b/arch/mips/netlogic/xlr/smp.c @@ -0,0 +1,225 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +void core_send_ipi(int logical_cpu, unsigned int action) +{ + int cpu = cpu_logical_map(logical_cpu); + u32 tid = cpu & 0x3; + u32 pid = (cpu >> 2) & 0x07; + u32 ipi = (tid << 16) | (pid << 20); + + if (action & SMP_CALL_FUNCTION) + ipi |= IRQ_IPI_SMP_FUNCTION; + else if (action & SMP_RESCHEDULE_YOURSELF) + ipi |= IRQ_IPI_SMP_RESCHEDULE; + else + return; + + pic_send_ipi(ipi); +} + +void nlm_send_ipi_single(int cpu, unsigned int action) +{ + core_send_ipi(cpu, action); +} + +void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + int cpu; + + for_each_cpu(cpu, mask) { + core_send_ipi(cpu, action); + } +} + +/* IRQ_IPI_SMP_FUNCTION Handler */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + smp_call_function_interrupt(); +} + +/* IRQ_IPI_SMP_RESCHEDULE handler */ +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + set_need_resched(); +} + +void nlm_common_ipi_handler(int irq, struct pt_regs *regs) +{ + if (irq == IRQ_IPI_SMP_FUNCTION) { + smp_call_function_interrupt(); + } else { + /* Announce that we are for reschduling */ + set_need_resched(); + } +} + +/* + * Called before going into mips code, early cpu init + */ +void nlm_early_init_secondary(void) +{ + write_c0_ebase((uint32_t)nlm_common_ebase); + /* TLB partition here later */ +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit nlm_init_secondary(void) +{ + nlm_smp_irq_init(); +} + +void nlm_smp_finish(void) +{ +#ifdef notyet + nlm_common_msgring_cpu_init(); +#endif +} + +void nlm_cpus_done(void) +{ +} + +/* + * Boot all other cpus in the system, initialize them, and bring them into + * the boot function + */ +int nlm_cpu_unblock[NR_CPUS]; +int nlm_cpu_ready[NR_CPUS]; +unsigned long nlm_next_gp; +unsigned long nlm_next_sp; +cpumask_t phys_cpu_present_map; + +void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long)task_thread_info(idle); + unsigned long sp = (unsigned long)__KSTK_TOS(idle); + int cpu = cpu_logical_map(logical_cpu); + + nlm_next_sp = sp; + nlm_next_gp = gp; + + /* barrier */ + __sync(); + nlm_cpu_unblock[cpu] = 1; +} + +void __init nlm_smp_setup(void) +{ + unsigned int boot_cpu; + int num_cpus, i; + + boot_cpu = hard_smp_processor_id(); + cpus_clear(phys_cpu_present_map); + + cpu_set(boot_cpu, phys_cpu_present_map); + __cpu_number_map[boot_cpu] = 0; + __cpu_logical_map[0] = boot_cpu; + cpu_set(0, cpu_possible_map); + + num_cpus = 1; + for (i = 0; i < NR_CPUS; i++) { + if (nlm_cpu_ready[i]) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = num_cpus; + __cpu_logical_map[num_cpus] = i; + cpu_set(num_cpus, cpu_possible_map); + ++num_cpus; + } + } + + pr_info("Phys CPU present map: %lx, possible map %lx\n", + (unsigned long)phys_cpu_present_map.bits[0], + (unsigned long)cpu_possible_map.bits[0]); + + pr_info("Detected %i Slave CPU(s)\n", num_cpus); +} + +void nlm_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops nlm_smp_ops = { + .send_ipi_single = nlm_send_ipi_single, + .send_ipi_mask = nlm_send_ipi_mask, + .init_secondary = nlm_init_secondary, + .smp_finish = nlm_smp_finish, + .cpus_done = nlm_cpus_done, + .boot_secondary = nlm_boot_secondary, + .smp_setup = nlm_smp_setup, + .prepare_cpus = nlm_prepare_cpus, +}; + +unsigned long secondary_entry_point; + +int nlm_wakeup_secondary_cpus(u32 wakeup_mask) +{ + unsigned int tid, pid, ipi, i, boot_cpu; + void *reset_vec; + + secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus; + reset_vec = (void *)CKSEG1ADDR(0x1fc00000); + memcpy(reset_vec, nlm_boot_smp_nmi, 0x80); + boot_cpu = hard_smp_processor_id(); + + for (i = 0; i < NR_CPUS; i++) { + if (i == boot_cpu) + continue; + if (wakeup_mask & (1u << i)) { + tid = i & 0x3; + pid = (i >> 2) & 0x7; + ipi = (tid << 16) | (pid << 20) | (1 << 8); + pic_send_ipi(ipi); + } + } + + return 0; +} diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S new file mode 100644 index 0000000..b8e0744 --- /dev/null +++ b/arch/mips/netlogic/xlr/smpboot.S @@ -0,0 +1,94 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/* Don't jump to linux function from Bootloader stack. Change it + * here. Kernel might allocate bootloader memory before all the CPUs are + * brought up (eg: Inode cache region) and we better don't overwrite this + * memory + */ +NESTED(prom_pre_boot_secondary_cpus, 16, sp) + .set mips64 + mfc0 t0, $15, 1 # read ebase + andi t0, 0x1f # t0 has the processor_id() + sll t0, 2 # offset in cpu array + + PTR_LA t1, nlm_cpu_ready # mark CPU ready + PTR_ADDU t1, t0 + li t2, 1 + sw t2, 0(t1) + + PTR_LA t1, nlm_cpu_unblock + PTR_ADDU t1, t0 +1: lw t2, 0(t1) # wait till unblocked + beqz t2, 1b + nop + + PTR_LA t1, nlm_next_sp + PTR_L sp, 0(t1) + PTR_LA t1, nlm_next_gp + PTR_L gp, 0(t1) + + PTR_LA t0, nlm_early_init_secondary + jalr t0 + nop + + PTR_LA t0, smp_bootstrap + jr t0 + nop +END(prom_pre_boot_secondary_cpus) + +NESTED(nlm_boot_smp_nmi, 0, sp) + .set push + .set noat + .set mips64 + .set noreorder + + /* Clear the NMI and BEV bits */ + MFC0 k0, CP0_STATUS + li k1, 0xffb7ffff + and k0, k0, k1 + MTC0 k0, CP0_STATUS + + PTR_LA k1, secondary_entry_point + PTR_L k0, 0(k1) + jr k0 + nop + .set pop +END(nlm_boot_smp_nmi) diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c new file mode 100644 index 0000000..0d81b26 --- /dev/null +++ b/arch/mips/netlogic/xlr/time.c @@ -0,0 +1,51 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return IRQ_TIMER; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = nlm_prom_info.cpu_frequency; + pr_info("MIPS counter frequency [%ld]\n", + (unsigned long)mips_hpt_frequency); +} diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/xlr_console.c new file mode 100644 index 0000000..759df06 --- /dev/null +++ b/arch/mips/netlogic/xlr/xlr_console.c @@ -0,0 +1,46 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +void prom_putchar(char c) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + while (netlogic_read_reg(mmio, 0x5) == 0) + ; + netlogic_write_reg(mmio, 0x0, c); +} -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri May 6 22:07:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:07:37 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:4836 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491107Ab1EFUHA (ORCPT ); Fri, 6 May 2011 22:07:00 +0200 X-TM-IMSS-Message-ID: <2cf5f8610003a954@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf5f8610003a954 ; Fri, 6 May 2011 13:06:32 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:07:41 -0700 Date: Sat, 7 May 2011 01:37:52 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 8/8] USB support for XLS platforms. Message-ID: <70d6e74aef472dfde06b0aeb4a63ebaf7666b155.1304712046.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:07:41.0682 (UTC) FILETIME=[415EB520:01CC0C29] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips update ehci-hcd.c and ohci-hcd.c to add XLS hcds add ehci/ohci devices to XLR/XLS platform driver Kconfig update Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 2 + arch/mips/netlogic/xlr/platform.c | 89 ++++++++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-xls.c | 161 +++++++++++++++++++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-xls.c | 151 ++++++++++++++++++++++++++++++++++ 6 files changed, 413 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-xls.c create mode 100644 drivers/usb/host/ohci-xls.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5016caa..7fa4f01 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -759,6 +759,8 @@ config NLM_XLR_BOARD select ZONE_DMA if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK + select USB_ARCH_HAS_OHCI if USB_SUPPORT + select USB_ARCH_HAS_EHCI if USB_SUPPORT help Support for systems based on Netlogic XLR and XLS processors. Say Y here if you have a XLR or XLS based board. diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c index 609ec25..bdcab10 100644 --- a/arch/mips/netlogic/xlr/platform.c +++ b/arch/mips/netlogic/xlr/platform.c @@ -96,3 +96,92 @@ static int __init nlm_uart_init(void) } arch_initcall(nlm_uart_init); + +#ifdef CONFIG_USB +/* Platform USB devices, only on XLS chips */ +static u64 xls_usb_dmamask = ~(u32)0; +#define USB_PLATFORM_DEV(n, i, irq) \ + { \ + .name = n, \ + .id = i, \ + .num_resources = 2, \ + .dev = { \ + .dma_mask = &xls_usb_dmamask, \ + .coherent_dma_mask = 0xffffffff, \ + }, \ + .resource = (struct resource[]) { \ + { \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }, \ + } + +static struct platform_device xls_usb_ehci_device = + USB_PLATFORM_DEV("ehci-xls", 0, PIC_USB_IRQ); +static struct platform_device xls_usb_ohci_device_0 = + USB_PLATFORM_DEV("ohci-xls-0", 1, PIC_USB_IRQ); +static struct platform_device xls_usb_ohci_device_1 = + USB_PLATFORM_DEV("ohci-xls-1", 2, PIC_USB_IRQ); + +static struct platform_device *xls_platform_devices[] __initdata = { + &xls_usb_ehci_device, + &xls_usb_ohci_device_0, + &xls_usb_ohci_device_1, +}; + +int xls_platform_usb_init(void) +{ + nlm_reg_t *usb_mmio, *gpio_mmio; + unsigned long memres; + uint32_t val; + + if (!nlm_chip_is_xls()) + return 0; + + gpio_mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); + usb_mmio = netlogic_io_mmio(NETLOGIC_IO_USB_1_OFFSET); + + /* Clear Rogue Phy INTs */ + netlogic_write_reg(usb_mmio, 49, 0x10000000); + /* Enable all interrupts */ + netlogic_write_reg(usb_mmio, 50, 0x1f000000); + + /* Enable ports */ + netlogic_write_reg(usb_mmio, 1, 0x07000500); + + val = netlogic_read_reg(gpio_mmio, 21); + if (((val >> 22) & 0x01) == 0) { + pr_info("Detected USB Device mode - Not supported!\n"); + netlogic_write_reg(usb_mmio, 0, 0x01000000); + return 0; + } + + pr_info("Detected USB Host mode - Adding XLS USB devices.\n"); + /* Clear reset, host mode */ + netlogic_write_reg(usb_mmio, 0, 0x02000000); + + /* Memory resource for various XLS usb ports */ + usb_mmio = netlogic_io_mmio(NETLOGIC_IO_USB_0_OFFSET); + memres = CPHYSADDR((unsigned long)usb_mmio); + xls_usb_ehci_device.resource[0].start = memres; + xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1; + + memres += 0x400; + xls_usb_ohci_device_0.resource[0].start = memres; + xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1; + + memres += 0x400; + xls_usb_ohci_device_1.resource[0].start = memres; + xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1; + + return platform_add_devices(xls_platform_devices, + ARRAY_SIZE(xls_platform_devices)); +} + +arch_initcall(xls_platform_usb_init); +#endif diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 78561d1..fde78c9 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1265,6 +1265,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER tegra_ehci_driver #endif +#ifdef CONFIG_NLM_XLR +#include "ehci-xls.c" +#define PLATFORM_DRIVER ehci_xls_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-xls.c b/drivers/usb/host/ehci-xls.c new file mode 100644 index 0000000..fe74bd6 --- /dev/null +++ b/drivers/usb/host/ehci-xls.c @@ -0,0 +1,161 @@ +/* + * EHCI HCD for Netlogic XLS processors. + * + * (C) Copyright 2011 Netlogic Microsystems Inc. + * + * Based on various ehci-*.c drivers + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include + +static int ehci_xls_setup(struct usb_hcd *hcd) +{ + int retval; + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + + retval = ehci_halt(ehci); + if (retval) + return retval; + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + ehci_reset(ehci); + + return retval; +} + +int ehci_xls_probe_internal(const struct hc_driver *driver, + struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int retval, irq; + + /* Get our IRQ from an earlier registered Platform Resource */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + + /* Get our Memory Handle */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Error: MMIO Handle %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) { + retval = -ENOMEM; + goto err1; + } + + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + retval = -EBUSY; + goto err2; + } + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + + if (hcd->regs == NULL) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + retval = -EFAULT; + goto err3; + } + + retval = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (retval != 0) + goto err4; + return retval; + +err4: + iounmap(hcd->regs); +err3: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err2: + usb_put_hcd(hcd); +err1: + dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), + retval); + return retval; +} + +static struct hc_driver ehci_xls_hc_driver = { + .description = hcd_name, + .product_desc = "XLS EHCI Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_USB2 | HCD_MEMORY, + .reset = ehci_xls_setup, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_xls_probe(struct platform_device *pdev) +{ + if (usb_disabled()) + return -ENODEV; + + return ehci_xls_probe_internal(&ehci_xls_hc_driver, pdev); +} + +static int ehci_xls_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + return 0; +} + +MODULE_ALIAS("ehci-xls"); + +static struct platform_driver ehci_xls_driver = { + .probe = ehci_xls_probe, + .remove = ehci_xls_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ehci-xls", + }, +}; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index d557235..7b8c12b 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1105,6 +1105,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver #endif +#ifdef CONFIG_NLM_XLR +#include "ohci-xls.c" +#define PLATFORM_DRIVER ohci_xls_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ diff --git a/drivers/usb/host/ohci-xls.c b/drivers/usb/host/ohci-xls.c new file mode 100644 index 0000000..a3a9c6f --- /dev/null +++ b/drivers/usb/host/ohci-xls.c @@ -0,0 +1,151 @@ +/* + * OHCI HCD for Netlogic XLS processors. + * + * (C) Copyright 2011 Netlogic Microsystems Inc. + * + * Based on ohci-au1xxx.c, and other Linux OHCI drivers. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include +#include + +static int ohci_xls_probe_internal(const struct hc_driver *driver, + struct platform_device *dev) +{ + struct resource *res; + struct usb_hcd *hcd; + int retval, irq; + + /* Get our IRQ from an earlier registered Platform Resource */ + irq = platform_get_irq(dev, 0); + if (irq < 0) { + dev_err(&dev->dev, "Found HC with no IRQ\n"); + return -ENODEV; + } + + /* Get our Memory Handle */ + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&dev->dev, "MMIO Handle incorrect!\n"); + return -ENODEV; + } + + hcd = usb_create_hcd(driver, &dev->dev, "XLS"); + if (!hcd) { + retval = -ENOMEM; + goto err1; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(&dev->dev, "Controller already in use\n"); + retval = -EBUSY; + goto err2; + } + + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (hcd->regs == NULL) { + dev_dbg(&dev->dev, "error mapping memory\n"); + retval = -EFAULT; + goto err3; + } + + retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (retval != 0) + goto err4; + return retval; + +err4: + iounmap(hcd->regs); +err3: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err2: + usb_put_hcd(hcd); +err1: + dev_err(&dev->dev, "init fail, %d\n", retval); + return retval; +} + +static int ohci_xls_reset(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + + ohci_hcd_init(ohci); + return ohci_init(ohci); +} + +static int __devinit ohci_xls_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci; + int ret; + + ohci = hcd_to_ohci(hcd); + ret = ohci_run(ohci); + if (ret < 0) { + err("can't start %s", hcd->self.bus_name); + ohci_stop(hcd); + return ret; + } + return 0; +} + +static struct hc_driver ohci_xls_hc_driver = { + .description = hcd_name, + .product_desc = "XLS OHCI Host Controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + .irq = ohci_irq, + .flags = HCD_MEMORY | HCD_USB11, + .reset = ohci_xls_reset, + .start = ohci_xls_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + .get_frame_number = ohci_get_frame, + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ohci_bus_suspend, + .bus_resume = ohci_bus_resume, +#endif + .start_port_reset = ohci_start_port_reset, +}; + +static int ohci_xls_probe(struct platform_device *dev) +{ + int ret; + + pr_debug("In ohci_xls_probe"); + if (usb_disabled()) + return -ENODEV; + ret = ohci_xls_probe_internal(&ohci_xls_hc_driver, dev); + return ret; +} + +static int ohci_xls_remove(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + return 0; +} + +static struct platform_driver ohci_xls_driver = { + .probe = ohci_xls_probe, + .remove = ohci_xls_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ohci-xls-0", + .owner = THIS_MODULE, + }, +}; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri May 6 22:07:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:08:02 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:4837 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491113Ab1EFUHB (ORCPT ); Fri, 6 May 2011 22:07:01 +0200 X-TM-IMSS-Message-ID: <2cf5f7f40003a953@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf5f7f40003a953 ; Fri, 6 May 2011 13:06:31 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:07:21 -0700 Date: Sat, 7 May 2011 01:37:31 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 7/8] PCI support for XLR/XLS Message-ID: <308b8963d3ed2beb54b96634e3b72d84c4b45cfa.1304712046.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:07:21.0369 (UTC) FILETIME=[35433090:01CC0C29] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Adds pci/pci-xlr.c to support for XLR PCI/PCI-X interface and XLS PCIe interface. Update irq.c to ack PCI interrupts, use irq handler data to do the PCI/PCIe bus ack. Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlr/xlr.h | 21 +++ arch/mips/netlogic/xlr/irq.c | 86 ++++++++++++- arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlr.c | 214 ++++++++++++++++++++++++++++++ 4 files changed, 321 insertions(+), 1 deletions(-) create mode 100644 arch/mips/pci/pci-xlr.c diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h index 454c236..3e63726 100644 --- a/arch/mips/include/asm/netlogic/xlr/xlr.h +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -41,6 +41,7 @@ unsigned int nlm_xlr_uart_in(struct uart_port *, int); void nlm_xlr_uart_out(struct uart_port *, int, int); /* SMP support functions */ +struct irq_desc; void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); int nlm_wakeup_secondary_cpus(u32 wakeup_mask); @@ -51,4 +52,24 @@ void prom_pre_boot_secondary_cpus(void); extern struct plat_smp_ops nlm_smp_ops; extern unsigned long nlm_common_ebase; +/* XLS B silicon "Rook" */ +static inline unsigned int nlm_chip_is_xls_b(void) +{ + uint32_t prid = read_c0_prid(); + + return ((prid & 0xf000) == 0x4000); +} + +/* + * XLR chip types + */ + /* The XLS product line has chip versions 0x[48c]? */ +static inline unsigned int nlm_chip_is_xls(void) +{ + uint32_t prid = read_c0_prid(); + + return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 || + (prid & 0xf000) == 0xc000); +} + #endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c index 2033f56..1446d58 100644 --- a/arch/mips/netlogic/xlr/irq.c +++ b/arch/mips/netlogic/xlr/irq.c @@ -83,14 +83,71 @@ static void xlr_pic_mask(struct irq_data *d) spin_unlock_irqrestore(&nlm_pic_lock, flags); } +#ifdef CONFIG_PCI +/* Extra ACK needed for XLR on chip PCI controller */ +static void xlr_pci_ack(struct irq_data *d) +{ + nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET); + + netlogic_read_reg(pci_mmio, (0x140 >> 2)); +} + +/* Extra ACK needed for XLS on chip PCIe controller */ +static void xls_pcie_ack(struct irq_data *d) +{ + nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET); + + switch (d->irq) { + case PIC_PCIE_LINK0_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK1_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK2_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK3_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff); + break; + } +} + +/* For XLS B silicon, the 3,4 PCI interrupts are different */ +static void xls_pcie_ack_b(struct irq_data *d) +{ + nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET); + + switch (d->irq) { + case PIC_PCIE_LINK0_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK1_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff); + break; + case PIC_PCIE_XLSB0_LINK2_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff); + break; + case PIC_PCIE_XLSB0_LINK3_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff); + break; + } +} +#endif + static void xlr_pic_ack(struct irq_data *d) { unsigned long flags; nlm_reg_t *mmio; int irq = d->irq; + void *hd = irq_data_get_irq_handler_data(d); WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + if (hd) { + void (*extra_ack)(void *) = hd; + extra_ack(d); + } mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); spin_lock_irqsave(&nlm_pic_lock, flags); netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); @@ -162,6 +219,33 @@ void __init init_xlr_irqs(void) nlm_irq_mask |= ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); #endif + +#ifdef CONFIG_PCI + /* + * For PCI interrupts, we need to ack the PIC controller too, overload + * irq handler data to do this + */ + if (nlm_chip_is_xls()) { + if (nlm_chip_is_xls_b()) { + irq_set_handler_data(PIC_PCIE_LINK0_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_LINK1_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, + xls_pcie_ack_b); + } else { + irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack); + } + } else { + /* XLR PCI controller ACK */ + irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack); + } +#endif /* unmask all PIC related interrupts. If no handler is installed by the * drivers, it'll just ack the interrupt and return */ @@ -199,7 +283,7 @@ asmlinkage void plat_irq_dispatch(void) return; } - /* TODO use dcltz: optimize below code */ + /* use dcltz: optimize below code */ for (i = 63; i != -1; i--) { if (eirr & (1ULL << i)) break; diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c9209ca..f0d5329 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o +obj-$(CONFIG_NLM_XLR) += pci-xlr.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c new file mode 100644 index 0000000..38fece1 --- /dev/null +++ b/arch/mips/pci/pci-xlr.c @@ -0,0 +1,214 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +static void *pci_config_base; + +#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) + +/* PCI ops */ +static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, + int where) +{ + u32 data; + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + data = *cfgaddr; + return cpu_to_le32(data); +} + +static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, + int where, u32 data) +{ + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + *cfgaddr = cpu_to_le32(data); +} + +static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + + +static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + pci_cfg_write_32bit(bus, devfn, where, data); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops nlm_pci_ops = { + .read = nlm_pcibios_read, + .write = nlm_pcibios_write +}; + +static struct resource nlm_pci_mem_resource = { + .name = "XLR PCI MEM", + .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ + .end = 0xdfffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource nlm_pci_io_resource = { + .name = "XLR IO MEM", + .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ + .end = 0x100fffffUL, + .flags = IORESOURCE_IO, +}; + +struct pci_controller nlm_pci_controller = { + .index = 0, + .pci_ops = &nlm_pci_ops, + .mem_resource = &nlm_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &nlm_pci_io_resource, + .io_offset = 0x00000000UL, +}; + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if (!nlm_chip_is_xls()) + return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ + + /* + * For XLS PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + if (dev->bus->self == NULL) + return 0; + + switch (dev->bus->self->devfn) { + case 0x0: + return PIC_PCIE_LINK0_IRQ; + case 0x8: + return PIC_PCIE_LINK1_IRQ; + case 0x10: + if (nlm_chip_is_xls_b()) + return PIC_PCIE_XLSB0_LINK2_IRQ; + else + return PIC_PCIE_LINK2_IRQ; + case 0x18: + if (nlm_chip_is_xls_b()) + return PIC_PCIE_XLSB0_LINK3_IRQ; + else + return PIC_PCIE_LINK3_IRQ; + } + WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); + return 0; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static int __init pcibios_init(void) +{ + /* PSB assigns PCI resources */ + pci_probe_only = 1; + pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); + + /* Extend IO port for memory mapped io */ + ioport_resource.start = 0; + ioport_resource.end = ~0; + + set_io_port_base(CKSEG1); + nlm_pci_controller.io_map_base = CKSEG1; + + pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); + register_pci_controller(&nlm_pci_controller); + + return 0; +} + +arch_initcall(pcibios_init); + +struct pci_fixup pcibios_fixups[] = { + {0} +}; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri May 6 22:08:21 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 May 2011 22:08:29 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:4838 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491114Ab1EFUHB (ORCPT ); Fri, 6 May 2011 22:07:01 +0200 X-TM-IMSS-Message-ID: <2cf5f7480003a952@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2cf5f7480003a952 ; Fri, 6 May 2011 13:06:31 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 May 2011 13:07:03 -0700 Date: Sat, 7 May 2011 01:37:14 +0530 From: Jayachandran C To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 6/8] Add default configuration for XLR/XLS processors Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 06 May 2011 20:07:03.0916 (UTC) FILETIME=[2ADC12C0:01CC0C29] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Enable XLR CPU support, SMP, initramfs based root filesystem etc. Signed-off-by: Jayachandran C --- arch/mips/configs/nlm_xlr_defconfig | 1705 +++++++++++++++++++++++++++++++++++ 1 files changed, 1705 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig new file mode 100644 index 0000000..a5a22f0 --- /dev/null +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -0,0 +1,1705 @@ +# +# Automatically generated make config: don't edit +# Linux/mips 2.6.39-rc1 Kernel Configuration +# Fri Apr 1 07:44:07 2011 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_NLM_XLR_BOARD=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_NLM_COMMON=y +CONFIG_NLM_XLR=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_FIND_BIT_LE=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYNC_R4K=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_XLR=y +CONFIG_SYS_HAS_CPU_XLR=y +CONFIG_WEAK_ORDERING=y +CONFIG_WEAK_REORDERING_BEYOND_LLSC=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_SMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_32=y +CONFIG_NR_CPUS=32 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_KEXEC=y +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +# CONFIG_EMBEDDED is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_VERBOSE is not set +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=m +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_IP_SET is not set +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +# CONFIG_IP_VS_PE_SIP is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +CONFIG_PHONET=m +CONFIG_IEEE802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_PARTITIONS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=y +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_SENSORS_LIS3LV02D is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FC_TGT_ATTRS=y +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +# CONFIG_ISCSI_BOOT_SYSFS is not set +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_N_HDLC=m +# CONFIG_N_GSM is not set +# CONFIG_DEVKMEM is not set +CONFIG_STALDRV=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XZ is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_MINIX_FS_NATIVE_ENDIAN=y +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_PSTORE is not set +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EXOFS_FS=m +# CONFIG_EXOFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_NEW_IDMAPPER is not set +CONFIG_NFSD=m +CONFIG_NFSD_DEPRECATED=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_ACL is not set +CONFIG_CIFS_EXPERIMENTAL=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +# CONFIG_NCPFS_SMALLDOS is not set +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +# CONFIG_AFS_DEBUG is not set +# CONFIG_AFS_FSCACHE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +# CONFIG_ACORN_PARTITION_CUMANA is not set +# CONFIG_ACORN_PARTITION_EESOX is not set +CONFIG_ACORN_PARTITION_ICS=y +# CONFIG_ACORN_PARTITION_ADFS is not set +# CONFIG_ACORN_PARTITION_POWERTEC is not set +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_DETECTOR_RUNNABLE=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +# CONFIG_KGDB_LOW_LEVEL_TRAP is not set +# CONFIG_KGDB_KDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_TOMOYO=y +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_IMA is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=m +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_VIRTUALIZATION is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From sboyd@codeaurora.org Sat May 7 07:57:21 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 07:57:28 +0200 (CEST) Received: from wolverine02.qualcomm.com ([199.106.114.251]:55866 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491079Ab1EGF5U (ORCPT ); Sat, 7 May 2011 07:57:20 +0200 X-IronPort-AV: E=McAfee;i="5400,1158,6338"; a="89861682" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/ADH-AES256-SHA; 06 May 2011 22:57:13 -0700 Received: from sboyd-linux.qualcomm.com (pdmz-snip-v218.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 26C6810004A2; Fri, 6 May 2011 22:56:55 -0700 (PDT) From: Stephen Boyd To: Andrew Morton Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m32r@ml.linux-m32r.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Chris Metcalf , user-mode-linux-devel@lists.sourceforge.net, x86@kernel.org Subject: [PATCH] lib: Consolidate DEBUG_STACK_USAGE option Date: Fri, 6 May 2011 22:57:11 -0700 Message-Id: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 1.7.5.185.g0b9dee Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sboyd@codeaurora.org Precedence: bulk X-list: linux-mips Most arches define CONFIG_DEBUG_STACK_USAGE exactly the same way. Move it to lib/Kconfig.debug so each arch doesn't have to define it. This obviously makes the option generic, but that's fine because the config is already used in generic code. It's not obvious to me that sysrq-P actually does anything different with this option enabled, but I erred on the side of caution by keeping the most inclusive wording. Cc: linux-arch@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: uclinux-dist-devel@blackfin.uclinux.org Cc: linux-m32r@ml.linux-m32r.org Cc: linux-mips@linux-mips.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-sh@vger.kernel.org Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf Cc: user-mode-linux-devel@lists.sourceforge.net Cc: x86@kernel.org Signed-off-by: Stephen Boyd --- This is on top of mmotm's lib-conslidate-debug_per_cpu_maps patch. arch/arm/Kconfig.debug | 7 ------- arch/blackfin/Kconfig.debug | 9 --------- arch/m32r/Kconfig.debug | 9 --------- arch/mips/Kconfig.debug | 9 --------- arch/powerpc/Kconfig.debug | 9 --------- arch/score/Kconfig.debug | 9 --------- arch/sh/Kconfig.debug | 9 --------- arch/sparc/Kconfig.debug | 9 --------- arch/tile/Kconfig.debug | 9 --------- arch/um/Kconfig.debug | 9 --------- arch/unicore32/Kconfig.debug | 7 ------- arch/x86/Kconfig.debug | 9 --------- lib/Kconfig.debug | 9 +++++++++ 13 files changed, 9 insertions(+), 104 deletions(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 03d01d7..81cbe40 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -63,13 +63,6 @@ config DEBUG_USER 8 - SIGSEGV faults 16 - SIGBUS faults -config DEBUG_STACK_USAGE - bool "Enable stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T output. - # These options are only for real kernel hackers who want to get their hands dirty. config DEBUG_LL bool "Kernel low-level debugging functions" diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index 2641731..19ccfb3 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug @@ -9,15 +9,6 @@ config DEBUG_STACKOVERFLOW This option will cause messages to be printed if free stack space drops below a certain limit. -config DEBUG_STACK_USAGE - bool "Enable stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T output. - - This option will slow down process creation somewhat. - config DEBUG_VERBOSE bool "Verbose fault messages" default y diff --git a/arch/m32r/Kconfig.debug b/arch/m32r/Kconfig.debug index 2e1019d..bb1afc1 100644 --- a/arch/m32r/Kconfig.debug +++ b/arch/m32r/Kconfig.debug @@ -9,15 +9,6 @@ config DEBUG_STACKOVERFLOW This option will cause messages to be printed if free stack space drops below a certain limit. -config DEBUG_STACK_USAGE - bool "Stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T and sysrq-P debug output. - - This option will slow down process creation somewhat. - config DEBUG_PAGEALLOC bool "Debug page memory allocations" depends on DEBUG_KERNEL && BROKEN diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 5358f90..83ed00a 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -76,15 +76,6 @@ config DEBUG_STACKOVERFLOW provides another way to check stack overflow happened on kernel mode stack usually caused by nested interruption. -config DEBUG_STACK_USAGE - bool "Enable stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T and sysrq-P debug output. - - This option will slow down process creation somewhat. - config SMTC_IDLE_HOOK_DEBUG bool "Enable additional debug checks before going into CPU idle loop" depends on DEBUG_KERNEL && MIPS_MT_SMTC diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index 12a8d18..f862fc0 100644 --- a/arch/powerpc/Kconfig.debug +++ b/arch/powerpc/Kconfig.debug @@ -35,15 +35,6 @@ config DEBUG_STACKOVERFLOW This option will cause messages to be printed if free stack space drops below a certain limit. -config DEBUG_STACK_USAGE - bool "Stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T and sysrq-P debug output. - - This option will slow down process creation somewhat. - config HCALL_STATS bool "Hypervisor call instrumentation" depends on PPC_PSERIES && DEBUG_FS && TRACEPOINTS diff --git a/arch/score/Kconfig.debug b/arch/score/Kconfig.debug index 451ed54..a1f346d 100644 --- a/arch/score/Kconfig.debug +++ b/arch/score/Kconfig.debug @@ -16,15 +16,6 @@ config CMDLINE other cases you can specify kernel args so that you don't have to set them up in board prom initialization routines. -config DEBUG_STACK_USAGE - bool "Enable stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T and sysrq-P debug output. - - This option will slow down process creation somewhat. - config RUNTIME_DEBUG bool "Enable run-time debugging" depends on DEBUG_KERNEL diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index 1553d56..c1d5a82 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -28,15 +28,6 @@ config STACK_DEBUG every function call and will therefore incur a major performance hit. Most users should say N. -config DEBUG_STACK_USAGE - bool "Stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T and sysrq-P debug output. - - This option will slow down process creation somewhat. - config 4KSTACKS bool "Use 4Kb for kernel stacks instead of 8Kb" depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB diff --git a/arch/sparc/Kconfig.debug b/arch/sparc/Kconfig.debug index d9a795e..6db35fb 100644 --- a/arch/sparc/Kconfig.debug +++ b/arch/sparc/Kconfig.debug @@ -6,15 +6,6 @@ config TRACE_IRQFLAGS_SUPPORT source "lib/Kconfig.debug" -config DEBUG_STACK_USAGE - bool "Enable stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T and sysrq-P debug output. - - This option will slow down process creation somewhat. - config DEBUG_DCFLUSH bool "D-cache flush debugging" depends on SPARC64 && DEBUG_KERNEL diff --git a/arch/tile/Kconfig.debug b/arch/tile/Kconfig.debug index 9bc161a..ddbfc33 100644 --- a/arch/tile/Kconfig.debug +++ b/arch/tile/Kconfig.debug @@ -21,15 +21,6 @@ config DEBUG_STACKOVERFLOW This option will cause messages to be printed if free stack space drops below a certain limit. -config DEBUG_STACK_USAGE - bool "Stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T and sysrq-P debug output. - - This option will slow down process creation somewhat. - config DEBUG_EXTRA_FLAGS string "Additional compiler arguments when building with '-g'" depends on DEBUG_INFO diff --git a/arch/um/Kconfig.debug b/arch/um/Kconfig.debug index 8fce5e5..34ac57f 100644 --- a/arch/um/Kconfig.debug +++ b/arch/um/Kconfig.debug @@ -28,13 +28,4 @@ config GCOV If you're involved in UML kernel development and want to use gcov, say Y. If you're unsure, say N. -config DEBUG_STACK_USAGE - bool "Stack utilization instrumentation" - default N - help - Track the maximum kernel stack usage - this will look at each - kernel stack at process exit and log it if it's the deepest - stack seen so far. - - This option will slow down process creation and destruction somewhat. endmenu diff --git a/arch/unicore32/Kconfig.debug b/arch/unicore32/Kconfig.debug index 3140151..ae2ec33 100644 --- a/arch/unicore32/Kconfig.debug +++ b/arch/unicore32/Kconfig.debug @@ -27,13 +27,6 @@ config EARLY_PRINTK with klogd/syslogd or the X server. You should normally N here, unless you want to debug such a crash. -config DEBUG_STACK_USAGE - bool "Enable stack utilization instrumentation" - depends on DEBUG_KERNEL - help - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T output. - # These options are only for real kernel hackers who want to get their hands dirty. config DEBUG_LL bool "Kernel low-level debugging functions" diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 1bf8839..c0f8a5c 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -66,15 +66,6 @@ config DEBUG_STACKOVERFLOW This option will cause messages to be printed if free stack space drops below a certain limit. -config DEBUG_STACK_USAGE - bool "Stack utilization instrumentation" - depends on DEBUG_KERNEL - ---help--- - Enables the display of the minimum amount of free stack which each - task has ever had available in the sysrq-T and sysrq-P debug output. - - This option will slow down process creation somewhat. - config X86_PTDUMP bool "Export kernel pagetable layout to userspace via debugfs" depends on DEBUG_KERNEL diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index c0872ee..37fae12 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -654,6 +654,15 @@ config STACKTRACE bool depends on STACKTRACE_SUPPORT +config DEBUG_STACK_USAGE + bool "Stack utilization instrumentation" + depends on DEBUG_KERNEL + help + Enables the display of the minimum amount of free stack which each + task has ever had available in the sysrq-T and sysrq-P debug output. + + This option will slow down process creation somewhat. + config DEBUG_KOBJECT bool "kobject debugging" depends on DEBUG_KERNEL -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. From davem@davemloft.net Sat May 7 09:59:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 09:59:31 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:41124 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491080Ab1EGH7Z (ORCPT ); Sat, 7 May 2011 09:59:25 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 4BBBF24C088; Sat, 7 May 2011 00:58:49 -0700 (PDT) Date: Sat, 07 May 2011 00:58:48 -0700 (PDT) Message-Id: <20110507.005848.226775736.davem@davemloft.net> To: sboyd@codeaurora.org Cc: akpm@linux-foundation.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m32r@ml.linux-m32r.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, cmetcalf@tilera.com, user-mode-linux-devel@lists.sourceforge.net, x86@kernel.org Subject: Re: [PATCH] lib: Consolidate DEBUG_STACK_USAGE option From: David Miller In-Reply-To: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> References: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Stephen Boyd Date: Fri, 6 May 2011 22:57:11 -0700 > Most arches define CONFIG_DEBUG_STACK_USAGE exactly the same way. > Move it to lib/Kconfig.debug so each arch doesn't have to define > it. This obviously makes the option generic, but that's fine > because the config is already used in generic code. > > It's not obvious to me that sysrq-P actually does anything > different with this option enabled, but I erred on the side of > caution by keeping the most inclusive wording. > > Cc: linux-arch@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: uclinux-dist-devel@blackfin.uclinux.org > Cc: linux-m32r@ml.linux-m32r.org > Cc: linux-mips@linux-mips.org > Cc: linuxppc-dev@lists.ozlabs.org > Cc: linux-sh@vger.kernel.org > Cc: sparclinux@vger.kernel.org > Cc: Chris Metcalf > Cc: user-mode-linux-devel@lists.sourceforge.net > Cc: x86@kernel.org > Signed-off-by: Stephen Boyd Acked-by: David S. Miller From richard.weinberger@gmail.com Sat May 7 11:34:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 11:34:23 +0200 (CEST) Received: from mail-qy0-f170.google.com ([209.85.216.170]:57428 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491091Ab1EGJeT (ORCPT ); Sat, 7 May 2011 11:34:19 +0200 Received: by qyk32 with SMTP id 32so173758qyk.15 for ; Sat, 07 May 2011 02:34:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=W5wBK0z0EUrvQyCJT8CpsoCttbsrZMtSsWXEPYVPEZc=; b=hwkmDLHujzf1JOmm3EhjyW8upxjRYgAZwbQ3OqQrt0/hSyIKdI8dOd6RGgiolW6PS4 9RYh0YYkBQ4E716Kp+gwynyBBxXy5P9zioXlXjxLyqzLRdw9yLuBECmPQtNVgYXZbHuX cXsU98EeZFAMydU4ZjEbYs7Y/T56fLxEF6EmU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=mgV2bLMx3VUAdB+8XUTU0H9RJ/WP+1TEAnuSBJ1vFVpKOTcIDroyKjWIMjqrc7nflU 0Y/UqcBlwgdKW0qhCcmexDYGUxopDjq2pM6PXuFMiLLogwXE56geGoe4Qbauz23ExPEX qWap9e9El189yStq2x45uRgQ2aOiQTjJq9s+w= MIME-Version: 1.0 Received: by 10.224.63.199 with SMTP id c7mr4432120qai.146.1304760853419; Sat, 07 May 2011 02:34:13 -0700 (PDT) Received: by 10.224.10.204 with HTTP; Sat, 7 May 2011 02:34:13 -0700 (PDT) In-Reply-To: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> References: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> Date: Sat, 7 May 2011 11:34:13 +0200 Message-ID: Subject: Re: [PATCH] lib: Consolidate DEBUG_STACK_USAGE option From: richard -rw- weinberger To: Stephen Boyd Cc: Andrew Morton , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m32r@ml.linux-m32r.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Chris Metcalf , user-mode-linux-devel@lists.sourceforge.net, x86@kernel.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: richard.weinberger@gmail.com Precedence: bulk X-list: linux-mips On Sat, May 7, 2011 at 7:57 AM, Stephen Boyd wrote: > Most arches define CONFIG_DEBUG_STACK_USAGE exactly the same way. > Move it to lib/Kconfig.debug so each arch doesn't have to define > it. This obviously makes the option generic, but that's fine > because the config is already used in generic code. > > It's not obvious to me that sysrq-P actually does anything > different with this option enabled, but I erred on the side of > caution by keeping the most inclusive wording. > > Cc: linux-arch@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: uclinux-dist-devel@blackfin.uclinux.org > Cc: linux-m32r@ml.linux-m32r.org > Cc: linux-mips@linux-mips.org > Cc: linuxppc-dev@lists.ozlabs.org > Cc: linux-sh@vger.kernel.org > Cc: sparclinux@vger.kernel.org > Cc: Chris Metcalf > Cc: user-mode-linux-devel@lists.sourceforge.net > Cc: x86@kernel.org > Signed-off-by: Stephen Boyd > --- Acked-by: Richard Weinberger -- Thanks, //richard From manuel.lauss@googlemail.com Sat May 7 13:55:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 13:55:39 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:50522 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491119Ab1EGLze (ORCPT ); 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Sat, 07 May 2011 04:55:28 -0700 (PDT) From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS , Manuel Lauss Subject: [PATCH] MIPS: Alchemy: fix xxs1500 build error Date: Sat, 7 May 2011 13:55:19 +0200 Message-Id: <1304769319-25167-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips This fixes: alchemy/xxs1500/init.c: In function 'prom_init': alchemy/xxs1500/init.c:57:17: error: ignoring return value of 'kstrtoul', declared with attribute warn_unused_result Signed-off-by: Manuel Lauss --- arch/mips/alchemy/xxs1500/init.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c index 0bf768f..0ee02cf 100644 --- a/arch/mips/alchemy/xxs1500/init.c +++ b/arch/mips/alchemy/xxs1500/init.c @@ -51,10 +51,9 @@ void __init prom_init(void) prom_init_cmdline(); memsize_str = prom_getenv("memsize"); - if (!memsize_str) + if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) memsize = 0x04000000; - else - strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); } -- 1.7.5.rc3 From hauke@hauke-m.de Sat May 7 14:28:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 14:28:08 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45531 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491121Ab1EGM2C (ORCPT ); Sat, 7 May 2011 14:28:02 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 0C53D8ACB; Sat, 7 May 2011 14:28:01 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OmfcjUvQQOlw; Sat, 7 May 2011 14:27:54 +0200 (CEST) Received: from localhost.localdomain (dyndsl-085-016-167-129.ewe-ip-backbone.de [85.16.167.129]) by hauke-m.de (Postfix) with ESMTPSA id 4BDC48AC9; Sat, 7 May 2011 14:27:54 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 0/5] MIPS: BCM47xx: Enhancements in Parsing the NVRAM data Date: Sat, 7 May 2011 14:27:38 +0200 Message-Id: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29856 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips The first 3 patches add the ability to provide an fallback sprom from the nvram when a card connected to the pci bus using a ssb bus itself has no own sprom. Then the ssb code now asks the architecture code for the data. In the bcm47xx architecture the sprom data is stored in the nvram for recent devices and they do not have an own sprom. Patch #4 looks for some more values in the sprom. Boradcom changed the names of some attributes with sprom revision 4. The last patch fixes the parsing of mac addresses on some devices. Hauke Mehrtens (5): ssb: Change fallback sprom to callback mechanism. MIPS: BCM47xx: extend bcm47xx_fill_sprom with prefix. MIPS: BCM47xx: register ssb fallback sprom callback MIPS: BCM47xx: extend the filling of sprom from nvram MIPS: BCM47xx: Fix mac address parsing. arch/mips/bcm47xx/nvram.c | 3 +- arch/mips/bcm47xx/setup.c | 130 +++++++++++++++++++++++----- arch/mips/bcm63xx/boards/board_bcm963xx.c | 16 +++- arch/mips/include/asm/mach-bcm47xx/nvram.h | 11 ++- drivers/ssb/pci.c | 16 +++- drivers/ssb/sprom.c | 26 +++--- drivers/ssb/ssb_private.h | 2 +- include/linux/ssb/ssb.h | 4 +- 8 files changed, 163 insertions(+), 45 deletions(-) -- 1.7.4.1 From hauke@hauke-m.de Sat May 7 14:28:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 14:28:30 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45543 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491122Ab1EGM2H (ORCPT ); Sat, 7 May 2011 14:28:07 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 530148ACE; Sat, 7 May 2011 14:28:07 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id omqL2Rkf17fe; Sat, 7 May 2011 14:28:02 +0200 (CEST) Received: from localhost.localdomain (dyndsl-085-016-167-129.ewe-ip-backbone.de [85.16.167.129]) by hauke-m.de (Postfix) with ESMTPSA id 248F28AC9; Sat, 7 May 2011 14:28:02 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens , Michael Buesch , netdev@vger.kernel.org, Florian Fainelli Subject: [PATCH 1/5] ssb: Change fallback sprom to callback mechanism. Date: Sat, 7 May 2011 14:27:39 +0200 Message-Id: <1304771263-10937-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Some embedded devices like the Netgear WNDR3300 have two SSB based cards without an own sprom on the pci bus. We have to provide two different fallback sproms for these and this was not possible with the old solution. In the bcm47xx architecture the sprom data is stored in the nvram in the main flash storage. The architecture code will be able to fill the sprom with the stored data based on the bus where the device was found. The bcm63xx code should to the same thing as before, just using the new API. CC: Michael Buesch CC: netdev@vger.kernel.org CC: Florian Fainelli Signed-off-by: Hauke Mehrtens --- arch/mips/bcm63xx/boards/board_bcm963xx.c | 16 ++++++++++++++-- drivers/ssb/pci.c | 16 +++++++++++----- drivers/ssb/sprom.c | 26 +++++++++++++++----------- drivers/ssb/ssb_private.h | 2 +- include/linux/ssb/ssb.h | 4 +++- 5 files changed, 44 insertions(+), 20 deletions(-) diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 8dba8cf..40b223b 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -643,6 +643,17 @@ static struct ssb_sprom bcm63xx_sprom = { .boardflags_lo = 0x2848, .boardflags_hi = 0x0000, }; + +int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +{ + if (bus->bustype == SSB_BUSTYPE_PCI) { + memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); + return 0; + } else { + printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); + return -EINVAL; + } +} #endif /* @@ -793,8 +804,9 @@ void __init board_prom_init(void) if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); - if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0) - printk(KERN_ERR "failed to register fallback SPROM\n"); + if (ssb_arch_register_fallback_sprom( + &bcm63xx_get_fallback_sprom) < 0) + printk(KERN_ERR PFX "failed to register fallback SPROM\n"); } #endif } diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c index 6f34963..34955d1 100644 --- a/drivers/ssb/pci.c +++ b/drivers/ssb/pci.c @@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out, static int ssb_pci_sprom_get(struct ssb_bus *bus, struct ssb_sprom *sprom) { - const struct ssb_sprom *fallback; int err; u16 *buf; @@ -707,10 +706,17 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus, if (err) { /* All CRC attempts failed. * Maybe there is no SPROM on the device? - * If we have a fallback, use that. */ - fallback = ssb_get_fallback_sprom(); - if (fallback) { - memcpy(sprom, fallback, sizeof(*sprom)); + * Now we ask the arch code if there is some sprom + * avaliable for this device in some other storage */ + err = ssb_fill_sprom_with_fallback(bus, sprom); + if (err) { + ssb_printk(KERN_WARNING PFX "WARNING: Using" + " fallback SPROM failed (err %d)\n", + err); + } else { + ssb_dprintk(KERN_DEBUG PFX "Using SPROM" + " revision %d provided by" + " platform.\n", sprom->revision); err = 0; goto out_free; } diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c index 5f34d7a..20cd139 100644 --- a/drivers/ssb/sprom.c +++ b/drivers/ssb/sprom.c @@ -17,7 +17,7 @@ #include -static const struct ssb_sprom *fallback_sprom; +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out); static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len, @@ -145,13 +145,14 @@ out: } /** - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found. + * ssb_arch_register_fallback_sprom - Registers a method providing a fallback + * SPROM if no SPROM is found. * - * @sprom: The SPROM data structure to register. + * @sprom_callback: The callbcak function. * - * With this function the architecture implementation may register a fallback - * SPROM data structure. The fallback is only used for PCI based SSB devices, - * where no valid SPROM can be found in the shadow registers. + * With this function the architecture implementation may register a callback + * handler which wills the SPROM data structure. The fallback is only used for + * PCI based SSB devices, where no valid SPROM can be found in the shadow registers. * * This function is useful for weird architectures that have a half-assed SSB device * hardwired to their PCI bus. @@ -163,18 +164,21 @@ out: * * This function is available for architecture code, only. So it is not exported. */ -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom) +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus, struct ssb_sprom *out)) { - if (fallback_sprom) + if (get_fallback_sprom) return -EEXIST; - fallback_sprom = sprom; + get_fallback_sprom = sprom_callback; return 0; } -const struct ssb_sprom *ssb_get_fallback_sprom(void) +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out) { - return fallback_sprom; + if (!get_fallback_sprom) + return -ENOENT; + + return get_fallback_sprom(bus, out); } /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h index 0331139..1a32f58 100644 --- a/drivers/ssb/ssb_private.h +++ b/drivers/ssb/ssb_private.h @@ -171,7 +171,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_bus *bus, const char *buf, size_t count, int (*sprom_check_crc)(const u16 *sprom, size_t size), int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom)); -extern const struct ssb_sprom *ssb_get_fallback_sprom(void); +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out); /* core.c */ diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 9659eff..045f72a 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -404,7 +404,9 @@ extern bool ssb_is_sprom_available(struct ssb_bus *bus); /* Set a fallback SPROM. * See kdoc at the function definition for complete documentation. */ -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom); +extern int ssb_arch_register_fallback_sprom( + int (*sprom_callback)(struct ssb_bus *bus, + struct ssb_sprom *out)); /* Suspend a SSB bus. * Call this from the parent bus suspend routine. */ -- 1.7.4.1 From hauke@hauke-m.de Sat May 7 14:28:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 14:28:58 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45552 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491130Ab1EGM2I (ORCPT ); Sat, 7 May 2011 14:28:08 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 900C68AD0; Sat, 7 May 2011 14:28:08 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Eaqw+vBxS1e6; Sat, 7 May 2011 14:28:04 +0200 (CEST) Received: from localhost.localdomain (dyndsl-085-016-167-129.ewe-ip-backbone.de [85.16.167.129]) by hauke-m.de (Postfix) with ESMTPSA id B9BFA8ACA; Sat, 7 May 2011 14:28:03 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 2/5] MIPS: BCM47xx: extend bcm47xx_fill_sprom with prefix. Date: Sat, 7 May 2011 14:27:40 +0200 Message-Id: <1304771263-10937-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips When an other ssb based device without an own sprom is attached, using the PCI bus to the main ssb based device, the data normally found in the sprom will be stored in the nvram on modern devices. The keys, to load the data from the nvram, are all using some sort of prefix like pci/1/1/, pci/1/3/ or sb/1/ before the actual key. This patch extends bcm47xx_fill_sprom() to make it possible to read out these values when some prefix was used. The keys for the sprom data used on the main chip does not have a prefix. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/setup.c | 29 +++++++++++++++++++++-------- 1 files changed, 21 insertions(+), 8 deletions(-) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index c95f90b..bbfcf9b 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -57,10 +57,23 @@ static void bcm47xx_machine_halt(void) } #define READ_FROM_NVRAM(_outvar, name, buf) \ - if (nvram_getenv(name, buf, sizeof(buf)) >= 0)\ + if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ sprom->_outvar = simple_strtoul(buf, NULL, 0); -static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) +static inline int nvram_getprefix(const char *prefix, char *name, + char *buf, int len) +{ + if (prefix) { + char key[100]; + + snprintf(key, sizeof(key), "%s%s", prefix, name); + return nvram_getenv(key, buf, len); + } + + return nvram_getenv(name, buf, len); +} + +static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) { char buf[100]; u32 boardflags; @@ -69,11 +82,11 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) sprom->revision = 1; /* Fallback: Old hardware does not define this. */ READ_FROM_NVRAM(revision, "sromrev", buf); - if (nvram_getenv("il0macaddr", buf, sizeof(buf)) >= 0) + if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->il0mac); - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0) + if (nvram_getprefix(prefix, "et0macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->et0mac); - if (nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0) + if (nvram_getprefix(prefix, "et1macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->et1mac); READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf); READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf); @@ -125,14 +138,14 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) READ_FROM_NVRAM(ofdm5gpo, "ofdm5gpo", buf); READ_FROM_NVRAM(ofdm5ghpo, "ofdm5ghpo", buf); - if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0) { + if (nvram_getprefix(prefix, "boardflags", buf, sizeof(buf)) >= 0) { boardflags = simple_strtoul(buf, NULL, 0); if (boardflags) { sprom->boardflags_lo = (boardflags & 0x0000FFFFU); sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16; } } - if (nvram_getenv("boardflags2", buf, sizeof(buf)) >= 0) { + if (nvram_getprefix(prefix, "boardflags2", buf, sizeof(buf)) >= 0) { boardflags = simple_strtoul(buf, NULL, 0); if (boardflags) { sprom->boardflags2_lo = (boardflags & 0x0000FFFFU); @@ -158,7 +171,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus, if (nvram_getenv("boardrev", buf, sizeof(buf)) >= 0) iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0); - bcm47xx_fill_sprom(&iv->sprom); + bcm47xx_fill_sprom(&iv->sprom, NULL); if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0) iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10); -- 1.7.4.1 From hauke@hauke-m.de Sat May 7 14:29:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 14:29:24 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45563 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491131Ab1EGM2M (ORCPT ); Sat, 7 May 2011 14:28:12 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id CBEDD8ACA; Sat, 7 May 2011 14:28:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Fxn3wuWHil-L; Sat, 7 May 2011 14:28:07 +0200 (CEST) Received: from localhost.localdomain (dyndsl-085-016-167-129.ewe-ip-backbone.de [85.16.167.129]) by hauke-m.de (Postfix) with ESMTPSA id 8AB0A8ACB; Sat, 7 May 2011 14:28:04 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 3/5] MIPS: BCM47xx: register ssb fallback sprom callback Date: Sat, 7 May 2011 14:27:41 +0200 Message-Id: <1304771263-10937-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29859 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips We are generating the prefix based on the PCI bus address the device is on. This is done like Broadcom does it in their code expect that the the bus number is increased by one. In the SB bus implementation used by Broadcom the SB bus emulates a PCI bus so the kernel sees one PCI bus more then in our implementation. We do not handle prefixes like sb/1/ yet as they are only used on the new bus which is not implemented yet. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/nvram.c | 3 ++- arch/mips/bcm47xx/setup.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletions(-) diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index e5b6615..54db815 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -3,6 +3,7 @@ * * Copyright (C) 2005 Broadcom Corporation * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2010-2011 Hauke Mehrtens * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -23,7 +24,7 @@ static char nvram_buf[NVRAM_SPACE]; /* Probe for NVRAM header */ -static void __init early_nvram_init(void) +static void early_nvram_init(void) { struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore; struct nvram_header *header; diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index bbfcf9b..258ffcf 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -3,6 +3,7 @@ * Copyright (C) 2006 Felix Fietkau * Copyright (C) 2006 Michael Buesch * Copyright (C) 2010 Waldemar Brodkorb + * Copyright (C) 2010-2011 Hauke Mehrtens * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -154,6 +155,22 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) } } +int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +{ + char prefix[10]; + + if (bus->bustype == SSB_BUSTYPE_PCI) { + snprintf(prefix, sizeof(prefix), "pci/%u/%u/", + bus->host_pci->bus->number + 1, + PCI_SLOT(bus->host_pci->devfn)); + bcm47xx_fill_sprom(out, prefix); + return 0; + } else { + printk(KERN_WARNING "bcm47xx: unable to fill SPROM for given bustype.\n"); + return -EINVAL; + } +} + static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv) { @@ -185,6 +202,11 @@ void __init plat_mem_setup(void) char buf[100]; struct ssb_mipscore *mcore; + err = ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom); + if (err) + printk(KERN_WARNING "bcm47xx: someone else already registered" + " a ssb SPROM callback handler (err %d)\n", err); + err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants); if (err) -- 1.7.4.1 From hauke@hauke-m.de Sat May 7 14:29:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 14:29:49 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45564 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491132Ab1EGM2N (ORCPT ); Sat, 7 May 2011 14:28:13 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 17ADC8ACA; Sat, 7 May 2011 14:28:13 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WLIc8fAmeV2E; Sat, 7 May 2011 14:28:08 +0200 (CEST) Received: from localhost.localdomain (dyndsl-085-016-167-129.ewe-ip-backbone.de [85.16.167.129]) by hauke-m.de (Postfix) with ESMTPSA id 74BE58ACC; Sat, 7 May 2011 14:28:05 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 4/5] MIPS: BCM47xx: extend the filling of sprom from nvram Date: Sat, 7 May 2011 14:27:42 +0200 Message-Id: <1304771263-10937-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Some members of the struct ssb_sprom where not filled with data available in the nvram. Some attribute names in the nvram changed from sprom version 3 to version 4. This patch was done by analyzing the the pci sprom parser in the ssb code and some open source parts of the braodcom wireless driver used on embedded devices. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/setup.c | 81 ++++++++++++++++++++++++++++++++++++-------- 1 files changed, 66 insertions(+), 15 deletions(-) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 258ffcf..73b529b 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -61,6 +61,11 @@ static void bcm47xx_machine_halt(void) if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ sprom->_outvar = simple_strtoul(buf, NULL, 0); +#define READ_FROM_NVRAM2(_outvar, name1, name2, buf) \ + if (nvram_getprefix(prefix, name1, buf, sizeof(buf)) >= 0 || \ + nvram_getprefix(prefix, name2, buf, sizeof(buf)) >= 0)\ + sprom->_outvar = simple_strtoul(buf, NULL, 0); + static inline int nvram_getprefix(const char *prefix, char *name, char *buf, int len) { @@ -74,6 +79,27 @@ static inline int nvram_getprefix(const char *prefix, char *name, return nvram_getenv(name, buf, len); } +static u32 nvram_getu32(const char *name, char *buf, int len) +{ + int rv; + char key[100]; + u16 var0, var1; + + snprintf(key, sizeof(key), "%s0", name); + rv = nvram_getenv(key, buf, len); + /* return 0 here so this looks like unset */ + if (rv < 0) + return 0; + var0 = simple_strtoul(buf, NULL, 0); + + snprintf(key, sizeof(key), "%s1", name); + rv = nvram_getenv(key, buf, len); + if (rv < 0) + return 0; + var1 = simple_strtoul(buf, NULL, 0); + return var1 << 16 | var0; +} + static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) { char buf[100]; @@ -83,7 +109,8 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) sprom->revision = 1; /* Fallback: Old hardware does not define this. */ READ_FROM_NVRAM(revision, "sromrev", buf); - if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0) + if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0 || + nvram_getprefix(prefix, "macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->il0mac); if (nvram_getprefix(prefix, "et0macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->et0mac); @@ -109,20 +136,36 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf); READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf); READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf); - READ_FROM_NVRAM(gpio0, "wl0gpio0", buf); - READ_FROM_NVRAM(gpio1, "wl0gpio1", buf); - READ_FROM_NVRAM(gpio2, "wl0gpio2", buf); - READ_FROM_NVRAM(gpio3, "wl0gpio3", buf); - READ_FROM_NVRAM(maxpwr_bg, "pa0maxpwr", buf); - READ_FROM_NVRAM(maxpwr_al, "pa1lomaxpwr", buf); - READ_FROM_NVRAM(maxpwr_a, "pa1maxpwr", buf); - READ_FROM_NVRAM(maxpwr_ah, "pa1himaxpwr", buf); - READ_FROM_NVRAM(itssi_a, "pa1itssit", buf); - READ_FROM_NVRAM(itssi_bg, "pa0itssit", buf); + READ_FROM_NVRAM2(gpio0, "ledbh0", "wl0gpio0", buf); + READ_FROM_NVRAM2(gpio1, "ledbh1", "wl0gpio1", buf); + READ_FROM_NVRAM2(gpio2, "ledbh2", "wl0gpio2", buf); + READ_FROM_NVRAM2(gpio3, "ledbh3", "wl0gpio3", buf); + READ_FROM_NVRAM2(maxpwr_bg, "maxp2ga0", "pa0maxpwr", buf); + READ_FROM_NVRAM2(maxpwr_al, "maxp5gla0", "pa1lomaxpwr", buf); + READ_FROM_NVRAM2(maxpwr_a, "maxp5ga0", "pa1maxpwr", buf); + READ_FROM_NVRAM2(maxpwr_ah, "maxp5gha0", "pa1himaxpwr", buf); + READ_FROM_NVRAM2(itssi_bg, "itt5ga0", "pa0itssit", buf); + READ_FROM_NVRAM2(itssi_a, "itt2ga0", "pa1itssit", buf); READ_FROM_NVRAM(tri2g, "tri2g", buf); READ_FROM_NVRAM(tri5gl, "tri5gl", buf); READ_FROM_NVRAM(tri5g, "tri5g", buf); READ_FROM_NVRAM(tri5gh, "tri5gh", buf); + READ_FROM_NVRAM(txpid2g[0], "txpid2ga0", buf); + READ_FROM_NVRAM(txpid2g[1], "txpid2ga1", buf); + READ_FROM_NVRAM(txpid2g[2], "txpid2ga2", buf); + READ_FROM_NVRAM(txpid2g[3], "txpid2ga3", buf); + READ_FROM_NVRAM(txpid5g[0], "txpid5ga0", buf); + READ_FROM_NVRAM(txpid5g[1], "txpid5ga1", buf); + READ_FROM_NVRAM(txpid5g[2], "txpid5ga2", buf); + READ_FROM_NVRAM(txpid5g[3], "txpid5ga3", buf); + READ_FROM_NVRAM(txpid5gl[0], "txpid5gla0", buf); + READ_FROM_NVRAM(txpid5gl[1], "txpid5gla1", buf); + READ_FROM_NVRAM(txpid5gl[2], "txpid5gla2", buf); + READ_FROM_NVRAM(txpid5gl[3], "txpid5gla3", buf); + READ_FROM_NVRAM(txpid5gh[0], "txpid5gha0", buf); + READ_FROM_NVRAM(txpid5gh[1], "txpid5gha1", buf); + READ_FROM_NVRAM(txpid5gh[2], "txpid5gha2", buf); + READ_FROM_NVRAM(txpid5gh[3], "txpid5gha3", buf); READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf); READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf); READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf); @@ -134,10 +177,18 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf); READ_FROM_NVRAM(bxa5g, "bxa5g", buf); READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf); - READ_FROM_NVRAM(ofdm2gpo, "ofdm2gpo", buf); - READ_FROM_NVRAM(ofdm5glpo, "ofdm5glpo", buf); - READ_FROM_NVRAM(ofdm5gpo, "ofdm5gpo", buf); - READ_FROM_NVRAM(ofdm5ghpo, "ofdm5ghpo", buf); + + sprom->ofdm2gpo = nvram_getu32("ofdm2gpo", buf, sizeof(buf)); + sprom->ofdm5glpo = nvram_getu32("ofdm5glpo", buf, sizeof(buf)); + sprom->ofdm5gpo = nvram_getu32("ofdm5gpo", buf, sizeof(buf)); + sprom->ofdm5ghpo = nvram_getu32("ofdm5ghpo", buf, sizeof(buf)); + + READ_FROM_NVRAM(antenna_gain.ghz24.a0, "ag0", buf); + READ_FROM_NVRAM(antenna_gain.ghz24.a1, "ag1", buf); + READ_FROM_NVRAM(antenna_gain.ghz24.a2, "ag2", buf); + READ_FROM_NVRAM(antenna_gain.ghz24.a3, "ag3", buf); + memcpy(&sprom->antenna_gain.ghz5, &sprom->antenna_gain.ghz24, + sizeof(sprom->antenna_gain.ghz5)); if (nvram_getprefix(prefix, "boardflags", buf, sizeof(buf)) >= 0) { boardflags = simple_strtoul(buf, NULL, 0); -- 1.7.4.1 From hauke@hauke-m.de Sat May 7 14:30:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 14:30:12 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45569 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491133Ab1EGM2P (ORCPT ); Sat, 7 May 2011 14:28:15 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 3B8A78ACA; Sat, 7 May 2011 14:28:15 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ofcW9B8Rw1Ux; Sat, 7 May 2011 14:28:12 +0200 (CEST) Received: from localhost.localdomain (dyndsl-085-016-167-129.ewe-ip-backbone.de [85.16.167.129]) by hauke-m.de (Postfix) with ESMTPSA id 7534A8ACD; Sat, 7 May 2011 14:28:06 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 5/5] MIPS: BCM47xx: Fix mac address parsing. Date: Sat, 7 May 2011 14:27:43 +0200 Message-Id: <1304771263-10937-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29861 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Some devices like the Netgear WGT634u are using minuses between the blocks of the mac address and other devices are using colons to separate them. Signed-off-by: Hauke Mehrtens --- arch/mips/include/asm/mach-bcm47xx/nvram.h | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h index 9759588..fcdeca7 100644 --- a/arch/mips/include/asm/mach-bcm47xx/nvram.h +++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h @@ -39,8 +39,15 @@ extern int nvram_getenv(char *name, char *val, size_t val_len); static inline void nvram_parse_macaddr(char *buf, u8 *macaddr) { - sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1], - &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); + if (strchr(buf, ':')) { + sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1], + &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); + } else if (strchr(buf, '-')) { + sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0], &macaddr[1], + &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); + } else { + printk(KERN_WARNING "Can not parse mac address: %s\n", buf); + } } #endif -- 1.7.4.1 From vapier.adi@gmail.com Sat May 7 15:58:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 15:58:05 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:62859 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491133Ab1EGN6C convert rfc822-to-8bit (ORCPT ); Sat, 7 May 2011 15:58:02 +0200 Received: by gwb1 with SMTP id 1so1690053gwb.36 for ; Sat, 07 May 2011 06:57:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type:content-transfer-encoding; bh=qdWXqpLcSdrAozQSyMRhm8+brTjY5ljbON6AkM7gwx4=; b=SigZo8TCsMtxb5LcTlVeJbAuf4BZQIL3JEmm1ZvwG0mPvcIF9NAvcIhGqkAmeACr0c 0Iu9ZD8HiPa7KrreNap/FzutuJQMGPn1IUY2hpu7yVbGJtOmrZyc2nuTo4J76k3fX4L7 4mnW0JvEF6g0NvIELuX84ZZ30S3XIuQLSAMJA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=uZNU4vBtr1nEzDniqj6ZZSb/STeRU4c7Li1naXui78IaDNyP+rOE2yrOj1Jnq6bA1k WSnSeNLRM7/B8Ul6Yq2l0e33egeSpjsbxNf5KRjAS4vE5LtLKvLVTjOB090mjNwcFunZ u7nex1U1AzW+fN+QwkR6l/uEQ3Iex/8UcKBcY= Received: by 10.91.69.37 with SMTP id w37mr4286956agk.196.1304776676200; Sat, 07 May 2011 06:57:56 -0700 (PDT) MIME-Version: 1.0 Received: by 10.91.54.28 with HTTP; Sat, 7 May 2011 06:57:36 -0700 (PDT) In-Reply-To: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> References: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> From: Mike Frysinger Date: Sat, 7 May 2011 09:57:36 -0400 Message-ID: Subject: Re: [PATCH] lib: Consolidate DEBUG_STACK_USAGE option To: Stephen Boyd Cc: Andrew Morton , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m32r@ml.linux-m32r.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Chris Metcalf , user-mode-linux-devel@lists.sourceforge.net, x86@kernel.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29862 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vapier.adi@gmail.com Precedence: bulk X-list: linux-mips On Sat, May 7, 2011 at 01:57, Stephen Boyd wrote: > Most arches define CONFIG_DEBUG_STACK_USAGE exactly the same way. > Move it to lib/Kconfig.debug so each arch doesn't have to define > it. This obviously makes the option generic, but that's fine > because the config is already used in generic code. > > It's not obvious to me that sysrq-P actually does anything > different with this option enabled, but I erred on the side of > caution by keeping the most inclusive wording. > > Cc: uclinux-dist-devel@blackfin.uclinux.org >  arch/blackfin/Kconfig.debug  |    9 --------- Acked-by: Mike Frysinger -mike From sshtylyov@mvista.com Sat May 7 17:06:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 17:06:43 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:55053 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491133Ab1EGPGh (ORCPT ); Sat, 7 May 2011 17:06:37 +0200 Received: by eyh6 with SMTP id 6so1363261eyh.36 for ; Sat, 07 May 2011 08:06:31 -0700 (PDT) Received: by 10.14.122.81 with SMTP id s57mr2584434eeh.195.1304780791456; Sat, 07 May 2011 08:06:31 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id s1sm2123276ees.3.2011.05.07.08.06.28 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 07 May 2011 08:06:29 -0700 (PDT) Message-ID: <4DC55F80.7010409@mvista.com> Date: Sat, 07 May 2011 19:04:32 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Hauke Mehrtens CC: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 5/5] MIPS: BCM47xx: Fix mac address parsing. References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> <1304771263-10937-6-git-send-email-hauke@hauke-m.de> In-Reply-To: <1304771263-10937-6-git-send-email-hauke@hauke-m.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29863 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Hauke Mehrtens wrote: > Some devices like the Netgear WGT634u are using minuses between the > blocks of the mac address and other devices are using colons to > separate them. > Signed-off-by: Hauke Mehrtens > --- > arch/mips/include/asm/mach-bcm47xx/nvram.h | 11 +++++++++-- > 1 files changed, 9 insertions(+), 2 deletions(-) > diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h > index 9759588..fcdeca7 100644 > --- a/arch/mips/include/asm/mach-bcm47xx/nvram.h > +++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h > @@ -39,8 +39,15 @@ extern int nvram_getenv(char *name, char *val, size_t val_len); > > static inline void nvram_parse_macaddr(char *buf, u8 *macaddr) > { > - sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1], > - &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); > + if (strchr(buf, ':')) { > + sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1], > + &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); > + } else if (strchr(buf, '-')) { > + sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0], &macaddr[1], > + &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); > + } else { > + printk(KERN_WARNING "Can not parse mac address: %s\n", buf); > + } > } > > #endif checkcptach.pl says: WARNING: line over 80 characters #21: FILE: arch/mips/include/asm/mach-bcm47xx/nvram.h:43: + sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1], WARNING: line over 80 characters #24: FILE: arch/mips/include/asm/mach-bcm47xx/nvram.h:46: + sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0], &macaddr[1], total: 0 errors, 2 warnings, 17 lines checked patches/MIPS-BCM47xx-Fix-mac-address-parsing.patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Additionally, though the script doesn't warn about this, {} are not necessary -- every branch is really a single statement. WBR, Sergei From hauke@hauke-m.de Sat May 7 18:15:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 18:15:47 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:44945 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491137Ab1EGQPk (ORCPT ); Sat, 7 May 2011 18:15:40 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id DAD688ACA; Sat, 7 May 2011 18:15:38 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QM64tl2acck1; Sat, 7 May 2011 18:15:35 +0200 (CEST) Received: from [192.168.0.151] (dyndsl-085-016-167-129.ewe-ip-backbone.de [85.16.167.129]) by hauke-m.de (Postfix) with ESMTPSA id 7F9FD8AC9; Sat, 7 May 2011 18:15:35 +0200 (CEST) Message-ID: <4DC57027.2010806@hauke-m.de> Date: Sat, 07 May 2011 18:15:35 +0200 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110424 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 To: Sergei Shtylyov CC: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 5/5] MIPS: BCM47xx: Fix mac address parsing. References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> <1304771263-10937-6-git-send-email-hauke@hauke-m.de> <4DC55F80.7010409@mvista.com> In-Reply-To: <4DC55F80.7010409@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29864 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips On 05/07/2011 05:04 PM, Sergei Shtylyov wrote: > Hello. > > Hauke Mehrtens wrote: > >> Some devices like the Netgear WGT634u are using minuses between the >> blocks of the mac address and other devices are using colons to >> separate them. > >> Signed-off-by: Hauke Mehrtens >> --- >> arch/mips/include/asm/mach-bcm47xx/nvram.h | 11 +++++++++-- >> 1 files changed, 9 insertions(+), 2 deletions(-) > >> diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h >> b/arch/mips/include/asm/mach-bcm47xx/nvram.h >> index 9759588..fcdeca7 100644 >> --- a/arch/mips/include/asm/mach-bcm47xx/nvram.h >> +++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h >> @@ -39,8 +39,15 @@ extern int nvram_getenv(char *name, char *val, >> size_t val_len); >> >> static inline void nvram_parse_macaddr(char *buf, u8 *macaddr) >> { >> - sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], >> &macaddr[1], >> - &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); >> + if (strchr(buf, ':')) { >> + sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], >> &macaddr[1], >> + &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); >> + } else if (strchr(buf, '-')) { >> + sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0], >> &macaddr[1], >> + &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); >> + } else { >> + printk(KERN_WARNING "Can not parse mac address: %s\n", buf); >> + } >> } >> >> #endif > > checkcptach.pl says: > > WARNING: line over 80 characters > #21: FILE: arch/mips/include/asm/mach-bcm47xx/nvram.h:43: > + sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], > &macaddr[1], > > WARNING: line over 80 characters > #24: FILE: arch/mips/include/asm/mach-bcm47xx/nvram.h:46: > + sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0], > &macaddr[1], > > total: 0 errors, 2 warnings, 17 lines checked > > patches/MIPS-BCM47xx-Fix-mac-address-parsing.patch has style problems, > please review. If any of these errors > are false positives report them to the maintainer, see > CHECKPATCH in MAINTAINERS. > > Additionally, though the script doesn't warn about this, {} are not > necessary -- every branch is really a single statement. > > WBR, Sergei Hi Sergei, I will fix this and send a new version. I checked it with checkpatch, but changed some parts after that. ;-) Hauke From jonas.gorski@gmail.com Sat May 7 19:24:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 May 2011 19:24:47 +0200 (CEST) Received: from mail-qy0-f177.google.com ([209.85.216.177]:40242 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491142Ab1EGRYo convert rfc822-to-8bit (ORCPT ); Sat, 7 May 2011 19:24:44 +0200 Received: by qyl38 with SMTP id 38so3761394qyl.15 for ; Sat, 07 May 2011 10:24:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type:content-transfer-encoding; bh=KjtSvzSNEK39jCQQvsWFfibn7y4jBmF8y0mBbjVhzdk=; b=xQIIgjROYREM7vbapu6XU6ImcnfwYhRh1TqtLTviyIRsLTWrSttWg1QjH8yJpzzcxT gHo6oo9SSNhfzRa9v9zEIA0K4JIMD++ov/VASajawXOUo9xzWbwte24N3P3oQPuh/DJE 5uaKmgXbke+Bqj1zdVHvPXgz6fwER1UW2kua0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=p1BA63pfHBxx+pGp0k01/JdZS+h3O9RRe7uEQ6xo1xsO4fFHpatkv/wK+tsgoWC1jY JEF8MqL+eVE5XYaMCTEB3++EECb5nbERgxjtBteHD4GXr7uRH/Qs2e71KaJRVaxCofy+ YGzfezZfr9mhzWQ3p8+v/wqQTD2u0oJ6s6weI= Received: by 10.229.197.13 with SMTP id ei13mr1629624qcb.50.1304789078194; Sat, 07 May 2011 10:24:38 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.184.69 with HTTP; Sat, 7 May 2011 10:24:18 -0700 (PDT) In-Reply-To: <1304771263-10937-2-git-send-email-hauke@hauke-m.de> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> <1304771263-10937-2-git-send-email-hauke@hauke-m.de> From: Jonas Gorski Date: Sat, 7 May 2011 19:24:18 +0200 Message-ID: Subject: Re: [PATCH 1/5] ssb: Change fallback sprom to callback mechanism. To: Hauke Mehrtens Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, Michael Buesch , netdev@vger.kernel.org, Florian Fainelli Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29865 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk X-list: linux-mips Hi, just some small small spelling nit-picks: On 7 May 2011 14:27, Hauke Mehrtens wrote: > Some embedded devices like the Netgear WNDR3300 have two SSB based > cards without an own sprom on the pci bus. We have to provide two > different fallback sproms for these and this was not possible with the > old solution. In the bcm47xx architecture the sprom data is stored in > the nvram in the main flash storage. The architecture code will be able > to fill the sprom with the stored data based on the bus where the > device was found. > > The bcm63xx code should to the same thing as before, just using the new to -> do > API. > > CC: Michael Buesch > CC: netdev@vger.kernel.org > CC: Florian Fainelli > Signed-off-by: Hauke Mehrtens > --- >  arch/mips/bcm63xx/boards/board_bcm963xx.c |   16 ++++++++++++++-- >  drivers/ssb/pci.c                         |   16 +++++++++++----- >  drivers/ssb/sprom.c                       |   26 +++++++++++++++----------- >  drivers/ssb/ssb_private.h                 |    2 +- >  include/linux/ssb/ssb.h                   |    4 +++- >  5 files changed, 44 insertions(+), 20 deletions(-) > > diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c > index 8dba8cf..40b223b 100644 > --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c > +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c > @@ -643,6 +643,17 @@ static struct ssb_sprom bcm63xx_sprom = { >        .boardflags_lo          = 0x2848, >        .boardflags_hi          = 0x0000, >  }; > + > +int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) > +{ > +       if (bus->bustype == SSB_BUSTYPE_PCI) { > +               memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); > +               return 0; > +       } else { > +               printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); > +               return -EINVAL; > +       } > +} >  #endif > >  /* > @@ -793,8 +804,9 @@ void __init board_prom_init(void) >        if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { >                memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); >                memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); > -               if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0) > -                       printk(KERN_ERR "failed to register fallback SPROM\n"); > +               if (ssb_arch_register_fallback_sprom( > +                               &bcm63xx_get_fallback_sprom) < 0) > +                       printk(KERN_ERR PFX "failed to register fallback SPROM\n"); >        } >  #endif >  } > diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c > index 6f34963..34955d1 100644 > --- a/drivers/ssb/pci.c > +++ b/drivers/ssb/pci.c > @@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out, >  static int ssb_pci_sprom_get(struct ssb_bus *bus, >                             struct ssb_sprom *sprom) >  { > -       const struct ssb_sprom *fallback; >        int err; >        u16 *buf; > > @@ -707,10 +706,17 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus, >                if (err) { >                        /* All CRC attempts failed. >                         * Maybe there is no SPROM on the device? > -                        * If we have a fallback, use that. */ > -                       fallback = ssb_get_fallback_sprom(); > -                       if (fallback) { > -                               memcpy(sprom, fallback, sizeof(*sprom)); > +                        * Now we ask the arch code if there is some sprom > +                        * avaliable for this device in some other storage */ avaliable -> available > +                       err = ssb_fill_sprom_with_fallback(bus, sprom); > +                       if (err) { > +                               ssb_printk(KERN_WARNING PFX "WARNING: Using" > +                                          " fallback SPROM failed (err %d)\n", > +                                          err); > +                       } else { > +                               ssb_dprintk(KERN_DEBUG PFX "Using SPROM" > +                                           " revision %d provided by" > +                                           " platform.\n", sprom->revision); >                                err = 0; >                                goto out_free; >                        } > diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c > index 5f34d7a..20cd139 100644 > --- a/drivers/ssb/sprom.c > +++ b/drivers/ssb/sprom.c > @@ -17,7 +17,7 @@ >  #include > > > -static const struct ssb_sprom *fallback_sprom; > +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out); > > >  static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len, > @@ -145,13 +145,14 @@ out: >  } > >  /** > - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found. > + * ssb_arch_register_fallback_sprom - Registers a method providing a fallback > + * SPROM if no SPROM is found. >  * > - * @sprom: The SPROM data structure to register. > + * @sprom_callback: The callbcak function. callbcak -> callback >  * > - * With this function the architecture implementation may register a fallback > - * SPROM data structure. The fallback is only used for PCI based SSB devices, > - * where no valid SPROM can be found in the shadow registers. > + * With this function the architecture implementation may register a callback > + * handler which wills the SPROM data structure. The fallback is only used for wills -> fills > + * PCI based SSB devices, where no valid SPROM can be found in the shadow registers. >  * >  * This function is useful for weird architectures that have a half-assed SSB device >  * hardwired to their PCI bus. > @@ -163,18 +164,21 @@ out: >  * >  * This function is available for architecture code, only. So it is not exported. >  */ > -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom) > +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus, struct ssb_sprom *out)) >  { > -       if (fallback_sprom) > +       if (get_fallback_sprom) >                return -EEXIST; > -       fallback_sprom = sprom; > +       get_fallback_sprom = sprom_callback; > >        return 0; >  } > > -const struct ssb_sprom *ssb_get_fallback_sprom(void) > +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out) >  { > -       return fallback_sprom; > +       if (!get_fallback_sprom) > +               return -ENOENT; > + > +       return get_fallback_sprom(bus, out); >  } > >  /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ > diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h > index 0331139..1a32f58 100644 > --- a/drivers/ssb/ssb_private.h > +++ b/drivers/ssb/ssb_private.h > @@ -171,7 +171,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_bus *bus, >                             const char *buf, size_t count, >                             int (*sprom_check_crc)(const u16 *sprom, size_t size), >                             int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom)); > -extern const struct ssb_sprom *ssb_get_fallback_sprom(void); > +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out); > > >  /* core.c */ > diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h > index 9659eff..045f72a 100644 > --- a/include/linux/ssb/ssb.h > +++ b/include/linux/ssb/ssb.h > @@ -404,7 +404,9 @@ extern bool ssb_is_sprom_available(struct ssb_bus *bus); > >  /* Set a fallback SPROM. >  * See kdoc at the function definition for complete documentation. */ > -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom); > +extern int ssb_arch_register_fallback_sprom( > +               int (*sprom_callback)(struct ssb_bus *bus, > +               struct ssb_sprom *out)); > >  /* Suspend a SSB bus. >  * Call this from the parent bus suspend routine. */ > -- > 1.7.4.1 > > > From manuel.lauss@googlemail.com Sun May 8 10:42:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:42:36 +0200 (CEST) Received: from mail-ww0-f41.google.com ([74.125.82.41]:63956 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491003Ab1EHImc (ORCPT ); Sun, 8 May 2011 10:42:32 +0200 Received: by wwi18 with SMTP id 18so1552983wwi.0 for ; Sun, 08 May 2011 01:42:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=+n2pmT7iV0bbHsoUmKpmt7xyvo1Nyi34sZ2c03sWQEI=; b=MfQH89jCSOa0+PUeiPD5ckhK1v559Y5bRjVYglj35oAZRy6oLMcW75yOjTc+AXQkYh hgabmIcBZXRJXX0R9tLKBQa/3vImOU9Y15vR5ITs9w36QHCiEHREXVN0/M0ooC26cFA+ Vq9wXXnDBg4+syR766xvx1vElRXraYposEU4I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=NopKJs0dbY1zjvvZSABVbATPhejf2jVn+2HH4bdtjQdep8XHneQCFPM87wKJDHwJTC oBKqs6HDP6+nLCLvYTNqk+4pabRrSciGCy15XpJAczG1yoDDPMG4C/2oIZ6DQadYRUMe ftLuVUDwqxpwUL4cMMNyqYFqJTQpbLhB9YcpE= Received: by 10.227.164.79 with SMTP id d15mr5952083wby.62.1304844145916; Sun, 08 May 2011 01:42:25 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.24 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:25 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [RFC PATCH 0/9] Misc. Alchemy updates Date: Sun, 8 May 2011 10:42:11 +0200 Message-Id: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29866 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips This is a RFC for a series of patches I've been sitting on a while, it applies on top of latest linus-git (#3-#9 need to be applied in sequence). These two are older; they've been updated a bit: #1 improves stability of DB1200 board, #2 is a buildfix for mtx-1 with gpiolib=n; the gpio api has been updated with new functions, which this patch adds. the other patches mainly replace au_readl/au_writel with __raw_* functions, and try to reduce the register address clutter in the au1000.h header. This was basically a single large patch broken down into smaller ones, one for each ip block. #3 removes most of the irq-controller related register defines and updates irq.c to get rid of au_readl/writel. #4 converts IRQ PM to syscore_ops #5 converts DBDMA PM to syscore_ops #6 rewrite UART setup to use runtime CPU detection, and get rid of most of the uart base address defines #7 rewrite ethernet setup to use runtime CPU detection, and get rid of most of the redundant ethernet constants #8 updates the old au1000 dma driver: according to the databooks physical addresses should be used for source and destination; this also allows then to remove another bunch of redundant address constants. #9 changes the GPIO1/GPIO2 defines into offsets from their respective ip block base. I also had to fixup the mtx-1 wdt driver a bit since it modified the gpio2 block directly. All patches have been compile tested, and except for #7, #8 and the wdt parts of #9 also been run- and PM-tested on the DB1200. CCing Florian and Wolfgang: If you have time, please test #7-#9 on your MTX-1 and GPR boards! I'd like to know whether ethernet and the mtx-1 watchdog still work! Thanks! Please test/comment! Thank you, Manuel Lauss Manuel Lauss (9): MIPS: DB1200: Set Config[OD] for improved stability. MIPS: Alchemy: update inlinable GPIO API MIPS: Alchemy: irq code and constant cleanup MIPS: Alchemy: convert irq.c to syscore_ops. MIPS: Alchemy: convert dbdma.c to syscore_ops MIPS: Alchemy: rewrite UART setup and constants. MIPS: Alchemy: rewrite ethernet platform setup MIPS: Alchemy: cleanup DMA addresses MIPS: Alchemy: clean up GPIO registers and accessors arch/mips/alchemy/common/dbdma.c | 123 +++----- arch/mips/alchemy/common/dma.c | 46 ++-- arch/mips/alchemy/common/irq.c | 345 +++++++++++----------- arch/mips/alchemy/common/platform.c | 250 ++++++++++------ arch/mips/alchemy/common/setup.c | 4 +- arch/mips/alchemy/devboards/db1200/setup.c | 7 + arch/mips/alchemy/devboards/pb1000/board_setup.c | 2 +- arch/mips/alchemy/devboards/pb1500/board_setup.c | 2 +- arch/mips/alchemy/devboards/prom.c | 2 +- arch/mips/alchemy/gpr/board_setup.c | 14 +- arch/mips/alchemy/gpr/init.c | 2 +- arch/mips/alchemy/mtx-1/board_setup.c | 2 +- arch/mips/alchemy/mtx-1/init.c | 2 +- arch/mips/alchemy/xxs1500/board_setup.c | 11 +- arch/mips/alchemy/xxs1500/init.c | 2 +- arch/mips/boot/compressed/uart-alchemy.c | 2 +- arch/mips/include/asm/mach-au1x00/au1000.h | 334 +++++---------------- arch/mips/include/asm/mach-au1x00/au1000_dma.h | 4 - arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 8 - arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 122 +++++++-- drivers/watchdog/mtx-1_wdt.c | 21 +- 21 files changed, 615 insertions(+), 690 deletions(-) -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:42:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:43:03 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:41234 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491008Ab1EHImd (ORCPT ); Sun, 8 May 2011 10:42:33 +0200 Received: by wyb28 with SMTP id 28so4138962wyb.36 for ; Sun, 08 May 2011 01:42:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=TCRo4cPwpnvL/NMiAJn7zK1JcabL5AzxEx7rmSYyG7Y=; b=sxkry0xVubAq8uNwA6O1MUvW6t30X60Jp8OGaB1sUxLDXOu5LhWs8Oy3YZxTF5Y28y pCZUZKjEmd8F88c1R55p4MFONNY4kfT6mWwy/HBjVY/HF2w6RYBFGu+7IpL3LXKbzDdN rFp2mezTw2GaVV5wPRf5cXIh3Gfn3cIXQk4RE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Q1umOwqIzO0cqpjDR7h/ARd51y65uM7vnNw/POl8Rma39tAo2W5usQDBrFTBWAoGsZ fhMRgZxJuKpjhjdGYjgft42jJjZfMSBgZbNwt/+RpK9Bk4uydxv5U8I3LP/jLOC5tg2m MMXDQv+or6AK7YOkVUnpktiiIg/tpD7TqtsqE= Received: by 10.227.199.82 with SMTP id er18mr5852811wbb.63.1304844147570; Sun, 08 May 2011 01:42:27 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.26 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:27 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 2/9] MIPS: Alchemy: update inlinable GPIO API Date: Sun, 8 May 2011 10:42:13 +0200 Message-Id: <1304844140-3259-3-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29867 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips This fixes a build failure with gpio_keys and CONFIG_GPIOLIB=n (mtx1): CC drivers/input/keyboard/gpio_keys.o gpio_keys.c: In function 'gpio_keys_report_event': gpio_keys.c:325:2: error: implicit declaration of function 'gpio_get_value_cansleep' gpio_keys.c: In function 'gpio_keys_setup_key': gpio_keys.c:390:3: error: implicit declaration of function 'gpio_set_debounce' Also add stubs for the other new functions. Signed-off-by: Manuel Lauss --- Updated version of a patch I submitted a few times earlier. arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 51 +++++++++++++++++++++++ 1 files changed, 51 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 62d2f13..8f8c1c5 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -24,6 +24,7 @@ #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) +struct gpio; static inline int au1000_gpio1_to_irq(int gpio) { @@ -556,6 +557,16 @@ static inline void gpio_set_value(int gpio, int v) alchemy_gpio_set_value(gpio, v); } +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + static inline int gpio_is_valid(int gpio) { return alchemy_gpio_is_valid(gpio); @@ -581,10 +592,50 @@ static inline int gpio_request(unsigned gpio, const char *label) return 0; } +static inline int gpio_request_one(unsigned gpio, + unsigned long flags, const char *label) +{ + return 0; +} + +static inline int gpio_request_array(struct gpio *array, size_t num) +{ + return 0; +} + static inline void gpio_free(unsigned gpio) { } +static inline void gpio_free_array(struct gpio *array, size_t num) +{ +} + +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:43:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:43:26 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:36067 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491004Ab1EHImd (ORCPT ); Sun, 8 May 2011 10:42:33 +0200 Received: by wyb28 with SMTP id 28so4138955wyb.36 for ; Sun, 08 May 2011 01:42:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=J4RKxbs9181p595Cd4T/UEI8Iim0Rs4bzKCl7bY0Dg8=; b=ICRet7yKvanqqGRL9COADppiHXdrcqhiYwFbvus9l9AM7u5ZTmuOaK3h3Yj05GJZ1w ReT1tUz06wJdUau16vwr7YuhKqPCx7Zc/zKQQiXENBQzVuSAqqcOnzxesLJ7bOuxhzor kEEcWZN5p78jwhYQZBEHqmHNIl+IdPis2Xb/Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=ZSDIkOnU4GQPSaB/v1qygLqSE88vp5JwEYNc+n7DtvVEyfpRhR+m4NefylUaOguE9m GMnFKO5aJ+Ds6OVAzPRBGjE1ywpd3p8ZJPBaeU5/sL/MyzXEmUtyz/lCAjrBJrjrPSdk KGbugF4OFOpPSvjaU2Rhl+V1bHmvfXTWZBJhU= Received: by 10.227.100.219 with SMTP id z27mr3205318wbn.45.1304844146683; Sun, 08 May 2011 01:42:26 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.25 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:26 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 1/9] MIPS: DB1200: Set Config[OD] for improved stability. Date: Sun, 8 May 2011 10:42:12 +0200 Message-Id: <1304844140-3259-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29868 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Setting Config[OD] gets rid of a _LOT_ of spurious CPLD interrupts, but also decreases overall performance a bit. Signed-off-by: Manuel Lauss --- Resend of a patch I submitted earlier. V2: fix up issues pointed out by Sergei Shtylyov. arch/mips/alchemy/common/setup.c | 4 ++-- arch/mips/alchemy/devboards/db1200/setup.c | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 561e5da..1b887c8 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -52,8 +52,6 @@ void __init plat_mem_setup(void) /* this is faster than wasting cycles trying to approximate it */ preset_lpj = (est_freq >> 1) / HZ; - board_setup(); /* board specific setup */ - if (au1xxx_cpu_needs_config_od()) /* Various early Au1xx0 errata corrected by this */ set_c0_config(1 << 19); /* Set Config[OD] */ @@ -61,6 +59,8 @@ void __init plat_mem_setup(void) /* Clear to obtain best system bus performance */ clear_c0_config(1 << 19); /* Clear Config[OD] */ + board_setup(); /* board specific setup */ + /* IO/MEM resources. */ set_io_port_base(0); ioport_resource.start = IOPORT_RESOURCE_START; diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index 4a89800..1dac4f2 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -23,6 +23,13 @@ void __init board_setup(void) unsigned long freq0, clksrc, div, pfc; unsigned short whoami; + /* Set Config[OD] (disable overlapping bus transaction): + * This gets rid of a _lot_ of spurious interrupts (especially + * wrt. IDE); but incurs ~10% performance hit in some + * cpu-bound applications. + */ + set_c0_config(1 << 19); + bcsr_init(DB1200_BCSR_PHYS_ADDR, DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:43:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:43:50 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:41234 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491010Ab1EHImd (ORCPT ); Sun, 8 May 2011 10:42:33 +0200 Received: by mail-wy0-f177.google.com with SMTP id 28so4138962wyb.36 for ; Sun, 08 May 2011 01:42:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=o4SuCZWzOEyTaQAUzNl6H4ExwRTV/wQLgylKqds5SvA=; b=i9Ul0TL2h6fJwImVjHsIR3KEPHZF7xLHRFnJpo4G5S88a4igZaJra29n1I79k6YdVQ WY6aw9tpAnj88eHKf2+410DlWgIpqS4GjvduaLHlVqz5bDyi8p8xpubyt5cXip0zhhAw g4ZPJxdsu6exE3mBF/6XIFfp2pr5f0lht7zLE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=lUMSqM4EAteKHUDdDt3OvU5UFVz/byHGQuKU9kTENHOsgC/BvGYLiItgaUyslBc+9q E/VSnJpqGu2epQbF9SvL1aUr1EaESI+dLf89p+BXbyKq/djyQ48I3v1myrayHiYrKPJN HV3dT8YSP9Jy6i/xwBTVBLg5obbygZQNcJ7zg= Received: by 10.227.208.65 with SMTP id gb1mr5902370wbb.42.1304844153456; Sun, 08 May 2011 01:42:33 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.32 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:33 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 8/9] MIPS: Alchemy: cleanup DMA addresses Date: Sun, 8 May 2011 10:42:19 +0200 Message-Id: <1304844140-3259-9-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29869 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips According to the databooks, the Au1000 DMA engine must be programmed with the physical FIFO addresses. This patch does that; furthermore this opened the possibility to get rid of a lot of now unnecessary address defines. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/dma.c | 46 ++++++++++-------- arch/mips/alchemy/common/platform.c | 8 ++-- arch/mips/include/asm/mach-au1x00/au1000.h | 62 ++--------------------- arch/mips/include/asm/mach-au1x00/au1000_dma.h | 4 -- 4 files changed, 35 insertions(+), 85 deletions(-) diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c index d527887..347980e 100644 --- a/arch/mips/alchemy/common/dma.c +++ b/arch/mips/alchemy/common/dma.c @@ -58,6 +58,9 @@ * returned from request_dma. */ +/* DMA Channel register block spacing */ +#define DMA_CHANNEL_LEN 0x00000100 + DEFINE_SPINLOCK(au1000_dma_spin_lock); struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = { @@ -77,22 +80,23 @@ static const struct dma_dev { unsigned int fifo_addr; unsigned int dma_mode; } dma_dev_table[DMA_NUM_DEV] = { - {UART0_ADDR + UART_TX, 0}, - {UART0_ADDR + UART_RX, 0}, - {0, 0}, - {0, 0}, - {AC97C_DATA, DMA_DW16 }, /* coherent */ - {AC97C_DATA, DMA_DR | DMA_DW16 }, /* coherent */ - {UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC}, - {UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC}, - {USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC}, - {USBD_EP0WR, DMA_DW8 | DMA_NC}, - {USBD_EP2WR, DMA_DW8 | DMA_NC}, - {USBD_EP3WR, DMA_DW8 | DMA_NC}, - {USBD_EP4RD, DMA_DR | DMA_DW8 | DMA_NC}, - {USBD_EP5RD, DMA_DR | DMA_DW8 | DMA_NC}, - {I2S_DATA, DMA_DW32 | DMA_NC}, - {I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC} + { AU1000_UART0_PHYS_ADDR + 0x04, DMA_DW8 }, /* UART0_TX */ + { AU1000_UART0_PHYS_ADDR + 0x00, DMA_DW8 | DMA_DR }, /* UART0_RX */ + { 0, 0 }, /* DMA_REQ0 */ + { 0, 0 }, /* DMA_REQ1 */ + { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 }, /* AC97 TX c */ + { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */ + { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */ + { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */ + { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ + { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ + { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ + { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ + { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ + { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ + /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */ + { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */ + { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */ }; int au1000_dma_read_proc(char *buf, char **start, off_t fpos, @@ -123,10 +127,10 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos, /* Device FIFO addresses and default DMA modes - 2nd bank */ static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = { - { SD0_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */ - { SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 }, /* coherent */ - { SD1_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */ - { SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 } /* coherent */ + { AU1100_SD0_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */ + { AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }, /* coherent */ + { AU1100_SD1_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */ + { AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR } /* coherent */ }; void dump_au1000_dma_channel(unsigned int dmanr) @@ -202,7 +206,7 @@ int request_au1000_dma(int dev_id, const char *dev_str, } /* fill it in */ - chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN; + chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN; chan->dev_id = dev_id; chan->dev_str = dev_str; chan->fifo_addr = dev->fifo_addr; diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 541fff2..3b2c18b 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -283,8 +283,8 @@ extern struct au1xmmc_platform_data au1xmmc_platdata[2]; static struct resource au1200_mmc0_resources[] = { [0] = { - .start = SD0_PHYS_ADDR, - .end = SD0_PHYS_ADDR + 0x7ffff, + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR + 0xfff, .flags = IORESOURCE_MEM, }, [1] = { @@ -319,8 +319,8 @@ static struct platform_device au1200_mmc0_device = { #ifndef CONFIG_MIPS_DB1200 static struct resource au1200_mmc1_resources[] = { [0] = { - .start = SD1_PHYS_ADDR, - .end = SD1_PHYS_ADDR + 0x7ffff, + .start = AU1100_SD1_PHYS_ADDR, + .end = AU1100_SD1_PHYS_ADDR + 0xfff, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 415d287..2dfff4f 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -686,10 +686,15 @@ enum soc_au1200_ints { * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 */ +#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ +#define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ +#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ +#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ +#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ @@ -698,6 +703,7 @@ enum soc_au1200_ints { #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ +#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ @@ -707,19 +713,8 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1000 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 #define IRDA_PHYS_ADDR 0x10300000 -#define I2S_PHYS_ADDR 0x11000000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 #define SYS_PHYS_ADDR 0x11900000 @@ -733,19 +728,8 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1500 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 #define PCI_PHYS_ADDR 0x14005000 -#define I2S_PHYS_ADDR 0x11000000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define PCI_MEM_PHYS_ADDR 0x400000000ULL @@ -762,21 +746,8 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1100 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define SD0_PHYS_ADDR 0x10600000 -#define SD1_PHYS_ADDR 0x10680000 -#define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 #define IRDA_PHYS_ADDR 0x10300000 -#define I2S_PHYS_ADDR 0x11000000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 #define GPIO2_PHYS_ADDR 0x11700000 @@ -793,7 +764,6 @@ enum soc_au1200_ints { #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 #define USBH_PHYS_ADDR 0x14020000 -#define USBD_PHYS_ADDR 0x10200000 #define PCI_PHYS_ADDR 0x14005000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 @@ -824,8 +794,6 @@ enum soc_au1200_ints { #define SYS_PHYS_ADDR 0x11900000 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 -#define SD0_PHYS_ADDR 0x10600000 -#define SD1_PHYS_ADDR 0x10680000 #define LCD_PHYS_ADDR 0x15000000 #define SWCNT_PHYS_ADDR 0x1110010C #define MAEFE_PHYS_ADDR 0x14012000 @@ -867,9 +835,6 @@ enum soc_au1200_ints { /* Au1000 */ #ifdef CONFIG_SOC_AU1000 -#define UART0_ADDR 0xB1100000 -#define UART3_ADDR 0xB1400000 - #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017FFFC #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT @@ -878,9 +843,6 @@ enum soc_au1200_ints { /* Au1500 */ #ifdef CONFIG_SOC_AU1500 -#define UART0_ADDR 0xB1100000 -#define UART3_ADDR 0xB1400000 - #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017fffc #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT @@ -889,16 +851,12 @@ enum soc_au1200_ints { /* Au1100 */ #ifdef CONFIG_SOC_AU1100 -#define UART0_ADDR 0xB1100000 -#define UART3_ADDR 0xB1400000 - #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017FFFC #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT #endif /* CONFIG_SOC_AU1100 */ #ifdef CONFIG_SOC_AU1550 -#define UART0_ADDR 0xB1100000 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ #define USB_OHCI_LEN 0x00060000 @@ -909,8 +867,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1200 -#define UART0_ADDR 0xB1100000 - #define USB_UOC_BASE 0x14020020 #define USB_UOC_LEN 0x20 #define USB_OHCI_BASE 0x14020100 @@ -1534,12 +1490,6 @@ enum soc_au1200_ints { # define AC97C_RS (1 << 1) # define AC97C_CE (1 << 0) -/* Secure Digital (SD) Controller */ -#define SD0_XMIT_FIFO 0xB0600000 -#define SD0_RECV_FIFO 0xB0600004 -#define SD1_XMIT_FIFO 0xB0680000 -#define SD1_RECV_FIFO 0xB0680004 - #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) /* Au1500 PCI Controller */ #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h index c333b4e..59f5b55 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h +++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h @@ -37,10 +37,6 @@ #define NUM_AU1000_DMA_CHANNELS 8 -/* DMA Channel Base Addresses */ -#define DMA_CHANNEL_BASE 0xB4002000 -#define DMA_CHANNEL_LEN 0x00000100 - /* DMA Channel Register Offsets */ #define DMA_MODE_SET 0x00000000 #define DMA_MODE_READ DMA_MODE_SET -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:44:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:44:17 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:36067 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491022Ab1EHIme (ORCPT ); Sun, 8 May 2011 10:42:34 +0200 Received: by mail-wy0-f177.google.com with SMTP id 28so4138955wyb.36 for ; Sun, 08 May 2011 01:42:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=OAi5A/OK1Z5M6JV8fC2ZaQQ64ZO9kqWZFTET0DOEbMc=; b=f1Dp4NUMzR31GnPKeBlA29pPyQuOGnmqsZnSVQsoRZsl9qahS4KQXsScsyD9A4VkI2 bG0wT9kH9RkdypGMMYAZ+Q4hwx+YbsnIfSx+e3R3MomXjrOWCnbt5duttyyCd5jGv7Il wpfU23GNF+dkQJ/DqFgbVpdLd4Bm5TF2I8Mp0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=dkajwmXwLUAu57d9JLqqjU8t8Ls0+/IPN+pwy2lYfieepnLHEoew0ahn9uKSwwqwyq OeggVsljxny+gqx5XMMFJhEpw2Zq/ul7ln8OUNzWnKD/U+f1Y3lFZ6rDMLPKEyLxkj10 OB303uWSpPzJItnGne0odL2fEsL0FQhhFW4Y8= Received: by 10.216.174.65 with SMTP id w43mr1387123wel.95.1304844154575; Sun, 08 May 2011 01:42:34 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.33 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:34 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 9/9] MIPS: Alchemy: clean up GPIO registers and accessors Date: Sun, 8 May 2011 10:42:20 +0200 Message-Id: <1304844140-3259-10-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29870 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips remove au_readl/au_writel, remove the predefined GPIO1/2 KSEG1 register addresses and fix the fallout in all boards and drivers. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/pb1000/board_setup.c | 2 +- arch/mips/alchemy/devboards/pb1500/board_setup.c | 2 +- arch/mips/alchemy/mtx-1/board_setup.c | 2 +- arch/mips/include/asm/mach-au1x00/au1000.h | 27 +-------- arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 71 +++++++++++++++------- drivers/watchdog/mtx-1_wdt.c | 21 ++++--- 6 files changed, 66 insertions(+), 59 deletions(-) diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index 2d85c4b..e64fdcb 100644 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c @@ -65,7 +65,7 @@ void __init board_setup(void) /* Set AUX clock to 12 MHz * 8 = 96 MHz */ au_writel(8, SYS_AUXPLL); - au_writel(0, SYS_PINSTATERD); + alchemy_gpio1_input_enable(); udelay(100); #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index 83f4621..3b4fa32 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c @@ -56,7 +56,7 @@ void __init board_setup(void) sys_clksrc = sys_freqctrl = pin_func = 0; /* Set AUX clock to 12 MHz * 8 = 96 MHz */ au_writel(8, SYS_AUXPLL); - au_writel(0, SYS_PINSTATERD); + alchemy_gpio1_input_enable(); udelay(100); /* GPIO201 is input for PCMCIA card detect */ diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index cf436ab..3ae984c 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -87,7 +87,7 @@ void __init board_setup(void) au_writel(SYS_PF_NI2, SYS_PINFUNC); /* Initialize GPIO */ - au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); + au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR); alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 2dfff4f..f260ebe 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -702,7 +702,9 @@ enum soc_au1200_ints { #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ +#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ +#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ @@ -717,7 +719,6 @@ enum soc_au1200_ints { #define IRDA_PHYS_ADDR 0x10300000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 -#define SYS_PHYS_ADDR 0x11900000 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL @@ -730,8 +731,6 @@ enum soc_au1200_ints { #define STATIC_MEM_PHYS_ADDR 0x14001000 #define USBH_PHYS_ADDR 0x10100000 #define PCI_PHYS_ADDR 0x14005000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 #define PCI_MEM_PHYS_ADDR 0x400000000ULL #define PCI_IO_PHYS_ADDR 0x500000000ULL #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL @@ -750,8 +749,6 @@ enum soc_au1200_ints { #define IRDA_PHYS_ADDR 0x10300000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 #define LCD_PHYS_ADDR 0x15000000 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL @@ -765,8 +762,6 @@ enum soc_au1200_ints { #define STATIC_MEM_PHYS_ADDR 0x14001000 #define USBH_PHYS_ADDR 0x14020000 #define PCI_PHYS_ADDR 0x14005000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 #define PE_PHYS_ADDR 0x14008000 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 @@ -790,8 +785,6 @@ enum soc_au1200_ints { #define CIM_PHYS_ADDR 0x14004000 #define USBM_PHYS_ADDR 0x14020000 #define USBH_PHYS_ADDR 0x14020100 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 #define LCD_PHYS_ADDR 0x15000000 @@ -1359,22 +1352,6 @@ enum soc_au1200_ints { #define SYS_PINFUNC_S1B (1 << 2) #endif -#define SYS_TRIOUTRD 0xB1900100 -#define SYS_TRIOUTCLR 0xB1900100 -#define SYS_OUTPUTRD 0xB1900108 -#define SYS_OUTPUTSET 0xB1900108 -#define SYS_OUTPUTCLR 0xB190010C -#define SYS_PINSTATERD 0xB1900110 -#define SYS_PININPUTEN 0xB1900110 - -/* GPIO2, Au1500, Au1550 only */ -#define GPIO2_BASE 0xB1700000 -#define GPIO2_DIR (GPIO2_BASE + 0) -#define GPIO2_OUTPUT (GPIO2_BASE + 8) -#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) -#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) -#define GPIO2_ENABLE (GPIO2_BASE + 0x14) - /* Power Management */ #define SYS_SCRATCH0 0xB1900018 #define SYS_SCRATCH1 0xB190001C diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 8f8c1c5..1f41a52 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -24,6 +24,22 @@ #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) +/* GPIO1 registers within SYS_ area */ +#define SYS_TRIOUTRD 0x100 +#define SYS_TRIOUTCLR 0x100 +#define SYS_OUTPUTRD 0x108 +#define SYS_OUTPUTSET 0x108 +#define SYS_OUTPUTCLR 0x10C +#define SYS_PINSTATERD 0x110 +#define SYS_PININPUTEN 0x110 + +/* register offsets within GPIO2 block */ +#define GPIO2_DIR 0x00 +#define GPIO2_OUTPUT 0x08 +#define GPIO2_PINSTATE 0x0C +#define GPIO2_INTENABLE 0x10 +#define GPIO2_ENABLE 0x14 + struct gpio; static inline int au1000_gpio1_to_irq(int gpio) @@ -201,23 +217,26 @@ static inline int au1200_irq_to_gpio(int irq) */ static inline void alchemy_gpio1_set_value(int gpio, int v) { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; - au_writel(mask, r); - au_sync(); + __raw_writel(mask, base + r); + wmb(); } static inline int alchemy_gpio1_get_value(int gpio) { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); - return au_readl(SYS_PINSTATERD) & mask; + return __raw_readl(base + SYS_PINSTATERD) & mask; } static inline int alchemy_gpio1_direction_input(int gpio) { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); - au_writel(mask, SYS_TRIOUTCLR); - au_sync(); + __raw_writel(mask, base + SYS_TRIOUTCLR); + wmb(); return 0; } @@ -258,27 +277,31 @@ static inline int alchemy_gpio1_to_irq(int gpio) */ static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); - unsigned long d = au_readl(GPIO2_DIR); + unsigned long d = __raw_readl(base + GPIO2_DIR); + if (to_out) d |= mask; else d &= ~mask; - au_writel(d, GPIO2_DIR); - au_sync(); + __raw_writel(d, base + GPIO2_DIR); + wmb(); } static inline void alchemy_gpio2_set_value(int gpio, int v) { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); unsigned long mask; mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); - au_writel(mask, GPIO2_OUTPUT); - au_sync(); + __raw_writel(mask, base + GPIO2_OUTPUT); + wmb(); } static inline int alchemy_gpio2_get_value(int gpio) { - return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); } static inline int alchemy_gpio2_direction_input(int gpio) @@ -330,21 +353,23 @@ static inline int alchemy_gpio2_to_irq(int gpio) */ static inline void alchemy_gpio1_input_enable(void) { - au_writel(0, SYS_PININPUTEN); /* the write op is key */ - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); + __raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */ + wmb(); } /* GPIO2 shared interrupts and control */ static inline void __alchemy_gpio2_mod_int(int gpio2, int en) { - unsigned long r = au_readl(GPIO2_INTENABLE); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + unsigned long r = __raw_readl(base + GPIO2_INTENABLE); if (en) r |= 1 << gpio2; else r &= ~(1 << gpio2); - au_writel(r, GPIO2_INTENABLE); - au_sync(); + __raw_writel(r, base + GPIO2_INTENABLE); + wmb(); } /** @@ -419,10 +444,11 @@ static inline void alchemy_gpio2_disable_int(int gpio2) */ static inline void alchemy_gpio2_enable(void) { - au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */ - au_sync(); - au_writel(1, GPIO2_ENABLE); /* clock enabled */ - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + __raw_writel(3, base + GPIO2_ENABLE); /* reset, clock enabled */ + wmb(); + __raw_writel(1, base + GPIO2_ENABLE); /* clock enabled */ + wmb(); } /** @@ -432,8 +458,9 @@ static inline void alchemy_gpio2_enable(void) */ static inline void alchemy_gpio2_disable(void) { - au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */ - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + __raw_writel(2, base + GPIO2_ENABLE); /* reset, clock disabled */ + wmb(); } /**********************************************************************/ diff --git a/drivers/watchdog/mtx-1_wdt.c b/drivers/watchdog/mtx-1_wdt.c index 5ec5ac1..1479dc4 100644 --- a/drivers/watchdog/mtx-1_wdt.c +++ b/drivers/watchdog/mtx-1_wdt.c @@ -66,6 +66,7 @@ static struct { int default_ticks; unsigned long inuse; unsigned gpio; + int gstate; } mtx1_wdt_device; static void mtx1_wdt_trigger(unsigned long unused) @@ -75,13 +76,13 @@ static void mtx1_wdt_trigger(unsigned long unused) spin_lock(&mtx1_wdt_device.lock); if (mtx1_wdt_device.running) ticks--; - /* - * toggle GPIO2_15 - */ - tmp = au_readl(GPIO2_DIR); - tmp = (tmp & ~(1 << mtx1_wdt_device.gpio)) | - ((~tmp) & (1 << mtx1_wdt_device.gpio)); - au_writel(tmp, GPIO2_DIR); + + /* toggle wdt gpio */ + mtx1_wdt_device.gstate = ~mtx1_wdt_device.gstate; + if (mtx1_wdt_device.gstate) + gpio_direction_output(mtx1_wdt_device.gpio, 1); + else + gpio_direction_input(mtx1_wdt_device.gpio); if (mtx1_wdt_device.queue && ticks) mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); @@ -103,7 +104,8 @@ static void mtx1_wdt_start(void) spin_lock_irqsave(&mtx1_wdt_device.lock, flags); if (!mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 1; - gpio_set_value(mtx1_wdt_device.gpio, 1); + mtx1_wdt_device.gstate = 1; + gpio_direction_output(mtx1_wdt_device.gpio, 1); mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); } mtx1_wdt_device.running++; @@ -117,7 +119,8 @@ static int mtx1_wdt_stop(void) spin_lock_irqsave(&mtx1_wdt_device.lock, flags); if (mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 0; - gpio_set_value(mtx1_wdt_device.gpio, 0); + mtx1_wdt_device.gstate = 0; + gpio_direction_output(mtx1_wdt_device.gpio, 0); } ticks = mtx1_wdt_device.default_ticks; spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags); -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:44:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:44:42 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:49933 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491037Ab1EHImf (ORCPT ); Sun, 8 May 2011 10:42:35 +0200 Received: by wwb17 with SMTP id 17so3946490wwb.24 for ; Sun, 08 May 2011 01:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=t+7IHzt2g7AEZV7M1GxKA4VwDcTC6m+aPRMTNRAv8u0=; b=IW4aStJ1Ws/+WOg0funAq9NOC85nrIfxqq1LHuOEpyoWWMakyRoTZAg0rj71M/vUHs Z3y2zN8ffUP7RZ76TuH/4GnHs1IyheHJZqy/Elhrib8jc1r5/H0rr+6eTLDRGCJxGByU 5v8eE1n5RnLDNOi6YKZl4Brb2V18mjzuE/oz0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=REYfU149ushQ8QfG+ZYN/fiXFPiYhbHLVNDcHNyymn5E1RaOzsH++acNWKNqkIXwLK FgasM21jyOvhN6JKSB2QUuis755iPsvyWlKfwtcF59ojsSaVDHcsTVLIhfzFtxNYRcXG CNEePQv8PBkKQmiU+07tO5NN876bTAxuoqljE= Received: by 10.227.201.13 with SMTP id ey13mr4182662wbb.57.1304844149504; Sun, 08 May 2011 01:42:29 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.28 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:29 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 4/9] MIPS: Alchemy: convert irq.c to syscore_ops. Date: Sun, 8 May 2011 10:42:15 +0200 Message-Id: <1304844140-3259-5-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29871 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips convert the PM sysdev to use syscore_ops instead. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/irq.c | 101 ++++++++++++++++------------------------ 1 files changed, 41 insertions(+), 60 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index b72e128..8b60ba0 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include @@ -585,81 +585,62 @@ void __init arch_init_irq(void) } } -struct alchemy_ic_sysdev { - struct sys_device sysdev; - void __iomem *base; - unsigned long pmdata[7]; -}; - -static int alchemy_ic_suspend(struct sys_device *dev, pm_message_t state) -{ - struct alchemy_ic_sysdev *icdev = - container_of(dev, struct alchemy_ic_sysdev, sysdev); - icdev->pmdata[0] = __raw_readl(icdev->base + IC_CFG0RD); - icdev->pmdata[1] = __raw_readl(icdev->base + IC_CFG1RD); - icdev->pmdata[2] = __raw_readl(icdev->base + IC_CFG2RD); - icdev->pmdata[3] = __raw_readl(icdev->base + IC_SRCRD); - icdev->pmdata[4] = __raw_readl(icdev->base + IC_ASSIGNRD); - icdev->pmdata[5] = __raw_readl(icdev->base + IC_WAKERD); - icdev->pmdata[6] = __raw_readl(icdev->base + IC_MASKRD); +static unsigned long alchemy_ic_pmdata[7 * 2]; - return 0; +static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d) +{ + d[0] = __raw_readl(base + IC_CFG0RD); + d[1] = __raw_readl(base + IC_CFG1RD); + d[2] = __raw_readl(base + IC_CFG2RD); + d[3] = __raw_readl(base + IC_SRCRD); + d[4] = __raw_readl(base + IC_ASSIGNRD); + d[5] = __raw_readl(base + IC_WAKERD); + d[6] = __raw_readl(base + IC_MASKRD); + ic_init(base); /* shut it up too while at it */ } -static int alchemy_ic_resume(struct sys_device *dev) +static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) { - struct alchemy_ic_sysdev *icdev = - container_of(dev, struct alchemy_ic_sysdev, sysdev); - - ic_init(icdev->base); - - __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET); - __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET); - __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET); - __raw_writel(icdev->pmdata[3], icdev->base + IC_SRCSET); - __raw_writel(icdev->pmdata[4], icdev->base + IC_ASSIGNSET); - __raw_writel(icdev->pmdata[5], icdev->base + IC_WAKESET); + ic_init(base); + + __raw_writel(d[0], base + IC_CFG0SET); + __raw_writel(d[1], base + IC_CFG1SET); + __raw_writel(d[2], base + IC_CFG2SET); + __raw_writel(d[3], base + IC_SRCSET); + __raw_writel(d[4], base + IC_ASSIGNSET); + __raw_writel(d[5], base + IC_WAKESET); wmb(); - __raw_writel(icdev->pmdata[6], icdev->base + IC_MASKSET); + __raw_writel(d[6], base + IC_MASKSET); wmb(); +} +static int alchemy_ic_suspend(void) +{ + alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), + alchemy_ic_pmdata); + alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), + &alchemy_ic_pmdata[7]); return 0; } -static struct sysdev_class alchemy_ic_sysdev_class = { - .name = "ic", +static void alchemy_ic_resume(void) +{ + alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), + &alchemy_ic_pmdata[7]); + alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), + alchemy_ic_pmdata); +} + +static struct syscore_ops alchemy_ic_syscore_ops = { .suspend = alchemy_ic_suspend, .resume = alchemy_ic_resume, }; -static int __init alchemy_ic_sysdev_init(void) +static int __init alchemy_ic_pm_init(void) { - struct alchemy_ic_sysdev *icdev; - unsigned long icbase[2] = { AU1000_IC0_PHYS_ADDR, AU1000_IC1_PHYS_ADDR }; - int err, i; - - err = sysdev_class_register(&alchemy_ic_sysdev_class); - if (err) - return err; - - for (i = 0; i < 2; i++) { - icdev = kzalloc(sizeof(struct alchemy_ic_sysdev), GFP_KERNEL); - if (!icdev) - return -ENOMEM; - - icdev->base = ioremap(icbase[i], 0x1000); - - icdev->sysdev.id = i; - icdev->sysdev.cls = &alchemy_ic_sysdev_class; - err = sysdev_register(&icdev->sysdev); - if (err) { - kfree(icdev); - return err; - } - } - + register_syscore_ops(&alchemy_ic_syscore_ops); return 0; } -device_initcall(alchemy_ic_sysdev_init); +device_initcall(alchemy_ic_pm_init); -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:45:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:45:07 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:49543 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491045Ab1EHImg (ORCPT ); Sun, 8 May 2011 10:42:36 +0200 Received: by wwb17 with SMTP id 17so3946498wwb.24 for ; Sun, 08 May 2011 01:42:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=kJeqd/+DSzUIXKRsvB/e3HALQssnFtetvXhte3QM8/s=; b=x8Zes5pJ79QHdqZT+meGyhl4Bm95GS578Cze2JJ0A0PmUrHY/96YV2h73Eb+a5DLoh fYKgywDzauf+fNRFLM2mOc/PTi+4BKXRH38DQQrMT/wXVkYxTTP3k/7cOd9/MlAworuA jRJbmdpL8BNjl/8WqvdF1jmxa9IfvzOfilfrE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=ShH386dnHbsNH3Eg2foLY3Sl4rgEUx8785kNlu+cNfMJTRNEWKF9/kDfbk8/I9eDL4 l9BHSoBElWjVOBcupCRBWHcsu9JkJgUM5QExPoc1D3Vu0cS/LMn/TzJVlKHG/vc1/s8t uZqPw102IAeA2xkpe2Qs+w+aoMtcoNgQ3jOR4= Received: by 10.216.237.155 with SMTP id y27mr1384159weq.82.1304844150390; Sun, 08 May 2011 01:42:30 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.29 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:30 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 5/9] MIPS: Alchemy: convert dbdma.c to syscore_ops Date: Sun, 8 May 2011 10:42:16 +0200 Message-Id: <1304844140-3259-6-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29872 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips convert the PM sysdev to syscore_ops and clean up the ddma addresses a bit. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/dbdma.c | 123 ++++++++-------------- arch/mips/include/asm/mach-au1x00/au1000.h | 4 +- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 8 -- 3 files changed, 47 insertions(+), 88 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index ca0506a..3a5abb5 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include @@ -58,7 +58,8 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); /* I couldn't find a macro that did this... */ #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) -static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; +static dbdma_global_t *dbdma_gptr = + (dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR); static int dbdma_initialized; static dbdev_tab_t dbdev_tab[] = { @@ -299,7 +300,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, if (ctp != NULL) { memset(ctp, 0, sizeof(chan_tab_t)); ctp->chan_index = chan = i; - dcp = DDMA_CHANNEL_BASE; + dcp = KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR); dcp += (0x0100 * chan); ctp->chan_ptr = (au1x_dma_chan_t *)dcp; cp = (au1x_dma_chan_t *)dcp; @@ -958,105 +959,75 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) } -struct alchemy_dbdma_sysdev { - struct sys_device sysdev; - u32 pm_regs[NUM_DBDMA_CHANS + 1][6]; -}; +static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6]; -static int alchemy_dbdma_suspend(struct sys_device *dev, - pm_message_t state) +static int alchemy_dbdma_suspend(void) { - struct alchemy_dbdma_sysdev *sdev = - container_of(dev, struct alchemy_dbdma_sysdev, sysdev); int i; - u32 addr; + void __iomem *addr; - addr = DDMA_GLOBAL_BASE; - sdev->pm_regs[0][0] = au_readl(addr + 0x00); - sdev->pm_regs[0][1] = au_readl(addr + 0x04); - sdev->pm_regs[0][2] = au_readl(addr + 0x08); - sdev->pm_regs[0][3] = au_readl(addr + 0x0c); + addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR); + alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00); + alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04); + alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08); + alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c); /* save channel configurations */ - for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { - sdev->pm_regs[i][0] = au_readl(addr + 0x00); - sdev->pm_regs[i][1] = au_readl(addr + 0x04); - sdev->pm_regs[i][2] = au_readl(addr + 0x08); - sdev->pm_regs[i][3] = au_readl(addr + 0x0c); - sdev->pm_regs[i][4] = au_readl(addr + 0x10); - sdev->pm_regs[i][5] = au_readl(addr + 0x14); + addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR); + for (i = 1; i <= NUM_DBDMA_CHANS; i++) { + alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00); + alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04); + alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08); + alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c); + alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10); + alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14); /* halt channel */ - au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00); - au_sync(); - while (!(au_readl(addr + 0x14) & 1)) - au_sync(); + __raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00); + wmb(); + while (!(__raw_readl(addr + 0x14) & 1)) + wmb(); addr += 0x100; /* next channel base */ } /* disable channel interrupts */ - au_writel(0, DDMA_GLOBAL_BASE + 0x0c); - au_sync(); + addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR); + __raw_writel(0, addr + 0x0c); + wmb(); return 0; } -static int alchemy_dbdma_resume(struct sys_device *dev) +static void alchemy_dbdma_resume(void) { - struct alchemy_dbdma_sysdev *sdev = - container_of(dev, struct alchemy_dbdma_sysdev, sysdev); int i; - u32 addr; + void __iomem *addr; - addr = DDMA_GLOBAL_BASE; - au_writel(sdev->pm_regs[0][0], addr + 0x00); - au_writel(sdev->pm_regs[0][1], addr + 0x04); - au_writel(sdev->pm_regs[0][2], addr + 0x08); - au_writel(sdev->pm_regs[0][3], addr + 0x0c); + addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR); + __raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00); + __raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04); + __raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08); + __raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c); /* restore channel configurations */ - for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { - au_writel(sdev->pm_regs[i][0], addr + 0x00); - au_writel(sdev->pm_regs[i][1], addr + 0x04); - au_writel(sdev->pm_regs[i][2], addr + 0x08); - au_writel(sdev->pm_regs[i][3], addr + 0x0c); - au_writel(sdev->pm_regs[i][4], addr + 0x10); - au_writel(sdev->pm_regs[i][5], addr + 0x14); - au_sync(); + addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR); + for (i = 1; i <= NUM_DBDMA_CHANS; i++) { + __raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00); + __raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04); + __raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08); + __raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c); + __raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10); + __raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14); + wmb(); addr += 0x100; /* next channel base */ } - - return 0; } -static struct sysdev_class alchemy_dbdma_sysdev_class = { - .name = "dbdma", +static struct syscore_ops alchemy_dbdma_syscore_ops = { .suspend = alchemy_dbdma_suspend, .resume = alchemy_dbdma_resume, }; -static int __init alchemy_dbdma_sysdev_init(void) -{ - struct alchemy_dbdma_sysdev *sdev; - int ret; - - ret = sysdev_class_register(&alchemy_dbdma_sysdev_class); - if (ret) - return ret; - - sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL); - if (!sdev) - return -ENOMEM; - - sdev->sysdev.id = -1; - sdev->sysdev.cls = &alchemy_dbdma_sysdev_class; - ret = sysdev_register(&sdev->sysdev); - if (ret) - kfree(sdev); - - return ret; -} - static int __init au1xxx_dbdma_init(void) { int irq_nr, ret; @@ -1084,11 +1055,7 @@ static int __init au1xxx_dbdma_init(void) else { dbdma_initialized = 1; printk(KERN_INFO "Alchemy DBDMA initialized\n"); - ret = alchemy_dbdma_sysdev_init(); - if (ret) { - printk(KERN_ERR "DBDMA PM init failed\n"); - ret = 0; - } + register_syscore_ops(&alchemy_dbdma_syscore_ops); } return ret; diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 66cfcdc..eb8f103 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -635,6 +635,8 @@ enum soc_au1200_ints { #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ +#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ +#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ #ifdef CONFIG_SOC_AU1000 @@ -761,7 +763,6 @@ enum soc_au1200_ints { #define UART3_PHYS_ADDR 0x11400000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 -#define DDMA_PHYS_ADDR 0x14002000 #define PE_PHYS_ADDR 0x14008000 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 @@ -789,7 +790,6 @@ enum soc_au1200_ints { #define UART1_PHYS_ADDR 0x11200000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 -#define DDMA_PHYS_ADDR 0x14002000 #define PSC0_PHYS_ADDR 0x11A00000 #define PSC1_PHYS_ADDR 0x11B00000 #define SD0_PHYS_ADDR 0x10600000 diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index c8a553a3..2fdacfe 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -37,14 +37,6 @@ #ifndef _LANGUAGE_ASSEMBLY -/* - * The DMA base addresses. - * The channels are every 256 bytes (0x0100) from the channel 0 base. - * Interrupt status/enable is bits 15:0 for channels 15 to zero. - */ -#define DDMA_GLOBAL_BASE 0xb4003000 -#define DDMA_CHANNEL_BASE 0xb4002000 - typedef volatile struct dbdma_global { u32 ddma_config; u32 ddma_intstat; -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:45:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:45:28 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:44184 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491141Ab1EHImg (ORCPT ); Sun, 8 May 2011 10:42:36 +0200 Received: by wyb28 with SMTP id 28so4138987wyb.36 for ; Sun, 08 May 2011 01:42:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=r+LfCDSKOmFBbid0W72U3RwaSD68VVlmguuuNUX9I3I=; b=iE31supcqQeTiDfWdKLnAMhcRtyg2l7M146YMz2PGz0Wh8hWgTCTk3KBPXjwzQXvyJ iVC4KFznXdd6rqMvdH/E6ZguD5pWoOztjIR1zVNZNNGiXHBwgj7yq8od/N5hWZAhD/wV mBWoVtqHcSBZsdL3omHv4xVZFUKhF8Wu7VtwU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=OIrHYNjb+SjLHfS3R7W8nRJT9b0S+RWqWk6bM7I9wyuh/9W6FNtRgq2PzhfDNl2Cyt bI31Nmd3K6waT9I+tR24AKLaI0guREO9I1hgnkT4TFCv8iNFa4cyUBv73sIw+lMyi1gT LteaU8gm7QMNVush3o1naQ2VtFE4VzRGoE2YA= Received: by 10.227.10.141 with SMTP id p13mr1243wbp.75.1304844151460; Sun, 08 May 2011 01:42:31 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.30 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:31 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 6/9] MIPS: Alchemy: rewrite UART setup and constants. Date: Sun, 8 May 2011 10:42:17 +0200 Message-Id: <1304844140-3259-7-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29873 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Detect CPU type at runtime and setup uarts accordingly; also clean up the uart base address mess in the process as far as possible. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 93 +++++++++++++++------------- arch/mips/alchemy/devboards/prom.c | 2 +- arch/mips/alchemy/gpr/board_setup.c | 14 +--- arch/mips/alchemy/gpr/init.c | 2 +- arch/mips/alchemy/mtx-1/init.c | 2 +- arch/mips/alchemy/xxs1500/board_setup.c | 11 +-- arch/mips/alchemy/xxs1500/init.c | 2 +- arch/mips/boot/compressed/uart-alchemy.c | 2 +- arch/mips/include/asm/mach-au1x00/au1000.h | 57 +++++++++++++---- 9 files changed, 107 insertions(+), 78 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 9e7814d..36489fb 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -30,21 +30,12 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, #ifdef CONFIG_SERIAL_8250 switch (state) { case 0: - if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) { - /* power-on sequence as suggested in the databooks */ - __raw_writel(0, port->membase + UART_MOD_CNTRL); - wmb(); - __raw_writel(1, port->membase + UART_MOD_CNTRL); - wmb(); - } - __raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */ - wmb(); + alchemy_uart_enable(CPHYSADDR(port->membase)); serial8250_do_pm(port, state, old_state); break; case 3: /* power off */ serial8250_do_pm(port, state, old_state); - __raw_writel(0, port->membase + UART_MOD_CNTRL); - wmb(); + alchemy_uart_disable(CPHYSADDR(port->membase)); break; default: serial8250_do_pm(port, state, old_state); @@ -65,38 +56,60 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, .pm = alchemy_8250_pm, \ } -static struct plat_serial8250_port au1x00_uart_data[] = { -#if defined(CONFIG_SOC_AU1000) - PORT(UART0_PHYS_ADDR, AU1000_UART0_INT), - PORT(UART1_PHYS_ADDR, AU1000_UART1_INT), - PORT(UART2_PHYS_ADDR, AU1000_UART2_INT), - PORT(UART3_PHYS_ADDR, AU1000_UART3_INT), -#elif defined(CONFIG_SOC_AU1500) - PORT(UART0_PHYS_ADDR, AU1500_UART0_INT), - PORT(UART3_PHYS_ADDR, AU1500_UART3_INT), -#elif defined(CONFIG_SOC_AU1100) - PORT(UART0_PHYS_ADDR, AU1100_UART0_INT), - PORT(UART1_PHYS_ADDR, AU1100_UART1_INT), - PORT(UART3_PHYS_ADDR, AU1100_UART3_INT), -#elif defined(CONFIG_SOC_AU1550) - PORT(UART0_PHYS_ADDR, AU1550_UART0_INT), - PORT(UART1_PHYS_ADDR, AU1550_UART1_INT), - PORT(UART3_PHYS_ADDR, AU1550_UART3_INT), -#elif defined(CONFIG_SOC_AU1200) - PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), - PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), -#endif - { }, +static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = { + [ALCHEMY_CPU_AU1000] = { + PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT), + PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT), + PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT), + PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT), + }, + [ALCHEMY_CPU_AU1500] = { + PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT), + PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT), + }, + [ALCHEMY_CPU_AU1100] = { + PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT), + PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT), + PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT), + }, + [ALCHEMY_CPU_AU1550] = { + PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT), + PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT), + PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT), + }, + [ALCHEMY_CPU_AU1200] = { + PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), + PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), + }, }; static struct platform_device au1xx0_uart_device = { .name = "serial8250", .id = PLAT8250_DEV_AU1X00, - .dev = { - .platform_data = au1x00_uart_data, - }, }; +static void __init alchemy_setup_uarts(int ctype) +{ + unsigned int uartclk = get_au1x00_uart_baud_base() * 16; + int s = sizeof(struct plat_serial8250_port); + int c = alchemy_get_uarts(ctype); + struct plat_serial8250_port *ports; + + ports = kzalloc(s * (c + 1), GFP_KERNEL); + if (!ports) { + printk(KERN_INFO "Alchemy: no memory for UART data\n"); + return; + } + memcpy(ports, au1x00_uart_data[ctype], s * c); + au1xx0_uart_device.dev.platform_data = ports; + + /* Fill up uartclk. */ + for (s = 0; s < c; s++) + ports[s].uartclk = uartclk; + if (platform_device_register(&au1xx0_uart_device)) + printk(KERN_INFO "Alchemy: failed to register UARTs\n"); +} + /* OHCI (USB full speed host controller) */ static struct resource au1xxx_usb_ohci_resources[] = { [0] = { @@ -442,7 +455,6 @@ void __init au1xxx_override_eth_cfg(unsigned int port, } static struct platform_device *au1xxx_platform_devices[] __initdata = { - &au1xx0_uart_device, &au1xxx_usb_ohci_device, #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, @@ -465,13 +477,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { static int __init au1xxx_platform_init(void) { - unsigned int uartclk = get_au1x00_uart_baud_base() * 16; - int err, i; + int err, i, ctype = alchemy_get_cputype(); unsigned char ethaddr[6]; - /* Fill up uartclk. */ - for (i = 0; au1x00_uart_data[i].flags; i++) - au1x00_uart_data[i].uartclk = uartclk; + alchemy_setup_uarts(ctype); /* use firmware-provided mac addr if available and necessary */ i = prom_get_ethernet_addr(ethaddr); diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index baeb213..e5306b5 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -62,5 +62,5 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { - alchemy_uart_putchar(UART0_PHYS_ADDR, c); + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); } diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c index ad2e3f1..5f8f069 100644 --- a/arch/mips/alchemy/gpr/board_setup.c +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -36,9 +36,6 @@ #include -#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR) -#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR) - char irq_tab_alchemy[][5] __initdata = { [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, }; @@ -67,18 +64,15 @@ static void gpr_power_off(void) void __init board_setup(void) { - printk(KERN_INFO "Tarpeze ITS GPR board\n"); + printk(KERN_INFO "Trapeze ITS GPR board\n"); pm_power_off = gpr_power_off; _machine_halt = gpr_power_off; _machine_restart = gpr_reset; - /* Enable UART3 */ - au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */ - au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ - /* Enable UART1 */ - au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ - au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + /* Enable UART1/3 */ + alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); + alchemy_uart_enable(AU1000_UART1_PHYS_ADDR); /* Take away Reset of UMTS-card */ alchemy_gpio_direction_output(215, 1); diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c index f044f4c..229aafa 100644 --- a/arch/mips/alchemy/gpr/init.c +++ b/arch/mips/alchemy/gpr/init.c @@ -59,5 +59,5 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { - alchemy_uart_putchar(UART0_PHYS_ADDR, c); + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); } diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c index f8d2557..2e81cc7 100644 --- a/arch/mips/alchemy/mtx-1/init.c +++ b/arch/mips/alchemy/mtx-1/init.c @@ -62,5 +62,5 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { - alchemy_uart_putchar(UART0_PHYS_ADDR, c); + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); } diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index febfb0f..81e57fa 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c @@ -66,13 +66,10 @@ void __init board_setup(void) au_writel(pin_func, SYS_PINFUNC); /* Enable UART */ - au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ - mdelay(10); - au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ - mdelay(10); - - /* Enable DTR = USB power up */ - au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */ + alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); + /* Enable DTR (MCR bit 0) = USB power up */ + __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); + wmb(); #ifdef CONFIG_PCI #if defined(__MIPSEB__) diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c index 15125c2..0bf768f 100644 --- a/arch/mips/alchemy/xxs1500/init.c +++ b/arch/mips/alchemy/xxs1500/init.c @@ -60,5 +60,5 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { - alchemy_uart_putchar(UART0_PHYS_ADDR, c); + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); } diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c index 1bff22f..eb063e6 100644 --- a/arch/mips/boot/compressed/uart-alchemy.c +++ b/arch/mips/boot/compressed/uart-alchemy.c @@ -3,5 +3,5 @@ void putc(char c) { /* all current (Jan. 2010) in-kernel boards */ - alchemy_uart_putchar(UART0_PHYS_ADDR, c); + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); } diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index eb8f103..c4ffb20 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -161,6 +161,45 @@ static inline int alchemy_get_cputype(void) return ALCHEMY_CPU_UNKNOWN; } +/* return number of uarts on a given cputype */ +static inline int alchemy_get_uarts(int type) +{ + switch (type) { + case ALCHEMY_CPU_AU1000: + return 4; + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1200: + return 2; + case ALCHEMY_CPU_AU1100: + case ALCHEMY_CPU_AU1550: + return 3; + } + return 0; +} + +/* enable an UART block if it isn't already */ +static inline void alchemy_uart_enable(u32 uart_phys) +{ + void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); + + /* reset, enable clock, deassert reset */ + if ((__raw_readl(addr + 0x100) & 3) != 3) { + __raw_writel(0, addr + 0x100); + wmb(); + __raw_writel(1, addr + 0x100); + wmb(); + } + __raw_writel(3, addr + 0x100); + wmb(); +} + +static inline void alchemy_uart_disable(u32 uart_phys) +{ + void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); + __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */ + wmb(); +} + static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) { void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys); @@ -634,6 +673,10 @@ enum soc_au1200_ints { */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ +#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ +#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ +#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ +#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ @@ -660,10 +703,6 @@ enum soc_au1200_ints { #define MACDMA0_PHYS_ADDR 0x14004000 #define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART2_PHYS_ADDR 0x11300000 -#define UART3_PHYS_ADDR 0x11400000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 #define SYS_PHYS_ADDR 0x11900000 @@ -695,8 +734,6 @@ enum soc_au1200_ints { #define MACDMA0_PHYS_ADDR 0x14004000 #define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART3_PHYS_ADDR 0x11400000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define PCI_MEM_PHYS_ADDR 0x400000000ULL @@ -732,9 +769,6 @@ enum soc_au1200_ints { #define MACDMA0_PHYS_ADDR 0x14004000 #define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART3_PHYS_ADDR 0x11400000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 #define GPIO2_PHYS_ADDR 0x11700000 @@ -758,9 +792,6 @@ enum soc_au1200_ints { #define MACEN_PHYS_ADDR 0x10520000 #define MACDMA0_PHYS_ADDR 0x14004000 #define MACDMA1_PHYS_ADDR 0x14004200 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART3_PHYS_ADDR 0x11400000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define PE_PHYS_ADDR 0x14008000 @@ -786,8 +817,6 @@ enum soc_au1200_ints { #define CIM_PHYS_ADDR 0x14004000 #define USBM_PHYS_ADDR 0x14020000 #define USBH_PHYS_ADDR 0x14020100 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define PSC0_PHYS_ADDR 0x11A00000 -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:45:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:45:52 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:37163 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491143Ab1EHImh (ORCPT ); Sun, 8 May 2011 10:42:37 +0200 Received: by wyb28 with SMTP id 28so4138997wyb.36 for ; Sun, 08 May 2011 01:42:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=aCPdHc/HEA8rxEDCbC7wzZOZf0G6iAQfFegRmvr9J5w=; b=ipyCrpVIpM7qXdXiWNOMJOxpgFKaFh7/KGizyGdsFtFNms0J5PljTiQLQ+l9EglyE7 /hIk30sJv1ToPOFeaScB2Zu/ueSlRs/Zh+QX61KH4sbQ/RkKDA2GLkrFhaPUX78u+Cpz OsI5K+3L0qtN97XVDoa5nWmOLbYcqOCwAsEv4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=gLj51AN3AT9CmKR1jE+7xhXUijDp+4dS37v3m8UzJXiEfGtxIkL1lcwSk67WkvImCo PypL1JQBlLj66d1fsJwXdogHlPOoNwxKSgElWYqEGeqv2md8y3OKYOI3cSugLKTxMey8 s/XUQ2w2KDGDwqTs7tSc/5bShZQpqUs2imUPA= Received: by 10.227.205.202 with SMTP id fr10mr5706224wbb.60.1304844152460; Sun, 08 May 2011 01:42:32 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.31 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:32 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 7/9] MIPS: Alchemy: rewrite ethernet platform setup Date: Sun, 8 May 2011 10:42:18 +0200 Message-Id: <1304844140-3259-8-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29874 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Rewrite ethernet setup to use runtime cpu detection, and also clean up the ethernet base address mess as far as possible. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 151 +++++++++++++++++++--------- arch/mips/include/asm/mach-au1x00/au1000.h | 63 ++++-------- 2 files changed, 123 insertions(+), 91 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 36489fb..541fff2 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -13,9 +13,10 @@ #include #include +#include #include #include -#include +#include #include #include @@ -372,15 +373,16 @@ static struct platform_device pbdb_smbus_device = { #endif /* Macro to help defining the Ethernet MAC resources */ +#define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */ #define MAC_RES(_base, _enable, _irq) \ { \ - .start = CPHYSADDR(_base), \ - .end = CPHYSADDR(_base + 0xffff), \ + .start = _base, \ + .end = _base + 0xffff, \ .flags = IORESOURCE_MEM, \ }, \ { \ - .start = CPHYSADDR(_enable), \ - .end = CPHYSADDR(_enable + 0x3), \ + .start = _enable, \ + .end = _enable + 0x3, \ .flags = IORESOURCE_MEM, \ }, \ { \ @@ -389,19 +391,29 @@ static struct platform_device pbdb_smbus_device = { .flags = IORESOURCE_IRQ \ } -static struct resource au1xxx_eth0_resources[] = { -#if defined(CONFIG_SOC_AU1000) - MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), -#elif defined(CONFIG_SOC_AU1100) - MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), -#elif defined(CONFIG_SOC_AU1550) - MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), -#elif defined(CONFIG_SOC_AU1500) - MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), -#endif +static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = { + [ALCHEMY_CPU_AU1000] = { + MAC_RES(AU1000_MAC0_PHYS_ADDR, + AU1000_MACEN_PHYS_ADDR, + AU1000_MAC0_DMA_INT) + }, + [ALCHEMY_CPU_AU1500] = { + MAC_RES(AU1500_MAC0_PHYS_ADDR, + AU1500_MACEN_PHYS_ADDR, + AU1500_MAC0_DMA_INT) + }, + [ALCHEMY_CPU_AU1100] = { + MAC_RES(AU1000_MAC0_PHYS_ADDR, + AU1000_MACEN_PHYS_ADDR, + AU1100_MAC0_DMA_INT) + }, + [ALCHEMY_CPU_AU1550] = { + MAC_RES(AU1000_MAC0_PHYS_ADDR, + AU1000_MACEN_PHYS_ADDR, + AU1550_MAC0_DMA_INT) + }, }; - static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { .phy1_search_mac0 = 1, }; @@ -409,20 +421,26 @@ static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { static struct platform_device au1xxx_eth0_device = { .name = "au1000-eth", .id = 0, - .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), - .resource = au1xxx_eth0_resources, + .num_resources = MAC_RES_COUNT, .dev.platform_data = &au1xxx_eth0_platform_data, }; -#ifndef CONFIG_SOC_AU1100 -static struct resource au1xxx_eth1_resources[] = { -#if defined(CONFIG_SOC_AU1000) - MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), -#elif defined(CONFIG_SOC_AU1550) - MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), -#elif defined(CONFIG_SOC_AU1500) - MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), -#endif +static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = { + [ALCHEMY_CPU_AU1000] = { + MAC_RES(AU1000_MAC1_PHYS_ADDR, + AU1000_MACEN_PHYS_ADDR + 4, + AU1000_MAC1_DMA_INT) + }, + [ALCHEMY_CPU_AU1500] = { + MAC_RES(AU1500_MAC1_PHYS_ADDR, + AU1500_MACEN_PHYS_ADDR + 4, + AU1500_MAC1_DMA_INT) + }, + [ALCHEMY_CPU_AU1550] = { + MAC_RES(AU1000_MAC1_PHYS_ADDR, + AU1000_MACEN_PHYS_ADDR + 4, + AU1550_MAC1_DMA_INT) + }, }; static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { @@ -432,11 +450,9 @@ static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { static struct platform_device au1xxx_eth1_device = { .name = "au1000-eth", .id = 1, - .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), - .resource = au1xxx_eth1_resources, + .num_resources = MAC_RES_COUNT, .dev.platform_data = &au1xxx_eth1_platform_data, }; -#endif void __init au1xxx_override_eth_cfg(unsigned int port, struct au1000_eth_platform_data *eth_data) @@ -447,11 +463,62 @@ void __init au1xxx_override_eth_cfg(unsigned int port, if (port == 0) memcpy(&au1xxx_eth0_platform_data, eth_data, sizeof(struct au1000_eth_platform_data)); -#ifndef CONFIG_SOC_AU1100 else memcpy(&au1xxx_eth1_platform_data, eth_data, sizeof(struct au1000_eth_platform_data)); -#endif +} + +static void __init alchemy_setup_macs(int ctype) +{ + int ret, i; + unsigned char ethaddr[6]; + struct resource *macres; + + /* Handle 1st MAC */ + if (alchemy_get_macs(ctype) < 1) + return; + + macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); + if (!macres) { + printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n"); + return; + } + memcpy(macres, au1xxx_eth0_resources[ctype], + sizeof(struct resource) * MAC_RES_COUNT); + au1xxx_eth0_device.resource = macres; + + i = prom_get_ethernet_addr(ethaddr); + if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac)) + memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6); + + ret = platform_device_register(&au1xxx_eth0_device); + if (!ret) + printk(KERN_INFO "Alchemy: failed to register MAC0\n"); + + + /* Handle 2nd MAC */ + if (alchemy_get_macs(ctype) < 2) + return; + + macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); + if (!macres) { + printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n"); + return; + } + memcpy(macres, au1xxx_eth1_resources[ctype], + sizeof(struct resource) * MAC_RES_COUNT); + au1xxx_eth1_device.resource = macres; + + ethaddr[5] += 1; /* next addr for 2nd MAC */ + if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac)) + memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6); + + /* Register second MAC if enabled in pinfunc */ + if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) { + ret = platform_device_register(&au1xxx_eth1_device); + if (ret) + printk(KERN_INFO "Alchemy: failed to register MAC1\n"); + } } static struct platform_device *au1xxx_platform_devices[] __initdata = { @@ -472,33 +539,17 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, #endif - &au1xxx_eth0_device, }; static int __init au1xxx_platform_init(void) { - int err, i, ctype = alchemy_get_cputype(); - unsigned char ethaddr[6]; + int err, ctype = alchemy_get_cputype(); alchemy_setup_uarts(ctype); - - /* use firmware-provided mac addr if available and necessary */ - i = prom_get_ethernet_addr(ethaddr); - if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac)) - memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6); + alchemy_setup_macs(ctype); err = platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices)); -#ifndef CONFIG_SOC_AU1100 - ethaddr[5] += 1; /* next addr for 2nd MAC */ - if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac)) - memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6); - - /* Register second MAC if enabled in pinfunc */ - if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) - err = platform_device_register(&au1xxx_eth1_device); -#endif - return err; } diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index c4ffb20..415d287 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -219,6 +219,20 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) wmb(); } +/* return number of ethernet MACs on a given cputype */ +static inline int alchemy_get_macs(int type) +{ + switch (type) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1550: + return 2; + case ALCHEMY_CPU_AU1100: + return 1; + } + return 0; +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); @@ -673,6 +687,12 @@ enum soc_au1200_ints { */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ +#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ +#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ +#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ +#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ +#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ +#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ @@ -680,6 +700,8 @@ enum soc_au1200_ints { #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ +#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ +#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ #ifdef CONFIG_SOC_AU1000 @@ -697,11 +719,6 @@ enum soc_au1200_ints { #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 #define IRDA_PHYS_ADDR 0x10300000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MAC1_PHYS_ADDR 0x10510000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 @@ -728,11 +745,6 @@ enum soc_au1200_ints { #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 #define PCI_PHYS_ADDR 0x14005000 -#define MAC0_PHYS_ADDR 0x11500000 -#define MAC1_PHYS_ADDR 0x11510000 -#define MACEN_PHYS_ADDR 0x11520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 @@ -764,10 +776,6 @@ enum soc_au1200_ints { #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 #define IRDA_PHYS_ADDR 0x10300000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 #define I2S_PHYS_ADDR 0x11000000 #define SSI0_PHYS_ADDR 0x11600000 #define SSI1_PHYS_ADDR 0x11680000 @@ -787,11 +795,6 @@ enum soc_au1200_ints { #define USBH_PHYS_ADDR 0x14020000 #define USBD_PHYS_ADDR 0x10200000 #define PCI_PHYS_ADDR 0x14005000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MAC1_PHYS_ADDR 0x10510000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 #define GPIO2_PHYS_ADDR 0x11700000 #define SYS_PHYS_ADDR 0x11900000 #define PE_PHYS_ADDR 0x14008000 @@ -870,12 +873,6 @@ enum soc_au1200_ints { #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017FFFC #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT - -#define AU1000_ETH0_BASE 0xB0500000 -#define AU1000_ETH1_BASE 0xB0510000 -#define AU1000_MAC0_ENABLE 0xB0520000 -#define AU1000_MAC1_ENABLE 0xB0520004 -#define NUM_ETH_INTERFACES 2 #endif /* CONFIG_SOC_AU1000 */ /* Au1500 */ @@ -887,12 +884,6 @@ enum soc_au1200_ints { #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017fffc #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT - -#define AU1500_ETH0_BASE 0xB1500000 -#define AU1500_ETH1_BASE 0xB1510000 -#define AU1500_MAC0_ENABLE 0xB1520000 -#define AU1500_MAC1_ENABLE 0xB1520004 -#define NUM_ETH_INTERFACES 2 #endif /* CONFIG_SOC_AU1500 */ /* Au1100 */ @@ -904,10 +895,6 @@ enum soc_au1200_ints { #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ #define USB_HOST_CONFIG 0xB017FFFC #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT - -#define AU1100_ETH0_BASE 0xB0500000 -#define AU1100_MAC0_ENABLE 0xB0520000 -#define NUM_ETH_INTERFACES 1 #endif /* CONFIG_SOC_AU1100 */ #ifdef CONFIG_SOC_AU1550 @@ -917,12 +904,6 @@ enum soc_au1200_ints { #define USB_OHCI_LEN 0x00060000 #define USB_HOST_CONFIG 0xB4027ffc #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT - -#define AU1550_ETH0_BASE 0xB0500000 -#define AU1550_ETH1_BASE 0xB0510000 -#define AU1550_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC1_ENABLE 0xB0520004 -#define NUM_ETH_INTERFACES 2 #endif /* CONFIG_SOC_AU1550 */ -- 1.7.5.rc3 From manuel.lauss@googlemail.com Sun May 8 10:46:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 10:46:19 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:37557 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491144Ab1EHInk (ORCPT ); Sun, 8 May 2011 10:43:40 +0200 Received: by wyb28 with SMTP id 28so4139292wyb.36 for ; Sun, 08 May 2011 01:43:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=SS4TZk+znwA0Ozs20RTuETmkEcTK08b+XO2XABSOF08=; b=OODciVFHVq9vNzviHIY4xVmNoJa2jIsNXWPXLeUG9qv1WgMYdon24CSFCtZgtcZcfz 4ZvNJe0vwyLqn3oalXFoISTFukVvvi0lYvtqsxDz3Oc7WATgySBWtWOwnCthSH3hw6pi ymEX4NVWxcQooukjnKrtZ7AO5HrZ0ylBISCus= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=cd9zy4O4HXklfyTsXvp1QRC3GZJo11rOD8nxlLFR9DKoUNotez9zfvc5AGTre20Smw gXAG+dviszE+OuO5rcJOiUM5FOfXG26M23WvVhlIcbKFPlUevHbewoA3wz4nHvjRRCM0 cG1a0de3CCk+hf7sTVgM/6b3bs2PbmZ/RF8/M= Received: by 10.216.12.146 with SMTP id 18mr1405099wez.63.1304844148670; Sun, 08 May 2011 01:42:28 -0700 (PDT) Received: from localhost.localdomain (178-191-5-255.adsl.highway.telekom.at [178.191.5.255]) by mx.google.com with ESMTPS id z9sm3022884wbx.34.2011.05.08.01.42.27 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 08 May 2011 01:42:28 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Florian Fainelli , Wolfgang Grandegger , Manuel Lauss Subject: [PATCH 3/9] MIPS: Alchemy: irq code and constant cleanup Date: Sun, 8 May 2011 10:42:14 +0200 Message-Id: <1304844140-3259-4-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.5.rc3 In-Reply-To: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29875 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips replace au_readl/au_writel with __raw_readl/__raw_writel, and clean up IC-related stuff from the headers. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/irq.c | 250 +++++++++++++++------------- arch/mips/include/asm/mach-au1x00/au1000.h | 121 +------------- 2 files changed, 140 insertions(+), 231 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 55dd7c8..b72e128 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -39,6 +39,36 @@ #include #endif +/* Interrupt Controller register offsets */ +#define IC_CFG0RD 0x40 +#define IC_CFG0SET 0x40 +#define IC_CFG0CLR 0x44 +#define IC_CFG1RD 0x48 +#define IC_CFG1SET 0x48 +#define IC_CFG1CLR 0x4C +#define IC_CFG2RD 0x50 +#define IC_CFG2SET 0x50 +#define IC_CFG2CLR 0x54 +#define IC_REQ0INT 0x54 +#define IC_SRCRD 0x58 +#define IC_SRCSET 0x58 +#define IC_SRCCLR 0x5C +#define IC_REQ1INT 0x5C +#define IC_ASSIGNRD 0x60 +#define IC_ASSIGNSET 0x60 +#define IC_ASSIGNCLR 0x64 +#define IC_WAKERD 0x68 +#define IC_WAKESET 0x68 +#define IC_WAKECLR 0x6C +#define IC_MASKRD 0x70 +#define IC_MASKSET 0x70 +#define IC_MASKCLR 0x74 +#define IC_RISINGRD 0x78 +#define IC_RISINGCLR 0x78 +#define IC_FALLINGRD 0x7C +#define IC_FALLINGCLR 0x7C +#define IC_TESTBIT 0x80 + static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); /* NOTE on interrupt priorities: The original writers of this code said: @@ -221,89 +251,101 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { static void au1x_ic0_unmask(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; - au_writel(1 << bit, IC0_MASKSET); - au_writel(1 << bit, IC0_WAKESET); - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); + + __raw_writel(1 << bit, base + IC_MASKSET); + __raw_writel(1 << bit, base + IC_WAKESET); + wmb(); } static void au1x_ic1_unmask(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; - au_writel(1 << bit, IC1_MASKSET); - au_writel(1 << bit, IC1_WAKESET); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); + + __raw_writel(1 << bit, base + IC_MASKSET); + __raw_writel(1 << bit, base + IC_WAKESET); /* very hacky. does the pb1000 cpld auto-disable this int? * nowhere in the current kernel sources is it disabled. --mlau */ #if defined(CONFIG_MIPS_PB1000) if (d->irq == AU1000_GPIO15_INT) - au_writel(0x4000, PB1000_MDR); /* enable int */ + __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */ #endif - au_sync(); + wmb(); } static void au1x_ic0_mask(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; - au_writel(1 << bit, IC0_MASKCLR); - au_writel(1 << bit, IC0_WAKECLR); - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); + + __raw_writel(1 << bit, base + IC_MASKCLR); + __raw_writel(1 << bit, base + IC_WAKECLR); + wmb(); } static void au1x_ic1_mask(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; - au_writel(1 << bit, IC1_MASKCLR); - au_writel(1 << bit, IC1_WAKECLR); - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); + + __raw_writel(1 << bit, base + IC_MASKCLR); + __raw_writel(1 << bit, base + IC_WAKECLR); + wmb(); } static void au1x_ic0_ack(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); /* * This may assume that we don't get interrupts from * both edges at once, or if we do, that we don't care. */ - au_writel(1 << bit, IC0_FALLINGCLR); - au_writel(1 << bit, IC0_RISINGCLR); - au_sync(); + __raw_writel(1 << bit, base + IC_FALLINGCLR); + __raw_writel(1 << bit, base + IC_RISINGCLR); + wmb(); } static void au1x_ic1_ack(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); /* * This may assume that we don't get interrupts from * both edges at once, or if we do, that we don't care. */ - au_writel(1 << bit, IC1_FALLINGCLR); - au_writel(1 << bit, IC1_RISINGCLR); - au_sync(); + __raw_writel(1 << bit, base + IC_FALLINGCLR); + __raw_writel(1 << bit, base + IC_RISINGCLR); + wmb(); } static void au1x_ic0_maskack(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); - au_writel(1 << bit, IC0_WAKECLR); - au_writel(1 << bit, IC0_MASKCLR); - au_writel(1 << bit, IC0_RISINGCLR); - au_writel(1 << bit, IC0_FALLINGCLR); - au_sync(); + __raw_writel(1 << bit, base + IC_WAKECLR); + __raw_writel(1 << bit, base + IC_MASKCLR); + __raw_writel(1 << bit, base + IC_RISINGCLR); + __raw_writel(1 << bit, base + IC_FALLINGCLR); + wmb(); } static void au1x_ic1_maskack(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); - au_writel(1 << bit, IC1_WAKECLR); - au_writel(1 << bit, IC1_MASKCLR); - au_writel(1 << bit, IC1_RISINGCLR); - au_writel(1 << bit, IC1_FALLINGCLR); - au_sync(); + __raw_writel(1 << bit, base + IC_WAKECLR); + __raw_writel(1 << bit, base + IC_MASKCLR); + __raw_writel(1 << bit, base + IC_RISINGCLR); + __raw_writel(1 << bit, base + IC_FALLINGCLR); + wmb(); } static int au1x_ic1_setwake(struct irq_data *d, unsigned int on) @@ -318,13 +360,13 @@ static int au1x_ic1_setwake(struct irq_data *d, unsigned int on) return -EINVAL; local_irq_save(flags); - wakemsk = au_readl(SYS_WAKEMSK); + wakemsk = __raw_readl((void __iomem *)SYS_WAKEMSK); if (on) wakemsk |= 1 << bit; else wakemsk &= ~(1 << bit); - au_writel(wakemsk, SYS_WAKEMSK); - au_sync(); + __raw_writel(wakemsk, (void __iomem *)SYS_WAKEMSK); + wmb(); local_irq_restore(flags); return 0; @@ -356,81 +398,74 @@ static struct irq_chip au1x_ic1_chip = { static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type) { struct irq_chip *chip; - unsigned long icr[6]; - unsigned int bit, ic, irq = d->irq; + unsigned int bit, irq = d->irq; irq_flow_handler_t handler = NULL; unsigned char *name = NULL; + void __iomem *base; int ret; if (irq >= AU1000_INTC1_INT_BASE) { bit = irq - AU1000_INTC1_INT_BASE; chip = &au1x_ic1_chip; - ic = 1; + base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); } else { bit = irq - AU1000_INTC0_INT_BASE; chip = &au1x_ic0_chip; - ic = 0; + base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); } if (bit > 31) return -EINVAL; - icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET; - icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET; - icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET; - icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR; - icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR; - icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR; - ret = 0; switch (flow_type) { /* cfgregs 2:1:0 */ case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[0]); + __raw_writel(1 << bit, base + IC_CFG2CLR); + __raw_writel(1 << bit, base + IC_CFG1CLR); + __raw_writel(1 << bit, base + IC_CFG0SET); handler = handle_edge_irq; name = "riseedge"; break; case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[3]); + __raw_writel(1 << bit, base + IC_CFG2CLR); + __raw_writel(1 << bit, base + IC_CFG1SET); + __raw_writel(1 << bit, base + IC_CFG0CLR); handler = handle_edge_irq; name = "falledge"; break; case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[0]); + __raw_writel(1 << bit, base + IC_CFG2CLR); + __raw_writel(1 << bit, base + IC_CFG1SET); + __raw_writel(1 << bit, base + IC_CFG0SET); handler = handle_edge_irq; name = "bothedge"; break; case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ - au_writel(1 << bit, icr[2]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[0]); + __raw_writel(1 << bit, base + IC_CFG2SET); + __raw_writel(1 << bit, base + IC_CFG1CLR); + __raw_writel(1 << bit, base + IC_CFG0SET); handler = handle_level_irq; name = "hilevel"; break; case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ - au_writel(1 << bit, icr[2]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[3]); + __raw_writel(1 << bit, base + IC_CFG2SET); + __raw_writel(1 << bit, base + IC_CFG1SET); + __raw_writel(1 << bit, base + IC_CFG0CLR); handler = handle_level_irq; name = "lowlevel"; break; case IRQ_TYPE_NONE: /* 0:0:0 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[3]); + __raw_writel(1 << bit, base + IC_CFG2CLR); + __raw_writel(1 << bit, base + IC_CFG1CLR); + __raw_writel(1 << bit, base + IC_CFG0CLR); break; default: ret = -EINVAL; } __irq_set_chip_handler_name_locked(d->irq, chip, handler, name); - au_sync(); + wmb(); return ret; } @@ -444,21 +479,21 @@ asmlinkage void plat_irq_dispatch(void) off = MIPS_CPU_IRQ_BASE + 7; goto handle; } else if (pending & CAUSEF_IP2) { - s = IC0_REQ0INT; + s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT; off = AU1000_INTC0_INT_BASE; } else if (pending & CAUSEF_IP3) { - s = IC0_REQ1INT; + s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT; off = AU1000_INTC0_INT_BASE; } else if (pending & CAUSEF_IP4) { - s = IC1_REQ0INT; + s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT; off = AU1000_INTC1_INT_BASE; } else if (pending & CAUSEF_IP5) { - s = IC1_REQ1INT; + s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT; off = AU1000_INTC1_INT_BASE; } else goto spurious; - s = au_readl(s); + s = __raw_readl((void __iomem *)s); if (unlikely(!s)) { spurious: spurious_interrupt(); @@ -469,48 +504,42 @@ handle: do_IRQ(off); } + +static inline void ic_init(void __iomem *base) +{ + /* initialize interrupt controller to a safe state */ + __raw_writel(0xffffffff, base + IC_CFG0CLR); + __raw_writel(0xffffffff, base + IC_CFG1CLR); + __raw_writel(0xffffffff, base + IC_CFG2CLR); + __raw_writel(0xffffffff, base + IC_MASKCLR); + __raw_writel(0xffffffff, base + IC_ASSIGNCLR); + __raw_writel(0xffffffff, base + IC_WAKECLR); + __raw_writel(0xffffffff, base + IC_SRCSET); + __raw_writel(0xffffffff, base + IC_FALLINGCLR); + __raw_writel(0xffffffff, base + IC_RISINGCLR); + __raw_writel(0x00000000, base + IC_TESTBIT); + wmb(); +} + static void __init au1000_init_irq(struct au1xxx_irqmap *map) { unsigned int bit, irq_nr; - int i; - - /* - * Initialize interrupt controllers to a safe state. - */ - au_writel(0xffffffff, IC0_CFG0CLR); - au_writel(0xffffffff, IC0_CFG1CLR); - au_writel(0xffffffff, IC0_CFG2CLR); - au_writel(0xffffffff, IC0_MASKCLR); - au_writel(0xffffffff, IC0_ASSIGNCLR); - au_writel(0xffffffff, IC0_WAKECLR); - au_writel(0xffffffff, IC0_SRCSET); - au_writel(0xffffffff, IC0_FALLINGCLR); - au_writel(0xffffffff, IC0_RISINGCLR); - au_writel(0x00000000, IC0_TESTBIT); - - au_writel(0xffffffff, IC1_CFG0CLR); - au_writel(0xffffffff, IC1_CFG1CLR); - au_writel(0xffffffff, IC1_CFG2CLR); - au_writel(0xffffffff, IC1_MASKCLR); - au_writel(0xffffffff, IC1_ASSIGNCLR); - au_writel(0xffffffff, IC1_WAKECLR); - au_writel(0xffffffff, IC1_SRCSET); - au_writel(0xffffffff, IC1_FALLINGCLR); - au_writel(0xffffffff, IC1_RISINGCLR); - au_writel(0x00000000, IC1_TESTBIT); + void __iomem *base; + ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); + ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); mips_cpu_irq_init(); /* register all 64 possible IC0+IC1 irq sources as type "none". * Use set_irq_type() to set edge/level behaviour at runtime. */ - for (i = AU1000_INTC0_INT_BASE; - (i < AU1000_INTC0_INT_BASE + 32); i++) - au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); + for (irq_nr = AU1000_INTC0_INT_BASE; + (irq_nr < AU1000_INTC0_INT_BASE + 32); irq_nr++) + au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE); - for (i = AU1000_INTC1_INT_BASE; - (i < AU1000_INTC1_INT_BASE + 32); i++) - au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); + for (irq_nr = AU1000_INTC1_INT_BASE; + (irq_nr < AU1000_INTC1_INT_BASE + 32); irq_nr++) + au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE); /* * Initialize IC0, which is fixed per processor. @@ -520,13 +549,13 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) if (irq_nr >= AU1000_INTC1_INT_BASE) { bit = irq_nr - AU1000_INTC1_INT_BASE; - if (map->im_request) - au_writel(1 << bit, IC1_ASSIGNSET); + base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); } else { bit = irq_nr - AU1000_INTC0_INT_BASE; - if (map->im_request) - au_writel(1 << bit, IC0_ASSIGNSET); + base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); } + if (map->im_request) + __raw_writel(1 << bit, base + IC_ASSIGNSET); au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type); ++map; @@ -583,17 +612,8 @@ static int alchemy_ic_resume(struct sys_device *dev) struct alchemy_ic_sysdev *icdev = container_of(dev, struct alchemy_ic_sysdev, sysdev); - __raw_writel(0xffffffff, icdev->base + IC_MASKCLR); - __raw_writel(0xffffffff, icdev->base + IC_CFG0CLR); - __raw_writel(0xffffffff, icdev->base + IC_CFG1CLR); - __raw_writel(0xffffffff, icdev->base + IC_CFG2CLR); - __raw_writel(0xffffffff, icdev->base + IC_SRCCLR); - __raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR); - __raw_writel(0xffffffff, icdev->base + IC_WAKECLR); - __raw_writel(0xffffffff, icdev->base + IC_RISINGCLR); - __raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR); - __raw_writel(0x00000000, icdev->base + IC_TESTBIT); - wmb(); + ic_init(icdev->base); + __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET); __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET); __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET); @@ -617,7 +637,7 @@ static struct sysdev_class alchemy_ic_sysdev_class = { static int __init alchemy_ic_sysdev_init(void) { struct alchemy_ic_sysdev *icdev; - unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR }; + unsigned long icbase[2] = { AU1000_IC0_PHYS_ADDR, AU1000_IC1_PHYS_ADDR }; int err, i; err = sysdev_class_register(&alchemy_ic_sysdev_class); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index a697661..66cfcdc 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -630,8 +630,13 @@ enum soc_au1200_ints { /* * Physical base addresses for integrated peripherals + * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 */ +#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ +#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ + + #ifdef CONFIG_SOC_AU1000 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 @@ -643,8 +648,6 @@ enum soc_au1200_ints { #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 @@ -680,8 +683,6 @@ enum soc_au1200_ints { #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 @@ -718,10 +719,8 @@ enum soc_au1200_ints { #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 #define SD0_PHYS_ADDR 0x10600000 #define SD1_PHYS_ADDR 0x10680000 -#define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 @@ -749,8 +748,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1550 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 #define USBH_PHYS_ADDR 0x14020000 #define USBD_PHYS_ADDR 0x10200000 #define PCI_PHYS_ADDR 0x14005000 @@ -786,8 +783,6 @@ enum soc_au1200_ints { #define STATIC_MEM_PHYS_ADDR 0x14001000 #define AES_PHYS_ADDR 0x10300000 #define CIM_PHYS_ADDR 0x14004000 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 #define USBM_PHYS_ADDR 0x14020000 #define USBH_PHYS_ADDR 0x14020100 #define UART0_PHYS_ADDR 0x11100000 @@ -835,112 +830,6 @@ enum soc_au1200_ints { #endif -/* Interrupt Controller register offsets */ -#define IC_CFG0RD 0x40 -#define IC_CFG0SET 0x40 -#define IC_CFG0CLR 0x44 -#define IC_CFG1RD 0x48 -#define IC_CFG1SET 0x48 -#define IC_CFG1CLR 0x4C -#define IC_CFG2RD 0x50 -#define IC_CFG2SET 0x50 -#define IC_CFG2CLR 0x54 -#define IC_REQ0INT 0x54 -#define IC_SRCRD 0x58 -#define IC_SRCSET 0x58 -#define IC_SRCCLR 0x5C -#define IC_REQ1INT 0x5C -#define IC_ASSIGNRD 0x60 -#define IC_ASSIGNSET 0x60 -#define IC_ASSIGNCLR 0x64 -#define IC_WAKERD 0x68 -#define IC_WAKESET 0x68 -#define IC_WAKECLR 0x6C -#define IC_MASKRD 0x70 -#define IC_MASKSET 0x70 -#define IC_MASKCLR 0x74 -#define IC_RISINGRD 0x78 -#define IC_RISINGCLR 0x78 -#define IC_FALLINGRD 0x7C -#define IC_FALLINGCLR 0x7C -#define IC_TESTBIT 0x80 - - -/* Interrupt Controller 0 */ -#define IC0_CFG0RD 0xB0400040 -#define IC0_CFG0SET 0xB0400040 -#define IC0_CFG0CLR 0xB0400044 - -#define IC0_CFG1RD 0xB0400048 -#define IC0_CFG1SET 0xB0400048 -#define IC0_CFG1CLR 0xB040004C - -#define IC0_CFG2RD 0xB0400050 -#define IC0_CFG2SET 0xB0400050 -#define IC0_CFG2CLR 0xB0400054 - -#define IC0_REQ0INT 0xB0400054 -#define IC0_SRCRD 0xB0400058 -#define IC0_SRCSET 0xB0400058 -#define IC0_SRCCLR 0xB040005C -#define IC0_REQ1INT 0xB040005C - -#define IC0_ASSIGNRD 0xB0400060 -#define IC0_ASSIGNSET 0xB0400060 -#define IC0_ASSIGNCLR 0xB0400064 - -#define IC0_WAKERD 0xB0400068 -#define IC0_WAKESET 0xB0400068 -#define IC0_WAKECLR 0xB040006C - -#define IC0_MASKRD 0xB0400070 -#define IC0_MASKSET 0xB0400070 -#define IC0_MASKCLR 0xB0400074 - -#define IC0_RISINGRD 0xB0400078 -#define IC0_RISINGCLR 0xB0400078 -#define IC0_FALLINGRD 0xB040007C -#define IC0_FALLINGCLR 0xB040007C - -#define IC0_TESTBIT 0xB0400080 - -/* Interrupt Controller 1 */ -#define IC1_CFG0RD 0xB1800040 -#define IC1_CFG0SET 0xB1800040 -#define IC1_CFG0CLR 0xB1800044 - -#define IC1_CFG1RD 0xB1800048 -#define IC1_CFG1SET 0xB1800048 -#define IC1_CFG1CLR 0xB180004C - -#define IC1_CFG2RD 0xB1800050 -#define IC1_CFG2SET 0xB1800050 -#define IC1_CFG2CLR 0xB1800054 - -#define IC1_REQ0INT 0xB1800054 -#define IC1_SRCRD 0xB1800058 -#define IC1_SRCSET 0xB1800058 -#define IC1_SRCCLR 0xB180005C -#define IC1_REQ1INT 0xB180005C - -#define IC1_ASSIGNRD 0xB1800060 -#define IC1_ASSIGNSET 0xB1800060 -#define IC1_ASSIGNCLR 0xB1800064 - -#define IC1_WAKERD 0xB1800068 -#define IC1_WAKESET 0xB1800068 -#define IC1_WAKECLR 0xB180006C - -#define IC1_MASKRD 0xB1800070 -#define IC1_MASKSET 0xB1800070 -#define IC1_MASKCLR 0xB1800074 - -#define IC1_RISINGRD 0xB1800078 -#define IC1_RISINGCLR 0xB1800078 -#define IC1_FALLINGRD 0xB180007C -#define IC1_FALLINGCLR 0xB180007C - -#define IC1_TESTBIT 0xB1800080 /* Au1000 */ -- 1.7.5.rc3 From linux+linux-mips=linux-mips.org@arm.linux.org.uk Sun May 8 11:24:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 11:24:39 +0200 (CEST) Received: from caramon.arm.linux.org.uk ([78.32.30.218]:60808 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491144Ab1EHJYg (ORCPT ); Sun, 8 May 2011 11:24:36 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=caramon; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=IUndsoD6xAL7Vws6YsrpZkfoP8BKP4c8hIlYddhG+5o=; b=LNjmFi8a8Cnz3iX1r1c8ceb0fiYeeOh6q2cwTc2mTQ/TpE0cVao3K6bVV9AigxrObkIds47KJCnHwr0zwKUOTefUbN2s8UsSIkqcJQ8qiihsYGXoiuBYocoRwC5RdpOA/BplZKNzhivy2Eee9IQXXfCLDD2vaXVB35WHb4Hbfhw=; Received: from n2100.arm.linux.org.uk ([2002:4e20:1eda:1:214:fdff:fe10:4f86]) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1QJ0De-0003fn-FA; Sun, 08 May 2011 10:24:07 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.72) (envelope-from ) id 1QJ0Dc-0007XK-Ds; Sun, 08 May 2011 10:24:04 +0100 Date: Sun, 8 May 2011 10:24:03 +0100 From: Russell King - ARM Linux To: Sven Eckelmann Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mips@linux-mips.org, linux-m32r@ml.linux-m32r.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org, linux-cris-kernel@axis.com, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, x86@kernel.org, Chris Metcalf , David Howells , linux-m68k@lists.linux-m68k.org, linux-am33-list@redhat.com, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] atomic: add *_dec_not_zero Message-ID: <20110508092403.GB27807@n2100.arm.linux.org.uk> References: <1304458235-28473-1-git-send-email-sven@narfation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29876 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux@arm.linux.org.uk Precedence: bulk X-list: linux-mips On Tue, May 03, 2011 at 11:30:35PM +0200, Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. ... > diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h > index 7e79503..a005265 100644 > --- a/arch/arm/include/asm/atomic.h > +++ b/arch/arm/include/asm/atomic.h > @@ -218,6 +218,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) > return c != u; > } > #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) > +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) > > #define atomic_inc(v) atomic_add(1, v) > #define atomic_dec(v) atomic_sub(1, v) > @@ -459,6 +460,7 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u) > #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v)) > #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) > #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL) > +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1LL, 0LL) > > #else /* !CONFIG_GENERIC_ATOMIC64 */ > #include Do we need atomic_dec_not_zero() et.al. in every arch header - is there no generic header which it could be added to? From sven@narfation.org Sun May 8 11:34:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 May 2011 11:34:08 +0200 (CEST) Received: from narfation.org ([79.140.41.39]:47506 "EHLO v3-1039.vlinux.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491144Ab1EHJeE (ORCPT ); Sun, 8 May 2011 11:34:04 +0200 Received: from sven-desktop.home.narfation.org (i59F6B054.versanet.de [89.246.176.84]) by v3-1039.vlinux.de (Postfix) with ESMTPSA id F2D20940DC; Sun, 8 May 2011 11:34:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=narfation.org; s=mail; t=1304847247; bh=ZsDp5I2ahHMgchtif3vZZU35EkCa+97w9vNVwQ5M3xA=; h=From:To:Subject:Date:Cc:References:In-Reply-To:MIME-Version: Content-Type:Content-Transfer-Encoding:Message-Id; b=UUW1EBfLxJNFvY/LDh8PBm8rGCZKtQvto51iZFwmd/nCE61DgW1bc0WMiUiJXJX9m /Lvq69R/oWN9CGVqFmqfpq8AoTUoP5yxfkdJ3SaXbNFEnNoBuSjeG3Iyced9l5r+oo GZ9D0K4j7Cx4IHK5bti3bLQwSBcoZ3B40M7iNn8o= From: Sven Eckelmann To: "Russell King - ARM Linux" Subject: Re: [PATCH] atomic: add *_dec_not_zero Date: Sun, 8 May 2011 11:33:48 +0200 User-Agent: KMail/1.13.7 (Linux/2.6.38-2-amd64; KDE/4.6.2; x86_64; ; ) Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mips@linux-mips.org, linux-m32r@ml.linux-m32r.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org, linux-cris-kernel@axis.com, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, x86@kernel.org, Chris Metcalf , David Howells , linux-m68k@lists.linux-m68k.org, linux-am33-list@redhat.com, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org References: <1304458235-28473-1-git-send-email-sven@narfation.org> <20110508092403.GB27807@n2100.arm.linux.org.uk> In-Reply-To: <20110508092403.GB27807@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart1677856.Ey88dTAy4V"; protocol="application/pgp-signature"; micalg=pgp-sha512 Content-Transfer-Encoding: 7bit Message-Id: <201105081133.50824.sven@narfation.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29877 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sven@narfation.org Precedence: bulk X-list: linux-mips --nextPart1677856.Ey88dTAy4V Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Russell King - ARM Linux wrote: [...] > Do we need atomic_dec_not_zero() et.al. in every arch header - is there no > generic header which it could be added to? Mike Frysinger already tried to answer it in=20 : > that's what asm-generic is for. if the arch isnt using it, it's > either because the arch needs to convert to it, or they're using SMP > and asm-generic doesnt yet support that for atomic.h. > > for example, the Blackfin port only needed updating for the SMP case. > in the non-SMP case, we're getting the def from asm-generic/atomic.h. > -mike =46eel free to change that but I just followed the style used by all other= =20 macros and will not redesign the complete atomic*.h idea. thanks, Sven --nextPart1677856.Ey88dTAy4V Content-Type: application/pgp-signature; name=signature.asc Content-Description: This is a digitally signed message part. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCgAGBQJNxmN9AAoJEF2HCgfBJntGmosP/0BjDtvk4ZKsL9hhonb8gZ4t /2/hY6jeQ3Mg30Z1v6+PIZDun17qML5ODBcTB72oJs1LujHyEgNKKtfQ9stYgAm3 79B2UAH5LYVzZzd2j5nMWemGYChUXl5v5N/hOFOp04ImC7DU27fwadcuO+q47vnS kKvrnccIFc0qUpnGwZ+1rqHIp9Rs3AQHjvyxaUDIuMs8ZWurYkS+e5SMini7qUpe QvsTQVZhyuNtemvZUzrWUcftMVPNXxTHwwV5aALBswX4SPreBJWX33b8j+NIHeFU hmwZ7/RzuDCyIzUFmeeXj/f0RCbWv5XkhQmNaCGFBdatgLRd2fnDOXzkuOeUPtBi SX2jkxoXSMGwEtl2mzOW8JhvcGrG1+oMw9j/BqdQyaQe0rRnuFg962eRUs1RvibI bej/DRfMexoXhlw7EIN9JGoniuMAW88Ws4RB79HuPURy6Ax1cr87ELH/Oj5ZvlOc +whWNM9JuDFamC9E4zaenxqf0jd3mlvCAMaljh66J7qECJF9xWd5eJyet7CE7/hp kE6iUT6Zf93Na9NImeTTeGK16LW1KqLkP8QyI+HUGO7A5wj/QvubGPBO0deHsp8G YkQBcQwZMSft69hsW2Ke1btpJv/ScGxeVuplmMNrlDa1hAqjm+aHo6+xxTS5Mp72 p5S21fQTeEf4fOJsQubR =ICmm -----END PGP SIGNATURE----- --nextPart1677856.Ey88dTAy4V-- From benh@kernel.crashing.org Mon May 9 00:16:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 00:16:31 +0200 (CEST) Received: from gate.crashing.org ([63.228.1.57]:59174 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491779Ab1EHWQN (ORCPT ); Mon, 9 May 2011 00:16:13 +0200 Received: from [IPv6:::1] (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p48MFfv7004073; Sun, 8 May 2011 17:15:42 -0500 Subject: Re: [PATCH] atomic: add *_dec_not_zero From: Benjamin Herrenschmidt To: Sven Eckelmann Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mips@linux-mips.org, linux-m32r@ml.linux-m32r.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org, linux-cris-kernel@axis.com, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, x86@kernel.org, Chris Metcalf , David Howells , linux-m68k@vger.kernel.org, linux-am33-list@redhat.com, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org In-Reply-To: <1304458235-28473-1-git-send-email-sven@narfation.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> Content-Type: text/plain; charset="UTF-8" Date: Mon, 09 May 2011 08:15:39 +1000 Message-ID: <1304892939.2513.503.camel@pasglop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: benh@kernel.crashing.org Precedence: bulk X-list: linux-mips On Tue, 2011-05-03 at 23:30 +0200, Sven Eckelmann wrote: > Introduce an *_dec_not_zero operation. Make this a special case of > *_add_unless because batman-adv uses atomic_dec_not_zero in different > places like re-broadcast queue or aggregation queue management. There > are other non-final patches which may also want to use this macro. For arch/powerpc: Acked-by: Benjamin Herrenschmidt (Sorry for catching up late) Cheers, Ben. > diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h > index b8f152e..906f49a 100644 > --- a/arch/powerpc/include/asm/atomic.h > +++ b/arch/powerpc/include/asm/atomic.h > @@ -213,6 +213,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) > } > > #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) > +#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) > > #define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0) > #define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0) > @@ -469,6 +470,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) > } > > #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) > +#define atomic64_dec_not_zero(v) atomic64_add_unless((v), -1, 0) > > #else /* __powerpc64__ */ > #include > diff --git a/arch/powerpc/include/asm/local.h b/arch/powerpc/include/asm/local.h > index c2410af..3d4c58a 100644 > --- a/arch/powerpc/include/asm/local.h > +++ b/arch/powerpc/include/asm/local.h > @@ -134,6 +134,7 @@ static __inline__ int local_add_unless(local_t *l, long a, long u) > } > > #define local_inc_not_zero(l) local_add_unless((l), 1, 0) > +#define local_dec_not_zero(l) local_add_unless((l), -1, 0) > > #define local_sub_and_test(a, l) (local_sub_return((a), (l)) == 0) > #define local_dec_and_test(l) (local_dec_return((l)) == 0) From vapier.adi@gmail.com Mon May 9 04:39:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 04:39:18 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:38882 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490988Ab1EICjK convert rfc822-to-8bit (ORCPT ); Mon, 9 May 2011 04:39:10 +0200 Received: by yxh35 with SMTP id 35so1959956yxh.36 for ; Sun, 08 May 2011 19:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type:content-transfer-encoding; bh=mOuq4v7R023AdXjNGMJ4biLjdHg3N+1rr0eqQVDw27c=; b=LhH/RU1r++uhruCrWPjpkFruq6qfOTQ62YDVEVNHUZijEwKgyBZjQHFj8pz7/JSykX RdrsEKS2AiM+gH6+9O/CdczqT4eJDetQuB0zWwB60FreGB0mpukuQtpZ+1r0jpAN90Yj pm/AzprmZxShOMdRafk07SJ6a1KC1lK5M0wbc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=Ruui1TAcLSmfUpNcK2vttOebS/h7hGv3zMRS9MIEXZrzNVVZcTODO2AxyYHzhR+kJO UeXqBkPV9xaNvwRLwyiBb+C62TRIjUzdPoZ7F3QStK1XnMCe82hf/lERwZgSKfhQ4lmd U4WEw7BYE9LAu6ThJRyhIsGg0F1e33bXZorBQ= Received: by 10.90.226.18 with SMTP id y18mr5201051agg.142.1304908743154; Sun, 08 May 2011 19:39:03 -0700 (PDT) MIME-Version: 1.0 Received: by 10.91.54.28 with HTTP; Sun, 8 May 2011 19:38:43 -0700 (PDT) In-Reply-To: <201105081133.50824.sven@narfation.org> References: <1304458235-28473-1-git-send-email-sven@narfation.org> <20110508092403.GB27807@n2100.arm.linux.org.uk> <201105081133.50824.sven@narfation.org> From: Mike Frysinger Date: Sun, 8 May 2011 22:38:43 -0400 Message-ID: Subject: Re: [PATCH] atomic: add *_dec_not_zero To: Sven Eckelmann Cc: Russell King - ARM Linux , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mips@linux-mips.org, linux-m32r@ml.linux-m32r.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org, linux-cris-kernel@axis.com, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, x86@kernel.org, Chris Metcalf , David Howells , linux-m68k@lists.linux-m68k.org, linux-am33-list@redhat.com, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, uclinux-dist-devel@blackfin.uclinux.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29879 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vapier.adi@gmail.com Precedence: bulk X-list: linux-mips On Sun, May 8, 2011 at 05:33, Sven Eckelmann wrote: > Russell King - ARM Linux wrote: > [...] >> Do we need atomic_dec_not_zero() et.al. in every arch header - is there no >> generic header which it could be added to? > > Mike Frysinger already tried to answer it in > : >> that's what asm-generic is for.  if the arch isnt using it, it's >> either because the arch needs to convert to it, or they're using SMP >> and asm-generic doesnt yet support that for atomic.h. >> >> for example, the Blackfin port only needed updating for the SMP case. >> in the non-SMP case, we're getting the def from asm-generic/atomic.h. > > Feel free to change that but I just followed the style used by all other > macros and will not redesign the complete atomic*.h idea. what you're doing is currently correct. i think merging SMP support into asm-generic for atomic* will take a bit of pondering first. -mike From ralf@linux-mips.org Mon May 9 16:27:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 16:27:37 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58610 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491064Ab1EIO1e (ORCPT ); Mon, 9 May 2011 16:27:34 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p49ESTYv012443; Mon, 9 May 2011 15:28:29 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p49ESSiD012440; Mon, 9 May 2011 15:28:28 +0100 Date: Mon, 9 May 2011 15:28:28 +0100 From: Ralf Baechle To: David Daney , linux-mips , GCC , binutils , Prasun Kapoor , rdsandiford@googlemail.com Subject: Re: RFC: A new MIPS64 ABI Message-ID: <20110509142828.GA7196@linux-mips.org> References: <4D5990A4.2050308__41923.1521235362$1297715435$gmane$org@caviumnetworks.com> <87hbbxqihm.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87hbbxqihm.fsf@firetop.home> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29880 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 21, 2011 at 07:45:41PM +0000, Richard Sandiford wrote: > David Daney writes: > > Background: > > > > Current MIPS 32-bit ABIs (both o32 and n32) are restricted to 2GB of > > user virtual memory space. This is due the way MIPS32 memory space is > > segmented. Only the range from 0..2^31-1 is available. Pointer > > values are always sign extended. > > > > Because there are not already enough MIPS ABIs, I present the ... > > > > Proposal: A new ABI to support 4GB of address space with 32-bit > > pointers. > > FWIW, I'd be happy to see this go into GCC. So am I for the kernel primarily because it's not really a new ABI but an enhancement of the existing N32 ABI. Ralf From blogic@openwrt.org Mon May 9 17:48:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 17:48:32 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:60548 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491099Ab1EIPs1 (ORCPT ); Mon, 9 May 2011 17:48:27 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 1/3] MIPS: lantiq: add DMA support Date: Mon, 9 May 2011 17:49:56 +0200 Message-Id: <1304956198-20426-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304956198-20426-1-git-send-email-blogic@openwrt.org> References: <1304956198-20426-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29881 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for the DMA engine found inside the XWAY family of SoCs. The engine has 5 ports and 20 channels. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- Changes in V2 * use spinlocks Changes in V3 * dma is not a platform device .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +- arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 60 +++++ arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/dma.c | 253 ++++++++++++++++++++ 4 files changed, 316 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h create mode 100644 arch/mips/lantiq/xway/dma.c diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 343e82c..4827afb 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -86,7 +86,8 @@ #define LTQ_PPE32_SIZE 0x40000 /* DMA */ -#define LTQ_DMA_BASE_ADDR 0xBE104100 +#define LTQ_DMA_BASE_ADDR 0x1E104100 +#define LTQ_DMA_SIZE 0x800 /* PCI */ #define PCI_CR_BASE_ADDR 0x1E105400 diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h new file mode 100644 index 0000000..872943a --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h @@ -0,0 +1,60 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#ifndef LTQ_DMA_H__ +#define LTQ_DMA_H__ + +#define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ +#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */ + +#define LTQ_DMA_OWN BIT(31) /* owner bit */ +#define LTQ_DMA_C BIT(30) /* complete bit */ +#define LTQ_DMA_SOP BIT(29) /* start of packet */ +#define LTQ_DMA_EOP BIT(28) /* end of packet */ +#define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */ +#define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */ +#define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */ + +struct ltq_dma_desc { + u32 ctl; + u32 addr; +}; + +struct ltq_dma_channel { + int nr; /* the channel number */ + int irq; /* the mapped irq */ + int desc; /* the current descriptor */ + struct ltq_dma_desc *desc_base; /* the descriptor base */ + int phys; /* physical addr */ +}; + +enum { + DMA_PORT_ETOP = 0, + DMA_PORT_DEU, +}; + +extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_open(struct ltq_dma_channel *ch); +extern void ltq_dma_close(struct ltq_dma_channel *ch); +extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch); +extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch); +extern void ltq_dma_free(struct ltq_dma_channel *ch); +extern void ltq_dma_init_port(int p); + +#endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index a021def..d88a3e8 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o +obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c new file mode 100644 index 0000000..4278a45 --- /dev/null +++ b/arch/mips/lantiq/xway/dma.c @@ -0,0 +1,253 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include + +#include +#include + +#define LTQ_DMA_CTRL 0x10 +#define LTQ_DMA_CPOLL 0x14 +#define LTQ_DMA_CS 0x18 +#define LTQ_DMA_CCTRL 0x1C +#define LTQ_DMA_CDBA 0x20 +#define LTQ_DMA_CDLEN 0x24 +#define LTQ_DMA_CIS 0x28 +#define LTQ_DMA_CIE 0x2C +#define LTQ_DMA_PS 0x40 +#define LTQ_DMA_PCTRL 0x44 +#define LTQ_DMA_IRNEN 0xf4 + +#define DMA_DESCPT BIT(3) /* descriptor complete irq */ +#define DMA_TX BIT(8) /* TX channel direction */ +#define DMA_CHAN_ON BIT(0) /* channel on / off bit */ +#define DMA_PDEN BIT(6) /* enable packet drop */ +#define DMA_CHAN_RST BIT(1) /* channel on / off bit */ +#define DMA_RESET BIT(0) /* channel on / off bit */ +#define DMA_IRQ_ACK 0x7e /* IRQ status register */ +#define DMA_POLL BIT(31) /* turn on channel polling */ +#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ +#define DMA_2W_BURST BIT(1) /* 2 word burst length */ +#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ +#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */ +#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ + +#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) +#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y)) +#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ + ltq_dma_membase + (z)) + +static struct resource ltq_dma_resource = { + .name = "dma", + .start = LTQ_DMA_BASE_ADDR, + .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static void __iomem *ltq_dma_membase; + +void +ltq_dma_enable_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_enable_irq); + +void +ltq_dma_disable_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_disable_irq); + +void +ltq_dma_ack_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_ack_irq); + +void +ltq_dma_open(struct ltq_dma_channel *ch) +{ + unsigned long flag; + + local_irq_save(flag); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL); + ltq_dma_enable_irq(ch); + local_irq_restore(flag); +} +EXPORT_SYMBOL_GPL(ltq_dma_open); + +void +ltq_dma_close(struct ltq_dma_channel *ch) +{ + unsigned long flag; + + local_irq_save(flag); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + ltq_dma_disable_irq(ch); + local_irq_restore(flag); +} +EXPORT_SYMBOL_GPL(ltq_dma_close); + +static void +ltq_dma_alloc(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ch->desc = 0; + ch->desc_base = dma_alloc_coherent(NULL, + LTQ_DESC_NUM * LTQ_DESC_SIZE, + &ch->phys, GFP_ATOMIC); + memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE); + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32(ch->phys, LTQ_DMA_CDBA); + ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + wmb(); + ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL); + while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST) + ; + local_irq_restore(flags); +} + +void +ltq_dma_alloc_tx(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ltq_dma_alloc(ch); + + local_irq_save(flags); + ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx); + +void +ltq_dma_alloc_rx(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ltq_dma_alloc(ch); + + local_irq_save(flags); + ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx); + +void +ltq_dma_free(struct ltq_dma_channel *ch) +{ + if (!ch->desc_base) + return; + ltq_dma_close(ch); + dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE, + ch->desc_base, ch->phys); +} +EXPORT_SYMBOL_GPL(ltq_dma_free); + +void +ltq_dma_init_port(int p) +{ + ltq_dma_w32(p, LTQ_DMA_PS); + switch (p) { + case DMA_PORT_ETOP: + /* + * Tell the DMA engine to swap the endianess of data frames and + * drop packets if the channel arbitration fails. + */ + ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN, + LTQ_DMA_PCTRL); + break; + + case DMA_PORT_DEU: + ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2), + LTQ_DMA_PCTRL); + break; + + default: + break; + } +} +EXPORT_SYMBOL_GPL(ltq_dma_init_port); + +int __init +ltq_dma_init(void) +{ + int i; + + /* insert and request the memory region */ + if (insert_resource(&iomem_resource, <q_dma_resource) < 0) + panic("Failed to insert dma memory\n"); + + if (request_mem_region(ltq_dma_resource.start, + resource_size(<q_dma_resource), "dma") < 0) + panic("Failed to request dma memory\n"); + + /* remap dma register range */ + ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, + resource_size(<q_dma_resource)); + if (!ltq_dma_membase) + panic("Failed to remap dma memory\n"); + + /* power up and reset the dma engine */ + ltq_pmu_enable(PMU_DMA); + ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); + + /* disable all interrupts */ + ltq_dma_w32(0, LTQ_DMA_IRNEN); + + /* reset/configure each channel */ + for (i = 0; i < DMA_MAX_CHANNEL; i++) { + ltq_dma_w32(i, LTQ_DMA_CS); + ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); + ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + } + return 0; +} + +postcore_initcall(ltq_dma_init); -- 1.7.2.3 From blogic@openwrt.org Mon May 9 17:48:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 17:48:55 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:60549 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491084Ab1EIPs1 (ORCPT ); Mon, 9 May 2011 17:48:27 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 3/3] MIPS: lantiq: etop board support Date: Mon, 9 May 2011 17:49:58 +0200 Message-Id: <1304956198-20426-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304956198-20426-1-git-send-email-blogic@openwrt.org> References: <1304956198-20426-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29882 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Register the etop platform device inside the machtype specific init code. -- Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org arch/mips/lantiq/xway/mach-easy50712.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c index 5242a27..0cbb30b 100644 --- a/arch/mips/lantiq/xway/mach-easy50712.c +++ b/arch/mips/lantiq/xway/mach-easy50712.c @@ -59,6 +59,10 @@ static struct ltq_pci_data ltq_pci_data = { }, }; +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_MII, +}; + static void __init easy50712_init(void) { ltq_register_gpio(); @@ -66,6 +70,7 @@ static void __init easy50712_init(void) ltq_register_nor(&easy50712_flash_data); ltq_register_wdt(); ltq_register_pci(<q_pci_data); + ltq_register_etop(<q_eth_data); } MIPS_MACHINE(LTQ_MACH_EASY50712, -- 1.7.2.3 From blogic@openwrt.org Mon May 9 17:49:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 17:49:24 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:60552 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491104Ab1EIPsa (ORCPT ); Mon, 9 May 2011 17:48:30 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: [PATCH V3 2/3] MIPS: lantiq: add ethernet driver Date: Mon, 9 May 2011 17:49:57 +0200 Message-Id: <1304956198-20426-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304956198-20426-1-git-send-email-blogic@openwrt.org> References: <1304956198-20426-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29883 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet work. Support for all 8 dma channels, gbit and the embedded switch found on the ar9/vr9 still needs to be implemented. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Acked-by: David S. Miller Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org --- Changes in V2: * use spinlocks * use NAPI * remove duplicate stats counter Changes in V3: * validate the MAC passed inside the platform data * make checkpatch happy .../mips/include/asm/mach-lantiq/lantiq_platform.h | 7 + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +- arch/mips/lantiq/xway/devices.c | 23 + arch/mips/lantiq/xway/devices.h | 2 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/lantiq_etop.c | 805 ++++++++++++++++++++ 7 files changed, 847 insertions(+), 2 deletions(-) create mode 100644 drivers/net/lantiq_etop.c diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h index 1f1dba6..a305f1d 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h @@ -10,6 +10,7 @@ #define _LANTIQ_PLATFORM_H__ #include +#include /* struct used to pass info to the pci core */ enum { @@ -43,4 +44,10 @@ struct ltq_pci_data { int irq[16]; }; +/* struct used to pass info to network drivers */ +struct ltq_eth_data { + struct sockaddr mac; + int mii_mode; +}; + #endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 4827afb..8a3c6be 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -82,8 +82,8 @@ #define PMU_SWITCH 0x10000000 /* ETOP - ethernet */ -#define LTQ_PPE32_BASE_ADDR 0xBE180000 -#define LTQ_PPE32_SIZE 0x40000 +#define LTQ_ETOP_BASE_ADDR 0x1E180000 +#define LTQ_ETOP_SIZE 0x40000 /* DMA */ #define LTQ_DMA_BASE_ADDR 0x1E104100 diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c index 7d58ae5..c257026 100644 --- a/arch/mips/lantiq/xway/devices.c +++ b/arch/mips/lantiq/xway/devices.c @@ -75,3 +75,26 @@ void __init ltq_register_gpio_stp(void) { platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1); } + +/* ethernet */ +static struct resource ltq_etop_resources = { + .name = "etop", + .start = LTQ_ETOP_BASE_ADDR, + .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ltq_etop = { + .name = "ltq_etop", + .resource = <q_etop_resources, + .num_resources = 1, +}; + +void __init +ltq_register_etop(struct ltq_eth_data *eth) +{ + if (eth) { + ltq_etop.dev.platform_data = eth; + platform_device_register(<q_etop); + } +} diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h index 87ba61e..2deb68e 100644 --- a/arch/mips/lantiq/xway/devices.h +++ b/arch/mips/lantiq/xway/devices.h @@ -10,8 +10,10 @@ #define _LTQ_DEVICES_XWAY_H__ #include "../devices.h" +#include extern void ltq_register_gpio(void); extern void ltq_register_gpio_stp(void); +extern void ltq_register_etop(struct ltq_eth_data *eth); #endif diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b30c688..4878587 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2017,6 +2017,13 @@ config FTMAC100 from Faraday. It is used on Faraday A320, Andes AG101 and some other ARM/NDS32 SoC's. +config LANTIQ_ETOP + tristate "Lantiq SoC ETOP driver" + depends on SOC_TYPE_XWAY + help + Support for the MII0 inside the Lantiq SoC + + source "drivers/net/fs_enet/Kconfig" source "drivers/net/octeon/Kconfig" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fbfca11..df71da7 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -261,6 +261,7 @@ obj-$(CONFIG_MLX4_CORE) += mlx4/ obj-$(CONFIG_ENC28J60) += enc28j60.o obj-$(CONFIG_ETHOC) += ethoc.o obj-$(CONFIG_GRETH) += greth.o +obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o diff --git a/drivers/net/lantiq_etop.c b/drivers/net/lantiq_etop.c new file mode 100644 index 0000000..45f252b --- /dev/null +++ b/drivers/net/lantiq_etop.c @@ -0,0 +1,805 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define LTQ_ETOP_MDIO 0x11804 +#define MDIO_REQUEST 0x80000000 +#define MDIO_READ 0x40000000 +#define MDIO_ADDR_MASK 0x1f +#define MDIO_ADDR_OFFSET 0x15 +#define MDIO_REG_MASK 0x1f +#define MDIO_REG_OFFSET 0x10 +#define MDIO_VAL_MASK 0xffff + +#define PPE32_CGEN 0x800 +#define LQ_PPE32_ENET_MAC_CFG 0x1840 + +#define LTQ_ETOP_ENETS0 0x11850 +#define LTQ_ETOP_MAC_DA0 0x1186C +#define LTQ_ETOP_MAC_DA1 0x11870 +#define LTQ_ETOP_CFG 0x16020 +#define LTQ_ETOP_IGPLEN 0x16080 + +#define MAX_DMA_CHAN 0x8 +#define MAX_DMA_CRC_LEN 0x4 +#define MAX_DMA_DATA_LEN 0x600 + +#define ETOP_FTCU BIT(28) +#define ETOP_MII_MASK 0xf +#define ETOP_MII_NORMAL 0xd +#define ETOP_MII_REVERSE 0xe +#define ETOP_PLEN_UNDER 0x40 +#define ETOP_CGEN 0x800 + +/* use 2 static channels for TX/RX */ +#define LTQ_ETOP_TX_CHANNEL 1 +#define LTQ_ETOP_RX_CHANNEL 6 +#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) + +#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) +#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) +#define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +#define DRV_VERSION "1.0" + +static void __iomem *ltq_etop_membase; + +struct ltq_etop_chan { + int idx; + int tx_free; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; + struct sk_buff *skb[LTQ_DESC_NUM]; +}; + +struct ltq_etop_priv { + struct net_device *netdev; + struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + struct phy_device *phydev; + + struct ltq_etop_chan ch[MAX_DMA_CHAN]; + int tx_free[MAX_DMA_CHAN >> 1]; + + spinlock_t lock; +}; + +static int +ltq_etop_alloc_skb(struct ltq_etop_chan *ch) +{ + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, + ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, + DMA_FROM_DEVICE); + ch->dma.desc_base[ch->dma.desc].addr = + CPHYSADDR(ch->skb[ch->dma.desc]->data); + ch->dma.desc_base[ch->dma.desc].ctl = + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | + MAX_DMA_DATA_LEN; + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); + return 0; +} + +static void +ltq_etop_hw_receive(struct ltq_etop_chan *ch) +{ + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + struct sk_buff *skb = ch->skb[ch->dma.desc]; + int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + if (ltq_etop_alloc_skb(ch)) { + netdev_err(ch->netdev, + "failed to allocate new rx buffer, stopping DMA\n"); + ltq_dma_close(&ch->dma); + } + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); + skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); +} + +static int +ltq_etop_poll_rx(struct napi_struct *napi, int budget) +{ + struct ltq_etop_chan *ch = container_of(napi, + struct ltq_etop_chan, napi); + int rx = 0; + int complete = 0; + + while ((rx < budget) && !complete) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + ltq_etop_hw_receive(ch); + rx++; + } else { + complete = 1; + } + } + if (complete || !rx) { + napi_complete(&ch->napi); + ltq_dma_ack_irq(&ch->dma); + } + return rx; +} + +static int +ltq_etop_poll_tx(struct napi_struct *napi, int budget) +{ + struct ltq_etop_chan *ch = + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = + netdev_get_tx_queue(ch->netdev, ch->idx >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, + sizeof(struct ltq_dma_desc)); + ch->tx_free++; + ch->tx_free %= LTQ_DESC_NUM; + } + spin_unlock_irqrestore(&priv->lock, flags); + + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); + ltq_dma_ack_irq(&ch->dma); + return 1; +} + +static irqreturn_t +ltq_etop_dma_irq(int irq, void *_priv) +{ + struct ltq_etop_priv *priv = _priv; + int ch = irq - LTQ_DMA_CH0_INT; + + napi_schedule(&priv->ch[ch].napi); + return IRQ_HANDLED; +} + +static void +ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); + if (IS_RX(ch->idx)) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); + } +} + +static void +ltq_etop_hw_exit(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + + ltq_pmu_disable(PMU_PPE); + for (i = 0; i < MAX_DMA_CHAN; i++) + if (IS_TX(i) || IS_RX(i)) + ltq_etop_free_channel(dev, &priv->ch[i]); +} + +static int +ltq_etop_hw_init(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + + ltq_pmu_enable(PMU_PPE); + + switch (priv->pldata->mii_mode) { + case PHY_INTERFACE_MODE_RMII: + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_REVERSE, LTQ_ETOP_CFG); + break; + + case PHY_INTERFACE_MODE_MII: + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_NORMAL, LTQ_ETOP_CFG); + break; + + default: + netdev_err(dev, "unknown mii mode %d\n", + priv->pldata->mii_mode); + return -ENOTSUPP; + } + + /* enable crc generation */ + ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); + + ltq_dma_init_port(DMA_PORT_ETOP); + + for (i = 0; i < MAX_DMA_CHAN; i++) { + int irq = LTQ_DMA_CH0_INT + i; + struct ltq_etop_chan *ch = &priv->ch[i]; + + ch->idx = ch->dma.nr = i; + + if (IS_TX(i)) { + ltq_dma_alloc_tx(&ch->dma); + request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, + "etop_tx", priv); + } else if (IS_RX(i)) { + ltq_dma_alloc_rx(&ch->dma); + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; + ch->dma.desc++) + if (ltq_etop_alloc_skb(ch)) + return -ENOMEM; + ch->dma.desc = 0; + request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, + "etop_rx", priv); + } + ch->dma.irq = irq; + } + return 0; +} + +static void +ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) +{ + strcpy(info->driver, "Lantiq ETOP"); + strcpy(info->bus_info, "internal"); + strcpy(info->version, DRV_VERSION); +} + +static int +ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + return phy_ethtool_gset(priv->phydev, cmd); +} + +static int +ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + return phy_ethtool_sset(priv->phydev, cmd); +} + +static int +ltq_etop_nway_reset(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + return phy_start_aneg(priv->phydev); +} + +static const struct ethtool_ops ltq_etop_ethtool_ops = { + .get_drvinfo = ltq_etop_get_drvinfo, + .get_settings = ltq_etop_get_settings, + .set_settings = ltq_etop_set_settings, + .nway_reset = ltq_etop_nway_reset, +}; + +static int +ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) +{ + u32 val = MDIO_REQUEST | + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + ltq_etop_w32(val, LTQ_ETOP_MDIO); + return 0; +} + +static int +ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) +{ + u32 val = MDIO_REQUEST | MDIO_READ | + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + ltq_etop_w32(val, LTQ_ETOP_MDIO); + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; + return val; +} + +static void +ltq_etop_mdio_link(struct net_device *dev) +{ + /* nothing to do */ +} + +static int +ltq_etop_mdio_probe(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; + int phy_addr; + + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (priv->mii_bus->phy_map[phy_addr]) { + phydev = priv->mii_bus->phy_map[phy_addr]; + break; + } + } + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); + return -ENODEV; + } + + phydev = phy_connect(dev, dev_name(&phydev->dev), <q_etop_mdio_link, + 0, priv->pldata->mii_mode); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + + phydev->supported &= (SUPPORTED_10baseT_Half + | SUPPORTED_10baseT_Full + | SUPPORTED_100baseT_Half + | SUPPORTED_100baseT_Full + | SUPPORTED_Autoneg + | SUPPORTED_MII + | SUPPORTED_TP); + + phydev->advertising = phydev->supported; + priv->phydev = phydev; + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", + dev->name, phydev->drv->name, + dev_name(&phydev->dev), phydev->irq); + + return 0; +} + +static int +ltq_etop_mdio_init(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + int err; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { + netdev_err(dev, "failed to allocate mii bus\n"); + err = -ENOMEM; + goto err_out; + } + + priv->mii_bus->priv = dev; + priv->mii_bus->read = ltq_etop_mdio_rd; + priv->mii_bus->write = ltq_etop_mdio_wr; + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); + priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); + if (!priv->mii_bus->irq) { + err = -ENOMEM; + goto err_out_free_mdiobus; + } + + for (i = 0; i < PHY_MAX_ADDR; ++i) + priv->mii_bus->irq[i] = PHY_POLL; + + if (mdiobus_register(priv->mii_bus)) { + err = -ENXIO; + goto err_out_free_mdio_irq; + } + + if (ltq_etop_mdio_probe(dev)) { + err = -ENXIO; + goto err_out_unregister_bus; + } + return 0; + +err_out_unregister_bus: + mdiobus_unregister(priv->mii_bus); +err_out_free_mdio_irq: + kfree(priv->mii_bus->irq); +err_out_free_mdiobus: + mdiobus_free(priv->mii_bus); +err_out: + return err; +} + +static void +ltq_etop_mdio_cleanup(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + phy_disconnect(priv->phydev); + mdiobus_unregister(priv->mii_bus); + kfree(priv->mii_bus->irq); + mdiobus_free(priv->mii_bus); +} + +static int +ltq_etop_open(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + + for (i = 0; i < MAX_DMA_CHAN; i++) { + struct ltq_etop_chan *ch = &priv->ch[i]; + + if (!IS_TX(i) && (!IS_RX(i))) + continue; + ltq_dma_open(&ch->dma); + napi_enable(&ch->napi); + } + phy_start(priv->phydev); + netif_tx_start_all_queues(dev); + return 0; +} + +static int +ltq_etop_stop(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int i; + + netif_tx_stop_all_queues(dev); + phy_stop(priv->phydev); + for (i = 0; i < MAX_DMA_CHAN; i++) { + struct ltq_etop_chan *ch = &priv->ch[i]; + + if (!IS_RX(i) && !IS_TX(i)) + continue; + napi_disable(&ch->napi); + ltq_dma_close(&ch->dma); + } + return 0; +} + +static int +ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) +{ + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); + struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + int len; + unsigned long flags; + u32 byte_offset; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { + dev_kfree_skb_any(skb); + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; + } + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; + ch->skb[ch->dma.desc] = skb; + + dev->trans_start = jiffies; + + spin_lock_irqsave(&priv->lock, flags); + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, + DMA_TO_DEVICE)) - byte_offset; + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + + if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +} + +static int +ltq_etop_change_mtu(struct net_device *dev, int new_mtu) +{ + int ret = eth_change_mtu(dev, new_mtu); + + if (!ret) { + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, + LTQ_ETOP_IGPLEN); + spin_unlock_irqrestore(&priv->lock, flags); + } + return ret; +} + +static int +ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ + return phy_mii_ioctl(priv->phydev, rq, cmd); +} + +static int +ltq_etop_set_mac_address(struct net_device *dev, void *p) +{ + int ret = eth_mac_addr(dev, p); + + if (!ret) { + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; + + /* store the mac for the unicast filter */ + spin_lock_irqsave(&priv->lock, flags); + ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); + ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, + LTQ_ETOP_MAC_DA1); + spin_unlock_irqrestore(&priv->lock, flags); + } + return ret; +} + +static void +ltq_etop_set_multicast_list(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; + + /* ensure that the unicast filter is not enabled in promiscious mode */ + spin_lock_irqsave(&priv->lock, flags); + if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) + ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); + else + ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static u16 +ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb) +{ + /* we are currently only using the first queue */ + return 0; +} + +static int +ltq_etop_init(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + struct sockaddr mac; + int err; + + ether_setup(dev); + dev->watchdog_timeo = 10 * HZ; + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + if (!is_valid_ether_addr(mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + random_ether_addr(mac.sa_data); + } + + err = ltq_etop_set_mac_address(dev, &mac); + if (err) + goto err_netdev; + ltq_etop_set_multicast_list(dev); + err = ltq_etop_mdio_init(dev); + if (err) + goto err_netdev; + return 0; + +err_netdev: + unregister_netdev(dev); + free_netdev(dev); +err_hw: + ltq_etop_hw_exit(dev); + return err; +} + +static void +ltq_etop_tx_timeout(struct net_device *dev) +{ + int err; + + ltq_etop_hw_exit(dev); + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; + dev->trans_start = jiffies; + netif_wake_queue(dev); + return; + +err_hw: + ltq_etop_hw_exit(dev); + netdev_err(dev, "failed to restart etop after TX timeout\n"); +} + +static const struct net_device_ops ltq_eth_netdev_ops = { + .ndo_open = ltq_etop_open, + .ndo_stop = ltq_etop_stop, + .ndo_start_xmit = ltq_etop_tx, + .ndo_change_mtu = ltq_etop_change_mtu, + .ndo_do_ioctl = ltq_etop_ioctl, + .ndo_set_mac_address = ltq_etop_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_multicast_list = ltq_etop_set_multicast_list, + .ndo_select_queue = ltq_etop_select_queue, + .ndo_init = ltq_etop_init, + .ndo_tx_timeout = ltq_etop_tx_timeout, +}; + +static int __init +ltq_etop_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct ltq_etop_priv *priv; + struct resource *res; + int err; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get etop resource\n"); + err = -ENOENT; + goto err_out; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request etop resource\n"); + err = -EBUSY; + goto err_out; + } + + ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_etop_membase) { + dev_err(&pdev->dev, "failed to remap etop engine %d\n", + pdev->id); + err = -ENOMEM; + goto err_out; + } + + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; + dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; + spin_lock_init(&priv->lock); + + for (i = 0; i < MAX_DMA_CHAN; i++) { + if (IS_TX(i)) + netif_napi_add(dev, &priv->ch[i].napi, + ltq_etop_poll_tx, 8); + else if (IS_RX(i)) + netif_napi_add(dev, &priv->ch[i].napi, + ltq_etop_poll_rx, 32); + priv->ch[i].netdev = dev; + } + + err = register_netdev(dev); + if (err) + goto err_free; + + platform_set_drvdata(pdev, dev); + return 0; + +err_free: + kfree(dev); +err_out: + return err; +} + +static int __devexit +ltq_etop_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (dev) { + netif_tx_stop_all_queues(dev); + ltq_etop_hw_exit(dev); + ltq_etop_mdio_cleanup(dev); + unregister_netdev(dev); + } + return 0; +} + +static struct platform_driver ltq_mii_driver = { + .remove = __devexit_p(ltq_etop_remove), + .driver = { + .name = "ltq_etop", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_etop(void) +{ + int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); + + if (ret) + pr_err("ltq_etop: Error registering platfom driver!"); + return ret; +} + +static void __exit +exit_ltq_etop(void) +{ + platform_driver_unregister(<q_mii_driver); +} + +module_init(init_ltq_etop); +module_exit(exit_ltq_etop); + +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC ETOP"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 From blogic@openwrt.org Mon May 9 18:47:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 18:47:43 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:45252 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491037Ab1EIQrj (ORCPT ); Mon, 9 May 2011 18:47:39 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org Subject: [PATCH 4/4] MIPS: lantiq: add a soc specific setup function Date: Mon, 9 May 2011 18:49:10 +0200 Message-Id: <1304959750-8557-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304959750-8557-1-git-send-email-blogic@openwrt.org> References: <1304959750-8557-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29884 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Add a setup-.c file for every xway variant. This file is responsible for registering the basic platform devices, that are always present. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/prom.h | 1 + arch/mips/lantiq/setup.c | 4 ++-- arch/mips/lantiq/xway/Makefile | 4 ++-- arch/mips/lantiq/xway/setup-ase.c | 19 +++++++++++++++++++ arch/mips/lantiq/xway/setup-xway.c | 20 ++++++++++++++++++++ 5 files changed, 44 insertions(+), 4 deletions(-) create mode 100644 arch/mips/lantiq/xway/setup-ase.c create mode 100644 arch/mips/lantiq/xway/setup-xway.c diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h index 4165ad1..b4229d9 100644 --- a/arch/mips/lantiq/prom.h +++ b/arch/mips/lantiq/prom.h @@ -20,5 +20,6 @@ struct ltq_soc_info { }; extern void ltq_soc_detect(struct ltq_soc_info *i); +extern void ltq_soc_setup(void); #endif diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c index 1d99b2b..2f27f58 100644 --- a/arch/mips/lantiq/setup.c +++ b/arch/mips/lantiq/setup.c @@ -16,6 +16,7 @@ #include "machtypes.h" #include "devices.h" +#include "prom.h" void __init plat_mem_setup(void) { @@ -45,8 +46,7 @@ void __init plat_mem_setup(void) static int __init lantiq_setup(void) { - ltq_register_asc(0); - ltq_register_asc(1); + ltq_soc_setup(); mips_machine_setup(); return 0; } diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index d88a3e8..c517f2e 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,7 +1,7 @@ obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c new file mode 100644 index 0000000..f6f3267 --- /dev/null +++ b/arch/mips/lantiq/xway/setup-ase.c @@ -0,0 +1,19 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 John Crispin + */ + +#include + +#include "../prom.h" +#include "devices.h" + +void __init ltq_soc_setup(void) +{ + ltq_register_ase_asc(); + ltq_register_gpio(); + ltq_register_wdt(); +} diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c new file mode 100644 index 0000000..c292f64 --- /dev/null +++ b/arch/mips/lantiq/xway/setup-xway.c @@ -0,0 +1,20 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 John Crispin + */ + +#include + +#include "../prom.h" +#include "devices.h" + +void __init ltq_soc_setup(void) +{ + ltq_register_asc(0); + ltq_register_asc(1); + ltq_register_gpio(); + ltq_register_wdt(); +} -- 1.7.2.3 From blogic@openwrt.org Mon May 9 18:48:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 18:48:09 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:45254 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491084Ab1EIQrj (ORCPT ); Mon, 9 May 2011 18:47:39 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org Subject: [PATCH 2/4] MIPS: lantiq: adds Amazon SE serial port platform device Date: Mon, 9 May 2011 18:49:08 +0200 Message-Id: <1304959750-8557-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304959750-8557-1-git-send-email-blogic@openwrt.org> References: <1304959750-8557-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29885 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Amazon SE only has 1 serial port. We use a seperate function to register the platform device as the IRQ mappings also differ. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org --- .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 4 +++ arch/mips/lantiq/xway/devices.c | 21 ++++++++++++++++++++ arch/mips/lantiq/xway/devices.h | 1 + 3 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h index 5c81c98..b4465a8 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -21,6 +21,10 @@ #define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) #define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) +#define LTQ_ASC_ASE_TIR INT_NUM_IM2_IRL0 +#define LTQ_ASC_ASE_RIR (INT_NUM_IM2_IRL0 + 2) +#define LTQ_ASC_ASE_EIR (INT_NUM_IM2_IRL0 + 3) + #define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15) #define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14) #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16) diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c index c257026..2fd1733 100644 --- a/arch/mips/lantiq/xway/devices.c +++ b/arch/mips/lantiq/xway/devices.c @@ -29,6 +29,8 @@ #include #include +#include "devices.h" + /* gpio */ static struct resource ltq_gpio_resource[] = { { @@ -98,3 +100,22 @@ ltq_register_etop(struct ltq_eth_data *eth) platform_device_register(<q_etop); } } + +/* asc ports - amazon se has its own serial mapping */ +static struct resource ltq_ase_asc_resources[] = { + { + .name = "asc0", + .start = LTQ_ASC1_BASE_ADDR, + .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + IRQ_RES(tx, LTQ_ASC_ASE_TIR), + IRQ_RES(rx, LTQ_ASC_ASE_RIR), + IRQ_RES(err, LTQ_ASC_ASE_EIR), +}; + +void __init ltq_register_ase_asc(void) +{ + platform_device_register_simple("ltq_asc", 0, + ltq_ase_asc_resources, ARRAY_SIZE(ltq_ase_asc_resources)); +} diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h index 2deb68e..e904934 100644 --- a/arch/mips/lantiq/xway/devices.h +++ b/arch/mips/lantiq/xway/devices.h @@ -14,6 +14,7 @@ extern void ltq_register_gpio(void); extern void ltq_register_gpio_stp(void); +extern void ltq_register_ase_asc(void); extern void ltq_register_etop(struct ltq_eth_data *eth); #endif -- 1.7.2.3 From blogic@openwrt.org Mon May 9 18:48:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 18:48:33 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:45256 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491099Ab1EIQrj (ORCPT ); Mon, 9 May 2011 18:47:39 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org Subject: [PATCH 1/4] MIPS: lantiq: move IRQ_RES macro to a headerfile Date: Mon, 9 May 2011 18:49:07 +0200 Message-Id: <1304959750-8557-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304959750-8557-1-git-send-email-blogic@openwrt.org> References: <1304959750-8557-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29886 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips The IRQ_RES macro should be located at a place where other *.c files can easily reuse it. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/devices.c | 3 --- arch/mips/lantiq/devices.h | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c index e758863..7b82c34 100644 --- a/arch/mips/lantiq/devices.c +++ b/arch/mips/lantiq/devices.c @@ -28,9 +28,6 @@ #include "devices.h" -#define IRQ_RES(resname, irq) \ - {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} - /* nor flash */ static struct resource ltq_nor_resource = { .name = "nor", diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h index 069006c..2947bb1 100644 --- a/arch/mips/lantiq/devices.h +++ b/arch/mips/lantiq/devices.h @@ -12,6 +12,9 @@ #include #include +#define IRQ_RES(resname, irq) \ + {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} + extern void ltq_register_nor(struct physmap_flash_data *data); extern void ltq_register_wdt(void); extern void ltq_register_asc(int port); -- 1.7.2.3 From blogic@openwrt.org Mon May 9 18:48:52 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 18:48:56 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:45260 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491104Ab1EIQrj (ORCPT ); Mon, 9 May 2011 18:47:39 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , linux-mips@linux-mips.org Subject: [PATCH 3/4] MIPS: lantiq: cleanup machine specific files Date: Mon, 9 May 2011 18:49:09 +0200 Message-Id: <1304959750-8557-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1304959750-8557-1-git-send-email-blogic@openwrt.org> References: <1304959750-8557-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29887 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips The platform driver register functions called in every machine init function get moved to setup-.c. Also remove superflous pci register call from Amazon SE machine code as the device and driver are not present on ASE. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/xway/mach-easy50601.c | 8 -------- arch/mips/lantiq/xway/mach-easy50712.c | 2 -- 2 files changed, 0 insertions(+), 10 deletions(-) diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c index 34a41d9..0002128 100644 --- a/arch/mips/lantiq/xway/mach-easy50601.c +++ b/arch/mips/lantiq/xway/mach-easy50601.c @@ -50,17 +50,9 @@ static struct physmap_flash_data easy50601_flash_data = { #endif }; -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_INT, - .req_mask = 0xf, -}; - static void __init easy50601_init(void) { - ltq_register_gpio(); ltq_register_nor(&easy50601_flash_data); - ltq_register_wdt(); - ltq_register_pci(<q_pci_data); } MIPS_MACHINE(LTQ_MACH_EASY50601, diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c index 0cbb30b..2512561 100644 --- a/arch/mips/lantiq/xway/mach-easy50712.c +++ b/arch/mips/lantiq/xway/mach-easy50712.c @@ -65,10 +65,8 @@ static struct ltq_eth_data ltq_eth_data = { static void __init easy50712_init(void) { - ltq_register_gpio(); ltq_register_gpio_stp(); ltq_register_nor(&easy50712_flash_data); - ltq_register_wdt(); ltq_register_pci(<q_pci_data); ltq_register_etop(<q_eth_data); } -- 1.7.2.3 From ralf@linux-mips.org Mon May 9 19:06:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 19:06:51 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35942 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491037Ab1EIRGs (ORCPT ); Mon, 9 May 2011 19:06:48 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p49H85M1026181; Mon, 9 May 2011 18:08:05 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p49H85bc026179; Mon, 9 May 2011 18:08:05 +0100 Date: Mon, 9 May 2011 18:08:04 +0100 From: Ralf Baechle To: John Crispin Cc: Ralph Hempel , linux-mips@linux-mips.org Subject: Re: [PATCH V3 1/3] MIPS: lantiq: add DMA support Message-ID: <20110509170804.GA23471@linux-mips.org> References: <1304956198-20426-1-git-send-email-blogic@openwrt.org> <1304956198-20426-2-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304956198-20426-2-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29888 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Mon May 9 19:07:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 19:07:17 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35946 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491099Ab1EIRG6 (ORCPT ); Mon, 9 May 2011 19:06:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p49H8DRC026195; Mon, 9 May 2011 18:08:13 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p49H8C2P026194; Mon, 9 May 2011 18:08:12 +0100 Date: Mon, 9 May 2011 18:08:12 +0100 From: Ralf Baechle To: John Crispin Cc: Ralph Hempel , linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH V3 2/3] MIPS: lantiq: add ethernet driver Message-ID: <20110509170812.GB23471@linux-mips.org> References: <1304956198-20426-1-git-send-email-blogic@openwrt.org> <1304956198-20426-3-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304956198-20426-3-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29889 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Mon May 9 19:07:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 19:07:38 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35953 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491101Ab1EIRHH (ORCPT ); Mon, 9 May 2011 19:07:07 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p49H8N4D026217; Mon, 9 May 2011 18:08:23 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p49H8NuJ026216; Mon, 9 May 2011 18:08:23 +0100 Date: Mon, 9 May 2011 18:08:23 +0100 From: Ralf Baechle To: John Crispin Cc: Ralph Hempel , linux-mips@linux-mips.org Subject: Re: [PATCH V3 3/3] MIPS: lantiq: etop board support Message-ID: <20110509170823.GC23471@linux-mips.org> References: <1304956198-20426-1-git-send-email-blogic@openwrt.org> <1304956198-20426-4-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304956198-20426-4-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29890 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From blogic@openwrt.org Mon May 9 19:08:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 19:09:00 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:34909 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491101Ab1EIRIz (ORCPT ); Mon, 9 May 2011 19:08:55 +0200 Message-ID: <4DC8200B.2050501@openwrt.org> Date: Mon, 09 May 2011 19:10:35 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: Ralf Baechle CC: Ralph Hempel , linux-mips@linux-mips.org Subject: Re: [PATCH V3 1/3] MIPS: lantiq: add DMA support References: <1304956198-20426-1-git-send-email-blogic@openwrt.org> <1304956198-20426-2-git-send-email-blogic@openwrt.org> <20110509170804.GA23471@linux-mips.org> In-Reply-To: <20110509170804.GA23471@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29891 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips On 09/05/11 19:08, Ralf Baechle wrote: > Queued for 2.6.40. > > Thanks, > > Ralf > > > thank you ! From David.Daney@caviumnetworks.com Mon May 9 19:47:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 May 2011 19:47:20 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:2630 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491084Ab1EIRrP (ORCPT ); Mon, 9 May 2011 19:47:15 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 09 May 2011 10:48:10 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 9 May 2011 10:47:08 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 9 May 2011 10:47:08 -0700 Message-ID: <4DC82897.7020206@caviumnetworks.com> Date: Mon, 09 May 2011 10:47:03 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips , GCC , binutils , Prasun Kapoor , rdsandiford@googlemail.com Subject: Re: RFC: A new MIPS64 ABI References: <4D5990A4.2050308__41923.1521235362$1297715435$gmane$org@caviumnetworks.com> <87hbbxqihm.fsf@firetop.home> <20110509142828.GA7196@linux-mips.org> In-Reply-To: <20110509142828.GA7196@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 09 May 2011 17:47:08.0570 (UTC) FILETIME=[1E152FA0:01CC0E71] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29892 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 05/09/2011 07:28 AM, Ralf Baechle wrote: > On Mon, Feb 21, 2011 at 07:45:41PM +0000, Richard Sandiford wrote: > >> David Daney writes: >>> Background: >>> >>> Current MIPS 32-bit ABIs (both o32 and n32) are restricted to 2GB of >>> user virtual memory space. This is due the way MIPS32 memory space is >>> segmented. Only the range from 0..2^31-1 is available. Pointer >>> values are always sign extended. >>> >>> Because there are not already enough MIPS ABIs, I present the ... >>> >>> Proposal: A new ABI to support 4GB of address space with 32-bit >>> pointers. >> >> FWIW, I'd be happy to see this go into GCC. > > So am I for the kernel primarily because it's not really a new ABI but > an enhancement of the existing N32 ABI. > The patches are resting peacefully on my laptop. Now with endorcements like these, I may be forced to actually finish them... David Daney From ralf@linux-mips.org Tue May 10 16:22:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 16:22:41 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59584 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491092Ab1EJOWi (ORCPT ); Tue, 10 May 2011 16:22:38 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AENxLf015747; Tue, 10 May 2011 15:24:00 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AENxLB015745; Tue, 10 May 2011 15:23:59 +0100 Date: Tue, 10 May 2011 15:23:59 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/4] MIPS: lantiq: move IRQ_RES macro to a headerfile Message-ID: <20110510142359.GA15184@linux-mips.org> References: <1304959750-8557-1-git-send-email-blogic@openwrt.org> <1304959750-8557-2-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304959750-8557-2-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29893 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips As discussed folded into the existing series in linux-queue. Could you please check if the result is making sense? Thanks, Ralf From ralf@linux-mips.org Tue May 10 16:22:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 16:23:04 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59587 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491782Ab1EJOWo (ORCPT ); Tue, 10 May 2011 16:22:44 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AEO728015767; Tue, 10 May 2011 15:24:07 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AEO7EJ015766; Tue, 10 May 2011 15:24:07 +0100 Date: Tue, 10 May 2011 15:24:07 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/4] MIPS: lantiq: adds Amazon SE serial port platform device Message-ID: <20110510142407.GB15184@linux-mips.org> References: <1304959750-8557-1-git-send-email-blogic@openwrt.org> <1304959750-8557-3-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304959750-8557-3-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29894 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips As discussed folded into the existing series in linux-queue. Could you please check if the result is making sense? Thanks, Ralf From ralf@linux-mips.org Tue May 10 16:23:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 16:23:27 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59590 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491795Ab1EJOWv (ORCPT ); Tue, 10 May 2011 16:22:51 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AEOE1I015780; Tue, 10 May 2011 15:24:14 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AEODmc015779; Tue, 10 May 2011 15:24:13 +0100 Date: Tue, 10 May 2011 15:24:13 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/4] MIPS: lantiq: cleanup machine specific files Message-ID: <20110510142413.GC15184@linux-mips.org> References: <1304959750-8557-1-git-send-email-blogic@openwrt.org> <1304959750-8557-4-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304959750-8557-4-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29895 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips As discussed folded into the existing series in linux-queue. Could you please check if the result is making sense? Thanks, Ralf From ralf@linux-mips.org Tue May 10 16:23:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 16:23:52 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59593 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491802Ab1EJOW6 (ORCPT ); Tue, 10 May 2011 16:22:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AEOL5A015793; Tue, 10 May 2011 15:24:21 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AEOLRp015792; Tue, 10 May 2011 15:24:21 +0100 Date: Tue, 10 May 2011 15:24:21 +0100 From: Ralf Baechle To: John Crispin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 4/4] MIPS: lantiq: add a soc specific setup function Message-ID: <20110510142421.GD15184@linux-mips.org> References: <1304959750-8557-1-git-send-email-blogic@openwrt.org> <1304959750-8557-5-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304959750-8557-5-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29896 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips As discussed folded into the existing series in linux-queue. Could you please check if the result is making sense? Thanks, Ralf From ralf@linux-mips.org Tue May 10 16:59:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 16:59:43 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40520 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491795Ab1EJO7k (ORCPT ); Tue, 10 May 2011 16:59:40 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF11Sm021914; Tue, 10 May 2011 16:01:01 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF11Cw021892; Tue, 10 May 2011 16:01:01 +0100 Date: Tue, 10 May 2011 16:01:01 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 1/9] MIPS: DB1200: Set Config[OD] for improved stability. Message-ID: <20110510150101.GA21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-2-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-2-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29897 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Tue May 10 17:00:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:00:09 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40525 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491808Ab1EJO76 (ORCPT ); Tue, 10 May 2011 16:59:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF1IYd021943; Tue, 10 May 2011 16:01:18 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF1Iar021942; Tue, 10 May 2011 16:01:18 +0100 Date: Tue, 10 May 2011 16:01:18 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 2/9] MIPS: Alchemy: update inlinable GPIO API Message-ID: <20110510150117.GB21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-3-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-3-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29898 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Tue May 10 17:00:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:00:34 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40530 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491795Ab1EJPAE (ORCPT ); Tue, 10 May 2011 17:00:04 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF1P5a021957; Tue, 10 May 2011 16:01:25 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF1PbY021955; Tue, 10 May 2011 16:01:25 +0100 Date: Tue, 10 May 2011 16:01:25 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 3/9] MIPS: Alchemy: irq code and constant cleanup Message-ID: <20110510150125.GC21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-4-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-4-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29899 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Tue May 10 17:00:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:01:00 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40535 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491814Ab1EJPAK (ORCPT ); Tue, 10 May 2011 17:00:10 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF1V2I021969; Tue, 10 May 2011 16:01:31 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF1VrL021968; Tue, 10 May 2011 16:01:31 +0100 Date: Tue, 10 May 2011 16:01:31 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 4/9] MIPS: Alchemy: convert irq.c to syscore_ops. Message-ID: <20110510150131.GD21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-5-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-5-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29900 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Tue May 10 17:01:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:01:24 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40540 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491815Ab1EJPA0 (ORCPT ); Tue, 10 May 2011 17:00:26 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF1lOf021991; Tue, 10 May 2011 16:01:47 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF1lNk021990; Tue, 10 May 2011 16:01:47 +0100 Date: Tue, 10 May 2011 16:01:47 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 5/9] MIPS: Alchemy: convert dbdma.c to syscore_ops Message-ID: <20110510150147.GE21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-6-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-6-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29901 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40, Ralf From ralf@linux-mips.org Tue May 10 17:01:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:01:46 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40545 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491816Ab1EJPAd (ORCPT ); Tue, 10 May 2011 17:00:33 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF1stm022004; Tue, 10 May 2011 16:01:54 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF1smk022003; Tue, 10 May 2011 16:01:54 +0100 Date: Tue, 10 May 2011 16:01:54 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 6/9] MIPS: Alchemy: rewrite UART setup and constants. Message-ID: <20110510150154.GF21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-7-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-7-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29902 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40, Ralf From ralf@linux-mips.org Tue May 10 17:02:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:02:12 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40550 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491818Ab1EJPAk (ORCPT ); Tue, 10 May 2011 17:00:40 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF21cf022017; Tue, 10 May 2011 16:02:01 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF21Es022016; Tue, 10 May 2011 16:02:01 +0100 Date: Tue, 10 May 2011 16:02:01 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 7/9] MIPS: Alchemy: rewrite ethernet platform setup Message-ID: <20110510150201.GG21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-8-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-8-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29903 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40, Ralf From ralf@linux-mips.org Tue May 10 17:02:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:02:35 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40555 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491819Ab1EJPAs (ORCPT ); Tue, 10 May 2011 17:00:48 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF28Lf022037; Tue, 10 May 2011 16:02:08 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF28aV022036; Tue, 10 May 2011 16:02:08 +0100 Date: Tue, 10 May 2011 16:02:08 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 8/9] MIPS: Alchemy: cleanup DMA addresses Message-ID: <20110510150208.GH21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-9-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-9-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29904 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40, Ralf From ralf@linux-mips.org Tue May 10 17:02:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:02:57 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40560 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491820Ab1EJPBR (ORCPT ); Tue, 10 May 2011 17:01:17 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AF2cdA022073; Tue, 10 May 2011 16:02:38 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AF2cEb022072; Tue, 10 May 2011 16:02:38 +0100 Date: Tue, 10 May 2011 16:02:38 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Subject: Re: [PATCH 9/9] MIPS: Alchemy: clean up GPIO registers and accessors Message-ID: <20110510150238.GI21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-10-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304844140-3259-10-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29905 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40 - but you really should cc the watchdog folks, too! Ralf From ralf@linux-mips.org Tue May 10 17:26:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:26:08 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:34800 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491819Ab1EJP0F (ORCPT ); Tue, 10 May 2011 17:26:05 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AFRCtD027060; Tue, 10 May 2011 16:27:12 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AFRBxn027057; Tue, 10 May 2011 16:27:11 +0100 Date: Tue, 10 May 2011 16:27:11 +0100 From: Ralf Baechle To: Jonas Gorski Cc: Hauke Mehrtens , linux-mips@linux-mips.org, Michael Buesch , netdev@vger.kernel.org, Florian Fainelli Subject: Re: [PATCH 1/5] ssb: Change fallback sprom to callback mechanism. Message-ID: <20110510152711.GA26759@linux-mips.org> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> <1304771263-10937-2-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29906 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, May 07, 2011 at 07:24:18PM +0200, Jonas Gorski wrote: > just some small small spelling nit-picks: > > CC: Michael Buesch > > CC: netdev@vger.kernel.org > > CC: Florian Fainelli > > Signed-off-by: Hauke Mehrtens Michael, can I have an Ack for this patch assuming the raised spelling issues will get fixed? Thanks, Ralf From ralf@linux-mips.org Tue May 10 17:26:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:26:42 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:34805 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491822Ab1EJP0f (ORCPT ); Tue, 10 May 2011 17:26:35 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AFRvdw027112; Tue, 10 May 2011 16:27:57 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AFRvGj027111; Tue, 10 May 2011 16:27:57 +0100 Date: Tue, 10 May 2011 16:27:57 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 0/5] MIPS: BCM47xx: Enhancements in Parsing the NVRAM data Message-ID: <20110510152757.GB26759@linux-mips.org> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29907 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips I assume you're going to resend the series with the raised issues fixed so I'll drop the entire series for now. Thanks! Ralf From m@bues.ch Tue May 10 17:28:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:28:22 +0200 (CEST) Received: from 80-190-117-144.ip-home.de ([80.190.117.144]:43563 "EHLO bues.ch" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491819Ab1EJP2S (ORCPT ); Tue, 10 May 2011 17:28:18 +0200 Received: by bues.ch with esmtpsa (Exim 4.69) (envelope-from ) id 1QJor7-00016V-Ul; Tue, 10 May 2011 17:28:14 +0200 Subject: Re: [PATCH 1/5] ssb: Change fallback sprom to callback mechanism. From: Michael =?ISO-8859-1?Q?B=FCsch?= To: Ralf Baechle Cc: Jonas Gorski , Hauke Mehrtens , linux-mips@linux-mips.org, Michael Buesch , netdev@vger.kernel.org, Florian Fainelli In-Reply-To: <20110510152711.GA26759@linux-mips.org> References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> <1304771263-10937-2-git-send-email-hauke@hauke-m.de> <20110510152711.GA26759@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Tue, 10 May 2011 17:28:06 +0200 Message-ID: <1305041286.29322.2.camel@maggie> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29908 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m@bues.ch Precedence: bulk X-list: linux-mips On Tue, 2011-05-10 at 16:27 +0100, Ralf Baechle wrote: > On Sat, May 07, 2011 at 07:24:18PM +0200, Jonas Gorski wrote: > > > just some small small spelling nit-picks: > > > > CC: Michael Buesch > > > CC: netdev@vger.kernel.org > > > CC: Florian Fainelli > > > Signed-off-by: Hauke Mehrtens > > Michael, > > can I have an Ack for this patch assuming the raised spelling issues will > get fixed? Thanks, I'd still prefer a platform-data based mechanism, but this would be much more intrusive. So yeah. ACK, for the time being. -- Greetings Michael. From hauke@hauke-m.de Tue May 10 17:29:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:29:41 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:40830 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491822Ab1EJP3j (ORCPT ); Tue, 10 May 2011 17:29:39 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 30B7D8ACA; Tue, 10 May 2011 17:29:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DjaS+xO+T6bh; Tue, 10 May 2011 17:29:31 +0200 (CEST) Received: from [192.168.0.151] (dyndsl-095-033-240-207.ewe-ip-backbone.de [95.33.240.207]) by hauke-m.de (Postfix) with ESMTPSA id 4AF4E8AC9; Tue, 10 May 2011 17:29:31 +0200 (CEST) Message-ID: <4DC959DA.6050904@hauke-m.de> Date: Tue, 10 May 2011 17:29:30 +0200 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110424 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH 0/5] MIPS: BCM47xx: Enhancements in Parsing the NVRAM data References: <1304771263-10937-1-git-send-email-hauke@hauke-m.de> <20110510152757.GB26759@linux-mips.org> In-Reply-To: <20110510152757.GB26759@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29909 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips On 05/10/2011 05:27 PM, Ralf Baechle wrote: > I assume you're going to resend the series with the raised issues fixed > so I'll drop the entire series for now. > > Thanks! > > Ralf Hi Ralf, yes I will fix the raised spelling issues and the checkpatch warnings and resend it today. Hauke From ralf@linux-mips.org Tue May 10 17:45:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 17:45:13 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47251 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491819Ab1EJPpK (ORCPT ); Tue, 10 May 2011 17:45:10 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4AFjE0N028464; Tue, 10 May 2011 16:45:14 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4AFiADj028391; Tue, 10 May 2011 16:44:10 +0100 Date: Tue, 10 May 2011 16:44:10 +0100 From: Ralf Baechle To: Stephen Boyd Cc: Andrew Morton , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-m32r@ml.linux-m32r.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Chris Metcalf , user-mode-linux-devel@lists.sourceforge.net, x86@kernel.org Subject: Re: [PATCH] lib: Consolidate DEBUG_STACK_USAGE option Message-ID: <20110510154410.GD26759@linux-mips.org> References: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304747831-2098-1-git-send-email-sboyd@codeaurora.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29910 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, May 06, 2011 at 10:57:11PM -0700, Stephen Boyd wrote: Acked-by: Ralf Baechle Ralf From manuel.lauss@googlemail.com Tue May 10 21:07:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 21:07:28 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:57720 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491029Ab1EJTHZ (ORCPT ); Tue, 10 May 2011 21:07:25 +0200 Received: by wwb17 with SMTP id 17so5994052wwb.24 for ; Tue, 10 May 2011 12:07:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=jeHDt++L+o5mWVl6V9Vi4nM5Gbl+VXb5OzHLmY65RN4=; b=QIYAdl8d48Dqm40TxYg/rpgZVpKXPYp/nSb5tilnODI31nfF8Bm5ltmlxjar9U47vH KX2/jroLrIFzTQ+8WwKYOIv8OV3m8xP3NBeOGu6w5heDYDgQ3PqxXQvt3VEEefSy/qTP VMgvy7znqqK2ShIDXEWIax7g7VaQykZO5P6yM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=Twl+UiIXrBUuhWLHtWhmPSzZf67yPuIZxcnQSgvgiLTEGx6Mjz2sGa3GZC35ghPWIl QSF/1PVYMHSrM+s1LcDYNA4ru3vsIISMK4cOeDt6gkMU5nhPqpaIteFdSZbGqCvtxU4S +diSPUNqS/XJ2frr50sJp46FEE7lnrZEBl72M= MIME-Version: 1.0 Received: by 10.216.140.147 with SMTP id e19mr8557624wej.49.1305054439500; Tue, 10 May 2011 12:07:19 -0700 (PDT) Received: by 10.216.49.211 with HTTP; Tue, 10 May 2011 12:07:19 -0700 (PDT) In-Reply-To: <20110510150238.GI21768@linux-mips.org> References: <1304844140-3259-1-git-send-email-manuel.lauss@googlemail.com> <1304844140-3259-10-git-send-email-manuel.lauss@googlemail.com> <20110510150238.GI21768@linux-mips.org> Date: Tue, 10 May 2011 21:07:19 +0200 Message-ID: Subject: Re: [PATCH 9/9] MIPS: Alchemy: clean up GPIO registers and accessors From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS , Florian Fainelli , Wolfgang Grandegger Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29911 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Tue, May 10, 2011 at 5:02 PM, Ralf Baechle wrote: > Thanks, queued for 2.6.40 - but you really should cc the watchdog folks, too! Thank you. Yesterday I split some of the patches in this series; among them is a stand-alone version of the mtx-1 watchdog patch which I sent to the watchdog maintainer and list. Manuel From hauke@hauke-m.de Tue May 10 23:31:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 23:31:59 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:48264 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491043Ab1EJVby (ORCPT ); Tue, 10 May 2011 23:31:54 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 382108ACC; Tue, 10 May 2011 23:31:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aMCYqQXyZAaC; Tue, 10 May 2011 23:31:49 +0200 (CEST) Received: from localhost.localdomain (host-091-097-255-123.ewe-ip-backbone.de [91.97.255.123]) by hauke-m.de (Postfix) with ESMTPSA id 1902B87E4; Tue, 10 May 2011 23:31:49 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 0/5] MIPS: BCM47xx: Enhancements in Parsing the NVRAM data Date: Tue, 10 May 2011 23:31:29 +0200 Message-Id: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29912 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips The first 3 patches add the ability to provide an fallback sprom from the nvram when a card connected to the pci bus using a ssb bus itself has no own sprom. Then the ssb code now asks the architecture code for the data. In the bcm47xx architecture the sprom data is stored in the nvram for recent devices and they do not have an own sprom. Patch #4 looks for some more values in the sprom. Boradcom changed the names of some attributes with sprom revision 4. The last patch fixes the parsing of mac addresses on some devices. There are still some checkpatch warnings about not using kstrto*. WARNING: consider using kstrto* in preference to simple_strtoul I will fix this in a later patch as there are many usages of simple_strtoul in arch/mips/bcm47xx/setup.c. v2: * fix some checkpatch errors and warnings * fix spelling issues Hauke Mehrtens (5): ssb: Change fallback sprom to callback mechanism. MIPS: BCM47xx: extend bcm47xx_fill_sprom with prefix. MIPS: BCM47xx: register ssb fallback sprom callback MIPS: BCM47xx: extend the filling of sprom from nvram MIPS: BCM47xx: Fix mac address parsing. arch/mips/bcm47xx/nvram.c | 3 +- arch/mips/bcm47xx/setup.c | 130 +++++++++++++++++++++++----- arch/mips/bcm63xx/boards/board_bcm963xx.c | 16 +++- arch/mips/include/asm/mach-bcm47xx/nvram.h | 12 ++- drivers/ssb/pci.c | 16 +++- drivers/ssb/sprom.c | 43 ++++++---- drivers/ssb/ssb_private.h | 3 +- include/linux/ssb/ssb.h | 4 +- 8 files changed, 175 insertions(+), 52 deletions(-) -- 1.7.4.1 From hauke@hauke-m.de Tue May 10 23:32:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 23:32:23 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:48272 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491045Ab1EJVcO (ORCPT ); Tue, 10 May 2011 23:32:14 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 69BD58ACA; Tue, 10 May 2011 23:32:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tuZlvmY-7Lla; Tue, 10 May 2011 23:32:10 +0200 (CEST) Received: from localhost.localdomain (host-091-097-255-123.ewe-ip-backbone.de [91.97.255.123]) by hauke-m.de (Postfix) with ESMTPSA id D157987E4; Tue, 10 May 2011 23:32:09 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens , netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Florian Fainelli Subject: [PATCH v2 1/5] ssb: Change fallback sprom to callback mechanism. Date: Tue, 10 May 2011 23:31:30 +0200 Message-Id: <1305063094-26656-2-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29913 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Some embedded devices like the Netgear WNDR3300 have two SSB based cards without an own sprom on the pci bus. We have to provide two different fallback sproms for these and this was not possible with the old solution. In the bcm47xx architecture the sprom data is stored in the nvram in the main flash storage. The architecture code will be able to fill the sprom with the stored data based on the bus where the device was found. The bcm63xx code should do the same thing as before, just using the new API. Acked-by: Michael Buesch CC: netdev@vger.kernel.org CC: linux-wireless@vger.kernel.org CC: Florian Fainelli Signed-off-by: Hauke Mehrtens --- v2: * fix some checkpatch errors and warnings * spelling issues arch/mips/bcm63xx/boards/board_bcm963xx.c | 16 +++++++++- drivers/ssb/pci.c | 16 +++++++--- drivers/ssb/sprom.c | 43 +++++++++++++++++------------ drivers/ssb/ssb_private.h | 3 +- include/linux/ssb/ssb.h | 4 ++- 5 files changed, 55 insertions(+), 27 deletions(-) diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 8dba8cf..40b223b 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -643,6 +643,17 @@ static struct ssb_sprom bcm63xx_sprom = { .boardflags_lo = 0x2848, .boardflags_hi = 0x0000, }; + +int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +{ + if (bus->bustype == SSB_BUSTYPE_PCI) { + memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); + return 0; + } else { + printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); + return -EINVAL; + } +} #endif /* @@ -793,8 +804,9 @@ void __init board_prom_init(void) if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); - if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0) - printk(KERN_ERR "failed to register fallback SPROM\n"); + if (ssb_arch_register_fallback_sprom( + &bcm63xx_get_fallback_sprom) < 0) + printk(KERN_ERR PFX "failed to register fallback SPROM\n"); } #endif } diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c index 6f34963..7ad4858 100644 --- a/drivers/ssb/pci.c +++ b/drivers/ssb/pci.c @@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out, static int ssb_pci_sprom_get(struct ssb_bus *bus, struct ssb_sprom *sprom) { - const struct ssb_sprom *fallback; int err; u16 *buf; @@ -707,10 +706,17 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus, if (err) { /* All CRC attempts failed. * Maybe there is no SPROM on the device? - * If we have a fallback, use that. */ - fallback = ssb_get_fallback_sprom(); - if (fallback) { - memcpy(sprom, fallback, sizeof(*sprom)); + * Now we ask the arch code if there is some sprom + * available for this device in some other storage */ + err = ssb_fill_sprom_with_fallback(bus, sprom); + if (err) { + ssb_printk(KERN_WARNING PFX "WARNING: Using" + " fallback SPROM failed (err %d)\n", + err); + } else { + ssb_dprintk(KERN_DEBUG PFX "Using SPROM" + " revision %d provided by" + " platform.\n", sprom->revision); err = 0; goto out_free; } diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c index 5f34d7a..45ff0e3 100644 --- a/drivers/ssb/sprom.c +++ b/drivers/ssb/sprom.c @@ -17,7 +17,7 @@ #include -static const struct ssb_sprom *fallback_sprom; +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out); static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len, @@ -145,36 +145,43 @@ out: } /** - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found. + * ssb_arch_register_fallback_sprom - Registers a method providing a + * fallback SPROM if no SPROM is found. * - * @sprom: The SPROM data structure to register. + * @sprom_callback: The callback function. * - * With this function the architecture implementation may register a fallback - * SPROM data structure. The fallback is only used for PCI based SSB devices, - * where no valid SPROM can be found in the shadow registers. + * With this function the architecture implementation may register a + * callback handler which fills the SPROM data structure. The fallback is + * only used for PCI based SSB devices, where no valid SPROM can be found + * in the shadow registers. * - * This function is useful for weird architectures that have a half-assed SSB device - * hardwired to their PCI bus. + * This function is useful for weird architectures that have a half-assed + * SSB device hardwired to their PCI bus. * - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently - * don't use this fallback. - * Architectures must provide the SPROM for native SSB devices anyway, - * so the fallback also isn't used for native devices. + * Note that it does only work with PCI attached SSB devices. PCMCIA + * devices currently don't use this fallback. + * Architectures must provide the SPROM for native SSB devices anyway, so + * the fallback also isn't used for native devices. * - * This function is available for architecture code, only. So it is not exported. + * This function is available for architecture code, only. So it is not + * exported. */ -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom) +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus, + struct ssb_sprom *out)) { - if (fallback_sprom) + if (get_fallback_sprom) return -EEXIST; - fallback_sprom = sprom; + get_fallback_sprom = sprom_callback; return 0; } -const struct ssb_sprom *ssb_get_fallback_sprom(void) +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out) { - return fallback_sprom; + if (!get_fallback_sprom) + return -ENOENT; + + return get_fallback_sprom(bus, out); } /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h index 0331139..7765301 100644 --- a/drivers/ssb/ssb_private.h +++ b/drivers/ssb/ssb_private.h @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_bus *bus, const char *buf, size_t count, int (*sprom_check_crc)(const u16 *sprom, size_t size), int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom)); -extern const struct ssb_sprom *ssb_get_fallback_sprom(void); +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, + struct ssb_sprom *out); /* core.c */ diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 9659eff..045f72a 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -404,7 +404,9 @@ extern bool ssb_is_sprom_available(struct ssb_bus *bus); /* Set a fallback SPROM. * See kdoc at the function definition for complete documentation. */ -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom); +extern int ssb_arch_register_fallback_sprom( + int (*sprom_callback)(struct ssb_bus *bus, + struct ssb_sprom *out)); /* Suspend a SSB bus. * Call this from the parent bus suspend routine. */ -- 1.7.4.1 From hauke@hauke-m.de Tue May 10 23:32:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 23:32:48 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45930 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491043Ab1EJVcU (ORCPT ); Tue, 10 May 2011 23:32:20 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 486338ACF; Tue, 10 May 2011 23:32:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JQssoBsPSWN3; Tue, 10 May 2011 23:32:17 +0200 (CEST) Received: from localhost.localdomain (host-091-097-255-123.ewe-ip-backbone.de [91.97.255.123]) by hauke-m.de (Postfix) with ESMTPSA id B347587E4; Tue, 10 May 2011 23:32:16 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 2/5] MIPS: BCM47xx: extend bcm47xx_fill_sprom with prefix. Date: Tue, 10 May 2011 23:31:31 +0200 Message-Id: <1305063094-26656-3-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29914 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips When an other ssb based device without an own sprom is attached, using the PCI bus to the main ssb based device, the data normally found in the sprom will be stored in the nvram on modern devices. The keys, to load the data from the nvram, are all using some sort of prefix like pci/1/1/, pci/1/3/ or sb/1/ before the actual key. This patch extends bcm47xx_fill_sprom() to make it possible to read out these values when some prefix was used. The keys for the sprom data used on the main chip does not have a prefix. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/setup.c | 29 +++++++++++++++++++++-------- 1 files changed, 21 insertions(+), 8 deletions(-) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index c95f90b..bbfcf9b 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -57,10 +57,23 @@ static void bcm47xx_machine_halt(void) } #define READ_FROM_NVRAM(_outvar, name, buf) \ - if (nvram_getenv(name, buf, sizeof(buf)) >= 0)\ + if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ sprom->_outvar = simple_strtoul(buf, NULL, 0); -static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) +static inline int nvram_getprefix(const char *prefix, char *name, + char *buf, int len) +{ + if (prefix) { + char key[100]; + + snprintf(key, sizeof(key), "%s%s", prefix, name); + return nvram_getenv(key, buf, len); + } + + return nvram_getenv(name, buf, len); +} + +static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) { char buf[100]; u32 boardflags; @@ -69,11 +82,11 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) sprom->revision = 1; /* Fallback: Old hardware does not define this. */ READ_FROM_NVRAM(revision, "sromrev", buf); - if (nvram_getenv("il0macaddr", buf, sizeof(buf)) >= 0) + if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->il0mac); - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0) + if (nvram_getprefix(prefix, "et0macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->et0mac); - if (nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0) + if (nvram_getprefix(prefix, "et1macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->et1mac); READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf); READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf); @@ -125,14 +138,14 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) READ_FROM_NVRAM(ofdm5gpo, "ofdm5gpo", buf); READ_FROM_NVRAM(ofdm5ghpo, "ofdm5ghpo", buf); - if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0) { + if (nvram_getprefix(prefix, "boardflags", buf, sizeof(buf)) >= 0) { boardflags = simple_strtoul(buf, NULL, 0); if (boardflags) { sprom->boardflags_lo = (boardflags & 0x0000FFFFU); sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16; } } - if (nvram_getenv("boardflags2", buf, sizeof(buf)) >= 0) { + if (nvram_getprefix(prefix, "boardflags2", buf, sizeof(buf)) >= 0) { boardflags = simple_strtoul(buf, NULL, 0); if (boardflags) { sprom->boardflags2_lo = (boardflags & 0x0000FFFFU); @@ -158,7 +171,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus, if (nvram_getenv("boardrev", buf, sizeof(buf)) >= 0) iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0); - bcm47xx_fill_sprom(&iv->sprom); + bcm47xx_fill_sprom(&iv->sprom, NULL); if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0) iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10); -- 1.7.4.1 From hauke@hauke-m.de Tue May 10 23:33:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 23:33:14 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45933 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491053Ab1EJVcV (ORCPT ); Tue, 10 May 2011 23:32:21 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 693998ACF; Tue, 10 May 2011 23:32:21 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4Ye7ETd4pcw3; Tue, 10 May 2011 23:32:17 +0200 (CEST) Received: from localhost.localdomain (host-091-097-255-123.ewe-ip-backbone.de [91.97.255.123]) by hauke-m.de (Postfix) with ESMTPSA id 9B4608ACA; Tue, 10 May 2011 23:32:17 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 3/5] MIPS: BCM47xx: register ssb fallback sprom callback Date: Tue, 10 May 2011 23:31:32 +0200 Message-Id: <1305063094-26656-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29915 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips We are generating the prefix based on the PCI bus address the device is on. This is done like Broadcom does it in their code expect that the the bus number is increased by one. In the SB bus implementation used by Broadcom the SB bus emulates a PCI bus so the kernel sees one PCI bus more then in our implementation. We do not handle prefixes like sb/1/ yet as they are only used on the new bus which is not implemented yet. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/nvram.c | 3 ++- arch/mips/bcm47xx/setup.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletions(-) diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index e5b6615..54db815 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -3,6 +3,7 @@ * * Copyright (C) 2005 Broadcom Corporation * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2010-2011 Hauke Mehrtens * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -23,7 +24,7 @@ static char nvram_buf[NVRAM_SPACE]; /* Probe for NVRAM header */ -static void __init early_nvram_init(void) +static void early_nvram_init(void) { struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore; struct nvram_header *header; diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index bbfcf9b..258ffcf 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -3,6 +3,7 @@ * Copyright (C) 2006 Felix Fietkau * Copyright (C) 2006 Michael Buesch * Copyright (C) 2010 Waldemar Brodkorb + * Copyright (C) 2010-2011 Hauke Mehrtens * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -154,6 +155,22 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) } } +int bcm47xx_get_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +{ + char prefix[10]; + + if (bus->bustype == SSB_BUSTYPE_PCI) { + snprintf(prefix, sizeof(prefix), "pci/%u/%u/", + bus->host_pci->bus->number + 1, + PCI_SLOT(bus->host_pci->devfn)); + bcm47xx_fill_sprom(out, prefix); + return 0; + } else { + printk(KERN_WARNING "bcm47xx: unable to fill SPROM for given bustype.\n"); + return -EINVAL; + } +} + static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv) { @@ -185,6 +202,11 @@ void __init plat_mem_setup(void) char buf[100]; struct ssb_mipscore *mcore; + err = ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom); + if (err) + printk(KERN_WARNING "bcm47xx: someone else already registered" + " a ssb SPROM callback handler (err %d)\n", err); + err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants); if (err) -- 1.7.4.1 From hauke@hauke-m.de Tue May 10 23:33:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 23:33:36 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45942 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491071Ab1EJVcZ (ORCPT ); Tue, 10 May 2011 23:32:25 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 8B6408ACA; Tue, 10 May 2011 23:32:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id atWoivsjm4bG; Tue, 10 May 2011 23:32:20 +0200 (CEST) Received: from localhost.localdomain (host-091-097-255-123.ewe-ip-backbone.de [91.97.255.123]) by hauke-m.de (Postfix) with ESMTPSA id 5DE258ACC; Tue, 10 May 2011 23:32:18 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH 4/5] MIPS: BCM47xx: extend the filling of sprom from nvram Date: Tue, 10 May 2011 23:31:33 +0200 Message-Id: <1305063094-26656-5-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29916 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Some members of the struct ssb_sprom where not filled with data available in the nvram. Some attribute names in the nvram changed from sprom version 3 to version 4. This patch was done by analyzing the the pci sprom parser in the ssb code and some open source parts of the braodcom wireless driver used on embedded devices. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/setup.c | 81 ++++++++++++++++++++++++++++++++++++-------- 1 files changed, 66 insertions(+), 15 deletions(-) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 258ffcf..73b529b 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -61,6 +61,11 @@ static void bcm47xx_machine_halt(void) if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ sprom->_outvar = simple_strtoul(buf, NULL, 0); +#define READ_FROM_NVRAM2(_outvar, name1, name2, buf) \ + if (nvram_getprefix(prefix, name1, buf, sizeof(buf)) >= 0 || \ + nvram_getprefix(prefix, name2, buf, sizeof(buf)) >= 0)\ + sprom->_outvar = simple_strtoul(buf, NULL, 0); + static inline int nvram_getprefix(const char *prefix, char *name, char *buf, int len) { @@ -74,6 +79,27 @@ static inline int nvram_getprefix(const char *prefix, char *name, return nvram_getenv(name, buf, len); } +static u32 nvram_getu32(const char *name, char *buf, int len) +{ + int rv; + char key[100]; + u16 var0, var1; + + snprintf(key, sizeof(key), "%s0", name); + rv = nvram_getenv(key, buf, len); + /* return 0 here so this looks like unset */ + if (rv < 0) + return 0; + var0 = simple_strtoul(buf, NULL, 0); + + snprintf(key, sizeof(key), "%s1", name); + rv = nvram_getenv(key, buf, len); + if (rv < 0) + return 0; + var1 = simple_strtoul(buf, NULL, 0); + return var1 << 16 | var0; +} + static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) { char buf[100]; @@ -83,7 +109,8 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) sprom->revision = 1; /* Fallback: Old hardware does not define this. */ READ_FROM_NVRAM(revision, "sromrev", buf); - if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0) + if (nvram_getprefix(prefix, "il0macaddr", buf, sizeof(buf)) >= 0 || + nvram_getprefix(prefix, "macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->il0mac); if (nvram_getprefix(prefix, "et0macaddr", buf, sizeof(buf)) >= 0) nvram_parse_macaddr(buf, sprom->et0mac); @@ -109,20 +136,36 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf); READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf); READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf); - READ_FROM_NVRAM(gpio0, "wl0gpio0", buf); - READ_FROM_NVRAM(gpio1, "wl0gpio1", buf); - READ_FROM_NVRAM(gpio2, "wl0gpio2", buf); - READ_FROM_NVRAM(gpio3, "wl0gpio3", buf); - READ_FROM_NVRAM(maxpwr_bg, "pa0maxpwr", buf); - READ_FROM_NVRAM(maxpwr_al, "pa1lomaxpwr", buf); - READ_FROM_NVRAM(maxpwr_a, "pa1maxpwr", buf); - READ_FROM_NVRAM(maxpwr_ah, "pa1himaxpwr", buf); - READ_FROM_NVRAM(itssi_a, "pa1itssit", buf); - READ_FROM_NVRAM(itssi_bg, "pa0itssit", buf); + READ_FROM_NVRAM2(gpio0, "ledbh0", "wl0gpio0", buf); + READ_FROM_NVRAM2(gpio1, "ledbh1", "wl0gpio1", buf); + READ_FROM_NVRAM2(gpio2, "ledbh2", "wl0gpio2", buf); + READ_FROM_NVRAM2(gpio3, "ledbh3", "wl0gpio3", buf); + READ_FROM_NVRAM2(maxpwr_bg, "maxp2ga0", "pa0maxpwr", buf); + READ_FROM_NVRAM2(maxpwr_al, "maxp5gla0", "pa1lomaxpwr", buf); + READ_FROM_NVRAM2(maxpwr_a, "maxp5ga0", "pa1maxpwr", buf); + READ_FROM_NVRAM2(maxpwr_ah, "maxp5gha0", "pa1himaxpwr", buf); + READ_FROM_NVRAM2(itssi_bg, "itt5ga0", "pa0itssit", buf); + READ_FROM_NVRAM2(itssi_a, "itt2ga0", "pa1itssit", buf); READ_FROM_NVRAM(tri2g, "tri2g", buf); READ_FROM_NVRAM(tri5gl, "tri5gl", buf); READ_FROM_NVRAM(tri5g, "tri5g", buf); READ_FROM_NVRAM(tri5gh, "tri5gh", buf); + READ_FROM_NVRAM(txpid2g[0], "txpid2ga0", buf); + READ_FROM_NVRAM(txpid2g[1], "txpid2ga1", buf); + READ_FROM_NVRAM(txpid2g[2], "txpid2ga2", buf); + READ_FROM_NVRAM(txpid2g[3], "txpid2ga3", buf); + READ_FROM_NVRAM(txpid5g[0], "txpid5ga0", buf); + READ_FROM_NVRAM(txpid5g[1], "txpid5ga1", buf); + READ_FROM_NVRAM(txpid5g[2], "txpid5ga2", buf); + READ_FROM_NVRAM(txpid5g[3], "txpid5ga3", buf); + READ_FROM_NVRAM(txpid5gl[0], "txpid5gla0", buf); + READ_FROM_NVRAM(txpid5gl[1], "txpid5gla1", buf); + READ_FROM_NVRAM(txpid5gl[2], "txpid5gla2", buf); + READ_FROM_NVRAM(txpid5gl[3], "txpid5gla3", buf); + READ_FROM_NVRAM(txpid5gh[0], "txpid5gha0", buf); + READ_FROM_NVRAM(txpid5gh[1], "txpid5gha1", buf); + READ_FROM_NVRAM(txpid5gh[2], "txpid5gha2", buf); + READ_FROM_NVRAM(txpid5gh[3], "txpid5gha3", buf); READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf); READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf); READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf); @@ -134,10 +177,18 @@ static void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix) READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf); READ_FROM_NVRAM(bxa5g, "bxa5g", buf); READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf); - READ_FROM_NVRAM(ofdm2gpo, "ofdm2gpo", buf); - READ_FROM_NVRAM(ofdm5glpo, "ofdm5glpo", buf); - READ_FROM_NVRAM(ofdm5gpo, "ofdm5gpo", buf); - READ_FROM_NVRAM(ofdm5ghpo, "ofdm5ghpo", buf); + + sprom->ofdm2gpo = nvram_getu32("ofdm2gpo", buf, sizeof(buf)); + sprom->ofdm5glpo = nvram_getu32("ofdm5glpo", buf, sizeof(buf)); + sprom->ofdm5gpo = nvram_getu32("ofdm5gpo", buf, sizeof(buf)); + sprom->ofdm5ghpo = nvram_getu32("ofdm5ghpo", buf, sizeof(buf)); + + READ_FROM_NVRAM(antenna_gain.ghz24.a0, "ag0", buf); + READ_FROM_NVRAM(antenna_gain.ghz24.a1, "ag1", buf); + READ_FROM_NVRAM(antenna_gain.ghz24.a2, "ag2", buf); + READ_FROM_NVRAM(antenna_gain.ghz24.a3, "ag3", buf); + memcpy(&sprom->antenna_gain.ghz5, &sprom->antenna_gain.ghz24, + sizeof(sprom->antenna_gain.ghz5)); if (nvram_getprefix(prefix, "boardflags", buf, sizeof(buf)) >= 0) { boardflags = simple_strtoul(buf, NULL, 0); -- 1.7.4.1 From hauke@hauke-m.de Tue May 10 23:33:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 May 2011 23:34:00 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:45943 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491078Ab1EJVc0 (ORCPT ); Tue, 10 May 2011 23:32:26 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id BEF3D8ACA; Tue, 10 May 2011 23:32:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id adc7WX0E0B2q; Tue, 10 May 2011 23:32:21 +0200 (CEST) Received: from localhost.localdomain (host-091-097-255-123.ewe-ip-backbone.de [91.97.255.123]) by hauke-m.de (Postfix) with ESMTPSA id 31CE28ACE; Tue, 10 May 2011 23:32:19 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH v2 5/5] MIPS: BCM47xx: Fix mac address parsing. Date: Tue, 10 May 2011 23:31:34 +0200 Message-Id: <1305063094-26656-6-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29917 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Some devices like the Netgear WGT634u are using minuses between the blocks of the mac address and other devices are using colons to separate them. Signed-off-by: Hauke Mehrtens --- v2: * fix some checkpatch errors and warnings arch/mips/include/asm/mach-bcm47xx/nvram.h | 12 ++++++++++-- 1 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h index 9759588..184d5ec 100644 --- a/arch/mips/include/asm/mach-bcm47xx/nvram.h +++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h @@ -39,8 +39,16 @@ extern int nvram_getenv(char *name, char *val, size_t val_len); static inline void nvram_parse_macaddr(char *buf, u8 *macaddr) { - sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1], - &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]); + if (strchr(buf, ':')) + sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], + &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4], + &macaddr[5]); + else if (strchr(buf, '-')) + sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0], + &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4], + &macaddr[5]); + else + printk(KERN_WARNING "Can not parse mac address: %s\n", buf); } #endif -- 1.7.4.1 From zajec5@gmail.com Wed May 11 01:12:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 01:12:42 +0200 (CEST) Received: from mail-qy0-f170.google.com ([209.85.216.170]:62896 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab1EJXMh convert rfc822-to-8bit (ORCPT ); Wed, 11 May 2011 01:12:37 +0200 Received: by qyk32 with SMTP id 32so2407784qyk.15 for ; Tue, 10 May 2011 16:12:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=S4Oga9zsqoYBOetVcx7aESLktw0t+gWRuXIPp5vNIlc=; b=sNyFSOvhegsmFuyTFsUZUdFwdwkL0YDJ2aweBhbvoGDWwebaKUHvphdSh7iVR6WaXJ dzAQM9fLhs7kUFazwKRhVYTf35apjoS88ckr+vNQrtLm8YCQoduVCCok458cxZlHW7Cn JSyWV+65kGeTc2jk0zOql/Ve4jLeN0vJGqfNk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=iNyQIPALuVW45i0UYYCtQ0vMCeWLMxGuQc4uLlgFWqKjiHx7FOrpu7fOZqptpyyctg xscV75mSgAkJacFllPAzcquUre86xagr16h/Srt3JJoCCfxRTi7S9ZNrNS3TV/BAMjsg yqoxSzsCFdxvLQRbAOaonYWAHzeyxCDYlQaWc= MIME-Version: 1.0 Received: by 10.229.18.77 with SMTP id v13mr6822935qca.56.1305069150900; Tue, 10 May 2011 16:12:30 -0700 (PDT) Received: by 10.229.211.5 with HTTP; Tue, 10 May 2011 16:12:30 -0700 (PDT) In-Reply-To: <1305063094-26656-2-git-send-email-hauke@hauke-m.de> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> <1305063094-26656-2-git-send-email-hauke@hauke-m.de> Date: Wed, 11 May 2011 01:12:30 +0200 Message-ID: Subject: Re: [PATCH v2 1/5] ssb: Change fallback sprom to callback mechanism. From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: Hauke Mehrtens Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Florian Fainelli Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29918 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zajec5@gmail.com Precedence: bulk X-list: linux-mips 2011/5/10 Hauke Mehrtens : > Some embedded devices like the Netgear WNDR3300 have two SSB based > cards without an own sprom on the pci bus. We have to provide two > different fallback sproms for these and this was not possible with the > old solution. In the bcm47xx architecture the sprom data is stored in > the nvram in the main flash storage. The architecture code will be able > to fill the sprom with the stored data based on the bus where the > device was found. > > The bcm63xx code should do the same thing as before, just using the new > API. > > Acked-by: Michael Buesch > CC: netdev@vger.kernel.org > CC: linux-wireless@vger.kernel.org > CC: Florian Fainelli > Signed-off-by: Hauke Mehrtens > --- > > v2: * fix some checkpatch errors and warnings >    * spelling issues > >  arch/mips/bcm63xx/boards/board_bcm963xx.c |   16 +++++++++- >  drivers/ssb/pci.c                         |   16 +++++++--- >  drivers/ssb/sprom.c                       |   43 +++++++++++++++++------------ >  drivers/ssb/ssb_private.h                 |    3 +- >  include/linux/ssb/ssb.h                   |    4 ++- >  5 files changed, 55 insertions(+), 27 deletions(-) > > diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c > index 8dba8cf..40b223b 100644 > --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c > +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c > @@ -643,6 +643,17 @@ static struct ssb_sprom bcm63xx_sprom = { >        .boardflags_lo          = 0x2848, >        .boardflags_hi          = 0x0000, >  }; > + > +int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) > +{ > +       if (bus->bustype == SSB_BUSTYPE_PCI) { > +               memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); > +               return 0; > +       } else { > +               printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); > +               return -EINVAL; > +       } > +} >  #endif > >  /* > @@ -793,8 +804,9 @@ void __init board_prom_init(void) >        if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { >                memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); >                memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); > -               if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0) > -                       printk(KERN_ERR "failed to register fallback SPROM\n"); > +               if (ssb_arch_register_fallback_sprom( > +                               &bcm63xx_get_fallback_sprom) < 0) > +                       printk(KERN_ERR PFX "failed to register fallback SPROM\n"); >        } >  #endif >  } > diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c > index 6f34963..7ad4858 100644 > --- a/drivers/ssb/pci.c > +++ b/drivers/ssb/pci.c > @@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out, >  static int ssb_pci_sprom_get(struct ssb_bus *bus, >                             struct ssb_sprom *sprom) >  { > -       const struct ssb_sprom *fallback; >        int err; >        u16 *buf; > > @@ -707,10 +706,17 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus, >                if (err) { >                        /* All CRC attempts failed. >                         * Maybe there is no SPROM on the device? > -                        * If we have a fallback, use that. */ > -                       fallback = ssb_get_fallback_sprom(); > -                       if (fallback) { > -                               memcpy(sprom, fallback, sizeof(*sprom)); > +                        * Now we ask the arch code if there is some sprom > +                        * available for this device in some other storage */ > +                       err = ssb_fill_sprom_with_fallback(bus, sprom); > +                       if (err) { > +                               ssb_printk(KERN_WARNING PFX "WARNING: Using" > +                                          " fallback SPROM failed (err %d)\n", > +                                          err); I was recently told we should not duplicate message levels info with own prefixes ("WARNING: "). -- RafaÅ‚ From jayachandranc@netlogicmicro.com Wed May 11 08:25:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 08:25:49 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:2427 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491100Ab1EKGZm (ORCPT ); Wed, 11 May 2011 08:25:42 +0200 X-TM-IMSS-Message-ID: <43c5c14e00043fd2@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 43c5c14e00043fd2 ; Tue, 10 May 2011 23:25:08 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 10 May 2011 23:19:23 -0700 Date: Wed, 11 May 2011 11:50:05 +0530 From: "Jayachandran C." To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/8] Netlogic XLR/XLS processor IDs. Message-ID: <20110511062004.GA10462@jayachandranc.netlogicmicro.com> References: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 11 May 2011 06:19:23.0708 (UTC) FILETIME=[5F226FC0:01CC0FA3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29919 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips On Sat, May 07, 2011 at 01:35:47AM +0530, Jayachandran C wrote: > Add Netlogic Microsystems company ID and processor IDs for XLR > and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. > > Signed-off-by: Jayachandran C > --- > arch/mips/include/asm/cpu.h | 27 ++++++++++++++++++++ > arch/mips/kernel/cpu-probe.c | 55 ++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 82 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h > index 8687753..34c0d3c 100644 [...] > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index f65d4c8..130aa7a 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -1034,6 +1087,8 @@ __cpuinit void cpu_probe(void) > break; > case PRID_COMP_INGENIC: > cpu_probe_ingenic(c, cpu); > + case PRID_COMP_NETLOGIC: > + cpu_probe_netlogic(c, cpu); > break; > } Found an issue here on review, this removed a break after PRID_COMP_INGENIC, I will send an updated patch today. JC. From jayachandranc@netlogicmicro.com Wed May 11 08:33:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 08:33:52 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:3458 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491095Ab1EKGdo (ORCPT ); Wed, 11 May 2011 08:33:44 +0200 X-TM-IMSS-Message-ID: <43cd23420004400f@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 43cd23420004400f ; Tue, 10 May 2011 23:33:12 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 10 May 2011 23:34:13 -0700 Date: Wed, 11 May 2011 12:04:58 +0530 From: "Jayachandran C." To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH 1/8, UPDATED] Netlogic XLR/XLS processor IDs. Message-ID: <20110511063457.GB10462@jayachandranc.netlogicmicro.com> References: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> <20110511062004.GA10462@jayachandranc.netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110511062004.GA10462@jayachandranc.netlogicmicro.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 11 May 2011 06:34:13.0558 (UTC) FILETIME=[7186C560:01CC0FA5] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29920 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips From 96a6fe21ee649e119f4d6b8053e0c1cd781c27a8 Mon Sep 17 00:00:00 2001 Message-Id: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> In-Reply-To: References: From: Jayachandran C Date: Fri, 22 Apr 2011 02:58:37 +0530 Subject: [PATCH 1/8] Netlogic XLR/XLS processor IDs. To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Add Netlogic Microsystems company ID and processor IDs for XLR and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. Signed-off-by: Jayachandran C --- arch/mips/include/asm/cpu.h | 27 ++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 56 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..34c0d3c 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 @@ -142,6 +143,31 @@ #define PRID_IMP_JZRISC 0x0200 /* + * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC + */ +#define PRID_IMP_NETLOGIC_XLR732 0x0000 +#define PRID_IMP_NETLOGIC_XLR716 0x0200 +#define PRID_IMP_NETLOGIC_XLR532 0x0900 +#define PRID_IMP_NETLOGIC_XLR308 0x0600 +#define PRID_IMP_NETLOGIC_XLR532C 0x0800 +#define PRID_IMP_NETLOGIC_XLR516C 0x0a00 +#define PRID_IMP_NETLOGIC_XLR508C 0x0b00 +#define PRID_IMP_NETLOGIC_XLR308C 0x0f00 +#define PRID_IMP_NETLOGIC_XLS608 0x8000 +#define PRID_IMP_NETLOGIC_XLS408 0x8800 +#define PRID_IMP_NETLOGIC_XLS404 0x8c00 +#define PRID_IMP_NETLOGIC_XLS208 0x8e00 +#define PRID_IMP_NETLOGIC_XLS204 0x8f00 +#define PRID_IMP_NETLOGIC_XLS108 0xce00 +#define PRID_IMP_NETLOGIC_XLS104 0xcf00 +#define PRID_IMP_NETLOGIC_XLS616B 0x4000 +#define PRID_IMP_NETLOGIC_XLS608B 0x4a00 +#define PRID_IMP_NETLOGIC_XLS416B 0x4400 +#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 +#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 +#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 + +/* * Definitions for 7:0 on legacy processors */ @@ -234,6 +260,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, + CPU_XLR, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..c7b7eb2 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + c->options = (MIPS_CPU_TLB | + MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | + MIPS_CPU_WATCH | + MIPS_CPU_EJTAG | + MIPS_CPU_LLSC); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_NETLOGIC_XLR732: + case PRID_IMP_NETLOGIC_XLR716: + case PRID_IMP_NETLOGIC_XLR532: + case PRID_IMP_NETLOGIC_XLR308: + case PRID_IMP_NETLOGIC_XLR532C: + case PRID_IMP_NETLOGIC_XLR516C: + case PRID_IMP_NETLOGIC_XLR508C: + case PRID_IMP_NETLOGIC_XLR308C: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLR"; + break; + + case PRID_IMP_NETLOGIC_XLS608: + case PRID_IMP_NETLOGIC_XLS408: + case PRID_IMP_NETLOGIC_XLS404: + case PRID_IMP_NETLOGIC_XLS208: + case PRID_IMP_NETLOGIC_XLS204: + case PRID_IMP_NETLOGIC_XLS108: + case PRID_IMP_NETLOGIC_XLS104: + case PRID_IMP_NETLOGIC_XLS616B: + case PRID_IMP_NETLOGIC_XLS608B: + case PRID_IMP_NETLOGIC_XLS416B: + case PRID_IMP_NETLOGIC_XLS412B: + case PRID_IMP_NETLOGIC_XLS408B: + case PRID_IMP_NETLOGIC_XLS404B: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLS"; + break; + + default: + printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", + c->processor_id); + c->cputype = CPU_XLR; + break; + } + + c->isa_level = MIPS_CPU_ISA_M64R1; + c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; +} + #ifdef CONFIG_64BIT /* For use by uaccess.h */ u64 __ua_limit; @@ -1035,6 +1088,9 @@ __cpuinit void cpu_probe(void) case PRID_COMP_INGENIC: cpu_probe_ingenic(c, cpu); break; + case PRID_COMP_NETLOGIC: + cpu_probe_netlogic(c, cpu); + break; } BUG_ON(!__cpu_name[cpu]); -- 1.7.1 From ralf@linux-mips.org Wed May 11 13:52:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 13:52:26 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46096 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491105Ab1EKLwW (ORCPT ); Wed, 11 May 2011 13:52:22 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BBrjui022850; Wed, 11 May 2011 12:53:46 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BBrjGY022848; Wed, 11 May 2011 12:53:45 +0100 Date: Wed, 11 May 2011 12:53:45 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Florian Fainelli Subject: Re: [PATCH v2 1/5] ssb: Change fallback sprom to callback mechanism. Message-ID: <20110511115344.GA13298@linux-mips.org> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> <1305063094-26656-2-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305063094-26656-2-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29921 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Wed May 11 13:53:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 13:53:17 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46106 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491105Ab1EKLxN (ORCPT ); Wed, 11 May 2011 13:53:13 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BBscI4022935; Wed, 11 May 2011 12:54:38 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BBscXK022933; Wed, 11 May 2011 12:54:38 +0100 Date: Wed, 11 May 2011 12:54:38 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/5] MIPS: BCM47xx: extend bcm47xx_fill_sprom with prefix. Message-ID: <20110511115438.GB13298@linux-mips.org> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> <1305063094-26656-3-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305063094-26656-3-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29922 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ral From ralf@linux-mips.org Wed May 11 13:53:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 13:53:41 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46110 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491120Ab1EKLx0 (ORCPT ); Wed, 11 May 2011 13:53:26 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BBsqGb022962; Wed, 11 May 2011 12:54:52 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BBspgU022961; Wed, 11 May 2011 12:54:51 +0100 Date: Wed, 11 May 2011 12:54:51 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/5] MIPS: BCM47xx: register ssb fallback sprom callback Message-ID: <20110511115451.GC13298@linux-mips.org> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> <1305063094-26656-4-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305063094-26656-4-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29923 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Wed May 11 13:53:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 13:54:04 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47487 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491121Ab1EKLxf (ORCPT ); Wed, 11 May 2011 13:53:35 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BBt1HX022977; Wed, 11 May 2011 12:55:01 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BBt1m4022976; Wed, 11 May 2011 12:55:01 +0100 Date: Wed, 11 May 2011 12:55:00 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 4/5] MIPS: BCM47xx: extend the filling of sprom from nvram Message-ID: <20110511115500.GD13298@linux-mips.org> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> <1305063094-26656-5-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305063094-26656-5-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29924 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Wed May 11 13:54:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 13:54:28 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47490 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491127Ab1EKLxp (ORCPT ); Wed, 11 May 2011 13:53:45 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BBtBe5022993; Wed, 11 May 2011 12:55:11 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BBtAwG022992; Wed, 11 May 2011 12:55:10 +0100 Date: Wed, 11 May 2011 12:55:10 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH v2 5/5] MIPS: BCM47xx: Fix mac address parsing. Message-ID: <20110511115510.GE13298@linux-mips.org> References: <1305063094-26656-1-git-send-email-hauke@hauke-m.de> <1305063094-26656-6-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305063094-26656-6-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29925 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Wed May 11 18:49:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:49:54 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45597 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491131Ab1EKQtv (ORCPT ); Wed, 11 May 2011 18:49:51 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGpHYU023804; Wed, 11 May 2011 17:51:17 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGpGGB023801; Wed, 11 May 2011 17:51:16 +0100 Date: Wed, 11 May 2011 17:51:16 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 8/8] USB support for XLS platforms. Message-ID: <20110511165116.GA20012@linux-mips.org> References: <70d6e74aef472dfde06b0aeb4a63ebaf7666b155.1304712046.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <70d6e74aef472dfde06b0aeb4a63ebaf7666b155.1304712046.git.jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29926 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, May 07, 2011 at 01:37:52AM +0530, Jayachandran C wrote: > update ehci-hcd.c and ohci-hcd.c to add XLS hcds > add ehci/ohci devices to XLR/XLS platform driver > Kconfig update > > Signed-off-by: Jayachandran C > --- > arch/mips/Kconfig | 2 + > arch/mips/netlogic/xlr/platform.c | 89 ++++++++++++++++++++ > drivers/usb/host/ehci-hcd.c | 5 + > drivers/usb/host/ehci-xls.c | 161 +++++++++++++++++++++++++++++++++++++ > drivers/usb/host/ohci-hcd.c | 5 + > drivers/usb/host/ohci-xls.c | 151 ++++++++++++++++++++++++++++++++++ > 6 files changed, 413 insertions(+), 0 deletions(-) This will need to be reviewed and acked by the USB maintainers. Can you repost ccing to linux-usb and the respective maintainers? Thanks! Ralf From ralf@linux-mips.org Wed May 11 18:50:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:50:45 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45604 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491131Ab1EKQum (ORCPT ); Wed, 11 May 2011 18:50:42 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGq9RV023893; Wed, 11 May 2011 17:52:09 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGq9Cp023892; Wed, 11 May 2011 17:52:09 +0100 Date: Wed, 11 May 2011 17:52:09 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/8] Netlogic XLR/XLS processor IDs. Message-ID: <20110511165209.GB20012@linux-mips.org> References: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29927 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Wed May 11 18:51:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:51:11 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45607 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491144Ab1EKQvD (ORCPT ); Wed, 11 May 2011 18:51:03 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGqUDX023920; Wed, 11 May 2011 17:52:30 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGqU8i023919; Wed, 11 May 2011 17:52:30 +0100 Date: Wed, 11 May 2011 17:52:30 +0100 From: Ralf Baechle To: "Jayachandran C." Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/8, UPDATED] Netlogic XLR/XLS processor IDs. Message-ID: <20110511165230.GC20012@linux-mips.org> References: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> <20110511062004.GA10462@jayachandranc.netlogicmicro.com> <20110511063457.GB10462@jayachandranc.netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110511063457.GB10462@jayachandranc.netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29928 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Wed May 11 18:52:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:52:15 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45614 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491139Ab1EKQwM (ORCPT ); Wed, 11 May 2011 18:52:12 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGrde6024029; Wed, 11 May 2011 17:53:39 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGrdp8024027; Wed, 11 May 2011 17:53:39 +0100 Date: Wed, 11 May 2011 17:53:39 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/8] Netlogic XLR/XLS processor IDs. Message-ID: <20110511165339.GA23941@linux-mips.org> References: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> <20110511165209.GB20012@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110511165209.GB20012@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29929 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, May 11, 2011 at 05:52:09PM +0100, Ralf Baechle wrote: > Date: Wed, 11 May 2011 17:52:09 +0100 > From: Ralf Baechle > To: Jayachandran C > Cc: linux-mips@linux-mips.org > Subject: Re: [PATCH 1/8] Netlogic XLR/XLS processor IDs. > Content-Type: text/plain; charset=us-ascii > > Queued for 2.6.40. Thanks, Just kidding. I really queued the the updated version. Ralf From ralf@linux-mips.org Wed May 11 18:52:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:52:42 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45617 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491145Ab1EKQw2 (ORCPT ); Wed, 11 May 2011 18:52:28 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGrtFf024057; Wed, 11 May 2011 17:53:55 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGrtCp024056; Wed, 11 May 2011 17:53:55 +0100 Date: Wed, 11 May 2011 17:53:55 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/8] mach-netlogic include directory and files. Message-ID: <20110511165355.GD20012@linux-mips.org> References: <9718c3f12f279f43876be5b266fcf6d35ec87306.1304712046.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9718c3f12f279f43876be5b266fcf6d35ec87306.1304712046.git.jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29930 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Wed May 11 18:53:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:53:06 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45621 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491139Ab1EKQwf (ORCPT ); Wed, 11 May 2011 18:52:35 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGs2O6024079; Wed, 11 May 2011 17:54:02 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGs2Ti024078; Wed, 11 May 2011 17:54:02 +0100 Date: Wed, 11 May 2011 17:54:02 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/8] Cache support, TLB support, asm/module.h entry Message-ID: <20110511165402.GE20012@linux-mips.org> References: <07e3b598b08cb1f1f31b4c6e461f3c06e8711c47.1304712046.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <07e3b598b08cb1f1f31b4c6e461f3c06e8711c47.1304712046.git.jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29931 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Wed May 11 18:53:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:53:32 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45627 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491146Ab1EKQwm (ORCPT ); Wed, 11 May 2011 18:52:42 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGs9Lk024101; Wed, 11 May 2011 17:54:09 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGs9SL024096; Wed, 11 May 2011 17:54:09 +0100 Date: Wed, 11 May 2011 17:54:09 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 4/8] Platform files for XLR/XLS processor support. Message-ID: <20110511165409.GF20012@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29932 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Wed May 11 18:53:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:53:59 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45630 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491147Ab1EKQwt (ORCPT ); Wed, 11 May 2011 18:52:49 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGsGsM024123; Wed, 11 May 2011 17:54:16 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGsGvO024122; Wed, 11 May 2011 17:54:16 +0100 Date: Wed, 11 May 2011 17:54:16 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 5/8] Kconfig and Makefile update for Netlogic XLR/XLS Message-ID: <20110511165416.GG20012@linux-mips.org> References: <88b9f2509f086d61c6621ae04a0e41f2353387e6.1304712046.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <88b9f2509f086d61c6621ae04a0e41f2353387e6.1304712046.git.jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29933 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Wed May 11 18:54:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:54:23 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45633 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491148Ab1EKQw6 (ORCPT ); Wed, 11 May 2011 18:52:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGsPjm024138; Wed, 11 May 2011 17:54:25 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGsP10024137; Wed, 11 May 2011 17:54:25 +0100 Date: Wed, 11 May 2011 17:54:25 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 6/8] Add default configuration for XLR/XLS processors Message-ID: <20110511165425.GH20012@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29934 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From ralf@linux-mips.org Wed May 11 18:54:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 18:54:47 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45636 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491145Ab1EKQxG (ORCPT ); Wed, 11 May 2011 18:53:06 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BGsX0u024152; Wed, 11 May 2011 17:54:33 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BGsXPV024150; Wed, 11 May 2011 17:54:33 +0100 Date: Wed, 11 May 2011 17:54:33 +0100 From: Ralf Baechle To: Jayachandran C Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 7/8] PCI support for XLR/XLS Message-ID: <20110511165433.GI20012@linux-mips.org> References: <308b8963d3ed2beb54b96634e3b72d84c4b45cfa.1304712046.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <308b8963d3ed2beb54b96634e3b72d84c4b45cfa.1304712046.git.jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29935 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks, Ralf From jayachandranc@netlogicmicro.com Wed May 11 18:59:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 19:00:03 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.203.210.36]:4571 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491139Ab1EKQ76 (ORCPT ); Wed, 11 May 2011 18:59:58 +0200 X-TM-IMSS-Message-ID: <460a6b450004564b@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 460a6b450004564b ; Wed, 11 May 2011 09:59:22 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 11 May 2011 10:00:44 -0700 Date: Wed, 11 May 2011 22:31:32 +0530 From: "Jayachandran C." To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/8] Netlogic XLR/XLS processor IDs. Message-ID: <20110511170131.GE10462@jayachandranc.netlogicmicro.com> References: <96a6fe21ee649e119f4d6b8053e0c1cd781c27a8.1304712046.git.jayachandranc@netlogicmicro.com> <20110511165209.GB20012@linux-mips.org> <20110511165339.GA23941@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110511165339.GA23941@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 11 May 2011 17:00:45.0371 (UTC) FILETIME=[F7FE38B0:01CC0FFC] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29936 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips On Wed, May 11, 2011 at 05:53:39PM +0100, Ralf Baechle wrote: > On Wed, May 11, 2011 at 05:52:09PM +0100, Ralf Baechle wrote: > > Date: Wed, 11 May 2011 17:52:09 +0100 > > From: Ralf Baechle > > To: Jayachandran C > > Cc: linux-mips@linux-mips.org > > Subject: Re: [PATCH 1/8] Netlogic XLR/XLS processor IDs. > > Content-Type: text/plain; charset=us-ascii > > > > Queued for 2.6.40. Thanks, > > Just kidding. I really queued the the updated version. Thanks! JC. From ralf@linux-mips.org Wed May 11 19:14:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 19:14:35 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36146 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491140Ab1EKRO2 (ORCPT ); Wed, 11 May 2011 19:14:28 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BHFgZR003659; Wed, 11 May 2011 18:15:42 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BHFfn0003656; Wed, 11 May 2011 18:15:41 +0100 Date: Wed, 11 May 2011 18:15:41 +0100 From: Ralf Baechle To: John Crispin Cc: Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V6] MIPS: lantiq: add watchdog support Message-ID: <20110511171541.GA32073@linux-mips.org> References: <1304629223-30537-1-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304629223-30537-1-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29937 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, May 05, 2011 at 11:00:23PM +0200, John Crispin wrote: > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel > Cc: Wim Van Sebroeck > Cc: linux-mips@linux-mips.org > Cc: linux-watchdog@vger.kernel.org I've folded your privately sent followon patch to use test_and_set_bit and clear_bit in ltq_wdt_open rsp. ltq_wdt_release as requested by Wim and have queued the result for 2.6.40. For your enjoyment I'm posting the resulting patch below. Thanks, Ralf Date: Thu, 5 May 2011 23:00:23 +0200 From: John Crispin MIPS: Lantiq: Add watchdog support This patch adds the driver for the watchdog found inside the Lantiq SoC family. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: Wim Van Sebroeck Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2327/ Signed-off-by: Ralf Baechle drivers/watchdog/Kconfig | 6 drivers/watchdog/Makefile | 1 drivers/watchdog/lantiq_wdt.c | 261 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+) Index: linux-queue/drivers/watchdog/Kconfig =================================================================== --- linux-queue.orig/drivers/watchdog/Kconfig +++ linux-queue/drivers/watchdog/Kconfig @@ -990,6 +990,12 @@ config BCM63XX_WDT To compile this driver as a loadable module, choose M here. The module will be called bcm63xx_wdt. +config LANTIQ_WDT + tristate "Lantiq SoC watchdog" + depends on LANTIQ + help + Hardware driver for the Lantiq SoC Watchdog Timer. + # PARISC Architecture # POWERPC Architecture Index: linux-queue/drivers/watchdog/Makefile =================================================================== --- linux-queue.orig/drivers/watchdog/Makefile +++ linux-queue/drivers/watchdog/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o obj-$(CONFIG_TXX9_WDT) += txx9wdt.o obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o # PARISC Architecture Index: linux-queue/drivers/watchdog/lantiq_wdt.c =================================================================== --- /dev/null +++ linux-queue/drivers/watchdog/lantiq_wdt.c @@ -0,0 +1,261 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + * Based on EP93xx wdt driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Section 3.4 of the datasheet + * The password sequence protects the WDT control register from unintended + * write actions, which might cause malfunction of the WDT. + * + * essentially the following two magic passwords need to be written to allow + * IO access to the WDT core + */ +#define LTQ_WDT_PW1 0x00BE0000 +#define LTQ_WDT_PW2 0x00DC0000 + +#define LTQ_WDT_CR 0x0 /* watchdog control register */ +#define LTQ_WDT_SR 0x8 /* watchdog status register */ + +#define LTQ_WDT_SR_EN (0x1 << 31) /* enable bit */ +#define LTQ_WDT_SR_PWD (0x3 << 26) /* turn on power */ +#define LTQ_WDT_SR_CLKDIV (0x3 << 24) /* turn on clock and set */ + /* divider to 0x40000 */ +#define LTQ_WDT_DIVIDER 0x40000 +#define LTQ_MAX_TIMEOUT ((1 << 16) - 1) /* the reload field is 16 bit */ + +static int nowayout = WATCHDOG_NOWAYOUT; + +static void __iomem *ltq_wdt_membase; +static unsigned long ltq_io_region_clk_rate; + +static unsigned long ltq_wdt_bootstatus; +static unsigned long ltq_wdt_in_use; +static int ltq_wdt_timeout = 30; +static int ltq_wdt_ok_to_close; + +static void +ltq_wdt_enable(void) +{ + ltq_wdt_timeout = ltq_wdt_timeout * + (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER) + 0x1000; + if (ltq_wdt_timeout > LTQ_MAX_TIMEOUT) + ltq_wdt_timeout = LTQ_MAX_TIMEOUT; + + /* write the first password magic */ + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); + /* write the second magic plus the configuration and new timeout */ + ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV | + LTQ_WDT_PW2 | ltq_wdt_timeout, ltq_wdt_membase + LTQ_WDT_CR); +} + +static void +ltq_wdt_disable(void) +{ + /* write the first password magic */ + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); + /* write the second password magic with no config + * this turns the watchdog off + */ + ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR); +} + +static ssize_t +ltq_wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) +{ + if (len) { + if (!nowayout) { + size_t i; + + ltq_wdt_ok_to_close = 0; + for (i = 0; i != len; i++) { + char c; + + if (get_user(c, data + i)) + return -EFAULT; + if (c == 'V') + ltq_wdt_ok_to_close = 1; + else + ltq_wdt_ok_to_close = 0; + } + } + ltq_wdt_enable(); + } + + return len; +} + +static struct watchdog_info ident = { + .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | + WDIOF_CARDRESET, + .identity = "ltq_wdt", +}; + +static long +ltq_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = -ENOTTY; + + switch (cmd) { + case WDIOC_GETSUPPORT: + ret = copy_to_user((struct watchdog_info __user *)arg, &ident, + sizeof(ident)) ? -EFAULT : 0; + break; + + case WDIOC_GETBOOTSTATUS: + ret = put_user(ltq_wdt_bootstatus, (int __user *)arg); + break; + + case WDIOC_GETSTATUS: + ret = put_user(0, (int __user *)arg); + break; + + case WDIOC_SETTIMEOUT: + ret = get_user(ltq_wdt_timeout, (int __user *)arg); + if (!ret) + ltq_wdt_enable(); + /* intentional drop through */ + case WDIOC_GETTIMEOUT: + ret = put_user(ltq_wdt_timeout, (int __user *)arg); + break; + + case WDIOC_KEEPALIVE: + ltq_wdt_enable(); + ret = 0; + break; + } + return ret; +} + +static int +ltq_wdt_open(struct inode *inode, struct file *file) +{ + if (test_and_set_bit(0, <q_wdt_in_use)) + return -EBUSY; + ltq_wdt_in_use = 1; + ltq_wdt_enable(); + + return nonseekable_open(inode, file); +} + +static int +ltq_wdt_release(struct inode *inode, struct file *file) +{ + if (ltq_wdt_ok_to_close) + ltq_wdt_disable(); + else + pr_err("ltq_wdt: watchdog closed without warning\n"); + ltq_wdt_ok_to_close = 0; + clear_bit(0, <q_wdt_in_use); + + return 0; +} + +static const struct file_operations ltq_wdt_fops = { + .owner = THIS_MODULE, + .write = ltq_wdt_write, + .unlocked_ioctl = ltq_wdt_ioctl, + .open = ltq_wdt_open, + .release = ltq_wdt_release, + .llseek = no_llseek, +}; + +static struct miscdevice ltq_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = <q_wdt_fops, +}; + +static int __init +ltq_wdt_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk *clk; + + if (!res) { + dev_err(&pdev->dev, "cannot obtain I/O memory region"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "cannot request I/O memory region"); + return -EBUSY; + } + ltq_wdt_membase = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ltq_wdt_membase) { + dev_err(&pdev->dev, "cannot remap I/O memory region\n"); + return -ENOMEM; + } + + /* we do not need to enable the clock as it is always running */ + clk = clk_get(&pdev->dev, "io"); + WARN_ON(!clk); + ltq_io_region_clk_rate = clk_get_rate(clk); + clk_put(clk); + + if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST) + ltq_wdt_bootstatus = WDIOF_CARDRESET; + + return misc_register(<q_wdt_miscdev); +} + +static int __devexit +ltq_wdt_remove(struct platform_device *pdev) +{ + misc_deregister(<q_wdt_miscdev); + + if (ltq_wdt_membase) + iounmap(ltq_wdt_membase); + + return 0; +} + + +static struct platform_driver ltq_wdt_driver = { + .remove = __devexit_p(ltq_wdt_remove), + .driver = { + .name = "ltq_wdt", + .owner = THIS_MODULE, + }, +}; + +static int __init +init_ltq_wdt(void) +{ + return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); +} + +static void __exit +exit_ltq_wdt(void) +{ + return platform_driver_unregister(<q_wdt_driver); +} + +module_init(init_ltq_wdt); +module_exit(exit_ltq_wdt); + +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); + +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC Watchdog"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); From ralf@linux-mips.org Wed May 11 19:20:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 19:20:05 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33962 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491140Ab1EKRUB (ORCPT ); Wed, 11 May 2011 19:20:01 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BHLSBc005711; Wed, 11 May 2011 18:21:28 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BHLRkD005708; Wed, 11 May 2011 18:21:27 +0100 Date: Wed, 11 May 2011 18:21:27 +0100 From: Ralf Baechle To: Maarten ter Huurne Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Lars-Peter Clausen Subject: Re: [PATCH] MIPS: JZ4740: setup: Autodetect physical memory. Message-ID: <20110511172127.GB32073@linux-mips.org> References: <1304329620-17659-1-git-send-email-maarten@treewalker.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1304329620-17659-1-git-send-email-maarten@treewalker.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29938 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Or does this have any relevance for 2.6.39 or -stable? Ralf From maarten@treewalker.org Wed May 11 20:37:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 20:37:23 +0200 (CEST) Received: from smtp-vbr13.xs4all.nl ([194.109.24.33]:3085 "EHLO smtp-vbr13.xs4all.nl" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491131Ab1EKShS (ORCPT ); Wed, 11 May 2011 20:37:18 +0200 Received: from starbug-2.trinair2002 (c74072.upc-c.chello.nl [212.187.74.72]) (authenticated bits=0) by smtp-vbr13.xs4all.nl (8.13.8/8.13.8) with ESMTP id p4BIamCl073199; Wed, 11 May 2011 20:37:07 +0200 (CEST) (envelope-from maarten@treewalker.org) Received: from hyperion.localnet (hyperion.trinair2002 [192.168.0.43]) by starbug-2.trinair2002 (Postfix) with ESMTP id 85EC5493E5; Wed, 11 May 2011 20:36:47 +0200 (CEST) From: Maarten ter Huurne To: Ralf Baechle Subject: Re: [PATCH] MIPS: JZ4740: setup: Autodetect physical memory. Date: Wed, 11 May 2011 20:36:46 +0200 User-Agent: KMail/1.13.7 (Linux/2.6.37.1-1.2-desktop; KDE/4.6.2; x86_64; ; ) Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, "Lars-Peter Clausen" References: <1304329620-17659-1-git-send-email-maarten@treewalker.org> <20110511172127.GB32073@linux-mips.org> In-Reply-To: <20110511172127.GB32073@linux-mips.org> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201105112036.46545.maarten@treewalker.org> X-Virus-Scanned: by XS4ALL Virus Scanner Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29939 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maarten@treewalker.org Precedence: bulk X-list: linux-mips On Wednesday 11 May 2011, Ralf Baechle wrote: > Thanks, queued for 2.6.40. Thanks. > Or does this have any relevance for 2.6.39 or -stable? No need to rush it out, having it in 2.6.40 would be fine. Bye, Maarten From ralf@linux-mips.org Wed May 11 21:34:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 21:34:23 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59597 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491147Ab1EKTeS (ORCPT ); Wed, 11 May 2011 21:34:18 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BJYkL9020963; Wed, 11 May 2011 20:34:49 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BJYXvl020950; Wed, 11 May 2011 20:34:33 +0100 Date: Wed, 11 May 2011 20:34:33 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: Robert Millan , David Daney , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] MIPS: Introduce set_elf_platform() helper function Message-ID: <20110511193433.GA17315@linux-mips.org> References: <12309140238d597edc0b48cbc07df218@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <12309140238d597edc0b48cbc07df218@localhost> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29940 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From David.Daney@caviumnetworks.com Wed May 11 22:22:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 22:22:48 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17640 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491144Ab1EKUWl (ORCPT ); Wed, 11 May 2011 22:22:41 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 11 May 2011 13:23:40 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 May 2011 13:22:38 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 May 2011 13:22:37 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p4BKMUbt032641; Wed, 11 May 2011 13:22:30 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p4BKMTmR032640; Wed, 11 May 2011 13:22:29 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , John Crispin Subject: [PATCH 0/3] MIPS: lantiq: Fix build problems on linux-queue. Date: Wed, 11 May 2011 13:22:24 -0700 Message-Id: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 11 May 2011 20:22:37.0870 (UTC) FILETIME=[2B9AE4E0:01CC1019] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29941 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips These patches fix three problems I encountered building a kernel for the lantiq platform. David Daney (3): MIPS: lantiq: Add missing include to mach-easy50712.c MIPS: lantiq: Fix section mismatch in gpio_stp.c MIPS: lantiq: Check return value from strict_strtoul(). arch/mips/lantiq/setup.c | 3 ++- arch/mips/lantiq/xway/gpio_stp.c | 2 +- arch/mips/lantiq/xway/mach-easy50712.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) Cc: John Crispin -- 1.7.2.3 From David.Daney@caviumnetworks.com Wed May 11 22:23:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 22:23:14 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17651 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491148Ab1EKUWn (ORCPT ); Wed, 11 May 2011 22:22:43 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 11 May 2011 13:23:43 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 May 2011 13:22:41 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 May 2011 13:22:41 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p4BKMbmx032650; Wed, 11 May 2011 13:22:37 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p4BKMbAD032649; Wed, 11 May 2011 13:22:37 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , John Crispin Subject: [PATCH 2/3] MIPS: lantiq: Fix section mismatch in gpio_stp.c Date: Wed, 11 May 2011 13:22:26 -0700 Message-Id: <1305145347-32605-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 11 May 2011 20:22:41.0152 (UTC) FILETIME=[2D8FB000:01CC1019] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29942 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips ltq_stp_probe() cannot be __init if ltq_stp_driver isn't also. Signed-off-by: David Daney Cc: John Crispin --- arch/mips/lantiq/xway/gpio_stp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index efa3782..eed5a45 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -111,7 +111,7 @@ static int ltq_stp_hw_init(void) return 0; } -static int __init ltq_stp_probe(struct platform_device *pdev) +static int ltq_stp_probe(struct platform_device *pdev) { struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); int ret = 0; -- 1.7.2.3 From David.Daney@caviumnetworks.com Wed May 11 22:23:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 22:23:38 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17650 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491147Ab1EKUWn (ORCPT ); Wed, 11 May 2011 22:22:43 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 11 May 2011 13:23:43 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 May 2011 13:22:41 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 May 2011 13:22:41 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p4BKMZEU032646; Wed, 11 May 2011 13:22:35 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p4BKMYCP032644; Wed, 11 May 2011 13:22:34 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , John Crispin Subject: [PATCH 1/3] MIPS: lantiq: Add missing include to mach-easy50712.c Date: Wed, 11 May 2011 13:22:25 -0700 Message-Id: <1305145347-32605-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 11 May 2011 20:22:41.0152 (UTC) FILETIME=[2D8FB000:01CC1019] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29943 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Without this we fail building with a missing definition for PHY_INTERFACE_MODE_MII. Signed-off-by: David Daney Cc: John Crispin --- arch/mips/lantiq/xway/mach-easy50712.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c index 2512561..30b8000 100644 --- a/arch/mips/lantiq/xway/mach-easy50712.c +++ b/arch/mips/lantiq/xway/mach-easy50712.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include -- 1.7.2.3 From David.Daney@caviumnetworks.com Wed May 11 22:23:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 22:24:02 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17656 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491151Ab1EKUWp (ORCPT ); Wed, 11 May 2011 22:22:45 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 11 May 2011 13:23:45 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 May 2011 13:22:43 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 May 2011 13:22:43 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p4BKMcMY032654; Wed, 11 May 2011 13:22:38 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p4BKMcSM032653; Wed, 11 May 2011 13:22:38 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , John Crispin Subject: [PATCH 3/3] MIPS: lantiq: Check return value from strict_strtoul(). Date: Wed, 11 May 2011 13:22:27 -0700 Message-Id: <1305145347-32605-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 11 May 2011 20:22:43.0652 (UTC) FILETIME=[2F0D2840:01CC1019] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29944 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The build fails if we don't check the return value from strict_strtoul(), so print a message if it fails. Signed-off-by: David Daney Cc: John Crispin --- arch/mips/lantiq/setup.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c index 2f27f58..9b8af77 100644 --- a/arch/mips/lantiq/setup.c +++ b/arch/mips/lantiq/setup.c @@ -35,7 +35,8 @@ void __init plat_mem_setup(void) char *e = (char *)KSEG1ADDR(*envp); if (!strncmp(e, "memsize=", 8)) { e += 8; - strict_strtoul(e, 0, &memsize); + if (strict_strtoul(e, 0, &memsize)) + pr_warn("bad memsize specified\n"); } envp++; } -- 1.7.2.3 From ralf@linux-mips.org Wed May 11 23:24:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 May 2011 23:24:20 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:55821 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491116Ab1EKVYR (ORCPT ); Wed, 11 May 2011 23:24:17 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BLPcZo031866; Wed, 11 May 2011 22:25:38 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BLPcSn031864; Wed, 11 May 2011 22:25:38 +0100 Date: Wed, 11 May 2011 22:25:38 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, John Crispin Subject: Re: [PATCH 1/3] MIPS: lantiq: Add missing include to mach-easy50712.c Message-ID: <20110511212538.GB17315@linux-mips.org> References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> <1305145347-32605-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305145347-32605-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29945 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, folded into "MIPS: Lantiq: Add etop board support". Ralf From ralf@linux-mips.org Thu May 12 00:48:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 00:48:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52197 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491116Ab1EKWsA (ORCPT ); Thu, 12 May 2011 00:48:00 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BMnKFM018475; Wed, 11 May 2011 23:49:25 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BMnJAf018472; Wed, 11 May 2011 23:49:19 +0100 Date: Wed, 11 May 2011 23:49:19 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, John Crispin Subject: Re: [PATCH 2/3] MIPS: lantiq: Fix section mismatch in gpio_stp.c Message-ID: <20110511224919.GC17315@linux-mips.org> References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> <1305145347-32605-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305145347-32605-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29946 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, May 11, 2011 at 01:22:26PM -0700, David Daney wrote: > ltq_stp_probe() cannot be __init if ltq_stp_driver isn't also. That would work - but a __devinit declaration would be even better. Ralf From ralf@linux-mips.org Thu May 12 00:52:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 00:52:11 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:43078 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491116Ab1EKWwF (ORCPT ); Thu, 12 May 2011 00:52:05 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4BMrVbW023810; Wed, 11 May 2011 23:53:31 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4BMrVoo023808; Wed, 11 May 2011 23:53:31 +0100 Date: Wed, 11 May 2011 23:53:31 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, John Crispin Subject: Re: [PATCH 3/3] MIPS: lantiq: Check return value from strict_strtoul(). Message-ID: <20110511225331.GD17315@linux-mips.org> References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> <1305145347-32605-4-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305145347-32605-4-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29947 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, May 11, 2011 at 01:22:27PM -0700, David Daney wrote: > Subject: [PATCH 3/3] MIPS: lantiq: Check return value from strict_strtoul(). Thanks, folded into "MIPS: Lantiq: Add initial support for Lantiq SoCs". Ralf From wad@chromium.org Thu May 12 05:06:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 05:06:46 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:59729 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491033Ab1ELDGh (ORCPT ); Thu, 12 May 2011 05:06:37 +0200 Received: by iyb39 with SMTP id 39so1090312iyb.36 for ; Wed, 11 May 2011 20:06:30 -0700 (PDT) Received: by 10.231.179.38 with SMTP id bo38mr2808066ibb.103.1305169587888; Wed, 11 May 2011 20:06:27 -0700 (PDT) Received: from localhost.localdomain (adsl-98-87-25-84.bna.bellsouth.net [98.87.25.84]) by mx.google.com with ESMTPS id y10sm300255iba.46.2011.05.11.20.06.22 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 May 2011 20:06:26 -0700 (PDT) From: Will Drewry To: linux-kernel@vger.kernel.org Cc: Steven Rostedt , Frederic Weisbecker , Eric Paris , Ingo Molnar , kees.cook@canonical.com, agl@chromium.org, jmorris@namei.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Will Drewry Subject: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Date: Wed, 11 May 2011 22:02:56 -0500 Message-Id: <1305169376-2363-1-git-send-email-wad@chromium.org> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1304017638.18763.205.camel@gandalf.stny.rr.com> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29948 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wad@chromium.org Precedence: bulk X-list: linux-mips This change adds a new seccomp mode based on the work by agl@chromium.org in [1]. This new mode, "filter mode", provides a hash table of seccomp_filter objects. When in the new mode (2), all system calls are checked against the filters - first by system call number, then by a filter string. If an entry exists for a given system call and all filter predicates evaluate to true, then the task may proceed. Otherwise, the task is killed (as per seccomp_mode == 1). Filter string parsing and evaluation is handled by the ftrace filter engine. Related patches tweak to the perf filter trace and free allow the call to be shared. Filters inherit their understanding of types and arguments for each system call from the CONFIG_FTRACE_SYSCALLS subsystem which already predefines this information in syscall_metadata associated enter_event (and exit_event) structures. If CONFIG_FTRACE and CONFIG_FTRACE_SYSCALLS are not compiled in, only "1" filter strings will be allowed. The net result is a process may have its system calls filtered using the ftrace filter engine's inherent understanding of systems calls. A logical ruleset for a process that only needs stdin/stdout may be: sys_read: fd == 0 sys_write: fd == 1 || fd == 2 sys_exit: 1 The set of filters is specified through the PR_SET_SECCOMP path in prctl(). For example: prctl(PR_SET_SECCOMP_FILTER, __NR_read, "fd == 0"); prctl(PR_SET_SECCOMP_FILTER, __NR_write, "fd == 1 || fd == 2"); prctl(PR_SET_SECCOMP_FILTER, __NR_exit, "1"); prctl(PR_SET_SECCOMP, 2, 0); v2: - changed to use the existing syscall number ABI. - prctl changes to minimize parsing in the kernel: prctl(PR_SET_SECCOMP, {0 | 1 | 2 }, { 0 | ON_EXEC }); prctl(PR_SET_SECCOMP_FILTER, __NR_read, "fd == 5"); prctl(PR_CLEAR_SECCOMP_FILTER, __NR_read); prctl(PR_GET_SECCOMP_FILTER, __NR_read, buf, bufsize); - defined PR_SECCOMP_MODE_STRICT and ..._FILTER - added flags - provide a default fail syscall_nr_to_meta in ftrace - provides fallback for unhooked system calls - use -ENOSYS and ERR_PTR(-ENOSYS) for stubbed functionality - added kernel/seccomp.h to share seccomp.c/seccomp_filter.c - moved to a hlist and 4 bit hash of linked lists - added support to operate without CONFIG_FTRACE_SYSCALLS - moved Kconfig support next to SECCOMP (should this be done in per-platform patches?) - made Kconfig entries dependent on EXPERIMENTAL - added macros to avoid ifdefs from kernel/fork.c - added compat task/filter matching - drop seccomp.h inclusion in sched.h and drop seccomp_t - added Filtering to "show" output - added on_exec state dup'ing when enabling after a fast-path accept. Signed-off-by: Will Drewry --- arch/arm/Kconfig | 10 + arch/microblaze/Kconfig | 10 + arch/mips/Kconfig | 10 + arch/powerpc/Kconfig | 10 + arch/s390/Kconfig | 10 + arch/sh/Kconfig | 10 + arch/sparc/Kconfig | 10 + arch/x86/Kconfig | 10 + include/linux/prctl.h | 9 + include/linux/sched.h | 5 +- include/linux/seccomp.h | 116 +++++++++- include/trace/syscall.h | 7 + kernel/Makefile | 3 + kernel/fork.c | 3 + kernel/seccomp.c | 228 +++++++++++++++++- kernel/seccomp.h | 74 ++++++ kernel/seccomp_filter.c | 581 +++++++++++++++++++++++++++++++++++++++++++++++ kernel/sys.c | 15 +- 18 files changed, 1100 insertions(+), 21 deletions(-) create mode 100644 kernel/seccomp.h create mode 100644 kernel/seccomp_filter.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 377a7a5..22e1668 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1664,6 +1664,16 @@ config SECCOMP and the task is only allowed to execute a few safe syscalls defined by each seccomp mode. +config SECCOMP_FILTER + bool "Enable seccomp-based system call filtering" + depends on SECCOMP && EXPERIMENTAL + help + Per-process, inherited system call filtering using shared code + across seccomp and ftrace_syscalls. If CONFIG_FTRACE_SYSCALLS + is not available, enhanced filters will not be available. + + See Documentation/prctl/seccomp_filter.txt for more detail. + config CC_STACKPROTECTOR bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" depends on EXPERIMENTAL diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index eccdefe..7641ee9 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -129,6 +129,16 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. +config SECCOMP_FILTER + bool "Enable seccomp-based system call filtering" + depends on SECCOMP && EXPERIMENTAL + help + Per-process, inherited system call filtering using shared code + across seccomp and ftrace_syscalls. If CONFIG_FTRACE_SYSCALLS + is not available, enhanced filters will not be available. + + See Documentation/prctl/seccomp_filter.txt for more detail. + endmenu menu "Advanced setup" diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8e256cc..fe4cbda 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2245,6 +2245,16 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. +config SECCOMP_FILTER + bool "Enable seccomp-based system call filtering" + depends on SECCOMP && EXPERIMENTAL + help + Per-process, inherited system call filtering using shared code + across seccomp and ftrace_syscalls. If CONFIG_FTRACE_SYSCALLS + is not available, enhanced filters will not be available. + + See Documentation/prctl/seccomp_filter.txt for more detail. + config USE_OF bool "Flattened Device Tree support" select OF diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 8f4d50b..83499e4 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -605,6 +605,16 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. +config SECCOMP_FILTER + bool "Enable seccomp-based system call filtering" + depends on SECCOMP && EXPERIMENTAL + help + Per-process, inherited system call filtering using shared code + across seccomp and ftrace_syscalls. If CONFIG_FTRACE_SYSCALLS + is not available, enhanced filters will not be available. + + See Documentation/prctl/seccomp_filter.txt for more detail. + endmenu config ISA_DMA_API diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 2508a6f..2777515 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -614,6 +614,16 @@ config SECCOMP If unsure, say Y. +config SECCOMP_FILTER + bool "Enable seccomp-based system call filtering" + depends on SECCOMP && EXPERIMENTAL + help + Per-process, inherited system call filtering using shared code + across seccomp and ftrace_syscalls. If CONFIG_FTRACE_SYSCALLS + is not available, enhanced filters will not be available. + + See Documentation/prctl/seccomp_filter.txt for more detail. + endmenu menu "Power Management" diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 4b89da2..00c1521 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -676,6 +676,16 @@ config SECCOMP If unsure, say N. +config SECCOMP_FILTER + bool "Enable seccomp-based system call filtering" + depends on SECCOMP && EXPERIMENTAL + help + Per-process, inherited system call filtering using shared code + across seccomp and ftrace_syscalls. If CONFIG_FTRACE_SYSCALLS + is not available, enhanced filters will not be available. + + See Documentation/prctl/seccomp_filter.txt for more detail. + config SMP bool "Symmetric multi-processing support" depends on SYS_SUPPORTS_SMP diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index e560d10..5b42255 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -270,6 +270,16 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. +config SECCOMP_FILTER + bool "Enable seccomp-based system call filtering" + depends on SECCOMP && EXPERIMENTAL + help + Per-process, inherited system call filtering using shared code + across seccomp and ftrace_syscalls. If CONFIG_FTRACE_SYSCALLS + is not available, enhanced filters will not be available. + + See Documentation/prctl/seccomp_filter.txt for more detail. + config HOTPLUG_CPU bool "Support for hot-pluggable CPUs" depends on SPARC64 && SMP diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cc6c53a..d6d44d9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1485,6 +1485,16 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. +config SECCOMP_FILTER + bool "Enable seccomp-based system call filtering" + depends on SECCOMP && EXPERIMENTAL + help + Per-process, inherited system call filtering using shared code + across seccomp and ftrace_syscalls. If CONFIG_FTRACE_SYSCALLS + is not available, enhanced filters will not be available. + + See Documentation/prctl/seccomp_filter.txt for more detail. + config CC_STACKPROTECTOR bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" ---help--- diff --git a/include/linux/prctl.h b/include/linux/prctl.h index a3baeb2..379b391 100644 --- a/include/linux/prctl.h +++ b/include/linux/prctl.h @@ -63,6 +63,15 @@ /* Get/set process seccomp mode */ #define PR_GET_SECCOMP 21 #define PR_SET_SECCOMP 22 +# define PR_SECCOMP_MODE_NONE 0 +# define PR_SECCOMP_MODE_STRICT 1 +# define PR_SECCOMP_MODE_FILTER 2 +# define PR_SECCOMP_FLAG_FILTER_ON_EXEC (1 << 1) + +/* Get/set process seccomp filters */ +#define PR_GET_SECCOMP_FILTER 35 +#define PR_SET_SECCOMP_FILTER 36 +#define PR_CLEAR_SECCOMP_FILTER 37 /* Get/set the capability bounding set (as per security/commoncap.c) */ #define PR_CAPBSET_READ 23 diff --git a/include/linux/sched.h b/include/linux/sched.h index 18d63ce..27eacf9 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -77,7 +77,6 @@ struct sched_param { #include #include #include -#include #include #include #include @@ -1190,6 +1189,8 @@ enum perf_event_task_context { perf_nr_task_contexts, }; +struct seccomp_state; + struct task_struct { volatile long state; /* -1 unrunnable, 0 runnable, >0 stopped */ void *stack; @@ -1374,7 +1375,7 @@ struct task_struct { uid_t loginuid; unsigned int sessionid; #endif - seccomp_t seccomp; + struct seccomp_state *seccomp; /* Thread group tracking */ u32 parent_exec_id; diff --git a/include/linux/seccomp.h b/include/linux/seccomp.h index 167c333..289c836 100644 --- a/include/linux/seccomp.h +++ b/include/linux/seccomp.h @@ -2,12 +2,34 @@ #define _LINUX_SECCOMP_H +/* Forward declare for proc interface */ +struct seq_file; + #ifdef CONFIG_SECCOMP +#include +#include #include +#include #include -typedef struct { int mode; } seccomp_t; +/** + * struct seccomp_state - the state of a seccomp'ed process + * + * @mode: + * if this is 1, the process is under standard seccomp rules + * is 2, the process is only allowed to make system calls where + * associated filters evaluate successfully. + * @usage: number of references to the current instance. + * @flags: a bitmask of behavior altering flags. + * @filters: Hash table of filters if using CONFIG_SECCOMP_FILTER. + */ +struct seccomp_state { + uint16_t mode; + atomic_t usage; + long flags; + struct seccomp_filter_table *filters; +}; extern void __secure_computing(int); static inline void secure_computing(int this_syscall) @@ -16,27 +38,113 @@ static inline void secure_computing(int this_syscall) __secure_computing(this_syscall); } +extern struct seccomp_state *seccomp_state_new(void); +extern struct seccomp_state *seccomp_state_dup(const struct seccomp_state *); +extern struct seccomp_state *get_seccomp_state(struct seccomp_state *); +extern void put_seccomp_state(struct seccomp_state *); + +extern long prctl_set_seccomp(unsigned long, unsigned long); extern long prctl_get_seccomp(void); -extern long prctl_set_seccomp(unsigned long); + +extern long prctl_set_seccomp_filter(unsigned long, char __user *); +extern long prctl_get_seccomp_filter(unsigned long, char __user *, + unsigned long); +extern long prctl_clear_seccomp_filter(unsigned long); + +#define inherit_tsk_seccomp_state(_child, _orig) \ + _child->seccomp = get_seccomp_state(_orig->seccomp); +#define put_tsk_seccomp_state(_tsk) put_seccomp_state(_tsk->seccomp) #else /* CONFIG_SECCOMP */ #include -typedef struct { } seccomp_t; +struct seccomp_state { }; #define secure_computing(x) do { } while (0) +#define inherit_tsk_seccomp_state(_child, _orig) do { } while (0) +#define put_tsk_seccomp_state(_tsk) do { } while (0) static inline long prctl_get_seccomp(void) { return -EINVAL; } -static inline long prctl_set_seccomp(unsigned long arg2) +static inline long prctl_set_seccomp(unsigned long a2, unsigned long a3) { return -EINVAL; } +static inline long prctl_set_seccomp_filter(unsigned long a2, char __user *a3) +{ + return -ENOSYS; +} + +static inline long prctl_clear_seccomp_filter(unsigned long a2) +{ + return -ENOSYS; +} + +static inline long prctl_get_seccomp_filter(unsigned long a2, char __user *a3, + unsigned long a4) +{ + return -ENOSYS; +} + +static inline struct seccomp_state *seccomp_state_new(void) +{ + return NULL; +} + +static inline struct seccomp_state *seccomp_state_dup( + const struct seccomp_state *state) +{ + return NULL; +} + +static inline struct seccomp_state *get_seccomp_state( + struct seccomp_state *state) +{ + return NULL; +} + +static inline void put_seccomp_state(struct seccomp_state *state) +{ +} + #endif /* CONFIG_SECCOMP */ +#ifdef CONFIG_SECCOMP_FILTER + +extern int seccomp_show_filters(struct seccomp_state *, struct seq_file *); +extern long seccomp_set_filter(int, char *); +extern long seccomp_clear_filter(int); +extern long seccomp_get_filter(int, char *, unsigned long); + +#else /* CONFIG_SECCOMP_FILTER */ + +static inline int seccomp_show_filters(struct seccomp_state *state, + struct seq_file *m) +{ + return -ENOSYS; +} + +static inline long seccomp_set_filter(int syscall_nr, char *filter) +{ + return -ENOSYS; +} + +static inline long seccomp_clear_filter(int syscall_nr) +{ + return -ENOSYS; +} + +static inline long seccomp_get_filter(int syscall_nr, + char *buf, unsigned long available) +{ + return -ENOSYS; +} + +#endif /* CONFIG_SECCOMP_FILTER */ + #endif /* _LINUX_SECCOMP_H */ diff --git a/include/trace/syscall.h b/include/trace/syscall.h index 242ae04..e061ad0 100644 --- a/include/trace/syscall.h +++ b/include/trace/syscall.h @@ -35,6 +35,8 @@ struct syscall_metadata { extern unsigned long arch_syscall_addr(int nr); extern int init_syscall_trace(struct ftrace_event_call *call); +extern struct syscall_metadata *syscall_nr_to_meta(int); + extern int reg_event_syscall_enter(struct ftrace_event_call *call); extern void unreg_event_syscall_enter(struct ftrace_event_call *call); extern int reg_event_syscall_exit(struct ftrace_event_call *call); @@ -49,6 +51,11 @@ enum print_line_t print_syscall_enter(struct trace_iterator *iter, int flags, struct trace_event *event); enum print_line_t print_syscall_exit(struct trace_iterator *iter, int flags, struct trace_event *event); +#else +static inline struct syscall_metadata *syscall_nr_to_meta(int nr) +{ + return NULL; +} #endif #ifdef CONFIG_PERF_EVENTS diff --git a/kernel/Makefile b/kernel/Makefile index 85cbfb3..84e7dfb 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -81,6 +81,9 @@ obj-$(CONFIG_DETECT_HUNG_TASK) += hung_task.o obj-$(CONFIG_LOCKUP_DETECTOR) += watchdog.o obj-$(CONFIG_GENERIC_HARDIRQS) += irq/ obj-$(CONFIG_SECCOMP) += seccomp.o +ifeq ($(CONFIG_SECCOMP_FILTER),y) +obj-$(CONFIG_SECCOMP) += seccomp_filter.o +endif obj-$(CONFIG_RCU_TORTURE_TEST) += rcutorture.o obj-$(CONFIG_TREE_RCU) += rcutree.o obj-$(CONFIG_TREE_PREEMPT_RCU) += rcutree.o diff --git a/kernel/fork.c b/kernel/fork.c index e7548de..46987d4 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -169,6 +170,7 @@ void free_task(struct task_struct *tsk) free_thread_info(tsk->stack); rt_mutex_debug_task_free(tsk); ftrace_graph_exit_task(tsk); + put_tsk_seccomp_state(tsk); free_task_struct(tsk); } EXPORT_SYMBOL(free_task); @@ -280,6 +282,7 @@ static struct task_struct *dup_task_struct(struct task_struct *orig) if (err) goto out; + inherit_tsk_seccomp_state(tsk, orig); setup_thread_stack(tsk, orig); clear_user_return_notifier(tsk); clear_tsk_need_resched(tsk); diff --git a/kernel/seccomp.c b/kernel/seccomp.c index 57d4b13..502ba04 100644 --- a/kernel/seccomp.c +++ b/kernel/seccomp.c @@ -6,12 +6,15 @@ * This defines a simple but solid secure-computing mode. */ +#include +#include #include #include +#include #include +#include -/* #define SECCOMP_DEBUG 1 */ -#define NR_SECCOMP_MODES 1 +#include "seccomp.h" /* * Secure computing mode 1 allows only read/write/exit/sigreturn. @@ -32,11 +35,13 @@ static int mode1_syscalls_32[] = { void __secure_computing(int this_syscall) { - int mode = current->seccomp.mode; + int mode = -1; + long ret = 0; int * syscall; - + if (current->seccomp) + mode = current->seccomp->mode; switch (mode) { - case 1: + case PR_SECCOMP_MODE_STRICT: syscall = mode1_syscalls; #ifdef CONFIG_COMPAT if (is_compat_task()) @@ -47,6 +52,20 @@ void __secure_computing(int this_syscall) return; } while (*++syscall); break; + case PR_SECCOMP_MODE_FILTER: + if (this_syscall >= NR_syscalls || this_syscall < 0) + break; + ret = seccomp_test_filters(current->seccomp, this_syscall); + if (!ret) + return; + /* Only check for an override if an access failure occurred. */ + if (ret != -EACCES) + break; + ret = seccomp_maybe_apply_filters(current, this_syscall); + if (!ret) + return; + seccomp_filter_log_failure(this_syscall); + break; default: BUG(); } @@ -57,30 +76,213 @@ void __secure_computing(int this_syscall) do_exit(SIGKILL); } +/* seccomp_state_new - allocate a new state object. */ +struct seccomp_state *seccomp_state_new() +{ + struct seccomp_state *new = kzalloc(sizeof(struct seccomp_state), + GFP_KERNEL); + if (!new) + return NULL; + + new->flags = 0; +#ifdef CONFIG_COMPAT + /* Annotate if this filterset is being created by a compat task. */ + if (is_compat_task()) + new->flags |= SECCOMP_FLAG_COMPAT; +#endif + + atomic_set(&new->usage, 1); + new->filters = seccomp_filter_table_new(); + /* Not supported errors are fine, others are a problem. */ + if (IS_ERR(new->filters) && PTR_ERR(new->filters) != -ENOSYS) { + kfree(new); + new = NULL; + } + return new; +} + +/* seccomp_state_dup - copies an existing state object. */ +struct seccomp_state *seccomp_state_dup(const struct seccomp_state *orig) +{ + int err; + struct seccomp_state *new_state = seccomp_state_new(); + + err = -ENOMEM; + if (!new_state) + goto fail; + new_state->mode = orig->mode; + /* Flag copying will hide if the new process is a compat task. However, + * if the rule was compat/non-compat and the process is the opposite, + * enforcement will terminate it. + */ + new_state->flags = orig->flags; + err = seccomp_copy_all_filters(new_state->filters, + orig->filters); + if (err) + goto fail; + + return new_state; +fail: + put_seccomp_state(new_state); + return NULL; +} + +/* get_seccomp_state - increments the reference count of @orig */ +struct seccomp_state *get_seccomp_state(struct seccomp_state *orig) +{ + if (!orig) + return NULL; + atomic_inc(&orig->usage); + return orig; +} + +static void __put_seccomp_state(struct seccomp_state *orig) +{ + WARN_ON(atomic_read(&orig->usage)); + seccomp_drop_all_filters(orig); + kfree(orig); +} + +/* put_seccomp_state - decrements the reference count of @orig and may free. */ +void put_seccomp_state(struct seccomp_state *orig) +{ + if (!orig) + return; + + if (atomic_dec_and_test(&orig->usage)) + __put_seccomp_state(orig); +} + long prctl_get_seccomp(void) { - return current->seccomp.mode; + if (!current->seccomp) + return 0; + return current->seccomp->mode; } -long prctl_set_seccomp(unsigned long seccomp_mode) +long prctl_set_seccomp(unsigned long seccomp_mode, unsigned long flags) { long ret; + struct seccomp_state *state, *cur_state; + cur_state = get_seccomp_state(current->seccomp); /* can set it only once to be even more secure */ ret = -EPERM; - if (unlikely(current->seccomp.mode)) + if (cur_state && unlikely(cur_state->mode)) goto out; ret = -EINVAL; - if (seccomp_mode && seccomp_mode <= NR_SECCOMP_MODES) { - current->seccomp.mode = seccomp_mode; - set_thread_flag(TIF_SECCOMP); + if (seccomp_mode <= 0 || seccomp_mode > NR_SECCOMP_MODES) + goto out; + + ret = -ENOMEM; + state = (cur_state ? seccomp_state_dup(cur_state) : + seccomp_state_new()); + if (!state) + goto out; + + if (seccomp_mode == PR_SECCOMP_MODE_STRICT) { #ifdef TIF_NOTSC disable_TSC(); #endif - ret = 0; } - out: + rcu_assign_pointer(current->seccomp, state); + synchronize_rcu(); + put_seccomp_state(cur_state); /* For the task */ + + /* Convert the ABI flag to the internal flag value. */ + if (seccomp_mode == PR_SECCOMP_MODE_FILTER && + (flags & PR_SECCOMP_FLAG_FILTER_ON_EXEC)) + state->flags |= SECCOMP_FLAG_ON_EXEC; + /* Encourage flag values to stay synchronized explicitly. */ + BUILD_BUG_ON(PR_SECCOMP_FLAG_FILTER_ON_EXEC != SECCOMP_FLAG_ON_EXEC); + + /* Only set the thread flag once after the new state is in place. */ + state->mode = seccomp_mode; + set_thread_flag(TIF_SECCOMP); + ret = 0; + +out: + put_seccomp_state(cur_state); /* for the get */ + return ret; +} + +long prctl_set_seccomp_filter(unsigned long syscall_nr, + char __user *user_filter) +{ + int nr; + long ret; + char filter[SECCOMP_MAX_FILTER_LENGTH]; + + ret = -EINVAL; + if (syscall_nr >= NR_syscalls || syscall_nr < 0) + goto out; + + ret = -EFAULT; + if (!user_filter || + strncpy_from_user(filter, user_filter, + sizeof(filter) - 1) < 0) + goto out; + + nr = (int) syscall_nr; + ret = seccomp_set_filter(nr, filter); + +out: + return ret; +} + +long prctl_clear_seccomp_filter(unsigned long syscall_nr) +{ + int nr = -1; + long ret; + + ret = -EINVAL; + if (syscall_nr >= NR_syscalls || syscall_nr < 0) + goto out; + + nr = (int) syscall_nr; + ret = seccomp_clear_filter(nr); + +out: + return ret; +} + +long prctl_get_seccomp_filter(unsigned long syscall_nr, char __user *dst, + unsigned long available) +{ + int ret, nr; + unsigned long copied; + char *buf = NULL; + ret = -EINVAL; + if (!available) + goto out; + /* Ignore extra buffer space. */ + if (available > SECCOMP_MAX_FILTER_LENGTH) + available = SECCOMP_MAX_FILTER_LENGTH; + + ret = -EINVAL; + if (syscall_nr >= NR_syscalls || syscall_nr < 0) + goto out; + nr = (int) syscall_nr; + + ret = -ENOMEM; + buf = kmalloc(available, GFP_KERNEL); + if (!buf) + goto out; + + ret = seccomp_get_filter(nr, buf, available); + if (ret < 0) + goto out; + + /* Include the NUL byte in the copy. */ + copied = copy_to_user(dst, buf, ret + 1); + ret = -ENOSPC; + if (copied) + goto out; + + ret = 0; +out: + kfree(buf); return ret; } diff --git a/kernel/seccomp.h b/kernel/seccomp.h new file mode 100644 index 0000000..5abd219 --- /dev/null +++ b/kernel/seccomp.h @@ -0,0 +1,74 @@ +/* + * seccomp/seccomp_filter shared internal prototypes and state. + * + * Copyright (C) 2011 Chromium OS Authors. + */ + +#ifndef __KERNEL_SECCOMP_H +#define __KERNEL_SECCOMP_H + +#include +#include + +/* #define SECCOMP_DEBUG 1 */ +#define NR_SECCOMP_MODES 2 + +/* Inherit the max filter length from the filtering engine. */ +#define SECCOMP_MAX_FILTER_LENGTH MAX_FILTER_STR_VAL + +/* Presently, flags only affect SECCOMP_FILTER. */ +#define _SECCOMP_FLAG_COMPAT 0 +#define _SECCOMP_FLAG_ON_EXEC 1 + +#define SECCOMP_FLAG_COMPAT (1 << (_SECCOMP_FLAG_COMPAT)) +#define SECCOMP_FLAG_ON_EXEC (1 << (_SECCOMP_FLAG_ON_EXEC)) + + +#ifdef CONFIG_SECCOMP_FILTER + +#define SECCOMP_FILTER_HASH_BITS 4 +#define SECCOMP_FILTER_HASH_SIZE (1 << SECCOMP_FILTER_HASH_BITS) + +struct seccomp_filter_table; +extern struct seccomp_filter_table *seccomp_filter_table_new(void); +extern int seccomp_copy_all_filters(struct seccomp_filter_table *, + const struct seccomp_filter_table *); +extern void seccomp_drop_all_filters(struct seccomp_state *); + +extern int seccomp_test_filters(struct seccomp_state *, int); +extern int seccomp_maybe_apply_filters(struct task_struct *, int); +extern void seccomp_filter_log_failure(int); + +#else /* CONFIG_SECCOMP_FILTER */ + +static inline void seccomp_filter_log_failure(int syscall) +{ +} + +static inline int seccomp_maybe_apply_filters(struct task_struct *tsk, + int syscall_nr) +{ + return -ENOSYS; +} + +static inline struct seccomp_filter_table *seccomp_filter_table_new(void) +{ + return ERR_PTR(-ENOSYS); +} + +static inline int seccomp_test_filters(struct seccomp_state *state, int nr) +{ + return -ENOSYS; +} + +extern inline int seccomp_copy_all_filters(struct seccomp_filter_table *dst, + const struct seccomp_filter_table *src) +{ + return 0; +} + +static inline void seccomp_drop_all_filters(struct seccomp_state *state) { } + +#endif /* CONFIG_SECCOMP_FILTER */ + +#endif /* __KERNEL_SECCOMP_H */ diff --git a/kernel/seccomp_filter.c b/kernel/seccomp_filter.c new file mode 100644 index 0000000..ff4e055 --- /dev/null +++ b/kernel/seccomp_filter.c @@ -0,0 +1,581 @@ +/* filter engine-based seccomp system call filtering. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 The Chromium OS Authors + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "seccomp.h" + +#define SECCOMP_MAX_FILTER_COUNT 512 +#define SECCOMP_WILDCARD_FILTER "1" + +struct seccomp_filter { + struct hlist_node node; + int syscall_nr; + struct syscall_metadata *data; + struct event_filter *event_filter; +}; + +struct seccomp_filter_table { + struct hlist_head heads[SECCOMP_FILTER_HASH_SIZE]; + int count; +}; + +struct seccomp_filter_table *seccomp_filter_table_new(void) +{ + struct seccomp_filter_table *t = + kzalloc(sizeof(struct seccomp_filter_table), GFP_KERNEL); + if (!t) + return ERR_PTR(-ENOMEM); + return t; +} + +static inline u32 syscall_hash(int syscall_nr) +{ + return hash_32(syscall_nr, SECCOMP_FILTER_HASH_BITS); +} + +static const char *get_filter_string(struct seccomp_filter *f) +{ + const char *str = SECCOMP_WILDCARD_FILTER; + if (!f) + return NULL; + + /* Missing event filters qualify as wildcard matches. */ + if (!f->event_filter) + return str; + +#ifdef CONFIG_FTRACE_SYSCALLS + str = ftrace_get_filter_string(f->event_filter); +#endif + return str; +} + +static struct seccomp_filter *alloc_seccomp_filter(int syscall_nr, + const char *filter_string) +{ + int err = -ENOMEM; + struct seccomp_filter *filter = kzalloc(sizeof(struct seccomp_filter), + GFP_KERNEL); + if (!filter) + goto fail; + + INIT_HLIST_NODE(&filter->node); + filter->syscall_nr = syscall_nr; + filter->data = syscall_nr_to_meta(syscall_nr); + + /* Treat a filter of SECCOMP_WILDCARD_FILTER as a wildcard and skip + * using a predicate at all. + */ + if (!strcmp(SECCOMP_WILDCARD_FILTER, filter_string)) + goto out; + + /* Argument-based filtering only works on ftrace-hooked syscalls. */ + if (!filter->data) { + err = -ENOSYS; + goto fail; + } + +#ifdef CONFIG_FTRACE_SYSCALLS + err = ftrace_parse_filter(&filter->event_filter, + filter->data->enter_event->event.type, + filter_string); + if (err) + goto fail; +#endif + +out: + return filter; + +fail: + kfree(filter); + return ERR_PTR(err); +} + +static void free_seccomp_filter(struct seccomp_filter *filter) +{ +#ifdef CONFIG_FTRACE_SYSCALLS + ftrace_free_filter(filter->event_filter); +#endif + kfree(filter); +} + +static struct seccomp_filter *copy_seccomp_filter(struct seccomp_filter *orig) +{ + return alloc_seccomp_filter(orig->syscall_nr, get_filter_string(orig)); +} + +/* Returns the matching filter or NULL */ +static struct seccomp_filter *find_filter(struct seccomp_state *state, + int syscall) +{ + struct hlist_node *this, *pos; + struct seccomp_filter *filter = NULL; + + u32 head = syscall_hash(syscall); + if (head >= SECCOMP_FILTER_HASH_SIZE) + goto out; + + hlist_for_each_safe(this, pos, &state->filters->heads[head]) { + filter = hlist_entry(this, struct seccomp_filter, node); + if (filter->syscall_nr == syscall) + goto out; + } + + filter = NULL; + +out: + return filter; +} + +/* Safely drops all filters for a given syscall. This should only be called + * on unattached seccomp_state objects. + */ +static void drop_filter(struct seccomp_state *state, int syscall_nr) +{ + struct seccomp_filter *filter = find_filter(state, syscall_nr); + if (!filter) + return; + + WARN_ON(state->filters->count == 0); + state->filters->count--; + hlist_del(&filter->node); + free_seccomp_filter(filter); +} + +/* This should only be called on unattached seccomp_state objects. */ +static int add_filter(struct seccomp_state *state, int syscall_nr, + char *filter_string) +{ + struct seccomp_filter *filter; + struct hlist_head *head; + char merged[SECCOMP_MAX_FILTER_LENGTH]; + int ret; + u32 hash = syscall_hash(syscall_nr); + + ret = -EINVAL; + if (state->filters->count == SECCOMP_MAX_FILTER_COUNT - 1) + goto out; + + filter_string = strstrip(filter_string); + + /* Disallow empty strings. */ + if (filter_string[0] == 0) + goto out; + + /* Get the right list head. */ + head = &state->filters->heads[hash]; + + /* Find out if there is an existing entry to append to and + * build the resultant filter string. The original filter can be + * destroyed here since the caller should be operating on a copy. + */ + filter = find_filter(state, syscall_nr); + if (filter) { + int expected = snprintf(merged, sizeof(merged), "(%s) && %s", + get_filter_string(filter), + filter_string); + ret = -E2BIG; + if (expected >= sizeof(merged) || expected < 0) + goto out; + filter_string = merged; + hlist_del(&filter->node); + free_seccomp_filter(filter); + } + + /* When in seccomp filtering mode, only allow additions. */ + ret = -EACCES; + if (filter == NULL && state->mode == PR_SECCOMP_MODE_FILTER) + goto out; + + ret = 0; + filter = alloc_seccomp_filter(syscall_nr, filter_string); + if (IS_ERR(filter)) { + ret = PTR_ERR(filter); + goto out; + } + + state->filters->count++; + hlist_add_head(&filter->node, head); +out: + return ret; +} + +/* Wrap optional ftrace syscall support. Returns 1 on match or if ftrace is not + * supported. + */ +static int do_ftrace_syscall_match(struct event_filter *event_filter) +{ + int err = 1; +#ifdef CONFIG_FTRACE_SYSCALLS + uint8_t syscall_state[64]; + + memset(syscall_state, 0, sizeof(syscall_state)); + + /* The generic tracing entry can remain zeroed. */ + err = ftrace_syscall_enter_state(syscall_state, sizeof(syscall_state), + NULL); + if (err) + return 0; + + err = filter_match_preds(event_filter, syscall_state); +#endif + return err; +} + +/* 1 on match, 0 otherwise. */ +static int filter_match_current(struct seccomp_filter *filter) +{ + /* If no event filter exists, we assume a wildcard match. */ + if (!filter->event_filter) + return 1; + + return do_ftrace_syscall_match(filter->event_filter); +} + +#ifndef KSTK_EIP +#define KSTK_EIP(x) 0L +#endif + +static const char *syscall_nr_to_name(int syscall) +{ + const char *syscall_name = "unknown"; + struct syscall_metadata *data = syscall_nr_to_meta(syscall); + if (data) + syscall_name = data->name; + return syscall_name; +} + +void seccomp_filter_log_failure(int syscall) +{ + printk(KERN_INFO + "%s[%d]: system call %d (%s) blocked at ip:%lx\n", + current->comm, task_pid_nr(current), syscall, + syscall_nr_to_name(syscall), KSTK_EIP(current)); +} + +/** + * seccomp_drop_all_filters - cleans up the filter list and frees the table + * @state: the seccomp_state to destroy the filters in. + */ +void seccomp_drop_all_filters(struct seccomp_state *state) +{ + struct hlist_node *this, *pos; + int head; + if (!state->filters) + return; + for (head = 0; head < SECCOMP_FILTER_HASH_SIZE; ++head) { + hlist_for_each_safe(this, pos, &state->filters->heads[head]) { + struct seccomp_filter *f = hlist_entry(this, + struct seccomp_filter, node); + WARN_ON(state->filters->count == 0); + hlist_del(this); + free_seccomp_filter(f); + state->filters->count--; + } + } + kfree(state->filters); +} + +/** + * seccomp_copy_all_filters - copies all filters from src to dst. + * + * @dst: seccomp_filter_table to populate. + * @src: table to read from. + * Returns non-zero on failure. + * Both the source and the destination should have no simultaneous + * writers, and dst should be exclusive to the caller. + */ +int seccomp_copy_all_filters(struct seccomp_filter_table *dst, + const struct seccomp_filter_table *src) +{ + struct seccomp_filter *filter; + int head, ret = 0; + BUG_ON(!dst || !src); + for (head = 0; head < SECCOMP_FILTER_HASH_SIZE; ++head) { + struct hlist_node *pos; + hlist_for_each_entry(filter, pos, &src->heads[head], node) { + struct seccomp_filter *new_filter = + copy_seccomp_filter(filter); + if (IS_ERR(new_filter)) { + ret = PTR_ERR(new_filter); + goto done; + } + hlist_add_head(&new_filter->node, + &dst->heads[head]); + dst->count++; + } + } + +done: + return ret; +} + +/** + * seccomp_show_filters - prints the filter state to a seq_file + * @state: the seccomp_state to enumerate the filter and bitmask of + * @m: the prepared seq_file to receive the data + * + * Returns 0 on a successful write. + */ +int seccomp_show_filters(struct seccomp_state *state, struct seq_file *m) +{ + int head; + struct hlist_node *pos; + struct seccomp_filter *filter; + int filtering = 0; + if (!state) + return 0; + if (!state->filters) + return 0; + + filtering = (state->mode == 2); + filtering &= !(state->flags & SECCOMP_FLAG_ON_EXEC); + seq_printf(m, "Filtering: %d\n", filtering); + seq_printf(m, "FilterCount: %d\n", state->filters->count); + for (head = 0; head < SECCOMP_FILTER_HASH_SIZE; ++head) { + hlist_for_each_entry(filter, pos, &state->filters->heads[head], + node) { + seq_printf(m, "SystemCall: %d (%s)\n", + filter->syscall_nr, + syscall_nr_to_name(filter->syscall_nr)); + seq_printf(m, "Filter: %s\n", + get_filter_string(filter)); + } + } + return 0; +} +EXPORT_SYMBOL_GPL(seccomp_show_filters); + +/** + * seccomp_maybe_apply_filters - conditionally applies seccomp filters + * @tsk: task to update + * @syscall_nr: current system call in progress + * tsk must already be in seccomp filter mode. + * + * Returns 0 if the call should be allowed or state has been updated. + * This call is only reach if no filters matched the current system call. + * In some cases, such as when the ON_EXEC flag is set, failure should + * not be terminal. + */ +int seccomp_maybe_apply_filters(struct task_struct *tsk, int syscall_nr) +{ + struct seccomp_state *state, *new_state = NULL; + int ret = -EACCES; + + /* There's no question of application if ON_EXEC is not set. */ + state = get_seccomp_state(tsk->seccomp); + if ((state->flags & SECCOMP_FLAG_ON_EXEC) == 0) + goto out; + + ret = 0; + if (syscall_nr != __NR_execve) + goto out; + + new_state = seccomp_state_dup(state); + ret = -ENOMEM; + if (!new_state) + goto out; + + ret = 0; + new_state->flags &= ~(SECCOMP_FLAG_ON_EXEC); + rcu_assign_pointer(tsk->seccomp, new_state); + synchronize_rcu(); + put_seccomp_state(state); /* for the task */ + +out: + put_seccomp_state(state); /* for the get */ + return ret; +} + +/** + * seccomp_test_filters - tests 'current' against the given syscall + * @state: seccomp_state of current to use. + * @syscall: number of the system call to test + * + * Returns 0 on ok and non-zero on error/failure. + */ +int seccomp_test_filters(struct seccomp_state *state, int syscall) +{ + struct seccomp_filter *filter = NULL; + int ret; + +#ifdef CONFIG_COMPAT + ret = -EPERM; + if (is_compat_task() == !!(state->flags & SECCOMP_FLAG_COMPAT)) { + printk(KERN_INFO "%s[%d]: seccomp filter compat() mismatch.\n", + current->comm, task_pid_nr(current)); + goto out; + } +#endif + + ret = 0; + filter = find_filter(state, syscall); + if (filter && filter_match_current(filter)) + goto out; + + ret = -EACCES; +out: + return ret; +} + +/** + * seccomp_get_filter - copies the filter_string into "buf" + * @syscall_nr: system call number to look up + * @buf: destination buffer + * @bufsize: available space in the buffer. + * + * Looks up the filter for the given system call number on current. If found, + * the string length of the NUL-terminated buffer is returned and < 0 is + * returned on error. The NUL byte is not included in the length. + */ +long seccomp_get_filter(int syscall_nr, char *buf, unsigned long bufsize) +{ + struct seccomp_state *state; + struct seccomp_filter *filter; + long ret = -ENOENT; + + if (bufsize > SECCOMP_MAX_FILTER_LENGTH) + bufsize = SECCOMP_MAX_FILTER_LENGTH; + + state = get_seccomp_state(current->seccomp); + if (!state) + goto out; + + filter = find_filter(state, syscall_nr); + if (!filter) + goto out; + + ret = strlcpy(buf, get_filter_string(filter), bufsize); + if (ret >= bufsize) { + ret = -ENOSPC; + goto out; + } + /* Zero out any remaining buffer, just in case. */ + memset(buf + ret, 0, bufsize - ret); +out: + put_seccomp_state(state); + return ret; +} +EXPORT_SYMBOL_GPL(seccomp_get_filter); + +/** + * seccomp_clear_filter: clears the seccomp filter for a syscall. + * @syscall_nr: the system call number to clear filters for. + * + * (acts as a frontend for seccomp_set_filter. All restrictions + * apply) + * + * Returns 0 on success. + */ +long seccomp_clear_filter(int syscall_nr) +{ + return seccomp_set_filter(syscall_nr, NULL); +} +EXPORT_SYMBOL_GPL(seccomp_clear_filter); + +/** + * seccomp_set_filter: - Adds/extends a seccomp filter for a syscall. + * @syscall_nr: system call number to apply the filter to. + * @filter: ftrace filter string to apply. + * + * Context: User context only. This function may sleep on allocation and + * operates on current. current must be attempting a system call + * when this is called. + * + * New filters may be added for system calls when the current task is + * not in a secure computing mode (seccomp). Otherwise, filters may only + * be added to already filtered system call entries. Any additions will + * be &&'d with the existing filter string to ensure no expansion of privileges + * will be possible. + * + * Returns 0 on success or an errno on failure. + */ +long seccomp_set_filter(int syscall_nr, char *filter) +{ + struct seccomp_state *state, *orig_state; + long ret = -EINVAL; + + orig_state = get_seccomp_state(current->seccomp); + + /* Prior to mutating the state, create a duplicate to avoid modifying + * the behavior of other instances sharing the state and ensure + * consistency. + */ + state = (orig_state ? seccomp_state_dup(orig_state) : + seccomp_state_new()); + if (!state) { + ret = -ENOMEM; + goto out; + } + + /* A NULL filter doubles as a drop value, but the exposed prctl + * interface requires a trip through seccomp_clear_filter(). + * Filter dropping is allowed across the is_compat_task() barrier. + */ + ret = 0; + if (filter == NULL) { + drop_filter(state, syscall_nr); + goto assign; + } + + /* Avoid amiguous filters which may have been inherited from a parent + * with different syscall numbers for the logically same calls. + */ +#ifdef CONFIG_COMPAT + ret = -EACCES; + if (is_compat_task() != !!(state->flags & SECCOMP_FLAG_COMPAT)) { + if (state->filters->count) + goto free_state; + /* It's safe to add if there are no existing ambiguous rules.*/ + if (is_compat_task()) + state->flags |= SECCOMP_FLAG_COMPAT; + else + state->flags &= ~(SECCOMP_FLAG_COMPAT); + } +#endif + + ret = add_filter(state, syscall_nr, filter); + if (ret) + goto free_state; + +assign: + rcu_assign_pointer(current->seccomp, state); + synchronize_rcu(); + put_seccomp_state(orig_state); /* for the task */ +out: + put_seccomp_state(orig_state); /* for the get */ + return ret; + +free_state: + put_seccomp_state(orig_state); /* for the get */ + put_seccomp_state(state); /* drop the dup/new */ + return ret; +} +EXPORT_SYMBOL_GPL(seccomp_set_filter); diff --git a/kernel/sys.c b/kernel/sys.c index af468ed..d29003a 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -1698,12 +1698,23 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, case PR_SET_ENDIAN: error = SET_ENDIAN(me, arg2); break; - case PR_GET_SECCOMP: error = prctl_get_seccomp(); break; case PR_SET_SECCOMP: - error = prctl_set_seccomp(arg2); + error = prctl_set_seccomp(arg2, arg3); + break; + case PR_SET_SECCOMP_FILTER: + error = prctl_set_seccomp_filter(arg2, + (char __user *) arg3); + break; + case PR_CLEAR_SECCOMP_FILTER: + error = prctl_clear_seccomp_filter(arg2); + break; + case PR_GET_SECCOMP_FILTER: + error = prctl_get_seccomp_filter(arg2, + (char __user *) arg3, + arg4); break; case PR_GET_TSC: error = GET_TSC_CTL(arg2); -- 1.7.0.4 From blogic@openwrt.org Thu May 12 07:56:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 07:56:27 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:49344 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491039Ab1ELF4Y (ORCPT ); Thu, 12 May 2011 07:56:24 +0200 Message-ID: <4DCB76E5.3070703@openwrt.org> Date: Thu, 12 May 2011 07:57:57 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: Ralf Baechle CC: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] MIPS: lantiq: Add missing include to mach-easy50712.c References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> <1305145347-32605-2-git-send-email-ddaney@caviumnetworks.com> <20110511212538.GB17315@linux-mips.org> In-Reply-To: <20110511212538.GB17315@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29949 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips On 11/05/11 23:25, Ralf Baechle wrote: > Thanks, folded into "MIPS: Lantiq: Add etop board support". > > Ralf > > Hi, the include should be in arch/lantiq/devices.h and not the mach-*.c file. this got lost int he folding and i thought we fixed it yesterday already . John From mingo@elte.hu Thu May 12 09:49:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 09:49:44 +0200 (CEST) Received: from mx2.mail.elte.hu ([157.181.151.9]:46235 "EHLO mx2.mail.elte.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491039Ab1ELHtg (ORCPT ); Thu, 12 May 2011 09:49:36 +0200 Received: from elvis.elte.hu ([157.181.1.14]) by mx2.mail.elte.hu with esmtp (Exim) id 1QKQdp-0007rv-Fa from ; Thu, 12 May 2011 09:49:12 +0200 Received: by elvis.elte.hu (Postfix, from userid 1004) id 1DF953E2300; Thu, 12 May 2011 09:48:46 +0200 (CEST) Date: Thu, 12 May 2011 09:48:50 +0200 From: Ingo Molnar To: Will Drewry Cc: linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, jmorris@namei.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Message-ID: <20110512074850.GA9937@elte.hu> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305169376-2363-1-git-send-email-wad@chromium.org> User-Agent: Mutt/1.5.20 (2009-08-17) Received-SPF: neutral (mx2.mail.elte.hu: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-SpamScore: -2.0 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=-2.0 required=5.9 tests=BAYES_00 autolearn=no SpamAssassin version=3.3.1 -2.0 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29950 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips Ok, i like the direction here, but i think the ABI should be done differently. In this patch the ftrace event filter mechanism is used: * Will Drewry wrote: > +static struct seccomp_filter *alloc_seccomp_filter(int syscall_nr, > + const char *filter_string) > +{ > + int err = -ENOMEM; > + struct seccomp_filter *filter = kzalloc(sizeof(struct seccomp_filter), > + GFP_KERNEL); > + if (!filter) > + goto fail; > + > + INIT_HLIST_NODE(&filter->node); > + filter->syscall_nr = syscall_nr; > + filter->data = syscall_nr_to_meta(syscall_nr); > + > + /* Treat a filter of SECCOMP_WILDCARD_FILTER as a wildcard and skip > + * using a predicate at all. > + */ > + if (!strcmp(SECCOMP_WILDCARD_FILTER, filter_string)) > + goto out; > + > + /* Argument-based filtering only works on ftrace-hooked syscalls. */ > + if (!filter->data) { > + err = -ENOSYS; > + goto fail; > + } > + > +#ifdef CONFIG_FTRACE_SYSCALLS > + err = ftrace_parse_filter(&filter->event_filter, > + filter->data->enter_event->event.type, > + filter_string); > + if (err) > + goto fail; > +#endif > + > +out: > + return filter; > + > +fail: > + kfree(filter); > + return ERR_PTR(err); > +} Via a prctl() ABI: > --- a/kernel/sys.c > +++ b/kernel/sys.c > @@ -1698,12 +1698,23 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, > case PR_SET_ENDIAN: > error = SET_ENDIAN(me, arg2); > break; > - > case PR_GET_SECCOMP: > error = prctl_get_seccomp(); > break; > case PR_SET_SECCOMP: > - error = prctl_set_seccomp(arg2); > + error = prctl_set_seccomp(arg2, arg3); > + break; > + case PR_SET_SECCOMP_FILTER: > + error = prctl_set_seccomp_filter(arg2, > + (char __user *) arg3); > + break; > + case PR_CLEAR_SECCOMP_FILTER: > + error = prctl_clear_seccomp_filter(arg2); > + break; > + case PR_GET_SECCOMP_FILTER: > + error = prctl_get_seccomp_filter(arg2, > + (char __user *) arg3, > + arg4); To restrict execution to system calls. Two observations: 1) We already have a specific ABI for this: you can set filters for events via an event fd. Why not extend that mechanism instead and improve *both* your sandboxing bits and the events code? This new seccomp code has a lot more to do with trace event filters than the minimal old seccomp code ... kernel/trace/trace_event_filter.c is 2000 lines of tricky code that interprets the ASCII filter expressions. kernel/seccomp.c is 86 lines of mostly trivial code. 2) Why should this concept not be made available wider, to allow the restriction of not just system calls but other security relevant components of the kernel as well? This too, if you approach the problem via the events code, will be a natural end result, while if you approach it from the seccomp prctl angle it will be a limited hack only. Note, the end result will be the same - just using a different ABI. So i really think the ABI itself should be closer related to the event code. What this "seccomp" code does is that it uses specific syscall events to restrict execution of certain event generating codepaths, such as system calls. Thanks, Ingo From kees.cook@canonical.com Thu May 12 11:27:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 11:27:59 +0200 (CEST) Received: from smtp.outflux.net ([198.145.64.163]:50968 "EHLO smtp.outflux.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491050Ab1ELJ1x (ORCPT ); Thu, 12 May 2011 11:27:53 +0200 Received: from www.outflux.net (serenity-end.outflux.net [10.2.0.2]) by vinyl.outflux.net (8.14.3/8.14.3/Debian-9.2ubuntu1) with ESMTP id p4C9OOuX016731; Thu, 12 May 2011 02:24:25 -0700 Date: Thu, 12 May 2011 02:24:24 -0700 From: Kees Cook To: Ingo Molnar Cc: Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , agl@chromium.org, jmorris@namei.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Message-ID: <20110512092424.GO28888@outflux.net> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110512074850.GA9937@elte.hu> Organization: Canonical X-MIMEDefang-Filter: outflux$Revision: 1.316 $ X-HELO: www.outflux.net X-Scanned-By: MIMEDefang 2.69 on 10.2.0.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29951 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kees.cook@canonical.com Precedence: bulk X-list: linux-mips Hi, On Thu, May 12, 2011 at 09:48:50AM +0200, Ingo Molnar wrote: > 1) We already have a specific ABI for this: you can set filters for events via > an event fd. > > Why not extend that mechanism instead and improve *both* your sandboxing > bits and the events code? This new seccomp code has a lot more > to do with trace event filters than the minimal old seccomp code ... Would this require privileges to get the event fd to start with? If so, I would prefer to avoid that, since using prctl() as shown in the patch set won't require any privs. -Kees -- Kees Cook Ubuntu Security Team From ralf@linux-mips.org Thu May 12 11:58:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 11:59:00 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42477 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491161Ab1ELJ66 (ORCPT ); Thu, 12 May 2011 11:58:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CA0C1d012311; Thu, 12 May 2011 11:00:12 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CA0ArF012308; Thu, 12 May 2011 11:00:10 +0100 Date: Thu, 12 May 2011 11:00:10 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: Robert Millan , David Daney , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] MIPS: Set ELF AT_PLATFORM string for BMIPS processors Message-ID: <20110512100010.GA11400@linux-mips.org> References: <7f27896d6ff6598a4b9e003454ef10e0@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7f27896d6ff6598a4b9e003454ef10e0@localhost> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29952 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks Kevin! Ralf From ralf@linux-mips.org Thu May 12 11:59:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 11:59:24 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42485 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491164Ab1ELJ7N (ORCPT ); Thu, 12 May 2011 11:59:13 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CA0aeu012348; Thu, 12 May 2011 11:00:36 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CA0Zmw012347; Thu, 12 May 2011 11:00:35 +0100 Date: Thu, 12 May 2011 11:00:35 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: Robert Millan , David Daney , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] MIPS: Set ELF AT_PLATFORM string for Loongson2 processors Message-ID: <20110512100035.GB11400@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29953 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks Kevin! Ralf From mingo@elte.hu Thu May 12 12:50:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 12:50:14 +0200 (CEST) Received: from mx3.mail.elte.hu ([157.181.1.138]:36706 "EHLO mx3.mail.elte.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491164Ab1ELKuI (ORCPT ); Thu, 12 May 2011 12:50:08 +0200 Received: from elvis.elte.hu ([157.181.1.14]) by mx3.mail.elte.hu with esmtp (Exim) id 1QKTSR-0000NH-23 from ; Thu, 12 May 2011 12:49:32 +0200 Received: by elvis.elte.hu (Postfix, from userid 1004) id 0DDB83E2526; Thu, 12 May 2011 12:49:11 +0200 (CEST) Date: Thu, 12 May 2011 12:49:16 +0200 From: Ingo Molnar To: Kees Cook Cc: Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , agl@chromium.org, jmorris@namei.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Message-ID: <20110512104916.GJ9937@elte.hu> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> <20110512092424.GO28888@outflux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110512092424.GO28888@outflux.net> User-Agent: Mutt/1.5.20 (2009-08-17) Received-SPF: neutral (mx3: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-SpamScore: -2.0 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=-2.0 required=5.9 tests=BAYES_00 autolearn=no SpamAssassin version=3.3.1 -2.0 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29954 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips * Kees Cook wrote: > Hi, > > On Thu, May 12, 2011 at 09:48:50AM +0200, Ingo Molnar wrote: > > 1) We already have a specific ABI for this: you can set filters for events via > > an event fd. > > > > Why not extend that mechanism instead and improve *both* your sandboxing > > bits and the events code? This new seccomp code has a lot more > > to do with trace event filters than the minimal old seccomp code ... > > Would this require privileges to get the event fd to start with? [...] No special privileges with the default perf_events_paranoid value. > [...] If so, I would prefer to avoid that, since using prctl() as shown in > the patch set won't require any privs. and we could also explicitly allow syscall events without any privileges, regardless of the setting of 'perf_events_paranoid' config value. Obviously a sandboxing host process wants to run with as low privileges as it can. Thanks, Ingo From jmorris@namei.org Thu May 12 13:37:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 13:37:41 +0200 (CEST) Received: from tundra.namei.org ([65.99.196.166]:60399 "EHLO tundra.namei.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491164Ab1ELLhe (ORCPT ); Thu, 12 May 2011 13:37:34 +0200 Received: from localhost (localhost [127.0.0.1]) by tundra.namei.org (8.13.1/8.13.1) with ESMTP id p4CBXROC031677; Thu, 12 May 2011 07:33:27 -0400 Date: Thu, 12 May 2011 21:33:27 +1000 (EST) From: James Morris To: Will Drewry cc: linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , Ingo Molnar , kees.cook@canonical.com, agl@chromium.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering In-Reply-To: <1305169376-2363-1-git-send-email-wad@chromium.org> Message-ID: References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> User-Agent: Alpine 2.00 (LRH 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29955 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jmorris@namei.org Precedence: bulk X-list: linux-mips On Wed, 11 May 2011, Will Drewry wrote: > +void seccomp_filter_log_failure(int syscall) > +{ > + printk(KERN_INFO > + "%s[%d]: system call %d (%s) blocked at ip:%lx\n", > + current->comm, task_pid_nr(current), syscall, > + syscall_nr_to_name(syscall), KSTK_EIP(current)); > +} I think it'd be a good idea to utilize the audit facility here. - James -- James Morris From jmorris@namei.org Thu May 12 13:49:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 13:49:11 +0200 (CEST) Received: from tundra.namei.org ([65.99.196.166]:51179 "EHLO tundra.namei.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491164Ab1ELLtE (ORCPT ); Thu, 12 May 2011 13:49:04 +0200 Received: from localhost (localhost [127.0.0.1]) by tundra.namei.org (8.13.1/8.13.1) with ESMTP id p4CBiGhI031727; Thu, 12 May 2011 07:44:16 -0400 Date: Thu, 12 May 2011 21:44:15 +1000 (EST) From: James Morris To: Ingo Molnar cc: Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering In-Reply-To: <20110512074850.GA9937@elte.hu> Message-ID: References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> User-Agent: Alpine 2.00 (LRH 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29956 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jmorris@namei.org Precedence: bulk X-list: linux-mips On Thu, 12 May 2011, Ingo Molnar wrote: > > 2) Why should this concept not be made available wider, to allow the > restriction of not just system calls but other security relevant components > of the kernel as well? Because the aim of this is to reduce the attack surface of the syscall interface. LSM is the correct level of abstraction for general security mediation, because it allows you to take into account all relevant security information in a race-free context. > This too, if you approach the problem via the events code, will be a natural > end result, while if you approach it from the seccomp prctl angle it will be > a limited hack only. I'd say it's a well-defined and readily understandable feature. - James -- James Morris From fweisbec@gmail.com Thu May 12 14:16:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 14:16:07 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:45326 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491164Ab1ELMQB (ORCPT ); Thu, 12 May 2011 14:16:01 +0200 Received: by gyh20 with SMTP id 20so569903gyh.36 for ; Thu, 12 May 2011 05:15:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; bh=txQMqIi9LZn4lEjkTGqv0UFvkSM1vSswuUucy6Gg13E=; b=wZ0cfcdqYS2PnPAOe53CcmUMPamg+gjU1wevIOV9gr9jKyak3a66QV8/nsgWCfMhLN +UGuBkBYNRh22v6qMYS0VxzoGu3/Pooz0w9COz7mdyoowfPEjdQa/XnfXbP+2xo+4lKW iLvk3waepMwth1E0NiJZqYA5i1UBYI3TC263Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; b=UnpCsnhpFpmMhVoAsNI4TJ1BFTEO26hPP852i1SbwUbR2zagzzwfumrZZK7CU2JnE/ C7o4FWjOvPt8LJGJKwLzy24/6ZL6jd1cxA4qyDAwHC8GgWNEejqh7DPaoOFfL409ObeS l0FHqB9Pl2+MSN14OdaNa6QLt36pukfGNPfmo= Received: by 10.236.185.105 with SMTP id t69mr143272yhm.18.1305202552916; Thu, 12 May 2011 05:15:52 -0700 (PDT) Received: from localhost (69.20.196-77.rev.gaoland.net [77.196.20.69]) by mx.google.com with ESMTPS id e8sm546316yhm.43.2011.05.12.05.15.44 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 12 May 2011 05:15:51 -0700 (PDT) Date: Thu, 12 May 2011 14:15:42 +0200 From: Frederic Weisbecker To: Ingo Molnar Cc: Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Eric Paris , kees.cook@canonical.com, agl@chromium.org, jmorris@namei.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Message-ID: <20110512121539.GA7410@nowhere> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110512074850.GA9937@elte.hu> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29957 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fweisbec@gmail.com Precedence: bulk X-list: linux-mips On Thu, May 12, 2011 at 09:48:50AM +0200, Ingo Molnar wrote: > To restrict execution to system calls. > > Two observations: > > 1) We already have a specific ABI for this: you can set filters for events via > an event fd. > > Why not extend that mechanism instead and improve *both* your sandboxing > bits and the events code? This new seccomp code has a lot more > to do with trace event filters than the minimal old seccomp code ... > > kernel/trace/trace_event_filter.c is 2000 lines of tricky code that > interprets the ASCII filter expressions. kernel/seccomp.c is 86 lines of > mostly trivial code. > > 2) Why should this concept not be made available wider, to allow the > restriction of not just system calls but other security relevant components > of the kernel as well? > > This too, if you approach the problem via the events code, will be a natural > end result, while if you approach it from the seccomp prctl angle it will be > a limited hack only. > > Note, the end result will be the same - just using a different ABI. > > So i really think the ABI itself should be closer related to the event code. > What this "seccomp" code does is that it uses specific syscall events to > restrict execution of certain event generating codepaths, such as system calls. > > Thanks, > > Ingo What's positive with that approach is that the code is all there already. Create a perf event for a given trace event, attach a filter to it. What needs to be added is an override of the effect of the filter. By default it's dropping the event, but there may be different flavours, including sending a signal. All in one, extending the current code to allow that looks trivial. The negative points are that * trace events are supposed to stay passive and not act on the system, except doing some endpoint things like writing to a buffer. We can't call do_exit() from a tracepoint for example, preemption is disabled there. * Also, is it actually relevant to extend that seccomp filtering to other events than syscalls? Exposing kernel events to filtering sounds actually to me bringing a new potential security issue. But with fine restrictions this can probably be dealt with. Especially if by default only syscalls can be filtered * I think Peter did not want to give such "active" role to perf in the system. From ralf@linux-mips.org Thu May 12 14:49:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 14:49:12 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57346 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491174Ab1ELMtG (ORCPT ); Thu, 12 May 2011 14:49:06 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CCoavX026310; Thu, 12 May 2011 13:50:36 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CCoZNW026307; Thu, 12 May 2011 13:50:35 +0100 Date: Thu, 12 May 2011 13:50:35 +0100 From: Ralf Baechle To: Yury Polyanskiy Cc: linux-mips@linux-mips.org, Jason Wessel Subject: Re: [PATCH] Notifier chain called twice Message-ID: <20110512125035.GC11400@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29958 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 12, 2011 at 02:44:58AM -0400, Yury Polyanskiy wrote: Shouldn't the conditional call be moved to an earlier location as below patch does? Then again once we're in die() this probably doesn't matter terribly much anymore. Ralf Signed-off-by: Ralf Baechle arch/mips/kernel/traps.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 71350f7..e9b3af2 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -374,7 +374,8 @@ void __noreturn die(const char *str, struct pt_regs *regs) unsigned long dvpret = dvpe(); #endif /* CONFIG_MIPS_MT_SMTC */ - notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV); + if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) + sig = 0; console_verbose(); spin_lock_irq(&die_lock); @@ -383,9 +384,6 @@ void __noreturn die(const char *str, struct pt_regs *regs) mips_mt_regdump(dvpret); #endif /* CONFIG_MIPS_MT_SMTC */ - if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) - sig = 0; - printk("%s[#%d]:\n", str, ++die_counter); show_registers(regs); add_taint(TAINT_DIE); From mingo@elte.hu Thu May 12 15:01:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 15:01:51 +0200 (CEST) Received: from mx3.mail.elte.hu ([157.181.1.138]:41708 "EHLO mx3.mail.elte.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491174Ab1ELNBo (ORCPT ); Thu, 12 May 2011 15:01:44 +0200 Received: from elvis.elte.hu ([157.181.1.14]) by mx3.mail.elte.hu with esmtp (Exim) id 1QKVVw-0008PC-P6 from ; Thu, 12 May 2011 15:01:17 +0200 Received: by elvis.elte.hu (Postfix, from userid 1004) id CB3B83E2526; Thu, 12 May 2011 15:01:04 +0200 (CEST) Date: Thu, 12 May 2011 15:01:04 +0200 From: Ingo Molnar To: James Morris Cc: Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Message-ID: <20110512130104.GA2912@elte.hu> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Received-SPF: neutral (mx3: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-SpamScore: -2.0 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=-2.0 required=5.9 tests=BAYES_00 autolearn=no SpamAssassin version=3.3.1 -2.0 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29959 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips * James Morris wrote: > On Thu, 12 May 2011, Ingo Molnar wrote: > > > 2) Why should this concept not be made available wider, to allow the > > restriction of not just system calls but other security relevant components > > of the kernel as well? > > Because the aim of this is to reduce the attack surface of the syscall > interface. What i suggest achieves the same, my argument is that we could aim it to be even more flexible and even more useful. > LSM is the correct level of abstraction for general security mediation, > because it allows you to take into account all relevant security information > in a race-free context. I don't care about LSM though, i find it poorly designed. The approach implemented here, the ability for *unprivileged code* to define (the seeds of ...) flexible security policies, in a proper Linuxish way, which is inherited along the task parent/child hieararchy and which allows nesting etc. is a *lot* more flexible. What Will implemented here is pretty huge in my opinion: it turns security from a root-only kind of weird hack into an essential component of its APIs, available to *any* app not just the select security policy/mechanism chosen by the distributor ... If implemented properly this could replace LSM in the long run. As a prctl() hack bound to seccomp (which, by all means, is a natural extension to the current seccomp ABI, so perfectly fine if we only want that scope), that is much less likely to happen. And if we merge the seccomp interface prematurely then interest towards a more flexible approach will disappear, so either we do it properly now or it will take some time for someone to come around and do it ... Also note that i do not consider the perf events ABI itself cast into stone - and we could very well add a new system call for this, independent of perf events. I just think that the seccomp scope itself is exciting but looks limited to what the real potential of this could be. > > This too, if you approach the problem via the events code, will be a natural > > end result, while if you approach it from the seccomp prctl angle it will be > > a limited hack only. > > I'd say it's a well-defined and readily understandable feature. Note, it was me who suggested this very event-filter-engine design a year ago, when the first submission still used a crude bitmap of allowed seccomp syscalls: http://lwn.net/Articles/332974/ Funnily enough, back then you wrote this: " I'm concerned that we're seeing yet another security scheme being designed on the fly, without a well-formed threat model, and without taking into account lessons learned from the seemingly endless parade of similar, failed schemes. " so when and how did your opinion of this scheme turn from it being an "endless parade of failed schemes" to it being a "well-defined and readily understandable feature"? :-) The idea itself has not changed since last year, what happened is that the filter engine got a couple of new features and Will has separated it out and has implemented a working prototype for sandboxing. What i do here is to suggest *further* steps down the same road, now that we see that this scheme can indeed be used to implement sandboxing ... I think it's a valid line of inquiry. Thanks, Ingo From ralf@linux-mips.org Thu May 12 16:10:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 16:10:49 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60854 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491177Ab1ELOKn (ORCPT ); Thu, 12 May 2011 16:10:43 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CEC9RE000523; Thu, 12 May 2011 15:12:09 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CEC8R2000521; Thu, 12 May 2011 15:12:08 +0100 Date: Thu, 12 May 2011 15:12:08 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: David Daney , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] MIPS: Replace _PAGE_READ with _PAGE_NO_READ Message-ID: <20110512141208.GA28063@linux-mips.org> References: <7aa38c32b7748a95e814e5bb0583f967@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7aa38c32b7748a95e814e5bb0583f967@localhost> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29960 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks Kevin! Ralf From ralf@linux-mips.org Thu May 12 16:11:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 16:11:15 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60859 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491179Ab1ELOKv (ORCPT ); Thu, 12 May 2011 16:10:51 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CECHUM000539; Thu, 12 May 2011 15:12:17 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CECHlJ000537; Thu, 12 May 2011 15:12:17 +0100 Date: Thu, 12 May 2011 15:12:17 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: David Daney , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/4] MIPS: Add dummy _PAGE_NO_EXEC field for R3000 and 64BIT_PHYS_ADDR cases Message-ID: <20110512141217.GB28063@linux-mips.org> References: <7aa38c32b7748a95e814e5bb0583f967@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29961 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks Kevin! Ralf From ralf@linux-mips.org Thu May 12 16:11:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 16:11:46 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60864 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491182Ab1ELOLA (ORCPT ); Thu, 12 May 2011 16:11:00 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CECPuN000555; Thu, 12 May 2011 15:12:25 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CECP54000554; Thu, 12 May 2011 15:12:25 +0100 Date: Thu, 12 May 2011 15:12:25 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: David Daney , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/4] MIPS: Clean up protection_map[] initialization Message-ID: <20110512141225.GC28063@linux-mips.org> References: <7aa38c32b7748a95e814e5bb0583f967@localhost> <305a554e4aa54669dfff53283de096eb@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <305a554e4aa54669dfff53283de096eb@localhost> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29962 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks Kevin! Ralf From ralf@linux-mips.org Thu May 12 16:12:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 16:12:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60870 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491180Ab1ELOLH (ORCPT ); Thu, 12 May 2011 16:11:07 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CECX4o000576; Thu, 12 May 2011 15:12:33 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CECXKN000568; Thu, 12 May 2011 15:12:33 +0100 Date: Thu, 12 May 2011 15:12:33 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: David Daney , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/4] MIPS: Remove unused PAGE_* definitions Message-ID: <20110512141233.GD28063@linux-mips.org> References: <7aa38c32b7748a95e814e5bb0583f967@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29963 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks Kevin! Ralf From wad@chromium.org Thu May 12 18:26:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 18:26:37 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:38447 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491184Ab1ELQ03 convert rfc822-to-8bit (ORCPT ); Thu, 12 May 2011 18:26:29 +0200 Received: by fxm14 with SMTP id 14so1601757fxm.36 for ; Thu, 12 May 2011 09:26:24 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.127.210 with SMTP id h18mr459652fas.77.1305217581776; Thu, 12 May 2011 09:26:21 -0700 (PDT) Received: by 10.223.101.204 with HTTP; Thu, 12 May 2011 09:26:21 -0700 (PDT) In-Reply-To: <20110512130104.GA2912@elte.hu> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> <20110512130104.GA2912@elte.hu> Date: Thu, 12 May 2011 11:26:21 -0500 Message-ID: Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering From: Will Drewry To: Ingo Molnar Cc: James Morris , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29964 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wad@chromium.org Precedence: bulk X-list: linux-mips [Thanks to everyone for the continued feedback and insights - I appreciate it!] On Thu, May 12, 2011 at 8:01 AM, Ingo Molnar wrote: > > * James Morris wrote: > >> On Thu, 12 May 2011, Ingo Molnar wrote: >> >> > 2) Why should this concept not be made available wider, to allow the >> >    restriction of not just system calls but other security relevant components >> >    of the kernel as well? >> >> Because the aim of this is to reduce the attack surface of the syscall >> interface. > > What i suggest achieves the same, my argument is that we could aim it to be > even more flexible and even more useful. > >> LSM is the correct level of abstraction for general security mediation, >> because it allows you to take into account all relevant security information >> in a race-free context. > > I don't care about LSM though, i find it poorly designed. > > The approach implemented here, the ability for *unprivileged code* to define > (the seeds of ...) flexible security policies, in a proper Linuxish way, which > is inherited along the task parent/child hieararchy and which allows nesting > etc. is a *lot* more flexible. > > What Will implemented here is pretty huge in my opinion: it turns security from > a root-only kind of weird hack into an essential component of its APIs, > available to *any* app not just the select security policy/mechanism chosen by > the distributor ... > > If implemented properly this could replace LSM in the long run. > > As a prctl() hack bound to seccomp (which, by all means, is a natural extension > to the current seccomp ABI, so perfectly fine if we only want that scope), that > is much less likely to happen. > > And if we merge the seccomp interface prematurely then interest towards a more > flexible approach will disappear, so either we do it properly now or it will > take some time for someone to come around and do it ... > > Also note that i do not consider the perf events ABI itself cast into stone - > and we could very well add a new system call for this, independent of perf > events. I just think that the seccomp scope itself is exciting but looks > limited to what the real potential of this could be. I agree with you on many of these points! However, I don't think that the views around LSMs, perf/ftrace infrastructure, or the current seccomp filtering implementation are necessarily in conflict. Here is my understanding of how the different worlds fit together and where I see this patchset living, along with where I could see future work going. Perhaps I'm being a trifle naive, but here goes anyway: 1. LSMs provide a global mechanism for hooking "security relevant" events at a point where all the incoming user-sourced data has been preprocessed and moved into userspace. The hooks are called every time one of those boundaries are crossed. 2. Perf and the ftrace infrastructure provide global function tracing and system call hooks with direct access to the caller's registers (and memory). 3. seccomp (as it exists today) provides a global system call entry hook point with a binary per-process decision about whether to provide "secure computing" behavior. When I boil that down to abstractions, I see: A. Globally scoped: LSMs, ftrace/perf B. Locally/process scoped: seccomp The result of that logical equivalence is that I see room for: I. A per-process, locally scoped security event hooking interface (the proposed changes in this patchset) II. A globally scoped security event hooking interface _prior_ to argument processing III. A globally scoped security event hooking interface _post_ argument processing II and III could be reduced further if I assume that ftrace/perf provides (II) and a simple intermediary layer (hook entry/exit) provides the argument processing steps that then call out a global security policy system. The driving motivation for this patchset is kernel attack surface reduction, but that need arises because we lack a process-scoped mechanism for making security decisions -- everything is global: creds/DAC, containers, LSM, etc. Adding ftrace filtering to agl's original bitmask-seccomp proposal opens up the process-local security world. At present, it can limit the attack surface with simple binary filters or apply limited security policy through the use of filter strings. Based on your mails, I see two main deficiencies in my proposed patchset: a. Deep argument analysis: Any arguments that live in user memory needs to be copied into the kernel, then checked, and substituted for the actual system call, then have the original pointers restored (when applicable) on system call exit. There is a large overhead here and the LSM hooks provide much of this support on a global level. b. Lack of support for non-system call events. For (a), if the long term view of ftrace/perf & LSMs is that LSM-like functionality will live on top of the ftrace/perf infrastructure, then adding support for the intermediary layer to analyze arguments will come with time. It's also likely that for process-local stuff (e.g.,) a new predicate could be added to callback to a userspace supervisor, or even a more generic ability for modules to register new predicates/functions in the filtering engine itself -- like "fd == 1 && check_path(path) == '/etc/safe.conf'" or "check_xattr(path, expected)". Of course, I'm just making stuff up right now :) For (b), we could just add a field we don't use right now in the prctl interface: prctl(PR_SET_SECCOMP_FILTER, int event_type, int event_or_syscall_nr, char *filter) [or something similar] Then we can add process-local/scoped supported event types somewhere down the road without an ABI change. Tying it all together, it'd look like: * Now -- add process-scoped security support: secocmp filter with support for "future" event types * Soon -- expand ftrace syscall hooks to hook more system calls * Later -- expand ftrace filter language to support either deep argument analysis and/or custom registered predicates * Later, later -- implement a LSM-like hooking layer for "interesting" event types on top of the ftrace hooks That would yield process-scoped security controls and global security controls and the ability to continue to create new and interesting security modules. All that said, I'm in over my head. I've focused primarily on the process-scoped security. I think James, some of the LSM authors, and out-of-tree security system maintainers would be good to help guide direction toward the security view you have in mind to ensure the flexibility desired exists. And that's even assuming this sketch is even vaguely interesting... [snip] > What i do here is to suggest *further* steps down the same road, now that we > see that this scheme can indeed be used to implement sandboxing ... I think > it's a valid line of inquiry. I certainly agree that it's a valid line of inquiry, but I worry about the massive scope expansion. I know it hurts my head, but I'm hoping the brain-dump above frames up how I think about this patch and your line of inquiry. ftrace hooking and the perf code certainly look a lot like LSMs if I squint hard :) But there is a substantial amount of work to merge the worlds, and (thankfully) I don't think that future directly impacts process-scoped security mechanisms even if they can interact nicely. thanks! will From David.Daney@caviumnetworks.com Thu May 12 19:09:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 19:09:45 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14594 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491187Ab1ELRJk (ORCPT ); Thu, 12 May 2011 19:09:40 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 12 May 2011 10:10:38 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 12 May 2011 10:09:36 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 12 May 2011 10:09:36 -0700 Message-ID: <4DCC1450.6060006@caviumnetworks.com> Date: Thu, 12 May 2011 10:09:36 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] MIPS: lantiq: Add missing include to mach-easy50712.c References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> <1305145347-32605-2-git-send-email-ddaney@caviumnetworks.com> <20110511212538.GB17315@linux-mips.org> <4DCB76E5.3070703@openwrt.org> In-Reply-To: <4DCB76E5.3070703@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 12 May 2011 17:09:36.0613 (UTC) FILETIME=[5F0D1150:01CC10C7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29965 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 05/11/2011 10:57 PM, John Crispin wrote: > On 11/05/11 23:25, Ralf Baechle wrote: >> Thanks, folded into "MIPS: Lantiq: Add etop board support". >> >> Ralf >> >> > > Hi, > > the include should be in arch/lantiq/devices.h and not the mach-*.c file. > It is best to keep the include pushed as far to the leaves of the build as possible. That makes compiling other files that need devices.h faster. > this got lost int he folding and i thought we fixed it yesterday already . In any event I think Ralf has it sorted out now. linux-queue is now building for me with no patches. David Daney From blogic@openwrt.org Thu May 12 19:13:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 19:13:43 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:59231 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491191Ab1ELRNj (ORCPT ); Thu, 12 May 2011 19:13:39 +0200 Message-ID: <4DCC15A1.2020103@openwrt.org> Date: Thu, 12 May 2011 19:15:13 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: David Daney CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] MIPS: lantiq: Add missing include to mach-easy50712.c References: <1305145347-32605-1-git-send-email-ddaney@caviumnetworks.com> <1305145347-32605-2-git-send-email-ddaney@caviumnetworks.com> <20110511212538.GB17315@linux-mips.org> <4DCB76E5.3070703@openwrt.org> <4DCC1450.6060006@caviumnetworks.com> In-Reply-To: <4DCC1450.6060006@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29966 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips > It is best to keep the include pushed as far to the leaves of the > build as possible. That makes compiling other files that need > devices.h faster. > >> this got lost int he folding and i thought we fixed it yesterday >> already . > > In any event I think Ralf has it sorted out now. linux-queue is now > building for me with no patches. yes its solved, current queue builds and runs as expected on lantiq socs From ralf@linux-mips.org Thu May 12 23:55:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 23:55:35 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:43230 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491201Ab1ELVzc (ORCPT ); Thu, 12 May 2011 23:55:32 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CLugt6026505; Thu, 12 May 2011 22:56:42 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CLueij026503; Thu, 12 May 2011 22:56:40 +0100 Date: Thu, 12 May 2011 22:56:40 +0100 From: Ralf Baechle To: wanlong.gao@gmail.com Cc: david.woodhouse@intel.com, akpm@linux-foundation.org, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS:fix the build warning Message-ID: <20110512215640.GA21865@linux-mips.org> References: <1302370937-832-1-git-send-email-wanlong.gao@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1302370937-832-1-git-send-email-wanlong.gao@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29967 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Thu May 12 23:57:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 May 2011 23:57:31 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:43272 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491201Ab1ELV52 (ORCPT ); Thu, 12 May 2011 23:57:28 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CLvphi026543; Thu, 12 May 2011 22:57:51 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CLvkur026542; Thu, 12 May 2011 22:57:46 +0100 Date: Thu, 12 May 2011 22:57:46 +0100 From: Ralf Baechle To: wanlong.gao@gmail.com Cc: linux@arm.linux.org.uk, hans-christian.egtvedt@atmel.com, benh@kernel.crashing.org, paulus@samba.org, david.woodhouse@intel.com, akpm@linux-foundation.org, u.kleine-koenig@pengutronix.de, mingo@elte.hu, rientjes@google.com, nicolas.ferre@atmel.com, eric@eukrea.com, tony@atomide.com, santosh.shilimkar@ti.com, khilman@deeprootsystems.com, ben-linux@fluff.org, sam@ravnborg.org, manuel.lauss@googlemail.com, galak@kernel.crashing.org, anton@samba.org, grant.likely@secretlab.ca, sfr@canb.auug.org.au, jwboyer@linux.vnet.ibm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] fix build warnings on defconfigs Message-ID: <20110512215746.GB21865@linux-mips.org> References: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29968 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Apr 10, 2011 at 03:04:18AM +0800, wanlong.gao@gmail.com wrote: > Subject: [PATCH] fix build warnings on defconfigs > > From: Wanlong Gao > > Change the BT_L2CAP and BT_SCO defconfigs from 'm' to 'y', > since BT_L2CAP and BT_SCO had changed to bool configs. > > Signed-off-by: Wanlong Gao I've queued the MIPS bits only for 2.6.40. Thanks. Ralf From ralf@linux-mips.org Fri May 13 00:15:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 00:15:40 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47494 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491207Ab1ELWPa (ORCPT ); Fri, 13 May 2011 00:15:30 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CMGxYB000462; Thu, 12 May 2011 23:16:59 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CMGxY0000459; Thu, 12 May 2011 23:16:59 +0100 Date: Thu, 12 May 2011 23:16:59 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, Chandrakala Chavva Subject: Re: [PATCH] MIPS: Octeon: Fix interrupt irq settings for performance counters. Message-ID: <20110512221659.GC21865@linux-mips.org> References: <1297979872-25738-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1297979872-25738-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29969 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.40. Ralf From ralf@linux-mips.org Fri May 13 00:23:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 00:23:51 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48881 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491201Ab1ELWXc (ORCPT ); Fri, 13 May 2011 00:23:32 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4CMOv8T002844; Thu, 12 May 2011 23:24:57 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4CMOvxH002842; Thu, 12 May 2011 23:24:57 +0100 Date: Thu, 12 May 2011 23:24:57 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: Don't request interrupts for unused IPI mailbox bits. Message-ID: <20110512222457.GD21865@linux-mips.org> References: <1297982872-5124-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1297982872-5124-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29970 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.40. Thanks David! Ralf From jmorris@namei.org Fri May 13 02:20:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 02:20:31 +0200 (CEST) Received: from tundra.namei.org ([65.99.196.166]:46849 "EHLO tundra.namei.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491766Ab1EMAU0 (ORCPT ); Fri, 13 May 2011 02:20:26 +0200 Received: from localhost (localhost [127.0.0.1]) by tundra.namei.org (8.13.1/8.13.1) with ESMTP id p4D0IqQM003478; Thu, 12 May 2011 20:18:52 -0400 Date: Fri, 13 May 2011 10:18:52 +1000 (EST) From: James Morris To: Ingo Molnar cc: Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering In-Reply-To: <20110512130104.GA2912@elte.hu> Message-ID: References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> <20110512130104.GA2912@elte.hu> User-Agent: Alpine 2.00 (LRH 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29971 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jmorris@namei.org Precedence: bulk X-list: linux-mips On Thu, 12 May 2011, Ingo Molnar wrote: > Funnily enough, back then you wrote this: > > " I'm concerned that we're seeing yet another security scheme being designed on > the fly, without a well-formed threat model, and without taking into account > lessons learned from the seemingly endless parade of similar, failed schemes. " > > so when and how did your opinion of this scheme turn from it being an "endless > parade of failed schemes" to it being a "well-defined and readily > understandable feature"? :-) When it was defined in a way which limited its purpose to reducing the attack surface of the sycall interface. - James -- James Morris From David.Daney@caviumnetworks.com Fri May 13 02:25:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 02:25:22 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10289 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491766Ab1EMAZR (ORCPT ); Fri, 13 May 2011 02:25:17 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 12 May 2011 17:26:15 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 12 May 2011 17:25:12 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 12 May 2011 17:25:12 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p4D0P7Tr007550; Thu, 12 May 2011 17:25:07 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p4D0P5xv007549; Thu, 12 May 2011 17:25:05 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Fix build breakage in cpu-probe.c Date: Thu, 12 May 2011 17:24:59 -0700 Message-Id: <1305246299-7517-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 13 May 2011 00:25:12.0631 (UTC) FILETIME=[3954EC70:01CC1104] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29972 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Move set_elf_platform() above all its uses. Signed-off-by: David Daney --- linux-queue is currently broken, this fixes it. arch/mips/kernel/cpu-probe.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 054a640..bb133d1 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -291,6 +291,12 @@ static inline int cpu_has_confreg(void) #endif } +static inline void set_elf_platform(int cpu, const char *plat) +{ + if (cpu == 0) + __elf_platform = plat; +} + /* * Get the FPU Implementation/Revision. */ @@ -781,12 +787,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) c->core = read_c0_ebase() & 0x3ff; } -static inline void set_elf_platform(int cpu, const char *plat) -{ - if (cpu == 0) - __elf_platform = plat; -} - static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); -- 1.7.2.3 From cernekee@gmail.com Fri May 13 03:26:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 03:26:25 +0200 (CEST) Received: from mail-px0-f182.google.com ([209.85.212.182]:49098 "EHLO mail-px0-f182.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491791Ab1EMB0T (ORCPT ); Fri, 13 May 2011 03:26:19 +0200 Received: by pxi20 with SMTP id 20so1470331pxi.27 for ; Thu, 12 May 2011 18:26:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=AqmK0JSCkIL2FwBTBJG+4iLx/AEUZpBx08IMWKRxFp0=; b=x2SeNnzCn5danH2/Mc/65LKa7J889cg/ZJk00yopTMEsnSGhizIdEKGCuhHj7N4E5a J+pC5JR0vlohZ53QMhV188D4TcBE/ghfp8jQa/j2LvP2pd0OtaWmiU8ARVH262PeSlLp 9+Ix7byA+24wipB69M3YmJ6V4wqtpngjltaBg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=CD31UjFphGgc8McfTkels91XS9WH+e0aZxc0Kp+t4Eb1M6w29wc+xHeWgbkmrX/eUG QksEWT0MVLDYbAHrrdD8vSAUMjoplV5fe+hhhrpKTaWz66hKg24O6ov3afKlctJ1pk+f S/yi1tXjNpPMnkSywtx9BZoUm83YIoVPUC554= MIME-Version: 1.0 Received: by 10.68.57.168 with SMTP id j8mr1301225pbq.111.1305249969334; Thu, 12 May 2011 18:26:09 -0700 (PDT) Received: by 10.68.51.72 with HTTP; Thu, 12 May 2011 18:26:09 -0700 (PDT) In-Reply-To: <1305246299-7517-1-git-send-email-ddaney@caviumnetworks.com> References: <1305246299-7517-1-git-send-email-ddaney@caviumnetworks.com> Date: Thu, 12 May 2011 18:26:09 -0700 Message-ID: Subject: Re: [PATCH] MIPS: Fix build breakage in cpu-probe.c From: Kevin Cernekee To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29973 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips On Thu, May 12, 2011 at 5:24 PM, David Daney wrote: > Move set_elf_platform() above all its uses. Whoops, should have retested the Loongson patch v1 with the set_elf_platform patch v2. Thanks for fixing this. Acked-by: Kevin Cernekee BTW: the commit messages got a little messed up on the two patches that had a secondary "From:" header to override the author field. Is there something I should be doing differently here? From ralf@linux-mips.org Fri May 13 11:12:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 11:12:33 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:39451 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491800Ab1EMJMa (ORCPT ); Fri, 13 May 2011 11:12:30 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4D9BvIW024060; Fri, 13 May 2011 10:11:57 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4D9Buda024058; Fri, 13 May 2011 10:11:56 +0100 Date: Fri, 13 May 2011 10:11:56 +0100 From: Ralf Baechle To: Kevin Cernekee Cc: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Fix build breakage in cpu-probe.c Message-ID: <20110513091156.GA18174@linux-mips.org> References: <1305246299-7517-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29974 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, May 12, 2011 at 06:26:09PM -0700, Kevin Cernekee wrote: > BTW: the commit messages got a little messed up on the two patches > that had a secondary "From:" header to override the author field. Is > there something I should be doing differently here? You did exactly the right thing. I messed up when manually converting the patch files into the pseudo quilt format I'm using for linux-queue. Ralf From ralf@linux-mips.org Fri May 13 11:13:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 11:13:11 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:39454 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491800Ab1EMJNI (ORCPT ); Fri, 13 May 2011 11:13:08 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4D9Cecu024073; Fri, 13 May 2011 10:12:40 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4D9CetF024072; Fri, 13 May 2011 10:12:40 +0100 Date: Fri, 13 May 2011 10:12:40 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Fix build breakage in cpu-probe.c Message-ID: <20110513091240.GB18174@linux-mips.org> References: <1305246299-7517-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305246299-7517-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29975 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Folded into the original patch. Thanks! Ralf From ralf@linux-mips.org Fri May 13 12:15:52 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 12:15:55 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44553 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491808Ab1EMKPw (ORCPT ); Fri, 13 May 2011 12:15:52 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p4DAHHoY025506; Fri, 13 May 2011 11:17:17 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p4DAHGaJ025504; Fri, 13 May 2011 11:17:16 +0100 Date: Fri, 13 May 2011 11:17:16 +0100 From: Ralf Baechle To: David Daney Cc: Kevin Cernekee , Wu Zhangjin , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: Squash pci_fixup_irqs() compiler warning Message-ID: <20110513101716.GB25345@linux-mips.org> References: <4DAC7499.5000602@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4DAC7499.5000602@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29976 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 18, 2011 at 10:27:53AM -0700, David Daney wrote: > >It's been two years since the original discussion, and the warning is > >still there. It is now the only warning left in my kernel build. > > > >I was hoping we could get this resolved for good (one way or another). [...] > NAK. > > I think Ralf's idea in the e-mail you referenced is the proper approach. > > Change pci_fixup_irqs(...) to take a 'const struct pci_dev *' > instead. There is a lot of work going on in the kernel to constify > things. This should be fairly easy to get accepted. It's a fairly big manual job but should be just right for spatch. Ralf From mingo@elte.hu Fri May 13 14:11:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:11:26 +0200 (CEST) Received: from mx2.mail.elte.hu ([157.181.151.9]:45693 "EHLO mx2.mail.elte.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491814Ab1EMMLU (ORCPT ); Fri, 13 May 2011 14:11:20 +0200 Received: from elvis.elte.hu ([157.181.1.14]) by mx2.mail.elte.hu with esmtp (Exim) id 1QKrCg-00045T-OE from ; Fri, 13 May 2011 14:10:55 +0200 Received: by elvis.elte.hu (Postfix, from userid 1004) id 81FD43E233D; Fri, 13 May 2011 14:10:35 +0200 (CEST) Date: Fri, 13 May 2011 14:10:34 +0200 From: Ingo Molnar To: James Morris Cc: Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, Peter Zijlstra , "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Message-ID: <20110513121034.GG21022@elte.hu> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> <20110512130104.GA2912@elte.hu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Received-SPF: neutral (mx2.mail.elte.hu: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-SpamScore: -2.0 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=-2.0 required=5.9 tests=BAYES_00 autolearn=no SpamAssassin version=3.3.1 -2.0 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29977 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips * James Morris wrote: > On Thu, 12 May 2011, Ingo Molnar wrote: > > Funnily enough, back then you wrote this: > > > > " I'm concerned that we're seeing yet another security scheme being designed on > > the fly, without a well-formed threat model, and without taking into account > > lessons learned from the seemingly endless parade of similar, failed schemes. " > > > > so when and how did your opinion of this scheme turn from it being an > > "endless parade of failed schemes" to it being a "well-defined and readily > > understandable feature"? :-) > > When it was defined in a way which limited its purpose to reducing the attack > surface of the sycall interface. Let me outline a simple example of a new filter expression based security feature that could be implemented outside the narrow system call boundary you find acceptable, and please tell what is bad about it. Say i'm a user-space sandbox developer who wants to enforce that sandboxed code should only be allowed to open files in /home/sandbox/, /lib/ and /usr/lib/. It is a simple and sensible security feature, agreed? It allows most code to run well and link to countless libraries - but no access to other files is allowed. I would also like my sandbox app to be able to install this policy without having to be root. I do not want the sandbox app to have permission to create labels on /lib and /usr/lib and what not. Firstly, using the filter code i deny the various link creation syscalls so that sandboxed code cannot escape for example by creating a symlink to outside the permitted VFS namespace. (Note: we opt-in to syscalls, that way new syscalls added by new kernels are denied by defalt. The current symlink creation syscalls are not opted in to.) But the next step, actually checking filenames, poses a big hurdle: i cannot implement the filename checking at the sys_open() syscall level in a secure way: because the pathname is passed to sys_open() by pointer, and if i check it at the generic sys_open() syscall level, another thread in the sandbox might modify the underlying filename *after* i've checked it. But if i had a VFS event at the fs/namei.c::getname() level, i would have access to a central point where the VFS string becomes stable to the kernel and can be checked (and denied if necessary). A sidenote, and not surprisingly, the audit subsystem already has an event callback there: audit_getname(result); Unfortunately this audit callback cannot be used for my purposes, because the event is single-purpose for auditd and because it allows no feedback (no deny/accept discretion for the security policy). But if had this simple event there: err = event_vfs_getname(result); I could implement this new filename based sandboxing policy, using a filter like this installed on the vfs::getname event and inherited by all sandboxed tasks (which cannot uninstall the filter, obviously): " if (strstr(name, "..")) return -EACCESS; if (!strncmp(name, "/home/sandbox/", 14) && !strncmp(name, "/lib/", 5) && !strncmp(name, "/usr/lib/", 9)) return -EACCESS; " # # Note1: Obviously the filter engine would be extended to allow such simple string # match functions. ) # # Note2: ".." is disallowed so that sandboxed code cannot escape the restrictions # using "/..". # This kind of flexible and dynamic sandboxing would allow a wide range of file ops within the sandbox, while still isolating it from files not included in the specified VFS namespace. ( Note that there are tons of other examples as well, for useful security features that are best done using events outside the syscall boundary. ) The security event filters code tied to seccomp and syscalls at the moment is useful, but limited in its future potential. So i argue that it should go slightly further and should become: - unprivileged: application-definable, allowing the embedding of security policy in *apps* as well, not just the system - flexible: can be added/removed runtime unprivileged, and cheaply so - transparent: does not impact executing code that meets the policy - nestable: it is inherited by child tasks and is fundamentally stackable, multiple policies will have the combined effect and they are transparent to each other. So if a child task within a sandbox adds *more* checks then those add to the already existing set of checks. We only narrow permissions, never extend them. - generic: allowing observation and (safe) control of security relevant parameters not just at the system call boundary but at other relevant places of kernel execution as well: which points/callbacks could also be used for other types of event extraction such as perf. It could even be shared with audit ... I argue that this is the LSM and audit subsystems designed right: in the long run it could allow everything that LSM does at the moment - and so much more ... And you argue that allowing this would be bad, if it was extended like that then you'd consider it a failed scheme? Why? Thanks, Ingo From peterz@infradead.org Fri May 13 14:19:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:19:51 +0200 (CEST) Received: from bombadil.infradead.org ([18.85.46.34]:50339 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab1EMMTl convert rfc822-to-8bit (ORCPT ); Fri, 13 May 2011 14:19:41 +0200 Received: from canuck.infradead.org ([134.117.69.58]) by bombadil.infradead.org with esmtps (Exim 4.72 #1 (Red Hat Linux)) id 1QKrKp-0008FR-9T; Fri, 13 May 2011 12:19:11 +0000 Received: from j77219.upc-j.chello.nl ([24.132.77.219] helo=twins) by canuck.infradead.org with esmtpsa (Exim 4.72 #1 (Red Hat Linux)) id 1QKrKn-0002FT-VS; Fri, 13 May 2011 12:19:10 +0000 Received: by twins (Postfix, from userid 1000) id CA096812E052; Fri, 13 May 2011 14:19:06 +0200 (CEST) Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering From: Peter Zijlstra To: Ingo Molnar Cc: James Morris , Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds In-Reply-To: <20110513121034.GG21022@elte.hu> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> <20110512130104.GA2912@elte.hu> <20110513121034.GG21022@elte.hu> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Date: Fri, 13 May 2011 14:19:06 +0200 Message-ID: <1305289146.2466.8.camel@twins> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29978 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: peterz@infradead.org Precedence: bulk X-list: linux-mips On Fri, 2011-05-13 at 14:10 +0200, Ingo Molnar wrote: > err = event_vfs_getname(result); I really think we should not do this. Events like we have them should be inactive, totally passive entities, only observe but not affect execution (other than the bare minimal time delay introduced by observance). If you want another entity that is more active, please invent a new name for it and create a new subsystem for them, now you could have these active entities also have an (automatic) passive event side, but that's some detail. From mingo@elte.hu Fri May 13 14:27:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:27:30 +0200 (CEST) Received: from mx2.mail.elte.hu ([157.181.151.9]:48286 "EHLO mx2.mail.elte.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab1EMM1X (ORCPT ); Fri, 13 May 2011 14:27:23 +0200 Received: from elvis.elte.hu ([157.181.1.14]) by mx2.mail.elte.hu with esmtp (Exim) id 1QKrSE-0000JC-S0 from ; Fri, 13 May 2011 14:26:57 +0200 Received: by elvis.elte.hu (Postfix, from userid 1004) id A22853E233D; Fri, 13 May 2011 14:26:43 +0200 (CEST) Date: Fri, 13 May 2011 14:26:46 +0200 From: Ingo Molnar To: Peter Zijlstra Cc: James Morris , Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Message-ID: <20110513122646.GA3924@elte.hu> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> <20110512130104.GA2912@elte.hu> <20110513121034.GG21022@elte.hu> <1305289146.2466.8.camel@twins> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1305289146.2466.8.camel@twins> User-Agent: Mutt/1.5.20 (2009-08-17) Received-SPF: neutral (mx2.mail.elte.hu: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-SpamScore: -2.0 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=-2.0 required=5.9 tests=BAYES_00 autolearn=no SpamAssassin version=3.3.1 -2.0 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29979 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips * Peter Zijlstra wrote: > On Fri, 2011-05-13 at 14:10 +0200, Ingo Molnar wrote: > > err = event_vfs_getname(result); > > I really think we should not do this. Events like we have them should be > inactive, totally passive entities, only observe but not affect execution > (other than the bare minimal time delay introduced by observance). Well, this patchset already demonstrates that we can use a single event callback for a rather useful purpose. Either it makes sense to do, in which case we should share facilities as much as possible, or it makes no sense, in which case we should not merge it at all. > If you want another entity that is more active, please invent a new name for > it and create a new subsystem for them, now you could have these active > entities also have an (automatic) passive event side, but that's some detail. Why should we have two callbacks next to each other: event_vfs_getname(result); result = check_event_vfs_getname(result); if one could do it all? Thanks, Ingo From gergely@homejinni.com Fri May 13 14:39:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:39:44 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:49448 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab1EMMjl (ORCPT ); Fri, 13 May 2011 14:39:41 +0200 Received: by fxm14 with SMTP id 14so2302504fxm.36 for ; Fri, 13 May 2011 05:39:35 -0700 (PDT) Received: by 10.223.85.155 with SMTP id o27mr1619874fal.109.1305290375340; Fri, 13 May 2011 05:39:35 -0700 (PDT) Received: from localhost.localdomain (540371FD.catv.pool.telekom.hu [84.3.113.253]) by mx.google.com with ESMTPS id 18sm568268fan.25.2011.05.13.05.39.33 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 13 May 2011 05:39:34 -0700 (PDT) From: Gergely Kis To: linux-mips@linux-mips.org Cc: oprofile-list@lists.sourceforge.net, Daniel Kalmar Subject: [PATCH 0/2] MIPS: oprofile: callgraph support Date: Fri, 13 May 2011 12:38:03 +0000 Message-Id: <1305290285-13818-1-git-send-email-gergely@homejinni.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29980 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gergely@homejinni.com Precedence: bulk X-list: linux-mips From: Daniel Kalmar These patches add callgraph/backtrace support to oprofile on MIPS. Stack unwinding is done by code examination. For kernelspace, the already existing unwind function is utilized that uses kallsyms to quickly find the beginning of functions. For userspace a new function was added that examines code at and before the pc. Daniel Kalmar (2): MIPS: Add unwind_stack_by_address to support unwinding from any kernel code address MIPS: oprofile: Add callgraph support arch/mips/include/asm/stacktrace.h | 4 + arch/mips/kernel/process.c | 18 +++- arch/mips/oprofile/Makefile | 2 +- arch/mips/oprofile/backtrace.c | 173 ++++++++++++++++++++++++++++++++++++ arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_impl.h | 2 + 6 files changed, 194 insertions(+), 6 deletions(-) create mode 100644 arch/mips/oprofile/backtrace.c From gergely@homejinni.com Fri May 13 14:40:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:40:06 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:49448 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491818Ab1EMMjt (ORCPT ); Fri, 13 May 2011 14:39:49 +0200 Received: by mail-fx0-f49.google.com with SMTP id 14so2302504fxm.36 for ; Fri, 13 May 2011 05:39:49 -0700 (PDT) Received: by 10.223.94.129 with SMTP id z1mr1680501fam.144.1305290388946; Fri, 13 May 2011 05:39:48 -0700 (PDT) Received: from localhost.localdomain (540371FD.catv.pool.telekom.hu [84.3.113.253]) by mx.google.com with ESMTPS id 18sm568268fan.25.2011.05.13.05.39.47 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 13 May 2011 05:39:47 -0700 (PDT) From: Gergely Kis To: linux-mips@linux-mips.org Cc: oprofile-list@lists.sourceforge.net, Daniel Kalmar , Gergely Kis Subject: [PATCH 1/2] MIPS: Add new unwind_stack variant Date: Fri, 13 May 2011 12:38:04 +0000 Message-Id: <1305290285-13818-2-git-send-email-gergely@homejinni.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1305290285-13818-1-git-send-email-gergely@homejinni.com> References: <1305290285-13818-1-git-send-email-gergely@homejinni.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29981 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gergely@homejinni.com Precedence: bulk X-list: linux-mips From: Daniel Kalmar The unwind_stack_by_address variant supports unwinding based on any kernel code address. This symbol is also exported so it can be called from modules. Signed-off-by: Daniel Kalmar Signed-off-by: Gergely Kis --- arch/mips/include/asm/stacktrace.h | 4 ++++ arch/mips/kernel/process.c | 18 +++++++++++++----- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/stacktrace.h b/arch/mips/include/asm/stacktrace.h index 0bf8281..780ee2c 100644 --- a/arch/mips/include/asm/stacktrace.h +++ b/arch/mips/include/asm/stacktrace.h @@ -7,6 +7,10 @@ extern int raw_show_trace; extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, unsigned long pc, unsigned long *ra); +extern unsigned long unwind_stack_by_address(unsigned long stack_page, + unsigned long *sp, + unsigned long pc, + unsigned long *ra); #else #define raw_show_trace 1 static inline unsigned long unwind_stack(struct task_struct *task, diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index d2112d3..0acb274 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -373,18 +373,18 @@ unsigned long thread_saved_pc(struct task_struct *tsk) #ifdef CONFIG_KALLSYMS -/* used by show_backtrace() */ -unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, - unsigned long pc, unsigned long *ra) +/* generic stack unwinding function */ +unsigned long notrace unwind_stack_by_address(unsigned long stack_page, + unsigned long *sp, + unsigned long pc, + unsigned long *ra) { - unsigned long stack_page; struct mips_frame_info info; unsigned long size, ofs; int leaf; extern void ret_from_irq(void); extern void ret_from_exception(void); - stack_page = (unsigned long)task_stack_page(task); if (!stack_page) return 0; @@ -443,6 +443,14 @@ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, *ra = 0; return __kernel_text_address(pc) ? pc : 0; } +EXPORT_SYMBOL(unwind_stack_by_address); + +/* used by show_backtrace() */ +unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, + unsigned long pc, unsigned long *ra) { + unsigned long stack_page = (unsigned long)task_stack_page(task); + return unwind_stack_by_address(stack_page, sp, pc, ra); +} #endif /* -- 1.7.0.4 From gergely@homejinni.com Fri May 13 14:40:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:40:33 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:49448 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491822Ab1EMMjz (ORCPT ); Fri, 13 May 2011 14:39:55 +0200 Received: by mail-fx0-f49.google.com with SMTP id 14so2302504fxm.36 for ; Fri, 13 May 2011 05:39:55 -0700 (PDT) Received: by 10.223.145.13 with SMTP id b13mr1684082fav.65.1305290394706; Fri, 13 May 2011 05:39:54 -0700 (PDT) Received: from localhost.localdomain (540371FD.catv.pool.telekom.hu [84.3.113.253]) by mx.google.com with ESMTPS id 18sm568268fan.25.2011.05.13.05.39.53 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 13 May 2011 05:39:53 -0700 (PDT) From: Gergely Kis To: linux-mips@linux-mips.org Cc: oprofile-list@lists.sourceforge.net, Daniel Kalmar , Gergely Kis Subject: [PATCH 2/2] MIPS: oprofile: Add callgraph support Date: Fri, 13 May 2011 12:38:05 +0000 Message-Id: <1305290285-13818-3-git-send-email-gergely@homejinni.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1305290285-13818-1-git-send-email-gergely@homejinni.com> References: <1305290285-13818-1-git-send-email-gergely@homejinni.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29982 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gergely@homejinni.com Precedence: bulk X-list: linux-mips From: Daniel Kalmar Stack unwinding is done by code examination. For kernelspace, the already existing unwind function is utilized that uses kallsyms to quickly find the beginning of functions. For userspace a new function was added that examines code at and before the pc. Signed-off-by: Daniel Kalmar Signed-off-by: Gergely Kis --- arch/mips/oprofile/Makefile | 2 +- arch/mips/oprofile/backtrace.c | 173 ++++++++++++++++++++++++++++++++++++++++ arch/mips/oprofile/common.c | 1 + arch/mips/oprofile/op_impl.h | 2 + 4 files changed, 177 insertions(+), 1 deletions(-) create mode 100644 arch/mips/oprofile/backtrace.c diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 4b9d704..29f2f13 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -8,7 +8,7 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \ oprofilefs.o oprofile_stats.o \ timer_int.o ) -oprofile-y := $(DRIVER_OBJS) common.o +oprofile-y := $(DRIVER_OBJS) common.o backtrace.o oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o diff --git a/arch/mips/oprofile/backtrace.c b/arch/mips/oprofile/backtrace.c new file mode 100644 index 0000000..d508e9e --- /dev/null +++ b/arch/mips/oprofile/backtrace.c @@ -0,0 +1,173 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct stackframe { + unsigned long sp; + unsigned long pc; + unsigned long ra; +}; + +static inline int get_mem(unsigned long addr, unsigned long *result) +{ + unsigned long *address = (unsigned long *) addr; + if (!access_ok(VERIFY_READ, addr, sizeof(unsigned long))) + return -1; + if (__copy_from_user_inatomic(result, address, sizeof(unsigned long))) + return -3; + return 0; +} + +/* + * These two instruction helpers were taken from process.c + */ +static inline int is_ra_save_ins(union mips_instruction *ip) +{ + /* sw / sd $ra, offset($sp) */ + return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) + && ip->i_format.rs == 29 && ip->i_format.rt == 31; +} + +static inline int is_sp_move_ins(union mips_instruction *ip) +{ + /* addiu/daddiu sp,sp,-imm */ + if (ip->i_format.rs != 29 || ip->i_format.rt != 29) + return 0; + if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) + return 1; + return 0; +} + +/* + * Looks for specific instructions that mark the end of a function. + * This usually means we ran into the code area of the previous function. + */ +static inline int is_end_of_function_marker(union mips_instruction *ip) +{ + /* jr ra */ + if (ip->r_format.func == jr_op && ip->r_format.rs == 31) + return 1; + /* lui gp */ + if (ip->i_format.opcode == lui_op && ip->i_format.rt == 28) + return 1; + return 0; +} + +/* + * TODO for userspace stack unwinding: + * - handle cases where the stack is adjusted inside a function + * (generally doesn't happen) + * - find optimal value for max_instr_check + * - try to find a way to handle leaf functions + */ + +static inline int unwind_user_frame(struct stackframe *old_frame, + const unsigned int max_instr_check) +{ + struct stackframe new_frame = *old_frame; + off_t ra_offset = 0; + size_t stack_size = 0; + unsigned long addr; + + if (old_frame->pc == 0 || old_frame->sp == 0 || old_frame->ra == 0) + return -9; + + for (addr = new_frame.pc; (addr + max_instr_check > new_frame.pc) + && (!ra_offset || !stack_size); --addr) { + union mips_instruction ip; + + if (get_mem(addr, (unsigned long *) &ip)) + return -11; + + if (is_sp_move_ins(&ip)) { + int stack_adjustment = ip.i_format.simmediate; + if (stack_adjustment > 0) + /* This marks the end of the previous function, + which means we overran. */ + break; + stack_size = (unsigned) stack_adjustment; + } else if (is_ra_save_ins(&ip)) { + int ra_slot = ip.i_format.simmediate; + if (ra_slot < 0) + /* This shouldn't happen. */ + break; + ra_offset = ra_slot; + } else if (is_end_of_function_marker(&ip)) + break; + } + + if (!ra_offset || !stack_size) + return -1; + + if (ra_offset) { + new_frame.ra = old_frame->sp + ra_offset; + if (get_mem(new_frame.ra, &(new_frame.ra))) + return -13; + } + + if (stack_size) { + new_frame.sp = old_frame->sp + stack_size; + if (get_mem(new_frame.sp, &(new_frame.sp))) + return -14; + } + + if (new_frame.sp > old_frame->sp) + return -2; + + new_frame.pc = old_frame->ra; + *old_frame = new_frame; + + return 0; +} + +static inline void do_user_backtrace(unsigned long low_addr, + struct stackframe *frame, + unsigned int depth) { + const unsigned int max_instr_check = 512; + const unsigned long high_addr = low_addr + THREAD_SIZE; + + while (depth-- && !unwind_user_frame(frame, max_instr_check)) { + oprofile_add_trace(frame->ra); + if (frame->sp < low_addr || frame->sp > high_addr) + break; + } +} + +#ifndef CONFIG_KALLSYMS +static inline void do_kernel_backtrace(unsigned long low_addr, + struct stackframe *frame, + unsigned int depth) { } +#else +static inline void do_kernel_backtrace(unsigned long low_addr, + struct stackframe *frame, + unsigned int depth) { + while (depth-- && frame->pc) { + frame->pc = unwind_stack_by_address(low_addr, + &(frame->sp), + frame->pc, + &(frame->ra)); + oprofile_add_trace(frame->ra); + } +} +#endif + +void notrace op_mips_backtrace(struct pt_regs *const regs, unsigned int depth) +{ + struct stackframe frame = { .sp = regs->regs[29], + .pc = regs->cp0_epc, + .ra = regs->regs[31] }; + const int userspace = user_mode(regs); + const unsigned long low_addr = ALIGN(frame.sp, THREAD_SIZE); + + if (userspace) + do_user_backtrace(low_addr, &frame, depth); + else + do_kernel_backtrace(low_addr, &frame, depth); +} diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index f9eb1ab..d1f2d4c 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -115,6 +115,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) ops->start = op_mips_start; ops->stop = op_mips_stop; ops->cpu_type = lmodel->cpu_type; + ops->backtrace = op_mips_backtrace; printk(KERN_INFO "oprofile: using %s performance monitoring.\n", lmodel->cpu_type); diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h index f04b54f..7c2da27 100644 --- a/arch/mips/oprofile/op_impl.h +++ b/arch/mips/oprofile/op_impl.h @@ -36,4 +36,6 @@ struct op_mips_model { unsigned char num_counters; }; +void op_mips_backtrace(struct pt_regs * const regs, unsigned int depth); + #endif -- 1.7.0.4 From peterz@infradead.org Fri May 13 14:40:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:40:56 +0200 (CEST) Received: from bombadil.infradead.org ([18.85.46.34]:45163 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491821Ab1EMMj6 convert rfc822-to-8bit (ORCPT ); Fri, 13 May 2011 14:39:58 +0200 Received: from canuck.infradead.org ([134.117.69.58]) by bombadil.infradead.org with esmtps (Exim 4.72 #1 (Red Hat Linux)) id 1QKreX-00062e-8B; Fri, 13 May 2011 12:39:33 +0000 Received: from j77219.upc-j.chello.nl ([24.132.77.219] helo=twins) by canuck.infradead.org with esmtpsa (Exim 4.72 #1 (Red Hat Linux)) id 1QKreW-0002OA-50; Fri, 13 May 2011 12:39:32 +0000 Received: by twins (Postfix, from userid 1000) id 4719A812FE74; Fri, 13 May 2011 14:39:30 +0200 (CEST) Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering From: Peter Zijlstra To: Ingo Molnar Cc: James Morris , Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds In-Reply-To: <20110513122646.GA3924@elte.hu> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> <20110512130104.GA2912@elte.hu> <20110513121034.GG21022@elte.hu> <1305289146.2466.8.camel@twins> <20110513122646.GA3924@elte.hu> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Date: Fri, 13 May 2011 14:39:30 +0200 Message-ID: <1305290370.2466.14.camel@twins> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29983 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: peterz@infradead.org Precedence: bulk X-list: linux-mips On Fri, 2011-05-13 at 14:26 +0200, Ingo Molnar wrote: > * Peter Zijlstra wrote: > > > On Fri, 2011-05-13 at 14:10 +0200, Ingo Molnar wrote: > > > err = event_vfs_getname(result); > > > > I really think we should not do this. Events like we have them should be > > inactive, totally passive entities, only observe but not affect execution > > (other than the bare minimal time delay introduced by observance). > > Well, this patchset already demonstrates that we can use a single event > callback for a rather useful purpose. Can and should are two distinct things. > Either it makes sense to do, in which case we should share facilities as much > as possible, or it makes no sense, in which case we should not merge it at all. And I'm arguing we should _not_. Observing is radically different from Affecting, at the very least the two things should have different permission schemes. We should not confuse these two matters. > > If you want another entity that is more active, please invent a new name for > > it and create a new subsystem for them, now you could have these active > > entities also have an (automatic) passive event side, but that's some detail. > > Why should we have two callbacks next to each other: > > event_vfs_getname(result); > result = check_event_vfs_getname(result); > > if one could do it all? Did you actually read the bit where I said that check_event_* (although I still think that name sucks) could imply a matching event_*? From peterz@infradead.org Fri May 13 14:43:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:43:54 +0200 (CEST) Received: from bombadil.infradead.org ([18.85.46.34]:43152 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491822Ab1EMMnv convert rfc822-to-8bit (ORCPT ); Fri, 13 May 2011 14:43:51 +0200 Received: from canuck.infradead.org ([134.117.69.58]) by bombadil.infradead.org with esmtps (Exim 4.72 #1 (Red Hat Linux)) id 1QKriR-0007Q5-Iq; Fri, 13 May 2011 12:43:35 +0000 Received: from j77219.upc-j.chello.nl ([24.132.77.219] helo=twins) by canuck.infradead.org with esmtpsa (Exim 4.72 #1 (Red Hat Linux)) id 1QKriQ-0002Qa-80; Fri, 13 May 2011 12:43:34 +0000 Received: by twins (Postfix, from userid 1000) id 49C64812E04A; Fri, 13 May 2011 14:43:32 +0200 (CEST) Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering From: Peter Zijlstra To: Ingo Molnar Cc: James Morris , Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds In-Reply-To: <1305290370.2466.14.camel@twins> References: <1304017638.18763.205.camel@gandalf.stny.rr.com> <1305169376-2363-1-git-send-email-wad@chromium.org> <20110512074850.GA9937@elte.hu> <20110512130104.GA2912@elte.hu> <20110513121034.GG21022@elte.hu> <1305289146.2466.8.camel@twins> <20110513122646.GA3924@elte.hu> <1305290370.2466.14.camel@twins> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Date: Fri, 13 May 2011 14:43:32 +0200 Message-ID: <1305290612.2466.17.camel@twins> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29984 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: peterz@infradead.org Precedence: bulk X-list: linux-mips On Fri, 2011-05-13 at 14:39 +0200, Peter Zijlstra wrote: > > > event_vfs_getname(result); > > result = check_event_vfs_getname(result); Another fundamental difference is how to treat the callback chains for these two. Observers won't have a return value and are assumed to never fail, therefore we can always call every entry on the callback list. Active things otoh do have a return value, and thus we need to have semantics that define what to do with that during callback iteration, when to continue and when to break. Thus for active elements its impossible to guarantee all entries will indeed be called. From mingo@elte.hu Fri May 13 14:49:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 May 2011 14:49:44 +0200 (CEST) Received: from mx3.mail.elte.hu ([157.181.1.138]:47072 "EHLO mx3.mail.elte.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491818Ab1EMMtj (ORCPT ); Fri, 13 May 2011 14:49:39 +0200 Received: from elvis.elte.hu ([157.181.1.14]) by mx3.mail.elte.hu with esmtp (Exim) id 1QKrns-0002sI-Lt from ; Fri, 13 May 2011 14:49:12 +0200 Received: by elvis.elte.hu (Postfix, from userid 1004) id A98F13E233D; Fri, 13 May 2011 14:48:57 +0200 (CEST) Date: Fri, 13 May 2011 14:49:02 +0200 From: Ingo Molnar To: Peter Zijlstra Cc: James Morris , Will Drewry , linux-kernel@vger.kernel.org, Steven Rostedt , Frederic Weisbecker , Eric Paris , kees.cook@canonical.com, agl@chromium.org, "Serge E. Hallyn" , Ingo Molnar , Andrew Morton , Tejun Heo , Michal Marek , Oleg Nesterov , Roland McGrath , Jiri Slaby , David Howells , Russell King , Michal Simek , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, linux-arm-kernel@lists.infradead.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering Message-ID: