From cernekee@gmail.com Fri Apr 1 02:38:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 02:38:35 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:41302 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab1DAAic (ORCPT ); Fri, 1 Apr 2011 02:38:32 +0200 Received: (qmail 9350 invoked from network); 1 Apr 2011 00:38:28 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 1 Apr 2011 00:38:28 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Thu, 31 Mar 2011 17:38:28 -0700 From: Kevin Cernekee To: Ralf Baechle Cc: Michael Sundius , David VomLehn , Dave Hansen , Andy Whitcroft , Jon Fraser , , , Subject: [PATCH v2] MIPS: Kernel crashes on boot with SPARSEMEM + HIGHMEM enabled Date: Thu, 31 Mar 2011 17:27:07 -0700 Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29663 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips From: Michael Sundius Fix 3 problems in the MIPS SPARSEMEM implementation: 1) mem_init() sets/clears PG_reserved on all pages in the HIGHMEM range without checking to see whether the page descriptor actually exists. 2) bootmem_init() never calls memory_present() on HIGHMEM pages, so page descriptors are never created for them if SPARSEMEM is enabled. 3) bootmem_init() calls memory_present() on lowmem pages before bootmem is fully set up. This is bad because memory_present() can allocate bootmem in some circumstances (e.g. if SPARSEMEM_EXTREME ever got enabled). Signed-off-by: Michael Sundius Signed-off-by: Kevin Cernekee Cc: stable@kernel.org --- arch/mips/kernel/setup.c | 18 +++++++++++++++++- arch/mips/mm/init.c | 3 +++ 2 files changed, 20 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 8ad1d56..1f9f902 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -390,7 +390,6 @@ static void __init bootmem_init(void) /* Register lowmem ranges */ free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT); - memory_present(0, start, end); } /* @@ -402,6 +401,23 @@ static void __init bootmem_init(void) * Reserve initrd memory if needed. */ finalize_initrd(); + + /* + * Call memory_present() on all valid ranges, for SPARSEMEM. + * This must be done after setting up bootmem, since memory_present() + * may allocate bootmem. + */ + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long start, end; + + if (boot_mem_map.map[i].type != BOOT_MEM_RAM) + continue; + + start = PFN_UP(boot_mem_map.map[i].addr); + end = PFN_DOWN(boot_mem_map.map[i].addr + + boot_mem_map.map[i].size); + memory_present(0, start, end); + } } #endif /* CONFIG_SGI_IP27 */ diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 279599e..78a4cf2 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -392,6 +392,9 @@ void __init mem_init(void) for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) { struct page *page = pfn_to_page(tmp); + if (!pfn_valid(tmp)) + continue; + if (!page_is_ram(tmp)) { SetPageReserved(page); continue; -- 1.7.4.2 From jayachandranc@netlogicmicro.com Fri Apr 1 05:06:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 05:06:58 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1461 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490959Ab1DADGx (ORCPT ); Fri, 1 Apr 2011 05:06:53 +0200 X-TM-IMSS-Message-ID: <7511d63500009b47@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 7511d63500009b47 ; Thu, 31 Mar 2011 20:06:42 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 31 Mar 2011 20:07:12 -0700 Date: Fri, 1 Apr 2011 08:36:46 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 1/6] Netlogic XLR/XLS processor IDs. Message-ID: <78353133b475bf81b53f0a512af6693455765363.1301626288.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 01 Apr 2011 03:07:12.0545 (UTC) FILETIME=[E5809910:01CBF019] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29664 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add Netlogic Microsystems company ID and processor IDs for XLR and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. Signed-off-by: Jayachandran C --- arch/mips/include/asm/cpu.h | 27 ++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..34c0d3c 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 @@ -142,6 +143,31 @@ #define PRID_IMP_JZRISC 0x0200 /* + * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC + */ +#define PRID_IMP_NETLOGIC_XLR732 0x0000 +#define PRID_IMP_NETLOGIC_XLR716 0x0200 +#define PRID_IMP_NETLOGIC_XLR532 0x0900 +#define PRID_IMP_NETLOGIC_XLR308 0x0600 +#define PRID_IMP_NETLOGIC_XLR532C 0x0800 +#define PRID_IMP_NETLOGIC_XLR516C 0x0a00 +#define PRID_IMP_NETLOGIC_XLR508C 0x0b00 +#define PRID_IMP_NETLOGIC_XLR308C 0x0f00 +#define PRID_IMP_NETLOGIC_XLS608 0x8000 +#define PRID_IMP_NETLOGIC_XLS408 0x8800 +#define PRID_IMP_NETLOGIC_XLS404 0x8c00 +#define PRID_IMP_NETLOGIC_XLS208 0x8e00 +#define PRID_IMP_NETLOGIC_XLS204 0x8f00 +#define PRID_IMP_NETLOGIC_XLS108 0xce00 +#define PRID_IMP_NETLOGIC_XLS104 0xcf00 +#define PRID_IMP_NETLOGIC_XLS616B 0x4000 +#define PRID_IMP_NETLOGIC_XLS608B 0x4a00 +#define PRID_IMP_NETLOGIC_XLS416B 0x4400 +#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 +#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 +#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 + +/* * Definitions for 7:0 on legacy processors */ @@ -234,6 +260,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, + CPU_XLR, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..a995d56 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + c->options = (MIPS_CPU_TLB | + MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | + MIPS_CPU_WATCH | + MIPS_CPU_EJTAG | + MIPS_CPU_LLSC); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_NETLOGIC_XLR732: + case PRID_IMP_NETLOGIC_XLR716: + case PRID_IMP_NETLOGIC_XLR532: + case PRID_IMP_NETLOGIC_XLR308: + case PRID_IMP_NETLOGIC_XLR532C: + case PRID_IMP_NETLOGIC_XLR516C: + case PRID_IMP_NETLOGIC_XLR508C: + case PRID_IMP_NETLOGIC_XLR308C: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLR"; + break; + + case PRID_IMP_NETLOGIC_XLS608: + case PRID_IMP_NETLOGIC_XLS408: + case PRID_IMP_NETLOGIC_XLS404: + case PRID_IMP_NETLOGIC_XLS208: + case PRID_IMP_NETLOGIC_XLS204: + case PRID_IMP_NETLOGIC_XLS108: + case PRID_IMP_NETLOGIC_XLS104: + case PRID_IMP_NETLOGIC_XLS616B: + case PRID_IMP_NETLOGIC_XLS608B: + case PRID_IMP_NETLOGIC_XLS416B: + case PRID_IMP_NETLOGIC_XLS412B: + case PRID_IMP_NETLOGIC_XLS408B: + case PRID_IMP_NETLOGIC_XLS404B: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLS"; + break; + + default: + printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", + c->processor_id); + c->cputype = CPU_XLR; + break; + } + + c->isa_level = MIPS_CPU_ISA_M64R1; + c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; +} + #ifdef CONFIG_64BIT /* For use by uaccess.h */ u64 __ua_limit; @@ -1034,6 +1087,8 @@ __cpuinit void cpu_probe(void) break; case PRID_COMP_INGENIC: cpu_probe_ingenic(c, cpu); + case PRID_COMP_NETLOGIC: + cpu_probe_netlogic(c, cpu); break; } -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Apr 1 05:07:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 05:07:21 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1462 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490975Ab1DADGx (ORCPT ); Fri, 1 Apr 2011 05:06:53 +0200 X-TM-IMSS-Message-ID: <7511d71000009b48@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 7511d71000009b48 ; Thu, 31 Mar 2011 20:06:43 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 31 Mar 2011 20:07:34 -0700 Date: Fri, 1 Apr 2011 08:37:08 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 2/6] mach-netlogic include directory and files. Message-ID: <6841269a1e6689072a1e87958a2bc579a25d0bdd.1301626288.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 01 Apr 2011 03:07:35.0014 (UTC) FILETIME=[F2E51860:01CBF019] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29665 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add war.h and irq.h with XLR/XLS definitions. Add feature overrides for XLR/XLS. Signed-off-by: Jayachandran C --- .../asm/mach-netlogic/cpu-feature-overrides.h | 47 ++++++++++++++++++++ arch/mips/include/asm/mach-netlogic/irq.h | 14 ++++++ arch/mips/include/asm/mach-netlogic/war.h | 26 +++++++++++ 3 files changed, 87 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h new file mode 100644 index 0000000..3b72827 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_counter 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_icache_snoops_remote_store 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h new file mode 100644 index 0000000..b590245 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/irq.h @@ -0,0 +1,14 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + */ +#ifndef __ASM_NETLOGIC_IRQ_H +#define __ASM_NETLOGIC_IRQ_H + +#define NR_IRQS 64 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* __ASM_NETLOGIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h new file mode 100644 index 0000000..22da893 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/war.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_NLM_WAR_H +#define __ASM_MIPS_MACH_NLM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_NLM_WAR_H */ -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Apr 1 05:07:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 05:07:46 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1460 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490970Ab1DADGx (ORCPT ); Fri, 1 Apr 2011 05:06:53 +0200 X-TM-IMSS-Message-ID: <7511d5b800009b45@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 7511d5b800009b45 ; Thu, 31 Mar 2011 20:06:42 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 31 Mar 2011 20:06:52 -0700 Date: Fri, 1 Apr 2011 08:36:26 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 0/6] Support for Netlogic XLR/XLS processors Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 01 Apr 2011 03:06:53.0186 (UTC) FILETIME=[D9F6A620:01CBF019] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29666 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Time to give this another go. This time the license of Netlogic files are updated to a dual license. I'm not giving up hope yet :) As always, comments on code and licenses are welcome. Changes from last version(v2): * Netlogic files updated to use a dual license (GPLv2 or Netlogic 2-clause BSD license.) * irq.c updated to use new style of irq_data based handlers. * Rebased to latest linux-mips master tip. * Minor reshuffle of patches to group them better. Changes from last version(v1): * Initial 64-bit support * cleanup irq.c, don't use irq_desc[] directly * couple of checkpatch.pl white-space fixes Changes from last version(v0): * Remove c-netlogic.c for now, c-r4k works well enough for the first cut, so the custom cache handler can be considered later. * More elaborate asm/mach-netlogic/cpu-feature-overrides.h (noted by David Daney) These set of patches add support for the XLR and XLS multi-core MIPS64 SoCs from Netlogic Microsystems. These changes enable us to boot linux-mips on Netlogic evaluation boards from the netlogic bootloader. Jayachandran C (6): Netlogic XLR/XLS processor IDs. mach-netlogic include directory and files. Cache support, TLB support, asm/module.h entry Platform files for XLR/XLS processor support Kconfig and Makefile update for Netlogic XLR/XLS Add default configuration for XLR/XLS processors arch/mips/Kconfig | 42 + arch/mips/Makefile | 12 + arch/mips/configs/nlm_xlr_defconfig | 1705 ++++++++++++++++++++ arch/mips/include/asm/cpu.h | 27 + .../asm/mach-netlogic/cpu-feature-overrides.h | 47 + arch/mips/include/asm/mach-netlogic/irq.h | 14 + arch/mips/include/asm/mach-netlogic/war.h | 26 + arch/mips/include/asm/module.h | 2 + arch/mips/include/asm/netlogic/interrupt.h | 45 + arch/mips/include/asm/netlogic/mips-extns.h | 76 + arch/mips/include/asm/netlogic/psb-bootinfo.h | 109 ++ arch/mips/include/asm/netlogic/xlr/gpio.h | 73 + arch/mips/include/asm/netlogic/xlr/iomap.h | 131 ++ arch/mips/include/asm/netlogic/xlr/pic.h | 231 +++ arch/mips/include/asm/netlogic/xlr/xlr.h | 54 + arch/mips/kernel/Makefile | 1 + arch/mips/kernel/cpu-probe.c | 55 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + arch/mips/netlogic/Kconfig | 5 + arch/mips/netlogic/xlr/Makefile | 5 + arch/mips/netlogic/xlr/irq.c | 221 +++ arch/mips/netlogic/xlr/platform.c | 100 ++ arch/mips/netlogic/xlr/setup.c | 188 +++ arch/mips/netlogic/xlr/smp.c | 225 +++ arch/mips/netlogic/xlr/smpboot.S | 94 ++ arch/mips/netlogic/xlr/time.c | 51 + arch/mips/netlogic/xlr/xlr_console.c | 46 + 30 files changed, 3589 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Apr 1 05:08:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 05:08:10 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1702 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491010Ab1DADHu (ORCPT ); Fri, 1 Apr 2011 05:07:50 +0200 X-TM-IMSS-Message-ID: <7512c2b800009b4b@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 7512c2b800009b4b ; Thu, 31 Mar 2011 20:07:43 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 31 Mar 2011 20:08:17 -0700 Date: Fri, 1 Apr 2011 08:37:50 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 3/6] Cache support, TLB support, asm/module.h entry Message-ID: <6a298284d465246ef09e1cb166494c16c1baf8ec.1301626288.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 01 Apr 2011 03:08:17.0983 (UTC) FILETIME=[0C81A4F0:01CBF01A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29667 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips CPU_XLR case added to mm/tlbex.c CPU_XLR case added to mm/c-r4k.c for PINDEX attribute Add XLR to asm/module.h Signed-off-by: Jayachandran C --- arch/mips/include/asm/module.h | 2 ++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 3 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index d94085a..bc01a02 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON2 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " +#elif defined CONFIG_CPU_XLR +#define MODULE_PROC_FAMILY "XLR " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 71bddf8..d9bc5d3 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1006,6 +1006,7 @@ static void __cpuinit probe_pcache(void) case CPU_25KF: case CPU_SB1: case CPU_SB1A: + case CPU_XLR: c->dcache.flags |= MIPS_CACHE_PINDEX; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 79e39e0..b3bf60d 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: + case CPU_XLR: uasm_i_nop(p); tlbw(p); break; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Apr 1 05:08:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 05:08:35 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1703 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491006Ab1DADHv (ORCPT ); Fri, 1 Apr 2011 05:07:51 +0200 X-TM-IMSS-Message-ID: <7512c31600009b4c@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 7512c31600009b4c ; Thu, 31 Mar 2011 20:07:43 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 31 Mar 2011 20:08:39 -0700 Date: Fri, 1 Apr 2011 08:38:12 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 4/6] Platform files for XLR/XLS processor support Message-ID: <7186c4dd2d7240b13a691afcd05d3b9815cf36eb.1301626288.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 01 Apr 2011 03:08:39.0499 (UTC) FILETIME=[1954B9B0:01CBF01A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29668 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips * include/asm/netlogic added with files common for all Netlogic processors (common with XLP which will be added later) * include/asm/netlogic/xlr for XLR/XLS chip specific files * netlogic/xlr for XLR/XLS platform files Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/interrupt.h | 45 +++++ arch/mips/include/asm/netlogic/mips-extns.h | 76 ++++++++ arch/mips/include/asm/netlogic/psb-bootinfo.h | 109 ++++++++++++ arch/mips/include/asm/netlogic/xlr/gpio.h | 73 ++++++++ arch/mips/include/asm/netlogic/xlr/iomap.h | 131 ++++++++++++++ arch/mips/include/asm/netlogic/xlr/pic.h | 231 +++++++++++++++++++++++++ arch/mips/include/asm/netlogic/xlr/xlr.h | 54 ++++++ arch/mips/netlogic/xlr/irq.c | 221 +++++++++++++++++++++++ arch/mips/netlogic/xlr/platform.c | 100 +++++++++++ arch/mips/netlogic/xlr/setup.c | 188 ++++++++++++++++++++ arch/mips/netlogic/xlr/smp.c | 225 ++++++++++++++++++++++++ arch/mips/netlogic/xlr/smpboot.S | 94 ++++++++++ arch/mips/netlogic/xlr/time.c | 51 ++++++ arch/mips/netlogic/xlr/xlr_console.c | 46 +++++ 14 files changed, 1644 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h new file mode 100644 index 0000000..a85aadb --- /dev/null +++ b/arch/mips/include/asm/netlogic/interrupt.h @@ -0,0 +1,45 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_INTERRUPT_H +#define _ASM_NLM_INTERRUPT_H + +/* Defines for the IRQ numbers */ + +#define IRQ_IPI_SMP_FUNCTION 3 +#define IRQ_IPI_SMP_RESCHEDULE 4 +#define IRQ_MSGRING 6 +#define IRQ_TIMER 7 + +#endif diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h new file mode 100644 index 0000000..8c53d0b --- /dev/null +++ b/arch/mips/include/asm/netlogic/mips-extns.h @@ -0,0 +1,76 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_MIPS_EXTS_H +#define _ASM_NLM_MIPS_EXTS_H + +/* + * XLR and XLP interrupt request and interrupt mask registers + */ +#define read_c0_eirr() __read_64bit_c0_register($9, 6) +#define read_c0_eimr() __read_64bit_c0_register($9, 7) +#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val) + +/* + * Writing EIMR in 32 bit is a special case, the lower 8 bit of the + * EIMR is shadowed in the status register, so we cannot save and + * restore status register for split read. + */ +#define write_c0_eimr(val) \ +do { \ + if (sizeof(unsigned long) == 4) { \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, $9, 7\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\ + local_irq_restore(__flags); \ + } else \ + __write_64bit_c0_register($9, 7, (val)); \ +} while (0) + +static inline int hard_smp_processor_id(void) +{ + return __read_32bit_c0_register($15, 1) & 0x3ff; +} + +#endif /*_ASM_NLM_MIPS_EXTS_H */ diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h new file mode 100644 index 0000000..6878307 --- /dev/null +++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h @@ -0,0 +1,109 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NETLOGIC_BOOTINFO_H +#define _ASM_NETLOGIC_BOOTINFO_H + +struct psb_info { + uint64_t boot_level; + uint64_t io_base; + uint64_t output_device; + uint64_t uart_print; + uint64_t led_output; + uint64_t init; + uint64_t exit; + uint64_t warm_reset; + uint64_t wakeup; + uint64_t online_cpu_map; + uint64_t master_reentry_sp; + uint64_t master_reentry_gp; + uint64_t master_reentry_fn; + uint64_t slave_reentry_fn; + uint64_t magic_dword; + uint64_t uart_putchar; + uint64_t size; + uint64_t uart_getchar; + uint64_t nmi_handler; + uint64_t psb_version; + uint64_t mac_addr; + uint64_t cpu_frequency; + uint64_t board_version; + uint64_t malloc; + uint64_t free; + uint64_t global_shmem_addr; + uint64_t global_shmem_size; + uint64_t psb_os_cpu_map; + uint64_t userapp_cpu_map; + uint64_t wakeup_os; + uint64_t psb_mem_map; + uint64_t board_major_version; + uint64_t board_minor_version; + uint64_t board_manf_revision; + uint64_t board_serial_number; + uint64_t psb_physaddr_map; + uint64_t xlr_loaderip_config; + uint64_t bldr_envp; + uint64_t avail_mem_map; +}; + +enum { + NETLOGIC_IO_SPACE = 0x10, + PCIX_IO_SPACE, + PCIX_CFG_SPACE, + PCIX_MEMORY_SPACE, + HT_IO_SPACE, + HT_CFG_SPACE, + HT_MEMORY_SPACE, + SRAM_SPACE, + FLASH_CONTROLLER_SPACE +}; + +#define NLM_MAX_ARGS 64 +#define NLM_MAX_ENVS 32 + +/* This is what netlboot passes and linux boot_mem_map is subtly different */ +#define NLM_BOOT_MEM_MAP_MAX 32 +struct nlm_boot_mem_map { + int nr_map; + struct nlm_boot_mem_map_entry { + uint64_t addr; /* start of memory segment */ + uint64_t size; /* size of memory segment */ + uint32_t type; /* type of memory segment */ + } map[NLM_BOOT_MEM_MAP_MAX]; +}; + +/* Pointer to saved boot loader info */ +extern struct psb_info nlm_prom_info; + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h new file mode 100644 index 0000000..51f6ad4 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/gpio.h @@ -0,0 +1,73 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_GPIO_H +#define _ASM_NLM_GPIO_H + +#define NETLOGIC_GPIO_INT_EN_REG 0 +#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 +#define NETLOGIC_GPIO_IO_DIR_REG 2 +#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 +#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 + +#define NETLOGIC_GPIO_SWRESET_REG 8 +#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 +#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 +#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 +#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 +#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 +#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 +#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 +#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 + +#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 +#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 +#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 +#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 + +#define NETLOGIC_GPIO_FUSE_BANK_REG 35 +#define NETLOGIC_GPIO_CPU_RESET_REG 40 +#define NETLOGIC_GPIO_RNG_REG 43 + +#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 +#define NETLOGIC_GPIO_LED_BITMAP 0x1700000 +#define NETLOGIC_GPIO_LED_0_SHIFT 20 +#define NETLOGIC_GPIO_LED_1_SHIFT 24 + +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h new file mode 100644 index 0000000..2e3a4dd --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/iomap.h @@ -0,0 +1,131 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_IOMAP_H +#define _ASM_NLM_IOMAP_H + +#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000) +#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 +#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 +#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 +#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 +#define NETLOGIC_IO_PIC_OFFSET 0x08000 +#define NETLOGIC_IO_UART_0_OFFSET 0x14000 +#define NETLOGIC_IO_UART_1_OFFSET 0x15100 + +#define NETLOGIC_IO_SIZE 0x1000 + +#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 + +#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 +#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 + +#define NETLOGIC_IO_SRAM_OFFSET 0x07000 + +#define NETLOGIC_IO_PCIX_OFFSET 0x09000 +#define NETLOGIC_IO_HT_OFFSET 0x0A000 + +#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 + +#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 +#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 +#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 +#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 + +/* XLS devices */ +#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 +#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 +#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 +#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 + +#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 +#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 +#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 +#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 + +#define NETLOGIC_IO_USB_0_OFFSET 0x24000 +#define NETLOGIC_IO_USB_1_OFFSET 0x25000 + +#define NETLOGIC_IO_COMP_OFFSET 0x1D000 +/* end XLS devices */ + +/* XLR devices */ +#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 +#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 +#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 +#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 +/* end XLR devices */ + +#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 +#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 + +#define NETLOGIC_IO_GPIO_OFFSET 0x18000 +#define NETLOGIC_IO_FLASH_OFFSET 0x19000 +#define NETLOGIC_IO_TB_OFFSET 0x1C000 + +#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) + +/* + * Base Address (Virtual) of the PCI Config address space + * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28) + * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes + * ie 1<<24 = 16M + */ +#define DEFAULT_PCI_CONFIG_BASE 0x18000000 +#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 +#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 + +#ifndef __ASSEMBLY__ +#include +#include + +typedef volatile __u32 nlm_reg_t; +extern unsigned long netlogic_io_base; + +/* FIXME read once in write_reg */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define netlogic_read_reg(base, offset) ((base)[(offset)]) +#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value)) +#else +#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)])) +#define netlogic_write_reg(base, offset, value) \ + ((base)[(offset)] = cpu_to_be32((value))) +#endif + +#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)])) +#define netlogic_write_reg_le32(base, offset, value) \ + ((base)[(offset)] = cpu_to_le32((value))) +#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset))) +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h new file mode 100644 index 0000000..5cceb74 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -0,0 +1,231 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_XLR_PIC_H +#define _ASM_NLM_XLR_PIC_H + +#define PIC_CLKS_PER_SEC 66666666ULL +/* PIC hardware interrupt numbers */ +#define PIC_IRT_WD_INDEX 0 +#define PIC_IRT_TIMER_0_INDEX 1 +#define PIC_IRT_TIMER_1_INDEX 2 +#define PIC_IRT_TIMER_2_INDEX 3 +#define PIC_IRT_TIMER_3_INDEX 4 +#define PIC_IRT_TIMER_4_INDEX 5 +#define PIC_IRT_TIMER_5_INDEX 6 +#define PIC_IRT_TIMER_6_INDEX 7 +#define PIC_IRT_TIMER_7_INDEX 8 +#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX +#define PIC_IRT_UART_0_INDEX 9 +#define PIC_IRT_UART_1_INDEX 10 +#define PIC_IRT_I2C_0_INDEX 11 +#define PIC_IRT_I2C_1_INDEX 12 +#define PIC_IRT_PCMCIA_INDEX 13 +#define PIC_IRT_GPIO_INDEX 14 +#define PIC_IRT_HYPER_INDEX 15 +#define PIC_IRT_PCIX_INDEX 16 +/* XLS */ +#define PIC_IRT_CDE_INDEX 15 +#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16 +/* XLS */ +#define PIC_IRT_GMAC0_INDEX 17 +#define PIC_IRT_GMAC1_INDEX 18 +#define PIC_IRT_GMAC2_INDEX 19 +#define PIC_IRT_GMAC3_INDEX 20 +#define PIC_IRT_XGS0_INDEX 21 +#define PIC_IRT_XGS1_INDEX 22 +#define PIC_IRT_HYPER_FATAL_INDEX 23 +#define PIC_IRT_PCIX_FATAL_INDEX 24 +#define PIC_IRT_BRIDGE_AERR_INDEX 25 +#define PIC_IRT_BRIDGE_BERR_INDEX 26 +#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27 +#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28 +/* XLS */ +#define PIC_IRT_GMAC4_INDEX 21 +#define PIC_IRT_GMAC5_INDEX 22 +#define PIC_IRT_GMAC6_INDEX 23 +#define PIC_IRT_GMAC7_INDEX 24 +#define PIC_IRT_BRIDGE_ERR_INDEX 25 +#define PIC_IRT_PCIE_LINK0_INDEX 26 +#define PIC_IRT_PCIE_LINK1_INDEX 27 +#define PIC_IRT_PCIE_LINK2_INDEX 23 +#define PIC_IRT_PCIE_LINK3_INDEX 24 +#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28 +#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29 +#define PIC_IRT_SRIO_LINK0_INDEX 26 +#define PIC_IRT_SRIO_LINK1_INDEX 27 +#define PIC_IRT_SRIO_LINK2_INDEX 28 +#define PIC_IRT_SRIO_LINK3_INDEX 29 +#define PIC_IRT_PCIE_INT_INDEX 28 +#define PIC_IRT_PCIE_FATAL_INDEX 29 +#define PIC_IRT_GPIO_B_INDEX 30 +#define PIC_IRT_USB_INDEX 31 +/* XLS */ +#define PIC_NUM_IRTS 32 + + +#define PIC_CLOCK_TIMER 7 + +/* PIC Registers */ +#define PIC_CTRL 0x00 +#define PIC_IPI 0x04 +#define PIC_INT_ACK 0x06 + +#define WD_MAX_VAL_0 0x08 +#define WD_MAX_VAL_1 0x09 +#define WD_MASK_0 0x0a +#define WD_MASK_1 0x0b +#define WD_HEARBEAT_0 0x0c +#define WD_HEARBEAT_1 0x0d + +#define PIC_IRT_0_BASE 0x40 +#define PIC_IRT_1_BASE 0x80 +#define PIC_TIMER_MAXVAL_0_BASE 0x100 +#define PIC_TIMER_MAXVAL_1_BASE 0x110 +#define PIC_TIMER_COUNT_0_BASE 0x120 +#define PIC_TIMER_COUNT_1_BASE 0x130 + +#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) +#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) + +#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) +#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i)) +#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i)) +#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i)) + +/* + * Mapping between hardware interrupt numbers and IRQs on CPU + * we use a simple scheme to map PIC interrupts 0-31 to IRQs + * 8-39. This leaves the IRQ 0-7 for cpu interrupts like + * count/compare and FMN + */ +#define PIC_IRQ_BASE 8 +#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) +#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) + +#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE +#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) +#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX) +#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX) +#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX) +#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX) +#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX) +#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX) +#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX) +#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX) +#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ) +#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX) +#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX) +#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX) +#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX) +#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX) +#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX) +#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX) +#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX) +/* XLS */ +#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX) +#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX) +/* end XLS */ +#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX) +#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX) +#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX) +#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX) +#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX) +#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX) +#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX) +#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX) +#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) +#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) +#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) +#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) +/* XLS defines */ +#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) +#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) +#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX) +#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX) +#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX) +#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX) +#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX) +#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX) +#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX) +#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX) +#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX) +#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX) +#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX) +#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX) +#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX) +#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX) +#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX) +#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX) +#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX) +#define PIC_IRT_LAST_IRQ PIC_USB_IRQ +/* end XLS */ + +#ifndef __ASSEMBLY__ +static inline void pic_send_ipi(u32 ipi) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_IPI, ipi); +} + +static inline u32 pic_read_control(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + return netlogic_read_reg(mmio, PIC_CTRL); +} + +static inline void pic_write_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, control); +} + +static inline void pic_update_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, + (control | netlogic_read_reg(mmio, PIC_CTRL))); +} + +#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ + ((irq) <= PIC_TIMER_7_IRQ)) +#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ + ((irq) <= PIC_IRT_LAST_IRQ)) +#endif + +#endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h new file mode 100644 index 0000000..454c236 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -0,0 +1,54 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_XLR_H +#define _ASM_NLM_XLR_H + +/* Platform UART functions */ +struct uart_port; +unsigned int nlm_xlr_uart_in(struct uart_port *, int); +void nlm_xlr_uart_out(struct uart_port *, int, int); + +/* SMP support functions */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); +int nlm_wakeup_secondary_cpus(u32 wakeup_mask); +void nlm_smp_irq_init(void); +void nlm_boot_smp_nmi(void); +void prom_pre_boot_secondary_cpus(void); + +extern struct plat_smp_ops nlm_smp_ops; +extern unsigned long nlm_common_ebase; + +#endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c new file mode 100644 index 0000000..7552a06 --- /dev/null +++ b/arch/mips/netlogic/xlr/irq.c @@ -0,0 +1,221 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +static u64 nlm_irq_mask; +static DEFINE_SPINLOCK(nlm_pic_lock); + +static void xlr_pic_enable(struct irq_data *d) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + unsigned long flags; + nlm_reg_t reg; + int irq = d->irq; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + reg | (1 << 6) | (1 << 30) | (1 << 31)); + spin_unlock_irqrestore(&nlm_pic_lock, flags); + + return; +} + +static void xlr_pic_mask(struct irq_data *d) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + unsigned long flags; + nlm_reg_t reg; + int irq = d->irq; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + reg | (1 << 6) | (1 << 30) | (0 << 31)); + spin_unlock_irqrestore(&nlm_pic_lock, flags); + + return; +} + +static void xlr_pic_ack(struct irq_data *d) +{ + unsigned long flags; + nlm_reg_t *mmio; + int irq = d->irq; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +/* + * This chip definition handles interrupts routed thru the XLR + * hardware PIC, currently IRQs 8-39 are mapped to hardware intr + * 0-31 wired the XLR PIC + */ +static struct irq_chip xlr_pic = { + .name = "XLR-PIC", + .irq_enable = xlr_pic_enable, + .irq_mask = xlr_pic_mask, + .irq_ack = xlr_pic_ack, +}; + +static void rsvd_irq_handler(struct irq_data *d) +{ + WARN_ON(d->irq >= PIC_IRQ_BASE); + return; +} + +/* + * Chip definition for CPU originated interrupts(timer, msg) and + * IPIs + */ +struct irq_chip nlm_cpu_intr = { + .name = "XLR-CPU-INTR", + .irq_enable = rsvd_irq_handler, + .irq_ack = rsvd_irq_handler, +}; + +void __init init_xlr_irqs(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + uint32_t thread_mask = 1; + int level, i; + + pr_info("Interrupt thread mask [%x]\n", thread_mask); + for (i = 0; i < PIC_NUM_IRTS; i++) { + level = PIC_IRQ_IS_EDGE_TRIGGERED(i); + + /* Bind all PIC irqs to boot cpu */ + netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask); + + /* + * Use local scheduling and high polarity for all IRTs + * Invalidate all IRTs, by default + */ + netlogic_write_reg(mmio, PIC_IRT_1_BASE + i, + (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i)); + } + + /* Make all IRQs as level triggered by default */ + for (i = 0; i < NR_IRQS; i++) + irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq); + +#ifdef CONFIG_SMP + irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr, + nlm_smp_function_ipi_handler); + irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr, + nlm_smp_resched_ipi_handler); + nlm_irq_mask |= + ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); +#endif + + /* unmask all PIC related interrupts. If no handler is installed by the + * drivers, it'll just ack the interrupt and return + */ + for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) + nlm_irq_mask |= (1ULL << i); + + nlm_irq_mask |= (1ULL << IRQ_TIMER); +} + +void __init arch_init_irq(void) +{ + /* Initialize the irq descriptors */ + init_xlr_irqs(); + write_c0_eimr(nlm_irq_mask); +} + +void __cpuinit nlm_smp_irq_init(void) +{ + /* set interrupt mask for non-zero cpus */ + write_c0_eimr(nlm_irq_mask); +} + +asmlinkage void plat_irq_dispatch(void) +{ + uint64_t eirr; + int i; + + eirr = read_c0_eirr() & read_c0_eimr(); + if (!eirr) + return; + + /* no need of EIRR here, writing compare clears interrupt */ + if (eirr & (1 << IRQ_TIMER)) { + do_IRQ(IRQ_TIMER); + return; + } + + /* TODO use dcltz: optimize below code */ + for (i = 63; i != -1; i--) { + if (eirr & (1ULL << i)) + break; + } + if (i == -1) { + pr_err("no interrupt !!\n"); + return; + } + + /* Ack eirr */ + write_c0_eirr(1ULL << i); + + do_IRQ(i); + return; +} diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c new file mode 100644 index 0000000..c376701 --- /dev/null +++ b/arch/mips/netlogic/xlr/platform.c @@ -0,0 +1,100 @@ +/* + * Copyright 2011, Netlogic Microsystems. + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) +{ + nlm_reg_t *mmio; + unsigned int value; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + value = netlogic_read_reg(mmio, 0); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + return value; +} + +void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) +{ + nlm_reg_t *mmio; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + netlogic_write_reg(mmio, 0, value); +} + +#define PORT(_irq) \ + { \ + .irq = _irq, \ + .regshift = 2, \ + .iotype = UPIO_MEM32, \ + .flags = (UPF_SKIP_TEST | \ + UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\ + .uartclk = PIC_CLKS_PER_SEC, \ + .type = PORT_16550A, \ + .serial_in = nlm_xlr_uart_in, \ + .serial_out = nlm_xlr_uart_out, \ + } + +static struct plat_serial8250_port xlr_uart_data[] = { + PORT(PIC_UART_0_IRQ), + PORT(PIC_UART_1_IRQ), + {}, +}; + +static struct platform_device uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = xlr_uart_data, + }, +}; + +static int __init nlm_uart_init(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + xlr_uart_data[0].iobase = (unsigned long)mmio; + xlr_uart_data[0].membase = (void __iomem *)mmio; + xlr_uart_data[0].mapbase = (unsigned long)mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); + xlr_uart_data[1].iobase = (unsigned long)mmio; + xlr_uart_data[1].membase = (void __iomem *)mmio; + xlr_uart_data[1].mapbase = (unsigned long)mmio; + + return platform_device_register(&uart_device); +} + +arch_initcall(nlm_uart_init); diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c new file mode 100644 index 0000000..4828025 --- /dev/null +++ b/arch/mips/netlogic/xlr/setup.c @@ -0,0 +1,188 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); +unsigned long nlm_common_ebase = 0x0; +struct psb_info nlm_prom_info; + +static void nlm_early_serial_setup(void) +{ + struct uart_port s; + nlm_reg_t *uart_base; + + uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + memset(&s, 0, sizeof(s)); + s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + s.iotype = UPIO_MEM32; + s.regshift = 2; + s.irq = PIC_UART_0_IRQ; + s.uartclk = PIC_CLKS_PER_SEC; + s.serial_in = nlm_xlr_uart_in; + s.serial_out = nlm_xlr_uart_out; + s.mapbase = (unsigned long)uart_base; + s.membase = (unsigned char __iomem *)uart_base; + early_serial_setup(&s); +} + +static void nlm_linux_exit(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); + /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ + netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); + for ( ; ; ) + cpu_wait(); +} + +void __init plat_mem_setup(void) +{ + panic_timeout = 5; + _machine_restart = (void (*)(char *))nlm_linux_exit; + _machine_halt = nlm_linux_exit; + pm_power_off = nlm_linux_exit; +} + +const char *get_system_type(void) +{ + return "Netlogic XLR/XLS Series"; +} + +void __init prom_free_prom_memory(void) +{ + /* Nothing yet */ +} + +static void build_arcs_cmdline(int *argv) +{ + int i, remain, len; + char *arg; + + remain = sizeof(arcs_cmdline) - 1; + arcs_cmdline[0] = '\0'; + for (i = 0; argv[i] != 0; i++) { + arg = (char *)(long)argv[i]; + len = strlen(arg); + if (len + 1 > remain) + break; + strcat(arcs_cmdline, arg); + strcat(arcs_cmdline, " "); + remain -= len + 1; + } + + /* Add the default options here */ + if ((strstr(arcs_cmdline, "console=")) == NULL) { + arg = "console=ttyS0,38400 "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#ifdef CONFIG_BLK_DEV_INITRD + if ((strstr(arcs_cmdline, "rdinit=")) == NULL) { + arg = "rdinit=/sbin/init "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#endif + return; +fail: + panic("Cannot add %s, command line too big!", arg); +} + +static void prom_add_memory(void) +{ + struct nlm_boot_mem_map *bootm; + u64 start, size; + u64 pref_backup = 512; /* avoid pref walking beyond end */ + int i; + + bootm = (void *)(long)nlm_prom_info.psb_mem_map; + for (i = 0; i < bootm->nr_map; i++) { + if (bootm->map[i].type != BOOT_MEM_RAM) + continue; + start = bootm->map[i].addr; + size = bootm->map[i].size; + + /* Work around for using bootloader mem */ + if (i == 0 && start == 0 && size == 0x0c000000) + size = 0x0ff00000; + + add_memory_region(start, size - pref_backup, BOOT_MEM_RAM); + } +} + +void __init prom_init(void) +{ + int *argv, *envp; /* passed as 32 bit ptrs */ + struct psb_info *prom_infop; + + /* truncate to 32 bit and sign extend all args */ + argv = (int *)(long)(int)fw_arg1; + envp = (int *)(long)(int)fw_arg2; + prom_infop = (struct psb_info *)(long)(int)fw_arg3; + + nlm_prom_info = *prom_infop; + + nlm_early_serial_setup(); + build_arcs_cmdline(argv); + nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); + prom_add_memory(); + +#ifdef CONFIG_SMP + nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map); + register_smp_ops(&nlm_smp_ops); +#endif +} diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c new file mode 100644 index 0000000..b495a7f --- /dev/null +++ b/arch/mips/netlogic/xlr/smp.c @@ -0,0 +1,225 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +void core_send_ipi(int logical_cpu, unsigned int action) +{ + int cpu = cpu_logical_map(logical_cpu); + u32 tid = cpu & 0x3; + u32 pid = (cpu >> 2) & 0x07; + u32 ipi = (tid << 16) | (pid << 20); + + if (action & SMP_CALL_FUNCTION) + ipi |= IRQ_IPI_SMP_FUNCTION; + else if (action & SMP_RESCHEDULE_YOURSELF) + ipi |= IRQ_IPI_SMP_RESCHEDULE; + else + return; + + pic_send_ipi(ipi); +} + +void nlm_send_ipi_single(int cpu, unsigned int action) +{ + core_send_ipi(cpu, action); +} + +void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + int cpu; + + for_each_cpu(cpu, mask) { + core_send_ipi(cpu, action); + } +} + +/* IRQ_IPI_SMP_FUNCTION Handler */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + smp_call_function_interrupt(); +} + +/* IRQ_IPI_SMP_RESCHEDULE handler */ +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + set_need_resched(); +} + +void nlm_common_ipi_handler(int irq, struct pt_regs *regs) +{ + if (irq == IRQ_IPI_SMP_FUNCTION) { + smp_call_function_interrupt(); + } else { + /* Announce that we are for reschduling */ + set_need_resched(); + } +} + +/* + * Called before going into mips code, early cpu init + */ +void nlm_early_init_secondary(void) +{ + write_c0_ebase((uint32_t)nlm_common_ebase); + /* TLB partition here later */ +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit nlm_init_secondary(void) +{ + nlm_smp_irq_init(); +} + +void nlm_smp_finish(void) +{ +#ifdef notyet + nlm_common_msgring_cpu_init(); +#endif +} + +void nlm_cpus_done(void) +{ +} + +/* + * Boot all other cpus in the system, initialize them, and bring them into + * the boot function + */ +int nlm_cpu_unblock[NR_CPUS]; +int nlm_cpu_ready[NR_CPUS]; +unsigned long nlm_next_gp; +unsigned long nlm_next_sp; +cpumask_t phys_cpu_present_map; + +void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long)task_thread_info(idle); + unsigned long sp = (unsigned long)__KSTK_TOS(idle); + int cpu = cpu_logical_map(logical_cpu); + + nlm_next_sp = sp; + nlm_next_gp = gp; + + /* barrier */ + __sync(); + nlm_cpu_unblock[cpu] = 1; +} + +void __init nlm_smp_setup(void) +{ + unsigned int boot_cpu; + int num_cpus, i; + + boot_cpu = hard_smp_processor_id(); + cpus_clear(phys_cpu_present_map); + + cpu_set(boot_cpu, phys_cpu_present_map); + __cpu_number_map[boot_cpu] = 0; + __cpu_logical_map[0] = boot_cpu; + cpu_set(0, cpu_possible_map); + + num_cpus = 1; + for (i = 0; i < NR_CPUS; i++) { + if (nlm_cpu_ready[i]) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = num_cpus; + __cpu_logical_map[num_cpus] = i; + cpu_set(num_cpus, cpu_possible_map); + ++num_cpus; + } + } + + pr_info("Phys CPU present map: %lx, possible map %lx\n", + (unsigned long)phys_cpu_present_map.bits[0], + (unsigned long)cpu_possible_map.bits[0]); + + pr_info("Detected %i Slave CPU(s)\n", num_cpus); +} + +void nlm_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops nlm_smp_ops = { + .send_ipi_single = nlm_send_ipi_single, + .send_ipi_mask = nlm_send_ipi_mask, + .init_secondary = nlm_init_secondary, + .smp_finish = nlm_smp_finish, + .cpus_done = nlm_cpus_done, + .boot_secondary = nlm_boot_secondary, + .smp_setup = nlm_smp_setup, + .prepare_cpus = nlm_prepare_cpus, +}; + +unsigned long secondary_entry_point; + +int nlm_wakeup_secondary_cpus(u32 wakeup_mask) +{ + unsigned int tid, pid, ipi, i, boot_cpu; + void *reset_vec; + + secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus; + reset_vec = (void *)CKSEG1ADDR(0x1fc00000); + memcpy(reset_vec, nlm_boot_smp_nmi, 0x80); + boot_cpu = hard_smp_processor_id(); + + for (i = 0; i < NR_CPUS; i++) { + if (i == boot_cpu) + continue; + if (wakeup_mask & (1u << i)) { + tid = i & 0x3; + pid = (i >> 2) & 0x7; + ipi = (tid << 16) | (pid << 20) | (1 << 8); + pic_send_ipi(ipi); + } + } + + return 0; +} diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S new file mode 100644 index 0000000..b8e0744 --- /dev/null +++ b/arch/mips/netlogic/xlr/smpboot.S @@ -0,0 +1,94 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/* Don't jump to linux function from Bootloader stack. Change it + * here. Kernel might allocate bootloader memory before all the CPUs are + * brought up (eg: Inode cache region) and we better don't overwrite this + * memory + */ +NESTED(prom_pre_boot_secondary_cpus, 16, sp) + .set mips64 + mfc0 t0, $15, 1 # read ebase + andi t0, 0x1f # t0 has the processor_id() + sll t0, 2 # offset in cpu array + + PTR_LA t1, nlm_cpu_ready # mark CPU ready + PTR_ADDU t1, t0 + li t2, 1 + sw t2, 0(t1) + + PTR_LA t1, nlm_cpu_unblock + PTR_ADDU t1, t0 +1: lw t2, 0(t1) # wait till unblocked + beqz t2, 1b + nop + + PTR_LA t1, nlm_next_sp + PTR_L sp, 0(t1) + PTR_LA t1, nlm_next_gp + PTR_L gp, 0(t1) + + PTR_LA t0, nlm_early_init_secondary + jalr t0 + nop + + PTR_LA t0, smp_bootstrap + jr t0 + nop +END(prom_pre_boot_secondary_cpus) + +NESTED(nlm_boot_smp_nmi, 0, sp) + .set push + .set noat + .set mips64 + .set noreorder + + /* Clear the NMI and BEV bits */ + MFC0 k0, CP0_STATUS + li k1, 0xffb7ffff + and k0, k0, k1 + MTC0 k0, CP0_STATUS + + PTR_LA k1, secondary_entry_point + PTR_L k0, 0(k1) + jr k0 + nop + .set pop +END(nlm_boot_smp_nmi) diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c new file mode 100644 index 0000000..0d81b26 --- /dev/null +++ b/arch/mips/netlogic/xlr/time.c @@ -0,0 +1,51 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return IRQ_TIMER; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = nlm_prom_info.cpu_frequency; + pr_info("MIPS counter frequency [%ld]\n", + (unsigned long)mips_hpt_frequency); +} diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/xlr_console.c new file mode 100644 index 0000000..759df06 --- /dev/null +++ b/arch/mips/netlogic/xlr/xlr_console.c @@ -0,0 +1,46 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +void prom_putchar(char c) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + while (netlogic_read_reg(mmio, 0x5) == 0) + ; + netlogic_write_reg(mmio, 0x0, c); +} -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Apr 1 05:08:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 05:08:59 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:2655 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491010Ab1DADIv (ORCPT ); Fri, 1 Apr 2011 05:08:51 +0200 X-TM-IMSS-Message-ID: <7513b18c00009b54@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 7513b18c00009b54 ; Thu, 31 Mar 2011 20:08:44 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 31 Mar 2011 20:08:58 -0700 Date: Fri, 1 Apr 2011 08:38:32 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 5/6] Kconfig and Makefile update for Netlogic XLR/XLS Message-ID: <4ed99b58db8aafa2bed24b90ede3486b64dcb0ff.1301626288.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 01 Apr 2011 03:08:59.0077 (UTC) FILETIME=[25001750:01CBF01A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29669 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add NLM_XLR_BOARD, CPU_XLR and other config options Makefile updates, mostly based on r4k Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 42 +++++++++++++++++++++++++++++++++++++++ arch/mips/Makefile | 12 +++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/netlogic/Kconfig | 5 ++++ arch/mips/netlogic/xlr/Makefile | 5 ++++ 7 files changed, 67 insertions(+), 0 deletions(-) create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 83aa5fb..d9e9b2b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -736,6 +736,33 @@ config CAVIUM_OCTEON_REFERENCE_BOARD Hikari Say Y here for most Octeon reference boards. +config NLM_XLR_BOARD + bool "Netlogic XLR/XLS based systems" + depends on EXPERIMENTAL + select BOOT_ELF32 + select NLM_COMMON + select NLM_XLR + select SYS_HAS_CPU_XLR + select SYS_SUPPORTS_SMP + select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select 64BIT_PHYS_ADDR + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select DMA_COHERENT + select NR_CPUS_DEFAULT_32 + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select ZONE_DMA if 64BIT + select SYNC_R4K + select SYS_HAS_EARLY_PRINTK + help + Support for systems based on Netlogic XLR and XLS processors. + Say Y here if you have a XLR or XLS based board. + endchoice source "arch/mips/alchemy/Kconfig" @@ -752,6 +779,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/netlogic/Kconfig" endmenu @@ -1425,6 +1453,17 @@ config CPU_BMIPS5000 help Broadcom BMIPS5000 processors. +config CPU_XLR + bool "Netlogic XLR SoC" + depends on SYS_HAS_CPU_XLR + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select CPU_SUPPORTS_HUGEPAGES + help + Netlogic Microsystems XLR/XLS processors. endchoice if CPU_LOONGSON2F @@ -1555,6 +1594,9 @@ config SYS_HAS_CPU_BMIPS4380 config SYS_HAS_CPU_BMIPS5000 bool +config SYS_HAS_CPU_XLR + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ac1d5b6..8302423 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -191,6 +191,18 @@ endif # include $(srctree)/arch/mips/Kbuild.platforms +# +# NETLOGIC SOC Common (common) +# +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic + +# +# NETLOGIC XLR/XLS SoC, Simulator and boards +# +core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ +load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 + cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cedee2b..83bba33 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o +obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 2adead5..b2cad4f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o +obj-$(CONFIG_CPU_XLR) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index d679c77..eb44636 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o +obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig new file mode 100644 index 0000000..a5ca743 --- /dev/null +++ b/arch/mips/netlogic/Kconfig @@ -0,0 +1,5 @@ +config NLM_COMMON + bool + +config NLM_XLR + bool diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile new file mode 100644 index 0000000..9bd3f73 --- /dev/null +++ b/arch/mips/netlogic/xlr/Makefile @@ -0,0 +1,5 @@ +obj-y += setup.o platform.o irq.o setup.o time.o +obj-$(CONFIG_SMP) += smp.o smpboot.o +obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o + +EXTRA_CFLAGS += -Werror -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Apr 1 05:09:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 05:09:24 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:2656 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491013Ab1DADIw (ORCPT ); Fri, 1 Apr 2011 05:08:52 +0200 X-TM-IMSS-Message-ID: <7513b20900009b55@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 7513b20900009b55 ; Thu, 31 Mar 2011 20:08:44 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 31 Mar 2011 20:09:19 -0700 Date: Fri, 1 Apr 2011 08:38:53 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 6/6] Add default configuration for XLR/XLS processors Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 01 Apr 2011 03:09:19.0671 (UTC) FILETIME=[31467C70:01CBF01A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29670 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Enable XLR CPU support, SMP, initramfs based root filesystem etc. Signed-off-by: Jayachandran C --- arch/mips/configs/nlm_xlr_defconfig | 1705 +++++++++++++++++++++++++++++++++++ 1 files changed, 1705 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig new file mode 100644 index 0000000..a5a22f0 --- /dev/null +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -0,0 +1,1705 @@ +# +# Automatically generated make config: don't edit +# Linux/mips 2.6.39-rc1 Kernel Configuration +# Fri Apr 1 07:44:07 2011 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_NLM_XLR_BOARD=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_NLM_COMMON=y +CONFIG_NLM_XLR=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_FIND_BIT_LE=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYNC_R4K=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_XLR=y +CONFIG_SYS_HAS_CPU_XLR=y +CONFIG_WEAK_ORDERING=y +CONFIG_WEAK_REORDERING_BEYOND_LLSC=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_SMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_32=y +CONFIG_NR_CPUS=32 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_KEXEC=y +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +# CONFIG_EMBEDDED is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_VERBOSE is not set +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=m +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_IP_SET is not set +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +# CONFIG_IP_VS_PE_SIP is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +CONFIG_PHONET=m +CONFIG_IEEE802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_PARTITIONS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=y +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_SENSORS_LIS3LV02D is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FC_TGT_ATTRS=y +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +# CONFIG_ISCSI_BOOT_SYSFS is not set +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_N_HDLC=m +# CONFIG_N_GSM is not set +# CONFIG_DEVKMEM is not set +CONFIG_STALDRV=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XZ is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_MINIX_FS_NATIVE_ENDIAN=y +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_PSTORE is not set +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EXOFS_FS=m +# CONFIG_EXOFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_NEW_IDMAPPER is not set +CONFIG_NFSD=m +CONFIG_NFSD_DEPRECATED=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_ACL is not set +CONFIG_CIFS_EXPERIMENTAL=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +# CONFIG_NCPFS_SMALLDOS is not set +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +# CONFIG_AFS_DEBUG is not set +# CONFIG_AFS_FSCACHE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +# CONFIG_ACORN_PARTITION_CUMANA is not set +# CONFIG_ACORN_PARTITION_EESOX is not set +CONFIG_ACORN_PARTITION_ICS=y +# CONFIG_ACORN_PARTITION_ADFS is not set +# CONFIG_ACORN_PARTITION_POWERTEC is not set +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_DETECTOR_RUNNABLE=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +# CONFIG_KGDB_LOW_LEVEL_TRAP is not set +# CONFIG_KGDB_KDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_TOMOYO=y +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_IMA is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=m +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_VIRTUALIZATION is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From ralf@linux-mips.org Fri Apr 1 12:23:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 12:23:26 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:42596 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491122Ab1DAKXW (ORCPT ); Fri, 1 Apr 2011 12:23:22 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p31ANL7u029728; Fri, 1 Apr 2011 12:23:21 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p31ANKtk029725; Fri, 1 Apr 2011 12:23:20 +0200 Date: Fri, 1 Apr 2011 12:23:20 +0200 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: Cleanup Kconfig IRQ_CPU* symbols. Message-ID: <20110401102320.GA29252@linux-mips.org> References: <1297980273-25920-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1297980273-25920-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29671 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Fri Apr 1 14:05:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 14:06:01 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:40280 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491122Ab1DAMF6 (ORCPT ); Fri, 1 Apr 2011 14:05:58 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p31C5v83006606; Fri, 1 Apr 2011 14:05:58 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p31C5uha006604; Fri, 1 Apr 2011 14:05:56 +0200 Date: Fri, 1 Apr 2011 14:05:56 +0200 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: Guard the body of arch/mips/cavium-octeon/Kconfig with CPU_CAVIUM_OCTEON Message-ID: <20110401120556.GB29252@linux-mips.org> References: <1297995812-4006-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1297995812-4006-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29672 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From dedekind1@gmail.com Fri Apr 1 14:46:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 14:46:36 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:43437 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491122Ab1DAMqd (ORCPT ); Fri, 1 Apr 2011 14:46:33 +0200 Received: by wyb28 with SMTP id 28so3547546wyb.36 for ; Fri, 01 Apr 2011 05:46:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=adrQ7VSquVD7fKJy7I1e8SFfnrVcUecTf9xdcWlkFJo=; b=PIh3I+8o+y4gtcvVguCeoed/G92uEzfJZoDhba4fRtjF7aPA3UyTRSK6VUGp5nX5eJ 2MgESkUi1uUdVRULa6dDa9T271Vmm+Kg1iAtmt+wsTjYELBbEA39O38vTgdo2kX6paTC cDAufyIx3YYNmTbLVRT+15CugnIbUFQHefa/k= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; b=x9AW3YANkbWm8jPOZ63A23cGLhCPZ2bnX2E26BpV89YY66Gp3vPVYMsFOxGdi2oGei zYsSH+MLce1zD96hJMYMNLQ+LyCdq/UAPhDRCEAIbJRamD7NJa1Z1moWWqXjR2uJmYi5 7j0GYSJQaj1sndUZf/mg76eyWU5Ir8A3V163Q= Received: by 10.216.69.196 with SMTP id n46mr497475wed.30.1301661986715; Fri, 01 Apr 2011 05:46:26 -0700 (PDT) Received: from ?IPv6:::1? (shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id c54sm981526wer.30.2011.04.01.05.46.17 (version=SSLv3 cipher=OTHER); Fri, 01 Apr 2011 05:46:18 -0700 (PDT) Subject: Re: [PATCH V5 06/10] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <1301470076-17279-7-git-send-email-blogic@openwrt.org> References: <1301470076-17279-1-git-send-email-blogic@openwrt.org> <1301470076-17279-7-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset="UTF-8" Date: Fri, 01 Apr 2011 15:43:52 +0300 Message-ID: <1301661832.2789.56.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29673 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips Hi, just few minor things. On Wed, 2011-03-30 at 09:27 +0200, John Crispin wrote: > +/* the NOR flash is connected to the same external bus unit (EBU) as PCI. > + * To make PCI work we need to enable the endianess swapping of the addr > + * written to the EBU. this however has some limitations and breaks when > + * using NOR. it does not really matter if the onflash data is in a swapped > + * order, however cfi sequences also fail. to workaround this we need to use > + * a complex map. We essentially software swap all addresses during probe > + * and then swizzle the unlock addresses. > + */ Would be nice to clean-up the comment a little bit and use capital letters at the start of the sentences. Also, I think the style for multi-line comments is: /* * bla * bla */ > +static void > +ltq_copy_from(struct map_info *map, void *to, > + unsigned long from, ssize_t len) > +{ > + unsigned char *f = (unsigned char *) (map->virt + from); > + unsigned char *t = (unsigned char *) to; > + unsigned long flags; > + > + spin_lock_irqsave(&ebu_lock, flags); > + while (len--) > + *t++ = *f++; > + spin_unlock_irqrestore(&ebu_lock, flags); Can you use memcpy here instead? > +} > + > +static void > +ltq_copy_to(struct map_info *map, unsigned long to, > + const void *from, ssize_t len) > +{ > + unsigned char *f = (unsigned char *) from; > + unsigned char *t = (unsigned char *) (map->virt + to); > + unsigned long flags; > + > + spin_lock_irqsave(&ebu_lock, flags); > + while (len--) > + *t++ = *f++; Can you use memcpy here instead? > + spin_unlock_irqrestore(&ebu_lock, flags); > +} > + > +static const char const *part_probe_types[] = { > + "cmdlinepart", NULL }; This can be one-liner, no need to make 2 lines. > + > +static struct map_info ltq_map = { > + .name = "ltq_nor", > + .bankwidth = 2, > + .read = ltq_read16, > + .write = ltq_write16, > + .copy_from = ltq_copy_from, > + .copy_to = ltq_copy_to, > +}; > + > +static int __init > +ltq_mtd_probe(struct platform_device *pdev) > +{ > + struct physmap_flash_data *ltq_mtd_data = > + dev_get_platdata(&pdev->dev); This can be one line - it takes only 79 characters. > + struct mtd_info *ltq_mtd = NULL; > + struct mtd_partition *parts = NULL; > + struct resource *res = 0; You do not need this initialization. > + int nr_parts = 0; > + struct cfi_private *cfi; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + dev_err(&pdev->dev, "failed to get memory resource"); > + return -ENOENT; > + } > + res = devm_request_mem_region(&pdev->dev, res->start, > + resource_size(res), dev_name(&pdev->dev)); > + if (!res) { > + dev_err(&pdev->dev, "failed to request mem resource"); > + return -EBUSY; > + } > + > + ltq_map.phys = res->start; > + ltq_map.size = resource_size(res); > + ltq_map.virt = devm_ioremap_nocache(&pdev->dev, ltq_map.phys, > + ltq_map.size); > + if (!ltq_map.virt) { > + dev_err(&pdev->dev, "failed to ioremap!\n"); > + return -EIO; > + } > + > + ltq_mtd_probing = 1; > + ltq_mtd = do_map_probe("cfi_probe", <q_map); > + ltq_mtd_probing = 0; > + if (!ltq_mtd) { > + iounmap(ltq_map.virt); > + dev_err(&pdev->dev, "probing failed\n"); > + return -ENXIO; > + } > + ltq_mtd->owner = THIS_MODULE; > + > + cfi = ltq_map.fldrv_priv; > + cfi->addr_unlock1 ^= 1; > + cfi->addr_unlock2 ^= 1; > + > + nr_parts = parse_mtd_partitions(ltq_mtd, part_probe_types, &parts, 0); > + if (nr_parts > 0) { > + dev_info(&pdev->dev, > + "using %d partitions from cmdline", nr_parts); > + } else { > + nr_parts = ltq_mtd_data->nr_parts; > + parts = ltq_mtd_data->parts; > + } > + > + add_mtd_partitions(ltq_mtd, parts, nr_parts); This function may return an error. > + return 0; > +} > + > +static struct platform_driver ltq_mtd_driver = { > + .driver = { > + .name = "ltq_nor", > + .owner = THIS_MODULE, > + }, > +}; > + > +int __init > +init_ltq_mtd(void) > +{ > + int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); > + > + if (ret) > + printk(KERN_INFO "ltq_nor: error registering platfom driver"); I think errors should be printed with KERN_ERR level. Anyway, use pr_err() here instead pleas. -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From David.Daney@caviumnetworks.com Fri Apr 1 18:57:11 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 18:57:14 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9011 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491154Ab1DAQ5L (ORCPT ); Fri, 1 Apr 2011 18:57:11 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 01 Apr 2011 09:58:00 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 1 Apr 2011 09:57:03 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 1 Apr 2011 09:57:03 -0700 Message-ID: <4D9603D8.2010709@caviumnetworks.com> Date: Fri, 01 Apr 2011 09:56:56 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , Michael Sundius , David VomLehn , Dave Hansen , Andy Whitcroft , Jon Fraser , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, stable@kernel.org Subject: Re: [PATCH v2] MIPS: Kernel crashes on boot with SPARSEMEM + HIGHMEM enabled References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Apr 2011 16:57:03.0017 (UTC) FILETIME=[D2EFB190:01CBF08D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29674 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 03/31/2011 05:27 PM, Kevin Cernekee wrote: > From: Michael Sundius > > Fix 3 problems in the MIPS SPARSEMEM implementation: > > 1) mem_init() sets/clears PG_reserved on all pages in the HIGHMEM range > without checking to see whether the page descriptor actually exists. > > 2) bootmem_init() never calls memory_present() on HIGHMEM pages, so > page descriptors are never created for them if SPARSEMEM is enabled. > > 3) bootmem_init() calls memory_present() on lowmem pages before bootmem > is fully set up. This is bad because memory_present() can allocate > bootmem in some circumstances (e.g. if SPARSEMEM_EXTREME ever got > enabled). > I think this may do the same thing as my patch: http://patchwork.linux-mips.org/patch/1988/ Although my patch had different motivations, and changes some other things around too. David Daney > Signed-off-by: Michael Sundius > Signed-off-by: Kevin Cernekee > Cc: stable@kernel.org > --- > arch/mips/kernel/setup.c | 18 +++++++++++++++++- > arch/mips/mm/init.c | 3 +++ > 2 files changed, 20 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c > index 8ad1d56..1f9f902 100644 > --- a/arch/mips/kernel/setup.c > +++ b/arch/mips/kernel/setup.c > @@ -390,7 +390,6 @@ static void __init bootmem_init(void) > > /* Register lowmem ranges */ > free_bootmem(PFN_PHYS(start), size<< PAGE_SHIFT); > - memory_present(0, start, end); > } > > /* > @@ -402,6 +401,23 @@ static void __init bootmem_init(void) > * Reserve initrd memory if needed. > */ > finalize_initrd(); > + > + /* > + * Call memory_present() on all valid ranges, for SPARSEMEM. > + * This must be done after setting up bootmem, since memory_present() > + * may allocate bootmem. > + */ > + for (i = 0; i< boot_mem_map.nr_map; i++) { > + unsigned long start, end; > + > + if (boot_mem_map.map[i].type != BOOT_MEM_RAM) > + continue; > + > + start = PFN_UP(boot_mem_map.map[i].addr); > + end = PFN_DOWN(boot_mem_map.map[i].addr > + + boot_mem_map.map[i].size); > + memory_present(0, start, end); > + } > } > > #endif /* CONFIG_SGI_IP27 */ > diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c > index 279599e..78a4cf2 100644 > --- a/arch/mips/mm/init.c > +++ b/arch/mips/mm/init.c > @@ -392,6 +392,9 @@ void __init mem_init(void) > for (tmp = highstart_pfn; tmp< highend_pfn; tmp++) { > struct page *page = pfn_to_page(tmp); > > + if (!pfn_valid(tmp)) > + continue; > + > if (!page_is_ram(tmp)) { > SetPageReserved(page); > continue; From cernekee@gmail.com Fri Apr 1 19:39:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 19:39:53 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:43934 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491820Ab1DARju (ORCPT ); Fri, 1 Apr 2011 19:39:50 +0200 Received: by fxm14 with SMTP id 14so3476288fxm.36 for ; Fri, 01 Apr 2011 10:39:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=/0MopB6npfGyCIIV+OXd0IFXS0quGBU7+0s0bLzeNkE=; b=Siuq+Ti0V/1gch32JrM91FVBFPqoFRC4Iot4SfAXXh/2YHVSxBB2WsZitfUdWetGvU wcmKhPnTXDxwOmnn9l8hBkJNSvmA6mQuxdWDDh+Bjpa2lZIkAMOwPnQHTA+7t0G7vGZH IwyxY5cV9f7hwZm5wj87jIaQngNXfuHbS2sqM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=MlqwM0ubKJnoNeh8vO9pILfiLZ+soduk9YweDrizIrd/X/Jv77q/LkIoNA6b4izsMU lZxf2q/9+4S3/hKX2aCRy6iyK4dPibEf3UDmbtNui5pKOik6TICWQQEtW+tPGoSCmamk QDGtHt5yZLmd2rMt1dT0lCJk7rJmahIAl2Yw0= MIME-Version: 1.0 Received: by 10.223.64.201 with SMTP id f9mr4541348fai.102.1301679117055; Fri, 01 Apr 2011 10:31:57 -0700 (PDT) Received: by 10.223.145.131 with HTTP; Fri, 1 Apr 2011 10:31:57 -0700 (PDT) In-Reply-To: <4D9603D8.2010709@caviumnetworks.com> References: <4D9603D8.2010709@caviumnetworks.com> Date: Fri, 1 Apr 2011 10:31:57 -0700 Message-ID: Subject: Re: [PATCH v2] MIPS: Kernel crashes on boot with SPARSEMEM + HIGHMEM enabled From: Kevin Cernekee To: David Daney , Ralf Baechle Cc: Michael Sundius , David VomLehn , Dave Hansen , Andy Whitcroft , Jon Fraser , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, stable@kernel.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29675 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips On Fri, Apr 1, 2011 at 9:56 AM, David Daney wrote: > I think this may do the same thing as my patch: > > http://patchwork.linux-mips.org/patch/1988/ > > Although my patch had different motivations, and changes some other things > around too. I noticed that some of the other architectures have started using the APIs for memory setup. Do you think this would be useful on MIPS, as part of a larger refactoring of bootmem_init() ? What I liked about Michael's fix was that it is simple and straightforward enough to meet the stable tree criteria. Long term it would probably be a good idea to clean up the memory init code and get rid of the cut&paste "for" loops. From msundius@cisco.com Fri Apr 1 20:42:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 20:42:42 +0200 (CEST) Received: from sj-iport-2.cisco.com ([171.71.176.71]:19749 "EHLO sj-iport-2.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491832Ab1DASmf (ORCPT ); Fri, 1 Apr 2011 20:42:35 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=msundius@cisco.com; l=401; q=dns/txt; s=iport; t=1301683355; x=1302892955; h=message-id:date:from:mime-version:to:cc:subject: references:in-reply-to:content-transfer-encoding; bh=ifSnFS60L/+GJEkut02Z5ikgbokeyw19FOhTWRc6PBk=; b=QMJ/ckTFNKmHzwLtZPB1xULMKxhyxL7XnJZzT12ra/DMjT7Ka6yLI63E 7Km0JDfPGw30YiOp0sJcdF+eT1TB57QUQDZhDZXdHSZ68Y2ulIW7asmYi +ToKCmOCkSSi6rIkqjJtUEq2P0a6FCD8We2zhFgZHYAtj6r6TedG4Ayj0 s=; X-IronPort-AV: E=Sophos;i="4.63,283,1299456000"; d="scan'208";a="329149870" Received: from mtv-core-1.cisco.com ([171.68.58.6]) by sj-iport-2.cisco.com with ESMTP; 01 Apr 2011 18:41:46 +0000 Received: from msundius-lnx1.corp.sa.net (dhcp-171-71-47-156.cisco.com [171.71.47.156]) by mtv-core-1.cisco.com (8.14.3/8.14.3) with ESMTP id p31Ifk7D028581; Fri, 1 Apr 2011 18:41:46 GMT Message-ID: <4D961C6A.9070808@cisco.com> Date: Fri, 01 Apr 2011 11:41:46 -0700 From: Michael Sundius User-Agent: Thunderbird 2.0.0.23 (X11/20090825) MIME-Version: 1.0 To: David Daney CC: Kevin Cernekee , Ralf Baechle , David VomLehn , Dave Hansen , Andy Whitcroft , Jon Fraser , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, stable@kernel.org Subject: Re: [PATCH v2] MIPS: Kernel crashes on boot with SPARSEMEM + HIGHMEM enabled References: <4D9603D8.2010709@caviumnetworks.com> In-Reply-To: <4D9603D8.2010709@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29676 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: msundius@cisco.com Precedence: bulk X-list: linux-mips David Daney wrote: > > > I think this may do the same thing as my patch: > > http://patchwork.linux-mips.org/patch/1988/ > > Although my patch had different motivations, and changes some other > things around too. > > David Daney > I'm not really sure why your kernel or initrd would be in memory was not within the range that had been accounted for. are you saying its in high mem? From David.Daney@caviumnetworks.com Fri Apr 1 20:48:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Apr 2011 20:48:07 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11018 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491832Ab1DASsE (ORCPT ); Fri, 1 Apr 2011 20:48:04 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 01 Apr 2011 11:48:59 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 1 Apr 2011 11:48:02 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 1 Apr 2011 11:48:02 -0700 Message-ID: <4D961DE1.50807@caviumnetworks.com> Date: Fri, 01 Apr 2011 11:48:01 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Michael Sundius CC: Kevin Cernekee , Ralf Baechle , David VomLehn , Dave Hansen , Andy Whitcroft , Jon Fraser , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, stable@kernel.org Subject: Re: [PATCH v2] MIPS: Kernel crashes on boot with SPARSEMEM + HIGHMEM enabled References: <4D9603D8.2010709@caviumnetworks.com> <4D961C6A.9070808@cisco.com> In-Reply-To: <4D961C6A.9070808@cisco.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Apr 2011 18:48:02.0048 (UTC) FILETIME=[54073000:01CBF09D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29677 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/01/2011 11:41 AM, Michael Sundius wrote: > David Daney wrote: >> >> >> I think this may do the same thing as my patch: >> >> http://patchwork.linux-mips.org/patch/1988/ >> >> Although my patch had different motivations, and changes some other >> things around too. >> >> David Daney >> > I'm not really sure why your kernel or initrd would be in memory was not > within > the range that had been accounted for. are you saying its in high mem? > Well the memory initialization code has a bunch of weird rules built in that prevent some memory from being used. For example if the kernel resides in a different SPARSE page than the rest of memory bad things happen because memory_present() was not called on something that is later freed (when init memory is released). If I try to put an initrd at a high physical address, the memory below that is not usable. My three patches try to make some sense out of the whole thing. David Daney From wilbur512@gmail.com Sun Apr 3 05:49:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Apr 2011 05:49:26 +0200 (CEST) Received: from mail-vx0-f177.google.com ([209.85.220.177]:45640 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491046Ab1DCDtT (ORCPT ); Sun, 3 Apr 2011 05:49:19 +0200 Received: by vxd2 with SMTP id 2so4269384vxd.36 for ; Sat, 02 Apr 2011 20:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:date:message-id:subject:from:to:cc :content-type; bh=S4Go7U19N/MZaCYDJY1f532FqR4InbX/UYpZ4PhUs3Q=; b=CR0YZ/8bETBpGmaA29RaRJl0wOF6syp/0yDm3Js55FhsSXbeQ8PJ/GtmUQDhUKYCQy l3GCr82rvWqR7BKcpDD3X+cHjoDvJt0AAcKmHJMBFbxIzKgw8eR/FPF+PWxzN6+ohMX1 kFnD5bwEXNNEVE+TFQVANhYnGPG6+uTWEIkIk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; b=IfCyrBDYyO0Nc94z45/UUXfbgmI+ZwYmTGWv4GC33BesCoIu6HHQtGiy7sJdK/V4t+ SHKpY68vqCyBcT7Hxw1KRlbm+X9dZVZvUR0fmcopFK0D05ICoEtRF4MuRXynUrY6sj11 OmGPXlOamfF95K/O8gm44a+ew5zPvTRX5vgyw= MIME-Version: 1.0 Received: by 10.52.66.135 with SMTP id f7mr469728vdt.198.1301802553404; Sat, 02 Apr 2011 20:49:13 -0700 (PDT) Received: by 10.52.161.169 with HTTP; Sat, 2 Apr 2011 20:49:13 -0700 (PDT) Date: Sun, 3 Apr 2011 11:49:13 +0800 Message-ID: Subject: System suffers frequent TLB miss From: "wilbur.chan" To: Linux MIPS Mailing List Cc: "Jayachandran C." Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29678 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips Hi all We have a system running on mips64 xlr 732. Our major application process is binded on CPU5, In order to reduce the tlb miss of our major process, we took the following steps: (I) Use 2 number of tlb entries to map the elf code segment and data segment, say, tlb_entry[i] { code segment} and tlb_entry[i+1] {data segment} respectively. (II) Use another 6 number of tlb entries to map 6 reserved memory regions. In this way, our process can manipulate these 6 regions without any tlb miss. However we found that, the tlib miss frequency for (I) and (II) is very high. We guess the reson for this is that, we use some malloc operation,which leads to great tlb miss, and replace our tlb entries. So we took messures to isolate our tlb entries and ordinary tlb entres that were used for malloc. (III) In tlb_init function, we set the wried register to 6, so when ordinary tlb miss occured, the tlb refill hander would write a random tlb entry above 6, at the same time we can use our own 6 tlb entries to map whatever we want. After this, we found that, process is still sufferring from TLB miss in our 6 tlb entries. I'm totally exhausted about the tlb miss, I wonder if we can record the virtual region of tlb miss and the miss count in each region, in that way, I can find out which part leads to this tlb miss.That is , to record C0_BADVADDR in tlb miss. However I'm not sure how to add code in build_r4000_tlb_refill_handler function, for it is wrote in some strage way . Any suggestion on how to reduce tlb miss? Thx in advance. From wilbur512@gmail.com Sun Apr 3 06:07:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Apr 2011 06:08:02 +0200 (CEST) Received: from mail-vx0-f177.google.com ([209.85.220.177]:56291 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491052Ab1DCEHz (ORCPT ); Sun, 3 Apr 2011 06:07:55 +0200 Received: by vxd2 with SMTP id 2so4273063vxd.36 for ; Sat, 02 Apr 2011 21:07:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=0vxJpsTYKCrKY3P20n5PBRylD7LwDdEbclzfqkuP9MM=; b=eJ9bpV6lCu1v/anBWv1zIxh5BPBmy3nb0OyS7FQ9cTN+oig8UEOFwJ2iR0f/x+zmwU 6hHeJG9lC1eyik0AGcr0DNNV6ZGRXV/KLA2xueTuSfkjpoPVJZPXal2LLPHkNIVcw8YV bDPxKtn0aNCSD/8PYvTyqc/RyB6UJSbdl7pSs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=nWNo99S59/JbZMLJA9HxTTV9rI4F+4Ii2esQp6n52vfwYW6iG2XbqcbaNVvytrL4me Fv5PSLd5e+X6TKoBUi1PnzPTiCMLlpiH0GocCmwNLvo1mfawQvObCKeqqZ/tmObHbj0r 7GpVerYWqAPQdSP40U0yLkZCEotAhXwbrH/P0= MIME-Version: 1.0 Received: by 10.52.0.9 with SMTP id 9mr6869425vda.278.1301803669930; Sat, 02 Apr 2011 21:07:49 -0700 (PDT) Received: by 10.52.161.169 with HTTP; Sat, 2 Apr 2011 21:07:49 -0700 (PDT) In-Reply-To: References: Date: Sun, 3 Apr 2011 12:07:49 +0800 Message-ID: Subject: Re: System suffers frequent TLB miss From: "wilbur.chan" To: Linux MIPS Mailing List Cc: "Jayachandran C." Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29679 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips We record our 6 tlb missing count in do_page_fault, because we don't have page table mapping for these tlb entris,each time tlb miss accured, tlb refilling handler would cause a page_fault From blogic@openwrt.org Mon Apr 4 15:35:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Apr 2011 15:35:31 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:36738 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491755Ab1DDNfZ (ORCPT ); Mon, 4 Apr 2011 15:35:25 +0200 Message-ID: <4D99C974.5060800@openwrt.org> Date: Mon, 04 Apr 2011 15:36:52 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: dedekind1@gmail.com CC: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse Subject: Re: [PATCH V5 06/10] MIPS: lantiq: add NOR flash support References: <1301470076-17279-1-git-send-email-blogic@openwrt.org> <1301470076-17279-7-git-send-email-blogic@openwrt.org> <1301661832.2789.56.camel@localhost> In-Reply-To: <1301661832.2789.56.camel@localhost> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29680 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Hi Artem thanks for the feedback, comments inline > >> +ltq_copy_from(struct map_info *map, void *to, >> + unsigned long from, ssize_t len) >> +{ >> + unsigned char *f = (unsigned char *) (map->virt + from); >> + unsigned char *t = (unsigned char *) to; >> + unsigned long flags; >> + >> + spin_lock_irqsave(&ebu_lock, flags); >> + while (len--) >> + *t++ = *f++; >> + spin_unlock_irqrestore(&ebu_lock, flags); >> > Can you use memcpy here instead? > > as we are copying to/from iomem, we cannot use memcpy as the pre-fetching breaks the copy process. the normal alternative is to use memcpy_to/fromio, however on MIPS this breaks down to a normal memcpy. i will fold your comments into the patch and resend it ASAP thanks, John From dedekind1@gmail.com Mon Apr 4 16:10:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Apr 2011 16:10:06 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:50304 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491137Ab1DDOKD (ORCPT ); Mon, 4 Apr 2011 16:10:03 +0200 Received: by wwb17 with SMTP id 17so5625259wwb.24 for ; Mon, 04 Apr 2011 07:09:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=kCmM27D4tp2kTmrFuEyuhe399TUQzmE8LNR3lwtlzeQ=; b=N9YU73bt5YVcww1RlhLCa/4gaqnZp7lR1i1AIrQcerYIJCbDv+vCH89KEWYLCWTar2 Twixj9yqVfvAaiTY+ijkUxwplCiz2OOX37sRpey+WJZicpXF86S1eu4ILGBJsgL62Q08 qm/5nIGDzm/+1Rw/j+bNgX9DIcd/VircF9Pkc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; b=xLgssEPxubnIEStvKJklxbD8HjyUEUFKe1x+pYn/FJGI/14EsX7UeORIvGdKjP/bMK vwOiyk/wm0oJ5/JJ+nxEqEX+VumkCIq0F8jhyh3L92/3NK8Y8yP4uGatZn1TSFKqCbyJ QNAVFZ3VDMXA8V5jyhU7lGnco+b/wZjphOdp0= Received: by 10.227.140.67 with SMTP id h3mr7039708wbu.80.1301926197527; Mon, 04 Apr 2011 07:09:57 -0700 (PDT) Received: from ?IPv6:::1? (shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id w25sm2938479wbd.56.2011.04.04.07.09.55 (version=SSLv3 cipher=OTHER); Mon, 04 Apr 2011 07:09:56 -0700 (PDT) Subject: Re: [PATCH V5 06/10] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <4D99C974.5060800@openwrt.org> References: <1301470076-17279-1-git-send-email-blogic@openwrt.org> <1301470076-17279-7-git-send-email-blogic@openwrt.org> <1301661832.2789.56.camel@localhost> <4D99C974.5060800@openwrt.org> Content-Type: text/plain; charset="UTF-8" Date: Mon, 04 Apr 2011 17:07:25 +0300 Message-ID: <1301926045.2760.86.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29681 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Mon, 2011-04-04 at 15:36 +0200, John Crispin wrote: > >> +ltq_copy_from(struct map_info *map, void *to, > >> + unsigned long from, ssize_t len) > >> +{ > >> + unsigned char *f = (unsigned char *) (map->virt + from); > >> + unsigned char *t = (unsigned char *) to; > >> + unsigned long flags; > >> + > >> + spin_lock_irqsave(&ebu_lock, flags); > >> + while (len--) > >> + *t++ = *f++; > >> + spin_unlock_irqrestore(&ebu_lock, flags); > >> > > Can you use memcpy here instead? > > > > > as we are copying to/from iomem, we cannot use memcpy as the > pre-fetching breaks the copy process. the normal alternative is to use > memcpy_to/fromio, however on MIPS this breaks down to a normal memcpy. Would be nice to have this comment in the code to make life of those who reads it a bit easier. -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From jayachandranc@netlogicmicro.com Mon Apr 4 19:41:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Apr 2011 19:41:29 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:3221 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491909Ab1DDRl0 (ORCPT ); Mon, 4 Apr 2011 19:41:26 +0200 X-TM-IMSS-Message-ID: <87a58c0000000126@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 87a58c0000000126 ; Mon, 4 Apr 2011 10:41:15 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 Apr 2011 10:42:15 -0700 Date: Mon, 4 Apr 2011 23:12:14 +0530 From: "Jayachandran C." To: "wilbur.chan" Cc: Linux MIPS Mailing List Subject: Re: System suffers frequent TLB miss Message-ID: <20110404174213.GA30412@jayachandranc.netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 04 Apr 2011 17:42:15.0630 (UTC) FILETIME=[A304D6E0:01CBF2EF] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29682 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips On Sun, Apr 03, 2011 at 11:49:13AM +0800, wilbur.chan wrote: > Hi all > > We have a system running on mips64 xlr 732. Our major application [...] > I'm totally exhausted about the tlb miss, I wonder if we can record > the virtual region of tlb miss and the miss count in each region, in > that way, > > I can find out which part leads to this tlb miss.That is , to record > C0_BADVADDR in tlb miss. > > > However I'm not sure how to add code in build_r4000_tlb_refill_handler > function, for it is wrote in some strage way . > > Any suggestion on how to reduce tlb miss? In our SDK linux, there is some code to add instructions in the TLB exception handler using the cpu scratch registers to count TLB misses. (see mips/mm/tlbex.c code generated with OS_SCRATCH_REG2) You can extend it with another scratch register containing the an address per cpu where to record TLB miss badvaddr values(you would just need to add code to add sizeof(void*) to the scratch reg value and UASM_i_SW to store addr). This should give you and idea which adresses are causing the TLB miss. I have not actually tried this out on linux(but I have implemented similar code on FreeBSD and vxWorks) so it should work, let me know if you are able to get this going... JC. From linkinjeon@gmail.com Tue Apr 5 10:17:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 10:17:35 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:57954 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491134Ab1DEIR3 convert rfc822-to-8bit (ORCPT ); Tue, 5 Apr 2011 10:17:29 +0200 Received: by wyb28 with SMTP id 28so117363wyb.36 for ; Tue, 05 Apr 2011 01:17:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=buN8xNYhHszaPsj64ATi3eB2TW8hU9D34YukIiaX6No=; b=QFw/paywn4YqVxWwWWckH8/uBNuZas1BLYpe2pdxRIvCgKwpfDzZF80dAbI2nZXmjU UhLIwVKq6qIBasJHcjWIoo0yiegPGlU3QG3O4gid8rfAXBef3Ric9Hvkty8xHzhFg6eW UuAWXuW+QvABwcB+0quK/0D1iAxB99+xm1CdE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=H9pS1gdiR0dmoX0XJ9yma1s5zmcfpV2Gq6JE1tpIoEcRSOFIbIza0x55vNpiiiu63b n+2MuZno1c2DLAu914DWMt2TB3SB+VoeX7YBPt0VDhgqz7t5MHtEepDbDhcospU2bvpc 0fvThpXpy81q6M0rHbBqbQ9ILuU8BdtTMeYdk= MIME-Version: 1.0 Received: by 10.227.163.13 with SMTP id y13mr2230082wbx.56.1301991443445; Tue, 05 Apr 2011 01:17:23 -0700 (PDT) Received: by 10.227.37.160 with HTTP; Tue, 5 Apr 2011 01:17:23 -0700 (PDT) In-Reply-To: References: <28c262361003230146o7bca61e6h3af2062b1172fdb2@mail.gmail.com> Date: Tue, 5 Apr 2011 17:17:23 +0900 Message-ID: Subject: Re: data consistency of high page From: NamJae Jeon To: Minchan Kim Cc: Ralf Baechle , lkml , linux-mips Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29683 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linkinjeon@gmail.com Precedence: bulk X-list: linux-mips Hi. As you know, there is cache operation about highpage in arm arch. arch/arm/mm/flush.c ----------------------------------------------------------------------------------------------- if (!PageHighMem(page)) { __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); } else { void *addr = kmap_high_get(page); if (addr) { __cpuc_flush_dcache_area(addr, PAGE_SIZE); kunmap_high(page); } else if (cache_is_vipt()) { /* unmapped pages might still be cached */ addr = kmap_atomic(page); __cpuc_flush_dcache_area(addr, PAGE_SIZE); kunmap_atomic(addr); } } ------------------------------------------------------------------------------------------------- currently, mips kernel just return without cache operation. Would you plz tell me your opinion ? Thanks. 2010/3/23 NamJae Jeon : > Hi. Ralf. > > I'm Namjae.jeon. nice to meet you. > > I face cache aliasing problem on mips 34ke. > > Our target cache is 34kB 4way i/d-cache , 32bytes linesize. > > As you know, there is possibility of cache aliasing on 8kB per way. > > But mips arch of kernel mainline can not properly  handile this case. > > For example, highmem handling in __fluash_dcache_page function is just return. > > So, if argument page is page in highmem, it can not flush in dcache line. > > I want to listen your opinion. > > Thanks. > > > 2010/3/23 Minchan Kim : >> Hi, Ralf. >> >> Below is thread long time ago. >> At that time, we can't end up the problem by some reason. >> Sorry for that. >> >> The problem would occur, again. >> >> On Fri, Oct 16, 2009 at 6:24 PM, Ralf Baechle wrote: >>> On Fri, Oct 16, 2009 at 02:17:19PM +0900, Minchan Kim wrote: >>> >>>> Many code of kernel fs usually allocate high page and flush. >>>> But flush_dcache_page of mips checks PageHighMem to avoid flush >>>> so that data consistency is broken, I think. >>> >>> What processor and cache configuration? >>> >>>> I found it's by you and Atsushi-san on 585fa724. >>>> Why do we need the check? >>>> Could you elaborte please? >>> >>> The if statement exists because __flush_dcache_page would crash if a page >>> is not mapped.  This of course isn't correct but that wasn't a problem >>> since highmem still is only supported on machines that don't have aliases. >>> >>>  Ralf >>> >> >> Our system is following as. >> >> mips 34ke >> primary i-cache 32kB VIPT 4way 32 byte line size. >> primary d-cache 32kB 4way  32 bytes linesize >> >> If you have further questions, Namjae, Could you follow question of Ralf? >> >> -- >> Kind regards, >> Minchan Kim >> > From blogic@openwrt.org Tue Apr 5 14:09:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 14:09:43 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:39277 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491171Ab1DEMJg (ORCPT ); Tue, 5 Apr 2011 14:09:36 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , Felix Fietkau , alan@lxorguk.ukuu.org.uk, linux-mips@linux-mips.org, linux-serial@vger.kernel.org Subject: [PATCH V6] MIPS: lantiq: add serial port support Date: Tue, 5 Apr 2011 14:10:57 +0200 Message-Id: <1302005458-8423-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29684 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the 2 serial ports found inside the Lantiq SoC family Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Signed-off-by: Felix Fietkau Cc: alan@lxorguk.ukuu.org.uk Cc: linux-mips@linux-mips.org Cc: linux-serial@vger.kernel.org --- Changes in V2 * small cleanups * use global register access macros * properly register memory resources Changes in V3 * whitespace * change __iomem void to void __iomem * multiline comments * use pr_* macros instead of printk Changes in V4 * remove unused defines * clean code that requests the interrupts * add linux-serial to the CC list Changes in V6 * spinlock code that accesses registers properly * properly use/handle refcounting of struct tty_struct * clear termios flags that are not supported by the driver/hardware * use ttyLTQ instead of ttyS and let the major/minor be assigned dynamically This patch should be merged via the MIPS tree drivers/tty/serial/Kconfig | 8 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/lantiq.c | 756 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 765 insertions(+), 0 deletions(-) create mode 100644 drivers/tty/serial/lantiq.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index e1aee37..bfb346b 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1391,6 +1391,14 @@ config SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE help Support for Console on the NWP serial ports. +config SERIAL_LANTIQ + bool "Lantiq serial driver" + depends on LANTIQ + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + help + Support for console and UART on Lantiq SoCs. + config SERIAL_QE tristate "Freescale QUICC Engine serial port support" depends on QUICC_ENGINE diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index fee0690..3527604 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o +obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c new file mode 100644 index 0000000..58cf279 --- /dev/null +++ b/drivers/tty/serial/lantiq.c @@ -0,0 +1,756 @@ +/* + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2004 Infineon IFAP DC COM CPE + * Copyright (C) 2007 Felix Fietkau + * Copyright (C) 2007 John Crispin + * Copyright (C) 2010 Thomas Langer, + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PORT_LTQ_ASC 111 +#define MAXPORTS 2 +#define UART_DUMMY_UER_RX 1 +#define DRVNAME "ltq_asc" +#ifdef __BIG_ENDIAN +#define LTQ_ASC_TBUF (0x0020 + 3) +#define LTQ_ASC_RBUF (0x0024 + 3) +#else +#define LTQ_ASC_TBUF 0x0020 +#define LTQ_ASC_RBUF 0x0024 +#endif +#define LTQ_ASC_FSTAT 0x0048 +#define LTQ_ASC_WHBSTATE 0x0018 +#define LTQ_ASC_STATE 0x0014 +#define LTQ_ASC_IRNCR 0x00F8 +#define LTQ_ASC_CLC 0x0000 +#define LTQ_ASC_ID 0x0008 +#define LTQ_ASC_PISEL 0x0004 +#define LTQ_ASC_TXFCON 0x0044 +#define LTQ_ASC_RXFCON 0x0040 +#define LTQ_ASC_CON 0x0010 +#define LTQ_ASC_BG 0x0050 +#define LTQ_ASC_IRNREN 0x00F4 + +#define ASC_IRNREN_TX 0x1 +#define ASC_IRNREN_RX 0x2 +#define ASC_IRNREN_ERR 0x4 +#define ASC_IRNREN_TX_BUF 0x8 +#define ASC_IRNCR_TIR 0x1 +#define ASC_IRNCR_RIR 0x2 +#define ASC_IRNCR_EIR 0x4 + +#define ASCOPT_CSIZE 0x3 +#define TXFIFO_FL 1 +#define RXFIFO_FL 1 +#define ASCCLC_DISS 0x2 +#define ASCCLC_RMCMASK 0x0000FF00 +#define ASCCLC_RMCOFFSET 8 +#define ASCCON_M_8ASYNC 0x0 +#define ASCCON_M_7ASYNC 0x2 +#define ASCCON_ODD 0x00000020 +#define ASCCON_STP 0x00000080 +#define ASCCON_BRS 0x00000100 +#define ASCCON_FDE 0x00000200 +#define ASCCON_R 0x00008000 +#define ASCCON_FEN 0x00020000 +#define ASCCON_ROEN 0x00080000 +#define ASCCON_TOEN 0x00100000 +#define ASCSTATE_PE 0x00010000 +#define ASCSTATE_FE 0x00020000 +#define ASCSTATE_ROE 0x00080000 +#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) +#define ASCWHBSTATE_CLRREN 0x00000001 +#define ASCWHBSTATE_SETREN 0x00000002 +#define ASCWHBSTATE_CLRPE 0x00000004 +#define ASCWHBSTATE_CLRFE 0x00000008 +#define ASCWHBSTATE_CLRROE 0x00000020 +#define ASCTXFCON_TXFEN 0x0001 +#define ASCTXFCON_TXFFLU 0x0002 +#define ASCTXFCON_TXFITLMASK 0x3F00 +#define ASCTXFCON_TXFITLOFF 8 +#define ASCRXFCON_RXFEN 0x0001 +#define ASCRXFCON_RXFFLU 0x0002 +#define ASCRXFCON_RXFITLMASK 0x3F00 +#define ASCRXFCON_RXFITLOFF 8 +#define ASCFSTAT_RXFFLMASK 0x003F +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFREEMASK 0x3F000000 +#define ASCFSTAT_TXFREEOFF 24 + +static void lqasc_tx_chars(struct uart_port *port); +static struct ltq_uart_port *lqasc_port[MAXPORTS]; +static struct uart_driver lqasc_reg; +static DEFINE_SPINLOCK(ltq_asc_lock); + +struct ltq_uart_port { + struct uart_port port; + struct clk *clk; + unsigned int tx_irq; + unsigned int rx_irq; + unsigned int err_irq; +}; + +static inline struct +ltq_uart_port *to_ltq_uart_port(struct uart_port *port) +{ + return container_of(port, struct ltq_uart_port, port); +} + +static void +lqasc_stop_tx(struct uart_port *port) +{ + return; +} + +static void +lqasc_start_tx(struct uart_port *port) +{ + unsigned long flags; + spin_lock_irqsave(<q_asc_lock, flags); + lqasc_tx_chars(port); + spin_unlock_irqrestore(<q_asc_lock, flags); + return; +} + +static void +lqasc_stop_rx(struct uart_port *port) +{ + ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); +} + +static void +lqasc_enable_ms(struct uart_port *port) +{ +} + +static int +lqasc_rx_chars(struct uart_port *port) +{ + struct tty_struct *tty = tty_port_tty_get(&port->state->port); + unsigned int ch = 0, rsr = 0, fifocnt; + + if (!tty) { + dev_dbg(port->dev, "%s:tty is busy now", __func__); + return -EBUSY; + } + fifocnt = + ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; + while (fifocnt--) { + u8 flag = TTY_NORMAL; + ch = ltq_r8(port->membase + LTQ_ASC_RBUF); + rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) + & ASCSTATE_ANY) | UART_DUMMY_UER_RX; + tty_flip_buffer_push(tty); + port->icount.rx++; + + /* + * Note that the error handling code is + * out of the main execution path + */ + if (rsr & ASCSTATE_ANY) { + if (rsr & ASCSTATE_PE) { + port->icount.parity++; + ltq_w32_mask(0, ASCWHBSTATE_CLRPE, + port->membase + LTQ_ASC_WHBSTATE); + } else if (rsr & ASCSTATE_FE) { + port->icount.frame++; + ltq_w32_mask(0, ASCWHBSTATE_CLRFE, + port->membase + LTQ_ASC_WHBSTATE); + } + if (rsr & ASCSTATE_ROE) { + port->icount.overrun++; + ltq_w32_mask(0, ASCWHBSTATE_CLRROE, + port->membase + LTQ_ASC_WHBSTATE); + } + + rsr &= port->read_status_mask; + + if (rsr & ASCSTATE_PE) + flag = TTY_PARITY; + else if (rsr & ASCSTATE_FE) + flag = TTY_FRAME; + } + + if ((rsr & port->ignore_status_mask) == 0) + tty_insert_flip_char(tty, ch, flag); + + if (rsr & ASCSTATE_ROE) + /* + * Overrun is special, since it's reported + * immediately, and doesn't affect the current + * character + */ + tty_insert_flip_char(tty, 0, TTY_OVERRUN); + } + if (ch != 0) + tty_flip_buffer_push(tty); + tty_kref_put(tty); + return 0; +} + +static void +lqasc_tx_chars(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + if (uart_tx_stopped(port)) { + lqasc_stop_tx(port); + return; + } + + while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { + if (port->x_char) { + ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); + port->icount.tx++; + port->x_char = 0; + continue; + } + + if (uart_circ_empty(xmit)) + break; + + ltq_w8(port->state->xmit.buf[port->state->xmit.tail], + port->membase + LTQ_ASC_TBUF); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); +} + +static irqreturn_t +lqasc_tx_int(int irq, void *_port) +{ + unsigned long flags; + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); + ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); + spin_unlock_irqrestore(<q_asc_lock, flags); + lqasc_start_tx(port); + return IRQ_HANDLED; +} + +static irqreturn_t +lqasc_err_int(int irq, void *_port) +{ + unsigned long flags; + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); + /* clear any pending interrupts */ + ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | + ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); + spin_unlock_irqrestore(<q_asc_lock, flags); + return IRQ_HANDLED; +} + +static irqreturn_t +lqasc_rx_int(int irq, void *_port) +{ + unsigned long flags; + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); + ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); + lqasc_rx_chars(port); + spin_unlock_irqrestore(<q_asc_lock, flags); + return IRQ_HANDLED; +} + +static unsigned int +lqasc_tx_empty(struct uart_port *port) +{ + int status; + status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; + return status ? 0 : TIOCSER_TEMT; +} + +static unsigned int +lqasc_get_mctrl(struct uart_port *port) +{ + return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; +} + +static void +lqasc_set_mctrl(struct uart_port *port, u_int mctrl) +{ +} + +static void +lqasc_break_ctl(struct uart_port *port, int break_state) +{ +} + +static int +lqasc_startup(struct uart_port *port) +{ + struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); + int retval; + + port->uartclk = clk_get_rate(ltq_port->clk); + + ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + port->membase + LTQ_ASC_CLC); + + ltq_w32(0, port->membase + LTQ_ASC_PISEL); + ltq_w32( + ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | + ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); + ltq_w32( + ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) + | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); + /* make sure other settings are written to hardware before + * setting enable bits + */ + wmb(); + ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | + ASCCON_ROEN, port->membase + LTQ_ASC_CON); + + retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, + IRQF_DISABLED, "asc_tx", port); + if (retval) { + pr_err("failed to request lqasc_tx_int\n"); + return retval; + } + + retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, + IRQF_DISABLED, "asc_rx", port); + if (retval) { + pr_err("failed to request lqasc_rx_int\n"); + goto err1; + } + + retval = request_irq(ltq_port->err_irq, lqasc_err_int, + IRQF_DISABLED, "asc_err", port); + if (retval) { + pr_err("failed to request lqasc_err_int\n"); + goto err2; + } + + ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, + port->membase + LTQ_ASC_IRNREN); + return 0; + +err2: + free_irq(ltq_port->rx_irq, port); +err1: + free_irq(ltq_port->tx_irq, port); + return retval; +} + +static void +lqasc_shutdown(struct uart_port *port) +{ + struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); + free_irq(ltq_port->tx_irq, port); + free_irq(ltq_port->rx_irq, port); + free_irq(ltq_port->err_irq, port); + + ltq_w32(0, port->membase + LTQ_ASC_CON); + ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); + ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); +} + +static void +lqasc_set_termios(struct uart_port *port, + struct ktermios *new, struct ktermios *old) +{ + unsigned int cflag; + unsigned int iflag; + unsigned int divisor; + unsigned int baud; + unsigned int con = 0; + unsigned long flags; + + cflag = new->c_cflag; + iflag = new->c_iflag; + + switch (cflag & CSIZE) { + case CS7: + con = ASCCON_M_7ASYNC; + break; + + case CS5: + case CS6: + default: + new->c_cflag &= ~ CSIZE; + new->c_cflag |= CS8; + con = ASCCON_M_8ASYNC; + break; + } + + cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ + + if (cflag & CSTOPB) + con |= ASCCON_STP; + + if (cflag & PARENB) { + if (!(cflag & PARODD)) + con &= ~ASCCON_ODD; + else + con |= ASCCON_ODD; + } + + port->read_status_mask = ASCSTATE_ROE; + if (iflag & INPCK) + port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; + + port->ignore_status_mask = 0; + if (iflag & IGNPAR) + port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; + + if (iflag & IGNBRK) { + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (iflag & IGNPAR) + port->ignore_status_mask |= ASCSTATE_ROE; + } + + if ((cflag & CREAD) == 0) + port->ignore_status_mask |= UART_DUMMY_UER_RX; + + /* set error signals - framing, parity and overrun, enable receiver */ + con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; + + spin_lock_irqsave(<q_asc_lock, flags); + + /* set up CON */ + ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); + + /* Set baud rate - take a divider of 2 into account */ + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); + divisor = uart_get_divisor(port, baud); + divisor = divisor / 2 - 1; + + /* disable the baudrate generator */ + ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); + + /* make sure the fractional divider is off */ + ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); + + /* set up to use divisor of 2 */ + ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); + + /* now we can write the new baudrate into the register */ + ltq_w32(divisor, port->membase + LTQ_ASC_BG); + + /* turn the baudrate generator back on */ + ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); + + /* enable rx */ + ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); + + spin_unlock_irqrestore(<q_asc_lock, flags); + + /* Don't rewrite B0 */ + if (tty_termios_baud_rate(new)) + tty_termios_encode_baud_rate(new, baud, baud); +} + +static const char* +lqasc_type(struct uart_port *port) +{ + if (port->type == PORT_LTQ_ASC) + return DRVNAME; + else + return NULL; +} + +static void +lqasc_release_port(struct uart_port *port) +{ + if (port->flags & UPF_IOREMAP) { + iounmap(port->membase); + port->membase = NULL; + } +} + +static int +lqasc_request_port(struct uart_port *port) +{ + struct platform_device *pdev = to_platform_device(port->dev); + struct resource *res; + int size; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "cannot obtain I/O memory region"); + return -ENODEV; + } + size = resource_size(res); + + res = devm_request_mem_region(&pdev->dev, res->start, + size, dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "cannot request I/O memory region"); + return -EBUSY; + } + + if (port->flags & UPF_IOREMAP) { + port->membase = devm_ioremap_nocache(&pdev->dev, + port->mapbase, size); + if (port->membase == NULL) + return -ENOMEM; + } + return 0; +} + +static void +lqasc_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) { + port->type = PORT_LTQ_ASC; + lqasc_request_port(port); + } +} + +static int +lqasc_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) + ret = -EINVAL; + if (ser->irq < 0 || ser->irq >= NR_IRQS) + ret = -EINVAL; + if (ser->baud_base < 9600) + ret = -EINVAL; + return ret; +} + +static struct uart_ops lqasc_pops = { + .tx_empty = lqasc_tx_empty, + .set_mctrl = lqasc_set_mctrl, + .get_mctrl = lqasc_get_mctrl, + .stop_tx = lqasc_stop_tx, + .start_tx = lqasc_start_tx, + .stop_rx = lqasc_stop_rx, + .enable_ms = lqasc_enable_ms, + .break_ctl = lqasc_break_ctl, + .startup = lqasc_startup, + .shutdown = lqasc_shutdown, + .set_termios = lqasc_set_termios, + .type = lqasc_type, + .release_port = lqasc_release_port, + .request_port = lqasc_request_port, + .config_port = lqasc_config_port, + .verify_port = lqasc_verify_port, +}; + +static void +lqasc_console_putchar(struct uart_port *port, int ch) +{ + int fifofree; + + if (!port->membase) + return; + + do { + fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) + & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; + } while (fifofree == 0); + ltq_w8(ch, port->membase + LTQ_ASC_TBUF); +} + + +static void +lqasc_console_write(struct console *co, const char *s, u_int count) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + unsigned long flags; + + if (co->index >= MAXPORTS) + return; + + ltq_port = lqasc_port[co->index]; + if (!ltq_port) + return; + + port = <q_port->port; + + spin_lock_irqsave(<q_asc_lock, flags); + uart_console_write(port, s, count, lqasc_console_putchar); + spin_unlock_irqrestore(<q_asc_lock, flags); +} + +static int __init +lqasc_console_setup(struct console *co, char *options) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + if (co->index >= MAXPORTS) + return -ENODEV; + + ltq_port = lqasc_port[co->index]; + if (!ltq_port) + return -ENODEV; + + port = <q_port->port; + + port->uartclk = clk_get_rate(ltq_port->clk); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console lqasc_console = { + .name = "ttyLTQ", + .write = lqasc_console_write, + .device = uart_console_device, + .setup = lqasc_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &lqasc_reg, +}; + +static int __init +lqasc_console_init(void) +{ + register_console(&lqasc_console); + return 0; +} +console_initcall(lqasc_console_init); + +static struct uart_driver lqasc_reg = { + .owner = THIS_MODULE, + .driver_name = DRVNAME, + .dev_name = "ttyLTQ", + .major = 0, + .minor = 0, + .nr = MAXPORTS, + .cons = &lqasc_console, +}; + +static int __init +lqasc_probe(struct platform_device *pdev) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + struct resource *mmres, *irqres; + int tx_irq, rx_irq, err_irq; + struct clk *clk; + int ret; + + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!mmres || !irqres) + return -ENODEV; + + if (pdev->id >= MAXPORTS) + return -EBUSY; + + if (lqasc_port[pdev->id] != NULL) + return -EBUSY; + + clk = clk_get(&pdev->dev, "fpi"); + if (IS_ERR(clk)) { + pr_err("failed to get fpi clk\n"); + return -ENOENT; + } + + tx_irq = platform_get_irq_byname(pdev, "tx"); + rx_irq = platform_get_irq_byname(pdev, "rx"); + err_irq = platform_get_irq_byname(pdev, "err"); + if ((tx_irq < 0) | (rx_irq < 0) | (err_irq < 0)) + return -ENODEV; + + ltq_port = kzalloc(sizeof(struct ltq_uart_port), GFP_KERNEL); + if (!ltq_port) + return -ENOMEM; + + port = <q_port->port; + + port->iotype = SERIAL_IO_MEM; + port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP; + port->ops = &lqasc_pops; + port->fifosize = 16; + port->type = PORT_LTQ_ASC, + port->line = pdev->id; + port->dev = &pdev->dev; + + port->irq = tx_irq; /* unused, just to be backward-compatibe */ + port->mapbase = mmres->start; + + ltq_port->clk = clk; + + ltq_port->tx_irq = tx_irq; + ltq_port->rx_irq = rx_irq; + ltq_port->err_irq = err_irq; + + lqasc_port[pdev->id] = ltq_port; + platform_set_drvdata(pdev, ltq_port); + + ret = uart_add_one_port(&lqasc_reg, port); + + return ret; +} + +static struct platform_driver lqasc_driver = { + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, +}; + +int __init +init_lqasc(void) +{ + int ret; + + ret = uart_register_driver(&lqasc_reg); + if (ret != 0) + return ret; + + ret = platform_driver_probe(&lqasc_driver, lqasc_probe); + if (ret != 0) + uart_unregister_driver(&lqasc_reg); + + return ret; +} + +module_init(init_lqasc); + +MODULE_DESCRIPTION("Lantiq serial port driver"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 From blogic@openwrt.org Tue Apr 5 14:14:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 14:14:06 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:56034 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491753Ab1DEMOA (ORCPT ); Tue, 5 Apr 2011 14:14:00 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: [PATCH V6] MIPS: lantiq: add NOR flash support Date: Tue, 5 Apr 2011 14:15:20 +0200 Message-Id: <1302005720-8508-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29685 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver/map for NOR devices attached to the SoC via the External Bus Unit (EBU). Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: David Woodhouse Cc: Daniel Schwierzeck Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Changes in V2 * handle the endianess bug inside the map code and not in the generic cfi code * remove the addr swizzle patch Changes in V3 * whitespace * change __iomem void to void __iomem Changes in V4 * fixes a checkpatch.pl bug, the second is a false positive * whitespace cleanups * remove unused typecasts * cleanup ltq_copy_from and ltq_copy_to Changes in V6 * cleanup/add comments * fix line breaks * properly handle return code of add_mtd_partitions() * use pr_err instead of printk This patch should be merged via the MIPS tree --- drivers/mtd/maps/Kconfig | 9 ++ drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq.c | 187 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/maps/lantiq.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 44b1f46..83376d3 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -260,6 +260,15 @@ config MTD_BCM963XX Support for parsing CFE image tag and creating MTD partitions on Broadcom BCM63xx boards. +config MTD_LANTIQ + bool "Lantiq SoC NOR support" + depends on LANTIQ + select MTD_PARTITIONS + help + Lantiq SoCs have a EBU (External Bus Unit). This IP allows to attach + a number of different peripherals to the SoC. This driver adds + support for NOR chips to be added. + config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 08533bd..0db4ba3 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o +obj-$(CONFIG_MTD_LANTIQ) += lantiq.o diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c new file mode 100644 index 0000000..e3db055 --- /dev/null +++ b/drivers/mtd/maps/lantiq.c @@ -0,0 +1,187 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * The NOR flash is connected to the same external bus unit (EBU) as PCI. + * To make PCI work we need to enable the endianess swapping for the address + * written to the EBU. This endianess swapping works for PCI correctly but + * fails for attached NOR devices. To workaround this we need to use a complex + * map. The workaround involves swapping all addresses whilste probing the chip. + * Once probing is complete we stop swapping the addresses but swizzle the + * unlock addresses to ensure that access to the NOR device works correctly. + */ + +static int ltq_mtd_probing; + +static map_word +ltq_read16(struct map_info *map, unsigned long adr) +{ + unsigned long flags; + map_word temp; + + if (ltq_mtd_probing) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + temp.x[0] = *((__u16 *)(map->virt + adr)); + spin_unlock_irqrestore(&ebu_lock, flags); + return temp; +} + +static void +ltq_write16(struct map_info *map, map_word d, unsigned long adr) +{ + unsigned long flags; + + if (ltq_mtd_probing) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + *((__u16 *)(map->virt + adr)) = d.x[0]; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +/* + * The following 2 functions copy data between iomem and a cached memory + * section. As memcpy() makes use of pre-fetching we cannot use it here. + * The normal alternative of using memcpy_{to,from}io also makes use of + * memcpy() on MIPS so it is not applicable either. We are therefore stuck + * with having to use our own loop. + */ +static void +ltq_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + unsigned char *f = (unsigned char *) (map->virt + from); + unsigned char *t = (unsigned char *) to; + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + while (len--) + *t++ = *f++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static void +ltq_copy_to(struct map_info *map, unsigned long to, + const void *from, ssize_t len) +{ + unsigned char *f = (unsigned char *) from; + unsigned char *t = (unsigned char *) (map->virt + to); + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + while (len--) + *t++ = *f++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static const char const *part_probe_types[] = { "cmdlinepart", NULL }; + +static struct map_info ltq_map = { + .name = "ltq_nor", + .bankwidth = 2, + .read = ltq_read16, + .write = ltq_write16, + .copy_from = ltq_copy_from, + .copy_to = ltq_copy_to, +}; + +static int __init +ltq_mtd_probe(struct platform_device *pdev) +{ + struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); + struct mtd_info *ltq_mtd = NULL; + struct mtd_partition *parts = NULL; + struct resource *res; + int nr_parts = 0; + struct cfi_private *cfi; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request mem resource"); + return -EBUSY; + } + + ltq_map.phys = res->start; + ltq_map.size = resource_size(res); + ltq_map.virt = devm_ioremap_nocache(&pdev->dev, ltq_map.phys, + ltq_map.size); + if (!ltq_map.virt) { + dev_err(&pdev->dev, "failed to ioremap!\n"); + return -EIO; + } + + ltq_mtd_probing = 1; + ltq_mtd = do_map_probe("cfi_probe", <q_map); + ltq_mtd_probing = 0; + if (!ltq_mtd) { + iounmap(ltq_map.virt); + dev_err(&pdev->dev, "probing failed\n"); + return -ENXIO; + } + ltq_mtd->owner = THIS_MODULE; + + cfi = ltq_map.fldrv_priv; + cfi->addr_unlock1 ^= 1; + cfi->addr_unlock2 ^= 1; + + nr_parts = parse_mtd_partitions(ltq_mtd, part_probe_types, &parts, 0); + if (nr_parts > 0) { + dev_info(&pdev->dev, + "using %d partitions from cmdline", nr_parts); + } else { + nr_parts = ltq_mtd_data->nr_parts; + parts = ltq_mtd_data->parts; + } + + return add_mtd_partitions(ltq_mtd, parts, nr_parts); +} + +static struct platform_driver ltq_mtd_driver = { + .driver = { + .name = "ltq_nor", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_mtd(void) +{ + int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); + + if (ret) + pr_err(KERN_INFO "ltq_nor: error registering platfom driver"); + return ret; +} + +module_init(init_ltq_mtd); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC NOR"); -- 1.7.2.3 From dedekind1@gmail.com Tue Apr 5 14:18:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 14:18:39 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:36507 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491755Ab1DEMSg (ORCPT ); Tue, 5 Apr 2011 14:18:36 +0200 Received: by ewy3 with SMTP id 3so93030ewy.36 for ; Tue, 05 Apr 2011 05:18:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=RGHgL3kQDTp2+D+kmn3Zx/UboP5IlQeXckXgKk3Lv0M=; b=r+wsWTwCJEhGHzHGnmZZLx5GvPji8stZj4aIFw0NSLk/mMuetvfvf/x/TncdJQ3FII bC1pS0zBvcqtvAe6McSn/S9N5V6v638p4NFH74qORevGQmjArj29MhbUQC5uUFSkcueb xB/ar+3Z4Dy+4vCcRPKAsy4ERdyufoirwJja0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; b=Bwn3AwzjlxWHeYc9mR23Gdfo4HoSPkdhD4UCMk/41sERd/PZNjLoUV1mUXeOaHi9Un oYdXe/40Blt1jsebkJhjoUHLSbhClEdQuIXsfLbyvyrOPygRaTqdqsGo2ZiCqbbZ8S7o L6IThc94dbOQdyAYUitwQu6wWXpm9JC14brWY= Received: by 10.213.100.197 with SMTP id z5mr2100451ebn.111.1302005910655; Tue, 05 Apr 2011 05:18:30 -0700 (PDT) Received: from ?IPv6:::1? (shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id q53sm3953987eeh.18.2011.04.05.05.18.28 (version=SSLv3 cipher=OTHER); Tue, 05 Apr 2011 05:18:29 -0700 (PDT) Subject: Re: [PATCH V6] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <1302005720-8508-1-git-send-email-blogic@openwrt.org> References: <1302005720-8508-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset="UTF-8" Date: Tue, 05 Apr 2011 15:15:51 +0300 Message-ID: <1302005751.2760.116.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29686 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2011-04-05 at 14:15 +0200, John Crispin wrote: > +int __init > +init_ltq_mtd(void) > +{ > + int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); > + > + if (ret) > + pr_err(KERN_INFO "ltq_nor: error registering platfom driver"); Sorry, but pr_err is defined as follows: #define pr_err(fmt, ...) \ printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) You should not add KERN_INFO. -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From blogic@openwrt.org Tue Apr 5 14:20:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 14:20:06 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:54497 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491755Ab1DEMUE (ORCPT ); Tue, 5 Apr 2011 14:20:04 +0200 Message-ID: <4D9B0951.3030206@openwrt.org> Date: Tue, 05 Apr 2011 14:21:37 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: dedekind1@gmail.com CC: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse Subject: Re: [PATCH V6] MIPS: lantiq: add NOR flash support References: <1302005720-8508-1-git-send-email-blogic@openwrt.org> <1302005751.2760.116.camel@localhost> In-Reply-To: <1302005751.2760.116.camel@localhost> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29687 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips > Sorry, but pr_err is defined as follows: > > #define pr_err(fmt, ...) \ > printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) > > You should not add KERN_INFO. > > Hi, i missed that one :( let me resend a fixed version sorry, John From ralf@linux-mips.org Tue Apr 5 14:21:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 14:21:40 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:33443 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491778Ab1DEMVh (ORCPT ); Tue, 5 Apr 2011 14:21:37 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p35CLWHD009222; Tue, 5 Apr 2011 14:21:32 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p35CLSXd009215; Tue, 5 Apr 2011 14:21:28 +0200 Date: Tue, 5 Apr 2011 14:21:28 +0200 From: Ralf Baechle To: "wilbur.chan" Cc: Linux MIPS Mailing List , "Jayachandran C." Subject: Re: System suffers frequent TLB miss Message-ID: <20110405122128.GB31210@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29688 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Apr 03, 2011 at 11:49:13AM +0800, wilbur.chan wrote: > We have a system running on mips64 xlr 732. Our major application > process is binded on CPU5, > > In order to reduce the tlb miss of our major process, we took the > following steps: What page size are you using? If you're still using 4K pages, try switching to 16K or even 64K pages. You also may want to look into using hugetlbfs. Ralf From blogic@openwrt.org Tue Apr 5 14:32:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 14:32:42 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:47001 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491171Ab1DEMcf (ORCPT ); Tue, 5 Apr 2011 14:32:35 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: [PATCH V7] MIPS: lantiq: add NOR flash support Date: Tue, 5 Apr 2011 14:33:50 +0200 Message-Id: <1302006830-10345-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29689 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver/map for NOR devices attached to the SoC via the External Bus Unit (EBU). Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: David Woodhouse Cc: Daniel Schwierzeck Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org --- Changes in V2 * handle the endianess bug inside the map code and not in the generic cfi code * remove the addr swizzle patch Changes in V3 * whitespace * change __iomem void to void __iomem Changes in V4 * fixes a checkpatch.pl bug, the second is a false positive * whitespace cleanups * remove unused typecasts * cleanup ltq_copy_from and ltq_copy_to Changes in V6 * cleanup/add comments * fix line breaks * properly handle return code of add_mtd_partitions() * use pr_err instead of printk Changes in V7 * remove bogus KERN_INFO from pr_err() call This patch should be merged via the MIPS tree drivers/mtd/maps/Kconfig | 9 ++ drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq.c | 187 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/maps/lantiq.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 44b1f46..83376d3 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -260,6 +260,15 @@ config MTD_BCM963XX Support for parsing CFE image tag and creating MTD partitions on Broadcom BCM63xx boards. +config MTD_LANTIQ + bool "Lantiq SoC NOR support" + depends on LANTIQ + select MTD_PARTITIONS + help + Lantiq SoCs have a EBU (External Bus Unit). This IP allows to attach + a number of different peripherals to the SoC. This driver adds + support for NOR chips to be added. + config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 08533bd..0db4ba3 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o +obj-$(CONFIG_MTD_LANTIQ) += lantiq.o diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c new file mode 100644 index 0000000..588e873 --- /dev/null +++ b/drivers/mtd/maps/lantiq.c @@ -0,0 +1,187 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * The NOR flash is connected to the same external bus unit (EBU) as PCI. + * To make PCI work we need to enable the endianess swapping for the address + * written to the EBU. This endianess swapping works for PCI correctly but + * fails for attached NOR devices. To workaround this we need to use a complex + * map. The workaround involves swapping all addresses whilste probing the chip. + * Once probing is complete we stop swapping the addresses but swizzle the + * unlock addresses to ensure that access to the NOR device works correctly. + */ + +static int ltq_mtd_probing; + +static map_word +ltq_read16(struct map_info *map, unsigned long adr) +{ + unsigned long flags; + map_word temp; + + if (ltq_mtd_probing) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + temp.x[0] = *((__u16 *)(map->virt + adr)); + spin_unlock_irqrestore(&ebu_lock, flags); + return temp; +} + +static void +ltq_write16(struct map_info *map, map_word d, unsigned long adr) +{ + unsigned long flags; + + if (ltq_mtd_probing) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + *((__u16 *)(map->virt + adr)) = d.x[0]; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +/* + * The following 2 functions copy data between iomem and a cached memory + * section. As memcpy() makes use of pre-fetching we cannot use it here. + * The normal alternative of using memcpy_{to,from}io also makes use of + * memcpy() on MIPS so it is not applicable either. We are therefore stuck + * with having to use our own loop. + */ +static void +ltq_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + unsigned char *f = (unsigned char *) (map->virt + from); + unsigned char *t = (unsigned char *) to; + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + while (len--) + *t++ = *f++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static void +ltq_copy_to(struct map_info *map, unsigned long to, + const void *from, ssize_t len) +{ + unsigned char *f = (unsigned char *) from; + unsigned char *t = (unsigned char *) (map->virt + to); + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + while (len--) + *t++ = *f++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static const char const *part_probe_types[] = { "cmdlinepart", NULL }; + +static struct map_info ltq_map = { + .name = "ltq_nor", + .bankwidth = 2, + .read = ltq_read16, + .write = ltq_write16, + .copy_from = ltq_copy_from, + .copy_to = ltq_copy_to, +}; + +static int __init +ltq_mtd_probe(struct platform_device *pdev) +{ + struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); + struct mtd_info *ltq_mtd = NULL; + struct mtd_partition *parts = NULL; + struct resource *res; + int nr_parts = 0; + struct cfi_private *cfi; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request mem resource"); + return -EBUSY; + } + + ltq_map.phys = res->start; + ltq_map.size = resource_size(res); + ltq_map.virt = devm_ioremap_nocache(&pdev->dev, ltq_map.phys, + ltq_map.size); + if (!ltq_map.virt) { + dev_err(&pdev->dev, "failed to ioremap!\n"); + return -EIO; + } + + ltq_mtd_probing = 1; + ltq_mtd = do_map_probe("cfi_probe", <q_map); + ltq_mtd_probing = 0; + if (!ltq_mtd) { + iounmap(ltq_map.virt); + dev_err(&pdev->dev, "probing failed\n"); + return -ENXIO; + } + ltq_mtd->owner = THIS_MODULE; + + cfi = ltq_map.fldrv_priv; + cfi->addr_unlock1 ^= 1; + cfi->addr_unlock2 ^= 1; + + nr_parts = parse_mtd_partitions(ltq_mtd, part_probe_types, &parts, 0); + if (nr_parts > 0) { + dev_info(&pdev->dev, + "using %d partitions from cmdline", nr_parts); + } else { + nr_parts = ltq_mtd_data->nr_parts; + parts = ltq_mtd_data->parts; + } + + return add_mtd_partitions(ltq_mtd, parts, nr_parts); +} + +static struct platform_driver ltq_mtd_driver = { + .driver = { + .name = "ltq_nor", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_mtd(void) +{ + int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); + + if (ret) + pr_err("ltq_nor: error registering platfom driver"); + return ret; +} + +module_init(init_ltq_mtd); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC NOR"); -- 1.7.2.3 From dedekind1@gmail.com Tue Apr 5 14:39:21 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 14:39:24 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:38057 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491791Ab1DEMjV (ORCPT ); Tue, 5 Apr 2011 14:39:21 +0200 Received: by wwb17 with SMTP id 17so370941wwb.24 for ; Tue, 05 Apr 2011 05:39:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=2xYNuAScJ9PM9Whs4G+CHX2yGB1Vd8TqRecRSqMDsWw=; b=n9otRSjh2yl0fHkWIRNUFSuLUb1Ams+eOmkc1BuxeN34ispwp0wfxO8c1PDvu4zXKp OxpVDyi+5Nb4b2fXfLIyHUT5gujK7E9pClIsbQF8h3evBZ3bsD/QFiIJUHYjrDlHkAx1 pzxPPzXix1xPqXPUVLf1mNVmvQlaQnq+kDWlo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; b=F2IyGSubHLmdW1oubxnHBiIC7UNMwKMJjH1PnYQlcuC6d8w/Ar5+BZl1I4omIBzSW4 q/PRCJXljYKmrX/w0ZjACw3JddleCfHwmS3Bklb75BOiLDvUiXuZ9rilBNdmbs4EkNp6 FOgcuFcBrFcUlZpUqV8VLadpSC1Tj0i8Qe9H0= Received: by 10.227.169.77 with SMTP id x13mr8499915wby.151.1302007154856; Tue, 05 Apr 2011 05:39:14 -0700 (PDT) Received: from ?IPv6:::1? (shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id y29sm3535093wbd.38.2011.04.05.05.39.13 (version=SSLv3 cipher=OTHER); Tue, 05 Apr 2011 05:39:14 -0700 (PDT) Subject: Re: [PATCH V7] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <1302006830-10345-1-git-send-email-blogic@openwrt.org> References: <1302006830-10345-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset="UTF-8" Date: Tue, 05 Apr 2011 15:36:35 +0300 Message-ID: <1302006995.2760.120.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29690 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2011-04-05 at 14:33 +0200, John Crispin wrote: > +#include > +#include > + > +/* > + * The NOR flash is connected to the same external bus unit (EBU) as PCI. > + * To make PCI work we need to enable the endianess swapping for the address > + * written to the EBU. This endianess swapping works for PCI correctly but > + * fails for attached NOR devices. To workaround this we need to use a complex > + * map. The workaround involves swapping all addresses whilste probing the chip. > + * Once probing is complete we stop swapping the addresses but swizzle the > + * unlock addresses to ensure that access to the NOR device works correctly. > + */ > + > +static int ltq_mtd_probing; Disclamer: I do not really understand the PCI/swapping issue, even though you wrote a comment about this, but still.... ... I'm worried about this global variable. If you have multiple instances of such NOR flash, then you theoretically may have a situation when one of them is being probed, while another is being used for real. And this single global switch will break the one which is used for real. IOW, the right solution would be to have per-chip flag, not a global flag. -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From blogic@openwrt.org Tue Apr 5 14:56:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 14:56:13 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:44808 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491171Ab1DEM4K (ORCPT ); Tue, 5 Apr 2011 14:56:10 +0200 Message-ID: <4D9B11C5.3030308@openwrt.org> Date: Tue, 05 Apr 2011 14:57:41 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: dedekind1@gmail.com CC: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse Subject: Re: [PATCH V7] MIPS: lantiq: add NOR flash support References: <1302006830-10345-1-git-send-email-blogic@openwrt.org> <1302006995.2760.120.camel@localhost> In-Reply-To: <1302006995.2760.120.camel@localhost> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29691 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips >> + >> +static int ltq_mtd_probing; >> > ... I'm worried about this global variable. If you have multiple > instances of such NOR flash, then you theoretically may have a situation > when one of them is being probed, while another is being used for real. > And this single global switch will break the one which is used for real. > > IOW, the right solution would be to have per-chip flag, not a global > flag. > > Hi, we could dynamically allocate the instance of struct map_info and then use map_priv_1 to indicate whether the device is probing or not. this would avoid using a global variable John From dedekind1@gmail.com Tue Apr 5 15:00:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 15:00:54 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:62199 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491171Ab1DENAv (ORCPT ); Tue, 5 Apr 2011 15:00:51 +0200 Received: by bwz1 with SMTP id 1so318312bwz.36 for ; Tue, 05 Apr 2011 06:00:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=SJpkY1fQtx8wcehJXAEfOQcnNAz/OEkUkK2T/Wpp0WA=; b=wZKhIBwjevF5rHEobZtp6GjXH/ZXR+jlRNeFaFD4QIucpL3pHt563pWw3JWApKdADI w5/j8mMkO7mNdQwILLHZPXtEchweiIjnOUxHH4N8ILAERWZ/SpqiIxpaTvU9zsCOinhU ZSUvDGKxHv5Wl5nrlL1VQFnt+2MBJ3EjCww6s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; b=F4zE06evtq1vxpPQoTudC+8bhXVkKjEiefFDahz0lSZrxNppZqpFxlTsWs+jyZA0JE 3+a6tki4Vh/QY4iU9gBFmWTkrrk5lJ1qB4djw9kwsDoPcpYXqHzvuaBLqKCV2xcwD4WL 2TCcGvxSY6V5Mr2BubwGsxf4uDTzKgeYQARps= Received: by 10.204.57.135 with SMTP id c7mr7261738bkh.88.1302008444113; Tue, 05 Apr 2011 06:00:44 -0700 (PDT) Received: from ?IPv6:::1? (shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id k5sm3743870bku.4.2011.04.05.06.00.42 (version=SSLv3 cipher=OTHER); Tue, 05 Apr 2011 06:00:43 -0700 (PDT) Subject: Re: [PATCH V7] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <4D9B11C5.3030308@openwrt.org> References: <1302006830-10345-1-git-send-email-blogic@openwrt.org> <1302006995.2760.120.camel@localhost> <4D9B11C5.3030308@openwrt.org> Content-Type: text/plain; charset="UTF-8" Date: Tue, 05 Apr 2011 15:58:04 +0300 Message-ID: <1302008284.2760.129.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29692 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2011-04-05 at 14:57 +0200, John Crispin wrote: > we could dynamically allocate the instance of struct map_info and then > use map_priv_1 to indicate whether the device is probing or not. Yeah, may be you could indeed use map_priv_1 instead of the global variable already now? -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From blogic@openwrt.org Tue Apr 5 15:05:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 15:05:10 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:47874 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491753Ab1DENFG (ORCPT ); Tue, 5 Apr 2011 15:05:06 +0200 Message-ID: <4D9B13E0.9000202@openwrt.org> Date: Tue, 05 Apr 2011 15:06:40 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: dedekind1@gmail.com CC: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse Subject: Re: [PATCH V7] MIPS: lantiq: add NOR flash support References: <1302006830-10345-1-git-send-email-blogic@openwrt.org> <1302006995.2760.120.camel@localhost> <4D9B11C5.3030308@openwrt.org> <1302008284.2760.129.camel@localhost> In-Reply-To: <1302008284.2760.129.camel@localhost> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29693 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips On 05/04/11 14:58, Artem Bityutskiy wrote: > On Tue, 2011-04-05 at 14:57 +0200, John Crispin wrote: > >> we could dynamically allocate the instance of struct map_info and then >> use map_priv_1 to indicate whether the device is probing or not. >> > Yeah, may be you could indeed use map_priv_1 instead of the global > variable already now? > > Hi, ok, let me add it to the patch ... thanks, John From alan@lxorguk.ukuu.org.uk Tue Apr 5 15:54:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 15:54:53 +0200 (CEST) Received: from earthlight.etchedpixels.co.uk ([81.2.110.250]:41700 "EHLO www.etchedpixels.co.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491768Ab1DENyp (ORCPT ); Tue, 5 Apr 2011 15:54:45 +0200 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by www.etchedpixels.co.uk (8.14.4/8.14.4) with ESMTP id p35DtJuC018447; Tue, 5 Apr 2011 14:55:20 +0100 Date: Tue, 5 Apr 2011 14:55:19 +0100 From: Alan Cox To: John Crispin Cc: Ralf Baechle , Ralph Hempel , Felix Fietkau , linux-mips@linux-mips.org, linux-serial@vger.kernel.org Subject: Re: [PATCH V6] MIPS: lantiq: add serial port support Message-ID: <20110405145519.5befce51@lxorguk.ukuu.org.uk> In-Reply-To: <1302005458-8423-1-git-send-email-blogic@openwrt.org> References: <1302005458-8423-1-git-send-email-blogic@openwrt.org> X-Mailer: Claws Mail 3.7.8 (GTK+ 2.22.0; x86_64-redhat-linux-gnu) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAFVBMVEWysKsSBQMIAwIZCwj///8wIhxoRDXH9QHCAAABeUlEQVQ4jaXTvW7DIBAAYCQTzz2hdq+rdg494ZmBeE5KYHZjm/d/hJ6NfzBJpp5kRb5PHJwvMPMk2L9As5Y9AmYRBL+HAyJKeOU5aHRhsAAvORQ+UEgAvgddj/lwAXndw2laEDqA4x6KEBhjYRCg9tBFCOuJFxg2OKegbWjbsRTk8PPhKPD7HcRxB7cqhgBRp9Dcqs+B8v4CQvFdqeot3Kov6hBUn0AJitrzY+sgUuiA8i0r7+B3AfqKcN6t8M6HtqQ+AOoELCikgQSbgabKaJW3kn5lBs47JSGDhhLKDUh1UMipwwinMYPTBuIBjEclSaGZUk9hDlTb5sUTYN2SFFQuPe4Gox1X0FZOufjgBiV1Vls7b+GvK3SU4wfmcGo9rPPQzgIabfj4TYQo15k3bTHX9RIw/kniir5YbtJF4jkFG+dsDK1IgE413zAthU/vR2HVMmFUPIHTvF6jWCpFaGw/A3qWgnbxpSm9MSmY5b3pM1gvNc/gQfwBsGwF0VCtxZgAAAAASUVORK5CYII= Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29694 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk X-list: linux-mips Acked-by: Alan Cox From blogic@openwrt.org Tue Apr 5 15:58:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 15:58:23 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:55602 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491778Ab1DEN6Q (ORCPT ); Tue, 5 Apr 2011 15:58:16 +0200 Message-ID: <4D9B2054.8090305@openwrt.org> Date: Tue, 05 Apr 2011 15:59:48 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: Alan Cox CC: Ralf Baechle , Ralph Hempel , Felix Fietkau , linux-mips@linux-mips.org, linux-serial@vger.kernel.org Subject: Re: [PATCH V6] MIPS: lantiq: add serial port support References: <1302005458-8423-1-git-send-email-blogic@openwrt.org> <20110405145519.5befce51@lxorguk.ukuu.org.uk> In-Reply-To: <20110405145519.5befce51@lxorguk.ukuu.org.uk> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29695 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips On 05/04/11 15:55, Alan Cox wrote: > Acked-by: Alan Cox > > Hi Alan, thanks alot :) John From blogic@openwrt.org Tue Apr 5 16:18:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 16:18:34 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:56908 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491768Ab1DEOS0 (ORCPT ); Tue, 5 Apr 2011 16:18:26 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: [PATCH V8] MIPS: lantiq: add NOR flash support Date: Tue, 5 Apr 2011 16:19:52 +0200 Message-Id: <1302013192-8854-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29696 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver/map for NOR devices attached to the SoC via the External Bus Unit (EBU). Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: David Woodhouse Cc: Daniel Schwierzeck Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org --- Changes in V2 * handle the endianess bug inside the map code and not in the generic cfi code * remove the addr swizzle patch Changes in V3 * whitespace * change __iomem void to void __iomem Changes in V4 * fixes a checkpatch.pl bug, the second is a false positive * whitespace cleanups * remove unused typecasts * cleanup ltq_copy_from and ltq_copy_to Changes in V6 * cleanup/add comments * fix line breaks * properly handle return code of add_mtd_partitions() * use pr_err instead of printk Changes in V7 * remove bogus KERN_INFO from pr_err() call Changes in V8 * dynamically allocate the instance of map_info allowing the use of .addr_unlock1 for indication of the probing state, thus eliminating the need for a global variable This patch should be merged via the MIPS tree drivers/mtd/maps/Kconfig | 9 ++ drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq.c | 197 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/maps/lantiq.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 44b1f46..83376d3 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -260,6 +260,15 @@ config MTD_BCM963XX Support for parsing CFE image tag and creating MTD partitions on Broadcom BCM63xx boards. +config MTD_LANTIQ + bool "Lantiq SoC NOR support" + depends on LANTIQ + select MTD_PARTITIONS + help + Lantiq SoCs have a EBU (External Bus Unit). This IP allows to attach + a number of different peripherals to the SoC. This driver adds + support for NOR chips to be added. + config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 08533bd..0db4ba3 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o +obj-$(CONFIG_MTD_LANTIQ) += lantiq.o diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c new file mode 100644 index 0000000..4f8c320 --- /dev/null +++ b/drivers/mtd/maps/lantiq.c @@ -0,0 +1,197 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * The NOR flash is connected to the same external bus unit (EBU) as PCI. + * To make PCI work we need to enable the endianess swapping for the address + * written to the EBU. This endianess swapping works for PCI correctly but + * fails for attached NOR devices. To workaround this we need to use a complex + * map. The workaround involves swapping all addresses whilste probing the chip. + * Once probing is complete we stop swapping the addresses but swizzle the + * unlock addresses to ensure that access to the NOR device works correctly. + */ + +enum ltq_nor_state { + LTQ_NOR_PROBING, + LTQ_NOR_NORMAL +}; + +static char ltq_map_name[] = "ltq_nor"; + +static map_word +ltq_read16(struct map_info *map, unsigned long adr) +{ + unsigned long flags; + map_word temp; + + if (map->map_priv_1 == LTQ_NOR_PROBING) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + temp.x[0] = *((__u16 *)(map->virt + adr)); + spin_unlock_irqrestore(&ebu_lock, flags); + return temp; +} + +static void +ltq_write16(struct map_info *map, map_word d, unsigned long adr) +{ + unsigned long flags; + + if (map->map_priv_1 == LTQ_NOR_PROBING) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + *((__u16 *)(map->virt + adr)) = d.x[0]; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +/* + * The following 2 functions copy data between iomem and a cached memory + * section. As memcpy() makes use of pre-fetching we cannot use it here. + * The normal alternative of using memcpy_{to,from}io also makes use of + * memcpy() on MIPS so it is not applicable either. We are therefore stuck + * with having to use our own loop. + */ +static void +ltq_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + unsigned char *f = (unsigned char *) (map->virt + from); + unsigned char *t = (unsigned char *) to; + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + while (len--) + *t++ = *f++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static void +ltq_copy_to(struct map_info *map, unsigned long to, + const void *from, ssize_t len) +{ + unsigned char *f = (unsigned char *) from; + unsigned char *t = (unsigned char *) (map->virt + to); + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + while (len--) + *t++ = *f++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static const char const *part_probe_types[] = { "cmdlinepart", NULL }; + +static int __init +ltq_mtd_probe(struct platform_device *pdev) +{ + struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); + struct mtd_info *ltq_mtd = NULL; + struct mtd_partition *parts = NULL; + struct resource *res; + int nr_parts = 0; + struct cfi_private *cfi; + struct map_info *ltq_map; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request mem resource"); + return -EBUSY; + } + + ltq_map = kzalloc(sizeof(struct map_info), GFP_KERNEL); + ltq_map->phys = res->start; + ltq_map->size = resource_size(res); + ltq_map->virt = devm_ioremap_nocache(&pdev->dev, ltq_map->phys, + ltq_map->size); + if (!ltq_map->virt) { + kfree(ltq_map); + dev_err(&pdev->dev, "failed to ioremap!\n"); + return -EIO; + } + + ltq_map->name = ltq_map_name, + ltq_map->bankwidth = 2, + ltq_map->read = ltq_read16, + ltq_map->write = ltq_write16, + ltq_map->copy_from = ltq_copy_from, + ltq_map->copy_to = ltq_copy_to, + + ltq_map->map_priv_1 = LTQ_NOR_PROBING; + ltq_mtd = do_map_probe("cfi_probe", ltq_map); + ltq_map->map_priv_1 = LTQ_NOR_NORMAL; + + if (!ltq_mtd) { + kfree(ltq_map); + iounmap(ltq_map->virt); + dev_err(&pdev->dev, "probing failed\n"); + return -ENXIO; + } + + ltq_mtd->owner = THIS_MODULE; + + cfi = ltq_map->fldrv_priv; + cfi->addr_unlock1 ^= 1; + cfi->addr_unlock2 ^= 1; + + nr_parts = parse_mtd_partitions(ltq_mtd, part_probe_types, &parts, 0); + if (nr_parts > 0) { + dev_info(&pdev->dev, + "using %d partitions from cmdline", nr_parts); + } else { + nr_parts = ltq_mtd_data->nr_parts; + parts = ltq_mtd_data->parts; + } + + return add_mtd_partitions(ltq_mtd, parts, nr_parts); +} + +static struct platform_driver ltq_mtd_driver = { + .driver = { + .name = "ltq_nor", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_mtd(void) +{ + int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); + + if (ret) + pr_err("ltq_nor: error registering platfom driver"); + return ret; +} + +module_init(init_ltq_mtd); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC NOR"); -- 1.7.2.3 From dedekind1@gmail.com Tue Apr 5 16:29:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 16:29:27 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:36580 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491768Ab1DEO3Y (ORCPT ); Tue, 5 Apr 2011 16:29:24 +0200 Received: by ewy3 with SMTP id 3so136988ewy.36 for ; Tue, 05 Apr 2011 07:29:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=XykkLfmIU2yUBfwPEX0XastlRZqvYOwUwDPpRCnKKws=; b=PjnmjHjG+zc+VwPZJohbALnQgwIanJp+44R7SJpwFFVPUX9v+abwmf6z44fz4ox3Mq yWKAGIC68JpZpAFdKQ9FMEiFDATu52ZqwqUwEpV2lGQa3YXGL+IU9GXSdSB8iZpFExPu GdXjqOuERPc54GSmGzpaPQblZHzkcMr0iAfSU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; b=cnuqJzggZGHVmJie1UsHOGum3lTLRA7SQJwsx/DDYOzlX3kF8FYsGuIcaZFwue2aEg M3o7KlHVNlCdH3DlvAtEV530hdysLE9OYWsxFU0J2SpT/1BL7+qb4kTtGMVL5+UoqB6r KToAn+0bitWCjGTltHnp8gOojE0u4+N984UuU= Received: by 10.213.34.207 with SMTP id m15mr2243098ebd.89.1302013758495; Tue, 05 Apr 2011 07:29:18 -0700 (PDT) Received: from ?IPv6:::1? (shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id y7sm4023261eeh.21.2011.04.05.07.29.16 (version=SSLv3 cipher=OTHER); Tue, 05 Apr 2011 07:29:17 -0700 (PDT) Subject: Re: [PATCH V8] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <1302013192-8854-1-git-send-email-blogic@openwrt.org> References: <1302013192-8854-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset="UTF-8" Date: Tue, 05 Apr 2011 17:26:38 +0300 Message-ID: <1302013598.2760.140.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29697 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2011-04-05 at 16:19 +0200, John Crispin wrote: > +/* > + * The NOR flash is connected to the same external bus unit (EBU) as PCI. > + * To make PCI work we need to enable the endianess swapping for the address > + * written to the EBU. This endianess swapping works for PCI correctly but > + * fails for attached NOR devices. To workaround this we need to use a complex > + * map. The workaround involves swapping all addresses whilste probing the chip. > + * Once probing is complete we stop swapping the addresses but swizzle the > + * unlock addresses to ensure that access to the NOR device works correctly. > + */ > + > +enum ltq_nor_state { > + LTQ_NOR_PROBING, > + LTQ_NOR_NORMAL > +}; You do not have to re-send because of this, just a note that in this case it makes more sense to use anonymous enum. Indeed, you do not need this 'ltq_nor_state' name at all, and C enums are not proper types anyway (no real type-checking), so it is just a tiny bit nicer to do: enum { LTQ_NOR_PROBING, LTQ_NOR_NORMAL }; But this is not important at all, just a side note :-) -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From justinmattock@gmail.com Tue Apr 5 18:59:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Apr 2011 18:59:07 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:63482 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491795Ab1DEQ7D (ORCPT ); Tue, 5 Apr 2011 18:59:03 +0200 Received: by pvh11 with SMTP id 11so258513pvh.36 for ; Tue, 05 Apr 2011 09:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=rcQzw8sKjrHSYVVWGrrtPVfC7iL7Yna0LT5K768Kx7I=; b=kVGoRQ26zKAy242lWSkgHTZYIA0BWdppQPwOj/w+KgRJBn8nQYwBvqiK4a0fwWxRtM pj5n0Zec+VhKpuSzyrmz3xttqayvTJmCVz8ODVmDubcO7pUV8ZKBr/P0yVeFMjgIz8av mc5Vm19p6BWTXp3Zr4RLtmGMCSMlis3EgnA/I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=QUgE/9dGlklhDfPsbjFndiUjGXIcLQVnjAXUVAaM1hZTWdTwRuf15Bf0Dk2bGDPl+L p33TtVKV4vnjKhNfoyZoPwu78p6k3tBBD24Mujl+00fCiigFzNIdv6akbbGUiwAc8gcg hFHl34Qy0OMwj5yxLf2avHVTi+HuVZkoZPTzM= Received: by 10.142.203.18 with SMTP id a18mr7599205wfg.397.1302022736972; Tue, 05 Apr 2011 09:58:56 -0700 (PDT) Received: from localhost.localdomain ([64.134.235.77]) by mx.google.com with ESMTPS id m10sm9213015wfl.23.2011.04.05.09.58.54 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 05 Apr 2011 09:58:55 -0700 (PDT) From: "Justin P. Mattock" To: trivial@kernel.org Cc: linux-kernel@vger.kernel.org, "Justin P. Mattock" , Ralf Baechle , linux-mips@linux-mips.org Subject: [RFC 3/5]arch:mips:pmc-sierra:msp71xx:Makefile Remove unused config in the Makefile. Date: Tue, 5 Apr 2011 09:58:20 -0700 Message-Id: <1302022702-24541-3-git-send-email-justinmattock@gmail.com> X-Mailer: git-send-email 1.7.4.2 In-Reply-To: <1302022702-24541-1-git-send-email-justinmattock@gmail.com> References: <1302022702-24541-1-git-send-email-justinmattock@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29698 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: justinmattock@gmail.com Precedence: bulk X-list: linux-mips The patch below removes an unused config variable found by using a kernel cleanup script. Note: I did try to cross compile these but hit erros while doing so.. (gcc is not setup to cross compile) and am unsure if anymore needs to be done. Please have a look if/when anybody has free time. Signed-off-by: Justin P. Mattock CC: Ralf Baechle CC: linux-mips@linux-mips.org --- arch/mips/pmc-sierra/msp71xx/Makefile | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile index cefba77..9201c8b 100644 --- a/arch/mips/pmc-sierra/msp71xx/Makefile +++ b/arch/mips/pmc-sierra/msp71xx/Makefile @@ -3,7 +3,6 @@ # obj-y += msp_prom.o msp_setup.o msp_irq.o \ msp_time.o msp_serial.o msp_elb.o -obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o -- 1.7.4.2 From ralf@linux-mips.org Wed Apr 6 01:58:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Apr 2011 01:58:17 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:41985 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491883Ab1DEX6O (ORCPT ); Wed, 6 Apr 2011 01:58:14 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p35NwEII011766; Wed, 6 Apr 2011 01:58:14 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p35NwAum011761; Wed, 6 Apr 2011 01:58:10 +0200 Date: Wed, 6 Apr 2011 01:58:10 +0200 From: Ralf Baechle To: John Crispin Cc: Alan Cox , Ralph Hempel , Felix Fietkau , linux-mips@linux-mips.org, linux-serial@vger.kernel.org Subject: Re: [PATCH V6] MIPS: lantiq: add serial port support Message-ID: <20110405235810.GA9962@linux-mips.org> References: <1302005458-8423-1-git-send-email-blogic@openwrt.org> <20110405145519.5befce51@lxorguk.ukuu.org.uk> <4D9B2054.8090305@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D9B2054.8090305@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29699 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 05, 2011 at 03:59:48PM +0200, John Crispin wrote: > > Acked-by: Alan Cox > > > > > Hi Alan, > > thanks alot :) Thanks everybody; queued for 2.6.40. Ralf From juhosg@openwrt.org Wed Apr 6 12:52:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Apr 2011 12:52:39 +0200 (CEST) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:54020 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490960Ab1DFKwd (ORCPT ); Wed, 6 Apr 2011 12:52:33 +0200 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 700461400CF; Wed, 6 Apr 2011 12:52:28 +0200 (CEST) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 06E0D14003E; Wed, 6 Apr 2011 12:52:28 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos Subject: [PATCH] MIPS: ath79: increase NR_IRQS Date: Wed, 6 Apr 2011 12:52:15 +0200 Message-Id: <1302087135-12517-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 X-VBMS: A1017C2AC1F | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29700 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The status register of the miscellaneous interrupt controller is 32 bits wide, but the actual value of NR_IRQS covers only 8 of them. Increase NR_IRQS in order to make all of those interrupt lines usable. Signed-off-by: Gabor Juhos --- arch/mips/include/asm/mach-ath79/irq.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 189bc6e..cffbeab 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -10,10 +10,10 @@ #define __ASM_MACH_ATH79_IRQ_H #define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 16 +#define NR_IRQS 40 #define ATH79_MISC_IRQ_BASE 8 -#define ATH79_MISC_IRQ_COUNT 8 +#define ATH79_MISC_IRQ_COUNT 32 #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) -- 1.7.2.1 From kumba@gentoo.org Thu Apr 7 15:15:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 15:15:42 +0200 (CEST) Received: from qmta14.emeryville.ca.mail.comcast.net ([76.96.27.212]:39327 "EHLO qmta14.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491059Ab1DGNPa (ORCPT ); Thu, 7 Apr 2011 15:15:30 +0200 Received: from omta15.emeryville.ca.mail.comcast.net ([76.96.30.71]) by qmta14.emeryville.ca.mail.comcast.net with comcast id Ucmv1g0051Y3wxoAEdFNk0; Thu, 07 Apr 2011 13:15:22 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta15.emeryville.ca.mail.comcast.net with comcast id UdFH1g00y3XYSBH8bdFJ0X; Thu, 07 Apr 2011 13:15:21 +0000 Message-ID: <4D9DB8A8.2020408@gentoo.org> Date: Thu, 07 Apr 2011 09:14:16 -0400 From: Joshua Kinard User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 MIME-Version: 1.0 To: rtc-linux@googlegroups.com, Alessandro Zummo CC: LKML , Linux MIPS List Subject: [PATCH 0/2]: rtc: rtc-ds1685: Add driver to support Dallas/Maxim DS1685/DS1687 & related chips X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29701 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 So I tried a little over a month ago to submit a driver to support the Dallas/Maxim DS1685/DS1687-series of RTC chips. After some very good feedback, I pretty much decided to re-write most of the driver and hope this time, it passes muster. If it does, I'd like to get this queued for 2.6.40. Please advise me of any required steps for this. Summary: The DS1685/DS1687-series RTCs are direct descendants of the DS1285 through DS1585 line of PC RTCs. They support the usual bits for time, calendar, alarm, and a small amount of user NVRAM through the use of four control registers (A through D). The DS1685/DS1687 extend this core support by adding two additional registers (4A, 4B), century bits, month day alarm, wake-up/kickstart, extended NV-SRAM, and a silicon-serial number. These features are accessed via an extended bank switched to by setting a bit in control register A. In addition to the DS1685/DS1687, this driver supports the older DS1688/DS1691 and DS1689/DS1693 RTC chips (no functional difference between these two types), as well as the newer DS17x85/DS17x87 chips that represent the current generation of this particular family. The key differences between all these models is primarily in the total amount of available extended NV-SRAM and minor features, such as burst-mode access to said NV-SRAM on the DS17x85/7 line. The driver provides functionality for time, calendar, alarm, periodic frequency, & power-off/management capabilities. The power management is customizable via platform_data on various platforms, in addition to configuring the register step-size (if needed). The driver currently relies on mmio to reach the registers, which is a requirement on MIPS. I've looked at a couple of other RTC drivers that implement pio access, and have plans to add that in the future once I hunt down some kind of gadget or dongle that maybe lets me test an RTC chip on my PC directly. I developed this driver primarily on an SGI O2 (IP32) system, which uses a DS1687-5 RTC. I have not been able to test the 17x87 line, though I am hoping to get my hands on a DS17287-5 shortly to see if it's functional in my O2. This particular patch is just the core driver only. Platform-specific bits (IP32) will follow this patch to the Linux/MIPS list for review there. If anyone notices anything outstanding, please let me know. Hopefully I covered all of my bases this time around... Thanks! - -- Joshua Kinard Gentoo/MIPS kumba@gentoo.org "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." - --Emperor Turhan, Centauri Republic -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.17 (MingW32) iQIcBAEBAgAGBQJNnbinAAoJENsjoH7SXZXjbqcP/21OzOGt2x5oxDehSX/cNnTG IV1pX4XXWxDBhKU9ssNdPUmgQOkDpEovuSUvcpDhpsMYWSKOP+CfxXm1IG80OzRx aj3l1GVmtevh9Kcy97Z/zOg+JVQCFqNz3wK0MhJzD2l20jrBfVrd5tIQp+2y2wv0 MW1sxDXXdaL0XZISySf9VpyMH/d8KJ0mn6AlqtBfXEgjVayb7jn5o4WccqpTOf5G OnhmiHVZR+5e/bOrC/dANams5FMKtroQzGdRqUiG1H4zM4i3mvULeNNDjjPcImN0 e74KqBzxWd4qXCoQ2CglTFgzg+gaScsOtV5KdLYn7Pu2k1z+gA9whKT/t/T+VjP7 yCdJktNGcto3KXHMLTSI3p7fghjlfHRT4x2r+EDpPoip3Yw8bpCzswTsh7zoO0XR bViJ0vJY6NtiLocaxSN56QNr1rutvHLBkYcBh2+aAFCEjsghgbpjR8nY77MFdD16 rlSweArek8TN22YzEBOAdJ6P1NIA5GAFIs8ba4B4R944cVyhqlG/MHUCNwbLe0CO oCntkpj30zAQTIX6rJPyfQhcaj/9D+fQjUaPpvQVC1bAXSrk6PSFx6810qvR2ZdJ wYO9nrTeifUPjde/FYdRNr3Uq+MsSD63FBgc42eU+Sbum5mRj2OVTHpkxYQFuNDb siylKDM6HSIgGa3FxpAo =Lpkk -----END PGP SIGNATURE----- From kumba@gentoo.org Thu Apr 7 15:16:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 15:16:56 +0200 (CEST) Received: from qmta01.emeryville.ca.mail.comcast.net ([76.96.30.16]:33710 "EHLO qmta01.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab1DGNQt (ORCPT ); Thu, 7 Apr 2011 15:16:49 +0200 Received: from omta04.emeryville.ca.mail.comcast.net ([76.96.30.35]) by qmta01.emeryville.ca.mail.comcast.net with comcast id Ud2M1g0040lTkoCA1dGhBE; Thu, 07 Apr 2011 13:16:41 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta04.emeryville.ca.mail.comcast.net with comcast id UdGb1g00s3XYSBH8QdGd8F; Thu, 07 Apr 2011 13:16:40 +0000 Message-ID: <4D9DB8F6.4080208@gentoo.org> Date: Thu, 07 Apr 2011 09:15:34 -0400 From: Joshua Kinard User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 MIME-Version: 1.0 To: rtc-linux@googlegroups.com, Alessandro Zummo CC: LKML , Linux MIPS List Subject: [PATCH 1/2]: rtc: rtc-ds1685: Add driver to support Dallas/Maxim DS1685/DS1687 & related chips X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29702 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 This patch adds the core driver in drivers/rtc, the header file in include/linux/rtc, and modifies the appropriate Kconfig & Makefiles. I want to give a shoutout to the people at StackOverflow that assisted in the register bit lookup table function. That helped reduce the overall code for the SysFS debug bits significantly. Thanks! Signed-off-by: Joshua Kinard - --- drivers/rtc/Kconfig | 90 + drivers/rtc/Makefile | 1 drivers/rtc/rtc-ds1685.c | 2178 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/rtc/ds1685.h | 334 ++++++ 4 files changed, 2603 insertions(+) diff -Naurp linux-2.6.orig/drivers/rtc/Kconfig linux-2.6.rtc/drivers/rtc/Kconfig - --- linux-2.6.orig/drivers/rtc/Kconfig 2011-04-04 03:08:22.182076000 -0400 +++ linux-2.6.rtc/drivers/rtc/Kconfig 2011-04-07 07:22:55.583871001 -0400 @@ -511,6 +511,96 @@ config RTC_DRV_DS1553 This driver can also be built as a module. If so, the module will be called rtc-ds1553. +config RTC_DRV_DS1685_FAMILY + tristate "Dallas/Maxim DS1685 Family" + help + If you say yes here you get support for the Dallas/Maxim DS1685 + family of real time chips. This family includes the DS1685/DS1687, + DS1689/DS1693, DS17285/DS17287, DS17485/DS17487, and + DS17885/DS17887 chips. + + This driver can also be built as a module. If so, the module + will be called rtc-ds1685. + +choice + prompt "Subtype" + depends on RTC_DRV_DS1685_FAMILY + default RTC_DRV_DS1685 + +config RTC_DRV_DS1685 + bool "DS1685/DS1687" + help + This enables support for the Dallas/Maxim DS1685/DS1687 real time + clock chip. + + This chip is commonly found in SGI O2 (IP32) and SGI Octane (IP30) + systems, as well as EPPC-405-UC modules by electronic system design + GmbH. + +config RTC_DRV_DS1689 + bool "DS1689/DS1693" + help + This enables support for the Dallas/Maxim DS1689/DS1693 real time + clock chip. + + This is an older RTC chip, supplanted by the DS1685/DS1687 above, + which supports a few minor features such as Vcc, Vbat, and Power + Cycle counters, plus a customer-specific, 8-byte ROM/Serial number. + + It also works for the even older DS1688/DS1691 RTC chips, which are + virtually the same and carry the same model number. Both chips + have 114 bytes of user NVRAM. + +config RTC_DRV_DS17285 + bool "DS17285/DS17287" + help + This enables support for the Dallas/Maxim DS17285/DS17287 real time + clock chip. + + This chip features 2kb of extended NV-SRAM. It may possibly be + found in some SGI O2 systems (rare). + +config RTC_DRV_DS17485 + bool "DS17485/DS17487" + help + This enables support for the Dallas/Maxim DS17485/DS17487 real time + clock chip. + + This chip features 4kb of extended NV-SRAM. + +config RTC_DRV_DS17885 + bool "DS17885/DS17887" + help + This enables support for the Dallas/Maxim DS17885/DS17887 real time + clock chip. + + This chip features 8kb of extended NV-SRAM. + +endchoice + +config RTC_DS1685_PROC_REGS + bool "Display register values in /proc" + depends on RTC_DRV_DS1685_FAMILY && PROC_FS + help + Enable this to display a readout of all of the RTC registers in + /proc/drivers/rtc. Keep in mind that this can potentially lead + to lost interrupts, as reading Control Register C will clear + all pending IRQ flags. + + Unless you are debugging this driver, choose N. + +config RTC_DS1685_SYSFS_REGS + bool "SysFS access to RTC register bits" + depends on RTC_DRV_DS1685_FAMILY && SYSFS + help + Enable this to provide access to the RTC control register bits + in /sys. Some of the bits are read-write, others are read-only. + + Keep in mind that reading Control C's bits automatically clears + all pending IRQ flags - this can cause lost interrupts. + + If you know that you need access to these bits, choose Y, Else N. + config RTC_DRV_DS1742 tristate "Maxim/Dallas DS1742/1743" help diff -Naurp linux-2.6.orig/drivers/rtc/Makefile linux-2.6.rtc/drivers/rtc/Makefile - --- linux-2.6.orig/drivers/rtc/Makefile 2011-04-04 03:08:22.182076000 -0400 +++ linux-2.6.rtc/drivers/rtc/Makefile 2011-04-07 07:22:55.583871001 -0400 @@ -39,6 +39,7 @@ obj-$(CONFIG_RTC_DRV_DS1390) += rtc-ds13 obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o +obj-$(CONFIG_RTC_DRV_DS1685_FAMILY) += rtc-ds1685.o obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o diff -Naurp linux-2.6.orig/drivers/rtc/rtc-ds1685.c linux-2.6.rtc/drivers/rtc/rtc-ds1685.c - --- linux-2.6.orig/drivers/rtc/rtc-ds1685.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.rtc/drivers/rtc/rtc-ds1685.c 2011-04-07 07:22:55.593871001 -0400 @@ -0,0 +1,2178 @@ +/* + * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time + * chips. + * + * Copyright (C) 2011 Joshua Kinard . + * Copyright (C) 2009 Matthias Fuchs . + * + * References: + * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. + * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. + * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. + * Application Note 90, Using the Multiplex Bus RTC Extended Features. + * + * Todo: + * - Implement pio access. mmio only for now. + * - Platform data function for custom time checks (some archs are weird). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_PROC_FS +#include +#endif + +#define DRV_VERSION "0.42" + + +/* ----------------------------------------------------------------------- */ +/* Inlined functions */ + +/** + * ds1685_read - read a value from an rtc register. + * @rtc: pointer to the ds1685 rtc structure. + * @reg: the register address to read. + */ +static inline u8 +ds1685_read(struct ds1685_priv *rtc, int reg) +{ + return readb((volatile u8 __iomem *)rtc->regs + + (reg * rtc->regstep)); +} + + +/** + * ds1685_write - write a value to an rtc register. + * @rtc: pointer to the ds1685 rtc structure. + * @reg: the register address to write. + * @value: value to write to the register. + */ +static inline void +ds1685_write(struct ds1685_priv *rtc, int reg, u8 value) +{ + writeb(value, (volatile u8 __iomem *)rtc->regs + + (reg * rtc->regstep)); +} + + +/** + * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0. + * @rtc: pointer to the ds1685 rtc structure. + */ +static inline void +ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc) +{ + ds1685_write(rtc, RTC_CTRL_A, + (ds1685_read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0))); +} + + +/** + * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1. + * @rtc: pointer to the ds1685 rtc structure. + */ +static inline void +ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc) +{ + ds1685_write(rtc, RTC_CTRL_A, + (ds1685_read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0)); +} + + +/** + * ds1685_rtc_begin_data_access - prepare the rtc for data access. + * @rtc: pointer to the ds1685 rtc structure. + * + * This takes several steps to prepare the rtc for access to get/set time + * and alarm values from the rtc registers: + * - Sets the SET bit in Control Register B. + * - Reads Control Register A and checks the UIP bit. + * - If UIP is active, a short delay is added before Control Register A + * is read again in a loop until UIP is inactive. + * - Switches the rtc to bank 1. This allows access to all relevant + * data for normal rtc operation, as bank 0 contains only the nvram. + */ +static inline void +ds1685_rtc_begin_data_access(struct ds1685_priv *rtc) +{ + unsigned long uip_watchdog = jiffies; + + /* Set the SET bit in Ctrl B */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); + + /* Read Ctrl A and check the UIP bit to avoid a lockout. */ + while ((ds1685_read(rtc, RTC_CTRL_A) & RTC_CTRL_A_UIP) && + (time_before(jiffies, uip_watchdog + (2 * HZ / 100)))) + cpu_relax(); + + /* Switch to Bank 1 */ + ds1685_rtc_switch_to_bank1(rtc); +} + + +/** + * ds1685_rtc_end_data_access - end data access on the rtc. + * @rtc: pointer to the ds1685 rtc structure. + * + * This ends what was started by ds1685_rtc_begin_data_access: + * - Switches the rtc back to bank 0. + * - Clears the SET bit in Control Register B. + */ +static inline void +ds1685_rtc_end_data_access(struct ds1685_priv *rtc) +{ + /* Switch back to Bank 0 */ + ds1685_rtc_switch_to_bank1(rtc); + + /* Clear the SET bit in Ctrl B */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); +} + + +/** + * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access. + * @rtc: pointer to the ds1685 rtc structure. + * @flags: irq flags variable for spin_lock_irqsave. + * + * This takes several steps to prepare the rtc for access to read just the + * control registers: + * - Sets a spinlock on the rtc IRQ. + * - Switches the rtc to bank 1. This allows access to the two extended + * control registers. + * + * Only use this where you are certain another lock will not be held. + */ +static inline void +ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long flags) +{ + spin_lock_irqsave(&rtc->lock, flags); + ds1685_rtc_switch_to_bank1(rtc); +} + + +/** + * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc. + * @rtc: pointer to the ds1685 rtc structure. + * @flags: irq flags variable for spin_unlock_irqrestore. + * + * This ends what was started by ds1685_rtc_begin_ctrl_access: + * - Switches the rtc back to bank 0. + * - Unsets the spinlock on the rtc IRQ. + */ +static inline void +ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags) +{ + ds1685_rtc_switch_to_bank0(rtc); + spin_unlock_irqrestore(&rtc->lock, flags); +} + + +/** + * ds1685_rtc_get_ssn - retrieve the silicon serial number. + * @rtc: pointer to the ds1685 rtc structure. + * @ssn: u8 array to hold the bits of the silicon serial number. + * + * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The + * first byte is the model number, the next six bytes are the serial number + * digits, and the final byte is a CRC check byte. Together, they form the + * silicon serial number. + * + * These values are stored in bank1, so call ds1685_rtc_switch_to_bank1 + * before calling this function, else you will read data out of the bank0 + * NVRAM! Remember to call ds1685_rtc_switch_to_bank0 when you're done to + * switch back to bank0. + */ +static inline void +ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn) +{ + ssn[0] = ds1685_read(rtc, RTC_BANK1_SSN_MODEL); + ssn[1] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_1); + ssn[2] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_2); + ssn[3] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_3); + ssn[4] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_4); + ssn[5] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_5); + ssn[6] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_6); + ssn[7] = ds1685_read(rtc, RTC_BANK1_SSN_CRC); +} +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* Read/Set Time & Alarm functions */ + +/** + * ds1685_rtc_read_time - reads the time registers. + * @dev: pointer to device structure. + * @tm: pointer to rtc_time structure. + */ +static int +ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrlb, century; + u8 seconds, minutes, hours, wday, mday, month, years; + + /* Fetch the time info from the RTC registers. */ + ds1685_rtc_begin_data_access(rtc); + seconds = ds1685_read(rtc, RTC_SECONDS) & RTC_SECONDS_MASK; + minutes = ds1685_read(rtc, RTC_MINUTES) & RTC_MINUTES_MASK; + hours = ds1685_read(rtc, RTC_HOURS) & RTC_HOURS_24_MASK; + wday = ds1685_read(rtc, RTC_WDAY) & RTC_WDAY_MASK; + mday = ds1685_read(rtc, RTC_MDAY) & RTC_MDAY_MASK; + month = ds1685_read(rtc, RTC_MONTH) & RTC_MONTH_MASK; + years = ds1685_read(rtc, RTC_YEAR) & RTC_YEAR_MASK; + century = ds1685_read(rtc, RTC_CENTURY) & RTC_CENTURY_MASK; + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ds1685_rtc_end_data_access(rtc); + + /* Convert to Binary, perform fixups, and store to rtc_time. */ + tm->tm_sec = bcd2bin(seconds); + tm->tm_min = bcd2bin(minutes); + tm->tm_hour = bcd2bin(hours); + tm->tm_wday = (bcd2bin(wday) - 1); + tm->tm_mday = bcd2bin(mday); + tm->tm_mon = (bcd2bin(month) - 1); + tm->tm_year = ((bcd2bin(years) + (bcd2bin(century) * 100)) - 1900); + tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); + tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */ + + return rtc_valid_tm(tm); +} + + +/** + * ds1685_rtc_set_time - sets the time registers. + * @dev: pointer to device structure. + * @tm: pointer to rtc_time structure. + */ +static int +ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 seconds, minutes, hours, wday, mday, month, years, century; + + /* Fetch the time info from rtc_time. */ + seconds = bin2bcd(tm->tm_sec); + minutes = bin2bcd(tm->tm_min); + hours = bin2bcd(tm->tm_hour); + wday = bin2bcd(tm->tm_wday + 1); + mday = bin2bcd(tm->tm_mday); + month = bin2bcd(tm->tm_mon + 1); + years = bin2bcd(tm->tm_year % 100); + century = bin2bcd((tm->tm_year + 1900) / 100); + + /* + * Perform Sanity Checks: + * - Months: !> 12, Month Day != 0. + * - Month Day !> Max days in current month. + * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. + */ + if ((month > 12) || (mday == 0)) + return -EDOM; + + if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) + return -EDOM; + + if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || + (tm->tm_sec >= 60) || (wday > 7)) + return -EDOM; + + /* + * Force datamode to BCD (DM=0) and and store the time values in + * the RTC registers. + */ + ds1685_rtc_begin_data_access(rtc); + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_DM))); + ds1685_write(rtc, RTC_SECONDS, seconds & RTC_SECONDS_MASK); + ds1685_write(rtc, RTC_MINUTES, minutes & RTC_MINUTES_MASK); + ds1685_write(rtc, RTC_HOURS, hours & RTC_HOURS_24_MASK); + ds1685_write(rtc, RTC_WDAY, wday & RTC_WDAY_MASK); + ds1685_write(rtc, RTC_MDAY, mday & RTC_MDAY_MASK); + ds1685_write(rtc, RTC_MONTH, month & RTC_MONTH_MASK); + ds1685_write(rtc, RTC_YEAR, years & RTC_YEAR_MASK); + ds1685_write(rtc, RTC_CENTURY, century & RTC_CENTURY_MASK); + ds1685_rtc_end_data_access(rtc); + + return 0; +} + + +/** + * ds1685_rtc_read_alarm - reads the alarm registers. + * @dev: pointer to device structure. + * @alrm: pointer to rtc_wkalrm structure. + * + * There are three primary alarm registers: seconds, minutes, and hours. + * A fourth alarm register for the month date is also available in bank1 for + * kickstart/wakeup features. The DS1685/DS1687 manual states that a + * "don't care" value ranging from 0xc0 to 0xff may be written into one or + * more of the three alarm bytes to act as a wildcard value. The fourth + * byte doesn't support a "don't care" value. + */ +static int +ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 seconds, minutes, hours, mday, ctrlb, ctrlc; + + /* Fetch the alarm info from the RTC alarm registers. */ + ds1685_rtc_begin_data_access(rtc); + seconds = ds1685_read(rtc, RTC_SECONDS_ALARM) & RTC_SECONDS_MASK; + minutes = ds1685_read(rtc, RTC_MINUTES_ALARM) & RTC_MINUTES_MASK; + hours = ds1685_read(rtc, RTC_HOURS_ALARM) & RTC_HOURS_24_MASK; + mday = ds1685_read(rtc, RTC_MDAY_ALARM) & RTC_MDAY_MASK; + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ctrlc = ds1685_read(rtc, RTC_CTRL_C); + ds1685_rtc_end_data_access(rtc); + + /* Check month date. */ + if (!(mday >= 1) && (mday <= 31)) + return -EDOM; + + /* + * Check the three alarm bytes. + * + * The Linux RTC system doesn't support the "don't care" capability + * of this RTC chip. We check for it anyways in case support is + * added in the future. + */ + if (unlikely((seconds >= 0xc0) && (seconds <= 0xff))) + alrm->time.tm_sec = -1; + else + alrm->time.tm_sec = bcd2bin(seconds); + + if (unlikely((minutes >= 0xc0) && (minutes <= 0xff))) + alrm->time.tm_min = -1; + else + alrm->time.tm_min = bcd2bin(minutes); + + if (unlikely((hours >= 0xc0) && (hours <= 0xff))) + alrm->time.tm_hour = -1; + else + alrm->time.tm_hour = bcd2bin(hours); + + /* Write the data to rtc_wkalrm. */ + alrm->time.tm_mday = bcd2bin(mday); + alrm->time.tm_mon = -1; + alrm->time.tm_year = -1; + alrm->time.tm_wday = -1; + alrm->time.tm_yday = -1; + alrm->time.tm_isdst = -1; + alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE); + alrm->pending = !!(ctrlc & RTC_CTRL_C_AF); + + return 0; +} + + +/** + * ds1685_rtc_set_alarm - sets the alarm in registers. + * @dev: pointer to device structure. + * @alrm: pointer to rtc_wkalrm structure. + */ +static int +ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 seconds, minutes, hours, mday, ctrlb; + + /* Fetch the alarm info and convert to BCD. */ + seconds = bin2bcd(alrm->time.tm_sec); + minutes = bin2bcd(alrm->time.tm_min); + hours = bin2bcd(alrm->time.tm_hour); + mday = bin2bcd(alrm->time.tm_mday); + + /* Check the month date for validity. */ + if (!(mday >= 1) && (mday <= 31)) + return -EDOM; + + /* + * Check the three alarm bytes. + * + * The Linux RTC system doesn't support the "don't care" capability + * of this RTC chip because rtc_valid_tm tries to validate every + * field, and we only support four fields. We put the support + * here anyways for the future. + */ + if (unlikely((seconds >= 0xc0) && (seconds <= 0xff))) + seconds = 0xff; + + if (unlikely((minutes >= 0xc0) && (minutes <= 0xff))) + minutes = 0xff; + + if (unlikely((hours >= 0xc0) && (hours <= 0xff))) + hours = 0xff; + + alrm->time.tm_mon = -1; + alrm->time.tm_year = -1; + alrm->time.tm_wday = -1; + alrm->time.tm_yday = -1; + alrm->time.tm_isdst = -1; + + /* Disable the alarm interrupt first. */ + ds1685_rtc_begin_data_access(rtc); + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ds1685_write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE))); + + /* Read ctrlc to clear RTC_CTRL_C_AF. */ + ds1685_read(rtc, RTC_CTRL_C); + + /* + * Force datamode to BCD (DM=0) and store the alarm values in the + * RTC registers. + */ + ds1685_rtc_begin_data_access(rtc); + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_DM))); + ds1685_write(rtc, RTC_SECONDS_ALARM, seconds & RTC_SECONDS_MASK); + ds1685_write(rtc, RTC_MINUTES_ALARM, minutes & RTC_MINUTES_MASK); + ds1685_write(rtc, RTC_HOURS_ALARM, hours & RTC_HOURS_24_MASK); + ds1685_write(rtc, RTC_MDAY_ALARM, mday & RTC_MDAY_MASK); + + /* Re-enable the alarm if needed. */ + if (alrm->enabled) { + ctrlb |= RTC_CTRL_B_AIE; + ds1685_write(rtc, RTC_CTRL_B, ctrlb); + } + + /* Done! */ + ds1685_rtc_end_data_access(rtc); + + return 0; +} +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ + +/* Periodic Interrupt Rate & Square-Wave Output functionality. */ + +#if defined(CONFIG_RTC_INTF_DEV) || defined(CONFIG_SYSFS) +/** + * ds1685_rtc_set_freq - sets the periodic irq rate/square-wave freq. + * @dev: pointer to device structure. + * @freq: integer value of the frequency to set. + */ +static int +ds1685_rtc_set_freq(struct device *dev, int freq) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 rate, ctrla, ctrlb, ctrl4b; + unsigned char e32k = 0; + unsigned long flags = 0; + + /* 8192Hz is the highest user-selectable frequency, unless 32768Hz. */ + if (((freq > RTC_MAX_USER_FREQ) && (freq != RTC_SQW_32768HZ)) || + (freq < 0)) + return -ERANGE; + + /* Set the rate/frequency. */ + switch (freq) { + case 0: rate = RTC_SQW_0HZ; break; + case 2: rate = RTC_SQW_2HZ; break; + case 4: rate = RTC_SQW_4HZ; break; + case 8: rate = RTC_SQW_8HZ; break; + case 16: rate = RTC_SQW_16HZ; break; + case 32: rate = RTC_SQW_32HZ; break; + case 64: rate = RTC_SQW_64HZ; break; + case 128: rate = RTC_SQW_128HZ; break; + case 256: rate = RTC_SQW_256HZ; break; + case 512: rate = RTC_SQW_512HZ; break; + case 1024: rate = RTC_SQW_1024HZ; break; + case 2048: rate = RTC_SQW_2048HZ; break; + case 4096: rate = RTC_SQW_4096HZ; break; + case 8192: rate = RTC_SQW_8192HZ; break; + case 32768: + rate = 0; + e32k = 1; + break; + default: + return -EDOM; + break; + } + + /* Read the current rate/frequency from the RTC. */ + ds1685_rtc_begin_ctrl_access(rtc, flags); + ctrla = ds1685_read(rtc, RTC_CTRL_A); + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + ds1685_rtc_end_ctrl_access(rtc, flags); + + /* If 32768Hz, clear RS3-RS0 in Ctrl A and set E32K in Ctrl 4B. */ + if (e32k) { + ctrla &= ~(RTC_CTRL_A_RS_MASK); + ctrl4b |= RTC_CTRL_4B_E32K; + } else { + /* Else, clear E32K in Ctrl 4B and set RS3-RS0 in Ctrl A. */ + ctrl4b &= ~(RTC_CTRL_4B_E32K); + ctrla &= ~(RTC_CTRL_A_RS_MASK); + ctrla |= rate; + } + + /* Write the rate/frequency to the RTC. */ + ds1685_rtc_begin_ctrl_access(rtc, flags); + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ds1685_write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_SQWE))); + ds1685_write(rtc, RTC_CTRL_A, ctrla); + ds1685_write(rtc, RTC_EXT_CTRL_4B, ctrl4b); + ds1685_write(rtc, RTC_CTRL_B, (ctrlb | RTC_CTRL_B_SQWE)); + ds1685_rtc_end_ctrl_access(rtc, flags); + + return 0; +} +#else +#define ds1685_rtc_set_freq NULL +#endif /* CONFIG_RTC_INTF_DEV || CONFIG_SYSFS */ +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* /dev/rtcX Interface functions */ + +#ifdef CONFIG_RTC_INTF_DEV +/** + * ds1685_rtc_irq_ctrl - enables/disables an interrupt. + * @rtc: pointer to the ds1685 rtc structure. + * @reg: the register address to use. + * @irq_bit: the register bit for the irq to modify. + * @enabled: boolean value indicating the state to set the irq bit to. + * @flags: irq flags variable for spin_lock_irqsave/spin_unlock_irqrestore. + * + * PIE/AIE/UIE are read/written in Ctrl B, and RIE/WIE/KSE in Ctrl 4B. + * RTC Core doesn't know about RIE/WIE/KSE, so they are not processed here. + */ +static inline void +ds1685_rtc_irq_ctrl(struct ds1685_priv *rtc, const int reg, const u8 irq_bit, + const u8 enabled, unsigned long flags) +{ + spin_lock_irqsave(&rtc->lock, flags); + + /* Flip the requisite interrupt-enable bit. */ + if (enabled) + ds1685_write(rtc, reg, (ds1685_read(rtc, reg) | irq_bit)); + else + ds1685_write(rtc, reg, (ds1685_read(rtc, reg) & ~(irq_bit))); + + /* Read Control C to clear all the flag bits. */ + ds1685_read(rtc, RTC_CTRL_C); + spin_unlock_irqrestore(&rtc->lock, flags); +} + + +/** + * ds1685_rtc_periodic_irq_enable - replaces ioctl() RTC_PIE on/off. + * @dev: pointer to device structure. + * @enabled: flag indicating whether to enable or disable. + * + * XXX: 2nd arg should be 'unsigned int', but needs fix in RTC core. + */ +static int +ds1685_rtc_periodic_irq_enable(struct device *dev, int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + unsigned long flags = 0; + + spin_lock_irqsave(&rtc->lock, flags); + ds1685_rtc_switch_to_bank1(rtc); + + /* Periodic IRQs are not possible if E32K = 1 in Control 4B. */ + if (ds1685_read(rtc, RTC_EXT_CTRL_4B) & RTC_CTRL_4B_E32K) + goto no_irq; + + /* Periodic IRQs are not possible if RS3-RS0 = 0 in Control A. */ + if (!(ds1685_read(rtc, RTC_CTRL_A) & RTC_CTRL_A_RS_MASK)) + goto no_irq; + + /* Done with our sanity checks. */ + ds1685_rtc_switch_to_bank0(rtc); + spin_unlock_irqrestore(&rtc->lock, flags); + + /* Enable/disable the Periodic IRQ-Enable flag. */ + ds1685_rtc_irq_ctrl(rtc, RTC_CTRL_B, RTC_CTRL_B_PIE, enabled, flags); + + return 0; + + no_irq: + ds1685_rtc_switch_to_bank0(rtc); + spin_unlock_irqrestore(&rtc->lock, flags); + return -EINVAL; +} + + +/** + * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off. + * @dev: pointer to device structure. + * @enabled: flag indicating whether to enable or disable. + */ +static int +ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + unsigned long flags = 0; + + /* Enable/disable the Alarm IRQ-Enable flag. */ + ds1685_rtc_irq_ctrl(rtc, RTC_CTRL_B, RTC_CTRL_B_AIE, enabled, flags); + + return 0; +} + + +/** + * ds1685_rtc_update_irq_enable - replaces ioctl() RTC_UIE on/off. + * @dev: pointer to device structure. + * @enabled: flag indicating whether to enable or disable. + */ +static int +ds1685_rtc_update_irq_enable(struct device *dev, unsigned int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + unsigned long flags = 0; + + /* Enable/disable the Update IRQ-Enable flag. */ + ds1685_rtc_irq_ctrl(rtc, RTC_CTRL_B, RTC_CTRL_B_UIE, enabled, flags); + + return 0; +} + + +#else +#define ds1685_rtc_periodic_irq_enable NULL +#define ds1685_rtc_alarm_irq_enable NULL +#define ds1685_rtc_update_irq_enable NULL +#endif /* CONFIG_RTC_INTF_DEV */ +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* IRQ handler & workqueue. */ + + +/** + * ds1685_rtc_irq_handler - IRQ handler. + * @irq: IRQ number. + * @dev_id: platform device pointer. + */ +static irqreturn_t +ds1685_rtc_irq_handler(int irq, void *dev_id) +{ + struct platform_device *pdev = dev_id; + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrlb, ctrlc; + unsigned long events = 0; + u8 num_irqs = 0; + + /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */ + if (unlikely(!rtc)) + return IRQ_HANDLED; + + /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */ + spin_lock(&rtc->lock); + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ctrlc = ds1685_read(rtc, RTC_CTRL_C); + + /* Is the IRQF bit set? */ + if (likely(ctrlc & RTC_CTRL_C_IRQF)) { + /* + * We need to determine if it was one of the standard + * events: PF, AF, or UF. If so, we handle them and + * update the RTC core. + */ + if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) { + events = RTC_IRQF; + + /* Check for a periodic interrupt. */ + if ((ctrlb & RTC_CTRL_B_PIE) && + (ctrlc & RTC_CTRL_C_PF)) { + events |= RTC_PF; + num_irqs++; + } + + /* Check for an alarm interrupt. */ + if ((ctrlb & RTC_CTRL_B_AIE) && + (ctrlc & RTC_CTRL_C_AF)) { + events |= RTC_AF; + num_irqs++; + } + + /* Check for an update interrupt. */ + if ((ctrlb & RTC_CTRL_B_UIE) && + (ctrlc & RTC_CTRL_C_UF)) { + events |= RTC_UF; + num_irqs++; + } + + rtc_update_irq(rtc->dev, num_irqs, events); + } else { + /* + * We received one of the "extended" interrupts + * which are not recognized by the RTC core. These + * need to be handled in task context as they can + * call other functions and we don't want to be in + * irq context for too long, so we schedule them + * into a workqueue and inform the RTC core that + * nothing happened. + */ + spin_unlock(&rtc->lock); + schedule_work(&rtc->work); + rtc_update_irq(rtc->dev, 0, 0); + return IRQ_HANDLED; + } + } + spin_unlock(&rtc->lock); + + return events ? IRQ_HANDLED : IRQ_NONE; +} + + +/** + * ds1685_rtc_work_queue - work queue handler. + * @work: work_struct containing data to work on in task context. + */ +static void +ds1685_rtc_work_queue(struct work_struct *work) +{ + struct ds1685_priv *rtc = container_of(work, + struct ds1685_priv, work); + struct platform_device *pdev = to_platform_device(&rtc->dev->dev); + struct mutex *rtc_mutex = &rtc->dev->ops_lock; + u8 ctrl4a, ctrl4b; + + mutex_lock(rtc_mutex); + + ds1685_rtc_switch_to_bank1(rtc); + ctrl4a = ds1685_read(rtc, RTC_EXT_CTRL_4A); + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + + /* + * Check for a kickstart interrupt. With Vcc applied, this + * typically means that the power button was pressed, so we + * begin the shutdown sequence. + */ + if ((ctrl4b & RTC_CTRL_4B_KSE) && + (ctrl4a & RTC_CTRL_4A_KF)) { + /* Briefly disable kickstarts to debounce button presses. */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) & + ~(RTC_CTRL_4B_KSE))); + + /* Clear the kickstart flag. */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ctrl4a & ~(RTC_CTRL_4A_KF))); + + + /* + * Sleep 500ms before re-enabling kickstarts. This allows + * adequate time to avoid reading signal jitter as additional + * button presses. + */ + msleep(500); + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) | + RTC_CTRL_4B_KSE)); + + /* Call the platform pre-poweroff function. Else, shutdown. */ + if (rtc->prepare_poweroff != NULL) + rtc->prepare_poweroff(); + else + ds1685_rtc_poweroff(pdev); + } + + /* + * Check for a wake-up interrupt. With Vcc applied, this is + * essentially a second alarm interrupt, except it takes into + * account the 'date' register in bank1 in addition to the + * standard three alarm registers. + */ + if ((ctrl4b & RTC_CTRL_4B_WIE) && + (ctrl4a & RTC_CTRL_4A_WF)) { + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ctrl4a & ~(RTC_CTRL_4A_WF))); + + /* Call the platform wake_alarm function if defined. */ + if (rtc->wake_alarm != NULL) + rtc->wake_alarm(); + else + dev_warn(&pdev->dev, + "Wake Alarm IRQ just occurred!\n"); + } + + /* + * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0 + * when RCE in 4B is set to a logic 1. This clears all NVRAM bytes + * in bank0 by setting each byte to a logic 1. This has no effect + * on any extended NV-SRAM that might be present, nor on the + * time/calendar/alarm registers. After a ram-clear is completed, + * there is a minimum recovery time of ~150ms in which all + * reads/writes are locked out. NOTE: A ram-clear can still occur + * if RCE=1 and RIE=0. We cannot catch this scenario. + */ + if ((ctrl4b & RTC_CTRL_4B_RIE) && + (ctrl4a & RTC_CTRL_4A_RF)) { + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ctrl4a & ~(RTC_CTRL_4A_RF))); + msleep(150); + + /* Call the platform post_ram_clear function if defined. */ + if (rtc->post_ram_clear != NULL) + rtc->post_ram_clear(); + else + dev_warn(&pdev->dev, + "RAM-Clear IRQ just occurred!\n"); + } + ds1685_rtc_switch_to_bank0(rtc); + + mutex_unlock(rtc_mutex); +} +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* ProcFS interface */ + +#ifdef CONFIG_PROC_FS +#define NUM_REGS 6 /* Num of control registers. */ +#define NUM_BITS 8 /* Num bits per register. */ +#define NUM_SPACES 4 /* Num spaces between each bit. */ + +/* + * Periodic Interrupt Rates. + */ +static const char *ds1685_rtc_pirq_rate[16] = { + "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms", + "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms", + "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" +}; + + +/* + * Square-Wave Output Frequencies. + */ +static const char *ds1685_rtc_sqw_freq[16] = { + "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", + "1024Hz", "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", + "8Hz", "4Hz", "2Hz" +}; + + +#ifdef CONFIG_RTC_DS1685_PROC_REGS +/** + * ds1685_rtc_print_regs - helper function to print register values. + * @hex: hex byte to convert into binary bits. + * @dest: destination char array. + * + * This is basically a hex->binary function, just with extra spacing between + * the digits. It only works on 1-byte values (8 bits). + */ +static char* +ds1685_rtc_print_regs(u8 hex, char *dest) +{ + u32 i, j; + char *tmp = dest; + + for (i = 0; i < NUM_BITS; i++) { + *tmp++ = ((hex & 0x80) != 0 ? '1' : '0'); + for (j = 0; j < NUM_SPACES; j++) + *tmp++ = ' '; + hex <<= 1; + } + *tmp++ = '\0'; + + return dest; +} +#endif + + +/** + * ds1685_rtc_proc - procfs access function. + * @dev: pointer to device structure. + * @seq: pointer to seq_file structure. + */ +static int +ds1685_rtc_proc(struct device *dev, struct seq_file *seq) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8]; + char *model = '\0'; +#ifdef CONFIG_RTC_DS1685_PROC_REGS + char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1]; +#endif + + /* Read all the relevant data from the control registers. */ + ds1685_rtc_switch_to_bank1(rtc); + ds1685_rtc_get_ssn(rtc, ssn); + ctrla = ds1685_read(rtc, RTC_CTRL_A); + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ctrlc = ds1685_read(rtc, RTC_CTRL_C); + ctrld = ds1685_read(rtc, RTC_CTRL_D); + ctrl4a = ds1685_read(rtc, RTC_EXT_CTRL_4A); + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + ds1685_rtc_switch_to_bank0(rtc); + + /* Determine the RTC model. */ + switch (ssn[0]) { + case RTC_MODEL_DS1685: model = "DS1685/DS1687\0"; break; + case RTC_MODEL_DS1689: model = "DS1689/DS1693\0"; break; + case RTC_MODEL_DS17285: model = "DS17285/DS17287\0"; break; + case RTC_MODEL_DS17485: model = "DS17485/DS17487\0"; break; + case RTC_MODEL_DS17885: model = "DS17885/DS17887\0"; break; + default: model = "Unknown\0"; break; + } + + /* Print out the information. */ + seq_printf(seq, + "Model\t\t: %s\n" + "Oscillator\t: %s\n" + "12/24hr\t\t: %s\n" + "DST\t\t: %s\n" + "Data mode\t: %s\n" + "Battery\t\t: %s\n" + "Aux batt\t: %s\n" + "Update IRQ\t: %s\n" + "Periodic IRQ\t: %s\n" + "Periodic Rate\t: %s\n" + "SQW Freq\t: %s\n" +#ifdef CONFIG_RTC_DS1685_PROC_REGS + "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n" + "Register Status\t:\n" + " Ctrl A\t: " + "UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n\t\t: %s\n" + " Ctrl B\t: " + "SET PIE AIE UIE SQWE DM 2412 DSE\n\t\t: %s\n" + " Ctrl C\t: " + "IRQF PF AF UF --- --- --- ---\n\t\t: %s\n" + " Ctrl D\t: " + "VRT --- --- --- --- --- --- ---\n\t\t: %s\n" + " Ctrl 4A\t: " + "VRT2 INCR --- --- PAB RF WF KF\n\t\t: %s\n" + " Ctrl 4B\t: " + "ABE E32k CS RCE PRS RIE WIE KSE\n\t\t: %s\n", +#else + "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", +#endif + model, + ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), + ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), + ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), + ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), + ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), + ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), + ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"), + ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"), + (!(ctrl4b & RTC_CTRL_4B_E32K) ? + ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"), + (!((ctrl4b & RTC_CTRL_4B_E32K)) ? + ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"), +#ifdef CONFIG_RTC_DS1685_PROC_REGS + ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], ssn[7], + ds1685_rtc_print_regs(ctrla, bits[0]), + ds1685_rtc_print_regs(ctrlb, bits[1]), + ds1685_rtc_print_regs(ctrlc, bits[2]), + ds1685_rtc_print_regs(ctrld, bits[3]), + ds1685_rtc_print_regs(ctrl4a, bits[4]), + ds1685_rtc_print_regs(ctrl4b, bits[5])); +#else + ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], ssn[7]); +#endif + return 0; +} +#else +#define ds1685_rtc_proc NULL +#endif /* CONFIG_PROC_FS */ +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* RTC Class operations */ + +static const struct rtc_class_ops ds1685_rtc_ops = { + .proc = ds1685_rtc_proc, + .read_time = ds1685_rtc_read_time, + .set_time = ds1685_rtc_set_time, + .read_alarm = ds1685_rtc_read_alarm, + .set_alarm = ds1685_rtc_set_alarm, + .irq_set_freq = ds1685_rtc_set_freq, + .irq_set_state = ds1685_rtc_periodic_irq_enable, + .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, + .update_irq_enable = ds1685_rtc_update_irq_enable, +}; +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* SysFS interface */ + +#ifdef CONFIG_SYSFS +/** + * ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs. + * @file: pointer to file structure. + * @kobj: pointer to kobject structure. + * @bin_attr: pointer to bin_attribute structure. + * @buf: pointer to char array to hold the output. + * @pos: current file position pointer. + * @size: size of the data to read. + */ +static ssize_t +ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t pos, size_t size) +{ + struct platform_device *pdev = + to_platform_device(container_of(kobj, struct device, kobj)); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + ssize_t count; + unsigned long flags = 0; + + spin_lock_irqsave(&rtc->lock, flags); + ds1685_rtc_switch_to_bank0(rtc); + + /* Read NVRAM in time and bank0 registers. */ + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; + count++, size--) { + if (count < NVRAM_SZ_TIME) + *buf++ = ds1685_read(rtc, (NVRAM_TIME_BASE + + pos++)); + else + *buf++ = ds1685_read(rtc, (NVRAM_BANK0_BASE + + pos++)); + } + +#ifndef CONFIG_RTC_DRV_DS1689 + if (size > 0) { + ds1685_rtc_switch_to_bank1(rtc); + +#ifndef CONFIG_RTC_DRV_DS1685 + /* Enable burst-mode on DS17x85/DS17x87 */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) | + RTC_CTRL_4A_BME)); + + /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start + * reading with burst-mode */ + ds1685_write(rtc, RTC_BANK1_RAM_ADDR_LSB, + (pos - NVRAM_TOTAL_SZ_BANK0)); +#endif + + /* Read NVRAM in bank1 registers. */ + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; + count++, size--) { +#ifdef CONFIG_RTC_DRV_DS1685 + /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR + * before each read. */ + ds1685_write(rtc, RTC_BANK1_RAM_ADDR, + (pos - NVRAM_TOTAL_SZ_BANK0)); +#endif + *buf++ = ds1685_read(rtc, RTC_BANK1_RAM_DATA_PORT); + pos++; + } + +#ifndef CONFIG_RTC_DRV_DS1685 + /* Disable burst-mode on DS17x85/DS17x87 */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) & + ~(RTC_CTRL_4A_BME))); +#endif + ds1685_rtc_switch_to_bank0(rtc); + } +#endif /* !CONFIG_RTC_DRV_DS1689 */ + spin_unlock_irqrestore(&rtc->lock, flags); + + /* + * XXX: Bug? this causes the function to get executed several times + * in succession. But it's the only way to actually get data written + * out to a file correctly. + */ + return count; +} + + +/** + * ds1685_rtc_sysfs_nvram_write - writes rtc nvram via sysfs. + * @file: pointer to file structure. + * @kobj: pointer to kobject structure. + * @bin_attr: pointer to bin_attribute structure. + * @buf: pointer to char array to hold the input. + * @pos: current file position pointer. + * @size: size of the data to write. + */ +static ssize_t +ds1685_rtc_sysfs_nvram_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t pos, size_t size) +{ + struct platform_device *pdev = + to_platform_device(container_of(kobj, struct device, kobj)); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + ssize_t count; + unsigned long flags = 0; + + spin_lock_irqsave(&rtc->lock, flags); + ds1685_rtc_switch_to_bank0(rtc); + + /* Write NVRAM in time and bank0 registers. */ + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; + count++, size--) + if (count < NVRAM_SZ_TIME) + ds1685_write(rtc, (NVRAM_TIME_BASE + pos++), + *buf++); + else + ds1685_write(rtc, (NVRAM_BANK0_BASE), *buf++); + +#ifndef CONFIG_RTC_DRV_DS1689 + if (size > 0) { + ds1685_rtc_switch_to_bank1(rtc); + +#ifndef CONFIG_RTC_DRV_DS1685 + /* Enable burst-mode on DS17x85/DS17x87 */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) | + RTC_CTRL_4A_BME)); + + /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start + * writing with burst-mode */ + ds1685_write(rtc, RTC_BANK1_RAM_ADDR_LSB, + (pos - NVRAM_TOTAL_SZ_BANK0)); +#endif + + /* Write NVRAM in bank1 registers. */ + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; + count++, size--) { +#ifdef CONFIG_RTC_DRV_DS1685 + /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR + * before each read. */ + ds1685_write(rtc, RTC_BANK1_RAM_ADDR, + (pos - NVRAM_TOTAL_SZ_BANK0)); +#endif + ds1685_write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++); + pos++; + } + +#ifndef CONFIG_RTC_DRV_DS1685 + /* Disable burst-mode on DS17x85/DS17x87 */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) & + ~(RTC_CTRL_4A_BME))); +#endif + ds1685_rtc_switch_to_bank0(rtc); + } +#endif /* !CONFIG_RTC_DRV_DS1689 */ + spin_unlock_irqrestore(&rtc->lock, flags); + + return count; +} + + +/** + * struct ds1685_rtc_sysfs_nvram_attr - sysfs attributes for rtc nvram. + * @attr: nvram attributes. + * @read: nvram read function. + * @write: nvram write function. + * @size: nvram total size (bank0 + extended). + */ +static struct bin_attribute ds1685_rtc_sysfs_nvram_attr = { + .attr = { + .name = "nvram", + .mode = S_IRUGO | S_IWUSR, + }, + .read = ds1685_rtc_sysfs_nvram_read, + .write = ds1685_rtc_sysfs_nvram_write, + .size = NVRAM_TOTAL_SZ +}; + + +/** + * ds1685_rtc_sysfs_sqwfreq_show - reads the square-wave freq via sysfs. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_sqwfreq_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrla, ctrl4b; + u32 freq = 0; + + /* Read the square-wave data from the RTC registers. */ + ds1685_rtc_switch_to_bank1(rtc); + ctrla = ds1685_read(rtc, RTC_CTRL_A); + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + ds1685_rtc_switch_to_bank0(rtc); + + /* If E32K is set, return 32768Hz. */ + if (ctrl4b & RTC_CTRL_4B_E32K) + return sprintf(buf, "%d\n", RTC_SQW_32768HZ); + + /* Else, return the user-selected frequency. */ + switch (ctrla & RTC_CTRL_A_RS_MASK) { + case RTC_SQW_0HZ: freq = 0; break; + case RTC_SQW_2HZ: freq = 2; break; + case RTC_SQW_4HZ: freq = 4; break; + case RTC_SQW_8HZ: freq = 8; break; + case RTC_SQW_16HZ: freq = 16; break; + case RTC_SQW_32HZ: freq = 32; break; + case RTC_SQW_64HZ: freq = 64; break; + case 0x02: + case RTC_SQW_128HZ: freq = 128; break; + case 0x01: + case RTC_SQW_256HZ: freq = 256; break; + case RTC_SQW_512HZ: freq = 512; break; + case RTC_SQW_1024HZ: freq = 1024; break; + case RTC_SQW_2048HZ: freq = 2048; break; + case RTC_SQW_4096HZ: freq = 4096; break; + case RTC_SQW_8192HZ: freq = 8192; break; + } + + return sprintf(buf, "%d\n", freq); +} + + +/** + * ds1685_rtc_sysfs_sqwfreq_store - sets the square-wave freq via sysfs. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + * @count: number of bytes written. + */ +static ssize_t +ds1685_rtc_sysfs_sqwfreq_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + long int freq = 0; + int ret; + + /* We only accept numbers. */ + if (strict_strtol(buf, 10, &freq) < 0) + return -EINVAL; + + /* Return the failure code if the frequency couldn't be set. */ + ret = ds1685_rtc_set_freq(dev, freq); + if (ret) + return ret; + + return count; +} +static DEVICE_ATTR(sqwfreq, S_IRUGO | S_IWUSR, ds1685_rtc_sysfs_sqwfreq_show, + ds1685_rtc_sysfs_sqwfreq_store); + + +/** + * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_battery_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrld; + + ctrld = ds1685_read(rtc, RTC_CTRL_D); + + return sprintf(buf, "%s\n", + (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A"); +} +static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL); + + +/** + * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_auxbatt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrl4a; + + ds1685_rtc_switch_to_bank1(rtc); + ctrl4a = ds1685_read(rtc, RTC_EXT_CTRL_4A); + ds1685_rtc_switch_to_bank0(rtc); + + return sprintf(buf, "%s\n", + (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A"); +} +static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL); + + +/** + * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_serial_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ssn[8]; + + ds1685_rtc_switch_to_bank1(rtc); + ds1685_rtc_get_ssn(rtc, ssn); + ds1685_rtc_switch_to_bank0(rtc); + + return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", + ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], + ssn[7]); + + return 0; +} +static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL); + +/** + * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features. + */ +static struct attribute* +ds1685_rtc_sysfs_misc_attrs[] = { + &dev_attr_sqwfreq.attr, + &dev_attr_battery.attr, + &dev_attr_auxbatt.attr, + &dev_attr_serial.attr, + NULL, +}; + + +/** + * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features. + */ +static const struct attribute_group +ds1685_rtc_sysfs_misc_grp = { + .name = "misc", + .attrs = ds1685_rtc_sysfs_misc_attrs, +}; + + +#ifdef CONFIG_RTC_DS1685_SYSFS_REGS +/** + * struct ds1685_rtc_regs. + * @name: char pointer for the bit name. + * @reg: control register the bit is in. + * @bit: the bit's offset in the register. + */ +struct ds1685_rtc_regs { + const char *name; + const u8 reg; + const u8 bit; +}; + + +/* + * Register bit lookup table. + */ +static const struct ds1685_rtc_regs +ds1685_regs_table[] = { + { "uip", RTC_CTRL_A, RTC_CTRL_A_UIP }, + { "dv2", RTC_CTRL_A, RTC_CTRL_A_DV2 }, + { "dv1", RTC_CTRL_A, RTC_CTRL_A_DV1 }, + { "dv0", RTC_CTRL_A, RTC_CTRL_A_DV0 }, + { "rs3", RTC_CTRL_A, RTC_CTRL_A_RS3 }, + { "rs2", RTC_CTRL_A, RTC_CTRL_A_RS2 }, + { "rs1", RTC_CTRL_A, RTC_CTRL_A_RS1 }, + { "rs0", RTC_CTRL_A, RTC_CTRL_A_RS0 }, + { "set", RTC_CTRL_B, RTC_CTRL_B_SET }, + { "pie", RTC_CTRL_B, RTC_CTRL_B_PIE }, + { "aie", RTC_CTRL_B, RTC_CTRL_B_AIE }, + { "uie", RTC_CTRL_B, RTC_CTRL_B_UIE }, + { "sqwe", RTC_CTRL_B, RTC_CTRL_B_SQWE }, + { "dm", RTC_CTRL_B, RTC_CTRL_B_DM }, + { "2412", RTC_CTRL_B, RTC_CTRL_B_2412 }, + { "dse", RTC_CTRL_B, RTC_CTRL_B_DSE }, + { "irqf", RTC_CTRL_C, RTC_CTRL_C_IRQF }, + { "pf", RTC_CTRL_C, RTC_CTRL_C_PF }, + { "af", RTC_CTRL_C, RTC_CTRL_C_AF }, + { "uf", RTC_CTRL_C, RTC_CTRL_C_UF }, + { "vrt", RTC_CTRL_D, RTC_CTRL_D_VRT }, + { "vrt2", RTC_EXT_CTRL_4A, RTC_CTRL_4A_VRT2 }, + { "incr", RTC_EXT_CTRL_4A, RTC_CTRL_4A_INCR }, + { "pab", RTC_EXT_CTRL_4A, RTC_CTRL_4A_PAB }, + { "rf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_RF }, + { "wf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_WF }, + { "kf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_KF }, +#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) + { "bme", RTC_EXT_CTRL_4A, RTC_CTRL_4A_BME }, +#endif + { "abe", RTC_EXT_CTRL_4B, RTC_CTRL_4B_ABE }, + { "e32k", RTC_EXT_CTRL_4B, RTC_CTRL_4B_E32K }, + { "cs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_CS }, + { "rce", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RCE }, + { "prs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_PRS }, + { "rie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RIE }, + { "wie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_WIE }, + { "kse", RTC_EXT_CTRL_4B, RTC_CTRL_4B_KSE }, + { NULL, 0, 0 }, +}; + + +/** + * ds1685_rtc_sysfs_regs_lookup - register bit lookup function. + * @name: register bit to look up in ds1685_regs_table. + */ +static const struct ds1685_rtc_regs* +ds1685_rtc_sysfs_regs_lookup(const char *name) +{ + const struct ds1685_rtc_regs *p = ds1685_regs_table; + + for (; p->name != NULL; ++p) + if (strcmp(p->name, name) == 0) + return p; + + return NULL; +} + + +/** + * ds1685_rtc_sysfs_ctrl_regs_show - reads a register bit via sysfs. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_ctrl_regs_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + u8 reg = 0, bit = 0, tmp; + const struct ds1685_rtc_regs *reg_info = + ds1685_rtc_sysfs_regs_lookup(attr->attr.name); + + /* Make sure we actually matched something. */ + if (!reg_info) + return -EINVAL; + + reg = reg_info->reg; + bit = reg_info->bit; + + /* No spinlock during a read -- mutex is already held. */ + ds1685_rtc_switch_to_bank1(rtc); + tmp = ds1685_read(rtc, reg) & bit; + ds1685_rtc_switch_to_bank0(rtc); + + return sprintf(buf, "%d\n", (tmp ? 1 : 0)); +} + + +/** + * ds1685_rtc_sysfs_ctrl_regs_store - writes a register bit via sysfs. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + * @count: number of bytes written. + */ +static ssize_t +ds1685_rtc_sysfs_ctrl_regs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + u8 reg = 0, bit = 0, tmp; + unsigned long flags = 0; + long int val = 0; + const struct ds1685_rtc_regs *reg_info = + ds1685_rtc_sysfs_regs_lookup(attr->attr.name); + + /* We only accept numbers. */ + if (strict_strtol(buf, 10, &val) < 0) + return -EINVAL; + + /* bits are binary, 0 or 1 only. */ + if ((val != 0) && (val != 1)) + return -ERANGE; + + /* Make sure we actually matched something. */ + if (!reg_info) + return -EINVAL; + + reg = reg_info->reg; + bit = reg_info->bit; + + /* Safe to spinlock during a write. */ + ds1685_rtc_begin_ctrl_access(rtc, flags); + tmp = ds1685_read(rtc, reg); + ds1685_write(rtc, reg, (val ? (tmp | bit) : (tmp & ~(bit)))); + ds1685_rtc_end_ctrl_access(rtc, flags); + + return count; +} + + +/** + * DS1685_RTC_SYSFS_REG_RO - device_attribute for a read-only register bit. + * @bit: bit to read. + */ +#define DS1685_RTC_SYSFS_REG_RO(bit) \ + static DEVICE_ATTR(bit, S_IRUGO, \ + ds1685_rtc_sysfs_ctrl_regs_show, NULL) + +/** + * DS1685_RTC_SYSFS_REG_RW - device_attribute for a read-write register bit. + * @bit: bit to read or write. + */ +#define DS1685_RTC_SYSFS_REG_RW(bit) \ + static DEVICE_ATTR(bit, S_IRUGO | S_IWUSR, \ + ds1685_rtc_sysfs_ctrl_regs_show, \ + ds1685_rtc_sysfs_ctrl_regs_store) + + +/* + * Control Register A bits. + */ +DS1685_RTC_SYSFS_REG_RO(uip); +DS1685_RTC_SYSFS_REG_RW(dv2); +DS1685_RTC_SYSFS_REG_RW(dv1); +DS1685_RTC_SYSFS_REG_RO(dv0); +DS1685_RTC_SYSFS_REG_RW(rs3); +DS1685_RTC_SYSFS_REG_RW(rs2); +DS1685_RTC_SYSFS_REG_RW(rs1); +DS1685_RTC_SYSFS_REG_RW(rs0); + +static struct attribute* +ds1685_rtc_sysfs_ctrla_attrs[] = { + &dev_attr_uip.attr, + &dev_attr_dv2.attr, + &dev_attr_dv1.attr, + &dev_attr_dv0.attr, + &dev_attr_rs3.attr, + &dev_attr_rs2.attr, + &dev_attr_rs1.attr, + &dev_attr_rs0.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrla_grp = { + .name = "ctrla", + .attrs = ds1685_rtc_sysfs_ctrla_attrs, +}; + + +/* + * Control Register B bits. + */ +DS1685_RTC_SYSFS_REG_RO(set); +DS1685_RTC_SYSFS_REG_RW(pie); +DS1685_RTC_SYSFS_REG_RW(aie); +DS1685_RTC_SYSFS_REG_RW(uie); +DS1685_RTC_SYSFS_REG_RW(sqwe); +DS1685_RTC_SYSFS_REG_RO(dm); +DS1685_RTC_SYSFS_REG_RO(2412); +DS1685_RTC_SYSFS_REG_RO(dse); + +static struct attribute* +ds1685_rtc_sysfs_ctrlb_attrs[] = { + &dev_attr_set.attr, + &dev_attr_pie.attr, + &dev_attr_aie.attr, + &dev_attr_uie.attr, + &dev_attr_sqwe.attr, + &dev_attr_dm.attr, + &dev_attr_2412.attr, + &dev_attr_dse.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrlb_grp = { + .name = "ctrlb", + .attrs = ds1685_rtc_sysfs_ctrlb_attrs, +}; + + +/* + * Control Register C bits. + * + * Reading Control C clears these bits! Reading them individually can + * possibly cause an interrupt to be missed. Use the /proc interface + * to see all the bits in this register simultaneously. + */ +DS1685_RTC_SYSFS_REG_RO(irqf); +DS1685_RTC_SYSFS_REG_RO(pf); +DS1685_RTC_SYSFS_REG_RO(af); +DS1685_RTC_SYSFS_REG_RO(uf); + +static struct attribute* +ds1685_rtc_sysfs_ctrlc_attrs[] = { + &dev_attr_irqf.attr, + &dev_attr_pf.attr, + &dev_attr_af.attr, + &dev_attr_uf.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrlc_grp = { + .name = "ctrlc", + .attrs = ds1685_rtc_sysfs_ctrlc_attrs, +}; + + +/* + * Control Register D bits. + */ +DS1685_RTC_SYSFS_REG_RO(vrt); + +static struct attribute* +ds1685_rtc_sysfs_ctrld_attrs[] = { + &dev_attr_vrt.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrld_grp = { + .name = "ctrld", + .attrs = ds1685_rtc_sysfs_ctrld_attrs, +}; + + +/* + * Control Register 4A bits. + */ +DS1685_RTC_SYSFS_REG_RO(vrt2); +DS1685_RTC_SYSFS_REG_RO(incr); +DS1685_RTC_SYSFS_REG_RW(pab); +DS1685_RTC_SYSFS_REG_RW(rf); +DS1685_RTC_SYSFS_REG_RW(wf); +DS1685_RTC_SYSFS_REG_RW(kf); +#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) +DS1685_RTC_SYSFS_REG_RO(bme); +#endif + +static struct attribute* +ds1685_rtc_sysfs_ctrl4a_attrs[] = { + &dev_attr_vrt2.attr, + &dev_attr_incr.attr, + &dev_attr_pab.attr, + &dev_attr_rf.attr, + &dev_attr_wf.attr, + &dev_attr_kf.attr, +#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) + &dev_attr_bme.attr, +#endif + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrl4a_grp = { + .name = "ctrl4a", + .attrs = ds1685_rtc_sysfs_ctrl4a_attrs, +}; + + +/* + * Control Register 4B bits. + */ +DS1685_RTC_SYSFS_REG_RW(abe); +DS1685_RTC_SYSFS_REG_RW(e32k); +DS1685_RTC_SYSFS_REG_RO(cs); +DS1685_RTC_SYSFS_REG_RW(rce); +DS1685_RTC_SYSFS_REG_RW(prs); +DS1685_RTC_SYSFS_REG_RW(rie); +DS1685_RTC_SYSFS_REG_RW(wie); +DS1685_RTC_SYSFS_REG_RW(kse); + +static struct attribute* +ds1685_rtc_sysfs_ctrl4b_attrs[] = { + &dev_attr_abe.attr, + &dev_attr_e32k.attr, + &dev_attr_cs.attr, + &dev_attr_rce.attr, + &dev_attr_prs.attr, + &dev_attr_rie.attr, + &dev_attr_wie.attr, + &dev_attr_kse.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrl4b_grp = { + .name = "ctrl4b", + .attrs = ds1685_rtc_sysfs_ctrl4b_attrs, +}; +#endif /* CONFIG_RTC_DS1685_SYSFS_REGS */ + + +/** + * ds1685_rtc_sysfs_register - register sysfs files. + * @dev: pointer to device structure. + */ +static int __devinit +ds1685_rtc_sysfs_register(struct device *dev) +{ + int ret = 0; + + sysfs_bin_attr_init(&ds1685_rtc_sysfs_nvram_attr); + ret = sysfs_create_bin_file(&dev->kobj, + &ds1685_rtc_sysfs_nvram_attr); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp); + if (ret) + return ret; + +#ifdef CONFIG_RTC_DS1685_SYSFS_REGS + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp); + if (ret) + return ret; +#endif + return 0; +} + + +/** + * ds1685_rtc_sysfs_unregister - unregister sysfs files. + * @dev: pointer to device structure. + */ +static int __devexit +ds1685_rtc_sysfs_unregister(struct device *dev) +{ + sysfs_remove_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp); + +#ifdef CONFIG_RTC_DS1685_SYSFS_REGS + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp); +#endif + + return 0; +} +#endif /* CONFIG_SYSFS */ + + + +/* ----------------------------------------------------------------------- */ +/* Driver Probe/Removal */ + +/** + * ds1685_rtc_probe - initializes rtc driver. + * @pdev: pointer to platform_device structure. + */ +static int __devinit +ds1685_rtc_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc_dev; + struct resource *res; + struct ds1685_priv *rtc; + struct ds1685_rtc_platform_data *pdata; + u8 ctrla, ctrlb, hours; + unsigned char am_pm; + int ret = 0; + + /* Get the platform resources. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENXIO; + + /* Get the platform data. */ + pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data; + if (!pdata) + return -ENODEV; + + /* Allocate memory for the rtc device. */ + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + rtc->size = resource_size(res); + + /* Request a memory region. */ + /* TODO: Only mmio for now. Need to add standard io. */ + if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size, + pdev->name)) + return -EBUSY; + + /* Set the base address for the rtc, and ioremap its registers. */ + rtc->baseaddr = res->start; + rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size); + if (!rtc->regs) + return -ENOMEM; + + /* Get the register step size. */ + if (pdata->regstep > 0) + rtc->regstep = pdata->regstep; + else + rtc->regstep = 1; + + /* Assign the pre-shutdown function, if defined. */ + if (pdata->plat_prepare_poweroff != NULL) + rtc->prepare_poweroff = pdata->plat_prepare_poweroff; + + /* Assign the wake_alarm function, if defined. */ + if (pdata->plat_wake_alarm != NULL) + rtc->wake_alarm = pdata->plat_wake_alarm; + + /* Assign the post_ram_clear function, if defined. */ + if (pdata->plat_post_ram_clear != NULL) + rtc->post_ram_clear = pdata->plat_post_ram_clear; + + /* Init the spinlock, workqueue, denouncer, & set the driver data. */ + spin_lock_init(&rtc->lock); + INIT_WORK(&rtc->work, ds1685_rtc_work_queue); + platform_set_drvdata(pdev, rtc); + + /* Turn the oscillator on if is not already on (DV1 = 1). */ + ctrla = ds1685_read(rtc, RTC_CTRL_A); + if (!(ctrla & RTC_CTRL_A_DV1)) + ctrla |= RTC_CTRL_A_DV1; + + /* Enable the countdown chain (DV2 = 0) */ + ctrla &= ~(RTC_CTRL_A_DV2); + + /* Clear RS3-RS0 in Control A. */ + ctrla &= ~(RTC_CTRL_A_RS_MASK); + + /* + * All done with Control A. Switch to Bank 1 for the remainder of + * the RTC setup so we have access to the extended functions. + */ + ctrla |= RTC_CTRL_A_DV0; + ds1685_write(rtc, RTC_CTRL_A, ctrla); + + /* Default to 32768kHz output. */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K)); + + /* + * Set the SET bit in Control B so we can do some housekeeping. + * We do not check UIP in Control A because this is a one-time + * thing during driver setup and we'll just hope that we don't + * hit in the middle of an update. + */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); + + /* Force BCD mode (DM = 0). */ + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + if (ctrlb & RTC_CTRL_B_DM) + ctrlb &= ~(RTC_CTRL_B_DM); + + /* + * Disable Daylight Savings Time (DSE = 0). + * The RTC has hardcoded timezone information that is rendered + * obselete. We'll let the OS deal with DST settings instead. + */ + if (ctrlb & RTC_CTRL_B_DSE) + ctrlb &= ~(RTC_CTRL_B_DSE); + + /* Force 24-hour mode (2412 = 1). */ + if (!(ctrlb & RTC_CTRL_B_2412)) { + /* Reinitialize the time hours. */ + hours = ds1685_read(rtc, RTC_HOURS); + am_pm = hours & RTC_HOURS_AMPM_MASK; + hours = bcd2bin(hours & RTC_HOURS_12_MASK); + hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); + + /* Enable 24-hour mode. */ + ctrlb |= RTC_CTRL_B_2412; + + /* Write back to Control B, including DM & DSE bits. */ + ds1685_write(rtc, RTC_CTRL_B, ctrlb); + + /* Write the time hours back. */ + ds1685_write(rtc, RTC_HOURS, + bin2bcd(hours) & RTC_HOURS_24_MASK); + + /* Reinitialize the alarm hours. */ + hours = ds1685_read(rtc, RTC_HOURS_ALARM); + am_pm = hours & RTC_HOURS_AMPM_MASK; + hours = bcd2bin(hours & RTC_HOURS_12_MASK); + hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); + + /* Write the alarm hours back. */ + ds1685_write(rtc, RTC_HOURS_ALARM, + bin2bcd(hours) & RTC_HOURS_24_MASK); + } else { + /* 24-hour mode is already set, so write Control B back. */ + ds1685_write(rtc, RTC_CTRL_B, ctrlb); + } + + /* Unset the SET bit in Control B so the RTC can update. */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); + + /* Check the main battery. */ + if (!(ds1685_read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT)) + dev_warn(&pdev->dev, + "Main battery is exhausted! RTC may be invalid!\n"); + + /* Check the auxillary battery. It is optional. */ + if (!(ds1685_read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2)) + dev_warn(&pdev->dev, + "Aux battery is exhausted or not available.\n"); + + /* Fetch the IRQ and setup the interrupt handler. */ + rtc->irq = platform_get_irq(pdev, 0); + if (rtc->irq > 0) { + /* Read Ctrl B and clear PIE/AIE/UIE. */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & + ~(RTC_CTRL_B_PAU_MASK))); + + /* Reading Ctrl C auto-clears PF/AF/UF. */ + ds1685_read(rtc, RTC_CTRL_C); + + /* Read Ctrl 4B and clear RIE/WIE/KSE. */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) & + ~(RTC_CTRL_4B_RWK_MASK))); + + /* Manually clear RF/WF/KF in Ctrl 4A. */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) & + ~(RTC_CTRL_4A_RWK_MASK))); + + /* Request an IRQ. */ + ret = devm_request_irq(&pdev->dev, rtc->irq, + ds1685_rtc_irq_handler, + IRQF_SHARED, pdev->name, pdev); + + /* Check to see if something came back. */ + if (unlikely(ret)) { + dev_warn(&pdev->dev, + "RTC interrupt not available\n"); + rtc->irq = 0; + } else { + /* + * Re-enable KSE to handle power button events. We + * do not enable WIE or RIE by default. + */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) | + RTC_CTRL_4B_KSE)); + } + } + + /* Setup complete. */ + ds1685_rtc_switch_to_bank0(rtc); + + /* Register the device as an RTC. */ + rtc_dev = rtc_device_register(pdev->name, &pdev->dev, + &ds1685_rtc_ops, THIS_MODULE); + + /* Success? */ + if (IS_ERR(rtc_dev)) + return PTR_ERR(rtc_dev); + + /* Maximum periodic rate is 8192Hz (0.122070ms). */ + rtc_dev->max_user_freq = RTC_MAX_USER_FREQ; + + rtc->dev = rtc_dev; + +#ifdef CONFIG_SYSFS + ret = ds1685_rtc_sysfs_register(&pdev->dev); + if (ret) + rtc_device_unregister(rtc->dev); +#endif + + /* Done! */ + return ret; +} + + +/** + * ds1685_rtc_remove - removes rtc driver. + * @pdev: pointer to platform_device structure. + */ +static int __devexit +ds1685_rtc_remove(struct platform_device *pdev) +{ + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + +#ifdef CONFIG_SYSFS + ds1685_rtc_sysfs_unregister(&pdev->dev); +#endif + + rtc_device_unregister(rtc->dev); + if (rtc->irq > 0) { + /* Read Ctrl B and clear PIE/AIE/UIE. */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & + ~(RTC_CTRL_B_PAU_MASK))); + + /* Reading Ctrl C auto-clears PF/AF/UF. */ + ds1685_read(rtc, RTC_CTRL_C); + + /* Read Ctrl 4B and clear RIE/WIE/KSE. */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) & + ~(RTC_CTRL_4B_RWK_MASK))); + + /* Manually clear RF/WF/KF in Ctrl 4A. */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) & + ~(RTC_CTRL_4A_RWK_MASK))); + } + flush_scheduled_work(); + + return 0; +} + + +/** + * ds1685_rtc_driver - rtc driver properties. + */ +static struct platform_driver ds1685_rtc_driver = { + .driver = { + .name = "rtc-ds1685", + .owner = THIS_MODULE, + }, + .probe = ds1685_rtc_probe, + .remove = __devexit_p(ds1685_rtc_remove), +}; + + +/** + * ds1685_rtc_init - rtc module init. + */ +static int __init +ds1685_rtc_init(void) +{ + return platform_driver_register(&ds1685_rtc_driver); +} + + +/** + * ds1685_rtc_exit - rtc module exit. + */ +static void __exit +ds1685_rtc_exit(void) +{ + platform_driver_unregister(&ds1685_rtc_driver); +} + +module_init(ds1685_rtc_init); +module_exit(ds1685_rtc_exit); +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* Poweroff function */ + +/** + * ds1685_rtc_poweroff - uses the RTC chip to power the system off. + * @pdev: pointer to platform_device structure. + */ +extern void ATTRIB_NORET +ds1685_rtc_poweroff(struct platform_device *pdev) +{ + u8 ctrla, ctrl4a, ctrl4b; + struct ds1685_priv *rtc; + + /* Check for valid RTC data, else, spin forever. */ + if (unlikely(!pdev)) + while (1); + else { + /* Get the rtc data. */ + rtc = platform_get_drvdata(pdev); + + /* + * Disable our IRQ. We're powering down, so we're not + * going to worry about cleaning up. Most of that should + * be taken care of by the shutdown scripts and we're the + * final call. + */ + disable_irq_nosync(rtc->irq); + + /* Ocsillator must be on and the countdown chain enabled. */ + ctrla = ds1685_read(rtc, RTC_CTRL_A); + ctrla |= RTC_CTRL_A_DV1; + ctrla &= ~(RTC_CTRL_A_DV2); + ds1685_write(rtc, RTC_CTRL_A, ctrla); + + /* + * Read Control 4A and check the status of the auxillary + * battery. This must be present and working (VRT2 = 1) + * for wakeup and kickstart functionality to be useful. + */ + ds1685_rtc_switch_to_bank1(rtc); + ctrl4a = ds1685_read(rtc, RTC_EXT_CTRL_4A); + if (ctrl4a & RTC_CTRL_4A_VRT2) { + /* Clear all the interrupt flags on Control 4A. */ + ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK); + ds1685_write(rtc, RTC_EXT_CTRL_4A, ctrl4a); + + /* + * The auxillary battery is present and working. + * Enable extended functions (ABE=1), enable + * wake-up (WUE=1), and enable kickstart (KSE=1) + * in Control 4B. + */ + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + ctrl4b |= RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE | + RTC_CTRL_4B_KSE; + ds1685_write(rtc, RTC_EXT_CTRL_4B, ctrl4b); + } + + /* Set PAB to 1 in Control 4A to power the system down. */ + printk(KERN_EMERG "Powerdown.\n"); + msleep(10); + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ctrl4a | RTC_CTRL_4A_PAB)); + + /* Spin ... we do not switch back to bank0. */ + while (1); + } +} +EXPORT_SYMBOL(ds1685_rtc_poweroff); +/* ----------------------------------------------------------------------- */ + + +MODULE_AUTHOR("Joshua Kinard "); +MODULE_AUTHOR("Matthias Fuchs "); +MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:rtc-ds1685"); diff -Naurp linux-2.6.orig/include/linux/rtc/ds1685.h linux-2.6.rtc/include/linux/rtc/ds1685.h - --- linux-2.6.orig/include/linux/rtc/ds1685.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.rtc/include/linux/rtc/ds1685.h 2011-04-07 07:22:55.593871001 -0400 @@ -0,0 +1,334 @@ +/* + * Definitions for the registers, addresses, and platform data of the + * DS1685/DS1687-series RTC chips. + * + * This Driver also works for the DS17X85/DS17X87 RTC chips. Functionally + * similar to the DS1685/DS1687, they support a few extra features which + * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC + * write counter. + * + * Copyright (C) 2009 Matthias Fuchs + * Copyright (C) 2011 Joshua Kinard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_RTC_DS1685_H_ +#define _LINUX_RTC_DS1685_H_ + +#include +#include +#include + +/** + * struct ds1685_priv - DS1685 private data structure. + * @dev: pointer to the rtc_device structure. + * @regs: iomapped base address pointer of the RTC registers. + * @regstep: padding/step size between registers (optional). + * @baseaddr: base address of the RTC device. + * @size: resource size. + * @lock: private lock variable for spin locking/unlocking. + * @work: private workqueue. + * @irq: IRQ number assigned to the RTC device. + * @prepare_poweroff: pointer to platform pre-poweroff function. + * @wake_alarm: pointer to platform wake alarm function. + * @post_ram_clear: pointer to platform post ram-clear function. + */ +struct ds1685_priv { + struct rtc_device *dev; + void __iomem *regs; + u32 regstep; + resource_size_t baseaddr; + size_t size; + spinlock_t lock; + struct work_struct work; + int irq; + void (*prepare_poweroff)(void); + void (*wake_alarm)(void); + void (*post_ram_clear)(void); +}; + + +/** + * struct ds1685_rtc_platform_data - platform data structure. + * @plat_prepare_poweroff: platform-specific pre-poweroff function. + * @plat_wake_alarm: platform-specific wake alarm function. + * @plat_post_ram_clear: platform-specific post ram-clear function. + * + * If your platform needs to use a custom padding/step size between + * registers, or uses one or more of the extended interrupts and needs special + * handling, then include this header file in your platform definition and + * set regstep and the plat_* pointers as appropriate. + */ +struct ds1685_rtc_platform_data { + void (*plat_prepare_poweroff)(void); + void (*plat_wake_alarm)(void); + void (*plat_post_ram_clear)(void); + const u32 regstep; +}; + + +/* + * Time Registers. + */ +#define RTC_SECONDS 0x00 /* Seconds 00-59 */ +#define RTC_SECONDS_ALARM 0x01 /* Alarm Seconds 00-59 */ +#define RTC_MINUTES 0x02 /* Minutes 00-59 */ +#define RTC_MINUTES_ALARM 0x03 /* Alarm Minutes 00-59 */ +#define RTC_HOURS 0x04 /* Hours 01-12 AM/PM || 00-23 */ +#define RTC_HOURS_ALARM 0x05 /* Alarm Hours 01-12 AM/PM || 00-23 */ +#define RTC_WDAY 0x06 /* Day of Week 01-07 */ +#define RTC_MDAY 0x07 /* Day of Month 01-31 */ +#define RTC_MONTH 0x08 /* Month 01-12 */ +#define RTC_YEAR 0x09 /* Year 00-99 */ +#define RTC_CENTURY 0x48 /* Century 00-99 */ +#define RTC_MDAY_ALARM 0x49 /* Alarm Day of Month 01-31 */ + + +/* + * Bit masks for the Time registers in BCD Mode (DM = 0). + */ +#define RTC_SECONDS_MASK 0x7f /* - x x x x x x x */ +#define RTC_MINUTES_MASK 0x7f /* - x x x x x x x */ +#define RTC_HOURS_12_MASK 0x1f /* - - - x x x x x */ +#define RTC_HOURS_24_MASK 0x3f /* - - x x x x x x */ +#define RTC_WDAY_MASK 0x07 /* - - - - - x x x */ +#define RTC_MDAY_MASK 0x3f /* - - x x x x x x */ +#define RTC_MONTH_MASK 0x1f /* - - - x x x x x */ +#define RTC_YEAR_MASK 0xff /* x x x x x x x x */ +#define RTC_CENTURY_MASK 0xff /* x x x x x x x x */ +#define RTC_HOURS_AMPM_MASK BIT(7) /* Mask for the AM/PM bit */ + + +/* + * Control Registers. + */ +#define RTC_CTRL_A 0x0a /* Control Register A */ +#define RTC_CTRL_B 0x0b /* Control Register B */ +#define RTC_CTRL_C 0x0c /* Control Register C */ +#define RTC_CTRL_D 0x0d /* Control Register D */ +#define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */ +#define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */ + + +/* + * Bit names in Control Register A. + */ +#define RTC_CTRL_A_UIP BIT(7) /* Update In Progress */ +#define RTC_CTRL_A_DV2 BIT(6) /* Countdown Chain */ +#define RTC_CTRL_A_DV1 BIT(5) /* Oscillator Enable */ +#define RTC_CTRL_A_DV0 BIT(4) /* Bank Select */ +#define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */ +#define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */ +#define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */ +#define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */ +#define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */ + +/* + * Bit names in Control Register B. + */ +#define RTC_CTRL_B_SET BIT(7) /* SET Bit */ +#define RTC_CTRL_B_PIE BIT(6) /* Periodic-Interrupt Enable */ +#define RTC_CTRL_B_AIE BIT(5) /* Alarm-Interrupt Enable */ +#define RTC_CTRL_B_UIE BIT(4) /* Update-Ended Interrupt-Enable */ +#define RTC_CTRL_B_SQWE BIT(3) /* Square-Wave Enable */ +#define RTC_CTRL_B_DM BIT(2) /* Data Mode */ +#define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */ +#define RTC_CTRL_B_DSE BIT(0) /* Daylight Savings Enable */ +#define RTC_CTRL_B_PAU_MASK 0x70 /* PIE + AIE + UIE */ + + +/* + * Bit names in Control Register C. + * + * BIT(0), BIT(1), BIT(2), & BIT(3) are unused, always return 0, and cannot + * be written to. + */ +#define RTC_CTRL_C_IRQF BIT(7) /* Interrupt-Request Flag */ +#define RTC_CTRL_C_PF BIT(6) /* Periodic-Interrupt Flag */ +#define RTC_CTRL_C_AF BIT(5) /* Alarm-Interrupt Flag */ +#define RTC_CTRL_C_UF BIT(4) /* Update-Ended Interrupt Flag */ +#define RTC_CTRL_C_PAU_MASK 0x70 /* PF + AF + UF */ + + +/* + * Bit names in Control Register D. + * + * BIT(0) through BIT(6) are unused, always return 0, and cannot + * be written to. + */ +#define RTC_CTRL_D_VRT BIT(7) /* Valid RAM and Time */ + + +/* + * Bit names in Extended Control Register 4A. + * + * On the DS1685/DS1687/DS1689/DS1693, BIT(4) and BIT(5) are reserved for + * future use. They can be read from and written to, but have no effect + * on the RTC's operation. + * + * On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows + * access to the extended NV-SRAM by automatically incrementing the address + * register when they are read from or written to. + */ +#define RTC_CTRL_4A_VRT2 BIT(7) /* Auxillary Battery Status */ +#define RTC_CTRL_4A_INCR BIT(6) /* Increment-in-Progress Status */ +#define RTC_CTRL_4A_PAB BIT(3) /* Power-Active Bar Control */ +#define RTC_CTRL_4A_RF BIT(2) /* RAM-Clear Flag */ +#define RTC_CTRL_4A_WF BIT(1) /* Wake-Up Alarm Flag */ +#define RTC_CTRL_4A_KF BIT(0) /* Kickstart Flag */ +#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) +#define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */ +#endif +#define RTC_CTRL_4A_RWK_MASK 0x07 /* RF + WF + KF */ + + +/* + * Bit names in Extended Control Register 4B. + */ +#define RTC_CTRL_4B_ABE BIT(7) /* Auxillary Battery Enable */ +#define RTC_CTRL_4B_E32K BIT(6) /* Enable 32.768Hz on SQW Pin */ +#define RTC_CTRL_4B_CS BIT(5) /* Crystal Select */ +#define RTC_CTRL_4B_RCE BIT(4) /* RAM Clear-Enable */ +#define RTC_CTRL_4B_PRS BIT(3) /* PAB Reset-Select */ +#define RTC_CTRL_4B_RIE BIT(2) /* RAM Clear-Interrupt Enable */ +#define RTC_CTRL_4B_WIE BIT(1) /* Wake-Up Alarm-Interrupt Enable */ +#define RTC_CTRL_4B_KSE BIT(0) /* Kickstart Interrupt-Enable */ +#define RTC_CTRL_4B_RWK_MASK 0x07 /* RIE + WIE + KSE */ + + +/* + * Misc register names in Bank 1. + * + * The DV0 bit in Control Register A must be set to 1 for these registers + * to become available, including Extended Control Registers 4A & 4B. + */ +#define RTC_BANK1_SSN_MODEL 0x40 /* Model Number */ +#define RTC_BANK1_SSN_BYTE_1 0x41 /* 1st Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_2 0x42 /* 2nd Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_3 0x43 /* 3rd Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_4 0x44 /* 4th Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_5 0x45 /* 5th Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_6 0x46 /* 6th Byte of Serial Number */ +#define RTC_BANK1_SSN_CRC 0x47 /* Serial CRC Byte */ +#define RTC_BANK1_RAM_DATA_PORT 0x53 /* Extended RAM Data Port */ + + +/* + * Model-specific registers in Bank 1. + * + * The addresses below differ depending on the model of the RTC chip + * selected in the kernel configuration. Not all of these features are + * supported in the main driver at present. + * + * DS1685/DS1687 - Extended NV-SRAM address (LSB only). + * DS1689/DS1693 - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N. + * DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter. + */ +#if defined(CONFIG_RTC_DRV_DS1685) +#define RTC_BANK1_RAM_ADDR 0x50 /* NV-SRAM Addr */ +#elif defined(CONFIG_RTC_DRV_DS1689) +#define RTC_BANK1_VCC_CTR_LSB 0x54 /* Vcc Counter Addr (LSB) */ +#define RTC_BANK1_VCC_CTR_MSB 0x57 /* Vcc Counter Addr (MSB) */ +#define RTC_BANK1_VBAT_CTR_LSB 0x58 /* Vbat Counter Addr (LSB) */ +#define RTC_BANK1_VBAT_CTR_MSB 0x5b /* Vbat Counter Addr (MSB) */ +#define RTC_BANK1_PWR_CTR_LSB 0x5c /* Pwr Cycle Counter Addr (LSB) */ +#define RTC_BANK1_PWR_CTR_MSB 0x5d /* Pwr Cycle Counter Addr (MSB) */ +#define RTC_BANK1_UNIQ_SN 0x60 /* Customer-specific S/N */ +#else /* DS17x85/DS17x87 */ +#define RTC_BANK1_RAM_ADDR_LSB 0x50 /* NV-SRAM Addr (LSB) */ +#define RTC_BANK1_RAM_ADDR_MSB 0x51 /* NV-SRAM Addr (MSB) */ +#define RTC_BANK1_WRITE_CTR 0x5e /* RTC Write Counter */ +#endif + + +/* + * Model numbers. + * + * The DS1688/DS1691 and DS1689/DS1693 chips share the same model number + * and the manual doesn't indicate any major differences. As such, they + * are regarded as the same chip in this driver. + */ +#define RTC_MODEL_DS1685 0x71 /* DS1685/DS1687 */ +#define RTC_MODEL_DS17285 0x72 /* DS17285/DS17287 */ +#define RTC_MODEL_DS1689 0x73 /* DS1688/DS1691/DS1689/DS1693 */ +#define RTC_MODEL_DS17485 0x74 /* DS17485/DS17487 */ +#define RTC_MODEL_DS17885 0x78 /* DS17885/DS17887 */ + + +/* + * Periodic Interrupt Rates / Square-Wave Output Frequency + * + * Periodic rates are selected by setting the RS3-RS0 bits in Control + * Register A and enabled via either the E32K bit in Extended Control + * Register 4B or the SQWE bit in Control Register B. + * + * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz + * on the SQW pin of the RTC chip. While there are 16 possible selections, + * the 1-of-16 decoder is only able to divide the base 32768Hz signal into + * 13 smaller frequencies. The values 0x01 and 0x02 are not used and are + * synonymous with 0x08 and 0x09, respectively. + * + * When E32K is set to a logic 1, periodic interrupts are disabled and + * reading /dev/rtc will return -EINVAL. This also applies if the periodic + * interrupt frequency is set to 0Hz. + */ + /* E32K RS3 RS2 RS1 RS0 */ +#define RTC_SQW_8192HZ 0x03 /* 0 0 0 1 1 */ +#define RTC_SQW_4096HZ 0x04 /* 0 0 1 0 0 */ +#define RTC_SQW_2048HZ 0x05 /* 0 0 1 0 1 */ +#define RTC_SQW_1024HZ 0x06 /* 0 0 1 1 0 */ +#define RTC_SQW_512HZ 0x07 /* 0 0 1 1 1 */ +#define RTC_SQW_256HZ 0x08 /* 0 1 0 0 0 */ +#define RTC_SQW_128HZ 0x09 /* 0 1 0 0 1 */ +#define RTC_SQW_64HZ 0x0a /* 0 1 0 1 0 */ +#define RTC_SQW_32HZ 0x0b /* 0 1 0 1 1 */ +#define RTC_SQW_16HZ 0x0c /* 0 1 1 0 0 */ +#define RTC_SQW_8HZ 0x0d /* 0 1 1 0 1 */ +#define RTC_SQW_4HZ 0x0e /* 0 1 1 1 0 */ +#define RTC_SQW_2HZ 0x0f /* 0 1 1 1 1 */ +#define RTC_SQW_0HZ 0x00 /* 0 0 0 0 0 */ +#define RTC_SQW_32768HZ 32768 /* 1 - - - - */ +#define RTC_MAX_USER_FREQ 8192 + + +/* + * NVRAM data & addresses: + * - 50 bytes of NVRAM are available just past the clock registers. + * - 64 additional bytes are available in Bank0. + * + * Extended, battery-backed NV-SRAM: + * - DS1685/DS1687 - 128 bytes. + * - DS1689/DS1693 - 0 bytes. + * - DS17285/DS17287 - 2048 bytes. + * - DS17485/DS17487 - 4096 bytes. + * - DS17885/DS17887 - 8192 bytes. + */ +#define NVRAM_TIME_BASE 0x0e /* NVRAM Addr in Time regs */ +#define NVRAM_BANK0_BASE 0x40 /* NVRAM Addr in Bank0 regs */ +#define NVRAM_SZ_TIME 50 +#define NVRAM_SZ_BANK0 64 +#if defined(CONFIG_RTC_DRV_DS1685) +# define NVRAM_SZ_EXTND 128 +#elif defined(CONFIG_RTC_DRV_DS1689) +# define NVRAM_SZ_EXTND 0 +#elif defined(CONFIG_RTC_DRV_DS17285) +# define NVRAM_SZ_EXTND 2048 +#elif defined(CONFIG_RTC_DRV_DS17485) +# define NVRAM_SZ_EXTND 4096 +#elif defined(CONFIG_RTC_DRV_DS17885) +# define NVRAM_SZ_EXTND 8192 +#endif +#define NVRAM_TOTAL_SZ_BANK0 (NVRAM_SZ_TIME + NVRAM_SZ_BANK0) +#define NVRAM_TOTAL_SZ (NVRAM_TOTAL_SZ_BANK0 + NVRAM_SZ_EXTND) + + +/* + * Function Prototypes. + */ +extern void ATTRIB_NORET + ds1685_rtc_poweroff(struct platform_device *pdev); + +#endif /* _LINUX_RTC_DS1685_H_ */ -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.17 (MingW32) iQIcBAEBAgAGBQJNnbjyAAoJENsjoH7SXZXj7jgP/3PIt0+GnVRcEv4jUyYhCRLR /huNyWEWUy3F82tnZ7H6Ti5gx6soUYaIAgWzN/TB4WEDiiH0Zx7TtL9GvRkb5kPJ Eo/WFBh4Y64JCQOv/LDO2AcxJeD4u+BuZmFn0k6fZLQK0KCIxe7BvouQgNO028AR QnSE5V9f0trJtRr8h+Zg7/IRvH+X9wVezYTXzZZKeMBQMmwb4nB5NcpJi0gmJwlh hemRQ/Pkc0snExBtPN03FSFbte3fSUzXVt035/4GCEryLllPp9Cv52hAoqJcd8Rx 085OSN2R2B4hX9RvGxjQEeskjieKNzNsnCvSXejeGLLkcAo3lbkYpHGvvRJb0UdA y3ZYJCWrWjrfQrlF+sxhIIUwpy01tyj9748uofh4wffdRImgad7q6K5x3IXKmRCK 5SUgrJFcFW28Cf5JYlRyEtwR+YiIR4DQYNmPlQisShVrMmmeRedj+pCrprR/YAwu H/fUHE9jaydTnjR3WLVQlwoLuP0MpwfYQtMsZWB2O15aZSJbaK3+/2kH7lVojFaA s4ZepDkdwDz0lBsBZcn4s+PYkkQEvvUmINaa3uqLScn37SQVutWrvYa3jK6wrDyO +PpAFQ0ZcovQaZs1LC9QeqOjuUtj/mrqxvROe/T1UVu+wqATGEVcZACHJVD2A4EK dOsqIgAuLAU7trIuLlKF =tge7 -----END PGP SIGNATURE----- From kumba@gentoo.org Thu Apr 7 15:18:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 15:18:33 +0200 (CEST) Received: from qmta08.emeryville.ca.mail.comcast.net ([76.96.30.80]:49737 "EHLO qmta08.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491062Ab1DGNS3 (ORCPT ); Thu, 7 Apr 2011 15:18:29 +0200 Received: from omta16.emeryville.ca.mail.comcast.net ([76.96.30.72]) by qmta08.emeryville.ca.mail.comcast.net with comcast id Ud4M1g0061ZMdJ4A8dJNxp; Thu, 07 Apr 2011 13:18:22 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta16.emeryville.ca.mail.comcast.net with comcast id UdJL1g0073XYSBH8cdJMdo; Thu, 07 Apr 2011 13:18:22 +0000 Message-ID: <4D9DB95F.8040100@gentoo.org> Date: Thu, 07 Apr 2011 09:17:19 -0400 From: Joshua Kinard User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 MIME-Version: 1.0 To: Linux MIPS List , Ralf Baechle CC: rtc-linux@googlegroups.com, LKML , Alessandro Zummo Subject: [PATCH 2/2]: MIPS: sgi-ip32: Add support for rtc-ds1685 to SGI O2 (IP32) X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29703 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 These are the modifications needed to the SGI O2 (IP32) codebase to switch off of rtc-cmos to rtc-ds1685. It needs to be applied after the main rtc-ds1685 patch. Key changes here eliminate the custom power-off code and call upon the version built into the main driver via platform_data, as well as defining the required register step-size of 256 bytes (0x100). Signed-off-by: Joshua Kinard - --- include/asm/mach-ip32/mc146818rtc.h | 36 ---------- sgi-ip32/ip32-platform.c | 49 ++++++++++++-- sgi-ip32/ip32-reset.c | 118 ++++++++---------------------------- 3 files changed, 67 insertions(+), 136 deletions(-) diff -Naurp mipslinux.orig/arch/mips/include/asm/mach-ip32/mc146818rtc.h mipslinux.ip32-rtc/arch/mips/include/asm/mach-ip32/mc146818rtc.h - --- mipslinux.orig/arch/mips/include/asm/mach-ip32/mc146818rtc.h 2009-04-28 20:29:27.000000000 -0400 +++ mipslinux.ip32-rtc/arch/mips/include/asm/mach-ip32/mc146818rtc.h 1969-12-31 19:00:00.000000000 -0500 @@ -1,36 +0,0 @@ - -/* - - * This file is subject to the terms and conditions of the GNU General Public - - * License. See the file "COPYING" in the main directory of this archive - - * for more details. - - * - - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - - * Copyright (C) 2000 Harald Koerfgen - - * - - * RTC routines for IP32 style attached Dallas chip. - - */ - -#ifndef __ASM_MACH_IP32_MC146818RTC_H - -#define __ASM_MACH_IP32_MC146818RTC_H - - - -#include - - - -#define RTC_PORT(x) (0x70 + (x)) - - - -static unsigned char CMOS_READ(unsigned long addr) - -{ - - return mace->isa.rtc[addr << 8]; - -} - - - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) - -{ - - mace->isa.rtc[addr << 8] = data; - -} - - - -/* - - * FIXME: Do it right. For now just assume that noone lives in 20th century - - * and no O2 user in 22th century ;-) - - */ - -#define mc146818_decode_year(year) ((year) + 2000) - - - -#define RTC_ALWAYS_BCD 0 - - - -#endif /* __ASM_MACH_IP32_MC146818RTC_H */ diff -Naurp mipslinux.orig/arch/mips/sgi-ip32/ip32-platform.c mipslinux.ip32-rtc/arch/mips/sgi-ip32/ip32-platform.c - --- mipslinux.orig/arch/mips/sgi-ip32/ip32-platform.c 2009-04-28 20:29:28.000000000 -0400 +++ mipslinux.ip32-rtc/arch/mips/sgi-ip32/ip32-platform.c 2011-04-07 08:02:00.063871001 -0400 @@ -9,10 +9,13 @@ #include #include #include +#include #include #include +extern void inline ip32_prepare_poweroff(void); + #define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1) #define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2) @@ -90,22 +93,50 @@ static __init int sgio2btns_devinit(void device_initcall(sgio2btns_devinit); - -static struct resource sgio2_cmos_rsrc[] = { +#define MACE_RTC_RES_START (MACE_BASE + offsetof(struct sgi_mace, isa.rtc)) +#define MACE_RTC_RES_END (MACE_RTC_RES_START + 32767) + +static struct resource ip32_rtc_resources[] = { { - - .start = 0x70, - - .end = 0x71, - - .flags = IORESOURCE_IO + .start = MACEISA_RTC_IRQ, + .end = MACEISA_RTC_IRQ, + .flags = IORESOURCE_IRQ + }, { + .start = MACE_RTC_RES_START, + .end = MACE_RTC_RES_END, + .flags = IORESOURCE_MEM, } }; - -static __init int sgio2_cmos_devinit(void) + +/* RTC registers on IP32 are each padded by 256 bytes (0x100). */ +static struct ds1685_rtc_platform_data +ip32_rtc_platform_data[] = { + { + .regstep = 0x100, + .plat_prepare_poweroff = ip32_prepare_poweroff, + }, +}; + +struct platform_device ip32_rtc_device = { + .name = "rtc-ds1685", + .id = -1, + .dev = { + .platform_data = ip32_rtc_platform_data, + }, + .num_resources = ARRAY_SIZE(ip32_rtc_resources), + .resource = ip32_rtc_resources, +}; +EXPORT_SYMBOL(ip32_rtc_device); + +static int __init sgio2_rtc_devinit(void) { - - return IS_ERR(platform_device_register_simple("rtc_cmos", -1, - - sgio2_cmos_rsrc, 1)); + return platform_device_register(&ip32_rtc_device); + } - -device_initcall(sgio2_cmos_devinit); +device_initcall(sgio2_rtc_devinit); MODULE_AUTHOR("Ralf Baechle "); MODULE_LICENSE("GPL"); - -MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2"); +MODULE_DESCRIPTION("IP32 platform setup for SGI IP32 aka O2"); diff -Naurp mipslinux.orig/arch/mips/sgi-ip32/ip32-reset.c mipslinux.ip32-rtc/arch/mips/sgi-ip32/ip32-reset.c - --- mipslinux.orig/arch/mips/sgi-ip32/ip32-reset.c 2009-05-23 12:01:03.025842703 - -0400 +++ mipslinux.ip32-rtc/arch/mips/sgi-ip32/ip32-reset.c 2011-04-07 08:02:00.063871001 -0400 @@ -13,7 +13,7 @@ #include #include #include - -#include +#include #include #include @@ -33,55 +33,31 @@ #define POWERDOWN_FREQ (HZ / 4) #define PANIC_FREQ (HZ / 8) - -static struct timer_list power_timer, blink_timer, debounce_timer; - -static int has_panicked, shuting_down; +extern struct ds1685_rtc_platform_data ip32_rtc_platform_data[]; +extern struct platform_device ip32_rtc_device; - -static void ip32_machine_restart(char *command) __attribute__((noreturn)); - -static void ip32_machine_halt(void) __attribute__((noreturn)); - -static void ip32_machine_power_off(void) __attribute__((noreturn)); +static struct timer_list power_timer, blink_timer; +static int has_panicked, shutting_down; - -static void ip32_machine_restart(char *cmd) +static void ip32_poweroff(void *data) { - - crime->control = CRIME_CONTROL_HARD_RESET; +#if defined(CONFIG_RTC_DRV_DS1685_FAMILY) && \ + (defined(CONFIG_RTC_DRV_DS1685) || defined(CONFIG_RTC_DRV_DS17285)) + ds1685_rtc_poweroff((struct platform_device *)data); +#else while (1); +#endif } - -static inline void ip32_machine_halt(void) - -{ - - ip32_machine_power_off(); - -} - -static void ip32_machine_power_off(void) +static void ip32_machine_restart(char *cmd) __attribute__((noreturn)); +static void ip32_machine_restart(char *cmd) { - - unsigned char reg_a, xctrl_a, xctrl_b; - - - - disable_irq(MACEISA_RTC_IRQ); - - reg_a = CMOS_READ(RTC_REG_A); - - - - /* setup for kickstart & wake-up (DS12287 Ref. Man. p. 19) */ - - reg_a &= ~DS_REGA_DV2; - - reg_a |= DS_REGA_DV1; - - - - CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); - - wbflush(); - - xctrl_b = CMOS_READ(DS_B1_XCTRL4B) - - | DS_XCTRL4B_ABE | DS_XCTRL4B_KFE; - - CMOS_WRITE(xctrl_b, DS_B1_XCTRL4B); - - xctrl_a = CMOS_READ(DS_B1_XCTRL4A) & ~DS_XCTRL4A_IFS; - - CMOS_WRITE(xctrl_a, DS_B1_XCTRL4A); - - wbflush(); - - /* adios amigos... */ - - CMOS_WRITE(xctrl_a | DS_XCTRL4A_PAB, DS_B1_XCTRL4A); - - CMOS_WRITE(reg_a, RTC_REG_A); - - wbflush(); + msleep(10); + crime->control = CRIME_CONTROL_HARD_RESET; while (1); } - -static void power_timeout(unsigned long data) - -{ - - ip32_machine_power_off(); - -} - - static void blink_timeout(unsigned long data) { unsigned long led = mace->perif.ctrl.misc ^ MACEISA_LED_RED; @@ -89,44 +65,27 @@ static void blink_timeout(unsigned long mod_timer(&blink_timer, jiffies + data); } - -static void debounce(unsigned long data) +static void ip32_machine_halt(void) { - - unsigned char reg_a, reg_c, xctrl_a; - - - - reg_c = CMOS_READ(RTC_INTR_FLAGS); - - reg_a = CMOS_READ(RTC_REG_A); - - CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); - - wbflush(); - - xctrl_a = CMOS_READ(DS_B1_XCTRL4A); - - if ((xctrl_a & DS_XCTRL4A_IFS) || (reg_c & RTC_IRQF )) { - - /* Interrupt still being sent. */ - - debounce_timer.expires = jiffies + 50; - - add_timer(&debounce_timer); - - - - /* clear interrupt source */ - - CMOS_WRITE(xctrl_a & ~DS_XCTRL4A_IFS, DS_B1_XCTRL4A); - - CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); - - return; - - } - - CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); - - - - if (has_panicked) - - ip32_machine_restart(NULL); + ip32_poweroff(&ip32_rtc_device); +} - - enable_irq(MACEISA_RTC_IRQ); +static void power_timeout(unsigned long data) +{ + ip32_poweroff(&ip32_rtc_device); } - -static inline void ip32_power_button(void) +void ip32_prepare_poweroff(void) { if (has_panicked) return; - - if (shuting_down || kill_cad_pid(SIGINT, 1)) { + if (shutting_down || kill_cad_pid(SIGINT, 1)) { /* No init process or button pressed twice. */ - - ip32_machine_power_off(); + ip32_poweroff(&ip32_rtc_device); } - - shuting_down = 1; + shutting_down = 1; blink_timer.data = POWERDOWN_FREQ; blink_timeout(POWERDOWN_FREQ); @@ -135,27 +94,7 @@ static inline void ip32_power_button(voi power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ; add_timer(&power_timer); } - - - -static irqreturn_t ip32_rtc_int(int irq, void *dev_id) - -{ - - unsigned char reg_c; - - - - reg_c = CMOS_READ(RTC_INTR_FLAGS); - - if (!(reg_c & RTC_IRQF)) { - - printk(KERN_WARNING - - "%s: RTC IRQ without RTC_IRQF\n", __func__); - - } - - /* Wait until interrupt goes away */ - - disable_irq_nosync(MACEISA_RTC_IRQ); - - init_timer(&debounce_timer); - - debounce_timer.function = debounce; - - debounce_timer.expires = jiffies + 50; - - add_timer(&debounce_timer); - - - - printk(KERN_DEBUG "Power button pressed\n"); - - ip32_power_button(); - - return IRQ_HANDLED; - -} +EXPORT_SYMBOL(ip32_prepare_poweroff); static int panic_event(struct notifier_block *this, unsigned long event, void *ptr) @@ -190,15 +129,12 @@ static __init int ip32_reboot_setup(void _machine_restart = ip32_machine_restart; _machine_halt = ip32_machine_halt; - - pm_power_off = ip32_machine_power_off; + pm_power_off = ip32_machine_halt; init_timer(&blink_timer); blink_timer.function = blink_timeout; atomic_notifier_chain_register(&panic_notifier_list, &panic_block); - - if (request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL)) - - panic("Can't allocate MACEISA RTC IRQ"); - - return 0; } -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.17 (MingW32) iQIcBAEBAgAGBQJNnbleAAoJENsjoH7SXZXjJvEQAL3xKzPuM69n9mTUTtkZUhDg tmjBH96abi0sI6SqvjhbiNf3UnMU+iDPkF1hi79XA1aelwolGCh31tf8lrQ2nJ5C qvbBiTyaAvzDuRBwr+mMXe5wO4bMRcJl+z1ikQQ+S52AdEmKWR2PVUbtnv0obslr wVVdQ/a0QUYcagOcFwPUPilgiftQ0/tK3Ck6FGoq7QGgDlda05Of1s/KoIBc7fB1 aZwc3z5VMaGnJuD6aAhu1BDWT3PBEMNBO73/PzpEtCsvHD/WjiAE7UwdaU9E/Rcf bpTDRa1F23qQ19ibS3EN5C7H3HtISPAo0SXr0iS+e0AsFfUCdAlQjD6v1PTXu46G 7Ryd3fYwOPBepq36IGsxvaA/Ca2PpP0SQcAScnuwUrQ3h5XKADAyj3OC1c/i//Tl Qy1pI00itnQ174a2AUCY3+3TP7IBMD849lKsjP4gsvJNP4xe/63ovNmWif1TUxgB xdzkrlTKdr8dUDUT+1YlfqPKlq6JhTbJ6cuRIOIOv+MDxDfrHLUzPe4hxIs9+8+1 Ya7yF0SznLGJ6Fftk0hm5gITl7mwmOtC7sLzzqJY8dCF7vXH4Rbz4qY83ydvoT0T U5cOh8xGETiwlgVaJ+38sy5saVeRXMcRySz6fTcuiAHB3j1JWKPUGPTuSaBsIc0/ iTe4vX2Kh3gHNt1EyA0e =r1bG -----END PGP SIGNATURE----- From sshtylyov@mvista.com Thu Apr 7 16:07:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 16:07:42 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:53394 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab1DGOHh (ORCPT ); Thu, 7 Apr 2011 16:07:37 +0200 Received: by wwb17 with SMTP id 17so2726518wwb.24 for ; Thu, 07 Apr 2011 07:07:32 -0700 (PDT) Received: by 10.216.191.208 with SMTP id g58mr865724wen.85.1302185251913; Thu, 07 Apr 2011 07:07:31 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id d6sm854006wer.2.2011.04.07.07.07.28 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Apr 2011 07:07:29 -0700 (PDT) Message-ID: <4D9DC4B7.2080706@mvista.com> Date: Thu, 07 Apr 2011 18:05:43 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH V8] MIPS: lantiq: add NOR flash support References: <1302013192-8854-1-git-send-email-blogic@openwrt.org> In-Reply-To: <1302013192-8854-1-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. John Crispin wrote: > This patch adds the driver/map for NOR devices attached to the SoC via the > External Bus Unit (EBU). > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel > Cc: David Woodhouse > Cc: Daniel Schwierzeck > Cc: linux-mips@linux-mips.org > Cc: linux-mtd@lists.infradead.org > diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c > new file mode 100644 > index 0000000..4f8c320 > --- /dev/null > +++ b/drivers/mtd/maps/lantiq.c > @@ -0,0 +1,197 @@ [...] > +/* > + * The NOR flash is connected to the same external bus unit (EBU) as PCI. > + * To make PCI work we need to enable the endianess swapping for the address s/endianess/endianness/ > + * written to the EBU. This endianess swapping works for PCI correctly but Here too. > + * fails for attached NOR devices. To workaround this we need to use a complex > + * map. The workaround involves swapping all addresses whilste probing the chip. s/whilste/whilst/ > + * Once probing is complete we stop swapping the addresses but swizzle the > + * unlock addresses to ensure that access to the NOR device works correctly. > + */ > + > +enum ltq_nor_state { > + LTQ_NOR_PROBING, > + LTQ_NOR_NORMAL > +}; > + > +static char ltq_map_name[] = "ltq_nor"; > + > +static map_word > +ltq_read16(struct map_info *map, unsigned long adr) > +{ > + unsigned long flags; > + map_word temp; > + > + if (map->map_priv_1 == LTQ_NOR_PROBING) > + adr ^= 2; > + spin_lock_irqsave(&ebu_lock, flags); > + temp.x[0] = *((__u16 *)(map->virt + adr)); Too many parens; the most external ones are not necessary. And why not just 'u16'? > + spin_unlock_irqrestore(&ebu_lock, flags); > + return temp; > +} > + > +static void > +ltq_write16(struct map_info *map, map_word d, unsigned long adr) > +{ > + unsigned long flags; > + > + if (map->map_priv_1 == LTQ_NOR_PROBING) > + adr ^= 2; > + spin_lock_irqsave(&ebu_lock, flags); > + *((__u16 *)(map->virt + adr)) = d.x[0]; Same here. > + spin_unlock_irqrestore(&ebu_lock, flags); > +} > + > +/* > + * The following 2 functions copy data between iomem and a cached memory > + * section. As memcpy() makes use of pre-fetching we cannot use it here. > + * The normal alternative of using memcpy_{to,from}io also makes use of > + * memcpy() on MIPS so it is not applicable either. We are therefore stuck > + * with having to use our own loop. > + */ > +static void > +ltq_copy_from(struct map_info *map, void *to, > + unsigned long from, ssize_t len) > +{ > + unsigned char *f = (unsigned char *) (map->virt + from); > + unsigned char *t = (unsigned char *) to; I think you should either always put a space between the type and value being cast or not -- you do both. :-) > + unsigned long flags; > + > + spin_lock_irqsave(&ebu_lock, flags); > + while (len--) > + *t++ = *f++; I'm still not sure: you've implemented only 16-bit single read/write, yet you copy byte-by-byte? Does the byte access really work? > + spin_unlock_irqrestore(&ebu_lock, flags); > +} > + [...] > +static int __init > +ltq_mtd_probe(struct platform_device *pdev) > +{ > + struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); > + struct mtd_info *ltq_mtd = NULL; > + struct mtd_partition *parts = NULL; > + struct resource *res; > + int nr_parts = 0; > + struct cfi_private *cfi; > + struct map_info *ltq_map; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + dev_err(&pdev->dev, "failed to get memory resource"); > + return -ENOENT; > + } > + res = devm_request_mem_region(&pdev->dev, res->start, > + resource_size(res), dev_name(&pdev->dev)); > + if (!res) { > + dev_err(&pdev->dev, "failed to request mem resource"); > + return -EBUSY; > + } > + > + ltq_map = kzalloc(sizeof(struct map_info), GFP_KERNEL); > + ltq_map->phys = res->start; > + ltq_map->size = resource_size(res); > + ltq_map->virt = devm_ioremap_nocache(&pdev->dev, ltq_map->phys, > + ltq_map->size); > + if (!ltq_map->virt) { > + kfree(ltq_map); You should do error cleanup in one places, using *goto* to jump to that code, to avoid duplicating the same code. > + dev_err(&pdev->dev, "failed to ioremap!\n"); > + return -EIO; Rather -ENOMEM. [...] > +int __init > +init_ltq_mtd(void) > +{ > + int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); > + > + if (ret) > + pr_err("ltq_nor: error registering platfom driver"); s/platfom/platform/ > + return ret; > +} > + > +module_init(init_ltq_mtd); How about module_exit()? WBR, Sergei From dedekind1@gmail.com Thu Apr 7 16:19:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 16:19:56 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:40055 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab1DGOTx (ORCPT ); Thu, 7 Apr 2011 16:19:53 +0200 Received: by wyb28 with SMTP id 28so2758609wyb.36 for ; Thu, 07 Apr 2011 07:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=OyXlaeCrGn3/nT1W/FGnZRrv5BU64jomkUEKgasbYQg=; b=cBqA23WSIzDzOd/ubcorMAARoz74vf1JGWq5e4It76RHI/Ls9tXusdMA7FQs6SE5z0 sHVkHJ62bo4+Qmu0V1JkNCX86sfTVPiCTXfxZs2xrFkNFzIPeF9/852l4XGZwrLBGpzL dVxn9Hlhg6Xs2jik2v7WE2QWLFpnlZJeTQcXc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; b=kVN7semO6gNIrQtO9sh2ZGPaC3yXqTbDTd884SurVj2w4F+yHWFG2/GsUzzgwl8Jb8 8ISbAr59Ztt4aA3yL4YRF/lUz4mOFRyO7eCHXPWclgZQc503F1lBbCNxARvEGq0c8qeC 2YCq+lW5dYfrkSHApP7JIuLo8Vvf7GwnK+7F0= Received: by 10.227.202.149 with SMTP id fe21mr935624wbb.205.1302185988031; Thu, 07 Apr 2011 07:19:48 -0700 (PDT) Received: from ?IPv6:::1? (shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id w12sm1087618wby.7.2011.04.07.07.19.45 (version=SSLv3 cipher=OTHER); Thu, 07 Apr 2011 07:19:46 -0700 (PDT) Subject: Re: [PATCH V8] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: Sergei Shtylyov Cc: John Crispin , linux-mips@linux-mips.org, Ralf Baechle , Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <4D9DC4B7.2080706@mvista.com> References: <1302013192-8854-1-git-send-email-blogic@openwrt.org> <4D9DC4B7.2080706@mvista.com> Content-Type: text/plain; charset="UTF-8" Date: Thu, 07 Apr 2011 17:17:03 +0300 Message-ID: <1302185823.2407.48.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29705 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips I've taken this patch to l2 tree, but I can change it with a new version easily. -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From blogic@openwrt.org Thu Apr 7 16:22:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 16:22:41 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:38584 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab1DGOWi (ORCPT ); Thu, 7 Apr 2011 16:22:38 +0200 Message-ID: <4D9DC904.1040105@openwrt.org> Date: Thu, 07 Apr 2011 16:24:04 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: dedekind1@gmail.com CC: Sergei Shtylyov , linux-mips@linux-mips.org, Ralf Baechle , Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse Subject: Re: [PATCH V8] MIPS: lantiq: add NOR flash support References: <1302013192-8854-1-git-send-email-blogic@openwrt.org> <4D9DC4B7.2080706@mvista.com> <1302185823.2407.48.camel@localhost> In-Reply-To: <1302185823.2407.48.camel@localhost> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips On 07/04/11 16:17, Artem Bityutskiy wrote: > I've taken this patch to l2 tree, but I can change it with a new version > easily. > > > let me fold the proposed changes into the patch, specially the typos :) From john@phrozen.org Thu Apr 7 16:28:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 16:28:30 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:50555 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab1DGO21 (ORCPT ); Thu, 7 Apr 2011 16:28:27 +0200 Message-ID: <4D9DCA62.2070606@phrozen.org> Date: Thu, 07 Apr 2011 16:29:54 +0200 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: dedekind1@gmail.com CC: Sergei Shtylyov , linux-mips@linux-mips.org, Ralf Baechle , Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse Subject: Re: [PATCH V8] MIPS: lantiq: add NOR flash support References: <1302013192-8854-1-git-send-email-blogic@openwrt.org> <4D9DC4B7.2080706@mvista.com> <1302185823.2407.48.camel@localhost> <4D9DC904.1040105@openwrt.org> In-Reply-To: <4D9DC904.1040105@openwrt.org> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: john@phrozen.org Precedence: bulk X-list: linux-mips On 07/04/11 16:24, John Crispin wrote: > On 07/04/11 16:17, Artem Bityutskiy wrote: >> I've taken this patch to l2 tree, but I can change it with a new version >> easily. >> >> >> > let me fold the proposed changes into the patch, specially the typos :) > > Hi, forgot to mention, this patch should go upstream via the MIPS tree thanks, John From dedekind1@gmail.com Thu Apr 7 16:31:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 16:31:52 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:42475 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab1DGObt (ORCPT ); Thu, 7 Apr 2011 16:31:49 +0200 Received: by fxm14 with SMTP id 14so2173143fxm.36 for ; Thu, 07 Apr 2011 07:31:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=KxTrPM2+kPlXwbMKmyrGzRGA1y12cmEGiOM7lJ3iXzM=; b=avJhd2HY4Saicfdd+rj96V1IO9zBmdVujWavjCguz/J1udm41PookyX4Oo0bo1kUtt UvB7BRs3NqH9EVqZmsTbkaoJ6QUdB80p22mz5QYwz3u3lXNvzOqW7IodAL5tCe3MGwnH MK5LxlxHvE9jnGgbUItRu/iPToJrM+M2RyZOs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; 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(shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id w3sm1111404bkt.5.2011.04.07.07.31.42 (version=SSLv3 cipher=OTHER); Thu, 07 Apr 2011 07:31:43 -0700 (PDT) Subject: Re: [PATCH V8] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Sergei Shtylyov , linux-mips@linux-mips.org, Ralf Baechle , Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <4D9DCA62.2070606@phrozen.org> References: <1302013192-8854-1-git-send-email-blogic@openwrt.org> <4D9DC4B7.2080706@mvista.com> <1302185823.2407.48.camel@localhost> <4D9DC904.1040105@openwrt.org> <4D9DCA62.2070606@phrozen.org> Content-Type: text/plain; charset="UTF-8" Date: Thu, 07 Apr 2011 17:28:59 +0300 Message-ID: <1302186539.2407.49.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Thu, 2011-04-07 at 16:29 +0200, John Crispin wrote: > On 07/04/11 16:24, John Crispin wrote: > > On 07/04/11 16:17, Artem Bityutskiy wrote: > >> I've taken this patch to l2 tree, but I can change it with a new version > >> easily. > >> > >> > >> > > let me fold the proposed changes into the patch, specially the typos :) > > > > > > Hi, > > forgot to mention, this patch should go upstream via the MIPS tree Oh, then I'm dropping it. -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From sshtylyov@mvista.com Thu Apr 7 16:33:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 16:33:27 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:56255 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab1DGOdX (ORCPT ); Thu, 7 Apr 2011 16:33:23 +0200 Received: by wyb28 with SMTP id 28so2773857wyb.36 for ; Thu, 07 Apr 2011 07:33:18 -0700 (PDT) Received: by 10.216.79.6 with SMTP id h6mr485270wee.68.1302186798387; Thu, 07 Apr 2011 07:33:18 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id m73sm863829wej.40.2011.04.07.07.33.15 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Apr 2011 07:33:16 -0700 (PDT) Message-ID: <4D9DCAC3.9090607@mvista.com> Date: Thu, 07 Apr 2011 18:31:31 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V5 05/10] MIPS: lantiq: add watchdog support References: <1301470076-17279-1-git-send-email-blogic@openwrt.org> <1301470076-17279-6-git-send-email-blogic@openwrt.org> In-Reply-To: <1301470076-17279-6-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29709 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. John Crispin wrote: > This patch adds the driver for the watchdog found inside the Lantiq SoC family. > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel > Cc: Wim Van Sebroeck > Cc: linux-mips@linux-mips.org > Cc: linux-watchdog@vger.kernel.org > diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c > new file mode 100644 > index 0000000..0a78dfb > --- /dev/null > +++ b/drivers/watchdog/lantiq_wdt.c > @@ -0,0 +1,217 @@ [...] > +/* Section 3.4 of the datasheet > + * The password sequence protects the WDT control register from unintended > + * write actions, which might cause malfunction of the WDT. > + * > + * essentially the following two magic passwords need to be written to allow > + * io access to the wdt core s/io/IO/, s/wdt/WDT. Be consistent. :-) > +static void > +ltq_wdt_enable(unsigned int timeout) This function is always called with 'ltw_wdt_timeout' as a parameter. Seems better to use it internally, and not pass it every time. > +{ > + timeout = ((timeout * (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER)) > + + 0x1000); The parens around rvalue are not needed. [...] > +static ssize_t > +ltq_wdt_write(struct file *file, const char __user *data, > + size_t len, loff_t *ppos) > +{ > + size_t i; > + > + if (!len) > + return 0; > +#ifndef CONFIG_WATCHDOG_NOWAYOUT Er, Documentation/CodingStyle asks not to use #ifdef inside the code. You could create a special function here... > + for (i = 0; i != len; i++) { > + char c; > + > + if (get_user(c, data + i)) > + return -EFAULT; > + if (c == 'V') > + ltq_wdt_ok_to_close = 1; > + } > +#endif > + ltq_wdt_enable(ltq_wdt_timeout); > + return len; > +} [...] > +static int __init > +ltq_wdt_probe(struct platform_device *pdev) > +{ > + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + struct clk *clk; > + > + if (!res) { > + dev_err(&pdev->dev, "cannot obtain I/O memory region"); > + return -ENOENT; > + } > + res = devm_request_mem_region(&pdev->dev, res->start, > + resource_size(res), dev_name(&pdev->dev)); > + if (!res) { > + dev_err(&pdev->dev, "cannot request I/O memory region"); > + return -EBUSY; > + } > + ltq_wdt_membase = devm_ioremap_nocache(&pdev->dev, res->start, > + resource_size(res)); > + if (!ltq_wdt_membase) { > + dev_err(&pdev->dev, "cannot remap I/O memory region\n"); > + return -ENOMEM; > + } > + /* we do not need to enable the clock as it is always running */ > + clk = clk_get(&pdev->dev, "io"); > + BUG_ON(!clk); WARN_ON(). We shouldn't kill the whole machine I think. > +static int __init > +init_ltq_wdt(void) > +{ > + return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); > +} > + > +module_init(init_ltq_wdt); How about module_exit()? WBR, Sergei From Andrei.Ardelean@idt.com Thu Apr 7 19:31:12 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 19:31:15 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:60501 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491115Ab1DGRbM convert rfc822-to-8bit (ORCPT ); Thu, 7 Apr 2011 19:31:12 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id p37HV4Wo009474 for ; Thu, 7 Apr 2011 10:31:04 -0700 Received: from corpml3.corp.idt.com (corpml3.corp.idt.com [157.165.140.25]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id p37HV4Pj005336 for ; Thu, 7 Apr 2011 10:31:04 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml3.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id p37HV2g14496 for ; Thu, 7 Apr 2011 10:31:03 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: After writing successfully a NAND block is this reliable ar reading as a NOR sector? Date: Thu, 7 Apr 2011 10:31:01 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: After writing successfully a NAND block is this reliable ar reading as a NOR sector? Thread-Index: Acv1SZCM2iZJg7PmSYSrxfmO5vrwtg== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, Am interested in using MT29F2G08AABWP NAND Flash memory for a new embedded design and I couldn't find a clear specification regarding how reliable is the NAND flash vs. NOR for reading operation. If I program successfully a NAND block, read back and verify successfully the information and never erase or program that particular block again, can I assume that block will remain a good block and the information written there is safe for READING, roughly as safe as a NOR sector? Is it any reason to keep in NAND copies of Kernel, bootloader or RFS? Is it a standard practice in the industry to keep copies in NAND even though we do not erase/program those during the normal operation? Thank you, Andrei From jabowery@gmail.com Thu Apr 7 22:16:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Apr 2011 22:16:46 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:64715 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491823Ab1DGUQn (ORCPT ); Thu, 7 Apr 2011 22:16:43 +0200 Received: by wwb17 with SMTP id 17so3062317wwb.24 for ; Thu, 07 Apr 2011 13:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:date:message-id:subject:from:to :content-type; bh=J+8r3+6c+Pq6MfsiPbQsRq5M+Ydd+CmjtUaCgPhe2g8=; b=wrl4ANUO3SeabqGrG4oaDcwcV3saGaKmqAlJGM+9MPFsdmVdnf9EiVVNk1K/yomsPX ktykPEQGYpP+iSVFR0kHyEeHb6pHZELhPHXzHfExE14zRZAQIPWyQ1fSaVBRHe9Onh7O IlMbBorhL3mnpCDy9CrVkS2FLKEgBE95kiidc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=JxPxZeNZHqeCGnB+NuCHWRdmjM6ItUZ65RMz9iunraY1YBzBiwSbi32IYVWsdgRvS7 EE3Yhdyit/laahLYOfHj/ACAYrq+8SI00+syA2eVYItY7Rs4Da7WLz8EFAljDSjOF1/z zyhygWms1t/srK7gi1gxAVoKLbzO1M2gb/P9k= MIME-Version: 1.0 Received: by 10.227.139.14 with SMTP id c14mr1365149wbu.55.1302207397323; Thu, 07 Apr 2011 13:16:37 -0700 (PDT) Received: by 10.227.145.146 with HTTP; Thu, 7 Apr 2011 13:16:37 -0700 (PDT) Date: Thu, 7 Apr 2011 15:16:37 -0500 Message-ID: Subject: Linux on MIPS emulator? From: James Bowery To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jabowery@gmail.com Precedence: bulk X-list: linux-mips I'd like to run Linux on a MIPS emulator. Presuming this has been done, is there a "how to" page for this? From bernhard@bwalle.de Fri Apr 8 07:00:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Apr 2011 07:00:54 +0200 (CEST) Received: from smtprelay06.ispgateway.de ([80.67.31.102]:59474 "EHLO smtprelay06.ispgateway.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490997Ab1DHFAs (ORCPT ); Fri, 8 Apr 2011 07:00:48 +0200 Received: from [78.47.165.117] (helo=regiomontanus) by smtprelay06.ispgateway.de with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.68) (envelope-from ) id 1Q83oK-0004XK-9R; Fri, 08 Apr 2011 07:00:44 +0200 Date: Fri, 8 Apr 2011 07:00:42 +0200 From: Bernhard Walle To: James Bowery Cc: linux-mips@linux-mips.org Subject: Re: Linux on MIPS emulator? Message-ID: <20110408050042.GA10423@regiomontanus> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Df-Sender: 1227806 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bernhard@bwalle.de Precedence: bulk X-list: linux-mips * James Bowery [2011-04-07 22:16]: > I'd like to run Linux on a MIPS emulator. > > Presuming this has been done, is there a "how to" page for this? http://www.linux-mips.org/wiki/Qemu. Regards, Bernhard From jonas.gorski@gmail.com Fri Apr 8 14:32:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Apr 2011 14:32:44 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:47661 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491071Ab1DHMcl (ORCPT ); Fri, 8 Apr 2011 14:32:41 +0200 Received: by bwz1 with SMTP id 1so3360758bwz.36 for ; Fri, 08 Apr 2011 05:32:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=npGl7l+TV6P9af+LHyosMQNUYegC2YQbCOB7SQRgMqQ=; b=Eo2+QKn7+5uq8vgTF6Fp3BYpfFmEou9BIUBJuW0nJK7MPLd5p6xXl3Gm636rHBsJzN REMwhrgUjQcCLNJtIQiYfcy3KizI6ftq/+pfrCE2mKfn3ZWxOupw1l5SzcnhbTwn1vKd 3hmuXVWgBI/H9wiSta4R5hGARiDv59M9pLvhg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=JtDA+CYWZxUQ6V1ckqEucB0USWfX92wXayAkI7Vaxn1gQlwMUDCS8aHXWLglKZx+7O tqq01CmoOVU0DCD2lrwB7M0vZtJgObKtRyA0uTnv2X7ynISeLGEV5z/I0cULNa2qiKiZ YolEEGc6wPbAN+hyVTVVYjtTtaCvTyX53/nXc= Received: by 10.204.80.29 with SMTP id r29mr1879452bkk.195.1302265952030; Fri, 08 Apr 2011 05:32:32 -0700 (PDT) Received: from localhost.localdomain (dslb-088-073-061-184.pools.arcor-ip.net [88.73.61.184]) by mx.google.com with ESMTPS id c11sm1625572bkc.2.2011.04.08.05.32.29 (version=SSLv3 cipher=OTHER); Fri, 08 Apr 2011 05:32:30 -0700 (PDT) From: Jonas Gorski To: Ralf Baechle Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH] MIPS: bcm63xx: Fix header_crc comment in bcm963xx_tag.h Date: Fri, 8 Apr 2011 14:32:15 +0200 Message-Id: <1302265935-23802-1-git-send-email-jonas.gorski@gmail.com> X-Mailer: git-send-email 1.5.6.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonas.gorski@gmail.com Precedence: bulk X-list: linux-mips The CRC32 actually includes the tag_version. Signed-off-by: Jonas Gorski --- This was already wrong in the original Broadcom sources (and it still seems to be). arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h index 5325084..73c499f 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h @@ -88,7 +88,7 @@ struct bcm_tag { char kernel_crc[CRC_LEN]; /* 228-235: Unused at present */ char reserved1[8]; - /* 236-239: CRC32 of header excluding tagVersion */ + /* 236-239: CRC32 of header excluding last 20 bytes */ char header_crc[CRC_LEN]; /* 240-255: Unused at present */ char reserved2[16]; -- 1.5.6.5 From f.fainelli@gmail.com Fri Apr 8 14:39:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Apr 2011 14:39:54 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:58493 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491073Ab1DHMjv (ORCPT ); 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Fri, 08 Apr 2011 05:39:43 -0700 (PDT) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id b20sm1682091wbb.67.2011.04.08.05.39.41 (version=SSLv3 cipher=OTHER); Fri, 08 Apr 2011 05:39:41 -0700 (PDT) From: Florian Fainelli Organization: OpenWrt To: Jonas Gorski Subject: Re: [PATCH] MIPS: bcm63xx: Fix header_crc comment in bcm963xx_tag.h Date: Fri, 8 Apr 2011 14:41:30 +0200 User-Agent: KMail/1.13.5 (Linux/2.6.35-25-server; KDE/4.5.1; x86_64; ; ) Cc: Ralf Baechle , linux-mips@linux-mips.org References: <1302265935-23802-1-git-send-email-jonas.gorski@gmail.com> In-Reply-To: <1302265935-23802-1-git-send-email-jonas.gorski@gmail.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201104081441.30827.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips On Friday 08 April 2011 14:32:15 Jonas Gorski wrote: > The CRC32 actually includes the tag_version. > > Signed-off-by: Jonas Gorski Acked-by: Florian Fainelli > --- > > This was already wrong in the original Broadcom sources (and it still > seems to be). > > arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h > b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h index 5325084..73c499f > 100644 > --- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h > +++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h > @@ -88,7 +88,7 @@ struct bcm_tag { > char kernel_crc[CRC_LEN]; > /* 228-235: Unused at present */ > char reserved1[8]; > - /* 236-239: CRC32 of header excluding tagVersion */ > + /* 236-239: CRC32 of header excluding last 20 bytes */ > char header_crc[CRC_LEN]; > /* 240-255: Unused at present */ > char reserved2[16]; From ralf@linux-mips.org Fri Apr 8 14:45:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Apr 2011 14:45:39 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:60094 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491079Ab1DHMph (ORCPT ); Fri, 8 Apr 2011 14:45:37 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p38Cj8l6016000; Fri, 8 Apr 2011 14:45:08 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p38Cj6Wx015993; Fri, 8 Apr 2011 14:45:06 +0200 Date: Fri, 8 Apr 2011 14:45:06 +0200 From: Ralf Baechle To: Jonas Gorski Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: Re: [PATCH] MIPS: bcm63xx: Fix header_crc comment in bcm963xx_tag.h Message-ID: <20110408124505.GA15953@linux-mips.org> References: <1302265935-23802-1-git-send-email-jonas.gorski@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1302265935-23802-1-git-send-email-jonas.gorski@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Fri Apr 8 15:08:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Apr 2011 15:08:42 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:55651 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491084Ab1DHNIj (ORCPT ); Fri, 8 Apr 2011 15:08:39 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p38D8CPb017836; Fri, 8 Apr 2011 15:08:12 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p38D8Bxi017833; Fri, 8 Apr 2011 15:08:11 +0200 Date: Fri, 8 Apr 2011 15:08:11 +0200 From: Ralf Baechle To: "Justin P. Mattock" Cc: trivial@kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [RFC 3/5]arch:mips:pmc-sierra:msp71xx:Makefile Remove unused config in the Makefile. Message-ID: <20110408130811.GA17431@linux-mips.org> References: <1302022702-24541-1-git-send-email-justinmattock@gmail.com> <1302022702-24541-3-git-send-email-justinmattock@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1302022702-24541-3-git-send-email-justinmattock@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 05, 2011 at 09:58:20AM -0700, Justin P. Mattock wrote: > The patch below removes an unused config variable found by using a kernel > cleanup script. > Note: I did try to cross compile these but hit erros while doing so.. > (gcc is not setup to cross compile) and am unsure if anymore needs to be done. > Please have a look if/when anybody has free time. NACK. This need a rewrite, not just chainsawing. Your code was only touching the makefile anyway, not the two referenced C files. Ralf Ralf From ralf@linux-mips.org Fri Apr 8 15:26:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Apr 2011 15:26:11 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:57608 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491087Ab1DHN0F (ORCPT ); Fri, 8 Apr 2011 15:26:05 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p38DPaeG019194; Fri, 8 Apr 2011 15:25:36 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p38DPYoj019191; Fri, 8 Apr 2011 15:25:34 +0200 Date: Fri, 8 Apr 2011 15:25:34 +0200 From: Ralf Baechle To: Joshua Kinard Cc: Linux MIPS List , rtc-linux@googlegroups.com, LKML , Alessandro Zummo Subject: Re: [PATCH 2/2]: MIPS: sgi-ip32: Add support for rtc-ds1685 to SGI O2 (IP32) Message-ID: <20110408132533.GA15416@linux-mips.org> References: <4D9DB95F.8040100@gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D9DB95F.8040100@gentoo.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Apr 07, 2011 at 09:17:19AM -0400, Joshua Kinard wrote: > Date: Thu, 07 Apr 2011 09:17:19 -0400 > From: Joshua Kinard > To: Linux MIPS List , Ralf Baechle > > CC: rtc-linux@googlegroups.com, LKML , > Alessandro Zummo > Subject: [PATCH 2/2]: MIPS: sgi-ip32: Add support for rtc-ds1685 to SGI O2 > (IP32) > Content-Type: text/plain; charset=ISO-8859-1 > > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 Please don't PGP sign patches. Nobody care about your PGP signature as long there's a valid Signed-off-by. > These are the modifications needed to the SGI O2 (IP32) codebase to switch off > of rtc-cmos to rtc-ds1685. It needs to be applied after the main rtc-ds1685 patch. > > Key changes here eliminate the custom power-off code and call upon the version > built into the main driver via platform_data, as well as defining the required > register step-size of 256 bytes (0x100). > > Signed-off-by: Joshua Kinard > - --- And this is a --- tearoff line corrupted by PGP. Just like every other line starting with a -. > include/asm/mach-ip32/mc146818rtc.h | 36 ---------- > sgi-ip32/ip32-platform.c | 49 ++++++++++++-- > sgi-ip32/ip32-reset.c | 118 ++++++++---------------------------- > 3 files changed, 67 insertions(+), 136 deletions(-) > > diff -Naurp mipslinux.orig/arch/mips/include/asm/mach-ip32/mc146818rtc.h > mipslinux.ip32-rtc/arch/mips/include/asm/mach-ip32/mc146818rtc.h > - --- mipslinux.orig/arch/mips/include/asm/mach-ip32/mc146818rtc.h 2009-04-28 > 20:29:27.000000000 -0400 > +++ mipslinux.ip32-rtc/arch/mips/include/asm/mach-ip32/mc146818rtc.h 1969-12-31 > 19:00:00.000000000 -0500 Two linewrapped lines rot in pieces here. Only recent patch versions are happy with this but git takes a harder look at patch headers and will reject it. > @@ -1,36 +0,0 @@ > - -/* Another GPG mangled line. > - - * This file is subject to the terms and conditions of the GNU General Public > - - * License. See the file "COPYING" in the main directory of this archive > - - * for more details. > - - * > - - * Copyright (C) 1998, 2001, 03 by Ralf Baechle > - - * Copyright (C) 2000 Harald Koerfgen > - - * > - - * RTC routines for IP32 style attached Dallas chip. > - - */ > - -#ifndef __ASM_MACH_IP32_MC146818RTC_H > - -#define __ASM_MACH_IP32_MC146818RTC_H > - - > - -#include > - - > - -#define RTC_PORT(x) (0x70 + (x)) > - - > - -static unsigned char CMOS_READ(unsigned long addr) > - -{ > - - return mace->isa.rtc[addr << 8]; > - -} > - - > - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) > - -{ > - - mace->isa.rtc[addr << 8] = data; > - -} > - - > - -/* > - - * FIXME: Do it right. For now just assume that noone lives in 20th century > - - * and no O2 user in 22th century ;-) > - - */ > - -#define mc146818_decode_year(year) ((year) + 2000) > - - > - -#define RTC_ALWAYS_BCD 0 > - - > - -#endif /* __ASM_MACH_IP32_MC146818RTC_H */ > diff -Naurp mipslinux.orig/arch/mips/sgi-ip32/ip32-platform.c > mipslinux.ip32-rtc/arch/mips/sgi-ip32/ip32-platform.c > - --- mipslinux.orig/arch/mips/sgi-ip32/ip32-platform.c 2009-04-28 > 20:29:28.000000000 -0400 > +++ mipslinux.ip32-rtc/arch/mips/sgi-ip32/ip32-platform.c 2011-04-07 > 08:02:00.063871001 -0400 > @@ -9,10 +9,13 @@ > #include > #include > #include > +#include > > #include > #include > > +extern void inline ip32_prepare_poweroff(void); An extern inline declaration is not online pointless; "extern inline" definitions also have a different meaning than what you probably want. Just get rid of the inline keyword here. Anyway, modern gccs have decent heuristics when to inline functions so the inline keyword is losing its importance. > + > #define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1) > #define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2) > > @@ -90,22 +93,50 @@ static __init int sgio2btns_devinit(void > > device_initcall(sgio2btns_devinit); > > - -static struct resource sgio2_cmos_rsrc[] = { > +#define MACE_RTC_RES_START (MACE_BASE + offsetof(struct sgi_mace, isa.rtc)) > +#define MACE_RTC_RES_END (MACE_RTC_RES_START + 32767) > + > +static struct resource ip32_rtc_resources[] = { > { > - - .start = 0x70, > - - .end = 0x71, > - - .flags = IORESOURCE_IO > + .start = MACEISA_RTC_IRQ, > + .end = MACEISA_RTC_IRQ, > + .flags = IORESOURCE_IRQ > + }, { > + .start = MACE_RTC_RES_START, > + .end = MACE_RTC_RES_END, > + .flags = IORESOURCE_MEM, > } > }; > > - -static __init int sgio2_cmos_devinit(void) > + > +/* RTC registers on IP32 are each padded by 256 bytes (0x100). */ > +static struct ds1685_rtc_platform_data > +ip32_rtc_platform_data[] = { > + { > + .regstep = 0x100, > + .plat_prepare_poweroff = ip32_prepare_poweroff, > + }, > +}; > + > +struct platform_device ip32_rtc_device = { > + .name = "rtc-ds1685", > + .id = -1, > + .dev = { > + .platform_data = ip32_rtc_platform_data, > + }, > + .num_resources = ARRAY_SIZE(ip32_rtc_resources), > + .resource = ip32_rtc_resources, > +}; > +EXPORT_SYMBOL(ip32_rtc_device); This export is unnecessary; remove it. > +static int __init sgio2_rtc_devinit(void) > { > - - return IS_ERR(platform_device_register_simple("rtc_cmos", -1, > - - sgio2_cmos_rsrc, 1)); > + return platform_device_register(&ip32_rtc_device); > + > } > > - -device_initcall(sgio2_cmos_devinit); > +device_initcall(sgio2_rtc_devinit); > > MODULE_AUTHOR("Ralf Baechle "); > MODULE_LICENSE("GPL"); > - -MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2"); > +MODULE_DESCRIPTION("IP32 platform setup for SGI IP32 aka O2"); > diff -Naurp mipslinux.orig/arch/mips/sgi-ip32/ip32-reset.c > mipslinux.ip32-rtc/arch/mips/sgi-ip32/ip32-reset.c > - --- mipslinux.orig/arch/mips/sgi-ip32/ip32-reset.c 2009-05-23 12:01:03.025842703 > - -0400 > +++ mipslinux.ip32-rtc/arch/mips/sgi-ip32/ip32-reset.c 2011-04-07 > 08:02:00.063871001 -0400 > @@ -13,7 +13,7 @@ > #include > #include > #include > - -#include > +#include > #include > #include > > @@ -33,55 +33,31 @@ > #define POWERDOWN_FREQ (HZ / 4) > #define PANIC_FREQ (HZ / 8) > > - -static struct timer_list power_timer, blink_timer, debounce_timer; > - -static int has_panicked, shuting_down; > +extern struct ds1685_rtc_platform_data ip32_rtc_platform_data[]; This declaration seems unnecessary. > +extern struct platform_device ip32_rtc_device; > > - -static void ip32_machine_restart(char *command) __attribute__((noreturn)); > - -static void ip32_machine_halt(void) __attribute__((noreturn)); > - -static void ip32_machine_power_off(void) __attribute__((noreturn)); > +static struct timer_list power_timer, blink_timer; > +static int has_panicked, shutting_down; > > - -static void ip32_machine_restart(char *cmd) > +static void ip32_poweroff(void *data) > { > - - crime->control = CRIME_CONTROL_HARD_RESET; > +#if defined(CONFIG_RTC_DRV_DS1685_FAMILY) && \ > + (defined(CONFIG_RTC_DRV_DS1685) || defined(CONFIG_RTC_DRV_DS17285)) > + ds1685_rtc_poweroff((struct platform_device *)data); > +#else > while (1); > +#endif That's the sort of #ifdefery is rather ugly. Switch the driver to a module and magically the poweroff code ceases to work ... > } > > - -static inline void ip32_machine_halt(void) > - -{ > - - ip32_machine_power_off(); > - -} > > - -static void ip32_machine_power_off(void) > +static void ip32_machine_restart(char *cmd) __attribute__((noreturn)); > +static void ip32_machine_restart(char *cmd) > { > - - unsigned char reg_a, xctrl_a, xctrl_b; > - - > - - disable_irq(MACEISA_RTC_IRQ); > - - reg_a = CMOS_READ(RTC_REG_A); > - - > - - /* setup for kickstart & wake-up (DS12287 Ref. Man. p. 19) */ > - - reg_a &= ~DS_REGA_DV2; > - - reg_a |= DS_REGA_DV1; > - - > - - CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); > - - wbflush(); > - - xctrl_b = CMOS_READ(DS_B1_XCTRL4B) > - - | DS_XCTRL4B_ABE | DS_XCTRL4B_KFE; > - - CMOS_WRITE(xctrl_b, DS_B1_XCTRL4B); > - - xctrl_a = CMOS_READ(DS_B1_XCTRL4A) & ~DS_XCTRL4A_IFS; > - - CMOS_WRITE(xctrl_a, DS_B1_XCTRL4A); > - - wbflush(); > - - /* adios amigos... */ > - - CMOS_WRITE(xctrl_a | DS_XCTRL4A_PAB, DS_B1_XCTRL4A); > - - CMOS_WRITE(reg_a, RTC_REG_A); > - - wbflush(); > + msleep(10); > + crime->control = CRIME_CONTROL_HARD_RESET; > while (1); > } > > - -static void power_timeout(unsigned long data) > - -{ > - - ip32_machine_power_off(); > - -} > - - > static void blink_timeout(unsigned long data) > { > unsigned long led = mace->perif.ctrl.misc ^ MACEISA_LED_RED; > @@ -89,44 +65,27 @@ static void blink_timeout(unsigned long > mod_timer(&blink_timer, jiffies + data); > } > > - -static void debounce(unsigned long data) > +static void ip32_machine_halt(void) > { > - - unsigned char reg_a, reg_c, xctrl_a; > - - > - - reg_c = CMOS_READ(RTC_INTR_FLAGS); > - - reg_a = CMOS_READ(RTC_REG_A); > - - CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); > - - wbflush(); > - - xctrl_a = CMOS_READ(DS_B1_XCTRL4A); > - - if ((xctrl_a & DS_XCTRL4A_IFS) || (reg_c & RTC_IRQF )) { > - - /* Interrupt still being sent. */ > - - debounce_timer.expires = jiffies + 50; > - - add_timer(&debounce_timer); > - - > - - /* clear interrupt source */ > - - CMOS_WRITE(xctrl_a & ~DS_XCTRL4A_IFS, DS_B1_XCTRL4A); > - - CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); > - - return; > - - } > - - CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); > - - > - - if (has_panicked) > - - ip32_machine_restart(NULL); > + ip32_poweroff(&ip32_rtc_device); > +} > > - - enable_irq(MACEISA_RTC_IRQ); > +static void power_timeout(unsigned long data) > +{ > + ip32_poweroff(&ip32_rtc_device); > } > > - -static inline void ip32_power_button(void) > +void ip32_prepare_poweroff(void) > { > if (has_panicked) > return; > > - - if (shuting_down || kill_cad_pid(SIGINT, 1)) { > + if (shutting_down || kill_cad_pid(SIGINT, 1)) { > /* No init process or button pressed twice. */ > - - ip32_machine_power_off(); > + ip32_poweroff(&ip32_rtc_device); > } > > - - shuting_down = 1; > + shutting_down = 1; > blink_timer.data = POWERDOWN_FREQ; > blink_timeout(POWERDOWN_FREQ); > > @@ -135,27 +94,7 @@ static inline void ip32_power_button(voi > power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ; > add_timer(&power_timer); > } > - - > - -static irqreturn_t ip32_rtc_int(int irq, void *dev_id) > - -{ > - - unsigned char reg_c; > - - > - - reg_c = CMOS_READ(RTC_INTR_FLAGS); > - - if (!(reg_c & RTC_IRQF)) { > - - printk(KERN_WARNING > - - "%s: RTC IRQ without RTC_IRQF\n", __func__); > - - } > - - /* Wait until interrupt goes away */ > - - disable_irq_nosync(MACEISA_RTC_IRQ); > - - init_timer(&debounce_timer); > - - debounce_timer.function = debounce; > - - debounce_timer.expires = jiffies + 50; > - - add_timer(&debounce_timer); > - - > - - printk(KERN_DEBUG "Power button pressed\n"); > - - ip32_power_button(); > - - return IRQ_HANDLED; > - -} > +EXPORT_SYMBOL(ip32_prepare_poweroff); Unnecessary export; remove it. > static int panic_event(struct notifier_block *this, unsigned long event, > void *ptr) > @@ -190,15 +129,12 @@ static __init int ip32_reboot_setup(void > > _machine_restart = ip32_machine_restart; > _machine_halt = ip32_machine_halt; > - - pm_power_off = ip32_machine_power_off; > + pm_power_off = ip32_machine_halt; > > init_timer(&blink_timer); > blink_timer.function = blink_timeout; > atomic_notifier_chain_register(&panic_notifier_list, &panic_block); > > - - if (request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL)) > - - panic("Can't allocate MACEISA RTC IRQ"); > - - > return 0; > } From justinmattock@gmail.com Fri Apr 8 17:10:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Apr 2011 17:10:52 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:65341 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491095Ab1DHPKt (ORCPT ); Fri, 8 Apr 2011 17:10:49 +0200 Received: by pzk5 with SMTP id 5so1518131pzk.36 for ; Fri, 08 Apr 2011 08:10:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=SvcLItcwgQhKPUixHhjwSOBE/05jxgMRgS9VIM1kJjE=; b=DgGja2xZu7obZh6qR4GbMhE5sv96iP+ezy4VXTEXW5QKLiWe5neQt8BmnJAA3h5N1Q 2O9dGn3MQKiJrS0jAi0YLNWqrD4hKsEFN2yKoFlYqDnRhfwG7KSbbAtqZiITI6EPoTuL PU4IVSGJW9Gn2vlmnk15EifxQlTGxelKeHl5s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=cdOSltA1C1jTO7FlNp/um0V23AWnoTzTCovoAqzU2Bcz7Pbr2KU1w/JhwCb/ZoSWx1 hdzXdRVKzPfx/W0S5vzdigD9euPgY0BCPvZdDjzMbpzMhIctk3N8jtloguuvVv6XzNgU OUQfsNdTdibimLHFAiKMo0WMRSeuVYkJ36Z9U= Received: by 10.142.144.15 with SMTP id r15mr1979939wfd.439.1302275441533; Fri, 08 Apr 2011 08:10:41 -0700 (PDT) Received: from [172.16.1.89] (74-206-12-204.static-ip.m.telepacific.net [74.206.12.204]) by mx.google.com with ESMTPS id w32sm3753253wfh.19.2011.04.08.08.10.40 (version=SSLv3 cipher=OTHER); Fri, 08 Apr 2011 08:10:40 -0700 (PDT) Message-ID: <4D9F2568.50204@gmail.com> Date: Fri, 08 Apr 2011 08:10:32 -0700 From: "Justin P. Mattock" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.15) Gecko/20110403 Fedora/3.1.9-6.fc15 Thunderbird/3.1.9 MIME-Version: 1.0 To: Ralf Baechle CC: trivial@kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [RFC 3/5]arch:mips:pmc-sierra:msp71xx:Makefile Remove unused config in the Makefile. References: <1302022702-24541-1-git-send-email-justinmattock@gmail.com> <1302022702-24541-3-git-send-email-justinmattock@gmail.com> <20110408130811.GA17431@linux-mips.org> In-Reply-To: <20110408130811.GA17431@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: justinmattock@gmail.com Precedence: bulk X-list: linux-mips On 04/08/2011 06:08 AM, Ralf Baechle wrote: > On Tue, Apr 05, 2011 at 09:58:20AM -0700, Justin P. Mattock wrote: > >> The patch below removes an unused config variable found by using a kernel >> cleanup script. >> Note: I did try to cross compile these but hit erros while doing so.. >> (gcc is not setup to cross compile) and am unsure if anymore needs to be done. >> Please have a look if/when anybody has free time. > > NACK. > > This need a rewrite, not just chainsawing. Your code was only touching > the makefile anyway, not the two referenced C files. > > Ralf > > Ralf > alright!! Justin P. Mattock From wanlong.gao@gmail.com Sat Apr 9 19:43:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Apr 2011 19:43:32 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:54343 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490988Ab1DIRnO (ORCPT ); Sat, 9 Apr 2011 19:43:14 +0200 Received: by iwn36 with SMTP id 36so5093538iwn.36 for ; Sat, 09 Apr 2011 10:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=K2SxquBAsrGztBy/4Ma46A+ekqzD7WXU+7KMCA045Vg=; b=mer9g6K+4ncCEwXGeVe3hgGYvnYOdxk8l+NoOzKlJKsBs03Lr0BUuDLr2Vb1Uuznd4 4k3O8KMDxZezB7e2SiBLOvRyZouDw3m22iAAtzRQ/3bzJOV0XYekYSJSI81gizfhRTSI 0/a4JmrOpBdG9mr/ZRrzMQ1/Q/BtCp6woXWiA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=DH1auiinRCx5nKIcc9NvTSUf0aXSXEcW0BL/n/XnW/bN27Gdgl6A23nJ57c6nFslrG DzW7olj0WBk44AKVd23pV4eM89ikxdU4OUNl+YL34Pl+1Jq6kQnyJ26vPio9wLgiRXjx u2N7uRM+AbNPe5IeSD2aGtMwkC9bdiIh0Qtww= Received: by 10.42.142.9 with SMTP id q9mr4933596icu.413.1302370986451; Sat, 09 Apr 2011 10:43:06 -0700 (PDT) Received: from localhost.localdomain ([182.32.130.75]) by mx.google.com with ESMTPS id e9sm2782765ibb.15.2011.04.09.10.42.59 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 09 Apr 2011 10:43:05 -0700 (PDT) From: wanlong.gao@gmail.com To: ralf@linux-mips.org, david.woodhouse@intel.com, akpm@linux-foundation.org, mingo@elte.hu Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Wanlong Gao Subject: [PATCH] MIPS:fix the build warning Date: Sun, 10 Apr 2011 01:42:17 +0800 Message-Id: <1302370937-832-1-git-send-email-wanlong.gao@gmail.com> X-Mailer: git-send-email 1.7.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wanlong.gao@gmail.com Precedence: bulk X-list: linux-mips From: Wanlong Gao LEDS_CLASS is a bool config . Value 'm' is invalid for LEDS_CLASS. Signed-off-by: Wanlong Gao --- arch/mips/configs/lemote2f_defconfig | 2 +- arch/mips/configs/malta_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index 167c1d0..cb2c5ea 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -329,7 +329,7 @@ CONFIG_USB_LED=m CONFIG_USB_GADGET=m CONFIG_USB_GADGET_M66592=y CONFIG_MMC=m -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_STAGING=y # CONFIG_STAGING_EXCLUDE_BUILD is not set CONFIG_FB_SM7XX=y diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 7270f31..5527abb 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -374,7 +374,7 @@ CONFIG_FB_CIRRUS=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_HID=m -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_IDE_DISK=y CONFIG_LEDS_TRIGGER_HEARTBEAT=m -- 1.7.3 From wanlong.gao@gmail.com Sat Apr 9 21:05:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Apr 2011 21:05:45 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:42682 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491014Ab1DITFk (ORCPT ); Sat, 9 Apr 2011 21:05:40 +0200 Received: by iwn36 with SMTP id 36so5138401iwn.36 for ; Sat, 09 Apr 2011 12:05:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=1ewKjE7SJpMyGD+b7/7JC33YIXwt/XKJbITBQ3VU58Q=; b=jZGDn+6cVAfFN0sPBIkQxb3Icr2cHtwU1t34DV7a8t9KX2gGuX/LbH0ivili/rgJvx Hglde5rI/nwqpnUFHSB6gFgnDPkwjMs40Q6v+RjUCC6WhY+1hTF5SVn6IjKcabn+872M iakP6+5Qhn3WftAMS7JLCs04WNImdSE4KCU7A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=JD7LaZSZdJch5T2g/kbeEr58l+5d3FrOfheYDpt8Zb5YBToUo/X8GvFO7iUQdmkNYu y3bqWCYcAzJzAu2pso6KIJ+elm1Juhiv55vAS/u+a2XpaslcSPOQ/1Ybk+UlOSs9LhTa vNObj77pPD0qAEpzrz2oIrSwN7MgAzxAJ2EUY= Received: by 10.43.54.210 with SMTP id vv18mr5372982icb.103.1302375933078; Sat, 09 Apr 2011 12:05:33 -0700 (PDT) Received: from localhost.localdomain ([182.32.130.75]) by mx.google.com with ESMTPS id 19sm2825783ibx.52.2011.04.09.12.05.11 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 09 Apr 2011 12:05:32 -0700 (PDT) From: wanlong.gao@gmail.com To: linux@arm.linux.org.uk, hans-christian.egtvedt@atmel.com, ralf@linux-mips.org, benh@kernel.crashing.org, paulus@samba.org, david.woodhouse@intel.com, akpm@linux-foundation.org, u.kleine-koenig@pengutronix.de, mingo@elte.hu, rientjes@google.com, nicolas.ferre@atmel.com, eric@eukrea.com, tony@atomide.com, santosh.shilimkar@ti.com, khilman@deeprootsystems.com, ben-linux@fluff.org, sam@ravnborg.org, manuel.lauss@googlemail.com, galak@kernel.crashing.org, anton@samba.org, grant.likely@secretlab.ca, sfr@canb.auug.org.au, jwboyer@linux.vnet.ibm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, Wanlong Gao Subject: [PATCH] fix build warnings on defconfigs Date: Sun, 10 Apr 2011 03:04:18 +0800 Message-Id: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> X-Mailer: git-send-email 1.7.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wanlong.gao@gmail.com Precedence: bulk X-list: linux-mips From: Wanlong Gao Change the BT_L2CAP and BT_SCO defconfigs from 'm' to 'y', since BT_L2CAP and BT_SCO had changed to bool configs. Signed-off-by: Wanlong Gao --- arch/arm/configs/am200epdkit_defconfig | 4 ++-- arch/arm/configs/at572d940hfek_defconfig | 2 +- arch/arm/configs/at91rm9200_defconfig | 4 ++-- arch/arm/configs/badge4_defconfig | 2 +- arch/arm/configs/cm_x2xx_defconfig | 4 ++-- arch/arm/configs/cm_x300_defconfig | 4 ++-- arch/arm/configs/colibri_pxa270_defconfig | 4 ++-- arch/arm/configs/corgi_defconfig | 4 ++-- arch/arm/configs/davinci_all_defconfig | 2 +- arch/arm/configs/em_x270_defconfig | 4 ++-- arch/arm/configs/magician_defconfig | 4 ++-- arch/arm/configs/mini2440_defconfig | 4 ++-- arch/arm/configs/nhk8815_defconfig | 4 ++-- arch/arm/configs/ns9xxx_defconfig | 2 +- arch/arm/configs/omap2plus_defconfig | 4 ++-- arch/arm/configs/pxa3xx_defconfig | 2 +- arch/arm/configs/s3c2410_defconfig | 6 +++--- arch/arm/configs/simpad_defconfig | 4 ++-- arch/arm/configs/spitz_defconfig | 4 ++-- arch/arm/configs/trizeps4_defconfig | 4 ++-- arch/arm/configs/viper_defconfig | 2 +- arch/arm/configs/zeus_defconfig | 4 ++-- arch/avr32/configs/atngw100_mrmt_defconfig | 2 +- arch/mips/configs/lemote2f_defconfig | 4 ++-- arch/mips/configs/mtx1_defconfig | 4 ++-- arch/powerpc/configs/c2k_defconfig | 4 ++-- arch/powerpc/configs/pmac32_defconfig | 4 ++-- arch/powerpc/configs/ppc6xx_defconfig | 4 ++-- arch/powerpc/configs/ps3_defconfig | 4 ++-- 29 files changed, 52 insertions(+), 52 deletions(-) diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig index f0dea52..0a7d807 100644 --- a/arch/arm/configs/am200epdkit_defconfig +++ b/arch/arm/configs/am200epdkit_defconfig @@ -34,8 +34,8 @@ CONFIG_INET=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig index 1b1158a..8409374 100644 --- a/arch/arm/configs/at572d940hfek_defconfig +++ b/arch/arm/configs/at572d940hfek_defconfig @@ -280,7 +280,7 @@ CONFIG_SDIO_UART=m CONFIG_MMC_AT91=m CONFIG_MMC_SPI=m CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig index 38cb7c9..b21dd9e 100644 --- a/arch/arm/configs/at91rm9200_defconfig +++ b/arch/arm/configs/at91rm9200_defconfig @@ -75,8 +75,8 @@ CONFIG_IPV6_TUNNEL=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig index 5b54abb..ddd8eb2 100644 --- a/arch/arm/configs/badge4_defconfig +++ b/arch/arm/configs/badge4_defconfig @@ -24,7 +24,7 @@ CONFIG_IRCOMM=y CONFIG_IRDA_ULTRA=y CONFIG_SA1100_FIR=y CONFIG_BT=m -CONFIG_BT_L2CAP=m +CONFIG_BT_L2CAP=y CONFIG_BT_HCIUART=m CONFIG_BT_HCIVHCI=m # CONFIG_FW_LOADER is not set diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig index a93ff8d..04bf923 100644 --- a/arch/arm/configs/cm_x2xx_defconfig +++ b/arch/arm/configs/cm_x2xx_defconfig @@ -43,8 +43,8 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_BNEP=m CONFIG_BT_HIDP=m diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index 921e56a..d7c7d99 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig @@ -40,8 +40,8 @@ CONFIG_IP_PNP_RARP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig index 2ef2c5e..a381317 100644 --- a/arch/arm/configs/colibri_pxa270_defconfig +++ b/arch/arm/configs/colibri_pxa270_defconfig @@ -45,8 +45,8 @@ CONFIG_IRDA_CACHE_LAST_LSAP=y CONFIG_IRDA_FAST_RR=y CONFIG_IRTTY_SIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig index e53c475..ee85811 100644 --- a/arch/arm/configs/corgi_defconfig +++ b/arch/arm/configs/corgi_defconfig @@ -69,8 +69,8 @@ CONFIG_IRNET=m CONFIG_IRCOMM=m CONFIG_PXA_FICP=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 889922a..9739ee2 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -152,7 +152,7 @@ CONFIG_MMC=m # CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_DAVINCI=m CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig index 60a21e0..9910c68 100644 --- a/arch/arm/configs/em_x270_defconfig +++ b/arch/arm/configs/em_x270_defconfig @@ -38,8 +38,8 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_BNEP=m CONFIG_BT_HIDP=m diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index a88e64d..eef5440 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig @@ -48,8 +48,8 @@ CONFIG_IRDA_DEBUG=y CONFIG_IRTTY_SIR=m CONFIG_PXA_FICP=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 2472a95..a0b5413 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -56,8 +56,8 @@ CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_NET_PKTGEN=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 37207d1..5129217 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -38,8 +38,8 @@ CONFIG_IP_MROUTE=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig index 1f528a0..56c20fc 100644 --- a/arch/arm/configs/ns9xxx_defconfig +++ b/arch/arm/configs/ns9xxx_defconfig @@ -38,7 +38,7 @@ CONFIG_I2C_GPIO=m # CONFIG_VGA_CONSOLE is not set # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 076db52..08cc79d 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -89,8 +89,8 @@ CONFIG_IP_PNP_RARP=y # CONFIG_IPV6 is not set CONFIG_NETFILTER=y CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig index 1677a06..573d882 100644 --- a/arch/arm/configs/pxa3xx_defconfig +++ b/arch/arm/configs/pxa3xx_defconfig @@ -99,7 +99,7 @@ CONFIG_LOGO=y CONFIG_MMC=y CONFIG_MMC_PXA=y CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=m CONFIG_LEDS_DA903X=m CONFIG_LEDS_TRIGGERS=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index f9096c1..3a0cd99 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -177,8 +177,8 @@ CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -387,7 +387,7 @@ CONFIG_MMC_TEST=m CONFIG_MMC_SDHCI=m CONFIG_MMC_SPI=m CONFIG_MMC_S3C=y -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_LEDS_S3C24XX=m CONFIG_LEDS_H1940=m CONFIG_LEDS_PCA9532=m diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig index d335815..8c6f806 100644 --- a/arch/arm/configs/simpad_defconfig +++ b/arch/arm/configs/simpad_defconfig @@ -33,8 +33,8 @@ CONFIG_IRCOMM=m CONFIG_IRTTY_SIR=m CONFIG_SA1100_FIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index 7015827..f0137dd 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -66,8 +66,8 @@ CONFIG_IRNET=m CONFIG_IRCOMM=m CONFIG_PXA_FICP=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig index 3162173..3d6ce92 100644 --- a/arch/arm/configs/trizeps4_defconfig +++ b/arch/arm/configs/trizeps4_defconfig @@ -49,8 +49,8 @@ CONFIG_IRDA_CACHE_LAST_LSAP=y CONFIG_IRDA_FAST_RR=y CONFIG_IRTTY_SIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig index 8b0c717..4fe0c80 100644 --- a/arch/arm/configs/viper_defconfig +++ b/arch/arm/configs/viper_defconfig @@ -37,7 +37,7 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m +CONFIG_BT_L2CAP=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig index 960f655..f8f9910 100644 --- a/arch/arm/configs/zeus_defconfig +++ b/arch/arm/configs/zeus_defconfig @@ -32,7 +32,7 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m +CONFIG_BT_L2CAP=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -150,7 +150,7 @@ CONFIG_MMC=y # CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_PXA=y CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m diff --git a/arch/avr32/configs/atngw100_mrmt_defconfig b/arch/avr32/configs/atngw100_mrmt_defconfig index 19f6cee..6f9ed2e 100644 --- a/arch/avr32/configs/atngw100_mrmt_defconfig +++ b/arch/avr32/configs/atngw100_mrmt_defconfig @@ -36,7 +36,7 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BT=m -CONFIG_BT_L2CAP=m +CONFIG_BT_L2CAP=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_HIDP=m diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index cb2c5ea..b6acd2f 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -86,8 +86,8 @@ CONFIG_NET_SCHED=y CONFIG_NET_EMATCH=y CONFIG_NET_CLS_ACT=y CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index a97a42c..37862b2 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -225,8 +225,8 @@ CONFIG_TOSHIBA_FIR=m CONFIG_VLSI_FIR=m CONFIG_MCS_FIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/powerpc/configs/c2k_defconfig b/arch/powerpc/configs/c2k_defconfig index f9e6a3e..2a84fd7 100644 --- a/arch/powerpc/configs/c2k_defconfig +++ b/arch/powerpc/configs/c2k_defconfig @@ -132,8 +132,8 @@ CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m CONFIG_NET_CLS_IND=y CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig index ac4fc41..f8b394a 100644 --- a/arch/powerpc/configs/pmac32_defconfig +++ b/arch/powerpc/configs/pmac32_defconfig @@ -112,8 +112,8 @@ CONFIG_IRDA_CACHE_LAST_LSAP=y CONFIG_IRDA_FAST_RR=y CONFIG_IRTTY_SIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 0a10fb0..2142089 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -351,8 +351,8 @@ CONFIG_VLSI_FIR=m CONFIG_VIA_FIR=m CONFIG_MCS_FIR=m CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig index caba919..6472322 100644 --- a/arch/powerpc/configs/ps3_defconfig +++ b/arch/powerpc/configs/ps3_defconfig @@ -52,8 +52,8 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_DIAG is not set CONFIG_IPV6=y CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m -- 1.7.3 From Valdis.Kletnieks@vt.edu Sat Apr 9 21:24:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Apr 2011 21:24:08 +0200 (CEST) Received: from lennier.cc.vt.edu ([198.82.162.213]:53667 "EHLO lennier.cc.vt.edu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491014Ab1DITYF (ORCPT ); Sat, 9 Apr 2011 21:24:05 +0200 Received: from steiner.cc.vt.edu (steiner.cc.vt.edu [198.82.163.51]) by lennier.cc.vt.edu (8.13.8/8.13.8) with ESMTP id p39JNqbc021959; Sat, 9 Apr 2011 15:23:52 -0400 Received: from auth3.smtp.vt.edu (EHLO auth3.smtp.vt.edu) ([198.82.161.152]) by steiner.cc.vt.edu (MOS 4.2.2-FCS FastPath queued) with ESMTP id OHT67467; Sat, 09 Apr 2011 15:23:50 -0400 (EDT) Received: from localhost (h80ad272e.async.vt.edu [128.173.39.46]) (authenticated bits=0) by auth3.smtp.vt.edu (8.13.8/8.13.8) with ESMTP id p39JNjmi029383 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 9 Apr 2011 15:23:48 -0400 X-Mailer: exmh version 2.7.2 01/07/2005 with nmh-1.3-dev To: Ralf Baechle Cc: Joshua Kinard , Linux MIPS List , rtc-linux@googlegroups.com, LKML , Alessandro Zummo Subject: Re: [PATCH 2/2]: MIPS: sgi-ip32: Add support for rtc-ds1685 to SGI O2 (IP32) In-Reply-To: Your message of "Fri, 08 Apr 2011 15:25:34 +0200." <20110408132533.GA15416@linux-mips.org> From: Valdis.Kletnieks@vt.edu References: <4D9DB95F.8040100@gentoo.org> <20110408132533.GA15416@linux-mips.org> Mime-Version: 1.0 Content-Type: multipart/signed; boundary="==_Exmh_1302377025_4802P"; micalg=pgp-sha1; protocol="application/pgp-signature" Content-Transfer-Encoding: 7bit Date: Sat, 09 Apr 2011 15:23:45 -0400 Message-ID: <105137.1302377025@localhost> X-Mirapoint-Received-SPF: 198.82.161.152 auth3.smtp.vt.edu Valdis.Kletnieks@vt.edu 2 pass X-Mirapoint-IP-Reputation: reputation=neutral-1, source=Fixed, refid=n/a, actions=MAILHURDLE SPF TAG X-Junkmail-Status: score=10/50, host=steiner.cc.vt.edu X-Junkmail-Signature-Raw: score=unknown, refid=str=0001.0A020207.4DA0B248.00C8,ss=1,fgs=0, ip=0.0.0.0, so=2010-07-22 22:03:31, dmn=2009-09-10 00:05:08, mode=single engine X-Junkmail-IWF: false Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Valdis.Kletnieks@vt.edu Precedence: bulk X-list: linux-mips --==_Exmh_1302377025_4802P Content-Type: text/plain; charset=us-ascii On Fri, 08 Apr 2011 15:25:34 +0200, Ralf Baechle said: > On Thu, Apr 07, 2011 at 09:17:19AM -0400, Joshua Kinard wrote: > > -----BEGIN PGP SIGNED MESSAGE----- > > Hash: SHA1 > > Please don't PGP sign patches. Nobody care about your PGP signature as > long there's a valid Signed-off-by. Alternatively, fix your mailer to not send a single text/plain that PGP has signed, but use the MIME multipart/signed construct, where (a) the text/plain main part isn't changed at all, and (b) the PGP signature is in a separate bodypart. > > Signed-off-by: Joshua Kinard > > - --- > And this is a --- tearoff line corrupted by PGP. Just like every other line > starting with a -. Doing this will prevent that. The following line should appear as a single dash: - See? You *can* have your cake and eat it too. ;) --==_Exmh_1302377025_4802P Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Exmh version 2.5 07/13/2001 iD8DBQFNoLJBcC3lWbTT17ARAhlvAKChAYth386x50ejraQj7tmelO6TQgCgirdh 7nzwhfrPig62Jkqm5eNYxDI= =Cy9B -----END PGP SIGNATURE----- --==_Exmh_1302377025_4802P-- From kumba@gentoo.org Sun Apr 10 08:12:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Apr 2011 08:12:24 +0200 (CEST) Received: from qmta14.emeryville.ca.mail.comcast.net ([76.96.27.212]:34249 "EHLO qmta14.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491006Ab1DJGMQ (ORCPT ); Sun, 10 Apr 2011 08:12:16 +0200 Received: from omta15.emeryville.ca.mail.comcast.net ([76.96.30.71]) by qmta14.emeryville.ca.mail.comcast.net with comcast id ViBR1g0061Y3wxoAEiC8Vv; Sun, 10 Apr 2011 06:12:08 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta15.emeryville.ca.mail.comcast.net with comcast id ViC31g0073XYSBH8biC4zL; Sun, 10 Apr 2011 06:12:07 +0000 Message-ID: <4DA14A0D.7080203@gentoo.org> Date: Sun, 10 Apr 2011 02:11:25 -0400 From: Joshua Kinard User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 MIME-Version: 1.0 To: rtc-linux@googlegroups.com, Alessandro Zummo CC: LKML , Linux MIPS List Subject: Re: [PATCH 1/2]: rtc: rtc-ds1685: Add driver to support Dallas/Maxim DS1685/DS1687 & related chips References: <4D9DB8F6.4080208@gentoo.org> In-Reply-To: <4D9DB8F6.4080208@gentoo.org> X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29722 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips On 04/07/2011 09:15, Joshua Kinard wrote: > > This patch adds the core driver in drivers/rtc, the header file in > include/linux/rtc, and modifies the appropriate Kconfig & Makefiles. > > I want to give a shoutout to the people at StackOverflow that assisted in the > register bit lookup table function. That helped reduce the overall code for the > SysFS debug bits significantly. Thanks! Updated patch, mostly addressing a few typos I discovered in some comments. Also, no PGP this time :) Signed-off-by: Joshua Kinard --- drivers/rtc/Kconfig | 90 + drivers/rtc/Makefile | 1 drivers/rtc/rtc-ds1685.c | 2178 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/rtc/ds1685.h | 334 ++++++ 4 files changed, 2603 insertions(+) diff -Naurp a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -511,6 +511,96 @@ config RTC_DRV_DS1553 This driver can also be built as a module. If so, the module will be called rtc-ds1553. +config RTC_DRV_DS1685_FAMILY + tristate "Dallas/Maxim DS1685 Family" + help + If you say yes here you get support for the Dallas/Maxim DS1685 + family of real time chips. This family includes the DS1685/DS1687, + DS1689/DS1693, DS17285/DS17287, DS17485/DS17487, and + DS17885/DS17887 chips. + + This driver can also be built as a module. If so, the module + will be called rtc-ds1685. + +choice + prompt "Subtype" + depends on RTC_DRV_DS1685_FAMILY + default RTC_DRV_DS1685 + +config RTC_DRV_DS1685 + bool "DS1685/DS1687" + help + This enables support for the Dallas/Maxim DS1685/DS1687 real time + clock chip. + + This chip is commonly found in SGI O2 (IP32) and SGI Octane (IP30) + systems, as well as EPPC-405-UC modules by electronic system design + GmbH. + +config RTC_DRV_DS1689 + bool "DS1689/DS1693" + help + This enables support for the Dallas/Maxim DS1689/DS1693 real time + clock chip. + + This is an older RTC chip, supplanted by the DS1685/DS1687 above, + which supports a few minor features such as Vcc, Vbat, and Power + Cycle counters, plus a customer-specific, 8-byte ROM/Serial number. + + It also works for the even older DS1688/DS1691 RTC chips, which are + virtually the same and carry the same model number. Both chips + have 114 bytes of user NVRAM. + +config RTC_DRV_DS17285 + bool "DS17285/DS17287" + help + This enables support for the Dallas/Maxim DS17285/DS17287 real time + clock chip. + + This chip features 2kb of extended NV-SRAM. It may possibly be + found in some SGI O2 systems (rare). + +config RTC_DRV_DS17485 + bool "DS17485/DS17487" + help + This enables support for the Dallas/Maxim DS17485/DS17487 real time + clock chip. + + This chip features 4kb of extended NV-SRAM. + +config RTC_DRV_DS17885 + bool "DS17885/DS17887" + help + This enables support for the Dallas/Maxim DS17885/DS17887 real time + clock chip. + + This chip features 8kb of extended NV-SRAM. + +endchoice + +config RTC_DS1685_PROC_REGS + bool "Display register values in /proc" + depends on RTC_DRV_DS1685_FAMILY && PROC_FS + help + Enable this to display a readout of all of the RTC registers in + /proc/drivers/rtc. Keep in mind that this can potentially lead + to lost interrupts, as reading Control Register C will clear + all pending IRQ flags. + + Unless you are debugging this driver, choose N. + +config RTC_DS1685_SYSFS_REGS + bool "SysFS access to RTC register bits" + depends on RTC_DRV_DS1685_FAMILY && SYSFS + help + Enable this to provide access to the RTC control register bits + in /sys. Some of the bits are read-write, others are read-only. + + Keep in mind that reading Control C's bits automatically clears + all pending IRQ flags - this can cause lost interrupts. + + If you know that you need access to these bits, choose Y, Else N. + config RTC_DRV_DS1742 tristate "Maxim/Dallas DS1742/1743" help diff -Naurp a/drivers/rtc/Makefile b/drivers/rtc/Makefile --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_RTC_DRV_DS1390) += rtc-ds13 obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o +obj-$(CONFIG_RTC_DRV_DS1685_FAMILY) += rtc-ds1685.o obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o diff -Naurp a/drivers/rtc/rtc-ds1685.c b/drivers/rtc/rtc-ds1685.c --- a/drivers/rtc/rtc-ds1685.c +++ b/drivers/rtc/rtc-ds1685.c @@ -0,0 +1,2178 @@ +/* + * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time + * chips. + * + * Copyright (C) 2011 Joshua Kinard . + * Copyright (C) 2009 Matthias Fuchs . + * + * References: + * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. + * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. + * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. + * Application Note 90, Using the Multiplex Bus RTC Extended Features. + * + * Todo: + * - Implement pio access. mmio only for now. + * - Platform data function for custom time checks (some archs are weird). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_PROC_FS +#include +#endif + +#define DRV_VERSION "0.42" + + +/* ----------------------------------------------------------------------- */ +/* Inlined functions */ + +/** + * ds1685_read - read a value from an rtc register. + * @rtc: pointer to the ds1685 rtc structure. + * @reg: the register address to read. + */ +static inline u8 +ds1685_read(struct ds1685_priv *rtc, int reg) +{ + return readb((volatile u8 __iomem *)rtc->regs + + (reg * rtc->regstep)); +} + + +/** + * ds1685_write - write a value to an rtc register. + * @rtc: pointer to the ds1685 rtc structure. + * @reg: the register address to write. + * @value: value to write to the register. + */ +static inline void +ds1685_write(struct ds1685_priv *rtc, int reg, u8 value) +{ + writeb(value, (volatile u8 __iomem *)rtc->regs + + (reg * rtc->regstep)); +} + + +/** + * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0. + * @rtc: pointer to the ds1685 rtc structure. + */ +static inline void +ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc) +{ + ds1685_write(rtc, RTC_CTRL_A, + (ds1685_read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0))); +} + + +/** + * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1. + * @rtc: pointer to the ds1685 rtc structure. + */ +static inline void +ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc) +{ + ds1685_write(rtc, RTC_CTRL_A, + (ds1685_read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0)); +} + + +/** + * ds1685_rtc_begin_data_access - prepare the rtc for data access. + * @rtc: pointer to the ds1685 rtc structure. + * + * This takes several steps to prepare the rtc for access to get/set time + * and alarm values from the rtc registers: + * - Sets the SET bit in Control Register B. + * - Reads Control Register A and checks the UIP bit. + * - If UIP is active, a short delay is added before Control Register A + * is read again in a loop until UIP is inactive. + * - Switches the rtc to bank 1. This allows access to all relevant + * data for normal rtc operation, as bank 0 contains only the nvram. + */ +static inline void +ds1685_rtc_begin_data_access(struct ds1685_priv *rtc) +{ + unsigned long uip_watchdog = jiffies; + + /* Set the SET bit in Ctrl B */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); + + /* Read Ctrl A and check the UIP bit to avoid a lockout. */ + while ((ds1685_read(rtc, RTC_CTRL_A) & RTC_CTRL_A_UIP) && + (time_before(jiffies, uip_watchdog + (2 * HZ / 100)))) + cpu_relax(); + + /* Switch to Bank 1 */ + ds1685_rtc_switch_to_bank1(rtc); +} + + +/** + * ds1685_rtc_end_data_access - end data access on the rtc. + * @rtc: pointer to the ds1685 rtc structure. + * + * This ends what was started by ds1685_rtc_begin_data_access: + * - Switches the rtc back to bank 0. + * - Clears the SET bit in Control Register B. + */ +static inline void +ds1685_rtc_end_data_access(struct ds1685_priv *rtc) +{ + /* Switch back to Bank 0 */ + ds1685_rtc_switch_to_bank1(rtc); + + /* Clear the SET bit in Ctrl B */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); +} + + +/** + * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access. + * @rtc: pointer to the ds1685 rtc structure. + * @flags: irq flags variable for spin_lock_irqsave. + * + * This takes several steps to prepare the rtc for access to read just the + * control registers: + * - Sets a spinlock on the rtc IRQ. + * - Switches the rtc to bank 1. This allows access to the two extended + * control registers. + * + * Only use this where you are certain another lock will not be held. + */ +static inline void +ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long flags) +{ + spin_lock_irqsave(&rtc->lock, flags); + ds1685_rtc_switch_to_bank1(rtc); +} + + +/** + * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc. + * @rtc: pointer to the ds1685 rtc structure. + * @flags: irq flags variable for spin_unlock_irqrestore. + * + * This ends what was started by ds1685_rtc_begin_ctrl_access: + * - Switches the rtc back to bank 0. + * - Unsets the spinlock on the rtc IRQ. + */ +static inline void +ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags) +{ + ds1685_rtc_switch_to_bank0(rtc); + spin_unlock_irqrestore(&rtc->lock, flags); +} + + +/** + * ds1685_rtc_get_ssn - retrieve the silicon serial number. + * @rtc: pointer to the ds1685 rtc structure. + * @ssn: u8 array to hold the bits of the silicon serial number. + * + * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The + * first byte is the model number, the next six bytes are the serial number + * digits, and the final byte is a CRC check byte. Together, they form the + * silicon serial number. + * + * These values are stored in bank1, so call ds1685_rtc_switch_to_bank1 + * before calling this function, else you will read data out of the bank0 + * NVRAM! Remember to call ds1685_rtc_switch_to_bank0 when you're done to + * switch back to bank0. + */ +static inline void +ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn) +{ + ssn[0] = ds1685_read(rtc, RTC_BANK1_SSN_MODEL); + ssn[1] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_1); + ssn[2] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_2); + ssn[3] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_3); + ssn[4] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_4); + ssn[5] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_5); + ssn[6] = ds1685_read(rtc, RTC_BANK1_SSN_BYTE_6); + ssn[7] = ds1685_read(rtc, RTC_BANK1_SSN_CRC); +} +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* Read/Set Time & Alarm functions */ + +/** + * ds1685_rtc_read_time - reads the time registers. + * @dev: pointer to device structure. + * @tm: pointer to rtc_time structure. + */ +static int +ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrlb, century; + u8 seconds, minutes, hours, wday, mday, month, years; + + /* Fetch the time info from the RTC registers. */ + ds1685_rtc_begin_data_access(rtc); + seconds = ds1685_read(rtc, RTC_SECONDS) & RTC_SECONDS_MASK; + minutes = ds1685_read(rtc, RTC_MINUTES) & RTC_MINUTES_MASK; + hours = ds1685_read(rtc, RTC_HOURS) & RTC_HOURS_24_MASK; + wday = ds1685_read(rtc, RTC_WDAY) & RTC_WDAY_MASK; + mday = ds1685_read(rtc, RTC_MDAY) & RTC_MDAY_MASK; + month = ds1685_read(rtc, RTC_MONTH) & RTC_MONTH_MASK; + years = ds1685_read(rtc, RTC_YEAR) & RTC_YEAR_MASK; + century = ds1685_read(rtc, RTC_CENTURY) & RTC_CENTURY_MASK; + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ds1685_rtc_end_data_access(rtc); + + /* Convert to Binary, perform fixups, and store to rtc_time. */ + tm->tm_sec = bcd2bin(seconds); + tm->tm_min = bcd2bin(minutes); + tm->tm_hour = bcd2bin(hours); + tm->tm_wday = (bcd2bin(wday) - 1); + tm->tm_mday = bcd2bin(mday); + tm->tm_mon = (bcd2bin(month) - 1); + tm->tm_year = ((bcd2bin(years) + (bcd2bin(century) * 100)) - 1900); + tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); + tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */ + + return rtc_valid_tm(tm); +} + + +/** + * ds1685_rtc_set_time - sets the time registers. + * @dev: pointer to device structure. + * @tm: pointer to rtc_time structure. + */ +static int +ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 seconds, minutes, hours, wday, mday, month, years, century; + + /* Fetch the time info from rtc_time. */ + seconds = bin2bcd(tm->tm_sec); + minutes = bin2bcd(tm->tm_min); + hours = bin2bcd(tm->tm_hour); + wday = bin2bcd(tm->tm_wday + 1); + mday = bin2bcd(tm->tm_mday); + month = bin2bcd(tm->tm_mon + 1); + years = bin2bcd(tm->tm_year % 100); + century = bin2bcd((tm->tm_year + 1900) / 100); + + /* + * Perform Sanity Checks: + * - Months: !> 12, Month Day != 0. + * - Month Day !> Max days in current month. + * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. + */ + if ((month > 12) || (mday == 0)) + return -EDOM; + + if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) + return -EDOM; + + if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || + (tm->tm_sec >= 60) || (wday > 7)) + return -EDOM; + + /* + * Force datamode to BCD (DM=0) and and store the time values in + * the RTC registers. + */ + ds1685_rtc_begin_data_access(rtc); + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_DM))); + ds1685_write(rtc, RTC_SECONDS, seconds & RTC_SECONDS_MASK); + ds1685_write(rtc, RTC_MINUTES, minutes & RTC_MINUTES_MASK); + ds1685_write(rtc, RTC_HOURS, hours & RTC_HOURS_24_MASK); + ds1685_write(rtc, RTC_WDAY, wday & RTC_WDAY_MASK); + ds1685_write(rtc, RTC_MDAY, mday & RTC_MDAY_MASK); + ds1685_write(rtc, RTC_MONTH, month & RTC_MONTH_MASK); + ds1685_write(rtc, RTC_YEAR, years & RTC_YEAR_MASK); + ds1685_write(rtc, RTC_CENTURY, century & RTC_CENTURY_MASK); + ds1685_rtc_end_data_access(rtc); + + return 0; +} + + +/** + * ds1685_rtc_read_alarm - reads the alarm registers. + * @dev: pointer to device structure. + * @alrm: pointer to rtc_wkalrm structure. + * + * There are three primary alarm registers: seconds, minutes, and hours. + * A fourth alarm register for the month date is also available in bank1 for + * kickstart/wakeup features. The DS1685/DS1687 manual states that a + * "don't care" value ranging from 0xc0 to 0xff may be written into one or + * more of the three alarm bytes to act as a wildcard value. The fourth + * byte doesn't support a "don't care" value. + */ +static int +ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 seconds, minutes, hours, mday, ctrlb, ctrlc; + + /* Fetch the alarm info from the RTC alarm registers. */ + ds1685_rtc_begin_data_access(rtc); + seconds = ds1685_read(rtc, RTC_SECONDS_ALARM) & RTC_SECONDS_MASK; + minutes = ds1685_read(rtc, RTC_MINUTES_ALARM) & RTC_MINUTES_MASK; + hours = ds1685_read(rtc, RTC_HOURS_ALARM) & RTC_HOURS_24_MASK; + mday = ds1685_read(rtc, RTC_MDAY_ALARM) & RTC_MDAY_MASK; + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ctrlc = ds1685_read(rtc, RTC_CTRL_C); + ds1685_rtc_end_data_access(rtc); + + /* Check month date. */ + if (!(mday >= 1) && (mday <= 31)) + return -EDOM; + + /* + * Check the three alarm bytes. + * + * The Linux RTC system doesn't support the "don't care" capability + * of this RTC chip. We check for it anyways in case support is + * added in the future. + */ + if (unlikely((seconds >= 0xc0) && (seconds <= 0xff))) + alrm->time.tm_sec = -1; + else + alrm->time.tm_sec = bcd2bin(seconds); + + if (unlikely((minutes >= 0xc0) && (minutes <= 0xff))) + alrm->time.tm_min = -1; + else + alrm->time.tm_min = bcd2bin(minutes); + + if (unlikely((hours >= 0xc0) && (hours <= 0xff))) + alrm->time.tm_hour = -1; + else + alrm->time.tm_hour = bcd2bin(hours); + + /* Write the data to rtc_wkalrm. */ + alrm->time.tm_mday = bcd2bin(mday); + alrm->time.tm_mon = -1; + alrm->time.tm_year = -1; + alrm->time.tm_wday = -1; + alrm->time.tm_yday = -1; + alrm->time.tm_isdst = -1; + alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE); + alrm->pending = !!(ctrlc & RTC_CTRL_C_AF); + + return 0; +} + + +/** + * ds1685_rtc_set_alarm - sets the alarm in registers. + * @dev: pointer to device structure. + * @alrm: pointer to rtc_wkalrm structure. + */ +static int +ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 seconds, minutes, hours, mday, ctrlb; + + /* Fetch the alarm info and convert to BCD. */ + seconds = bin2bcd(alrm->time.tm_sec); + minutes = bin2bcd(alrm->time.tm_min); + hours = bin2bcd(alrm->time.tm_hour); + mday = bin2bcd(alrm->time.tm_mday); + + /* Check the month date for validity. */ + if (!(mday >= 1) && (mday <= 31)) + return -EDOM; + + /* + * Check the three alarm bytes. + * + * The Linux RTC system doesn't support the "don't care" capability + * of this RTC chip because rtc_valid_tm tries to validate every + * field, and we only support four fields. We put the support + * here anyways for the future. + */ + if (unlikely((seconds >= 0xc0) && (seconds <= 0xff))) + seconds = 0xff; + + if (unlikely((minutes >= 0xc0) && (minutes <= 0xff))) + minutes = 0xff; + + if (unlikely((hours >= 0xc0) && (hours <= 0xff))) + hours = 0xff; + + alrm->time.tm_mon = -1; + alrm->time.tm_year = -1; + alrm->time.tm_wday = -1; + alrm->time.tm_yday = -1; + alrm->time.tm_isdst = -1; + + /* Disable the alarm interrupt first. */ + ds1685_rtc_begin_data_access(rtc); + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ds1685_write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE))); + + /* Read ctrlc to clear RTC_CTRL_C_AF. */ + ds1685_read(rtc, RTC_CTRL_C); + + /* + * Force datamode to BCD (DM=0) and store the alarm values in the + * RTC registers. + */ + ds1685_rtc_begin_data_access(rtc); + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_DM))); + ds1685_write(rtc, RTC_SECONDS_ALARM, seconds & RTC_SECONDS_MASK); + ds1685_write(rtc, RTC_MINUTES_ALARM, minutes & RTC_MINUTES_MASK); + ds1685_write(rtc, RTC_HOURS_ALARM, hours & RTC_HOURS_24_MASK); + ds1685_write(rtc, RTC_MDAY_ALARM, mday & RTC_MDAY_MASK); + + /* Re-enable the alarm if needed. */ + if (alrm->enabled) { + ctrlb |= RTC_CTRL_B_AIE; + ds1685_write(rtc, RTC_CTRL_B, ctrlb); + } + + /* Done! */ + ds1685_rtc_end_data_access(rtc); + + return 0; +} +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ + +/* Periodic Interrupt Rate & Square-Wave Output functionality. */ + +#if defined(CONFIG_RTC_INTF_DEV) || defined(CONFIG_SYSFS) +/** + * ds1685_rtc_set_freq - sets the periodic irq rate/square-wave freq. + * @dev: pointer to device structure. + * @freq: integer value of the frequency to set. + */ +static int +ds1685_rtc_set_freq(struct device *dev, int freq) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 rate, ctrla, ctrlb, ctrl4b; + unsigned char e32k = 0; + unsigned long flags = 0; + + /* 8192Hz is the highest user-selectable frequency, unless 32768Hz. */ + if (((freq > RTC_MAX_USER_FREQ) && (freq != RTC_SQW_32768HZ)) || + (freq < 0)) + return -ERANGE; + + /* Set the rate/frequency. */ + switch (freq) { + case 0: rate = RTC_SQW_0HZ; break; + case 2: rate = RTC_SQW_2HZ; break; + case 4: rate = RTC_SQW_4HZ; break; + case 8: rate = RTC_SQW_8HZ; break; + case 16: rate = RTC_SQW_16HZ; break; + case 32: rate = RTC_SQW_32HZ; break; + case 64: rate = RTC_SQW_64HZ; break; + case 128: rate = RTC_SQW_128HZ; break; + case 256: rate = RTC_SQW_256HZ; break; + case 512: rate = RTC_SQW_512HZ; break; + case 1024: rate = RTC_SQW_1024HZ; break; + case 2048: rate = RTC_SQW_2048HZ; break; + case 4096: rate = RTC_SQW_4096HZ; break; + case 8192: rate = RTC_SQW_8192HZ; break; + case 32768: + rate = 0; + e32k = 1; + break; + default: + return -EDOM; + break; + } + + /* Read the current rate/frequency from the RTC. */ + ds1685_rtc_begin_ctrl_access(rtc, flags); + ctrla = ds1685_read(rtc, RTC_CTRL_A); + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + ds1685_rtc_end_ctrl_access(rtc, flags); + + /* If 32768Hz, clear RS3-RS0 in Ctrl A and set E32K in Ctrl 4B. */ + if (e32k) { + ctrla &= ~(RTC_CTRL_A_RS_MASK); + ctrl4b |= RTC_CTRL_4B_E32K; + } else { + /* Else, clear E32K in Ctrl 4B and set RS3-RS0 in Ctrl A. */ + ctrl4b &= ~(RTC_CTRL_4B_E32K); + ctrla &= ~(RTC_CTRL_A_RS_MASK); + ctrla |= rate; + } + + /* Write the rate/frequency to the RTC. */ + ds1685_rtc_begin_ctrl_access(rtc, flags); + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ds1685_write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_SQWE))); + ds1685_write(rtc, RTC_CTRL_A, ctrla); + ds1685_write(rtc, RTC_EXT_CTRL_4B, ctrl4b); + ds1685_write(rtc, RTC_CTRL_B, (ctrlb | RTC_CTRL_B_SQWE)); + ds1685_rtc_end_ctrl_access(rtc, flags); + + return 0; +} +#else +#define ds1685_rtc_set_freq NULL +#endif /* CONFIG_RTC_INTF_DEV || CONFIG_SYSFS */ +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* /dev/rtcX Interface functions */ + +#ifdef CONFIG_RTC_INTF_DEV +/** + * ds1685_rtc_irq_ctrl - enables/disables an interrupt. + * @rtc: pointer to the ds1685 rtc structure. + * @reg: the register address to use. + * @irq_bit: the register bit for the irq to modify. + * @enabled: boolean value indicating the state to set the irq bit to. + * @flags: irq flags variable for spin_lock_irqsave/spin_unlock_irqrestore. + * + * PIE/AIE/UIE are read/written in Ctrl B, and RIE/WIE/KSE in Ctrl 4B. + * RTC Core doesn't know about RIE/WIE/KSE, so they are not processed here. + */ +static inline void +ds1685_rtc_irq_ctrl(struct ds1685_priv *rtc, const int reg, const u8 irq_bit, + const u8 enabled, unsigned long flags) +{ + spin_lock_irqsave(&rtc->lock, flags); + + /* Flip the requisite interrupt-enable bit. */ + if (enabled) + ds1685_write(rtc, reg, (ds1685_read(rtc, reg) | irq_bit)); + else + ds1685_write(rtc, reg, (ds1685_read(rtc, reg) & ~(irq_bit))); + + /* Read Control C to clear all the flag bits. */ + ds1685_read(rtc, RTC_CTRL_C); + spin_unlock_irqrestore(&rtc->lock, flags); +} + + +/** + * ds1685_rtc_periodic_irq_enable - replaces ioctl() RTC_PIE on/off. + * @dev: pointer to device structure. + * @enabled: flag indicating whether to enable or disable. + * + * XXX: 2nd arg should be 'unsigned int', but needs fix in RTC core. + */ +static int +ds1685_rtc_periodic_irq_enable(struct device *dev, int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + unsigned long flags = 0; + + spin_lock_irqsave(&rtc->lock, flags); + ds1685_rtc_switch_to_bank1(rtc); + + /* Periodic IRQs are not possible if E32K = 1 in Control 4B. */ + if (ds1685_read(rtc, RTC_EXT_CTRL_4B) & RTC_CTRL_4B_E32K) + goto no_irq; + + /* Periodic IRQs are not possible if RS3-RS0 = 0 in Control A. */ + if (!(ds1685_read(rtc, RTC_CTRL_A) & RTC_CTRL_A_RS_MASK)) + goto no_irq; + + /* Done with our sanity checks. */ + ds1685_rtc_switch_to_bank0(rtc); + spin_unlock_irqrestore(&rtc->lock, flags); + + /* Enable/disable the Periodic IRQ-Enable flag. */ + ds1685_rtc_irq_ctrl(rtc, RTC_CTRL_B, RTC_CTRL_B_PIE, enabled, flags); + + return 0; + + no_irq: + ds1685_rtc_switch_to_bank0(rtc); + spin_unlock_irqrestore(&rtc->lock, flags); + return -EINVAL; +} + + +/** + * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off. + * @dev: pointer to device structure. + * @enabled: flag indicating whether to enable or disable. + */ +static int +ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + unsigned long flags = 0; + + /* Enable/disable the Alarm IRQ-Enable flag. */ + ds1685_rtc_irq_ctrl(rtc, RTC_CTRL_B, RTC_CTRL_B_AIE, enabled, flags); + + return 0; +} + + +/** + * ds1685_rtc_update_irq_enable - replaces ioctl() RTC_UIE on/off. + * @dev: pointer to device structure. + * @enabled: flag indicating whether to enable or disable. + */ +static int +ds1685_rtc_update_irq_enable(struct device *dev, unsigned int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + unsigned long flags = 0; + + /* Enable/disable the Update IRQ-Enable flag. */ + ds1685_rtc_irq_ctrl(rtc, RTC_CTRL_B, RTC_CTRL_B_UIE, enabled, flags); + + return 0; +} + + +#else +#define ds1685_rtc_periodic_irq_enable NULL +#define ds1685_rtc_alarm_irq_enable NULL +#define ds1685_rtc_update_irq_enable NULL +#endif /* CONFIG_RTC_INTF_DEV */ +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* IRQ handler & workqueue. */ + + +/** + * ds1685_rtc_irq_handler - IRQ handler. + * @irq: IRQ number. + * @dev_id: platform device pointer. + */ +static irqreturn_t +ds1685_rtc_irq_handler(int irq, void *dev_id) +{ + struct platform_device *pdev = dev_id; + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrlb, ctrlc; + unsigned long events = 0; + u8 num_irqs = 0; + + /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */ + if (unlikely(!rtc)) + return IRQ_HANDLED; + + /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */ + spin_lock(&rtc->lock); + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ctrlc = ds1685_read(rtc, RTC_CTRL_C); + + /* Is the IRQF bit set? */ + if (likely(ctrlc & RTC_CTRL_C_IRQF)) { + /* + * We need to determine if it was one of the standard + * events: PF, AF, or UF. If so, we handle them and + * update the RTC core. + */ + if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) { + events = RTC_IRQF; + + /* Check for a periodic interrupt. */ + if ((ctrlb & RTC_CTRL_B_PIE) && + (ctrlc & RTC_CTRL_C_PF)) { + events |= RTC_PF; + num_irqs++; + } + + /* Check for an alarm interrupt. */ + if ((ctrlb & RTC_CTRL_B_AIE) && + (ctrlc & RTC_CTRL_C_AF)) { + events |= RTC_AF; + num_irqs++; + } + + /* Check for an update interrupt. */ + if ((ctrlb & RTC_CTRL_B_UIE) && + (ctrlc & RTC_CTRL_C_UF)) { + events |= RTC_UF; + num_irqs++; + } + + rtc_update_irq(rtc->dev, num_irqs, events); + } else { + /* + * We received one of the "extended" interrupts + * which are not recognized by the RTC core. These + * need to be handled in task context as they can + * call other functions and we don't want to be in + * irq context for too long, so we schedule them + * into a workqueue and inform the RTC core that + * nothing happened. + */ + spin_unlock(&rtc->lock); + schedule_work(&rtc->work); + rtc_update_irq(rtc->dev, 0, 0); + return IRQ_HANDLED; + } + } + spin_unlock(&rtc->lock); + + return events ? IRQ_HANDLED : IRQ_NONE; +} + + +/** + * ds1685_rtc_work_queue - work queue handler. + * @work: work_struct containing data to work on in task context. + */ +static void +ds1685_rtc_work_queue(struct work_struct *work) +{ + struct ds1685_priv *rtc = container_of(work, + struct ds1685_priv, work); + struct platform_device *pdev = to_platform_device(&rtc->dev->dev); + struct mutex *rtc_mutex = &rtc->dev->ops_lock; + u8 ctrl4a, ctrl4b; + + mutex_lock(rtc_mutex); + + ds1685_rtc_switch_to_bank1(rtc); + ctrl4a = ds1685_read(rtc, RTC_EXT_CTRL_4A); + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + + /* + * Check for a kickstart interrupt. With Vcc applied, this + * typically means that the power button was pressed, so we + * begin the shutdown sequence. + */ + if ((ctrl4b & RTC_CTRL_4B_KSE) && + (ctrl4a & RTC_CTRL_4A_KF)) { + /* Briefly disable kickstarts to debounce button presses. */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) & + ~(RTC_CTRL_4B_KSE))); + + /* Clear the kickstart flag. */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ctrl4a & ~(RTC_CTRL_4A_KF))); + + + /* + * Sleep 500ms before re-enabling kickstarts. This allows + * adequate time to avoid reading signal jitter as additional + * button presses. + */ + msleep(500); + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) | + RTC_CTRL_4B_KSE)); + + /* Call the platform pre-poweroff function. Else, shutdown. */ + if (rtc->prepare_poweroff != NULL) + rtc->prepare_poweroff(); + else + ds1685_rtc_poweroff(pdev); + } + + /* + * Check for a wake-up interrupt. With Vcc applied, this is + * essentially a second alarm interrupt, except it takes into + * account the 'date' register in bank1 in addition to the + * standard three alarm registers. + */ + if ((ctrl4b & RTC_CTRL_4B_WIE) && + (ctrl4a & RTC_CTRL_4A_WF)) { + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ctrl4a & ~(RTC_CTRL_4A_WF))); + + /* Call the platform wake_alarm function if defined. */ + if (rtc->wake_alarm != NULL) + rtc->wake_alarm(); + else + dev_warn(&pdev->dev, + "Wake Alarm IRQ just occurred!\n"); + } + + /* + * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0 + * when RCE in 4B is set to a logic 1. This clears all NVRAM bytes + * in bank0 by setting each byte to a logic 1. This has no effect + * on any extended NV-SRAM that might be present, nor on the + * time/calendar/alarm registers. After a ram-clear is completed, + * there is a minimum recovery time of ~150ms in which all + * reads/writes are locked out. NOTE: A ram-clear can still occur + * if RCE=1 and RIE=0. We cannot catch this scenario. + */ + if ((ctrl4b & RTC_CTRL_4B_RIE) && + (ctrl4a & RTC_CTRL_4A_RF)) { + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ctrl4a & ~(RTC_CTRL_4A_RF))); + msleep(150); + + /* Call the platform post_ram_clear function if defined. */ + if (rtc->post_ram_clear != NULL) + rtc->post_ram_clear(); + else + dev_warn(&pdev->dev, + "RAM-Clear IRQ just occurred!\n"); + } + ds1685_rtc_switch_to_bank0(rtc); + + mutex_unlock(rtc_mutex); +} +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* ProcFS interface */ + +#ifdef CONFIG_PROC_FS +#define NUM_REGS 6 /* Num of control registers. */ +#define NUM_BITS 8 /* Num bits per register. */ +#define NUM_SPACES 4 /* Num spaces between each bit. */ + +/* + * Periodic Interrupt Rates. + */ +static const char *ds1685_rtc_pirq_rate[16] = { + "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms", + "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms", + "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" +}; + + +/* + * Square-Wave Output Frequencies. + */ +static const char *ds1685_rtc_sqw_freq[16] = { + "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", + "1024Hz", "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", + "8Hz", "4Hz", "2Hz" +}; + + +#ifdef CONFIG_RTC_DS1685_PROC_REGS +/** + * ds1685_rtc_print_regs - helper function to print register values. + * @hex: hex byte to convert into binary bits. + * @dest: destination char array. + * + * This is basically a hex->binary function, just with extra spacing between + * the digits. It only works on 1-byte values (8 bits). + */ +static char* +ds1685_rtc_print_regs(u8 hex, char *dest) +{ + u32 i, j; + char *tmp = dest; + + for (i = 0; i < NUM_BITS; i++) { + *tmp++ = ((hex & 0x80) != 0 ? '1' : '0'); + for (j = 0; j < NUM_SPACES; j++) + *tmp++ = ' '; + hex <<= 1; + } + *tmp++ = '\0'; + + return dest; +} +#endif + + +/** + * ds1685_rtc_proc - procfs access function. + * @dev: pointer to device structure. + * @seq: pointer to seq_file structure. + */ +static int +ds1685_rtc_proc(struct device *dev, struct seq_file *seq) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8]; + char *model = '\0'; +#ifdef CONFIG_RTC_DS1685_PROC_REGS + char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1]; +#endif + + /* Read all the relevant data from the control registers. */ + ds1685_rtc_switch_to_bank1(rtc); + ds1685_rtc_get_ssn(rtc, ssn); + ctrla = ds1685_read(rtc, RTC_CTRL_A); + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + ctrlc = ds1685_read(rtc, RTC_CTRL_C); + ctrld = ds1685_read(rtc, RTC_CTRL_D); + ctrl4a = ds1685_read(rtc, RTC_EXT_CTRL_4A); + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + ds1685_rtc_switch_to_bank0(rtc); + + /* Determine the RTC model. */ + switch (ssn[0]) { + case RTC_MODEL_DS1685: model = "DS1685/DS1687\0"; break; + case RTC_MODEL_DS1689: model = "DS1689/DS1693\0"; break; + case RTC_MODEL_DS17285: model = "DS17285/DS17287\0"; break; + case RTC_MODEL_DS17485: model = "DS17485/DS17487\0"; break; + case RTC_MODEL_DS17885: model = "DS17885/DS17887\0"; break; + default: model = "Unknown\0"; break; + } + + /* Print out the information. */ + seq_printf(seq, + "Model\t\t: %s\n" + "Oscillator\t: %s\n" + "12/24hr\t\t: %s\n" + "DST\t\t: %s\n" + "Data mode\t: %s\n" + "Battery\t\t: %s\n" + "Aux batt\t: %s\n" + "Update IRQ\t: %s\n" + "Periodic IRQ\t: %s\n" + "Periodic Rate\t: %s\n" + "SQW Freq\t: %s\n" +#ifdef CONFIG_RTC_DS1685_PROC_REGS + "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n" + "Register Status\t:\n" + " Ctrl A\t: " + "UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n\t\t: %s\n" + " Ctrl B\t: " + "SET PIE AIE UIE SQWE DM 2412 DSE\n\t\t: %s\n" + " Ctrl C\t: " + "IRQF PF AF UF --- --- --- ---\n\t\t: %s\n" + " Ctrl D\t: " + "VRT --- --- --- --- --- --- ---\n\t\t: %s\n" + " Ctrl 4A\t: " + "VRT2 INCR --- --- PAB RF WF KF\n\t\t: %s\n" + " Ctrl 4B\t: " + "ABE E32k CS RCE PRS RIE WIE KSE\n\t\t: %s\n", +#else + "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", +#endif + model, + ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), + ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), + ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), + ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), + ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), + ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), + ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"), + ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"), + (!(ctrl4b & RTC_CTRL_4B_E32K) ? + ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"), + (!((ctrl4b & RTC_CTRL_4B_E32K)) ? + ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"), +#ifdef CONFIG_RTC_DS1685_PROC_REGS + ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], ssn[7], + ds1685_rtc_print_regs(ctrla, bits[0]), + ds1685_rtc_print_regs(ctrlb, bits[1]), + ds1685_rtc_print_regs(ctrlc, bits[2]), + ds1685_rtc_print_regs(ctrld, bits[3]), + ds1685_rtc_print_regs(ctrl4a, bits[4]), + ds1685_rtc_print_regs(ctrl4b, bits[5])); +#else + ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], ssn[7]); +#endif + return 0; +} +#else +#define ds1685_rtc_proc NULL +#endif /* CONFIG_PROC_FS */ +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* RTC Class operations */ + +static const struct rtc_class_ops ds1685_rtc_ops = { + .proc = ds1685_rtc_proc, + .read_time = ds1685_rtc_read_time, + .set_time = ds1685_rtc_set_time, + .read_alarm = ds1685_rtc_read_alarm, + .set_alarm = ds1685_rtc_set_alarm, + .irq_set_freq = ds1685_rtc_set_freq, + .irq_set_state = ds1685_rtc_periodic_irq_enable, + .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, + .update_irq_enable = ds1685_rtc_update_irq_enable, +}; +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* SysFS interface */ + +#ifdef CONFIG_SYSFS +/** + * ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs. + * @file: pointer to file structure. + * @kobj: pointer to kobject structure. + * @bin_attr: pointer to bin_attribute structure. + * @buf: pointer to char array to hold the output. + * @pos: current file position pointer. + * @size: size of the data to read. + */ +static ssize_t +ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t pos, size_t size) +{ + struct platform_device *pdev = + to_platform_device(container_of(kobj, struct device, kobj)); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + ssize_t count; + unsigned long flags = 0; + + spin_lock_irqsave(&rtc->lock, flags); + ds1685_rtc_switch_to_bank0(rtc); + + /* Read NVRAM in time and bank0 registers. */ + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; + count++, size--) { + if (count < NVRAM_SZ_TIME) + *buf++ = ds1685_read(rtc, (NVRAM_TIME_BASE + + pos++)); + else + *buf++ = ds1685_read(rtc, (NVRAM_BANK0_BASE + + pos++)); + } + +#ifndef CONFIG_RTC_DRV_DS1689 + if (size > 0) { + ds1685_rtc_switch_to_bank1(rtc); + +#ifndef CONFIG_RTC_DRV_DS1685 + /* Enable burst-mode on DS17x85/DS17x87 */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) | + RTC_CTRL_4A_BME)); + + /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start + * reading with burst-mode */ + ds1685_write(rtc, RTC_BANK1_RAM_ADDR_LSB, + (pos - NVRAM_TOTAL_SZ_BANK0)); +#endif + + /* Read NVRAM in bank1 registers. */ + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; + count++, size--) { +#ifdef CONFIG_RTC_DRV_DS1685 + /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR + * before each read. */ + ds1685_write(rtc, RTC_BANK1_RAM_ADDR, + (pos - NVRAM_TOTAL_SZ_BANK0)); +#endif + *buf++ = ds1685_read(rtc, RTC_BANK1_RAM_DATA_PORT); + pos++; + } + +#ifndef CONFIG_RTC_DRV_DS1685 + /* Disable burst-mode on DS17x85/DS17x87 */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) & + ~(RTC_CTRL_4A_BME))); +#endif + ds1685_rtc_switch_to_bank0(rtc); + } +#endif /* !CONFIG_RTC_DRV_DS1689 */ + spin_unlock_irqrestore(&rtc->lock, flags); + + /* + * XXX: Bug? this causes the function to get executed several times + * in succession. But it's the only way to actually get data written + * out to a file correctly. + */ + return count; +} + + +/** + * ds1685_rtc_sysfs_nvram_write - writes rtc nvram via sysfs. + * @file: pointer to file structure. + * @kobj: pointer to kobject structure. + * @bin_attr: pointer to bin_attribute structure. + * @buf: pointer to char array to hold the input. + * @pos: current file position pointer. + * @size: size of the data to write. + */ +static ssize_t +ds1685_rtc_sysfs_nvram_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t pos, size_t size) +{ + struct platform_device *pdev = + to_platform_device(container_of(kobj, struct device, kobj)); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + ssize_t count; + unsigned long flags = 0; + + spin_lock_irqsave(&rtc->lock, flags); + ds1685_rtc_switch_to_bank0(rtc); + + /* Write NVRAM in time and bank0 registers. */ + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; + count++, size--) + if (count < NVRAM_SZ_TIME) + ds1685_write(rtc, (NVRAM_TIME_BASE + pos++), + *buf++); + else + ds1685_write(rtc, (NVRAM_BANK0_BASE), *buf++); + +#ifndef CONFIG_RTC_DRV_DS1689 + if (size > 0) { + ds1685_rtc_switch_to_bank1(rtc); + +#ifndef CONFIG_RTC_DRV_DS1685 + /* Enable burst-mode on DS17x85/DS17x87 */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) | + RTC_CTRL_4A_BME)); + + /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start + * writing with burst-mode */ + ds1685_write(rtc, RTC_BANK1_RAM_ADDR_LSB, + (pos - NVRAM_TOTAL_SZ_BANK0)); +#endif + + /* Write NVRAM in bank1 registers. */ + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; + count++, size--) { +#ifdef CONFIG_RTC_DRV_DS1685 + /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR + * before each read. */ + ds1685_write(rtc, RTC_BANK1_RAM_ADDR, + (pos - NVRAM_TOTAL_SZ_BANK0)); +#endif + ds1685_write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++); + pos++; + } + +#ifndef CONFIG_RTC_DRV_DS1685 + /* Disable burst-mode on DS17x85/DS17x87 */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) & + ~(RTC_CTRL_4A_BME))); +#endif + ds1685_rtc_switch_to_bank0(rtc); + } +#endif /* !CONFIG_RTC_DRV_DS1689 */ + spin_unlock_irqrestore(&rtc->lock, flags); + + return count; +} + + +/** + * struct ds1685_rtc_sysfs_nvram_attr - sysfs attributes for rtc nvram. + * @attr: nvram attributes. + * @read: nvram read function. + * @write: nvram write function. + * @size: nvram total size (bank0 + extended). + */ +static struct bin_attribute ds1685_rtc_sysfs_nvram_attr = { + .attr = { + .name = "nvram", + .mode = S_IRUGO | S_IWUSR, + }, + .read = ds1685_rtc_sysfs_nvram_read, + .write = ds1685_rtc_sysfs_nvram_write, + .size = NVRAM_TOTAL_SZ +}; + + +/** + * ds1685_rtc_sysfs_sqwfreq_show - reads the square-wave freq via sysfs. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_sqwfreq_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrla, ctrl4b; + u32 freq = 0; + + /* Read the square-wave data from the RTC registers. */ + ds1685_rtc_switch_to_bank1(rtc); + ctrla = ds1685_read(rtc, RTC_CTRL_A); + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + ds1685_rtc_switch_to_bank0(rtc); + + /* If E32K is set, return 32768Hz. */ + if (ctrl4b & RTC_CTRL_4B_E32K) + return sprintf(buf, "%d\n", RTC_SQW_32768HZ); + + /* Else, return the user-selected frequency. */ + switch (ctrla & RTC_CTRL_A_RS_MASK) { + case RTC_SQW_0HZ: freq = 0; break; + case RTC_SQW_2HZ: freq = 2; break; + case RTC_SQW_4HZ: freq = 4; break; + case RTC_SQW_8HZ: freq = 8; break; + case RTC_SQW_16HZ: freq = 16; break; + case RTC_SQW_32HZ: freq = 32; break; + case RTC_SQW_64HZ: freq = 64; break; + case 0x02: + case RTC_SQW_128HZ: freq = 128; break; + case 0x01: + case RTC_SQW_256HZ: freq = 256; break; + case RTC_SQW_512HZ: freq = 512; break; + case RTC_SQW_1024HZ: freq = 1024; break; + case RTC_SQW_2048HZ: freq = 2048; break; + case RTC_SQW_4096HZ: freq = 4096; break; + case RTC_SQW_8192HZ: freq = 8192; break; + } + + return sprintf(buf, "%d\n", freq); +} + + +/** + * ds1685_rtc_sysfs_sqwfreq_store - sets the square-wave freq via sysfs. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + * @count: number of bytes written. + */ +static ssize_t +ds1685_rtc_sysfs_sqwfreq_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + long int freq = 0; + int ret; + + /* We only accept numbers. */ + if (strict_strtol(buf, 10, &freq) < 0) + return -EINVAL; + + /* Return the failure code if the frequency couldn't be set. */ + ret = ds1685_rtc_set_freq(dev, freq); + if (ret) + return ret; + + return count; +} +static DEVICE_ATTR(sqwfreq, S_IRUGO | S_IWUSR, ds1685_rtc_sysfs_sqwfreq_show, + ds1685_rtc_sysfs_sqwfreq_store); + + +/** + * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_battery_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrld; + + ctrld = ds1685_read(rtc, RTC_CTRL_D); + + return sprintf(buf, "%s\n", + (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A"); +} +static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL); + + +/** + * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_auxbatt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ctrl4a; + + ds1685_rtc_switch_to_bank1(rtc); + ctrl4a = ds1685_read(rtc, RTC_EXT_CTRL_4A); + ds1685_rtc_switch_to_bank0(rtc); + + return sprintf(buf, "%s\n", + (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A"); +} +static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL); + + +/** + * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_serial_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + u8 ssn[8]; + + ds1685_rtc_switch_to_bank1(rtc); + ds1685_rtc_get_ssn(rtc, ssn); + ds1685_rtc_switch_to_bank0(rtc); + + return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", + ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], ssn[6], + ssn[7]); + + return 0; +} +static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL); + +/** + * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features. + */ +static struct attribute* +ds1685_rtc_sysfs_misc_attrs[] = { + &dev_attr_sqwfreq.attr, + &dev_attr_battery.attr, + &dev_attr_auxbatt.attr, + &dev_attr_serial.attr, + NULL, +}; + + +/** + * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features. + */ +static const struct attribute_group +ds1685_rtc_sysfs_misc_grp = { + .name = "misc", + .attrs = ds1685_rtc_sysfs_misc_attrs, +}; + + +#ifdef CONFIG_RTC_DS1685_SYSFS_REGS +/** + * struct ds1685_rtc_regs. + * @name: char pointer for the bit name. + * @reg: control register the bit is in. + * @bit: the bit's offset in the register. + */ +struct ds1685_rtc_regs { + const char *name; + const u8 reg; + const u8 bit; +}; + + +/* + * Register bit lookup table. + */ +static const struct ds1685_rtc_regs +ds1685_regs_table[] = { + { "uip", RTC_CTRL_A, RTC_CTRL_A_UIP }, + { "dv2", RTC_CTRL_A, RTC_CTRL_A_DV2 }, + { "dv1", RTC_CTRL_A, RTC_CTRL_A_DV1 }, + { "dv0", RTC_CTRL_A, RTC_CTRL_A_DV0 }, + { "rs3", RTC_CTRL_A, RTC_CTRL_A_RS3 }, + { "rs2", RTC_CTRL_A, RTC_CTRL_A_RS2 }, + { "rs1", RTC_CTRL_A, RTC_CTRL_A_RS1 }, + { "rs0", RTC_CTRL_A, RTC_CTRL_A_RS0 }, + { "set", RTC_CTRL_B, RTC_CTRL_B_SET }, + { "pie", RTC_CTRL_B, RTC_CTRL_B_PIE }, + { "aie", RTC_CTRL_B, RTC_CTRL_B_AIE }, + { "uie", RTC_CTRL_B, RTC_CTRL_B_UIE }, + { "sqwe", RTC_CTRL_B, RTC_CTRL_B_SQWE }, + { "dm", RTC_CTRL_B, RTC_CTRL_B_DM }, + { "2412", RTC_CTRL_B, RTC_CTRL_B_2412 }, + { "dse", RTC_CTRL_B, RTC_CTRL_B_DSE }, + { "irqf", RTC_CTRL_C, RTC_CTRL_C_IRQF }, + { "pf", RTC_CTRL_C, RTC_CTRL_C_PF }, + { "af", RTC_CTRL_C, RTC_CTRL_C_AF }, + { "uf", RTC_CTRL_C, RTC_CTRL_C_UF }, + { "vrt", RTC_CTRL_D, RTC_CTRL_D_VRT }, + { "vrt2", RTC_EXT_CTRL_4A, RTC_CTRL_4A_VRT2 }, + { "incr", RTC_EXT_CTRL_4A, RTC_CTRL_4A_INCR }, + { "pab", RTC_EXT_CTRL_4A, RTC_CTRL_4A_PAB }, + { "rf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_RF }, + { "wf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_WF }, + { "kf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_KF }, +#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) + { "bme", RTC_EXT_CTRL_4A, RTC_CTRL_4A_BME }, +#endif + { "abe", RTC_EXT_CTRL_4B, RTC_CTRL_4B_ABE }, + { "e32k", RTC_EXT_CTRL_4B, RTC_CTRL_4B_E32K }, + { "cs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_CS }, + { "rce", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RCE }, + { "prs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_PRS }, + { "rie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RIE }, + { "wie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_WIE }, + { "kse", RTC_EXT_CTRL_4B, RTC_CTRL_4B_KSE }, + { NULL, 0, 0 }, +}; + + +/** + * ds1685_rtc_sysfs_regs_lookup - register bit lookup function. + * @name: register bit to look up in ds1685_regs_table. + */ +static const struct ds1685_rtc_regs* +ds1685_rtc_sysfs_regs_lookup(const char *name) +{ + const struct ds1685_rtc_regs *p = ds1685_regs_table; + + for (; p->name != NULL; ++p) + if (strcmp(p->name, name) == 0) + return p; + + return NULL; +} + + +/** + * ds1685_rtc_sysfs_ctrl_regs_show - reads a register bit via sysfs. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + */ +static ssize_t +ds1685_rtc_sysfs_ctrl_regs_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + u8 reg = 0, bit = 0, tmp; + const struct ds1685_rtc_regs *reg_info = + ds1685_rtc_sysfs_regs_lookup(attr->attr.name); + + /* Make sure we actually matched something. */ + if (!reg_info) + return -EINVAL; + + reg = reg_info->reg; + bit = reg_info->bit; + + /* No spinlock during a read -- mutex is already held. */ + ds1685_rtc_switch_to_bank1(rtc); + tmp = ds1685_read(rtc, reg) & bit; + ds1685_rtc_switch_to_bank0(rtc); + + return sprintf(buf, "%d\n", (tmp ? 1 : 0)); +} + + +/** + * ds1685_rtc_sysfs_ctrl_regs_store - writes a register bit via sysfs. + * @dev: pointer to device structure. + * @attr: pointer to device_attribute structure. + * @buf: pointer to char array to hold the output. + * @count: number of bytes written. + */ +static ssize_t +ds1685_rtc_sysfs_ctrl_regs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + u8 reg = 0, bit = 0, tmp; + unsigned long flags = 0; + long int val = 0; + const struct ds1685_rtc_regs *reg_info = + ds1685_rtc_sysfs_regs_lookup(attr->attr.name); + + /* We only accept numbers. */ + if (strict_strtol(buf, 10, &val) < 0) + return -EINVAL; + + /* bits are binary, 0 or 1 only. */ + if ((val != 0) && (val != 1)) + return -ERANGE; + + /* Make sure we actually matched something. */ + if (!reg_info) + return -EINVAL; + + reg = reg_info->reg; + bit = reg_info->bit; + + /* Safe to spinlock during a write. */ + ds1685_rtc_begin_ctrl_access(rtc, flags); + tmp = ds1685_read(rtc, reg); + ds1685_write(rtc, reg, (val ? (tmp | bit) : (tmp & ~(bit)))); + ds1685_rtc_end_ctrl_access(rtc, flags); + + return count; +} + + +/** + * DS1685_RTC_SYSFS_REG_RO - device_attribute for a read-only register bit. + * @bit: bit to read. + */ +#define DS1685_RTC_SYSFS_REG_RO(bit) \ + static DEVICE_ATTR(bit, S_IRUGO, \ + ds1685_rtc_sysfs_ctrl_regs_show, NULL) + +/** + * DS1685_RTC_SYSFS_REG_RW - device_attribute for a read-write register bit. + * @bit: bit to read or write. + */ +#define DS1685_RTC_SYSFS_REG_RW(bit) \ + static DEVICE_ATTR(bit, S_IRUGO | S_IWUSR, \ + ds1685_rtc_sysfs_ctrl_regs_show, \ + ds1685_rtc_sysfs_ctrl_regs_store) + + +/* + * Control Register A bits. + */ +DS1685_RTC_SYSFS_REG_RO(uip); +DS1685_RTC_SYSFS_REG_RW(dv2); +DS1685_RTC_SYSFS_REG_RW(dv1); +DS1685_RTC_SYSFS_REG_RO(dv0); +DS1685_RTC_SYSFS_REG_RW(rs3); +DS1685_RTC_SYSFS_REG_RW(rs2); +DS1685_RTC_SYSFS_REG_RW(rs1); +DS1685_RTC_SYSFS_REG_RW(rs0); + +static struct attribute* +ds1685_rtc_sysfs_ctrla_attrs[] = { + &dev_attr_uip.attr, + &dev_attr_dv2.attr, + &dev_attr_dv1.attr, + &dev_attr_dv0.attr, + &dev_attr_rs3.attr, + &dev_attr_rs2.attr, + &dev_attr_rs1.attr, + &dev_attr_rs0.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrla_grp = { + .name = "ctrla", + .attrs = ds1685_rtc_sysfs_ctrla_attrs, +}; + + +/* + * Control Register B bits. + */ +DS1685_RTC_SYSFS_REG_RO(set); +DS1685_RTC_SYSFS_REG_RW(pie); +DS1685_RTC_SYSFS_REG_RW(aie); +DS1685_RTC_SYSFS_REG_RW(uie); +DS1685_RTC_SYSFS_REG_RW(sqwe); +DS1685_RTC_SYSFS_REG_RO(dm); +DS1685_RTC_SYSFS_REG_RO(2412); +DS1685_RTC_SYSFS_REG_RO(dse); + +static struct attribute* +ds1685_rtc_sysfs_ctrlb_attrs[] = { + &dev_attr_set.attr, + &dev_attr_pie.attr, + &dev_attr_aie.attr, + &dev_attr_uie.attr, + &dev_attr_sqwe.attr, + &dev_attr_dm.attr, + &dev_attr_2412.attr, + &dev_attr_dse.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrlb_grp = { + .name = "ctrlb", + .attrs = ds1685_rtc_sysfs_ctrlb_attrs, +}; + + +/* + * Control Register C bits. + * + * Reading Control C clears these bits! Reading them individually can + * possibly cause an interrupt to be missed. Use the /proc interface + * to see all the bits in this register simultaneously. + */ +DS1685_RTC_SYSFS_REG_RO(irqf); +DS1685_RTC_SYSFS_REG_RO(pf); +DS1685_RTC_SYSFS_REG_RO(af); +DS1685_RTC_SYSFS_REG_RO(uf); + +static struct attribute* +ds1685_rtc_sysfs_ctrlc_attrs[] = { + &dev_attr_irqf.attr, + &dev_attr_pf.attr, + &dev_attr_af.attr, + &dev_attr_uf.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrlc_grp = { + .name = "ctrlc", + .attrs = ds1685_rtc_sysfs_ctrlc_attrs, +}; + + +/* + * Control Register D bits. + */ +DS1685_RTC_SYSFS_REG_RO(vrt); + +static struct attribute* +ds1685_rtc_sysfs_ctrld_attrs[] = { + &dev_attr_vrt.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrld_grp = { + .name = "ctrld", + .attrs = ds1685_rtc_sysfs_ctrld_attrs, +}; + + +/* + * Control Register 4A bits. + */ +DS1685_RTC_SYSFS_REG_RO(vrt2); +DS1685_RTC_SYSFS_REG_RO(incr); +DS1685_RTC_SYSFS_REG_RW(pab); +DS1685_RTC_SYSFS_REG_RW(rf); +DS1685_RTC_SYSFS_REG_RW(wf); +DS1685_RTC_SYSFS_REG_RW(kf); +#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) +DS1685_RTC_SYSFS_REG_RO(bme); +#endif + +static struct attribute* +ds1685_rtc_sysfs_ctrl4a_attrs[] = { + &dev_attr_vrt2.attr, + &dev_attr_incr.attr, + &dev_attr_pab.attr, + &dev_attr_rf.attr, + &dev_attr_wf.attr, + &dev_attr_kf.attr, +#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) + &dev_attr_bme.attr, +#endif + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrl4a_grp = { + .name = "ctrl4a", + .attrs = ds1685_rtc_sysfs_ctrl4a_attrs, +}; + + +/* + * Control Register 4B bits. + */ +DS1685_RTC_SYSFS_REG_RW(abe); +DS1685_RTC_SYSFS_REG_RW(e32k); +DS1685_RTC_SYSFS_REG_RO(cs); +DS1685_RTC_SYSFS_REG_RW(rce); +DS1685_RTC_SYSFS_REG_RW(prs); +DS1685_RTC_SYSFS_REG_RW(rie); +DS1685_RTC_SYSFS_REG_RW(wie); +DS1685_RTC_SYSFS_REG_RW(kse); + +static struct attribute* +ds1685_rtc_sysfs_ctrl4b_attrs[] = { + &dev_attr_abe.attr, + &dev_attr_e32k.attr, + &dev_attr_cs.attr, + &dev_attr_rce.attr, + &dev_attr_prs.attr, + &dev_attr_rie.attr, + &dev_attr_wie.attr, + &dev_attr_kse.attr, + NULL, +}; + +static const struct attribute_group +ds1685_rtc_sysfs_ctrl4b_grp = { + .name = "ctrl4b", + .attrs = ds1685_rtc_sysfs_ctrl4b_attrs, +}; +#endif /* CONFIG_RTC_DS1685_SYSFS_REGS */ + + +/** + * ds1685_rtc_sysfs_register - register sysfs files. + * @dev: pointer to device structure. + */ +static int __devinit +ds1685_rtc_sysfs_register(struct device *dev) +{ + int ret = 0; + + sysfs_bin_attr_init(&ds1685_rtc_sysfs_nvram_attr); + ret = sysfs_create_bin_file(&dev->kobj, + &ds1685_rtc_sysfs_nvram_attr); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp); + if (ret) + return ret; + +#ifdef CONFIG_RTC_DS1685_SYSFS_REGS + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp); + if (ret) + return ret; + + ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp); + if (ret) + return ret; +#endif + return 0; +} + + +/** + * ds1685_rtc_sysfs_unregister - unregister sysfs files. + * @dev: pointer to device structure. + */ +static int __devexit +ds1685_rtc_sysfs_unregister(struct device *dev) +{ + sysfs_remove_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp); + +#ifdef CONFIG_RTC_DS1685_SYSFS_REGS + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp); + sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp); +#endif + + return 0; +} +#endif /* CONFIG_SYSFS */ + + + +/* ----------------------------------------------------------------------- */ +/* Driver Probe/Removal */ + +/** + * ds1685_rtc_probe - initializes rtc driver. + * @pdev: pointer to platform_device structure. + */ +static int __devinit +ds1685_rtc_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc_dev; + struct resource *res; + struct ds1685_priv *rtc; + struct ds1685_rtc_platform_data *pdata; + u8 ctrla, ctrlb, hours; + unsigned char am_pm; + int ret = 0; + + /* Get the platform resources. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENXIO; + + /* Get the platform data. */ + pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data; + if (!pdata) + return -ENODEV; + + /* Allocate memory for the rtc device. */ + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + rtc->size = resource_size(res); + + /* Request a memory region. */ + /* TODO: Only mmio for now. Need to add standard io. */ + if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size, + pdev->name)) + return -EBUSY; + + /* Set the base address for the rtc, and ioremap its registers. */ + rtc->baseaddr = res->start; + rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size); + if (!rtc->regs) + return -ENOMEM; + + /* Get the register step size. */ + if (pdata->regstep > 0) + rtc->regstep = pdata->regstep; + else + rtc->regstep = 1; + + /* Assign the pre-shutdown function, if defined. */ + if (pdata->plat_prepare_poweroff != NULL) + rtc->prepare_poweroff = pdata->plat_prepare_poweroff; + + /* Assign the wake_alarm function, if defined. */ + if (pdata->plat_wake_alarm != NULL) + rtc->wake_alarm = pdata->plat_wake_alarm; + + /* Assign the post_ram_clear function, if defined. */ + if (pdata->plat_post_ram_clear != NULL) + rtc->post_ram_clear = pdata->plat_post_ram_clear; + + /* Init the spinlock, workqueue, & set the driver data. */ + spin_lock_init(&rtc->lock); + INIT_WORK(&rtc->work, ds1685_rtc_work_queue); + platform_set_drvdata(pdev, rtc); + + /* Turn the oscillator on if is not already on (DV1 = 1). */ + ctrla = ds1685_read(rtc, RTC_CTRL_A); + if (!(ctrla & RTC_CTRL_A_DV1)) + ctrla |= RTC_CTRL_A_DV1; + + /* Enable the countdown chain (DV2 = 0) */ + ctrla &= ~(RTC_CTRL_A_DV2); + + /* Clear RS3-RS0 in Control A. */ + ctrla &= ~(RTC_CTRL_A_RS_MASK); + + /* + * All done with Control A. Switch to Bank 1 for the remainder of + * the RTC setup so we have access to the extended functions. + */ + ctrla |= RTC_CTRL_A_DV0; + ds1685_write(rtc, RTC_CTRL_A, ctrla); + + /* Default to 32768kHz output. */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K)); + + /* + * Set the SET bit in Control B so we can do some housekeeping. + * We do not check UIP in Control A because this is a one-time + * thing during driver setup and we'll just hope that we don't + * hit in the middle of an update. + */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); + + /* Force BCD mode (DM = 0). */ + ctrlb = ds1685_read(rtc, RTC_CTRL_B); + if (ctrlb & RTC_CTRL_B_DM) + ctrlb &= ~(RTC_CTRL_B_DM); + + /* + * Disable Daylight Savings Time (DSE = 0). + * The RTC has hardcoded timezone information that is rendered + * obselete. We'll let the OS deal with DST settings instead. + */ + if (ctrlb & RTC_CTRL_B_DSE) + ctrlb &= ~(RTC_CTRL_B_DSE); + + /* Force 24-hour mode (2412 = 1). */ + if (!(ctrlb & RTC_CTRL_B_2412)) { + /* Reinitialize the time hours. */ + hours = ds1685_read(rtc, RTC_HOURS); + am_pm = hours & RTC_HOURS_AMPM_MASK; + hours = bcd2bin(hours & RTC_HOURS_12_MASK); + hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); + + /* Enable 24-hour mode. */ + ctrlb |= RTC_CTRL_B_2412; + + /* Write back to Control B, including DM & DSE bits. */ + ds1685_write(rtc, RTC_CTRL_B, ctrlb); + + /* Write the time hours back. */ + ds1685_write(rtc, RTC_HOURS, + bin2bcd(hours) & RTC_HOURS_24_MASK); + + /* Reinitialize the alarm hours. */ + hours = ds1685_read(rtc, RTC_HOURS_ALARM); + am_pm = hours & RTC_HOURS_AMPM_MASK; + hours = bcd2bin(hours & RTC_HOURS_12_MASK); + hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); + + /* Write the alarm hours back. */ + ds1685_write(rtc, RTC_HOURS_ALARM, + bin2bcd(hours) & RTC_HOURS_24_MASK); + } else { + /* 24-hour mode is already set, so write Control B back. */ + ds1685_write(rtc, RTC_CTRL_B, ctrlb); + } + + /* Unset the SET bit in Control B so the RTC can update. */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); + + /* Check the main battery. */ + if (!(ds1685_read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT)) + dev_warn(&pdev->dev, + "Main battery is exhausted! RTC may be invalid!\n"); + + /* Check the auxillary battery. It is optional. */ + if (!(ds1685_read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2)) + dev_warn(&pdev->dev, + "Aux battery is exhausted or not available.\n"); + + /* Fetch the IRQ and setup the interrupt handler. */ + rtc->irq = platform_get_irq(pdev, 0); + if (rtc->irq > 0) { + /* Read Ctrl B and clear PIE/AIE/UIE. */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & + ~(RTC_CTRL_B_PAU_MASK))); + + /* Reading Ctrl C auto-clears PF/AF/UF. */ + ds1685_read(rtc, RTC_CTRL_C); + + /* Read Ctrl 4B and clear RIE/WIE/KSE. */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) & + ~(RTC_CTRL_4B_RWK_MASK))); + + /* Manually clear RF/WF/KF in Ctrl 4A. */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) & + ~(RTC_CTRL_4A_RWK_MASK))); + + /* Request an IRQ. */ + ret = devm_request_irq(&pdev->dev, rtc->irq, + ds1685_rtc_irq_handler, + IRQF_SHARED, pdev->name, pdev); + + /* Check to see if something came back. */ + if (unlikely(ret)) { + dev_warn(&pdev->dev, + "RTC interrupt not available\n"); + rtc->irq = 0; + } else { + /* + * Re-enable KSE to handle power button events. We + * do not enable WIE or RIE by default. + */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) | + RTC_CTRL_4B_KSE)); + } + } + + /* Setup complete. */ + ds1685_rtc_switch_to_bank0(rtc); + + /* Register the device as an RTC. */ + rtc_dev = rtc_device_register(pdev->name, &pdev->dev, + &ds1685_rtc_ops, THIS_MODULE); + + /* Success? */ + if (IS_ERR(rtc_dev)) + return PTR_ERR(rtc_dev); + + /* Maximum periodic rate is 8192Hz (0.122070ms). */ + rtc_dev->max_user_freq = RTC_MAX_USER_FREQ; + + rtc->dev = rtc_dev; + +#ifdef CONFIG_SYSFS + ret = ds1685_rtc_sysfs_register(&pdev->dev); + if (ret) + rtc_device_unregister(rtc->dev); +#endif + + /* Done! */ + return ret; +} + + +/** + * ds1685_rtc_remove - removes rtc driver. + * @pdev: pointer to platform_device structure. + */ +static int __devexit +ds1685_rtc_remove(struct platform_device *pdev) +{ + struct ds1685_priv *rtc = platform_get_drvdata(pdev); + +#ifdef CONFIG_SYSFS + ds1685_rtc_sysfs_unregister(&pdev->dev); +#endif + + rtc_device_unregister(rtc->dev); + if (rtc->irq > 0) { + /* Read Ctrl B and clear PIE/AIE/UIE. */ + ds1685_write(rtc, RTC_CTRL_B, + (ds1685_read(rtc, RTC_CTRL_B) & + ~(RTC_CTRL_B_PAU_MASK))); + + /* Reading Ctrl C auto-clears PF/AF/UF. */ + ds1685_read(rtc, RTC_CTRL_C); + + /* Read Ctrl 4B and clear RIE/WIE/KSE. */ + ds1685_write(rtc, RTC_EXT_CTRL_4B, + (ds1685_read(rtc, RTC_EXT_CTRL_4B) & + ~(RTC_CTRL_4B_RWK_MASK))); + + /* Manually clear RF/WF/KF in Ctrl 4A. */ + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ds1685_read(rtc, RTC_EXT_CTRL_4A) & + ~(RTC_CTRL_4A_RWK_MASK))); + } + flush_scheduled_work(); + + return 0; +} + + +/** + * ds1685_rtc_driver - rtc driver properties. + */ +static struct platform_driver ds1685_rtc_driver = { + .driver = { + .name = "rtc-ds1685", + .owner = THIS_MODULE, + }, + .probe = ds1685_rtc_probe, + .remove = __devexit_p(ds1685_rtc_remove), +}; + + +/** + * ds1685_rtc_init - rtc module init. + */ +static int __init +ds1685_rtc_init(void) +{ + return platform_driver_register(&ds1685_rtc_driver); +} + + +/** + * ds1685_rtc_exit - rtc module exit. + */ +static void __exit +ds1685_rtc_exit(void) +{ + platform_driver_unregister(&ds1685_rtc_driver); +} + +module_init(ds1685_rtc_init); +module_exit(ds1685_rtc_exit); +/* ----------------------------------------------------------------------- */ + + +/* ----------------------------------------------------------------------- */ +/* Poweroff function */ + +/** + * ds1685_rtc_poweroff - uses the RTC chip to power the system off. + * @pdev: pointer to platform_device structure. + */ +extern void ATTRIB_NORET +ds1685_rtc_poweroff(struct platform_device *pdev) +{ + u8 ctrla, ctrl4a, ctrl4b; + struct ds1685_priv *rtc; + + /* Check for valid RTC data, else, spin forever. */ + if (unlikely(!pdev)) + while (1); + else { + /* Get the rtc data. */ + rtc = platform_get_drvdata(pdev); + + /* + * Disable our IRQ. We're powering down, so we're not + * going to worry about cleaning up. Most of that should + * be taken care of by the shutdown scripts and we're the + * final call. + */ + disable_irq_nosync(rtc->irq); + + /* Ocsillator must be on and the countdown chain enabled. */ + ctrla = ds1685_read(rtc, RTC_CTRL_A); + ctrla |= RTC_CTRL_A_DV1; + ctrla &= ~(RTC_CTRL_A_DV2); + ds1685_write(rtc, RTC_CTRL_A, ctrla); + + /* + * Read Control 4A and check the status of the auxillary + * battery. This must be present and working (VRT2 = 1) + * for wakeup and kickstart functionality to be useful. + */ + ds1685_rtc_switch_to_bank1(rtc); + ctrl4a = ds1685_read(rtc, RTC_EXT_CTRL_4A); + if (ctrl4a & RTC_CTRL_4A_VRT2) { + /* Clear all the interrupt flags on Control 4A. */ + ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK); + ds1685_write(rtc, RTC_EXT_CTRL_4A, ctrl4a); + + /* + * The auxillary battery is present and working. + * Enable extended functions (ABE=1), enable + * wake-up (WIE=1), and enable kickstart (KSE=1) + * in Control 4B. + */ + ctrl4b = ds1685_read(rtc, RTC_EXT_CTRL_4B); + ctrl4b |= RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE | + RTC_CTRL_4B_KSE; + ds1685_write(rtc, RTC_EXT_CTRL_4B, ctrl4b); + } + + /* Set PAB to 1 in Control 4A to power the system down. */ + printk(KERN_EMERG "Powerdown.\n"); + msleep(10); + ds1685_write(rtc, RTC_EXT_CTRL_4A, + (ctrl4a | RTC_CTRL_4A_PAB)); + + /* Spin ... we do not switch back to bank0. */ + while (1); + } +} +EXPORT_SYMBOL(ds1685_rtc_poweroff); +/* ----------------------------------------------------------------------- */ + + +MODULE_AUTHOR("Joshua Kinard "); +MODULE_AUTHOR("Matthias Fuchs "); +MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:rtc-ds1685"); diff -Naurp a/include/linux/rtc/ds1685.h b/include/linux/rtc/ds1685.h --- a/include/linux/rtc/ds1685.h +++ b/include/linux/rtc/ds1685.h @@ -0,0 +1,334 @@ +/* + * Definitions for the registers, addresses, and platform data of the + * DS1685/DS1687-series RTC chips. + * + * This Driver also works for the DS17X85/DS17X87 RTC chips. Functionally + * similar to the DS1685/DS1687, they support a few extra features which + * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC + * write counter. + * + * Copyright (C) 2009 Matthias Fuchs + * Copyright (C) 2011 Joshua Kinard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_RTC_DS1685_H_ +#define _LINUX_RTC_DS1685_H_ + +#include +#include +#include + +/** + * struct ds1685_priv - DS1685 private data structure. + * @dev: pointer to the rtc_device structure. + * @regs: iomapped base address pointer of the RTC registers. + * @regstep: padding/step size between registers (optional). + * @baseaddr: base address of the RTC device. + * @size: resource size. + * @lock: private lock variable for spin locking/unlocking. + * @work: private workqueue. + * @irq: IRQ number assigned to the RTC device. + * @prepare_poweroff: pointer to platform pre-poweroff function. + * @wake_alarm: pointer to platform wake alarm function. + * @post_ram_clear: pointer to platform post ram-clear function. + */ +struct ds1685_priv { + struct rtc_device *dev; + void __iomem *regs; + u32 regstep; + resource_size_t baseaddr; + size_t size; + spinlock_t lock; + struct work_struct work; + int irq; + void (*prepare_poweroff)(void); + void (*wake_alarm)(void); + void (*post_ram_clear)(void); +}; + + +/** + * struct ds1685_rtc_platform_data - platform data structure. + * @plat_prepare_poweroff: platform-specific pre-poweroff function. + * @plat_wake_alarm: platform-specific wake alarm function. + * @plat_post_ram_clear: platform-specific post ram-clear function. + * + * If your platform needs to use a custom padding/step size between + * registers, or uses one or more of the extended interrupts and needs special + * handling, then include this header file in your platform definition and + * set regstep and the plat_* pointers as appropriate. + */ +struct ds1685_rtc_platform_data { + void (*plat_prepare_poweroff)(void); + void (*plat_wake_alarm)(void); + void (*plat_post_ram_clear)(void); + const u32 regstep; +}; + + +/* + * Time Registers. + */ +#define RTC_SECONDS 0x00 /* Seconds 00-59 */ +#define RTC_SECONDS_ALARM 0x01 /* Alarm Seconds 00-59 */ +#define RTC_MINUTES 0x02 /* Minutes 00-59 */ +#define RTC_MINUTES_ALARM 0x03 /* Alarm Minutes 00-59 */ +#define RTC_HOURS 0x04 /* Hours 01-12 AM/PM || 00-23 */ +#define RTC_HOURS_ALARM 0x05 /* Alarm Hours 01-12 AM/PM || 00-23 */ +#define RTC_WDAY 0x06 /* Day of Week 01-07 */ +#define RTC_MDAY 0x07 /* Day of Month 01-31 */ +#define RTC_MONTH 0x08 /* Month 01-12 */ +#define RTC_YEAR 0x09 /* Year 00-99 */ +#define RTC_CENTURY 0x48 /* Century 00-99 */ +#define RTC_MDAY_ALARM 0x49 /* Alarm Day of Month 01-31 */ + + +/* + * Bit masks for the Time registers in BCD Mode (DM = 0). + */ +#define RTC_SECONDS_MASK 0x7f /* - x x x x x x x */ +#define RTC_MINUTES_MASK 0x7f /* - x x x x x x x */ +#define RTC_HOURS_12_MASK 0x1f /* - - - x x x x x */ +#define RTC_HOURS_24_MASK 0x3f /* - - x x x x x x */ +#define RTC_WDAY_MASK 0x07 /* - - - - - x x x */ +#define RTC_MDAY_MASK 0x3f /* - - x x x x x x */ +#define RTC_MONTH_MASK 0x1f /* - - - x x x x x */ +#define RTC_YEAR_MASK 0xff /* x x x x x x x x */ +#define RTC_CENTURY_MASK 0xff /* x x x x x x x x */ +#define RTC_HOURS_AMPM_MASK BIT(7) /* Mask for the AM/PM bit */ + + +/* + * Control Registers. + */ +#define RTC_CTRL_A 0x0a /* Control Register A */ +#define RTC_CTRL_B 0x0b /* Control Register B */ +#define RTC_CTRL_C 0x0c /* Control Register C */ +#define RTC_CTRL_D 0x0d /* Control Register D */ +#define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */ +#define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */ + + +/* + * Bit names in Control Register A. + */ +#define RTC_CTRL_A_UIP BIT(7) /* Update In Progress */ +#define RTC_CTRL_A_DV2 BIT(6) /* Countdown Chain */ +#define RTC_CTRL_A_DV1 BIT(5) /* Oscillator Enable */ +#define RTC_CTRL_A_DV0 BIT(4) /* Bank Select */ +#define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */ +#define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */ +#define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */ +#define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */ +#define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */ + +/* + * Bit names in Control Register B. + */ +#define RTC_CTRL_B_SET BIT(7) /* SET Bit */ +#define RTC_CTRL_B_PIE BIT(6) /* Periodic-Interrupt Enable */ +#define RTC_CTRL_B_AIE BIT(5) /* Alarm-Interrupt Enable */ +#define RTC_CTRL_B_UIE BIT(4) /* Update-Ended Interrupt-Enable */ +#define RTC_CTRL_B_SQWE BIT(3) /* Square-Wave Enable */ +#define RTC_CTRL_B_DM BIT(2) /* Data Mode */ +#define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */ +#define RTC_CTRL_B_DSE BIT(0) /* Daylight Savings Enable */ +#define RTC_CTRL_B_PAU_MASK 0x70 /* PIE + AIE + UIE */ + + +/* + * Bit names in Control Register C. + * + * BIT(0), BIT(1), BIT(2), & BIT(3) are unused, always return 0, and cannot + * be written to. + */ +#define RTC_CTRL_C_IRQF BIT(7) /* Interrupt-Request Flag */ +#define RTC_CTRL_C_PF BIT(6) /* Periodic-Interrupt Flag */ +#define RTC_CTRL_C_AF BIT(5) /* Alarm-Interrupt Flag */ +#define RTC_CTRL_C_UF BIT(4) /* Update-Ended Interrupt Flag */ +#define RTC_CTRL_C_PAU_MASK 0x70 /* PF + AF + UF */ + + +/* + * Bit names in Control Register D. + * + * BIT(0) through BIT(6) are unused, always return 0, and cannot + * be written to. + */ +#define RTC_CTRL_D_VRT BIT(7) /* Valid RAM and Time */ + + +/* + * Bit names in Extended Control Register 4A. + * + * On the DS1685/DS1687/DS1689/DS1693, BIT(4) and BIT(5) are reserved for + * future use. They can be read from and written to, but have no effect + * on the RTC's operation. + * + * On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows + * access to the extended NV-SRAM by automatically incrementing the address + * register when they are read from or written to. + */ +#define RTC_CTRL_4A_VRT2 BIT(7) /* Auxillary Battery Status */ +#define RTC_CTRL_4A_INCR BIT(6) /* Increment-in-Progress Status */ +#define RTC_CTRL_4A_PAB BIT(3) /* Power-Active Bar Control */ +#define RTC_CTRL_4A_RF BIT(2) /* RAM-Clear Flag */ +#define RTC_CTRL_4A_WF BIT(1) /* Wake-Up Alarm Flag */ +#define RTC_CTRL_4A_KF BIT(0) /* Kickstart Flag */ +#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) +#define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */ +#endif +#define RTC_CTRL_4A_RWK_MASK 0x07 /* RF + WF + KF */ + + +/* + * Bit names in Extended Control Register 4B. + */ +#define RTC_CTRL_4B_ABE BIT(7) /* Auxillary Battery Enable */ +#define RTC_CTRL_4B_E32K BIT(6) /* Enable 32.768Hz on SQW Pin */ +#define RTC_CTRL_4B_CS BIT(5) /* Crystal Select */ +#define RTC_CTRL_4B_RCE BIT(4) /* RAM Clear-Enable */ +#define RTC_CTRL_4B_PRS BIT(3) /* PAB Reset-Select */ +#define RTC_CTRL_4B_RIE BIT(2) /* RAM Clear-Interrupt Enable */ +#define RTC_CTRL_4B_WIE BIT(1) /* Wake-Up Alarm-Interrupt Enable */ +#define RTC_CTRL_4B_KSE BIT(0) /* Kickstart Interrupt-Enable */ +#define RTC_CTRL_4B_RWK_MASK 0x07 /* RIE + WIE + KSE */ + + +/* + * Misc register names in Bank 1. + * + * The DV0 bit in Control Register A must be set to 1 for these registers + * to become available, including Extended Control Registers 4A & 4B. + */ +#define RTC_BANK1_SSN_MODEL 0x40 /* Model Number */ +#define RTC_BANK1_SSN_BYTE_1 0x41 /* 1st Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_2 0x42 /* 2nd Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_3 0x43 /* 3rd Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_4 0x44 /* 4th Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_5 0x45 /* 5th Byte of Serial Number */ +#define RTC_BANK1_SSN_BYTE_6 0x46 /* 6th Byte of Serial Number */ +#define RTC_BANK1_SSN_CRC 0x47 /* Serial CRC Byte */ +#define RTC_BANK1_RAM_DATA_PORT 0x53 /* Extended RAM Data Port */ + + +/* + * Model-specific registers in Bank 1. + * + * The addresses below differ depending on the model of the RTC chip + * selected in the kernel configuration. Not all of these features are + * supported in the main driver at present. + * + * DS1685/DS1687 - Extended NV-SRAM address (LSB only). + * DS1689/DS1693 - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N. + * DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter. + */ +#if defined(CONFIG_RTC_DRV_DS1685) +#define RTC_BANK1_RAM_ADDR 0x50 /* NV-SRAM Addr */ +#elif defined(CONFIG_RTC_DRV_DS1689) +#define RTC_BANK1_VCC_CTR_LSB 0x54 /* Vcc Counter Addr (LSB) */ +#define RTC_BANK1_VCC_CTR_MSB 0x57 /* Vcc Counter Addr (MSB) */ +#define RTC_BANK1_VBAT_CTR_LSB 0x58 /* Vbat Counter Addr (LSB) */ +#define RTC_BANK1_VBAT_CTR_MSB 0x5b /* Vbat Counter Addr (MSB) */ +#define RTC_BANK1_PWR_CTR_LSB 0x5c /* Pwr Cycle Counter Addr (LSB) */ +#define RTC_BANK1_PWR_CTR_MSB 0x5d /* Pwr Cycle Counter Addr (MSB) */ +#define RTC_BANK1_UNIQ_SN 0x60 /* Customer-specific S/N */ +#else /* DS17x85/DS17x87 */ +#define RTC_BANK1_RAM_ADDR_LSB 0x50 /* NV-SRAM Addr (LSB) */ +#define RTC_BANK1_RAM_ADDR_MSB 0x51 /* NV-SRAM Addr (MSB) */ +#define RTC_BANK1_WRITE_CTR 0x5e /* RTC Write Counter */ +#endif + + +/* + * Model numbers. + * + * The DS1688/DS1691 and DS1689/DS1693 chips share the same model number + * and the manual doesn't indicate any major differences. As such, they + * are regarded as the same chip in this driver. + */ +#define RTC_MODEL_DS1685 0x71 /* DS1685/DS1687 */ +#define RTC_MODEL_DS17285 0x72 /* DS17285/DS17287 */ +#define RTC_MODEL_DS1689 0x73 /* DS1688/DS1691/DS1689/DS1693 */ +#define RTC_MODEL_DS17485 0x74 /* DS17485/DS17487 */ +#define RTC_MODEL_DS17885 0x78 /* DS17885/DS17887 */ + + +/* + * Periodic Interrupt Rates / Square-Wave Output Frequency + * + * Periodic rates are selected by setting the RS3-RS0 bits in Control + * Register A and enabled via either the E32K bit in Extended Control + * Register 4B or the SQWE bit in Control Register B. + * + * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz + * on the SQW pin of the RTC chip. While there are 16 possible selections, + * the 1-of-16 decoder is only able to divide the base 32768Hz signal into + * 13 smaller frequencies. The values 0x01 and 0x02 are not used and are + * synonymous with 0x08 and 0x09, respectively. + * + * When E32K is set to a logic 1, periodic interrupts are disabled and + * reading /dev/rtc will return -EINVAL. This also applies if the periodic + * interrupt frequency is set to 0Hz. + */ + /* E32K RS3 RS2 RS1 RS0 */ +#define RTC_SQW_8192HZ 0x03 /* 0 0 0 1 1 */ +#define RTC_SQW_4096HZ 0x04 /* 0 0 1 0 0 */ +#define RTC_SQW_2048HZ 0x05 /* 0 0 1 0 1 */ +#define RTC_SQW_1024HZ 0x06 /* 0 0 1 1 0 */ +#define RTC_SQW_512HZ 0x07 /* 0 0 1 1 1 */ +#define RTC_SQW_256HZ 0x08 /* 0 1 0 0 0 */ +#define RTC_SQW_128HZ 0x09 /* 0 1 0 0 1 */ +#define RTC_SQW_64HZ 0x0a /* 0 1 0 1 0 */ +#define RTC_SQW_32HZ 0x0b /* 0 1 0 1 1 */ +#define RTC_SQW_16HZ 0x0c /* 0 1 1 0 0 */ +#define RTC_SQW_8HZ 0x0d /* 0 1 1 0 1 */ +#define RTC_SQW_4HZ 0x0e /* 0 1 1 1 0 */ +#define RTC_SQW_2HZ 0x0f /* 0 1 1 1 1 */ +#define RTC_SQW_0HZ 0x00 /* 0 0 0 0 0 */ +#define RTC_SQW_32768HZ 32768 /* 1 - - - - */ +#define RTC_MAX_USER_FREQ 8192 + + +/* + * NVRAM data & addresses: + * - 50 bytes of NVRAM are available just past the clock registers. + * - 64 additional bytes are available in Bank0. + * + * Extended, battery-backed NV-SRAM: + * - DS1685/DS1687 - 128 bytes. + * - DS1689/DS1693 - 0 bytes. + * - DS17285/DS17287 - 2048 bytes. + * - DS17485/DS17487 - 4096 bytes. + * - DS17885/DS17887 - 8192 bytes. + */ +#define NVRAM_TIME_BASE 0x0e /* NVRAM Addr in Time regs */ +#define NVRAM_BANK0_BASE 0x40 /* NVRAM Addr in Bank0 regs */ +#define NVRAM_SZ_TIME 50 +#define NVRAM_SZ_BANK0 64 +#if defined(CONFIG_RTC_DRV_DS1685) +# define NVRAM_SZ_EXTND 128 +#elif defined(CONFIG_RTC_DRV_DS1689) +# define NVRAM_SZ_EXTND 0 +#elif defined(CONFIG_RTC_DRV_DS17285) +# define NVRAM_SZ_EXTND 2048 +#elif defined(CONFIG_RTC_DRV_DS17485) +# define NVRAM_SZ_EXTND 4096 +#elif defined(CONFIG_RTC_DRV_DS17885) +# define NVRAM_SZ_EXTND 8192 +#endif +#define NVRAM_TOTAL_SZ_BANK0 (NVRAM_SZ_TIME + NVRAM_SZ_BANK0) +#define NVRAM_TOTAL_SZ (NVRAM_TOTAL_SZ_BANK0 + NVRAM_SZ_EXTND) + + +/* + * Function Prototypes. + */ +extern void ATTRIB_NORET + ds1685_rtc_poweroff(struct platform_device *pdev); + +#endif /* _LINUX_RTC_DS1685_H_ */ From kumba@gentoo.org Sun Apr 10 08:16:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Apr 2011 08:16:57 +0200 (CEST) Received: from qmta07.westchester.pa.mail.comcast.net ([76.96.62.64]:47482 "EHLO qmta07.westchester.pa.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491010Ab1DJGQv (ORCPT ); Sun, 10 Apr 2011 08:16:51 +0200 Received: from omta07.westchester.pa.mail.comcast.net ([76.96.62.59]) by qmta07.westchester.pa.mail.comcast.net with comcast id ViGk1g0011GhbT857iGkf3; Sun, 10 Apr 2011 06:16:44 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta07.westchester.pa.mail.comcast.net with comcast id ViGj1g00S3XYSBH3TiGjVB; Sun, 10 Apr 2011 06:16:44 +0000 Message-ID: <4DA14B24.3070207@gentoo.org> Date: Sun, 10 Apr 2011 02:16:04 -0400 From: Joshua Kinard User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 MIME-Version: 1.0 To: Linux MIPS List , Ralf Baechle CC: rtc-linux@googlegroups.com, LKML , Alessandro Zummo Subject: Re: [PATCH 2/2]: MIPS: sgi-ip32: Add support for rtc-ds1685 to SGI O2 (IP32) References: <4D9DB95F.8040100@gentoo.org> In-Reply-To: <4D9DB95F.8040100@gentoo.org> X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29723 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips On 04/07/2011 09:17, Joshua Kinard wrote: > > These are the modifications needed to the SGI O2 (IP32) codebase to switch off > of rtc-cmos to rtc-ds1685. It needs to be applied after the main rtc-ds1685 patch. > > Key changes here eliminate the custom power-off code and call upon the version > built into the main driver via platform_data, as well as defining the required > register step-size of 256 bytes (0x100). Updated patch, factoring in Ralf's comments and re-working the ip32_poweroff() function to properly handle accessing the RTC's power-off function regardless if it's a module or not. Signed-off-by: Joshua Kinard --- include/asm/mach-ip32/mc146818rtc.h | 36 ---------- sgi-ip32/ip32-platform.c | 48 ++++++++++--- sgi-ip32/ip32-reset.c | 128 ++++++++++-------------------------- 3 files changed, 77 insertions(+), 135 deletions(-) diff -Naurp a/arch/mips/include/asm/mach-ip32/mc146818rtc.h b/arch/mips/include/asm/mach-ip32/mc146818rtc.h --- a/arch/mips/include/asm/mach-ip32/mc146818rtc.h +++ b/arch/mips/include/asm/mach-ip32/mc146818rtc.h @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * Copyright (C) 2000 Harald Koerfgen - * - * RTC routines for IP32 style attached Dallas chip. - */ -#ifndef __ASM_MACH_IP32_MC146818RTC_H -#define __ASM_MACH_IP32_MC146818RTC_H - -#include - -#define RTC_PORT(x) (0x70 + (x)) - -static unsigned char CMOS_READ(unsigned long addr) -{ - return mace->isa.rtc[addr << 8]; -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - mace->isa.rtc[addr << 8] = data; -} - -/* - * FIXME: Do it right. For now just assume that no one lives in 20th century - * and no O2 user in 22th century ;-) - */ -#define mc146818_decode_year(year) ((year) + 2000) - -#define RTC_ALWAYS_BCD 0 - -#endif /* __ASM_MACH_IP32_MC146818RTC_H */ diff -Naurp a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c --- a/arch/mips/sgi-ip32/ip32-platform.c +++ b/arch/mips/sgi-ip32/ip32-platform.c @@ -9,10 +9,13 @@ #include #include #include +#include #include #include +extern void ip32_prepare_poweroff(void); + #define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1) #define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2) @@ -90,22 +93,49 @@ static __init int sgio2btns_devinit(void device_initcall(sgio2btns_devinit); -static struct resource sgio2_cmos_rsrc[] = { +#define MACE_RTC_RES_START (MACE_BASE + offsetof(struct sgi_mace, isa.rtc)) +#define MACE_RTC_RES_END (MACE_RTC_RES_START + 32767) + +static struct resource ip32_rtc_resources[] = { { - .start = 0x70, - .end = 0x71, - .flags = IORESOURCE_IO + .start = MACEISA_RTC_IRQ, + .end = MACEISA_RTC_IRQ, + .flags = IORESOURCE_IRQ + }, { + .start = MACE_RTC_RES_START, + .end = MACE_RTC_RES_END, + .flags = IORESOURCE_MEM, } }; -static __init int sgio2_cmos_devinit(void) + +/* RTC registers on IP32 are each padded by 256 bytes (0x100). */ +static struct ds1685_rtc_platform_data +ip32_rtc_platform_data[] = { + { + .regstep = 0x100, + .plat_prepare_poweroff = ip32_prepare_poweroff, + }, +}; + +struct platform_device ip32_rtc_device = { + .name = "rtc-ds1685", + .id = -1, + .dev = { + .platform_data = ip32_rtc_platform_data, + }, + .num_resources = ARRAY_SIZE(ip32_rtc_resources), + .resource = ip32_rtc_resources, +}; + +static int __init sgio2_rtc_devinit(void) { - return IS_ERR(platform_device_register_simple("rtc_cmos", -1, - sgio2_cmos_rsrc, 1)); + return platform_device_register(&ip32_rtc_device); + } -device_initcall(sgio2_cmos_devinit); +device_initcall(sgio2_rtc_devinit); MODULE_AUTHOR("Ralf Baechle "); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2"); +MODULE_DESCRIPTION("IP32 platform setup for SGI IP32 aka O2"); diff -Naurp a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include @@ -33,53 +33,42 @@ #define POWERDOWN_FREQ (HZ / 4) #define PANIC_FREQ (HZ / 8) -static struct timer_list power_timer, blink_timer, debounce_timer; -static int has_panicked, shuting_down; +extern struct platform_device ip32_rtc_device; -static void ip32_machine_restart(char *command) __attribute__((noreturn)); -static void ip32_machine_halt(void) __attribute__((noreturn)); -static void ip32_machine_power_off(void) __attribute__((noreturn)); +static struct timer_list power_timer, blink_timer; +static int has_panicked, shutting_down; -static void ip32_machine_restart(char *cmd) +static ATTRIB_NORET void ip32_poweroff(void *data) { - crime->control = CRIME_CONTROL_HARD_RESET; - while (1); -} + const char *poweroff_func_name = "ds1685_rtc_poweroff\0"; + void (*poweroff_func)(void *) = __symbol_get(poweroff_func_name); -static inline void ip32_machine_halt(void) -{ - ip32_machine_power_off(); -} +#ifdef CONFIG_MODULES + /* If the first __symbol_get failed, our module wasn't loaded. */ + if (!poweroff_func) { + request_module("rtc-ds1685"); + poweroff_func = __symbol_get(poweroff_func_name); + } +#endif -static void ip32_machine_power_off(void) -{ - unsigned char reg_a, xctrl_a, xctrl_b; + if (!poweroff_func) + printk(KERN_EMERG "RTC not available for power-off. " + "Spinning forever ...\n"); + else { + (*poweroff_func)((struct platform_device *)data); + __symbol_put(poweroff_func_name); + } - disable_irq(MACEISA_RTC_IRQ); - reg_a = CMOS_READ(RTC_REG_A); - - /* setup for kickstart & wake-up (DS12287 Ref. Man. p. 19) */ - reg_a &= ~DS_REGA_DV2; - reg_a |= DS_REGA_DV1; - - CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); - wbflush(); - xctrl_b = CMOS_READ(DS_B1_XCTRL4B) - | DS_XCTRL4B_ABE | DS_XCTRL4B_KFE; - CMOS_WRITE(xctrl_b, DS_B1_XCTRL4B); - xctrl_a = CMOS_READ(DS_B1_XCTRL4A) & ~DS_XCTRL4A_IFS; - CMOS_WRITE(xctrl_a, DS_B1_XCTRL4A); - wbflush(); - /* adios amigos... */ - CMOS_WRITE(xctrl_a | DS_XCTRL4A_PAB, DS_B1_XCTRL4A); - CMOS_WRITE(reg_a, RTC_REG_A); - wbflush(); while (1); } -static void power_timeout(unsigned long data) + +static void ip32_machine_restart(char *cmd) __attribute__((noreturn)); +static void ip32_machine_restart(char *cmd) { - ip32_machine_power_off(); + msleep(10); + crime->control = CRIME_CONTROL_HARD_RESET; + while (1); } static void blink_timeout(unsigned long data) @@ -89,44 +78,27 @@ static void blink_timeout(unsigned long mod_timer(&blink_timer, jiffies + data); } -static void debounce(unsigned long data) +static void ip32_machine_halt(void) { - unsigned char reg_a, reg_c, xctrl_a; - - reg_c = CMOS_READ(RTC_INTR_FLAGS); - reg_a = CMOS_READ(RTC_REG_A); - CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); - wbflush(); - xctrl_a = CMOS_READ(DS_B1_XCTRL4A); - if ((xctrl_a & DS_XCTRL4A_IFS) || (reg_c & RTC_IRQF )) { - /* Interrupt still being sent. */ - debounce_timer.expires = jiffies + 50; - add_timer(&debounce_timer); - - /* clear interrupt source */ - CMOS_WRITE(xctrl_a & ~DS_XCTRL4A_IFS, DS_B1_XCTRL4A); - CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); - return; - } - CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); - - if (has_panicked) - ip32_machine_restart(NULL); + ip32_poweroff(&ip32_rtc_device); +} - enable_irq(MACEISA_RTC_IRQ); +static void power_timeout(unsigned long data) +{ + ip32_poweroff(&ip32_rtc_device); } -static inline void ip32_power_button(void) +void ip32_prepare_poweroff(void) { if (has_panicked) return; - if (shuting_down || kill_cad_pid(SIGINT, 1)) { + if (shutting_down || kill_cad_pid(SIGINT, 1)) { /* No init process or button pressed twice. */ - ip32_machine_power_off(); + ip32_poweroff(&ip32_rtc_device); } - shuting_down = 1; + shutting_down = 1; blink_timer.data = POWERDOWN_FREQ; blink_timeout(POWERDOWN_FREQ); @@ -136,27 +108,6 @@ static inline void ip32_power_button(voi add_timer(&power_timer); } -static irqreturn_t ip32_rtc_int(int irq, void *dev_id) -{ - unsigned char reg_c; - - reg_c = CMOS_READ(RTC_INTR_FLAGS); - if (!(reg_c & RTC_IRQF)) { - printk(KERN_WARNING - "%s: RTC IRQ without RTC_IRQF\n", __func__); - } - /* Wait until interrupt goes away */ - disable_irq_nosync(MACEISA_RTC_IRQ); - init_timer(&debounce_timer); - debounce_timer.function = debounce; - debounce_timer.expires = jiffies + 50; - add_timer(&debounce_timer); - - printk(KERN_DEBUG "Power button pressed\n"); - ip32_power_button(); - return IRQ_HANDLED; -} - static int panic_event(struct notifier_block *this, unsigned long event, void *ptr) { @@ -190,15 +141,12 @@ static __init int ip32_reboot_setup(void _machine_restart = ip32_machine_restart; _machine_halt = ip32_machine_halt; - pm_power_off = ip32_machine_power_off; + pm_power_off = ip32_machine_halt; init_timer(&blink_timer); blink_timer.function = blink_timeout; atomic_notifier_chain_register(&panic_notifier_list, &panic_block); - if (request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL)) - panic("Can't allocate MACEISA RTC IRQ"); - return 0; } From jkosina@suse.cz Sun Apr 10 17:09:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Apr 2011 17:09:13 +0200 (CEST) Received: from cantor.suse.de ([195.135.220.2]:55195 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491117Ab1DJPJJ (ORCPT ); Sun, 10 Apr 2011 17:09:09 +0200 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 1D8A18FEA2; Sun, 10 Apr 2011 17:09:08 +0200 (CEST) Date: Sun, 10 Apr 2011 08:09:06 -0700 (PDT) From: Jiri Kosina To: Joe Perches Cc: Srinidhi Kasagar , Linus Walleij , David Brown , Daniel Walker , Bryan Huntsman , Wim Van Sebroeck , Russell King , Ralf Baechle , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux-arm-msm@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: Re: [trivial PATCH 1/2] treewide: Fix iomap resource size miscalculations In-Reply-To: Message-ID: References: User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29724 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jkosina@suse.cz Precedence: bulk X-list: linux-mips On Wed, 23 Mar 2011, Joe Perches wrote: > Convert off-by-1 r->end - r->start to resource_size(r) > > Signed-off-by: Joe Perches > --- > arch/arm/mach-ux500/mbox-db5500.c | 6 ++---- > arch/mips/rb532/gpio.c | 2 +- > drivers/video/msm/mddi.c | 2 +- > drivers/watchdog/bcm63xx_wdt.c | 2 +- > 4 files changed, 5 insertions(+), 7 deletions(-) Applied, thanks > > diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c > index a4ffb9f..2b2d51c 100644 > --- a/arch/arm/mach-ux500/mbox-db5500.c > +++ b/arch/arm/mach-ux500/mbox-db5500.c > @@ -416,8 +416,7 @@ struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv) > dev_dbg(&(mbox->pdev->dev), > "Resource name: %s start: 0x%X, end: 0x%X\n", > resource->name, resource->start, resource->end); > - mbox->virtbase_peer = > - ioremap(resource->start, resource->end - resource->start); > + mbox->virtbase_peer = ioremap(resource->start, resource_size(resource)); > if (!mbox->virtbase_peer) { > dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n"); > mbox = NULL; > @@ -440,8 +439,7 @@ struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv) > dev_dbg(&(mbox->pdev->dev), > "Resource name: %s start: 0x%X, end: 0x%X\n", > resource->name, resource->start, resource->end); > - mbox->virtbase_local = > - ioremap(resource->start, resource->end - resource->start); > + mbox->virtbase_local = ioremap(resource->start, resource_size(resource)); > if (!mbox->virtbase_local) { > dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n"); > mbox = NULL; > diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c > index 37de05d..6c47dfe 100644 > --- a/arch/mips/rb532/gpio.c > +++ b/arch/mips/rb532/gpio.c > @@ -185,7 +185,7 @@ int __init rb532_gpio_init(void) > struct resource *r; > > r = rb532_gpio_reg0_res; > - rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start); > + rb532_gpio_chip->regbase = ioremap_nocache(r->start, resource_size(r)); > > if (!rb532_gpio_chip->regbase) { > printk(KERN_ERR "rb532: cannot remap GPIO register 0\n"); > diff --git a/drivers/video/msm/mddi.c b/drivers/video/msm/mddi.c > index b66d86a..178b072 100644 > --- a/drivers/video/msm/mddi.c > +++ b/drivers/video/msm/mddi.c > @@ -679,7 +679,7 @@ static int __devinit mddi_probe(struct platform_device *pdev) > printk(KERN_ERR "mddi: no associated mem resource!\n"); > return -ENOMEM; > } > - mddi->base = ioremap(resource->start, resource->end - resource->start); > + mddi->base = ioremap(resource->start, resource_size(resource)); > if (!mddi->base) { > printk(KERN_ERR "mddi: failed to remap base!\n"); > ret = -EINVAL; > diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c > index 3c5045a..5064e83 100644 > --- a/drivers/watchdog/bcm63xx_wdt.c > +++ b/drivers/watchdog/bcm63xx_wdt.c > @@ -248,7 +248,7 @@ static int __devinit bcm63xx_wdt_probe(struct platform_device *pdev) > return -ENODEV; > } > > - bcm63xx_wdt_device.regs = ioremap_nocache(r->start, r->end - r->start); > + bcm63xx_wdt_device.regs = ioremap_nocache(r->start, resource_size(r)); > if (!bcm63xx_wdt_device.regs) { > dev_err(&pdev->dev, "failed to remap I/O resources\n"); > return -ENXIO; > -- > 1.7.4.2.g597a6.dirty > -- Jiri Kosina SUSE Labs, Novell Inc. From ukl@pengutronix.de Sun Apr 10 20:13:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Apr 2011 20:13:57 +0200 (CEST) Received: from metis.ext.pengutronix.de ([92.198.50.35]:42186 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491154Ab1DJSNy (ORCPT ); Sun, 10 Apr 2011 20:13:54 +0200 Received: from octopus.hi.pengutronix.de ([2001:6f8:1178:2:215:17ff:fe12:23b0]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1Q8z85-0004cW-4K; Sun, 10 Apr 2011 20:12:57 +0200 Received: from ukl by octopus.hi.pengutronix.de with local (Exim 4.69) (envelope-from ) id 1Q8z7m-0002qv-8J; Sun, 10 Apr 2011 20:12:38 +0200 Date: Sun, 10 Apr 2011 20:12:38 +0200 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= To: wanlong.gao@gmail.com Cc: linux@arm.linux.org.uk, hans-christian.egtvedt@atmel.com, ralf@linux-mips.org, benh@kernel.crashing.org, paulus@samba.org, david.woodhouse@intel.com, akpm@linux-foundation.org, mingo@elte.hu, rientjes@google.com, nicolas.ferre@atmel.com, eric@eukrea.com, tony@atomide.com, santosh.shilimkar@ti.com, khilman@deeprootsystems.com, ben-linux@fluff.org, sam@ravnborg.org, manuel.lauss@googlemail.com, galak@kernel.crashing.org, anton@samba.org, grant.likely@secretlab.ca, sfr@canb.auug.org.au, jwboyer@linux.vnet.ibm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] fix build warnings on defconfigs Message-ID: <20110410181238.GE18601@pengutronix.de> References: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-SA-Exim-Connect-IP: 2001:6f8:1178:2:215:17ff:fe12:23b0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-mips@linux-mips.org Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29725 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ukl@pengutronix.de Precedence: bulk X-list: linux-mips On Sun, Apr 10, 2011 at 03:04:18AM +0800, wanlong.gao@gmail.com wrote: > From: Wanlong Gao > > Change the BT_L2CAP and BT_SCO defconfigs from 'm' to 'y', > since BT_L2CAP and BT_SCO had changed to bool configs. Pointing out the commit that changed these two in the commit log would be nice. Something like: The BT_L2CAP and BT_SCO configs are bool since 6427451 (Bluetooth: Merge L2CAP and SCO modules into bluetooth.ko) . So change all defconfigs from =m to =y. Other than that Acked-by: Uwe Kleine-König Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | From juhosg@openwrt.org Sun Apr 10 22:05:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Apr 2011 22:05:20 +0200 (CEST) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43737 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491189Ab1DJUFO (ORCPT ); Sun, 10 Apr 2011 22:05:14 +0200 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 9353D14013D; Sun, 10 Apr 2011 22:05:09 +0200 (CEST) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 1ADF7140035; Sun, 10 Apr 2011 22:05:09 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos , Imre Kaloz , Greg Kroah-Hartman , Alan Stern , linux-usb@vger.kernel.org Subject: [PATCH 1/3] USB: ehci: add bus glue for the Atheros AR7XXX/AR9XXX SoCs Date: Sun, 10 Apr 2011 22:04:58 +0200 Message-Id: <1302465900-16814-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 X-VBMS: A17F9B4D533 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The Atheros AR71XX/AR9XXX SoCs have a built-in EHCI controller. This patch adds the necessary glue code to make the generic EHCI driver usable for them. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org --- arch/mips/ath79/Kconfig | 3 + drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/ehci-ath79.c | 200 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + 4 files changed, 216 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-ath79.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index b058282..649a2a3 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -26,12 +26,15 @@ config ATH79_MACH_PB44 endmenu config SOC_AR71XX + select USB_ARCH_HAS_EHCI def_bool n config SOC_AR724X + select USB_ARCH_HAS_EHCI def_bool n config SOC_AR913X + select USB_ARCH_HAS_EHCI def_bool n config ATH79_DEV_AR913X_WMAC diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 9483acd..9970c86 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -202,6 +202,14 @@ config USB_CNS3XXX_EHCI It is needed for high-speed (480Mbit/sec) USB 2.0 device support. +config USB_EHCI_ATH79 + bool "EHCI support for AR7XX/AR9XXX SoCs" + depends on USB_EHCI_HCD && ATH79 + select USB_EHCI_ROOT_HUB_TT + ---help--- + Enables support for the built-in EHCI controller present + on the Atheros AR7XXX/AR9XXX SoCs. + config USB_OXU210HP_HCD tristate "OXU210HP HCD support" depends on USB diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c new file mode 100644 index 0000000..74325b8 --- /dev/null +++ b/drivers/usb/host/ehci-ath79.c @@ -0,0 +1,200 @@ +/* + * Bus Glue for Atheros AR7XXX/AR9XXX built-in EHCI controller. + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * Copyright (C) 2007 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +enum { + EHCI_ATH79_IP_V1 = 0, + EHCI_ATH79_IP_V2, +}; + +static const struct platform_device_id ehci_ath79_id_table[] = { + { + .name = "ar71xx-ehci", + .driver_data = EHCI_ATH79_IP_V1, + }, + { + .name = "ar724x-ehci", + .driver_data = EHCI_ATH79_IP_V2, + }, + { + .name = "ar913x-ehci", + .driver_data = EHCI_ATH79_IP_V2, + }, + { + /* terminating entry */ + }, +}; + +MODULE_DEVICE_TABLE(platform, ehci_ath79_id_table); + +static int ehci_ath79_init(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct platform_device *pdev = to_platform_device(hcd->self.controller); + const struct platform_device_id *id; + int ret; + + id = platform_get_device_id(pdev); + if (!id) { + dev_err(hcd->self.controller, "missing device id\n"); + return -EINVAL; + } + + switch (id->driver_data) { + case EHCI_ATH79_IP_V1: + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + break; + + case EHCI_ATH79_IP_V2: + hcd->has_tt = 1; + + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + break; + + default: + BUG(); + } + + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + ehci->sbrn = 0x20; + + ehci_reset(ehci); + + ret = ehci_init(hcd); + if (ret) + return ret; + + ehci_port_power(ehci, 0); + + return 0; +} + +static const struct hc_driver ehci_ath79_hc_driver = { + .description = hcd_name, + .product_desc = "Atheros built-in EHCI controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + .reset = ehci_ath79_init, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_ath79_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_dbg(&pdev->dev, "no IRQ specified\n"); + return -ENODEV; + } + irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "no base address specified\n"); + return -ENODEV; + } + + hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (ret) + goto err_iounmap; + + return 0; + +err_iounmap: + iounmap(hcd->regs); + +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_ath79_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static struct platform_driver ehci_ath79_driver = { + .probe = ehci_ath79_probe, + .remove = ehci_ath79_remove, + .id_table = ehci_ath79_id_table, + .driver = { + .owner = THIS_MODULE, + .name = "ath79-ehci", + } +}; + +MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ehci"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 78561d1..a29527d 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1265,6 +1265,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER tegra_ehci_driver #endif +#ifdef CONFIG_USB_EHCI_ATH79 +#include "ehci-ath79.c" +#define PLATFORM_DRIVER ehci_ath79_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) -- 1.7.2.1 From juhosg@openwrt.org Sun Apr 10 22:05:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Apr 2011 22:05:43 +0200 (CEST) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43743 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491190Ab1DJUFP (ORCPT ); Sun, 10 Apr 2011 22:05:15 +0200 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id E0780140107; Sun, 10 Apr 2011 22:05:09 +0200 (CEST) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 50A00140035; Sun, 10 Apr 2011 22:05:09 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos , Greg Kroah-Hartman , Alan Stern , linux-usb@vger.kernel.org Subject: [PATCH 2/3] USB: ehci: add workaround for Synopsys HC bug Date: Sun, 10 Apr 2011 22:04:59 +0200 Message-Id: <1302465900-16814-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1302465900-16814-1-git-send-email-juhosg@openwrt.org> References: <1302465900-16814-1-git-send-email-juhosg@openwrt.org> X-VBMS: A17FA77C70A | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips A Synopsys USB core used in various SoCs has a bug which might cause that the host controller not issuing ping. When software uses the Doorbell mechanism to remove queue heads, the host controller still has references to the removed queue head even after indicating an Interrupt on Async Advance. This happens if the last executed queue head's Next Link queue head is removed. Consequences of the defect: The Host controller fetches the removed queue head, using memory that would otherwise be deallocated.This results in incorrect transactions on both the USB and system memory. This may result in undefined behavior. Workarounds: 1) If no queue head is active (no Status field's Active bit is set) after removing the queue heads, the software can write one of the valid queue head addresses to the ASYNCLISTADDR register and deallocate the removed queue head's memory after 2 microframes. If one or more of the queue heads is active (the Active bit is set in the Status field) after removing the queue heads, the software can delay memory deallocation after time X, where X is the time required for the Host Controller to go through all the queue heads once. X varies with the number of queue heads and the time required to process periodic transactions: if more periodic transactions must be performed, the Host Controller has less time to process asynchronous transaction processing. 2) Do not use the Doorbell mechanism to remove the queue heads. Disable the Asynchronous Schedule Enable bit instead. The bug has been discussed on the linux-usb-devel mailing-list four years ago, the original thread can be found here: http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg45345.html This patch implements the first workaround as suggested by David Brownell. The built-in USB host controller of the Atheros AR7130/AR7141/AR7161 SoCs requires this to work properly. Signed-off-by: Gabor Juhos Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org --- drivers/usb/host/ehci-ath79.c | 2 ++ drivers/usb/host/ehci-q.c | 3 +++ drivers/usb/host/ehci.h | 1 + 3 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c index 74325b8..7ea23b5 100644 --- a/drivers/usb/host/ehci-ath79.c +++ b/drivers/usb/host/ehci-ath79.c @@ -54,6 +54,8 @@ static int ehci_ath79_init(struct usb_hcd *hcd) switch (id->driver_data) { case EHCI_ATH79_IP_V1: + ehci->has_synopsys_hc_bug = 1; + ehci->caps = hcd->regs; ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c index 98ded66..38c1206 100644 --- a/drivers/usb/host/ehci-q.c +++ b/drivers/usb/host/ehci-q.c @@ -1183,6 +1183,9 @@ static void end_unlink_async (struct ehci_hcd *ehci) ehci->reclaim = NULL; start_unlink_async (ehci, next); } + + if (ehci->has_synopsys_hc_bug) + writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); } /* makes sure the async qh will become idle */ diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index f86d3fa..28ef8ca 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -134,6 +134,7 @@ struct ehci_hcd { /* one per controller */ unsigned amd_pll_fix:1; unsigned fs_i_thresh:1; /* Intel iso scheduling */ unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ + unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ /* required for usb32 quirk */ #define OHCI_CTRL_HCFS (3 << 6) -- 1.7.2.1 From juhosg@openwrt.org Sun Apr 10 22:06:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Apr 2011 22:06:07 +0200 (CEST) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43749 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491191Ab1DJUFP (ORCPT ); Sun, 10 Apr 2011 22:05:15 +0200 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 200CA140138; Sun, 10 Apr 2011 22:05:10 +0200 (CEST) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 81F59140035; Sun, 10 Apr 2011 22:05:09 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos , Imre Kaloz , Greg Kroah-Hartman , Alan Stern , linux-usb@vger.kernel.org Subject: [PATCH 3/3] USB: ohci: add bus glue for the Atheros AR71XX/AR7240 SoCs Date: Sun, 10 Apr 2011 22:05:00 +0200 Message-Id: <1302465900-16814-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1302465900-16814-1-git-send-email-juhosg@openwrt.org> References: <1302465900-16814-1-git-send-email-juhosg@openwrt.org> X-VBMS: A17FBAD2CCF | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29728 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The Atheros AR71XX/AR7240 SoCs have a built-in OHCI controller. This patch adds the necessary glue code to make the generic OHCI driver usable for them. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org --- arch/mips/ath79/Kconfig | 2 + drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/ohci-ath79.c | 151 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 5 ++ 4 files changed, 166 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ohci-ath79.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 649a2a3..4770741 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -27,10 +27,12 @@ endmenu config SOC_AR71XX select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI def_bool n config SOC_AR724X select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI def_bool n config SOC_AR913X diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 9970c86..9a6751e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -295,6 +295,14 @@ config USB_OHCI_HCD_OMAP3 Enables support for the on-chip OHCI controller on OMAP3 and later chips. +config USB_OHCI_ATH79 + bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs" + depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) + default y + help + Enables support for the built-in OHCI controller present on the + Atheros AR71XX/AR7240 SoCs. + config USB_OHCI_HCD_PPC_SOC bool "OHCI support for on-chip PPC USB controller" depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) diff --git a/drivers/usb/host/ohci-ath79.c b/drivers/usb/host/ohci-ath79.c new file mode 100644 index 0000000..ffea3e7 --- /dev/null +++ b/drivers/usb/host/ohci-ath79.c @@ -0,0 +1,151 @@ +/* + * OHCI HCD (Host Controller Driver) for USB. + * + * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * Copyright (C) 2007 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +static int __devinit ohci_ath79_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int ret; + + ret = ohci_init(ohci); + if (ret < 0) + return ret; + + ret = ohci_run(ohci); + if (ret < 0) + goto err; + + return 0; + +err: + ohci_stop(hcd); + return ret; +} + +static const struct hc_driver ohci_ath79_hc_driver = { + .description = hcd_name, + .product_desc = "Atheros built-in OHCI controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + + .irq = ohci_irq, + .flags = HCD_USB11 | HCD_MEMORY, + + .start = ohci_ath79_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ohci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, + .start_port_reset = ohci_start_port_reset, +}; + +static int ohci_ath79_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_dbg(&pdev->dev, "no IRQ specified\n"); + return -ENODEV; + } + irq = res->start; + + hcd = usb_create_hcd(&ohci_ath79_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "no base address specified\n"); + ret = -ENODEV; + goto err_put_hcd; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ohci_hcd_init(hcd_to_ohci(hcd)); + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); + if (ret) + goto err_stop_hcd; + + return 0; + +err_stop_hcd: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +static int ohci_ath79_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static struct platform_driver ohci_hcd_ath79_driver = { + .probe = ohci_ath79_probe, + .remove = ohci_ath79_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ath79-ohci", + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ohci"); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index e728863..8aec65f 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1105,6 +1105,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver #endif +#ifdef CONFIG_USB_OHCI_ATH79 +#include "ohci-ath79.c" +#define PLATFORM_DRIVER ohci_hcd_ath79_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ -- 1.7.2.1 From wanlong.gao@gmail.com Mon Apr 11 01:35:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Apr 2011 01:35:04 +0200 (CEST) Received: from mail-pw0-f65.google.com ([209.85.160.65]:37329 "EHLO mail-pw0-f65.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491202Ab1DJXfC convert rfc822-to-8bit (ORCPT ); Mon, 11 Apr 2011 01:35:02 +0200 Received: by pwi8 with SMTP id 8so742910pwi.0 for ; Sun, 10 Apr 2011 16:34:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=lA2nLszBgqtSEGbYAA0xeWBtUJBxO4hI2wyvJwECP6I=; b=pwPRXOsjCK6xbuzLlP9j2BLQ/TlXeS8pIvpDbpv3jhASUeQD6YMeCbo+UGLqpkR3VK HuPlGHsm4LlSsG+hPfcqbUcbvT/svEUtejzBRK04bKEYnCN4TzxYyvFFcW6SKXD1sWUn Sb1hGkkSX44AXQ24cmRRfjwQNcKpMLXb/klLM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=tsOeg/3dJ+YKU43gq/9oJpR9ZaTEjPO4mNlPoQzOKNKtV3Px3UpFfImoFUUslURHxN UaQTIe1xARKGAYHZI88Ghb7xMs4Pyo5qEKCNuju6yNuTbcPxIhHJaqVsTOrkHges5Opr E2y2zkJWPaxIiM1SCTN3uHQZwUwnm4J7eBz1Q= MIME-Version: 1.0 Received: by 10.142.250.5 with SMTP id x5mr4820436wfh.440.1302478493247; Sun, 10 Apr 2011 16:34:53 -0700 (PDT) Received: by 10.68.64.232 with HTTP; Sun, 10 Apr 2011 16:34:53 -0700 (PDT) In-Reply-To: <20110410181238.GE18601@pengutronix.de> References: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> <20110410181238.GE18601@pengutronix.de> Date: Mon, 11 Apr 2011 07:34:53 +0800 Message-ID: Subject: Re: [PATCH] fix build warnings on defconfigs From: wanlong gao To: =?ISO-8859-1?Q?Uwe_Kleine=2DK=F6nig?= Cc: linux@arm.linux.org.uk, hans-christian.egtvedt@atmel.com, ralf@linux-mips.org, benh@kernel.crashing.org, paulus@samba.org, david.woodhouse@intel.com, akpm@linux-foundation.org, mingo@elte.hu, rientjes@google.com, nicolas.ferre@atmel.com, eric@eukrea.com, tony@atomide.com, santosh.shilimkar@ti.com, khilman@deeprootsystems.com, ben-linux@fluff.org, sam@ravnborg.org, manuel.lauss@googlemail.com, galak@kernel.crashing.org, anton@samba.org, grant.likely@secretlab.ca, sfr@canb.auug.org.au, jwboyer@linux.vnet.ibm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wanlong.gao@gmail.com Precedence: bulk X-list: linux-mips On 4/11/11, Uwe Kleine-König wrote: > On Sun, Apr 10, 2011 at 03:04:18AM +0800, wanlong.gao@gmail.com wrote: >> From: Wanlong Gao >> >> Change the BT_L2CAP and BT_SCO defconfigs from 'm' to 'y', >> since BT_L2CAP and BT_SCO had changed to bool configs. > Pointing out the commit that changed these two in the commit log would > be nice. Something like: > > The BT_L2CAP and BT_SCO configs are bool since > > 6427451 (Bluetooth: Merge L2CAP and SCO modules into bluetooth.ko) > > . So change all defconfigs from =m to =y. > > Other than that > Acked-by: Uwe Kleine-König Thanks . > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | http://www.pengutronix.de/ | > From plagnioj@jcrosoft.com Mon Apr 11 04:57:21 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Apr 2011 04:57:25 +0200 (CEST) Received: from 30.mail-out.ovh.net ([213.186.62.213]:57881 "HELO 30.mail-out.ovh.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1490957Ab1DKC5V (ORCPT ); Mon, 11 Apr 2011 04:57:21 +0200 Received: (qmail 8951 invoked by uid 503); 11 Apr 2011 02:45:22 -0000 Received: from b9.ovh.net (HELO mail419.ha.ovh.net) (213.186.33.59) by 30.mail-out.ovh.net with SMTP; 11 Apr 2011 02:45:21 -0000 Received: from b0.ovh.net (HELO queueout) (213.186.33.50) by b0.ovh.net with SMTP; 11 Apr 2011 04:57:17 +0200 Received: from ns32433.ovh.net (HELO localhost) (plagnioj%jcrosoft.com@213.251.161.87) by ns0.ovh.net with SMTP; 11 Apr 2011 04:57:16 +0200 Date: Mon, 11 Apr 2011 04:45:59 +0200 From: Jean-Christophe PLAGNIOL-VILLARD To: wanlong.gao@gmail.com Cc: linux@arm.linux.org.uk, hans-christian.egtvedt@atmel.com, ralf@linux-mips.org, benh@kernel.crashing.org, paulus@samba.org, david.woodhouse@intel.com, akpm@linux-foundation.org, u.kleine-koenig@pengutronix.de, mingo@elte.hu, rientjes@google.com, nicolas.ferre@atmel.com, eric@eukrea.com, tony@atomide.com, santosh.shilimkar@ti.com, khilman@deeprootsystems.com, ben-linux@fluff.org, sam@ravnborg.org, manuel.lauss@googlemail.com, galak@kernel.crashing.org, anton@samba.org, grant.likely@secretlab.ca, sfr@canb.auug.org.au, jwboyer@linux.vnet.ibm.com, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] fix build warnings on defconfigs Message-ID: <20110411024559.GB18925@game.jcrosoft.org> References: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> X-PGP-Key: http://uboot.jcrosoft.org/plagnioj.asc X-PGP-key-fingerprint: 6309 2BBA 16C8 3A07 1772 CC24 DEFC FFA3 279C CE7C User-Agent: Mutt/1.5.20 (2009-06-14) X-Ovh-Tracer-Id: 7876232800264039283 X-Ovh-Remote: 213.251.161.87 (ns32433.ovh.net) X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: plagnioj@jcrosoft.com Precedence: bulk X-list: linux-mips On 03:04 Sun 10 Apr , wanlong.gao@gmail.com wrote: > From: Wanlong Gao > > Change the BT_L2CAP and BT_SCO defconfigs from 'm' to 'y', > since BT_L2CAP and BT_SCO had changed to bool configs. > > Signed-off-by: Wanlong Gao > --- for at91 Acked-by: Jean-Christophe PLAGNIOL-VILLARD Best Regards, J. From grinberg@compulab.co.il Mon Apr 11 08:11:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Apr 2011 08:12:01 +0200 (CEST) Received: from 50.23.254.54-static.reverse.softlayer.com ([50.23.254.54]:60779 "EHLO softlayer.compulab.co.il" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490982Ab1DKGL6 (ORCPT ); Mon, 11 Apr 2011 08:11:58 +0200 Received: from [62.90.235.247] (port=59178 helo=zimbra-mta.compulab.co.il) by softlayer.compulab.co.il with esmtp (Exim 4.69) (envelope-from ) id 1Q9AL0-0000eq-G9; Mon, 11 Apr 2011 09:11:02 +0300 Received: from localhost (localhost.localdomain [127.0.0.1]) by zimbra-mta.compulab.co.il (Postfix) with ESMTP id 5DE4A7E91FF; Mon, 11 Apr 2011 09:11:01 +0300 (IDT) X-Virus-Scanned: amavisd-new at compulab.co.il Received: from zimbra-mta.compulab.co.il ([127.0.0.1]) by localhost (zimbra-mta.compulab.co.il [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Yuy1LUAuTvwF; Mon, 11 Apr 2011 09:11:00 +0300 (IDT) Received: from [10.1.1.13] (grinberg-pc.compulab.local [10.1.1.13]) by zimbra-mta.compulab.co.il (Postfix) with ESMTP id 567E77E91EF; Mon, 11 Apr 2011 09:11:00 +0300 (IDT) Message-ID: <4DA29B75.4090401@compulab.co.il> Date: Mon, 11 Apr 2011 09:11:01 +0300 From: Igor Grinberg Organization: CompuLab Ltd. User-Agent: Mozilla/5.0 (X11; U; Linux i686; en; rv:1.9.2.13) Gecko/20101211 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: wanlong.gao@gmail.com CC: linux@arm.linux.org.uk, hans-christian.egtvedt@atmel.com, ralf@linux-mips.org, benh@kernel.crashing.org, paulus@samba.org, david.woodhouse@intel.com, akpm@linux-foundation.org, u.kleine-koenig@pengutronix.de, mingo@elte.hu, rientjes@google.com, nicolas.ferre@atmel.com, eric@eukrea.com, tony@atomide.com, santosh.shilimkar@ti.com, khilman@deeprootsystems.com, ben-linux@fluff.org, sam@ravnborg.org, manuel.lauss@googlemail.com, galak@kernel.crashing.org, anton@samba.org, grant.likely@secretlab.ca, sfr@canb.auug.org.au, jwboyer@linux.vnet.ibm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] fix build warnings on defconfigs References: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> In-Reply-To: <1302375858-11253-1-git-send-email-wanlong.gao@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - softlayer.compulab.co.il X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - compulab.co.il Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29731 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grinberg@compulab.co.il Precedence: bulk X-list: linux-mips On 04/09/11 22:04, wanlong.gao@gmail.com wrote: > From: Wanlong Gao > > Change the BT_L2CAP and BT_SCO defconfigs from 'm' to 'y', > since BT_L2CAP and BT_SCO had changed to bool configs. > > Signed-off-by: Wanlong Gao > --- For: > arch/arm/configs/cm_x2xx_defconfig | 4 ++-- > arch/arm/configs/cm_x300_defconfig | 4 ++-- > arch/arm/configs/em_x270_defconfig | 4 ++-- Acked-by: Igor Grinberg -- Regards, Igor. From yyuasa@gmail.com Mon Apr 11 14:56:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Apr 2011 14:56:59 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:35773 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490987Ab1DKM4x (ORCPT ); Mon, 11 Apr 2011 14:56:53 +0200 Received: by iwn36 with SMTP id 36so6553274iwn.36 for ; Mon, 11 Apr 2011 05:56:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:date:from:to:cc:subject:message-id :x-mailer:mime-version:content-type:content-transfer-encoding; bh=VoI3ZvmUjucURZ9OhTtR3FGvlbTE5c7WuNr8805Np1o=; b=KVyG0wuJ6KheD2lAHnRF82SERKYDAgv9DdzV1Hr4FrRWoDlWTF24qTsAMzt7MQUvNM VQoCeU6fSMSk/EsP1rcT9j6jiuzu/42Qd2yyJnTVQRS85Ya9yN/TmVbGmTIwKh0ekbEq S7u8N8EXgHs+DlqxF+GdgUc6zcBFah7npIRhI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=n5+IpdbTg1SgZkD9fpz3j0wTlbpR64SDMDnKx9hwc5DhO0ffQBcyNVa+JhIX//YOqr zoodEp8pq6sltzC4gLtV7Jij3+E4LVaCawUHnnvofpXSR22mJGBLF3uRk8miZzD0gkj6 ji6uR4KVCJuDobij9NraK71Vxa9Ors2SGAHDg= Received: by 10.43.135.8 with SMTP id ie8mr8565882icc.171.1302526605529; Mon, 11 Apr 2011 05:56:45 -0700 (PDT) Received: from stratos (sannin29007.nirai.ne.jp [203.160.29.7]) by mx.google.com with ESMTPS id o3sm4220044ibd.61.2011.04.11.05.56.41 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 11 Apr 2011 05:56:43 -0700 (PDT) Date: Mon, 11 Apr 2011 21:56:39 +0900 From: Yoichi Yuasa To: Greg Kroah-Hartman Cc: yuasa@linux-mips.org, linux-usb , linux-mips Subject: [PATCH] USB: ohci-au1xxx: fix warning "__BIG_ENDIAN" is not defined Message-Id: <20110411215639.6c443295.yuasa@linux-mips.org> X-Mailer: Sylpheed 3.1.0 (GTK+ 2.22.0; x86_64-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29732 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips In file included from drivers/usb/host/ohci-hcd.c:1028:0: drivers/usb/host/ohci-au1xxx.c:36:7: warning: "__BIG_ENDIAN" is not defined Signed-off-by: Yoichi Yuasa --- drivers/usb/host/ohci-au1xxx.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 17a6043..958d985 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -33,7 +33,7 @@ #ifdef __LITTLE_ENDIAN #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) -#elif __BIG_ENDIAN +#elif defined(__BIG_ENDIAN) #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \ USBH_ENABLE_BE) #else -- 1.7.3.4 From stern+4dbee946@rowland.harvard.edu Mon Apr 11 20:54:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Apr 2011 20:54:11 +0200 (CEST) Received: from iolanthe.rowland.org ([192.131.102.54]:58017 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491143Ab1DKSyE (ORCPT ); Mon, 11 Apr 2011 20:54:04 +0200 Received: (qmail 3979 invoked by uid 2102); 11 Apr 2011 14:53:53 -0400 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 11 Apr 2011 14:53:53 -0400 Date: Mon, 11 Apr 2011 14:53:53 -0400 (EDT) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Gabor Juhos cc: Ralf Baechle , , Greg Kroah-Hartman , Subject: Re: [PATCH 2/3] USB: ehci: add workaround for Synopsys HC bug In-Reply-To: <1302465900-16814-2-git-send-email-juhosg@openwrt.org> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29733 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips On Sun, 10 Apr 2011, Gabor Juhos wrote: > A Synopsys USB core used in various SoCs has a bug which might cause > that the host controller not issuing ping. > > When software uses the Doorbell mechanism to remove queue heads, the > host controller still has references to the removed queue head even > after indicating an Interrupt on Async Advance. This happens if the last > executed queue head's Next Link queue head is removed. > > Consequences of the defect: > The Host controller fetches the removed queue head, using memory that > would otherwise be deallocated.This results in incorrect transactions on > both the USB and system memory. This may result in undefined behavior. > --- a/drivers/usb/host/ehci-q.c > +++ b/drivers/usb/host/ehci-q.c > @@ -1183,6 +1183,9 @@ static void end_unlink_async (struct ehci_hcd *ehci) > ehci->reclaim = NULL; > start_unlink_async (ehci, next); > } > + > + if (ehci->has_synopsys_hc_bug) > + writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); > } This should be ehci_writel(ehci, ...). Alan Stern From juhosg@openwrt.org Mon Apr 11 21:42:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Apr 2011 21:42:33 +0200 (CEST) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:36503 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491143Ab1DKTma convert rfc822-to-8bit (ORCPT ); Mon, 11 Apr 2011 21:42:30 +0200 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id F0DFE14014A; Mon, 11 Apr 2011 21:42:22 +0200 (CEST) Received: from [127.0.0.1] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 7A3AB14013D; Mon, 11 Apr 2011 21:42:22 +0200 (CEST) Message-ID: <4DA359A0.5020503@openwrt.org> Date: Mon, 11 Apr 2011 21:42:24 +0200 From: Gabor Juhos User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; hu-HU; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 MIME-Version: 1.0 To: Alan Stern CC: Ralf Baechle , linux-mips@linux-mips.org, Greg Kroah-Hartman , linux-usb@vger.kernel.org Subject: Re: [PATCH 2/3] USB: ehci: add workaround for Synopsys HC bug References: In-Reply-To: X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 X-Antivirus: avast! (VPS 110411-0, 2011.04.11), Outbound message X-Antivirus-Status: Clean Content-Transfer-Encoding: 8BIT X-VBMS: A166A1A67D0 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29734 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips 2011.04.11. 20:53 keltezéssel, Alan Stern írta: > On Sun, 10 Apr 2011, Gabor Juhos wrote: > >> A Synopsys USB core used in various SoCs has a bug which might cause >> that the host controller not issuing ping. >> >> When software uses the Doorbell mechanism to remove queue heads, the >> host controller still has references to the removed queue head even >> after indicating an Interrupt on Async Advance. This happens if the last >> executed queue head's Next Link queue head is removed. >> >> Consequences of the defect: >> The Host controller fetches the removed queue head, using memory that >> would otherwise be deallocated.This results in incorrect transactions on >> both the USB and system memory. This may result in undefined behavior. > >> --- a/drivers/usb/host/ehci-q.c >> +++ b/drivers/usb/host/ehci-q.c >> @@ -1183,6 +1183,9 @@ static void end_unlink_async (struct ehci_hcd *ehci) >> ehci->reclaim = NULL; >> start_unlink_async (ehci, next); >> } >> + >> + if (ehci->has_synopsys_hc_bug) >> + writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); >> } > > This should be ehci_writel(ehci, ...). You are right, I will change that. Thanks, Gabor From polyanskiy@gmail.com Tue Apr 12 08:45:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 08:45:09 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:54249 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490958Ab1DLGpF (ORCPT ); Tue, 12 Apr 2011 08:45:05 +0200 Received: by pzk5 with SMTP id 5so2725546pzk.36 for ; Mon, 11 Apr 2011 23:44:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:date:x-google-sender-auth :message-id:subject:from:to:content-type; bh=F5MaIqWVrDA/lUXai7iti8FnaKSDWXvpc71W70VETdw=; b=lA9S1Xpe5NH5MSu9sFKhe2aafMZSN6Uv4SmTEYzL1PRrsVRp1DNq5bRxrnACFau/yo NTisKrA5XngJgXiA7a/9Bh5xUdl3GqzOeg535hUXigNGZbJxwDyvMeyfsIqvLRs4B5KT 8kDim+3l/DLGWB/A8+IOfX9zEiZaPBWjiPWZw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:content-type; b=qAfVSt0LgaValEC1ZfguuoLJSJtPQ/cAsFfvVLvI5zHpnvxZ9VWJTX1xWS0JOWYqf6 vnXbyorAD6PrxAlV0h2ryBTtds9wlrVMAvAbFATFYih1hwc3O5ly3o+Ox1Tk5nyNdrad 9q/OUleEYwwgwKLutbtQqQlEwxofy8e5+WENA= MIME-Version: 1.0 Received: by 10.142.178.17 with SMTP id a17mr895806wff.64.1302590698121; Mon, 11 Apr 2011 23:44:58 -0700 (PDT) Received: by 10.68.43.106 with HTTP; Mon, 11 Apr 2011 23:44:58 -0700 (PDT) Date: Tue, 12 Apr 2011 02:44:58 -0400 X-Google-Sender-Auth: PBUBfxprRCuHUL-1-NJtreJ9n68 Message-ID: Subject: [PATCH] Notifier chain called twice From: Yury Polyanskiy To: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=000e0cd2df94d9696604a0b3078a Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ypolyans@princeton.edu Precedence: bulk X-list: linux-mips --000e0cd2df94d9696604a0b3078a Content-Type: text/plain; charset=ISO-8859-1 Dear all, The notifier chain is currently called twice on OOPS. Patch below. Best, Yury diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 4e00f9b..fdc6773 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -375,8 +375,6 @@ void __noreturn die(const char *str, str unsigned long dvpret = dvpe(); #endif /* CONFIG_MIPS_MT_SMTC */ - notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV); - console_verbose(); spin_lock_irq(&die_lock); bust_spinlocks(1); --000e0cd2df94d9696604a0b3078a Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Dear all,

The notifier chain is currently called twice on OOPS. Patc= h below.

Best,
Yury




diff --git a/arch/mips/ker= nel/traps.c b/arch/mips/kernel/traps.c
index 4e00f9b..fdc6773 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -375= ,8 +375,6 @@ void __noreturn die(const char *str, str
=A0=A0=A0=A0=A0=A0= =A0 unsigned long dvpret =3D dvpe();
=A0#endif /* CONFIG_MIPS_MT_SMTC */=
=A0
-=A0=A0=A0=A0=A0=A0 notify_die(DIE_OOPS, str, regs, 0, regs_to_t= rapnr(regs), SIGSEGV);
-
=A0=A0=A0=A0=A0=A0=A0 console_verbose();
=A0=A0=A0=A0=A0=A0=A0 spin= _lock_irq(&die_lock);
=A0=A0=A0=A0=A0=A0=A0 bust_spinlocks(1);
--000e0cd2df94d9696604a0b3078a-- From sshtylyov@mvista.com Tue Apr 12 12:41:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 12:41:39 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:50770 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491021Ab1DLKlg (ORCPT ); Tue, 12 Apr 2011 12:41:36 +0200 Received: by bwz1 with SMTP id 1so6437032bwz.36 for ; Tue, 12 Apr 2011 03:41:29 -0700 (PDT) Received: by 10.204.14.11 with SMTP id e11mr1211756bka.185.1302604889278; Tue, 12 Apr 2011 03:41:29 -0700 (PDT) Received: from [192.168.2.2] ([91.79.65.152]) by mx.google.com with ESMTPS id c11sm3765447bkc.2.2011.04.12.03.41.27 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 12 Apr 2011 03:41:28 -0700 (PDT) Message-ID: <4DA42BFB.2010908@mvista.com> Date: Tue, 12 Apr 2011 14:39:55 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 MIME-Version: 1.0 To: Yury Polyanskiy CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Notifier chain called twice References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29736 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 12-04-2011 10:44, Yury Polyanskiy wrote: > Dear all, > The notifier chain is currently called twice on OOPS. Patch below. You need to provide your signoff for the patch to be applied. > Best, > Yury The greeting and goodbye shouldn't be parts of the patch. > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index 4e00f9b..fdc6773 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -375,8 +375,6 @@ void __noreturn die(const char *str, str > unsigned long dvpret = dvpe(); > #endif /* CONFIG_MIPS_MT_SMTC */ > > - notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV); > - Unfortunately, the patch is whitespace-mangled: all tabs have been replaced by spaces. WBR, Sergei From blogic@openwrt.org Tue Apr 12 18:08:38 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 18:08:42 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:51728 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491065Ab1DLQIi (ORCPT ); Tue, 12 Apr 2011 18:08:38 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: [PATCH V9] MIPS: lantiq: add NOR flash support Date: Tue, 12 Apr 2011 18:10:01 +0200 Message-Id: <1302624601-18571-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29737 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver/map for NOR devices attached to the SoC via the External Bus Unit (EBU). Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: David Woodhouse Cc: Daniel Schwierzeck Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org --- Changes in V2 * handle the endianess bug inside the map code and not in the generic cfi code * remove the addr swizzle patch Changes in V3 * whitespace * change __iomem void to void __iomem Changes in V4 * fixes a checkpatch.pl bug, the second is a false positive * whitespace cleanups * remove unused typecasts * cleanup ltq_copy_from and ltq_copy_to Changes in V6 * cleanup/add comments * fix line breaks * properly handle return code of add_mtd_partitions() * use pr_err instead of printk Changes in V7 * remove bogus KERN_INFO from pr_err() call Changes in V8 * dynamically allocate the instance of map_info allowing the use of .addr_unlock1 for indication of the probing state, thus eliminating the need for a global variable Changes in V9 * fixes spelling errors * adds proper exit path to init function * adds remove function This patch should be merged via the MIPS tree drivers/mtd/maps/Kconfig | 9 ++ drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq-flash.c | 251 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/maps/lantiq-flash.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 44b1f46..0cf5c57 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -260,6 +260,15 @@ config MTD_BCM963XX Support for parsing CFE image tag and creating MTD partitions on Broadcom BCM63xx boards. +config MTD_LANTIQ + tristate "Lantiq SoC NOR support" + depends on LANTIQ + select MTD_PARTITIONS + help + Lantiq SoCs have a EBU (External Bus Unit). This IP allows to attach + a number of different peripherals to the SoC. This driver adds + support for NOR chips to be added. + config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 08533bd..6adf4c9 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o +obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c new file mode 100644 index 0000000..983c88f --- /dev/null +++ b/drivers/mtd/maps/lantiq-flash.c @@ -0,0 +1,251 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * The NOR flash is connected to the same external bus unit (EBU) as PCI. + * To make PCI work we need to enable the endianness swapping for the address + * written to the EBU. This endianness swapping works for PCI correctly but + * fails for attached NOR devices. To workaround this we need to use a complex + * map. The workaround involves swapping all addresses whilst probing the chip. + * Once probing is complete we stop swapping the addresses but swizzle the + * unlock addresses to ensure that access to the NOR device works correctly. + */ + +enum { + LTQ_NOR_PROBING, + LTQ_NOR_NORMAL +}; + +struct ltq_mtd { + struct resource *res; + struct mtd_info *mtd; + struct map_info *map; +}; + +static char ltq_map_name[] = "ltq_nor"; + +static map_word +ltq_read16(struct map_info *map, unsigned long adr) +{ + unsigned long flags; + map_word temp; + + if (map->map_priv_1 == LTQ_NOR_PROBING) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + temp.x[0] = *(u16 *)(map->virt + adr); + spin_unlock_irqrestore(&ebu_lock, flags); + return temp; +} + +static void +ltq_write16(struct map_info *map, map_word d, unsigned long adr) +{ + unsigned long flags; + + if (map->map_priv_1 == LTQ_NOR_PROBING) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + *(u16 *)(map->virt + adr) = d.x[0]; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +/* + * The following 2 functions copy data between iomem and a cached memory + * section. As memcpy() makes use of pre-fetching we cannot use it here. + * The normal alternative of using memcpy_{to,from}io also makes use of + * memcpy() on MIPS so it is not applicable either. We are therefore stuck + * with having to use our own loop. + */ +static void +ltq_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + unsigned char *f = (unsigned char *)map->virt + from; + unsigned char *t = (unsigned char *)to; + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + while (len--) + *t++ = *f++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static void +ltq_copy_to(struct map_info *map, unsigned long to, + const void *from, ssize_t len) +{ + unsigned char *f = (unsigned char *)from; + unsigned char *t = (unsigned char *)map->virt + to; + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + while (len--) + *t++ = *f++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static const char const *part_probe_types[] = { "cmdlinepart", NULL }; + +static int __init +ltq_mtd_probe(struct platform_device *pdev) +{ + struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); + struct ltq_mtd *ltq_mtd; + struct mtd_partition *parts; + struct resource *res; + int nr_parts = 0; + struct cfi_private *cfi; + int err; + + ltq_mtd = kzalloc(sizeof(struct ltq_mtd), GFP_KERNEL); + platform_set_drvdata(pdev, ltq_mtd); + + ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!ltq_mtd->res) { + dev_err(&pdev->dev, "failed to get memory resource"); + err = -ENOENT; + goto err_out; + } + + res = devm_request_mem_region(&pdev->dev, ltq_mtd->res->start, + resource_size(ltq_mtd->res), dev_name(&pdev->dev)); + if (!ltq_mtd->res) { + dev_err(&pdev->dev, "failed to request mem resource"); + err = -EBUSY; + goto err_out; + } + + ltq_mtd->map = kzalloc(sizeof(struct map_info), GFP_KERNEL); + ltq_mtd->map->phys = res->start; + ltq_mtd->map->size = resource_size(res); + ltq_mtd->map->virt = devm_ioremap_nocache(&pdev->dev, + ltq_mtd->map->phys, ltq_mtd->map->size); + if (!ltq_mtd->map->virt) { + dev_err(&pdev->dev, "failed to ioremap!\n"); + err = -ENOMEM; + goto err_free; + } + + ltq_mtd->map->name = ltq_map_name; + ltq_mtd->map->bankwidth = 2; + ltq_mtd->map->read = ltq_read16; + ltq_mtd->map->write = ltq_write16; + ltq_mtd->map->copy_from = ltq_copy_from; + ltq_mtd->map->copy_to = ltq_copy_to; + + ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; + ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); + ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; + + if (!ltq_mtd->mtd) { + dev_err(&pdev->dev, "probing failed\n"); + err = -ENXIO; + goto err_unmap; + } + + ltq_mtd->mtd->owner = THIS_MODULE; + + cfi = ltq_mtd->map->fldrv_priv; + cfi->addr_unlock1 ^= 1; + cfi->addr_unlock2 ^= 1; + + nr_parts = parse_mtd_partitions(ltq_mtd->mtd, + part_probe_types, &parts, 0); + if (nr_parts > 0) { + dev_info(&pdev->dev, + "using %d partitions from cmdline", nr_parts); + } else { + nr_parts = ltq_mtd_data->nr_parts; + parts = ltq_mtd_data->parts; + } + + err = add_mtd_partitions(ltq_mtd->mtd, parts, nr_parts); + if (err) { + dev_err(&pdev->dev, "failed to add partitions\n"); + goto err_destroy; + } + + return 0; + +err_destroy: + map_destroy(ltq_mtd->mtd); +err_unmap: + iounmap(ltq_mtd->map->virt); +err_free: + kfree(ltq_mtd->map); +err_out: + kfree(ltq_mtd); + return err; +} + +static int __devexit +ltq_mtd_remove(struct platform_device *pdev) +{ + struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); + + if (ltq_mtd) { + if (ltq_mtd->mtd) { + del_mtd_partitions(ltq_mtd->mtd); + map_destroy(ltq_mtd->mtd); + } + if (ltq_mtd->map->virt) + iounmap(ltq_mtd->map->virt); + kfree(ltq_mtd->map); + kfree(ltq_mtd); + } + return 0; +} + +static struct platform_driver ltq_mtd_driver = { + .remove = __devexit_p(ltq_mtd_remove), + .driver = { + .name = "ltq_nor", + .owner = THIS_MODULE, + }, +}; + +static int __init +init_ltq_mtd(void) +{ + int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); + + if (ret) + pr_err("ltq_nor: error registering platform driver"); + return ret; +} + +static void __exit +exit_ltq_mtd(void) +{ + platform_driver_unregister(<q_mtd_driver); +} + +module_init(init_ltq_mtd); +module_exit(exit_ltq_mtd); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC NOR"); -- 1.7.2.3 From blogic@openwrt.org Tue Apr 12 18:09:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 18:09:52 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:58426 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491109Ab1DLQJp (ORCPT ); Tue, 12 Apr 2011 18:09:45 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH 1/3] MIPS: lantiq: add DMA support Date: Tue, 12 Apr 2011 18:11:13 +0200 Message-Id: <1302624675-18652-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1302624675-18652-1-git-send-email-blogic@openwrt.org> References: <1302624675-18652-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29738 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for the DMA engine found inside the XWAY family of SoCs. The engine has 5 ports and 20 channels. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +- arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 60 +++++ arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/dma.c | 272 ++++++++++++++++++++ 4 files changed, 335 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h create mode 100644 arch/mips/lantiq/xway/dma.c diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 34bc993..95f1882 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -85,7 +85,8 @@ #define LTQ_PPE32_SIZE 0x40000 /* DMA */ -#define LTQ_DMA_BASE_ADDR 0xBE104100 +#define LTQ_DMA_BASE_ADDR 0x1E104100 +#define LTQ_DMA_SIZE 0x800 /* PCI */ #define PCI_CR_BASE_ADDR 0x1E105400 diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h new file mode 100644 index 0000000..872943a --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h @@ -0,0 +1,60 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#ifndef LTQ_DMA_H__ +#define LTQ_DMA_H__ + +#define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ +#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */ + +#define LTQ_DMA_OWN BIT(31) /* owner bit */ +#define LTQ_DMA_C BIT(30) /* complete bit */ +#define LTQ_DMA_SOP BIT(29) /* start of packet */ +#define LTQ_DMA_EOP BIT(28) /* end of packet */ +#define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */ +#define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */ +#define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */ + +struct ltq_dma_desc { + u32 ctl; + u32 addr; +}; + +struct ltq_dma_channel { + int nr; /* the channel number */ + int irq; /* the mapped irq */ + int desc; /* the current descriptor */ + struct ltq_dma_desc *desc_base; /* the descriptor base */ + int phys; /* physical addr */ +}; + +enum { + DMA_PORT_ETOP = 0, + DMA_PORT_DEU, +}; + +extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch); +extern void ltq_dma_open(struct ltq_dma_channel *ch); +extern void ltq_dma_close(struct ltq_dma_channel *ch); +extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch); +extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch); +extern void ltq_dma_free(struct ltq_dma_channel *ch); +extern void ltq_dma_init_port(int p); + +#endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index a021def..d88a3e8 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o +obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c new file mode 100644 index 0000000..485d5bf --- /dev/null +++ b/arch/mips/lantiq/xway/dma.c @@ -0,0 +1,272 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include + +#include +#include + +#define LTQ_DMA_CTRL 0x10 +#define LTQ_DMA_CPOLL 0x14 +#define LTQ_DMA_CS 0x18 +#define LTQ_DMA_CCTRL 0x1C +#define LTQ_DMA_CDBA 0x20 +#define LTQ_DMA_CDLEN 0x24 +#define LTQ_DMA_CIS 0x28 +#define LTQ_DMA_CIE 0x2C +#define LTQ_DMA_PS 0x40 +#define LTQ_DMA_PCTRL 0x44 +#define LTQ_DMA_IRNEN 0xf4 + +#define DMA_DESCPT BIT(3) /* descriptor complete irq */ +#define DMA_TX BIT(8) /* TX channel direction */ +#define DMA_CHAN_ON BIT(0) /* channel on / off bit */ +#define DMA_PDEN BIT(6) /* enable packet drop */ +#define DMA_CHAN_RST BIT(1) /* channel on / off bit */ +#define DMA_RESET BIT(0) /* channel on / off bit */ +#define DMA_IRQ_ACK 0x7e /* IRQ status register */ +#define DMA_POLL BIT(31) /* turn on channel polling */ +#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ +#define DMA_2W_BURST BIT(1) /* 2 word burst length */ +#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ +#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */ +#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ + +#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) +#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y)) +#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ + ltq_dma_membase + (z)) + +static void __iomem *ltq_dma_membase; + +void +ltq_dma_enable_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_enable_irq); + +void +ltq_dma_disable_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_disable_irq); + +void +ltq_dma_ack_irq(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_ack_irq); + +void +ltq_dma_open(struct ltq_dma_channel *ch) +{ + unsigned long flag; + + local_irq_save(flag); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL); + ltq_dma_enable_irq(ch); + local_irq_restore(flag); +} +EXPORT_SYMBOL_GPL(ltq_dma_open); + +void +ltq_dma_close(struct ltq_dma_channel *ch) +{ + unsigned long flag; + + local_irq_save(flag); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + ltq_dma_disable_irq(ch); + local_irq_restore(flag); +} +EXPORT_SYMBOL_GPL(ltq_dma_close); + +static void +ltq_dma_alloc(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ch->desc = 0; + ch->desc_base = dma_alloc_coherent(NULL, + LTQ_DESC_NUM * LTQ_DESC_SIZE, + &ch->phys, GFP_ATOMIC); + memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE); + + local_irq_save(flags); + ltq_dma_w32(ch->nr, LTQ_DMA_CS); + ltq_dma_w32(ch->phys, LTQ_DMA_CDBA); + ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + wmb(); + ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL); + while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST) + ; + local_irq_restore(flags); +} + +void +ltq_dma_alloc_tx(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ltq_dma_alloc(ch); + + local_irq_save(flags); + ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx); + +void +ltq_dma_alloc_rx(struct ltq_dma_channel *ch) +{ + unsigned long flags; + + ltq_dma_alloc(ch); + + local_irq_save(flags); + ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); + ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); + ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx); + +void +ltq_dma_free(struct ltq_dma_channel *ch) +{ + if (!ch->desc_base) + return; + ltq_dma_close(ch); + dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE, + ch->desc_base, ch->phys); +} +EXPORT_SYMBOL_GPL(ltq_dma_free); + +void +ltq_dma_init_port(int p) +{ + ltq_dma_w32(p, LTQ_DMA_PS); + switch (p) { + case DMA_PORT_ETOP: + /* + * Tell the DMA engine to swap the endianess of data frames and + * drop packets if the channel arbitration fails. + */ + ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN, + LTQ_DMA_PCTRL); + break; + + case DMA_PORT_DEU: + ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2), + LTQ_DMA_PCTRL); + break; + + default: + break; + } +} +EXPORT_SYMBOL_GPL(ltq_dma_init_port); + +static int +ltq_dma_probe(struct platform_device *pdev) +{ + struct resource *res; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get dma resource\n"); + return -ENOENT; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request dma resource\n"); + return -EBUSY; + } + + ltq_dma_membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_dma_membase) { + dev_err(&pdev->dev, "failed to remap dma engine %d\n", + pdev->id); + return -ENOMEM; + } + + /* power up and reset the dma engine */ + ltq_pmu_enable(PMU_DMA); + ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); + + /* disable all interrupts */ + ltq_dma_w32(0, LTQ_DMA_IRNEN); + + /* reset/configure each channel */ + for (i = 0; i < DMA_MAX_CHANNEL; i++) { + ltq_dma_w32(i, LTQ_DMA_CS); + ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); + ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); + ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); + } + return 0; +} + +static struct platform_driver ltq_dma_driver = { + .probe = ltq_dma_probe, + .driver = { + .name = "ltq_dma", + .owner = THIS_MODULE, + }, +}; + +int __init +ltq_dma_init(void) +{ + int ret = platform_driver_register(<q_dma_driver); + + if (ret) + pr_info("ltq_dma : Error registering platfom driver!"); + return ret; +} + +postcore_initcall(ltq_dma_init); -- 1.7.2.3 From blogic@openwrt.org Tue Apr 12 18:10:11 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 18:10:20 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:58429 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491065Ab1DLQJq (ORCPT ); Tue, 12 Apr 2011 18:09:46 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH 3/3] MIPS: lantiq: add dma/etop board support Date: Tue, 12 Apr 2011 18:11:15 +0200 Message-Id: <1302624675-18652-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1302624675-18652-1-git-send-email-blogic@openwrt.org> References: <1302624675-18652-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29739 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds functions to register the etop and dma platform devices and calls them from the board specific setup code. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/devices.c | 13 +++++++++++++ arch/mips/lantiq/devices.h | 1 + arch/mips/lantiq/xway/devices.c | 27 +++++++++++++++++++++++++++ arch/mips/lantiq/xway/devices.h | 1 + arch/mips/lantiq/xway/mach-easy50712.c | 10 ++++++++++ 5 files changed, 52 insertions(+), 0 deletions(-) diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c index e758863..a10244e 100644 --- a/arch/mips/lantiq/devices.c +++ b/arch/mips/lantiq/devices.c @@ -31,6 +31,19 @@ #define IRQ_RES(resname, irq) \ {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} +/* dma engine */ +static struct resource ltq_dma_resource = { + .name = "dma", + .start = LTQ_DMA_BASE_ADDR, + .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +void __init ltq_register_dma(void) +{ + platform_device_register_simple("ltq_dma", 0, <q_dma_resource, 1); +} + /* nor flash */ static struct resource ltq_nor_resource = { .name = "nor", diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h index 069006c..d339963 100644 --- a/arch/mips/lantiq/devices.h +++ b/arch/mips/lantiq/devices.h @@ -12,6 +12,7 @@ #include #include +extern void ltq_register_dma(void); extern void ltq_register_nor(struct physmap_flash_data *data); extern void ltq_register_wdt(void); extern void ltq_register_asc(int port); diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c index 7d58ae5..99ff2ef 100644 --- a/arch/mips/lantiq/xway/devices.c +++ b/arch/mips/lantiq/xway/devices.c @@ -75,3 +75,30 @@ void __init ltq_register_gpio_stp(void) { platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1); } + +/* ethernet */ +static struct resource ltq_ethernet_resources = { + .name = "etop", + .start = LTQ_ETOP_BASE_ADDR, + .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ltq_ethernet = { + .name = "ltq_etop", + .resource = <q_ethernet_resources, + .num_resources = 1, +}; + +void __init +ltq_register_ethernet(struct ltq_eth_data *eth) +{ + if (!eth) + return; + if (!is_valid_ether_addr(eth->mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + random_ether_addr(eth->mac.sa_data); + } + ltq_ethernet.dev.platform_data = eth; + platform_device_register(<q_ethernet); +} diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h index 87ba61e..2095c3a 100644 --- a/arch/mips/lantiq/xway/devices.h +++ b/arch/mips/lantiq/xway/devices.h @@ -13,5 +13,6 @@ extern void ltq_register_gpio(void); extern void ltq_register_gpio_stp(void); +extern void ltq_register_ethernet(struct ltq_eth_data *eth); #endif diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c index 5242a27..f69460c 100644 --- a/arch/mips/lantiq/xway/mach-easy50712.c +++ b/arch/mips/lantiq/xway/mach-easy50712.c @@ -59,13 +59,23 @@ static struct ltq_pci_data ltq_pci_data = { }, }; +static struct ltq_eth_data ltq_eth_data = { + .mii_mode = REV_MII_MODE, + .channel = { + [1] = 1, + [6] = 1, + }, +}; + static void __init easy50712_init(void) { + ltq_register_dma(); ltq_register_gpio(); ltq_register_gpio_stp(); ltq_register_nor(&easy50712_flash_data); ltq_register_wdt(); ltq_register_pci(<q_pci_data); + ltq_register_ethernet(<q_eth_data); } MIPS_MACHINE(LTQ_MACH_EASY50712, -- 1.7.2.3 From blogic@openwrt.org Tue Apr 12 18:10:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 18:10:46 +0200 (CEST) Received: from nbd.name ([46.4.11.11]:58436 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491086Ab1DLQJs (ORCPT ); Tue, 12 Apr 2011 18:09:48 +0200 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: [PATCH 2/3] MIPS: lantiq: add ethernet driver Date: Tue, 12 Apr 2011 18:11:14 +0200 Message-Id: <1302624675-18652-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1302624675-18652-1-git-send-email-blogic@openwrt.org> References: <1302624675-18652-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29740 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet work. Support for all 8 dma channels, gbit and the embedded switch found on the ar9/vr9 still needs to be implemented. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org -- This Patch thould go via the MIPS tree. .../mips/include/asm/mach-lantiq/lantiq_platform.h | 14 + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/lantiq_etop.c | 710 ++++++++++++++++++++ 5 files changed, 734 insertions(+), 2 deletions(-) create mode 100644 drivers/net/lantiq_etop.c diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h index 1f1dba6..d6b600c 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h @@ -10,6 +10,7 @@ #define _LANTIQ_PLATFORM_H__ #include +#include /* struct used to pass info to the pci core */ enum { @@ -43,4 +44,17 @@ struct ltq_pci_data { int irq[16]; }; +/* struct used to pass info to network drivers */ +enum { + MII_MODE, + REV_MII_MODE, +}; + +#define LTQ_ETH_DATA_CHAN_MAX 0x8 +struct ltq_eth_data { + struct sockaddr mac; + int mii_mode; + int channel[LTQ_ETH_DATA_CHAN_MAX]; +}; + #endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 95f1882..0213601 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -81,8 +81,8 @@ #define PMU_SWITCH 0x10000000 /* ETOP - ethernet */ -#define LTQ_PPE32_BASE_ADDR 0xBE180000 -#define LTQ_PPE32_SIZE 0x40000 +#define LTQ_ETOP_BASE_ADDR 0x1E180000 +#define LTQ_ETOP_SIZE 0x40000 /* DMA */ #define LTQ_DMA_BASE_ADDR 0x1E104100 diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b30c688..4878587 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2017,6 +2017,13 @@ config FTMAC100 from Faraday. It is used on Faraday A320, Andes AG101 and some other ARM/NDS32 SoC's. +config LANTIQ_ETOP + tristate "Lantiq SoC ETOP driver" + depends on SOC_TYPE_XWAY + help + Support for the MII0 inside the Lantiq SoC + + source "drivers/net/fs_enet/Kconfig" source "drivers/net/octeon/Kconfig" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fbfca11..df71da7 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -261,6 +261,7 @@ obj-$(CONFIG_MLX4_CORE) += mlx4/ obj-$(CONFIG_ENC28J60) += enc28j60.o obj-$(CONFIG_ETHOC) += ethoc.o obj-$(CONFIG_GRETH) += greth.o +obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o diff --git a/drivers/net/lantiq_etop.c b/drivers/net/lantiq_etop.c new file mode 100644 index 0000000..ec70a24 --- /dev/null +++ b/drivers/net/lantiq_etop.c @@ -0,0 +1,710 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define LTQ_ETOP_MDIO 0x11804 +#define MDIO_REQUEST 0x80000000 +#define MDIO_READ 0x40000000 +#define MDIO_ADDR_MASK 0x1f +#define MDIO_ADDR_OFFSET 0x15 +#define MDIO_REG_MASK 0x1f +#define MDIO_REG_OFFSET 0x10 +#define MDIO_VAL_MASK 0xffff + +#define PPE32_CGEN 0x800 +#define LQ_PPE32_ENET_MAC_CFG 0x1840 + +#define LTQ_ETOP_ENETS0 0x11850 +#define LTQ_ETOP_MAC_DA0 0x1186C +#define LTQ_ETOP_MAC_DA1 0x11870 +#define LTQ_ETOP_CFG 0x16020 +#define LTQ_ETOP_IGPLEN 0x16080 + +#define MAX_DMA_CHAN 0x8 +#define MAX_DMA_CRC_LEN 0x4 +#define MAX_DMA_DATA_LEN 0x600 + +#define ETOP_FTCU BIT(28) +#define ETOP_MII_MASK 0xf +#define ETOP_MII_NORMAL 0xd +#define ETOP_MII_REVERSE 0xe +#define ETOP_PLEN_UNDER 0x40 +#define ETOP_CGEN 0x800 + +#define IS_TX(x) (x % 2) + +#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) +#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) +#define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +static void __iomem *ltq_etop_membase; + +struct ltq_mii_priv { + struct ltq_eth_data *pldata; + struct resource *res; + struct net_device_stats stats; + + struct mii_bus *mii_bus; + struct phy_device *phydev; + + struct ltq_dma_channel dma[MAX_DMA_CHAN]; + struct sk_buff *tx_skb[MAX_DMA_CHAN >> 1][LTQ_DESC_NUM]; + struct sk_buff *rx_skb[MAX_DMA_CHAN >> 1][LTQ_DESC_NUM]; + + struct tasklet_struct rx_tasklet; + int rx_tasklet_running; + u32 rx_channel_mask; + + struct tasklet_struct tx_tasklet; + int tx_tasklet_running; + u32 tx_channel_mask; + int tx_free[MAX_DMA_CHAN >> 1]; +}; + +static int +ltq_etop_alloc_rx_skb(struct ltq_mii_priv *priv, int ch, int desc) +{ + int idx = ch >> 1; + + priv->rx_skb[idx][desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!priv->rx_skb[idx][desc]) + return -ENOMEM; + + priv->dma[ch].desc_base[desc].addr = dma_map_single(NULL, + priv->rx_skb[idx][desc]->data, + MAX_DMA_DATA_LEN, DMA_FROM_DEVICE); + priv->dma[ch].desc_base[desc].addr = + CPHYSADDR(priv->rx_skb[idx][desc]->data); + priv->dma[ch].desc_base[desc].ctl = + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(2) | MAX_DMA_DATA_LEN; + skb_reserve(priv->rx_skb[idx][desc], 2); + return 0; +} + +static void +ltq_etop_hw_receive(struct net_device *dev, struct ltq_mii_priv *priv, int ch) +{ + struct ltq_dma_desc *d = &priv->dma[ch].desc_base[priv->dma[ch].desc]; + int len = (d->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; + struct sk_buff *skb = priv->rx_skb[ch >> 1][priv->dma[ch].desc]; + + if (ltq_etop_alloc_rx_skb(priv, ch, priv->dma[ch].desc)) { + netdev_err(dev, + "failed to allocate new rx buffer, stopping DMA\n"); + ltq_dma_close(&priv->dma[ch]); + } + + priv->dma[ch].desc++; + priv->dma[ch].desc %= LTQ_DESC_NUM; + + skb_put(skb, len); + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + priv->stats.rx_packets++; + priv->stats.rx_bytes += len; +} + +static void +ltq_etop_rx_tasklet(unsigned long _dev) +{ + struct net_device *dev = (struct net_device *)_dev; + struct ltq_mii_priv *priv = netdev_priv(dev); + unsigned long flags; + int max_irq = 16; + + while (priv->rx_channel_mask && max_irq--) { + int ch = __fls(priv->rx_channel_mask); + int idx = priv->dma[ch].desc; + struct ltq_dma_desc *desc = &priv->dma[ch].desc_base[idx]; + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + /* this is a completed rx transaction */ + ltq_etop_hw_receive(dev, priv, ch); + } else { + /* there are no more complete descriptors */ + priv->rx_channel_mask &= ~BIT(ch); + ltq_dma_ack_irq(&priv->dma[ch]); + } + } + + local_irq_save(flags); + priv->rx_tasklet_running = 0; + if (priv->rx_channel_mask) { + priv->rx_tasklet_running = 1; + tasklet_schedule(&priv->rx_tasklet); + } + local_irq_restore(flags); +} + +static int +ltq_etop_tx_housekeeping(struct net_device *dev, int ch) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + int idx = ch >> 1; + int start_queue = 0; + + while ((priv->dma[ch].desc_base[priv->tx_free[idx]].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + dev_kfree_skb_any(priv->tx_skb[idx][priv->tx_free[idx]]); + priv->tx_skb[idx][priv->tx_free[idx]] = NULL; + memset(&priv->dma[ch].desc_base[priv->tx_free[idx]], 0, + sizeof(struct ltq_dma_desc)); + priv->tx_free[idx]++; + priv->tx_free[idx] %= LTQ_DESC_NUM; + start_queue = 1; + } + return start_queue; +} + +static void +ltq_etop_tx_tasklet(unsigned long _dev) +{ + struct net_device *dev = (struct net_device *)_dev; + struct ltq_mii_priv *priv = netdev_priv(dev); + int start_queue = 0; + + while (priv->tx_channel_mask) { + int ch = __fls(priv->tx_channel_mask); + priv->tx_channel_mask &= ~BIT(ch); + start_queue |= ltq_etop_tx_housekeeping(dev, ch); + ltq_dma_ack_irq(&priv->dma[ch]); + } + if (start_queue) + netif_start_queue(dev); + priv->tx_tasklet_running = 0; +} + +static irqreturn_t +ltq_etop_dma_irq(int irq, void *_priv) +{ + struct ltq_mii_priv *priv = _priv; + int ch = irq - LTQ_DMA_CH0_INT; + + if (!IS_TX(ch) && !priv->rx_tasklet_running) { + priv->rx_channel_mask |= BIT(ch); + priv->rx_tasklet_running = 1; + tasklet_schedule(&priv->rx_tasklet); + } + + if (IS_TX(ch) && !priv->tx_tasklet_running) { + priv->tx_channel_mask |= BIT(ch); + priv->tx_tasklet_running = 1; + tasklet_schedule(&priv->tx_tasklet); + } + return IRQ_HANDLED; +} + +static void +ltq_etop_free_channel(struct net_device *dev, struct ltq_dma_channel *ch) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + + ltq_dma_free(ch); + if (ch->irq) + free_irq(ch->irq, priv); + + if (!IS_TX(ch->nr)) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + if (priv->rx_skb[ch->nr >> 1][desc]) + dev_kfree_skb_any( + priv->rx_skb[ch->nr >> 1][desc]); + } +} + +static void +ltq_etop_hw_exit(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + int ch; + + ltq_pmu_disable(PMU_PPE); + for (ch = 0; ch < MAX_DMA_CHAN; ch++) + if (priv->pldata->channel[ch]) + ltq_etop_free_channel(dev, &priv->dma[ch]); +} + +static int +ltq_etop_hw_init(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + int ch; + + ltq_pmu_enable(PMU_PPE); + + if (priv->pldata->mii_mode == REV_MII_MODE) + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_REVERSE, LTQ_ETOP_CFG); + else + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_NORMAL, LTQ_ETOP_CFG); + ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); + + ltq_dma_init_port(DMA_PORT_ETOP); + + for (ch = 0; ch < MAX_DMA_CHAN; ch++) { + int irq = LTQ_DMA_CH0_INT + ch; + + if (!priv->pldata->channel[ch]) + continue; + + priv->dma[ch].nr = ch; + + if (IS_TX(priv->dma[ch].nr)) { + ltq_dma_alloc_tx(&priv->dma[ch]); + request_irq(irq, ltq_etop_dma_irq, + IRQF_DISABLED, "etop_tx", priv); + } else { + int desc; + ltq_dma_alloc_rx(&priv->dma[ch]); + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + if (ltq_etop_alloc_rx_skb(priv, ch, desc)) + return -ENOMEM; + request_irq(irq, ltq_etop_dma_irq, + IRQF_DISABLED, "etop_rx", priv); + } + priv->dma[ch].irq = irq; + } + tasklet_init(&priv->rx_tasklet, ltq_etop_rx_tasklet, + (unsigned long)dev); + tasklet_init(&priv->tx_tasklet, ltq_etop_tx_tasklet, + (unsigned long)dev); + return 0; +} + +static int +ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) +{ + u32 val = MDIO_REQUEST | + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + ltq_etop_w32(val, LTQ_ETOP_MDIO); + return 0; +} + +static int +ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) +{ + u32 val = MDIO_REQUEST | MDIO_READ | + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + ltq_etop_w32(val, LTQ_ETOP_MDIO); + while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) + ; + val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; + return val; +} + +static void +ltq_etop_mdio_link(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + struct phy_device *phydev = priv->phydev; + + phy_print_status(phydev); +} + +static int +ltq_etop_mdio_probe(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; + int phy_addr; + + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (priv->mii_bus->phy_map[phy_addr]) { + phydev = priv->mii_bus->phy_map[phy_addr]; + break; + } + } + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); + return -ENODEV; + } + + phydev = phy_connect(dev, dev_name(&phydev->dev), <q_etop_mdio_link, + 0, PHY_INTERFACE_MODE_MII); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + + phydev->supported &= (SUPPORTED_10baseT_Half + | SUPPORTED_10baseT_Full + | SUPPORTED_100baseT_Half + | SUPPORTED_100baseT_Full + | SUPPORTED_Autoneg + | SUPPORTED_MII + | SUPPORTED_TP); + + phydev->advertising = phydev->supported; + priv->phydev = phydev; + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", + dev->name, phydev->drv->name, + dev_name(&phydev->dev), phydev->irq); + + return 0; +} + +static int +ltq_etop_mdio_init(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + int i; + int err; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { + netdev_err(dev, "failed to allocate mii bus\n"); + err = -ENOMEM; + goto err_out; + } + + priv->mii_bus->priv = dev; + priv->mii_bus->read = ltq_etop_mdio_rd; + priv->mii_bus->write = ltq_etop_mdio_wr; + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); + priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); + if (!priv->mii_bus->irq) { + err = -ENOMEM; + goto err_out_free_mdiobus; + } + + for (i = 0; i < PHY_MAX_ADDR; ++i) + priv->mii_bus->irq[i] = PHY_POLL; + + if (mdiobus_register(priv->mii_bus)) { + err = -ENXIO; + goto err_out_free_mdio_irq; + } + + if (ltq_etop_mdio_probe(dev)) { + err = -ENXIO; + goto err_out_unregister_bus; + } + return 0; + +err_out_unregister_bus: + mdiobus_unregister(priv->mii_bus); +err_out_free_mdio_irq: + kfree(priv->mii_bus->irq); +err_out_free_mdiobus: + mdiobus_free(priv->mii_bus); +err_out: + return err; +} + +static void +ltq_etop_mdio_cleanup(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + phy_disconnect(priv->phydev); + mdiobus_unregister(priv->mii_bus); + kfree(priv->mii_bus->irq); + mdiobus_free(priv->mii_bus); +} + +static int +ltq_etop_open(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + int ch; + + for (ch = 0; ch < MAX_DMA_CHAN; ch++) + if (priv->pldata->channel[ch]) + ltq_dma_open(&priv->dma[ch]); + netif_start_queue(dev); + return 0; +} + +static int +ltq_etop_stop(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + int ch; + + for (ch = 0; ch < MAX_DMA_CHAN; ch++) + if (priv->pldata->channel[ch]) + ltq_dma_close(&priv->dma[ch]); + netif_stop_queue(dev); + return 0; +} + +static int +ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) +{ + int ch = 1; + struct ltq_mii_priv *priv = netdev_priv(dev); + struct ltq_dma_desc *d = &priv->dma[ch].desc_base[priv->dma[ch].desc]; + int len; + unsigned long flags; + u32 byte_offset; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + dev->trans_start = jiffies; + + if ((d->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || + priv->tx_skb[ch >> 1][priv->dma[ch].desc]) { + priv->stats.tx_errors++; + priv->stats.tx_dropped++; + dev_kfree_skb_any(skb); + netdev_err(dev, "tx ring full\n"); + netif_stop_queue(dev); + return NETDEV_TX_BUSY; + } + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; + priv->tx_skb[ch >> 1][priv->dma[ch].desc] = skb; + + local_irq_save(flags); + d->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, + DMA_TO_DEVICE)) - byte_offset; + wmb(); + d->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); + local_irq_restore(flags); + + priv->dma[ch].desc++; + priv->dma[ch].desc %= LTQ_DESC_NUM; + + if (priv->dma[ch].desc_base[priv->dma[ch].desc].ctl & LTQ_DMA_OWN) + netif_stop_queue(dev); + + priv->stats.tx_packets++; + priv->stats.tx_bytes += len; + return NETDEV_TX_OK; +} + +static void +ltq_etop_tx_timeout(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + + priv->stats.tx_errors++; + netif_wake_queue(dev); +} + +static int +ltq_etop_change_mtu(struct net_device *dev, int new_mtu) +{ + int retval = eth_change_mtu(dev, new_mtu); + + if (!retval) + ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, + LTQ_ETOP_IGPLEN); + return retval; +} + +static int +ltq_etop_set_mac_address(struct net_device *dev, void *p) +{ + int retcode = eth_mac_addr(dev, p); + + if (!retcode) { + /* store the mac for the unicast filter */ + ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); + ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, + LTQ_ETOP_MAC_DA1); + } + return retcode; +} + +static void +ltq_etop_set_multicast_list(struct net_device *dev) +{ + /* ensure that the unicast filter is not enabled in promiscious mode */ + if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) + ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); + else + ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); +} + +static int +ltq_etop_init(struct net_device *dev) +{ + struct ltq_mii_priv *priv = netdev_priv(dev); + int err; + + ether_setup(dev); + dev->watchdog_timeo = 10 * HZ; + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); + err = ltq_etop_set_mac_address(dev, &priv->pldata->mac); + if (err) + goto err_netdev; + ltq_etop_set_multicast_list(dev); + err = ltq_etop_mdio_init(dev); + if (err) + goto err_netdev; + return 0; + +err_netdev: + unregister_netdev(dev); + free_netdev(dev); +err_hw: + ltq_etop_hw_exit(dev); + return err; +} + +static const struct net_device_ops ltq_eth_netdev_ops = { + .ndo_open = ltq_etop_open, + .ndo_stop = ltq_etop_stop, + .ndo_start_xmit = ltq_etop_tx, + .ndo_tx_timeout = ltq_etop_tx_timeout, + .ndo_change_mtu = ltq_etop_change_mtu, + .ndo_set_mac_address = ltq_etop_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_multicast_list = ltq_etop_set_multicast_list, + .ndo_init = ltq_etop_init, +}; + +static int __init +ltq_etop_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct ltq_mii_priv *priv; + struct resource *res; + int err; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get etop resource\n"); + err = -ENOENT; + goto err_out; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request etop resource\n"); + err = -EBUSY; + goto err_out; + } + + ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_etop_membase) { + dev_err(&pdev->dev, "failed to remap etop engine %d\n", + pdev->id); + err = -ENOMEM; + goto err_out; + } + + dev = alloc_etherdev(sizeof(struct ltq_mii_priv)); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pldata = dev_get_platdata(&pdev->dev); + + err = register_netdev(dev); + if (err) + goto err_free; + + platform_set_drvdata(pdev, dev); + return 0; + +err_free: + kfree(dev); +err_out: + return err; +} + +static int __devexit +ltq_etop_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (dev) { + netif_stop_queue(dev); + ltq_etop_hw_exit(dev); + ltq_etop_mdio_cleanup(dev); + unregister_netdev(dev); + } + return 0; +} + +static struct platform_driver ltq_mii_driver = { + .remove = __devexit_p(ltq_etop_remove), + .driver = { + .name = "ltq_etop", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_etop(void) +{ + int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); + + if (ret) + pr_err("ltq_etop: Error registering platfom driver!"); + return ret; +} + +static void __exit +exit_ltq_etop(void) +{ + platform_driver_unregister(<q_mii_driver); +} + +module_init(init_ltq_etop); +module_exit(exit_ltq_etop); + +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC ETOP"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 From ralf@linux-mips.org Tue Apr 12 18:53:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 18:53:21 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:44587 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491194Ab1DLQxS (ORCPT ); Tue, 12 Apr 2011 18:53:18 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p3CGqEGE010332; Tue, 12 Apr 2011 18:52:14 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p3CGqCSS010328; Tue, 12 Apr 2011 18:52:12 +0200 Date: Tue, 12 Apr 2011 18:52:12 +0200 From: Ralf Baechle To: John Crispin Cc: Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH V9] MIPS: lantiq: add NOR flash support Message-ID: <20110412165212.GA10118@linux-mips.org> References: <1302624601-18571-1-git-send-email-blogic@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1302624601-18571-1-git-send-email-blogic@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29741 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 12, 2011 at 06:10:01PM +0200, John Crispin wrote: Queued for 2.6.40 with the trailing whitespace fixed up as this was already pre-acked by Artem on IRC. Thanks! Ralf From mirq@rere.qmqm.pl Tue Apr 12 21:48:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 21:48:23 +0200 (CEST) Received: from rere.qmqm.pl ([89.167.52.164]:59496 "EHLO rere.qmqm.pl" rhost-flags-OK-FAIL-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491018Ab1DLTsT (ORCPT ); Tue, 12 Apr 2011 21:48:19 +0200 Received: by rere.qmqm.pl (Postfix, from userid 1000) id 3420713A65; Tue, 12 Apr 2011 21:48:17 +0200 (CEST) From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Subject: [PATCH] net: ioc3: convert to hw_features MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To: netdev@vger.kernel.org Cc: Ralf Baechle , linux-mips@linux-mips.org Message-Id: <20110412194817.3420713A65@rere.qmqm.pl> Date: Tue, 12 Apr 2011 21:48:17 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29742 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mirq-linux@rere.qmqm.pl Precedence: bulk X-list: linux-mips Signed-off-by: MichaÅ‚ MirosÅ‚aw --- drivers/net/ioc3-eth.c | 30 ++---------------------------- 1 files changed, 2 insertions(+), 28 deletions(-) diff --git a/drivers/net/ioc3-eth.c b/drivers/net/ioc3-eth.c index c8ee8d2..96c9561 100644 --- a/drivers/net/ioc3-eth.c +++ b/drivers/net/ioc3-eth.c @@ -90,8 +90,6 @@ struct ioc3_private { u32 emcr, ehar_h, ehar_l; spinlock_t ioc3_lock; struct mii_if_info mii; - unsigned long flags; -#define IOC3_FLAG_RX_CHECKSUMS 1 struct pci_dev *pdev; @@ -609,7 +607,7 @@ static inline void ioc3_rx(struct net_device *dev) goto next; } - if (likely(ip->flags & IOC3_FLAG_RX_CHECKSUMS)) + if (likely(dev->features & NETIF_F_RXCSUM)) ioc3_tcpudp_checksum(skb, w0 & ERXBUF_IPCKSUM_MASK, len); @@ -1328,6 +1326,7 @@ static int __devinit ioc3_probe(struct pci_dev *pdev, dev->watchdog_timeo = 5 * HZ; dev->netdev_ops = &ioc3_netdev_ops; dev->ethtool_ops = &ioc3_ethtool_ops; + dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM; dev->features = NETIF_F_IP_CSUM; sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1); @@ -1618,37 +1617,12 @@ static u32 ioc3_get_link(struct net_device *dev) return rc; } -static u32 ioc3_get_rx_csum(struct net_device *dev) -{ - struct ioc3_private *ip = netdev_priv(dev); - - return ip->flags & IOC3_FLAG_RX_CHECKSUMS; -} - -static int ioc3_set_rx_csum(struct net_device *dev, u32 data) -{ - struct ioc3_private *ip = netdev_priv(dev); - - spin_lock_bh(&ip->ioc3_lock); - if (data) - ip->flags |= IOC3_FLAG_RX_CHECKSUMS; - else - ip->flags &= ~IOC3_FLAG_RX_CHECKSUMS; - spin_unlock_bh(&ip->ioc3_lock); - - return 0; -} - static const struct ethtool_ops ioc3_ethtool_ops = { .get_drvinfo = ioc3_get_drvinfo, .get_settings = ioc3_get_settings, .set_settings = ioc3_set_settings, .nway_reset = ioc3_nway_reset, .get_link = ioc3_get_link, - .get_rx_csum = ioc3_get_rx_csum, - .set_rx_csum = ioc3_set_rx_csum, - .get_tx_csum = ethtool_op_get_tx_csum, - .set_tx_csum = ethtool_op_set_tx_csum }; static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -- 1.7.2.5 From davem@davemloft.net Tue Apr 12 23:53:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Apr 2011 23:53:46 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:57745 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491048Ab1DLVxm (ORCPT ); Tue, 12 Apr 2011 23:53:42 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id BC45730001; Tue, 12 Apr 2011 14:53:05 -0700 (PDT) Date: Tue, 12 Apr 2011 14:53:05 -0700 (PDT) Message-Id: <20110412.145305.179937235.davem@davemloft.net> To: mirq-linux@rere.qmqm.pl Cc: netdev@vger.kernel.org, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] net: ioc3: convert to hw_features From: David Miller In-Reply-To: <20110412194817.3420713A65@rere.qmqm.pl> References: <20110412194817.3420713A65@rere.qmqm.pl> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=euc-kr Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29743 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Micha©© Miros©©aw Date: Tue, 12 Apr 2011 21:48:17 +0200 (CEST) > Signed-off-by: Micha©© Miros©©aw Applied. From davem@davemloft.net Wed Apr 13 00:47:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Apr 2011 00:47:23 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:51022 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491085Ab1DLWrU (ORCPT ); Wed, 13 Apr 2011 00:47:20 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 9530830001; Tue, 12 Apr 2011 15:46:42 -0700 (PDT) Date: Tue, 12 Apr 2011 15:46:42 -0700 (PDT) Message-Id: <20110412.154642.200375628.davem@davemloft.net> To: blogic@openwrt.org Cc: ralf@linux-mips.org, ralph.hempel@lantiq.com, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 2/3] MIPS: lantiq: add ethernet driver From: David Miller In-Reply-To: <1302624675-18652-3-git-send-email-blogic@openwrt.org> References: <1302624675-18652-1-git-send-email-blogic@openwrt.org> <1302624675-18652-3-git-send-email-blogic@openwrt.org> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29744 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: John Crispin Date: Tue, 12 Apr 2011 18:11:14 +0200 > This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found > inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet > work. Support for all 8 dma channels, gbit and the embedded switch found on > the ar9/vr9 still needs to be implemented. > > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel This driver needs some work. > + > + skb_put(skb, len); > + skb->dev = dev; > + skb->protocol = eth_type_trans(skb, dev); > + netif_rx(skb); > + priv->stats.rx_packets++; > + priv->stats.rx_bytes += len; Please convert this driver to use NAPI for packet reception. > + local_irq_save(flags); > + priv->rx_tasklet_running = 0; > + if (priv->rx_channel_mask) { > + priv->rx_tasklet_running = 1; > + tasklet_schedule(&priv->rx_tasklet); > + } > + local_irq_restore(flags); This doesn't protect anything, use proper locking. From shemminger@vyatta.com Wed Apr 13 01:54:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Apr 2011 01:54:38 +0200 (CEST) Received: from mail.vyatta.com ([76.74.103.46]:44260 "EHLO mail.vyatta.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491194Ab1DLXye (ORCPT ); Wed, 13 Apr 2011 01:54:34 +0200 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.vyatta.com (Postfix) with ESMTP id 3FD4D18298B6; Tue, 12 Apr 2011 16:54:27 -0700 (PDT) X-Virus-Scanned: amavisd-new at tahiti.vyatta.com Received: from mail.vyatta.com ([127.0.0.1]) by localhost (mail.vyatta.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AV6FADaB47BD; Tue, 12 Apr 2011 16:54:26 -0700 (PDT) Received: from nehalam (static-50-53-80-93.bvtn.or.frontiernet.net [50.53.80.93]) by mail.vyatta.com (Postfix) with ESMTPSA id 4E0DB1829045; Tue, 12 Apr 2011 16:54:26 -0700 (PDT) Date: Tue, 12 Apr 2011 16:54:24 -0700 From: Stephen Hemminger To: John Crispin Cc: Ralf Baechle , Ralph Hempel , linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 2/3] MIPS: lantiq: add ethernet driver Message-ID: <20110412165424.0b6ba71a@nehalam> In-Reply-To: <1302624675-18652-3-git-send-email-blogic@openwrt.org> References: <1302624675-18652-1-git-send-email-blogic@openwrt.org> <1302624675-18652-3-git-send-email-blogic@openwrt.org> Organization: Vyatta X-Mailer: Claws Mail 3.7.6 (GTK+ 2.22.0; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29745 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shemminger@vyatta.com Precedence: bulk X-list: linux-mips On Tue, 12 Apr 2011 18:11:14 +0200 John Crispin wrote: > + > +struct ltq_mii_priv { > + struct ltq_eth_data *pldata; > + struct resource *res; > + struct net_device_stats stats; You don't need to have private stats structure it is part of net_device in recent kernels. In fact, since you don't set .ndo_get_stats, the driver is getting the default function which prints the values from network_device, not your priv structure. Also, please consider adding basic ethtool support to show speed/duplex and driver information. -- From juhosg@openwrt.org Wed Apr 13 10:54:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Apr 2011 10:54:40 +0200 (CEST) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:60089 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491102Ab1DMIyg (ORCPT ); Wed, 13 Apr 2011 10:54:36 +0200 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 75D5F14014E; Wed, 13 Apr 2011 10:54:31 +0200 (CEST) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id EB13B140152; Wed, 13 Apr 2011 10:54:30 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos , Imre Kaloz , Greg Kroah-Hartman , Alan Stern , linux-usb@vger.kernel.org Subject: [PATCH v2 1/3] USB: ehci: add bus glue for the Atheros AR71XX/AR724X/AR91XX SoCs Date: Wed, 13 Apr 2011 10:54:22 +0200 Message-Id: <1302684864-12484-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 X-VBMS: A11A1E22549 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29746 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The Atheros AR71XX/AR91XX SoCs have a built-in EHCI controller. This patch adds the necessary glue code to make the generic EHCI driver usable for them. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org --- Changes since v1: * remove XXX from the subject line because: host vger.kernel.org[209.132.180.67] said: 550 5.7.1 Content-Policy reject msg: The capital Triple-X in subject is way too often associated with junk email, please rephrase. * fix a typo in the prompt of USB_EHCI_ATH79 * use (SOC_AR71XX || SOC_AR724X || SOC_AR913X) as a dependency instead of ATH79 * add 'default y' arch/mips/ath79/Kconfig | 3 + drivers/usb/host/Kconfig | 9 ++ drivers/usb/host/ehci-ath79.c | 200 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + 4 files changed, 217 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-ath79.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index b058282..649a2a3 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -26,12 +26,15 @@ config ATH79_MACH_PB44 endmenu config SOC_AR71XX + select USB_ARCH_HAS_EHCI def_bool n config SOC_AR724X + select USB_ARCH_HAS_EHCI def_bool n config SOC_AR913X + select USB_ARCH_HAS_EHCI def_bool n config ATH79_DEV_AR913X_WMAC diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 9483acd..bcfe42c 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -202,6 +202,15 @@ config USB_CNS3XXX_EHCI It is needed for high-speed (480Mbit/sec) USB 2.0 device support. +config USB_EHCI_ATH79 + bool "EHCI support for AR7XXX/AR9XXX SoCs" + depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X) + select USB_EHCI_ROOT_HUB_TT + default y + ---help--- + Enables support for the built-in EHCI controller present + on the Atheros AR7XXX/AR9XXX SoCs. + config USB_OXU210HP_HCD tristate "OXU210HP HCD support" depends on USB diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c new file mode 100644 index 0000000..74325b8 --- /dev/null +++ b/drivers/usb/host/ehci-ath79.c @@ -0,0 +1,200 @@ +/* + * Bus Glue for Atheros AR7XXX/AR9XXX built-in EHCI controller. + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * Copyright (C) 2007 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +enum { + EHCI_ATH79_IP_V1 = 0, + EHCI_ATH79_IP_V2, +}; + +static const struct platform_device_id ehci_ath79_id_table[] = { + { + .name = "ar71xx-ehci", + .driver_data = EHCI_ATH79_IP_V1, + }, + { + .name = "ar724x-ehci", + .driver_data = EHCI_ATH79_IP_V2, + }, + { + .name = "ar913x-ehci", + .driver_data = EHCI_ATH79_IP_V2, + }, + { + /* terminating entry */ + }, +}; + +MODULE_DEVICE_TABLE(platform, ehci_ath79_id_table); + +static int ehci_ath79_init(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct platform_device *pdev = to_platform_device(hcd->self.controller); + const struct platform_device_id *id; + int ret; + + id = platform_get_device_id(pdev); + if (!id) { + dev_err(hcd->self.controller, "missing device id\n"); + return -EINVAL; + } + + switch (id->driver_data) { + case EHCI_ATH79_IP_V1: + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + break; + + case EHCI_ATH79_IP_V2: + hcd->has_tt = 1; + + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + break; + + default: + BUG(); + } + + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + ehci->sbrn = 0x20; + + ehci_reset(ehci); + + ret = ehci_init(hcd); + if (ret) + return ret; + + ehci_port_power(ehci, 0); + + return 0; +} + +static const struct hc_driver ehci_ath79_hc_driver = { + .description = hcd_name, + .product_desc = "Atheros built-in EHCI controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + .reset = ehci_ath79_init, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_ath79_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_dbg(&pdev->dev, "no IRQ specified\n"); + return -ENODEV; + } + irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "no base address specified\n"); + return -ENODEV; + } + + hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (ret) + goto err_iounmap; + + return 0; + +err_iounmap: + iounmap(hcd->regs); + +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_ath79_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static struct platform_driver ehci_ath79_driver = { + .probe = ehci_ath79_probe, + .remove = ehci_ath79_remove, + .id_table = ehci_ath79_id_table, + .driver = { + .owner = THIS_MODULE, + .name = "ath79-ehci", + } +}; + +MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ehci"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 78561d1..a29527d 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1265,6 +1265,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER tegra_ehci_driver #endif +#ifdef CONFIG_USB_EHCI_ATH79 +#include "ehci-ath79.c" +#define PLATFORM_DRIVER ehci_ath79_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) -- 1.7.2.1 From juhosg@openwrt.org Wed Apr 13 10:54:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Apr 2011 10:55:05 +0200 (CEST) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:60096 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491104Ab1DMIyg (ORCPT ); Wed, 13 Apr 2011 10:54:36 +0200 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id C2E5D14014B; Wed, 13 Apr 2011 10:54:31 +0200 (CEST) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 4EC3A140119; Wed, 13 Apr 2011 10:54:31 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos , Imre Kaloz , Greg Kroah-Hartman , Alan Stern , linux-usb@vger.kernel.org Subject: [PATCH v2 3/3] USB: ohci: add bus glue for the Atheros AR71XX/AR7240 SoCs Date: Wed, 13 Apr 2011 10:54:24 +0200 Message-Id: <1302684864-12484-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1302684864-12484-1-git-send-email-juhosg@openwrt.org> References: <1302684864-12484-1-git-send-email-juhosg@openwrt.org> X-VBMS: A11A2979CDE | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29747 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The Atheros AR71XX/AR7240 SoCs have a built-in OHCI controller. This patch adds the necessary glue code to make the generic OHCI driver usable for them. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org --- Changes since v1: --- arch/mips/ath79/Kconfig | 2 + drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/ohci-ath79.c | 151 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 5 ++ 4 files changed, 166 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ohci-ath79.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 649a2a3..4770741 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -27,10 +27,12 @@ endmenu config SOC_AR71XX select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI def_bool n config SOC_AR724X select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI def_bool n config SOC_AR913X diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index bcfe42c..b95cbcc 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -296,6 +296,14 @@ config USB_OHCI_HCD_OMAP3 Enables support for the on-chip OHCI controller on OMAP3 and later chips. +config USB_OHCI_ATH79 + bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs" + depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) + default y + help + Enables support for the built-in OHCI controller present on the + Atheros AR71XX/AR7240 SoCs. + config USB_OHCI_HCD_PPC_SOC bool "OHCI support for on-chip PPC USB controller" depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) diff --git a/drivers/usb/host/ohci-ath79.c b/drivers/usb/host/ohci-ath79.c new file mode 100644 index 0000000..ffea3e7 --- /dev/null +++ b/drivers/usb/host/ohci-ath79.c @@ -0,0 +1,151 @@ +/* + * OHCI HCD (Host Controller Driver) for USB. + * + * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * Copyright (C) 2007 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +static int __devinit ohci_ath79_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int ret; + + ret = ohci_init(ohci); + if (ret < 0) + return ret; + + ret = ohci_run(ohci); + if (ret < 0) + goto err; + + return 0; + +err: + ohci_stop(hcd); + return ret; +} + +static const struct hc_driver ohci_ath79_hc_driver = { + .description = hcd_name, + .product_desc = "Atheros built-in OHCI controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + + .irq = ohci_irq, + .flags = HCD_USB11 | HCD_MEMORY, + + .start = ohci_ath79_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ohci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, + .start_port_reset = ohci_start_port_reset, +}; + +static int ohci_ath79_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_dbg(&pdev->dev, "no IRQ specified\n"); + return -ENODEV; + } + irq = res->start; + + hcd = usb_create_hcd(&ohci_ath79_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "no base address specified\n"); + ret = -ENODEV; + goto err_put_hcd; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ohci_hcd_init(hcd_to_ohci(hcd)); + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); + if (ret) + goto err_stop_hcd; + + return 0; + +err_stop_hcd: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +static int ohci_ath79_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static struct platform_driver ohci_hcd_ath79_driver = { + .probe = ohci_ath79_probe, + .remove = ohci_ath79_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ath79-ohci", + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ohci"); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index e728863..8aec65f 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1105,6 +1105,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver #endif +#ifdef CONFIG_USB_OHCI_ATH79 +#include "ohci-ath79.c" +#define PLATFORM_DRIVER ohci_hcd_ath79_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ -- 1.7.2.1 From juhosg@openwrt.org Wed Apr 13 10:55:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Apr 2011 10:55:28 +0200 (CEST) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:60092 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491106Ab1DMIyg (ORCPT ); Wed, 13 Apr 2011 10:54:36 +0200 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id A8873140151; Wed, 13 Apr 2011 10:54:31 +0200 (CEST) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 26334140119; Wed, 13 Apr 2011 10:54:31 +0200 (CEST) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Gabor Juhos , Greg Kroah-Hartman , Alan Stern , linux-usb@vger.kernel.org Subject: [PATCH v2 2/3] USB: ehci: add workaround for Synopsys HC bug Date: Wed, 13 Apr 2011 10:54:23 +0200 Message-Id: <1302684864-12484-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1302684864-12484-1-git-send-email-juhosg@openwrt.org> References: <1302684864-12484-1-git-send-email-juhosg@openwrt.org> X-VBMS: A11A244AF47 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29748 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips A Synopsys USB core used in various SoCs has a bug which might cause that the host controller not issuing ping. When software uses the Doorbell mechanism to remove queue heads, the host controller still has references to the removed queue head even after indicating an Interrupt on Async Advance. This happens if the last executed queue head's Next Link queue head is removed. Consequences of the defect: The Host controller fetches the removed queue head, using memory that would otherwise be deallocated.This results in incorrect transactions on both the USB and system memory. This may result in undefined behavior. Workarounds: 1) If no queue head is active (no Status field's Active bit is set) after removing the queue heads, the software can write one of the valid queue head addresses to the ASYNCLISTADDR register and deallocate the removed queue head's memory after 2 microframes. If one or more of the queue heads is active (the Active bit is set in the Status field) after removing the queue heads, the software can delay memory deallocation after time X, where X is the time required for the Host Controller to go through all the queue heads once. X varies with the number of queue heads and the time required to process periodic transactions: if more periodic transactions must be performed, the Host Controller has less time to process asynchronous transaction processing. 2) Do not use the Doorbell mechanism to remove the queue heads. Disable the Asynchronous Schedule Enable bit instead. The bug has been discussed on the linux-usb-devel mailing-list four years ago, the original thread can be found here: http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg45345.html This patch implements the first workaround as suggested by David Brownell. The built-in USB host controller of the Atheros AR7130/AR7141/AR7161 SoCs requires this to work properly. Signed-off-by: Gabor Juhos Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org --- Changes since v1: * use ehci_writel instead of writel drivers/usb/host/ehci-ath79.c | 2 ++ drivers/usb/host/ehci-q.c | 4 ++++ drivers/usb/host/ehci.h | 1 + 3 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c index 74325b8..7ea23b5 100644 --- a/drivers/usb/host/ehci-ath79.c +++ b/drivers/usb/host/ehci-ath79.c @@ -54,6 +54,8 @@ static int ehci_ath79_init(struct usb_hcd *hcd) switch (id->driver_data) { case EHCI_ATH79_IP_V1: + ehci->has_synopsys_hc_bug = 1; + ehci->caps = hcd->regs; ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c index 98ded66..6582aea 100644 --- a/drivers/usb/host/ehci-q.c +++ b/drivers/usb/host/ehci-q.c @@ -1183,6 +1183,10 @@ static void end_unlink_async (struct ehci_hcd *ehci) ehci->reclaim = NULL; start_unlink_async (ehci, next); } + + if (ehci->has_synopsys_hc_bug) + ehci_writel(ehci, (u32) ehci->async->qh_dma, + &ehci->regs->async_next); } /* makes sure the async qh will become idle */ diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index f86d3fa..28ef8ca 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -134,6 +134,7 @@ struct ehci_hcd { /* one per controller */ unsigned amd_pll_fix:1; unsigned fs_i_thresh:1; /* Intel iso scheduling */ unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ + unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ /* required for usb32 quirk */ #define OHCI_CTRL_HCFS (3 << 6) -- 1.7.2.1 From stern+4dbee946@rowland.harvard.edu Wed Apr 13 17:08:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Apr 2011 17:08:29 +0200 (CEST) Received: from iolanthe.rowland.org ([192.131.102.54]:36330 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491765Ab1DMPIZ (ORCPT ); Wed, 13 Apr 2011 17:08:25 +0200 Received: (qmail 2729 invoked by uid 2102); 13 Apr 2011 11:08:21 -0400 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 13 Apr 2011 11:08:21 -0400 Date: Wed, 13 Apr 2011 11:08:21 -0400 (EDT) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Gabor Juhos cc: Ralf Baechle , , Greg Kroah-Hartman , Subject: Re: [PATCH v2 2/3] USB: ehci: add workaround for Synopsys HC bug In-Reply-To: <1302684864-12484-2-git-send-email-juhosg@openwrt.org> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29749 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips On Wed, 13 Apr 2011, Gabor Juhos wrote: > A Synopsys USB core used in various SoCs has a bug which might cause > that the host controller not issuing ping. > > When software uses the Doorbell mechanism to remove queue heads, the > host controller still has references to the removed queue head even > after indicating an Interrupt on Async Advance. This happens if the last > executed queue head's Next Link queue head is removed. > > Consequences of the defect: > The Host controller fetches the removed queue head, using memory that > would otherwise be deallocated.This results in incorrect transactions on > both the USB and system memory. This may result in undefined behavior. > > Workarounds: > > 1) If no queue head is active (no Status field's Active bit is set) > after removing the queue heads, the software can write one of the valid > queue head addresses to the ASYNCLISTADDR register and deallocate the > removed queue head's memory after 2 microframes. > > If one or more of the queue heads is active (the Active bit is set in > the Status field) after removing the queue heads, the software can delay > memory deallocation after time X, where X is the time required for the > Host Controller to go through all the queue heads once. X varies with > the number of queue heads and the time required to process periodic > transactions: if more periodic transactions must be performed, the Host > Controller has less time to process asynchronous transaction processing. > > 2) Do not use the Doorbell mechanism to remove the queue heads. Disable > the Asynchronous Schedule Enable bit instead. > > The bug has been discussed on the linux-usb-devel mailing-list > four years ago, the original thread can be found here: > http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg45345.html > > This patch implements the first workaround as suggested by David Brownell. > > The built-in USB host controller of the Atheros AR7130/AR7141/AR7161 SoCs > requires this to work properly. > > Signed-off-by: Gabor Juhos > Cc: Greg Kroah-Hartman > Cc: Alan Stern > Cc: linux-usb@vger.kernel.org Acked-by: Alan Stern From pjohn@mvista.com Wed Apr 13 18:08:12 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Apr 2011 18:08:17 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:41953 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491170Ab1DMQIM (ORCPT ); Wed, 13 Apr 2011 18:08:12 +0200 Received: by iwn36 with SMTP id 36so848302iwn.36 for ; Wed, 13 Apr 2011 09:08:06 -0700 (PDT) Received: by 10.231.65.209 with SMTP id k17mr7966536ibi.127.1302710794226; Wed, 13 Apr 2011 09:06:34 -0700 (PDT) Received: from [10.162.22.222] ([115.119.134.194]) by mx.google.com with ESMTPS id d9sm522117ibb.36.2011.04.13.09.06.30 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 13 Apr 2011 09:06:32 -0700 (PDT) Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section From: philby john To: linux-mips@linux-mips.org Cc: David Daney Content-Type: text/plain; charset="UTF-8" Date: Wed, 13 Apr 2011 21:37:13 +0530 Message-ID: <1302710833.14458.1.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.32.1 (2.32.1-1.fc14) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29750 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk X-list: linux-mips From: Philby John Date: Wed, 13 Apr 2011 20:46:32 +0530 Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section Some early Octeon bootloaders cannot process PT_NOTE program headers as reported in numerous sections of the web, here is an example http://www.spinics.net/lists/mips/msg37799.html Loading usually fails with such an error ... Error allocating memory for elf image! The work around usually is to strip the .notes section by using such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux It is expected that the vmlinux image got after compilation be bootable. Add a Kconfig option to ignore the PT_NOTE section. Signed-off-by: Philby John --- arch/mips/cavium-octeon/Kconfig | 8 ++++++++ arch/mips/kernel/vmlinux.lds.S | 6 ++++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index caae228..ddecee3 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -90,6 +90,14 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY help Lock the kernel's implementation of memcpy() into L2. +config DISABLE_ELF_NOTE_HEADER + bool "Disable the creation of the ELF PT_NOTE program header in vmlinux" + depends on CPU_CAVIUM_OCTEON + help + Some early Octeon bootloaders cannot process PT_NOTE program + headers. Select y to omit these headers so that the kernel + can be loaded with older bootloaders. + config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 832afbb..0536910 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -8,7 +8,9 @@ OUTPUT_ARCH(mips) ENTRY(kernel_entry) PHDRS { text PT_LOAD FLAGS(7); /* RWX */ +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER note PT_NOTE FLAGS(4); /* R__ */ +#endif } #ifdef CONFIG_32BIT @@ -62,7 +64,11 @@ SECTIONS __stop___dbe_table = .; } +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER NOTES :text :note +#else + NOTES :text +#endif .dummy : { *(.dummy) } :text RODATA -- 1.7.4 From David.Daney@caviumnetworks.com Wed Apr 13 19:38:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Apr 2011 19:38:10 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1476 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491772Ab1DMRiG (ORCPT ); Wed, 13 Apr 2011 19:38:06 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 13 Apr 2011 10:39:02 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 13 Apr 2011 10:38:03 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 13 Apr 2011 10:38:02 -0700 Message-ID: <4DA5DF7A.1030207@caviumnetworks.com> Date: Wed, 13 Apr 2011 10:38:02 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: philby john CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section References: <1302710833.14458.1.camel@localhost.localdomain> In-Reply-To: <1302710833.14458.1.camel@localhost.localdomain> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 13 Apr 2011 17:38:02.0981 (UTC) FILETIME=[8A256950:01CBFA01] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29751 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/13/2011 09:07 AM, philby john wrote: > From: Philby John ^^^^^^^^ I believe that statement to be not entirely correct. Perhaps you should change it to something like: From: David Daney > Date: Wed, 13 Apr 2011 20:46:32 +0530 > Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section > > Some early Octeon bootloaders cannot process PT_NOTE program > headers as reported in numerous sections of the web, here is > an example http://www.spinics.net/lists/mips/msg37799.html > Loading usually fails with such an error ... > Error allocating memory for elf image! > > The work around usually is to strip the .notes section by using > such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux > It is expected that the vmlinux image got after compilation be > bootable. Add a Kconfig option to ignore the PT_NOTE section. > > Signed-off-by: Philby John > --- From ralf@linux-mips.org Thu Apr 14 01:24:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Apr 2011 01:24:29 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:45814 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491872Ab1DMXY0 (ORCPT ); Thu, 14 Apr 2011 01:24:26 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p3DNNA4H001690; Thu, 14 Apr 2011 01:23:10 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p3DNN8kA001684; Thu, 14 Apr 2011 01:23:08 +0200 Date: Thu, 14 Apr 2011 01:23:08 +0200 From: Ralf Baechle To: Greg Kroah-Hartman , linux-usb@vger.kernel.org Cc: Manuel Lauss , linux-mips@linux-mips.org Subject: [PATCH] USB: OHCI: Fix build warning on Alchemy Message-ID: <20110413232308.GA22925@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29752 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips CC drivers/usb/host/ohci-hcd.o In file included from drivers/usb/host/ohci-hcd.c:1028:0: drivers/usb/host/ohci-au1xxx.c:36:7: warning: "__BIG_ENDIAN" is not defined [-Wundef] Fix the warning and some other build bullet proofing; let's not rely on other needed header files getting dragged in magically. Signed-off-by: Ralf Baechle --- drivers/usb/host/ohci-au1xxx.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 17a6043..0723990 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -19,7 +19,10 @@ */ #include -#include +#include +#include +#include +#include #include @@ -33,7 +36,7 @@ #ifdef __LITTLE_ENDIAN #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) -#elif __BIG_ENDIAN +#elif defined(__BIG_ENDIAN) #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \ USBH_ENABLE_BE) #else From gregkh@suse.de Thu Apr 14 01:44:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Apr 2011 01:44:59 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:47924 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491824Ab1DMXox (ORCPT ); Thu, 14 Apr 2011 01:44:53 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) by mx2.suse.de (Postfix) with ESMTP id 3E8EC86A2E; Thu, 14 Apr 2011 01:44:51 +0200 (CEST) Date: Wed, 13 Apr 2011 16:43:17 -0700 From: Greg KH To: Ralf Baechle Cc: linux-usb@vger.kernel.org, Manuel Lauss , linux-mips@linux-mips.org Subject: Re: [PATCH] USB: OHCI: Fix build warning on Alchemy Message-ID: <20110413234317.GB17342@suse.de> References: <20110413232308.GA22925@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110413232308.GA22925@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29753 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips On Thu, Apr 14, 2011 at 01:23:08AM +0200, Ralf Baechle wrote: > CC drivers/usb/host/ohci-hcd.o > In file included from drivers/usb/host/ohci-hcd.c:1028:0: > drivers/usb/host/ohci-au1xxx.c:36:7: warning: "__BIG_ENDIAN" is not defined [-Wundef] > > Fix the warning and some other build bullet proofing; let's not rely on > other needed header files getting dragged in magically. Ick, I just applied the second part of this patch to my "for-linus" tree as a patch from someone else. Are the #include changes really needed right now? thanks, greg k-h From ralf@linux-mips.org Thu Apr 14 02:32:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Apr 2011 02:32:45 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:41180 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491912Ab1DNAcl (ORCPT ); Thu, 14 Apr 2011 02:32:41 +0200 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p3E0VPa9009976; Thu, 14 Apr 2011 02:31:25 +0200 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p3E0VOTL009971; Thu, 14 Apr 2011 02:31:24 +0200 Date: Thu, 14 Apr 2011 02:31:24 +0200 From: Ralf Baechle To: Greg KH Cc: linux-usb@vger.kernel.org, Manuel Lauss , linux-mips@linux-mips.org Subject: Re: [PATCH] USB: OHCI: Fix build warning on Alchemy Message-ID: <20110414003124.GA9660@linux-mips.org> References: <20110413232308.GA22925@linux-mips.org> <20110413234317.GB17342@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110413234317.GB17342@suse.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29754 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 13, 2011 at 04:43:17PM -0700, Greg KH wrote: > On Thu, Apr 14, 2011 at 01:23:08AM +0200, Ralf Baechle wrote: > > CC drivers/usb/host/ohci-hcd.o > > In file included from drivers/usb/host/ohci-hcd.c:1028:0: > > drivers/usb/host/ohci-au1xxx.c:36:7: warning: "__BIG_ENDIAN" is not defined [-Wundef] > > > > Fix the warning and some other build bullet proofing; let's not rely on > > other needed header files getting dragged in magically. > > Ick, I just applied the second part of this patch to my "for-linus" > tree as a patch from someone else. Are the #include changes really > needed right now? No, the include stuff was more for paranoia. However the warning fixed by the 2nd part of the patch exists back to at least 2.6.27. Ralf From gregkh@suse.de Thu Apr 14 04:24:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Apr 2011 04:24:49 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:50747 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490969Ab1DNCYp (ORCPT ); Thu, 14 Apr 2011 04:24:45 +0200 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) by mx2.suse.de (Postfix) with ESMTP id 7585D867E2; Thu, 14 Apr 2011 04:24:45 +0200 (CEST) Date: Wed, 13 Apr 2011 19:16:56 -0700 From: Greg KH To: Ralf Baechle Cc: linux-usb@vger.kernel.org, Manuel Lauss , linux-mips@linux-mips.org Subject: Re: [PATCH] USB: OHCI: Fix build warning on Alchemy Message-ID: <20110414021656.GB13169@suse.de> References: <20110413232308.GA22925@linux-mips.org> <20110413234317.GB17342@suse.de> <20110414003124.GA9660@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110414003124.GA9660@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29755 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips On Thu, Apr 14, 2011 at 02:31:24AM +0200, Ralf Baechle wrote: > On Wed, Apr 13, 2011 at 04:43:17PM -0700, Greg KH wrote: > > > On Thu, Apr 14, 2011 at 01:23:08AM +0200, Ralf Baechle wrote: > > > CC drivers/usb/host/ohci-hcd.o > > > In file included from drivers/usb/host/ohci-hcd.c:1028:0: > > > drivers/usb/host/ohci-au1xxx.c:36:7: warning: "__BIG_ENDIAN" is not defined [-Wundef] > > > > > > Fix the warning and some other build bullet proofing; let's not rely on > > > other needed header files getting dragged in magically. > > > > Ick, I just applied the second part of this patch to my "for-linus" > > tree as a patch from someone else. Are the #include changes really > > needed right now? > > No, the include stuff was more for paranoia. > > However the warning fixed by the 2nd part of the patch exists back to > at least 2.6.27. Ah, it's not that much of a rush then :) thanks, greg k-h From pjohn@mvista.com Thu Apr 14 19:54:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Apr 2011 19:54:14 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:60564 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491755Ab1DNRyI (ORCPT ); Thu, 14 Apr 2011 19:54:08 +0200 Received: by pzk5 with SMTP id 5so720445pzk.36 for ; Thu, 14 Apr 2011 10:54:01 -0700 (PDT) Received: by 10.68.71.133 with SMTP id v5mr659776pbu.487.1302803641376; Thu, 14 Apr 2011 10:54:01 -0700 (PDT) Received: from [10.0.0.3] ([122.172.162.249]) by mx.google.com with ESMTPS id 25sm2582803wfb.10.2011.04.14.10.53.58 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 14 Apr 2011 10:53:59 -0700 (PDT) Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section From: philby john To: David Daney Cc: linux-mips@linux-mips.org In-Reply-To: <4DA5DF7A.1030207@caviumnetworks.com> References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Date: Thu, 14 Apr 2011 23:24:45 +0530 Message-ID: <1302803685.3322.2.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.32.1 (2.32.1-1.fc14) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29756 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk X-list: linux-mips On Wed, 2011-04-13 at 10:38 -0700, David Daney wrote: > On 04/13/2011 09:07 AM, philby john wrote: > > From: Philby John > > ^^^^^^^^ I believe that statement to be not entirely correct. To be honest, we had a xyz customer report this issue with a patch that had no original author sign-off. Good to know its origin. Another shot with correct attributions follows in a second. Regards, Philby > > Perhaps you should change it to something like: > From: David Daney > > > > Date: Wed, 13 Apr 2011 20:46:32 +0530 > > Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section > > > > Some early Octeon bootloaders cannot process PT_NOTE program > > headers as reported in numerous sections of the web, here is > > an example http://www.spinics.net/lists/mips/msg37799.html > > Loading usually fails with such an error ... > > Error allocating memory for elf image! > > > > The work around usually is to strip the .notes section by using > > such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux > > It is expected that the vmlinux image got after compilation be > > bootable. Add a Kconfig option to ignore the PT_NOTE section. > > > > Signed-off-by: Philby John > > --- From pjohn@mvista.com Thu Apr 14 19:56:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Apr 2011 19:56:12 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:34990 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491768Ab1DNR4F (ORCPT ); Thu, 14 Apr 2011 19:56:05 +0200 Received: by iyb39 with SMTP id 39so1999294iyb.36 for ; Thu, 14 Apr 2011 10:55:59 -0700 (PDT) Received: by 10.43.54.9 with SMTP id vs9mr1585040icb.5.1302803758910; Thu, 14 Apr 2011 10:55:58 -0700 (PDT) Received: from [10.0.0.3] ([122.172.162.249]) by mx.google.com with ESMTPS id d9sm1330705ibb.53.2011.04.14.10.55.56 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 14 Apr 2011 10:55:58 -0700 (PDT) Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section From: philby john To: linux-mips@linux-mips.org Cc: David Daney In-Reply-To: <4DA5DF7A.1030207@caviumnetworks.com> References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Date: Thu, 14 Apr 2011 23:26:55 +0530 Message-ID: <1302803815.3322.4.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.32.1 (2.32.1-1.fc14) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29757 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk X-list: linux-mips From: David Daney Date: Wed, 13 Apr 2011 20:46:32 +0530 Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section Some early Octeon bootloaders cannot process PT_NOTE program headers as reported in numerous sections of the web, here is an example http://www.spinics.net/lists/mips/msg37799.html Loading usually fails with such an error ... Error allocating memory for elf image! The work around usually is to strip the .notes section by using such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux It is expected that the vmlinux image got after compilation be bootable. Add a Kconfig option to ignore the PT_NOTE section. Signed-off-by: David Daney Signed-off-by: Philby John --- arch/mips/cavium-octeon/Kconfig | 8 ++++++++ arch/mips/kernel/vmlinux.lds.S | 6 ++++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index caae228..ddecee3 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -90,6 +90,14 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY help Lock the kernel's implementation of memcpy() into L2. +config DISABLE_ELF_NOTE_HEADER + bool "Disable the creation of the ELF PT_NOTE program header in vmlinux" + depends on CPU_CAVIUM_OCTEON + help + Some early Octeon bootloaders cannot process PT_NOTE program + headers. Select y to omit these headers so that the kernel + can be loaded with older bootloaders. + config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 832afbb..0536910 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -8,7 +8,9 @@ OUTPUT_ARCH(mips) ENTRY(kernel_entry) PHDRS { text PT_LOAD FLAGS(7); /* RWX */ +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER note PT_NOTE FLAGS(4); /* R__ */ +#endif } #ifdef CONFIG_32BIT @@ -62,7 +64,11 @@ SECTIONS __stop___dbe_table = .; } +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER NOTES :text :note +#else + NOTES :text +#endif .dummy : { *(.dummy) } :text RODATA -- 1.7.4 From pjohn@mvista.com Thu Apr 14 21:41:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Apr 2011 21:41:05 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:41877 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491768Ab1DNTlC (ORCPT ); Thu, 14 Apr 2011 21:41:02 +0200 Received: by iyb39 with SMTP id 39so2081203iyb.36 for ; Thu, 14 Apr 2011 12:40:54 -0700 (PDT) Received: by 10.42.150.8 with SMTP id y8mr1602952icv.471.1302810054719; Thu, 14 Apr 2011 12:40:54 -0700 (PDT) Received: from localhost.localdomain ([122.172.162.249]) by mx.google.com with ESMTPS id c1sm1388286ibe.0.2011.04.14.12.40.52 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 14 Apr 2011 12:40:53 -0700 (PDT) Message-ID: <4DA74DFE.7030905@mvista.com> Date: Fri, 15 Apr 2011 01:11:50 +0530 From: Philby John User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101209 Fedora/3.1.7-0.35.b3pre.fc14 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: linux-mips@linux-mips.org CC: David Daney Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> <1302803815.3322.4.camel@localhost.localdomain> In-Reply-To: <1302803815.3322.4.camel@localhost.localdomain> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29758 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk X-list: linux-mips Another finding to be noted about this approach is that, booting works fine with just these lines of code +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER NOTES :text :note +#else + NOTES :text +#endif And IMHO we should be just using this, which is what you get if one were to use the command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux So with just the above lines of code or with the strip command above readelf shows this output Elf file type is EXEC (Executable file) Entry point 0xffffffff81105d10 There are 2 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000010000 0xffffffff81100000 0xffffffff81100000 0x000000000098be00 0x0000000000a00000 RWE 10000 NOTE 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 R 8 Section to Segment mapping: Segment Sections... 00 .text __ex_table .notes .rodata .pci_fixup __ksymtab __ksymtab_gpl __ksymtab_strings __init_rodata __param .data .init.text .init.data .exit.text .data.percpu .bss .bss.superpage_aligned 01 Where as if one were to remove the PT_NOTE section readelf would show ... Elf file type is EXEC (Executable file) Entry point 0xffffffff81105d10 There are 1 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000010000 0xffffffff81100000 0xffffffff81100000 0x000000000098be00 0x0000000000a00000 RWE 10000 Section to Segment mapping: Segment Sections... 00 .text __ex_table .notes .rodata .pci_fixup __ksymtab __ksymtab_gpl __ksymtab_strings __init_rodata __param .data .init.text .init.data .exit.text .data.percpu .bss .bss.superpage_aligned Shouldn't we just follow what strip does? Regards, Philby On 04/14/2011 11:26 PM, philby john wrote: > From: David Daney > Date: Wed, 13 Apr 2011 20:46:32 +0530 > Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section > > Some early Octeon bootloaders cannot process PT_NOTE program > headers as reported in numerous sections of the web, here is > an example http://www.spinics.net/lists/mips/msg37799.html > Loading usually fails with such an error ... > Error allocating memory for elf image! > > The work around usually is to strip the .notes section by using > such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux > It is expected that the vmlinux image got after compilation be > bootable. Add a Kconfig option to ignore the PT_NOTE section. > > Signed-off-by: David Daney > Signed-off-by: Philby John > --- > arch/mips/cavium-octeon/Kconfig | 8 ++++++++ > arch/mips/kernel/vmlinux.lds.S | 6 ++++++ > 2 files changed, 14 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig > index caae228..ddecee3 100644 > --- a/arch/mips/cavium-octeon/Kconfig > +++ b/arch/mips/cavium-octeon/Kconfig > @@ -90,6 +90,14 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY > help > Lock the kernel's implementation of memcpy() into L2. > > +config DISABLE_ELF_NOTE_HEADER > + bool "Disable the creation of the ELF PT_NOTE program header in vmlinux" > + depends on CPU_CAVIUM_OCTEON > + help > + Some early Octeon bootloaders cannot process PT_NOTE program > + headers. Select y to omit these headers so that the kernel > + can be loaded with older bootloaders. > + > config ARCH_SPARSEMEM_ENABLE > def_bool y > select SPARSEMEM_STATIC > diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S > index 832afbb..0536910 100644 > --- a/arch/mips/kernel/vmlinux.lds.S > +++ b/arch/mips/kernel/vmlinux.lds.S > @@ -8,7 +8,9 @@ OUTPUT_ARCH(mips) > ENTRY(kernel_entry) > PHDRS { > text PT_LOAD FLAGS(7); /* RWX */ > +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER > note PT_NOTE FLAGS(4); /* R__ */ > +#endif > } > > #ifdef CONFIG_32BIT > @@ -62,7 +64,11 @@ SECTIONS > __stop___dbe_table = .; > } > > +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER > NOTES :text :note > +#else > + NOTES :text > +#endif > .dummy : { *(.dummy) } :text > > RODATA From David.Daney@caviumnetworks.com Thu Apr 14 22:02:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Apr 2011 22:02:36 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:6067 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491768Ab1DNUCc (ORCPT ); Thu, 14 Apr 2011 22:02:32 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 14 Apr 2011 13:03:27 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 14 Apr 2011 13:02:28 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 14 Apr 2011 13:02:28 -0700 Message-ID: <4DA752CE.3010009@caviumnetworks.com> Date: Thu, 14 Apr 2011 13:02:22 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Philby John CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> <1302803815.3322.4.camel@localhost.localdomain> <4DA74DFE.7030905@mvista.com> In-Reply-To: <4DA74DFE.7030905@mvista.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 14 Apr 2011 20:02:28.0152 (UTC) FILETIME=[E1675380:01CBFADE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29759 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/14/2011 12:41 PM, Philby John wrote: > Another finding to be noted about this approach is that, booting works > fine with just these lines of code > > +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER > NOTES :text :note > +#else > + NOTES :text > +#endif > > And IMHO we should be just using this, which is what you get if one were > to use the command > $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux > > So with just the above lines of code or with the strip command above > readelf shows this output > > Elf file type is EXEC (Executable file) > Entry point 0xffffffff81105d10 > There are 2 program headers, starting at offset 64 > > Program Headers: > Type Offset VirtAddr PhysAddr > FileSiz MemSiz Flags Align > LOAD 0x0000000000010000 0xffffffff81100000 0xffffffff81100000 > 0x000000000098be00 0x0000000000a00000 RWE 10000 > NOTE 0x0000000000000000 0x0000000000000000 0x0000000000000000 > 0x0000000000000000 0x0000000000000000 R 8 > Can someone with a defective bootloader verify that a zero size PT_NOTE header is as good as *no* PT_NOTE header? If so, we should just omit the patch all together and tell people who are interested to use the strip command instead. David Daney > Section to Segment mapping: > Segment Sections... > 00 .text __ex_table .notes .rodata .pci_fixup __ksymtab > __ksymtab_gpl __ksymtab_strings __init_rodata __param .data .init.text > .init.data .exit.text .data.percpu .bss .bss.superpage_aligned > 01 > > Where as if one were to remove the PT_NOTE section readelf would show ... > > Elf file type is EXEC (Executable file) > Entry point 0xffffffff81105d10 > There are 1 program headers, starting at offset 64 > > Program Headers: > Type Offset VirtAddr PhysAddr > FileSiz MemSiz Flags Align > LOAD 0x0000000000010000 0xffffffff81100000 0xffffffff81100000 > 0x000000000098be00 0x0000000000a00000 RWE 10000 > > Section to Segment mapping: > Segment Sections... > 00 .text __ex_table .notes .rodata .pci_fixup __ksymtab > __ksymtab_gpl __ksymtab_strings __init_rodata __param .data .init.text > .init.data .exit.text .data.percpu .bss .bss.superpage_aligned > > > Shouldn't we just follow what strip does? > > Regards, > Philby > > On 04/14/2011 11:26 PM, philby john wrote: >> From: David Daney >> Date: Wed, 13 Apr 2011 20:46:32 +0530 >> Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section >> >> Some early Octeon bootloaders cannot process PT_NOTE program >> headers as reported in numerous sections of the web, here is >> an example http://www.spinics.net/lists/mips/msg37799.html >> Loading usually fails with such an error ... >> Error allocating memory for elf image! >> >> The work around usually is to strip the .notes section by using >> such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux >> It is expected that the vmlinux image got after compilation be >> bootable. Add a Kconfig option to ignore the PT_NOTE section. >> >> Signed-off-by: David Daney >> Signed-off-by: Philby John >> --- >> arch/mips/cavium-octeon/Kconfig | 8 ++++++++ >> arch/mips/kernel/vmlinux.lds.S | 6 ++++++ >> 2 files changed, 14 insertions(+), 0 deletions(-) >> >> diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig >> index caae228..ddecee3 100644 >> --- a/arch/mips/cavium-octeon/Kconfig >> +++ b/arch/mips/cavium-octeon/Kconfig >> @@ -90,6 +90,14 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY >> help >> Lock the kernel's implementation of memcpy() into L2. >> >> +config DISABLE_ELF_NOTE_HEADER >> + bool "Disable the creation of the ELF PT_NOTE program header in vmlinux" >> + depends on CPU_CAVIUM_OCTEON >> + help >> + Some early Octeon bootloaders cannot process PT_NOTE program >> + headers. Select y to omit these headers so that the kernel >> + can be loaded with older bootloaders. >> + >> config ARCH_SPARSEMEM_ENABLE >> def_bool y >> select SPARSEMEM_STATIC >> diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S >> index 832afbb..0536910 100644 >> --- a/arch/mips/kernel/vmlinux.lds.S >> +++ b/arch/mips/kernel/vmlinux.lds.S >> @@ -8,7 +8,9 @@ OUTPUT_ARCH(mips) >> ENTRY(kernel_entry) >> PHDRS { >> text PT_LOAD FLAGS(7); /* RWX */ >> +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER >> note PT_NOTE FLAGS(4); /* R__ */ >> +#endif >> } >> >> #ifdef CONFIG_32BIT >> @@ -62,7 +64,11 @@ SECTIONS >> __stop___dbe_table = .; >> } >> >> +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER >> NOTES :text :note >> +#else >> + NOTES :text >> +#endif >> .dummy : { *(.dummy) } :text >> >> RODATA > > From f.fainelli@gmail.com Fri Apr 15 10:21:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Apr 2011 10:21:42 +0200 (CEST) Received: from mail-ww0-f41.google.com ([74.125.82.41]:32940 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491857Ab1DOIVi (ORCPT ); Fri, 15 Apr 2011 10:21:38 +0200 Received: by wwi18 with SMTP id 18so6945804wwi.0 for ; Fri, 15 Apr 2011 01:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:organization:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:message-id; bh=03Y0wsXIGLZCPGECkKlTRdsOaPN6xzprDkJ2pobSyo4=; b=P4PyJOFz814XvZGyDUrye92yxXlTIYNTNgYe/BmL9Y7FNwqVmAC9w08YVJwePe6HOR 1C/Vijj9mXeG2p/45++xukyKYQmJwiJbsrhCaI6fE7ftp8tRYO+TwkNMwn8yPQzJCKJz GuEa/LE4JWyFQCmm+h0F/IxUkT6JlTxpSDbrE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=NBRBDPe2rX1zFq/fzpfmgYdNbjgEtQHIWMhs91q1XMsFuMshFNECz8Fu6YuOSmillI GNcMkuFXSs3X6mL2zPHm39HCxLPikOy7LAkvuWKzJqmPl4iiPdmKE1sTGUPYYYBcWQq8 6RH4UQagX8JV4pOtnBOQNMXUpDTasuhIyUBzk= Received: by 10.216.143.7 with SMTP id k7mr1628797wej.95.1302855693434; Fri, 15 Apr 2011 01:21:33 -0700 (PDT) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id f30sm1168195wef.31.2011.04.15.01.21.31 (version=SSLv3 cipher=OTHER); Fri, 15 Apr 2011 01:21:31 -0700 (PDT) From: Florian Fainelli Organization: OpenWrt To: David Daney Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section Date: Fri, 15 Apr 2011 10:24:07 +0200 User-Agent: KMail/1.13.5 (Linux/2.6.35-25-server; KDE/4.5.1; x86_64; ; ) Cc: philby john , linux-mips@linux-mips.org References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> In-Reply-To: <4DA5DF7A.1030207@caviumnetworks.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201104151024.07859.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29760 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hello, On Wednesday 13 April 2011 19:38:02 David Daney wrote: > On 04/13/2011 09:07 AM, philby john wrote: > > From: Philby John > > ^^^^^^^^ I believe that statement to be not entirely correct. > > Perhaps you should change it to something like: > From: David Daney > > > Date: Wed, 13 Apr 2011 20:46:32 +0530 > > Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section > > > > Some early Octeon bootloaders cannot process PT_NOTE program > > headers as reported in numerous sections of the web, here is > > an example http://www.spinics.net/lists/mips/msg37799.html > > Loading usually fails with such an error ... > > Error allocating memory for elf image! > > > > The work around usually is to strip the .notes section by using > > such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux > > It is expected that the vmlinux image got after compilation be > > bootable. Add a Kconfig option to ignore the PT_NOTE section. Do we really want this to be in the kernel? In my opinion, this is a fixup which distributions should be aware of, but not necessarily take place here in the kernel Makefiles. -- Florian From pjohn@mvista.com Fri Apr 15 10:55:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Apr 2011 10:55:12 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:52114 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491857Ab1DOIzI (ORCPT ); Fri, 15 Apr 2011 10:55:08 +0200 Received: by pvh11 with SMTP id 11so1189491pvh.36 for ; Fri, 15 Apr 2011 01:55:01 -0700 (PDT) Received: by 10.68.55.33 with SMTP id o1mr1691275pbp.274.1302857701364; Fri, 15 Apr 2011 01:55:01 -0700 (PDT) Received: from localhost.localdomain ([122.172.20.218]) by mx.google.com with ESMTPS id k4sm315306pbi.62.2011.04.15.01.54.58 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 15 Apr 2011 01:55:00 -0700 (PDT) Message-ID: <4DA8081D.9050608@mvista.com> Date: Fri, 15 Apr 2011 14:25:57 +0530 From: Philby John User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101209 Fedora/3.1.7-0.35.b3pre.fc14 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Florian Fainelli CC: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> <201104151024.07859.florian@openwrt.org> In-Reply-To: <201104151024.07859.florian@openwrt.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29761 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk X-list: linux-mips On 04/15/2011 01:54 PM, Florian Fainelli wrote: > Hello, > > On Wednesday 13 April 2011 19:38:02 David Daney wrote: >> On 04/13/2011 09:07 AM, philby john wrote: >>> From: Philby John >> >> ^^^^^^^^ I believe that statement to be not entirely correct. >> >> Perhaps you should change it to something like: >> From: David Daney >> >>> Date: Wed, 13 Apr 2011 20:46:32 +0530 >>> Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section >>> >>> Some early Octeon bootloaders cannot process PT_NOTE program >>> headers as reported in numerous sections of the web, here is >>> an example http://www.spinics.net/lists/mips/msg37799.html >>> Loading usually fails with such an error ... >>> Error allocating memory for elf image! >>> >>> The work around usually is to strip the .notes section by using >>> such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux >>> It is expected that the vmlinux image got after compilation be >>> bootable. Add a Kconfig option to ignore the PT_NOTE section. > > Do we really want this to be in the kernel? In my opinion, this is a fixup > which distributions should be aware of, but not necessarily take place here in > the kernel Makefiles. You are right in one way. But as an OS vendor company we will definitely include this patch in our distribution. This incident has been reported many a times and its a pain to see the image not boot up, throw up an error, with the user having to search the work around on the web. What we are trying to do is save all that trouble. If it can be fixed why not fix it. Cheers, Philby From David.Daney@caviumnetworks.com Fri Apr 15 18:27:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Apr 2011 18:27:50 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4558 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491877Ab1DOQ1o (ORCPT ); Fri, 15 Apr 2011 18:27:44 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 15 Apr 2011 09:28:38 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 15 Apr 2011 09:27:39 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 15 Apr 2011 09:27:39 -0700 Message-ID: <4DA871F5.40809@caviumnetworks.com> Date: Fri, 15 Apr 2011 09:27:33 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Philby John CC: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> <201104151024.07859.florian@openwrt.org> <4DA8081D.9050608@mvista.com> In-Reply-To: <4DA8081D.9050608@mvista.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 15 Apr 2011 16:27:39.0440 (UTC) FILETIME=[098BB300:01CBFB8A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29762 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/15/2011 01:55 AM, Philby John wrote: > On 04/15/2011 01:54 PM, Florian Fainelli wrote: >> Hello, >> >> On Wednesday 13 April 2011 19:38:02 David Daney wrote: >>> On 04/13/2011 09:07 AM, philby john wrote: >>>> From: Philby John >>> >>> ^^^^^^^^ I believe that statement to be not entirely correct. >>> >>> Perhaps you should change it to something like: >>> From: David Daney >>> >>>> Date: Wed, 13 Apr 2011 20:46:32 +0530 >>>> Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section >>>> >>>> Some early Octeon bootloaders cannot process PT_NOTE program >>>> headers as reported in numerous sections of the web, here is >>>> an example http://www.spinics.net/lists/mips/msg37799.html >>>> Loading usually fails with such an error ... >>>> Error allocating memory for elf image! >>>> >>>> The work around usually is to strip the .notes section by using >>>> such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux >>>> It is expected that the vmlinux image got after compilation be >>>> bootable. Add a Kconfig option to ignore the PT_NOTE section. >> >> Do we really want this to be in the kernel? In my opinion, this is a fixup >> which distributions should be aware of, but not necessarily take place here in >> the kernel Makefiles. > > You are right in one way. But as an OS vendor company we will definitely > include this patch in our distribution. This incident has been reported > many a times and its a pain to see the image not boot up, throw up an > error, with the user having to search the work around on the web. What > we are trying to do is save all that trouble. If it can be fixed why not > fix it. > I don't care one way or another. We too (perhaps one and the same...) provide kernels to our SDK customers with the patch applied. An alternative approach would be to put the $(CROSS_COMPILE)strip command into the arch/mips/Makefile. David Daney From pjohn@mvista.com Sat Apr 16 17:20:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 17:20:40 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:58002 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490984Ab1DPPUg (ORCPT ); Sat, 16 Apr 2011 17:20:36 +0200 Received: by pwi8 with SMTP id 8so1873107pwi.36 for ; Sat, 16 Apr 2011 08:20:29 -0700 (PDT) Received: by 10.68.39.105 with SMTP id o9mr3920790pbk.45.1302967229113; Sat, 16 Apr 2011 08:20:29 -0700 (PDT) Received: from localhost.localdomain ([122.167.175.128]) by mx.google.com with ESMTPS id r10sm1128853pbn.94.2011.04.16.08.20.25 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 16 Apr 2011 08:20:27 -0700 (PDT) Message-ID: <4DA9B3F3.50805@mvista.com> Date: Sat, 16 Apr 2011 20:51:23 +0530 From: Philby John User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101209 Fedora/3.1.7-0.35.b3pre.fc14 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: David Daney CC: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> <201104151024.07859.florian@openwrt.org> <4DA8081D.9050608@mvista.com> <4DA871F5.40809@caviumnetworks.com> In-Reply-To: <4DA871F5.40809@caviumnetworks.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29763 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk X-list: linux-mips On 04/15/2011 09:57 PM, David Daney wrote: > On 04/15/2011 01:55 AM, Philby John wrote: >> On 04/15/2011 01:54 PM, Florian Fainelli wrote: >>> Hello, >>> >>> On Wednesday 13 April 2011 19:38:02 David Daney wrote: >>>> On 04/13/2011 09:07 AM, philby john wrote: >>>>> From: Philby John >>>> >>>> ^^^^^^^^ I believe that statement to be not entirely correct. >>>> >>>> Perhaps you should change it to something like: >>>> From: David Daney >>>> >>>>> Date: Wed, 13 Apr 2011 20:46:32 +0530 >>>>> Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section >>>>> >>>>> Some early Octeon bootloaders cannot process PT_NOTE program >>>>> headers as reported in numerous sections of the web, here is >>>>> an example http://www.spinics.net/lists/mips/msg37799.html >>>>> Loading usually fails with such an error ... >>>>> Error allocating memory for elf image! >>>>> >>>>> The work around usually is to strip the .notes section by using >>>>> such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux >>>>> It is expected that the vmlinux image got after compilation be >>>>> bootable. Add a Kconfig option to ignore the PT_NOTE section. >>> >>> Do we really want this to be in the kernel? In my opinion, this is a >>> fixup >>> which distributions should be aware of, but not necessarily take >>> place here in >>> the kernel Makefiles. >> >> You are right in one way. But as an OS vendor company we will definitely >> include this patch in our distribution. This incident has been reported >> many a times and its a pain to see the image not boot up, throw up an >> error, with the user having to search the work around on the web. What >> we are trying to do is save all that trouble. If it can be fixed why not >> fix it. >> > > I don't care one way or another. We too (perhaps one and the same...) > provide kernels to our SDK customers with the patch applied. > > An alternative approach would be to put the $(CROSS_COMPILE)strip > command into the arch/mips/Makefile. I doubt that's any good, strip also removes debug symbols along with the notes section and I am not aware of a specific command to strip just the PT_NOTE section. Just these lines of code seem to get the job done though ... +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER NOTES :text :note +#else + NOTES :text +#endif Regards, Philby From f.fainelli@gmail.com Sat Apr 16 17:51:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 17:52:02 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:51016 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491031Ab1DPPvz (ORCPT ); Sat, 16 Apr 2011 17:51:55 +0200 Received: by wwb17 with SMTP id 17so3579492wwb.24 for ; Sat, 16 Apr 2011 08:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:message-id:date:from:organization :user-agent:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; bh=GGRJpzTDbZPT0EGLm/Nxut+0r6J0MNSKporSEvfsjJQ=; b=RLgdpn7ToHCZiTRc3CxCdyxRIv/jsyKYmLjUU6mTvwUgsumc0iK9fYj8nOF6zItaEl LeAh0rAEsj3CIm88TyDe1gWFA7T/gvZttXDP09lkXsD8a+xW3TiyUgEow18LCC6GnO/I 5Du15/xMb2k/ncYEP/UhNLrZSqBqW4VtmcA/8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:message-id:date:from:organization:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; b=U9HseavHqL0c8oB35obuUgyXT8zsvrWIHydnzvHpBSvCgygQPTq8JUA1n7x0lneYrU qnbmbC7J5/4BO+10haBouqZx69tKkLkvWIEr+fkxJIGCeP8NI7ADGuGwLCnn/CoDV9T4 G++ZP537zhoSFOr5OTQ3zJIjR1tomQd9+LY8g= Received: by 10.227.140.77 with SMTP id h13mr3165617wbu.217.1302969108672; Sat, 16 Apr 2011 08:51:48 -0700 (PDT) Received: from [127.0.0.1] (fbx.mimichou.net [82.236.225.16]) by mx.google.com with ESMTPS id o6sm2226719wbo.54.2011.04.16.08.51.46 (version=SSLv3 cipher=OTHER); Sat, 16 Apr 2011 08:51:47 -0700 (PDT) Message-ID: <4DA9BB10.5030309@openwrt.org> Date: Sat, 16 Apr 2011 17:51:44 +0200 From: Florian Fainelli Organization: OpenWrt User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 MIME-Version: 1.0 To: Philby John CC: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> <201104151024.07859.florian@openwrt.org> <4DA8081D.9050608@mvista.com> <4DA871F5.40809@caviumnetworks.com> <4DA9B3F3.50805@mvista.com> In-Reply-To: <4DA9B3F3.50805@mvista.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29764 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hello, Le 16/04/2011 17:21, Philby John a écrit : > On 04/15/2011 09:57 PM, David Daney wrote: >> On 04/15/2011 01:55 AM, Philby John wrote: >>> On 04/15/2011 01:54 PM, Florian Fainelli wrote: >>>> Hello, >>>> >>>> On Wednesday 13 April 2011 19:38:02 David Daney wrote: >>>>> On 04/13/2011 09:07 AM, philby john wrote: >>>>>> From: Philby John >>>>> >>>>> ^^^^^^^^ I believe that statement to be not entirely correct. >>>>> >>>>> Perhaps you should change it to something like: >>>>> From: David Daney >>>>> >>>>>> Date: Wed, 13 Apr 2011 20:46:32 +0530 >>>>>> Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section >>>>>> >>>>>> Some early Octeon bootloaders cannot process PT_NOTE program >>>>>> headers as reported in numerous sections of the web, here is >>>>>> an example http://www.spinics.net/lists/mips/msg37799.html >>>>>> Loading usually fails with such an error ... >>>>>> Error allocating memory for elf image! >>>>>> >>>>>> The work around usually is to strip the .notes section by using >>>>>> such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux >>>>>> It is expected that the vmlinux image got after compilation be >>>>>> bootable. Add a Kconfig option to ignore the PT_NOTE section. >>>> >>>> Do we really want this to be in the kernel? In my opinion, this is a >>>> fixup >>>> which distributions should be aware of, but not necessarily take >>>> place here in >>>> the kernel Makefiles. >>> >>> You are right in one way. But as an OS vendor company we will definitely >>> include this patch in our distribution. This incident has been reported >>> many a times and its a pain to see the image not boot up, throw up an >>> error, with the user having to search the work around on the web. What >>> we are trying to do is save all that trouble. If it can be fixed why not >>> fix it. >>> >> >> I don't care one way or another. We too (perhaps one and the same...) >> provide kernels to our SDK customers with the patch applied. >> >> An alternative approach would be to put the $(CROSS_COMPILE)strip >> command into the arch/mips/Makefile. > > I doubt that's any good, strip also removes debug symbols along with the > notes section and I am not aware of a specific command to strip just the > PT_NOTE section. Just these lines of code seem to get the job done > though ... > > +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER > NOTES :text :note > +#else > + NOTES :text > +#endif strip can be told to only strip a particular section, e.g: $(TARGET_CROSS)strip -R .notes like David, I prefer this option rather than modifying the linker script. -- Florian From cernekee@gmail.com Sat Apr 16 18:51:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 18:51:28 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:41380 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491059Ab1DPQvY (ORCPT ); Sat, 16 Apr 2011 18:51:24 +0200 Received: (qmail 23766 invoked from network); 16 Apr 2011 16:51:18 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 16 Apr 2011 16:51:18 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 16 Apr 2011 09:51:18 -0700 From: Kevin Cernekee To: Ralf Baechle , David Daney Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] MIPS: Replace _PAGE_READ with _PAGE_NO_READ Date: Sat, 16 Apr 2011 09:44:29 -0700 Message-Id: <7aa38c32b7748a95e814e5bb0583f967@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29765 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Reuse more of the same definitions for the non-RIXI and RIXI cases. This avoids having special cases for kernel_uses_smartmips_rixi cluttering up the pgtable*.h files. On hardware that does not support RI/XI, EntryLo bits 31:30 / 63:62 will remain unset and RI/XI permissions will not be enforced. Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/pgtable-bits.h | 23 ++++++++--------------- arch/mips/include/asm/pgtable.h | 21 ++++++++------------- arch/mips/mm/tlbex.c | 17 +++++------------ 3 files changed, 21 insertions(+), 40 deletions(-) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index e9fe7e9..7afba78 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -35,7 +35,7 @@ #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define _PAGE_PRESENT (1<<6) /* implemented in software */ -#define _PAGE_READ (1<<7) /* implemented in software */ +#define _PAGE_NO_READ (1<<7) /* implemented in software */ #define _PAGE_WRITE (1<<8) /* implemented in software */ #define _PAGE_ACCESSED (1<<9) /* implemented in software */ #define _PAGE_MODIFIED (1<<10) /* implemented in software */ @@ -53,7 +53,7 @@ #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) #define _PAGE_PRESENT (1<<0) /* implemented in software */ -#define _PAGE_READ (1<<1) /* implemented in software */ +#define _PAGE_NO_READ (1<<1) /* implemented in software */ #define _PAGE_WRITE (1<<2) /* implemented in software */ #define _PAGE_ACCESSED (1<<3) /* implemented in software */ #define _PAGE_MODIFIED (1<<4) /* implemented in software */ @@ -79,11 +79,8 @@ /* implemented in software */ #define _PAGE_PRESENT_SHIFT (0) #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) -/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */ -#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) -#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) /* implemented in software */ -#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1) #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) /* implemented in software */ #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) @@ -104,12 +101,12 @@ #endif /* Page cannot be executed */ -#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) -#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) +#define _PAGE_NO_EXEC_SHIFT (_PAGE_HUGE_SHIFT + 1) +#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT) /* Page cannot be read */ -#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) -#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) +#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) +#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT) #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) @@ -136,10 +133,6 @@ #endif #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) -#ifndef _PAGE_NO_READ -#define _PAGE_NO_READ ({BUG(); 0; }) -#define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) -#endif #ifndef _PAGE_NO_EXEC #define _PAGE_NO_EXEC ({BUG(); 0; }) #endif @@ -220,7 +213,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #endif -#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ)) +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 7e40f37..0b3e7c6 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -22,15 +22,15 @@ struct mm_struct; struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \ _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ - (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | \ + _page_cachable_default) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | \ _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \ _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -250,7 +250,7 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte.pte_low |= _PAGE_ACCESSED; - if (pte.pte_low & _PAGE_READ) { + if (!(pte.pte_low & _PAGE_NO_READ)) { pte.pte_low |= _PAGE_SILENT_READ; pte.pte_high |= _PAGE_SILENT_READ; } @@ -299,13 +299,8 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; - if (kernel_uses_smartmips_rixi) { - if (!(pte_val(pte) & _PAGE_NO_READ)) - pte_val(pte) |= _PAGE_SILENT_READ; - } else { - if (pte_val(pte) & _PAGE_READ) - pte_val(pte) |= _PAGE_SILENT_READ; - } + if (!(pte_val(pte) & _PAGE_NO_READ)) + pte_val(pte) |= _PAGE_SILENT_READ; return pte; } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index f5734c2..451735b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1463,19 +1463,12 @@ static void __cpuinit build_pte_present(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { - if (kernel_uses_smartmips_rixi) { - if (use_bbit_insns()) { - uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); - uasm_i_nop(p); - } else { - uasm_i_andi(p, pte, pte, _PAGE_PRESENT); - uasm_il_beqz(p, r, pte, lid); - iPTE_LW(p, pte, ptr); - } + if (use_bbit_insns()) { + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); + uasm_i_nop(p); } else { - uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); - uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); - uasm_il_bnez(p, r, pte, lid); + uasm_i_andi(p, pte, pte, _PAGE_PRESENT); + uasm_il_beqz(p, r, pte, lid); iPTE_LW(p, pte, ptr); } } -- 1.7.4.3 From cernekee@gmail.com Sat Apr 16 18:51:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 18:51:51 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:41374 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491054Ab1DPQvY (ORCPT ); Sat, 16 Apr 2011 18:51:24 +0200 Received: (qmail 23807 invoked from network); 16 Apr 2011 16:51:20 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 16 Apr 2011 16:51:20 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 16 Apr 2011 09:51:20 -0700 From: Kevin Cernekee To: Ralf Baechle , David Daney Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] MIPS: Add dummy _PAGE_NO_EXEC field for R3000 and 64BIT_PHYS_ADDR cases Date: Sat, 16 Apr 2011 09:44:30 -0700 Message-Id: In-Reply-To: <7aa38c32b7748a95e814e5bb0583f967@localhost> References: <7aa38c32b7748a95e814e5bb0583f967@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29766 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Add a non-functional (software-only) _PAGE_NO_EXEC bit for all MIPS pte layouts. This allows for the elimination of the special case for non-RIXI when initializing the page protection map. Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/pgtable-bits.h | 21 ++++++------- arch/mips/mm/cache.c | 54 ++++++++++----------------------- 2 files changed, 27 insertions(+), 48 deletions(-) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 7afba78..c83eaca 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -36,10 +36,11 @@ #define _PAGE_PRESENT (1<<6) /* implemented in software */ #define _PAGE_NO_READ (1<<7) /* implemented in software */ -#define _PAGE_WRITE (1<<8) /* implemented in software */ -#define _PAGE_ACCESSED (1<<9) /* implemented in software */ -#define _PAGE_MODIFIED (1<<10) /* implemented in software */ -#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ +#define _PAGE_NO_EXEC (1<<8) /* implemented in software */ +#define _PAGE_WRITE (1<<9) /* implemented in software */ +#define _PAGE_ACCESSED (1<<10) /* implemented in software */ +#define _PAGE_MODIFIED (1<<11) /* implemented in software */ +#define _PAGE_FILE (1<<11) /* set:pagecache unset:swap */ #define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */ #define _PAGE_GLOBAL (1<<0) @@ -54,10 +55,11 @@ #define _PAGE_PRESENT (1<<0) /* implemented in software */ #define _PAGE_NO_READ (1<<1) /* implemented in software */ -#define _PAGE_WRITE (1<<2) /* implemented in software */ -#define _PAGE_ACCESSED (1<<3) /* implemented in software */ -#define _PAGE_MODIFIED (1<<4) /* implemented in software */ -#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ +#define _PAGE_NO_EXEC (1<<2) /* implemented in software */ +#define _PAGE_WRITE (1<<3) /* implemented in software */ +#define _PAGE_ACCESSED (1<<4) /* implemented in software */ +#define _PAGE_MODIFIED (1<<5) /* implemented in software */ +#define _PAGE_FILE (1<<5) /* set:pagecache unset:swap */ #define _PAGE_GLOBAL (1<<8) #define _PAGE_VALID (1<<9) @@ -133,9 +135,6 @@ #endif #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) -#ifndef _PAGE_NO_EXEC -#define _PAGE_NO_EXEC ({BUG(); 0; }) -#endif #ifndef _PAGE_GLOBAL_SHIFT #define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL) #endif diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 12af739..7c251e6 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -137,43 +137,23 @@ EXPORT_SYMBOL(_page_cachable_default); static inline void setup_protection_map(void) { - if (kernel_uses_smartmips_rixi) { - protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[3] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); - protection_map[5] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); - protection_map[7] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - - protection_map[8] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[9] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ); - protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); - protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); - protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE | _PAGE_NO_READ); - protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE); - - } else { - protection_map[0] = PAGE_NONE; - protection_map[1] = PAGE_READONLY; - protection_map[2] = PAGE_COPY; - protection_map[3] = PAGE_COPY; - protection_map[4] = PAGE_READONLY; - protection_map[5] = PAGE_READONLY; - protection_map[6] = PAGE_COPY; - protection_map[7] = PAGE_COPY; - protection_map[8] = PAGE_NONE; - protection_map[9] = PAGE_READONLY; - protection_map[10] = PAGE_SHARED; - protection_map[11] = PAGE_SHARED; - protection_map[12] = PAGE_READONLY; - protection_map[13] = PAGE_READONLY; - protection_map[14] = PAGE_SHARED; - protection_map[15] = PAGE_SHARED; - } + protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[3] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); + protection_map[5] = __pgprot(_page_cachable_default | _PAGE_PRESENT); + protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); + protection_map[7] = __pgprot(_page_cachable_default | _PAGE_PRESENT); + + protection_map[8] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[9] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ); + protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); + protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); + protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT); + protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE | _PAGE_NO_READ); + protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE); } void __cpuinit cpu_cache_init(void) -- 1.7.4.3 From cernekee@gmail.com Sat Apr 16 18:52:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 18:52:13 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:41392 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab1DPQv0 (ORCPT ); Sat, 16 Apr 2011 18:51:26 +0200 Received: (qmail 24053 invoked from network); 16 Apr 2011 16:51:22 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 16 Apr 2011 16:51:22 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 16 Apr 2011 09:51:22 -0700 From: Kevin Cernekee To: Ralf Baechle , David Daney Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] MIPS: Clean up protection_map[] initialization Date: Sat, 16 Apr 2011 09:44:31 -0700 Message-Id: <305a554e4aa54669dfff53283de096eb@localhost> In-Reply-To: <7aa38c32b7748a95e814e5bb0583f967@localhost> References: <7aa38c32b7748a95e814e5bb0583f967@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29767 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Fix long lines, factor out cut&paste flags, and add comments to explain the pgprot flags used. Signed-off-by: Kevin Cernekee --- arch/mips/mm/cache.c | 42 +++++++++++++++++++++++++----------------- 1 files changed, 25 insertions(+), 17 deletions(-) diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 7c251e6..edb003f 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -137,23 +137,31 @@ EXPORT_SYMBOL(_page_cachable_default); static inline void setup_protection_map(void) { - protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[3] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); - protection_map[5] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); - protection_map[7] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - - protection_map[8] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[9] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ); - protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); - protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); - protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE | _PAGE_NO_READ); - protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE); + int i; + const unsigned long prot[] = { + /* private mappings (clear the dirty bit until written) */ + [0] = _PAGE_NO_EXEC | _PAGE_NO_READ, /* --- */ + [1] = _PAGE_NO_EXEC, /* r-- */ + [2] = _PAGE_NO_EXEC | _PAGE_NO_READ, /* -w- */ + [3] = _PAGE_NO_EXEC, /* rw- */ + [4] = _PAGE_NO_READ, /* --x */ + [5] = 0, /* r-x */ + [6] = _PAGE_NO_READ, /* -wx */ + [7] = 0, /* rwx */ + /* shared mappings */ + [8] = _PAGE_NO_EXEC | _PAGE_NO_READ, /* --- */ + [9] = _PAGE_NO_EXEC, /* r-- */ + [10] = _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ, /* -w- */ + [11] = _PAGE_NO_EXEC | _PAGE_WRITE, /* rw- */ + [12] = _PAGE_NO_READ, /* --x */ + [13] = 0, /* r-x */ + [14] = _PAGE_WRITE | _PAGE_NO_READ, /* -wx */ + [15] = _PAGE_WRITE, /* rwx */ + }; + + for (i = 0; i < ARRAY_SIZE(protection_map); i++) + protection_map[i] = __pgprot(_page_cachable_default | + _PAGE_PRESENT | prot[i]); } void __cpuinit cpu_cache_init(void) -- 1.7.4.3 From cernekee@gmail.com Sat Apr 16 18:52:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 18:52:37 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:41412 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491075Ab1DPQv1 (ORCPT ); Sat, 16 Apr 2011 18:51:27 +0200 Received: (qmail 24271 invoked from network); 16 Apr 2011 16:51:24 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 16 Apr 2011 16:51:24 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 16 Apr 2011 09:51:24 -0700 From: Kevin Cernekee To: Ralf Baechle , David Daney Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] MIPS: Remove unused PAGE_* definitions Date: Sat, 16 Apr 2011 09:44:32 -0700 Message-Id: In-Reply-To: <7aa38c32b7748a95e814e5bb0583f967@localhost> References: <7aa38c32b7748a95e814e5bb0583f967@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29768 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips PAGE_{NONE,READONLY,COPY,SHARED} are no longer needed after refactoring setup_protection_map() to explicitly list r/w/x permissions. Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/pgtable.h | 7 ------- 1 files changed, 0 insertions(+), 7 deletions(-) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 0b3e7c6..718991c 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -21,13 +21,6 @@ struct mm_struct; struct vm_area_struct; -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \ - _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | \ - _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | \ - _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) #define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \ -- 1.7.4.3 From cernekee@gmail.com Sat Apr 16 20:37:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 20:37:28 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:59226 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491090Ab1DPShZ (ORCPT ); Sat, 16 Apr 2011 20:37:25 +0200 Received: (qmail 27950 invoked from network); 16 Apr 2011 18:37:21 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 16 Apr 2011 18:37:21 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 16 Apr 2011 11:37:21 -0700 From: Kevin Cernekee To: Ralf Baechle Cc: Robert Millan , David Daney , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] MIPS: Set ELF AT_PLATFORM string for BMIPS processors Date: Sat, 16 Apr 2011 11:29:28 -0700 Message-Id: <7f27896d6ff6598a4b9e003454ef10e0@localhost> In-Reply-To: References: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29769 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Signed-off-by: Kevin Cernekee --- arch/mips/kernel/cpu-probe.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5633ab1..e3cf292 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -911,12 +911,14 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_BMIPS32_REV8: c->cputype = CPU_BMIPS32; __cpu_name[cpu] = "Broadcom BMIPS32"; + set_elf_platform(cpu, "bmips32"); break; case PRID_IMP_BMIPS3300: case PRID_IMP_BMIPS3300_ALT: case PRID_IMP_BMIPS3300_BUG: c->cputype = CPU_BMIPS3300; __cpu_name[cpu] = "Broadcom BMIPS3300"; + set_elf_platform(cpu, "bmips3300"); break; case PRID_IMP_BMIPS43XX: { int rev = c->processor_id & 0xff; @@ -925,15 +927,18 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) rev <= PRID_REV_BMIPS4380_HI) { c->cputype = CPU_BMIPS4380; __cpu_name[cpu] = "Broadcom BMIPS4380"; + set_elf_platform(cpu, "bmips4380"); } else { c->cputype = CPU_BMIPS4350; __cpu_name[cpu] = "Broadcom BMIPS4350"; + set_elf_platform(cpu, "bmips4350"); } break; } case PRID_IMP_BMIPS5000: c->cputype = CPU_BMIPS5000; __cpu_name[cpu] = "Broadcom BMIPS5000"; + set_elf_platform(cpu, "bmips5000"); c->options |= MIPS_CPU_ULRI; break; } -- 1.7.4.3 From cernekee@gmail.com Sat Apr 16 20:37:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 20:37:51 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:59228 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491109Ab1DPShZ (ORCPT ); Sat, 16 Apr 2011 20:37:25 +0200 Received: (qmail 27922 invoked from network); 16 Apr 2011 18:37:19 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 16 Apr 2011 18:37:19 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 16 Apr 2011 11:37:19 -0700 From: Kevin Cernekee To: Ralf Baechle Cc: Robert Millan , David Daney , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] MIPS: Introduce set_elf_platform() helper function Date: Sat, 16 Apr 2011 11:29:27 -0700 Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29770 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips From: Robert Millan Replace these sequences: if (cpu == 0) __elf_platform = "foo"; with a trivial inline function. Signed-off-by: Robert Millan Acked-by: David Daney Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/elf.h | 6 ++++++ arch/mips/kernel/cpu-probe.c | 6 ++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index 455c0ac..455da05 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -348,6 +348,12 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_PLATFORM __elf_platform extern const char *__elf_platform; +static inline void set_elf_platform(int cpu, const char *plat) +{ + if (cpu == 0) + __elf_platform = plat; +} + /* * See comments in asm-alpha/elf.h, this is the same thing * on the MIPS. diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..5633ab1 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -956,14 +956,12 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_CAVIUM_OCTEON_PLUS; __cpu_name[cpu] = "Cavium Octeon+"; platform: - if (cpu == 0) - __elf_platform = "octeon"; + set_elf_platform(cpu, "octeon"); break; case PRID_IMP_CAVIUM_CN63XX: c->cputype = CPU_CAVIUM_OCTEON2; __cpu_name[cpu] = "Cavium Octeon II"; - if (cpu == 0) - __elf_platform = "octeon2"; + set_elf_platform(cpu, "octeon2"); break; default: printk(KERN_INFO "Unknown Octeon chip!\n"); -- 1.7.4.3 From cernekee@gmail.com Sat Apr 16 20:38:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 16 Apr 2011 20:38:16 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:59235 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491115Ab1DPSh0 (ORCPT ); Sat, 16 Apr 2011 20:37:26 +0200 Received: (qmail 27986 invoked from network); 16 Apr 2011 18:37:23 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 16 Apr 2011 18:37:23 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sat, 16 Apr 2011 11:37:23 -0700 From: Kevin Cernekee To: Ralf Baechle Cc: Robert Millan , David Daney , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] MIPS: Set ELF AT_PLATFORM string for Loongson2 processors Date: Sat, 16 Apr 2011 11:29:29 -0700 Message-Id: In-Reply-To: References: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29771 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips From: Robert Millan Signed-off-by: Robert Millan Acked-by: David Daney Signed-off-by: Kevin Cernekee --- arch/mips/kernel/cpu-probe.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index e3cf292..27ef0fc 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -614,6 +614,16 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_LOONGSON2: c->cputype = CPU_LOONGSON2; __cpu_name[cpu] = "ICT Loongson-2"; + + switch (c->processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON2E: + set_elf_platform(cpu, "loongson2e"); + break; + case PRID_REV_LOONGSON2F: + set_elf_platform(cpu, "loongson2f"); + break; + } + c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | -- 1.7.4.3 From pjohn@mvista.com Sun Apr 17 07:15:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Apr 2011 07:15:57 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:34508 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490953Ab1DQFPx (ORCPT ); Sun, 17 Apr 2011 07:15:53 +0200 Received: by pzk5 with SMTP id 5so1891316pzk.36 for ; Sat, 16 Apr 2011 22:15:46 -0700 (PDT) Received: by 10.68.46.200 with SMTP id x8mr4874828pbm.102.1303017346278; Sat, 16 Apr 2011 22:15:46 -0700 (PDT) Received: from localhost.localdomain ([122.172.164.87]) by mx.google.com with ESMTPS id g4sm1468958pbt.79.2011.04.16.22.15.43 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 16 Apr 2011 22:15:44 -0700 (PDT) Message-ID: <4DAA77B5.6000103@mvista.com> Date: Sun, 17 Apr 2011 10:46:37 +0530 From: Philby John User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101209 Fedora/3.1.7-0.35.b3pre.fc14 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Florian Fainelli CC: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section References: <1302710833.14458.1.camel@localhost.localdomain> <4DA5DF7A.1030207@caviumnetworks.com> <201104151024.07859.florian@openwrt.org> <4DA8081D.9050608@mvista.com> <4DA871F5.40809@caviumnetworks.com> <4DA9B3F3.50805@mvista.com> <4DA9BB10.5030309@openwrt.org> In-Reply-To: <4DA9BB10.5030309@openwrt.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29772 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk X-list: linux-mips On 04/16/2011 09:21 PM, Florian Fainelli wrote: > Hello, > > Le 16/04/2011 17:21, Philby John a écrit : >> On 04/15/2011 09:57 PM, David Daney wrote: >>> On 04/15/2011 01:55 AM, Philby John wrote: >>>> On 04/15/2011 01:54 PM, Florian Fainelli wrote: >>>>> Hello, >>>>> >>>>> On Wednesday 13 April 2011 19:38:02 David Daney wrote: >>>>>> On 04/13/2011 09:07 AM, philby john wrote: >>>>>>> From: Philby John >>>>>> >>>>>> ^^^^^^^^ I believe that statement to be not entirely correct. >>>>>> >>>>>> Perhaps you should change it to something like: >>>>>> From: David Daney >>>>>> >>>>>>> Date: Wed, 13 Apr 2011 20:46:32 +0530 >>>>>>> Subject: [PATCH] MIPS: Octeon: add option to ignore PT_NOTE section >>>>>>> >>>>>>> Some early Octeon bootloaders cannot process PT_NOTE program >>>>>>> headers as reported in numerous sections of the web, here is >>>>>>> an example http://www.spinics.net/lists/mips/msg37799.html >>>>>>> Loading usually fails with such an error ... >>>>>>> Error allocating memory for elf image! >>>>>>> >>>>>>> The work around usually is to strip the .notes section by using >>>>>>> such a command $mips-gnu-strip -R .notes vmlinux -o fixed-vmlinux >>>>>>> It is expected that the vmlinux image got after compilation be >>>>>>> bootable. Add a Kconfig option to ignore the PT_NOTE section. >>>>> >>>>> Do we really want this to be in the kernel? In my opinion, this is a >>>>> fixup >>>>> which distributions should be aware of, but not necessarily take >>>>> place here in >>>>> the kernel Makefiles. >>>> >>>> You are right in one way. But as an OS vendor company we will >>>> definitely >>>> include this patch in our distribution. This incident has been reported >>>> many a times and its a pain to see the image not boot up, throw up an >>>> error, with the user having to search the work around on the web. What >>>> we are trying to do is save all that trouble. If it can be fixed why >>>> not >>>> fix it. >>>> >>> >>> I don't care one way or another. We too (perhaps one and the same...) >>> provide kernels to our SDK customers with the patch applied. >>> >>> An alternative approach would be to put the $(CROSS_COMPILE)strip >>> command into the arch/mips/Makefile. >> >> I doubt that's any good, strip also removes debug symbols along with the >> notes section and I am not aware of a specific command to strip just the >> PT_NOTE section. Just these lines of code seem to get the job done >> though ... >> >> +#ifndef CONFIG_DISABLE_ELF_NOTE_HEADER >> NOTES :text :note >> +#else >> + NOTES :text >> +#endif > > strip can be told to only strip a particular section, e.g: > $(TARGET_CROSS)strip -R .notes > But this strips the debug symbols as well, from what I saw. Problems with the strip command? Anyways, I won't be pursuing this matter any further given the limited scope of its inclusion. Regards, Philby From cernekee@gmail.com Sun Apr 17 21:08:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Apr 2011 21:08:34 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:55953 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1492955Ab1DQTIa (ORCPT ); Sun, 17 Apr 2011 21:08:30 +0200 Received: (qmail 21722 invoked from network); 17 Apr 2011 19:08:25 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 17 Apr 2011 19:08:25 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Sun, 17 Apr 2011 12:08:24 -0700 From: Kevin Cernekee To: Ralf Baechle Cc: Wu Zhangjin , , Subject: [PATCH] MIPS: Squash pci_fixup_irqs() compiler warning Date: Sun, 17 Apr 2011 12:01:08 -0700 Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29773 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips MIPS Linux is unique in that it uses a "const struct pci_dev *" argument to discourage bad coding practices in pcibios_map_irq(). Add a cast so that this warning goes away: arch/mips/pci/pci.c: In function 'pcibios_init': arch/mips/pci/pci.c:165:45: warning: passing argument 2 of 'pci_fixup_irqs' from incompatible pointer type include/linux/pci.h:856:6: note: expected 'int (*)(struct pci_dev *, u8, u8)' but argument is of type 'struct pci_dev *' Signed-off-by: Kevin Cernekee --- Reference: http://www.mail-archive.com/gnewsense-dev@nongnu.org/msg00706.html It's been two years since the original discussion, and the warning is still there. It is now the only warning left in my kernel build. I was hoping we could get this resolved for good (one way or another). arch/mips/pci/pci.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 33bba7b..9a35cd6 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -157,7 +157,8 @@ static int __init pcibios_init(void) for (hose = hose_head; hose; hose = hose->next) pcibios_scanbus(hose); - pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq); + pci_fixup_irqs(pci_common_swizzle, + (int (*)(struct pci_dev *, u8, u8))pcibios_map_irq); pci_initialized = 1; -- 1.7.4.3 From Andrei.Ardelean@idt.com Mon Apr 18 17:41:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 17:42:03 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:34212 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493075Ab1DRPl7 convert rfc822-to-8bit (ORCPT ); Mon, 18 Apr 2011 17:41:59 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id p3IFfpg5009262 for ; Mon, 18 Apr 2011 08:41:51 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id p3IFfp17017699 for ; Mon, 18 Apr 2011 08:41:51 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id p3IFfoD00568 for ; Mon, 18 Apr 2011 08:41:50 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: How can I access h/w registers in user space? Date: Mon, 18 Apr 2011 08:41:48 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: How can I access h/w registers in user space? Thread-Index: Acv93yESpVtD7h5CTqqtT7JP0JzO/A== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29774 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, 1. My video processor has many h/w registers mapped in MIPS CPU physical memory space. Do I have in Linux MIPS something like iopl() to allow me to access h/w registers in user space? Is it anything similar available? 2. I studied mmap() solution but what I found unpleased is that I need to malloc() space in user space equal to the IO memory space I want to access which it is quite lot and it takes from system DDR RAM available I have here. What I need is just to access a physical space which I know that is mapped on internal registers. Thanks, Andrei From manuel.lauss@googlemail.com Mon Apr 18 17:47:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 17:47:53 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:46206 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493077Ab1DRPru (ORCPT ); Mon, 18 Apr 2011 17:47:50 +0200 Received: by wyb28 with SMTP id 28so5106883wyb.36 for ; Mon, 18 Apr 2011 08:47:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=QyRLLGxY/FSqlugykx1mskrRCd/l1ol9tQh7da5H5YE=; b=pCLQgWzbmtztCzewVqln7YHeEaCw+2ruwJNqokK8dRKFKeGYvFCKxLtkqRPRL8aADy LKQFBU1m/XQw7IgfY8rwrzHg5JWGXxo2utpsQARanCGR2PFw3fLpP7KKjJAXgzbZCYwG l99Z7A3uLloWXNN86yGJt4Jf0H7F6RzrdppHs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=gUitwkGeJnUkl6BxfaYy6sIvOclI68qqY7KhgntB62ECokJ/vlcGk01++JmAoN7ZT7 6uyuO7hOj9rfLRzr6NxJEts+w65U7bpSyxFg+OcOYfnHhzpO5nRQNXfwKVIOA+IV6Nui RuXK+YCL4bISRiqygMSW+Lx31XBjSXZBfrSTo= MIME-Version: 1.0 Received: by 10.216.82.68 with SMTP id n46mr5061771wee.57.1303141663946; Mon, 18 Apr 2011 08:47:43 -0700 (PDT) Received: by 10.216.237.218 with HTTP; Mon, 18 Apr 2011 08:47:43 -0700 (PDT) In-Reply-To: References: Date: Mon, 18 Apr 2011 17:47:43 +0200 Message-ID: Subject: Re: How can I access h/w registers in user space? From: Manuel Lauss To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29775 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Mon, Apr 18, 2011 at 5:41 PM, Ardelean, Andrei wrote: > 1. My video processor has many h/w registers mapped in MIPS CPU physical > memory space. Do I have in Linux MIPS something like iopl() to allow me > to access h/w registers in user space? Is it anything similar available? I believe iopl() is a x86-specific hack. > 2. I studied mmap() solution but what I found unpleased is that I need > to malloc() space in user space equal to the IO memory space I want to > access which it is quite lot and it takes from system DDR RAM available > I have here. What I need is just to access a physical space which I know > that is mapped on internal registers. I usually open /dev/mem then simply mmap() the base of the physical area I'm interested in. Hope that helps! Manuel Lauss From ddaney.cavm@gmail.com Mon Apr 18 19:28:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 19:28:08 +0200 (CEST) Received: from mail-iy0-f177.google.com ([209.85.210.177]:35342 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493095Ab1DRR2D (ORCPT ); Mon, 18 Apr 2011 19:28:03 +0200 Received: by iyb39 with SMTP id 39so5096192iyb.36 for ; Mon, 18 Apr 2011 10:27:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=TQ8QofcuR+uRBP25ysB8KfHxqtdPJcWtSYjxHfVW5+I=; b=hltxnJzTuRxRMPTgj0Hnsgh8DboY55z1gQaJ/wMCpC7Df5o442m/mQ90wAyaTNYwL4 1uNa+tBqyLjk2pGQnVRBTOD+hkar2V3q7zSeQUIxSbsljUhzb7B3NcdyOuJNO0lhbuy3 nY7SW3sFPCA4maSyf/YRKKmS5ltM8LJcTa060= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=Ai93AOg86KTdRC+MQKHQ3jGKbG8/56l6D7NYI+GZSKoux6PKl2Ujq3fajuaFQP/YCZ ru3XAk2OnSYHopaAJkNYCMY0b9dAAlJSwn1BmqVN0LEjNlJgTpAnknciRKFZ/AZR9jbs nLFIiUDVXMNNx0HVcDYgoHdsW5kePXnsvB820= Received: by 10.42.96.8 with SMTP id h8mr6657504icn.461.1303147676731; Mon, 18 Apr 2011 10:27:56 -0700 (PDT) Received: from dd1.caveonetworks.com ([12.108.191.226]) by mx.google.com with ESMTPS id i20sm2921031iby.48.2011.04.18.10.27.54 (version=SSLv3 cipher=OTHER); Mon, 18 Apr 2011 10:27:55 -0700 (PDT) Message-ID: <4DAC7499.5000602@gmail.com> Date: Mon, 18 Apr 2011 10:27:53 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , Wu Zhangjin , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: Squash pci_fixup_irqs() compiler warning References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29776 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney.cavm@gmail.com Precedence: bulk X-list: linux-mips On 04/17/2011 12:01 PM, Kevin Cernekee wrote: > MIPS Linux is unique in that it uses a "const struct pci_dev *" argument > to discourage bad coding practices in pcibios_map_irq(). Add a cast so > that this warning goes away: > > arch/mips/pci/pci.c: In function 'pcibios_init': > arch/mips/pci/pci.c:165:45: warning: passing argument 2 of 'pci_fixup_irqs' from incompatible pointer type > include/linux/pci.h:856:6: note: expected 'int (*)(struct pci_dev *, u8, u8)' but argument is of type 'struct pci_dev *' > > Signed-off-by: Kevin Cernekee > --- > > Reference: > > http://www.mail-archive.com/gnewsense-dev@nongnu.org/msg00706.html > > It's been two years since the original discussion, and the warning is > still there. It is now the only warning left in my kernel build. > > I was hoping we could get this resolved for good (one way or another). > > arch/mips/pci/pci.c | 3 ++- > 1 files changed, 2 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c > index 33bba7b..9a35cd6 100644 > --- a/arch/mips/pci/pci.c > +++ b/arch/mips/pci/pci.c > @@ -157,7 +157,8 @@ static int __init pcibios_init(void) > for (hose = hose_head; hose; hose = hose->next) > pcibios_scanbus(hose); > > - pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq); > + pci_fixup_irqs(pci_common_swizzle, > + (int (*)(struct pci_dev *, u8, u8))pcibios_map_irq); > NAK. I think Ralf's idea in the e-mail you referenced is the proper approach. Change pci_fixup_irqs(...) to take a 'const struct pci_dev *' instead. There is a lot of work going on in the kernel to constify things. This should be fairly easy to get accepted. The alternative is to change all the pcibios_map_irq to match what is expected by pci_fixup_irqs(). David Daney > pci_initialized = 1; > From David.Daney@caviumnetworks.com Mon Apr 18 19:30:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 19:31:04 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:3025 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493100Ab1DRRa6 (ORCPT ); Mon, 18 Apr 2011 19:30:58 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 18 Apr 2011 10:31:55 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 18 Apr 2011 10:30:55 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 18 Apr 2011 10:30:55 -0700 Message-ID: <4DAC754A.3080207@caviumnetworks.com> Date: Mon, 18 Apr 2011 10:30:50 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , Robert Millan , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] MIPS: Introduce set_elf_platform() helper function References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 18 Apr 2011 17:30:55.0619 (UTC) FILETIME=[5F7BE530:01CBFDEE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29777 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/16/2011 11:29 AM, Kevin Cernekee wrote: > From: Robert Millan > > Replace these sequences: > > if (cpu == 0) > __elf_platform = "foo"; > > with a trivial inline function. > > Signed-off-by: Robert Millan > Acked-by: David Daney > Signed-off-by: Kevin Cernekee > --- > arch/mips/include/asm/elf.h | 6 ++++++ > arch/mips/kernel/cpu-probe.c | 6 ++---- > 2 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h > index 455c0ac..455da05 100644 > --- a/arch/mips/include/asm/elf.h > +++ b/arch/mips/include/asm/elf.h > @@ -348,6 +348,12 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); > #define ELF_PLATFORM __elf_platform > extern const char *__elf_platform; > > +static inline void set_elf_platform(int cpu, const char *plat) > +{ > + if (cpu == 0) > + __elf_platform = plat; > +} > + Now I want to NAK it. This function is only ever used in cpu-probe.c, can't we just put it in there (and then make it non-inline)? The less stuff in elf.h the better. David Daney > /* > * See comments in asm-alpha/elf.h, this is the same thing > * on the MIPS. > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index f65d4c8..5633ab1 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -956,14 +956,12 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) > c->cputype = CPU_CAVIUM_OCTEON_PLUS; > __cpu_name[cpu] = "Cavium Octeon+"; > platform: > - if (cpu == 0) > - __elf_platform = "octeon"; > + set_elf_platform(cpu, "octeon"); > break; > case PRID_IMP_CAVIUM_CN63XX: > c->cputype = CPU_CAVIUM_OCTEON2; > __cpu_name[cpu] = "Cavium Octeon II"; > - if (cpu == 0) > - __elf_platform = "octeon2"; > + set_elf_platform(cpu, "octeon2"); > break; > default: > printk(KERN_INFO "Unknown Octeon chip!\n"); From David.Daney@caviumnetworks.com Mon Apr 18 19:32:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 19:33:01 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:3063 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493100Ab1DRRc4 (ORCPT ); Mon, 18 Apr 2011 19:32:56 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 18 Apr 2011 10:33:54 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 18 Apr 2011 10:32:54 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 18 Apr 2011 10:32:54 -0700 Message-ID: <4DAC75C6.2060504@caviumnetworks.com> Date: Mon, 18 Apr 2011 10:32:54 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] MIPS: Replace _PAGE_READ with _PAGE_NO_READ References: <7aa38c32b7748a95e814e5bb0583f967@localhost> In-Reply-To: <7aa38c32b7748a95e814e5bb0583f967@localhost> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 18 Apr 2011 17:32:54.0540 (UTC) FILETIME=[A65DCCC0:01CBFDEE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29778 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/16/2011 09:44 AM, Kevin Cernekee wrote: > Reuse more of the same definitions for the non-RIXI and RIXI cases. This > avoids having special cases for kernel_uses_smartmips_rixi cluttering up > the pgtable*.h files. > > On hardware that does not support RI/XI, EntryLo bits 31:30 / 63:62 will > remain unset and RI/XI permissions will not be enforced. > > Signed-off-by: Kevin Cernekee > --- > arch/mips/include/asm/pgtable-bits.h | 23 ++++++++--------------- > arch/mips/include/asm/pgtable.h | 21 ++++++++------------- > arch/mips/mm/tlbex.c | 17 +++++------------ > 3 files changed, 21 insertions(+), 40 deletions(-) > [...] I like this patch. How much testing have you done on non-RI/XI CPUs? David Daney From Andrei.Ardelean@idt.com Mon Apr 18 20:14:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 20:14:46 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:41490 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493114Ab1DRSOn convert rfc822-to-8bit (ORCPT ); Mon, 18 Apr 2011 20:14:43 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id p3IIEYBQ020801; Mon, 18 Apr 2011 11:14:34 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id p3IIEXCs006894; Mon, 18 Apr 2011 11:14:33 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id p3IIEXf06258; Mon, 18 Apr 2011 11:14:33 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: How can I access h/w registers in user space? Date: Mon, 18 Apr 2011 11:14:32 -0700 Message-ID: In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: How can I access h/w registers in user space? Thread-Index: Acv94LXbFQYxe8swS82Fzq24UnJ9RQAEoqEw References: From: "Ardelean, Andrei" To: "Manuel Lauss" , X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29779 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, Mmap() worked fine for one io memory region, but when I tried to open twice for different io memory regions with different base addresses and sizes it didn't work. It returned the same memory pointer value in both cases. In my design the h/w guys put those h/w registers in two distinct memory mapped regions with a large reserved area in between. Is it any solution for this case? Thanks, Andrei From cernekee@gmail.com Mon Apr 18 20:24:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 20:24:32 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:48836 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493115Ab1DRSY1 (ORCPT ); Mon, 18 Apr 2011 20:24:27 +0200 Received: by pwi8 with SMTP id 8so2835382pwi.36 for ; Mon, 18 Apr 2011 11:24:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=uotnw6pBAl+DSn7zUSezkGJ3ev3wSyh69y6Qw5FOS/I=; b=xn7agZ2nDjLhxxaSw/OHQesL6MeKQoKIfgVIuQLWfviZTmbGfq7+TsTnw6rm0tBevG YIWEUjicKC0r10mcOY5J3eq3dRXOTfTQOztt/Ea/7V34jvaeztd3R0t8Ts8VOOuI9SFg whUPNfyPHZQYMd1X9gtD+AhoHYqkMCfDDdRng= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=nt1Ja5cLNKIq9iBaXwjx8lcyxMBRY3JZopsyetdcEUpb4b2u3joVB39h84zoyqZnkN B16j6mQbWSz4mn1qIh/mwnWV2hJ99UiboyiSjfGirWqlx+fTe940CJMvcZri1PBd6/yP kPCnm4XPaQYRNqoLriLgQBZzfaDo+xkJy/o2E= MIME-Version: 1.0 Received: by 10.68.1.36 with SMTP id 4mr7711657pbj.251.1303151060325; Mon, 18 Apr 2011 11:24:20 -0700 (PDT) Received: by 10.68.46.169 with HTTP; Mon, 18 Apr 2011 11:24:20 -0700 (PDT) In-Reply-To: <4DAC75C6.2060504@caviumnetworks.com> References: <7aa38c32b7748a95e814e5bb0583f967@localhost> <4DAC75C6.2060504@caviumnetworks.com> Date: Mon, 18 Apr 2011 11:24:20 -0700 Message-ID: Subject: Re: [PATCH 1/4] MIPS: Replace _PAGE_READ with _PAGE_NO_READ From: Kevin Cernekee To: David Daney Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29780 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips On Mon, Apr 18, 2011 at 10:32 AM, David Daney wrote: > How much testing have you done on non-RI/XI CPUs? On a non-RIXI CPU I was able to boot the system, run a basic GUI application, create R/W shared mappings to /dev/mem, insert/remove kernel modules, run a broken program that dumps core, etc. I guess it would be a good idea to make sure swap still works. Didn't try that yet. Can you think of anything else that might exercise the bits that were touched by the patch? Were there any tests you ran during the development of RIXI support which uncovered subtle issues? Thanks. From manuel.lauss@googlemail.com Mon Apr 18 20:27:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 20:27:57 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:47802 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493116Ab1DRS1v (ORCPT ); Mon, 18 Apr 2011 20:27:51 +0200 Received: by wyb28 with SMTP id 28so5306004wyb.36 for ; Mon, 18 Apr 2011 11:27:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=8hLX4ZiK/XW7ZNxY60elYzUZ4UbxZzBRpS1POsBw0Zs=; b=N3S23RLFClf/yVDkiiWkPwXtJqMxcsIIydbgwTZTuu2REaj0aQ02qA8lCj/P0WzRaM aCuT1ggg+d1cygF/2MqDE9Y/tLiHOJVP+G3R6bSZg+4qayUnkSnBFE38nQjRScD5P44X 6uceyhzy8qXeWZKw8zpeAWNUNGJPmk8aXuwVY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=dPyl8SWdl32WGK5ttVU9phmS0zjIFGhuxCe1nUqYCWS4VN1Mifz76LFOlHu3ZrSHZp Wb+Z0+H5+stWzsMbPglrBjROOBR4bbsn5v3lZfh6ntZL/mm8OpzM4Mc6AEj8LqRQGZi/ PeaMIIaDPxzYtHd/EAHPeGsAjPC/Zu2rcYO74= MIME-Version: 1.0 Received: by 10.216.144.134 with SMTP id n6mr5380392wej.27.1303151266327; Mon, 18 Apr 2011 11:27:46 -0700 (PDT) Received: by 10.216.237.218 with HTTP; Mon, 18 Apr 2011 11:27:46 -0700 (PDT) In-Reply-To: References: Date: Mon, 18 Apr 2011 20:27:46 +0200 Message-ID: Subject: Re: How can I access h/w registers in user space? From: Manuel Lauss To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29781 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Mon, Apr 18, 2011 at 8:14 PM, Ardelean, Andrei wrote: > Mmap() worked fine for one io memory region, but when I tried to open > twice for different io memory regions with different base addresses and > sizes it didn't work. It returned the same memory pointer value in both > cases. In my design the h/w guys put those h/w registers in two distinct > memory mapped regions with a large reserved area in between. Is it any > solution for this case? This works for me. Unlike QNX, you can only map multiples of the page size and the base must also be aligned on a page boundary: #define MMIO 0x11900000 /* SYS_xxx */ #define MMIO2 0x14000000 /* MEM_xxx */ memfd = open("/dev/mem", O_RDWR); pgsize = sysconf(_SC_PAGESIZE); mmio = (unsigned long)mmap(0, pgsize, PROT_READ | PROT_WRITE, MAP_SHARED, memfd, MMIO); mmio2 = (unsigned long)mmap(0, 2 * pgsize, PROT_READ | PROT_WRITE, MAP_SHARED, memfd, MMIO2); Manuel From cernekee@gmail.com Mon Apr 18 20:44:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 20:44:14 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:45718 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1493122Ab1DRSoJ (ORCPT ); Mon, 18 Apr 2011 20:44:09 +0200 Received: (qmail 24230 invoked from network); 18 Apr 2011 18:44:02 -0000 Received: from localhost (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by localhost with (DHE-RSA-AES128-SHA encrypted) SMTP; 18 Apr 2011 18:44:02 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Mon, 18 Apr 2011 11:44:02 -0700 From: Kevin Cernekee To: Ralf Baechle Cc: Robert Millan , David Daney , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] MIPS: Introduce set_elf_platform() helper function Date: Mon, 18 Apr 2011 11:37:55 -0700 Message-Id: <12309140238d597edc0b48cbc07df218@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29782 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips From: Robert Millan Replace these sequences: if (cpu == 0) __elf_platform = "foo"; with a trivial inline function. Signed-off-by: Robert Millan Signed-off-by: Kevin Cernekee --- v2: Move the new function into cpu-probe.c . Retained the "inline" qualifier because all but one of the other helper functions in cpu-probe.c use it. arch/mips/kernel/cpu-probe.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..4e4a0fd 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -771,6 +771,12 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) c->core = read_c0_ebase() & 0x3ff; } +static inline void set_elf_platform(int cpu, const char *plat) +{ + if (cpu == 0) + __elf_platform = plat; +} + static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); @@ -956,14 +962,12 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_CAVIUM_OCTEON_PLUS; __cpu_name[cpu] = "Cavium Octeon+"; platform: - if (cpu == 0) - __elf_platform = "octeon"; + set_elf_platform(cpu, "octeon"); break; case PRID_IMP_CAVIUM_CN63XX: c->cputype = CPU_CAVIUM_OCTEON2; __cpu_name[cpu] = "Cavium Octeon II"; - if (cpu == 0) - __elf_platform = "octeon2"; + set_elf_platform(cpu, "octeon2"); break; default: printk(KERN_INFO "Unknown Octeon chip!\n"); -- 1.7.4.3 From David.Daney@caviumnetworks.com Mon Apr 18 20:52:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Apr 2011 20:52:34 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4506 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493124Ab1DRSw1 (ORCPT ); Mon, 18 Apr 2011 20:52:27 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 18 Apr 2011 11:53:24 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 18 Apr 2011 11:52:24 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 18 Apr 2011 11:52:24 -0700 Message-ID: <4DAC8868.4090003@caviumnetworks.com> Date: Mon, 18 Apr 2011 11:52:24 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] MIPS: Replace _PAGE_READ with _PAGE_NO_READ References: <7aa38c32b7748a95e814e5bb0583f967@localhost> <4DAC75C6.2060504@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 18 Apr 2011 18:52:24.0662 (UTC) FILETIME=[C194A760:01CBFDF9] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29783 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/18/2011 11:24 AM, Kevin Cernekee wrote: > On Mon, Apr 18, 2011 at 10:32 AM, David Daney wrote: >> How much testing have you done on non-RI/XI CPUs? > > On a non-RIXI CPU I was able to boot the system, run a basic GUI > application, create R/W shared mappings to /dev/mem, insert/remove > kernel modules, run a broken program that dumps core, etc. > > I guess it would be a good idea to make sure swap still works. Didn't > try that yet. > > Can you think of anything else that might exercise the bits that were > touched by the patch? Were there any tests you ran during the > development of RIXI support which uncovered subtle issues? > We run the LTP, I think it tests these things. We also have a small test case that tests for both the no-read and no-execute parts, but that would be expected to fail on platforms that don't have RI/XI bits. David Daney From nietzsche@lysator.liu.se Wed Apr 20 01:17:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Apr 2011 01:17:10 +0200 (CEST) Received: from mail.lysator.liu.se ([130.236.254.3]:54730 "EHLO mail.lysator.liu.se" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493186Ab1DSXRH convert rfc822-to-8bit (ORCPT ); Wed, 20 Apr 2011 01:17:07 +0200 Received: from mail.lysator.liu.se (localhost [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id 1F24B40004 for ; Wed, 20 Apr 2011 01:17:07 +0200 (CEST) Received: by mail.lysator.liu.se (Postfix, from userid 1004) id 13F694000B; Wed, 20 Apr 2011 01:17:07 +0200 (CEST) Received: from [192.168.10.106] (c83-251-17-172.bredband.comhem.se [83.251.17.172]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTPSA id D861140004 for ; Wed, 20 Apr 2011 01:17:05 +0200 (CEST) From: Markus Gothe Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8BIT Subject: Realtek's LX 5181 vs LX 5280 Date: Wed, 20 Apr 2011 01:16:54 +0200 Message-Id: <484613BA-E568-45C8-9179-1E0729BAAD5B@lysator.liu.se> To: linux-mips@linux-mips.org Mime-Version: 1.0 (Apple Message framework v1084) X-Pgp-Agent: GPGMail 1.3.3 X-Mailer: Apple Mail (2.1084) X-Virus-Scanned: ClamAV using ClamSMTP Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29784 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nietzsche@lysator.liu.se Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, does anyone have any good information about how Realtek's "LX 5181" differs from LX 5280? Any suggestions, observation etcetera on the toolchains out in the 'wild' would be highly appreciated. Best Regards, //Markus - The panama-hat hacker -----BEGIN PGP SIGNATURE----- Version: GnuPG/MacGPG2 v2.0.16 (Darwin) iD8DBQFNrhfw6I0XmJx2NrwRAsPDAKDM1gM6jfElol8yTRsvnINEgrNbDACfXbe/ Nq0U7QezHFkrrrQGu4dlvYE= =Ytk5 -----END PGP SIGNATURE----- From jayachandranc@netlogicmicro.com Fri Apr 22 18:53:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:53:58 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:3937 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491104Ab1DVQxx (ORCPT ); Fri, 22 Apr 2011 18:53:53 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42c476800016b68 ; Fri, 22 Apr 2011 09:53:34 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:54:40 -0700 Date: Fri, 22 Apr 2011 22:31:19 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 2/8] mach-netlogic include directory and files. Message-ID: <2f31c4ee3bc81e04fea211ff83514a181b8c6413.1303487516.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:54:40.0774 (UTC) FILETIME=[F8D3E260:01CC010D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29785 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add war.h and irq.h with XLR/XLS definitions. Add feature overrides for XLR/XLS. Signed-off-by: Jayachandran C --- .../asm/mach-netlogic/cpu-feature-overrides.h | 47 ++++++++++++++++++++ arch/mips/include/asm/mach-netlogic/irq.h | 14 ++++++ arch/mips/include/asm/mach-netlogic/war.h | 26 +++++++++++ 3 files changed, 87 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h new file mode 100644 index 0000000..3b72827 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_counter 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_icache_snoops_remote_store 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h new file mode 100644 index 0000000..b590245 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/irq.h @@ -0,0 +1,14 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + */ +#ifndef __ASM_NETLOGIC_IRQ_H +#define __ASM_NETLOGIC_IRQ_H + +#define NR_IRQS 64 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* __ASM_NETLOGIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h new file mode 100644 index 0000000..22da893 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/war.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_NLM_WAR_H +#define __ASM_MIPS_MACH_NLM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_NLM_WAR_H */ -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri Apr 22 18:54:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:54:21 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:3936 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491098Ab1DVQxx (ORCPT ); Fri, 22 Apr 2011 18:53:53 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42c46bc00016b67 ; Fri, 22 Apr 2011 09:53:34 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:54:23 -0700 Date: Fri, 22 Apr 2011 22:31:03 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 1/8] Netlogic XLR/XLS processor IDs. Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:54:23.0961 (UTC) FILETIME=[EECE6C90:01CC010D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29786 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add Netlogic Microsystems company ID and processor IDs for XLR and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. Signed-off-by: Jayachandran C --- arch/mips/include/asm/cpu.h | 27 ++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..34c0d3c 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 @@ -142,6 +143,31 @@ #define PRID_IMP_JZRISC 0x0200 /* + * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC + */ +#define PRID_IMP_NETLOGIC_XLR732 0x0000 +#define PRID_IMP_NETLOGIC_XLR716 0x0200 +#define PRID_IMP_NETLOGIC_XLR532 0x0900 +#define PRID_IMP_NETLOGIC_XLR308 0x0600 +#define PRID_IMP_NETLOGIC_XLR532C 0x0800 +#define PRID_IMP_NETLOGIC_XLR516C 0x0a00 +#define PRID_IMP_NETLOGIC_XLR508C 0x0b00 +#define PRID_IMP_NETLOGIC_XLR308C 0x0f00 +#define PRID_IMP_NETLOGIC_XLS608 0x8000 +#define PRID_IMP_NETLOGIC_XLS408 0x8800 +#define PRID_IMP_NETLOGIC_XLS404 0x8c00 +#define PRID_IMP_NETLOGIC_XLS208 0x8e00 +#define PRID_IMP_NETLOGIC_XLS204 0x8f00 +#define PRID_IMP_NETLOGIC_XLS108 0xce00 +#define PRID_IMP_NETLOGIC_XLS104 0xcf00 +#define PRID_IMP_NETLOGIC_XLS616B 0x4000 +#define PRID_IMP_NETLOGIC_XLS608B 0x4a00 +#define PRID_IMP_NETLOGIC_XLS416B 0x4400 +#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 +#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 +#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 + +/* * Definitions for 7:0 on legacy processors */ @@ -234,6 +260,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, + CPU_XLR, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..130aa7a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + c->options = (MIPS_CPU_TLB | + MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | + MIPS_CPU_WATCH | + MIPS_CPU_EJTAG | + MIPS_CPU_LLSC); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_NETLOGIC_XLR732: + case PRID_IMP_NETLOGIC_XLR716: + case PRID_IMP_NETLOGIC_XLR532: + case PRID_IMP_NETLOGIC_XLR308: + case PRID_IMP_NETLOGIC_XLR532C: + case PRID_IMP_NETLOGIC_XLR516C: + case PRID_IMP_NETLOGIC_XLR508C: + case PRID_IMP_NETLOGIC_XLR308C: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLR"; + break; + + case PRID_IMP_NETLOGIC_XLS608: + case PRID_IMP_NETLOGIC_XLS408: + case PRID_IMP_NETLOGIC_XLS404: + case PRID_IMP_NETLOGIC_XLS208: + case PRID_IMP_NETLOGIC_XLS204: + case PRID_IMP_NETLOGIC_XLS108: + case PRID_IMP_NETLOGIC_XLS104: + case PRID_IMP_NETLOGIC_XLS616B: + case PRID_IMP_NETLOGIC_XLS608B: + case PRID_IMP_NETLOGIC_XLS416B: + case PRID_IMP_NETLOGIC_XLS412B: + case PRID_IMP_NETLOGIC_XLS408B: + case PRID_IMP_NETLOGIC_XLS404B: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLS"; + break; + + default: + printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", + c->processor_id); + c->cputype = CPU_XLR; + break; + } + + c->isa_level = MIPS_CPU_ISA_M64R1; + c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; +} + #ifdef CONFIG_64BIT /* For use by uaccess.h */ u64 __ua_limit; @@ -1034,6 +1087,8 @@ __cpuinit void cpu_probe(void) break; case PRID_COMP_INGENIC: cpu_probe_ingenic(c, cpu); + case PRID_COMP_NETLOGIC: + cpu_probe_netlogic(c, cpu); break; } -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri Apr 22 18:54:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:54:47 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:3938 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491097Ab1DVQxx (ORCPT ); Fri, 22 Apr 2011 18:53:53 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42c461000016b66 ; Fri, 22 Apr 2011 09:53:34 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:54:06 -0700 Date: Fri, 22 Apr 2011 22:30:45 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 0/8] Support for Netlogic XLR/XLS processors Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:54:06.0649 (UTC) FILETIME=[E47CD290:01CC010D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29787 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Here's the latest version of the patchset for XLR/XLS support on Linux/MIPS, with PCI and USB support added. I would really appreciate a ACK/NAK if there is any issue with the code or license, since at this point I'm not sure why this patchset has not been merged. Thanks, JC. Changes from last version(v3): * USB support for XLS processors * PCI support for XLR/XLS processors * irq code updated - added PCI interrupts, minor fixes. Changes from last version(v2): * Netlogic files updated to use a dual license (GPLv2 or Netlogic 2-clause BSD license.) * irq.c updated to use new style of irq_data based handlers. * Rebased to latest linux-mips master tip. * Minor reshuffle of patches to group them better. Changes from last version(v1): * Initial 64-bit support * cleanup irq.c, don't use irq_desc[] directly * couple of checkpatch.pl white-space fixes Changes from last version(v0): * Remove c-netlogic.c for now, c-r4k works well enough for the first cut, so the custom cache handler can be considered later. * More elaborate asm/mach-netlogic/cpu-feature-overrides.h (noted by David Daney) These set of patches add support for the XLR and XLS multi-core MIPS64 SoCs from Netlogic Microsystems. These changes enable us to boot linux-mips on Netlogic evaluation boards from the netlogic bootloader. Jayachandran C (8): Netlogic XLR/XLS processor IDs. mach-netlogic include directory and files. Cache support, TLB support, asm/module.h entry Platform files for XLR/XLS processor support. Kconfig and Makefile update for Netlogic XLR/XLS Add default configuration for XLR/XLS processors USB support for XLS platforms. PCI support for XLR/XLS arch/mips/Kconfig | 44 + arch/mips/Makefile | 12 + arch/mips/configs/nlm_xlr_defconfig | 1705 ++++++++++++++++++++ arch/mips/include/asm/cpu.h | 27 + .../asm/mach-netlogic/cpu-feature-overrides.h | 47 + arch/mips/include/asm/mach-netlogic/irq.h | 14 + arch/mips/include/asm/mach-netlogic/war.h | 26 + arch/mips/include/asm/module.h | 2 + arch/mips/include/asm/netlogic/interrupt.h | 45 + arch/mips/include/asm/netlogic/mips-extns.h | 76 + arch/mips/include/asm/netlogic/pci.h | 8 + arch/mips/include/asm/netlogic/psb-bootinfo.h | 109 ++ arch/mips/include/asm/netlogic/xlr/gpio.h | 73 + arch/mips/include/asm/netlogic/xlr/iomap.h | 131 ++ arch/mips/include/asm/netlogic/xlr/pic.h | 231 +++ arch/mips/include/asm/netlogic/xlr/xlr.h | 75 + arch/mips/kernel/Makefile | 1 + arch/mips/kernel/cpu-probe.c | 55 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + arch/mips/netlogic/Kconfig | 5 + arch/mips/netlogic/xlr/Makefile | 5 + arch/mips/netlogic/xlr/irq.c | 300 ++++ arch/mips/netlogic/xlr/platform.c | 189 +++ arch/mips/netlogic/xlr/setup.c | 188 +++ arch/mips/netlogic/xlr/smp.c | 225 +++ arch/mips/netlogic/xlr/smpboot.S | 94 ++ arch/mips/netlogic/xlr/time.c | 51 + arch/mips/netlogic/xlr/xlr_console.c | 46 + arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlr.c | 215 +++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-xls.c | 170 ++ drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-xls.c | 160 ++ 37 files changed, 4344 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/pci.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c create mode 100644 arch/mips/pci/pci-xlr.c create mode 100644 drivers/usb/host/ehci-xls.c create mode 100644 drivers/usb/host/ohci-xls.c -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri Apr 22 18:55:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:55:09 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4460 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491107Ab1DVQyv (ORCPT ); Fri, 22 Apr 2011 18:54:51 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42d32c200016b6e ; Fri, 22 Apr 2011 09:54:34 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:54:59 -0700 Date: Fri, 22 Apr 2011 22:31:38 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 3/8] Cache support, TLB support, asm/module.h entry Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:54:59.0461 (UTC) FILETIME=[03F74B50:01CC010E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29788 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips CPU_XLR case added to mm/tlbex.c CPU_XLR case added to mm/c-r4k.c for PINDEX attribute Add XLR to asm/module.h Signed-off-by: Jayachandran C --- arch/mips/include/asm/module.h | 2 ++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 3 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index d94085a..bc01a02 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON2 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " +#elif defined CONFIG_CPU_XLR +#define MODULE_PROC_FAMILY "XLR " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 71bddf8..d9bc5d3 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1006,6 +1006,7 @@ static void __cpuinit probe_pcache(void) case CPU_25KF: case CPU_SB1: case CPU_SB1A: + case CPU_XLR: c->dcache.flags |= MIPS_CACHE_PINDEX; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index f5734c2..424ed4b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: + case CPU_XLR: uasm_i_nop(p); tlbw(p); break; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri Apr 22 18:55:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:55:35 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4716 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491114Ab1DVQyw (ORCPT ); Fri, 22 Apr 2011 18:54:52 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42d33ea00016b70 ; Fri, 22 Apr 2011 09:54:35 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:55:36 -0700 Date: Fri, 22 Apr 2011 22:32:16 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 5/8] Kconfig and Makefile update for Netlogic XLR/XLS Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:55:37.0024 (UTC) FILETIME=[1A5AF400:01CC010E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29789 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add NLM_XLR_BOARD, CPU_XLR and other config options Makefile updates, mostly based on r4k Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 42 +++++++++++++++++++++++++++++++++++++++ arch/mips/Makefile | 12 +++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/netlogic/Kconfig | 5 ++++ arch/mips/netlogic/xlr/Makefile | 5 ++++ 7 files changed, 67 insertions(+), 0 deletions(-) create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 351c80f..5016caa 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -736,6 +736,33 @@ config CAVIUM_OCTEON_REFERENCE_BOARD Hikari Say Y here for most Octeon reference boards. +config NLM_XLR_BOARD + bool "Netlogic XLR/XLS based systems" + depends on EXPERIMENTAL + select BOOT_ELF32 + select NLM_COMMON + select NLM_XLR + select SYS_HAS_CPU_XLR + select SYS_SUPPORTS_SMP + select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select 64BIT_PHYS_ADDR + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select DMA_COHERENT + select NR_CPUS_DEFAULT_32 + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select ZONE_DMA if 64BIT + select SYNC_R4K + select SYS_HAS_EARLY_PRINTK + help + Support for systems based on Netlogic XLR and XLS processors. + Say Y here if you have a XLR or XLS based board. + endchoice source "arch/mips/alchemy/Kconfig" @@ -752,6 +779,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/netlogic/Kconfig" endmenu @@ -1420,6 +1448,17 @@ config CPU_BMIPS5000 help Broadcom BMIPS5000 processors. +config CPU_XLR + bool "Netlogic XLR SoC" + depends on SYS_HAS_CPU_XLR + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select CPU_SUPPORTS_HUGEPAGES + help + Netlogic Microsystems XLR/XLS processors. endchoice if CPU_LOONGSON2F @@ -1550,6 +1589,9 @@ config SYS_HAS_CPU_BMIPS4380 config SYS_HAS_CPU_BMIPS5000 bool +config SYS_HAS_CPU_XLR + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 53e3514..884819c 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -191,6 +191,18 @@ endif # include $(srctree)/arch/mips/Kbuild.platforms +# +# NETLOGIC SOC Common (common) +# +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic + +# +# NETLOGIC XLR/XLS SoC, Simulator and boards +# +core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ +load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 + cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cedee2b..83bba33 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o +obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 2adead5..b2cad4f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o +obj-$(CONFIG_CPU_XLR) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index d679c77..eb44636 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o +obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig new file mode 100644 index 0000000..a5ca743 --- /dev/null +++ b/arch/mips/netlogic/Kconfig @@ -0,0 +1,5 @@ +config NLM_COMMON + bool + +config NLM_XLR + bool diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile new file mode 100644 index 0000000..9bd3f73 --- /dev/null +++ b/arch/mips/netlogic/xlr/Makefile @@ -0,0 +1,5 @@ +obj-y += setup.o platform.o irq.o setup.o time.o +obj-$(CONFIG_SMP) += smp.o smpboot.o +obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o + +EXTRA_CFLAGS += -Werror -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri Apr 22 18:55:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:56:01 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4717 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491116Ab1DVQyy (ORCPT ); Fri, 22 Apr 2011 18:54:54 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42d332f00016b6f ; Fri, 22 Apr 2011 09:54:34 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:55:18 -0700 Date: Fri, 22 Apr 2011 22:31:58 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 4/8] Platform files for XLR/XLS processor support. Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:55:18.0962 (UTC) FILETIME=[0F96E920:01CC010E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29790 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips * include/asm/netlogic added with files common for all Netlogic processors (common with XLP which will be added later) * include/asm/netlogic/xlr for XLR/XLS chip specific files * netlogic/xlr for XLR/XLS platform files Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/interrupt.h | 45 +++++ arch/mips/include/asm/netlogic/mips-extns.h | 76 ++++++++ arch/mips/include/asm/netlogic/psb-bootinfo.h | 109 ++++++++++++ arch/mips/include/asm/netlogic/xlr/gpio.h | 73 ++++++++ arch/mips/include/asm/netlogic/xlr/iomap.h | 131 ++++++++++++++ arch/mips/include/asm/netlogic/xlr/pic.h | 231 +++++++++++++++++++++++++ arch/mips/include/asm/netlogic/xlr/xlr.h | 54 ++++++ arch/mips/netlogic/xlr/irq.c | 216 +++++++++++++++++++++++ arch/mips/netlogic/xlr/platform.c | 98 +++++++++++ arch/mips/netlogic/xlr/setup.c | 188 ++++++++++++++++++++ arch/mips/netlogic/xlr/smp.c | 225 ++++++++++++++++++++++++ arch/mips/netlogic/xlr/smpboot.S | 94 ++++++++++ arch/mips/netlogic/xlr/time.c | 51 ++++++ arch/mips/netlogic/xlr/xlr_console.c | 46 +++++ 14 files changed, 1637 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h new file mode 100644 index 0000000..a85aadb --- /dev/null +++ b/arch/mips/include/asm/netlogic/interrupt.h @@ -0,0 +1,45 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_INTERRUPT_H +#define _ASM_NLM_INTERRUPT_H + +/* Defines for the IRQ numbers */ + +#define IRQ_IPI_SMP_FUNCTION 3 +#define IRQ_IPI_SMP_RESCHEDULE 4 +#define IRQ_MSGRING 6 +#define IRQ_TIMER 7 + +#endif diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h new file mode 100644 index 0000000..8c53d0b --- /dev/null +++ b/arch/mips/include/asm/netlogic/mips-extns.h @@ -0,0 +1,76 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_MIPS_EXTS_H +#define _ASM_NLM_MIPS_EXTS_H + +/* + * XLR and XLP interrupt request and interrupt mask registers + */ +#define read_c0_eirr() __read_64bit_c0_register($9, 6) +#define read_c0_eimr() __read_64bit_c0_register($9, 7) +#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val) + +/* + * Writing EIMR in 32 bit is a special case, the lower 8 bit of the + * EIMR is shadowed in the status register, so we cannot save and + * restore status register for split read. + */ +#define write_c0_eimr(val) \ +do { \ + if (sizeof(unsigned long) == 4) { \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, $9, 7\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\ + local_irq_restore(__flags); \ + } else \ + __write_64bit_c0_register($9, 7, (val)); \ +} while (0) + +static inline int hard_smp_processor_id(void) +{ + return __read_32bit_c0_register($15, 1) & 0x3ff; +} + +#endif /*_ASM_NLM_MIPS_EXTS_H */ diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h new file mode 100644 index 0000000..6878307 --- /dev/null +++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h @@ -0,0 +1,109 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NETLOGIC_BOOTINFO_H +#define _ASM_NETLOGIC_BOOTINFO_H + +struct psb_info { + uint64_t boot_level; + uint64_t io_base; + uint64_t output_device; + uint64_t uart_print; + uint64_t led_output; + uint64_t init; + uint64_t exit; + uint64_t warm_reset; + uint64_t wakeup; + uint64_t online_cpu_map; + uint64_t master_reentry_sp; + uint64_t master_reentry_gp; + uint64_t master_reentry_fn; + uint64_t slave_reentry_fn; + uint64_t magic_dword; + uint64_t uart_putchar; + uint64_t size; + uint64_t uart_getchar; + uint64_t nmi_handler; + uint64_t psb_version; + uint64_t mac_addr; + uint64_t cpu_frequency; + uint64_t board_version; + uint64_t malloc; + uint64_t free; + uint64_t global_shmem_addr; + uint64_t global_shmem_size; + uint64_t psb_os_cpu_map; + uint64_t userapp_cpu_map; + uint64_t wakeup_os; + uint64_t psb_mem_map; + uint64_t board_major_version; + uint64_t board_minor_version; + uint64_t board_manf_revision; + uint64_t board_serial_number; + uint64_t psb_physaddr_map; + uint64_t xlr_loaderip_config; + uint64_t bldr_envp; + uint64_t avail_mem_map; +}; + +enum { + NETLOGIC_IO_SPACE = 0x10, + PCIX_IO_SPACE, + PCIX_CFG_SPACE, + PCIX_MEMORY_SPACE, + HT_IO_SPACE, + HT_CFG_SPACE, + HT_MEMORY_SPACE, + SRAM_SPACE, + FLASH_CONTROLLER_SPACE +}; + +#define NLM_MAX_ARGS 64 +#define NLM_MAX_ENVS 32 + +/* This is what netlboot passes and linux boot_mem_map is subtly different */ +#define NLM_BOOT_MEM_MAP_MAX 32 +struct nlm_boot_mem_map { + int nr_map; + struct nlm_boot_mem_map_entry { + uint64_t addr; /* start of memory segment */ + uint64_t size; /* size of memory segment */ + uint32_t type; /* type of memory segment */ + } map[NLM_BOOT_MEM_MAP_MAX]; +}; + +/* Pointer to saved boot loader info */ +extern struct psb_info nlm_prom_info; + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h new file mode 100644 index 0000000..51f6ad4 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/gpio.h @@ -0,0 +1,73 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_GPIO_H +#define _ASM_NLM_GPIO_H + +#define NETLOGIC_GPIO_INT_EN_REG 0 +#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 +#define NETLOGIC_GPIO_IO_DIR_REG 2 +#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 +#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 + +#define NETLOGIC_GPIO_SWRESET_REG 8 +#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 +#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 +#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 +#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 +#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 +#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 +#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 +#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 + +#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 +#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 +#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 +#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 + +#define NETLOGIC_GPIO_FUSE_BANK_REG 35 +#define NETLOGIC_GPIO_CPU_RESET_REG 40 +#define NETLOGIC_GPIO_RNG_REG 43 + +#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 +#define NETLOGIC_GPIO_LED_BITMAP 0x1700000 +#define NETLOGIC_GPIO_LED_0_SHIFT 20 +#define NETLOGIC_GPIO_LED_1_SHIFT 24 + +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h new file mode 100644 index 0000000..2e3a4dd --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/iomap.h @@ -0,0 +1,131 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_IOMAP_H +#define _ASM_NLM_IOMAP_H + +#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000) +#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 +#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 +#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 +#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 +#define NETLOGIC_IO_PIC_OFFSET 0x08000 +#define NETLOGIC_IO_UART_0_OFFSET 0x14000 +#define NETLOGIC_IO_UART_1_OFFSET 0x15100 + +#define NETLOGIC_IO_SIZE 0x1000 + +#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 + +#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 +#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 + +#define NETLOGIC_IO_SRAM_OFFSET 0x07000 + +#define NETLOGIC_IO_PCIX_OFFSET 0x09000 +#define NETLOGIC_IO_HT_OFFSET 0x0A000 + +#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 + +#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 +#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 +#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 +#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 + +/* XLS devices */ +#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 +#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 +#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 +#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 + +#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 +#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 +#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 +#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 + +#define NETLOGIC_IO_USB_0_OFFSET 0x24000 +#define NETLOGIC_IO_USB_1_OFFSET 0x25000 + +#define NETLOGIC_IO_COMP_OFFSET 0x1D000 +/* end XLS devices */ + +/* XLR devices */ +#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 +#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 +#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 +#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 +/* end XLR devices */ + +#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 +#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 + +#define NETLOGIC_IO_GPIO_OFFSET 0x18000 +#define NETLOGIC_IO_FLASH_OFFSET 0x19000 +#define NETLOGIC_IO_TB_OFFSET 0x1C000 + +#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) + +/* + * Base Address (Virtual) of the PCI Config address space + * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28) + * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes + * ie 1<<24 = 16M + */ +#define DEFAULT_PCI_CONFIG_BASE 0x18000000 +#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 +#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 + +#ifndef __ASSEMBLY__ +#include +#include + +typedef volatile __u32 nlm_reg_t; +extern unsigned long netlogic_io_base; + +/* FIXME read once in write_reg */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define netlogic_read_reg(base, offset) ((base)[(offset)]) +#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value)) +#else +#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)])) +#define netlogic_write_reg(base, offset, value) \ + ((base)[(offset)] = cpu_to_be32((value))) +#endif + +#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)])) +#define netlogic_write_reg_le32(base, offset, value) \ + ((base)[(offset)] = cpu_to_le32((value))) +#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset))) +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h new file mode 100644 index 0000000..5cceb74 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -0,0 +1,231 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_XLR_PIC_H +#define _ASM_NLM_XLR_PIC_H + +#define PIC_CLKS_PER_SEC 66666666ULL +/* PIC hardware interrupt numbers */ +#define PIC_IRT_WD_INDEX 0 +#define PIC_IRT_TIMER_0_INDEX 1 +#define PIC_IRT_TIMER_1_INDEX 2 +#define PIC_IRT_TIMER_2_INDEX 3 +#define PIC_IRT_TIMER_3_INDEX 4 +#define PIC_IRT_TIMER_4_INDEX 5 +#define PIC_IRT_TIMER_5_INDEX 6 +#define PIC_IRT_TIMER_6_INDEX 7 +#define PIC_IRT_TIMER_7_INDEX 8 +#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX +#define PIC_IRT_UART_0_INDEX 9 +#define PIC_IRT_UART_1_INDEX 10 +#define PIC_IRT_I2C_0_INDEX 11 +#define PIC_IRT_I2C_1_INDEX 12 +#define PIC_IRT_PCMCIA_INDEX 13 +#define PIC_IRT_GPIO_INDEX 14 +#define PIC_IRT_HYPER_INDEX 15 +#define PIC_IRT_PCIX_INDEX 16 +/* XLS */ +#define PIC_IRT_CDE_INDEX 15 +#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16 +/* XLS */ +#define PIC_IRT_GMAC0_INDEX 17 +#define PIC_IRT_GMAC1_INDEX 18 +#define PIC_IRT_GMAC2_INDEX 19 +#define PIC_IRT_GMAC3_INDEX 20 +#define PIC_IRT_XGS0_INDEX 21 +#define PIC_IRT_XGS1_INDEX 22 +#define PIC_IRT_HYPER_FATAL_INDEX 23 +#define PIC_IRT_PCIX_FATAL_INDEX 24 +#define PIC_IRT_BRIDGE_AERR_INDEX 25 +#define PIC_IRT_BRIDGE_BERR_INDEX 26 +#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27 +#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28 +/* XLS */ +#define PIC_IRT_GMAC4_INDEX 21 +#define PIC_IRT_GMAC5_INDEX 22 +#define PIC_IRT_GMAC6_INDEX 23 +#define PIC_IRT_GMAC7_INDEX 24 +#define PIC_IRT_BRIDGE_ERR_INDEX 25 +#define PIC_IRT_PCIE_LINK0_INDEX 26 +#define PIC_IRT_PCIE_LINK1_INDEX 27 +#define PIC_IRT_PCIE_LINK2_INDEX 23 +#define PIC_IRT_PCIE_LINK3_INDEX 24 +#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28 +#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29 +#define PIC_IRT_SRIO_LINK0_INDEX 26 +#define PIC_IRT_SRIO_LINK1_INDEX 27 +#define PIC_IRT_SRIO_LINK2_INDEX 28 +#define PIC_IRT_SRIO_LINK3_INDEX 29 +#define PIC_IRT_PCIE_INT_INDEX 28 +#define PIC_IRT_PCIE_FATAL_INDEX 29 +#define PIC_IRT_GPIO_B_INDEX 30 +#define PIC_IRT_USB_INDEX 31 +/* XLS */ +#define PIC_NUM_IRTS 32 + + +#define PIC_CLOCK_TIMER 7 + +/* PIC Registers */ +#define PIC_CTRL 0x00 +#define PIC_IPI 0x04 +#define PIC_INT_ACK 0x06 + +#define WD_MAX_VAL_0 0x08 +#define WD_MAX_VAL_1 0x09 +#define WD_MASK_0 0x0a +#define WD_MASK_1 0x0b +#define WD_HEARBEAT_0 0x0c +#define WD_HEARBEAT_1 0x0d + +#define PIC_IRT_0_BASE 0x40 +#define PIC_IRT_1_BASE 0x80 +#define PIC_TIMER_MAXVAL_0_BASE 0x100 +#define PIC_TIMER_MAXVAL_1_BASE 0x110 +#define PIC_TIMER_COUNT_0_BASE 0x120 +#define PIC_TIMER_COUNT_1_BASE 0x130 + +#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) +#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) + +#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) +#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i)) +#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i)) +#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i)) + +/* + * Mapping between hardware interrupt numbers and IRQs on CPU + * we use a simple scheme to map PIC interrupts 0-31 to IRQs + * 8-39. This leaves the IRQ 0-7 for cpu interrupts like + * count/compare and FMN + */ +#define PIC_IRQ_BASE 8 +#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) +#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) + +#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE +#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) +#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX) +#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX) +#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX) +#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX) +#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX) +#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX) +#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX) +#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX) +#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ) +#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX) +#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX) +#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX) +#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX) +#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX) +#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX) +#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX) +#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX) +/* XLS */ +#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX) +#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX) +/* end XLS */ +#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX) +#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX) +#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX) +#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX) +#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX) +#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX) +#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX) +#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX) +#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) +#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) +#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) +#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) +/* XLS defines */ +#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) +#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) +#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX) +#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX) +#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX) +#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX) +#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX) +#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX) +#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX) +#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX) +#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX) +#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX) +#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX) +#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX) +#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX) +#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX) +#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX) +#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX) +#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX) +#define PIC_IRT_LAST_IRQ PIC_USB_IRQ +/* end XLS */ + +#ifndef __ASSEMBLY__ +static inline void pic_send_ipi(u32 ipi) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_IPI, ipi); +} + +static inline u32 pic_read_control(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + return netlogic_read_reg(mmio, PIC_CTRL); +} + +static inline void pic_write_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, control); +} + +static inline void pic_update_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, + (control | netlogic_read_reg(mmio, PIC_CTRL))); +} + +#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ + ((irq) <= PIC_TIMER_7_IRQ)) +#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ + ((irq) <= PIC_IRT_LAST_IRQ)) +#endif + +#endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h new file mode 100644 index 0000000..454c236 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -0,0 +1,54 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_XLR_H +#define _ASM_NLM_XLR_H + +/* Platform UART functions */ +struct uart_port; +unsigned int nlm_xlr_uart_in(struct uart_port *, int); +void nlm_xlr_uart_out(struct uart_port *, int, int); + +/* SMP support functions */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); +int nlm_wakeup_secondary_cpus(u32 wakeup_mask); +void nlm_smp_irq_init(void); +void nlm_boot_smp_nmi(void); +void prom_pre_boot_secondary_cpus(void); + +extern struct plat_smp_ops nlm_smp_ops; +extern unsigned long nlm_common_ebase; + +#endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c new file mode 100644 index 0000000..2033f56 --- /dev/null +++ b/arch/mips/netlogic/xlr/irq.c @@ -0,0 +1,216 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +static u64 nlm_irq_mask; +static DEFINE_SPINLOCK(nlm_pic_lock); + +static void xlr_pic_enable(struct irq_data *d) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + unsigned long flags; + nlm_reg_t reg; + int irq = d->irq; + + WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + reg | (1 << 6) | (1 << 30) | (1 << 31)); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static void xlr_pic_mask(struct irq_data *d) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + unsigned long flags; + nlm_reg_t reg; + int irq = d->irq; + + WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + reg | (1 << 6) | (1 << 30) | (0 << 31)); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static void xlr_pic_ack(struct irq_data *d) +{ + unsigned long flags; + nlm_reg_t *mmio; + int irq = d->irq; + + WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +/* + * This chip definition handles interrupts routed thru the XLR + * hardware PIC, currently IRQs 8-39 are mapped to hardware intr + * 0-31 wired the XLR PIC + */ +static struct irq_chip xlr_pic = { + .name = "XLR-PIC", + .irq_enable = xlr_pic_enable, + .irq_mask = xlr_pic_mask, + .irq_ack = xlr_pic_ack, +}; + +static void rsvd_irq_handler(struct irq_data *d) +{ + WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq); +} + +/* + * Chip definition for CPU originated interrupts(timer, msg) and + * IPIs + */ +struct irq_chip nlm_cpu_intr = { + .name = "XLR-CPU-INTR", + .irq_enable = rsvd_irq_handler, + .irq_mask = rsvd_irq_handler, + .irq_ack = rsvd_irq_handler, +}; + +void __init init_xlr_irqs(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + uint32_t thread_mask = 1; + int level, i; + + pr_info("Interrupt thread mask [%x]\n", thread_mask); + for (i = 0; i < PIC_NUM_IRTS; i++) { + level = PIC_IRQ_IS_EDGE_TRIGGERED(i); + + /* Bind all PIC irqs to boot cpu */ + netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask); + + /* + * Use local scheduling and high polarity for all IRTs + * Invalidate all IRTs, by default + */ + netlogic_write_reg(mmio, PIC_IRT_1_BASE + i, + (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i)); + } + + /* Make all IRQs as level triggered by default */ + for (i = 0; i < NR_IRQS; i++) { + if (PIC_IRQ_IS_IRT(i)) + irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq); + else + irq_set_chip_and_handler(i, &nlm_cpu_intr, + handle_level_irq); + } +#ifdef CONFIG_SMP + irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr, + nlm_smp_function_ipi_handler); + irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr, + nlm_smp_resched_ipi_handler); + nlm_irq_mask |= + ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); +#endif + /* unmask all PIC related interrupts. If no handler is installed by the + * drivers, it'll just ack the interrupt and return + */ + for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) + nlm_irq_mask |= (1ULL << i); + + nlm_irq_mask |= (1ULL << IRQ_TIMER); +} + +void __init arch_init_irq(void) +{ + /* Initialize the irq descriptors */ + init_xlr_irqs(); + write_c0_eimr(nlm_irq_mask); +} + +void __cpuinit nlm_smp_irq_init(void) +{ + /* set interrupt mask for non-zero cpus */ + write_c0_eimr(nlm_irq_mask); +} + +asmlinkage void plat_irq_dispatch(void) +{ + uint64_t eirr; + int i; + + eirr = read_c0_eirr() & read_c0_eimr(); + if (!eirr) + return; + + /* no need of EIRR here, writing compare clears interrupt */ + if (eirr & (1 << IRQ_TIMER)) { + do_IRQ(IRQ_TIMER); + return; + } + + /* TODO use dcltz: optimize below code */ + for (i = 63; i != -1; i--) { + if (eirr & (1ULL << i)) + break; + } + if (i == -1) { + pr_err("no interrupt !!\n"); + return; + } + + /* Ack eirr */ + write_c0_eirr(1ULL << i); + + do_IRQ(i); +} diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c new file mode 100644 index 0000000..609ec25 --- /dev/null +++ b/arch/mips/netlogic/xlr/platform.c @@ -0,0 +1,98 @@ +/* + * Copyright 2011, Netlogic Microsystems. + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) +{ + nlm_reg_t *mmio; + unsigned int value; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + value = netlogic_read_reg(mmio, 0); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + return value; +} + +void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) +{ + nlm_reg_t *mmio; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + netlogic_write_reg(mmio, 0, value); +} + +#define PORT(_irq) \ + { \ + .irq = _irq, \ + .regshift = 2, \ + .iotype = UPIO_MEM32, \ + .flags = (UPF_SKIP_TEST | \ + UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\ + .uartclk = PIC_CLKS_PER_SEC, \ + .type = PORT_16550A, \ + .serial_in = nlm_xlr_uart_in, \ + .serial_out = nlm_xlr_uart_out, \ + } + +static struct plat_serial8250_port xlr_uart_data[] = { + PORT(PIC_UART_0_IRQ), + PORT(PIC_UART_1_IRQ), + {}, +}; + +static struct platform_device uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = xlr_uart_data, + }, +}; + +static int __init nlm_uart_init(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + xlr_uart_data[0].membase = (void __iomem *)mmio; + xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio); + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); + xlr_uart_data[1].membase = (void __iomem *)mmio; + xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio); + + return platform_device_register(&uart_device); +} + +arch_initcall(nlm_uart_init); diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c new file mode 100644 index 0000000..4828025 --- /dev/null +++ b/arch/mips/netlogic/xlr/setup.c @@ -0,0 +1,188 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); +unsigned long nlm_common_ebase = 0x0; +struct psb_info nlm_prom_info; + +static void nlm_early_serial_setup(void) +{ + struct uart_port s; + nlm_reg_t *uart_base; + + uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + memset(&s, 0, sizeof(s)); + s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + s.iotype = UPIO_MEM32; + s.regshift = 2; + s.irq = PIC_UART_0_IRQ; + s.uartclk = PIC_CLKS_PER_SEC; + s.serial_in = nlm_xlr_uart_in; + s.serial_out = nlm_xlr_uart_out; + s.mapbase = (unsigned long)uart_base; + s.membase = (unsigned char __iomem *)uart_base; + early_serial_setup(&s); +} + +static void nlm_linux_exit(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); + /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ + netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); + for ( ; ; ) + cpu_wait(); +} + +void __init plat_mem_setup(void) +{ + panic_timeout = 5; + _machine_restart = (void (*)(char *))nlm_linux_exit; + _machine_halt = nlm_linux_exit; + pm_power_off = nlm_linux_exit; +} + +const char *get_system_type(void) +{ + return "Netlogic XLR/XLS Series"; +} + +void __init prom_free_prom_memory(void) +{ + /* Nothing yet */ +} + +static void build_arcs_cmdline(int *argv) +{ + int i, remain, len; + char *arg; + + remain = sizeof(arcs_cmdline) - 1; + arcs_cmdline[0] = '\0'; + for (i = 0; argv[i] != 0; i++) { + arg = (char *)(long)argv[i]; + len = strlen(arg); + if (len + 1 > remain) + break; + strcat(arcs_cmdline, arg); + strcat(arcs_cmdline, " "); + remain -= len + 1; + } + + /* Add the default options here */ + if ((strstr(arcs_cmdline, "console=")) == NULL) { + arg = "console=ttyS0,38400 "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#ifdef CONFIG_BLK_DEV_INITRD + if ((strstr(arcs_cmdline, "rdinit=")) == NULL) { + arg = "rdinit=/sbin/init "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#endif + return; +fail: + panic("Cannot add %s, command line too big!", arg); +} + +static void prom_add_memory(void) +{ + struct nlm_boot_mem_map *bootm; + u64 start, size; + u64 pref_backup = 512; /* avoid pref walking beyond end */ + int i; + + bootm = (void *)(long)nlm_prom_info.psb_mem_map; + for (i = 0; i < bootm->nr_map; i++) { + if (bootm->map[i].type != BOOT_MEM_RAM) + continue; + start = bootm->map[i].addr; + size = bootm->map[i].size; + + /* Work around for using bootloader mem */ + if (i == 0 && start == 0 && size == 0x0c000000) + size = 0x0ff00000; + + add_memory_region(start, size - pref_backup, BOOT_MEM_RAM); + } +} + +void __init prom_init(void) +{ + int *argv, *envp; /* passed as 32 bit ptrs */ + struct psb_info *prom_infop; + + /* truncate to 32 bit and sign extend all args */ + argv = (int *)(long)(int)fw_arg1; + envp = (int *)(long)(int)fw_arg2; + prom_infop = (struct psb_info *)(long)(int)fw_arg3; + + nlm_prom_info = *prom_infop; + + nlm_early_serial_setup(); + build_arcs_cmdline(argv); + nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); + prom_add_memory(); + +#ifdef CONFIG_SMP + nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map); + register_smp_ops(&nlm_smp_ops); +#endif +} diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c new file mode 100644 index 0000000..b495a7f --- /dev/null +++ b/arch/mips/netlogic/xlr/smp.c @@ -0,0 +1,225 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +void core_send_ipi(int logical_cpu, unsigned int action) +{ + int cpu = cpu_logical_map(logical_cpu); + u32 tid = cpu & 0x3; + u32 pid = (cpu >> 2) & 0x07; + u32 ipi = (tid << 16) | (pid << 20); + + if (action & SMP_CALL_FUNCTION) + ipi |= IRQ_IPI_SMP_FUNCTION; + else if (action & SMP_RESCHEDULE_YOURSELF) + ipi |= IRQ_IPI_SMP_RESCHEDULE; + else + return; + + pic_send_ipi(ipi); +} + +void nlm_send_ipi_single(int cpu, unsigned int action) +{ + core_send_ipi(cpu, action); +} + +void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + int cpu; + + for_each_cpu(cpu, mask) { + core_send_ipi(cpu, action); + } +} + +/* IRQ_IPI_SMP_FUNCTION Handler */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + smp_call_function_interrupt(); +} + +/* IRQ_IPI_SMP_RESCHEDULE handler */ +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + set_need_resched(); +} + +void nlm_common_ipi_handler(int irq, struct pt_regs *regs) +{ + if (irq == IRQ_IPI_SMP_FUNCTION) { + smp_call_function_interrupt(); + } else { + /* Announce that we are for reschduling */ + set_need_resched(); + } +} + +/* + * Called before going into mips code, early cpu init + */ +void nlm_early_init_secondary(void) +{ + write_c0_ebase((uint32_t)nlm_common_ebase); + /* TLB partition here later */ +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit nlm_init_secondary(void) +{ + nlm_smp_irq_init(); +} + +void nlm_smp_finish(void) +{ +#ifdef notyet + nlm_common_msgring_cpu_init(); +#endif +} + +void nlm_cpus_done(void) +{ +} + +/* + * Boot all other cpus in the system, initialize them, and bring them into + * the boot function + */ +int nlm_cpu_unblock[NR_CPUS]; +int nlm_cpu_ready[NR_CPUS]; +unsigned long nlm_next_gp; +unsigned long nlm_next_sp; +cpumask_t phys_cpu_present_map; + +void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long)task_thread_info(idle); + unsigned long sp = (unsigned long)__KSTK_TOS(idle); + int cpu = cpu_logical_map(logical_cpu); + + nlm_next_sp = sp; + nlm_next_gp = gp; + + /* barrier */ + __sync(); + nlm_cpu_unblock[cpu] = 1; +} + +void __init nlm_smp_setup(void) +{ + unsigned int boot_cpu; + int num_cpus, i; + + boot_cpu = hard_smp_processor_id(); + cpus_clear(phys_cpu_present_map); + + cpu_set(boot_cpu, phys_cpu_present_map); + __cpu_number_map[boot_cpu] = 0; + __cpu_logical_map[0] = boot_cpu; + cpu_set(0, cpu_possible_map); + + num_cpus = 1; + for (i = 0; i < NR_CPUS; i++) { + if (nlm_cpu_ready[i]) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = num_cpus; + __cpu_logical_map[num_cpus] = i; + cpu_set(num_cpus, cpu_possible_map); + ++num_cpus; + } + } + + pr_info("Phys CPU present map: %lx, possible map %lx\n", + (unsigned long)phys_cpu_present_map.bits[0], + (unsigned long)cpu_possible_map.bits[0]); + + pr_info("Detected %i Slave CPU(s)\n", num_cpus); +} + +void nlm_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops nlm_smp_ops = { + .send_ipi_single = nlm_send_ipi_single, + .send_ipi_mask = nlm_send_ipi_mask, + .init_secondary = nlm_init_secondary, + .smp_finish = nlm_smp_finish, + .cpus_done = nlm_cpus_done, + .boot_secondary = nlm_boot_secondary, + .smp_setup = nlm_smp_setup, + .prepare_cpus = nlm_prepare_cpus, +}; + +unsigned long secondary_entry_point; + +int nlm_wakeup_secondary_cpus(u32 wakeup_mask) +{ + unsigned int tid, pid, ipi, i, boot_cpu; + void *reset_vec; + + secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus; + reset_vec = (void *)CKSEG1ADDR(0x1fc00000); + memcpy(reset_vec, nlm_boot_smp_nmi, 0x80); + boot_cpu = hard_smp_processor_id(); + + for (i = 0; i < NR_CPUS; i++) { + if (i == boot_cpu) + continue; + if (wakeup_mask & (1u << i)) { + tid = i & 0x3; + pid = (i >> 2) & 0x7; + ipi = (tid << 16) | (pid << 20) | (1 << 8); + pic_send_ipi(ipi); + } + } + + return 0; +} diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S new file mode 100644 index 0000000..b8e0744 --- /dev/null +++ b/arch/mips/netlogic/xlr/smpboot.S @@ -0,0 +1,94 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/* Don't jump to linux function from Bootloader stack. Change it + * here. Kernel might allocate bootloader memory before all the CPUs are + * brought up (eg: Inode cache region) and we better don't overwrite this + * memory + */ +NESTED(prom_pre_boot_secondary_cpus, 16, sp) + .set mips64 + mfc0 t0, $15, 1 # read ebase + andi t0, 0x1f # t0 has the processor_id() + sll t0, 2 # offset in cpu array + + PTR_LA t1, nlm_cpu_ready # mark CPU ready + PTR_ADDU t1, t0 + li t2, 1 + sw t2, 0(t1) + + PTR_LA t1, nlm_cpu_unblock + PTR_ADDU t1, t0 +1: lw t2, 0(t1) # wait till unblocked + beqz t2, 1b + nop + + PTR_LA t1, nlm_next_sp + PTR_L sp, 0(t1) + PTR_LA t1, nlm_next_gp + PTR_L gp, 0(t1) + + PTR_LA t0, nlm_early_init_secondary + jalr t0 + nop + + PTR_LA t0, smp_bootstrap + jr t0 + nop +END(prom_pre_boot_secondary_cpus) + +NESTED(nlm_boot_smp_nmi, 0, sp) + .set push + .set noat + .set mips64 + .set noreorder + + /* Clear the NMI and BEV bits */ + MFC0 k0, CP0_STATUS + li k1, 0xffb7ffff + and k0, k0, k1 + MTC0 k0, CP0_STATUS + + PTR_LA k1, secondary_entry_point + PTR_L k0, 0(k1) + jr k0 + nop + .set pop +END(nlm_boot_smp_nmi) diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c new file mode 100644 index 0000000..0d81b26 --- /dev/null +++ b/arch/mips/netlogic/xlr/time.c @@ -0,0 +1,51 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return IRQ_TIMER; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = nlm_prom_info.cpu_frequency; + pr_info("MIPS counter frequency [%ld]\n", + (unsigned long)mips_hpt_frequency); +} diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/xlr_console.c new file mode 100644 index 0000000..759df06 --- /dev/null +++ b/arch/mips/netlogic/xlr/xlr_console.c @@ -0,0 +1,46 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +void prom_putchar(char c) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + while (netlogic_read_reg(mmio, 0x5) == 0) + ; + netlogic_write_reg(mmio, 0x0, c); +} -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri Apr 22 18:56:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:56:27 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1341 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491106Ab1DVQzw (ORCPT ); Fri, 22 Apr 2011 18:55:52 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42e213800016b7a ; Fri, 22 Apr 2011 09:55:35 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:56:18 -0700 Date: Fri, 22 Apr 2011 22:32:57 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 7/8] USB support for XLS platforms. Message-ID: <21ae06c6f50f7a770b62d61265e6f509f37d1762.1303487516.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:56:18.0368 (UTC) FILETIME=[32FF8C00:01CC010E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29791 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips update ehci-hcd.c and ohci-hcd.c to add XLS hcds add ehci/ohci devices to XLR/XLS platform driver Kconfig update Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 2 + arch/mips/include/asm/netlogic/xlr/xlr.h | 12 ++ arch/mips/netlogic/xlr/platform.c | 91 ++++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-xls.c | 170 ++++++++++++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-xls.c | 160 ++++++++++++++++++++++++++++ 7 files changed, 445 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-xls.c create mode 100644 drivers/usb/host/ohci-xls.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5016caa..7fa4f01 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -759,6 +759,8 @@ config NLM_XLR_BOARD select ZONE_DMA if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK + select USB_ARCH_HAS_OHCI if USB_SUPPORT + select USB_ARCH_HAS_EHCI if USB_SUPPORT help Support for systems based on Netlogic XLR and XLS processors. Say Y here if you have a XLR or XLS based board. diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h index 454c236..1cffd21 100644 --- a/arch/mips/include/asm/netlogic/xlr/xlr.h +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -51,4 +51,16 @@ void prom_pre_boot_secondary_cpus(void); extern struct plat_smp_ops nlm_smp_ops; extern unsigned long nlm_common_ebase; +/* + * XLR chip types + */ + /* The XLS product line has chip versions 0x[48c]? */ +static inline unsigned int nlm_chip_is_xls(void) +{ + uint32_t prid = read_c0_prid(); + + return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 || + (prid & 0xf000) == 0xc000); +} + #endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c index 609ec25..ac70144 100644 --- a/arch/mips/netlogic/xlr/platform.c +++ b/arch/mips/netlogic/xlr/platform.c @@ -96,3 +96,94 @@ static int __init nlm_uart_init(void) } arch_initcall(nlm_uart_init); + +/* Platform I2C devices */ + +#ifdef CONFIG_USB +/* Platform USB devices, only on XLS chips */ +static u64 xls_usb_dmamask = ~(u32)0; +#define USB_PLATFORM_DEV(n, i, irq) \ + { \ + .name = n, \ + .id = i, \ + .num_resources = 2, \ + .dev = { \ + .dma_mask = &xls_usb_dmamask, \ + .coherent_dma_mask = 0xffffffff, \ + }, \ + .resource = (struct resource[]) { \ + { \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }, \ + } + +static struct platform_device xls_usb_ehci_device = + USB_PLATFORM_DEV("ehci-xls", 0, PIC_USB_IRQ); +static struct platform_device xls_usb_ohci_device_0 = + USB_PLATFORM_DEV("ohci-xls-0", 1, PIC_USB_IRQ); +static struct platform_device xls_usb_ohci_device_1 = + USB_PLATFORM_DEV("ohci-xls-1", 2, PIC_USB_IRQ); + +static struct platform_device *xls_platform_devices[] __initdata = { + &xls_usb_ehci_device, + &xls_usb_ohci_device_0, + &xls_usb_ohci_device_1, +}; + +int xls_platform_usb_init(void) +{ + nlm_reg_t *usb_mmio, *gpio_mmio; + unsigned long memres; + uint32_t val; + + if (!nlm_chip_is_xls()) + return 0; + + gpio_mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); + usb_mmio = netlogic_io_mmio(NETLOGIC_IO_USB_1_OFFSET); + + /* Clear Rogue Phy INTs */ + netlogic_write_reg(usb_mmio, 49, 0x10000000); + /* Enable all interrupts */ + netlogic_write_reg(usb_mmio, 50, 0x1f000000); + + /* Enable ports */ + netlogic_write_reg(usb_mmio, 1, 0x07000500); + + val = netlogic_read_reg(gpio_mmio, 21); + if (((val >> 22) & 0x01) == 0) { + pr_info("Detected USB Device mode - Not supported!\n"); + netlogic_write_reg(usb_mmio, 0, 0x01000000); + return 0; + } + + pr_info("Detected USB Host mode - Adding XLS USB devices.\n"); + /* Clear reset, host mode */ + netlogic_write_reg(usb_mmio, 0, 0x02000000); + + /* Memory resource for various XLS usb ports */ + usb_mmio = netlogic_io_mmio(NETLOGIC_IO_USB_0_OFFSET); + memres = CPHYSADDR((unsigned long)usb_mmio); + xls_usb_ehci_device.resource[0].start = memres; + xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1; + + memres += 0x400; + xls_usb_ohci_device_0.resource[0].start = memres; + xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1; + + memres += 0x400; + xls_usb_ohci_device_1.resource[0].start = memres; + xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1; + + return platform_add_devices(xls_platform_devices, + ARRAY_SIZE(xls_platform_devices)); +} + +arch_initcall(xls_platform_usb_init); +#endif diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 78561d1..fde78c9 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1265,6 +1265,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER tegra_ehci_driver #endif +#ifdef CONFIG_NLM_XLR +#include "ehci-xls.c" +#define PLATFORM_DRIVER ehci_xls_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-xls.c b/drivers/usb/host/ehci-xls.c new file mode 100644 index 0000000..54467c6 --- /dev/null +++ b/drivers/usb/host/ehci-xls.c @@ -0,0 +1,170 @@ +/* + * OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 2011 Netlogic Microsystems Inc. + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * (C) Copyright 2002 Hewlett-Packard Company + * + * Bus Glue for AMD Alchemy Au1xxx + * + * Written by Christopher Hoover + * Based on fragments of previous driver by Rusell King et al. + * + * Modified for LH7A404 from ohci-sa1111.c + * by Durgesh Pattamatta + * Modified for AMD Alchemy Au1xxx + * by Matt Porter + * + * This file is licenced under the GPL. + */ + +#include + +static int ehci_xls_setup(struct usb_hcd *hcd) +{ + int retval; + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + + retval = ehci_halt(ehci); + if (retval) + return retval; + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + ehci_reset(ehci); + + return retval; +} + +int ehci_xls_probe_internal(const struct hc_driver *driver, + struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int retval, irq; + + /* Get our IRQ from an earlier registered Platform Resource */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + + /* Get our Memory Handle */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Error: MMIO Handle %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) { + retval = -ENOMEM; + goto err1; + } + + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + retval = -EBUSY; + goto err2; + } + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + + if (hcd->regs == NULL) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + retval = -EFAULT; + goto err3; + } + + retval = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (retval != 0) + goto err4; + return retval; + +err4: + iounmap(hcd->regs); +err3: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err2: + usb_put_hcd(hcd); +err1: + dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), + retval); + return retval; +} + +static struct hc_driver ehci_xls_hc_driver = { + .description = hcd_name, + .product_desc = "XLS EHCI Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_USB2 | HCD_MEMORY, + .reset = ehci_xls_setup, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_xls_probe(struct platform_device *pdev) +{ + if (usb_disabled()) + return -ENODEV; + + return ehci_xls_probe_internal(&ehci_xls_hc_driver, pdev); +} + +static int ehci_xls_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + return 0; +} + +MODULE_ALIAS("ehci-xls"); + +static struct platform_driver ehci_xls_driver = { + .probe = ehci_xls_probe, + .remove = ehci_xls_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ehci-xls", + }, +}; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index d557235..7b8c12b 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1105,6 +1105,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver #endif +#ifdef CONFIG_NLM_XLR +#include "ohci-xls.c" +#define PLATFORM_DRIVER ohci_xls_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ diff --git a/drivers/usb/host/ohci-xls.c b/drivers/usb/host/ohci-xls.c new file mode 100644 index 0000000..106d4f0 --- /dev/null +++ b/drivers/usb/host/ohci-xls.c @@ -0,0 +1,160 @@ +/* + * OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 2011 Netlogic Microsystems Inc. + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * (C) Copyright 2002 Hewlett-Packard Company + * + * Bus Glue for AMD Alchemy Au1xxx + * + * Written by Christopher Hoover + * Based on fragments of previous driver by Rusell King et al. + * + * Modified for LH7A404 from ohci-sa1111.c + * by Durgesh Pattamatta + * Modified for AMD Alchemy Au1xxx + * by Matt Porter + * + * This file is licenced under the GPL. + */ + +#include +#include + +static int ohci_xls_probe_internal(const struct hc_driver *driver, + struct platform_device *dev) +{ + struct resource *res; + struct usb_hcd *hcd; + int retval, irq; + + /* Get our IRQ from an earlier registered Platform Resource */ + irq = platform_get_irq(dev, 0); + if (irq < 0) { + dev_err(&dev->dev, "Found HC with no IRQ\n"); + return -ENODEV; + } + + /* Get our Memory Handle */ + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&dev->dev, "MMIO Handle incorrect!\n"); + return -ENODEV; + } + + hcd = usb_create_hcd(driver, &dev->dev, "XLS"); + if (!hcd) { + retval = -ENOMEM; + goto err1; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(&dev->dev, "Controller already in use\n"); + retval = -EBUSY; + goto err2; + } + + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (hcd->regs == NULL) { + dev_dbg(&dev->dev, "error mapping memory\n"); + retval = -EFAULT; + goto err3; + } + + retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (retval != 0) + goto err4; + return retval; + +err4: + iounmap(hcd->regs); +err3: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err2: + usb_put_hcd(hcd); +err1: + dev_err(&dev->dev, "init fail, %d\n", retval); + return retval; +} + +static int ohci_xls_reset(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + + ohci_hcd_init(ohci); + return ohci_init(ohci); +} + +static int __devinit ohci_xls_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci; + int ret; + + ohci = hcd_to_ohci(hcd); + ret = ohci_run(ohci); + if (ret < 0) { + err("can't start %s", hcd->self.bus_name); + ohci_stop(hcd); + return ret; + } + return 0; +} + +static struct hc_driver ohci_xls_hc_driver = { + .description = hcd_name, + .product_desc = "XLS OHCI Host Controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + .irq = ohci_irq, + .flags = HCD_MEMORY | HCD_USB11, + .reset = ohci_xls_reset, + .start = ohci_xls_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + .get_frame_number = ohci_get_frame, + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ohci_bus_suspend, + .bus_resume = ohci_bus_resume, +#endif + .start_port_reset = ohci_start_port_reset, +}; + +static int ohci_xls_probe(struct platform_device *dev) +{ + int ret; + + pr_debug("In ohci_xls_probe"); + if (usb_disabled()) + return -ENODEV; + ret = ohci_xls_probe_internal(&ohci_xls_hc_driver, dev); + return ret; +} + +static int ohci_xls_remove(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + return 0; +} + +static struct platform_driver ohci_xls_driver = { + .probe = ohci_xls_probe, + .remove = ohci_xls_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ohci-xls-0", + .owner = THIS_MODULE, + }, +}; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri Apr 22 18:56:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:56:55 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1342 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491117Ab1DVQzx (ORCPT ); Fri, 22 Apr 2011 18:55:53 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42e207d00016b79 ; Fri, 22 Apr 2011 09:55:35 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:55:54 -0700 Date: Fri, 22 Apr 2011 22:32:33 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 6/8] Add default configuration for XLR/XLS processors Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:55:54.0899 (UTC) FILETIME=[25027630:01CC010E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29792 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Enable XLR CPU support, SMP, initramfs based root filesystem etc. Signed-off-by: Jayachandran C --- arch/mips/configs/nlm_xlr_defconfig | 1705 +++++++++++++++++++++++++++++++++++ 1 files changed, 1705 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig new file mode 100644 index 0000000..a5a22f0 --- /dev/null +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -0,0 +1,1705 @@ +# +# Automatically generated make config: don't edit +# Linux/mips 2.6.39-rc1 Kernel Configuration +# Fri Apr 1 07:44:07 2011 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_NLM_XLR_BOARD=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_NLM_COMMON=y +CONFIG_NLM_XLR=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_FIND_BIT_LE=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYNC_R4K=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_XLR=y +CONFIG_SYS_HAS_CPU_XLR=y +CONFIG_WEAK_ORDERING=y +CONFIG_WEAK_REORDERING_BEYOND_LLSC=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_SMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_32=y +CONFIG_NR_CPUS=32 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_KEXEC=y +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +# CONFIG_EMBEDDED is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_VERBOSE is not set +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=m +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_IP_SET is not set +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +# CONFIG_IP_VS_PE_SIP is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +CONFIG_PHONET=m +CONFIG_IEEE802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_PARTITIONS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=y +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_SENSORS_LIS3LV02D is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FC_TGT_ATTRS=y +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +# CONFIG_ISCSI_BOOT_SYSFS is not set +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_N_HDLC=m +# CONFIG_N_GSM is not set +# CONFIG_DEVKMEM is not set +CONFIG_STALDRV=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XZ is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_MINIX_FS_NATIVE_ENDIAN=y +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_PSTORE is not set +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EXOFS_FS=m +# CONFIG_EXOFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_NEW_IDMAPPER is not set +CONFIG_NFSD=m +CONFIG_NFSD_DEPRECATED=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_ACL is not set +CONFIG_CIFS_EXPERIMENTAL=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +# CONFIG_NCPFS_SMALLDOS is not set +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +# CONFIG_AFS_DEBUG is not set +# CONFIG_AFS_FSCACHE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +# CONFIG_ACORN_PARTITION_CUMANA is not set +# CONFIG_ACORN_PARTITION_EESOX is not set +CONFIG_ACORN_PARTITION_ICS=y +# CONFIG_ACORN_PARTITION_ADFS is not set +# CONFIG_ACORN_PARTITION_POWERTEC is not set +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_DETECTOR_RUNNABLE=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +# CONFIG_KGDB_LOW_LEVEL_TRAP is not set +# CONFIG_KGDB_KDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_TOMOYO=y +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_IMA is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=m +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_VIRTUALIZATION is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Fri Apr 22 18:57:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 18:57:20 +0200 (CEST) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1518 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491123Ab1DVQzy (ORCPT ); Fri, 22 Apr 2011 18:55:54 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id e42e21a600016b7b ; Fri, 22 Apr 2011 09:55:35 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Apr 2011 09:56:37 -0700 Date: Fri, 22 Apr 2011 22:33:17 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 8/8] PCI support for XLR/XLS Message-ID: <326dfb7dab3c14b2c632db707bf033cdb44da926.1303487516.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 22 Apr 2011 16:56:38.0071 (UTC) FILETIME=[3EBDFC70:01CC010E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29793 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Adds pci/pci-xlr.c to support for XLR PCI/PCI-X interface and XLS PCIe interface. Update irq.c to ack PCI interrupts, use irq handler data to do the PCI/PCIe bus ack. Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/pci.h | 8 + arch/mips/include/asm/netlogic/xlr/xlr.h | 9 ++ arch/mips/netlogic/xlr/irq.c | 86 ++++++++++++- arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlr.c | 215 ++++++++++++++++++++++++++++++ 5 files changed, 318 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/pci.h create mode 100644 arch/mips/pci/pci-xlr.c diff --git a/arch/mips/include/asm/netlogic/pci.h b/arch/mips/include/asm/netlogic/pci.h new file mode 100644 index 0000000..6316bf4 --- /dev/null +++ b/arch/mips/include/asm/netlogic/pci.h @@ -0,0 +1,8 @@ +#ifndef _ASM_NLM_PCI_H +#define _ASM_NLM_PCI_H + +#define NLM_PCI_VENDOR_ID 0xfecc +#define NLM_PCI_UART_DEV_ID 2 +#define NLM_PCI_DUMMY_MAC_DEV_ID 16 + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h index 1cffd21..4d8b9e6 100644 --- a/arch/mips/include/asm/netlogic/xlr/xlr.h +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -41,6 +41,7 @@ unsigned int nlm_xlr_uart_in(struct uart_port *, int); void nlm_xlr_uart_out(struct uart_port *, int, int); /* SMP support functions */ +struct irq_desc; void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); int nlm_wakeup_secondary_cpus(u32 wakeup_mask); @@ -63,4 +64,12 @@ static inline unsigned int nlm_chip_is_xls(void) (prid & 0xf000) == 0xc000); } +/* XLS B silicon "Rook" */ +static inline unsigned int nlm_chip_is_xls_b(void) +{ + uint32_t prid = read_c0_prid(); + + return ((prid & 0xf000) == 0x4000); +} + #endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c index 2033f56..1446d58 100644 --- a/arch/mips/netlogic/xlr/irq.c +++ b/arch/mips/netlogic/xlr/irq.c @@ -83,14 +83,71 @@ static void xlr_pic_mask(struct irq_data *d) spin_unlock_irqrestore(&nlm_pic_lock, flags); } +#ifdef CONFIG_PCI +/* Extra ACK needed for XLR on chip PCI controller */ +static void xlr_pci_ack(struct irq_data *d) +{ + nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET); + + netlogic_read_reg(pci_mmio, (0x140 >> 2)); +} + +/* Extra ACK needed for XLS on chip PCIe controller */ +static void xls_pcie_ack(struct irq_data *d) +{ + nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET); + + switch (d->irq) { + case PIC_PCIE_LINK0_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK1_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK2_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK3_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff); + break; + } +} + +/* For XLS B silicon, the 3,4 PCI interrupts are different */ +static void xls_pcie_ack_b(struct irq_data *d) +{ + nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET); + + switch (d->irq) { + case PIC_PCIE_LINK0_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK1_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff); + break; + case PIC_PCIE_XLSB0_LINK2_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff); + break; + case PIC_PCIE_XLSB0_LINK3_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff); + break; + } +} +#endif + static void xlr_pic_ack(struct irq_data *d) { unsigned long flags; nlm_reg_t *mmio; int irq = d->irq; + void *hd = irq_data_get_irq_handler_data(d); WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + if (hd) { + void (*extra_ack)(void *) = hd; + extra_ack(d); + } mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); spin_lock_irqsave(&nlm_pic_lock, flags); netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); @@ -162,6 +219,33 @@ void __init init_xlr_irqs(void) nlm_irq_mask |= ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); #endif + +#ifdef CONFIG_PCI + /* + * For PCI interrupts, we need to ack the PIC controller too, overload + * irq handler data to do this + */ + if (nlm_chip_is_xls()) { + if (nlm_chip_is_xls_b()) { + irq_set_handler_data(PIC_PCIE_LINK0_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_LINK1_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, + xls_pcie_ack_b); + } else { + irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack); + } + } else { + /* XLR PCI controller ACK */ + irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack); + } +#endif /* unmask all PIC related interrupts. If no handler is installed by the * drivers, it'll just ack the interrupt and return */ @@ -199,7 +283,7 @@ asmlinkage void plat_irq_dispatch(void) return; } - /* TODO use dcltz: optimize below code */ + /* use dcltz: optimize below code */ for (i = 63; i != -1; i--) { if (eirr & (1ULL << i)) break; diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c9209ca..f0d5329 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o +obj-$(CONFIG_NLM_XLR) += pci-xlr.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c new file mode 100644 index 0000000..66d77f7 --- /dev/null +++ b/arch/mips/pci/pci-xlr.c @@ -0,0 +1,215 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +static void *pci_config_base; + +#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) + +/* PCI ops */ +static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, + int where) +{ + u32 data; + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + data = *cfgaddr; + return cpu_to_le32(data); +} + +static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, + int where, u32 data) +{ + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + *cfgaddr = cpu_to_le32(data); +} + +static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + + +static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + pci_cfg_write_32bit(bus, devfn, where, data); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops nlm_pci_ops = { + .read = nlm_pcibios_read, + .write = nlm_pcibios_write +}; + +static struct resource nlm_pci_mem_resource = { + .name = "XLR PCI MEM", + .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ + .end = 0xdfffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource nlm_pci_io_resource = { + .name = "XLR IO MEM", + .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ + .end = 0x100fffffUL, + .flags = IORESOURCE_IO, +}; + +struct pci_controller nlm_pci_controller = { + .index = 0, + .pci_ops = &nlm_pci_ops, + .mem_resource = &nlm_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &nlm_pci_io_resource, + .io_offset = 0x00000000UL, +}; + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if (!nlm_chip_is_xls()) + return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ + + /* + * For XLS PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + if (dev->bus->self == NULL) + return 0; + + switch (dev->bus->self->devfn) { + case 0x0: + return PIC_PCIE_LINK0_IRQ; + case 0x8: + return PIC_PCIE_LINK1_IRQ; + case 0x10: + if (nlm_chip_is_xls_b()) + return PIC_PCIE_XLSB0_LINK2_IRQ; + else + return PIC_PCIE_LINK2_IRQ; + case 0x18: + if (nlm_chip_is_xls_b()) + return PIC_PCIE_XLSB0_LINK3_IRQ; + else + return PIC_PCIE_LINK3_IRQ; + } + WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); + return 0; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static int __init pcibios_init(void) +{ + /* PSB assigns PCI resources */ + pci_probe_only = 1; + pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); + + /* Extend IO port for memory mapped io */ + ioport_resource.start = 0; + ioport_resource.end = ~0; + + set_io_port_base(CKSEG1); + nlm_pci_controller.io_map_base = CKSEG1; + + pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); + register_pci_controller(&nlm_pci_controller); + + return 0; +} + +arch_initcall(pcibios_init); + +struct pci_fixup pcibios_fixups[] = { + {0} +}; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From manuel.lauss@googlemail.com Fri Apr 22 19:03:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 22 Apr 2011 19:03:34 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:45644 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491097Ab1DVRD3 convert rfc822-to-8bit (ORCPT ); Fri, 22 Apr 2011 19:03:29 +0200 Received: by wyb28 with SMTP id 28so694556wyb.36 for ; Fri, 22 Apr 2011 10:03:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Uvn0J8RURnZGmjUVnLXbpYW35ZB2STd/i7SSpHC8eGo=; b=Uoo2S1TJ+/cBoXSevz59K83byKMROnZ3LyILzwgeJymp7jKx1uX8WYAcLNGWuLMrVK SQYxVxjETne0p/PDcUiYgDejhAD/b1QvlwAMWe0eGVG9TbDN79CfUxjxopJ0vgbhuuzF 4rhuFyFQ1tE8DgxgAua4lgWKZHqum0TWwKmCU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=JDPhN7dfA2Ck/yAzdDDPpurwOuNlmrwXnLlTLrkvzbra0HShb9N1oq/6csKMbPr/au lBbIblBr0neTA8klQGXpBpwaMobKEeXUnjBuzob+FeI7WqJj0tgMGz+IONxeOjKLURgS 84XnY46dhXKSPNoj64FolHNaElJo6u1naj4T0= MIME-Version: 1.0 Received: by 10.216.239.65 with SMTP id b43mr1309864wer.29.1303491803907; Fri, 22 Apr 2011 10:03:23 -0700 (PDT) Received: by 10.216.46.74 with HTTP; Fri, 22 Apr 2011 10:03:23 -0700 (PDT) In-Reply-To: <21ae06c6f50f7a770b62d61265e6f509f37d1762.1303487516.git.jayachandranc@netlogicmicro.com> References: <21ae06c6f50f7a770b62d61265e6f509f37d1762.1303487516.git.jayachandranc@netlogicmicro.com> Date: Fri, 22 Apr 2011 19:03:23 +0200 Message-ID: Subject: Re: [PATCH 7/8] USB support for XLS platforms. From: Manuel Lauss To: Jayachandran C Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29794 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Hi, On Fri, Apr 22, 2011 at 7:02 PM, Jayachandran C wrote: > update ehci-hcd.c and ohci-hcd.c to add XLS hcds > add ehci/ohci devices to XLR/XLS platform driver > Kconfig update > > Signed-off-by: Jayachandran C > --- >  arch/mips/Kconfig                        |    2 + >  arch/mips/include/asm/netlogic/xlr/xlr.h |   12 ++ >  arch/mips/netlogic/xlr/platform.c        |   91 ++++++++++++++++ >  drivers/usb/host/ehci-hcd.c              |    5 + >  drivers/usb/host/ehci-xls.c              |  170 ++++++++++++++++++++++++++++++ >  drivers/usb/host/ohci-hcd.c              |    5 + >  drivers/usb/host/ohci-xls.c              |  160 ++++++++++++++++++++++++++++ >  7 files changed, 445 insertions(+), 0 deletions(-) >  create mode 100644 drivers/usb/host/ehci-xls.c >  create mode 100644 drivers/usb/host/ohci-xls.c > diff --git a/drivers/usb/host/ehci-xls.c b/drivers/usb/host/ehci-xls.c > new file mode 100644 > index 0000000..54467c6 > --- /dev/null > +++ b/drivers/usb/host/ehci-xls.c > @@ -0,0 +1,170 @@ > +/* > + * OHCI HCD (Host Controller Driver) for USB. > + * > + * (C) Copyright 2011 Netlogic Microsystems Inc. > + * (C) Copyright 1999 Roman Weissgaerber > + * (C) Copyright 2000-2002 David Brownell > + * (C) Copyright 2002 Hewlett-Packard Company > + * > + * Bus Glue for AMD Alchemy Au1xxx > + * Written by Christopher Hoover > + * Based on fragments of previous driver by Rusell King et al. > + * > + * Modified for LH7A404 from ohci-sa1111.c > + *  by Durgesh Pattamatta > + * Modified for AMD Alchemy Au1xxx > + *  by Matt Porter > + * > + * This file is licenced under the GPL. > + */ Please correct the comments! I also think that most of the people which are attributed here should be removed. Perhaps simply state which file you used for inspiration? ("derived from ohci-whatever.c"). Manuel From wuzhangjin@gmail.com Sat Apr 23 23:57:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 23 Apr 2011 23:57:28 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:60412 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491198Ab1DWV5X (ORCPT ); Sat, 23 Apr 2011 23:57:23 +0200 Received: by pwi8 with SMTP id 8so872149pwi.36 for ; Sat, 23 Apr 2011 14:57:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=KQqnBW5MpAvzVyAes1a/IXzomYv59NHyU2apFqBJvBI=; b=IhlmDgdQdtGlAfnxWWYN3OEY5PiSPzl0M42d87t1Djxh5ottiXE16R0wLnStry3cp8 MQGdVGgZpcp3JYWJDdyQJ609aNxqwgEBbHPA3BLyapYvjZMo1Sd0Cnxj4TL9miC5XlUG wMx9hYp4i+AnuzkBpaharFDduYzfVT3M7Dg/s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=wVw2fDYmKMWLrfbZ9dUzDYPXAgKJyxTWYz0BSN2nYlcD8VbzwwW71S1dVeoobHypZN HExWULlC8e4xxNcgGsHv5sGvJbwwYwCBPQxv/Pjz0X+Dv3bnkaO/UpVeAEKjb5AYv1zl iws3woDEfbmSJZNGWOrBd5QsnITq7hI4Cl0Cc= Received: by 10.68.2.1 with SMTP id 1mr4025742pbq.102.1303595833461; Sat, 23 Apr 2011 14:57:13 -0700 (PDT) Received: from localhost.localdomain ([123.113.111.220]) by mx.google.com with ESMTPS id i4sm2357428pbr.42.2011.04.23.14.57.10 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 23 Apr 2011 14:57:12 -0700 (PDT) From: Wu Zhangjin To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, Wu Zhangjin Subject: [PATCH] MIPS: Hibernation: Fixes for PAGE_SIZE >= 64kb Date: Sun, 24 Apr 2011 05:56:59 +0800 Message-Id: <1303595819-19299-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29795 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips PAGE_SIZE >= 64kb (1 << 16) is too big to be the immediate of the addiu/daddiu instruction, so, use addu/daddu instruction instead. The following compiling error is fixed: AS arch/mips/power/hibernate.o arch/mips/power/hibernate.S: Assembler messages: arch/mips/power/hibernate.S:38: Error: expression out of range make[2]: *** [arch/mips/power/hibernate.o] Error 1 make[1]: *** [arch/mips/power] Error 2 Reported-by: Roman Mamedov Signed-off-by: Wu Zhangjin --- arch/mips/power/hibernate.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S index dbb5c7b..f8a751c 100644 --- a/arch/mips/power/hibernate.S +++ b/arch/mips/power/hibernate.S @@ -35,7 +35,7 @@ LEAF(swsusp_arch_resume) 0: PTR_L t1, PBE_ADDRESS(t0) /* source */ PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */ - PTR_ADDIU t3, t1, PAGE_SIZE + PTR_ADDU t3, t1, PAGE_SIZE 1: REG_L t8, (t1) REG_S t8, (t2) -- 1.7.1 From jayachandranc@netlogicmicro.com Mon Apr 25 12:51:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 25 Apr 2011 12:51:28 +0200 (CEST) Received: from [12.203.210.36] ([12.203.210.36]:2179 "EHLO orion5.netlogicmicro.com" rhost-flags-FAIL-FAIL-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490954Ab1DYKvT (ORCPT ); Mon, 25 Apr 2011 12:51:19 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id f25364300001a04a ; Mon, 25 Apr 2011 03:50:58 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 25 Apr 2011 03:52:14 -0700 Date: Mon, 25 Apr 2011 16:21:05 +0530 From: "Jayachandran C." To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Manuel Lauss Subject: Re: [PATCH 7/8] USB support for XLS platforms. Message-ID: <20110425105105.GA14277@jayachandranc.netlogicmicro.com> References: <21ae06c6f50f7a770b62d61265e6f509f37d1762.1303487516.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 25 Apr 2011 10:52:14.0767 (UTC) FILETIME=[D66FCBF0:01CC0336] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29796 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips On Fri, Apr 22, 2011 at 07:03:23PM +0200, Manuel Lauss wrote: > On Fri, Apr 22, 2011 at 7:02 PM, Jayachandran C > wrote: > > update ehci-hcd.c and ohci-hcd.c to add XLS hcds > > add ehci/ohci devices to XLR/XLS platform driver > > Kconfig update > > > > Signed-off-by: Jayachandran C > > --- > >  arch/mips/Kconfig                        |    2 + > >  arch/mips/include/asm/netlogic/xlr/xlr.h |   12 ++ > >  arch/mips/netlogic/xlr/platform.c        |   91 ++++++++++++++++ > >  drivers/usb/host/ehci-hcd.c              |    5 + > >  drivers/usb/host/ehci-xls.c              |  170 ++++++++++++++++++++++++++++++ > >  drivers/usb/host/ohci-hcd.c              |    5 + > >  drivers/usb/host/ohci-xls.c              |  160 ++++++++++++++++++++++++++++ > >  7 files changed, 445 insertions(+), 0 deletions(-) > >  create mode 100644 drivers/usb/host/ehci-xls.c > >  create mode 100644 drivers/usb/host/ohci-xls.c > > diff --git a/drivers/usb/host/ehci-xls.c b/drivers/usb/host/ehci-xls.c > > new file mode 100644 > > index 0000000..54467c6 > > --- /dev/null > > +++ b/drivers/usb/host/ehci-xls.c > > @@ -0,0 +1,170 @@ > > +/* > > + * OHCI HCD (Host Controller Driver) for USB. > > + * > > + * (C) Copyright 2011 Netlogic Microsystems Inc. > > + * (C) Copyright 1999 Roman Weissgaerber > > + * (C) Copyright 2000-2002 David Brownell > > + * (C) Copyright 2002 Hewlett-Packard Company > > + * > > + * Bus Glue for AMD Alchemy Au1xxx > > + * Written by Christopher Hoover > > + * Based on fragments of previous driver by Rusell King et al. > > + * > > + * Modified for LH7A404 from ohci-sa1111.c > > + *  by Durgesh Pattamatta > > + * Modified for AMD Alchemy Au1xxx > > + *  by Matt Porter > > + * > > + * This file is licenced under the GPL. > > + */ > > Please correct the comments! I also think that most of the people > which are attributed > here should be removed. Perhaps simply state which file you used for > inspiration? > ("derived from ohci-whatever.c"). I will post a new version of the PCI and USB support patches, with this and another minor change. Thanks, JC. From jayachandranc@netlogicmicro.com Mon Apr 25 13:21:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 25 Apr 2011 13:21:37 +0200 (CEST) Received: from [12.203.210.36] ([12.203.210.36]:2711 "EHLO orion5.netlogicmicro.com" rhost-flags-FAIL-FAIL-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490954Ab1DYLVb (ORCPT ); Mon, 25 Apr 2011 13:21:31 +0200 X-TM-IMSS-Message-ID: Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id f26f0add0001a0ea ; Mon, 25 Apr 2011 04:21:10 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 25 Apr 2011 04:22:26 -0700 Date: Mon, 25 Apr 2011 16:51:21 +0530 From: "Jayachandran C." To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 7/8, UPDATED] PCI support for XLR/XLS Message-ID: <20110425112119.GB14277@jayachandranc.netlogicmicro.com> References: <21ae06c6f50f7a770b62d61265e6f509f37d1762.1303487516.git.jayachandranc@netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <21ae06c6f50f7a770b62d61265e6f509f37d1762.1303487516.git.jayachandranc@netlogicmicro.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 25 Apr 2011 11:22:26.0678 (UTC) FILETIME=[0E6B7960:01CC033B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Adds pci/pci-xlr.c to support for XLR PCI/PCI-X interface and XLS PCIe interface. Update irq.c to ack PCI interrupts, use irq handler data to do the PCI/PCIe bus ack. Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/xlr/xlr.h | 21 +++ arch/mips/netlogic/xlr/irq.c | 86 ++++++++++++- arch/mips/pci/Makefile | 1 + arch/mips/pci/pci-xlr.c | 214 ++++++++++++++++++++++++++++++ 4 files changed, 321 insertions(+), 1 deletions(-) create mode 100644 arch/mips/pci/pci-xlr.c diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h index 454c236..3e63726 100644 --- a/arch/mips/include/asm/netlogic/xlr/xlr.h +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -41,6 +41,7 @@ unsigned int nlm_xlr_uart_in(struct uart_port *, int); void nlm_xlr_uart_out(struct uart_port *, int, int); /* SMP support functions */ +struct irq_desc; void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); int nlm_wakeup_secondary_cpus(u32 wakeup_mask); @@ -51,4 +52,24 @@ void prom_pre_boot_secondary_cpus(void); extern struct plat_smp_ops nlm_smp_ops; extern unsigned long nlm_common_ebase; +/* XLS B silicon "Rook" */ +static inline unsigned int nlm_chip_is_xls_b(void) +{ + uint32_t prid = read_c0_prid(); + + return ((prid & 0xf000) == 0x4000); +} + +/* + * XLR chip types + */ + /* The XLS product line has chip versions 0x[48c]? */ +static inline unsigned int nlm_chip_is_xls(void) +{ + uint32_t prid = read_c0_prid(); + + return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 || + (prid & 0xf000) == 0xc000); +} + #endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c index 2033f56..1446d58 100644 --- a/arch/mips/netlogic/xlr/irq.c +++ b/arch/mips/netlogic/xlr/irq.c @@ -83,14 +83,71 @@ static void xlr_pic_mask(struct irq_data *d) spin_unlock_irqrestore(&nlm_pic_lock, flags); } +#ifdef CONFIG_PCI +/* Extra ACK needed for XLR on chip PCI controller */ +static void xlr_pci_ack(struct irq_data *d) +{ + nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET); + + netlogic_read_reg(pci_mmio, (0x140 >> 2)); +} + +/* Extra ACK needed for XLS on chip PCIe controller */ +static void xls_pcie_ack(struct irq_data *d) +{ + nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET); + + switch (d->irq) { + case PIC_PCIE_LINK0_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK1_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK2_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK3_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff); + break; + } +} + +/* For XLS B silicon, the 3,4 PCI interrupts are different */ +static void xls_pcie_ack_b(struct irq_data *d) +{ + nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET); + + switch (d->irq) { + case PIC_PCIE_LINK0_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff); + break; + case PIC_PCIE_LINK1_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff); + break; + case PIC_PCIE_XLSB0_LINK2_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff); + break; + case PIC_PCIE_XLSB0_LINK3_IRQ: + netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff); + break; + } +} +#endif + static void xlr_pic_ack(struct irq_data *d) { unsigned long flags; nlm_reg_t *mmio; int irq = d->irq; + void *hd = irq_data_get_irq_handler_data(d); WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq); + if (hd) { + void (*extra_ack)(void *) = hd; + extra_ack(d); + } mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); spin_lock_irqsave(&nlm_pic_lock, flags); netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); @@ -162,6 +219,33 @@ void __init init_xlr_irqs(void) nlm_irq_mask |= ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); #endif + +#ifdef CONFIG_PCI + /* + * For PCI interrupts, we need to ack the PIC controller too, overload + * irq handler data to do this + */ + if (nlm_chip_is_xls()) { + if (nlm_chip_is_xls_b()) { + irq_set_handler_data(PIC_PCIE_LINK0_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_LINK1_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ, + xls_pcie_ack_b); + irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, + xls_pcie_ack_b); + } else { + irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack); + irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack); + } + } else { + /* XLR PCI controller ACK */ + irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack); + } +#endif /* unmask all PIC related interrupts. If no handler is installed by the * drivers, it'll just ack the interrupt and return */ @@ -199,7 +283,7 @@ asmlinkage void plat_irq_dispatch(void) return; } - /* TODO use dcltz: optimize below code */ + /* use dcltz: optimize below code */ for (i = 63; i != -1; i--) { if (eirr & (1ULL << i)) break; diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c9209ca..f0d5329 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o +obj-$(CONFIG_NLM_XLR) += pci-xlr.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c new file mode 100644 index 0000000..38fece1 --- /dev/null +++ b/arch/mips/pci/pci-xlr.c @@ -0,0 +1,214 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +static void *pci_config_base; + +#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) + +/* PCI ops */ +static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, + int where) +{ + u32 data; + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + data = *cfgaddr; + return cpu_to_le32(data); +} + +static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, + int where, u32 data) +{ + u32 *cfgaddr; + + cfgaddr = (u32 *)(pci_config_base + + pci_cfg_addr(bus->number, devfn, where & ~3)); + *cfgaddr = cpu_to_le32(data); +} + +static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + + +static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = pci_cfg_read_32bit(bus, devfn, where); + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + pci_cfg_write_32bit(bus, devfn, where, data); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops nlm_pci_ops = { + .read = nlm_pcibios_read, + .write = nlm_pcibios_write +}; + +static struct resource nlm_pci_mem_resource = { + .name = "XLR PCI MEM", + .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ + .end = 0xdfffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource nlm_pci_io_resource = { + .name = "XLR IO MEM", + .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ + .end = 0x100fffffUL, + .flags = IORESOURCE_IO, +}; + +struct pci_controller nlm_pci_controller = { + .index = 0, + .pci_ops = &nlm_pci_ops, + .mem_resource = &nlm_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &nlm_pci_io_resource, + .io_offset = 0x00000000UL, +}; + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if (!nlm_chip_is_xls()) + return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ + + /* + * For XLS PCIe, there is an IRQ per Link, find out which + * link the device is on to assign interrupts + */ + if (dev->bus->self == NULL) + return 0; + + switch (dev->bus->self->devfn) { + case 0x0: + return PIC_PCIE_LINK0_IRQ; + case 0x8: + return PIC_PCIE_LINK1_IRQ; + case 0x10: + if (nlm_chip_is_xls_b()) + return PIC_PCIE_XLSB0_LINK2_IRQ; + else + return PIC_PCIE_LINK2_IRQ; + case 0x18: + if (nlm_chip_is_xls_b()) + return PIC_PCIE_XLSB0_LINK3_IRQ; + else + return PIC_PCIE_LINK3_IRQ; + } + WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); + return 0; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static int __init pcibios_init(void) +{ + /* PSB assigns PCI resources */ + pci_probe_only = 1; + pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); + + /* Extend IO port for memory mapped io */ + ioport_resource.start = 0; + ioport_resource.end = ~0; + + set_io_port_base(CKSEG1); + nlm_pci_controller.io_map_base = CKSEG1; + + pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); + register_pci_controller(&nlm_pci_controller); + + return 0; +} + +arch_initcall(pcibios_init); + +struct pci_fixup pcibios_fixups[] = { + {0} +}; -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) From jayachandranc@netlogicmicro.com Mon Apr 25 13:23:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 25 Apr 2011 13:23:31 +0200 (CEST) Received: from [12.203.210.36] ([12.203.210.36]:3272 "EHLO orion5.netlogicmicro.com" rhost-flags-FAIL-FAIL-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490954Ab