From mcuelenaere@gmail.com Tue Mar 1 00:20:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 00:20:13 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:61250 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491930Ab1B1XUK (ORCPT ); Tue, 1 Mar 2011 00:20:10 +0100 Received: by eyh6 with SMTP id 6so1427099eyh.36 for ; Mon, 28 Feb 2011 15:20:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:to:cc:from:subject; bh=wcOcApCsYHqet0aED2yEfDQQeEdaTtfnRNBHe2279T0=; b=Qs41YrDZ4HGQzvGwvtsQhUd4nuRui9e2Cezu3xM/xmE+2WyMRqL8nm0E9KHEZnNTYy LDfZsNftqaqReolw3ButfQrUzlSBk8Js0Ko6EPSDETpBNqyn1XfZwWLzF55PfeJeJQtC 7txJPguj2rFTPF1A0geOqKwjB1GhQBoVI6M4g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:to:cc:from:subject; b=BYeDtvyEsL/XKLsKHWenkeKOhHq/0HhidpmOwAmvgNkLF+Fl6EnDtWTZEJ1fW7pxol EWp7S0bTF7YJWwViL+n0n6kqzdOZi1cM4yexolDYAv+BGLZO51psyOIaQGsB0dvNVyhR 2WZ8SMoVMPjaE2ehDQhqj4UxNyNORd3ofwm3Y= Received: by 10.14.45.75 with SMTP id o51mr4258163eeb.49.1298935203892; Mon, 28 Feb 2011 15:20:03 -0800 (PST) Received: from maurus-desktop (78-22-96-2.access.telenet.be [78.22.96.2]) by mx.google.com with ESMTPS id b52sm3612265eei.13.2011.02.28.15.20.02 (version=SSLv3 cipher=OTHER); Mon, 28 Feb 2011 15:20:03 -0800 (PST) Message-ID: <4d6c2da3.cc7e0e0a.2116.ffffde18@mx.google.com> Received: by maurus-desktop (sSMTP sendmail emulation); Tue, 1 Mar 2011 00:20:01 +0100 Date: Tue, 1 Mar 2011 00:20:01 +0100 To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Ralf Baechle From: Maurus Cuelenaere Subject: [PATCH] MIPS: Jz4740: Add HAVE_CLK Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29299 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcuelenaere@gmail.com Precedence: bulk X-list: linux-mips Jz4740 supports the clock framework but doesn't have HAVE_CLK defined, so define it! Signed-off-by: Maurus Cuelenaere --- arch/mips/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f5ecc05..6199128 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -208,6 +208,7 @@ config MACH_JZ4740 select ARCH_REQUIRE_GPIOLIB select SYS_HAS_EARLY_PRINTK select HAVE_PWM + select HAVE_CLK config LASAT bool "LASAT Networks platforms" -- 1.7.4 From Yang.Shi@windriver.com Tue Mar 1 09:06:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 09:06:52 +0100 (CET) Received: from mail.windriver.com ([147.11.1.11]:55736 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490960Ab1CAIGt (ORCPT ); Tue, 1 Mar 2011 09:06:49 +0100 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id p2186eSU021498; Tue, 1 Mar 2011 00:06:40 -0800 (PST) Received: from [128.224.162.190] ([128.224.162.190]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 1 Mar 2011 00:06:39 -0800 Message-ID: <4D6CA90D.10609@windriver.com> Date: Tue, 01 Mar 2011 16:06:37 +0800 From: Yang Shi User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: Himanshu Chauhan CC: "Kevin D. Kissell" , linux-mips Subject: Re: Kernel link address assumption References: <4D669FCE.8000601@nulltrace.org> <4D66A08F.7050605@paralogos.com> <4D66A1AC.2090007@nulltrace.org> In-Reply-To: <4D66A1AC.2090007@nulltrace.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 01 Mar 2011 08:06:39.0993 (UTC) FILETIME=[98215690:01CBD7E7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29300 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yang.shi@windriver.com Precedence: bulk X-list: linux-mips Himanshu Chauhan 写道: > On Thursday 24 February 2011 11:46 PM, Kevin D. Kissell wrote: > >> On 02/24/11 10:13, Himanshu Chauhan wrote: >> >>> Hi, >>> >>> Does Linux kernel for MIPS assumes that its link address is always in >>> Kseg0? >>> What if I change the link address to somewhere in useg? >>> > > >> Your page fault handlers will be in for an interesting time. ;o) >> >> What you describe can be, and is done, for virtualized kernels running >> on top >> of a hypervisor, but there's a bit more involved than just changing >> the link address. >> > Hi Kevin, > > You just caught that. Thats what I am trying to evaluate. What all I > would need to do apart from changing the link address. I am working on a > bare metal hypervisor for MIPS architecture. > You need setup suitable TLB mappings for Linux kernel in bootloader or Hypervisor. Yang > Any pointers? > > Regards > Himanshu > > > > From lars@metafoo.de Tue Mar 1 10:16:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 10:16:39 +0100 (CET) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:44034 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491004Ab1CAJQf (ORCPT ); Tue, 1 Mar 2011 10:16:35 +0100 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 9F3ADC38; Tue, 1 Mar 2011 10:16:29 +0100 (CET) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id skVypyW5XrdL; Tue, 1 Mar 2011 10:16:29 +0100 (CET) Received: from [192.168.123.148] (e177168005.adsl.alicedsl.de [85.177.168.5]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id AC66FC37; Tue, 1 Mar 2011 10:16:28 +0100 (CET) Message-ID: <4D6CB9C4.8000609@metafoo.de> Date: Tue, 01 Mar 2011 10:17:56 +0100 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20101226 Icedove/3.0.11 MIME-Version: 1.0 To: Maurus Cuelenaere CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: Re: [PATCH] MIPS: Jz4740: Add HAVE_CLK References: <4d6c2da3.cc7e0e0a.2116.ffffde18@mx.google.com> In-Reply-To: <4d6c2da3.cc7e0e0a.2116.ffffde18@mx.google.com> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29301 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips On 03/01/2011 12:20 AM, Maurus Cuelenaere wrote: > Jz4740 supports the clock framework but doesn't have HAVE_CLK defined, so define > it! > > Signed-off-by: Maurus Cuelenaere Acked-by: Lars-Peter Clausen > --- > arch/mips/Kconfig | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index f5ecc05..6199128 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -208,6 +208,7 @@ config MACH_JZ4740 > select ARCH_REQUIRE_GPIOLIB > select SYS_HAS_EARLY_PRINTK > select HAVE_PWM > + select HAVE_CLK > > config LASAT > bool "LASAT Networks platforms" From blogic@openwrt.org Tue Mar 1 17:12:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:12:35 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51010 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491822Ab1CAQM2 (ORCPT ); Tue, 1 Mar 2011 17:12:28 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 02/10] MIPS: lantiq: add SoC specific code for XWAY family Date: Tue, 1 Mar 2011 17:13:18 +0100 Message-Id: <1298996006-15960-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29302 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Add support for the Lantiq XWAY family of Mips24KEc SoCs. * Danube (PSB50702) * Twinpass (PSB4000) * AR9 (PSB50802) * Amazon SE (PSB5061) The Amazon SE is a lightweight SoC and has no PCI as well as a different clock. We split the code out into seperate files to handle this. The GPIO pins on the SoCs are multi function and there are several bits we can use to configure the pins. To be as compatible as possible to GPIOLIB we add a function int lq_gpio_request(unsigned int pin, unsigned int alt0, unsigned int alt1, unsigned int dir, const char *name); which lets you configure the 2 "alternate function" bits. This way drivers like PCI can make use of GPIOLIB without a cubersome wrapper. The pll code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was taken from a 2.4.20 source tree and was never really changed by me since then. Changes in V2 * properly ioremap all register regions and provide accessor macros (pmu,ebu,cgu) * add handling for EXIN irq sources * small cleanups Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- arch/mips/Kconfig | 1 + arch/mips/include/asm/mach-lantiq/xway/irq.h | 18 ++ .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 62 ++++++ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 145 +++++++++++++ arch/mips/lantiq/Kconfig | 21 ++ arch/mips/lantiq/Makefile | 2 + arch/mips/lantiq/Platform | 1 + arch/mips/lantiq/xway/Makefile | 4 + arch/mips/lantiq/xway/clk-ase.c | 52 +++++ arch/mips/lantiq/xway/clk-xway.c | 224 ++++++++++++++++++++ arch/mips/lantiq/xway/ebu.c | 36 +++ arch/mips/lantiq/xway/gpio.c | 195 +++++++++++++++++ arch/mips/lantiq/xway/pmu.c | 57 +++++ arch/mips/lantiq/xway/prom-ase.c | 40 ++++ arch/mips/lantiq/xway/prom-xway.c | 55 +++++ arch/mips/lantiq/xway/reset.c | 67 ++++++ 16 files changed, 980 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/xway/irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h create mode 100644 arch/mips/lantiq/Kconfig create mode 100644 arch/mips/lantiq/xway/Makefile create mode 100644 arch/mips/lantiq/xway/clk-ase.c create mode 100644 arch/mips/lantiq/xway/clk-xway.c create mode 100644 arch/mips/lantiq/xway/ebu.c create mode 100644 arch/mips/lantiq/xway/gpio.c create mode 100644 arch/mips/lantiq/xway/pmu.c create mode 100644 arch/mips/lantiq/xway/prom-ase.c create mode 100644 arch/mips/lantiq/xway/prom-xway.c create mode 100644 arch/mips/lantiq/xway/reset.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f975932..756e67a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -758,6 +758,7 @@ source "arch/mips/ath79/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" +source "arch/mips/lantiq/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/powertv/Kconfig" diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h new file mode 100644 index 0000000..a1471d2 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef __LANTIQ_IRQ_H +#define __LANTIQ_IRQ_H + +#include + +#define NR_IRQS 256 + +#include_next + +#endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h new file mode 100644 index 0000000..5c81c98 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -0,0 +1,62 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LANTIQ_XWAY_IRQ_H__ +#define _LANTIQ_XWAY_IRQ_H__ + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) +#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) +#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) + +#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15) +#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14) +#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16) + +#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) +#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23) + +#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) +#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22) +#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) + +#define MIPS_CPU_TIMER_IRQ 7 + +#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) +#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) +#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) +#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) +#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) +#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) +#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) +#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) +#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) +#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) +#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) +#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) +#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) +#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) +#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) +#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) +#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) +#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) +#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) +#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) + +#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) + +#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) + +#endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h new file mode 100644 index 0000000..f410948 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -0,0 +1,145 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifdef CONFIG_SOC_TYPE_XWAY + +#ifndef _LTQ_XWAY_H__ +#define _LTQ_XWAY_H__ + +#include + +/* Chip IDs */ +#define SOC_ID_DANUBE1 0x129 +#define SOC_ID_DANUBE2 0x12B +#define SOC_ID_TWINPASS 0x12D +#define SOC_ID_AMAZON_SE 0x152 +#define SOC_ID_ARX188 0x16C +#define SOC_ID_ARX168 0x16D +#define SOC_ID_ARX182 0x16F + +/* SoC Types */ +#define SOC_TYPE_DANUBE 0x01 +#define SOC_TYPE_TWINPASS 0x02 +#define SOC_TYPE_AR9 0x03 +#define SOC_TYPE_VR9 0x04 +#define SOC_TYPE_AMAZON_SE 0x05 + +/* ASC0/1 - serial port */ +#define LTQ_ASC0_BASE_ADDR 0x1E100400 +#define LTQ_ASC1_BASE_ADDR 0x1E100C00 +#define LTQ_ASC_SIZE 0x400 + +/* RCU - reset control unit */ +#define LTQ_RCU_BASE_ADDR 0x1F203000 +#define LTQ_RCU_SIZE 0x1000 + +/* GPTU - general purpose timer unit */ +#define LTQ_GPTU_BASE_ADDR 0x18000300 + +/* EBU - external bus unit */ +#define LTQ_EBU_GPIO_START 0x14000000 +#define LTQ_EBU_GPIO_SIZE 0x1000 + +#define LTQ_EBU_BASE_ADDR 0x1E105300 +#define LTQ_EBU_SIZE 0x100 + +#define LTQ_EBU_BUSCON0 0x0060 +#define LTQ_EBU_PCC_CON 0x0090 +#define LTQ_EBU_PCC_IEN 0x00A4 +#define LTQ_EBU_PCC_ISTAT 0x00A0 +#define LTQ_EBU_BUSCON1 0x0064 +#define LTQ_EBU_ADDRSEL1 0x0024 +#define EBU_WRDIS 0x80000000 + +/* CGU - clock generation unit */ +#define LTQ_CGU_BASE_ADDR 0x1F103000 +#define LTQ_CGU_SIZE 0x1000 + +/* ICU - interrupt control unit */ +#define LTQ_ICU_BASE_ADDR 0x1F880200 +#define LTQ_ICU_SIZE 0x100 + +/* EIU - external interrupt unit */ +#define LTQ_EIU_BASE_ADDR 0x1F101000 +#define LTQ_EIU_SIZE 0x1000 + +/* PMU - power management unit */ +#define LTQ_PMU_BASE_ADDR 0x1F102000 +#define LTQ_PMU_SIZE 0x1000 + +#define PMU_DMA 0x0020 +#define PMU_USB 0x8041 +#define PMU_LED 0x0800 +#define PMU_GPT 0x1000 +#define PMU_PPE 0x2000 +#define PMU_FPI 0x4000 +#define PMU_SWITCH 0x10000000 + +/* ETOP - ethernet */ +#define LTQ_PPE32_BASE_ADDR 0xBE180000 +#define LTQ_PPE32_SIZE 0x40000 + +/* DMA */ +#define LTQ_DMA_BASE_ADDR 0xBE104100 + +/* PCI */ +#define PCI_CR_BASE_ADDR 0x1E105400 +#define PCI_CR_SIZE 0x400 + +/* WDT */ +#define LTQ_WDT_BASE_ADDR 0x1F880000 +#define LTQ_WDT_SIZE 0x400 + +/* STP - serial to parallel conversion unit */ +#define LTQ_STP_BASE_ADDR 0x1E100BB0 +#define LTQ_STP_SIZE 0x40 + +/* GPIO */ +#define LTQ_GPIO0_BASE_ADDR 0x1E100B10 +#define LTQ_GPIO1_BASE_ADDR 0x1E100B40 +#define LTQ_GPIO2_BASE_ADDR 0x1E100B70 +#define LTQ_GPIO_SIZE 0x30 + +/* SSC */ +#define LTQ_SSC_BASE_ADDR 0x1e100800 +#define LTQ_SSC_SIZE 0x100 + +/* MEI - dsl core */ +#define LTQ_MEI_BASE_ADDR 0x1E116000 + +/* DEU - data encryption unit */ +#define LTQ_DEU_BASE_ADDR 0x1E103100 + +/* MPS - multi processor unit (voice) */ +#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) +#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) + +/* request a non-gpio and set the PIO config */ +extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, + unsigned int alt1, unsigned int dir, const char *name); +extern int ltq_gpio_setconfig(unsigned int pin, + unsigned int reg, unsigned int val); + +extern void ltq_pmu_enable(unsigned int module); +extern void ltq_pmu_disable(unsigned int module); + +static inline int +ltq_is_ar9(void) +{ + return (ltq_get_soc_type() == SOC_TYPE_AR9); +} + +static inline int +ltq_is_vr9(void) +{ + return (ltq_get_soc_type() == SOC_TYPE_VR9); +} + +#endif + +#endif diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig new file mode 100644 index 0000000..2780461 --- /dev/null +++ b/arch/mips/lantiq/Kconfig @@ -0,0 +1,21 @@ +if LANTIQ + +config SOC_TYPE_XWAY + bool + default n + +choice + prompt "SoC Type" + default SOC_XWAY + +config SOC_AMAZON_SE + bool "Amazon SE" + select SOC_TYPE_XWAY + +config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HW_HAS_PCI +endchoice + +endif diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index 6a30de6..a268391 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -7,3 +7,5 @@ obj-y := irq.o setup.o clk.o prom.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform index eef587f..f3dff05 100644 --- a/arch/mips/lantiq/Platform +++ b/arch/mips/lantiq/Platform @@ -5,3 +5,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/ cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq load-$(CONFIG_LANTIQ) = 0xffffffff80002000 +cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile new file mode 100644 index 0000000..9c85ff9 --- /dev/null +++ b/arch/mips/lantiq/xway/Makefile @@ -0,0 +1,4 @@ +obj-y := pmu.o ebu.o reset.o gpio.o + +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c new file mode 100644 index 0000000..5444917 --- /dev/null +++ b/arch/mips/lantiq/xway/clk-ase.c @@ -0,0 +1,52 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* cgu registers */ +#define LTQ_CGU_SYS 0x0010 + +unsigned int +ltq_get_io_region_clock(void) +{ + return CLOCK_133M; +} +EXPORT_SYMBOL(ltq_get_io_region_clock); + +unsigned int +ltq_get_fpi_bus_clock(int fpi) +{ + return CLOCK_133M; +} +EXPORT_SYMBOL(ltq_get_fpi_bus_clock); + +unsigned int +ltq_get_cpu_hz(void) +{ + if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) + return CLOCK_266M; + else + return CLOCK_133M; +} +EXPORT_SYMBOL(ltq_get_cpu_hz); + +unsigned int +ltq_get_fpi_hz(void) +{ + return CLOCK_133M; +} +EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c new file mode 100644 index 0000000..5dcc01b --- /dev/null +++ b/arch/mips/lantiq/xway/clk-xway.c @@ -0,0 +1,224 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +static unsigned int ltq_ram_clocks[] = { + CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; +#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] + +#define BASIC_FREQUENCY_1 35328000 +#define BASIC_FREQUENCY_2 36000000 +#define BASIS_REQUENCY_USB 12000000 + +#define GET_BITS(x, msb, lsb) \ + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) + +#define LTQ_CGU_PLL0_CFG 0x0004 +#define LTQ_CGU_PLL1_CFG 0x0008 +#define LTQ_CGU_PLL2_CFG 0x000C +#define LTQ_CGU_SYS 0x0010 +#define LTQ_CGU_UPDATE 0x0014 +#define LTQ_CGU_IF_CLK 0x0018 +#define LTQ_CGU_OSC_CON 0x001C +#define LTQ_CGU_SMD 0x0020 +#define LTQ_CGU_CT1SR 0x0028 +#define LTQ_CGU_CT2SR 0x002C +#define LTQ_CGU_PCMCR 0x0030 +#define LTQ_CGU_PCI_CR 0x0034 +#define LTQ_CGU_PD_PC 0x0038 +#define LTQ_CGU_FMR 0x003C + +#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) +#define CGU_PLL0_BYPASS \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) +#define CGU_PLL0_CFG_DSMSEL \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) +#define CGU_PLL0_CFG_FRAC_EN \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) +#define CGU_PLL1_SRC \ + (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) +#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) +#define CGU_SYS_FPI_SEL (1 << 6) +#define CGU_SYS_DDR_SEL 0x3 +#define CGU_PLL0_SRC (1 << 29) + +#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) +#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) +#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) +#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) + +static unsigned int ltq_get_pll0_fdiv(void); + +static inline unsigned int +get_input_clock(int pll) +{ + switch (pll) { + case 0: + if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 1: + if (CGU_PLL1_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 2: + switch (CGU_PLL2_SRC) { + case 0: + return ltq_get_pll0_fdiv(); + case 1: + return CGU_PLL2_PHASE_DIVIDER_ENABLE ? + BASIC_FREQUENCY_1 : + BASIC_FREQUENCY_2; + case 2: + return BASIS_REQUENCY_USB; + } + default: + return 0; + } +} + +static inline unsigned int +cal_dsm(int pll, unsigned int num, unsigned int den) +{ + u64 res, clock = get_input_clock(pll); + res = num * clock; + do_div(res, den); + return res; +} + +static inline unsigned int +mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K) +{ + unsigned int num = ((N + 1) << 10) + K; + unsigned int den = (M + 1) << 10; + return cal_dsm(pll, num, den); +} + +static inline unsigned int +ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K) +{ + unsigned int num = ((N + 1) << 11) + K + 512; + unsigned int den = (M + 1) << 11; + return cal_dsm(pll, num, den); +} + +static inline unsigned int +ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K) +{ + unsigned int num = K >= 512 ? + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; + unsigned int den = (M + 1) << 12; + return cal_dsm(pll, num, den); +} + +static inline unsigned int +dsm(int pll, unsigned int M, unsigned int N, unsigned int K, + unsigned int dsmsel, unsigned int phase_div_en) +{ + if (!dsmsel) + return mash_dsm(pll, M, N, K); + else if (!phase_div_en) + return mash_dsm(pll, M, N, K); + else + return ssff_dsm_2(pll, M, N, K); +} + +static inline unsigned int +ltq_get_pll0_fosc(void) +{ + if (CGU_PLL0_BYPASS) + return get_input_clock(0); + else + return !CGU_PLL0_CFG_FRAC_EN + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, + CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE) + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, + CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE); +} + +static unsigned int +ltq_get_pll0_fdiv(void) +{ + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; + return (ltq_get_pll0_fosc() + (div >> 1)) / div; +} + +unsigned int +ltq_get_io_region_clock(void) +{ + unsigned int ret = ltq_get_pll0_fosc(); + switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { + default: + case 0: + return (ret + 1) / 2; + case 1: + return (ret * 2 + 2) / 5; + case 2: + return (ret + 1) / 3; + case 3: + return (ret + 2) / 4; + } +} +EXPORT_SYMBOL(ltq_get_io_region_clock); + +unsigned int +ltq_get_fpi_bus_clock(int fpi) +{ + unsigned int ret = ltq_get_io_region_clock(); + if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) + ret >>= 1; + return ret; +} +EXPORT_SYMBOL(ltq_get_fpi_bus_clock); + +unsigned int +ltq_get_cpu_hz(void) +{ + switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { + case 0: + return CLOCK_333M; + case 4: + return DDR_HZ; + case 8: + return DDR_HZ << 1; + default: + return DDR_HZ >> 1; + } +} +EXPORT_SYMBOL(ltq_get_cpu_hz); + +unsigned int +ltq_get_fpi_hz(void) +{ + unsigned int ddr_clock = DDR_HZ; + if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) + return ddr_clock >> 1; + return ddr_clock; +} +EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c new file mode 100644 index 0000000..3e714c7 --- /dev/null +++ b/arch/mips/lantiq/xway/ebu.c @@ -0,0 +1,36 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * EBU - the external bus unit attaches PCI, NOR and NAND + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include + +#include + +/* all access to the ebu must be locked */ +DEFINE_SPINLOCK(ebu_lock); +EXPORT_SYMBOL_GPL(ebu_lock); + +/* remapped base addr of the clock unit and external bus unit */ +__iomem void *ltq_ebu_membase; + +static int __init +lantiq_ebu_init(void) +{ + /* remap ebu register range */ + ltq_ebu_membase = ioremap_nocache(LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + if (!ltq_ebu_membase) { + printk(KERN_ERR "Failed to remap ebu memory\n"); + unreachable(); + } + return 0; +} + +postcore_initcall(lantiq_ebu_init); diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c new file mode 100644 index 0000000..5186f9a --- /dev/null +++ b/arch/mips/lantiq/xway/gpio.c @@ -0,0 +1,195 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define LTQ_GPIO_OUT 0x00 +#define LTQ_GPIO_IN 0x04 +#define LTQ_GPIO_DIR 0x08 +#define LTQ_GPIO_ALTSEL0 0x0C +#define LTQ_GPIO_ALTSEL1 0x10 +#define LTQ_GPIO_OD 0x14 + +#define PINS_PER_PORT 16 +#define MAX_PORTS 3 + +#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) +#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) +#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) + +struct ltq_gpio { + void __iomem *membase; + struct gpio_chip chip; +}; + +static struct ltq_gpio ltq_gpio_port[MAX_PORTS]; + +int +gpio_to_irq(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int +irq_to_gpio(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); + +int +ltq_gpio_request(unsigned int pin, unsigned int alt0, + unsigned int alt1, unsigned int dir, const char *name) +{ + int id = 0; + if (pin >= (MAX_PORTS * PINS_PER_PORT)) + return -EINVAL; + if (gpio_request(pin, name)) { + printk(KERN_ERR "failed to setup lantiq gpio: %s\n", name); + return -EBUSY; + } + if (dir) + gpio_direction_output(pin, 1); + else + gpio_direction_input(pin); + while (pin >= PINS_PER_PORT) { + pin -= PINS_PER_PORT; + id++; + } + if (alt0) + ltq_gpio_setbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); + else + ltq_gpio_clearbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); + if (alt1) + ltq_gpio_setbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL1, pin); + else + ltq_gpio_clearbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL1, pin); + return 0; +} +EXPORT_SYMBOL(ltq_gpio_request); + +static void +ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + if (value) + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); + else + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); +} + +static int +ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset); +} + +static int +ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + return 0; +} + +static int +ltq_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + ltq_gpio_set(chip, offset, value); + return 0; +} + +static int +ltq_gpio_req(struct gpio_chip *chip, unsigned offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); + return 0; +} + +static int +ltq_gpio_probe(struct platform_device *pdev) +{ + struct resource *res; + if (pdev->id >= MAX_PORTS) { + dev_err(&pdev->dev, "invalid gpio port %d\n", + pdev->id); + return -EINVAL; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", + pdev->id); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, + "failed to request memory for gpio port %d\n", + pdev->id); + return -EBUSY; + } + ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_gpio_port[pdev->id].membase) { + dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n", + pdev->id); + return -ENOMEM; + } + ltq_gpio_port[pdev->id].chip.label = "ltq_gpio"; + ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input; + ltq_gpio_port[pdev->id].chip.direction_output = + ltq_gpio_direction_output; + ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get; + ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; + ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; + ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; + ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; + platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); + return gpiochip_add(<q_gpio_port[pdev->id].chip); +} + +static struct platform_driver +ltq_gpio_driver = { + .probe = ltq_gpio_probe, + .driver = { + .name = "ltq_gpio", + .owner = THIS_MODULE, + }, +}; + +int __init +ltq_gpio_init(void) +{ + int ret = platform_driver_register(<q_gpio_driver); + if (ret) + printk(KERN_INFO "ltq_gpio : Error registering platfom driver!"); + return ret; +} + +postcore_initcall(ltq_gpio_init); diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c new file mode 100644 index 0000000..a5db888 --- /dev/null +++ b/arch/mips/lantiq/xway/pmu.c @@ -0,0 +1,57 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include + +#include + +/* PMU - the power management unit allows us to turn part of the core + * on and off + */ + +/* the enable / disable register */ +#define LTQ_PMU_PWDCR 0x1C +#define LTQ_PMU_PWDSR 0x20 + +#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) +#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) + +static __iomem void *ltq_pmu_membase; + +void +ltq_pmu_enable(unsigned int module) +{ + int err = 1000000; + + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); + do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); + + if (!err) + panic("activating PMU module failed!"); +} + +void +ltq_pmu_disable(unsigned int module) +{ + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); +} + +int __init +ltq_pmu_init(void) +{ + ltq_pmu_membase = ioremap_nocache(LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); + if (!ltq_pmu_membase) { + printk(KERN_ERR "Failed to remap pmu memory\n"); + unreachable(); + } + return 0; +} + +core_initcall(ltq_pmu_init); diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c new file mode 100644 index 0000000..a7faf77 --- /dev/null +++ b/arch/mips/lantiq/xway/prom-ase.c @@ -0,0 +1,40 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "../prom.h" + +#define SOC_AMAZON_SE "Amazon_SE" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + switch (i->partnum) { + case SOC_ID_AMAZON_SE: + i->name = SOC_AMAZON_SE; + i->type = SOC_TYPE_AMAZON_SE; + break; + + default: + unreachable(); + break; + } +} diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c new file mode 100644 index 0000000..e7270e5 --- /dev/null +++ b/arch/mips/lantiq/xway/prom-xway.c @@ -0,0 +1,55 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "../prom.h" + +#define SOC_DANUBE "Danube" +#define SOC_TWINPASS "Twinpass" +#define SOC_AR9 "AR9" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + switch (i->partnum) { + case SOC_ID_DANUBE1: + case SOC_ID_DANUBE2: + i->name = SOC_DANUBE; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_TWINPASS: + i->name = SOC_TWINPASS; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_ARX188: + case SOC_ID_ARX168: + case SOC_ID_ARX182: + i->name = SOC_AR9; + i->type = SOC_TYPE_AR9; + break; + + default: + unreachable(); + break; + } +} diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c new file mode 100644 index 0000000..949f305 --- /dev/null +++ b/arch/mips/lantiq/xway/reset.c @@ -0,0 +1,67 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) +#define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) + +/* register definitions */ +#define LTQ_RCU_RST 0x0010 +#define LTQ_RCU_RST_ALL 0x40000000 + +/* remapped base addr of the reset control unit */ +static __iomem void *ltq_rcu_membase; + +static void +ltq_machine_restart(char *command) +{ + printk(KERN_NOTICE "System restart\n"); + local_irq_disable(); + ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST); + unreachable(); +} + +static void +ltq_machine_halt(void) +{ + printk(KERN_NOTICE "System halted.\n"); + local_irq_disable(); + unreachable(); +} + +static void +ltq_machine_power_off(void) +{ + printk(KERN_NOTICE "Please turn off the power now.\n"); + local_irq_disable(); + unreachable(); +} + +static int __init +mips_reboot_setup(void) +{ + /* remap rcu register range */ + ltq_rcu_membase = ioremap_nocache(LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE); + if (!ltq_rcu_membase) { + printk(KERN_ERR "Failed to remap rcu memory\n"); + unreachable(); + } + + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; + return 0; +} + +arch_initcall(mips_reboot_setup); -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:12:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:12:59 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51009 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491821Ab1CAQM2 (ORCPT ); Tue, 1 Mar 2011 17:12:28 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 00/10] MIPS: add support for Lantiq SoCs Date: Tue, 1 Mar 2011 17:13:16 +0100 Message-Id: <1298996006-15960-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29303 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This series will add support for the Lantiq/XWAY family of SoCs. Cc: Ralph Hempel Cc: linux-mips@linux-mips.org John Crispin (10): MIPS: lantiq: add initial support for Lantiq SoCs MIPS: lantiq: add SoC specific code for XWAY family MIPS: lantiq: add PCI controller support. MIPS: lantiq: add serial port support MIPS: lantiq: add watchdog support MIPS: lantiq: add NOR flash support MIPS: lantiq: add platform device support MIPS: lantiq: add mips_machine support MIPS: lantiq: add machtypes for lantiq eval kits MIPS: lantiq: add more gpio drivers arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 19 + arch/mips/include/asm/mach-lantiq/lantiq.h | 58 ++ .../mips/include/asm/mach-lantiq/lantiq_platform.h | 46 ++ arch/mips/include/asm/mach-lantiq/war.h | 24 + arch/mips/include/asm/mach-lantiq/xway/irq.h | 18 + .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 62 ++ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 145 ++++ arch/mips/lantiq/Kconfig | 23 + arch/mips/lantiq/Makefile | 11 + arch/mips/lantiq/Platform | 8 + arch/mips/lantiq/clk.c | 132 ++++ arch/mips/lantiq/clk.h | 18 + arch/mips/lantiq/devices.c | 128 ++++ arch/mips/lantiq/devices.h | 20 + arch/mips/lantiq/early_printk.c | 33 + arch/mips/lantiq/irq.c | 311 ++++++++ arch/mips/lantiq/machtypes.h | 20 + arch/mips/lantiq/prom.c | 74 ++ arch/mips/lantiq/prom.h | 24 + arch/mips/lantiq/setup.c | 72 ++ arch/mips/lantiq/xway/Kconfig | 25 + arch/mips/lantiq/xway/Makefile | 7 + arch/mips/lantiq/xway/clk-ase.c | 52 ++ arch/mips/lantiq/xway/clk-xway.c | 224 ++++++ arch/mips/lantiq/xway/devices.c | 79 ++ arch/mips/lantiq/xway/devices.h | 17 + arch/mips/lantiq/xway/ebu.c | 36 + arch/mips/lantiq/xway/gpio.c | 195 +++++ arch/mips/lantiq/xway/gpio_ebu.c | 125 ++++ arch/mips/lantiq/xway/gpio_stp.c | 157 ++++ arch/mips/lantiq/xway/mach-easy50601.c | 70 ++ arch/mips/lantiq/xway/mach-easy50712.c | 75 ++ arch/mips/lantiq/xway/pmu.c | 57 ++ arch/mips/lantiq/xway/prom-ase.c | 40 + arch/mips/lantiq/xway/prom-xway.c | 55 ++ arch/mips/lantiq/xway/reset.c | 67 ++ arch/mips/pci/Makefile | 1 + arch/mips/pci/ops-lantiq.c | 119 +++ arch/mips/pci/pci-lantiq.c | 303 ++++++++ arch/mips/pci/pci-lantiq.h | 18 + drivers/mtd/maps/Kconfig | 7 + drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq.c | 186 +++++ drivers/tty/serial/Kconfig | 8 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/lantiq.c | 775 ++++++++++++++++++++ drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/lantiq_wdt.c | 233 ++++++ 50 files changed, 4187 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq.h create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_platform.h create mode 100644 arch/mips/include/asm/mach-lantiq/war.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h create mode 100644 arch/mips/lantiq/Kconfig create mode 100644 arch/mips/lantiq/Makefile create mode 100644 arch/mips/lantiq/Platform create mode 100644 arch/mips/lantiq/clk.c create mode 100644 arch/mips/lantiq/clk.h create mode 100644 arch/mips/lantiq/devices.c create mode 100644 arch/mips/lantiq/devices.h create mode 100644 arch/mips/lantiq/early_printk.c create mode 100644 arch/mips/lantiq/irq.c create mode 100644 arch/mips/lantiq/machtypes.h create mode 100644 arch/mips/lantiq/prom.c create mode 100644 arch/mips/lantiq/prom.h create mode 100644 arch/mips/lantiq/setup.c create mode 100644 arch/mips/lantiq/xway/Kconfig create mode 100644 arch/mips/lantiq/xway/Makefile create mode 100644 arch/mips/lantiq/xway/clk-ase.c create mode 100644 arch/mips/lantiq/xway/clk-xway.c create mode 100644 arch/mips/lantiq/xway/devices.c create mode 100644 arch/mips/lantiq/xway/devices.h create mode 100644 arch/mips/lantiq/xway/ebu.c create mode 100644 arch/mips/lantiq/xway/gpio.c create mode 100644 arch/mips/lantiq/xway/gpio_ebu.c create mode 100644 arch/mips/lantiq/xway/gpio_stp.c create mode 100644 arch/mips/lantiq/xway/mach-easy50601.c create mode 100644 arch/mips/lantiq/xway/mach-easy50712.c create mode 100644 arch/mips/lantiq/xway/pmu.c create mode 100644 arch/mips/lantiq/xway/prom-ase.c create mode 100644 arch/mips/lantiq/xway/prom-xway.c create mode 100644 arch/mips/lantiq/xway/reset.c create mode 100644 arch/mips/pci/ops-lantiq.c create mode 100644 arch/mips/pci/pci-lantiq.c create mode 100644 arch/mips/pci/pci-lantiq.h create mode 100644 drivers/mtd/maps/lantiq.c create mode 100644 drivers/tty/serial/lantiq.c create mode 100644 drivers/watchdog/lantiq_wdt.c -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:13:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:13:26 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51008 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491185Ab1CAQM2 (ORCPT ); Tue, 1 Mar 2011 17:12:28 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 03/10] MIPS: lantiq: add PCI controller support. Date: Tue, 1 Mar 2011 17:13:19 +0100 Message-Id: <1298996006-15960-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29304 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds the driver that allows us to use the EBU as a PCI controller. In order for PCI to work the EBU is set to endianess swap all the data. In addition we need to make use of SWAP_IO_SPACE for device->host DMA to work. The clock of the PCI works in several modes (internal/external). If this is not configured correctly the SoC will hang. Changes in V2 * add handling for more than 1 pci device * add properly handling and registration of gpios * properly remap the memory regions Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- .../mips/include/asm/mach-lantiq/lantiq_platform.h | 46 +++ arch/mips/pci/Makefile | 1 + arch/mips/pci/ops-lantiq.c | 119 ++++++++ arch/mips/pci/pci-lantiq.c | 303 ++++++++++++++++++++ arch/mips/pci/pci-lantiq.h | 18 ++ 5 files changed, 487 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_platform.h create mode 100644 arch/mips/pci/ops-lantiq.c create mode 100644 arch/mips/pci/pci-lantiq.c create mode 100644 arch/mips/pci/pci-lantiq.h diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h new file mode 100644 index 0000000..54e873c --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h @@ -0,0 +1,46 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LANTIQ_PLATFORM_H__ +#define _LANTIQ_PLATFORM_H__ + +#include + +/* struct used to pass info to the pci core */ +enum { + PCI_CLOCK_INT = 0, + PCI_CLOCK_EXT +}; + +#define PCI_EXIN0 0x0001 +#define PCI_EXIN1 0x0002 +#define PCI_EXIN2 0x0004 +#define PCI_EXIN3 0x0008 +#define PCI_EXIN4 0x0010 +#define PCI_EXIN5 0x0020 +#define PCI_EXIN_MAX 6 + +#define PCI_GNT1 0x0040 +#define PCI_GNT2 0x0080 +#define PCI_GNT3 0x0100 +#define PCI_GNT4 0x0200 + +#define PCI_REQ1 0x0400 +#define PCI_REQ2 0x0800 +#define PCI_REQ3 0x1000 +#define PCI_REQ4 0x2000 +#define PCI_REQ_SHIFT 10 +#define PCI_REQ_MASK 0xf + +struct ltq_pci_data { + int clock; + int gpio; + int irq[16]; +}; + +#endif diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c9209ca..4a5d1ae 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o +obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c new file mode 100644 index 0000000..ee28018 --- /dev/null +++ b/arch/mips/pci/ops-lantiq.c @@ -0,0 +1,119 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "pci-lantiq.h" + +#define LTQ_PCI_CFG_BUSNUM_SHF 16 +#define LTQ_PCI_CFG_DEVNUM_SHF 11 +#define LTQ_PCI_CFG_FUNNUM_SHF 8 + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +static int +ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int devfn, unsigned int where, u32 *data) +{ + unsigned long cfg_base; + unsigned long flags; + u32 temp; + + /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the + SoC itself */ + if ((bus->number != 0) || ((devfn & 0xf8) > 0x78) + || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68)) + return 1; + + spin_lock_irqsave(&ebu_lock, flags); + + cfg_base = (unsigned long) ltq_pci_mapped_cfg; + cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn << + LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3); + + /* Perform access */ + if (access_type == PCI_ACCESS_WRITE) { + ltq_w32(swab32(*data), ((u32 *)cfg_base)); + } else { + *data = ltq_r32(((u32 *)(cfg_base))); + *data = swab32(*data); + } + wmb(); + + /* clean possible Master abort */ + cfg_base = (unsigned long) ltq_pci_mapped_cfg; + cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; + temp = ltq_r32(((u32 *)(cfg_base))); + temp = swab32(temp); + cfg_base = (unsigned long) ltq_pci_mapped_cfg; + cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; + ltq_w32(temp, ((u32 *)cfg_base)); + + spin_unlock_irqrestore(&ebu_lock, flags); + + if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ)) + return 1; + + return 0; +} + +int +ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data = 0; + + if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +int +ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + + if (size == 4) { + data = val; + } else { + if (ltq_pci_config_access(PCI_ACCESS_READ, bus, + devfn, where, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + } + + if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c new file mode 100644 index 0000000..1dde03f --- /dev/null +++ b/arch/mips/pci/pci-lantiq.c @@ -0,0 +1,303 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "pci-lantiq.h" + +#define LTQ_PCI_CFG_BASE 0x17000000 +#define LTQ_PCI_CFG_SIZE 0x00008000 +#define LTQ_PCI_MEM_BASE 0x18000000 +#define LTQ_PCI_MEM_SIZE 0x02000000 +#define LTQ_PCI_IO_BASE 0x1AE00000 +#define LTQ_PCI_IO_SIZE 0x00200000 + +#define PCI_CR_FCI_ADDR_MAP0 0x00C0 +#define PCI_CR_FCI_ADDR_MAP1 0x00C4 +#define PCI_CR_FCI_ADDR_MAP2 0x00C8 +#define PCI_CR_FCI_ADDR_MAP3 0x00CC +#define PCI_CR_FCI_ADDR_MAP4 0x00D0 +#define PCI_CR_FCI_ADDR_MAP5 0x00D4 +#define PCI_CR_FCI_ADDR_MAP6 0x00D8 +#define PCI_CR_FCI_ADDR_MAP7 0x00DC +#define PCI_CR_CLK_CTRL 0x0000 +#define PCI_CR_PCI_MOD 0x0030 +#define PCI_CR_PC_ARB 0x0080 +#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4 +#define PCI_CR_BAR11MASK 0x0044 +#define PCI_CR_BAR12MASK 0x0048 +#define PCI_CR_BAR13MASK 0x004C +#define PCI_CS_BASE_ADDR1 0x0010 +#define PCI_CR_PCI_ADDR_MAP11 0x0064 +#define PCI_CR_FCI_BURST_LENGTH 0x00E8 +#define PCI_CR_PCI_EOI 0x002C +#define PCI_CS_STS_CMD 0x0004 + +#define PCI_MASTER0_REQ_MASK_2BITS 8 +#define PCI_MASTER1_REQ_MASK_2BITS 10 +#define PCI_MASTER2_REQ_MASK_2BITS 12 +#define INTERNAL_ARB_ENABLE_BIT 0 + +#define LTQ_CGU_IFCCR 0x0018 +#define LTQ_CGU_PCICR 0x0034 + +#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y)) +#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x)) + +#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) +#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) + +struct ltq_pci_gpio_map { + int pin; + int alt0; + int alt1; + int dir; + char *name; +}; + +/* the pci core can make use of the following gpios */ +static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { + { 0, 1, 0, 0, "pci-exin0" }, + { 1, 1, 0, 0, "pci-exin1" }, + { 2, 1, 0, 0, "pci-exin2" }, + { 39, 1, 0, 0, "pci-exin3" }, + { 10, 1, 0, 0, "pci-exin4" }, + { 9, 1, 0, 0, "pci-exin5" }, + { 30, 1, 0, 1, "pci-gnt1" }, + { 23, 1, 0, 1, "pci-gnt2" }, + { 19, 1, 0, 1, "pci-gnt3" }, + { 38, 1, 0, 1, "pci-gnt4" }, + { 29, 1, 0, 0, "pci-req1" }, + { 31, 1, 0, 0, "pci-req2" }, + { 3, 1, 0, 0, "pci-req3" }, + { 37, 1, 0, 0, "pci-req4" }, +}; + +__iomem void *ltq_pci_mapped_cfg; +static __iomem void *ltq_pci_membase; + +int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; + +/* Since the PCI REQ pins can be reused for other functionality, make it + possible to exclude those from interpretation by the PCI controller */ +static int ltq_pci_req_mask = 0xf; + +static int *ltq_pci_irq_map; + +struct pci_ops ltq_pci_ops = { + .read = ltq_pci_read_config_dword, + .write = ltq_pci_write_config_dword +}; + +static struct resource pci_io_resource = { + .name = "pci io space", + .start = LTQ_PCI_IO_BASE, + .end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + .name = "pci memory space", + .start = LTQ_PCI_MEM_BASE, + .end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM +}; + +static struct pci_controller ltq_pci_controller = { + .pci_ops = <q_pci_ops, + .mem_resource = &pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &pci_io_resource, + .io_offset = 0x00000000UL, +}; + +int +pcibios_plat_dev_init(struct pci_dev *dev) +{ + if (ltqpci_plat_dev_init) + return ltqpci_plat_dev_init(dev); + + return 0; +} + +static u32 +ltq_calc_bar11mask(void) +{ + u32 mem, bar11mask; + + /* BAR11MASK value depends on available memory on system. */ + mem = num_physpages * PAGE_SIZE; + bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; + + return bar11mask; +} + +static void +ltq_pci_setup_gpio(int gpio) +{ + int i; + for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) + { + if(gpio & (1 << i)) + { + ltq_gpio_request(ltq_pci_gpio_map[i].pin, + ltq_pci_gpio_map[i].alt0, + ltq_pci_gpio_map[i].alt1, + ltq_pci_gpio_map[i].dir, + ltq_pci_gpio_map[i].name); + } + } + ltq_gpio_request(21, 0, 0, 1, "pci-reset"); + ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; +} + +static int __devinit +ltq_pci_startup(struct ltq_pci_data *conf) +{ + u32 temp_buffer; + + /* set clock to 33Mhz */ + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); + + /* external or internal clock ? */ + if (conf->clock) { + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16), + LTQ_CGU_IFCCR); + ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR); + } else { + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16), + LTQ_CGU_IFCCR); + ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR); + } + + /* setup pci clock and gpis used by pci */ + ltq_pci_setup_gpio(conf->gpio); + + /* enable auto-switching between PCI and EBU */ + ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); + + /* busy, i.e. configuration is not done, PCI access has to be retried */ + ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD); + wmb(); + /* BUS Master/IO/MEM access */ + ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD); + + /* enable external 2 PCI masters */ + temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB); + temp_buffer &= (~(ltq_pci_req_mask << 16)); + /* enable internal arbiter */ + temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); + /* enable internal PCI master reqest */ + temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); + + /* enable EBU request */ + temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS)); + + /* enable all external masters request */ + temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); + ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB); + wmb(); + + /* setup BAR memory regions */ + ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0); + ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1); + ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2); + ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3); + ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4); + ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5); + ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6); + ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7); + ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg); + ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK); + ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11); + ltq_pci_w32(0, PCI_CS_BASE_ADDR1); + /* both TX and RX endian swap are enabled */ + ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI); + wmb(); + ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000, + PCI_CR_BAR12MASK); + ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000, + PCI_CR_BAR13MASK); + /*use 8 dw burst length */ + ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH); + ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD); + wmb(); + + /* setup irq line */ + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON); + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); + + /* toggle reset pin */ + __gpio_set_value(21, 0); + wmb(); + mdelay(1); + __gpio_set_value(21, 1); + return 0; +} + +int __init +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if(ltq_pci_irq_map[slot]) + return ltq_pci_irq_map[slot]; + printk("lq_pci: trying to map irq for unknown slot %d\n", slot); + return 0; +} + +static int __devinit +ltq_pci_probe(struct platform_device *pdev) +{ + struct ltq_pci_data *ltq_pci_data = + (struct ltq_pci_data *) pdev->dev.platform_data; + pci_probe_only = 0; + ltq_pci_irq_map = ltq_pci_data->irq; + ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); + ltq_pci_mapped_cfg = + ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); + ltq_pci_controller.io_map_base = + (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); + ltq_pci_startup(ltq_pci_data); + register_pci_controller(<q_pci_controller); + return 0; +} + +static struct platform_driver +ltq_pci_driver = { + .probe = ltq_pci_probe, + .driver = { + .name = "ltq_pci", + .owner = THIS_MODULE, + }, +}; + +int __init +pcibios_init(void) +{ + int ret = platform_driver_register(<q_pci_driver); + if (ret) + printk(KERN_INFO "ltq_pci: Error registering platfom driver!"); + return ret; +} + +arch_initcall(pcibios_init); diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h new file mode 100644 index 0000000..66bf6cd --- /dev/null +++ b/arch/mips/pci/pci-lantiq.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_PCI_H__ +#define _LTQ_PCI_H__ + +extern __iomem void *ltq_pci_mapped_cfg; +extern int ltq_pci_read_config_dword(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *val); +extern int ltq_pci_write_config_dword(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 val); + +#endif -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:13:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:13:51 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51015 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491940Ab1CAQM2 (ORCPT ); Tue, 1 Mar 2011 17:12:28 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , Felix Fietkau , linux-mips@linux-mips.org Subject: [PATCH V2 04/10] MIPS: lantiq: add serial port support Date: Tue, 1 Mar 2011 17:13:20 +0100 Message-Id: <1298996006-15960-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29305 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the 2 serial ports found inside the Lantiq SoC family Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Signed-off-by: Felix Fietkau Cc: linux-mips@linux-mips.org Changes in V2 * small cleanups * use global register access macros * properly register memory resources --- drivers/tty/serial/Kconfig | 8 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/lantiq.c | 775 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 784 insertions(+), 0 deletions(-) create mode 100644 drivers/tty/serial/lantiq.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 2b83346..8f286eb 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1402,6 +1402,14 @@ config SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE help Support for Console on the NWP serial ports. +config SERIAL_LANTIQ + bool "Lantiq serial driver" + depends on LANTIQ + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + help + Support for console and UART on Lantiq SoCs. + config SERIAL_QE tristate "Freescale QUICC Engine serial port support" depends on QUICC_ENGINE diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 8ea92e9..1aebd4d 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -92,3 +92,4 @@ obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o +obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c new file mode 100644 index 0000000..4c22642 --- /dev/null +++ b/drivers/tty/serial/lantiq.c @@ -0,0 +1,775 @@ +/* + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2004 Infineon IFAP DC COM CPE + * Copyright (C) 2007 Felix Fietkau + * Copyright (C) 2007 John Crispin + * Copyright (C) 2010 Thomas Langer, + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PORT_LTQ_ASC 111 +#define MAXPORTS 2 +#define UART_DUMMY_UER_RX 1 +#define DRVNAME "ltq_asc" +#ifdef __BIG_ENDIAN +#define LTQ_ASC_TBUF (0x0020 + 3) +#define LTQ_ASC_RBUF (0x0024 + 3) +#else +#define LTQ_ASC_TBUF 0x0020 +#define LTQ_ASC_RBUF 0x0024 +#endif +#define LTQ_ASC_FSTAT 0x0048 +#define LTQ_ASC_WHBSTATE 0x0018 +#define LTQ_ASC_STATE 0x0014 +#define LTQ_ASC_IRNCR 0x00F8 +#define LTQ_ASC_CLC 0x0000 +#define LTQ_ASC_ID 0x0008 +#define LTQ_ASC_PISEL 0x0004 +#define LTQ_ASC_TXFCON 0x0044 +#define LTQ_ASC_RXFCON 0x0040 +#define LTQ_ASC_CON 0x0010 +#define LTQ_ASC_BG 0x0050 +#define LTQ_ASC_IRNREN 0x00F4 + +#define ASC_IRNREN_TX 0x1 +#define ASC_IRNREN_RX 0x2 +#define ASC_IRNREN_ERR 0x4 +#define ASC_IRNREN_TX_BUF 0x8 +#define ASC_IRNCR_TIR 0x1 +#define ASC_IRNCR_RIR 0x2 +#define ASC_IRNCR_EIR 0x4 + +#define ASCOPT_CSIZE 0x3 +#define ASCOPT_CS7 0x1 +#define ASCOPT_CS8 0x2 +#define ASCOPT_PARENB 0x4 +#define ASCOPT_STOPB 0x8 +#define ASCOPT_PARODD 0x0 +#define ASCOPT_CREAD 0x20 +#define TXFIFO_FL 1 +#define RXFIFO_FL 1 +#define ASCCLC_DISS 0x2 +#define ASCCLC_RMCMASK 0x0000FF00 +#define ASCCLC_RMCOFFSET 8 +#define ASCCON_M_8ASYNC 0x0 +#define ASCCON_M_7ASYNC 0x2 +#define ASCCON_ODD 0x00000020 +#define ASCCON_STP 0x00000080 +#define ASCCON_BRS 0x00000100 +#define ASCCON_FDE 0x00000200 +#define ASCCON_R 0x00008000 +#define ASCCON_FEN 0x00020000 +#define ASCCON_ROEN 0x00080000 +#define ASCCON_TOEN 0x00100000 +#define ASCSTATE_PE 0x00010000 +#define ASCSTATE_FE 0x00020000 +#define ASCSTATE_ROE 0x00080000 +#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) +#define ASCWHBSTATE_CLRREN 0x00000001 +#define ASCWHBSTATE_SETREN 0x00000002 +#define ASCWHBSTATE_CLRPE 0x00000004 +#define ASCWHBSTATE_CLRFE 0x00000008 +#define ASCWHBSTATE_CLRROE 0x00000020 +#define ASCTXFCON_TXFEN 0x0001 +#define ASCTXFCON_TXFFLU 0x0002 +#define ASCTXFCON_TXFITLMASK 0x3F00 +#define ASCTXFCON_TXFITLOFF 8 +#define ASCRXFCON_RXFEN 0x0001 +#define ASCRXFCON_RXFFLU 0x0002 +#define ASCRXFCON_RXFITLMASK 0x3F00 +#define ASCRXFCON_RXFITLOFF 8 +#define ASCFSTAT_RXFFLMASK 0x003F +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFFLOFF 8 +#define ASCFSTAT_RXFREEMASK 0x003F0000 +#define ASCFSTAT_RXFREEOFF 16 +#define ASCFSTAT_TXFREEMASK 0x3F000000 +#define ASCFSTAT_TXFREEOFF 24 + +static void lqasc_tx_chars(struct uart_port *port); +static struct ltq_uart_port *lqasc_port[2]; +static struct uart_driver lqasc_reg; + +struct ltq_uart_port { + struct uart_port port; + struct clk *clk; + unsigned int tx_irq; + unsigned int rx_irq; + unsigned int err_irq; +}; + +static inline struct +ltq_uart_port *to_ltq_uart_port(struct uart_port *port) +{ + return container_of(port, struct ltq_uart_port, port); +} + +static void +lqasc_stop_tx(struct uart_port *port) +{ + return; +} + +static void +lqasc_start_tx(struct uart_port *port) +{ + unsigned long flags; + local_irq_save(flags); + lqasc_tx_chars(port); + local_irq_restore(flags); + return; +} + +static void +lqasc_stop_rx(struct uart_port *port) +{ + ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); +} + +static void +lqasc_enable_ms(struct uart_port *port) +{ +} + +static void +lqasc_rx_chars(struct uart_port *port) +{ + struct tty_struct *tty = port->state->port.tty; + unsigned int ch = 0, rsr = 0, fifocnt; + + fifocnt = + ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; + while (fifocnt--) { + u8 flag = TTY_NORMAL; + ch = ltq_r8(port->membase + LTQ_ASC_RBUF); + rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) + & ASCSTATE_ANY) | UART_DUMMY_UER_RX; + tty_flip_buffer_push(tty); + port->icount.rx++; + + /* + * Note that the error handling code is + * out of the main execution path + */ + if (rsr & ASCSTATE_ANY) { + if (rsr & ASCSTATE_PE) { + port->icount.parity++; + ltq_w32_mask(0, ASCWHBSTATE_CLRPE, + port->membase + LTQ_ASC_WHBSTATE); + } else if (rsr & ASCSTATE_FE) { + port->icount.frame++; + ltq_w32_mask(0, ASCWHBSTATE_CLRFE, + port->membase + LTQ_ASC_WHBSTATE); + } + if (rsr & ASCSTATE_ROE) { + port->icount.overrun++; + ltq_w32_mask(0, ASCWHBSTATE_CLRROE, + port->membase + LTQ_ASC_WHBSTATE); + } + + rsr &= port->read_status_mask; + + if (rsr & ASCSTATE_PE) + flag = TTY_PARITY; + else if (rsr & ASCSTATE_FE) + flag = TTY_FRAME; + } + + if ((rsr & port->ignore_status_mask) == 0) + tty_insert_flip_char(tty, ch, flag); + + if (rsr & ASCSTATE_ROE) + /* + * Overrun is special, since it's reported + * immediately, and doesn't affect the current + * character + */ + tty_insert_flip_char(tty, 0, TTY_OVERRUN); + } + if (ch != 0) + tty_flip_buffer_push(tty); + return; +} + +static void +lqasc_tx_chars(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + if (uart_tx_stopped(port)) { + lqasc_stop_tx(port); + return; + } + + while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { + if (port->x_char) { + ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); + port->icount.tx++; + port->x_char = 0; + continue; + } + + if (uart_circ_empty(xmit)) + break; + + ltq_w8(port->state->xmit.buf[port->state->xmit.tail], + port->membase + LTQ_ASC_TBUF); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); +} + +static irqreturn_t +lqasc_tx_int(int irq, void *_port) +{ + struct uart_port *port = (struct uart_port *)_port; + ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); + lqasc_start_tx(port); + return IRQ_HANDLED; +} + +static irqreturn_t +lqasc_err_int(int irq, void *_port) +{ + struct uart_port *port = (struct uart_port *)_port; + /* clear any pending interrupts */ + ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | + ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); + return IRQ_HANDLED; +} + +static irqreturn_t +lqasc_rx_int(int irq, void *_port) +{ + struct uart_port *port = (struct uart_port *)_port; + ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); + lqasc_rx_chars(port); + return IRQ_HANDLED; +} + +static unsigned int +lqasc_tx_empty(struct uart_port *port) +{ + int status; + status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; + return status ? 0 : TIOCSER_TEMT; +} + +static unsigned int +lqasc_get_mctrl(struct uart_port *port) +{ + return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; +} + +static void +lqasc_set_mctrl(struct uart_port *port, u_int mctrl) +{ +} + +static void +lqasc_break_ctl(struct uart_port *port, int break_state) +{ +} + +static int +lqasc_startup(struct uart_port *port) +{ + struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); + int retval; + + port->uartclk = clk_get_rate(ltq_port->clk); + + ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + port->membase + LTQ_ASC_CLC); + + ltq_w32(0, port->membase + LTQ_ASC_PISEL); + ltq_w32( + ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | + ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); + ltq_w32( + ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) + | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); + /* make sure other settings are written to hardware before + setting enable bits */ + wmb(); + ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | + ASCCON_ROEN, port->membase + LTQ_ASC_CON); + + retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, + IRQF_DISABLED, "asc_tx", port); + if (retval) { + pr_err("failed to request lqasc_tx_int\n"); + return retval; + } + + retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, + IRQF_DISABLED, "asc_rx", port); + if (retval) { + pr_err("failed to request lqasc_rx_int\n"); + goto err1; + } + + retval = request_irq(ltq_port->err_irq, lqasc_err_int, + IRQF_DISABLED, "asc_err", port); + if (retval) { + pr_err("failed to request lqasc_err_int\n"); + goto err2; + } + + ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, + port->membase + LTQ_ASC_IRNREN); + return 0; + +err2: + free_irq(ltq_port->rx_irq, port); +err1: + free_irq(ltq_port->tx_irq, port); + return retval; +} + +static void +lqasc_shutdown(struct uart_port *port) +{ + struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); + free_irq(ltq_port->tx_irq, port); + free_irq(ltq_port->rx_irq, port); + free_irq(ltq_port->err_irq, port); + + ltq_w32(0, port->membase + LTQ_ASC_CON); + ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); + ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); +} + +static void +lqasc_set_termios(struct uart_port *port, + struct ktermios *new, struct ktermios *old) +{ + unsigned int cflag; + unsigned int iflag; + unsigned int quot; + unsigned int baud; + unsigned int con = 0; + unsigned long flags; + + cflag = new->c_cflag; + iflag = new->c_iflag; + + switch (cflag & CSIZE) { + case CS7: + con = ASCCON_M_7ASYNC; + break; + + case CS5: + case CS6: + default: + con = ASCCON_M_8ASYNC; + break; + } + + if (cflag & CSTOPB) + con |= ASCCON_STP; + + if (cflag & PARENB) { + if (!(cflag & PARODD)) + con &= ~ASCCON_ODD; + else + con |= ASCCON_ODD; + } + + port->read_status_mask = ASCSTATE_ROE; + if (iflag & INPCK) + port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; + + port->ignore_status_mask = 0; + if (iflag & IGNPAR) + port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; + + if (iflag & IGNBRK) { + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (iflag & IGNPAR) + port->ignore_status_mask |= ASCSTATE_ROE; + } + + if ((cflag & CREAD) == 0) + port->ignore_status_mask |= UART_DUMMY_UER_RX; + + /* set error signals - framing, parity and overrun, enable receiver */ + con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; + + local_irq_save(flags); + + /* set up CON */ + ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); + + /* Set baud rate - take a divider of 2 into account */ + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); + quot = uart_get_divisor(port, baud); + quot = quot / 2 - 1; + + /* disable the baudrate generator */ + ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); + + /* make sure the fractional divider is off */ + ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); + + /* set up to use divisor of 2 */ + ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); + + /* now we can write the new baudrate into the register */ + ltq_w32(quot, port->membase + LTQ_ASC_BG); + + /* turn the baudrate generator back on */ + ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); + + /* enable rx */ + ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); + + local_irq_restore(flags); +} + +static const char* +lqasc_type(struct uart_port *port) +{ + if (port->type == PORT_LTQ_ASC) + return DRVNAME; + else + return NULL; +} + +static void +lqasc_release_port(struct uart_port *port) +{ + if (port->flags & UPF_IOREMAP) { + iounmap(port->membase); + port->membase = NULL; + } +} + +static int +lqasc_request_port(struct uart_port *port) +{ + struct platform_device *pdev = to_platform_device(port->dev); + struct resource *res; + int size; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "cannot obtain I/O memory region"); + return -ENODEV; + } + size = resource_size(res); + + res = devm_request_mem_region(&pdev->dev, res->start, + size, dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "cannot request I/O memory region"); + return -EBUSY; + } + + if (port->flags & UPF_IOREMAP) { + port->membase = devm_ioremap_nocache(&pdev->dev, + port->mapbase, size); + if (port->membase == NULL) + return -ENOMEM; + } + return 0; +} + +static void +lqasc_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) { + port->type = PORT_LTQ_ASC; + lqasc_request_port(port); + } +} + +static int +lqasc_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) + ret = -EINVAL; + if (ser->irq < 0 || ser->irq >= NR_IRQS) + ret = -EINVAL; + if (ser->baud_base < 9600) + ret = -EINVAL; + return ret; +} + +static struct uart_ops lqasc_pops = { + .tx_empty = lqasc_tx_empty, + .set_mctrl = lqasc_set_mctrl, + .get_mctrl = lqasc_get_mctrl, + .stop_tx = lqasc_stop_tx, + .start_tx = lqasc_start_tx, + .stop_rx = lqasc_stop_rx, + .enable_ms = lqasc_enable_ms, + .break_ctl = lqasc_break_ctl, + .startup = lqasc_startup, + .shutdown = lqasc_shutdown, + .set_termios = lqasc_set_termios, + .type = lqasc_type, + .release_port = lqasc_release_port, + .request_port = lqasc_request_port, + .config_port = lqasc_config_port, + .verify_port = lqasc_verify_port, +}; + +static void +lqasc_console_putchar(struct uart_port *port, int ch) +{ + int fifofree; + + if (!port->membase) + return; + + do { + fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) + & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; + } while (fifofree == 0); + ltq_w8(ch, port->membase + LTQ_ASC_TBUF); +} + + +static void +lqasc_console_write(struct console *co, const char *s, u_int count) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + unsigned long flags; + + if (co->index >= MAXPORTS) + return; + + ltq_port = lqasc_port[co->index]; + if (!ltq_port) + return; + + port = <q_port->port; + + local_irq_save(flags); + uart_console_write(port, s, count, lqasc_console_putchar); + local_irq_restore(flags); +} + +static int __init +lqasc_console_setup(struct console *co, char *options) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + if (co->index >= MAXPORTS) + return -ENODEV; + + ltq_port = lqasc_port[co->index]; + if (!ltq_port) + return -ENODEV; + + port = <q_port->port; + + port->uartclk = clk_get_rate(ltq_port->clk); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console lqasc_console = { + .name = "ttyS", + .write = lqasc_console_write, + .device = uart_console_device, + .setup = lqasc_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &lqasc_reg, +}; + +static int __init +lqasc_console_init(void) +{ + register_console(&lqasc_console); + return 0; +} +console_initcall(lqasc_console_init); + +static struct uart_driver lqasc_reg = { + .owner = THIS_MODULE, + .driver_name = DRVNAME, + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .nr = MAXPORTS, + .cons = &lqasc_console, +}; + +static int __devinit +lqasc_probe(struct platform_device *pdev) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + struct resource *mmres, *irqres; + int tx_irq, rx_irq, err_irq; + struct clk *clk; + int ret; + + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!mmres || !irqres) + return -ENODEV; + + if (pdev->id >= MAXPORTS) + return -EBUSY; + + if (lqasc_port[pdev->id] != NULL) + return -EBUSY; + + clk = clk_get(&pdev->dev, "fpi"); + if (IS_ERR(clk)) { + pr_err("failed to get fpi clk\n"); + return -ENOENT; + } + + tx_irq = platform_get_irq_byname(pdev, "tx"); + if (tx_irq < 0) { + /* without named resources: assume standard irq scheme */ + tx_irq = irqres->start; + rx_irq = irqres->start+2; + err_irq = irqres->start+3; + } else { + /* other irqs must be named also! */ + rx_irq = platform_get_irq_byname(pdev, "rx"); + err_irq = platform_get_irq_byname(pdev, "err"); + if ((rx_irq < 0) | (err_irq < 0)) + return -ENODEV; + } + + ltq_port = kzalloc(sizeof(struct ltq_uart_port), GFP_KERNEL); + if (!ltq_port) + return -ENOMEM; + + port = <q_port->port; + + port->iotype = SERIAL_IO_MEM; + port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP; + port->ops = &lqasc_pops; + port->fifosize = 16; + port->type = PORT_LTQ_ASC, + port->line = pdev->id; + port->dev = &pdev->dev; + + port->irq = tx_irq; /* unused, just to be backward-compatibe */ + port->mapbase = mmres->start; + + ltq_port->clk = clk; + + ltq_port->tx_irq = tx_irq; + ltq_port->rx_irq = rx_irq; + ltq_port->err_irq = err_irq; + + lqasc_port[pdev->id] = ltq_port; + platform_set_drvdata(pdev, ltq_port); + + ret = uart_add_one_port(&lqasc_reg, port); + + return ret; +} + +static int __devexit +lqasc_remove(struct platform_device *pdev) +{ + struct ltq_uart_port *ltq_port = platform_get_drvdata(pdev); + int ret; + + clk_put(ltq_port->clk); + platform_set_drvdata(pdev, NULL); + lqasc_port[pdev->id] = NULL; + ret = uart_remove_one_port(&lqasc_reg, <q_port->port); + kfree(ltq_port); + + return 0; +} + +static struct platform_driver lqasc_driver = { + .probe = lqasc_probe, + .remove = __devexit_p(lqasc_remove), + + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, +}; + +int __init +init_lqasc(void) +{ + int ret; + + ret = uart_register_driver(&lqasc_reg); + if (ret != 0) + return ret; + + ret = platform_driver_register(&lqasc_driver); + if (ret != 0) + uart_unregister_driver(&lqasc_reg); + + return ret; +} + +void __exit +exit_lqasc(void) +{ + platform_driver_unregister(&lqasc_driver); + uart_unregister_driver(&lqasc_reg); +} + +module_init(init_lqasc); +module_exit(exit_lqasc); + +MODULE_DESCRIPTION("Lantiq serial port driver"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:14:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:14:17 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51016 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491941Ab1CAQM2 (ORCPT ); Tue, 1 Mar 2011 17:12:28 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 01/10] MIPS: lantiq: add initial support for Lantiq SoCs Date: Tue, 1 Mar 2011 17:13:17 +0100 Message-Id: <1298996006-15960-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29306 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. Changes in V2 * handle external interrup sources * properly set io_base * handle CMDLINE properly * remove custom early_printf Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 17 ++ arch/mips/include/asm/mach-lantiq/lantiq.h | 58 +++++ arch/mips/include/asm/mach-lantiq/war.h | 24 +++ arch/mips/lantiq/Makefile | 9 + arch/mips/lantiq/Platform | 7 + arch/mips/lantiq/clk.c | 132 ++++++++++++ arch/mips/lantiq/clk.h | 18 ++ arch/mips/lantiq/early_printk.c | 33 +++ arch/mips/lantiq/irq.c | 311 ++++++++++++++++++++++++++++ arch/mips/lantiq/prom.c | 74 +++++++ arch/mips/lantiq/prom.h | 24 +++ arch/mips/lantiq/setup.c | 47 +++++ 13 files changed, 755 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq.h create mode 100644 arch/mips/include/asm/mach-lantiq/war.h create mode 100644 arch/mips/lantiq/Makefile create mode 100644 arch/mips/lantiq/Platform create mode 100644 arch/mips/lantiq/clk.c create mode 100644 arch/mips/lantiq/clk.h create mode 100644 arch/mips/lantiq/early_printk.c create mode 100644 arch/mips/lantiq/irq.c create mode 100644 arch/mips/lantiq/prom.c create mode 100644 arch/mips/lantiq/prom.h create mode 100644 arch/mips/lantiq/setup.c diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 7ff9b54..aef6c91 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -11,6 +11,7 @@ platforms += dec platforms += emma platforms += jazz platforms += jz4740 +platforms += lantiq platforms += lasat platforms += loongson platforms += mipssim diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bd7b64d..f975932 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -210,6 +210,23 @@ config MACH_JZ4740 select SYS_HAS_EARLY_PRINTK select HAVE_PWM +config LANTIQ + bool "Lantiq based platforms" + select DMA_NONCOHERENT + select IRQ_CPU + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_MULTITHREADING + select SYS_HAS_EARLY_PRINTK + select ARCH_REQUIRE_GPIOLIB + select SWAP_IO_SPACE + select BOOT_RAW + select HAVE_CLK + config LASAT bool "LASAT Networks platforms" select CEVT_R4K diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h new file mode 100644 index 0000000..f7f4516 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -0,0 +1,58 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LANTIQ_H__ +#define _LANTIQ_H__ + +/* generic reg access functions */ +#define ltq_r32(reg) __raw_readl(reg) +#define ltq_w32(val, reg) __raw_writel(val, reg) +#define ltq_w32_mask(clear, set, reg) \ + ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg) +#define ltq_r8(reg) __raw_readb(reg) +#define ltq_w8(val, reg) __raw_writeb(val, reg) + +/* register access macros for EBU and CGU */ +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) +#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) +#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) + +extern __iomem void *ltq_ebu_membase; +extern __iomem void *ltq_cgu_membase; + +extern unsigned int ltq_get_cpu_ver(void); +extern unsigned int ltq_get_soc_type(void); + +/* clock speeds */ +#define CLOCK_60M 60000000 +#define CLOCK_83M 83333333 +#define CLOCK_111M 111111111 +#define CLOCK_133M 133333333 +#define CLOCK_167M 166666667 +#define CLOCK_200M 200000000 +#define CLOCK_266M 266666666 +#define CLOCK_333M 333333333 +#define CLOCK_400M 400000000 + +/* spinlock all ebu i/o */ +extern spinlock_t ebu_lock; + +/* some irq helpers */ +extern void ltq_disable_irq(unsigned int irq_nr); +extern void ltq_mask_and_ack_irq(unsigned int irq_nr); +extern void ltq_enable_irq(unsigned int irq_nr); + +#define IOPORT_RESOURCE_START 0x10000000 +#define IOPORT_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_START 0x10000000 +#define IOMEM_RESOURCE_END 0xffffffff +#define LTQ_FLASH_START 0x10000000 +#define LTQ_FLASH_MAX 0x04000000 + +#endif diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h new file mode 100644 index 0000000..01b08ef --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/war.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H +#define __ASM_MIPS_MACH_LANTIQ_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile new file mode 100644 index 0000000..6a30de6 --- /dev/null +++ b/arch/mips/lantiq/Makefile @@ -0,0 +1,9 @@ +# Copyright (C) 2010 John Crispin +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := irq.o setup.o clk.o prom.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform new file mode 100644 index 0000000..eef587f --- /dev/null +++ b/arch/mips/lantiq/Platform @@ -0,0 +1,7 @@ +# +# Lantiq +# + +platform-$(CONFIG_LANTIQ) += lantiq/ +cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq +load-$(CONFIG_LANTIQ) = 0xffffffff80002000 diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c new file mode 100644 index 0000000..cffca96 --- /dev/null +++ b/arch/mips/lantiq/clk.c @@ -0,0 +1,132 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "clk.h" + +struct clk { + const char *name; + unsigned long rate; + unsigned long (*get_rate) (void); +}; + +static struct clk *cpu_clk; +static int cpu_clk_cnt; + +/* lantiq socs have 3 static clocks */ +static struct clk cpu_clk_generic[] = { + { + .name = "cpu", + .get_rate = ltq_get_cpu_hz, + }, { + .name = "fpi", + .get_rate = ltq_get_fpi_hz, + }, { + .name = "io", + .get_rate = ltq_get_io_region_clock, + }, +}; + +/* remapped clock register range */ +__iomem void *ltq_cgu_membase; + +void +clk_init(void) +{ + cpu_clk = cpu_clk_generic; + cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic); +} + +static inline int +clk_good(struct clk *clk) +{ + return clk && !IS_ERR(clk); +} + +unsigned long +clk_get_rate(struct clk *clk) +{ + if (unlikely(!clk_good(clk))) + return 0; + + if (clk->rate != 0) + return clk->rate; + + if (clk->get_rate != NULL) + return clk->get_rate(); + + return 0; +} +EXPORT_SYMBOL(clk_get_rate); + +struct clk* +clk_get(struct device *dev, const char *id) +{ + int i; + for (i = 0; i < cpu_clk_cnt; i++) + if (!strcmp(id, cpu_clk[i].name)) + return &cpu_clk[i]; + BUG(); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +void +clk_put(struct clk *clk) +{ + /* not used */ +} +EXPORT_SYMBOL(clk_put); + +static inline u32 +ltq_get_counter_resolution(void) +{ + u32 res; + __asm__ __volatile__( + ".set push\n" + ".set mips32r2\n" + ".set noreorder\n" + "rdhwr %0, $3\n" + "ehb\n" + ".set pop\n" + : "=&r" (res) + : /* no input */ + : "memory"); + instruction_hazard(); + return res; +} + +void __init +plat_time_init(void) +{ + struct clk *clk; + ltq_cgu_membase = ioremap_nocache(LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); + if (!ltq_cgu_membase) { + printk(KERN_ERR "Failed to remap cgu memory\n"); + unreachable(); + } + clk = clk_get(0, "cpu"); + mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); + write_c0_compare(read_c0_count()); + clk_put(clk); +} diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h new file mode 100644 index 0000000..3328925 --- /dev/null +++ b/arch/mips/lantiq/clk.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_CLK_H__ +#define _LTQ_CLK_H__ + +extern void clk_init(void); + +extern unsigned long ltq_get_cpu_hz(void); +extern unsigned long ltq_get_fpi_hz(void); +extern unsigned long ltq_get_io_region_clock(void); + +#endif diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c new file mode 100644 index 0000000..195b3b6 --- /dev/null +++ b/arch/mips/lantiq/early_printk.c @@ -0,0 +1,33 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include + +#include +#include + +/* no ioremap possible at this early stage, lets use KSEG1 instead */ +#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) +#define ASC_BUF 1024 +#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) +#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) +#define TXMASK 0x3F00 +#define TXOFFSET 8 + +void +prom_putchar(char c) +{ + unsigned long flags; + local_irq_save(flags); + do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); + if (c == '\n') + ltq_w32('\r', LTQ_ASC_TBUF); + ltq_w32(c, LTQ_ASC_TBUF); + local_irq_restore(flags); +} diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c new file mode 100644 index 0000000..ecec87b --- /dev/null +++ b/arch/mips/lantiq/irq.c @@ -0,0 +1,311 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + * Copyright (C) 2010 Thomas Langer + */ + +#include +#include + +#include +#include + +#include +#include + +/* register definitions */ +#define LTQ_ICU_IM0_ISR 0x0000 +#define LTQ_ICU_IM0_IER 0x0008 +#define LTQ_ICU_IM0_IOSR 0x0010 +#define LTQ_ICU_IM0_IRSR 0x0018 +#define LTQ_ICU_IM0_IMR 0x0020 +#define LTQ_ICU_IM1_ISR 0x0028 +#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) + +#define LTQ_EIU_EXIN_C 0x0000 +#define LTQ_EIU_EXIN_INIC 0x0004 +#define LTQ_EIU_EXIN_INEN 0x000C + +/* irq numbers used by the external interrupt unit (EIU) */ +#define LTQ_EIU_IR0 INT_NUM_IM4_IRL0 + 30 +#define LTQ_EIU_IR1 INT_NUM_IM3_IRL0 + 31 +#define LTQ_EIU_IR2 INT_NUM_IM1_IRL0 + 26 +#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0 +#define LTQ_EIU_IR4 INT_NUM_IM1_IRL0 + 1 +#define LTQ_EIU_IR5 INT_NUM_IM1_IRL0 + 2 +#define LTQ_EIU_IR6 INT_NUM_IM2_IRL0 + 30 + +#define MAX_EIU 6 + +/* irqs generated by device attached to the EBU need to be acked in + a special manner */ +#define LTQ_ICU_EBU_IRQ 22 + +#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y)) +#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x)) + +#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) +#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) + +static unsigned short ltq_eiu_irq[MAX_EIU] = { + LTQ_EIU_IR0, + LTQ_EIU_IR1, + LTQ_EIU_IR2, + LTQ_EIU_IR3, + LTQ_EIU_IR4, + LTQ_EIU_IR5, +}; + +static __iomem void *ltq_icu_membase; +static __iomem void *ltq_eiu_membase; + +void +ltq_disable_irq(unsigned int irq_nr) +{ + u32 ier = LTQ_ICU_IM0_IER; + irq_nr -= INT_NUM_IRQ0; + ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); +} + +void +ltq_mask_and_ack_irq(unsigned int irq_nr) +{ + u32 ier = LTQ_ICU_IM0_IER; + u32 isr = LTQ_ICU_IM0_ISR; + irq_nr -= INT_NUM_IRQ0; + ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); + ltq_icu_w32((1 << irq_nr), isr); +} + +static void +ltq_ack_irq(unsigned int irq_nr) +{ + u32 isr = LTQ_ICU_IM0_ISR; + irq_nr -= INT_NUM_IRQ0; + isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + ltq_icu_w32((1 << irq_nr), isr); +} + +void +ltq_enable_irq(unsigned int irq_nr) +{ + u32 ier = LTQ_ICU_IM0_IER; + irq_nr -= INT_NUM_IRQ0; + ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier); +} + +static unsigned int +ltq_startup_eiu_irq(unsigned int irq) +{ + int i; + ltq_enable_irq(irq); + for (i = 0; i < MAX_EIU; i++) { + if (irq == ltq_eiu_irq[i]) { + /* low level - we should really handle set_type */ + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | (0x6 << (i * 4)), + LTQ_EIU_EXIN_C); + /* clear all pending */ + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~(1 << i), + LTQ_EIU_EXIN_INIC); + /* enable */ + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | (1 << i), + LTQ_EIU_EXIN_INEN); + break; + } + } + return 0; +} + +static void +ltq_shutdown_eiu_irq(unsigned int irq) +{ + int i; + ltq_disable_irq(irq); + for (i = 0; i < MAX_EIU; i++) { + if (irq == ltq_eiu_irq[i]) { + /* disable */ + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i), + LTQ_EIU_EXIN_INEN); + break; + } + } +} + +static void +ltq_end_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + ltq_enable_irq(irq); +} + +static struct irq_chip +ltq_irq_type = { + "ltq_irq", + .enable = ltq_enable_irq, + .disable = ltq_disable_irq, + .unmask = ltq_enable_irq, + .ack = ltq_ack_irq, + .mask = ltq_disable_irq, + .mask_ack = ltq_mask_and_ack_irq, + .end = ltq_end_irq, +}; + +static struct irq_chip +ltq_eiu_type = { + "ltq_eiu_irq", + .startup = ltq_startup_eiu_irq, + .shutdown = ltq_shutdown_eiu_irq, + .enable = ltq_enable_irq, + .disable = ltq_disable_irq, + .unmask = ltq_enable_irq, + .ack = ltq_ack_irq, + .mask = ltq_disable_irq, + .mask_ack = ltq_mask_and_ack_irq, + .end = ltq_end_irq, +}; + +static void +ltq_hw_irqdispatch(int module) +{ + u32 irq; + + irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); + if (irq == 0) + return; + + /* silicon bug causes only the msb set to 1 to be valid. all + other bits might be bogus */ + irq = __fls(irq); + do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); + + /* if this is a EBU irq, we need to ack it or get a deadlock */ + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, + LTQ_EBU_PCC_ISTAT); +} + +#define DEFINE_HWx_IRQDISPATCH(x) \ +static void ltq_hw ## x ## _irqdispatch(void)\ +{\ + ltq_hw_irqdispatch(x); \ +} +DEFINE_HWx_IRQDISPATCH(0) +DEFINE_HWx_IRQDISPATCH(1) +DEFINE_HWx_IRQDISPATCH(2) +DEFINE_HWx_IRQDISPATCH(3) +DEFINE_HWx_IRQDISPATCH(4) + +static void ltq_hw5_irqdispatch(void) +{ + do_IRQ(MIPS_CPU_TIMER_IRQ); +} + +asmlinkage void +plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + unsigned int i; + + if (pending & CAUSEF_IP7) { + do_IRQ(MIPS_CPU_TIMER_IRQ); + goto out; + } else { + for (i = 0; i < 5; i++) { + if (pending & (CAUSEF_IP2 << i)) { + ltq_hw_irqdispatch(i); + goto out; + } + } + } + printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); + +out: + return; +} + +static struct irqaction +cascade = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "cascade", +}; + +void __init +arch_init_irq(void) +{ + int i; + + ltq_icu_membase = ioremap_nocache(LTQ_ICU_BASE_ADDR, LTQ_ICU_SIZE); + if (!ltq_icu_membase) { + printk(KERN_ERR "Failed to remap irq memory\n"); + unreachable(); + } + + ltq_eiu_membase = ioremap_nocache(LTQ_EIU_BASE_ADDR, LTQ_EIU_SIZE); + if (!ltq_eiu_membase) { + printk(KERN_ERR "Failed to remap eiu memory\n"); + unreachable(); + } + + /* make sure all irqs are turned off by default */ + for (i = 0; i < 5; i++) + ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); + + /* clear all possibly pending interrupts */ + ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); + + mips_cpu_irq_init(); + + for (i = 2; i <= 6; i++) + setup_irq(i, &cascade); + + if (cpu_has_vint) { + printk(KERN_INFO "Setting up vectored interrupts\n"); + set_vi_handler(2, ltq_hw0_irqdispatch); + set_vi_handler(3, ltq_hw1_irqdispatch); + set_vi_handler(4, ltq_hw2_irqdispatch); + set_vi_handler(5, ltq_hw3_irqdispatch); + set_vi_handler(6, ltq_hw4_irqdispatch); + set_vi_handler(7, ltq_hw5_irqdispatch); + } + + for (i = INT_NUM_IRQ0; + i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) + if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || + (i == LTQ_EIU_IR2)) + set_irq_chip_and_handler(i, <q_eiu_type, + handle_level_irq); + /* EIU3-5 only exist on ar9 and vr9 */ + else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) || + (i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9())) + set_irq_chip_and_handler(i, <q_eiu_type, + handle_level_irq); + else + set_irq_chip_and_handler(i, <q_irq_type, + handle_level_irq); + +#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | + IE_IRQ3 | IE_IRQ4 | IE_IRQ5); +#else + set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | + IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); +#endif +} + +unsigned int __cpuinit +get_c0_compare_int(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c new file mode 100644 index 0000000..c00df3e --- /dev/null +++ b/arch/mips/lantiq/prom.c @@ -0,0 +1,74 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "prom.h" +#include "clk.h" + +static struct ltq_soc_info soc_info; + +unsigned int +ltq_get_cpu_ver(void) +{ + return soc_info.rev; +} +EXPORT_SYMBOL(ltq_get_cpu_ver); + +unsigned int +ltq_get_soc_type(void) +{ + return soc_info.type; +} +EXPORT_SYMBOL(ltq_get_soc_type); + +const char* +get_system_type(void) +{ + return soc_info.sys_type; +} + +void +prom_free_prom_memory(void) +{ +} + +static void __init +prom_init_cmdline(void) +{ + int argc = fw_arg0; + char **argv = (char **) KSEG1ADDR(fw_arg1); + int i; + for (i = 0; i < argc; i++) { + char *p = (char *) KSEG1ADDR(argv[i]); + if (p && *p) { + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + } + } +} + +void __init +prom_init(void) +{ + struct clk *clk; + ltq_soc_detect(&soc_info); + clk_init(); + clk = clk_get(0, "cpu"); + snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", + soc_info.name, soc_info.rev); + clk_put(clk); + soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; + printk(KERN_INFO "SoC: %s\n", soc_info.sys_type); + prom_init_cmdline(); +} diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h new file mode 100644 index 0000000..b9d6562 --- /dev/null +++ b/arch/mips/lantiq/prom.h @@ -0,0 +1,24 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_PROM_H__ +#define _LTQ_PROM_H__ + +#define LTQ_SYS_TYPE_LEN 0x100 + +struct ltq_soc_info { + unsigned char *name; + unsigned int rev; + unsigned int partnum; + unsigned int type; + unsigned char sys_type[LTQ_SYS_TYPE_LEN]; +}; + +void ltq_soc_detect(struct ltq_soc_info *i); + +#endif diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c new file mode 100644 index 0000000..edeb076 --- /dev/null +++ b/arch/mips/lantiq/setup.c @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include + +#include + +void __init +plat_mem_setup(void) +{ + /* assume 16M as default incase uboot fails to pass proper ramsize */ + unsigned long memsize = 16; + char **envp = (char **) KSEG1ADDR(fw_arg2); + u32 status; + + /* make sure to have no "reverse endian" for user mode */ + status = read_c0_status(); + status &= (~(1<<25)); + write_c0_status(status); + + ioport_resource.start = IOPORT_RESOURCE_START; + ioport_resource.end = IOPORT_RESOURCE_END; + iomem_resource.start = IOMEM_RESOURCE_START; + iomem_resource.end = IOMEM_RESOURCE_END; + + set_io_port_base((unsigned long) KSEG1); + + while (*envp) { + char *e = (char *)KSEG1ADDR(*envp); + if (!strncmp(e, "memsize=", 8)) { + e += 8; + strict_strtoul(e, 0, &memsize); + } + envp++; + } + memsize *= 1024 * 1024; + add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); +} -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:14:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:14:55 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51024 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491942Ab1CAQMa (ORCPT ); Tue, 1 Mar 2011 17:12:30 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 07/10] MIPS: lantiq: add platform device support Date: Tue, 1 Mar 2011 17:13:23 +0100 Message-Id: <1298996006-15960-8-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29307 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the wrappers for registering our platform devices. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/Makefile | 2 +- arch/mips/lantiq/devices.c | 128 +++++++++++++++++++++++++++++++++++++++ arch/mips/lantiq/devices.h | 20 ++++++ arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/devices.c | 79 ++++++++++++++++++++++++ arch/mips/lantiq/xway/devices.h | 17 +++++ 6 files changed, 246 insertions(+), 2 deletions(-) create mode 100644 arch/mips/lantiq/devices.c create mode 100644 arch/mips/lantiq/devices.h create mode 100644 arch/mips/lantiq/xway/devices.c create mode 100644 arch/mips/lantiq/xway/devices.h diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index a268391..e5dae0e 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -4,7 +4,7 @@ # under the terms of the GNU General Public License version 2 as published # by the Free Software Foundation. -obj-y := irq.o setup.o clk.o prom.o +obj-y := irq.o setup.o clk.o prom.o devices.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c new file mode 100644 index 0000000..6384b1f --- /dev/null +++ b/arch/mips/lantiq/devices.c @@ -0,0 +1,128 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "devices.h" + +#define IRQ_RES(resname, irq) \ + {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} + +/* nor flash */ +static struct resource ltq_nor_resource = { + .name = "nor", + .start = LTQ_FLASH_START, + .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ltq_nor = { + .name = "ltq_nor", + .resource = <q_nor_resource, + .num_resources = 1, +}; + +void __init +ltq_register_nor(struct physmap_flash_data *data) +{ + ltq_nor.dev.platform_data = data; + platform_device_register(<q_nor); +} + +/* watchdog */ +static struct resource ltq_wdt_resource = { + .name = "watchdog", + .start = LTQ_WDT_BASE_ADDR, + .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +void __init +ltq_register_wdt(void) +{ + platform_device_register_simple("ltq_wdt", 0, <q_wdt_resource, 1); +} + +/* asc ports */ +static struct resource ltq_asc0_resources[] = { + { + .start = LTQ_ASC0_BASE_ADDR, + .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + IRQ_RES(tx, LTQ_ASC_TIR(0)), + IRQ_RES(rx, LTQ_ASC_RIR(0)), + IRQ_RES(err, LTQ_ASC_EIR(0)), +}; + +static struct resource ltq_asc1_resources[] = { + { + .start = LTQ_ASC1_BASE_ADDR, + .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + IRQ_RES(tx, LTQ_ASC_TIR(1)), + IRQ_RES(rx, LTQ_ASC_RIR(1)), + IRQ_RES(err, LTQ_ASC_EIR(1)), +}; + +void __init +ltq_register_asc(int port) +{ + switch (port) { + case 0: + platform_device_register_simple("ltq_asc", 0, + ltq_asc0_resources, ARRAY_SIZE(ltq_asc0_resources)); + break; + case 1: + platform_device_register_simple("ltq_asc", 1, + ltq_asc1_resources, ARRAY_SIZE(ltq_asc1_resources)); + break; + default: + break; + } +} + +#ifdef CONFIG_PCI +/* pci */ +static struct platform_device ltq_pci = { + .name = "ltq_pci", + .num_resources = 0, +}; + +void __init +ltq_register_pci(struct ltq_pci_data *data) +{ + ltq_pci.dev.platform_data = data; + platform_device_register(<q_pci); +} +#else +void __init +ltq_register_pci(struct ltq_pci_data *data) +{ + printk(KERN_INFO "kernel is compiled without PCI support\n"); +} +#endif diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h new file mode 100644 index 0000000..069006c --- /dev/null +++ b/arch/mips/lantiq/devices.h @@ -0,0 +1,20 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_DEVICES_H__ +#define _LTQ_DEVICES_H__ + +#include +#include + +extern void ltq_register_nor(struct physmap_flash_data *data); +extern void ltq_register_wdt(void); +extern void ltq_register_asc(int port); +extern void ltq_register_pci(struct ltq_pci_data *data); + +#endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 9c85ff9..74ce438 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := pmu.o ebu.o reset.o gpio.o +obj-y := pmu.o ebu.o reset.o gpio.o devices.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c new file mode 100644 index 0000000..37543f8 --- /dev/null +++ b/arch/mips/lantiq/xway/devices.c @@ -0,0 +1,79 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +/* gpio */ +static struct resource ltq_gpio_resource[] = { + { + .name = "gpio0", + .start = LTQ_GPIO0_BASE_ADDR, + .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "gpio1", + .start = LTQ_GPIO1_BASE_ADDR, + .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "gpio2", + .start = LTQ_GPIO2_BASE_ADDR, + .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +void __init +ltq_register_gpio(void) +{ + platform_device_register_simple("ltq_gpio", 0, + <q_gpio_resource[0], 1); + platform_device_register_simple("ltq_gpio", 1, + <q_gpio_resource[1], 1); + + /* AR9 and VR9 have an extra gpio block */ + if (ltq_is_ar9() || ltq_is_vr9()) { + platform_device_register_simple("ltq_gpio", 2, + <q_gpio_resource[2], 1); + } +} + +/* serial to parallel conversion */ +static struct resource ltq_stp_resource = { + .name = "stp", + .start = LTQ_STP_BASE_ADDR, + .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +void __init +ltq_register_gpio_stp(void) +{ + platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1); +} diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h new file mode 100644 index 0000000..87ba61e --- /dev/null +++ b/arch/mips/lantiq/xway/devices.h @@ -0,0 +1,17 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_DEVICES_XWAY_H__ +#define _LTQ_DEVICES_XWAY_H__ + +#include "../devices.h" + +extern void ltq_register_gpio(void); +extern void ltq_register_gpio_stp(void); + +#endif -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:15:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:15:18 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51029 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491943Ab1CAQMb (ORCPT ); Tue, 1 Mar 2011 17:12:31 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , Gabor Juhos , linux-mips@linux-mips.org Subject: [PATCH V2 08/10] MIPS: lantiq: add mips_machine support Date: Tue, 1 Mar 2011 17:13:24 +0100 Message-Id: <1298996006-15960-9-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29308 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for Gabor's mips_machine patch. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: Gabor Juhos Cc: linux-mips@linux-mips.org --- arch/mips/Kconfig | 1 + arch/mips/lantiq/machtypes.h | 18 ++++++++++++++++++ arch/mips/lantiq/setup.c | 25 +++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 0 deletions(-) create mode 100644 arch/mips/lantiq/machtypes.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 756e67a..90f405c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -226,6 +226,7 @@ config LANTIQ select SWAP_IO_SPACE select BOOT_RAW select HAVE_CLK + select MIPS_MACHINE config LASAT bool "LASAT Networks platforms" diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h new file mode 100644 index 0000000..ffcacfc --- /dev/null +++ b/arch/mips/lantiq/machtypes.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LANTIQ_MACH_H__ +#define _LANTIQ_MACH_H__ + +#include + +enum lantiq_mach_type { + LTQ_MACH_GENERIC = 0, +}; + +#endif diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c index edeb076..bf35435 100644 --- a/arch/mips/lantiq/setup.c +++ b/arch/mips/lantiq/setup.c @@ -14,6 +14,9 @@ #include +#include "machtypes.h" +#include "devices.h" + void __init plat_mem_setup(void) { @@ -45,3 +48,25 @@ plat_mem_setup(void) memsize *= 1024 * 1024; add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); } + +static int __init +lantiq_setup(void) +{ + ltq_register_asc(0); + ltq_register_asc(1); + mips_machine_setup(); + return 0; +} + +arch_initcall(lantiq_setup); + +static void __init +lantiq_generic_init(void) +{ + /* Nothing to do */ +} + +MIPS_MACHINE(LTQ_MACH_GENERIC, + "Generic", + "Generic Lantiq based board", + lantiq_generic_init); -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:15:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:15:42 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51030 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491944Ab1CAQMb (ORCPT ); Tue, 1 Mar 2011 17:12:31 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: [PATCH V2 05/10] MIPS: lantiq: add watchdog support Date: Tue, 1 Mar 2011 17:13:21 +0100 Message-Id: <1298996006-15960-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29309 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the watchdog found inside the Lantiq SoC family. Changes in V2 * add comments to explain register access * cleanup resource allocation * cleanup clock handling * whitespace fixes Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: Wim Van Sebroeck Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/lantiq_wdt.c | 233 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 240 insertions(+), 0 deletions(-) create mode 100644 drivers/watchdog/lantiq_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 2e2400e..c64f8c3 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -972,6 +972,12 @@ config BCM63XX_WDT To compile this driver as a loadable module, choose M here. The module will be called bcm63xx_wdt. +config LANTIQ_WDT + tristate "Lantiq SoC watchdog" + depends on LANTIQ + help + Hardware driver for the Lantiq SoC Watchdog Timer. + # PARISC Architecture # POWERPC Architecture diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index dd77665..68299db 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -121,6 +121,7 @@ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o obj-$(CONFIG_TXX9_WDT) += txx9wdt.o obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o # PARISC Architecture diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c new file mode 100644 index 0000000..8515c1f --- /dev/null +++ b/drivers/watchdog/lantiq_wdt.c @@ -0,0 +1,233 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + * Based on EP93xx wdt driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Section 3.4 of the datasheet + The password sequence protects the WDT control register from unintended + write actions, which might cause malfunction of the WDT. + + essentially the following two magic passwords need to be written to allow + io access to the wdt core */ +#define LTQ_WDT_PW1 0x00BE0000 +#define LTQ_WDT_PW2 0x00DC0000 + +#define LTQ_WDT_CR 0x03F0 /* watchdog control register */ +#define LTQ_WDT_SR 0x03F8 /* watchdog status register */ + +#define LTQ_WDT_SR_EN (0x1 << 31) /* enable bit */ +#define LTQ_WDT_SR_PWD (0x3 << 26) /* turn on power */ +#define LTQ_WDT_SR_CLKDIV (0x3 << 24) /* turn on clock and set */ + /* divider to 0x40000 */ +#define LTQ_WDT_DIVIDER 0x40000 +#define LTQ_MAX_TIMEOUT ((1 << 16) - 1) /* the reload field is 16 bit */ + +#ifndef CONFIG_WATCHDOG_NOWAYOUT +static int ltq_wdt_ok_to_close; +#endif + +static int ltq_wdt_timeout = 30; +static __iomem void *ltq_wdt_membase; +static unsigned long ltq_io_region_clk_rate; + +static int +ltq_wdt_enable(unsigned int timeout) +{ + timeout = ((timeout * (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER)) + + 0x1000); + if (timeout > LTQ_MAX_TIMEOUT) + timeout = LTQ_MAX_TIMEOUT; + + /* write the first paswword magic */ + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); + /* write the second magic plus the configuration and new timeout */ + ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV | + LTQ_WDT_PW2 | timeout, ltq_wdt_membase + LTQ_WDT_CR); + return 0; +} + +static void +ltq_wdt_disable(void) +{ +#ifndef CONFIG_WATCHDOG_NOWAYOUT + ltq_wdt_ok_to_close = 0; +#endif + /* write the first paswword magic */ + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); + /* write the second paswword magic with no config + this turns the watchdog off */ + ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR); +} + +static ssize_t +ltq_wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) +{ + size_t i; + if (!len) + return 0; +#ifndef CONFIG_WATCHDOG_NOWAYOUT + for (i = 0; i != len; i++) { + char c; + if (get_user(c, data + i)) + return -EFAULT; + if (c == 'V') + ltq_wdt_ok_to_close = 1; + } +#endif + ltq_wdt_enable(ltq_wdt_timeout); + return len; +} + +static struct watchdog_info ident = { + .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, + .identity = "ltq_wdt", +}; + +static long +ltq_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = -ENOTTY; + switch (cmd) { + case WDIOC_GETSUPPORT: + ret = copy_to_user((struct watchdog_info __user *)arg, &ident, + sizeof(ident)) ? -EFAULT : 0; + break; + + case WDIOC_GETTIMEOUT: + ret = put_user(ltq_wdt_timeout, (int __user *)arg); + break; + + case WDIOC_SETTIMEOUT: + ret = get_user(ltq_wdt_timeout, (int __user *)arg); + if (!ret) + ltq_wdt_enable(ltq_wdt_timeout); + break; + + case WDIOC_KEEPALIVE: + ltq_wdt_enable(ltq_wdt_timeout); + ret = 0; + break; + } + return ret; +} + +static int +ltq_wdt_open(struct inode *inode, struct file *file) +{ + ltq_wdt_enable(ltq_wdt_timeout); + return nonseekable_open(inode, file); +} + +static int +ltq_wdt_release(struct inode *inode, struct file *file) +{ +#ifndef CONFIG_WATCHDOG_NOWAYOUT + if (ltq_wdt_ok_to_close) + ltq_wdt_disable(); + else +#endif + printk(KERN_ERR "ltq_wdt: watchdog closed without warning\n"); + return 0; +} + +static const struct file_operations ltq_wdt_fops = { + .owner = THIS_MODULE, + .write = ltq_wdt_write, + .unlocked_ioctl = ltq_wdt_ioctl, + .open = ltq_wdt_open, + .release = ltq_wdt_release, + .llseek = no_llseek, +}; + +static struct miscdevice ltq_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = <q_wdt_fops, +}; + +static int +ltq_wdt_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk *clk; + int ret = 0; + if (!res) { + dev_err(&pdev->dev, "cannot obtain I/O memory region"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "cannot request I/O memory region"); + return -EBUSY; + } + ltq_wdt_membase = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ltq_wdt_membase) { + dev_err(&pdev->dev, "cannot remap I/O memory region\n"); + return -ENOMEM; + } + /* we do not need to enable the clock as it is always running */ + clk = clk_get(&pdev->dev, "io"); + ltq_io_region_clk_rate = clk_get_rate(clk); + clk_put(clk); + ret = misc_register(<q_wdt_miscdev); + if (ret) + return 0; + + return ret; +} + +static int +ltq_wdt_remove(struct platform_device *dev) +{ + ltq_wdt_disable(); + misc_deregister(<q_wdt_miscdev); + return 0; +} + +static struct platform_driver ltq_wdt_driver = { + .probe = ltq_wdt_probe, + .remove = ltq_wdt_remove, + .driver = { + .name = "ltq_wdt", + .owner = THIS_MODULE, + }, +}; + +static int __init +init_ltq_wdt(void) +{ + return platform_driver_register(<q_wdt_driver); +} + +static void __exit +exit_ltq_wdt(void) +{ + platform_driver_unregister(<q_wdt_driver); +} + +module_init(init_ltq_wdt); +module_exit(exit_ltq_wdt); + +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq Watchdog"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:16:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:16:06 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51034 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491945Ab1CAQMc (ORCPT ); Tue, 1 Mar 2011 17:12:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 09/10] MIPS: lantiq: add machtypes for lantiq eval kits Date: Tue, 1 Mar 2011 17:13:25 +0100 Message-Id: <1298996006-15960-10-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29310 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds mach specific code for the Lantiq EASY50712/50601 evaluation boards Changes in V2: * fix pci platform_device data Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/Kconfig | 2 + arch/mips/lantiq/machtypes.h | 2 + arch/mips/lantiq/xway/Kconfig | 25 +++++++++++ arch/mips/lantiq/xway/Makefile | 3 + arch/mips/lantiq/xway/mach-easy50601.c | 70 +++++++++++++++++++++++++++++ arch/mips/lantiq/xway/mach-easy50712.c | 75 ++++++++++++++++++++++++++++++++ 6 files changed, 177 insertions(+), 0 deletions(-) create mode 100644 arch/mips/lantiq/xway/Kconfig create mode 100644 arch/mips/lantiq/xway/mach-easy50601.c create mode 100644 arch/mips/lantiq/xway/mach-easy50712.c diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 2780461..3fccf21 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -18,4 +18,6 @@ config SOC_XWAY select HW_HAS_PCI endchoice +source "arch/mips/lantiq/xway/Kconfig" + endif diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h index ffcacfc..7e01b8c 100644 --- a/arch/mips/lantiq/machtypes.h +++ b/arch/mips/lantiq/machtypes.h @@ -13,6 +13,8 @@ enum lantiq_mach_type { LTQ_MACH_GENERIC = 0, + LTQ_MACH_EASY50712, /* Danube evaluation board */ + LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ }; #endif diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig new file mode 100644 index 0000000..f6d0bec --- /dev/null +++ b/arch/mips/lantiq/xway/Kconfig @@ -0,0 +1,25 @@ +if SOC_XWAY + +menu "Mips Machine" + +config LANTIQ_MACH_EASY50712 + bool "Easy50712 - Danube" + default y + +endmenu + +endif + +if SOC_AMAZON_SE + +menu "Mips Machine" + +config LANTIQ_MACH_EASY50601 + bool "Easy50601 - Amazon SE" + default y + +endmenu + +endif + + diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 74ce438..08dcc10 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -2,3 +2,6 @@ obj-y := pmu.o ebu.o reset.o gpio.o devices.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o + +obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o +obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c new file mode 100644 index 0000000..ce081d7 --- /dev/null +++ b/arch/mips/lantiq/xway/mach-easy50601.c @@ -0,0 +1,70 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "../machtypes.h" +#include "devices.h" + +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition easy50601_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x10000, + }, + { + .name = "uboot_env", + .offset = 0x10000, + .size = 0x10000, + }, + { + .name = "linux", + .offset = 0x20000, + .size = 0xE0000, + }, + { + .name = "rootfs", + .offset = 0x100000, + .size = 0x300000, + }, +}; +#endif + +static struct physmap_flash_data easy50601_flash_data = { +#ifdef CONFIG_MTD_PARTITIONS + .nr_parts = ARRAY_SIZE(easy50601_partitions), + .parts = easy50601_partitions, +#endif +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .req_mask = 0xf, +}; + +static void __init +easy50601_init(void) +{ + ltq_register_gpio(); + ltq_register_nor(&easy50601_flash_data); + ltq_register_wdt(); + ltq_register_pci(<q_pci_data); +} + +MIPS_MACHINE(LTQ_MACH_EASY50601, + "EASY50601", + "EASY50601 Eval Board", + easy50601_init); diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c new file mode 100644 index 0000000..d7963c6 --- /dev/null +++ b/arch/mips/lantiq/xway/mach-easy50712.c @@ -0,0 +1,75 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../machtypes.h" +#include "devices.h" + +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition easy50712_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x10000, + }, + { + .name = "uboot_env", + .offset = 0x10000, + .size = 0x10000, + }, + { + .name = "linux", + .offset = 0x20000, + .size = 0xe0000, + }, + { + .name = "rootfs", + .offset = 0x100000, + .size = 0x300000, + }, +}; +#endif + +static struct physmap_flash_data easy50712_flash_data = { +#ifdef CONFIG_MTD_PARTITIONS + .nr_parts = ARRAY_SIZE(easy50712_partitions), + .parts = easy50712_partitions, +#endif +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .gpio = PCI_GNT1 | PCI_REQ1, + .irq = { + [14] = INT_NUM_IM0_IRL0 + 22, + }, +}; + +static void __init +easy50712_init(void) +{ + ltq_register_gpio(); + ltq_register_gpio_stp(); + ltq_register_nor(&easy50712_flash_data); + ltq_register_wdt(); + ltq_register_pci(<q_pci_data); +} + +MIPS_MACHINE(LTQ_MACH_EASY50712, + "EASY50712", + "EASY50712 Eval Board", + easy50712_init); -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:16:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:16:29 +0100 (CET) Received: from nbd.name ([46.4.11.11]:51035 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491946Ab1CAQMc (ORCPT ); Tue, 1 Mar 2011 17:12:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: [PATCH V2 06/10] MIPS: lantiq: add NOR flash support Date: Tue, 1 Mar 2011 17:13:22 +0100 Message-Id: <1298996006-15960-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29311 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described in the PCI patch, the EBU is a little buggy, resulting in the upper and lower 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2) To work around this we do a addr^=2 during the probe. Once probed we adapt cfi->addr_unlock1 and cfi->addr_unlock2 to represent the endianess bug. Changes in V2 * handle the endianess bug inside the map code and not in the generic cfi code * remove the addr swizzle patch Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: David Woodhouse Cc: Daniel Schwierzeck Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org --- drivers/mtd/maps/Kconfig | 7 ++ drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq.c | 186 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 194 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/maps/lantiq.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 5d37d31..587468e 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -260,6 +260,13 @@ config MTD_BCM963XX Support for parsing CFE image tag and creating MTD partitions on Broadcom BCM63xx boards. +config MTD_LANTIQ + bool "Lantiq SoC NOR support" + depends on LANTIQ && MTD_PARTITIONS + help + Support for NOR flash chips on Lantiq SoC. The Chips are connected + to the SoCs EBU (External Bus Unit) + config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index c7869c7..bb2ce2f 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o obj-$(CONFIG_MTD_VMU) += vmu-flash.o obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o +obj-$(CONFIG_MTD_LANTIQ) += lantiq.o diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c new file mode 100644 index 0000000..a630804 --- /dev/null +++ b/drivers/mtd/maps/lantiq.c @@ -0,0 +1,186 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* the NOR flash is connected to the same external bus unit (EBU) as PCI + to make PCI work we need to enable the endianess swapping of the addr + written to the EBU. this however has some limitations and breaks when + using NOR. it does not really matter if the onflash data is in a swapped + order, however cfi sequences also fail. to workaround this we need to use + a complex map. We essentially software swap all addresses during probe + and then swizzle the unlock addresses. + */ +static int ltq_mtd_probing; + +static map_word +ltq_read16(struct map_info *map, unsigned long adr) +{ + unsigned long flags; + map_word temp; + if (ltq_mtd_probing) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + temp.x[0] = *((__u16 *)(map->virt + adr)); + spin_unlock_irqrestore(&ebu_lock, flags); + return temp; +} + +static void +ltq_write16(struct map_info *map, map_word d, unsigned long adr) +{ + unsigned long flags; + if (ltq_mtd_probing) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + *((__u16 *)(map->virt + adr)) = d.x[0]; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +void +ltq_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + unsigned char *p; + unsigned char *to_8; + unsigned long flags; + spin_lock_irqsave(&ebu_lock, flags); + from = (unsigned long) (map->virt + from); + p = (unsigned char *) from; + to_8 = (unsigned char *) to; + while (len--) + *to_8++ = *p++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +void +ltq_copy_to(struct map_info *map, unsigned long to, + const void *from, ssize_t len) +{ + unsigned char *p = (unsigned char *)from; + unsigned char *to_8; + unsigned long flags; + spin_lock_irqsave(&ebu_lock, flags); + to += (unsigned long) map->virt; + to_8 = (unsigned char *)to; + while (len--) + *p++ = *to_8++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static const char *part_probe_types[] = { + "cmdlinepart", NULL }; + +static struct map_info ltq_map = { + .name = "ltq_nor", + .bankwidth = 2, + .read = ltq_read16, + .write = ltq_write16, + .copy_from = ltq_copy_from, + .copy_to = ltq_copy_to, +}; + +static int +ltq_mtd_probe(struct platform_device *pdev) +{ + struct physmap_flash_data *ltq_mtd_data = + (struct physmap_flash_data *) dev_get_platdata(&pdev->dev); + struct mtd_info *ltq_mtd = NULL; + struct mtd_partition *parts = NULL; + struct resource *res = 0; + int nr_parts = 0; + struct cfi_private *cfi; + +#ifdef CONFIG_SOC_TYPE_XWAY + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); +#endif + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request mem resource"); + return -EBUSY; + } + + ltq_map.phys = res->start; + ltq_map.size = resource_size(res); + ltq_map.virt = devm_ioremap_nocache(&pdev->dev, ltq_map.phys, + ltq_map.size); + if (!ltq_map.virt) { + dev_err(&pdev->dev, "failed to ioremap!\n"); + return -EIO; + } + + ltq_mtd_probing = 1; + ltq_mtd = (struct mtd_info *) do_map_probe("cfi_probe", <q_map); + ltq_mtd_probing = 0; + if (!ltq_mtd) { + iounmap(ltq_map.virt); + dev_err(&pdev->dev, "probing failed\n"); + return -ENXIO; + } + ltq_mtd->owner = THIS_MODULE; + + cfi = (struct cfi_private *)ltq_map.fldrv_priv; + cfi->addr_unlock1 ^= 1; + cfi->addr_unlock2 ^= 1; + + nr_parts = parse_mtd_partitions(ltq_mtd, part_probe_types, &parts, 0); + if (nr_parts > 0) { + dev_info(&pdev->dev, + "using %d partitions from cmdline", nr_parts); + } else { + nr_parts = ltq_mtd_data->nr_parts; + parts = ltq_mtd_data->parts; + } + + add_mtd_partitions(ltq_mtd, parts, nr_parts); + return 0; +} + +static struct platform_driver ltq_mtd_driver = { + .probe = ltq_mtd_probe, + .driver = { + .name = "ltq_nor", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_mtd(void) +{ + int ret = platform_driver_register(<q_mtd_driver); + if (ret) + printk(KERN_INFO "ltq_nor: error registering platfom driver"); + return ret; +} + +module_init(init_ltq_mtd); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC NOR"); -- 1.7.2.3 From blogic@openwrt.org Tue Mar 1 17:17:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Mar 2011 17:17:40 +0100 (CET) Received: from nbd.name ([46.4.11.11]:54381 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491942Ab1CAQRg (ORCPT ); Tue, 1 Mar 2011 17:17:36 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V2 10/10] MIPS: lantiq: add more gpio drivers Date: Tue, 1 Mar 2011 17:13:26 +0100 Message-Id: <1298996006-15960-11-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298996006-15960-1-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29312 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips The XWAY family allows to extend the number of gpios by using shift registers or latches. This patch adds the 2 drivers needed for this. The extended gpios are output only. Added in V2 Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/gpio_ebu.c | 125 ++++++++++++++++++++++++++++++ arch/mips/lantiq/xway/gpio_stp.c | 157 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 283 insertions(+), 1 deletions(-) create mode 100644 arch/mips/lantiq/xway/gpio_ebu.c create mode 100644 arch/mips/lantiq/xway/gpio_stp.c diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 08dcc10..a021def 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := pmu.o ebu.o reset.o gpio.o devices.o +obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c new file mode 100644 index 0000000..74c3837 --- /dev/null +++ b/arch/mips/lantiq/xway/gpio_ebu.c @@ -0,0 +1,125 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* By attaching hardware latches to the EBU it is possible to create output + * only gpios. This driver configures a special memory address, which when + * written to outputs 16 bit to the latches. + */ + +#define LTQ_EBU_BUSCON 0x1e7ff /* 16 bit access, slowest timing */ +#define LTQ_EBU_WP 0x80000000 /* write protect bit */ + +/* we keep a ltq_ebu_gpio_shadow value of the last value written to the ebu */ +static int ltq_ebu_gpio_shadow = 0x0; +static __iomem void *ltq_ebu_gpio_membase; + +static void +ltq_ebu_apply(void) +{ + unsigned long flags; + spin_lock_irqsave(&ebu_lock, flags); + ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1); + *((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow; + ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1); + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static void +ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value) +{ + if (value) + ltq_ebu_gpio_shadow |= (1 << offset); + else + ltq_ebu_gpio_shadow &= ~(1 << offset); + ltq_ebu_apply(); +} + +static int +ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + ltq_ebu_set(chip, offset, value); + return 0; +} + +static struct gpio_chip +ltq_ebu_chip = { + .label = "ltq_ebu", + .direction_output = ltq_ebu_direction_output, + .set = ltq_ebu_set, + .base = 72, + .ngpio = 16, + .can_sleep = 1, + .owner = THIS_MODULE, +}; + +static int __devinit +ltq_ebu_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource\n"); + return -ENOENT; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + return -EBUSY; + } + + ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ltq_ebu_gpio_membase) { + dev_err(&pdev->dev, "Failed to ioremap mem region\n"); + return -ENOMEM; + } + + /* grab the default shadow value passed form the platform code */ + ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data; + + /* tell the ebu controller which mem addr we will be using */ + ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1); + + /* write protect the region */ + ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1); + + ret = gpiochip_add(<q_ebu_chip); + if (!ret) + ltq_ebu_apply(); + return ret; +} + +static struct platform_driver +ltq_ebu_driver = { + .probe = ltq_ebu_probe, + .driver = { + .name = "ltq_ebu", + .owner = THIS_MODULE, + }, +}; + +static int __init +ltq_ebu_init(void) +{ + return platform_driver_register(<q_ebu_driver); +} + +postcore_initcall(ltq_ebu_init); diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c new file mode 100644 index 0000000..97e724a --- /dev/null +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -0,0 +1,157 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2007 John Crispin + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LTQ_STP_CON0 0x00 +#define LTQ_STP_CON1 0x04 +#define LTQ_STP_CPU0 0x08 +#define LTQ_STP_CPU1 0x0C +#define LTQ_STP_AR 0x10 + +#define STP_CON0_SWU (1 << 31) +#define LTQ_STP_2HZ (0) +#define LTQ_STP_4HZ (1 << 23) +#define LTQ_STP_8HZ (2 << 23) +#define LTQ_STP_10HZ (3 << 23) +#define LTQ_STP_MASK (0xf << 23) +#define LTQ_STP_UPD_SRC_FPI (1 << 31) +#define LTQ_STP_UPD_MASK (3 << 30) +#define LTQ_STP_ADSL_SRC (3 << 24) + +#define LTQ_STP_GROUP0 (1 << 0) + +#define LTQ_STP_RISING 0 +#define LTQ_STP_FALLING (1 << 26) +#define LTQ_STP_EDGE_MASK (1 << 26) + +#define ltq_stp_r32(reg) __raw_readl(ltq_stp_membase + reg) +#define ltq_stp_w32(val, reg) __raw_writel(val, ltq_stp_membase + reg) +#define ltq_stp_w32_mask(clear, set, reg) \ + ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \ + ltq_stp_membase + (reg)) + +static int ltq_stp_shadow = 0xffff; +static __iomem void *ltq_stp_membase; + +static void +ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value) +{ + if (value) + ltq_stp_shadow |= (1 << offset); + else + ltq_stp_shadow &= ~(1 << offset); + ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0); +} + +static int +ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + ltq_stp_set(chip, offset, value); + return 0; +} + +static struct gpio_chip ltq_stp_chip = { + .label = "ltq_stp", + .direction_output = ltq_stp_direction_output, + .set = ltq_stp_set, + .base = 48, + .ngpio = 24, + .can_sleep = 1, + .owner = THIS_MODULE, +}; + +static int +ltq_stp_hw_init(void) +{ + /* the 3 pins used to control the external stp */ + ltq_gpio_request(4, 1, 0, 1, "stp-st"); + ltq_gpio_request(5, 1, 0, 1, "stp-d"); + ltq_gpio_request(6, 1, 0, 1, "stp-sh"); + + /* sane defaults */ + ltq_stp_w32(0, LTQ_STP_AR); + ltq_stp_w32(0, LTQ_STP_CPU0); + ltq_stp_w32(0, LTQ_STP_CPU1); + ltq_stp_w32(STP_CON0_SWU, LTQ_STP_CON0); + ltq_stp_w32(0, LTQ_STP_CON1); + + /* rising or falling edge */ + ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0); + + /* per default stp 15-0 are set */ + ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1); + + /* stp are update periodically by the FPID */ + ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_SRC_FPI, LTQ_STP_CON1); + + /* set stp update speed */ + ltq_stp_w32_mask(LTQ_STP_MASK, LTQ_STP_8HZ, LTQ_STP_CON1); + + /* adsl 0 and 1 stp are updated by the arc */ + ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0); + + ltq_pmu_enable(PMU_LED); + return 0; +} + +static int +ltq_stp_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + int ret = 0; + if (!res) + return -ENOENT; + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request STP memory\n"); + return -EBUSY; + } + ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ltq_stp_membase) { + dev_err(&pdev->dev, "failed to remap STP memory\n"); + return -ENOMEM; + } + ret = gpiochip_add(<q_stp_chip); + if (!ret) + ret = ltq_stp_hw_init(); + + return ret; +} + +static struct platform_driver ltq_stp_driver = { + .probe = ltq_stp_probe, + .driver = { + .name = "ltq_stp", + .owner = THIS_MODULE, + }, +}; + +int __init +ltq_stp_init(void) +{ + int ret = platform_driver_register(<q_stp_driver); + if (ret) + printk(KERN_INFO + "ltq_stp: error registering platfom driver"); + return ret; +} + +postcore_initcall(ltq_stp_init); -- 1.7.2.3 From sshtylyov@mvista.com Wed Mar 2 12:23:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Mar 2011 12:23:53 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:56005 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491054Ab1CBLXt (ORCPT ); Wed, 2 Mar 2011 12:23:49 +0100 Received: by bwz1 with SMTP id 1so51926bwz.36 for ; Wed, 02 Mar 2011 03:23:42 -0800 (PST) Received: by 10.204.22.16 with SMTP id l16mr7249947bkb.198.1299065021994; Wed, 02 Mar 2011 03:23:41 -0800 (PST) Received: from [192.168.2.2] ([91.79.108.232]) by mx.google.com with ESMTPS id b16sm4073689bkw.2.2011.03.02.03.23.39 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 Mar 2011 03:23:40 -0800 (PST) Message-ID: <4D6E286D.9050100@mvista.com> Date: Wed, 02 Mar 2011 14:22:21 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> In-Reply-To: <1298996006-15960-6-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29313 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 01-03-2011 19:13, John Crispin wrote: > This patch adds the driver for the watchdog found inside the Lantiq SoC family. > Changes in V2 > * add comments to explain register access > * cleanup resource allocation > * cleanup clock handling > * whitespace fixes The patch revision history is normally put under --- tearline. > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel > Cc: Wim Van Sebroeck > Cc: linux-mips@linux-mips.org > Cc: linux-watchdog@vger.kernel.org [...] > diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c > new file mode 100644 > index 0000000..8515c1f > --- /dev/null > +++ b/drivers/watchdog/lantiq_wdt.c > @@ -0,0 +1,233 @@ > +/* > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + * > + * Copyright (C) 2010 John Crispin > + * Based on EP93xx wdt driver > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +/* Section 3.4 of the datasheet > + The password sequence protects the WDT control register from unintended > + write actions, which might cause malfunction of the WDT. > + > + essentially the following two magic passwords need to be written to allow > + io access to the wdt core */ The preferred style for the multi-line comments is this: /* * bla * bla */ > +#define LTQ_WDT_CR 0x03F0 /* watchdog control register */ > +#define LTQ_WDT_SR 0x03F8 /* watchdog status register */ > + > +#define LTQ_WDT_SR_EN (0x1 << 31) /* enable bit */ > +#define LTQ_WDT_SR_PWD (0x3 << 26) /* turn on power */ > +#define LTQ_WDT_SR_CLKDIV (0x3 << 24) /* turn on clock and set */ > + /* divider to 0x40000 */ > +#define LTQ_WDT_DIVIDER 0x40000 > +#define LTQ_MAX_TIMEOUT ((1 << 16) - 1) /* the reload field is 16 bit */ Should align like the above... > + > +#ifndef CONFIG_WATCHDOG_NOWAYOUT > +static int ltq_wdt_ok_to_close; > +#endif > + > +static int ltq_wdt_timeout = 30; > +static __iomem void *ltq_wdt_membase; It's normally "void __iomem *". > +static unsigned long ltq_io_region_clk_rate; > + > +static int > +ltq_wdt_enable(unsigned int timeout) > +{ > + timeout = ((timeout * (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER)) > + + 0x1000); > + if (timeout > LTQ_MAX_TIMEOUT) > + timeout = LTQ_MAX_TIMEOUT; > + > + /* write the first paswword magic */ s/paswword/password/. > + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); > + /* write the second magic plus the configuration and new timeout */ > + ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV | > + LTQ_WDT_PW2 | timeout, ltq_wdt_membase + LTQ_WDT_CR); > + return 0; This function should be *void* -- you alway return 0 and never check the result. > +} > + > +static void > +ltq_wdt_disable(void) > +{ > +#ifndef CONFIG_WATCHDOG_NOWAYOUT > + ltq_wdt_ok_to_close = 0; > +#endif > + /* write the first paswword magic */ > + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); > + /* write the second paswword magic with no config > + this turns the watchdog off */ Multi-line comment style... > + ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR); > +} > + > +static ssize_t > +ltq_wdt_write(struct file *file, const char __user *data, > + size_t len, loff_t *ppos) > +{ > + size_t i; Empty line between the variables and code won't hurt... > + if (!len) > + return 0; > +#ifndef CONFIG_WATCHDOG_NOWAYOUT > + for (i = 0; i != len; i++) { > + char c; Here too... > + if (get_user(c, data + i)) > + return -EFAULT; > + if (c == 'V') > + ltq_wdt_ok_to_close = 1; > + } > +#endif [...] > +static long > +ltq_wdt_ioctl(struct file *file, > + unsigned int cmd, unsigned long arg) > +{ > + int ret = -ENOTTY; Empty line between the variables and code won't hurt... > + switch (cmd) { > + case WDIOC_GETSUPPORT: > + ret = copy_to_user((struct watchdog_info __user *)arg, &ident, > + sizeof(ident)) ? -EFAULT : 0; Doesn't copy_to_user() return 0 or -EFAULT? > +static int > +ltq_wdt_release(struct inode *inode, struct file *file) > +{ > +#ifndef CONFIG_WATCHDOG_NOWAYOUT > + if (ltq_wdt_ok_to_close) > + ltq_wdt_disable(); > + else > +#endif > + printk(KERN_ERR "ltq_wdt: watchdog closed without warning\n"); Use pr_err() instead. > +static int > +ltq_wdt_probe(struct platform_device *pdev) > +{ > + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + struct clk *clk; > + int ret = 0; Empty line between the variables and code won't hurt... > + /* we do not need to enable the clock as it is always running */ > + clk = clk_get(&pdev->dev, "io"); clk_get() may fail... > + ret = misc_register(<q_wdt_miscdev); > + if (ret) > + return 0; Er, didn't you mean: if (!ret) return 0; > + return ret; 'ret' is always 0 here with your code. > +} > + > +static int > +ltq_wdt_remove(struct platform_device *dev) __exit? > +static int __init > +init_ltq_wdt(void) > +{ > + return platform_driver_register(<q_wdt_driver); Why not platfrom_driver_probe()? It's hardly a hotplug device... WBR, Sergei From ralf@linux-mips.org Wed Mar 2 16:00:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Mar 2011 16:00:30 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:42565 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491174Ab1CBPA1 (ORCPT ); Wed, 2 Mar 2011 16:00:27 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p22ETb39019651; Wed, 2 Mar 2011 15:29:37 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p22ETXlH019645; Wed, 2 Mar 2011 15:29:33 +0100 Date: Wed, 2 Mar 2011 15:29:33 +0100 From: Ralf Baechle To: Sergei Shtylyov Cc: John Crispin , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support Message-ID: <20110302142933.GA18221@linux-mips.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> <4D6E286D.9050100@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D6E286D.9050100@mvista.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29314 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Mar 02, 2011 at 02:22:21PM +0300, Sergei Shtylyov wrote: > >+ switch (cmd) { > >+ case WDIOC_GETSUPPORT: > >+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, > >+ sizeof(ident)) ? -EFAULT : 0; > > Doesn't copy_to_user() return 0 or -EFAULT? No and that's a common cause of bugs. copy_{from,to}_user returns the number of characters that could be be copied so the conversion to an error code is needed here. The function takes a void argument and there is no benefit from casting to the full struct watchdog_info __user * pointer type other than maybe clarity to the human reader. While nitpicking - there should be one space between include and < in #include . Ralf From blogic@openwrt.org Wed Mar 2 16:03:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Mar 2011 16:04:01 +0100 (CET) Received: from nbd.name ([46.4.11.11]:55522 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491174Ab1CBPD7 (ORCPT ); Wed, 2 Mar 2011 16:03:59 +0100 Message-ID: <4D6E5CA9.5090201@openwrt.org> Date: Wed, 02 Mar 2011 16:05:13 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: Ralf Baechle CC: Sergei Shtylyov , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> <4D6E286D.9050100@mvista.com> <20110302142933.GA18221@linux-mips.org> In-Reply-To: <20110302142933.GA18221@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29315 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Hi Ralf, > While nitpicking - there should be one space between include and < in > #include . > > where did you see that ? thanks, John From blogic@openwrt.org Wed Mar 2 16:42:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Mar 2011 16:42:53 +0100 (CET) Received: from nbd.name ([46.4.11.11]:60820 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491174Ab1CBPmu (ORCPT ); Wed, 2 Mar 2011 16:42:50 +0100 Message-ID: <4D6E65C8.4020500@openwrt.org> Date: Wed, 02 Mar 2011 16:44:08 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> <4D6E286D.9050100@mvista.com> In-Reply-To: <4D6E286D.9050100@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29316 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Hi Sergei, thanks for the comments, one question below >> + /* we do not need to enable the clock as it is always running */ >> + clk = clk_get(&pdev->dev, "io"); > > clk_get() may fail... > lantiq socs have 2 static clock that are always running. so i think it is safe to assume that this wont fail unless someone renames the clocks. alternatively i could add a if (!clk) BUG(); but i am not sure if it is required. thanks, John From ralf@linux-mips.org Wed Mar 2 17:27:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Mar 2011 17:27:49 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58567 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491180Ab1CBQ1q (ORCPT ); Wed, 2 Mar 2011 17:27:46 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p22GRWSx030766; Wed, 2 Mar 2011 17:27:32 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p22GRUWc030761; Wed, 2 Mar 2011 17:27:30 +0100 Date: Wed, 2 Mar 2011 17:27:30 +0100 From: Ralf Baechle To: John Crispin Cc: Sergei Shtylyov , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support Message-ID: <20110302162730.GA23666@linux-mips.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> <4D6E286D.9050100@mvista.com> <20110302142933.GA18221@linux-mips.org> <4D6E5CA9.5090201@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D6E5CA9.5090201@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29317 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Mar 02, 2011 at 04:05:13PM +0100, John Crispin wrote: > Hi Ralf, > > While nitpicking - there should be one space between include and < in > > #include . > > > > > where did you see that ? > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include But that only seems to have happened to the code quoted in Sergei's mail. Ralf From sshtylyov@mvista.com Wed Mar 2 18:36:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Mar 2011 18:36:33 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:44153 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491182Ab1CBRga (ORCPT ); Wed, 2 Mar 2011 18:36:30 +0100 Received: by bwz1 with SMTP id 1so394569bwz.36 for ; Wed, 02 Mar 2011 09:36:23 -0800 (PST) Received: by 10.204.61.10 with SMTP id r10mr251899bkh.195.1299087383496; Wed, 02 Mar 2011 09:36:23 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id x6sm138173bkv.0.2011.03.02.09.36.21 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 Mar 2011 09:36:22 -0800 (PST) Message-ID: <4D6E7FBC.6040805@mvista.com> Date: Wed, 02 Mar 2011 20:34:52 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Ralf Baechle CC: John Crispin , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> <4D6E286D.9050100@mvista.com> <20110302142933.GA18221@linux-mips.org> In-Reply-To: <20110302142933.GA18221@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29318 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Ralf Baechle wrote: >>> + switch (cmd) { >>> + case WDIOC_GETSUPPORT: >>> + ret = copy_to_user((struct watchdog_info __user *)arg, &ident, >>> + sizeof(ident)) ? -EFAULT : 0; >> Doesn't copy_to_user() return 0 or -EFAULT? > No and that's a common cause of bugs. copy_{from,to}_user returns the > number of characters that could be be copied so the conversion to an > error code is needed here. But then the code above would be wrong. Actually, it returns the number of bytes that could NOT be copied as I now see. > The function takes a void argument and there is no benefit from casting > to the full struct watchdog_info __user * pointer type other than maybe > clarity to the human reader. Indeed. > Ralf WBR, Sergei From sshtylyov@mvista.com Wed Mar 2 18:38:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Mar 2011 18:38:16 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:59206 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491180Ab1CBRiN (ORCPT ); Wed, 2 Mar 2011 18:38:13 +0100 Received: by bwz1 with SMTP id 1so396373bwz.36 for ; Wed, 02 Mar 2011 09:38:08 -0800 (PST) Received: by 10.204.45.86 with SMTP id d22mr311812bkf.8.1299087488075; Wed, 02 Mar 2011 09:38:08 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id z18sm135552bkf.8.2011.03.02.09.38.06 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 Mar 2011 09:38:07 -0800 (PST) Message-ID: <4D6E8025.2030702@mvista.com> Date: Wed, 02 Mar 2011 20:36:37 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Ralf Baechle CC: John Crispin , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> <4D6E286D.9050100@mvista.com> <20110302142933.GA18221@linux-mips.org> <4D6E5CA9.5090201@openwrt.org> <20110302162730.GA23666@linux-mips.org> In-Reply-To: <20110302162730.GA23666@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29319 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Ralf Baechle wrote: >> Hi Ralf, >>> While nitpicking - there should be one space between include and < in >>> #include . >> where did you see that ? >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include > But that only seems to have happened to the code quoted in Sergei's mail. Stupid Thunderbird is to be blamed here. :-) > Ralf WBR, Sergei From ukl@pengutronix.de Wed Mar 2 21:48:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Mar 2011 21:48:32 +0100 (CET) Received: from metis.ext.pengutronix.de ([92.198.50.35]:51966 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491203Ab1CBUs3 (ORCPT ); Wed, 2 Mar 2011 21:48:29 +0100 Received: from octopus.hi.pengutronix.de ([2001:6f8:1178:2:215:17ff:fe12:23b0]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1Pusxq-0005ki-Dp; Wed, 02 Mar 2011 21:48:06 +0100 Received: from ukl by octopus.hi.pengutronix.de with local (Exim 4.69) (envelope-from ) id 1Pusxn-0001HK-SF; Wed, 02 Mar 2011 21:48:03 +0100 Date: Wed, 2 Mar 2011 21:48:03 +0100 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= To: linux-arm-kernel@lists.infradead.org, Hans-Christian Egtvedt , uclinux-dist-devel@blackfin.uclinux.org, linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, Borislav Petkov , Mike Frysinger , Andrew Morton Cc: kernel@pengutronix.de Subject: about MISC_DEVICES not being enabled in many defconfigs Message-ID: <20110302204803.GI22310@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit User-Agent: Mutt/1.5.20 (2009-06-14) X-SA-Exim-Connect-IP: 2001:6f8:1178:2:215:17ff:fe12:23b0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-mips@linux-mips.org Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29320 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ukl@pengutronix.de Precedence: bulk X-list: linux-mips Hello, while working on an defconfig (arm/mx27) I noticed that just updating it[1] results in removing CONFIG_EEPROM_AT24=y. The reason is that since commit v2.6.36-5965-g5f2365d (misc devices: do not enable by default) MISC_DEVICES isn't enabled anymore by default. So all defconfigs that have CONFIG_SOME_SYMBOL=y (or =m) (with SOME_SYMBOL depending on MISC_DEVICES) but not CONFIG_MISC_DEVICES=y suffer from the same problem. As a defconfig that was reduced before 5f2365d obviously didn't have CONFIG_MISC_DEVICES=y many defconfigs have that problem. I did the following to (hopefully) find all affected defconfigs: $ git describe v2.6.38-rc7 $ git ls-files drivers/misc | grep Kconfig | xargs grep -h ^config | sed 's/config \(.*\)/CONFIG_\1=/' > miscsymbols $ git ls-files *defconfig | xargs grep -L CONFIG_MISC_DEVICES= | xargs grep -F -f miscsymbols arch/arm/configs/afeb9260_defconfig:CONFIG_ATMEL_SSC=y arch/arm/configs/afeb9260_defconfig:CONFIG_EEPROM_AT24=y arch/arm/configs/at572d940hfek_defconfig:CONFIG_ATMEL_TCLIB=y arch/arm/configs/at572d940hfek_defconfig:CONFIG_ATMEL_SSC=m arch/arm/configs/at572d940hfek_defconfig:CONFIG_SENSORS_TSL2550=m arch/arm/configs/at572d940hfek_defconfig:CONFIG_DS1682=m arch/arm/configs/at91cap9adk_defconfig:CONFIG_ATMEL_SSC=y arch/arm/configs/at91rm9200_defconfig:CONFIG_ATMEL_TCLIB=y arch/arm/configs/at91rm9200_defconfig:CONFIG_EEPROM_LEGACY=m arch/arm/configs/at91sam9260ek_defconfig:CONFIG_ATMEL_SSC=y arch/arm/configs/at91sam9261ek_defconfig:CONFIG_ATMEL_SSC=y arch/arm/configs/at91sam9263ek_defconfig:CONFIG_ATMEL_SSC=y arch/arm/configs/at91sam9g20ek_defconfig:CONFIG_ATMEL_SSC=y arch/arm/configs/at91sam9rlek_defconfig:CONFIG_ATMEL_SSC=y arch/arm/configs/da8xx_omapl_defconfig:CONFIG_EEPROM_AT24=y arch/arm/configs/davinci_all_defconfig:CONFIG_EEPROM_AT24=y arch/arm/configs/ep93xx_defconfig:CONFIG_EEPROM_LEGACY=y arch/arm/configs/ixp2000_defconfig:CONFIG_EEPROM_LEGACY=y arch/arm/configs/ixp23xx_defconfig:CONFIG_EEPROM_LEGACY=y arch/arm/configs/ixp4xx_defconfig:CONFIG_EEPROM_LEGACY=y arch/arm/configs/mini2440_defconfig:CONFIG_SENSORS_TSL2550=m arch/arm/configs/mx27_defconfig:CONFIG_EEPROM_AT24=y arch/arm/configs/mx3_defconfig:CONFIG_EEPROM_AT24=y arch/arm/configs/neocore926_defconfig:CONFIG_ATMEL_PWM=y arch/arm/configs/neocore926_defconfig:CONFIG_ATMEL_TCLIB=y arch/arm/configs/omap2plus_defconfig:CONFIG_EEPROM_LEGACY=y arch/arm/configs/pcontrol_g20_defconfig:CONFIG_ATMEL_TCLIB=y arch/arm/configs/pcontrol_g20_defconfig:CONFIG_EEPROM_AT24=m arch/arm/configs/pnx4008_defconfig:CONFIG_EEPROM_LEGACY=m arch/arm/configs/raumfeld_defconfig:CONFIG_ISL29003=y arch/arm/configs/raumfeld_defconfig:CONFIG_TI_DAC7512=y arch/arm/configs/realview-smp_defconfig:CONFIG_ARM_CHARLCD=y arch/arm/configs/realview_defconfig:CONFIG_ARM_CHARLCD=y arch/arm/configs/s3c2410_defconfig:CONFIG_EEPROM_AT25=m arch/arm/configs/s3c2410_defconfig:CONFIG_EEPROM_LEGACY=m arch/arm/configs/s3c2410_defconfig:CONFIG_EEPROM_93CX6=m arch/arm/configs/s3c6400_defconfig:CONFIG_EEPROM_AT24=y arch/arm/configs/s5pc100_defconfig:CONFIG_EEPROM_AT24=y arch/arm/configs/versatile_defconfig:CONFIG_EEPROM_LEGACY=m arch/arm/configs/zeus_defconfig:CONFIG_EEPROM_AT24=m arch/avr32/configs/atngw100_mrmt_defconfig:CONFIG_ATMEL_PWM=y arch/avr32/configs/favr-32_defconfig:CONFIG_ATMEL_PWM=m arch/avr32/configs/favr-32_defconfig:CONFIG_ATMEL_TCLIB=y arch/avr32/configs/favr-32_defconfig:CONFIG_ATMEL_SSC=m arch/avr32/configs/hammerhead_defconfig:CONFIG_ATMEL_TCLIB=y arch/avr32/configs/merisc_defconfig:CONFIG_ATMEL_PWM=y arch/avr32/configs/merisc_defconfig:CONFIG_ATMEL_SSC=y arch/avr32/configs/mimc200_defconfig:CONFIG_ATMEL_TCLIB=y arch/avr32/configs/mimc200_defconfig:CONFIG_EEPROM_AT24=y arch/avr32/configs/mimc200_defconfig:CONFIG_EEPROM_AT25=y arch/blackfin/configs/BlackStamp_defconfig:CONFIG_EEPROM_AT25=y arch/blackfin/configs/H8606_defconfig:CONFIG_EEPROM_AT25=y arch/blackfin/configs/SRV1_defconfig:CONFIG_EEPROM_AT25=m arch/ia64/configs/generic_defconfig:CONFIG_SGI_IOC4=y arch/ia64/configs/generic_defconfig:CONFIG_SGI_XP=m arch/ia64/configs/gensparse_defconfig:CONFIG_SGI_IOC4=y arch/mips/configs/bigsur_defconfig:CONFIG_SGI_IOC4=m arch/mips/configs/bigsur_defconfig:CONFIG_EEPROM_LEGACY=y arch/mips/configs/bigsur_defconfig:CONFIG_EEPROM_MAX6875=y arch/mips/configs/gpr_defconfig:CONFIG_TIFM_CORE=m arch/mips/configs/ip32_defconfig:CONFIG_SGI_IOC4=y arch/mips/configs/markeins_defconfig:CONFIG_SGI_IOC4=m arch/mips/configs/pnx8550-jbs_defconfig:CONFIG_SGI_IOC4=m arch/mips/configs/rm200_defconfig:CONFIG_SGI_IOC4=m arch/mips/configs/sb1250-swarm_defconfig:CONFIG_SGI_IOC4=m arch/mips/configs/wrppmc_defconfig:CONFIG_SGI_IOC4=m arch/mips/configs/yosemite_defconfig:CONFIG_SGI_IOC4=m arch/powerpc/configs/44x/warp_defconfig:CONFIG_EEPROM_AT24=y arch/powerpc/configs/52xx/motionpro_defconfig:CONFIG_EEPROM_LEGACY=y arch/powerpc/configs/86xx/gef_ppc9a_defconfig:CONFIG_DS1682=y arch/powerpc/configs/86xx/gef_sbc310_defconfig:CONFIG_DS1682=y arch/powerpc/configs/86xx/gef_sbc610_defconfig:CONFIG_DS1682=y arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig:CONFIG_EEPROM_LEGACY=y arch/powerpc/configs/e55xx_smp_defconfig:CONFIG_EEPROM_LEGACY=y arch/powerpc/configs/linkstation_defconfig:CONFIG_EEPROM_LEGACY=m arch/powerpc/configs/mpc512x_defconfig:CONFIG_EEPROM_AT24=y arch/powerpc/configs/mpc5200_defconfig:CONFIG_EEPROM_AT24=y arch/powerpc/configs/mpc85xx_defconfig:CONFIG_EEPROM_LEGACY=y arch/powerpc/configs/mpc85xx_smp_defconfig:CONFIG_EEPROM_LEGACY=y arch/powerpc/configs/mpc86xx_defconfig:CONFIG_EEPROM_LEGACY=y arch/powerpc/configs/pasemi_defconfig:CONFIG_EEPROM_LEGACY=y arch/powerpc/configs/ppc6xx_defconfig:CONFIG_ENCLOSURE_SERVICES=m arch/powerpc/configs/ppc6xx_defconfig:CONFIG_SENSORS_TSL2550=m arch/powerpc/configs/ppc6xx_defconfig:CONFIG_EEPROM_AT24=m arch/powerpc/configs/ppc6xx_defconfig:CONFIG_EEPROM_LEGACY=m arch/powerpc/configs/ppc6xx_defconfig:CONFIG_EEPROM_MAX6875=m arch/powerpc/configs/ppc6xx_defconfig:CONFIG_EEPROM_93CX6=m arch/sh/configs/se7206_defconfig:CONFIG_EEPROM_93CX6=y (For those wondering about the commands above: A line arch/$arch/configs/xyz_defconfig:CONFIG_SOME_DEVICE=y means here, that running make ARCH=$arch xyz_defconfig results in a config without SOME_DEVICE. I don't know if that bothers you, but if it does, you should add CONFIG_MISC_DEVICES=y to your defconfig. Just to let you know ... Best regards Uwe [1] make mx27_defconfig make savedefconfig mv defconfig arch/arm/configs/mx27_defconfig -- Pengutronix e.K. | Uwe Kleine-Knig | Industrial Linux Solutions | http://www.pengutronix.de/ | From jm@lentin.co.uk Thu Mar 3 00:54:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 00:54:30 +0100 (CET) Received: from chipmunk.wormnet.eu ([195.195.131.226]:34805 "EHLO chipmunk.wormnet.eu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491753Ab1CBXy2 (ORCPT ); Thu, 3 Mar 2011 00:54:28 +0100 Received: from [10.150.1.116] (lentinj.plus.com [80.229.158.163]) by chipmunk.wormnet.eu (Postfix) with ESMTPSA id 08B028262D for ; Wed, 2 Mar 2011 23:54:22 +0000 (GMT) Date: Wed, 2 Mar 2011 23:54:21 +0000 (GMT) From: Jamie Lentin X-X-Sender: lentinj@gonzo To: linux-mips@linux-mips.org Subject: BCM47xx: Serial port swapping Message-ID: User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; format=flowed; charset=US-ASCII X-Virus-Scanned: clamav-milter 0.96.5 at chipmunk X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29321 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jm@lentin.co.uk Precedence: bulk X-list: linux-mips Hi, I am running Debian on a Netgear WGT634U with a ~mainline 2.6.37 kernel. Upon upgrading from .32 I noticed this patch:- diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 87a3055..c95f90b 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -169,12 +169,28 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus, void __init plat_mem_setup(void) { int err; + char buf[100]; + struct ssb_mipscore *mcore; err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants); if (err) panic("Failed to initialize SSB bus (err %d)\n", err); + mcore = &ssb_bcm47xx.mipscore; + if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) { + if (strstr(buf, "console=ttyS1")) { + struct ssb_serial_port port; + + printk(KERN_DEBUG "Swapping serial ports!\n"); + /* swap serial ports */ + memcpy(&port, &mcore->serial_ports[0], sizeof(port)); + memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], + sizeof(port)); + memcpy(&mcore->serial_ports[1], &port, sizeof(port)); + } A WGT634U only has the header on the second serial port, this is where CFE outputs it's console by default, and where I have my serial cable attached. If I specify console=ttyS1, then the above kicks in and the serial port I am attached to becomes ttyS0 early in the boot process, and I loose console output. If I specify console=ttyS0, the above doesn't do anything so the kernel continues to use the unattached serial port. Either way I cannot get any console output without some hacking. Currently I have removed the block, specified "console=ttyS1" in the commandline, and this gives me working console all the way through boot. I'm happy to test/supply any further patches, solutions I can think of are:- * Remove it entirely: I think this code has it's origins in OpenWRT code that swapped ports so the userland didn't have to use ttyS1 for a bunch of devices, ttyS0 for another. It's certainly not required to get console output on my device, not tested any other variants of this platform. * Invert the strstr logic, so that the swap happens if I don't specify ttyS1 as my console. Then regardless of whether I use ttyS0 or ttyS1, I get a console. * Have a more explict "swap_serial_ports" kernel parameter Cheers, -- Jamie Lentin From blogic@openwrt.org Thu Mar 3 11:02:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:02:36 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57603 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491854Ab1CCKCc (ORCPT ); Thu, 3 Mar 2011 11:02:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 03/10] MIPS: lantiq: add PCI controller support. Date: Thu, 3 Mar 2011 11:03:39 +0100 Message-Id: <1299146626-17428-4-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29322 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds the driver that allows us to use the EBU as a PCI controller. In order for PCI to work the EBU is set to endianess swap all the data. In addition we need to make use of SWAP_IO_SPACE for device->host DMA to work. The clock of the PCI works in several modes (internal/external). If this is not configured correctly the SoC will hang. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- Changes in V2 * add handling for more than 1 pci device * add properly handling and registration of gpios * properly remap the memory regions .../mips/include/asm/mach-lantiq/lantiq_platform.h | 46 +++ arch/mips/pci/Makefile | 1 + arch/mips/pci/ops-lantiq.c | 119 ++++++++ arch/mips/pci/pci-lantiq.c | 303 ++++++++++++++++++++ arch/mips/pci/pci-lantiq.h | 18 ++ 5 files changed, 487 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_platform.h create mode 100644 arch/mips/pci/ops-lantiq.c create mode 100644 arch/mips/pci/pci-lantiq.c create mode 100644 arch/mips/pci/pci-lantiq.h diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h new file mode 100644 index 0000000..54e873c --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h @@ -0,0 +1,46 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LANTIQ_PLATFORM_H__ +#define _LANTIQ_PLATFORM_H__ + +#include + +/* struct used to pass info to the pci core */ +enum { + PCI_CLOCK_INT = 0, + PCI_CLOCK_EXT +}; + +#define PCI_EXIN0 0x0001 +#define PCI_EXIN1 0x0002 +#define PCI_EXIN2 0x0004 +#define PCI_EXIN3 0x0008 +#define PCI_EXIN4 0x0010 +#define PCI_EXIN5 0x0020 +#define PCI_EXIN_MAX 6 + +#define PCI_GNT1 0x0040 +#define PCI_GNT2 0x0080 +#define PCI_GNT3 0x0100 +#define PCI_GNT4 0x0200 + +#define PCI_REQ1 0x0400 +#define PCI_REQ2 0x0800 +#define PCI_REQ3 0x1000 +#define PCI_REQ4 0x2000 +#define PCI_REQ_SHIFT 10 +#define PCI_REQ_MASK 0xf + +struct ltq_pci_data { + int clock; + int gpio; + int irq[16]; +}; + +#endif diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c9209ca..4a5d1ae 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o +obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c new file mode 100644 index 0000000..ee28018 --- /dev/null +++ b/arch/mips/pci/ops-lantiq.c @@ -0,0 +1,119 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "pci-lantiq.h" + +#define LTQ_PCI_CFG_BUSNUM_SHF 16 +#define LTQ_PCI_CFG_DEVNUM_SHF 11 +#define LTQ_PCI_CFG_FUNNUM_SHF 8 + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +static int +ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int devfn, unsigned int where, u32 *data) +{ + unsigned long cfg_base; + unsigned long flags; + u32 temp; + + /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the + SoC itself */ + if ((bus->number != 0) || ((devfn & 0xf8) > 0x78) + || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68)) + return 1; + + spin_lock_irqsave(&ebu_lock, flags); + + cfg_base = (unsigned long) ltq_pci_mapped_cfg; + cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn << + LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3); + + /* Perform access */ + if (access_type == PCI_ACCESS_WRITE) { + ltq_w32(swab32(*data), ((u32 *)cfg_base)); + } else { + *data = ltq_r32(((u32 *)(cfg_base))); + *data = swab32(*data); + } + wmb(); + + /* clean possible Master abort */ + cfg_base = (unsigned long) ltq_pci_mapped_cfg; + cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; + temp = ltq_r32(((u32 *)(cfg_base))); + temp = swab32(temp); + cfg_base = (unsigned long) ltq_pci_mapped_cfg; + cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; + ltq_w32(temp, ((u32 *)cfg_base)); + + spin_unlock_irqrestore(&ebu_lock, flags); + + if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ)) + return 1; + + return 0; +} + +int +ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data = 0; + + if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +int +ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + + if (size == 4) { + data = val; + } else { + if (ltq_pci_config_access(PCI_ACCESS_READ, bus, + devfn, where, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + } + + if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c new file mode 100644 index 0000000..1dde03f --- /dev/null +++ b/arch/mips/pci/pci-lantiq.c @@ -0,0 +1,303 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "pci-lantiq.h" + +#define LTQ_PCI_CFG_BASE 0x17000000 +#define LTQ_PCI_CFG_SIZE 0x00008000 +#define LTQ_PCI_MEM_BASE 0x18000000 +#define LTQ_PCI_MEM_SIZE 0x02000000 +#define LTQ_PCI_IO_BASE 0x1AE00000 +#define LTQ_PCI_IO_SIZE 0x00200000 + +#define PCI_CR_FCI_ADDR_MAP0 0x00C0 +#define PCI_CR_FCI_ADDR_MAP1 0x00C4 +#define PCI_CR_FCI_ADDR_MAP2 0x00C8 +#define PCI_CR_FCI_ADDR_MAP3 0x00CC +#define PCI_CR_FCI_ADDR_MAP4 0x00D0 +#define PCI_CR_FCI_ADDR_MAP5 0x00D4 +#define PCI_CR_FCI_ADDR_MAP6 0x00D8 +#define PCI_CR_FCI_ADDR_MAP7 0x00DC +#define PCI_CR_CLK_CTRL 0x0000 +#define PCI_CR_PCI_MOD 0x0030 +#define PCI_CR_PC_ARB 0x0080 +#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4 +#define PCI_CR_BAR11MASK 0x0044 +#define PCI_CR_BAR12MASK 0x0048 +#define PCI_CR_BAR13MASK 0x004C +#define PCI_CS_BASE_ADDR1 0x0010 +#define PCI_CR_PCI_ADDR_MAP11 0x0064 +#define PCI_CR_FCI_BURST_LENGTH 0x00E8 +#define PCI_CR_PCI_EOI 0x002C +#define PCI_CS_STS_CMD 0x0004 + +#define PCI_MASTER0_REQ_MASK_2BITS 8 +#define PCI_MASTER1_REQ_MASK_2BITS 10 +#define PCI_MASTER2_REQ_MASK_2BITS 12 +#define INTERNAL_ARB_ENABLE_BIT 0 + +#define LTQ_CGU_IFCCR 0x0018 +#define LTQ_CGU_PCICR 0x0034 + +#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y)) +#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x)) + +#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) +#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) + +struct ltq_pci_gpio_map { + int pin; + int alt0; + int alt1; + int dir; + char *name; +}; + +/* the pci core can make use of the following gpios */ +static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { + { 0, 1, 0, 0, "pci-exin0" }, + { 1, 1, 0, 0, "pci-exin1" }, + { 2, 1, 0, 0, "pci-exin2" }, + { 39, 1, 0, 0, "pci-exin3" }, + { 10, 1, 0, 0, "pci-exin4" }, + { 9, 1, 0, 0, "pci-exin5" }, + { 30, 1, 0, 1, "pci-gnt1" }, + { 23, 1, 0, 1, "pci-gnt2" }, + { 19, 1, 0, 1, "pci-gnt3" }, + { 38, 1, 0, 1, "pci-gnt4" }, + { 29, 1, 0, 0, "pci-req1" }, + { 31, 1, 0, 0, "pci-req2" }, + { 3, 1, 0, 0, "pci-req3" }, + { 37, 1, 0, 0, "pci-req4" }, +}; + +__iomem void *ltq_pci_mapped_cfg; +static __iomem void *ltq_pci_membase; + +int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; + +/* Since the PCI REQ pins can be reused for other functionality, make it + possible to exclude those from interpretation by the PCI controller */ +static int ltq_pci_req_mask = 0xf; + +static int *ltq_pci_irq_map; + +struct pci_ops ltq_pci_ops = { + .read = ltq_pci_read_config_dword, + .write = ltq_pci_write_config_dword +}; + +static struct resource pci_io_resource = { + .name = "pci io space", + .start = LTQ_PCI_IO_BASE, + .end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + .name = "pci memory space", + .start = LTQ_PCI_MEM_BASE, + .end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM +}; + +static struct pci_controller ltq_pci_controller = { + .pci_ops = <q_pci_ops, + .mem_resource = &pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &pci_io_resource, + .io_offset = 0x00000000UL, +}; + +int +pcibios_plat_dev_init(struct pci_dev *dev) +{ + if (ltqpci_plat_dev_init) + return ltqpci_plat_dev_init(dev); + + return 0; +} + +static u32 +ltq_calc_bar11mask(void) +{ + u32 mem, bar11mask; + + /* BAR11MASK value depends on available memory on system. */ + mem = num_physpages * PAGE_SIZE; + bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; + + return bar11mask; +} + +static void +ltq_pci_setup_gpio(int gpio) +{ + int i; + for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) + { + if(gpio & (1 << i)) + { + ltq_gpio_request(ltq_pci_gpio_map[i].pin, + ltq_pci_gpio_map[i].alt0, + ltq_pci_gpio_map[i].alt1, + ltq_pci_gpio_map[i].dir, + ltq_pci_gpio_map[i].name); + } + } + ltq_gpio_request(21, 0, 0, 1, "pci-reset"); + ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; +} + +static int __devinit +ltq_pci_startup(struct ltq_pci_data *conf) +{ + u32 temp_buffer; + + /* set clock to 33Mhz */ + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); + + /* external or internal clock ? */ + if (conf->clock) { + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16), + LTQ_CGU_IFCCR); + ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR); + } else { + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16), + LTQ_CGU_IFCCR); + ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR); + } + + /* setup pci clock and gpis used by pci */ + ltq_pci_setup_gpio(conf->gpio); + + /* enable auto-switching between PCI and EBU */ + ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); + + /* busy, i.e. configuration is not done, PCI access has to be retried */ + ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD); + wmb(); + /* BUS Master/IO/MEM access */ + ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD); + + /* enable external 2 PCI masters */ + temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB); + temp_buffer &= (~(ltq_pci_req_mask << 16)); + /* enable internal arbiter */ + temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); + /* enable internal PCI master reqest */ + temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); + + /* enable EBU request */ + temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS)); + + /* enable all external masters request */ + temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); + ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB); + wmb(); + + /* setup BAR memory regions */ + ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0); + ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1); + ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2); + ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3); + ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4); + ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5); + ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6); + ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7); + ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg); + ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK); + ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11); + ltq_pci_w32(0, PCI_CS_BASE_ADDR1); + /* both TX and RX endian swap are enabled */ + ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI); + wmb(); + ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000, + PCI_CR_BAR12MASK); + ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000, + PCI_CR_BAR13MASK); + /*use 8 dw burst length */ + ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH); + ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD); + wmb(); + + /* setup irq line */ + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON); + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); + + /* toggle reset pin */ + __gpio_set_value(21, 0); + wmb(); + mdelay(1); + __gpio_set_value(21, 1); + return 0; +} + +int __init +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if(ltq_pci_irq_map[slot]) + return ltq_pci_irq_map[slot]; + printk("lq_pci: trying to map irq for unknown slot %d\n", slot); + return 0; +} + +static int __devinit +ltq_pci_probe(struct platform_device *pdev) +{ + struct ltq_pci_data *ltq_pci_data = + (struct ltq_pci_data *) pdev->dev.platform_data; + pci_probe_only = 0; + ltq_pci_irq_map = ltq_pci_data->irq; + ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); + ltq_pci_mapped_cfg = + ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); + ltq_pci_controller.io_map_base = + (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); + ltq_pci_startup(ltq_pci_data); + register_pci_controller(<q_pci_controller); + return 0; +} + +static struct platform_driver +ltq_pci_driver = { + .probe = ltq_pci_probe, + .driver = { + .name = "ltq_pci", + .owner = THIS_MODULE, + }, +}; + +int __init +pcibios_init(void) +{ + int ret = platform_driver_register(<q_pci_driver); + if (ret) + printk(KERN_INFO "ltq_pci: Error registering platfom driver!"); + return ret; +} + +arch_initcall(pcibios_init); diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h new file mode 100644 index 0000000..66bf6cd --- /dev/null +++ b/arch/mips/pci/pci-lantiq.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_PCI_H__ +#define _LTQ_PCI_H__ + +extern __iomem void *ltq_pci_mapped_cfg; +extern int ltq_pci_read_config_dword(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *val); +extern int ltq_pci_write_config_dword(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 val); + +#endif -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:02:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:03:05 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57598 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1CCKCc (ORCPT ); Thu, 3 Mar 2011 11:02:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 02/10] MIPS: lantiq: add SoC specific code for XWAY family Date: Thu, 3 Mar 2011 11:03:38 +0100 Message-Id: <1299146626-17428-3-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29323 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Add support for the Lantiq XWAY family of Mips24KEc SoCs. * Danube (PSB50702) * Twinpass (PSB4000) * AR9 (PSB50802) * Amazon SE (PSB5061) The Amazon SE is a lightweight SoC and has no PCI as well as a different clock. We split the code out into seperate files to handle this. The GPIO pins on the SoCs are multi function and there are several bits we can use to configure the pins. To be as compatible as possible to GPIOLIB we add a function int lq_gpio_request(unsigned int pin, unsigned int alt0, unsigned int alt1, unsigned int dir, const char *name); which lets you configure the 2 "alternate function" bits. This way drivers like PCI can make use of GPIOLIB without a cubersome wrapper. The pll code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was taken from a 2.4.20 source tree and was never really changed by me since then. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- Changes in V2 * properly ioremap all register regions and provide accessor macros (pmu,ebu,cgu) * add handling for EXIN irq sources * small cleanups Changes in V3 * whitespace * change __iomem void to void __iomem * multiline comments * use pr_* macros instead of printk arch/mips/Kconfig | 1 + arch/mips/include/asm/mach-lantiq/xway/irq.h | 18 ++ .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 62 ++++++ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 145 ++++++++++++ arch/mips/lantiq/Kconfig | 21 ++ arch/mips/lantiq/Makefile | 2 + arch/mips/lantiq/Platform | 1 + arch/mips/lantiq/xway/Makefile | 4 + arch/mips/lantiq/xway/clk-ase.c | 52 +++++ arch/mips/lantiq/xway/clk-xway.c | 232 ++++++++++++++++++++ arch/mips/lantiq/xway/ebu.c | 36 +++ arch/mips/lantiq/xway/gpio.c | 203 +++++++++++++++++ arch/mips/lantiq/xway/pmu.c | 57 +++++ arch/mips/lantiq/xway/prom-ase.c | 40 ++++ arch/mips/lantiq/xway/prom-xway.c | 55 +++++ arch/mips/lantiq/xway/reset.c | 67 ++++++ 16 files changed, 996 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/xway/irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h create mode 100644 arch/mips/lantiq/Kconfig create mode 100644 arch/mips/lantiq/xway/Makefile create mode 100644 arch/mips/lantiq/xway/clk-ase.c create mode 100644 arch/mips/lantiq/xway/clk-xway.c create mode 100644 arch/mips/lantiq/xway/ebu.c create mode 100644 arch/mips/lantiq/xway/gpio.c create mode 100644 arch/mips/lantiq/xway/pmu.c create mode 100644 arch/mips/lantiq/xway/prom-ase.c create mode 100644 arch/mips/lantiq/xway/prom-xway.c create mode 100644 arch/mips/lantiq/xway/reset.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f975932..756e67a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -758,6 +758,7 @@ source "arch/mips/ath79/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" +source "arch/mips/lantiq/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/powertv/Kconfig" diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h new file mode 100644 index 0000000..a1471d2 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef __LANTIQ_IRQ_H +#define __LANTIQ_IRQ_H + +#include + +#define NR_IRQS 256 + +#include_next + +#endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h new file mode 100644 index 0000000..5c81c98 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -0,0 +1,62 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LANTIQ_XWAY_IRQ_H__ +#define _LANTIQ_XWAY_IRQ_H__ + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) +#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) +#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) + +#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15) +#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14) +#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16) + +#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) +#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23) + +#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) +#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22) +#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) + +#define MIPS_CPU_TIMER_IRQ 7 + +#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) +#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) +#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) +#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) +#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) +#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) +#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) +#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) +#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) +#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) +#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) +#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) +#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) +#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) +#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) +#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) +#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) +#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) +#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) +#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) + +#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) + +#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) + +#endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h new file mode 100644 index 0000000..f410948 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -0,0 +1,145 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifdef CONFIG_SOC_TYPE_XWAY + +#ifndef _LTQ_XWAY_H__ +#define _LTQ_XWAY_H__ + +#include + +/* Chip IDs */ +#define SOC_ID_DANUBE1 0x129 +#define SOC_ID_DANUBE2 0x12B +#define SOC_ID_TWINPASS 0x12D +#define SOC_ID_AMAZON_SE 0x152 +#define SOC_ID_ARX188 0x16C +#define SOC_ID_ARX168 0x16D +#define SOC_ID_ARX182 0x16F + +/* SoC Types */ +#define SOC_TYPE_DANUBE 0x01 +#define SOC_TYPE_TWINPASS 0x02 +#define SOC_TYPE_AR9 0x03 +#define SOC_TYPE_VR9 0x04 +#define SOC_TYPE_AMAZON_SE 0x05 + +/* ASC0/1 - serial port */ +#define LTQ_ASC0_BASE_ADDR 0x1E100400 +#define LTQ_ASC1_BASE_ADDR 0x1E100C00 +#define LTQ_ASC_SIZE 0x400 + +/* RCU - reset control unit */ +#define LTQ_RCU_BASE_ADDR 0x1F203000 +#define LTQ_RCU_SIZE 0x1000 + +/* GPTU - general purpose timer unit */ +#define LTQ_GPTU_BASE_ADDR 0x18000300 + +/* EBU - external bus unit */ +#define LTQ_EBU_GPIO_START 0x14000000 +#define LTQ_EBU_GPIO_SIZE 0x1000 + +#define LTQ_EBU_BASE_ADDR 0x1E105300 +#define LTQ_EBU_SIZE 0x100 + +#define LTQ_EBU_BUSCON0 0x0060 +#define LTQ_EBU_PCC_CON 0x0090 +#define LTQ_EBU_PCC_IEN 0x00A4 +#define LTQ_EBU_PCC_ISTAT 0x00A0 +#define LTQ_EBU_BUSCON1 0x0064 +#define LTQ_EBU_ADDRSEL1 0x0024 +#define EBU_WRDIS 0x80000000 + +/* CGU - clock generation unit */ +#define LTQ_CGU_BASE_ADDR 0x1F103000 +#define LTQ_CGU_SIZE 0x1000 + +/* ICU - interrupt control unit */ +#define LTQ_ICU_BASE_ADDR 0x1F880200 +#define LTQ_ICU_SIZE 0x100 + +/* EIU - external interrupt unit */ +#define LTQ_EIU_BASE_ADDR 0x1F101000 +#define LTQ_EIU_SIZE 0x1000 + +/* PMU - power management unit */ +#define LTQ_PMU_BASE_ADDR 0x1F102000 +#define LTQ_PMU_SIZE 0x1000 + +#define PMU_DMA 0x0020 +#define PMU_USB 0x8041 +#define PMU_LED 0x0800 +#define PMU_GPT 0x1000 +#define PMU_PPE 0x2000 +#define PMU_FPI 0x4000 +#define PMU_SWITCH 0x10000000 + +/* ETOP - ethernet */ +#define LTQ_PPE32_BASE_ADDR 0xBE180000 +#define LTQ_PPE32_SIZE 0x40000 + +/* DMA */ +#define LTQ_DMA_BASE_ADDR 0xBE104100 + +/* PCI */ +#define PCI_CR_BASE_ADDR 0x1E105400 +#define PCI_CR_SIZE 0x400 + +/* WDT */ +#define LTQ_WDT_BASE_ADDR 0x1F880000 +#define LTQ_WDT_SIZE 0x400 + +/* STP - serial to parallel conversion unit */ +#define LTQ_STP_BASE_ADDR 0x1E100BB0 +#define LTQ_STP_SIZE 0x40 + +/* GPIO */ +#define LTQ_GPIO0_BASE_ADDR 0x1E100B10 +#define LTQ_GPIO1_BASE_ADDR 0x1E100B40 +#define LTQ_GPIO2_BASE_ADDR 0x1E100B70 +#define LTQ_GPIO_SIZE 0x30 + +/* SSC */ +#define LTQ_SSC_BASE_ADDR 0x1e100800 +#define LTQ_SSC_SIZE 0x100 + +/* MEI - dsl core */ +#define LTQ_MEI_BASE_ADDR 0x1E116000 + +/* DEU - data encryption unit */ +#define LTQ_DEU_BASE_ADDR 0x1E103100 + +/* MPS - multi processor unit (voice) */ +#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) +#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) + +/* request a non-gpio and set the PIO config */ +extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, + unsigned int alt1, unsigned int dir, const char *name); +extern int ltq_gpio_setconfig(unsigned int pin, + unsigned int reg, unsigned int val); + +extern void ltq_pmu_enable(unsigned int module); +extern void ltq_pmu_disable(unsigned int module); + +static inline int +ltq_is_ar9(void) +{ + return (ltq_get_soc_type() == SOC_TYPE_AR9); +} + +static inline int +ltq_is_vr9(void) +{ + return (ltq_get_soc_type() == SOC_TYPE_VR9); +} + +#endif + +#endif diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig new file mode 100644 index 0000000..2780461 --- /dev/null +++ b/arch/mips/lantiq/Kconfig @@ -0,0 +1,21 @@ +if LANTIQ + +config SOC_TYPE_XWAY + bool + default n + +choice + prompt "SoC Type" + default SOC_XWAY + +config SOC_AMAZON_SE + bool "Amazon SE" + select SOC_TYPE_XWAY + +config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HW_HAS_PCI +endchoice + +endif diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index 6a30de6..a268391 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -7,3 +7,5 @@ obj-y := irq.o setup.o clk.o prom.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform index eef587f..f3dff05 100644 --- a/arch/mips/lantiq/Platform +++ b/arch/mips/lantiq/Platform @@ -5,3 +5,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/ cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq load-$(CONFIG_LANTIQ) = 0xffffffff80002000 +cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile new file mode 100644 index 0000000..9c85ff9 --- /dev/null +++ b/arch/mips/lantiq/xway/Makefile @@ -0,0 +1,4 @@ +obj-y := pmu.o ebu.o reset.o gpio.o + +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c new file mode 100644 index 0000000..5444917 --- /dev/null +++ b/arch/mips/lantiq/xway/clk-ase.c @@ -0,0 +1,52 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* cgu registers */ +#define LTQ_CGU_SYS 0x0010 + +unsigned int +ltq_get_io_region_clock(void) +{ + return CLOCK_133M; +} +EXPORT_SYMBOL(ltq_get_io_region_clock); + +unsigned int +ltq_get_fpi_bus_clock(int fpi) +{ + return CLOCK_133M; +} +EXPORT_SYMBOL(ltq_get_fpi_bus_clock); + +unsigned int +ltq_get_cpu_hz(void) +{ + if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) + return CLOCK_266M; + else + return CLOCK_133M; +} +EXPORT_SYMBOL(ltq_get_cpu_hz); + +unsigned int +ltq_get_fpi_hz(void) +{ + return CLOCK_133M; +} +EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c new file mode 100644 index 0000000..89246be --- /dev/null +++ b/arch/mips/lantiq/xway/clk-xway.c @@ -0,0 +1,232 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +static unsigned int ltq_ram_clocks[] = { + CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; +#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] + +#define BASIC_FREQUENCY_1 35328000 +#define BASIC_FREQUENCY_2 36000000 +#define BASIS_REQUENCY_USB 12000000 + +#define GET_BITS(x, msb, lsb) \ + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) + +#define LTQ_CGU_PLL0_CFG 0x0004 +#define LTQ_CGU_PLL1_CFG 0x0008 +#define LTQ_CGU_PLL2_CFG 0x000C +#define LTQ_CGU_SYS 0x0010 +#define LTQ_CGU_UPDATE 0x0014 +#define LTQ_CGU_IF_CLK 0x0018 +#define LTQ_CGU_OSC_CON 0x001C +#define LTQ_CGU_SMD 0x0020 +#define LTQ_CGU_CT1SR 0x0028 +#define LTQ_CGU_CT2SR 0x002C +#define LTQ_CGU_PCMCR 0x0030 +#define LTQ_CGU_PCI_CR 0x0034 +#define LTQ_CGU_PD_PC 0x0038 +#define LTQ_CGU_FMR 0x003C + +#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) +#define CGU_PLL0_BYPASS \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) +#define CGU_PLL0_CFG_DSMSEL \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) +#define CGU_PLL0_CFG_FRAC_EN \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) +#define CGU_PLL1_SRC \ + (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) +#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) +#define CGU_SYS_FPI_SEL (1 << 6) +#define CGU_SYS_DDR_SEL 0x3 +#define CGU_PLL0_SRC (1 << 29) + +#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) +#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) +#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) +#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) + +static unsigned int ltq_get_pll0_fdiv(void); + +static inline unsigned int +get_input_clock(int pll) +{ + switch (pll) { + case 0: + if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 1: + if (CGU_PLL1_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 2: + switch (CGU_PLL2_SRC) { + case 0: + return ltq_get_pll0_fdiv(); + case 1: + return CGU_PLL2_PHASE_DIVIDER_ENABLE ? + BASIC_FREQUENCY_1 : + BASIC_FREQUENCY_2; + case 2: + return BASIS_REQUENCY_USB; + } + default: + return 0; + } +} + +static inline unsigned int +cal_dsm(int pll, unsigned int num, unsigned int den) +{ + u64 res, clock = get_input_clock(pll); + + res = num * clock; + do_div(res, den); + return res; +} + +static inline unsigned int +mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K) +{ + unsigned int num = ((N + 1) << 10) + K; + unsigned int den = (M + 1) << 10; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int +ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K) +{ + unsigned int num = ((N + 1) << 11) + K + 512; + unsigned int den = (M + 1) << 11; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int +ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K) +{ + unsigned int num = K >= 512 ? + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; + unsigned int den = (M + 1) << 12; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int +dsm(int pll, unsigned int M, unsigned int N, unsigned int K, + unsigned int dsmsel, unsigned int phase_div_en) +{ + if (!dsmsel) + return mash_dsm(pll, M, N, K); + else if (!phase_div_en) + return mash_dsm(pll, M, N, K); + else + return ssff_dsm_2(pll, M, N, K); +} + +static inline unsigned int +ltq_get_pll0_fosc(void) +{ + if (CGU_PLL0_BYPASS) + return get_input_clock(0); + else + return !CGU_PLL0_CFG_FRAC_EN + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, + CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE) + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, + CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE); +} + +static unsigned int +ltq_get_pll0_fdiv(void) +{ + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; + + return (ltq_get_pll0_fosc() + (div >> 1)) / div; +} + +unsigned int +ltq_get_io_region_clock(void) +{ + unsigned int ret = ltq_get_pll0_fosc(); + + switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { + default: + case 0: + return (ret + 1) / 2; + case 1: + return (ret * 2 + 2) / 5; + case 2: + return (ret + 1) / 3; + case 3: + return (ret + 2) / 4; + } +} +EXPORT_SYMBOL(ltq_get_io_region_clock); + +unsigned int +ltq_get_fpi_bus_clock(int fpi) +{ + unsigned int ret = ltq_get_io_region_clock(); + + if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) + ret >>= 1; + return ret; +} +EXPORT_SYMBOL(ltq_get_fpi_bus_clock); + +unsigned int +ltq_get_cpu_hz(void) +{ + switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { + case 0: + return CLOCK_333M; + case 4: + return DDR_HZ; + case 8: + return DDR_HZ << 1; + default: + return DDR_HZ >> 1; + } +} +EXPORT_SYMBOL(ltq_get_cpu_hz); + +unsigned int +ltq_get_fpi_hz(void) +{ + unsigned int ddr_clock = DDR_HZ; + + if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) + return ddr_clock >> 1; + return ddr_clock; +} +EXPORT_SYMBOL(ltq_get_fpi_hz); diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c new file mode 100644 index 0000000..9d52c45 --- /dev/null +++ b/arch/mips/lantiq/xway/ebu.c @@ -0,0 +1,36 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * EBU - the external bus unit attaches PCI, NOR and NAND + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include + +#include + +/* all access to the ebu must be locked */ +DEFINE_SPINLOCK(ebu_lock); +EXPORT_SYMBOL_GPL(ebu_lock); + +/* remapped base addr of the clock unit and external bus unit */ +void __iomem *ltq_ebu_membase; + +static int __init +lantiq_ebu_init(void) +{ + /* remap ebu register range */ + ltq_ebu_membase = ioremap_nocache(LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + if (!ltq_ebu_membase) { + printk(KERN_ERR "Failed to remap ebu memory\n"); + unreachable(); + } + return 0; +} + +postcore_initcall(lantiq_ebu_init); diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c new file mode 100644 index 0000000..f9ff776 --- /dev/null +++ b/arch/mips/lantiq/xway/gpio.c @@ -0,0 +1,203 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define LTQ_GPIO_OUT 0x00 +#define LTQ_GPIO_IN 0x04 +#define LTQ_GPIO_DIR 0x08 +#define LTQ_GPIO_ALTSEL0 0x0C +#define LTQ_GPIO_ALTSEL1 0x10 +#define LTQ_GPIO_OD 0x14 + +#define PINS_PER_PORT 16 +#define MAX_PORTS 3 + +#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) +#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) +#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r) + +struct ltq_gpio { + void __iomem *membase; + struct gpio_chip chip; +}; + +static struct ltq_gpio ltq_gpio_port[MAX_PORTS]; + +int +gpio_to_irq(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int +irq_to_gpio(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); + +int +ltq_gpio_request(unsigned int pin, unsigned int alt0, + unsigned int alt1, unsigned int dir, const char *name) +{ + int id = 0; + + if (pin >= (MAX_PORTS * PINS_PER_PORT)) + return -EINVAL; + if (gpio_request(pin, name)) { + pr_err("failed to setup lantiq gpio: %s\n", name); + return -EBUSY; + } + if (dir) + gpio_direction_output(pin, 1); + else + gpio_direction_input(pin); + while (pin >= PINS_PER_PORT) { + pin -= PINS_PER_PORT; + id++; + } + if (alt0) + ltq_gpio_setbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); + else + ltq_gpio_clearbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); + if (alt1) + ltq_gpio_setbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL1, pin); + else + ltq_gpio_clearbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL1, pin); + return 0; +} +EXPORT_SYMBOL(ltq_gpio_request); + +static void +ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + if (value) + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); + else + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset); +} + +static int +ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset); +} + +static int +ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + return 0; +} + +static int +ltq_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + ltq_gpio_set(chip, offset, value); + return 0; +} + +static int +ltq_gpio_req(struct gpio_chip *chip, unsigned offset) +{ + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); + return 0; +} + +static int +ltq_gpio_probe(struct platform_device *pdev) +{ + struct resource *res; + + if (pdev->id >= MAX_PORTS) { + dev_err(&pdev->dev, "invalid gpio port %d\n", + pdev->id); + return -EINVAL; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", + pdev->id); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, + "failed to request memory for gpio port %d\n", + pdev->id); + return -EBUSY; + } + ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_gpio_port[pdev->id].membase) { + dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n", + pdev->id); + return -ENOMEM; + } + ltq_gpio_port[pdev->id].chip.label = "ltq_gpio"; + ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input; + ltq_gpio_port[pdev->id].chip.direction_output = + ltq_gpio_direction_output; + ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get; + ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; + ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; + ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; + ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; + platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); + return gpiochip_add(<q_gpio_port[pdev->id].chip); +} + +static struct platform_driver +ltq_gpio_driver = { + .probe = ltq_gpio_probe, + .driver = { + .name = "ltq_gpio", + .owner = THIS_MODULE, + }, +}; + +int __init +ltq_gpio_init(void) +{ + int ret = platform_driver_register(<q_gpio_driver); + + if (ret) + pr_info("ltq_gpio : Error registering platfom driver!"); + return ret; +} + +postcore_initcall(ltq_gpio_init); diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c new file mode 100644 index 0000000..8ed6d09 --- /dev/null +++ b/arch/mips/lantiq/xway/pmu.c @@ -0,0 +1,57 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include + +#include + +/* PMU - the power management unit allows us to turn part of the core + * on and off + */ + +/* the enable / disable register */ +#define LTQ_PMU_PWDCR 0x1C +#define LTQ_PMU_PWDSR 0x20 + +#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) +#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) + +static void __iomem *ltq_pmu_membase; + +void +ltq_pmu_enable(unsigned int module) +{ + int err = 1000000; + + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); + do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); + + if (!err) + panic("activating PMU module failed!\n"); +} + +void +ltq_pmu_disable(unsigned int module) +{ + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); +} + +int __init +ltq_pmu_init(void) +{ + ltq_pmu_membase = ioremap_nocache(LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); + if (!ltq_pmu_membase) { + pr_err("Failed to remap pmu memory\n"); + unreachable(); + } + return 0; +} + +core_initcall(ltq_pmu_init); diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c new file mode 100644 index 0000000..a7faf77 --- /dev/null +++ b/arch/mips/lantiq/xway/prom-ase.c @@ -0,0 +1,40 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "../prom.h" + +#define SOC_AMAZON_SE "Amazon_SE" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + switch (i->partnum) { + case SOC_ID_AMAZON_SE: + i->name = SOC_AMAZON_SE; + i->type = SOC_TYPE_AMAZON_SE; + break; + + default: + unreachable(); + break; + } +} diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c new file mode 100644 index 0000000..e7270e5 --- /dev/null +++ b/arch/mips/lantiq/xway/prom-xway.c @@ -0,0 +1,55 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "../prom.h" + +#define SOC_DANUBE "Danube" +#define SOC_TWINPASS "Twinpass" +#define SOC_AR9 "AR9" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + switch (i->partnum) { + case SOC_ID_DANUBE1: + case SOC_ID_DANUBE2: + i->name = SOC_DANUBE; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_TWINPASS: + i->name = SOC_TWINPASS; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_ARX188: + case SOC_ID_ARX168: + case SOC_ID_ARX182: + i->name = SOC_AR9; + i->type = SOC_TYPE_AR9; + break; + + default: + unreachable(); + break; + } +} diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c new file mode 100644 index 0000000..3ed78b8 --- /dev/null +++ b/arch/mips/lantiq/xway/reset.c @@ -0,0 +1,67 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) +#define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) + +/* register definitions */ +#define LTQ_RCU_RST 0x0010 +#define LTQ_RCU_RST_ALL 0x40000000 + +/* remapped base addr of the reset control unit */ +static void __iomem *ltq_rcu_membase; + +static void +ltq_machine_restart(char *command) +{ + pr_notice("System restart\n"); + local_irq_disable(); + ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST); + unreachable(); +} + +static void +ltq_machine_halt(void) +{ + pr_notice("System halted.\n"); + local_irq_disable(); + unreachable(); +} + +static void +ltq_machine_power_off(void) +{ + pr_notice("Please turn off the power now.\n"); + local_irq_disable(); + unreachable(); +} + +static int __init +mips_reboot_setup(void) +{ + /* remap rcu register range */ + ltq_rcu_membase = ioremap_nocache(LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE); + if (!ltq_rcu_membase) { + pr_err("Failed to remap rcu memory\n"); + unreachable(); + } + + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; + return 0; +} + +arch_initcall(mips_reboot_setup); -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:03:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:03:30 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57610 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491864Ab1CCKCc (ORCPT ); Thu, 3 Mar 2011 11:02:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 00/10] MIPS: add initial support for the Lantiq SoCs Date: Thu, 3 Mar 2011 11:03:36 +0100 Message-Id: <1299146626-17428-1-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29324 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This series will add support for the Lantiq/XWAY family of SoCs. you can find the public gitweb at : http://nbd.name/gitweb.cgi?p=lantiq.git;a=summary and the tree at : git@nbd.name:lantiq Cc: Ralph Hempel Cc: linux-mips@linux-mips.org John Crispin (10): MIPS: lantiq: add initial support for Lantiq SoCs MIPS: lantiq: add SoC specific code for XWAY family MIPS: lantiq: add PCI controller support. MIPS: lantiq: add serial port support MIPS: lantiq: add watchdog support MIPS: lantiq: add NOR flash support MIPS: lantiq: add platform device support MIPS: lantiq: add mips_machine support MIPS: lantiq: add machtypes for lantiq eval kits MIPS: lantiq: add more gpio drivers arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 19 + arch/mips/include/asm/mach-lantiq/lantiq.h | 58 ++ .../mips/include/asm/mach-lantiq/lantiq_platform.h | 46 ++ arch/mips/include/asm/mach-lantiq/war.h | 24 + arch/mips/include/asm/mach-lantiq/xway/irq.h | 18 + .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 62 ++ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 145 ++++ arch/mips/lantiq/Kconfig | 23 + arch/mips/lantiq/Makefile | 11 + arch/mips/lantiq/Platform | 8 + arch/mips/lantiq/clk.c | 135 ++++ arch/mips/lantiq/clk.h | 18 + arch/mips/lantiq/devices.c | 128 ++++ arch/mips/lantiq/devices.h | 20 + arch/mips/lantiq/early_printk.c | 34 + arch/mips/lantiq/irq.c | 319 ++++++++ arch/mips/lantiq/machtypes.h | 20 + arch/mips/lantiq/prom.c | 77 ++ arch/mips/lantiq/prom.h | 24 + arch/mips/lantiq/setup.c | 72 ++ arch/mips/lantiq/xway/Kconfig | 25 + arch/mips/lantiq/xway/Makefile | 7 + arch/mips/lantiq/xway/clk-ase.c | 52 ++ arch/mips/lantiq/xway/clk-xway.c | 232 ++++++ arch/mips/lantiq/xway/devices.c | 79 ++ arch/mips/lantiq/xway/devices.h | 17 + arch/mips/lantiq/xway/ebu.c | 36 + arch/mips/lantiq/xway/gpio.c | 203 +++++ arch/mips/lantiq/xway/gpio_ebu.c | 126 ++++ arch/mips/lantiq/xway/gpio_stp.c | 158 ++++ arch/mips/lantiq/xway/mach-easy50601.c | 70 ++ arch/mips/lantiq/xway/mach-easy50712.c | 75 ++ arch/mips/lantiq/xway/pmu.c | 57 ++ arch/mips/lantiq/xway/prom-ase.c | 40 + arch/mips/lantiq/xway/prom-xway.c | 55 ++ arch/mips/lantiq/xway/reset.c | 67 ++ arch/mips/pci/Makefile | 1 + arch/mips/pci/ops-lantiq.c | 119 +++ arch/mips/pci/pci-lantiq.c | 303 ++++++++ arch/mips/pci/pci-lantiq.h | 18 + drivers/mtd/maps/Kconfig | 7 + drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq.c | 190 +++++ drivers/tty/serial/Kconfig | 8 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/lantiq.c | 775 ++++++++++++++++++++ drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/lantiq_wdt.c | 235 ++++++ 50 files changed, 4226 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq.h create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_platform.h create mode 100644 arch/mips/include/asm/mach-lantiq/war.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h create mode 100644 arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h create mode 100644 arch/mips/lantiq/Kconfig create mode 100644 arch/mips/lantiq/Makefile create mode 100644 arch/mips/lantiq/Platform create mode 100644 arch/mips/lantiq/clk.c create mode 100644 arch/mips/lantiq/clk.h create mode 100644 arch/mips/lantiq/devices.c create mode 100644 arch/mips/lantiq/devices.h create mode 100644 arch/mips/lantiq/early_printk.c create mode 100644 arch/mips/lantiq/irq.c create mode 100644 arch/mips/lantiq/machtypes.h create mode 100644 arch/mips/lantiq/prom.c create mode 100644 arch/mips/lantiq/prom.h create mode 100644 arch/mips/lantiq/setup.c create mode 100644 arch/mips/lantiq/xway/Kconfig create mode 100644 arch/mips/lantiq/xway/Makefile create mode 100644 arch/mips/lantiq/xway/clk-ase.c create mode 100644 arch/mips/lantiq/xway/clk-xway.c create mode 100644 arch/mips/lantiq/xway/devices.c create mode 100644 arch/mips/lantiq/xway/devices.h create mode 100644 arch/mips/lantiq/xway/ebu.c create mode 100644 arch/mips/lantiq/xway/gpio.c create mode 100644 arch/mips/lantiq/xway/gpio_ebu.c create mode 100644 arch/mips/lantiq/xway/gpio_stp.c create mode 100644 arch/mips/lantiq/xway/mach-easy50601.c create mode 100644 arch/mips/lantiq/xway/mach-easy50712.c create mode 100644 arch/mips/lantiq/xway/pmu.c create mode 100644 arch/mips/lantiq/xway/prom-ase.c create mode 100644 arch/mips/lantiq/xway/prom-xway.c create mode 100644 arch/mips/lantiq/xway/reset.c create mode 100644 arch/mips/pci/ops-lantiq.c create mode 100644 arch/mips/pci/pci-lantiq.c create mode 100644 arch/mips/pci/pci-lantiq.h create mode 100644 drivers/mtd/maps/lantiq.c create mode 100644 drivers/tty/serial/lantiq.c create mode 100644 drivers/watchdog/lantiq_wdt.c -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:03:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:03:57 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57613 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491872Ab1CCKCc (ORCPT ); Thu, 3 Mar 2011 11:02:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 07/10] MIPS: lantiq: add platform device support Date: Thu, 3 Mar 2011 11:03:43 +0100 Message-Id: <1299146626-17428-8-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29325 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the wrappers for registering our platform devices. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- Changes in V3 * use pr_* macros instead of printk arch/mips/lantiq/Makefile | 2 +- arch/mips/lantiq/devices.c | 128 +++++++++++++++++++++++++++++++++++++++ arch/mips/lantiq/devices.h | 20 ++++++ arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/devices.c | 79 ++++++++++++++++++++++++ arch/mips/lantiq/xway/devices.h | 17 +++++ 6 files changed, 246 insertions(+), 2 deletions(-) create mode 100644 arch/mips/lantiq/devices.c create mode 100644 arch/mips/lantiq/devices.h create mode 100644 arch/mips/lantiq/xway/devices.c create mode 100644 arch/mips/lantiq/xway/devices.h diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index a268391..e5dae0e 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -4,7 +4,7 @@ # under the terms of the GNU General Public License version 2 as published # by the Free Software Foundation. -obj-y := irq.o setup.o clk.o prom.o +obj-y := irq.o setup.o clk.o prom.o devices.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c new file mode 100644 index 0000000..6dfaffd --- /dev/null +++ b/arch/mips/lantiq/devices.c @@ -0,0 +1,128 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "devices.h" + +#define IRQ_RES(resname, irq) \ + {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} + +/* nor flash */ +static struct resource ltq_nor_resource = { + .name = "nor", + .start = LTQ_FLASH_START, + .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ltq_nor = { + .name = "ltq_nor", + .resource = <q_nor_resource, + .num_resources = 1, +}; + +void __init +ltq_register_nor(struct physmap_flash_data *data) +{ + ltq_nor.dev.platform_data = data; + platform_device_register(<q_nor); +} + +/* watchdog */ +static struct resource ltq_wdt_resource = { + .name = "watchdog", + .start = LTQ_WDT_BASE_ADDR, + .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +void __init +ltq_register_wdt(void) +{ + platform_device_register_simple("ltq_wdt", 0, <q_wdt_resource, 1); +} + +/* asc ports */ +static struct resource ltq_asc0_resources[] = { + { + .start = LTQ_ASC0_BASE_ADDR, + .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + IRQ_RES(tx, LTQ_ASC_TIR(0)), + IRQ_RES(rx, LTQ_ASC_RIR(0)), + IRQ_RES(err, LTQ_ASC_EIR(0)), +}; + +static struct resource ltq_asc1_resources[] = { + { + .start = LTQ_ASC1_BASE_ADDR, + .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + IRQ_RES(tx, LTQ_ASC_TIR(1)), + IRQ_RES(rx, LTQ_ASC_RIR(1)), + IRQ_RES(err, LTQ_ASC_EIR(1)), +}; + +void __init +ltq_register_asc(int port) +{ + switch (port) { + case 0: + platform_device_register_simple("ltq_asc", 0, + ltq_asc0_resources, ARRAY_SIZE(ltq_asc0_resources)); + break; + case 1: + platform_device_register_simple("ltq_asc", 1, + ltq_asc1_resources, ARRAY_SIZE(ltq_asc1_resources)); + break; + default: + break; + } +} + +#ifdef CONFIG_PCI +/* pci */ +static struct platform_device ltq_pci = { + .name = "ltq_pci", + .num_resources = 0, +}; + +void __init +ltq_register_pci(struct ltq_pci_data *data) +{ + ltq_pci.dev.platform_data = data; + platform_device_register(<q_pci); +} +#else +void __init +ltq_register_pci(struct ltq_pci_data *data) +{ + pr_err("kernel is compiled without PCI support\n"); +} +#endif diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h new file mode 100644 index 0000000..069006c --- /dev/null +++ b/arch/mips/lantiq/devices.h @@ -0,0 +1,20 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_DEVICES_H__ +#define _LTQ_DEVICES_H__ + +#include +#include + +extern void ltq_register_nor(struct physmap_flash_data *data); +extern void ltq_register_wdt(void); +extern void ltq_register_asc(int port); +extern void ltq_register_pci(struct ltq_pci_data *data); + +#endif diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 9c85ff9..74ce438 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := pmu.o ebu.o reset.o gpio.o +obj-y := pmu.o ebu.o reset.o gpio.o devices.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c new file mode 100644 index 0000000..37543f8 --- /dev/null +++ b/arch/mips/lantiq/xway/devices.c @@ -0,0 +1,79 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +/* gpio */ +static struct resource ltq_gpio_resource[] = { + { + .name = "gpio0", + .start = LTQ_GPIO0_BASE_ADDR, + .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "gpio1", + .start = LTQ_GPIO1_BASE_ADDR, + .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "gpio2", + .start = LTQ_GPIO2_BASE_ADDR, + .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +void __init +ltq_register_gpio(void) +{ + platform_device_register_simple("ltq_gpio", 0, + <q_gpio_resource[0], 1); + platform_device_register_simple("ltq_gpio", 1, + <q_gpio_resource[1], 1); + + /* AR9 and VR9 have an extra gpio block */ + if (ltq_is_ar9() || ltq_is_vr9()) { + platform_device_register_simple("ltq_gpio", 2, + <q_gpio_resource[2], 1); + } +} + +/* serial to parallel conversion */ +static struct resource ltq_stp_resource = { + .name = "stp", + .start = LTQ_STP_BASE_ADDR, + .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +void __init +ltq_register_gpio_stp(void) +{ + platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1); +} diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h new file mode 100644 index 0000000..87ba61e --- /dev/null +++ b/arch/mips/lantiq/xway/devices.h @@ -0,0 +1,17 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_DEVICES_XWAY_H__ +#define _LTQ_DEVICES_XWAY_H__ + +#include "../devices.h" + +extern void ltq_register_gpio(void); +extern void ltq_register_gpio_stp(void); + +#endif -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:04:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:04:25 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57614 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491881Ab1CCKCc (ORCPT ); Thu, 3 Mar 2011 11:02:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: [PATCH V3 05/10] MIPS: lantiq: add watchdog support Date: Thu, 3 Mar 2011 11:03:41 +0100 Message-Id: <1299146626-17428-6-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29326 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the watchdog found inside the Lantiq SoC family. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: Wim Van Sebroeck Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org --- Changes in V2 * add comments to explain register access * cleanup resource allocation * cleanup clock handling * whitespace fixes Changes in V3 * whitespace * change __iomem void to void __iomem * typo fixes * comment style * fix exit path in init function drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/lantiq_wdt.c | 235 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+), 0 deletions(-) create mode 100644 drivers/watchdog/lantiq_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 2e2400e..c64f8c3 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -972,6 +972,12 @@ config BCM63XX_WDT To compile this driver as a loadable module, choose M here. The module will be called bcm63xx_wdt. +config LANTIQ_WDT + tristate "Lantiq SoC watchdog" + depends on LANTIQ + help + Hardware driver for the Lantiq SoC Watchdog Timer. + # PARISC Architecture # POWERPC Architecture diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index dd77665..68299db 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -121,6 +121,7 @@ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o obj-$(CONFIG_TXX9_WDT) += txx9wdt.o obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o # PARISC Architecture diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c new file mode 100644 index 0000000..d49ddaa --- /dev/null +++ b/drivers/watchdog/lantiq_wdt.c @@ -0,0 +1,235 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + * Based on EP93xx wdt driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Section 3.4 of the datasheet + * The password sequence protects the WDT control register from unintended + * write actions, which might cause malfunction of the WDT. + * + * essentially the following two magic passwords need to be written to allow + * io access to the wdt core + */ +#define LTQ_WDT_PW1 0x00BE0000 +#define LTQ_WDT_PW2 0x00DC0000 + +#define LTQ_WDT_CR 0x03F0 /* watchdog control register */ +#define LTQ_WDT_SR 0x03F8 /* watchdog status register */ + +#define LTQ_WDT_SR_EN (0x1 << 31) /* enable bit */ +#define LTQ_WDT_SR_PWD (0x3 << 26) /* turn on power */ +#define LTQ_WDT_SR_CLKDIV (0x3 << 24) /* turn on clock and set */ + /* divider to 0x40000 */ +#define LTQ_WDT_DIVIDER 0x40000 +#define LTQ_MAX_TIMEOUT ((1 << 16) - 1) /* the reload field is 16 bit */ + +#ifndef CONFIG_WATCHDOG_NOWAYOUT +static int ltq_wdt_ok_to_close; +#endif + +static int ltq_wdt_timeout = 30; +static void __iomem *ltq_wdt_membase; +static unsigned long ltq_io_region_clk_rate; + +static void +ltq_wdt_enable(unsigned int timeout) +{ + timeout = ((timeout * (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER)) + + 0x1000); + if (timeout > LTQ_MAX_TIMEOUT) + timeout = LTQ_MAX_TIMEOUT; + + /* write the first password magic */ + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); + /* write the second magic plus the configuration and new timeout */ + ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV | + LTQ_WDT_PW2 | timeout, ltq_wdt_membase + LTQ_WDT_CR); +} + +static void +ltq_wdt_disable(void) +{ +#ifndef CONFIG_WATCHDOG_NOWAYOUT + ltq_wdt_ok_to_close = 0; +#endif + /* write the first paswword magic */ + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); + /* write the second paswword magic with no config + * this turns the watchdog off + */ + ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR); +} + +static ssize_t +ltq_wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) +{ + size_t i; + + if (!len) + return 0; +#ifndef CONFIG_WATCHDOG_NOWAYOUT + for (i = 0; i != len; i++) { + char c; + + if (get_user(c, data + i)) + return -EFAULT; + if (c == 'V') + ltq_wdt_ok_to_close = 1; + } +#endif + ltq_wdt_enable(ltq_wdt_timeout); + return len; +} + +static struct watchdog_info ident = { + .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, + .identity = "ltq_wdt", +}; + +static long +ltq_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = -ENOTTY; + + switch (cmd) { + case WDIOC_GETSUPPORT: + ret = copy_to_user((struct watchdog_info __user *)arg, &ident, + sizeof(ident)) ? -EFAULT : 0; + break; + + case WDIOC_GETTIMEOUT: + ret = put_user(ltq_wdt_timeout, (int __user *)arg); + break; + + case WDIOC_SETTIMEOUT: + ret = get_user(ltq_wdt_timeout, (int __user *)arg); + if (!ret) + ltq_wdt_enable(ltq_wdt_timeout); + break; + + case WDIOC_KEEPALIVE: + ltq_wdt_enable(ltq_wdt_timeout); + ret = 0; + break; + } + return ret; +} + +static int +ltq_wdt_open(struct inode *inode, struct file *file) +{ + ltq_wdt_enable(ltq_wdt_timeout); + return nonseekable_open(inode, file); +} + +static int +ltq_wdt_release(struct inode *inode, struct file *file) +{ +#ifndef CONFIG_WATCHDOG_NOWAYOUT + if (ltq_wdt_ok_to_close) + ltq_wdt_disable(); + else +#endif + pr_err("ltq_wdt: watchdog closed without warning\n"); + return 0; +} + +static const struct file_operations ltq_wdt_fops = { + .owner = THIS_MODULE, + .write = ltq_wdt_write, + .unlocked_ioctl = ltq_wdt_ioctl, + .open = ltq_wdt_open, + .release = ltq_wdt_release, + .llseek = no_llseek, +}; + +static struct miscdevice ltq_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = <q_wdt_fops, +}; + +static int +ltq_wdt_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk *clk; + + if (!res) { + dev_err(&pdev->dev, "cannot obtain I/O memory region"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "cannot request I/O memory region"); + return -EBUSY; + } + ltq_wdt_membase = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ltq_wdt_membase) { + dev_err(&pdev->dev, "cannot remap I/O memory region\n"); + return -ENOMEM; + } + /* we do not need to enable the clock as it is always running */ + clk = clk_get(&pdev->dev, "io"); + if (!clk) + BUG(); + ltq_io_region_clk_rate = clk_get_rate(clk); + clk_put(clk); + return misc_register(<q_wdt_miscdev); +} + +static int __exit +ltq_wdt_remove(struct platform_device *dev) +{ + ltq_wdt_disable(); + misc_deregister(<q_wdt_miscdev); + return 0; +} + +static struct platform_driver ltq_wdt_driver = { + .probe = ltq_wdt_probe, + .remove = ltq_wdt_remove, + .driver = { + .name = "ltq_wdt", + .owner = THIS_MODULE, + }, +}; + +static int __init +init_ltq_wdt(void) +{ + return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); +} + +static void __exit +exit_ltq_wdt(void) +{ + platform_driver_unregister(<q_wdt_driver); +} + +module_init(init_ltq_wdt); +module_exit(exit_ltq_wdt); + +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq Watchdog"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:04:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:04:49 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57611 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491868Ab1CCKCc (ORCPT ); Thu, 3 Mar 2011 11:02:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , Felix Fietkau , linux-mips@linux-mips.org Subject: [PATCH V3 04/10] MIPS: lantiq: add serial port support Date: Thu, 3 Mar 2011 11:03:40 +0100 Message-Id: <1299146626-17428-5-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29327 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the driver for the 2 serial ports found inside the Lantiq SoC family Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Signed-off-by: Felix Fietkau Cc: linux-mips@linux-mips.org --- Changes in V2 * small cleanups * use global register access macros * properly register memory resources Changes in V3 * whitespace * change __iomem void to void __iomem * multiline comments * use pr_* macros instead of printk drivers/tty/serial/Kconfig | 8 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/lantiq.c | 775 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 784 insertions(+), 0 deletions(-) create mode 100644 drivers/tty/serial/lantiq.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 2b83346..8f286eb 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1402,6 +1402,14 @@ config SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE help Support for Console on the NWP serial ports. +config SERIAL_LANTIQ + bool "Lantiq serial driver" + depends on LANTIQ + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + help + Support for console and UART on Lantiq SoCs. + config SERIAL_QE tristate "Freescale QUICC Engine serial port support" depends on QUICC_ENGINE diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 8ea92e9..1aebd4d 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -92,3 +92,4 @@ obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o +obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c new file mode 100644 index 0000000..32ea464 --- /dev/null +++ b/drivers/tty/serial/lantiq.c @@ -0,0 +1,775 @@ +/* + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (C) 2004 Infineon IFAP DC COM CPE + * Copyright (C) 2007 Felix Fietkau + * Copyright (C) 2007 John Crispin + * Copyright (C) 2010 Thomas Langer, + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PORT_LTQ_ASC 111 +#define MAXPORTS 2 +#define UART_DUMMY_UER_RX 1 +#define DRVNAME "ltq_asc" +#ifdef __BIG_ENDIAN +#define LTQ_ASC_TBUF (0x0020 + 3) +#define LTQ_ASC_RBUF (0x0024 + 3) +#else +#define LTQ_ASC_TBUF 0x0020 +#define LTQ_ASC_RBUF 0x0024 +#endif +#define LTQ_ASC_FSTAT 0x0048 +#define LTQ_ASC_WHBSTATE 0x0018 +#define LTQ_ASC_STATE 0x0014 +#define LTQ_ASC_IRNCR 0x00F8 +#define LTQ_ASC_CLC 0x0000 +#define LTQ_ASC_ID 0x0008 +#define LTQ_ASC_PISEL 0x0004 +#define LTQ_ASC_TXFCON 0x0044 +#define LTQ_ASC_RXFCON 0x0040 +#define LTQ_ASC_CON 0x0010 +#define LTQ_ASC_BG 0x0050 +#define LTQ_ASC_IRNREN 0x00F4 + +#define ASC_IRNREN_TX 0x1 +#define ASC_IRNREN_RX 0x2 +#define ASC_IRNREN_ERR 0x4 +#define ASC_IRNREN_TX_BUF 0x8 +#define ASC_IRNCR_TIR 0x1 +#define ASC_IRNCR_RIR 0x2 +#define ASC_IRNCR_EIR 0x4 + +#define ASCOPT_CSIZE 0x3 +#define ASCOPT_CS7 0x1 +#define ASCOPT_CS8 0x2 +#define ASCOPT_PARENB 0x4 +#define ASCOPT_STOPB 0x8 +#define ASCOPT_PARODD 0x0 +#define ASCOPT_CREAD 0x20 +#define TXFIFO_FL 1 +#define RXFIFO_FL 1 +#define ASCCLC_DISS 0x2 +#define ASCCLC_RMCMASK 0x0000FF00 +#define ASCCLC_RMCOFFSET 8 +#define ASCCON_M_8ASYNC 0x0 +#define ASCCON_M_7ASYNC 0x2 +#define ASCCON_ODD 0x00000020 +#define ASCCON_STP 0x00000080 +#define ASCCON_BRS 0x00000100 +#define ASCCON_FDE 0x00000200 +#define ASCCON_R 0x00008000 +#define ASCCON_FEN 0x00020000 +#define ASCCON_ROEN 0x00080000 +#define ASCCON_TOEN 0x00100000 +#define ASCSTATE_PE 0x00010000 +#define ASCSTATE_FE 0x00020000 +#define ASCSTATE_ROE 0x00080000 +#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) +#define ASCWHBSTATE_CLRREN 0x00000001 +#define ASCWHBSTATE_SETREN 0x00000002 +#define ASCWHBSTATE_CLRPE 0x00000004 +#define ASCWHBSTATE_CLRFE 0x00000008 +#define ASCWHBSTATE_CLRROE 0x00000020 +#define ASCTXFCON_TXFEN 0x0001 +#define ASCTXFCON_TXFFLU 0x0002 +#define ASCTXFCON_TXFITLMASK 0x3F00 +#define ASCTXFCON_TXFITLOFF 8 +#define ASCRXFCON_RXFEN 0x0001 +#define ASCRXFCON_RXFFLU 0x0002 +#define ASCRXFCON_RXFITLMASK 0x3F00 +#define ASCRXFCON_RXFITLOFF 8 +#define ASCFSTAT_RXFFLMASK 0x003F +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFFLOFF 8 +#define ASCFSTAT_RXFREEMASK 0x003F0000 +#define ASCFSTAT_RXFREEOFF 16 +#define ASCFSTAT_TXFREEMASK 0x3F000000 +#define ASCFSTAT_TXFREEOFF 24 + +static void lqasc_tx_chars(struct uart_port *port); +static struct ltq_uart_port *lqasc_port[2]; +static struct uart_driver lqasc_reg; + +struct ltq_uart_port { + struct uart_port port; + struct clk *clk; + unsigned int tx_irq; + unsigned int rx_irq; + unsigned int err_irq; +}; + +static inline struct +ltq_uart_port *to_ltq_uart_port(struct uart_port *port) +{ + return container_of(port, struct ltq_uart_port, port); +} + +static void +lqasc_stop_tx(struct uart_port *port) +{ + return; +} + +static void +lqasc_start_tx(struct uart_port *port) +{ + unsigned long flags; + local_irq_save(flags); + lqasc_tx_chars(port); + local_irq_restore(flags); + return; +} + +static void +lqasc_stop_rx(struct uart_port *port) +{ + ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); +} + +static void +lqasc_enable_ms(struct uart_port *port) +{ +} + +static void +lqasc_rx_chars(struct uart_port *port) +{ + struct tty_struct *tty = port->state->port.tty; + unsigned int ch = 0, rsr = 0, fifocnt; + + fifocnt = + ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; + while (fifocnt--) { + u8 flag = TTY_NORMAL; + ch = ltq_r8(port->membase + LTQ_ASC_RBUF); + rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) + & ASCSTATE_ANY) | UART_DUMMY_UER_RX; + tty_flip_buffer_push(tty); + port->icount.rx++; + + /* + * Note that the error handling code is + * out of the main execution path + */ + if (rsr & ASCSTATE_ANY) { + if (rsr & ASCSTATE_PE) { + port->icount.parity++; + ltq_w32_mask(0, ASCWHBSTATE_CLRPE, + port->membase + LTQ_ASC_WHBSTATE); + } else if (rsr & ASCSTATE_FE) { + port->icount.frame++; + ltq_w32_mask(0, ASCWHBSTATE_CLRFE, + port->membase + LTQ_ASC_WHBSTATE); + } + if (rsr & ASCSTATE_ROE) { + port->icount.overrun++; + ltq_w32_mask(0, ASCWHBSTATE_CLRROE, + port->membase + LTQ_ASC_WHBSTATE); + } + + rsr &= port->read_status_mask; + + if (rsr & ASCSTATE_PE) + flag = TTY_PARITY; + else if (rsr & ASCSTATE_FE) + flag = TTY_FRAME; + } + + if ((rsr & port->ignore_status_mask) == 0) + tty_insert_flip_char(tty, ch, flag); + + if (rsr & ASCSTATE_ROE) + /* + * Overrun is special, since it's reported + * immediately, and doesn't affect the current + * character + */ + tty_insert_flip_char(tty, 0, TTY_OVERRUN); + } + if (ch != 0) + tty_flip_buffer_push(tty); + return; +} + +static void +lqasc_tx_chars(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + if (uart_tx_stopped(port)) { + lqasc_stop_tx(port); + return; + } + + while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { + if (port->x_char) { + ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); + port->icount.tx++; + port->x_char = 0; + continue; + } + + if (uart_circ_empty(xmit)) + break; + + ltq_w8(port->state->xmit.buf[port->state->xmit.tail], + port->membase + LTQ_ASC_TBUF); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); +} + +static irqreturn_t +lqasc_tx_int(int irq, void *_port) +{ + struct uart_port *port = (struct uart_port *)_port; + ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); + lqasc_start_tx(port); + return IRQ_HANDLED; +} + +static irqreturn_t +lqasc_err_int(int irq, void *_port) +{ + struct uart_port *port = (struct uart_port *)_port; + /* clear any pending interrupts */ + ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | + ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); + return IRQ_HANDLED; +} + +static irqreturn_t +lqasc_rx_int(int irq, void *_port) +{ + struct uart_port *port = (struct uart_port *)_port; + ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); + lqasc_rx_chars(port); + return IRQ_HANDLED; +} + +static unsigned int +lqasc_tx_empty(struct uart_port *port) +{ + int status; + status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; + return status ? 0 : TIOCSER_TEMT; +} + +static unsigned int +lqasc_get_mctrl(struct uart_port *port) +{ + return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; +} + +static void +lqasc_set_mctrl(struct uart_port *port, u_int mctrl) +{ +} + +static void +lqasc_break_ctl(struct uart_port *port, int break_state) +{ +} + +static int +lqasc_startup(struct uart_port *port) +{ + struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); + int retval; + + port->uartclk = clk_get_rate(ltq_port->clk); + + ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + port->membase + LTQ_ASC_CLC); + + ltq_w32(0, port->membase + LTQ_ASC_PISEL); + ltq_w32( + ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | + ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); + ltq_w32( + ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) + | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); + /* make sure other settings are written to hardware before + * setting enable bits + */ + wmb(); + ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | + ASCCON_ROEN, port->membase + LTQ_ASC_CON); + + retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, + IRQF_DISABLED, "asc_tx", port); + if (retval) { + pr_err("failed to request lqasc_tx_int\n"); + return retval; + } + + retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, + IRQF_DISABLED, "asc_rx", port); + if (retval) { + pr_err("failed to request lqasc_rx_int\n"); + goto err1; + } + + retval = request_irq(ltq_port->err_irq, lqasc_err_int, + IRQF_DISABLED, "asc_err", port); + if (retval) { + pr_err("failed to request lqasc_err_int\n"); + goto err2; + } + + ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, + port->membase + LTQ_ASC_IRNREN); + return 0; + +err2: + free_irq(ltq_port->rx_irq, port); +err1: + free_irq(ltq_port->tx_irq, port); + return retval; +} + +static void +lqasc_shutdown(struct uart_port *port) +{ + struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); + free_irq(ltq_port->tx_irq, port); + free_irq(ltq_port->rx_irq, port); + free_irq(ltq_port->err_irq, port); + + ltq_w32(0, port->membase + LTQ_ASC_CON); + ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); + ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); +} + +static void +lqasc_set_termios(struct uart_port *port, + struct ktermios *new, struct ktermios *old) +{ + unsigned int cflag; + unsigned int iflag; + unsigned int quot; + unsigned int baud; + unsigned int con = 0; + unsigned long flags; + + cflag = new->c_cflag; + iflag = new->c_iflag; + + switch (cflag & CSIZE) { + case CS7: + con = ASCCON_M_7ASYNC; + break; + + case CS5: + case CS6: + default: + con = ASCCON_M_8ASYNC; + break; + } + + if (cflag & CSTOPB) + con |= ASCCON_STP; + + if (cflag & PARENB) { + if (!(cflag & PARODD)) + con &= ~ASCCON_ODD; + else + con |= ASCCON_ODD; + } + + port->read_status_mask = ASCSTATE_ROE; + if (iflag & INPCK) + port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; + + port->ignore_status_mask = 0; + if (iflag & IGNPAR) + port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; + + if (iflag & IGNBRK) { + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (iflag & IGNPAR) + port->ignore_status_mask |= ASCSTATE_ROE; + } + + if ((cflag & CREAD) == 0) + port->ignore_status_mask |= UART_DUMMY_UER_RX; + + /* set error signals - framing, parity and overrun, enable receiver */ + con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; + + local_irq_save(flags); + + /* set up CON */ + ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); + + /* Set baud rate - take a divider of 2 into account */ + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); + quot = uart_get_divisor(port, baud); + quot = quot / 2 - 1; + + /* disable the baudrate generator */ + ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); + + /* make sure the fractional divider is off */ + ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); + + /* set up to use divisor of 2 */ + ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); + + /* now we can write the new baudrate into the register */ + ltq_w32(quot, port->membase + LTQ_ASC_BG); + + /* turn the baudrate generator back on */ + ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); + + /* enable rx */ + ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); + + local_irq_restore(flags); +} + +static const char* +lqasc_type(struct uart_port *port) +{ + if (port->type == PORT_LTQ_ASC) + return DRVNAME; + else + return NULL; +} + +static void +lqasc_release_port(struct uart_port *port) +{ + if (port->flags & UPF_IOREMAP) { + iounmap(port->membase); + port->membase = NULL; + } +} + +static int +lqasc_request_port(struct uart_port *port) +{ + struct platform_device *pdev = to_platform_device(port->dev); + struct resource *res; + int size; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "cannot obtain I/O memory region"); + return -ENODEV; + } + size = resource_size(res); + + res = devm_request_mem_region(&pdev->dev, res->start, + size, dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "cannot request I/O memory region"); + return -EBUSY; + } + + if (port->flags & UPF_IOREMAP) { + port->membase = devm_ioremap_nocache(&pdev->dev, + port->mapbase, size); + if (port->membase == NULL) + return -ENOMEM; + } + return 0; +} + +static void +lqasc_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) { + port->type = PORT_LTQ_ASC; + lqasc_request_port(port); + } +} + +static int +lqasc_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) + ret = -EINVAL; + if (ser->irq < 0 || ser->irq >= NR_IRQS) + ret = -EINVAL; + if (ser->baud_base < 9600) + ret = -EINVAL; + return ret; +} + +static struct uart_ops lqasc_pops = { + .tx_empty = lqasc_tx_empty, + .set_mctrl = lqasc_set_mctrl, + .get_mctrl = lqasc_get_mctrl, + .stop_tx = lqasc_stop_tx, + .start_tx = lqasc_start_tx, + .stop_rx = lqasc_stop_rx, + .enable_ms = lqasc_enable_ms, + .break_ctl = lqasc_break_ctl, + .startup = lqasc_startup, + .shutdown = lqasc_shutdown, + .set_termios = lqasc_set_termios, + .type = lqasc_type, + .release_port = lqasc_release_port, + .request_port = lqasc_request_port, + .config_port = lqasc_config_port, + .verify_port = lqasc_verify_port, +}; + +static void +lqasc_console_putchar(struct uart_port *port, int ch) +{ + int fifofree; + + if (!port->membase) + return; + + do { + fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) + & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; + } while (fifofree == 0); + ltq_w8(ch, port->membase + LTQ_ASC_TBUF); +} + + +static void +lqasc_console_write(struct console *co, const char *s, u_int count) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + unsigned long flags; + + if (co->index >= MAXPORTS) + return; + + ltq_port = lqasc_port[co->index]; + if (!ltq_port) + return; + + port = <q_port->port; + + local_irq_save(flags); + uart_console_write(port, s, count, lqasc_console_putchar); + local_irq_restore(flags); +} + +static int __init +lqasc_console_setup(struct console *co, char *options) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + if (co->index >= MAXPORTS) + return -ENODEV; + + ltq_port = lqasc_port[co->index]; + if (!ltq_port) + return -ENODEV; + + port = <q_port->port; + + port->uartclk = clk_get_rate(ltq_port->clk); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console lqasc_console = { + .name = "ttyS", + .write = lqasc_console_write, + .device = uart_console_device, + .setup = lqasc_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &lqasc_reg, +}; + +static int __init +lqasc_console_init(void) +{ + register_console(&lqasc_console); + return 0; +} +console_initcall(lqasc_console_init); + +static struct uart_driver lqasc_reg = { + .owner = THIS_MODULE, + .driver_name = DRVNAME, + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .nr = MAXPORTS, + .cons = &lqasc_console, +}; + +static int __devinit +lqasc_probe(struct platform_device *pdev) +{ + struct ltq_uart_port *ltq_port; + struct uart_port *port; + struct resource *mmres, *irqres; + int tx_irq, rx_irq, err_irq; + struct clk *clk; + int ret; + + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!mmres || !irqres) + return -ENODEV; + + if (pdev->id >= MAXPORTS) + return -EBUSY; + + if (lqasc_port[pdev->id] != NULL) + return -EBUSY; + + clk = clk_get(&pdev->dev, "fpi"); + if (IS_ERR(clk)) { + pr_err("failed to get fpi clk\n"); + return -ENOENT; + } + + tx_irq = platform_get_irq_byname(pdev, "tx"); + if (tx_irq < 0) { + /* without named resources: assume standard irq scheme */ + tx_irq = irqres->start; + rx_irq = irqres->start+2; + err_irq = irqres->start+3; + } else { + /* other irqs must be named also! */ + rx_irq = platform_get_irq_byname(pdev, "rx"); + err_irq = platform_get_irq_byname(pdev, "err"); + if ((rx_irq < 0) | (err_irq < 0)) + return -ENODEV; + } + + ltq_port = kzalloc(sizeof(struct ltq_uart_port), GFP_KERNEL); + if (!ltq_port) + return -ENOMEM; + + port = <q_port->port; + + port->iotype = SERIAL_IO_MEM; + port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP; + port->ops = &lqasc_pops; + port->fifosize = 16; + port->type = PORT_LTQ_ASC, + port->line = pdev->id; + port->dev = &pdev->dev; + + port->irq = tx_irq; /* unused, just to be backward-compatibe */ + port->mapbase = mmres->start; + + ltq_port->clk = clk; + + ltq_port->tx_irq = tx_irq; + ltq_port->rx_irq = rx_irq; + ltq_port->err_irq = err_irq; + + lqasc_port[pdev->id] = ltq_port; + platform_set_drvdata(pdev, ltq_port); + + ret = uart_add_one_port(&lqasc_reg, port); + + return ret; +} + +static int __devexit +lqasc_remove(struct platform_device *pdev) +{ + struct ltq_uart_port *ltq_port = platform_get_drvdata(pdev); + int ret; + + clk_put(ltq_port->clk); + platform_set_drvdata(pdev, NULL); + lqasc_port[pdev->id] = NULL; + ret = uart_remove_one_port(&lqasc_reg, <q_port->port); + kfree(ltq_port); + + return 0; +} + +static struct platform_driver lqasc_driver = { + .probe = lqasc_probe, + .remove = __devexit_p(lqasc_remove), + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, +}; + +int __init +init_lqasc(void) +{ + int ret; + + ret = uart_register_driver(&lqasc_reg); + if (ret != 0) + return ret; + + ret = platform_driver_register(&lqasc_driver); + if (ret != 0) + uart_unregister_driver(&lqasc_reg); + + return ret; +} + +void __exit +exit_lqasc(void) +{ + platform_driver_unregister(&lqasc_driver); + uart_unregister_driver(&lqasc_reg); +} + +module_init(init_lqasc); +module_exit(exit_lqasc); + +MODULE_DESCRIPTION("Lantiq serial port driver"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:05:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:05:13 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57612 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491870Ab1CCKCc (ORCPT ); Thu, 3 Mar 2011 11:02:32 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 01/10] MIPS: lantiq: add initial support for Lantiq SoCs Date: Thu, 3 Mar 2011 11:03:37 +0100 Message-Id: <1299146626-17428-2-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29328 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- Changes in V2 * handle external interrup sources * properly set io_base * handle CMDLINE properly * remove custom early_printf Changes in V3 * whitespace * change __iomem void to void __iomem * multiline comments * use pr_* macros instead of printk arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 17 ++ arch/mips/include/asm/mach-lantiq/lantiq.h | 58 +++++ arch/mips/include/asm/mach-lantiq/war.h | 24 ++ arch/mips/lantiq/Makefile | 9 + arch/mips/lantiq/Platform | 7 + arch/mips/lantiq/clk.c | 135 ++++++++++++ arch/mips/lantiq/clk.h | 18 ++ arch/mips/lantiq/early_printk.c | 34 +++ arch/mips/lantiq/irq.c | 319 ++++++++++++++++++++++++++++ arch/mips/lantiq/prom.c | 77 +++++++ arch/mips/lantiq/prom.h | 24 ++ arch/mips/lantiq/setup.c | 47 ++++ 13 files changed, 770 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq.h create mode 100644 arch/mips/include/asm/mach-lantiq/war.h create mode 100644 arch/mips/lantiq/Makefile create mode 100644 arch/mips/lantiq/Platform create mode 100644 arch/mips/lantiq/clk.c create mode 100644 arch/mips/lantiq/clk.h create mode 100644 arch/mips/lantiq/early_printk.c create mode 100644 arch/mips/lantiq/irq.c create mode 100644 arch/mips/lantiq/prom.c create mode 100644 arch/mips/lantiq/prom.h create mode 100644 arch/mips/lantiq/setup.c diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 7ff9b54..aef6c91 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -11,6 +11,7 @@ platforms += dec platforms += emma platforms += jazz platforms += jz4740 +platforms += lantiq platforms += lasat platforms += loongson platforms += mipssim diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bd7b64d..f975932 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -210,6 +210,23 @@ config MACH_JZ4740 select SYS_HAS_EARLY_PRINTK select HAVE_PWM +config LANTIQ + bool "Lantiq based platforms" + select DMA_NONCOHERENT + select IRQ_CPU + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_MULTITHREADING + select SYS_HAS_EARLY_PRINTK + select ARCH_REQUIRE_GPIOLIB + select SWAP_IO_SPACE + select BOOT_RAW + select HAVE_CLK + config LASAT bool "LASAT Networks platforms" select CEVT_R4K diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h new file mode 100644 index 0000000..f7f4516 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -0,0 +1,58 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LANTIQ_H__ +#define _LANTIQ_H__ + +/* generic reg access functions */ +#define ltq_r32(reg) __raw_readl(reg) +#define ltq_w32(val, reg) __raw_writel(val, reg) +#define ltq_w32_mask(clear, set, reg) \ + ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg) +#define ltq_r8(reg) __raw_readb(reg) +#define ltq_w8(val, reg) __raw_writeb(val, reg) + +/* register access macros for EBU and CGU */ +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) +#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) +#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) + +extern __iomem void *ltq_ebu_membase; +extern __iomem void *ltq_cgu_membase; + +extern unsigned int ltq_get_cpu_ver(void); +extern unsigned int ltq_get_soc_type(void); + +/* clock speeds */ +#define CLOCK_60M 60000000 +#define CLOCK_83M 83333333 +#define CLOCK_111M 111111111 +#define CLOCK_133M 133333333 +#define CLOCK_167M 166666667 +#define CLOCK_200M 200000000 +#define CLOCK_266M 266666666 +#define CLOCK_333M 333333333 +#define CLOCK_400M 400000000 + +/* spinlock all ebu i/o */ +extern spinlock_t ebu_lock; + +/* some irq helpers */ +extern void ltq_disable_irq(unsigned int irq_nr); +extern void ltq_mask_and_ack_irq(unsigned int irq_nr); +extern void ltq_enable_irq(unsigned int irq_nr); + +#define IOPORT_RESOURCE_START 0x10000000 +#define IOPORT_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_START 0x10000000 +#define IOMEM_RESOURCE_END 0xffffffff +#define LTQ_FLASH_START 0x10000000 +#define LTQ_FLASH_MAX 0x04000000 + +#endif diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h new file mode 100644 index 0000000..01b08ef --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/war.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H +#define __ASM_MIPS_MACH_LANTIQ_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile new file mode 100644 index 0000000..6a30de6 --- /dev/null +++ b/arch/mips/lantiq/Makefile @@ -0,0 +1,9 @@ +# Copyright (C) 2010 John Crispin +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := irq.o setup.o clk.o prom.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform new file mode 100644 index 0000000..eef587f --- /dev/null +++ b/arch/mips/lantiq/Platform @@ -0,0 +1,7 @@ +# +# Lantiq +# + +platform-$(CONFIG_LANTIQ) += lantiq/ +cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq +load-$(CONFIG_LANTIQ) = 0xffffffff80002000 diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c new file mode 100644 index 0000000..d0c060e --- /dev/null +++ b/arch/mips/lantiq/clk.c @@ -0,0 +1,135 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "clk.h" + +struct clk { + const char *name; + unsigned long rate; + unsigned long (*get_rate) (void); +}; + +static struct clk *cpu_clk; +static int cpu_clk_cnt; + +/* lantiq socs have 3 static clocks */ +static struct clk cpu_clk_generic[] = { + { + .name = "cpu", + .get_rate = ltq_get_cpu_hz, + }, { + .name = "fpi", + .get_rate = ltq_get_fpi_hz, + }, { + .name = "io", + .get_rate = ltq_get_io_region_clock, + }, +}; + +/* remapped clock register range */ +void __iomem *ltq_cgu_membase; + +void +clk_init(void) +{ + cpu_clk = cpu_clk_generic; + cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic); +} + +static inline int +clk_good(struct clk *clk) +{ + return clk && !IS_ERR(clk); +} + +unsigned long +clk_get_rate(struct clk *clk) +{ + if (unlikely(!clk_good(clk))) + return 0; + + if (clk->rate != 0) + return clk->rate; + + if (clk->get_rate != NULL) + return clk->get_rate(); + + return 0; +} +EXPORT_SYMBOL(clk_get_rate); + +struct clk* +clk_get(struct device *dev, const char *id) +{ + int i; + + for (i = 0; i < cpu_clk_cnt; i++) + if (!strcmp(id, cpu_clk[i].name)) + return &cpu_clk[i]; + BUG(); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +void +clk_put(struct clk *clk) +{ + /* not used */ +} +EXPORT_SYMBOL(clk_put); + +static inline u32 +ltq_get_counter_resolution(void) +{ + u32 res; + + __asm__ __volatile__( + ".set push\n" + ".set mips32r2\n" + ".set noreorder\n" + "rdhwr %0, $3\n" + "ehb\n" + ".set pop\n" + : "=&r" (res) + : /* no input */ + : "memory"); + instruction_hazard(); + return res; +} + +void __init +plat_time_init(void) +{ + struct clk *clk; + + ltq_cgu_membase = ioremap_nocache(LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); + if (!ltq_cgu_membase) { + pr_err("Failed to remap cgu memory\n"); + unreachable(); + } + clk = clk_get(0, "cpu"); + mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); + write_c0_compare(read_c0_count()); + clk_put(clk); +} diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h new file mode 100644 index 0000000..3328925 --- /dev/null +++ b/arch/mips/lantiq/clk.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_CLK_H__ +#define _LTQ_CLK_H__ + +extern void clk_init(void); + +extern unsigned long ltq_get_cpu_hz(void); +extern unsigned long ltq_get_fpi_hz(void); +extern unsigned long ltq_get_io_region_clock(void); + +#endif diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c new file mode 100644 index 0000000..ebccf60 --- /dev/null +++ b/arch/mips/lantiq/early_printk.c @@ -0,0 +1,34 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include + +#include +#include + +/* no ioremap possible at this early stage, lets use KSEG1 instead */ +#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) +#define ASC_BUF 1024 +#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) +#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) +#define TXMASK 0x3F00 +#define TXOFFSET 8 + +void +prom_putchar(char c) +{ + unsigned long flags; + + local_irq_save(flags); + do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); + if (c == '\n') + ltq_w32('\r', LTQ_ASC_TBUF); + ltq_w32(c, LTQ_ASC_TBUF); + local_irq_restore(flags); +} diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c new file mode 100644 index 0000000..bd3c166 --- /dev/null +++ b/arch/mips/lantiq/irq.c @@ -0,0 +1,319 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + * Copyright (C) 2010 Thomas Langer + */ + +#include +#include + +#include +#include + +#include +#include + +/* register definitions */ +#define LTQ_ICU_IM0_ISR 0x0000 +#define LTQ_ICU_IM0_IER 0x0008 +#define LTQ_ICU_IM0_IOSR 0x0010 +#define LTQ_ICU_IM0_IRSR 0x0018 +#define LTQ_ICU_IM0_IMR 0x0020 +#define LTQ_ICU_IM1_ISR 0x0028 +#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) + +#define LTQ_EIU_EXIN_C 0x0000 +#define LTQ_EIU_EXIN_INIC 0x0004 +#define LTQ_EIU_EXIN_INEN 0x000C + +/* irq numbers used by the external interrupt unit (EIU) */ +#define LTQ_EIU_IR0 INT_NUM_IM4_IRL0 + 30 +#define LTQ_EIU_IR1 INT_NUM_IM3_IRL0 + 31 +#define LTQ_EIU_IR2 INT_NUM_IM1_IRL0 + 26 +#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0 +#define LTQ_EIU_IR4 INT_NUM_IM1_IRL0 + 1 +#define LTQ_EIU_IR5 INT_NUM_IM1_IRL0 + 2 +#define LTQ_EIU_IR6 INT_NUM_IM2_IRL0 + 30 + +#define MAX_EIU 6 + +/* irqs generated by device attached to the EBU need to be acked in + * a special manner + */ +#define LTQ_ICU_EBU_IRQ 22 + +#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y)) +#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x)) + +#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) +#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) + +static unsigned short ltq_eiu_irq[MAX_EIU] = { + LTQ_EIU_IR0, + LTQ_EIU_IR1, + LTQ_EIU_IR2, + LTQ_EIU_IR3, + LTQ_EIU_IR4, + LTQ_EIU_IR5, +}; + +static void __iomem *ltq_icu_membase; +static void __iomem *ltq_eiu_membase; + +void +ltq_disable_irq(unsigned int irq_nr) +{ + u32 ier = LTQ_ICU_IM0_IER; + + irq_nr -= INT_NUM_IRQ0; + ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); +} + +void +ltq_mask_and_ack_irq(unsigned int irq_nr) +{ + u32 ier = LTQ_ICU_IM0_IER; + u32 isr = LTQ_ICU_IM0_ISR; + + irq_nr -= INT_NUM_IRQ0; + ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); + ltq_icu_w32((1 << irq_nr), isr); +} + +static void +ltq_ack_irq(unsigned int irq_nr) +{ + u32 isr = LTQ_ICU_IM0_ISR; + + irq_nr -= INT_NUM_IRQ0; + isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + ltq_icu_w32((1 << irq_nr), isr); +} + +void +ltq_enable_irq(unsigned int irq_nr) +{ + u32 ier = LTQ_ICU_IM0_IER; + + irq_nr -= INT_NUM_IRQ0; + ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier); +} + +static unsigned int +ltq_startup_eiu_irq(unsigned int irq) +{ + int i; + + ltq_enable_irq(irq); + for (i = 0; i < MAX_EIU; i++) { + if (irq == ltq_eiu_irq[i]) { + /* low level - we should really handle set_type */ + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | (0x6 << (i * 4)), + LTQ_EIU_EXIN_C); + /* clear all pending */ + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~(1 << i), + LTQ_EIU_EXIN_INIC); + /* enable */ + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | (1 << i), + LTQ_EIU_EXIN_INEN); + break; + } + } + return 0; +} + +static void +ltq_shutdown_eiu_irq(unsigned int irq) +{ + int i; + + ltq_disable_irq(irq); + for (i = 0; i < MAX_EIU; i++) { + if (irq == ltq_eiu_irq[i]) { + /* disable */ + ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i), + LTQ_EIU_EXIN_INEN); + break; + } + } +} + +static void +ltq_end_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + ltq_enable_irq(irq); +} + +static struct irq_chip +ltq_irq_type = { + "ltq_irq", + .enable = ltq_enable_irq, + .disable = ltq_disable_irq, + .unmask = ltq_enable_irq, + .ack = ltq_ack_irq, + .mask = ltq_disable_irq, + .mask_ack = ltq_mask_and_ack_irq, + .end = ltq_end_irq, +}; + +static struct irq_chip +ltq_eiu_type = { + "ltq_eiu_irq", + .startup = ltq_startup_eiu_irq, + .shutdown = ltq_shutdown_eiu_irq, + .enable = ltq_enable_irq, + .disable = ltq_disable_irq, + .unmask = ltq_enable_irq, + .ack = ltq_ack_irq, + .mask = ltq_disable_irq, + .mask_ack = ltq_mask_and_ack_irq, + .end = ltq_end_irq, +}; + +static void +ltq_hw_irqdispatch(int module) +{ + u32 irq; + + irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); + if (irq == 0) + return; + + /* silicon bug causes only the msb set to 1 to be valid. all + * other bits might be bogus + */ + irq = __fls(irq); + do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); + + /* if this is a EBU irq, we need to ack it or get a deadlock */ + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, + LTQ_EBU_PCC_ISTAT); +} + +#define DEFINE_HWx_IRQDISPATCH(x) \ +static void ltq_hw ## x ## _irqdispatch(void)\ +{\ + ltq_hw_irqdispatch(x); \ +} +DEFINE_HWx_IRQDISPATCH(0) +DEFINE_HWx_IRQDISPATCH(1) +DEFINE_HWx_IRQDISPATCH(2) +DEFINE_HWx_IRQDISPATCH(3) +DEFINE_HWx_IRQDISPATCH(4) + +static void ltq_hw5_irqdispatch(void) +{ + do_IRQ(MIPS_CPU_TIMER_IRQ); +} + +asmlinkage void +plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + unsigned int i; + + if (pending & CAUSEF_IP7) { + do_IRQ(MIPS_CPU_TIMER_IRQ); + goto out; + } else { + for (i = 0; i < 5; i++) { + if (pending & (CAUSEF_IP2 << i)) { + ltq_hw_irqdispatch(i); + goto out; + } + } + } + pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); + +out: + return; +} + +static struct irqaction +cascade = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "cascade", +}; + +void __init +arch_init_irq(void) +{ + int i; + + ltq_icu_membase = ioremap_nocache(LTQ_ICU_BASE_ADDR, LTQ_ICU_SIZE); + if (!ltq_icu_membase) { + pr_err("Failed to remap irq memory\n"); + unreachable(); + } + + ltq_eiu_membase = ioremap_nocache(LTQ_EIU_BASE_ADDR, LTQ_EIU_SIZE); + if (!ltq_eiu_membase) { + pr_err("Failed to remap eiu memory\n"); + unreachable(); + } + + /* make sure all irqs are turned off by default */ + for (i = 0; i < 5; i++) + ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); + + /* clear all possibly pending interrupts */ + ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); + + mips_cpu_irq_init(); + + for (i = 2; i <= 6; i++) + setup_irq(i, &cascade); + + if (cpu_has_vint) { + pr_info("Setting up vectored interrupts\n"); + set_vi_handler(2, ltq_hw0_irqdispatch); + set_vi_handler(3, ltq_hw1_irqdispatch); + set_vi_handler(4, ltq_hw2_irqdispatch); + set_vi_handler(5, ltq_hw3_irqdispatch); + set_vi_handler(6, ltq_hw4_irqdispatch); + set_vi_handler(7, ltq_hw5_irqdispatch); + } + + for (i = INT_NUM_IRQ0; + i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) + if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || + (i == LTQ_EIU_IR2)) + set_irq_chip_and_handler(i, <q_eiu_type, + handle_level_irq); + /* EIU3-5 only exist on ar9 and vr9 */ + else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) || + (i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9())) + set_irq_chip_and_handler(i, <q_eiu_type, + handle_level_irq); + else + set_irq_chip_and_handler(i, <q_irq_type, + handle_level_irq); + +#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | + IE_IRQ3 | IE_IRQ4 | IE_IRQ5); +#else + set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | + IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); +#endif +} + +unsigned int __cpuinit +get_c0_compare_int(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c new file mode 100644 index 0000000..d873830 --- /dev/null +++ b/arch/mips/lantiq/prom.c @@ -0,0 +1,77 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "prom.h" +#include "clk.h" + +static struct ltq_soc_info soc_info; + +unsigned int +ltq_get_cpu_ver(void) +{ + return soc_info.rev; +} +EXPORT_SYMBOL(ltq_get_cpu_ver); + +unsigned int +ltq_get_soc_type(void) +{ + return soc_info.type; +} +EXPORT_SYMBOL(ltq_get_soc_type); + +const char* +get_system_type(void) +{ + return soc_info.sys_type; +} + +void +prom_free_prom_memory(void) +{ +} + +static void __init +prom_init_cmdline(void) +{ + int argc = fw_arg0; + char **argv = (char **) KSEG1ADDR(fw_arg1); + int i; + + for (i = 0; i < argc; i++) { + char *p = (char *) KSEG1ADDR(argv[i]); + + if (p && *p) { + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + } + } +} + +void __init +prom_init(void) +{ + struct clk *clk; + + ltq_soc_detect(&soc_info); + clk_init(); + clk = clk_get(0, "cpu"); + snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", + soc_info.name, soc_info.rev); + clk_put(clk); + soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; + pr_info("SoC: %s\n", soc_info.sys_type); + prom_init_cmdline(); +} diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h new file mode 100644 index 0000000..b9d6562 --- /dev/null +++ b/arch/mips/lantiq/prom.h @@ -0,0 +1,24 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_PROM_H__ +#define _LTQ_PROM_H__ + +#define LTQ_SYS_TYPE_LEN 0x100 + +struct ltq_soc_info { + unsigned char *name; + unsigned int rev; + unsigned int partnum; + unsigned int type; + unsigned char sys_type[LTQ_SYS_TYPE_LEN]; +}; + +void ltq_soc_detect(struct ltq_soc_info *i); + +#endif diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c new file mode 100644 index 0000000..edeb076 --- /dev/null +++ b/arch/mips/lantiq/setup.c @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include + +#include + +void __init +plat_mem_setup(void) +{ + /* assume 16M as default incase uboot fails to pass proper ramsize */ + unsigned long memsize = 16; + char **envp = (char **) KSEG1ADDR(fw_arg2); + u32 status; + + /* make sure to have no "reverse endian" for user mode */ + status = read_c0_status(); + status &= (~(1<<25)); + write_c0_status(status); + + ioport_resource.start = IOPORT_RESOURCE_START; + ioport_resource.end = IOPORT_RESOURCE_END; + iomem_resource.start = IOMEM_RESOURCE_START; + iomem_resource.end = IOMEM_RESOURCE_END; + + set_io_port_base((unsigned long) KSEG1); + + while (*envp) { + char *e = (char *)KSEG1ADDR(*envp); + if (!strncmp(e, "memsize=", 8)) { + e += 8; + strict_strtoul(e, 0, &memsize); + } + envp++; + } + memsize *= 1024 * 1024; + add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); +} -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:05:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:05:40 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57621 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491886Ab1CCKCd (ORCPT ); Thu, 3 Mar 2011 11:02:33 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , Gabor Juhos , linux-mips@linux-mips.org Subject: [PATCH V3 08/10] MIPS: lantiq: add mips_machine support Date: Thu, 3 Mar 2011 11:03:44 +0100 Message-Id: <1299146626-17428-9-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29329 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for Gabor's mips_machine patch. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: Gabor Juhos Cc: linux-mips@linux-mips.org --- arch/mips/Kconfig | 1 + arch/mips/lantiq/machtypes.h | 18 ++++++++++++++++++ arch/mips/lantiq/setup.c | 25 +++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 0 deletions(-) create mode 100644 arch/mips/lantiq/machtypes.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 756e67a..90f405c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -226,6 +226,7 @@ config LANTIQ select SWAP_IO_SPACE select BOOT_RAW select HAVE_CLK + select MIPS_MACHINE config LASAT bool "LASAT Networks platforms" diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h new file mode 100644 index 0000000..ffcacfc --- /dev/null +++ b/arch/mips/lantiq/machtypes.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LANTIQ_MACH_H__ +#define _LANTIQ_MACH_H__ + +#include + +enum lantiq_mach_type { + LTQ_MACH_GENERIC = 0, +}; + +#endif diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c index edeb076..bf35435 100644 --- a/arch/mips/lantiq/setup.c +++ b/arch/mips/lantiq/setup.c @@ -14,6 +14,9 @@ #include +#include "machtypes.h" +#include "devices.h" + void __init plat_mem_setup(void) { @@ -45,3 +48,25 @@ plat_mem_setup(void) memsize *= 1024 * 1024; add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); } + +static int __init +lantiq_setup(void) +{ + ltq_register_asc(0); + ltq_register_asc(1); + mips_machine_setup(); + return 0; +} + +arch_initcall(lantiq_setup); + +static void __init +lantiq_generic_init(void) +{ + /* Nothing to do */ +} + +MIPS_MACHINE(LTQ_MACH_GENERIC, + "Generic", + "Generic Lantiq based board", + lantiq_generic_init); -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:05:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:06:05 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57625 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491887Ab1CCKCd (ORCPT ); Thu, 3 Mar 2011 11:02:33 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 09/10] MIPS: lantiq: add machtypes for lantiq eval kits Date: Thu, 3 Mar 2011 11:03:45 +0100 Message-Id: <1299146626-17428-10-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29330 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips This patch adds mach specific code for the Lantiq EASY50712/50601 evaluation boards Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- Changes in V2 * fix pci platform_device data Changes in V3 * fix Mips -> MIPS typo arch/mips/lantiq/Kconfig | 2 + arch/mips/lantiq/machtypes.h | 2 + arch/mips/lantiq/xway/Kconfig | 25 +++++++++++ arch/mips/lantiq/xway/Makefile | 3 + arch/mips/lantiq/xway/mach-easy50601.c | 70 +++++++++++++++++++++++++++++ arch/mips/lantiq/xway/mach-easy50712.c | 75 ++++++++++++++++++++++++++++++++ 6 files changed, 177 insertions(+), 0 deletions(-) create mode 100644 arch/mips/lantiq/xway/Kconfig create mode 100644 arch/mips/lantiq/xway/mach-easy50601.c create mode 100644 arch/mips/lantiq/xway/mach-easy50712.c diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig index 2780461..3fccf21 100644 --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -18,4 +18,6 @@ config SOC_XWAY select HW_HAS_PCI endchoice +source "arch/mips/lantiq/xway/Kconfig" + endif diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h index ffcacfc..7e01b8c 100644 --- a/arch/mips/lantiq/machtypes.h +++ b/arch/mips/lantiq/machtypes.h @@ -13,6 +13,8 @@ enum lantiq_mach_type { LTQ_MACH_GENERIC = 0, + LTQ_MACH_EASY50712, /* Danube evaluation board */ + LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ }; #endif diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig new file mode 100644 index 0000000..f8a5e3b --- /dev/null +++ b/arch/mips/lantiq/xway/Kconfig @@ -0,0 +1,25 @@ +if SOC_XWAY + +menu "MIPS Machine" + +config LANTIQ_MACH_EASY50712 + bool "Easy50712 - Danube" + default y + +endmenu + +endif + +if SOC_AMAZON_SE + +menu "MIPS Machine" + +config LANTIQ_MACH_EASY50601 + bool "Easy50601 - Amazon SE" + default y + +endmenu + +endif + + diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 74ce438..08dcc10 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -2,3 +2,6 @@ obj-y := pmu.o ebu.o reset.o gpio.o devices.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o + +obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o +obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c new file mode 100644 index 0000000..ce081d7 --- /dev/null +++ b/arch/mips/lantiq/xway/mach-easy50601.c @@ -0,0 +1,70 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "../machtypes.h" +#include "devices.h" + +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition easy50601_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x10000, + }, + { + .name = "uboot_env", + .offset = 0x10000, + .size = 0x10000, + }, + { + .name = "linux", + .offset = 0x20000, + .size = 0xE0000, + }, + { + .name = "rootfs", + .offset = 0x100000, + .size = 0x300000, + }, +}; +#endif + +static struct physmap_flash_data easy50601_flash_data = { +#ifdef CONFIG_MTD_PARTITIONS + .nr_parts = ARRAY_SIZE(easy50601_partitions), + .parts = easy50601_partitions, +#endif +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .req_mask = 0xf, +}; + +static void __init +easy50601_init(void) +{ + ltq_register_gpio(); + ltq_register_nor(&easy50601_flash_data); + ltq_register_wdt(); + ltq_register_pci(<q_pci_data); +} + +MIPS_MACHINE(LTQ_MACH_EASY50601, + "EASY50601", + "EASY50601 Eval Board", + easy50601_init); diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c new file mode 100644 index 0000000..d7963c6 --- /dev/null +++ b/arch/mips/lantiq/xway/mach-easy50712.c @@ -0,0 +1,75 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../machtypes.h" +#include "devices.h" + +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition easy50712_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x10000, + }, + { + .name = "uboot_env", + .offset = 0x10000, + .size = 0x10000, + }, + { + .name = "linux", + .offset = 0x20000, + .size = 0xe0000, + }, + { + .name = "rootfs", + .offset = 0x100000, + .size = 0x300000, + }, +}; +#endif + +static struct physmap_flash_data easy50712_flash_data = { +#ifdef CONFIG_MTD_PARTITIONS + .nr_parts = ARRAY_SIZE(easy50712_partitions), + .parts = easy50712_partitions, +#endif +}; + +static struct ltq_pci_data ltq_pci_data = { + .clock = PCI_CLOCK_INT, + .gpio = PCI_GNT1 | PCI_REQ1, + .irq = { + [14] = INT_NUM_IM0_IRL0 + 22, + }, +}; + +static void __init +easy50712_init(void) +{ + ltq_register_gpio(); + ltq_register_gpio_stp(); + ltq_register_nor(&easy50712_flash_data); + ltq_register_wdt(); + ltq_register_pci(<q_pci_data); +} + +MIPS_MACHINE(LTQ_MACH_EASY50712, + "EASY50712", + "EASY50712 Eval Board", + easy50712_init); -- 1.7.2.3 From blogic@openwrt.org Thu Mar 3 11:06:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:06:29 +0100 (CET) Received: from nbd.name ([46.4.11.11]:57628 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491907Ab1CCKCh (ORCPT ); Thu, 3 Mar 2011 11:02:37 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: [PATCH V3 06/10] MIPS: lantiq: add NOR flash support Date: Thu, 3 Mar 2011 11:03:42 +0100 Message-Id: <1299146626-17428-7-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29331 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described in the PCI patch, the EBU is a little buggy, resulting in the upper and lower 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2) To work around this we do a addr^=2 during the probe. Once probed we adapt cfi->addr_unlock1 and cfi->addr_unlock2 to represent the endianess bug. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: David Woodhouse Cc: Daniel Schwierzeck Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org --- Changes in V2 * handle the endianess bug inside the map code and not in the generic cfi code * remove the addr swizzle patch Changes in V3 * whitespace * change __iomem void to void __iomem drivers/mtd/maps/Kconfig | 7 ++ drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq.c | 190 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/maps/lantiq.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 5d37d31..587468e 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -260,6 +260,13 @@ config MTD_BCM963XX Support for parsing CFE image tag and creating MTD partitions on Broadcom BCM63xx boards. +config MTD_LANTIQ + bool "Lantiq SoC NOR support" + depends on LANTIQ && MTD_PARTITIONS + help + Support for NOR flash chips on Lantiq SoC. The Chips are connected + to the SoCs EBU (External Bus Unit) + config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index c7869c7..bb2ce2f 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o obj-$(CONFIG_MTD_VMU) += vmu-flash.o obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o +obj-$(CONFIG_MTD_LANTIQ) += lantiq.o diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c new file mode 100644 index 0000000..674be0a --- /dev/null +++ b/drivers/mtd/maps/lantiq.c @@ -0,0 +1,190 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* the NOR flash is connected to the same external bus unit (EBU) as PCI + * to make PCI work we need to enable the endianess swapping of the addr + * written to the EBU. this however has some limitations and breaks when + * using NOR. it does not really matter if the onflash data is in a swapped + * order, however cfi sequences also fail. to workaround this we need to use + * a complex map. We essentially software swap all addresses during probe + * and then swizzle the unlock addresses. + */ +static int ltq_mtd_probing; + +static map_word +ltq_read16(struct map_info *map, unsigned long adr) +{ + unsigned long flags; + + map_word temp; + if (ltq_mtd_probing) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + temp.x[0] = *((__u16 *)(map->virt + adr)); + spin_unlock_irqrestore(&ebu_lock, flags); + return temp; +} + +static void +ltq_write16(struct map_info *map, map_word d, unsigned long adr) +{ + unsigned long flags; + + if (ltq_mtd_probing) + adr ^= 2; + spin_lock_irqsave(&ebu_lock, flags); + *((__u16 *)(map->virt + adr)) = d.x[0]; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +void +ltq_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + unsigned char *p; + unsigned char *to_8; + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + from = (unsigned long) (map->virt + from); + p = (unsigned char *) from; + to_8 = (unsigned char *) to; + while (len--) + *to_8++ = *p++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +void +ltq_copy_to(struct map_info *map, unsigned long to, + const void *from, ssize_t len) +{ + unsigned char *p = (unsigned char *)from; + unsigned char *to_8; + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + to += (unsigned long) map->virt; + to_8 = (unsigned char *)to; + while (len--) + *p++ = *to_8++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static const char *part_probe_types[] = { + "cmdlinepart", NULL }; + +static struct map_info ltq_map = { + .name = "ltq_nor", + .bankwidth = 2, + .read = ltq_read16, + .write = ltq_write16, + .copy_from = ltq_copy_from, + .copy_to = ltq_copy_to, +}; + +static int +ltq_mtd_probe(struct platform_device *pdev) +{ + struct physmap_flash_data *ltq_mtd_data = + (struct physmap_flash_data *) dev_get_platdata(&pdev->dev); + struct mtd_info *ltq_mtd = NULL; + struct mtd_partition *parts = NULL; + struct resource *res = 0; + int nr_parts = 0; + struct cfi_private *cfi; + +#ifdef CONFIG_SOC_TYPE_XWAY + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); +#endif + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource"); + return -ENOENT; + } + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request mem resource"); + return -EBUSY; + } + + ltq_map.phys = res->start; + ltq_map.size = resource_size(res); + ltq_map.virt = devm_ioremap_nocache(&pdev->dev, ltq_map.phys, + ltq_map.size); + if (!ltq_map.virt) { + dev_err(&pdev->dev, "failed to ioremap!\n"); + return -EIO; + } + + ltq_mtd_probing = 1; + ltq_mtd = (struct mtd_info *) do_map_probe("cfi_probe", <q_map); + ltq_mtd_probing = 0; + if (!ltq_mtd) { + iounmap(ltq_map.virt); + dev_err(&pdev->dev, "probing failed\n"); + return -ENXIO; + } + ltq_mtd->owner = THIS_MODULE; + + cfi = (struct cfi_private *)ltq_map.fldrv_priv; + cfi->addr_unlock1 ^= 1; + cfi->addr_unlock2 ^= 1; + + nr_parts = parse_mtd_partitions(ltq_mtd, part_probe_types, &parts, 0); + if (nr_parts > 0) { + dev_info(&pdev->dev, + "using %d partitions from cmdline", nr_parts); + } else { + nr_parts = ltq_mtd_data->nr_parts; + parts = ltq_mtd_data->parts; + } + + add_mtd_partitions(ltq_mtd, parts, nr_parts); + return 0; +} + +static struct platform_driver ltq_mtd_driver = { + .probe = ltq_mtd_probe, + .driver = { + .name = "ltq_nor", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_mtd(void) +{ + int ret = platform_driver_register(<q_mtd_driver); + + if (ret) + printk(KERN_INFO "ltq_nor: error registering platfom driver"); + return ret; +} + +module_init(init_ltq_mtd); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC NOR"); -- 1.7.2.3 From jamie@jamieiles.com Thu Mar 3 11:15:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:15:43 +0100 (CET) Received: from mail-ww0-f41.google.com ([74.125.82.41]:58526 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1CCKPk (ORCPT ); Thu, 3 Mar 2011 11:15:40 +0100 Received: by wwb29 with SMTP id 29so4978180wwb.0 for ; Thu, 03 Mar 2011 02:15:33 -0800 (PST) Received: by 10.216.155.205 with SMTP id j55mr391566wek.90.1299147333615; Thu, 03 Mar 2011 02:15:33 -0800 (PST) Received: from localhost (cpc3-chap8-2-0-cust205.aztw.cable.virginmedia.com [94.171.253.206]) by mx.google.com with ESMTPS id m6sm486383wej.34.2011.03.03.02.15.30 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 Mar 2011 02:15:32 -0800 (PST) Date: Thu, 3 Mar 2011 10:15:27 +0000 From: Jamie Iles To: Sergei Shtylyov Cc: John Crispin , Ralf Baechle , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support Message-ID: <20110303101527.GE2955@pulham.picochip.com> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> <4D6E286D.9050100@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D6E286D.9050100@mvista.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29332 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jamie@jamieiles.com Precedence: bulk X-list: linux-mips On Wed, Mar 02, 2011 at 02:22:21PM +0300, Sergei Shtylyov wrote: > >+static int > >+ltq_wdt_remove(struct platform_device *dev) > > __exit? No, I think this should be __devexit and the probe function should be __devinit. When assigning the exit function to the platform_driver it should be surrounded with __devexit_p(). Jamie From kale.pandurang@gmail.com Thu Mar 3 11:16:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:16:35 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:62942 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1CCKQc (ORCPT ); Thu, 3 Mar 2011 11:16:32 +0100 Received: by iyf40 with SMTP id 40so854134iyf.36 for ; Thu, 03 Mar 2011 02:16:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:date:message-id:subject:from:to :content-type; bh=qBcb6W07W/jq8EOIJXpNQnVOnfjQtzWBg1X+FsUt1ic=; b=tgCTz4Uw8medgoLPR5iORi9arzhhpwyliYpZpiDWNCANX1W5buI0Bije4d/Ier31+1 dCD8fAitjvDpm7bevWYqshYI31s2a7ctAyeVlXPOUd5jGgeyCXba+TTkdHC9zRDu5Uqr S65T0xta/lhTyUrxuVWwfI75oOkaShhJOHw84= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=glgMOVzCbrj99aIAIfwoON+uXfcua9ISsYmQIdnVsSfT1UkhwLZGTNOm8q2pqsxjxN s+HQDGhp78eOB91d0fHZpMfDZ/ZK9Yrl5pw0BOqAnYcXPQPWF14S9HYVYR8rluwpY8CD velhoUIpFjiaVa0tnm4TQNnCc0FWLgipq2VRw= MIME-Version: 1.0 Received: by 10.231.20.13 with SMTP id d13mr830365ibb.57.1299147385917; Thu, 03 Mar 2011 02:16:25 -0800 (PST) Received: by 10.231.183.20 with HTTP; Thu, 3 Mar 2011 02:16:25 -0800 (PST) Date: Thu, 3 Mar 2011 10:16:25 +0000 Message-ID: Subject: uboot for MIPS: need help to skip relocate uboot and start uboot from RAM From: Pandurang Kale To: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=00221532cb7872d53d049d91523c Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29333 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kale.pandurang@gmail.com Precedence: bulk X-list: linux-mips --00221532cb7872d53d049d91523c Content-Type: text/plain; charset=ISO-8859-1 Hello Everyone, We have MIPS based development board and I am trying to get the uboot up and running on it. We have a primary bootloader which check for the valid mod-image stored on the flash. This mod-image consist of header, uboot and linux kernel. Depending on the recent, active and stable imagethe primary bootloader first copies the uboot image. and later on we would copy the kernel image from uboot. But when primary bootloader copies the uboot image to the RAM and passes the control to the uboot, uboot (MIPS version of start.S and arch/mips/lib/borad.c) tries to relocate the already copied image from RAM (the primary bootloader copied it to start of the RAM+1MB address) to top of the RAM (0x87fc0000) region thinking that the uboot image is stored in flash. All I need to do is skip the uboot relocate code in MIPS version of uboot startup as the primary bootloader has already relocated the uboot from Flash to RAM and set up the stack pointer and other global data appropriately, which it does after relocation. I can see there is a switch for ARM processor, CONFIG_SKIP_RELOCATE_UBOOT, which skips the relocation of uboot code and tries to run the uboot from RAM. I cannot see a similar switch implemented for MIPS and didnt find any related thread anywhere in mailing list or on net. Do we have similar ARM like switch to SKIP the RELOCATION? If not has anyone done this before? I would really appreciate if you can guide me to overcome this issue to run the uboot cleanly skipping the relocation. Thanks in advance, Pandu --00221532cb7872d53d049d91523c Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Hello Everyone,

We have MIPS based development board and I am trying= to get the uboot up and running on it.
We have a primary bootloader whi= ch check for the valid mod-image stored on the flash. This mod-image consis= t of header, uboot and linux kernel.
Depending on the recent, active and stable imagethe primary bootloader firs= t copies the uboot image. and later on we would copy the kernel image from = uboot.

But when primary bootloader copies the uboot image to the RAM= and passes the control to the uboot, uboot (MIPS version of start.S and ar= ch/mips/lib/borad.c) tries to relocate the
already copied image from RAM (the primary bootloader copied it to start of= the RAM+1MB address) to top of the RAM (0x87fc0000) region thinking that t= he uboot image is stored in flash.

All I need to do is skip the uboo= t relocate code in MIPS version of uboot startup as the primary bootloader = has already relocated the uboot from Flash to RAM and set up the stack poin= ter and other global data appropriately, which it does after relocation. I can see there is a switch for ARM processor, CONFIG_SKIP_RELOCATE_UBOOT, = which skips the relocation of uboot code and tries to run the uboot from RA= M. I
cannot see a similar switch implemented for MIPS and didnt find any= related thread anywhere in mailing list or on net.

Do we have similar ARM like switch to SKIP the RELOCATION? If not has a= nyone done this before?

I would really appreciate if you can guide m= e to overcome this issue to run the uboot cleanly skipping the relocation.<= br>
Thanks in advance,
Pandu
--00221532cb7872d53d049d91523c-- From blogic@openwrt.org Thu Mar 3 11:16:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 11:17:03 +0100 (CET) Received: from nbd.name ([46.4.11.11]:49391 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491907Ab1CCKQw (ORCPT ); Thu, 3 Mar 2011 11:16:52 +0100 From: John Crispin To: Ralf Baechle Cc: John Crispin , Ralph Hempel , linux-mips@linux-mips.org Subject: [PATCH V3 10/10] MIPS: lantiq: add more gpio drivers Date: Thu, 3 Mar 2011 11:03:46 +0100 Message-Id: <1299146626-17428-11-git-send-email-blogic@openwrt.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299146626-17428-1-git-send-email-blogic@openwrt.org> References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29334 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips The XWAY family allows to extend the number of gpios by using shift registers or latches. This patch adds the 2 drivers needed for this. The extended gpios are output only. Signed-off-by: John Crispin Signed-off-by: Ralph Hempel Cc: linux-mips@linux-mips.org --- Added in V2 Changes in V3 * whitespace * change __iomem void to void __iomem * multiline comments * use pr_* macros instead of printk arch/mips/lantiq/xway/Makefile | 2 +- arch/mips/lantiq/xway/gpio_ebu.c | 126 ++++++++++++++++++++++++++++++ arch/mips/lantiq/xway/gpio_stp.c | 158 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 285 insertions(+), 1 deletions(-) create mode 100644 arch/mips/lantiq/xway/gpio_ebu.c create mode 100644 arch/mips/lantiq/xway/gpio_stp.c diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile index 08dcc10..a021def 100644 --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -1,4 +1,4 @@ -obj-y := pmu.o ebu.o reset.o gpio.o devices.o +obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c new file mode 100644 index 0000000..a3ae6b8 --- /dev/null +++ b/arch/mips/lantiq/xway/gpio_ebu.c @@ -0,0 +1,126 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* By attaching hardware latches to the EBU it is possible to create output + * only gpios. This driver configures a special memory address, which when + * written to outputs 16 bit to the latches. + */ + +#define LTQ_EBU_BUSCON 0x1e7ff /* 16 bit access, slowest timing */ +#define LTQ_EBU_WP 0x80000000 /* write protect bit */ + +/* we keep a ltq_ebu_gpio_shadow value of the last value written to the ebu */ +static int ltq_ebu_gpio_shadow = 0x0; +static void __iomem *ltq_ebu_gpio_membase; + +static void +ltq_ebu_apply(void) +{ + unsigned long flags; + + spin_lock_irqsave(&ebu_lock, flags); + ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1); + *((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow; + ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1); + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static void +ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value) +{ + if (value) + ltq_ebu_gpio_shadow |= (1 << offset); + else + ltq_ebu_gpio_shadow &= ~(1 << offset); + ltq_ebu_apply(); +} + +static int +ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + ltq_ebu_set(chip, offset, value); + return 0; +} + +static struct gpio_chip +ltq_ebu_chip = { + .label = "ltq_ebu", + .direction_output = ltq_ebu_direction_output, + .set = ltq_ebu_set, + .base = 72, + .ngpio = 16, + .can_sleep = 1, + .owner = THIS_MODULE, +}; + +static int __devinit +ltq_ebu_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource\n"); + return -ENOENT; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + return -EBUSY; + } + + ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ltq_ebu_gpio_membase) { + dev_err(&pdev->dev, "Failed to ioremap mem region\n"); + return -ENOMEM; + } + + /* grab the default shadow value passed form the platform code */ + ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data; + + /* tell the ebu controller which mem addr we will be using */ + ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1); + + /* write protect the region */ + ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1); + + ret = gpiochip_add(<q_ebu_chip); + if (!ret) + ltq_ebu_apply(); + return ret; +} + +static struct platform_driver +ltq_ebu_driver = { + .probe = ltq_ebu_probe, + .driver = { + .name = "ltq_ebu", + .owner = THIS_MODULE, + }, +}; + +static int __init +ltq_ebu_init(void) +{ + return platform_driver_register(<q_ebu_driver); +} + +postcore_initcall(ltq_ebu_init); diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c new file mode 100644 index 0000000..f0f4e68 --- /dev/null +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -0,0 +1,158 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2007 John Crispin + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LTQ_STP_CON0 0x00 +#define LTQ_STP_CON1 0x04 +#define LTQ_STP_CPU0 0x08 +#define LTQ_STP_CPU1 0x0C +#define LTQ_STP_AR 0x10 + +#define STP_CON0_SWU (1 << 31) +#define LTQ_STP_2HZ (0) +#define LTQ_STP_4HZ (1 << 23) +#define LTQ_STP_8HZ (2 << 23) +#define LTQ_STP_10HZ (3 << 23) +#define LTQ_STP_MASK (0xf << 23) +#define LTQ_STP_UPD_SRC_FPI (1 << 31) +#define LTQ_STP_UPD_MASK (3 << 30) +#define LTQ_STP_ADSL_SRC (3 << 24) + +#define LTQ_STP_GROUP0 (1 << 0) + +#define LTQ_STP_RISING 0 +#define LTQ_STP_FALLING (1 << 26) +#define LTQ_STP_EDGE_MASK (1 << 26) + +#define ltq_stp_r32(reg) __raw_readl(ltq_stp_membase + reg) +#define ltq_stp_w32(val, reg) __raw_writel(val, ltq_stp_membase + reg) +#define ltq_stp_w32_mask(clear, set, reg) \ + ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \ + ltq_stp_membase + (reg)) + +static int ltq_stp_shadow = 0xffff; +static void __iomem *ltq_stp_membase; + +static void +ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value) +{ + if (value) + ltq_stp_shadow |= (1 << offset); + else + ltq_stp_shadow &= ~(1 << offset); + ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0); +} + +static int +ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + ltq_stp_set(chip, offset, value); + return 0; +} + +static struct gpio_chip ltq_stp_chip = { + .label = "ltq_stp", + .direction_output = ltq_stp_direction_output, + .set = ltq_stp_set, + .base = 48, + .ngpio = 24, + .can_sleep = 1, + .owner = THIS_MODULE, +}; + +static int +ltq_stp_hw_init(void) +{ + /* the 3 pins used to control the external stp */ + ltq_gpio_request(4, 1, 0, 1, "stp-st"); + ltq_gpio_request(5, 1, 0, 1, "stp-d"); + ltq_gpio_request(6, 1, 0, 1, "stp-sh"); + + /* sane defaults */ + ltq_stp_w32(0, LTQ_STP_AR); + ltq_stp_w32(0, LTQ_STP_CPU0); + ltq_stp_w32(0, LTQ_STP_CPU1); + ltq_stp_w32(STP_CON0_SWU, LTQ_STP_CON0); + ltq_stp_w32(0, LTQ_STP_CON1); + + /* rising or falling edge */ + ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0); + + /* per default stp 15-0 are set */ + ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1); + + /* stp are update periodically by the FPID */ + ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_SRC_FPI, LTQ_STP_CON1); + + /* set stp update speed */ + ltq_stp_w32_mask(LTQ_STP_MASK, LTQ_STP_8HZ, LTQ_STP_CON1); + + /* adsl 0 and 1 stp are updated by the arc */ + ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0); + + ltq_pmu_enable(PMU_LED); + return 0; +} + +static int +ltq_stp_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + int ret = 0; + + if (!res) + return -ENOENT; + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request STP memory\n"); + return -EBUSY; + } + ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!ltq_stp_membase) { + dev_err(&pdev->dev, "failed to remap STP memory\n"); + return -ENOMEM; + } + ret = gpiochip_add(<q_stp_chip); + if (!ret) + ret = ltq_stp_hw_init(); + + return ret; +} + +static struct platform_driver ltq_stp_driver = { + .probe = ltq_stp_probe, + .driver = { + .name = "ltq_stp", + .owner = THIS_MODULE, + }, +}; + +int __init +ltq_stp_init(void) +{ + int ret = platform_driver_register(<q_stp_driver); + + if (ret) + pr_info("ltq_stp: error registering platfom driver"); + return ret; +} + +postcore_initcall(ltq_stp_init); -- 1.7.2.3 From sshtylyov@mvista.com Thu Mar 3 12:22:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 12:22:37 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:54316 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491042Ab1CCLWe (ORCPT ); Thu, 3 Mar 2011 12:22:34 +0100 Received: by bwz1 with SMTP id 1so1092505bwz.36 for ; Thu, 03 Mar 2011 03:22:26 -0800 (PST) Received: by 10.204.23.15 with SMTP id p15mr1301653bkb.108.1299151346022; Thu, 03 Mar 2011 03:22:26 -0800 (PST) Received: from [192.168.2.2] ([91.79.88.81]) by mx.google.com with ESMTPS id w3sm668170bkt.5.2011.03.03.03.22.23 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 Mar 2011 03:22:24 -0800 (PST) Message-ID: <4D6F79A0.6050903@mvista.com> Date: Thu, 03 Mar 2011 14:21:04 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.14) Gecko/20110221 Thunderbird/3.1.8 MIME-Version: 1.0 To: Jamie Iles CC: John Crispin , Ralf Baechle , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V2 05/10] MIPS: lantiq: add watchdog support References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-6-git-send-email-blogic@openwrt.org> <4D6E286D.9050100@mvista.com> <20110303101527.GE2955@pulham.picochip.com> In-Reply-To: <20110303101527.GE2955@pulham.picochip.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29335 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 03-03-2011 13:15, Jamie Iles wrote: >>> +static int >>> +ltq_wdt_remove(struct platform_device *dev) >> __exit? > No, I think this should be __devexit and the probe function should be > __devinit. When assigning the exit function to the platform_driver it > should be surrounded with __devexit_p(). Why? Is WDT really a hotplug device? > Jamie WBR, Sergei From sshtylyov@mvista.com Thu Mar 3 12:45:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 12:45:58 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:56175 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491044Ab1CCLpz (ORCPT ); Thu, 3 Mar 2011 12:45:55 +0100 Received: by bwz1 with SMTP id 1so1107397bwz.36 for ; Thu, 03 Mar 2011 03:45:49 -0800 (PST) Received: by 10.204.80.161 with SMTP id t33mr1339818bkk.121.1299152749491; Thu, 03 Mar 2011 03:45:49 -0800 (PST) Received: from [192.168.2.2] ([91.79.88.81]) by mx.google.com with ESMTPS id f20sm683888bkf.4.2011.03.03.03.45.47 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 Mar 2011 03:45:48 -0800 (PST) Message-ID: <4D6F7F1C.5040001@mvista.com> Date: Thu, 03 Mar 2011 14:44:28 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.14) Gecko/20110221 Thunderbird/3.1.8 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V3 05/10] MIPS: lantiq: add watchdog support References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> <1299146626-17428-6-git-send-email-blogic@openwrt.org> In-Reply-To: <1299146626-17428-6-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29336 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 03-03-2011 13:03, John Crispin wrote: > This patch adds the driver for the watchdog found inside the Lantiq SoC family. > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel > Cc: Wim Van Sebroeck > Cc: linux-mips@linux-mips.org > Cc: linux-watchdog@vger.kernel.org [...] > diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c > new file mode 100644 > index 0000000..d49ddaa > --- /dev/null > +++ b/drivers/watchdog/lantiq_wdt.c > @@ -0,0 +1,235 @@ [...] > +static void > +ltq_wdt_disable(void) > +{ > +#ifndef CONFIG_WATCHDOG_NOWAYOUT > + ltq_wdt_ok_to_close = 0; > +#endif > + /* write the first paswword magic */ ^ You still didn't fix the typo here. :-) > + ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR); > + /* write the second paswword magic with no config ^ And here... > +static int > +ltq_wdt_probe(struct platform_device *pdev) Should be __init now that you're using platform_driver_probe()... > + /* we do not need to enable the clock as it is always running */ > + clk = clk_get(&pdev->dev, "io"); > + if (!clk) > + BUG(); BUG_ON(!clk); > +static struct platform_driver ltq_wdt_driver = { > + .probe = ltq_wdt_probe, No need to initialize it now that you're using platform_driver_probe()... > + .remove = ltq_wdt_remove, Shouldn't 'ltq_wdt_remove' be enclosed in __exit_p()? WBR, Sergei From blogic@openwrt.org Thu Mar 3 12:57:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 12:57:39 +0100 (CET) Received: from nbd.name ([46.4.11.11]:55216 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491076Ab1CCL5g (ORCPT ); Thu, 3 Mar 2011 12:57:36 +0100 Message-ID: <4D6F827B.8040902@openwrt.org> Date: Thu, 03 Mar 2011 12:58:51 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , Ralph Hempel , Wim Van Sebroeck , linux-mips@linux-mips.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH V3 05/10] MIPS: lantiq: add watchdog support References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> <1299146626-17428-6-git-send-email-blogic@openwrt.org> <4D6F7F1C.5040001@mvista.com> In-Reply-To: <4D6F7F1C.5040001@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29337 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips >> + /* write the first paswword magic */ > ^ > You still didn't fix the typo here. :-) > Hi, grml... changed it in the wrong folder :) i'll add it for the V4 thanks, John From raydudu@gmail.com Thu Mar 3 13:46:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 13:46:49 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:48949 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1CCMqq (ORCPT ); Thu, 3 Mar 2011 13:46:46 +0100 Received: by fxm16 with SMTP id 16so1130983fxm.36 for ; Thu, 03 Mar 2011 04:46:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:from:user-agent:mime-version:to :subject:references:in-reply-to:content-type :content-transfer-encoding; bh=TzkMwUH63BrQOIU3zD+H+AbqVBXpDXAgIVVf67NrL8U=; b=wKxjgIgLpPkecn84h547qCUI582DLGgxFnRC/gXW0w58zRioSWiI190mFQESHKQDKW i0CRnOnjEppqORm3HagrLEcgfv2QQPYMIUeM3d9kKMsg0Ffbv9UcNDkJznYayGpXpaPN xQ/idHUQyFASf2UZve7ir5o2TGhYIFxaj+KVY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:subject:references :in-reply-to:content-type:content-transfer-encoding; b=Cq41dS+oVrQE5uamwlVOnTFNimwZS+g0hKOqxumPLKmtVUZLUAr8e9pzEhVSy0s/Uc EN0lr4RBUVnOeep2jA9wf0aixm0jPGNeuYja6FyilVdrrYDMA7Klwl1nfTJM2ruShwFJ +79iC4vST8kEsG5fM8O9z2DDb5rDlcDzTkpfc= Received: by 10.223.70.142 with SMTP id d14mr1400341faj.110.1299156399788; Thu, 03 Mar 2011 04:46:39 -0800 (PST) Received: from [192.168.23.19] ([193.105.30.100]) by mx.google.com with ESMTPS id 17sm545165far.19.2011.03.03.04.46.37 (version=SSLv3 cipher=OTHER); Thu, 03 Mar 2011 04:46:38 -0800 (PST) Message-ID: <4D6F8DAC.20807@gmail.com> Date: Thu, 03 Mar 2011 14:46:36 +0200 From: Ray Dudu User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101220 Lightning/1.0b3pre Thunderbird/3.1.7 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: uboot for MIPS: need help to skip relocate uboot and start uboot from RAM References: In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29338 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raydudu@gmail.com Precedence: bulk X-list: linux-mips Hi, I'm not so familira with uboot, however, I done proprietary booter implementation for my company. Similar functionality was required, for different purposes actually, but it doesn't change the idea. So in my booter code I done simple check of code location. In case when the code detects that it is already in RAM, it skips memory/caches initialization and self coping. Some useful pieces of code: Supporting function. ------CUT-HERE-------- LEAF(set_ra) jr ra nop END(set_ra) ------CUT-HERE-------- Actually the check: ------CUT-HERE-------- bal set_ra /* first get the current program counter */ nop move t0, ra li t1, 0x10000000 and t1, t1, t0 bne zero, t1, 1f /* code in ROM/flash */ nop li s3,0 /* code in RAM */ b 2f nop 1: /* jump to system initialization and code coping routine here */ 2: /* continue normal boot */ ------CUT-HERE-------- I suppose you can do similar in u-boot and it will be quite generic solution. Such code can be executed from RAM and FLASH without need to reconfigure and rebuild. 03.03.11 12:16, Pandurang Kale написав(ла): > Hello Everyone, > > We have MIPS based development board and I am trying to get the uboot up > and running on it. > We have a primary bootloader which check for the valid mod-image stored > on the flash. This mod-image consist of header, uboot and linux kernel. > Depending on the recent, active and stable imagethe primary bootloader > first copies the uboot image. and later on we would copy the kernel > image from uboot. > > But when primary bootloader copies the uboot image to the RAM and passes > the control to the uboot, uboot (MIPS version of start.S and > arch/mips/lib/borad.c) tries to relocate the > already copied image from RAM (the primary bootloader copied it to start > of the RAM+1MB address) to top of the RAM (0x87fc0000) region thinking > that the uboot image is stored in flash. > > All I need to do is skip the uboot relocate code in MIPS version of > uboot startup as the primary bootloader has already relocated the uboot > from Flash to RAM and set up the stack pointer and other global data > appropriately, which it does after relocation. > I can see there is a switch for ARM processor, > CONFIG_SKIP_RELOCATE_UBOOT, which skips the relocation of uboot code and > tries to run the uboot from RAM. I > cannot see a similar switch implemented for MIPS and didnt find any > related thread anywhere in mailing list or on net. > > Do we have similar ARM like switch to SKIP the RELOCATION? If not has > anyone done this before? > > I would really appreciate if you can guide me to overcome this issue to > run the uboot cleanly skipping the relocation. > > Thanks in advance, > Pandu -- Best regards, RD18-UANIC From sshtylyov@mvista.com Thu Mar 3 13:52:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 13:52:24 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:48888 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1CCMwS (ORCPT ); Thu, 3 Mar 2011 13:52:18 +0100 Received: by bwz1 with SMTP id 1so1154054bwz.36 for ; Thu, 03 Mar 2011 04:52:12 -0800 (PST) Received: by 10.204.81.72 with SMTP id w8mr1369673bkk.205.1299156732660; Thu, 03 Mar 2011 04:52:12 -0800 (PST) Received: from [192.168.2.2] ([91.79.88.81]) by mx.google.com with ESMTPS id d17sm723778bkd.13.2011.03.03.04.52.10 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 Mar 2011 04:52:11 -0800 (PST) Message-ID: <4D6F8EAB.2030306@mvista.com> Date: Thu, 03 Mar 2011 15:50:51 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.14) Gecko/20110221 Thunderbird/3.1.8 MIME-Version: 1.0 To: Pandurang Kale CC: linux-mips@linux-mips.org Subject: Re: uboot for MIPS: need help to skip relocate uboot and start uboot from RAM References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29339 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 03-03-2011 13:16, Pandurang Kale wrote: > We have MIPS based development board and I am trying to get the uboot up and > running on it. There's U-Boot mailing list (u-boot@lists.denx.de), why don't you ask there instead? > Thanks in advance, > Pandu WBR, Sergei From yad.naveen@gmail.com Thu Mar 3 14:07:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 14:07:55 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:48899 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491870Ab1CCNHu (ORCPT ); Thu, 3 Mar 2011 14:07:50 +0100 Received: by vws7 with SMTP id 7so982452vws.36 for ; Thu, 03 Mar 2011 05:07:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:date:message-id:subject:from:to :content-type; bh=rt/LLtR5/j2rftoW0h6pjM4pzLkQOq7B0UfzqHYT6EQ=; b=DFLuiahnVViwVPuVn9IEGYOlVnI/BkAat/9k38jSCK8fO/dRctc08iry4O8P0DBCvt OeaYbvT0B2AKsBpyMncuGneG7dh1GhzhYqgf4Cz7pYk7fIdtMmN0Bu/C2fGamKBkvFNO 5Jn/sQ9WmCtfKsJELapa8bil1NH4UO3MyV/C4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=EAhNp8bZNw3AbxCszS2TR+D/Tf1LWnSQ76CDPAwb2p1I8UTZRjwHNVwDaZkelxDrFO zp+dUCmdIjAMYC8CY/mbZL7eYqbnnRJpZQF3rJQFmklkmdgFVd72lrs/MUluKB7T3prR gzVtEnqBGWHWegGyPT6AvKZ52CDgXbLIsqmBU= MIME-Version: 1.0 Received: by 10.52.70.82 with SMTP id k18mr1671531vdu.194.1299157355389; Thu, 03 Mar 2011 05:02:35 -0800 (PST) Received: by 10.52.158.71 with HTTP; Thu, 3 Mar 2011 05:02:35 -0800 (PST) Date: Thu, 3 Mar 2011 18:32:35 +0530 Message-ID: Subject: Memory Compaction feature. From: naveen yadav To: kernelnewbies@nl.linux.org, linux-mips@linux-mips.org, linux-arm-kernel-request@lists.arm.linux.org.uk Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29340 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Hi All, I want clarification is anybody verify this feature on ARM or MIPS architecture. http://lwn.net/Articles/381677/ Kind regards From ralf@linux-mips.org Thu Mar 3 17:47:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Mar 2011 17:48:06 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:52060 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491891Ab1CCQr7 (ORCPT ); Thu, 3 Mar 2011 17:47:59 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p23Glfhn004740; Thu, 3 Mar 2011 17:47:41 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p23GlcSx004736; Thu, 3 Mar 2011 17:47:38 +0100 Date: Thu, 3 Mar 2011 17:47:38 +0100 From: Ralf Baechle To: naveen yadav Cc: kernelnewbies@nl.linux.org, linux-mips@linux-mips.org, linux-arm-kernel@lists.infradead.org Subject: Re: Memory Compaction feature. Message-ID: <20110303164738.GA3863@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29341 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Mar 03, 2011 at 06:32:35PM +0530, naveen yadav wrote: [I changed the bogus linux-arm-kernel-request@lists.arm.linux.org.uk address to linux-arm-kernel@lists.infradead.org. I have no idea where people keep pulling out -request addresses.] > I want clarification is anybody verify this feature on ARM or MIPS architecture. > > http://lwn.net/Articles/381677/ This got merged for 2.6.35 and as it doesn't tinker with architecture specific code I assume it should just work on all architectures. However I have no reports of success or failure on MIPS. Ralf From sshtylyov@mvista.com Fri Mar 4 13:42:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 13:42:46 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:39443 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491784Ab1CDMmn (ORCPT ); Fri, 4 Mar 2011 13:42:43 +0100 Received: by bwz1 with SMTP id 1so2113140bwz.36 for ; Fri, 04 Mar 2011 04:42:36 -0800 (PST) Received: by 10.204.48.33 with SMTP id p33mr510497bkf.153.1299242555856; Fri, 04 Mar 2011 04:42:35 -0800 (PST) Received: from [192.168.2.2] ([91.79.86.215]) by mx.google.com with ESMTPS id x6sm1522166bkv.0.2011.03.04.04.42.33 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 04:42:34 -0800 (PST) Message-ID: <4D70DDEA.2050308@mvista.com> Date: Fri, 04 Mar 2011 15:41:14 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.14) Gecko/20110221 Thunderbird/3.1.8 MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH V3 06/10] MIPS: lantiq: add NOR flash support References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> <1299146626-17428-7-git-send-email-blogic@openwrt.org> In-Reply-To: <1299146626-17428-7-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29342 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 03-03-2011 13:03, John Crispin wrote: > NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described > in the PCI patch, the EBU is a little buggy, resulting in the upper and lower > 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2) "Are" not needed. > To work around this we do a addr^=2 during the probe. Once probed we adapt > cfi->addr_unlock1 and cfi->addr_unlock2 to represent the endianess bug. > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel > Cc: David Woodhouse > Cc: Daniel Schwierzeck > Cc: linux-mips@linux-mips.org > Cc: linux-mtd@lists.infradead.org [...] > diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig > index 5d37d31..587468e 100644 > --- a/drivers/mtd/maps/Kconfig > +++ b/drivers/mtd/maps/Kconfig > @@ -260,6 +260,13 @@ config MTD_BCM963XX > Support for parsing CFE image tag and creating MTD partitions on > Broadcom BCM63xx boards. > > +config MTD_LANTIQ > + bool "Lantiq SoC NOR support" > + depends on LANTIQ && MTD_PARTITIONS Maybe you should select MTD_PARTITIONS instead? [...] > diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c > new file mode 100644 > index 0000000..674be0a > --- /dev/null > +++ b/drivers/mtd/maps/lantiq.c > @@ -0,0 +1,190 @@ > +/* > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + * > + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE > + * Copyright (C) 2010 John Crispin > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +/* the NOR flash is connected to the same external bus unit (EBU) as PCI Period at end of statment missing? > + * to make PCI work we need to enable the endianess swapping of the addr > + * written to the EBU. this however has some limitations and breaks when > + * using NOR. it does not really matter if the onflash data is in a swapped > + * order, however cfi sequences also fail. to workaround this we need to use > + * a complex map. We essentially software swap all addresses during probe > + * and then swizzle the unlock addresses. > + */ > +static int ltq_mtd_probing; > + > +static map_word > +ltq_read16(struct map_info *map, unsigned long adr) > +{ > + unsigned long flags; > + > + map_word temp; Empty line should be here, not above. > + if (ltq_mtd_probing) > + adr ^= 2; > + spin_lock_irqsave(&ebu_lock, flags); > + temp.x[0] = *((__u16 *)(map->virt + adr)); > + spin_unlock_irqrestore(&ebu_lock, flags); Hm, what does this lock gain, if the read is atomic anyway? > +void > +ltq_copy_from(struct map_info *map, void *to, > + unsigned long from, ssize_t len) Shouldn't it be static? > +{ > + unsigned char *p; > + unsigned char *to_8; > + unsigned long flags; > + > + spin_lock_irqsave(&ebu_lock, flags); > + from = (unsigned long) (map->virt + from); Why not: from += (unsigned long) map->virt; like you do in ltq_copy_to()? > + p = (unsigned char *) from; Could be done in initializer, like in ltq_copy_to(). > + to_8 = (unsigned char *) to; > + while (len--) > + *to_8++ = *p++; BTW, you could use memcpy_fromio(). > + spin_unlock_irqrestore(&ebu_lock, flags); > +} > + > +void > +ltq_copy_to(struct map_info *map, unsigned long to, > + const void *from, ssize_t len) Shouldn't it be static? > +{ > + unsigned char *p = (unsigned char *)from; > + unsigned char *to_8; > + unsigned long flags; > + > + spin_lock_irqsave(&ebu_lock, flags); > + to += (unsigned long) map->virt; > + to_8 = (unsigned char *)to; > + while (len--) > + *p++ = *to_8++; I think you have this backwards. It should be: *to_8++ = *p++; BTW, you could use memcpy_toio(). > + spin_unlock_irqrestore(&ebu_lock, flags); > +} [...] > +static int > +ltq_mtd_probe(struct platform_device *pdev) > +{ > + struct physmap_flash_data *ltq_mtd_data = > + (struct physmap_flash_data *) dev_get_platdata(&pdev->dev); Cast from 'void *' is automatic -- no need for explicit one. > +#ifdef CONFIG_SOC_TYPE_XWAY > + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); > +#endif Hm, can't you do this in the platform code? > + ltq_map.phys = res->start; > + ltq_map.size = resource_size(res); > + ltq_map.virt = devm_ioremap_nocache(&pdev->dev, ltq_map.phys, > + ltq_map.size); Hm, could you indent the last line more to the right? > + if (!ltq_map.virt) { > + dev_err(&pdev->dev, "failed to ioremap!\n"); > + return -EIO; > + } > + > + ltq_mtd_probing = 1; > + ltq_mtd = (struct mtd_info *) do_map_probe("cfi_probe",<q_map); do_map_probe() already returns that type, why cast to it? > + ltq_mtd_probing = 0; > + if (!ltq_mtd) { > + iounmap(ltq_map.virt); > + dev_err(&pdev->dev, "probing failed\n"); > + return -ENXIO; > + } > + ltq_mtd->owner = THIS_MODULE; > + > + cfi = (struct cfi_private *)ltq_map.fldrv_priv; Cast from 'void *' is automatic -- no need for explicit one. > +int __init > +init_ltq_mtd(void) > +{ > + int ret = platform_driver_register(<q_mtd_driver); Use platform_driver_probe() instead, as the device is not a hotplug one. Then ltq_mtd_probe() can become '__init'. WBR, Sergei From sshtylyov@mvista.com Fri Mar 4 16:12:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 16:12:16 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:33903 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491154Ab1CDPMN (ORCPT ); Fri, 4 Mar 2011 16:12:13 +0100 Received: by bwz1 with SMTP id 1so2235555bwz.36 for ; Fri, 04 Mar 2011 07:12:03 -0800 (PST) Received: by 10.204.233.15 with SMTP id jw15mr684226bkb.48.1299251523453; Fri, 04 Mar 2011 07:12:03 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id b16sm1621228bkw.2.2011.03.04.07.12.01 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 07:12:02 -0800 (PST) Message-ID: <4D7100E8.101@mvista.com> Date: Fri, 04 Mar 2011 18:10:32 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: John Crispin CC: Ralf Baechle , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH V3 06/10] MIPS: lantiq: add NOR flash support References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> <1299146626-17428-7-git-send-email-blogic@openwrt.org> <4D70DDEA.2050308@mvista.com> In-Reply-To: <4D70DDEA.2050308@mvista.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29343 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips I wrote: >> NOR flash is attached to the same EBU (External Bus Unit) as PCI. As >> described >> in the PCI patch, the EBU is a little buggy, resulting in the upper >> and lower >> 16 bit of the data on a 32 bit read are swapped. (essentially we have >> a addr^=2) > "Are" not needed. >> To work around this we do a addr^=2 during the probe. Once probed we >> adapt >> cfi->addr_unlock1 and cfi->addr_unlock2 to represent the endianess bug. >> Signed-off-by: John Crispin >> Signed-off-by: Ralph Hempel >> Cc: David Woodhouse >> Cc: Daniel Schwierzeck >> Cc: linux-mips@linux-mips.org >> Cc: linux-mtd@lists.infradead.org > [...] >> diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c >> new file mode 100644 >> index 0000000..674be0a >> --- /dev/null >> +++ b/drivers/mtd/maps/lantiq.c >> @@ -0,0 +1,190 @@ [...] >> +void >> +ltq_copy_from(struct map_info *map, void *to, > > + unsigned long from, ssize_t len) > Shouldn't it be static? >> +{ >> + unsigned char *p; >> + unsigned char *to_8; >> + unsigned long flags; >> + >> + spin_lock_irqsave(&ebu_lock, flags); >> + from = (unsigned long) (map->virt + from); > Why not: > from += (unsigned long) map->virt; > like you do in ltq_copy_to()? >> + p = (unsigned char *) from; > Could be done in initializer, like in ltq_copy_to(). >> + to_8 = (unsigned char *) to; >> + while (len--) >> + *to_8++ = *p++; > BTW, you could use memcpy_fromio(). Actually not, as on MIPS it's implemented via memcpy(). On ARM it doesn byte-by-byte copying -- that's why I remembered about it... WBR, Sergei From ralf@linux-mips.org Fri Mar 4 16:49:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 16:49:41 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:49353 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491800Ab1CDPth (ORCPT ); Fri, 4 Mar 2011 16:49:37 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p24FnFSr026722; Fri, 4 Mar 2011 16:49:15 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p24FnCX3026719; Fri, 4 Mar 2011 16:49:12 +0100 Date: Fri, 4 Mar 2011 16:49:12 +0100 From: Ralf Baechle To: Lars-Peter Clausen Cc: Maurus Cuelenaere , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: Jz4740: Add HAVE_CLK Message-ID: <20110304154912.GA24966@linux-mips.org> References: <4d6c2da3.cc7e0e0a.2116.ffffde18@mx.google.com> <4D6CB9C4.8000609@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D6CB9C4.8000609@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29344 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Mar 01, 2011 at 10:17:56AM +0100, Lars-Peter Clausen wrote: > On 03/01/2011 12:20 AM, Maurus Cuelenaere wrote: > > Jz4740 supports the clock framework but doesn't have HAVE_CLK defined, so define > > it! > > > > Signed-off-by: Maurus Cuelenaere > > Acked-by: Lars-Peter Clausen Thanks folks. Applied, Ralf From ralf@linux-mips.org Fri Mar 4 17:13:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 17:13:40 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:60723 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491800Ab1CDQNh (ORCPT ); Fri, 4 Mar 2011 17:13:37 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p24GDF1Y028989; Fri, 4 Mar 2011 17:13:16 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p24GDFu1028987; Fri, 4 Mar 2011 17:13:15 +0100 Date: Fri, 4 Mar 2011 17:13:15 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MTX-1: make au1000_eth probes all PHY addresses Message-ID: <20110304161315.GB24966@linux-mips.org> References: <201102271953.54065.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201102271953.54065.florian@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29345 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Feb 27, 2011 at 07:53:53PM +0100, Florian Fainelli wrote: > From: Florian Fainelli > > When au1000_eth probes the MII bus for PHY address, if we do not set au1000_eth > platform data's phy_search_highest_address, the MII probing logic will exit > early and will assume a valid PHY is found at address 0. For MTX-1, the PHY is > at address 31, and without this patch, the link detection/speed/duplex would not > work correctly. > > CC: stable@kernel.org > Signed-off-by: Florian Fainelli > --- > Stable: 2.6.34+ Thanks, applied to 2.6.34+. Note that while you added a CC stable@kernel.org that address was not actually on the mail's cc list! Ralf From David.Daney@caviumnetworks.com Fri Mar 4 20:42:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:42:47 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11797 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491984Ab1CDTmo (ORCPT ); Fri, 4 Mar 2011 20:42:44 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:36 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:42 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:42 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24Jgdai017335; Fri, 4 Mar 2011 11:42:39 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgcR4017334; Fri, 4 Mar 2011 11:42:38 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 03/12] of: Make of_find_node_by_path() traverse /aliases for relative paths. Date: Fri, 4 Mar 2011 11:42:15 -0800 Message-Id: <1299267744-17278-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:42.0403 (UTC) FILETIME=[53B4A330:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29346 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Currently all paths passed to of_find_node_by_path() must begin with a '/', indicating a full path to the desired node. Augment the look-up code so that if a path does *not* begin with '/', the path is used as the name of an /aliases property. The value of this alias is then used as the full node path to be found. Signed-off-by: David Daney --- This patch is unchanged from the previous version I send separately. I have not forgotten about Grant's feedback, just deferred it to the next version. drivers/of/base.c | 24 +++++++++++++++++++++++- 1 files changed, 23 insertions(+), 1 deletions(-) diff --git a/drivers/of/base.c b/drivers/of/base.c index 710b53b..e63da9c 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -340,7 +340,10 @@ EXPORT_SYMBOL(of_get_next_child); /** * of_find_node_by_path - Find a node matching a full OF path - * @path: The full path to match + * @path: Either the full path to match, or if the path does not + * start with '/', the name of a property of the /aliases + * node (an alias). In the case of an alias, the node + * matching the alias' value will be returned. * * Returns a node pointer with refcount incremented, use * of_node_put() on it when done. @@ -348,13 +351,32 @@ EXPORT_SYMBOL(of_get_next_child); struct device_node *of_find_node_by_path(const char *path) { struct device_node *np = allnodes; + struct device_node *aliases = NULL; read_lock(&devtree_lock); + + if (path[0] != '/') { + aliases = of_find_node_by_path("/aliases"); + if (!aliases) + goto out; + path = of_get_property(aliases, path, NULL); + /* + * The alias must begin with '/', otherwise we could + * get stuck in an endless loop and blow out the + * stack. + */ + if (!path || path[0] != '/') + goto out; + } + for (; np; np = np->allnext) { if (np->full_name && (of_node_cmp(np->full_name, path) == 0) && of_node_get(np)) break; } +out: + if (aliases) + of_node_put(aliases); read_unlock(&devtree_lock); return np; } -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:43:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:43:13 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11786 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491982Ab1CDTmo (ORCPT ); Fri, 4 Mar 2011 20:42:44 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:31 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:37 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:37 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24JgUii017323; Fri, 4 Mar 2011 11:42:30 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgRUH017322; Fri, 4 Mar 2011 11:42:27 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 00/12] MIPS: Octeon: Use Device Tree. Date: Fri, 4 Mar 2011 11:42:12 -0800 Message-Id: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 04 Mar 2011 19:42:37.0450 (UTC) FILETIME=[50C0DEA0:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29347 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips New in v2: Changed many device tree bindings. They should be closer to the standard naming scheme now. Editing of the template device tree is done in the flattened form using libfdt. Standard platform driver functions used in preference to the of_platform variety. v1: Background: The Octeon family of SOCs has a variety of on-chip controllers for Ethernet, MDIO, I2C, and several other I/O devices. These chips are used on boards with a great variety of different configurations. To date, the configuration and bus topology information has been hard coded in the drivers and support code. To facilitate supporting new chips and boards, we would like to make use use the Device Tree to encode the configuration information. I would like to get some feedback on the current code I am working with. The migration approach is as follows: o Several device tree templates are statically linked into the kernel image. Based on SOC type and board type one of these is selected in early boot. Legacy configuration probing code is used to prune and patch the device tree template. o New SOCs and boards will directly use a device tree passed by the bootloader (This patch set doesn't actually implement this, but it is trivial to add). 01/12 - Move configuration code to common place for use by Device Tree pruning and patching code. 02/12 - Infrastructure to allow scripts/dtc/libfdt to be used in the kernel. 03/12 - OF patch to simplify of_find_node_by_path(). This one I previously sent seperatly and receive as of yet unacted upon feedback. 04/12 - Add the statically linked Device Tree templates. 05/10 - Remove unused arch/mips/prom.c code that conflicts with following patches. 06/10 - irq_create_of_mapping() function. 07/10 - Rearrange legacy configuration code for following patch. 08/10 - Fix up Device Tree template for current environment. 09/10 - Convert I2C driver to use Device Tree. 10/10 - Convert MDIO driver to use Device Tree. 11/10 - Convert Ethernet mgmt driver to use Device Tree. 12/10 - Convert Octeon Ethernet driver to use Device Tree. David Daney (12): MIPS: Octeon: Move some Ethernet support files out of staging. of: Allow scripts/dtc/libfdt to be used from kernel code of: Make of_find_node_by_path() traverse /aliases for relative paths. MIPS: Octeon: Add device tree source files. MIPS: Prune some target specific code out of prom.c MIPS: Octeon: Add a irq_create_of_mapping() implementation. MIPS: Octeon: Rearrance CVMX files in preperation for device tree MIPS: Octeon: Initialize and fixup device tree. i2c: Convert i2c-octeon.c to use device tree. netdev: mdio-octeon.c: Convert to use device tree. netdev: octeon_mgmt: Convert to use device tree. staging: octeon_ethernet: Convert to use device tree. arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 13 + arch/mips/cavium-octeon/executive/Makefile | 5 + .../mips/cavium-octeon/executive}/cvmx-cmd-queue.c | 8 +- .../mips/cavium-octeon/executive}/cvmx-fpa.c | 0 .../cavium-octeon/executive}/cvmx-helper-board.c | 18 +- .../cavium-octeon/executive}/cvmx-helper-fpa.c | 0 .../cavium-octeon/executive}/cvmx-helper-loop.c | 6 +- .../cavium-octeon/executive}/cvmx-helper-npi.c | 6 +- .../cavium-octeon/executive}/cvmx-helper-rgmii.c | 17 +- .../cavium-octeon/executive}/cvmx-helper-sgmii.c | 18 +- .../cavium-octeon/executive}/cvmx-helper-spi.c | 20 +- .../cavium-octeon/executive}/cvmx-helper-util.c | 16 +- .../cavium-octeon/executive}/cvmx-helper-xaui.c | 32 +- .../mips/cavium-octeon/executive}/cvmx-helper.c | 120 +++++-- .../executive}/cvmx-interrupt-decodes.c | 10 +- .../cavium-octeon/executive}/cvmx-interrupt-rsl.c | 4 +- .../mips/cavium-octeon/executive}/cvmx-pko.c | 6 +- .../mips/cavium-octeon/executive}/cvmx-spi.c | 12 +- arch/mips/cavium-octeon/octeon-irq.c | 25 ++ arch/mips/cavium-octeon/octeon-platform.c | 410 +++++++++++--------- arch/mips/cavium-octeon/octeon_3xxx.dts | 330 ++++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 116 ++++++ arch/mips/cavium-octeon/setup.c | 17 + .../mips/include/asm}/octeon/cvmx-address.h | 0 .../mips/include/asm}/octeon/cvmx-asxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-cmd-queue.h | 0 .../mips/include/asm}/octeon/cvmx-config.h | 0 .../mips/include/asm}/octeon/cvmx-dbg-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fau.h | 0 .../mips/include/asm}/octeon/cvmx-fpa-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-gmxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-helper-board.h | 0 .../mips/include/asm}/octeon/cvmx-helper-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-helper-loop.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-npi.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-rgmii.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-sgmii.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-spi.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-util.h | 0 .../mips/include/asm}/octeon/cvmx-helper-xaui.h | 1 + .../mips/include/asm}/octeon/cvmx-helper.h | 1 + .../mips/include/asm}/octeon/cvmx-ipd.h | 0 .../mips/include/asm}/octeon/cvmx-mdio.h | 0 .../mips/include/asm}/octeon/cvmx-pcsx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pcsxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip.h | 0 .../mips/include/asm}/octeon/cvmx-pko-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pko.h | 0 .../mips/include/asm}/octeon/cvmx-pow.h | 0 .../mips/include/asm}/octeon/cvmx-scratch.h | 0 .../mips/include/asm}/octeon/cvmx-spi.h | 0 .../mips/include/asm}/octeon/cvmx-spxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-srxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-stxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-wqe.h | 0 arch/mips/include/asm/octeon/octeon.h | 5 - arch/mips/kernel/prom.c | 49 --- drivers/i2c/busses/i2c-octeon.c | 69 ++-- drivers/net/octeon/octeon_mgmt.c | 321 +++++++++++----- drivers/net/phy/mdio-octeon.c | 92 +++-- drivers/of/base.c | 24 ++- drivers/staging/octeon/Makefile | 5 - drivers/staging/octeon/cvmx-packet.h | 65 --- drivers/staging/octeon/cvmx-smix-defs.h | 178 --------- drivers/staging/octeon/ethernet-defines.h | 2 +- drivers/staging/octeon/ethernet-mdio.c | 31 +- drivers/staging/octeon/ethernet-mem.c | 2 +- drivers/staging/octeon/ethernet-rgmii.c | 4 +- drivers/staging/octeon/ethernet-rx.c | 14 +- drivers/staging/octeon/ethernet-rx.h | 2 +- drivers/staging/octeon/ethernet-sgmii.c | 4 +- drivers/staging/octeon/ethernet-spi.c | 6 +- drivers/staging/octeon/ethernet-tx.c | 12 +- drivers/staging/octeon/ethernet-xaui.c | 4 +- drivers/staging/octeon/ethernet.c | 102 +++-- drivers/staging/octeon/octeon-ethernet.h | 3 + include/linux/libfdt.h | 3 + lib/Kconfig | 6 + lib/Makefile | 2 + lib/libfdt/Makefile | 7 + lib/libfdt/libfdt_env.h | 21 + scripts/dtc/libfdt/libfdt.h | 4 +- 86 files changed, 1421 insertions(+), 835 deletions(-) create mode 100644 arch/mips/cavium-octeon/.gitignore rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-cmd-queue.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-board.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-loop.c (95%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-npi.c (96%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-rgmii.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-sgmii.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-spi.c (94%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-util.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-xaui.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper.c (93%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-decodes.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-rsl.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-pko.c (99%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-spi.c (99%) create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-address.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-asxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-cmd-queue.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-config.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-dbg-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fau.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-gmxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-board.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-loop.h (96%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-npi.h (96%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-rgmii.h (98%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-sgmii.h (98%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-spi.h (98%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-util.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-xaui.h (98%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper.h (99%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-ipd.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-mdio.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pow.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-scratch.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-srxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-stxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-wqe.h (100%) delete mode 100644 drivers/staging/octeon/cvmx-packet.h delete mode 100644 drivers/staging/octeon/cvmx-smix-defs.h create mode 100644 include/linux/libfdt.h create mode 100644 lib/libfdt/Makefile create mode 100644 lib/libfdt/libfdt_env.h -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:43:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:43:39 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11785 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491983Ab1CDTmp (ORCPT ); Fri, 4 Mar 2011 20:42:45 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:34 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:39 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:39 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24JgYcI017327; Fri, 4 Mar 2011 11:42:34 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgWFV017326; Fri, 4 Mar 2011 11:42:32 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 01/12] MIPS: Octeon: Move some Ethernet support files out of staging. Date: Fri, 4 Mar 2011 11:42:13 -0800 Message-Id: <1299267744-17278-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:39.0857 (UTC) FILETIME=[52302610:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29348 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/cavium-octeon/executive/Makefile | 5 + .../mips/cavium-octeon/executive}/cvmx-cmd-queue.c | 8 +- .../mips/cavium-octeon/executive}/cvmx-fpa.c | 0 .../cavium-octeon/executive}/cvmx-helper-board.c | 18 +-- .../cavium-octeon/executive}/cvmx-helper-fpa.c | 0 .../cavium-octeon/executive}/cvmx-helper-loop.c | 6 +- .../cavium-octeon/executive}/cvmx-helper-npi.c | 6 +- .../cavium-octeon/executive}/cvmx-helper-rgmii.c | 17 +- .../cavium-octeon/executive}/cvmx-helper-sgmii.c | 12 +- .../cavium-octeon/executive}/cvmx-helper-spi.c | 10 +- .../cavium-octeon/executive}/cvmx-helper-util.c | 16 +- .../cavium-octeon/executive}/cvmx-helper-xaui.c | 10 +- .../mips/cavium-octeon/executive}/cvmx-helper.c | 27 ++-- .../executive}/cvmx-interrupt-decodes.c | 10 +- .../cavium-octeon/executive}/cvmx-interrupt-rsl.c | 4 +- .../mips/cavium-octeon/executive}/cvmx-pko.c | 6 +- .../mips/cavium-octeon/executive}/cvmx-spi.c | 12 +- .../mips/include/asm}/octeon/cvmx-address.h | 0 .../mips/include/asm}/octeon/cvmx-asxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-cmd-queue.h | 0 .../mips/include/asm}/octeon/cvmx-config.h | 0 .../mips/include/asm}/octeon/cvmx-dbg-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fau.h | 0 .../mips/include/asm}/octeon/cvmx-fpa-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-gmxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-helper-board.h | 0 .../mips/include/asm}/octeon/cvmx-helper-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-helper-loop.h | 0 .../mips/include/asm}/octeon/cvmx-helper-npi.h | 0 .../mips/include/asm}/octeon/cvmx-helper-rgmii.h | 0 .../mips/include/asm}/octeon/cvmx-helper-sgmii.h | 0 .../mips/include/asm}/octeon/cvmx-helper-spi.h | 0 .../mips/include/asm}/octeon/cvmx-helper-util.h | 0 .../mips/include/asm}/octeon/cvmx-helper-xaui.h | 0 .../mips/include/asm}/octeon/cvmx-helper.h | 0 .../mips/include/asm}/octeon/cvmx-ipd.h | 0 .../mips/include/asm}/octeon/cvmx-mdio.h | 0 .../mips/include/asm}/octeon/cvmx-pcsx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pcsxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip.h | 0 .../mips/include/asm}/octeon/cvmx-pko-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pko.h | 0 .../mips/include/asm}/octeon/cvmx-pow.h | 0 .../mips/include/asm}/octeon/cvmx-scratch.h | 0 .../mips/include/asm}/octeon/cvmx-spi.h | 0 .../mips/include/asm}/octeon/cvmx-spxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-srxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-stxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-wqe.h | 0 drivers/staging/octeon/Makefile | 5 - drivers/staging/octeon/cvmx-packet.h | 65 ------- drivers/staging/octeon/cvmx-smix-defs.h | 178 -------------------- drivers/staging/octeon/ethernet-defines.h | 2 +- drivers/staging/octeon/ethernet-mdio.c | 4 +- drivers/staging/octeon/ethernet-mem.c | 2 +- drivers/staging/octeon/ethernet-rgmii.c | 4 +- drivers/staging/octeon/ethernet-rx.c | 14 +- drivers/staging/octeon/ethernet-rx.h | 2 +- drivers/staging/octeon/ethernet-sgmii.c | 4 +- drivers/staging/octeon/ethernet-spi.c | 6 +- drivers/staging/octeon/ethernet-tx.c | 12 +- drivers/staging/octeon/ethernet-xaui.c | 4 +- drivers/staging/octeon/ethernet.c | 14 +- 65 files changed, 116 insertions(+), 367 deletions(-) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-cmd-queue.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-board.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-loop.c (95%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-npi.c (96%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-rgmii.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-sgmii.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-spi.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-util.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-xaui.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-decodes.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-rsl.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-pko.c (99%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-spi.c (99%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-address.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-asxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-cmd-queue.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-config.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-dbg-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fau.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-gmxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-board.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-loop.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-npi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-rgmii.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-sgmii.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-spi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-util.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-xaui.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-ipd.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-mdio.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pow.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-scratch.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-srxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-stxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-wqe.h (100%) delete mode 100644 drivers/staging/octeon/cvmx-packet.h delete mode 100644 drivers/staging/octeon/cvmx-smix-defs.h diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile index 7f41c5b..eec0b88 100644 --- a/arch/mips/cavium-octeon/executive/Makefile +++ b/arch/mips/cavium-octeon/executive/Makefile @@ -10,5 +10,10 @@ # obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o +obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ + cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ + cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ + cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ + cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c similarity index 98% rename from drivers/staging/octeon/cvmx-cmd-queue.c rename to arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c index e9809d3..132bccc 100644 --- a/drivers/staging/octeon/cvmx-cmd-queue.c +++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c @@ -34,13 +34,13 @@ #include -#include "cvmx-config.h" -#include "cvmx-fpa.h" -#include "cvmx-cmd-queue.h" +#include +#include +#include #include #include -#include "cvmx-pko-defs.h" +#include /** * This application uses this pointer to access the global queue diff --git a/drivers/staging/octeon/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c similarity index 100% rename from drivers/staging/octeon/cvmx-fpa.c rename to arch/mips/cavium-octeon/executive/cvmx-fpa.c diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-board.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-board.c index 57d35dc..71590a3 100644 --- a/drivers/staging/octeon/cvmx-helper-board.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -34,16 +34,16 @@ #include #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" +#include -#include "cvmx-helper.h" -#include "cvmx-helper-util.h" -#include "cvmx-helper-board.h" +#include +#include +#include -#include "cvmx-gmxx-defs.h" -#include "cvmx-asxx-defs.h" +#include +#include /** * cvmx_override_board_link_get(int ipd_port) is a function @@ -493,7 +493,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_mdio_phy_reg_control_t reg_control; cvmx_mdio_phy_reg_status_t reg_status; cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; - cvmx_mdio_phy_reg_extended_status_t reg_extended_status; cvmx_mdio_phy_reg_control_1000_t reg_control_1000; reg_status.u16 = @@ -508,9 +507,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, reg_autoneg_adver.s.advert_100base_tx_full = 0; reg_autoneg_adver.s.advert_100base_tx_half = 0; if (reg_status.s.capable_extended_status) { - reg_extended_status.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_EXTENDED_STATUS); reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000); diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c similarity index 100% rename from drivers/staging/octeon/cvmx-helper-fpa.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c similarity index 95% rename from drivers/staging/octeon/cvmx-helper-loop.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-loop.c index 55a571a..bfbd461 100644 --- a/drivers/staging/octeon/cvmx-helper-loop.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c @@ -31,10 +31,10 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" -#include "cvmx-pip-defs.h" +#include +#include /** * Probe a LOOP interface and determine the number of ports diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c similarity index 96% rename from drivers/staging/octeon/cvmx-helper-npi.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-npi.c index 7388a1e..cc94cfa 100644 --- a/drivers/staging/octeon/cvmx-helper-npi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c @@ -31,11 +31,11 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" +#include -#include "cvmx-pip-defs.h" +#include /** * Probe a NPI interface and determine the number of ports diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-rgmii.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c index aa2d5d7..82b2184 100644 --- a/drivers/staging/octeon/cvmx-helper-rgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c @@ -31,18 +31,18 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include +#include #include -#include "cvmx-gmxx-defs.h" -#include "cvmx-asxx-defs.h" -#include "cvmx-dbg-defs.h" +#include +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_asxx_enable(int block); @@ -326,6 +326,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & ~(1 << index)); + memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save)); /* Disable all queues so that TX should become idle */ for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { int queue = cvmx_pko_get_base_queue(ipd_port) + i; diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-sgmii.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c index 6214e3b..464347f 100644 --- a/drivers/staging/octeon/cvmx-helper-sgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -32,14 +32,14 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsx-defs.h" +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-spi.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-spi.c index 8ba6c83..02a4442 100644 --- a/drivers/staging/octeon/cvmx-helper-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -35,12 +35,12 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index); */ #include -#include "cvmx-config.h" -#include "cvmx-spi.h" -#include "cvmx-helper.h" +#include +#include +#include -#include "cvmx-pip-defs.h" -#include "cvmx-pko-defs.h" +#include +#include /* * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-util.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-util.c index 41ef8a4..8c98a22 100644 --- a/drivers/staging/octeon/cvmx-helper-util.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c @@ -32,16 +32,16 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-fpa.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-ipd.h" -#include "cvmx-spi.h" +#include +#include +#include +#include +#include -#include "cvmx-helper.h" -#include "cvmx-helper-util.h" +#include +#include #include diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-xaui.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index a11e676..667a8e3 100644 --- a/drivers/staging/octeon/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -33,13 +33,13 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" +#include -#include "cvmx-pko-defs.h" -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsxx-defs.h" +#include +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); diff --git a/drivers/staging/octeon/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper.c rename to arch/mips/cavium-octeon/executive/cvmx-helper.c index 5915066..6238a22 100644 --- a/drivers/staging/octeon/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -32,19 +32,19 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-fpa.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-ipd.h" -#include "cvmx-spi.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include +#include +#include +#include +#include -#include "cvmx-pip-defs.h" -#include "cvmx-smix-defs.h" -#include "cvmx-asxx-defs.h" +#include +#include +#include /** * cvmx_override_pko_queue_priority(int ipd_port, uint64_t @@ -548,7 +548,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) union cvmx_gmxx_prtx_cfg gmx_cfg; int retry_cnt; int retry_loop_cnt; - int mtu; int i; cvmx_helper_link_info_t link_info; @@ -662,10 +661,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); - mtu = - cvmx_read_csr(CVMX_GMXX_RXX_JABBER - (INDEX(FIX_IPD_OUTPORT), - INTERFACE(FIX_IPD_OUTPORT))); cvmx_write_csr(CVMX_GMXX_RXX_JABBER (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c similarity index 98% rename from drivers/staging/octeon/cvmx-interrupt-decodes.c rename to arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c index a3337e3..e59d1b7 100644 --- a/drivers/staging/octeon/cvmx-interrupt-decodes.c +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c @@ -34,11 +34,11 @@ #include -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsx-defs.h" -#include "cvmx-pcsxx-defs.h" -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" +#include +#include +#include +#include +#include #ifndef PRINT_ERROR #define PRINT_ERROR(format, ...) diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c similarity index 97% rename from drivers/staging/octeon/cvmx-interrupt-rsl.c rename to arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c index df50048..bea7538 100644 --- a/drivers/staging/octeon/cvmx-interrupt-rsl.c +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c @@ -32,8 +32,8 @@ #include -#include "cvmx-asxx-defs.h" -#include "cvmx-gmxx-defs.h" +#include +#include #ifndef PRINT_ERROR #define PRINT_ERROR(format, ...) diff --git a/drivers/staging/octeon/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c similarity index 99% rename from drivers/staging/octeon/cvmx-pko.c rename to arch/mips/cavium-octeon/executive/cvmx-pko.c index 00db915..f557084 100644 --- a/drivers/staging/octeon/cvmx-pko.c +++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c @@ -31,9 +31,9 @@ #include -#include "cvmx-config.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" +#include +#include +#include /** * Internal state of packet output diff --git a/drivers/staging/octeon/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c similarity index 99% rename from drivers/staging/octeon/cvmx-spi.c rename to arch/mips/cavium-octeon/executive/cvmx-spi.c index 82794d9..74afb17 100644 --- a/drivers/staging/octeon/cvmx-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c @@ -31,14 +31,14 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-pko.h" -#include "cvmx-spi.h" +#include +#include -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" -#include "cvmx-srxx-defs.h" +#include +#include +#include #define INVOKE_CB(function_p, args...) \ do { \ diff --git a/drivers/staging/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h similarity index 100% rename from drivers/staging/octeon/cvmx-address.h rename to arch/mips/include/asm/octeon/cvmx-address.h diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-asxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-asxx-defs.h diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h similarity index 100% rename from drivers/staging/octeon/cvmx-cmd-queue.h rename to arch/mips/include/asm/octeon/cvmx-cmd-queue.h diff --git a/drivers/staging/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h similarity index 100% rename from drivers/staging/octeon/cvmx-config.h rename to arch/mips/include/asm/octeon/cvmx-config.h diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-dbg-defs.h rename to arch/mips/include/asm/octeon/cvmx-dbg-defs.h diff --git a/drivers/staging/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h similarity index 100% rename from drivers/staging/octeon/cvmx-fau.h rename to arch/mips/include/asm/octeon/cvmx-fau.h diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-fpa-defs.h rename to arch/mips/include/asm/octeon/cvmx-fpa-defs.h diff --git a/drivers/staging/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h similarity index 100% rename from drivers/staging/octeon/cvmx-fpa.h rename to arch/mips/include/asm/octeon/cvmx-fpa.h diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-gmxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-gmxx-defs.h diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-board.h rename to arch/mips/include/asm/octeon/cvmx-helper-board.h diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-fpa.h rename to arch/mips/include/asm/octeon/cvmx-helper-fpa.h diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-loop.h rename to arch/mips/include/asm/octeon/cvmx-helper-loop.h diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-npi.h rename to arch/mips/include/asm/octeon/cvmx-helper-npi.h diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-rgmii.h rename to arch/mips/include/asm/octeon/cvmx-helper-rgmii.h diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-sgmii.h rename to arch/mips/include/asm/octeon/cvmx-helper-sgmii.h diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-spi.h rename to arch/mips/include/asm/octeon/cvmx-helper-spi.h diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-util.h rename to arch/mips/include/asm/octeon/cvmx-helper-util.h diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-xaui.h rename to arch/mips/include/asm/octeon/cvmx-helper-xaui.h diff --git a/drivers/staging/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper.h rename to arch/mips/include/asm/octeon/cvmx-helper.h diff --git a/drivers/staging/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h similarity index 100% rename from drivers/staging/octeon/cvmx-ipd.h rename to arch/mips/include/asm/octeon/cvmx-ipd.h diff --git a/drivers/staging/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h similarity index 100% rename from drivers/staging/octeon/cvmx-mdio.h rename to arch/mips/include/asm/octeon/cvmx-mdio.h diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pcsx-defs.h rename to arch/mips/include/asm/octeon/cvmx-pcsx-defs.h diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pcsxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pip-defs.h rename to arch/mips/include/asm/octeon/cvmx-pip-defs.h diff --git a/drivers/staging/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h similarity index 100% rename from drivers/staging/octeon/cvmx-pip.h rename to arch/mips/include/asm/octeon/cvmx-pip.h diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pko-defs.h rename to arch/mips/include/asm/octeon/cvmx-pko-defs.h diff --git a/drivers/staging/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h similarity index 100% rename from drivers/staging/octeon/cvmx-pko.h rename to arch/mips/include/asm/octeon/cvmx-pko.h diff --git a/drivers/staging/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h similarity index 100% rename from drivers/staging/octeon/cvmx-pow.h rename to arch/mips/include/asm/octeon/cvmx-pow.h diff --git a/drivers/staging/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h similarity index 100% rename from drivers/staging/octeon/cvmx-scratch.h rename to arch/mips/include/asm/octeon/cvmx-scratch.h diff --git a/drivers/staging/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h similarity index 100% rename from drivers/staging/octeon/cvmx-spi.h rename to arch/mips/include/asm/octeon/cvmx-spi.h diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-spxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-spxx-defs.h diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-srxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-srxx-defs.h diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-stxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-stxx-defs.h diff --git a/drivers/staging/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h similarity index 100% rename from drivers/staging/octeon/cvmx-wqe.h rename to arch/mips/include/asm/octeon/cvmx-wqe.h diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile index fc850ba..9012dee 100644 --- a/drivers/staging/octeon/Makefile +++ b/drivers/staging/octeon/Makefile @@ -20,9 +20,4 @@ octeon-ethernet-y += ethernet-sgmii.o octeon-ethernet-y += ethernet-spi.o octeon-ethernet-y += ethernet-tx.o octeon-ethernet-y += ethernet-xaui.o -octeon-ethernet-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ - cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ - cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ - cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ - cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h deleted file mode 100644 index 62ffe78..0000000 --- a/drivers/staging/octeon/cvmx-packet.h +++ /dev/null @@ -1,65 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Packet buffer defines. - */ - -#ifndef __CVMX_PACKET_H__ -#define __CVMX_PACKET_H__ - -/** - * This structure defines a buffer pointer on Octeon - */ -union cvmx_buf_ptr { - void *ptr; - uint64_t u64; - struct { - /* - * if set, invert the "free" pick of the overall - * packet. HW always sets this bit to 0 on inbound - * packet - */ - uint64_t i:1; - /* - * Indicates the amount to back up to get to the - * buffer start in cache lines. In most cases this is - * less than one complete cache line, so the value is - * zero. - */ - uint64_t back:4; - /* The pool that the buffer came from / goes to */ - uint64_t pool:3; - /* The size of the segment pointed to by addr (in bytes) */ - uint64_t size:16; - /* Pointer to the first byte of the data, NOT buffer */ - uint64_t addr:40; - } s; -}; - -#endif /* __CVMX_PACKET_H__ */ diff --git a/drivers/staging/octeon/cvmx-smix-defs.h b/drivers/staging/octeon/cvmx-smix-defs.h deleted file mode 100644 index 9ae45fc..0000000 --- a/drivers/staging/octeon/cvmx-smix-defs.h +++ /dev/null @@ -1,178 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_SMIX_DEFS_H__ -#define __CVMX_SMIX_DEFS_H__ - -#define CVMX_SMIX_CLK(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_CMD(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_EN(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_RD_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_WR_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256)) - -union cvmx_smix_clk { - uint64_t u64; - struct cvmx_smix_clk_s { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t sample_mode:1; - uint64_t reserved_14_14:1; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } s; - struct cvmx_smix_clk_cn30xx { - uint64_t reserved_21_63:43; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn30xx; - struct cvmx_smix_clk_cn30xx cn31xx; - struct cvmx_smix_clk_cn30xx cn38xx; - struct cvmx_smix_clk_cn30xx cn38xxp2; - struct cvmx_smix_clk_cn50xx { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn50xx; - struct cvmx_smix_clk_s cn52xx; - struct cvmx_smix_clk_cn50xx cn52xxp1; - struct cvmx_smix_clk_s cn56xx; - struct cvmx_smix_clk_cn50xx cn56xxp1; - struct cvmx_smix_clk_cn30xx cn58xx; - struct cvmx_smix_clk_cn30xx cn58xxp1; -}; - -union cvmx_smix_cmd { - uint64_t u64; - struct cvmx_smix_cmd_s { - uint64_t reserved_18_63:46; - uint64_t phy_op:2; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } s; - struct cvmx_smix_cmd_cn30xx { - uint64_t reserved_17_63:47; - uint64_t phy_op:1; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } cn30xx; - struct cvmx_smix_cmd_cn30xx cn31xx; - struct cvmx_smix_cmd_cn30xx cn38xx; - struct cvmx_smix_cmd_cn30xx cn38xxp2; - struct cvmx_smix_cmd_s cn50xx; - struct cvmx_smix_cmd_s cn52xx; - struct cvmx_smix_cmd_s cn52xxp1; - struct cvmx_smix_cmd_s cn56xx; - struct cvmx_smix_cmd_s cn56xxp1; - struct cvmx_smix_cmd_cn30xx cn58xx; - struct cvmx_smix_cmd_cn30xx cn58xxp1; -}; - -union cvmx_smix_en { - uint64_t u64; - struct cvmx_smix_en_s { - uint64_t reserved_1_63:63; - uint64_t en:1; - } s; - struct cvmx_smix_en_s cn30xx; - struct cvmx_smix_en_s cn31xx; - struct cvmx_smix_en_s cn38xx; - struct cvmx_smix_en_s cn38xxp2; - struct cvmx_smix_en_s cn50xx; - struct cvmx_smix_en_s cn52xx; - struct cvmx_smix_en_s cn52xxp1; - struct cvmx_smix_en_s cn56xx; - struct cvmx_smix_en_s cn56xxp1; - struct cvmx_smix_en_s cn58xx; - struct cvmx_smix_en_s cn58xxp1; -}; - -union cvmx_smix_rd_dat { - uint64_t u64; - struct cvmx_smix_rd_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_rd_dat_s cn30xx; - struct cvmx_smix_rd_dat_s cn31xx; - struct cvmx_smix_rd_dat_s cn38xx; - struct cvmx_smix_rd_dat_s cn38xxp2; - struct cvmx_smix_rd_dat_s cn50xx; - struct cvmx_smix_rd_dat_s cn52xx; - struct cvmx_smix_rd_dat_s cn52xxp1; - struct cvmx_smix_rd_dat_s cn56xx; - struct cvmx_smix_rd_dat_s cn56xxp1; - struct cvmx_smix_rd_dat_s cn58xx; - struct cvmx_smix_rd_dat_s cn58xxp1; -}; - -union cvmx_smix_wr_dat { - uint64_t u64; - struct cvmx_smix_wr_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_wr_dat_s cn30xx; - struct cvmx_smix_wr_dat_s cn31xx; - struct cvmx_smix_wr_dat_s cn38xx; - struct cvmx_smix_wr_dat_s cn38xxp2; - struct cvmx_smix_wr_dat_s cn50xx; - struct cvmx_smix_wr_dat_s cn52xx; - struct cvmx_smix_wr_dat_s cn52xxp1; - struct cvmx_smix_wr_dat_s cn56xx; - struct cvmx_smix_wr_dat_s cn56xxp1; - struct cvmx_smix_wr_dat_s cn58xx; - struct cvmx_smix_wr_dat_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h index 6a2cd50..bdaec8d 100644 --- a/drivers/staging/octeon/ethernet-defines.h +++ b/drivers/staging/octeon/ethernet-defines.h @@ -59,7 +59,7 @@ #ifndef __ETHERNET_DEFINES_H__ #define __ETHERNET_DEFINES_H__ -#include "cvmx-config.h" +#include #define OCTEON_ETHERNET_VERSION "1.9" diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 10a82ef..0e5dab7 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -37,9 +37,9 @@ #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "cvmx-helper-board.h" +#include -#include "cvmx-smix-defs.h" +#include static void cvm_oct_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c index 635bb86..78b6cb7 100644 --- a/drivers/staging/octeon/ethernet-mem.c +++ b/drivers/staging/octeon/ethernet-mem.c @@ -32,7 +32,7 @@ #include "ethernet-defines.h" -#include "cvmx-fpa.h" +#include /** * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c index a0d4d4b..849af10 100644 --- a/drivers/staging/octeon/ethernet-rgmii.c +++ b/drivers/staging/octeon/ethernet-rgmii.c @@ -35,11 +35,11 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include #include #include -#include "cvmx-gmxx-defs.h" +#include DEFINE_SPINLOCK(global_register_lock); diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c index cb38f9e..d830393 100644 --- a/drivers/staging/octeon/ethernet-rx.c +++ b/drivers/staging/octeon/ethernet-rx.c @@ -51,14 +51,14 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" -#include "cvmx-wqe.h" -#include "cvmx-fau.h" -#include "cvmx-pow.h" -#include "cvmx-pip.h" -#include "cvmx-scratch.h" - -#include "cvmx-gmxx-defs.h" +#include +#include +#include +#include +#include +#include + +#include struct cvm_napi_wrapper { struct napi_struct napi; diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h index a0743b8..9240c85 100644 --- a/drivers/staging/octeon/ethernet-rx.h +++ b/drivers/staging/octeon/ethernet-rx.h @@ -24,7 +24,7 @@ * This file may also be available under a different license from Cavium. * Contact Cavium Networks for more information *********************************************************************/ -#include "cvmx-fau.h" +#include void cvm_oct_poll_controller(struct net_device *dev); void cvm_oct_rx_initialize(void); diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c index 2d8589e..d102277 100644 --- a/drivers/staging/octeon/ethernet-sgmii.c +++ b/drivers/staging/octeon/ethernet-sgmii.c @@ -34,9 +34,9 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include -#include "cvmx-gmxx-defs.h" +#include int cvm_oct_sgmii_open(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c index 9708254..2ce9135 100644 --- a/drivers/staging/octeon/ethernet-spi.c +++ b/drivers/staging/octeon/ethernet-spi.c @@ -34,11 +34,11 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-spi.h" +#include #include -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" +#include +#include static int number_spi_ports; static int need_retrain[2] = { 0, 0 }; diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c index afc2b73..1f03eb6 100644 --- a/drivers/staging/octeon/ethernet-tx.c +++ b/drivers/staging/octeon/ethernet-tx.c @@ -46,13 +46,13 @@ #include "ethernet-tx.h" #include "ethernet-util.h" -#include "cvmx-wqe.h" -#include "cvmx-fau.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" +#include +#include +#include +#include +#include -#include "cvmx-gmxx-defs.h" +#include #define CVM_OCT_SKB_CB(skb) ((u64 *)((skb)->cb)) diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c index 3fca1cc..321fafc 100644 --- a/drivers/staging/octeon/ethernet-xaui.c +++ b/drivers/staging/octeon/ethernet-xaui.c @@ -34,9 +34,9 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include -#include "cvmx-gmxx-defs.h" +#include int cvm_oct_xaui_open(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index a8f780e..042adf7 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -44,14 +44,14 @@ #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-fau.h" -#include "cvmx-ipd.h" -#include "cvmx-helper.h" - -#include "cvmx-gmxx-defs.h" -#include "cvmx-smix-defs.h" +#include +#include +#include +#include +#include + +#include +#include #if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \ && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:43:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:44:03 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11806 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491985Ab1CDTmq (ORCPT ); Fri, 4 Mar 2011 20:42:46 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:36 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:42 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:42 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24Jga31017331; Fri, 4 Mar 2011 11:42:36 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgZt7017330; Fri, 4 Mar 2011 11:42:35 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 02/12] of: Allow scripts/dtc/libfdt to be used from kernel code Date: Fri, 4 Mar 2011 11:42:14 -0800 Message-Id: <1299267744-17278-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:42.0403 (UTC) FILETIME=[53B4A330:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29349 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- include/linux/libfdt.h | 3 +++ lib/Kconfig | 6 ++++++ lib/Makefile | 2 ++ lib/libfdt/Makefile | 7 +++++++ lib/libfdt/libfdt_env.h | 21 +++++++++++++++++++++ scripts/dtc/libfdt/libfdt.h | 4 ++-- 6 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 include/linux/libfdt.h create mode 100644 lib/libfdt/Makefile create mode 100644 lib/libfdt/libfdt_env.h diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h new file mode 100644 index 0000000..10bce91 --- /dev/null +++ b/include/linux/libfdt.h @@ -0,0 +1,3 @@ +#include "../../lib/libfdt/libfdt_env.h" +#include "../../scripts/dtc/libfdt/fdt.h" +#include "../../scripts/dtc/libfdt/libfdt.h" diff --git a/lib/Kconfig b/lib/Kconfig index 0ee67e0..e8a2638 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -219,4 +219,10 @@ config LRU_CACHE config AVERAGE bool +# +# The Flattened Device Tree manipulation library +# +config LIBFDT + bool + endmenu diff --git a/lib/Makefile b/lib/Makefile index cbb774f..5840115 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -110,6 +110,8 @@ obj-$(CONFIG_ATOMIC64_SELFTEST) += atomic64_test.o obj-$(CONFIG_AVERAGE) += average.o +obj-$(CONFIG_LIBFDT) += libfdt/ + hostprogs-y := gen_crc32table clean-files := crc32table.h diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile new file mode 100644 index 0000000..6c1a496 --- /dev/null +++ b/lib/libfdt/Makefile @@ -0,0 +1,7 @@ +obj-y = fdt.o fdt_wip.o fdt_ro.o + +EXTRA_CFLAGS += -include $(src)/libfdt_env.h -I$(src)/../../scripts/dtc/libfdt + +$(obj)/%.o: $(src)/../../scripts/dtc/libfdt/%.c FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) diff --git a/lib/libfdt/libfdt_env.h b/lib/libfdt/libfdt_env.h new file mode 100644 index 0000000..d977b8b --- /dev/null +++ b/lib/libfdt/libfdt_env.h @@ -0,0 +1,21 @@ +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H + +#include + +#define _B(n) ((unsigned long long)((uint8_t *)&x)[n]) +static inline uint32_t fdt32_to_cpu(uint32_t x) +{ + return (_B(0) << 24) | (_B(1) << 16) | (_B(2) << 8) | _B(3); +} +#define cpu_to_fdt32(x) fdt32_to_cpu(x) + +static inline uint64_t fdt64_to_cpu(uint64_t x) +{ + return (_B(0) << 56) | (_B(1) << 48) | (_B(2) << 40) | (_B(3) << 32) + | (_B(4) << 24) | (_B(5) << 16) | (_B(6) << 8) | _B(7); +} +#define cpu_to_fdt64(x) fdt64_to_cpu(x) +#undef _B + +#endif /* _LIBFDT_ENV_H */ diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h index ce80e4f..33a0c4d 100644 --- a/scripts/dtc/libfdt/libfdt.h +++ b/scripts/dtc/libfdt/libfdt.h @@ -51,8 +51,8 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include -#include +#include "libfdt_env.h" +#include "fdt.h" #define FDT_FIRST_SUPPORTED_VERSION 0x10 #define FDT_LAST_SUPPORTED_VERSION 0x11 -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:44:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:44:26 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11809 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491987Ab1CDTmv (ORCPT ); Fri, 4 Mar 2011 20:42:51 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:49 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:49 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24Jgh9j017345; Fri, 4 Mar 2011 11:42:43 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24Jgg6T017344; Fri, 4 Mar 2011 11:42:42 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 05/12] MIPS: Prune some target specific code out of prom.c Date: Fri, 4 Mar 2011 11:42:17 -0800 Message-Id: <1299267744-17278-6-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:49.0419 (UTC) FILETIME=[57E331B0:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29350 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This code is not common enough to be in a shared file. It is also not used by any existing boards, so just remove it. Signed-off-by: David Daney --- arch/mips/kernel/prom.c | 49 ----------------------------------------------- 1 files changed, 0 insertions(+), 49 deletions(-) diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index a19811e9..a07b6f1 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -59,52 +59,3 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start, initrd_below_start_ok = 1; } #endif - -/* - * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# - * - * Currently the mapping mechanism is trivial; simple flat hwirq numbers are - * mapped 1:1 onto Linux irq numbers. Cascaded irq controllers are not - * supported. - */ -unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) -{ - return intspec[0]; -} -EXPORT_SYMBOL_GPL(irq_create_of_mapping); - -void __init early_init_devtree(void *params) -{ - /* Setup flat device-tree pointer */ - initial_boot_params = params; - - /* Retrieve various informations from the /chosen node of the - * device-tree, including the platform type, initrd location and - * size, and more ... - */ - of_scan_flat_dt(early_init_dt_scan_chosen, NULL); - - /* Scan memory nodes */ - of_scan_flat_dt(early_init_dt_scan_root, NULL); - of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL); -} - -void __init device_tree_init(void) -{ - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_mem_mach(base, size); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_mem_mach(base, size); -} -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:44:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:44:50 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11813 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491988Ab1CDTmv (ORCPT ); Fri, 4 Mar 2011 20:42:51 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:49 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:49 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24JggRT017341; Fri, 4 Mar 2011 11:42:42 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgeIc017338; Fri, 4 Mar 2011 11:42:40 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 04/12] MIPS: Octeon: Add device tree source files. Date: Fri, 4 Mar 2011 11:42:16 -0800 Message-Id: <1299267744-17278-5-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:49.0622 (UTC) FILETIME=[58022B60:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29351 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 13 ++ arch/mips/cavium-octeon/octeon_3xxx.dts | 330 +++++++++++++++++++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 116 +++++++++++ 4 files changed, 461 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore new file mode 100644 index 0000000..39c9686 --- /dev/null +++ b/arch/mips/cavium-octeon/.gitignore @@ -0,0 +1,2 @@ +*.dtb.S +*.dtb diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 19eb043..5e25dce 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -15,3 +15,16 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o + +DTS_FILES = octeon_3xxx.dts octeon_68xx.dts +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) + +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) + +$(obj)/%.dtb: $(src)/%.dts + $(call cmd,dtc) + +# Let's keep the .dtb files around in case we want to look at them. +.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) + +clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts new file mode 100644 index 0000000..6910d9d --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_3xxx.dts @@ -0,0 +1,330 @@ +/dts-v1/; +/* + * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + model = "OCTEON"; + compatible = "cavium,octeon-3860"; + #address-cells = <2>; + #size-cells = <2>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + #address-cells = <0>; + /* Interrupts are specified by three parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + * 3) Triggering (0 - level active high + * 1 - level active low + * 2 - edge rising + * 3 - edge falling + * + * For non-GPIO sources, the triggering cannot be + * changed and is ignored. + */ + #interrupt-cells = <3>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; + + smi0: mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000001900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + device_type = "network"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupt-parent = <&ciu>; + interrupts = <0 62 0>, <1 46 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + mix1: ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + device_type = "network"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupt-parent = <&ciu>; + interrupts = <1 18 0>, < 1 46 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy5>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy6>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy7>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy8>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy9>; + }; + }; + + interface@2 { /* DPI interface. */ + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@3 { /* Loop interface. */ + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + device_type = "network"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupt-parent = <&ciu>; + interrupts = <0 45 0>; + clock-rate = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupt-parent = <&ciu>; + interrupts = <0 59 0>; + clock-rate = <100000>; + }; + }; + + aliases { + mix0 = &mix0; + mix1 = &mix1; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + twsi0 = &twsi0; + twsi1 = &twsi1; + }; + }; diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts new file mode 100644 index 0000000..f2a8eab --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_68xx.dts @@ -0,0 +1,116 @@ +/dts-v1/; +/* + * OCTEON 68XX device tree skeleton. + */ +/ { + model = "OCTEON"; + compatible = "cavium,octeon-6880"; + #address-cells = <2>; + #size-cells = <2>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu2: interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; + + smi0: mdio@1180000003800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003800 0x0 0x40>; + + phy0: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + device_type = "ethernet-phy"; + }; + }; + + smi1: mdio@1180000003880 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003880 0x0 0x40>; + }; + + smi2: mdio@1180000003900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003900 0x0 0x40>; + }; + + smi3: mdio@1180000003980 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003980 0x0 0x40>; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + device_type = "network"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupt-parent = <&ciu2>; + interrupts = <0 62>, <1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupt-parent = <&ciu2>; + interrupts = <0 45>; + clock-rate = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupt-parent = <&ciu2>; + interrupts = <0 59>; + clock-rate = <100000>; + }; + }; + aliases { + mix0 = &mix0; + smi0 = &smi0; + smi1 = &smi1; + smi2 = &smi2; + smi3 = &smi3; + twsi0 = &twsi0; + twsi1 = &twsi1; + }; + }; -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:45:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:45:13 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11817 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491989Ab1CDTmw (ORCPT ); Fri, 4 Mar 2011 20:42:52 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:44 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:50 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:50 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24JgjR4017349; Fri, 4 Mar 2011 11:42:45 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgiIr017348; Fri, 4 Mar 2011 11:42:44 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 06/12] MIPS: Octeon: Add a irq_create_of_mapping() implementation. Date: Fri, 4 Mar 2011 11:42:18 -0800 Message-Id: <1299267744-17278-7-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:50.0388 (UTC) FILETIME=[58770D40:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29352 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is needed for Octeon to use the Device Tree. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index b365710..b0a9261 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -8,7 +8,9 @@ #include #include +#include #include +#include #include #include @@ -64,6 +66,29 @@ static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, octeon_irq_ciu_to_irq[line][bit] = irq; } +/* + * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# + * + * Octeon irq maps are a pair of indexes. The first selects either + * ciu0 or ciu1, the second is the bit within the ciu register. + */ +unsigned int irq_create_of_mapping(struct device_node *controller, + const u32 *intspec, unsigned int intsize) +{ + int ciu, bit; + unsigned int irq = 0; + + ciu = be32_to_cpup(intspec); + bit = be32_to_cpup(intspec + 1); + + if (ciu < 8 && bit < 64) + irq = octeon_irq_ciu_to_irq[ciu][bit]; + + return irq; +} +EXPORT_SYMBOL_GPL(irq_create_of_mapping); + + static int octeon_coreid_for_cpu(int cpu) { #ifdef CONFIG_SMP -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:45:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:45:38 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11824 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491990Ab1CDTmx (ORCPT ); Fri, 4 Mar 2011 20:42:53 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:45 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:51 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:51 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24Jgk6h017362; Fri, 4 Mar 2011 11:42:46 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgkKH017352; Fri, 4 Mar 2011 11:42:46 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 07/12] MIPS: Octeon: Rearrance CVMX files in preperation for device tree Date: Fri, 4 Mar 2011 11:42:19 -0800 Message-Id: <1299267744-17278-8-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:51.0607 (UTC) FILETIME=[59310E70:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29353 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- .../cavium-octeon/executive/cvmx-helper-sgmii.c | 6 +- .../mips/cavium-octeon/executive/cvmx-helper-spi.c | 10 ++ .../cavium-octeon/executive/cvmx-helper-xaui.c | 22 +++-- arch/mips/cavium-octeon/executive/cvmx-helper.c | 93 ++++++++++++++++--- arch/mips/include/asm/octeon/cvmx-helper-loop.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-npi.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-rgmii.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-sgmii.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-spi.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-xaui.h | 1 + arch/mips/include/asm/octeon/cvmx-helper.h | 1 + 11 files changed, 114 insertions(+), 24 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c index 464347f..0c0bf5d 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -326,6 +326,10 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) return 0; } +int __cvmx_helper_sgmii_enumerate(int interface) +{ + return 4; +} /** * Probe a SGMII interface and determine the number of ports * connected to it. The SGMII interface should still be down after @@ -347,7 +351,7 @@ int __cvmx_helper_sgmii_probe(int interface) mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); mode.s.en = 1; cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); - return 4; + return __cvmx_helper_sgmii_enumerate(interface); } /** diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c index 02a4442..2830e4b 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -51,6 +51,16 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index); #define CVMX_HELPER_SPI_TIMEOUT 10 #endif +int __cvmx_helper_spi_enumerate(int interface) +{ + if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && + cvmx_spi4000_is_present(interface)) { + return 10; + } else { + return 16; + } +} + /** * Probe a SPI interface and determine the number of ports * connected to it. The SPI interface should still be down after diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index 667a8e3..1723248e 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -44,6 +44,19 @@ void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); + +int __cvmx_helper_xaui_enumerate(int interface) +{ + union cvmx_gmxx_hg2_control gmx_hg2_control; + + /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ + gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); + if (gmx_hg2_control.s.hg2tx_en) + return 16; + else + return 1; +} + /** * Probe a XAUI interface and determine the number of ports * connected to it. The XAUI interface should still be down @@ -56,7 +69,6 @@ void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); int __cvmx_helper_xaui_probe(int interface) { int i; - union cvmx_gmxx_hg2_control gmx_hg2_control; union cvmx_gmxx_inf_mode mode; /* @@ -90,13 +102,7 @@ int __cvmx_helper_xaui_probe(int interface) pko_mem_port_ptrs.s.pid = interface * 16 + i; cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); } - - /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ - gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); - if (gmx_hg2_control.s.hg2tx_en) - return 16; - else - return 1; + return __cvmx_helper_xaui_enumerate(interface); } /** diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index 6238a22..bea6ab6 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -234,21 +234,16 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port) } /** - * This function probes an interface to determine the actual - * number of hardware ports connected to it. It doesn't setup the - * ports or enable them. The main goal here is to set the global - * interface_port_count[interface] correctly. Hardware setup of the - * ports will be performed later. + * This function sets the interface_port_count[interface] correctly, + * without modifying any hardware configuration. Hardware setup of + * the ports will be performed later. * * @interface: Interface to probe * * Returns Zero on success, negative on failure */ -int cvmx_helper_interface_probe(int interface) +int cvmx_helper_interface_enumerate(int interface) { - /* At this stage in the game we don't want packets to be moving yet. - The following probe calls should perform hardware setup - needed to determine port counts. Receive must still be disabled */ switch (cvmx_helper_interface_get_mode(interface)) { /* These types don't support ports to IPD/PKO */ case CVMX_HELPER_INTERFACE_MODE_DISABLED: @@ -258,7 +253,7 @@ int cvmx_helper_interface_probe(int interface) /* XAUI is a single high speed port */ case CVMX_HELPER_INTERFACE_MODE_XAUI: interface_port_count[interface] = - __cvmx_helper_xaui_probe(interface); + __cvmx_helper_xaui_enumerate(interface); break; /* * RGMII/GMII/MII are all treated about the same. Most @@ -267,7 +262,7 @@ int cvmx_helper_interface_probe(int interface) case CVMX_HELPER_INTERFACE_MODE_RGMII: case CVMX_HELPER_INTERFACE_MODE_GMII: interface_port_count[interface] = - __cvmx_helper_rgmii_probe(interface); + __cvmx_helper_rgmii_enumerate(interface); break; /* * SPI4 can have 1-16 ports depending on the device at @@ -275,7 +270,7 @@ int cvmx_helper_interface_probe(int interface) */ case CVMX_HELPER_INTERFACE_MODE_SPI: interface_port_count[interface] = - __cvmx_helper_spi_probe(interface); + __cvmx_helper_spi_enumerate(interface); break; /* * SGMII can have 1-4 ports depending on how many are @@ -284,12 +279,12 @@ int cvmx_helper_interface_probe(int interface) case CVMX_HELPER_INTERFACE_MODE_SGMII: case CVMX_HELPER_INTERFACE_MODE_PICMG: interface_port_count[interface] = - __cvmx_helper_sgmii_probe(interface); + __cvmx_helper_sgmii_enumerate(interface); break; /* PCI target Network Packet Interface */ case CVMX_HELPER_INTERFACE_MODE_NPI: interface_port_count[interface] = - __cvmx_helper_npi_probe(interface); + __cvmx_helper_npi_enumerate(interface); break; /* * Special loopback only ports. These are not the same @@ -297,7 +292,7 @@ int cvmx_helper_interface_probe(int interface) */ case CVMX_HELPER_INTERFACE_MODE_LOOP: interface_port_count[interface] = - __cvmx_helper_loop_probe(interface); + __cvmx_helper_loop_enumerate(interface); break; } @@ -313,6 +308,74 @@ int cvmx_helper_interface_probe(int interface) } /** + * This function probes an interface to determine the actual + * number of hardware ports connected to it. It doesn't setup the + * ports or enable them. The main goal here is to set the global + * interface_port_count[interface] correctly. Hardware setup of the + * ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_interface_probe(int interface) +{ + cvmx_helper_interface_enumerate(interface); + /* At this stage in the game we don't want packets to be moving yet. + The following probe calls should perform hardware setup + needed to determine port counts. Receive must still be disabled */ + switch (cvmx_helper_interface_get_mode(interface)) { + /* These types don't support ports to IPD/PKO */ + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + break; + /* XAUI is a single high speed port */ + case CVMX_HELPER_INTERFACE_MODE_XAUI: + __cvmx_helper_xaui_probe(interface); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII. + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + __cvmx_helper_rgmii_probe(interface); + break; + /* + * SPI4 can have 1-16 ports depending on the device at + * the other end. + */ + case CVMX_HELPER_INTERFACE_MODE_SPI: + __cvmx_helper_spi_probe(interface); + break; + /* + * SGMII can have 1-4 ports depending on how many are + * hooked up. + */ + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + __cvmx_helper_sgmii_probe(interface); + break; + /* PCI target Network Packet Interface */ + case CVMX_HELPER_INTERFACE_MODE_NPI: + __cvmx_helper_npi_probe(interface); + break; + /* + * Special loopback only ports. These are not the same + * as other ports in loopback mode. + */ + case CVMX_HELPER_INTERFACE_MODE_LOOP: + __cvmx_helper_loop_probe(interface); + break; + } + + /* Make sure all global variables propagate to other cores */ + CVMX_SYNCWS; + + return 0; +} + +/** * Setup the IPD/PIP for the ports on an interface. Packet * classification and tagging are set for every port on the * interface. The number of ports on the interface must already diff --git a/arch/mips/include/asm/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h index e646a6c..0a2488e 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-loop.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h @@ -44,6 +44,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_loop_probe(int interface); +static inline int __cvmx_helper_loop_enumerate(int interface) {return 4;} /** * Bringup and enable a LOOP interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h index 908e7b0..8df4c7f 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-npi.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_npi_probe(int interface); +#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe /** * Bringup and enable a NPI interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h index ea26526..78295ba 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h @@ -43,6 +43,7 @@ * Returns Number of RGMII/GMII/MII ports (0-4). */ extern int __cvmx_helper_rgmii_probe(int interface); +#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe /** * Put an RGMII interface in loopback mode. Internal packets sent diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h index 19b48d6..9a9b6c1 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_sgmii_probe(int interface); +extern int __cvmx_helper_sgmii_enumerate(int interface); /** * Bringup and enable a SGMII interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h index 69bac03..9f1c6b9 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-spi.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h @@ -42,6 +42,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_spi_probe(int interface); +extern int __cvmx_helper_spi_enumerate(int interface); /** * Bringup and enable a SPI interface. After this call packet I/O diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h index 4b4db2f..f6fbc4f 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_xaui_probe(int interface); +extern int __cvmx_helper_xaui_enumerate(int interface); /** * Bringup and enable a XAUI interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h index 51916f3..3169cd7 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper.h +++ b/arch/mips/include/asm/octeon/cvmx-helper.h @@ -207,6 +207,7 @@ extern int cvmx_helper_link_set(int ipd_port, * Returns Zero on success, negative on failure */ extern int cvmx_helper_interface_probe(int interface); +extern int cvmx_helper_interface_enumerate(int interface); /** * Configure a port for internal and/or external loopback. Internal loopback -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:45:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:46:02 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11828 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491991Ab1CDTmy (ORCPT ); Fri, 4 Mar 2011 20:42:54 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:47 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:52 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24Jgl4f017366; Fri, 4 Mar 2011 11:42:47 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24Jgl7T017365; Fri, 4 Mar 2011 11:42:47 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH v2 08/12] MIPS: Octeon: Initialize and fixup device tree. Date: Fri, 4 Mar 2011 11:42:20 -0800 Message-Id: <1299267744-17278-9-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:52.0810 (UTC) FILETIME=[59E89EA0:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29354 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/octeon-platform.c | 234 +++++++++++++++++++++++++++++ arch/mips/cavium-octeon/setup.c | 17 ++ 3 files changed, 252 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4baf7f2..021be61 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1355,6 +1355,7 @@ config CPU_CAVIUM_OCTEON select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES select GENERIC_HARDIRQS_NO_DEPRECATED + select LIBFDT help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index cecaf62..87512c5 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -13,10 +13,16 @@ #include #include #include +#include #include +#include +#include +#include #include #include +#include +#include static struct octeon_cf_data octeon_cf_data; @@ -440,6 +446,234 @@ device_initcall(octeon_ohci_device_init); #endif /* CONFIG_USB */ +static struct of_device_id __initdata octeon_ids[] = { + { .name = "soc@0", }, + { .compatible = "simple-bus", }, + {}, +}; + +static void __init octeon_fdt_set_phy(int eth, int phy_addr) +{ + const __be32 *phy_handle; + const __be32 *reg; + struct fdt_node_header *raw_node; + u32 phandle; + int phy; + char new_address[3]; + char *cp; + + phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); + if (!phy_handle) + return; + + phandle = be32_to_cpup(phy_handle); + phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); + if (phy_addr < 0 || phy < 0) { + /* Delete the PHY things */ + if (phy >= 0) + fdt_nop_node(initial_boot_params, phy); + fdt_nop_property(initial_boot_params, eth, "phy-handle"); + return; + } + + reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); + if (phy_addr == be32_to_cpup(reg)) + return; + + fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); + + snprintf(new_address, sizeof(new_address), "%x", phy_addr); + /* + * All PHYs in the template have a name like 'ethernet-phy@0', + * that is 14 characters, which allows us to replace the + * address portion with up to two characters without + * clobbering things past a multiple of 4 boundry. + */ + raw_node = (void *)fdt_offset_ptr(initial_boot_params, phy, 0); + cp = strchr(raw_node->name, '@'); + if (!cp) + return; + cp++; + cp[0] = new_address[0]; + cp[1] = new_address[1]; + +} + +static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) +{ + u8 new_mac[6]; + u64 mac = *pmac; + int r; + + new_mac[0] = (mac >> 40) & 0xff; + new_mac[1] = (mac >> 32) & 0xff; + new_mac[2] = (mac >> 24) & 0xff; + new_mac[3] = (mac >> 16) & 0xff; + new_mac[4] = (mac >> 8) & 0xff; + new_mac[5] = mac & 0xff; + + r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", + new_mac, sizeof(new_mac)); + + if (r) { + pr_err("Setting \"local-mac-address\" failed %d", r); + return; + } + *pmac = mac + 1; +} + +static void __init octeon_fdt_rm_ethernet(int node) +{ + const __be32 *phy_handle; + + phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); + if (phy_handle) { + u32 ph = be32_to_cpup(phy_handle); + int p = fdt_node_offset_by_phandle(initial_boot_params, ph); + if (p >= 0) + fdt_nop_node(initial_boot_params, p); + } + fdt_nop_node(initial_boot_params, node); +} + +static void __init octeon_fdt_pip_port(int iface, int i, int p, u64 *pmac) +{ + char name_buffer[20]; + int eth; + int phy_addr; + + snprintf(name_buffer, sizeof(name_buffer), "ethernet@%d", p); + eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); + if (eth < 0) + return; + if (p >= cvmx_helper_ports_on_interface(i)) { + pr_notice("Deleting port %x:%x\n", i, p); + octeon_fdt_rm_ethernet(eth); + return; + } + + phy_addr = cvmx_helper_board_get_mii_address(16 * i + p); + octeon_fdt_set_phy(eth, phy_addr); + octeon_fdt_set_mac_addr(eth, pmac); +} + +static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) +{ + char name_buffer[20]; + int iface; + int p; + + cvmx_helper_interface_enumerate(idx); + snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); + iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); + if (iface < 0) + return; + + for (p = 0; p < 4; p++) + octeon_fdt_pip_port(iface, idx, p, pmac); +} + +int __init octeon_prune_device_tree(void) +{ + int i, max_port; + const char *pip_path; + char name_buffer[20]; + int aliases; + u64 mac_addr_base; + + if (fdt_check_header(initial_boot_params)) + panic("Corrupt Device Tree."); + + aliases = fdt_path_offset(initial_boot_params, "/aliases"); + if (aliases < 0) { + pr_err("Error: No /aliases node in device tree."); + return -EINVAL; + } + + + mac_addr_base = + ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | + ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | + ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | + ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | + ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | + (octeon_bootinfo->mac_addr_base[5] & 0xffull); + + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) + max_port = 2; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 1; + else + max_port = 0; + + for (i = 0; i < 2; i++) { + const char *alias_prop; + int mgmt; + snprintf(name_buffer, sizeof(name_buffer), + "mix%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + if (alias_prop) { + mgmt = fdt_path_offset(initial_boot_params, alias_prop); + if (mgmt < 0) + continue; + if (i >= max_port) { + pr_notice("Deleting mix%d\n", i); + octeon_fdt_rm_ethernet(mgmt); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } else { + octeon_fdt_set_phy(mgmt, i); + octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); + } + } + } + + pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); + if (pip_path) { + int pip = fdt_path_offset(initial_boot_params, pip_path); + if (pip >= 0) + for (i = 0; i < 4; i++) + octeon_fdt_pip_iface(pip, i, &mac_addr_base); + } + + /* I2C */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + const char *alias_prop; + int i2c; + snprintf(name_buffer, sizeof(name_buffer), + "twsi%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + i2c = fdt_path_offset(initial_boot_params, alias_prop); + if (i2c < 0) + continue; + if (i >= max_port) { + pr_notice("Deleting i2c%d\n", i); + fdt_nop_node(initial_boot_params, i2c); + } + } + } + + return 0; +} + +static int __init octeon_publish_devices(void) +{ + return of_platform_bus_probe(NULL, octeon_ids, NULL); +} +device_initcall(octeon_publish_devices); + + MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index ab1a106..02765d6 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #ifdef CONFIG_BLK_DEV_INITRD #include #endif @@ -797,3 +798,19 @@ void prom_free_prom_memory(void) } #endif } + +int octeon_prune_device_tree(void); + +extern const char __dtb_octeon_3xxx_begin; +extern const char __dtb_octeon_3xxx_end; +void __init device_tree_init(void) +{ + int dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; + /* Copy the default tree from init memory. */ + initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); + if (initial_boot_params == NULL) + panic("Could not allocate initial_boot_params\n"); + memcpy(initial_boot_params, &__dtb_octeon_3xxx_begin, dt_size); + octeon_prune_device_tree(); + unflatten_device_tree(); +} -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:46:21 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:46:27 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11837 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491994Ab1CDTnA (ORCPT ); Fri, 4 Mar 2011 20:43:00 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:52 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:58 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:58 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24JgoPl017370; Fri, 4 Mar 2011 11:42:50 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgmwH017369; Fri, 4 Mar 2011 11:42:48 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney , "Jean Delvare (PC drivers, core)" , "Ben Dooks (embedded platforms)" , linux-i2c@vger.kernel.org Subject: [RFC PATCH v2 09/12] i2c: Convert i2c-octeon.c to use device tree. Date: Fri, 4 Mar 2011 11:42:21 -0800 Message-Id: <1299267744-17278-10-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:58.0451 (UTC) FILETIME=[5D455E30:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29355 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney Cc: "Jean Delvare (PC drivers, core)" Cc: "Ben Dooks (embedded platforms)" Cc: linux-i2c@vger.kernel.org --- arch/mips/cavium-octeon/octeon-platform.c | 84 ----------------------------- arch/mips/include/asm/octeon/octeon.h | 5 -- drivers/i2c/busses/i2c-octeon.c | 69 ++++++++++++++---------- 3 files changed, 41 insertions(+), 117 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 87512c5..0533351 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,90 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -static struct i2c_board_info __initdata octeon_i2c_devices[] = { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static int __init octeon_i2c_devices_init(void) -{ - return i2c_register_board_info(0, octeon_i2c_devices, - ARRAY_SIZE(octeon_i2c_devices)); -} -arch_initcall(octeon_i2c_devices_init); - -#define OCTEON_I2C_IO_BASE 0x1180000001000ull -#define OCTEON_I2C_IO_UNIT_OFFSET 0x200 - -static struct octeon_i2c_data octeon_i2c_data[2]; - -static int __init octeon_i2c_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource i2c_resources[] = { - { - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, - } - }; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) - num_ports = 2; - else - num_ports = 1; - - for (port = 0; port < num_ports; port++) { - octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate(); - /*FIXME: should be examined. At the moment is set for 100Khz */ - octeon_i2c_data[port].i2c_freq = 100000; - - pd = platform_device_alloc("i2c-octeon", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - pd->dev.platform_data = octeon_i2c_data + port; - - i2c_resources[0].start = - OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET); - i2c_resources[0].end = i2c_resources[0].start + 0x1f; - switch (port) { - case 0: - i2c_resources[1].start = OCTEON_IRQ_TWSI; - i2c_resources[1].end = OCTEON_IRQ_TWSI; - break; - case 1: - i2c_resources[1].start = OCTEON_IRQ_TWSI2; - i2c_resources[1].end = OCTEON_IRQ_TWSI2; - break; - default: - BUG(); - } - - ret = platform_device_add_resources(pd, - i2c_resources, - ARRAY_SIZE(i2c_resources)); - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); -out: - return ret; -} -device_initcall(octeon_i2c_device_init); - /* Octeon SMI/MDIO interface. */ static int __init octeon_mdiobus_device_init(void) { diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index f72f768..1e2486e 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -215,11 +215,6 @@ struct octeon_cf_data { int dma_engine; /* -1 for no DMA */ }; -struct octeon_i2c_data { - unsigned int sys_freq; - unsigned int i2c_freq; -}; - extern void octeon_write_lcd(const char *s); extern void octeon_check_cpu_bist(void); extern int octeon_get_boot_debug_flag(void); diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c index 56dbe54..cb34725 100644 --- a/drivers/i2c/busses/i2c-octeon.c +++ b/drivers/i2c/busses/i2c-octeon.c @@ -2,7 +2,7 @@ * (C) Copyright 2009-2010 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com * - * Portions Copyright (C) 2010 Cavium Networks, Inc. + * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc. * * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors. * @@ -11,17 +11,18 @@ * warranty of any kind, whether express or implied. */ +#include +#include #include #include +#include +#include #include #include #include - -#include #include -#include -#include -#include +#include +#include #include @@ -121,10 +122,8 @@ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg) */ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) { - u64 tmp; - __raw_writeq(data, i2c->twsi_base + TWSI_INT); - tmp = __raw_readq(i2c->twsi_base + TWSI_INT); + __raw_readq(i2c->twsi_base + TWSI_INT); } /** @@ -515,22 +514,22 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) { int irq, result = 0; struct octeon_i2c *i2c; - struct octeon_i2c_data *i2c_data; struct resource *res_mem; + const __be32 *data; + int len; /* All adaptors have an irq. */ irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; - i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); if (!i2c) { dev_err(&pdev->dev, "kzalloc failed\n"); result = -ENOMEM; goto out; } i2c->dev = &pdev->dev; - i2c_data = pdev->dev.platform_data; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -539,19 +538,22 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) result = -ENXIO; goto fail_region; } + i2c->twsi_phys = res_mem->start; + i2c->regsize = resource_size(res_mem); - if (i2c_data == NULL) { - dev_err(i2c->dev, "no I2C frequency data\n"); + data = of_get_property(pdev->dev.of_node, "clock-rate", &len); + if (data && len == sizeof(*data)) { + i2c->twsi_freq = be32_to_cpup(data); + } else { + dev_err(i2c->dev, "no I2C 'clock-rate' property\n"); result = -ENXIO; goto fail_region; } - i2c->twsi_phys = res_mem->start; - i2c->regsize = resource_size(res_mem); - i2c->twsi_freq = i2c_data->i2c_freq; - i2c->sys_freq = i2c_data->sys_freq; + i2c->sys_freq = octeon_get_io_clock_rate(); - if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) { + if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize, + res_mem->name)) { dev_err(i2c->dev, "request_mem_region failed\n"); goto fail_region; } @@ -581,28 +583,31 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) i2c->adap = octeon_i2c_ops; i2c->adap.dev.parent = &pdev->dev; - i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0; + i2c->adap.dev.of_node = pdev->dev.of_node; i2c_set_adapdata(&i2c->adap, i2c); platform_set_drvdata(pdev, i2c); - result = i2c_add_numbered_adapter(&i2c->adap); + result = i2c_add_adapter(&i2c->adap); if (result < 0) { dev_err(i2c->dev, "failed to add adapter\n"); goto fail_add; } - dev_info(i2c->dev, "version %s\n", DRV_VERSION); - return result; + of_i2c_register_devices(&i2c->adap); + + return 0; fail_add: platform_set_drvdata(pdev, NULL); free_irq(i2c->irq, i2c); fail_irq: iounmap(i2c->twsi_base); - release_mem_region(i2c->twsi_phys, i2c->regsize); + + devm_release_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize); fail_region: - kfree(i2c); + + devm_kfree(&pdev->dev, i2c); out: return result; }; @@ -615,17 +620,26 @@ static int __devexit octeon_i2c_remove(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); free_irq(i2c->irq, i2c); iounmap(i2c->twsi_base); - release_mem_region(i2c->twsi_phys, i2c->regsize); - kfree(i2c); + devm_release_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize); + devm_kfree(&pdev->dev, i2c); return 0; }; +static struct of_device_id octeon_i2c_match[] = { + { + .compatible = "cavium,octeon-3860-twsi", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_i2c_match); + static struct platform_driver octeon_i2c_driver = { .probe = octeon_i2c_probe, .remove = __devexit_p(octeon_i2c_remove), .driver = { .owner = THIS_MODULE, .name = DRV_NAME, + .of_match_table = octeon_i2c_match, }, }; @@ -646,7 +660,6 @@ MODULE_AUTHOR("Michael Lawnick "); MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_VERSION); -MODULE_ALIAS("platform:" DRV_NAME); module_init(octeon_i2c_init); module_exit(octeon_i2c_exit); -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:46:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:46:50 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11853 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491997Ab1CDTnB (ORCPT ); Fri, 4 Mar 2011 20:43:01 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:54 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:59 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:42:59 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24Jgs5F017374; Fri, 4 Mar 2011 11:42:54 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgsGd017373; Fri, 4 Mar 2011 11:42:54 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney , "David S. Miller" , netdev@vger.kernel.org Subject: [RFC PATCH v2 10/12] netdev: mdio-octeon.c: Convert to use device tree. Date: Fri, 4 Mar 2011 11:42:22 -0800 Message-Id: <1299267744-17278-11-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:42:59.0872 (UTC) FILETIME=[5E1E3200:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29356 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Get the MDIO bus controller addresses from the device tree. Signed-off-by: David Daney Cc: "David S. Miller" Cc: netdev@vger.kernel.org --- arch/mips/cavium-octeon/octeon-platform.c | 30 --------- drivers/net/phy/mdio-octeon.c | 92 +++++++++++++++++++--------- 2 files changed, 62 insertions(+), 60 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 0533351..ce471bd 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,36 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -/* Octeon SMI/MDIO interface. */ -static int __init octeon_mdiobus_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - - if (octeon_is_simulation()) - return 0; /* No mdio in the simulator. */ - - /* The bus number is the platform_device id. */ - pd = platform_device_alloc("mdio-octeon", 0); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - ret = platform_device_add(pd); - if (ret) - goto fail; - - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mdiobus_device_init); - /* Octeon mgmt port Ethernet interface. */ static int __init octeon_mgmt_device_init(void) { diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c index bd12ba9..dd33023 100644 --- a/drivers/net/phy/mdio-octeon.c +++ b/drivers/net/phy/mdio-octeon.c @@ -3,13 +3,15 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2009 Cavium Networks + * Copyright (C) 2009, 2010, 2011 Cavium Networks */ -#include -#include -#include #include +#include +#include +#include +#include +#include #include #include @@ -18,9 +20,17 @@ #define DRV_VERSION "1.0" #define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver" +#define SMI_CMD 0x0 +#define SMI_WR_DAT 0x8 +#define SMI_RD_DAT 0x10 +#define SMI_CLK 0x18 +#define SMI_EN 0x20 + struct octeon_mdiobus { struct mii_bus *mii_bus; - int unit; + u64 register_base; + resource_size_t mdio_phys; + resource_size_t regsize; int phy_irq[PHY_MAX_ADDR]; }; @@ -35,15 +45,15 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum) smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); + cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - cvmx_wait(1000); - smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit)); + __delay(1000); + smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT); } while (smi_rd.s.pending && --timeout); if (smi_rd.s.val) @@ -62,21 +72,21 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, smi_wr.u64 = 0; smi_wr.s.dat = val; - cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64); + cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64); smi_cmd.u64 = 0; smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); + cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - cvmx_wait(1000); - smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit)); + __delay(1000); + smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT); } while (smi_wr.s.pending && --timeout); if (timeout <= 0) @@ -88,8 +98,8 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) { struct octeon_mdiobus *bus; + struct resource *res_mem; union cvmx_smix_en smi_en; - int i; int err = -ENOENT; bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); @@ -97,28 +107,36 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) return -ENOMEM; /* The platform_device id is our unit number. */ - bus->unit = pdev->id; + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (res_mem == NULL) { + dev_err(&pdev->dev, "found no memory resource\n"); + err = -ENXIO; + goto fail_region; + } + bus->mdio_phys = res_mem->start; + bus->regsize = resource_size(res_mem); + if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize, + res_mem->name)) { + dev_err(&pdev->dev, "request_mem_region failed\n"); + goto fail_region; + } + bus->register_base = (u64)ioremap(bus->mdio_phys, bus->regsize); bus->mii_bus = mdiobus_alloc(); if (!bus->mii_bus) - goto err; + goto fail_mdio_alloc; smi_en.u64 = 0; smi_en.s.en = 1; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); - /* - * Standard Octeon evaluation boards don't support phy - * interrupts, we need to poll. - */ - for (i = 0; i < PHY_MAX_ADDR; i++) - bus->phy_irq[i] = PHY_POLL; bus->mii_bus->priv = bus; bus->mii_bus->irq = bus->phy_irq; bus->mii_bus->name = "mdio-octeon"; - snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%x", bus->unit); + snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base); bus->mii_bus->parent = &pdev->dev; bus->mii_bus->read = octeon_mdiobus_read; @@ -126,20 +144,23 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, bus); - err = mdiobus_register(bus->mii_bus); + err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node); if (err) - goto err_register; + goto fail_register; dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); return 0; -err_register: +fail_register: mdiobus_free(bus->mii_bus); -err: - devm_kfree(&pdev->dev, bus); +fail_mdio_alloc: + devm_release_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize); + +fail_region: smi_en.u64 = 0; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + devm_kfree(&pdev->dev, bus); return err; } @@ -152,15 +173,26 @@ static int __devexit octeon_mdiobus_remove(struct platform_device *pdev) mdiobus_unregister(bus->mii_bus); mdiobus_free(bus->mii_bus); + devm_release_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize); smi_en.u64 = 0; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + devm_kfree(&pdev->dev, bus); return 0; } +static struct of_device_id octeon_mdiobus_match[] = { + { + .compatible = "cavium,octeon-3860-mdio", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mdiobus_match); + static struct platform_driver octeon_mdiobus_driver = { .driver = { .name = "mdio-octeon", .owner = THIS_MODULE, + .of_match_table = octeon_mdiobus_match, }, .probe = octeon_mdiobus_probe, .remove = __devexit_p(octeon_mdiobus_remove), -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:47:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:47:16 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11861 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491998Ab1CDTnD (ORCPT ); Fri, 4 Mar 2011 20:43:03 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:55 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:43:01 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:43:01 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24Jgtjt017378; Fri, 4 Mar 2011 11:42:56 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24JgtxT017377; Fri, 4 Mar 2011 11:42:55 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney , "David S. Miller" , netdev@vger.kernel.org Subject: [RFC PATCH v2 11/12] netdev: octeon_mgmt: Convert to use device tree. Date: Fri, 4 Mar 2011 11:42:23 -0800 Message-Id: <1299267744-17278-12-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:43:01.0138 (UTC) FILETIME=[5EDF5F20:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29357 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The device tree will supply the register bank base addresses, make register addressing relative to those. PHY connection is now described by the device tree. Signed-off-by: David Daney Cc: "David S. Miller" Cc: netdev@vger.kernel.org --- arch/mips/cavium-octeon/octeon-platform.c | 62 ------ drivers/net/octeon/octeon_mgmt.c | 321 +++++++++++++++++++---------- 2 files changed, 217 insertions(+), 166 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index ce471bd..104713c 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,68 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -/* Octeon mgmt port Ethernet interface. */ -static int __init octeon_mgmt_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource mgmt_port_resource = { - .flags = IORESOURCE_IRQ, - .start = -1, - .end = -1 - }; - - if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX)) - return 0; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - num_ports = 1; - else - num_ports = 2; - - for (port = 0; port < num_ports; port++) { - pd = platform_device_alloc("octeon_mgmt", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - /* No DMA restrictions */ - pd->dev.coherent_dma_mask = DMA_BIT_MASK(64); - pd->dev.dma_mask = &pd->dev.coherent_dma_mask; - - switch (port) { - case 0: - mgmt_port_resource.start = OCTEON_IRQ_MII0; - break; - case 1: - mgmt_port_resource.start = OCTEON_IRQ_MII1; - break; - default: - BUG(); - } - mgmt_port_resource.end = mgmt_port_resource.start; - - ret = platform_device_add_resources(pd, &mgmt_port_resource, 1); - - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mgmt_device_init); - #ifdef CONFIG_USB static int __init octeon_ehci_device_init(void) diff --git a/drivers/net/octeon/octeon_mgmt.c b/drivers/net/octeon/octeon_mgmt.c index b264f0f..17be326 100644 --- a/drivers/net/octeon/octeon_mgmt.c +++ b/drivers/net/octeon/octeon_mgmt.c @@ -6,16 +6,18 @@ * Copyright (C) 2009 Cavium Networks */ -#include -#include -#include #include -#include +#include #include +#include +#include +#include #include +#include +#include +#include #include #include -#include #include #include @@ -55,8 +57,56 @@ union mgmt_port_ring_entry { } s; }; +#define MIX_ORING1 0x0 +#define MIX_ORING2 0x8 +#define MIX_IRING1 0x10 +#define MIX_IRING2 0x18 +#define MIX_CTL 0x20 +#define MIX_IRHWM 0x28 +#define MIX_IRCNT 0x30 +#define MIX_ORHWM 0x38 +#define MIX_ORCNT 0x40 +#define MIX_ISR 0x48 +#define MIX_INTENA 0x50 +#define MIX_REMCNT 0x58 +#define MIX_BIST 0x78 + +#define AGL_GMX_PRT_CFG 0x10 +#define AGL_GMX_RX_FRM_CTL 0x18 +#define AGL_GMX_RX_FRM_MAX 0x30 +#define AGL_GMX_RX_JABBER 0x38 +#define AGL_GMX_RX_STATS_CTL 0x50 + +#define AGL_GMX_RX_STATS_PKTS_DRP 0xb0 +#define AGL_GMX_RX_STATS_OCTS_DRP 0xb8 +#define AGL_GMX_RX_STATS_PKTS_BAD 0xc0 + +#define AGL_GMX_RX_ADR_CTL 0x100 +#define AGL_GMX_RX_ADR_CAM_EN 0x108 +#define AGL_GMX_RX_ADR_CAM0 0x180 +#define AGL_GMX_RX_ADR_CAM1 0x188 +#define AGL_GMX_RX_ADR_CAM2 0x190 +#define AGL_GMX_RX_ADR_CAM3 0x198 +#define AGL_GMX_RX_ADR_CAM4 0x1a0 +#define AGL_GMX_RX_ADR_CAM5 0x1a8 + +#define AGL_GMX_TX_STATS_CTL 0x268 +#define AGL_GMX_TX_CTL 0x270 +#define AGL_GMX_TX_STAT0 0x280 +#define AGL_GMX_TX_STAT1 0x288 +#define AGL_GMX_TX_STAT2 0x290 +#define AGL_GMX_TX_STAT3 0x298 +#define AGL_GMX_TX_STAT4 0x2a0 +#define AGL_GMX_TX_STAT5 0x2a8 +#define AGL_GMX_TX_STAT6 0x2b0 +#define AGL_GMX_TX_STAT7 0x2b8 +#define AGL_GMX_TX_STAT8 0x2c0 +#define AGL_GMX_TX_STAT9 0x2c8 + struct octeon_mgmt { struct net_device *netdev; + u64 mix; + u64 agl; int port; int irq; u64 *tx_ring; @@ -82,31 +132,34 @@ struct octeon_mgmt { struct napi_struct napi; struct tasklet_struct tx_clean_tasklet; struct phy_device *phydev; + struct device_node *phy_np; + resource_size_t mix_phys; + resource_size_t mix_size; + resource_size_t agl_phys; + resource_size_t agl_size; }; static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) { - int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); + mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); mix_intena.s.ithena = enable ? 1 : 0; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) { - int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); + mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); mix_intena.s.othena = enable ? 1 : 0; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -143,7 +196,6 @@ static unsigned int ring_size_to_bytes(unsigned int ring_size) static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) { unsigned int size; @@ -174,24 +226,23 @@ static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE; p->rx_current_fill++; /* Ring the bell. */ - cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); + cvmx_write_csr(p->mix + MIX_IRING2, 1); } } static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) { - int port = p->port; union cvmx_mixx_orcnt mix_orcnt; union mgmt_port_ring_entry re; struct sk_buff *skb; int cleaned = 0; unsigned long flags; - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); while (mix_orcnt.s.orcnt) { spin_lock_irqsave(&p->tx_list.lock, flags); - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); if (mix_orcnt.s.orcnt == 0) { spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -211,7 +262,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) mix_orcnt.s.orcnt = 1; /* Acknowledge to hardware that we have the buffer. */ - cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64); + cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); p->tx_current_fill--; spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -221,7 +272,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) dev_kfree_skb_any(skb); cleaned++; - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); } if (cleaned && netif_queue_stopped(p->netdev)) @@ -238,13 +289,12 @@ static void octeon_mgmt_clean_tx_tasklet(unsigned long arg) static void octeon_mgmt_update_rx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; unsigned long flags; u64 drop, bad; /* These reads also clear the count registers. */ - drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port)); - bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port)); + drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP); + bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD); if (drop || bad) { /* Do an atomic update. */ @@ -258,15 +308,14 @@ static void octeon_mgmt_update_rx_stats(struct net_device *netdev) static void octeon_mgmt_update_tx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; unsigned long flags; union cvmx_agl_gmx_txx_stat0 s0; union cvmx_agl_gmx_txx_stat1 s1; /* These reads also clear the count registers. */ - s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port)); - s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port)); + s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); + s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1); if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { /* Do an atomic update. */ @@ -305,7 +354,6 @@ static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p, static int octeon_mgmt_receive_one(struct octeon_mgmt *p) { - int port = p->port; struct net_device *netdev = p->netdev; union cvmx_mixx_ircnt mix_ircnt; union mgmt_port_ring_entry re; @@ -378,18 +426,17 @@ done: /* Tell the hardware we processed a packet. */ mix_ircnt.u64 = 0; mix_ircnt.s.ircnt = 1; - cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64); + cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); return rc; } static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) { - int port = p->port; unsigned int work_done = 0; union cvmx_mixx_ircnt mix_ircnt; int rc; - mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); + mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); while (work_done < budget && mix_ircnt.s.ircnt) { rc = octeon_mgmt_receive_one(p); @@ -397,7 +444,7 @@ static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) work_done++; /* Check for more packets. */ - mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); + mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); } octeon_mgmt_rx_fill_ring(p->netdev); @@ -431,16 +478,16 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) union cvmx_agl_gmx_bist agl_gmx_bist; mix_ctl.u64 = 0; - cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); } while (mix_ctl.s.busy); mix_ctl.s.reset = 1; - cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); - cvmx_read_csr(CVMX_MIXX_CTL(p->port)); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); + cvmx_read_csr(p->mix + MIX_CTL); cvmx_wait(64); - mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port)); + mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); if (mix_bist.u64) dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n", (unsigned long long)mix_bist.u64); @@ -471,7 +518,6 @@ static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs, static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_agl_gmx_rxx_adr_ctl adr_ctl; union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx; unsigned long flags; @@ -517,29 +563,29 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) spin_lock_irqsave(&p->lock, flags); /* Disable packet I/O. */ - agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prev_packet_enable = agl_gmx_prtx.s.en; agl_gmx_prtx.s.en = 0; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); adr_ctl.u64 = 0; adr_ctl.s.cam_mode = cam_mode; adr_ctl.s.mcst = multicast_mode; adr_ctl.s.bcst = 1; /* Allow broadcast */ - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask); /* Restore packet I/O. */ agl_gmx_prtx.s.en = prev_packet_enable; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -561,7 +607,6 @@ static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; /* @@ -577,8 +622,8 @@ static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) netdev->mtu = new_mtu; - cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs); - cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, size_without_fcs); + cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER, (size_without_fcs + 7) & 0xfff8); return 0; @@ -588,14 +633,13 @@ static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) { struct net_device *netdev = dev_id; struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_mixx_isr mixx_isr; - mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port)); + mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR); /* Clear any pending interrupts */ - cvmx_write_csr(CVMX_MIXX_ISR(port), mixx_isr.u64); - cvmx_read_csr(CVMX_MIXX_ISR(port)); + cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64); + cvmx_read_csr(p->mix + MIX_ISR); if (mixx_isr.s.irthresh) { octeon_mgmt_disable_rx_irq(p); @@ -626,7 +670,6 @@ static int octeon_mgmt_ioctl(struct net_device *netdev, static void octeon_mgmt_adjust_link(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_agl_gmx_prtx_cfg prtx_cfg; unsigned long flags; int link_changed = 0; @@ -637,11 +680,9 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) link_changed = 1; if (p->last_duplex != p->phydev->duplex) { p->last_duplex = p->phydev->duplex; - prtx_cfg.u64 = - cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.duplex = p->phydev->duplex; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), - prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); } } else { if (p->last_link) @@ -667,18 +708,16 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) static int octeon_mgmt_init_phy(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - char phy_id[20]; - if (octeon_is_simulation()) { + if (octeon_is_simulation() || p->phy_np == NULL) { /* No PHYs in the simulator. */ netif_carrier_on(netdev); return 0; } - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", p->port); - - p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0, - PHY_INTERFACE_MODE_MII); + p->phydev = of_phy_connect(netdev, p->phy_np, + octeon_mgmt_adjust_link, 0, + PHY_INTERFACE_MODE_MII); if (IS_ERR(p->phydev)) { p->phydev = NULL; @@ -734,14 +773,14 @@ static int octeon_mgmt_open(struct net_device *netdev) octeon_mgmt_reset_hw(p); - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); /* Bring it out of reset if needed. */ if (mix_ctl.s.reset) { mix_ctl.s.reset = 0; - cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); } while (mix_ctl.s.reset); } @@ -752,17 +791,17 @@ static int octeon_mgmt_open(struct net_device *netdev) oring1.u64 = 0; oring1.s.obase = p->tx_ring_handle >> 3; oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE; - cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64); + cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64); iring1.u64 = 0; iring1.s.ibase = p->rx_ring_handle >> 3; iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; - cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64); + cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); /* Disable packet I/O. */ - prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.en = 0; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); octeon_mgmt_set_mac_address(netdev, &sa); @@ -779,7 +818,7 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_ctl.s.nbtarb = 0; /* Arbitration mode */ /* MII CB-request FIFO programmable high watermark */ mix_ctl.s.mrq_hwm = 1; - cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { @@ -806,16 +845,16 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Clear statistics. */ /* Clear on read. */ - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1); - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0); - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0); + cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1); + cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0); + cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0); /* Clear any pending interrupts */ - cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port))); + cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name, netdev)) { @@ -826,18 +865,18 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Interrupt every single RX packet */ mix_irhwm.u64 = 0; mix_irhwm.s.irhwm = 0; - cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64); + cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64); /* Interrupt when we have 1 or more packets to clean. */ mix_orhwm.u64 = 0; mix_orhwm.s.orhwm = 1; - cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64); + cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); /* Enable receive and transmit interrupts */ mix_intena.u64 = 0; mix_intena.s.ithena = 1; mix_intena.s.othena = 1; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); /* Enable packet I/O. */ @@ -868,7 +907,7 @@ static int octeon_mgmt_open(struct net_device *netdev) * frame. GMX checks that the PREAMBLE is sent correctly. */ rxx_frm_ctl.s.pre_chk = 1; - cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); /* Enable the AGL block */ agl_gmx_inf_mode.u64 = 0; @@ -876,13 +915,13 @@ static int octeon_mgmt_open(struct net_device *netdev) cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); /* Configure the port duplex and enables */ - prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.tx_en = 1; prtx_cfg.s.rx_en = 1; prtx_cfg.s.en = 1; p->last_duplex = 1; prtx_cfg.s.duplex = p->last_duplex; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); p->last_link = 0; netif_carrier_off(netdev); @@ -946,7 +985,6 @@ static int octeon_mgmt_stop(struct net_device *netdev) static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union mgmt_port_ring_entry re; unsigned long flags; int rv = NETDEV_TX_BUSY; @@ -990,7 +1028,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) netdev->stats.tx_bytes += skb->len; /* Ring the bell. */ - cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); + cvmx_write_csr(p->mix + MIX_ORING2, 1); rv = NETDEV_TX_OK; out: @@ -1069,10 +1107,14 @@ static const struct net_device_ops octeon_mgmt_ops = { static int __devinit octeon_mgmt_probe(struct platform_device *pdev) { - struct resource *res_irq; struct net_device *netdev; struct octeon_mgmt *p; - int i; + const __be32 *data; + const u8 *mac; + struct resource *res_mix; + struct resource *res_agl; + int len; + int result; netdev = alloc_etherdev(sizeof(struct octeon_mgmt)); if (netdev == NULL) @@ -1086,14 +1128,63 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) p->netdev = netdev; p->dev = &pdev->dev; - p->port = pdev->id; + data = of_get_property(pdev->dev.of_node, "cell-index", &len); + if (data && len == sizeof(*data)) { + p->port = be32_to_cpup(data); + } else { + dev_err(&pdev->dev, "no 'cell-index' property\n"); + result = -ENXIO; + goto err; + } + snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port); - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_irq) + result = platform_get_irq(pdev, 0); + if (result < 0) + goto err; + + p->irq = result; + + res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res_mix == NULL) { + dev_err(&pdev->dev, "no 'reg' resource\n"); + result = -ENXIO; + goto err; + } + + res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res_agl == NULL) { + dev_err(&pdev->dev, "no 'reg' resource\n"); + result = -ENXIO; goto err; + } + + p->mix_phys = res_mix->start; + p->mix_size = resource_size(res_mix); + p->agl_phys = res_agl->start; + p->agl_size = resource_size(res_agl); + + + if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size, + res_mix->name)) { + dev_err(&pdev->dev, "request_mem_region (%s) failed\n", + res_mix->name); + result = -ENXIO; + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size, + res_agl->name)) { + result = -ENXIO; + dev_err(&pdev->dev, "request_mem_region (%s) failed\n", + res_agl->name); + goto fail_region1; + } + + + p->mix = (u64)ioremap(p->mix_phys, p->mix_size); + p->agl = (u64)ioremap(p->agl_phys, p->agl_size); - p->irq = res_irq->start; spin_lock_init(&p->lock); skb_queue_head_init(&p->tx_list); @@ -1104,39 +1195,61 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) netdev->netdev_ops = &octeon_mgmt_ops; netdev->ethtool_ops = &octeon_mgmt_ethtool_ops; - /* The mgmt ports get the first N MACs. */ - for (i = 0; i < 6; i++) - netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i]; - netdev->dev_addr[5] += p->port; + mac = of_get_mac_address(pdev->dev.of_node); - if (p->port >= octeon_bootinfo->mac_addr_count) - dev_err(&pdev->dev, - "Error %s: Using MAC outside of the assigned range: %pM\n", - netdev->name, netdev->dev_addr); + if (mac) + memcpy(netdev->dev_addr, mac, 6); - if (register_netdev(netdev)) - goto err; + p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); + + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + + result = register_netdev(netdev); + if (result) + goto fail_region2; dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); return 0; + +fail_region2: + iounmap((void *)p->agl); + iounmap((void *)p->mix); + devm_release_mem_region(&pdev->dev, p->agl_phys, p->agl_size); +fail_region1: + devm_release_mem_region(&pdev->dev, p->mix_phys, p->mix_size); err: free_netdev(netdev); - return -ENOENT; + return result; } static int __devexit octeon_mgmt_remove(struct platform_device *pdev) { struct net_device *netdev = dev_get_drvdata(&pdev->dev); + struct octeon_mgmt *p = netdev_priv(netdev); unregister_netdev(netdev); + iounmap((void *)p->agl); + iounmap((void *)p->mix); + devm_release_mem_region(&pdev->dev, p->agl_phys, p->agl_size); + devm_release_mem_region(&pdev->dev, p->mix_phys, p->mix_size); free_netdev(netdev); return 0; } +static struct of_device_id octeon_mgmt_match[] = { + { + .compatible = "cavium,octeon-5750-mix", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mgmt_match); + static struct platform_driver octeon_mgmt_driver = { .driver = { .name = "octeon_mgmt", .owner = THIS_MODULE, + .of_match_table = octeon_mgmt_match, }, .probe = octeon_mgmt_probe, .remove = __devexit_p(octeon_mgmt_remove), -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Mar 4 20:47:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 20:47:39 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11869 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491999Ab1CDTnE (ORCPT ); Fri, 4 Mar 2011 20:43:04 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Mar 2011 11:43:56 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:43:02 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Mar 2011 11:43:02 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p24JgvKO017382; Fri, 4 Mar 2011 11:42:57 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p24Jgur3017381; Fri, 4 Mar 2011 11:42:56 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney , "David S. Miller" , netdev@vger.kernel.org Subject: [RFC PATCH v2 12/12] staging: octeon_ethernet: Convert to use device tree. Date: Fri, 4 Mar 2011 11:42:24 -0800 Message-Id: <1299267744-17278-13-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 04 Mar 2011 19:43:02.0451 (UTC) FILETIME=[5FA7B830:01CBDAA4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29358 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Get MAC address and PHY connection from the device tree. Signed-off-by: David Daney Cc: "David S. Miller" Cc: netdev@vger.kernel.org --- drivers/staging/octeon/ethernet-mdio.c | 27 +++++---- drivers/staging/octeon/ethernet.c | 88 +++++++++++++++++------------- drivers/staging/octeon/octeon-ethernet.h | 3 + 3 files changed, 69 insertions(+), 49 deletions(-) diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 0e5dab7..38a0153 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -27,6 +27,7 @@ #include #include #include +#include #include @@ -162,22 +163,24 @@ static void cvm_oct_adjust_link(struct net_device *dev) int cvm_oct_phy_setup_device(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); + struct device_node *phy_node; - int phy_addr = cvmx_helper_board_get_mii_address(priv->port); - if (phy_addr != -1) { - char phy_id[20]; + if (!priv->of_node) + return 0; - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", phy_addr); + phy_node = of_parse_phandle(priv->of_node, "phy-handle", 0); + if (!phy_node) + return 0; - priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, - PHY_INTERFACE_MODE_GMII); + priv->phydev = of_phy_connect(dev, phy_node, cvm_oct_adjust_link, 0, + PHY_INTERFACE_MODE_GMII); - if (IS_ERR(priv->phydev)) { - priv->phydev = NULL; - return -1; - } - priv->last_link = 0; - phy_start_aneg(priv->phydev); + if (IS_ERR(priv->phydev)) { + priv->phydev = NULL; + return -1; } + priv->last_link = 0; + phy_start_aneg(priv->phydev); + return 0; } diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 042adf7..16c93e4 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -31,6 +31,7 @@ #include #include #include +#include #include @@ -112,15 +113,6 @@ int rx_napi_weight = 32; module_param(rx_napi_weight, int, 0444); MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter."); -/* - * The offset from mac_addr_base that should be used for the next port - * that is configured. By convention, if any mgmt ports exist on the - * chip, they get the first mac addresses, The ports controlled by - * this driver are numbered sequencially following any mgmt addresses - * that may exist. - */ -static unsigned int cvm_oct_mac_addr_offset; - /** * cvm_oct_poll_queue - Workqueue for polling operations. */ @@ -447,26 +439,13 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) int cvm_oct_common_init(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); - struct sockaddr sa; - u64 mac = ((u64)(octeon_bootinfo->mac_addr_base[0] & 0xff) << 40) | - ((u64)(octeon_bootinfo->mac_addr_base[1] & 0xff) << 32) | - ((u64)(octeon_bootinfo->mac_addr_base[2] & 0xff) << 24) | - ((u64)(octeon_bootinfo->mac_addr_base[3] & 0xff) << 16) | - ((u64)(octeon_bootinfo->mac_addr_base[4] & 0xff) << 8) | - (u64)(octeon_bootinfo->mac_addr_base[5] & 0xff); - - mac += cvm_oct_mac_addr_offset; - sa.sa_data[0] = (mac >> 40) & 0xff; - sa.sa_data[1] = (mac >> 32) & 0xff; - sa.sa_data[2] = (mac >> 24) & 0xff; - sa.sa_data[3] = (mac >> 16) & 0xff; - sa.sa_data[4] = (mac >> 8) & 0xff; - sa.sa_data[5] = mac & 0xff; - - if (cvm_oct_mac_addr_offset >= octeon_bootinfo->mac_addr_count) - printk(KERN_DEBUG "%s: Using MAC outside of the assigned range:" - " %pM\n", dev->name, sa.sa_data); - cvm_oct_mac_addr_offset++; + struct sockaddr sa = {0}; + + if (priv->of_node) { + const u8 *mac = of_get_mac_address(priv->of_node); + if (mac) + memcpy(sa.sa_data, mac, 6); + } /* * Force the interface to use the POW send if always_use_pow @@ -594,22 +573,55 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = { extern void octeon_mdiobus_force_mod_depencency(void); +static struct device_node * __init cvm_oct_of_get_child(const struct device_node *parent, + int reg_val) +{ + struct device_node *node = NULL; + int size; + const __be32 *addr; + + for (;;) { + node = of_get_next_child(parent, node); + if (!node) + break; + addr = of_get_property(node, "reg", &size); + if (addr && (be32_to_cpu(*addr) == reg_val)) + break; + } + return node; +} + +static struct device_node * __init cvm_oct_node_for_port(struct device_node *pip, + int interface, int port) +{ + struct device_node *ni, *np; + + ni = cvm_oct_of_get_child(pip, interface); + if (!ni) + return NULL; + + np = cvm_oct_of_get_child(ni, port); + of_node_put(ni); + + return np; +} + static int __init cvm_oct_init_module(void) { int num_interfaces; int interface; int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; int qos; + struct device_node *pip; octeon_mdiobus_force_mod_depencency(); pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) - cvm_oct_mac_addr_offset = 2; /* First two are the mgmt ports. */ - else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - cvm_oct_mac_addr_offset = 1; /* First one is the mgmt port. */ - else - cvm_oct_mac_addr_offset = 0; + pip = of_find_node_by_path("pip"); + if (!pip) { + pr_err("Error: No 'pip' in /aliases\n"); + return -EINVAL; + } cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet"); if (cvm_oct_poll_queue == NULL) { @@ -688,10 +700,11 @@ static int __init cvm_oct_init_module(void) cvmx_helper_interface_get_mode(interface); int num_ports = cvmx_helper_ports_on_interface(interface); int port; + int port_index; - for (port = cvmx_helper_get_ipd_port(interface, 0); + for (port_index = 0, port = cvmx_helper_get_ipd_port(interface, 0); port < cvmx_helper_get_ipd_port(interface, num_ports); - port++) { + port_index++, port++) { struct octeon_ethernet *priv; struct net_device *dev = alloc_etherdev(sizeof(struct octeon_ethernet)); @@ -702,6 +715,7 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ priv = netdev_priv(dev); + priv->of_node = cvm_oct_node_for_port(pip, interface, port_index); INIT_DELAYED_WORK(&priv->port_periodic_work, cvm_oct_periodic_worker); diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index d581925..9360e22 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -31,6 +31,8 @@ #ifndef OCTEON_ETHERNET_H #define OCTEON_ETHERNET_H +#include + /** * This is the definition of the Ethernet driver's private * driver state stored in netdev_priv(dev). @@ -59,6 +61,7 @@ struct octeon_ethernet { void (*poll) (struct net_device *dev); struct delayed_work port_periodic_work; struct work_struct port_work; /* may be unused. */ + struct device_node *of_node; }; int cvm_oct_free_work(void *work_queue_entry); -- 1.7.2.3 From blogic@openwrt.org Fri Mar 4 21:11:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 21:11:50 +0100 (CET) Received: from nbd.name ([46.4.11.11]:38260 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491993Ab1CDULq (ORCPT ); Fri, 4 Mar 2011 21:11:46 +0100 Message-ID: <4D7147CC.1020009@openwrt.org> Date: Fri, 04 Mar 2011 21:13:00 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , Ralph Hempel , David Woodhouse , Daniel Schwierzeck , linux-mips@linux-mips.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH V3 06/10] MIPS: lantiq: add NOR flash support References: <1299146626-17428-1-git-send-email-blogic@openwrt.org> <1299146626-17428-7-git-send-email-blogic@openwrt.org> <4D70DDEA.2050308@mvista.com> In-Reply-To: <4D70DDEA.2050308@mvista.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29359 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips Hi, >> + if (ltq_mtd_probing) >> + adr ^= 2; >> + spin_lock_irqsave(&ebu_lock, flags); >> + temp.x[0] = *((__u16 *)(map->virt + adr)); >> + spin_unlock_irqrestore(&ebu_lock, flags); > > Hm, what does this lock gain, if the read is atomic anyway? the SoC has a hardware arbitor for the EBU. I have so far not been able to activate it properly and the lock is needed to protect from PCI and NOR i/o clashing with eachother. i know that the arbitor works when using lantiqs 2.6.28. i will provide a follow up patch once i figured how to bring up the arbitor properly. until that time we need to use the lock. thanks, John From davem@davemloft.net Fri Mar 4 22:10:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 22:10:03 +0100 (CET) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:51586 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491998Ab1CDVKA (ORCPT ); Fri, 4 Mar 2011 22:10:00 +0100 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id E0EA924C087; Fri, 4 Mar 2011 13:10:31 -0800 (PST) Date: Fri, 04 Mar 2011 13:10:31 -0800 (PST) Message-Id: <20110304.131031.189690288.davem@davemloft.net> To: ddaney@caviumnetworks.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [RFC PATCH v2 10/12] netdev: mdio-octeon.c: Convert to use device tree. From: David Miller In-Reply-To: <1299267744-17278-11-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-11-git-send-email-ddaney@caviumnetworks.com> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29360 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: David Daney Date: Fri, 4 Mar 2011 11:42:22 -0800 > Get the MDIO bus controller addresses from the device tree. > > Signed-off-by: David Daney Acked-by: David S. Miller From davem@davemloft.net Fri Mar 4 22:10:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 22:10:27 +0100 (CET) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:51591 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491994Ab1CDVKC (ORCPT ); Fri, 4 Mar 2011 22:10:02 +0100 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 537A424C087; Fri, 4 Mar 2011 13:10:39 -0800 (PST) Date: Fri, 04 Mar 2011 13:10:39 -0800 (PST) Message-Id: <20110304.131039.112585485.davem@davemloft.net> To: ddaney@caviumnetworks.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [RFC PATCH v2 11/12] netdev: octeon_mgmt: Convert to use device tree. From: David Miller In-Reply-To: <1299267744-17278-12-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-12-git-send-email-ddaney@caviumnetworks.com> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29361 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: David Daney Date: Fri, 4 Mar 2011 11:42:23 -0800 > The device tree will supply the register bank base addresses, make > register addressing relative to those. PHY connection is now > described by the device tree. > > Signed-off-by: David Daney Acked-by: David S. Miller From davem@davemloft.net Fri Mar 4 22:10:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 22:10:51 +0100 (CET) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:51598 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492007Ab1CDVKJ (ORCPT ); Fri, 4 Mar 2011 22:10:09 +0100 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 5BFCC24C087; Fri, 4 Mar 2011 13:10:46 -0800 (PST) Date: Fri, 04 Mar 2011 13:10:46 -0800 (PST) Message-Id: <20110304.131046.183062389.davem@davemloft.net> To: ddaney@caviumnetworks.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [RFC PATCH v2 12/12] staging: octeon_ethernet: Convert to use device tree. From: David Miller In-Reply-To: <1299267744-17278-13-git-send-email-ddaney@caviumnetworks.com> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-13-git-send-email-ddaney@caviumnetworks.com> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29362 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: David Daney Date: Fri, 4 Mar 2011 11:42:24 -0800 > Get MAC address and PHY connection from the device tree. > > Signed-off-by: David Daney Acked-by: David S. Miller From glikely@secretlab.ca Fri Mar 4 22:55:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Mar 2011 22:55:39 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:38647 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491880Ab1CDVzd (ORCPT ); Fri, 4 Mar 2011 22:55:33 +0100 Received: by pwi8 with SMTP id 8so477208pwi.36 for ; Fri, 04 Mar 2011 13:55:26 -0800 (PST) Received: by 10.142.127.16 with SMTP id z16mr821655wfc.319.1299275726487; Fri, 04 Mar 2011 13:55:26 -0800 (PST) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id m10sm3499935wfl.23.2011.03.04.13.55.25 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 13:55:25 -0800 (PST) Received: by angua (Postfix, from userid 1000) id 8B3DD3C00D3; Fri, 4 Mar 2011 14:55:24 -0700 (MST) Date: Fri, 4 Mar 2011 14:55:24 -0700 From: Grant Likely To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 03/12] of: Make of_find_node_by_path() traverse /aliases for relative paths. Message-ID: <20110304215524.GB7579@angua.secretlab.ca> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-4-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1299267744-17278-4-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29363 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Fri, Mar 04, 2011 at 11:42:15AM -0800, David Daney wrote: > Currently all paths passed to of_find_node_by_path() must begin with a > '/', indicating a full path to the desired node. > > Augment the look-up code so that if a path does *not* begin with '/', > the path is used as the name of an /aliases property. The value of > this alias is then used as the full node path to be found. > > Signed-off-by: David Daney > --- > > This patch is unchanged from the previous version I send separately. I > have not forgotten about Grant's feedback, just deferred it to the > next version. okay; I'll wait for the next version before I consider picking it up. g. From glikely@secretlab.ca Sat Mar 5 01:58:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Mar 2011 01:58:04 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:42305 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491981Ab1CEA6B (ORCPT ); Sat, 5 Mar 2011 01:58:01 +0100 Received: by ywa8 with SMTP id 8so1035463ywa.36 for ; Fri, 04 Mar 2011 16:57:54 -0800 (PST) Received: by 10.150.7.2 with SMTP id 2mr26269ybg.300.1299286674069; Fri, 04 Mar 2011 16:57:54 -0800 (PST) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id q13sm100181yba.20.2011.03.04.16.57.52 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 16:57:53 -0800 (PST) Received: by angua (Postfix, from userid 1000) id 0E7083C00D3; Fri, 4 Mar 2011 17:57:50 -0700 (MST) Date: Fri, 4 Mar 2011 17:57:50 -0700 From: Grant Likely To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 02/12] of: Allow scripts/dtc/libfdt to be used from kernel code Message-ID: <20110305005750.GC7579@angua.secretlab.ca> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1299267744-17278-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29364 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips [cc'ing David Gibson] On Fri, Mar 04, 2011 at 11:42:14AM -0800, David Daney wrote: > Signed-off-by: David Daney > --- > include/linux/libfdt.h | 3 +++ > lib/Kconfig | 6 ++++++ > lib/Makefile | 2 ++ > lib/libfdt/Makefile | 7 +++++++ > lib/libfdt/libfdt_env.h | 21 +++++++++++++++++++++ > scripts/dtc/libfdt/libfdt.h | 4 ++-- > 6 files changed, 41 insertions(+), 2 deletions(-) > create mode 100644 include/linux/libfdt.h > create mode 100644 lib/libfdt/Makefile > create mode 100644 lib/libfdt/libfdt_env.h > > diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h > new file mode 100644 > index 0000000..10bce91 > --- /dev/null > +++ b/include/linux/libfdt.h > @@ -0,0 +1,3 @@ > +#include "../../lib/libfdt/libfdt_env.h" libfdt_env.h should be in include/linux > +#include "../../scripts/dtc/libfdt/fdt.h" > +#include "../../scripts/dtc/libfdt/libfdt.h" Hmmm... I wonder if there is a better way to do this. I don't much care for the relative path references. Also, need to have #ifdef _INCLUDE_LIBFDT_H_ protection > diff --git a/lib/Kconfig b/lib/Kconfig > index 0ee67e0..e8a2638 100644 > --- a/lib/Kconfig > +++ b/lib/Kconfig > @@ -219,4 +219,10 @@ config LRU_CACHE > config AVERAGE > bool > > +# > +# The Flattened Device Tree manipulation library > +# > +config LIBFDT > + bool > + This should be in drivers/of/Kconfig > endmenu > diff --git a/lib/Makefile b/lib/Makefile > index cbb774f..5840115 100644 > --- a/lib/Makefile > +++ b/lib/Makefile > @@ -110,6 +110,8 @@ obj-$(CONFIG_ATOMIC64_SELFTEST) += atomic64_test.o > > obj-$(CONFIG_AVERAGE) += average.o > > +obj-$(CONFIG_LIBFDT) += libfdt/ > + Ditto here; drivers/of/libfdt > hostprogs-y := gen_crc32table > clean-files := crc32table.h > > diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile > new file mode 100644 > index 0000000..6c1a496 > --- /dev/null > +++ b/lib/libfdt/Makefile > @@ -0,0 +1,7 @@ > +obj-y = fdt.o fdt_wip.o fdt_ro.o > + > +EXTRA_CFLAGS += -include $(src)/libfdt_env.h -I$(src)/../../scripts/dtc/libfdt > + > +$(obj)/%.o: $(src)/../../scripts/dtc/libfdt/%.c FORCE > + $(call cmd,force_checksrc) > + $(call if_changed_rule,cc_o_c) > diff --git a/lib/libfdt/libfdt_env.h b/lib/libfdt/libfdt_env.h > new file mode 100644 > index 0000000..d977b8b > --- /dev/null > +++ b/lib/libfdt/libfdt_env.h > @@ -0,0 +1,21 @@ > +#ifndef _LIBFDT_ENV_H > +#define _LIBFDT_ENV_H > + > +#include > + > +#define _B(n) ((unsigned long long)((uint8_t *)&x)[n]) > +static inline uint32_t fdt32_to_cpu(uint32_t x) > +{ > + return (_B(0) << 24) | (_B(1) << 16) | (_B(2) << 8) | _B(3); > +} > +#define cpu_to_fdt32(x) fdt32_to_cpu(x) > + > +static inline uint64_t fdt64_to_cpu(uint64_t x) > +{ > + return (_B(0) << 56) | (_B(1) << 48) | (_B(2) << 40) | (_B(3) << 32) > + | (_B(4) << 24) | (_B(5) << 16) | (_B(6) << 8) | _B(7); > +} > +#define cpu_to_fdt64(x) fdt64_to_cpu(x) > +#undef _B > + This isn't necessary, the kernel already has efficient architecture macros for converting endianess. #define fdt32_to_cpu(x) be32_to_cpu(x) #define cpu_to_fdt32(x) cpu_to_be32(x) #define fdt64_to_cpu(x) be64_to_cpu(x) #define cpu_to_fdt64(x) cpu_to_be64(x) > +#endif /* _LIBFDT_ENV_H */ > diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h > index ce80e4f..33a0c4d 100644 > --- a/scripts/dtc/libfdt/libfdt.h > +++ b/scripts/dtc/libfdt/libfdt.h > @@ -51,8 +51,8 @@ > * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > */ > > -#include > -#include > +#include "libfdt_env.h" > +#include "fdt.h" This causes problems. libfdt is an external library that is periodically copied into the kernel tree. It would be better to add "-Iscripts/dtc/libfdt" to CFLAGS for .c files that want to call libfdt routines. > > #define FDT_FIRST_SUPPORTED_VERSION 0x10 > #define FDT_LAST_SUPPORTED_VERSION 0x11 > -- > 1.7.2.3 > From glikely@secretlab.ca Sat Mar 5 01:59:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Mar 2011 01:59:56 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:46112 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491981Ab1CEA7x convert rfc822-to-8bit (ORCPT ); Sat, 5 Mar 2011 01:59:53 +0100 Received: by iyf40 with SMTP id 40so2622678iyf.36 for ; Fri, 04 Mar 2011 16:59:47 -0800 (PST) Received: by 10.231.64.144 with SMTP id e16mr6428ibi.22.1299286787092; Fri, 04 Mar 2011 16:59:47 -0800 (PST) MIME-Version: 1.0 Received: by 10.231.166.130 with HTTP; Fri, 4 Mar 2011 16:59:27 -0800 (PST) In-Reply-To: <20110305005750.GC7579@angua.secretlab.ca> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-3-git-send-email-ddaney@caviumnetworks.com> <20110305005750.GC7579@angua.secretlab.ca> From: Grant Likely Date: Fri, 4 Mar 2011 17:59:27 -0700 X-Google-Sender-Auth: CjfYjSpyKbXjanJlnCU2ZiUxxMA Message-ID: Subject: Re: [RFC PATCH v2 02/12] of: Allow scripts/dtc/libfdt to be used from kernel code To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, David Gibson Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29365 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips [actually cc'ing David Gibson this time] On Fri, Mar 4, 2011 at 5:57 PM, Grant Likely wrote: > [cc'ing David Gibson] > On Fri, Mar 04, 2011 at 11:42:14AM -0800, David Daney wrote: >> Signed-off-by: David Daney >> --- >> include/linux/libfdt.h | 3 +++ >> lib/Kconfig | 6 ++++++ >> lib/Makefile | 2 ++ >> lib/libfdt/Makefile | 7 +++++++ >> lib/libfdt/libfdt_env.h | 21 +++++++++++++++++++++ >> scripts/dtc/libfdt/libfdt.h | 4 ++-- >> 6 files changed, 41 insertions(+), 2 deletions(-) >> create mode 100644 include/linux/libfdt.h >> create mode 100644 lib/libfdt/Makefile >> create mode 100644 lib/libfdt/libfdt_env.h >> >> diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h >> new file mode 100644 >> index 0000000..10bce91 >> --- /dev/null >> +++ b/include/linux/libfdt.h >> @@ -0,0 +1,3 @@ >> +#include "../../lib/libfdt/libfdt_env.h" > > libfdt_env.h should be in include/linux > >> +#include "../../scripts/dtc/libfdt/fdt.h" >> +#include "../../scripts/dtc/libfdt/libfdt.h" > > Hmmm... I wonder if there is a better way to do this. I don't much > care for the relative path references. > > Also, need to have #ifdef _INCLUDE_LIBFDT_H_ protection > >> diff --git a/lib/Kconfig b/lib/Kconfig >> index 0ee67e0..e8a2638 100644 >> --- a/lib/Kconfig >> +++ b/lib/Kconfig >> @@ -219,4 +219,10 @@ config LRU_CACHE >> config AVERAGE >> bool >> >> +# >> +# The Flattened Device Tree manipulation library >> +# >> +config LIBFDT >> + bool >> + > > This should be in drivers/of/Kconfig > >> endmenu >> diff --git a/lib/Makefile b/lib/Makefile >> index cbb774f..5840115 100644 >> --- a/lib/Makefile >> +++ b/lib/Makefile >> @@ -110,6 +110,8 @@ obj-$(CONFIG_ATOMIC64_SELFTEST) += atomic64_test.o >> >> obj-$(CONFIG_AVERAGE) += average.o >> >> +obj-$(CONFIG_LIBFDT) += libfdt/ >> + > > Ditto here; drivers/of/libfdt > >> hostprogs-y := gen_crc32table >> clean-files := crc32table.h >> >> diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile >> new file mode 100644 >> index 0000000..6c1a496 >> --- /dev/null >> +++ b/lib/libfdt/Makefile >> @@ -0,0 +1,7 @@ >> +obj-y = fdt.o fdt_wip.o fdt_ro.o >> + >> +EXTRA_CFLAGS += -include $(src)/libfdt_env.h -I$(src)/../../scripts/dtc/libfdt >> + >> +$(obj)/%.o: $(src)/../../scripts/dtc/libfdt/%.c FORCE >> + $(call cmd,force_checksrc) >> + $(call if_changed_rule,cc_o_c) >> diff --git a/lib/libfdt/libfdt_env.h b/lib/libfdt/libfdt_env.h >> new file mode 100644 >> index 0000000..d977b8b >> --- /dev/null >> +++ b/lib/libfdt/libfdt_env.h >> @@ -0,0 +1,21 @@ >> +#ifndef _LIBFDT_ENV_H >> +#define _LIBFDT_ENV_H >> + >> +#include >> + >> +#define _B(n) ((unsigned long long)((uint8_t *)&x)[n]) >> +static inline uint32_t fdt32_to_cpu(uint32_t x) >> +{ >> + return (_B(0) << 24) | (_B(1) << 16) | (_B(2) << 8) | _B(3); >> +} >> +#define cpu_to_fdt32(x) fdt32_to_cpu(x) >> + >> +static inline uint64_t fdt64_to_cpu(uint64_t x) >> +{ >> + return (_B(0) << 56) | (_B(1) << 48) | (_B(2) << 40) | (_B(3) << 32) >> + | (_B(4) << 24) | (_B(5) << 16) | (_B(6) << 8) | _B(7); >> +} >> +#define cpu_to_fdt64(x) fdt64_to_cpu(x) >> +#undef _B >> + > > This isn't necessary, the kernel already has efficient architecture > macros for converting endianess. > > #define fdt32_to_cpu(x) be32_to_cpu(x) > #define cpu_to_fdt32(x) cpu_to_be32(x) > #define fdt64_to_cpu(x) be64_to_cpu(x) > #define cpu_to_fdt64(x) cpu_to_be64(x) > >> +#endif /* _LIBFDT_ENV_H */ >> diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h >> index ce80e4f..33a0c4d 100644 >> --- a/scripts/dtc/libfdt/libfdt.h >> +++ b/scripts/dtc/libfdt/libfdt.h >> @@ -51,8 +51,8 @@ >> * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> */ >> >> -#include >> -#include >> +#include "libfdt_env.h" >> +#include "fdt.h" > > This causes problems. libfdt is an external library that is > periodically copied into the kernel tree. It would be better to add > "-Iscripts/dtc/libfdt" to CFLAGS for .c files that want to call libfdt > routines. > >> >> #define FDT_FIRST_SUPPORTED_VERSION 0x10 >> #define FDT_LAST_SUPPORTED_VERSION 0x11 >> -- >> 1.7.2.3 >> > -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. From glikely@secretlab.ca Sat Mar 5 02:07:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Mar 2011 02:07:59 +0100 (CET) Received: from mail-iw0-f177.google.com ([209.85.214.177]:51755 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492009Ab1CEBH4 (ORCPT ); Sat, 5 Mar 2011 02:07:56 +0100 Received: by iwn36 with SMTP id 36so2643173iwn.36 for ; Fri, 04 Mar 2011 17:07:49 -0800 (PST) Received: by 10.43.55.9 with SMTP id vw9mr1474833icb.259.1299287269854; Fri, 04 Mar 2011 17:07:49 -0800 (PST) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id xa8sm2059017icb.10.2011.03.04.17.07.48 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 17:07:49 -0800 (PST) Received: by angua (Postfix, from userid 1000) id BC1033C00D3; Fri, 4 Mar 2011 18:07:46 -0700 (MST) Date: Fri, 4 Mar 2011 18:07:46 -0700 From: Grant Likely To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 06/12] MIPS: Octeon: Add a irq_create_of_mapping() implementation. Message-ID: <20110305010746.GD7579@angua.secretlab.ca> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-7-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1299267744-17278-7-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29366 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Fri, Mar 04, 2011 at 11:42:18AM -0800, David Daney wrote: > This is needed for Octeon to use the Device Tree. > > Signed-off-by: David Daney > --- > arch/mips/cavium-octeon/octeon-irq.c | 25 +++++++++++++++++++++++++ > 1 files changed, 25 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c > index b365710..b0a9261 100644 > --- a/arch/mips/cavium-octeon/octeon-irq.c > +++ b/arch/mips/cavium-octeon/octeon-irq.c > @@ -8,7 +8,9 @@ > > #include > #include > +#include > #include > +#include > #include > #include > > @@ -64,6 +66,29 @@ static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, > octeon_irq_ciu_to_irq[line][bit] = irq; > } > > +/* > + * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# > + * > + * Octeon irq maps are a pair of indexes. The first selects either > + * ciu0 or ciu1, the second is the bit within the ciu register. > + */ Is each 'ciu' an interrupt controller, or a 'bank' within the controller? Also, it is typical to have another cell for specifying flags if there is any kind of configuration for each irq line, like edge vs. level and active high or active low. (the counter example is PCI which doesn't use a flags cell because all PCI irqs are level active. You'll need to supply documentation for the ciu binding to Documentation/devicetree/bindings before this patch gets merged. > +unsigned int irq_create_of_mapping(struct device_node *controller, > + const u32 *intspec, unsigned int intsize) > +{ > + int ciu, bit; > + unsigned int irq = 0; > + > + ciu = be32_to_cpup(intspec); > + bit = be32_to_cpup(intspec + 1); > + > + if (ciu < 8 && bit < 64) > + irq = octeon_irq_ciu_to_irq[ciu][bit]; > + > + return irq; > +} > +EXPORT_SYMBOL_GPL(irq_create_of_mapping); > + > + > static int octeon_coreid_for_cpu(int cpu) > { > #ifdef CONFIG_SMP > -- > 1.7.2.3 > From glikely@secretlab.ca Sat Mar 5 02:15:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Mar 2011 02:15:40 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:55925 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491981Ab1CEBPh (ORCPT ); Sat, 5 Mar 2011 02:15:37 +0100 Received: by yxh35 with SMTP id 35so1045289yxh.36 for ; Fri, 04 Mar 2011 17:15:30 -0800 (PST) Received: by 10.101.211.6 with SMTP id n6mr49159anq.253.1299287730469; Fri, 04 Mar 2011 17:15:30 -0800 (PST) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id w6sm12663anf.6.2011.03.04.17.15.28 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 17:15:29 -0800 (PST) Received: by angua (Postfix, from userid 1000) id E361F3C00D3; Fri, 4 Mar 2011 18:15:26 -0700 (MST) Date: Fri, 4 Mar 2011 18:15:26 -0700 From: Grant Likely To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 04/12] MIPS: Octeon: Add device tree source files. Message-ID: <20110305011526.GE7579@angua.secretlab.ca> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-5-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1299267744-17278-5-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29367 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Fri, Mar 04, 2011 at 11:42:16AM -0800, David Daney wrote: > Signed-off-by: David Daney > --- > arch/mips/cavium-octeon/.gitignore | 2 + > arch/mips/cavium-octeon/Makefile | 13 ++ > arch/mips/cavium-octeon/octeon_3xxx.dts | 330 +++++++++++++++++++++++++++++++ > arch/mips/cavium-octeon/octeon_68xx.dts | 116 +++++++++++ > 4 files changed, 461 insertions(+), 0 deletions(-) > create mode 100644 arch/mips/cavium-octeon/.gitignore > create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts > create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts > > diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore > new file mode 100644 > index 0000000..39c9686 > --- /dev/null > +++ b/arch/mips/cavium-octeon/.gitignore > @@ -0,0 +1,2 @@ > +*.dtb.S > +*.dtb > diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile > index 19eb043..5e25dce 100644 > --- a/arch/mips/cavium-octeon/Makefile > +++ b/arch/mips/cavium-octeon/Makefile > @@ -15,3 +15,16 @@ obj-y += octeon-memcpy.o > obj-y += executive/ > > obj-$(CONFIG_SMP) += smp.o > + > +DTS_FILES = octeon_3xxx.dts octeon_68xx.dts > +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) > + > +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) > + > +$(obj)/%.dtb: $(src)/%.dts > + $(call cmd,dtc) > + > +# Let's keep the .dtb files around in case we want to look at them. > +.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) > + > +clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) > diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts > new file mode 100644 > index 0000000..6910d9d > --- /dev/null > +++ b/arch/mips/cavium-octeon/octeon_3xxx.dts > @@ -0,0 +1,330 @@ > +/dts-v1/; > +/* > + * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. > + * > + * This device tree is pruned and patched by early boot code before > + * use. Because of this, it contains a super-set of the available > + * devices and properties. > + */ > +/ { > + model = "OCTEON"; Be more specific in the model property. What is the full (human readable) name of this board? Since your using this simply as a template, it may be better to just omit this property entirely. > + compatible = "cavium,octeon-3860"; All of the new compatible values in this file need to be documented in Documentation/devicetree/bindings. > + #address-cells = <2>; > + #size-cells = <2>; > + > + soc@0 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; /* Direct mapping */ > + > + ciu: interrupt-controller@1070000000000 { > + compatible = "cavium,octeon-3860-ciu"; > + interrupt-controller; > + #address-cells = <0>; > + /* Interrupts are specified by three parts: > + * 1) Controller register (0 or 1) > + * 2) Bit within the register (0..63) > + * 3) Triggering (0 - level active high > + * 1 - level active low > + * 2 - edge rising > + * 3 - edge falling > + * > + * For non-GPIO sources, the triggering cannot be > + * changed and is ignored. > + */ > + #interrupt-cells = <3>; > + reg = <0x10700 0x00000000 0x0 0x7000>; > + }; > + > + smi0: mdio@1180000001800 { > + compatible = "cavium,octeon-3860-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0x00001800 0x0 0x40>; > + > + phy0: ethernet-phy@0 { > + reg = <0>; Should have a compatible property for each of the phys > + }; > + > + phy1: ethernet-phy@1 { > + reg = <1>; > + }; > + > + phy2: ethernet-phy@2 { > + reg = <2>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy3: ethernet-phy@3 { > + reg = <3>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy4: ethernet-phy@4 { > + reg = <4>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy5: ethernet-phy@5 { > + reg = <5>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + > + phy6: ethernet-phy@6 { > + reg = <6>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy7: ethernet-phy@7 { > + reg = <7>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy8: ethernet-phy@8 { > + reg = <8>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy9: ethernet-phy@9 { > + reg = <9>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + }; > + > + smi1: mdio@1180000001900 { > + compatible = "cavium,octeon-3860-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0x00001900 0x0 0x40>; > + }; > + > + mix0: ethernet@1070000100000 { > + compatible = "cavium,octeon-5750-mix"; > + device_type = "network"; Drop 'device_type' property. It only makes sense if you have a real OpenFirmware implementation. Ditto through the rest of the file. > + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ > + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ > + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ > + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ > + cell-index = <0>; > + interrupt-parent = <&ciu>; If you put this property up in the root node, then you can omit it from everywhere else because they'll pick it up as the default interrupt controller. > + interrupts = <0 62 0>, <1 46 0>; > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy0>; > + }; > + > + mix1: ethernet@1070000100800 { > + compatible = "cavium,octeon-5750-mix"; > + device_type = "network"; > + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ > + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ > + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ > + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ > + cell-index = <1>; > + interrupt-parent = <&ciu>; > + interrupts = <1 18 0>, < 1 46 0>; > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy1>; > + }; > + > + pip: pip@11800a0000000 { > + compatible = "cavium,octeon-3860-pip"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0xa0000000 0x0 0x2000>; > + > + interface@0 { > + compatible = "cavium,octeon-3860-pip-interface"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; /* interface */ > + > + ethernet@0 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x0>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy2>; > + }; > + ethernet@1 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x1>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy3>; > + }; > + ethernet@2 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x2>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy4>; > + }; > + ethernet@3 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x3>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy5>; > + }; > + }; > + > + interface@1 { > + compatible = "cavium,octeon-3860-pip-interface"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; /* interface */ > + > + ethernet@0 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x0>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy6>; > + }; > + ethernet@1 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x1>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy7>; > + }; > + ethernet@2 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x2>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy8>; > + }; > + ethernet@3 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x3>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy9>; > + }; > + }; > + > + interface@2 { /* DPI interface. */ > + compatible = "cavium,octeon-3860-pip-interface"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <2>; /* interface */ > + > + ethernet@0 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x0>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + }; > + ethernet@1 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x1>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + }; > + ethernet@2 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x2>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + }; > + ethernet@3 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x3>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + }; > + }; > + > + interface@3 { /* Loop interface. */ > + compatible = "cavium,octeon-3860-pip-interface"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <3>; /* interface */ > + > + ethernet@0 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x0>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + }; > + ethernet@1 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x1>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + }; > + ethernet@2 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x2>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + }; > + ethernet@3 { > + compatible = "cavium,octeon-3860-pip-port"; > + device_type = "network"; > + reg = <0x3>; /* Port */ > + local-mac-address = [ 00 00 00 00 00 00 ]; > + }; > + }; > + }; > + > + twsi0: i2c@1180000001000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "cavium,octeon-3860-twsi"; > + reg = <0x11800 0x00001000 0x0 0x200>; > + interrupt-parent = <&ciu>; > + interrupts = <0 45 0>; > + clock-rate = <100000>; > + > + rtc@68 { > + compatible = "dallas,ds1337"; > + reg = <0x68>; > + }; > + tmp@4c { > + compatible = "ti,tmp421"; > + reg = <0x4c>; > + }; > + }; > + > + twsi1: i2c@1180000001200 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "cavium,octeon-3860-twsi"; > + reg = <0x11800 0x00001200 0x0 0x200>; > + interrupt-parent = <&ciu>; > + interrupts = <0 59 0>; > + clock-rate = <100000>; > + }; > + }; > + > + aliases { > + mix0 = &mix0; > + mix1 = &mix1; > + pip = &pip; > + smi0 = &smi0; > + smi1 = &smi1; > + twsi0 = &twsi0; > + twsi1 = &twsi1; > + }; > + }; > diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts > new file mode 100644 > index 0000000..f2a8eab > --- /dev/null > +++ b/arch/mips/cavium-octeon/octeon_68xx.dts > @@ -0,0 +1,116 @@ > +/dts-v1/; > +/* > + * OCTEON 68XX device tree skeleton. > + */ > +/ { > + model = "OCTEON"; > + compatible = "cavium,octeon-6880"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + soc@0 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; /* Direct mapping */ > + > + ciu2: interrupt-controller@1070100000000 { > + compatible = "cavium,octeon-6880-ciu2"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + reg = <0x10701 0x00000000 0x0 0x4000000>; > + }; > + > + smi0: mdio@1180000003800 { > + compatible = "cavium,octeon-3860-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0x00003800 0x0 0x40>; > + > + phy0: ethernet-phy@0 { > + reg = <0>; > + device_type = "ethernet-phy"; > + }; > + > + phy1: ethernet-phy@1 { > + reg = <1>; > + device_type = "ethernet-phy"; > + }; > + > + phy3: ethernet-phy@3 { > + reg = <3>; > + device_type = "ethernet-phy"; > + }; > + }; > + > + smi1: mdio@1180000003880 { > + compatible = "cavium,octeon-3860-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0x00003880 0x0 0x40>; > + }; > + > + smi2: mdio@1180000003900 { > + compatible = "cavium,octeon-3860-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0x00003900 0x0 0x40>; > + }; > + > + smi3: mdio@1180000003980 { > + compatible = "cavium,octeon-3860-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0x00003980 0x0 0x40>; > + }; > + > + mix0: ethernet@1070000100000 { > + compatible = "cavium,octeon-5750-mix"; > + device_type = "network"; > + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ > + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ > + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ > + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ > + cell-index = <0>; > + interrupt-parent = <&ciu2>; > + interrupts = <0 62>, <1 46>; > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy0>; > + }; > + > + twsi0: i2c@1180000001000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "cavium,octeon-3860-twsi"; > + reg = <0x11800 0x00001000 0x0 0x200>; > + interrupt-parent = <&ciu2>; > + interrupts = <0 45>; > + clock-rate = <100000>; > + > + rtc@68 { > + compatible = "dallas,ds1337"; > + reg = <0x68>; > + }; > + }; > + > + twsi1: i2c@1180000001200 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "cavium,octeon-3860-twsi"; > + reg = <0x11800 0x00001200 0x0 0x200>; > + interrupt-parent = <&ciu2>; > + interrupts = <0 59>; > + clock-rate = <100000>; > + }; > + }; > + aliases { > + mix0 = &mix0; > + smi0 = &smi0; > + smi1 = &smi1; > + smi2 = &smi2; > + smi3 = &smi3; > + twsi0 = &twsi0; > + twsi1 = &twsi1; > + }; > + }; > -- > 1.7.2.3 > From glikely@secretlab.ca Sat Mar 5 04:05:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Mar 2011 04:05:19 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:51405 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491895Ab1CEDFO (ORCPT ); Sat, 5 Mar 2011 04:05:14 +0100 Received: by yxh35 with SMTP id 35so1067571yxh.36 for ; Fri, 04 Mar 2011 19:05:07 -0800 (PST) Received: by 10.150.186.6 with SMTP id j6mr1652444ybf.100.1299294307820; Fri, 04 Mar 2011 19:05:07 -0800 (PST) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id p29sm101290ybk.1.2011.03.04.19.05.06 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 19:05:07 -0800 (PST) Received: by angua (Postfix, from userid 1000) id CD0CC3C00D3; Fri, 4 Mar 2011 20:05:03 -0700 (MST) Date: Fri, 4 Mar 2011 20:05:03 -0700 From: Grant Likely To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 08/12] MIPS: Octeon: Initialize and fixup device tree. Message-ID: <20110305030503.GF7579@angua.secretlab.ca> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-9-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1299267744-17278-9-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29368 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Fri, Mar 04, 2011 at 11:42:20AM -0800, David Daney wrote: > Signed-off-by: David Daney > --- > arch/mips/Kconfig | 1 + > arch/mips/cavium-octeon/octeon-platform.c | 234 +++++++++++++++++++++++++++++ > arch/mips/cavium-octeon/setup.c | 17 ++ > 3 files changed, 252 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 4baf7f2..021be61 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1355,6 +1355,7 @@ config CPU_CAVIUM_OCTEON > select CPU_SUPPORTS_HIGHMEM > select CPU_SUPPORTS_HUGEPAGES > select GENERIC_HARDIRQS_NO_DEPRECATED > + select LIBFDT > help > The Cavium Octeon processor is a highly integrated chip containing > many ethernet hardware widgets for networking tasks. The processor > diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c > index cecaf62..87512c5 100644 > --- a/arch/mips/cavium-octeon/octeon-platform.c > +++ b/arch/mips/cavium-octeon/octeon-platform.c > @@ -13,10 +13,16 @@ > #include > #include > #include > +#include > #include > +#include > +#include > +#include > > #include > #include > +#include > +#include > > static struct octeon_cf_data octeon_cf_data; > > @@ -440,6 +446,234 @@ device_initcall(octeon_ohci_device_init); > > #endif /* CONFIG_USB */ > > +static struct of_device_id __initdata octeon_ids[] = { > + { .name = "soc@0", }, In general it is strongly discouraged to bind on name. It causes all kinds of problems. Stick with simply binding on 'compatible'. > + { .compatible = "simple-bus", }, > + {}, > +}; > + > +static void __init octeon_fdt_set_phy(int eth, int phy_addr) > +{ > + const __be32 *phy_handle; > + const __be32 *reg; > + struct fdt_node_header *raw_node; > + u32 phandle; > + int phy; > + char new_address[3]; > + char *cp; > + > + phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); > + if (!phy_handle) > + return; > + > + phandle = be32_to_cpup(phy_handle); > + phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); > + if (phy_addr < 0 || phy < 0) { > + /* Delete the PHY things */ > + if (phy >= 0) > + fdt_nop_node(initial_boot_params, phy); > + fdt_nop_property(initial_boot_params, eth, "phy-handle"); > + return; > + } > + > + reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); > + if (phy_addr == be32_to_cpup(reg)) > + return; > + > + fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); > + > + snprintf(new_address, sizeof(new_address), "%x", phy_addr); > + /* > + * All PHYs in the template have a name like 'ethernet-phy@0', > + * that is 14 characters, which allows us to replace the > + * address portion with up to two characters without > + * clobbering things past a multiple of 4 boundry. > + */ Yikes; that's just asking for trouble when someone changes the name in the future without knowing about this code. You must do bounds checking. > + raw_node = (void *)fdt_offset_ptr(initial_boot_params, phy, 0); > + cp = strchr(raw_node->name, '@'); > + if (!cp) > + return; > + cp++; > + cp[0] = new_address[0]; > + cp[1] = new_address[1]; > + > +} > + > +static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) > +{ > + u8 new_mac[6]; > + u64 mac = *pmac; > + int r; > + > + new_mac[0] = (mac >> 40) & 0xff; > + new_mac[1] = (mac >> 32) & 0xff; > + new_mac[2] = (mac >> 24) & 0xff; > + new_mac[3] = (mac >> 16) & 0xff; > + new_mac[4] = (mac >> 8) & 0xff; > + new_mac[5] = mac & 0xff; > + > + r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", > + new_mac, sizeof(new_mac)); > + > + if (r) { > + pr_err("Setting \"local-mac-address\" failed %d", r); > + return; > + } > + *pmac = mac + 1; > +} > + > +static void __init octeon_fdt_rm_ethernet(int node) > +{ > + const __be32 *phy_handle; > + > + phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); > + if (phy_handle) { > + u32 ph = be32_to_cpup(phy_handle); > + int p = fdt_node_offset_by_phandle(initial_boot_params, ph); > + if (p >= 0) > + fdt_nop_node(initial_boot_params, p); > + } > + fdt_nop_node(initial_boot_params, node); > +} > + > +static void __init octeon_fdt_pip_port(int iface, int i, int p, u64 *pmac) > +{ > + char name_buffer[20]; > + int eth; > + int phy_addr; > + > + snprintf(name_buffer, sizeof(name_buffer), "ethernet@%d", p); > + eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); > + if (eth < 0) > + return; > + if (p >= cvmx_helper_ports_on_interface(i)) { > + pr_notice("Deleting port %x:%x\n", i, p); > + octeon_fdt_rm_ethernet(eth); > + return; > + } > + > + phy_addr = cvmx_helper_board_get_mii_address(16 * i + p); > + octeon_fdt_set_phy(eth, phy_addr); > + octeon_fdt_set_mac_addr(eth, pmac); > +} > + > +static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) > +{ > + char name_buffer[20]; > + int iface; > + int p; > + > + cvmx_helper_interface_enumerate(idx); > + snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); > + iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); > + if (iface < 0) > + return; > + > + for (p = 0; p < 4; p++) > + octeon_fdt_pip_port(iface, idx, p, pmac); > +} > + > +int __init octeon_prune_device_tree(void) > +{ > + int i, max_port; > + const char *pip_path; > + char name_buffer[20]; > + int aliases; > + u64 mac_addr_base; > + > + if (fdt_check_header(initial_boot_params)) > + panic("Corrupt Device Tree."); > + > + aliases = fdt_path_offset(initial_boot_params, "/aliases"); > + if (aliases < 0) { > + pr_err("Error: No /aliases node in device tree."); > + return -EINVAL; > + } > + > + > + mac_addr_base = > + ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | > + ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | > + ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | > + ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | > + ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | > + (octeon_bootinfo->mac_addr_base[5] & 0xffull); > + > + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) > + max_port = 2; > + else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) > + max_port = 1; > + else > + max_port = 0; > + > + for (i = 0; i < 2; i++) { > + const char *alias_prop; > + int mgmt; > + snprintf(name_buffer, sizeof(name_buffer), > + "mix%d", i); > + alias_prop = fdt_getprop(initial_boot_params, aliases, > + name_buffer, NULL); > + if (alias_prop) { > + mgmt = fdt_path_offset(initial_boot_params, alias_prop); > + if (mgmt < 0) > + continue; > + if (i >= max_port) { > + pr_notice("Deleting mix%d\n", i); > + octeon_fdt_rm_ethernet(mgmt); > + fdt_nop_property(initial_boot_params, aliases, > + name_buffer); > + } else { > + octeon_fdt_set_phy(mgmt, i); > + octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); > + } > + } > + } > + > + pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); > + if (pip_path) { > + int pip = fdt_path_offset(initial_boot_params, pip_path); > + if (pip >= 0) > + for (i = 0; i < 4; i++) > + octeon_fdt_pip_iface(pip, i, &mac_addr_base); > + } > + > + /* I2C */ > + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || > + OCTEON_IS_MODEL(OCTEON_CN63XX) || > + OCTEON_IS_MODEL(OCTEON_CN56XX)) > + max_port = 2; > + else > + max_port = 1; > + > + for (i = 0; i < 2; i++) { > + const char *alias_prop; > + int i2c; > + snprintf(name_buffer, sizeof(name_buffer), > + "twsi%d", i); > + alias_prop = fdt_getprop(initial_boot_params, aliases, > + name_buffer, NULL); > + > + if (alias_prop) { > + i2c = fdt_path_offset(initial_boot_params, alias_prop); > + if (i2c < 0) > + continue; > + if (i >= max_port) { > + pr_notice("Deleting i2c%d\n", i); > + fdt_nop_node(initial_boot_params, i2c); > + } > + } > + } > + > + return 0; > +} > + > +static int __init octeon_publish_devices(void) > +{ > + return of_platform_bus_probe(NULL, octeon_ids, NULL); > +} > +device_initcall(octeon_publish_devices); > + > + > MODULE_AUTHOR("David Daney "); > MODULE_LICENSE("GPL"); > MODULE_DESCRIPTION("Platform driver for Octeon SOC"); > diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c > index ab1a106..02765d6 100644 > --- a/arch/mips/cavium-octeon/setup.c > +++ b/arch/mips/cavium-octeon/setup.c > @@ -20,6 +20,7 @@ > #include > #include > #include > +#include > #ifdef CONFIG_BLK_DEV_INITRD > #include > #endif > @@ -797,3 +798,19 @@ void prom_free_prom_memory(void) > } > #endif > } > + > +int octeon_prune_device_tree(void); > + > +extern const char __dtb_octeon_3xxx_begin; > +extern const char __dtb_octeon_3xxx_end; > +void __init device_tree_init(void) > +{ > + int dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; > + /* Copy the default tree from init memory. */ > + initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); > + if (initial_boot_params == NULL) > + panic("Could not allocate initial_boot_params\n"); > + memcpy(initial_boot_params, &__dtb_octeon_3xxx_begin, dt_size); > + octeon_prune_device_tree(); > + unflatten_device_tree(); > +} > -- > 1.7.2.3 > From dgibson@ozlabs.org Sat Mar 5 09:30:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Mar 2011 09:30:31 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:46837 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491017Ab1CEIaH (ORCPT ); Sat, 5 Mar 2011 09:30:07 +0100 Received: by ozlabs.org (Postfix, from userid 1007) id 02AB2B70E3; Sat, 5 Mar 2011 19:30:02 +1100 (EST) Date: Sat, 5 Mar 2011 19:24:09 +1100 From: David Gibson To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 02/12] of: Allow scripts/dtc/libfdt to be used from kernel code Message-ID: <20110305082409.GB3312@yookeroo> Mail-Followup-To: David Gibson , David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1299267744-17278-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29369 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david@gibson.dropbear.id.au Precedence: bulk X-list: linux-mips On Fri, Mar 04, 2011 at 11:42:14AM -0800, David Daney wrote: > Signed-off-by: David Daney [snip] > --- /dev/null > +++ b/lib/libfdt/libfdt_env.h > @@ -0,0 +1,21 @@ > +#ifndef _LIBFDT_ENV_H > +#define _LIBFDT_ENV_H > + > +#include > + > +#define _B(n) ((unsigned long long)((uint8_t *)&x)[n]) > +static inline uint32_t fdt32_to_cpu(uint32_t x) > +{ > + return (_B(0) << 24) | (_B(1) << 16) | (_B(2) << 8) | _B(3); > +} > +#define cpu_to_fdt32(x) fdt32_to_cpu(x) > + > +static inline uint64_t fdt64_to_cpu(uint64_t x) > +{ > + return (_B(0) << 56) | (_B(1) << 48) | (_B(2) << 40) | (_B(3) << 32) > + | (_B(4) << 24) | (_B(5) << 16) | (_B(6) << 8) | _B(7); > +} > +#define cpu_to_fdt64(x) fdt64_to_cpu(x) > +#undef _B Ah, yuck. I only used those nasty macros in the userspace version of libfdt_env.h because bytesex.h is such a portability nightmare. The kernel already has cpu_to_be{32,64}(), and the fdt byteswapping functions should just be aliased to them. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson From sam@ravnborg.org Sat Mar 5 23:04:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Mar 2011 23:04:53 +0100 (CET) Received: from pfepa.post.tele.dk ([195.41.46.235]:39825 "EHLO pfepa.post.tele.dk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491814Ab1CEWEu (ORCPT ); Sat, 5 Mar 2011 23:04:50 +0100 Received: from merkur.ravnborg.org (x1-6-30-46-9a-75-8a-52.k1039.webspeed.dk [93.167.48.205]) by pfepa.post.tele.dk (Postfix) with ESMTP id 8A398A5001B; Sat, 5 Mar 2011 23:04:46 +0100 (CET) Date: Sat, 5 Mar 2011 23:04:47 +0100 From: Sam Ravnborg To: Grant Likely Cc: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 02/12] of: Allow scripts/dtc/libfdt to be used from kernel code Message-ID: <20110305220447.GB21728@merkur.ravnborg.org> References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-3-git-send-email-ddaney@caviumnetworks.com> <20110305005750.GC7579@angua.secretlab.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110305005750.GC7579@angua.secretlab.ca> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29370 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips > > libfdt_env.h should be in include/linux > > > +#include "../../scripts/dtc/libfdt/fdt.h" > > +#include "../../scripts/dtc/libfdt/libfdt.h" > > Hmmm... I wonder if there is a better way to do this. I don't much > care for the relative path references. I assume: #include "scripts/dtc/libfdt/fdt.h" #include "scripts/dtc/libfdt/libfdt.h" works. Because working direcotry is root of kernel tree. But it is long time ago I played with this so my memory may foul me. Just noticed this... > > + > > +EXTRA_CFLAGS += -include $(src)/libfdt_env.h -I$(src)/../../scripts/dtc/libfdt "ccflags-y := ..." is recommended these days. Sam From dedekind1@gmail.com Mon Mar 7 10:00:12 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Mar 2011 10:00:15 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:39872 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491036Ab1CGJAM (ORCPT ); Mon, 7 Mar 2011 10:00:12 +0100 Received: by wwe15 with SMTP id 15so4239072wwe.24 for ; Mon, 07 Mar 2011 01:00:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:reply-to:to:cc:in-reply-to :references:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=nmM6ASsNO7sMYFATQoqN5B7MvJ2AU85hJ3FaMo5bKq8=; b=ohPeP8oGV2DnIURDzKtFn1PjtIduq8AsqgJyc/94GPoGYoRglKui7ZqLLN/gNJfFif MIXJn/r+b4mLNbFrNDzH0nU7APQEP2TwqjXZv3rRK+H2diDQNJGGC9vjz0VZO5SPWSUu hFei6JpSEABsL8W6lb2des2hp0U9c/ZPr33yU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; b=JdqkfNuPfv1cQKHE8WeN/vvyIvtCb+Fia66Ic1JjV8vFeL9T70dHt+I6VA/6W9tjWm E5caDZ+wL1uI430hIWRoNaJKm8d286D5lxMLMsWMA6v9iyTZZ9nSVC6UWCTcSinU3jXc Ntne4ev8o18K6au7kRvB4rJQJFs4W3wt+w1qU= Received: by 10.216.221.14 with SMTP id q14mr2165055wep.49.1299488406259; Mon, 07 Mar 2011 01:00:06 -0800 (PST) Received: from ?IPv6:::1? (shutemov.name [188.40.19.243]) by mx.google.com with ESMTPS id n1sm1156660weq.7.2011.03.07.01.00.02 (version=SSLv3 cipher=OTHER); Mon, 07 Mar 2011 01:00:04 -0800 (PST) Subject: Re: [PATCH V2 06/10] MIPS: lantiq: add NOR flash support From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: John Crispin Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse In-Reply-To: <1298996006-15960-7-git-send-email-blogic@openwrt.org> References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-7-git-send-email-blogic@openwrt.org> Content-Type: text/plain; charset="UTF-8" Date: Mon, 07 Mar 2011 10:58:40 +0200 Message-ID: <1299488320.2746.5.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.32.1 (2.32.1-1.fc14) Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29371 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2011-03-01 at 17:13 +0100, John Crispin wrote: > NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described > in the PCI patch, the EBU is a little buggy, resulting in the upper and lower > 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2) > > To work around this we do a addr^=2 during the probe. Once probed we adapt > cfi->addr_unlock1 and cfi->addr_unlock2 to represent the endianess bug. > > Changes in V2 > * handle the endianess bug inside the map code and not in the generic cfi code > * remove the addr swizzle patch > > Signed-off-by: John Crispin > Signed-off-by: Ralph Hempel > Cc: David Woodhouse > Cc: Daniel Schwierzeck > Cc: linux-mips@linux-mips.org > Cc: linux-mtd@lists.infradead.org There are a couple checkpatch.pl warnings, would you please address them and resend? -- Best Regards, Artem Bityutskiy (Артём Битюцкий) From blogic@openwrt.org Mon Mar 7 13:24:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Mar 2011 13:24:28 +0100 (CET) Received: from nbd.name ([46.4.11.11]:34172 "EHLO nbd.name" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491862Ab1CGMYZ (ORCPT ); Mon, 7 Mar 2011 13:24:25 +0100 Message-ID: <4D74CEC2.4040506@openwrt.org> Date: Mon, 07 Mar 2011 13:25:38 +0100 From: John Crispin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100913 Icedove/3.0.7 MIME-Version: 1.0 To: dedekind1@gmail.com CC: Ralf Baechle , linux-mips@linux-mips.org, Ralph Hempel , linux-mtd@lists.infradead.org, Daniel Schwierzeck , David Woodhouse Subject: Re: [PATCH V2 06/10] MIPS: lantiq: add NOR flash support References: <1298996006-15960-1-git-send-email-blogic@openwrt.org> <1298996006-15960-7-git-send-email-blogic@openwrt.org> <1299488320.2746.5.camel@localhost> In-Reply-To: <1299488320.2746.5.camel@localhost> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29372 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: blogic@openwrt.org Precedence: bulk X-list: linux-mips On 07/03/11 09:58, Artem Bityutskiy wrote: > On Tue, 2011-03-01 at 17:13 +0100, John Crispin wrote: > >> NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described >> in the PCI patch, the EBU is a little buggy, resulting in the upper and lower >> 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2) >> >> To work around this we do a addr^=2 during the probe. Once probed we adapt >> cfi->addr_unlock1 and cfi->addr_unlock2 to represent the endianess bug. >> >> Changes in V2 >> * handle the endianess bug inside the map code and not in the generic cfi code >> * remove the addr swizzle patch >> >> Signed-off-by: John Crispin >> Signed-off-by: Ralph Hempel >> Cc: David Woodhouse >> Cc: Daniel Schwierzeck >> Cc: linux-mips@linux-mips.org >> Cc: linux-mtd@lists.infradead.org >> > There are a couple checkpatch.pl warnings, would you please address them > and resend? > > Hi, of course. thanks, John From info@western.com Wed Mar 9 10:36:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Mar 2011 10:36:52 +0100 (CET) Received: from smtp4.cica.es ([150.214.5.182]:43328 "EHLO smtp.cica.es" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492015Ab1CIJgs convert rfc822-to-8bit (ORCPT ); Wed, 9 Mar 2011 10:36:48 +0100 Received: from localhost (unknown [127.0.0.1]) by smtp.cica.es (Postfix) with ESMTP id A33D7F453A; Wed, 9 Mar 2011 09:36:38 +0000 (UTC) X-Virus-Scanned: amavisd-new at cica.es Received: from smtp.cica.es ([127.0.0.1]) by localhost (mail.cica.es [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nUWQmOmEIt9y; Wed, 9 Mar 2011 10:36:38 +0100 (CET) Received: by smtp.cica.es (Postfix, from userid 48) id AA815F4535; Wed, 9 Mar 2011 10:36:37 +0100 (CET) Received: from 74-115-3-61.anchorfree.com (74-115-3-61.anchorfree.com [74.115.3.61]) by webmail.cica.es (Horde Framework) with HTTP; Wed, 09 Mar 2011 10:36:36 +0100 Message-ID: <20110309103636.12156odh9eqwobvo@webmail.cica.es> Date: Wed, 09 Mar 2011 10:36:36 +0100 From: Western Union Office Reply-to: westernu9@w.cn To: undisclosed-recipients:; Subject: Dear Western Union Customer MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; DelSp="Yes"; format="flowed" Content-Disposition: inline Content-Transfer-Encoding: 8BIT User-Agent: Internet Messaging Program (IMP) H3 (4.3.4) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29373 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: info@western.com Precedence: bulk X-list: linux-mips -- Welcome To Western Union Office REF NO: 245/0090/11 BATCH: 2010/wumt/393 Website: www.westernunion.com Dear Western Union Customer, You have been awarded with the sum of $50,000 USD by our office, as one of our customers who use Western Union in their daily business transaction. This award was been selected through the internet, where your e-mail address was indicated and notified. It is a Grand Donation from the United Nation to support individuals financially due to the global and financial economic meltdown. Your email address was selected globally as one of the beneficiaries this year. Please provide Mr. Bruce Anthony with the following details listed below so that your fund will be remited to you through Western Union. 1. Name:______ 2. Address:______ 3. Country:_______ 4. Phone Number:____ Mr. Bruce Anthony (Transfer Officer) TEL: +234 8075700974 E-Mail: westernu9@w.cn As soon as these details are received and verified, your fund will be transferred to you. Thank you, for using western union. ---------------------------------------------------------------- This message was sent using IMP, the Internet Messaging Program. From David.Daney@caviumnetworks.com Fri Mar 11 19:27:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Mar 2011 19:28:01 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4953 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491203Ab1CKS16 (ORCPT ); Fri, 11 Mar 2011 19:27:58 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 11 Mar 2011 10:28:49 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 11 Mar 2011 10:27:54 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 11 Mar 2011 10:27:53 -0800 Message-ID: <4D7A69A9.40206@caviumnetworks.com> Date: Fri, 11 Mar 2011 10:27:53 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Grant Likely CC: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 06/12] MIPS: Octeon: Add a irq_create_of_mapping() implementation. References: <1299267744-17278-1-git-send-email-ddaney@caviumnetworks.com> <1299267744-17278-7-git-send-email-ddaney@caviumnetworks.com> <20110305010746.GD7579@angua.secretlab.ca> In-Reply-To: <20110305010746.GD7579@angua.secretlab.ca> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 11 Mar 2011 18:27:53.0951 (UTC) FILETIME=[094576F0:01CBE01A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29374 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 03/04/2011 05:07 PM, Grant Likely wrote: > On Fri, Mar 04, 2011 at 11:42:18AM -0800, David Daney wrote: [...] >> +/* >> + * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# >> + * >> + * Octeon irq maps are a pair of indexes. The first selects either >> + * ciu0 or ciu1, the second is the bit within the ciu register. >> + */ > > Is each 'ciu' an interrupt controller, or a 'bank' within the > controller? The ciu0 and ciu1 are 'banks' within a single interrupt controller. Each of these 'banks' has 64 bits, each bit corresponds to the finest grained source that can be routed via the interrupt infrastructure. Each interrupt source can therefore be completely specified by its bank and bit numbers. > Also, it is typical to have another cell for specifying > flags if there is any kind of configuration for each irq line, like > edge vs. level and active high or active low. (the counter example is > PCI which doesn't use a flags cell because all PCI irqs are level > active. > If you look in patch 04/12, you will see that I have added such a flag cell to the device tree. In the next revision of this patch, I will be adding the logic to actually configure the polarity and triggering based on the flag cell. There are only 16 sources (GPIO pins that can actually be configured. The remaining sources will ignore the triggering flags as they are hard wired. > You'll need to supply documentation for the ciu binding to > Documentation/devicetree/bindings before this patch gets merged. OK, I will work on that too. Thanks, David Daney From jayachandranc@netlogicmicro.com Sat Mar 12 19:22:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Mar 2011 19:23:03 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:3645 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491855Ab1CLSWy (ORCPT ); Sat, 12 Mar 2011 19:22:54 +0100 X-TM-IMSS-Message-ID: <115987710000acbd@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 115987710000acbd ; Sat, 12 Mar 2011 10:22:43 -0800 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Sat, 12 Mar 2011 10:22:33 -0800 Date: Sat, 12 Mar 2011 23:57:14 +0530 From: "Jayachandran C." To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH] Support for Netlogic XLR/XLS processors Message-ID: <20110312182714.GC2217@jayachandranc.netlogicmicro.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="zhXaljGHf11kAtnf" Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 12 Mar 2011 18:22:33.0591 (UTC) FILETIME=[74BC2870:01CBE0E2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29375 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips --zhXaljGHf11kAtnf Content-Type: text/plain; charset=us-ascii Content-Disposition: inline I would like to start the process of contributing support for Netlogic XLR/XLS and XLP processors into linux mips. Our linux code is currently maintained internally as a Software Development Kit distributed to customers, and the plan is to move to a more open model for Linux development. As part of this, I would like to extract relevant parts of the SDK, clean it up, re-base t and submit for inclusion in the linux-mips tree. This is the very first (and self contained) patch), which adds basic support for Netlogic XLR and XLS processors. If all goes well, I would like to follow it up with patches for XLP processors, and patches for device support for both XLR/XLS and XLP processors. The attached patch adds Netlogic XLR CPU support, support for platform UART, PIC, and SMP support. The code is licensed with a 2-clause BSD license which should be compatible with GPL2. Please let me know your comments, the patches can be split up further if needed, and any comments on code, coding style oj better ways of implementation are welcome. Even thought just the netlogic/xlr directory is present now, we will be adding a netlogic/xlp directory when the XLP processor support is added. Regards, JC. -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Processors India) jchandra@freebsd.org (The FreeBSD Project) --zhXaljGHf11kAtnf Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="mips-netlogic-xlr-support.diff" Support for Netlogic XLR and XLS processors. Add support for XLR and XLS families of multi-core MIPS64 SoCs from Netlogic Microsystems. The changes are: * support for XLR/XLS in the kernel config and build * support for XLR and XLS cpu types in MIPS cpu probe. * XLR/XLS cache support with mm/c-netlogic.c. * Platform UART and early printk support * IRQs with XLR/XLS PIC * SMP support for upto 32 processors (8 cores, 4 threads per core). These changes enable us to boot linux-mips on Netlogic evaluation boards from the netlogic bootloader. Signed-off-by: Jayachandran C. diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d889835..a955ced 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -735,6 +735,33 @@ config CAVIUM_OCTEON_REFERENCE_BOARD Hikari Say Y here for most Octeon reference boards. +config NLM_XLR_BOARD + bool "Netlogic XLR/XLS based systems" + depends on EXPERIMENTAL + select BOOT_ELF32 + select NLM_COMMON + select NLM_XLR + select SYS_HAS_CPU_XLR + select SYS_SUPPORTS_SMP + select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select 64BIT_PHYS_ADDR + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select DMA_COHERENT + select NR_CPUS_DEFAULT_32 + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select ZONE_DMA if 64BIT + select SYNC_R4K + select SYS_HAS_EARLY_PRINTK + help + Support for systems based on Netlogic XLR and XLS processors. + Say Y here if you have a XLR or XLS based board. + endchoice source "arch/mips/alchemy/Kconfig" @@ -751,6 +778,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/netlogic/Kconfig" endmenu @@ -1417,6 +1445,17 @@ config CPU_BMIPS5000 help Broadcom BMIPS5000 processors. +config CPU_XLR + bool "Netlogic XLR SoC" + depends on SYS_HAS_CPU_XLR + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select CPU_SUPPORTS_HUGEPAGES + help + Netlogic Microsystems XLR/XLS processors. endchoice if CPU_LOONGSON2F @@ -1547,6 +1586,9 @@ config SYS_HAS_CPU_BMIPS4380 config SYS_HAS_CPU_BMIPS5000 bool +config SYS_HAS_CPU_XLR + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7c1102e..63182c9 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -191,6 +191,18 @@ endif # include $(srctree)/arch/mips/Kbuild.platforms +# +# NETLOGIC SOC Common (common) +# +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic + +# +# NETLOGIC XLR/XLS SoC, Simulator and boards +# +core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ +load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 + cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig new file mode 100644 index 0000000..b747e82 --- /dev/null +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -0,0 +1,1700 @@ +# +# Automatically generated make config: don't edit +# Linux/mips 2.6.38-rc7 Kernel Configuration +# Tue Mar 8 16:18:25 2011 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_NLM_XLR_BOARD=y +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_NLM_COMMON=y +CONFIG_NLM_XLR=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYNC_R4K=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_XLR=y +CONFIG_SYS_HAS_CPU_XLR=y +CONFIG_WEAK_ORDERING=y +CONFIG_WEAK_REORDERING_BEYOND_LLSC=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_SMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_32=y +CONFIG_NR_CPUS=32 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_KEXEC=y +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED is not set +# CONFIG_HAVE_SPARSE_IRQ is not set +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_PENDING_IRQ is not set +# CONFIG_AUTO_IRQ_AFFINITY is not set +CONFIG_IRQ_PER_CPU=y +# CONFIG_HARDIRQS_SW_RESEND is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +# CONFIG_EMBEDDED is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_VERBOSE is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM_OPS=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +# CONFIG_IP_VS_PE_SIP is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +CONFIG_PHONET=m +# CONFIG_PHONET_PIPECTRLR is not set +CONFIG_IEEE802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_RPS=y +CONFIG_XPS=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=y +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FC_TGT_ATTRS=y +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +# CONFIG_ISCSI_BOOT_SYSFS is not set +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_N_HDLC=m +# CONFIG_N_GSM is not set +CONFIG_RISCOM8=m +CONFIG_SPECIALIX=m +CONFIG_STALDRV=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=m +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XZ is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EXOFS_FS=m +# CONFIG_EXOFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_NEW_IDMAPPER is not set +CONFIG_NFSD=m +CONFIG_NFSD_DEPRECATED=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_ACL is not set +CONFIG_CIFS_EXPERIMENTAL=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +# CONFIG_NCPFS_SMALLDOS is not set +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +# CONFIG_AFS_DEBUG is not set +# CONFIG_AFS_FSCACHE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +# CONFIG_ACORN_PARTITION_CUMANA is not set +# CONFIG_ACORN_PARTITION_EESOX is not set +CONFIG_ACORN_PARTITION_ICS=y +# CONFIG_ACORN_PARTITION_ADFS is not set +# CONFIG_ACORN_PARTITION_POWERTEC is not set +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +CONFIG_BKL=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_DETECTOR_RUNNABLE=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +# CONFIG_KGDB_LOW_LEVEL_TRAP is not set +# CONFIG_KGDB_KDB is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_TOMOYO=y +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_IMA is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=m +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_VIRTUALIZATION is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7..bbf8f35 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -41,6 +41,9 @@ #ifndef cpu_has_octeon_cache #define cpu_has_octeon_cache 0 #endif +#ifndef cpu_has_netlogic_cache +#define cpu_has_netlogic_cache 0 +#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..34c0d3c 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 @@ -142,6 +143,31 @@ #define PRID_IMP_JZRISC 0x0200 /* + * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC + */ +#define PRID_IMP_NETLOGIC_XLR732 0x0000 +#define PRID_IMP_NETLOGIC_XLR716 0x0200 +#define PRID_IMP_NETLOGIC_XLR532 0x0900 +#define PRID_IMP_NETLOGIC_XLR308 0x0600 +#define PRID_IMP_NETLOGIC_XLR532C 0x0800 +#define PRID_IMP_NETLOGIC_XLR516C 0x0a00 +#define PRID_IMP_NETLOGIC_XLR508C 0x0b00 +#define PRID_IMP_NETLOGIC_XLR308C 0x0f00 +#define PRID_IMP_NETLOGIC_XLS608 0x8000 +#define PRID_IMP_NETLOGIC_XLS408 0x8800 +#define PRID_IMP_NETLOGIC_XLS404 0x8c00 +#define PRID_IMP_NETLOGIC_XLS208 0x8e00 +#define PRID_IMP_NETLOGIC_XLS204 0x8f00 +#define PRID_IMP_NETLOGIC_XLS108 0xce00 +#define PRID_IMP_NETLOGIC_XLS104 0xcf00 +#define PRID_IMP_NETLOGIC_XLS616B 0x4000 +#define PRID_IMP_NETLOGIC_XLS608B 0x4a00 +#define PRID_IMP_NETLOGIC_XLS416B 0x4400 +#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 +#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 +#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 + +/* * Definitions for 7:0 on legacy processors */ @@ -234,6 +260,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, + CPU_XLR, CPU_LAST }; diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h new file mode 100644 index 0000000..7740401 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H + +/* + * Most of the properties are in cpu->options + */ +#define cpu_has_netlogic_cache 1 + +#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h new file mode 100644 index 0000000..b590245 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/irq.h @@ -0,0 +1,14 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + */ +#ifndef __ASM_NETLOGIC_IRQ_H +#define __ASM_NETLOGIC_IRQ_H + +#define NR_IRQS 64 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* __ASM_NETLOGIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h new file mode 100644 index 0000000..22da893 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/war.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_NLM_WAR_H +#define __ASM_MIPS_MACH_NLM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_NLM_WAR_H */ diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index d94085a..bc01a02 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON2 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " +#elif defined CONFIG_CPU_XLR +#define MODULE_PROC_FAMILY "XLR " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h new file mode 100644 index 0000000..433f7e2 --- /dev/null +++ b/arch/mips/include/asm/netlogic/interrupt.h @@ -0,0 +1,39 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_INTERRUPT_H +#define _ASM_NLM_INTERRUPT_H + +/* Defines for the IRQ numbers */ + +#define IRQ_IPI_SMP_FUNCTION 3 +#define IRQ_IPI_SMP_RESCHEDULE 4 +#define IRQ_MSGRING 6 +#define IRQ_TIMER 7 + +#endif diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h new file mode 100644 index 0000000..d08359a --- /dev/null +++ b/arch/mips/include/asm/netlogic/mips-extns.h @@ -0,0 +1,69 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _ASM_NLM_MIPS_EXTS_H +#define _ASM_NLM_MIPS_EXTS_H + +/* + * XLR and XLP interrupt request and interrupt mask registers + */ +#define read_c0_eirr() __read_64bit_c0_register($9, 6) +#define read_c0_eimr() __read_64bit_c0_register($9, 7) +#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val) + +/* + * Writing EIMR in 32 bit is a special case, the lower 8 bit of the + * EIMR is shadowed in the status register, so we cannot save and + * restore status register for split read. + */ +#define write_c0_eimr(val) \ +do { \ + if (sizeof(unsigned long) == 4) { \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, $9, 7\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\ + local_irq_restore(__flags); \ + } else \ + __write_64bit_c0_register($9, 7, (val)); \ +} while (0) + +static inline int hard_smp_processor_id(void) +{ + return __read_32bit_c0_register($15, 1) & 0x3ff; +} + +#endif /*_ASM_NLM_MIPS_EXTS_H */ diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h new file mode 100644 index 0000000..8283f03 --- /dev/null +++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h @@ -0,0 +1,103 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NETLOGIC_BOOTINFO_H +#define _ASM_NETLOGIC_BOOTINFO_H + +struct psb_info { + uint64_t boot_level; + uint64_t io_base; + uint64_t output_device; + uint64_t uart_print; + uint64_t led_output; + uint64_t init; + uint64_t exit; + uint64_t warm_reset; + uint64_t wakeup; + uint64_t online_cpu_map; + uint64_t master_reentry_sp; + uint64_t master_reentry_gp; + uint64_t master_reentry_fn; + uint64_t slave_reentry_fn; + uint64_t magic_dword; + uint64_t uart_putchar; + uint64_t size; + uint64_t uart_getchar; + uint64_t nmi_handler; + uint64_t psb_version; + uint64_t mac_addr; + uint64_t cpu_frequency; + uint64_t board_version; + uint64_t malloc; + uint64_t free; + uint64_t global_shmem_addr; + uint64_t global_shmem_size; + uint64_t psb_os_cpu_map; + uint64_t userapp_cpu_map; + uint64_t wakeup_os; + uint64_t psb_mem_map; + uint64_t board_major_version; + uint64_t board_minor_version; + uint64_t board_manf_revision; + uint64_t board_serial_number; + uint64_t psb_physaddr_map; + uint64_t xlr_loaderip_config; + uint64_t bldr_envp; + uint64_t avail_mem_map; +}; + +enum { + NETLOGIC_IO_SPACE = 0x10, + PCIX_IO_SPACE, + PCIX_CFG_SPACE, + PCIX_MEMORY_SPACE, + HT_IO_SPACE, + HT_CFG_SPACE, + HT_MEMORY_SPACE, + SRAM_SPACE, + FLASH_CONTROLLER_SPACE +}; + +#define NLM_MAX_ARGS 64 +#define NLM_MAX_ENVS 32 + +/* This is what netlboot passes and linux boot_mem_map is subtly different */ +#define NLM_BOOT_MEM_MAP_MAX 32 +struct nlm_boot_mem_map { + int nr_map; + struct nlm_boot_mem_map_entry { + uint64_t addr; /* start of memory segment */ + uint64_t size; /* size of memory segment */ + uint32_t type; /* type of memory segment */ + } map[NLM_BOOT_MEM_MAP_MAX]; +}; + +/* Pointer to saved boot loader info */ +extern struct psb_info nlm_prom_info; + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h new file mode 100644 index 0000000..2782c97 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/gpio.h @@ -0,0 +1,67 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_GPIO_H +#define _ASM_NLM_GPIO_H + +#define NETLOGIC_GPIO_INT_EN_REG 0 +#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 +#define NETLOGIC_GPIO_IO_DIR_REG 2 +#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 +#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 + +#define NETLOGIC_GPIO_SWRESET_REG 8 +#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 +#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 +#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 +#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 +#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 +#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 +#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 +#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 + +#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 +#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 +#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 +#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 + +#define NETLOGIC_GPIO_FUSE_BANK_REG 35 +#define NETLOGIC_GPIO_CPU_RESET_REG 40 +#define NETLOGIC_GPIO_RNG_REG 43 + +#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 +#define NETLOGIC_GPIO_LED_BITMAP 0x1700000 +#define NETLOGIC_GPIO_LED_0_SHIFT 20 +#define NETLOGIC_GPIO_LED_1_SHIFT 24 + +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h new file mode 100644 index 0000000..79d2a16 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/iomap.h @@ -0,0 +1,125 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_IOMAP_H +#define _ASM_NLM_IOMAP_H + +#define DEFAULT_NETLOGIC_IO_BASE KSEG1ADDR(0x1ef00000) +#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 +#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 +#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 +#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 +#define NETLOGIC_IO_PIC_OFFSET 0x08000 +#define NETLOGIC_IO_UART_0_OFFSET 0x14000 +#define NETLOGIC_IO_UART_1_OFFSET 0x15100 + +#define NETLOGIC_IO_SIZE 0x1000 + +#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 + +#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 +#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 + +#define NETLOGIC_IO_SRAM_OFFSET 0x07000 + +#define NETLOGIC_IO_PCIX_OFFSET 0x09000 +#define NETLOGIC_IO_HT_OFFSET 0x0A000 + +#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 + +#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 +#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 +#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 +#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 + +/* XLS devices */ +#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 +#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 +#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 +#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 + +#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 +#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 +#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 +#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 + +#define NETLOGIC_IO_USB_0_OFFSET 0x24000 +#define NETLOGIC_IO_USB_1_OFFSET 0x25000 + +#define NETLOGIC_IO_COMP_OFFSET 0x1D000 +/* end XLS devices */ + +/* XLR devices */ +#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 +#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 +#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 +#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 +/* end XLR devices */ + +#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 +#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 + +#define NETLOGIC_IO_GPIO_OFFSET 0x18000 +#define NETLOGIC_IO_FLASH_OFFSET 0x19000 +#define NETLOGIC_IO_TB_OFFSET 0x1C000 + +#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) + +/* + * Base Address (Virtual) of the PCI Config address space + * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28) + * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes + * ie 1<<24 = 16M + */ +#define DEFAULT_PCI_CONFIG_BASE 0x18000000 +#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 +#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 + +#ifndef __ASSEMBLY__ +#include +#include + +typedef volatile __u32 nlm_reg_t; +extern unsigned long netlogic_io_base; + +/* FIXME read once in write_reg */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define netlogic_read_reg(base, offset) ((base)[(offset)]) +#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value)) +#else +#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)])) +#define netlogic_write_reg(base, offset, value) \ + ((base)[(offset)] = cpu_to_be32((value))) +#endif + +#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)])) +#define netlogic_write_reg_le32(base, offset, value) \ + ((base)[(offset)] = cpu_to_le32((value))) +#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset))) +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h new file mode 100644 index 0000000..61da78d --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -0,0 +1,225 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_XLR_PIC_H +#define _ASM_NLM_XLR_PIC_H + +#define PIC_CLKS_PER_SEC 66666666ULL +/* PIC hardware interrupt numbers */ +#define PIC_IRT_WD_INDEX 0 +#define PIC_IRT_TIMER_0_INDEX 1 +#define PIC_IRT_TIMER_1_INDEX 2 +#define PIC_IRT_TIMER_2_INDEX 3 +#define PIC_IRT_TIMER_3_INDEX 4 +#define PIC_IRT_TIMER_4_INDEX 5 +#define PIC_IRT_TIMER_5_INDEX 6 +#define PIC_IRT_TIMER_6_INDEX 7 +#define PIC_IRT_TIMER_7_INDEX 8 +#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX +#define PIC_IRT_UART_0_INDEX 9 +#define PIC_IRT_UART_1_INDEX 10 +#define PIC_IRT_I2C_0_INDEX 11 +#define PIC_IRT_I2C_1_INDEX 12 +#define PIC_IRT_PCMCIA_INDEX 13 +#define PIC_IRT_GPIO_INDEX 14 +#define PIC_IRT_HYPER_INDEX 15 +#define PIC_IRT_PCIX_INDEX 16 +/* XLS */ +#define PIC_IRT_CDE_INDEX 15 +#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16 +/* XLS */ +#define PIC_IRT_GMAC0_INDEX 17 +#define PIC_IRT_GMAC1_INDEX 18 +#define PIC_IRT_GMAC2_INDEX 19 +#define PIC_IRT_GMAC3_INDEX 20 +#define PIC_IRT_XGS0_INDEX 21 +#define PIC_IRT_XGS1_INDEX 22 +#define PIC_IRT_HYPER_FATAL_INDEX 23 +#define PIC_IRT_PCIX_FATAL_INDEX 24 +#define PIC_IRT_BRIDGE_AERR_INDEX 25 +#define PIC_IRT_BRIDGE_BERR_INDEX 26 +#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27 +#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28 +/* XLS */ +#define PIC_IRT_GMAC4_INDEX 21 +#define PIC_IRT_GMAC5_INDEX 22 +#define PIC_IRT_GMAC6_INDEX 23 +#define PIC_IRT_GMAC7_INDEX 24 +#define PIC_IRT_BRIDGE_ERR_INDEX 25 +#define PIC_IRT_PCIE_LINK0_INDEX 26 +#define PIC_IRT_PCIE_LINK1_INDEX 27 +#define PIC_IRT_PCIE_LINK2_INDEX 23 +#define PIC_IRT_PCIE_LINK3_INDEX 24 +#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28 +#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29 +#define PIC_IRT_SRIO_LINK0_INDEX 26 +#define PIC_IRT_SRIO_LINK1_INDEX 27 +#define PIC_IRT_SRIO_LINK2_INDEX 28 +#define PIC_IRT_SRIO_LINK3_INDEX 29 +#define PIC_IRT_PCIE_INT_INDEX 28 +#define PIC_IRT_PCIE_FATAL_INDEX 29 +#define PIC_IRT_GPIO_B_INDEX 30 +#define PIC_IRT_USB_INDEX 31 +/* XLS */ +#define PIC_NUM_IRTS 32 + + +#define PIC_CLOCK_TIMER 7 + +/* PIC Registers */ +#define PIC_CTRL 0x00 +#define PIC_IPI 0x04 +#define PIC_INT_ACK 0x06 + +#define WD_MAX_VAL_0 0x08 +#define WD_MAX_VAL_1 0x09 +#define WD_MASK_0 0x0a +#define WD_MASK_1 0x0b +#define WD_HEARBEAT_0 0x0c +#define WD_HEARBEAT_1 0x0d + +#define PIC_IRT_0_BASE 0x40 +#define PIC_IRT_1_BASE 0x80 +#define PIC_TIMER_MAXVAL_0_BASE 0x100 +#define PIC_TIMER_MAXVAL_1_BASE 0x110 +#define PIC_TIMER_COUNT_0_BASE 0x120 +#define PIC_TIMER_COUNT_1_BASE 0x130 + +#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) +#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) + +#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) +#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i)) +#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i)) +#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i)) + +/* + * Mapping between hardware interrupt numbers and IRQs on CPU + * we use a simple scheme to map PIC interrupts 0-31 to IRQs + * 8-39. This leaves the IRQ 0-7 for cpu interrupts like + * count/compare and FMN + */ +#define PIC_IRQ_BASE 8 +#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) +#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) + +#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE +#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) +#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX) +#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX) +#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX) +#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX) +#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX) +#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX) +#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX) +#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX) +#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ) +#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX) +#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX) +#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX) +#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX) +#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX) +#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX) +#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX) +#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX) +/* XLS */ +#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX) +#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX) +/* end XLS */ +#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX) +#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX) +#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX) +#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX) +#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX) +#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX) +#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX) +#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX) +#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) +#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) +#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) +#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) +/* XLS defines */ +#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) +#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) +#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX) +#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX) +#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX) +#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX) +#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX) +#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX) +#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX) +#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX) +#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX) +#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX) +#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX) +#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX) +#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX) +#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX) +#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX) +#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX) +#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX) +#define PIC_IRT_LAST_IRQ PIC_USB_IRQ +/* end XLS */ + +#ifndef __ASSEMBLY__ +static inline void pic_send_ipi(u32 ipi) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_IPI, ipi); +} + +static inline u32 pic_read_control(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + return netlogic_read_reg(mmio, PIC_CTRL); +} + +static inline void pic_write_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, control); +} + +static inline void pic_update_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, + (control | netlogic_read_reg(mmio, PIC_CTRL))); +} + +#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ + ((irq) <= PIC_TIMER_7_IRQ)) +#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ + ((irq) <= PIC_IRT_LAST_IRQ)) +#endif + +#endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h new file mode 100644 index 0000000..174bbdd --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -0,0 +1,20 @@ +#ifndef _ASM_NLM_XLR_H +#define _ASM_NLM_XLR_H + +/* Platform UART functions */ +struct uart_port; +unsigned int nlm_xlr_uart_in(struct uart_port *, int); +void nlm_xlr_uart_out(struct uart_port *, int, int); + +/* SMP support functions */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); +int nlm_wakeup_secondary_cpus(u32 wakeup_mask); +void nlm_smp_irq_init(void); +void nlm_boot_smp_nmi(void); +void prom_pre_boot_secondary_cpus(void); + +extern struct plat_smp_ops nlm_smp_ops; +extern unsigned long nlm_common_ebase; + +#endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cedee2b..83bba33 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o +obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..a995d56 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + c->options = (MIPS_CPU_TLB | + MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | + MIPS_CPU_WATCH | + MIPS_CPU_EJTAG | + MIPS_CPU_LLSC); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_NETLOGIC_XLR732: + case PRID_IMP_NETLOGIC_XLR716: + case PRID_IMP_NETLOGIC_XLR532: + case PRID_IMP_NETLOGIC_XLR308: + case PRID_IMP_NETLOGIC_XLR532C: + case PRID_IMP_NETLOGIC_XLR516C: + case PRID_IMP_NETLOGIC_XLR508C: + case PRID_IMP_NETLOGIC_XLR308C: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLR"; + break; + + case PRID_IMP_NETLOGIC_XLS608: + case PRID_IMP_NETLOGIC_XLS408: + case PRID_IMP_NETLOGIC_XLS404: + case PRID_IMP_NETLOGIC_XLS208: + case PRID_IMP_NETLOGIC_XLS204: + case PRID_IMP_NETLOGIC_XLS108: + case PRID_IMP_NETLOGIC_XLS104: + case PRID_IMP_NETLOGIC_XLS616B: + case PRID_IMP_NETLOGIC_XLS608B: + case PRID_IMP_NETLOGIC_XLS416B: + case PRID_IMP_NETLOGIC_XLS412B: + case PRID_IMP_NETLOGIC_XLS408B: + case PRID_IMP_NETLOGIC_XLS404B: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLS"; + break; + + default: + printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", + c->processor_id); + c->cputype = CPU_XLR; + break; + } + + c->isa_level = MIPS_CPU_ISA_M64R1; + c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; +} + #ifdef CONFIG_64BIT /* For use by uaccess.h */ u64 __ua_limit; @@ -1034,6 +1087,8 @@ __cpuinit void cpu_probe(void) break; case PRID_COMP_INGENIC: cpu_probe_ingenic(c, cpu); + case PRID_COMP_NETLOGIC: + cpu_probe_netlogic(c, cpu); break; } diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 2adead5..b2cad4f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o +obj-$(CONFIG_CPU_XLR) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index d679c77..7fea5ff 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o +obj-$(CONFIG_CPU_XLR) += c-netlogic.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/mm/c-netlogic.c b/arch/mips/mm/c-netlogic.c new file mode 100644 index 0000000..27a0067 --- /dev/null +++ b/arch/mips/mm/c-netlogic.c @@ -0,0 +1,450 @@ +/* + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2011 Netlogic Microsystems. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int icache_linesz; +static unsigned int icache_lines; + +#define cacheop(op, base) \ + __asm__ __volatile__ ( \ + " .set push\n" \ + " .set mips4\n" \ + " cache %0, 0(%1)\n" \ + " .set pop\n" \ + : : "i"(op), "r"(base)) + +#define cacheop_extable(op, base) do { \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set noreorder\n" \ + " .set mips4\n" \ + "1: cache %0, 0(%1)\n" \ + "2: .set pop\n" \ + " .section __ex_table,\"a\"\n"\ + STR(PTR)" 1b, 2b\n" \ + " .previous\n" \ + : : "i" (op), "r" (base)); \ + } while (0) + +static inline void sync_istream(void) +{ + __asm__ __volatile__ ( + " .set push\n" + " .set noreorder\n" + " nop;nop;nop;nop;nop\n" + " nop;nop;nop;nop;nop\n" + " .set pop\n" + ); +} + +static inline void cacheop_hazard(void) +{ + __asm__ __volatile__ ( + " .set push\n" + " .set noreorder\n" + " nop;nop;nop;nop\n" + " nop;nop;nop;nop\n" + " .set pop\n" + ); +} + +static inline void cacheop_sync_istream(void) +{ + cacheop_hazard(); + sync_istream(); +} + +extern unsigned long nlm_common_ebase; +/* + * These routines support Generic Kernel cache flush requirements + */ +void nlm_common_flush_dcache_page(struct page *page) +{ + ClearPageDcacheDirty(page); +} + +static void nlm_common_local_flush_icache_range(unsigned long start, + unsigned long end) +{ + unsigned long addr; + + for (addr = (start & ~((unsigned long)(icache_linesz - 1))); + addr < end; addr += icache_linesz) { + cacheop_extable(Hit_Invalidate_I, addr); + } + cacheop_sync_istream(); +} + +struct flush_icache_range_args { + unsigned long start; + unsigned long end; +}; + +struct flush_icache_range_args_paddr { + phys_t start; + phys_t end; +}; + +static void nlm_common_flush_icache_range_ipi(void *info) +{ + struct flush_icache_range_args *args = info; + + nlm_common_local_flush_icache_range(args->start, args->end); +} + +void nlm_common_flush_icache_range(unsigned long start, unsigned long end) +{ + struct flush_icache_range_args args; + + if ((end - start) > PAGE_SIZE) + pr_info("flushing more than page size of icache addresses" + " starting @ %lx\n", start); + + args.start = start; + args.end = end; + on_each_cpu(nlm_common_flush_icache_range_ipi, &args, 1); +} + +static void nlm_common_flush_cache_sigtramp_ipi(void *info) +{ + unsigned long addr = (unsigned long)info; + + addr = addr & ~(icache_linesz - 1); + cacheop_extable(Hit_Invalidate_I, addr); + cacheop_sync_istream(); +} + +static void nlm_common_flush_cache_sigtramp(unsigned long addr) +{ + on_each_cpu(nlm_common_flush_cache_sigtramp_ipi, (void *)addr, 1); +} + +/* + * These routines support MIPS specific cache flush requirements. + * These are called only during bootup or special system calls + */ + +static void nlm_common_local_flush_icache(void) +{ + int i = 0; + unsigned long base = CKSEG0; + + /* Index Invalidate all the lines and the ways */ + for (i = 0; i < icache_lines; i++) { + cacheop(Index_Invalidate_I, base); + base += icache_linesz; + } + + cacheop_sync_istream(); +} + +static void nlm_common_local_flush_dcache(void) +{ + int i = 0; + unsigned long base = CKSEG0; + unsigned int lines; + + lines = current_cpu_data.dcache.ways * current_cpu_data.dcache.sets; + + /* Index Invalidate all the lines and the ways */ + for (i = 0; i < lines; i++) { + cacheop(Index_Writeback_Inv_D, base); + base += current_cpu_data.dcache.linesz; + } + + cacheop_hazard(); +} + +#ifdef CONFIG_KGDB +void nlm_common_flush_l1_icache_ipi(void *info) +{ + nlm_common_local_flush_icache(); +} +#endif + +#ifdef CONFIG_KGDB +void nlm_common_flush_l1_caches_ipi(void *info) +#else +static void nlm_common_flush_l1_caches_ipi(void *info) +#endif +{ + nlm_common_local_flush_dcache(); + nlm_common_local_flush_icache(); +} + +static void nlm_common_flush_l1_caches(void) +{ + pr_err("CACHE FLUSH: flushing L1 caches on all cpus!\n"); + on_each_cpu(nlm_common_flush_l1_caches_ipi, (void *)NULL, 1); +} + +static void nlm_common_noflush(void) {/* do nothing */} + +static __init void probe_l1_cache(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config1 = read_c0_config1(); + int lsize, icache_size, dcache_size; + + lsize = (config1 >> 19) & 7; + if (lsize != 0) + c->icache.linesz = 2 << lsize; + else + c->icache.linesz = lsize; + c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + + icache_size = c->icache.sets * + c->icache.ways * c->icache.linesz; + c->icache.waybit = ffs(icache_size/c->icache.ways) - 1; + + c->dcache.flags = 0; + + lsize = (config1 >> 10) & 7; + if (lsize != 0) + c->dcache.linesz = 2 << lsize; + else + c->dcache.linesz = lsize; + c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.ways = 1 + ((config1 >> 7) & 7); + + dcache_size = c->dcache.sets * + c->dcache.ways * c->dcache.linesz; + c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1; + + if (smp_processor_id() == 0) { + pr_info("Primary instruction cache %dkB, %d-way, linesize" + " %d bytes.\n", icache_size >> 10, c->icache.ways, + c->icache.linesz); + pr_info("Primary data cache %dkB %d-way, linesize %d bytes.\n", + dcache_size >> 10, c->dcache.ways, c->dcache.linesz); + } +} + +static inline void install_cerr_handler(void) +{ + extern char except_vec2_generic; + + memcpy((void *)(nlm_common_ebase + 0x100), &except_vec2_generic, 0x80); +} + +static void update_kseg0_coherency(void) +{ + int attr = read_c0_config() & CONF_CM_CMASK; + + if (attr != 0x3) { + nlm_common_local_flush_dcache(); + nlm_common_local_flush_icache(); + + change_c0_config(CONF_CM_CMASK, 0x3); + sync_istream(); + } + _page_cachable_default = (0x3 << _CACHE_SHIFT); +} + +void nlm_cache_init(void) +{ + extern void build_clear_page(void); + extern void build_copy_page(void); + /* update cpu_data */ + + probe_l1_cache(); + if (smp_processor_id() != 0) { + nlm_common_local_flush_icache(); + update_kseg0_coherency(); + return; + } + + /* These values are assumed to be the same for all cores */ + icache_lines = current_cpu_data.icache.ways * + current_cpu_data.icache.sets; + icache_linesz = current_cpu_data.icache.linesz; + + /* + * When does this function get called? Looks like MIPS has some syscalls + * to flush the caches. + */ + __flush_cache_all = nlm_common_flush_l1_caches; + + /* flush_cache_all: makes all kernel data coherent. + * This gets called just before changing or removing + * a mapping in the page-table-mapped kernel segment (kmap). + * Physical Cache -> do nothing + */ + flush_cache_all = nlm_common_noflush; + + /* flush_icache_range: makes the range of addresses coherent w.r.t + * I-cache and D-cache. This gets called after the instructions are + * written to memory. All addresses are valid kernel or mapped + * user-space virtual addresses + */ + flush_icache_range = nlm_common_flush_icache_range; + + /* flush_cache_{mm, range, page}: make these memory locations, that + * may have been written by a user process, coherent. These get called + * when virtual->physical translation of a user address space is about + * to be changed. These are closely related to TLB coherency + * (flush_tlb_{mm, range, page}) + */ + flush_cache_mm = (void (*)(struct mm_struct *))nlm_common_noflush; + flush_cache_range = (void *) nlm_common_noflush; + flush_cache_page = (void *) nlm_common_noflush; + + /* + * flush_icache_page: flush_dcache_page + update_mmu_cache takes care + * of this + */ + flush_data_cache_page = (void *) nlm_common_noflush; + + /* + * flush_cache_sigtramp: flush the single I-cache line with the proper + * fixup code + */ + flush_cache_sigtramp = nlm_common_flush_cache_sigtramp; + + /* + * flush_icache_all: This should get called only for Virtuall Tagged + * I-Caches + */ + flush_icache_all = (void *)nlm_common_noflush; + + local_flush_icache_range = nlm_common_local_flush_icache_range; + local_flush_data_cache_page = (void *)nlm_common_noflush; + + __flush_cache_vmap = (void *)nlm_common_noflush; + __flush_cache_vunmap = (void *)nlm_common_noflush; + + install_cerr_handler(); + + build_clear_page(); + build_copy_page(); + + nlm_common_local_flush_icache(); + + update_kseg0_coherency(); +} + +#ifdef CONFIG_64BIT +#define cacheop_paddr(op, base) \ + __asm__ __volatile__ ( \ + " .set push\n" \ + " .set mips64\n" \ + " cache %0, 0($8)\n" \ + " .set pop\n" \ + : : "i"(op), "r"((base) | 0x9800000000000000ULL)) + +#else +#define cacheop_paddr(op, base) \ + do { \ + uint32_t msb, lsb; \ + \ + msb = 0; \ + if (sizeof(base) == 8) \ + msb = ((base) >> 32); \ + msb |= 0x98000000U; \ + lsb = ((base) & 0xffffffff); \ + \ + __asm__ volatile( \ + " .set push\n" \ + " .set noreorder\n" \ + " .set mips64\n" \ + " dsll32 $8, %1, 0\n" \ + " dsll32 $9, %2, 0\n" \ + " dsrl32 $9, $9, 0\n" \ + " or $8, $8, $9\n" \ + " cache %0, 0($8)\n" \ + " .set pop\n" \ + : : "i"(op), "r"(msb), "r"(lsb) \ + : "$8", "$9"); \ + } while (0) +#endif + +#define c0_enable_kx(flags) \ + do { \ + preempt_disable(); \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set noreorder\n" \ + " mfc0 %0, $12\n" \ + " ori $8, %0, 0x81\n" \ + " xori $8, 1\n" \ + " mtc0 $8, $12\n" \ + " .set pop\n" \ + : "=r"(flags) \ + : : "$8"); \ + preempt_enable(); \ + } while (0) + +#define c0_restore_kx(flags) \ + __asm__ __volatile__ ( \ + " mtc0 %0, $12\n" \ + : : "r"(flags) \ + ) + +#define SETS_PER_WAY_SHIFT 22 +#define SETS_PER_WAY_MASK 0x7 +#define CACHELINE_SIZE_BITS 5 + +static void nlm_common_local_flush_icache_range_paddr(phys_t start, phys_t end) +{ + phys_t addr; +#ifdef CONFIG_32BIT + unsigned long flags; +#endif + +#ifdef CONFIG_32BIT + c0_enable_kx(flags); +#endif + for (addr = (start & ~(phys_t)(icache_linesz - 1)); addr < end; + addr += icache_linesz) { + cacheop_paddr(Hit_Invalidate_I, addr); + } + +#ifdef CONFIG_32BIT + c0_restore_kx(flags); +#endif + cacheop_sync_istream(); +} + +static void nlm_common_flush_icache_range_paddr_ipi(void *info) +{ + struct flush_icache_range_args_paddr *args = info; + + nlm_common_local_flush_icache_range_paddr(args->start, args->end); +} + +void nlm_common_flush_icache_range_paddr(phys_t start) +{ + struct flush_icache_range_args_paddr args; + + args.start = start; + args.end = start + PAGE_SIZE; + on_each_cpu(nlm_common_flush_icache_range_paddr_ipi, &args, 1); +} diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 12af739..b8186ae 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -209,6 +209,11 @@ void __cpuinit cpu_cache_init(void) octeon_cache_init(); } + if (cpu_has_netlogic_cache) { + extern void __weak nlm_cache_init(void); + + nlm_cache_init(); + } setup_protection_map(); } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 04f9e17..c9f9e27 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: + case CPU_XLR: uasm_i_nop(p); tlbw(p); break; diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig new file mode 100644 index 0000000..8ab46ee --- /dev/null +++ b/arch/mips/netlogic/Kconfig @@ -0,0 +1,6 @@ +config NLM_COMMON + bool + +config NLM_XLR + bool + diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile new file mode 100644 index 0000000..9bd3f73 --- /dev/null +++ b/arch/mips/netlogic/xlr/Makefile @@ -0,0 +1,5 @@ +obj-y += setup.o platform.o irq.o setup.o time.o +obj-$(CONFIG_SMP) += smp.o smpboot.o +obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c new file mode 100644 index 0000000..6d2b4ff --- /dev/null +++ b/arch/mips/netlogic/xlr/irq.c @@ -0,0 +1,281 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +static u64 nlm_irq_mask; +static DEFINE_SPINLOCK(nlm_pic_lock); + +static void pic_unmask(unsigned int irq) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + unsigned long flags; + nlm_reg_t reg; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + reg | (1 << 6) | (1 << 30) | (1 << 31)); + spin_unlock_irqrestore(&nlm_pic_lock, flags); + + return; +} + +static void pic_ack(unsigned int irq) +{ + unsigned long flags; + nlm_reg_t *mmio; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static void pic_end(unsigned int irq) +{ + unsigned long flags; + nlm_reg_t *mmio; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + if (PIC_IRQ_IS_EDGE_TRIGGERED(irq)) + return; + + /* If level triggered, ack it after the device condition is cleared */ + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static void pic_shutdown(unsigned int irq) +{ + nlm_reg_t *mmio; + unsigned long flags; + nlm_reg_t reg; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + (reg & ~(1 << 31))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static int pic_set_affinity(unsigned int irq, const struct cpumask *mask) +{ + nlm_reg_t *mmio; + unsigned long flags; + + if (!PIC_IRQ_IS_IRT(irq)) + return -1; + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_IRT_0_BASE + irq - PIC_IRQ_BASE, + (uint32_t)(mask->bits[0])); + spin_unlock_irqrestore(&nlm_pic_lock, flags); + + return 0; +} + +static struct irq_chip xlr_pic = { + .name = "XLR-PIC", + .unmask = pic_unmask, + .mask = pic_shutdown, + .ack = pic_ack, + .end = pic_end, + .set_affinity = pic_set_affinity +}; + +static void rsvd_pic_handler_1(unsigned int irq) +{ + WARN_ON(irq >= PIC_IRQ_BASE); + return; +} + +static int rsvd_pic_handler_2(unsigned int irq, const struct cpumask *mask) +{ + if (irq < PIC_IRQ_BASE) + return -1; + + BUG(); + return 0; +} + +struct irq_chip nlm_rsvd_pic = { + .name = "XLR-RSVD-PIC", + .unmask = rsvd_pic_handler_1, + .mask = rsvd_pic_handler_1, + .ack = rsvd_pic_handler_1, + .end = rsvd_pic_handler_1, + .set_affinity = rsvd_pic_handler_2 +}; + +static irqreturn_t nlm_rsvd_irq_handler(int irq, void *dev_id) +{ + if (irq == IRQ_TIMER) + return IRQ_HANDLED; + BUG(); + return IRQ_NONE; +} + +struct irqaction xlr_rsvd_action = { + .handler = nlm_rsvd_irq_handler, + .flags = 0, + .name = "xlr_rsvd_action", + .dev_id = 0, + .next = 0 +}; + +void __init init_xlr_irqs(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + uint32_t thread_mask = 1; + int level, i; + + pr_info("Interrupt thread mask [%x]\n", thread_mask); + for (i = 0; i < PIC_NUM_IRTS; i++) { + level = PIC_IRQ_IS_EDGE_TRIGGERED(i); + + /* Bind all PIC irqs to boot cpu */ + netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask); + + /* + * Use local scheduling and high polarity for all IRTs + * Invalidate all IRTs, by default + */ + netlogic_write_reg(mmio, PIC_IRT_1_BASE + i, + (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i)); + } + + /* Make all IRQs as level triggered by default */ + for (i = 0; i < NR_IRQS; i++) { + set_irq_chip(i, &xlr_pic); + set_irq_handler(i, handle_level_irq); + } + +#ifdef CONFIG_SMP + irq_desc[IRQ_IPI_SMP_FUNCTION].chip = &nlm_rsvd_pic; + irq_desc[IRQ_IPI_SMP_FUNCTION].action = &xlr_rsvd_action; + set_irq_handler(IRQ_IPI_SMP_FUNCTION, nlm_smp_function_ipi_handler); + + irq_desc[IRQ_IPI_SMP_RESCHEDULE].chip = &nlm_rsvd_pic; + irq_desc[IRQ_IPI_SMP_RESCHEDULE].action = &xlr_rsvd_action; + set_irq_handler(IRQ_IPI_SMP_RESCHEDULE, nlm_smp_resched_ipi_handler); + + nlm_irq_mask |= + ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); +#endif + +#ifdef notyet /* message ring driver not enabled yet */ + /* msgring interrupt */ + irq_desc[IRQ_MSGRING].chip = &nlm_rsvd_pic; + irq_desc[IRQ_MSGRING].action = &xlr_rsvd_action; + nlm_irq_mask |= (1ULL << IRQ_MSGRING); + set_irq_handler(IRQ_MSGRING, nlm_msgring_int_handler); +#endif + + /* unmask all PIC related interrupts. If no handler is installed by the + * drivers, it'll just ack the interrupt and return + */ + for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) + nlm_irq_mask |= (1ULL << i); + + nlm_irq_mask |= (1ULL << IRQ_TIMER); +} + +void __init arch_init_irq(void) +{ + /* Initialize the irq descriptors */ + init_xlr_irqs(); + write_c0_eimr(nlm_irq_mask); +} + +void __cpuinit nlm_smp_irq_init(void) +{ + /* set interrupt mask for non-zero cpus */ + write_c0_eimr(nlm_irq_mask); +} + +asmlinkage void plat_irq_dispatch(void) +{ + uint64_t eirr; + int i; + + eirr = read_c0_eirr() & read_c0_eimr(); + if (!eirr) + return; + + /* no need of EIRR here, writing compare clears interrupt */ + if (eirr & (1 << IRQ_TIMER)) { + do_IRQ(IRQ_TIMER); + return; + } + + /* TODO use dcltz: optimize below code */ + for (i = 63; i != -1; i--) { + if (eirr & (1ULL << i)) + break; + } + if (i == -1) { + pr_err("no interrupt !!\n"); + return; + } + + /* Ack eirr */ + write_c0_eirr(1ULL << i); + + do_IRQ(i); + return; +} diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c new file mode 100644 index 0000000..09d484d --- /dev/null +++ b/arch/mips/netlogic/xlr/platform.c @@ -0,0 +1,99 @@ +/* + * Copyright 2011, Netlogic Microsystems. + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) +{ + nlm_reg_t *mmio; + unsigned int value; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + value = netlogic_read_reg(mmio, 0); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + return value; +} + +void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) +{ + nlm_reg_t *mmio; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + netlogic_write_reg(mmio, 0, value); +} + +#define PORT(_irq) \ + { \ + .irq = _irq, \ + .regshift = 2, \ + .iotype = UPIO_MEM32, \ + .flags = (UPF_SKIP_TEST | \ + UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\ + .uartclk = PIC_CLKS_PER_SEC, \ + .type = PORT_16550A, \ + .serial_in = nlm_xlr_uart_in, \ + .serial_out = nlm_xlr_uart_out, \ + } + +static struct plat_serial8250_port xlr_uart_data[] = { + PORT(PIC_UART_0_IRQ), + PORT(PIC_UART_1_IRQ), + {}, +}; + +static struct platform_device uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = xlr_uart_data, + }, +}; + +static int __init nlm_uart_init(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + xlr_uart_data[0].iobase = (unsigned long)mmio; + xlr_uart_data[0].membase = (void __iomem *)mmio; + xlr_uart_data[0].mapbase = (unsigned long)mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); + xlr_uart_data[1].iobase = (unsigned long)mmio; + xlr_uart_data[1].membase = (void __iomem *)mmio; + xlr_uart_data[1].mapbase = (unsigned long)mmio; + + return platform_device_register(&uart_device); +} + +arch_initcall(nlm_uart_init); diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c new file mode 100644 index 0000000..db42568 --- /dev/null +++ b/arch/mips/netlogic/xlr/setup.c @@ -0,0 +1,181 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); +unsigned long nlm_common_ebase = 0x0; +struct psb_info nlm_prom_info; + +static void nlm_early_serial_setup(void) +{ + struct uart_port s; + nlm_reg_t *uart_base; + + uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + memset(&s, 0, sizeof(s)); + s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + s.iotype = UPIO_MEM32; + s.regshift = 2; + s.irq = PIC_UART_0_IRQ; + s.uartclk = PIC_CLKS_PER_SEC; + s.serial_in = nlm_xlr_uart_in; + s.serial_out = nlm_xlr_uart_out; + s.mapbase = (unsigned long)uart_base; + s.membase = (unsigned char __iomem *)uart_base; + early_serial_setup(&s); +} + +static void nlm_linux_exit(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); + /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ + netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); + for ( ; ; ) + cpu_wait(); +} + +void __init plat_mem_setup(void) +{ + panic_timeout = 5; + _machine_restart = (void (*)(char *))nlm_linux_exit; + _machine_halt = nlm_linux_exit; + pm_power_off = nlm_linux_exit; +} + +const char *get_system_type(void) +{ + return "Netlogic XLR/XLS Series"; +} + +void __init prom_free_prom_memory(void) +{ + /* Nothing yet */ +} + +static void build_arcs_cmdline(char **argv) +{ + int i, remain, len; + char *arg; + + remain = sizeof(arcs_cmdline) - 1; + arcs_cmdline[0] = '\0'; + for (i = 0; argv[i] != NULL; i++) { + arg = argv[i]; + len = strlen(arg); + if (len + 1 > remain) + break; + strcat(arcs_cmdline, arg); + strcat(arcs_cmdline, " "); + remain -= len + 1; + } + + /* Add the default options here */ + if ((strstr(arcs_cmdline, "console=")) == NULL) { + arg = "console=ttyS0,38400 "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#ifdef CONFIG_BLK_DEV_INITRD + if ((strstr(arcs_cmdline, "rdinit=")) == NULL) { + arg = "rdinit=/sbin/init "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#endif + return; +fail: + panic("Cannot add %s, command line too big!", arg); +} + +static void prom_add_memory(void) +{ + struct nlm_boot_mem_map *bootm; + u64 start, size; + u64 pref_backup = 512; /* avoid pref walking beyond end */ + int i; + + bootm = (void *)(unsigned long)nlm_prom_info.psb_mem_map; + for (i = 0; i < bootm->nr_map; i++) { + if (bootm->map[i].type != BOOT_MEM_RAM) + continue; + start = bootm->map[i].addr; + size = bootm->map[i].size; + + /* Work around for using bootloader mem */ + if (i == 0 && start == 0 && size == 0x0c000000) + size = 0x0ff00000; + + add_memory_region(start, size - pref_backup, BOOT_MEM_RAM); + } +} + +void __init prom_init(void) +{ + char **argv, **envp; + struct psb_info *prom_infop; + + argv = (char **)(int)fw_arg1; + envp = (char **)(int)fw_arg2; + prom_infop = (struct psb_info *)(int)fw_arg3; + + nlm_prom_info = *prom_infop; + + nlm_early_serial_setup(); + build_arcs_cmdline(argv); + nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); + prom_add_memory(); + +#ifdef CONFIG_SMP + nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map); + register_smp_ops(&nlm_smp_ops); +#endif +} diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c new file mode 100644 index 0000000..0c3b6d0 --- /dev/null +++ b/arch/mips/netlogic/xlr/smp.c @@ -0,0 +1,219 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +void core_send_ipi(int logical_cpu, unsigned int action) +{ + int cpu = cpu_logical_map(logical_cpu); + u32 tid = cpu & 0x3; + u32 pid = (cpu >> 2) & 0x07; + u32 ipi = (tid << 16) | (pid << 20); + + if (action & SMP_CALL_FUNCTION) + ipi |= IRQ_IPI_SMP_FUNCTION; + else if (action & SMP_RESCHEDULE_YOURSELF) + ipi |= IRQ_IPI_SMP_RESCHEDULE; + else + return; + + pic_send_ipi(ipi); +} + +void nlm_send_ipi_single(int cpu, unsigned int action) +{ + core_send_ipi(cpu, action); +} + +void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + int cpu; + + for_each_cpu(cpu, mask) { + core_send_ipi(cpu, action); + } +} + +/* IRQ_IPI_SMP_FUNCTION Handler */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + smp_call_function_interrupt(); +} + +/* IRQ_IPI_SMP_RESCHEDULE handler */ +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + set_need_resched(); +} + +void nlm_common_ipi_handler(int irq, struct pt_regs *regs) +{ + if (irq == IRQ_IPI_SMP_FUNCTION) { + smp_call_function_interrupt(); + } else { + /* Announce that we are for reschduling */ + set_need_resched(); + } +} + +/* + * Called before going into mips code, early cpu init + */ +void nlm_early_init_secondary(void) +{ + write_c0_ebase((uint32_t)nlm_common_ebase); + /* TLB partition here later */ +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit nlm_init_secondary(void) +{ + nlm_smp_irq_init(); +} + +void nlm_smp_finish(void) +{ +#ifdef notyet + nlm_common_msgring_cpu_init(); +#endif +} + +void nlm_cpus_done(void) +{ +} + +/* + * Boot all other cpus in the system, initialize them, and bring them into + * the boot function + */ +int nlm_cpu_unblock[NR_CPUS]; +int nlm_cpu_ready[NR_CPUS]; +unsigned long nlm_next_gp; +unsigned long nlm_next_sp; +cpumask_t phys_cpu_present_map; + +void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long)task_thread_info(idle); + unsigned long sp = (unsigned long)__KSTK_TOS(idle); + int cpu = cpu_logical_map(logical_cpu); + + nlm_next_sp = sp; + nlm_next_gp = gp; + + /* barrier */ + __sync(); + nlm_cpu_unblock[cpu] = 1; +} + +void __init nlm_smp_setup(void) +{ + unsigned int boot_cpu; + int num_cpus, i; + + boot_cpu = hard_smp_processor_id(); + cpus_clear(phys_cpu_present_map); + + cpu_set(boot_cpu, phys_cpu_present_map); + __cpu_number_map[boot_cpu] = 0; + __cpu_logical_map[0] = boot_cpu; + cpu_set(0, cpu_possible_map); + + num_cpus = 1; + for (i = 0; i < NR_CPUS; i++) { + if (nlm_cpu_ready[i]) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = num_cpus; + __cpu_logical_map[num_cpus] = i; + cpu_set(num_cpus, cpu_possible_map); + ++num_cpus; + } + } + + pr_info("Phys CPU present map: %lx, possible map %lx\n", + (unsigned long)phys_cpu_present_map.bits[0], + (unsigned long)cpu_possible_map.bits[0]); + + pr_info("Detected %i Slave CPU(s)\n", num_cpus); +} + +void nlm_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops nlm_smp_ops = { + .send_ipi_single = nlm_send_ipi_single, + .send_ipi_mask = nlm_send_ipi_mask, + .init_secondary = nlm_init_secondary, + .smp_finish = nlm_smp_finish, + .cpus_done = nlm_cpus_done, + .boot_secondary = nlm_boot_secondary, + .smp_setup = nlm_smp_setup, + .prepare_cpus = nlm_prepare_cpus, +}; + +unsigned long secondary_entry_point; + +int nlm_wakeup_secondary_cpus(u32 wakeup_mask) +{ + unsigned int tid, pid, ipi, i, boot_cpu; + void *reset_vec; + + secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus; + reset_vec = (void *)CKSEG1ADDR(0x1fc00000); + memcpy(reset_vec, nlm_boot_smp_nmi, 0x80); + boot_cpu = hard_smp_processor_id(); + + for (i = 0; i < NR_CPUS; i++) { + if (i == boot_cpu) + continue; + if (wakeup_mask & (1u << i)) { + tid = i & 0x3; + pid = (i >> 2) & 0x7; + ipi = (tid << 16) | (pid << 20) | (1 << 8); + pic_send_ipi(ipi); + } + } + + return 0; +} diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S new file mode 100644 index 0000000..0ccbc75 --- /dev/null +++ b/arch/mips/netlogic/xlr/smpboot.S @@ -0,0 +1,88 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/* Don't jump to linux function from Bootloader stack. Change it + * here. Kernel might allocate bootloader memory before all the CPUs are + * brought up (eg: Inode cache region) and we better don't overwrite this + * memory + */ +NESTED(prom_pre_boot_secondary_cpus, 16, sp) + .set mips64 + mfc0 t0, $15, 1 # read ebase + andi t0, 0x1f # t0 has the processor_id() + sll t0, 2 # offset in cpu array + + PTR_LA t1, nlm_cpu_ready # mark CPU ready + PTR_ADDU t1, t0 + li t2, 1 + sw t2, 0(t1) + + PTR_LA t1, nlm_cpu_unblock + PTR_ADDU t1, t0 +1: lw t2, 0(t1) # wait till unblocked + beqz t2, 1b + nop + + PTR_LA t1, nlm_next_sp + PTR_L sp, 0(t1) + PTR_LA t1, nlm_next_gp + PTR_L gp, 0(t1) + + PTR_LA t0, nlm_early_init_secondary + jalr t0 + nop + + PTR_LA t0, smp_bootstrap + jr t0 + nop +END(prom_pre_boot_secondary_cpus) + +NESTED(nlm_boot_smp_nmi, 0, sp) + .set push + .set noat + .set mips64 + .set noreorder + + /* Clear the NMI and BEV bits */ + MFC0 k0, CP0_STATUS + li k1, 0xffb7ffff + and k0, k0, k1 + MTC0 k0, CP0_STATUS + + PTR_LA k1, secondary_entry_point + PTR_L k0, 0(k1) + jr k0 + nop + .set pop +END(nlm_boot_smp_nmi) diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c new file mode 100644 index 0000000..896b398 --- /dev/null +++ b/arch/mips/netlogic/xlr/time.c @@ -0,0 +1,45 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return IRQ_TIMER; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = nlm_prom_info.cpu_frequency; + pr_info("MIPS counter frequency [%ld]\n", + (unsigned long)mips_hpt_frequency); +} diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/xlr_console.c new file mode 100644 index 0000000..cf8e128 --- /dev/null +++ b/arch/mips/netlogic/xlr/xlr_console.c @@ -0,0 +1,40 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +void prom_putchar(char c) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + while (netlogic_read_reg(mmio, 0x5) == 0) + ; + netlogic_write_reg(mmio, 0x0, c); +} --zhXaljGHf11kAtnf-- From wilbur512@gmail.com Mon Mar 14 13:19:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Mar 2011 13:19:31 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:39574 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491013Ab1CNMT2 (ORCPT ); Mon, 14 Mar 2011 13:19:28 +0100 Received: by vws8 with SMTP id 8so2471435vws.36 for ; Mon, 14 Mar 2011 05:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=Ny2wlvJPZ3YRD6KvjbKm0oEl2qHVcOrRSpJRYIOv0Ig=; b=aq0xF0cIJXmd3F/5br9yKaWg6Nc33yp16oDpl0xcX0cqtC3YXDNSfEtnLOmZ5E7f+F MOlgOUCfv91h/G1RtY90p+qRNLxkvqG2Y+UDqJODux4hjp8xua/EwD9PsGQlpspZiy6N gwbYCTHA3tR3zKBFxGXYpNvYIfNrdCegMjgWE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=GyTO1NQ/DjlWVVE0pakZLNB3+sQ4CWfhxTYqRZ9iuPRqRwE4+WXjKEurl7Z/tkH4f2 EEV3WoN2LSEMrw+Qwy9Gx/b/4MV8HJofjzSRAH3/nlh8tOjocqjr1tvw3Et/iS69gXID eiHyPNhUeLnbsvdXzqMYee3O3Lhav+ai65SD0= MIME-Version: 1.0 Received: by 10.52.98.97 with SMTP id eh1mr9797842vdb.148.1300105162751; Mon, 14 Mar 2011 05:19:22 -0700 (PDT) Received: by 10.52.157.36 with HTTP; Mon, 14 Mar 2011 05:19:22 -0700 (PDT) In-Reply-To: <20110312182714.GC2217@jayachandranc.netlogicmicro.com> References: <20110312182714.GC2217@jayachandranc.netlogicmicro.com> Date: Mon, 14 Mar 2011 20:19:22 +0800 Message-ID: Subject: Re: [PATCH] Support for Netlogic XLR/XLS processors From: "wilbur.chan" To: "Jayachandran C." Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29376 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips Will kexec be supported on XLS/XLR/XLP ? From jayachandranc@netlogicmicro.com Mon Mar 14 15:24:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Mar 2011 15:24:36 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4443 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491038Ab1CNOYd (ORCPT ); Mon, 14 Mar 2011 15:24:33 +0100 X-TM-IMSS-Message-ID: <1acc0a5c0000d8bb@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 1acc0a5c0000d8bb ; Mon, 14 Mar 2011 07:24:24 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 14 Mar 2011 07:24:37 -0700 Date: Mon, 14 Mar 2011 19:59:27 +0530 From: "Jayachandran C." To: "wilbur.chan" Cc: Linux MIPS Mailing List Subject: Re: [PATCH] Support for Netlogic XLR/XLS processors Message-ID: <20110314142927.GA18480@jayachandranc.netlogicmicro.com> References: <20110312182714.GC2217@jayachandranc.netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 14 Mar 2011 14:24:38.0248 (UTC) FILETIME=[8CCB2E80:01CBE253] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29377 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips On Mon, Mar 14, 2011 at 08:19:22PM +0800, wilbur.chan wrote: > Will kexec be supported on XLS/XLR/XLP ? The patches I have does not support it. I haven't really looked at what is needed in XLR platform code to support kexec, so I'm not sure what it takes to support it for XLR either. Any pointers? JC. -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From ralf@linux-mips.org Mon Mar 14 15:25:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Mar 2011 15:25:11 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:56504 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491189Ab1CNOZI (ORCPT ); Mon, 14 Mar 2011 15:25:08 +0100 Received: from duck.linux-mips.net (duck.linux-mips.net [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p2EEOvZ3025362; Mon, 14 Mar 2011 15:24:57 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p2EEOuc1025361; Mon, 14 Mar 2011 15:24:56 +0100 Date: Mon, 14 Mar 2011 15:24:56 +0100 From: Ralf Baechle To: br1@einfach.org Cc: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH] Alchemy: fix reset for MTX-1 and XXS1500 Message-ID: <20110314142455.GA24987@linux-mips.org> References: <201102211428.02125.florian@openwrt.org> <02e6152682aed8348b84dac4508bef70.squirrel@webmail.einfach.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <02e6152682aed8348b84dac4508bef70.squirrel@webmail.einfach.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29378 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 21, 2011 at 09:38:27PM +0100, br1@einfach.org wrote: > Acked-by: Bruno Randolf Thanks, applied. Ralf > From prasadjoshi124@gmail.com Mon Mar 14 18:23:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Mar 2011 18:23:42 +0100 (CET) Received: from mail-qy0-f177.google.com ([209.85.216.177]:64737 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491861Ab1CNRXj (ORCPT ); Mon, 14 Mar 2011 18:23:39 +0100 Received: by qyl38 with SMTP id 38so4681804qyl.15 for ; Mon, 14 Mar 2011 10:23:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:date:message-id:subject:from:to :content-type; bh=A0zAokSg4DYc+1kYQa3wBzPCLK/TCbb4yuymDvfxhIo=; b=NUUs+4Hbcx0ICHHkRCP6PStAMGT8/lIIF7nF8+nlz5OPVqrV0u2cXlGR5oGYBxyk86 Mn1mPjf+EEPsE0VAk7fuEWvZmxODd0NJZ8qzb/Qu4EiJDr5m6JeDZO3LKWLJK5yDXH9+ GTUWMe10WKSbxJLk3obMS3/Bhdp1Q+e6kTJz0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=PmfAgB4iz8tFRz2UuJ3dxuQ20UoYPiatbthi5jXr9Is3SoWSs3AaD4ATgekKCP3OkQ pSlPA5tkg1GJCIuUcW8BfqCQsGMgMk4O1wSRa7TZar/3TtZHq1iBkWuBVcM4u1nfPflI 9J8d2vNmJKx7pCyTGLN7auMJ7dqZ3xNBnJlgM= MIME-Version: 1.0 Received: by 10.229.135.14 with SMTP id l14mr10303678qct.93.1300123409249; Mon, 14 Mar 2011 10:23:29 -0700 (PDT) Received: by 10.229.99.68 with HTTP; Mon, 14 Mar 2011 10:23:29 -0700 (PDT) Date: Mon, 14 Mar 2011 17:23:29 +0000 Message-ID: Subject: [RFC][PATCH v2 00/23] __vmalloc: Propagating GFP allocation flag inside __vmalloc(). From: Prasad Joshi To: Richard Henderson , Ivan Kokshaysky , Matt Turner , linux-alpha@vger.kernel.org, Russell King , linux-arm-kernel@lists.infradead.org, Hans-Christian Egtvedt , Mikael Starvik , Jesper Nilsson , linux-cris-kernel@axis.com, David Howells , Tony Luck , Fenghua Yu , linux-ia64@vger.kernel.org, Hirokazu Takata , linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, Geert Uytterhoeven , Roman Zippel , linux-m68k@lists.linux-m68k.org, Sam Creasey , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Ralf Baechle , linux-mips@linux-mips.org, Koichi Yasutake , linux-am33-list@redhat.com, Kyle McMartin , Helge Deller , "James E.J. Bottomley" , linux-parisc@vger.kernel.org, Paul Mackerras , linuxppc-dev@lists.ozlabs.org, Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Chen Liqin , Lennox Wu , Paul Mundt , linux-sh@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf , Ingo Molnar , "H. Peter Anvin" , Thomas Gleixner , x86@kernel.org, Chris Zankel , Prasad Joshi , Anand Mitra , Andrew Morton , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29379 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: prasadjoshi124@gmail.com Precedence: bulk X-list: linux-mips A filesystem might run into a problem while calling __vmalloc(GFP_NOFS) inside a lock. It is expected than __vmalloc when called with GFP_NOFS should not callback the filesystem code even incase of the increased memory pressure. But the problem is that even if we pass this flag, __vmalloc itself allocates memory with GFP_KERNEL. Using GFP_KERNEL allocations may go into the memory reclaim path and try to free memory by calling file system evict_inode function. Which might lead into deadlock. For further details http://marc.info/?l=linux-mm&m=128942194520631&w=4 https://bugzilla.kernel.org/show_bug.cgi?id=30702 The patch passes the gfp allocation flag all the way down to those allocating functions. arch/alpha/include/asm/pgalloc.h | 18 +++++++-- arch/arm/include/asm/pgalloc.h | 11 +++++- arch/avr32/include/asm/pgalloc.h | 8 ++++- arch/cris/include/asm/pgalloc.h | 10 ++++- arch/frv/include/asm/pgalloc.h | 3 ++ arch/frv/include/asm/pgtable.h | 1 + arch/frv/mm/pgalloc.c | 9 ++++- arch/ia64/include/asm/pgalloc.h | 24 +++++++++++-- arch/m32r/include/asm/pgalloc.h | 11 ++++-- arch/m68k/include/asm/motorola_pgalloc.h | 20 +++++++++-- arch/m68k/include/asm/sun3_pgalloc.h | 14 ++++++-- arch/m68k/mm/memory.c | 9 ++++- arch/microblaze/include/asm/pgalloc.h | 3 ++ arch/microblaze/mm/pgtable.c | 13 +++++-- arch/mips/include/asm/pgalloc.h | 22 ++++++++---- arch/mn10300/include/asm/pgalloc.h | 2 + arch/mn10300/mm/pgtable.c | 10 ++++- arch/parisc/include/asm/pgalloc.h | 21 ++++++++--- arch/powerpc/include/asm/pgalloc-32.h | 2 + arch/powerpc/include/asm/pgalloc-64.h | 27 +++++++++++--- arch/powerpc/mm/pgtable_32.c | 10 ++++- arch/s390/include/asm/pgalloc.h | 30 +++++++++++++--- arch/s390/mm/pgtable.c | 22 +++++++++--- arch/score/include/asm/pgalloc.h | 13 ++++--- arch/sh/include/asm/pgalloc.h | 8 ++++- arch/sh/mm/pgtable.c | 8 ++++- arch/sparc/include/asm/pgalloc_32.h | 5 +++ arch/sparc/include/asm/pgalloc_64.h | 17 ++++++++- arch/tile/include/asm/pgalloc.h | 13 ++++++- arch/tile/mm/pgtable.c | 10 ++++- arch/um/include/asm/pgalloc.h | 1 + arch/um/kernel/mem.c | 21 ++++++++--- arch/x86/include/asm/pgalloc.h | 17 ++++++++- arch/x86/mm/pgtable.c | 8 ++++- arch/xtensa/include/asm/pgalloc.h | 9 ++++- arch/xtensa/mm/pgtable.c | 11 +++++- include/asm-generic/4level-fixup.h | 8 +++- include/asm-generic/pgtable-nopmd.h | 3 +- include/asm-generic/pgtable-nopud.h | 1 + include/linux/mm.h | 40 ++++++++++++++++----- mm/memory.c | 14 ++++--- mm/vmalloc.c | 57 ++++++++++++++++++++---------- 42 files changed, 441 insertions(+), 123 deletions(-) From prasadjoshi124@gmail.com Mon Mar 14 18:46:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Mar 2011 18:46:31 +0100 (CET) Received: from mail-qy0-f177.google.com ([209.85.216.177]:43154 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491869Ab1CNRq1 (ORCPT ); Mon, 14 Mar 2011 18:46:27 +0100 Received: by qyl38 with SMTP id 38so4703025qyl.15 for ; Mon, 14 Mar 2011 10:46:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:date:message-id:subject:from:to :content-type; bh=SHXpsHO9iRdOOn0Fd+FGP/x21MYrZD3UGbO8b0hSVJs=; b=VBD7c8YwYqSeJ5ruTWy5Whr/RCvzD7n4Ur3no1PyK8x+URm2l1qEHzNx+zuORpkpPg I2nkGUUAlNPaZw+ZinuWDoFLVC5b1AvFkZVyZZEgtJYZPHS7L3eyDJ1F2nwGUlEqoc5f L8g9wtX1J3z0rwXlsfyXZipcw3dvwkm3Iai0Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=ko9LwlM2OKT6tcm6jHA/64ungQxBcf0snftR6zC7N/K1iEFpyXH22MRXsRK7JBw6+j MR7nnpCjnE9aq9A9lzqGAgine7TPLeFxnp6KFZp8wJZj8ksBPY7WfEM/twu6GI/5z9Iz MjZl7tMesoX4DqxB70jLbp54W1HuasOAYa6Y8= MIME-Version: 1.0 Received: by 10.229.76.4 with SMTP id a4mr5927509qck.55.1300124781397; Mon, 14 Mar 2011 10:46:21 -0700 (PDT) Received: by 10.229.99.68 with HTTP; Mon, 14 Mar 2011 10:46:21 -0700 (PDT) Date: Mon, 14 Mar 2011 17:46:21 +0000 Message-ID: Subject: [RFC][PATCH v2 10/23] (mips) __vmalloc: add gfp flags variant of pte and pmd allocation From: Prasad Joshi To: Prasad Joshi , Anand Mitra , Andrew Morton , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29380 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: prasadjoshi124@gmail.com Precedence: bulk X-list: linux-mips __vmalloc: propagating GFP allocation flag. - adds functions to allow caller to pass the GFP flag for memory allocation - helps in fixing the Bug 30702 (__vmalloc(GFP_NOFS) can callback file system evict_inode). Signed-off-by: Anand Mitra Signed-off-by: Prasad Joshi --- Chnagelog: arch/mips/include/asm/pgalloc.h | 22 +++++++++++++++------- 1 files changed, 15 insertions(+), 7 deletions(-) --- diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h index 881d18b..f2c5439 100644 --- a/arch/mips/include/asm/pgalloc.h +++ b/arch/mips/include/asm/pgalloc.h @@ -64,14 +64,16 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) free_pages((unsigned long)pgd, PGD_ORDER); } +static inline pte_t *__pte_alloc_one_kernel(struct mm_struct *mm, + unsigned long address, gfp_t gfp_mask) +{ + return (pte_t *) __get_free_pages(gfp_mask | __GFP_ZERO, PTE_ORDER); +} + static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) { - pte_t *pte; - - pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, PTE_ORDER); - - return pte; + return __pte_alloc_one_kernel(mm, address, GFP_KERNEL | __GFP_REPEAT); } static inline struct page *pte_alloc_one(struct mm_struct *mm, @@ -106,16 +108,22 @@ do { \ #ifndef __PAGETABLE_PMD_FOLDED -static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) +static inline pmd_t * +__pmd_alloc_one(struct mm_struct *mm, unsigned long address, gfp_t gfp_mask) { pmd_t *pmd; - pmd = (pmd_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, PMD_ORDER); + pmd = (pmd_t *) __get_free_pages(gfp_mask, PMD_ORDER); if (pmd) pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table); return pmd; } +static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) +{ + return __pmd_alloc_one(mm, address, GFP_KERNEL | __GFP_REPEAT); +} + static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd) { free_pages((unsigned long)pmd, PMD_ORDER); From prasadjoshi124@gmail.com Mon Mar 14 19:38:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Mar 2011 19:38:35 +0100 (CET) Received: from mail-qy0-f177.google.com ([209.85.216.177]:35555 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491895Ab1CNSib (ORCPT ); Mon, 14 Mar 2011 19:38:31 +0100 Received: by qyl38 with SMTP id 38so4749025qyl.15 for ; Mon, 14 Mar 2011 11:38:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:date:message-id:subject:from:to :content-type; bh=lkuHJNc66aHsILA7EmaOEyCjkF6Y9syZkXZuSwkRmVo=; b=bVeGSM8A0HjMgX5SLj0XTLmnLVifE2jGLOa37ONz2WdfRqt5aZGB70TgpWQrxUo13k G73WfwChSWvTJ0omSwQnCCniXe8ap+lE7GTZIoTWcukock/RyGpv5QPesmIWB8+0S9ZF CAc7uLdpfm1Eq0pdZY1wgQgRnR/W9mL8yxmmY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=P6cVzqDWSkj+acwVoQg/YYqEOGl0m6BFomtU8U/u5a+UXJyOMBL9567HRzoE5I3xef wuGKXtckUmwCMTaB6Unf2o8tW2m4+egnKJE4soiS1IR6nb+B72inncem6D8+9Cn8C8JZ A5MptqB3EB00GORjd+Fl21qLX1uoMrPbEi/70= MIME-Version: 1.0 Received: by 10.224.30.212 with SMTP id v20mr11548453qac.129.1300127903875; Mon, 14 Mar 2011 11:38:23 -0700 (PDT) Received: by 10.229.99.68 with HTTP; Mon, 14 Mar 2011 11:38:23 -0700 (PDT) Date: Mon, 14 Mar 2011 18:38:23 +0000 Message-ID: Subject: [RFC][PATCH v2 23/23] __vmalloc: add gfp flags variant of pte, pmd, and pud allocation From: Prasad Joshi To: Prasad Joshi , Anand Mitra , Andrew Morton , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r-ja@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29381 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: prasadjoshi124@gmail.com Precedence: bulk X-list: linux-mips __vmalloc: propagating GFP allocation flag. - Added __map_vm_area, __vmap_page_range, __vmap_page_range_noflush to accept the gfp_t allocation flag - Added pud_alloc_with_mask(), similar to pud_alloc(), but also accepts allocation flag - Added pmd_alloc_with_mask - Added pte_alloc_kernel_with_mask - Modified __pte_alloc_kernel to accept allocation flag - Every architecture has to add a function __pte_alloc_one_kernel(struct mm_struct*, unsigned long, gfp_t) - Modified __pmd_alloc to accept the allocation flag - Every architecture has to add a function __pmd_alloc_one(struct mm_struct *, unsigned long, gfp_t) - Changed __pud_alloc to accepts gfp allocation flag - Every architecture that uses pud has to add a function __pud_alloc_one(struct mm_struct *, unsigned long, gfp_t) - fixes the Bug 30702 (__vmalloc(GFP_NOFS) can callback file system evict_inode). Signed-off-by: Anand Mitra Signed-off-by: Prasad Joshi --- Chnagelog: include/linux/mm.h | 40 +++++++++++++++++++++++++++--------- mm/memory.c | 14 +++++++----- mm/vmalloc.c | 57 ++++++++++++++++++++++++++++++++++----------------- 3 files changed, 76 insertions(+), 35 deletions(-) --- diff --git a/include/linux/mm.h b/include/linux/mm.h index f6385fc..5ff89df 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -1156,44 +1156,60 @@ static inline pte_t *get_locked_pte(struct mm_struct *mm, unsigned long addr, #ifdef __PAGETABLE_PUD_FOLDED static inline int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, - unsigned long address) + unsigned long address, gfp_t gfp_mask) { return 0; } #else -int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address); +int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address, + gfp_t gfp_mask); #endif #ifdef __PAGETABLE_PMD_FOLDED static inline int __pmd_alloc(struct mm_struct *mm, pud_t *pud, - unsigned long address) + unsigned long address, gfp_t gfp_mask) { return 0; } #else -int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address); +int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address, + gfp_t gfp_mask); #endif int __pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma, pmd_t *pmd, unsigned long address); -int __pte_alloc_kernel(pmd_t *pmd, unsigned long address); +int __pte_alloc_kernel(pmd_t *pmd, unsigned long address, gfp_t gfp_mask); /* * The following ifdef needed to get the 4level-fixup.h header to work. * Remove it when 4level-fixup.h has been removed. */ #if defined(CONFIG_MMU) && !defined(__ARCH_HAS_4LEVEL_HACK) -static inline pud_t *pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address) +static inline pud_t *pud_alloc_with_mask(struct mm_struct *mm, pgd_t *pgd, + unsigned long address, gfp_t gfp_mask) { - return (unlikely(pgd_none(*pgd)) && __pud_alloc(mm, pgd, address))? + return (unlikely(pgd_none(*pgd)) && __pud_alloc(mm, pgd, address, gfp_mask))? NULL: pud_offset(pgd, address); } -static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address) +static inline pud_t *pud_alloc(struct mm_struct *mm, pgd_t *pgd, + unsigned long address) { - return (unlikely(pud_none(*pud)) && __pmd_alloc(mm, pud, address))? + return pud_alloc_with_mask(mm, pgd, address, GFP_KERNEL); +} + +static inline pmd_t *pmd_alloc_with_mask(struct mm_struct *mm, pud_t *pud, + unsigned long address, gfp_t gfp_mask) +{ + return (unlikely(pud_none(*pud)) && __pmd_alloc(mm, pud, address, gfp_mask))? NULL: pmd_offset(pud, address); } + +static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, + unsigned long address) +{ + return pmd_alloc_with_mask(mm, pud, address, GFP_KERNEL); +} #endif /* CONFIG_MMU && !__ARCH_HAS_4LEVEL_HACK */ #if USE_SPLIT_PTLOCKS @@ -1254,8 +1270,12 @@ static inline void pgtable_page_dtor(struct page *page) pmd, address))? \ NULL: pte_offset_map_lock(mm, pmd, address, ptlp)) +#define pte_alloc_kernel_with_mask(pmd, address, mask) \ + ((unlikely(pmd_none(*(pmd))) && __pte_alloc_kernel(pmd, address, mask))? \ + NULL: pte_offset_kernel(pmd, address)) + #define pte_alloc_kernel(pmd, address) \ - ((unlikely(pmd_none(*(pmd))) && __pte_alloc_kernel(pmd, address))? \ + ((unlikely(pmd_none(*(pmd))) && __pte_alloc_kernel(pmd, address, GFP_KERNEL))? \ NULL: pte_offset_kernel(pmd, address)) extern void free_area_init(unsigned long * zones_size); diff --git a/mm/memory.c b/mm/memory.c index 5823698..dc4964e 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -433,9 +433,9 @@ int __pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma, return 0; } -int __pte_alloc_kernel(pmd_t *pmd, unsigned long address) +int __pte_alloc_kernel(pmd_t *pmd, unsigned long address, gfp_t gfp_mask) { - pte_t *new = pte_alloc_one_kernel(&init_mm, address); + pte_t *new = __pte_alloc_one_kernel(&init_mm, address, gfp_mask); if (!new) return -ENOMEM; @@ -3343,9 +3343,10 @@ int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, * Allocate page upper directory. * We've already handled the fast-path in-line. */ -int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address) +int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address, + gfp_t gfp_mask) { - pud_t *new = pud_alloc_one(mm, address); + pud_t *new = __pud_alloc_one(mm, address, gfp_mask); if (!new) return -ENOMEM; @@ -3366,9 +3367,10 @@ int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address) * Allocate page middle directory. * We've already handled the fast-path in-line. */ -int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address) +int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address, + gfp_t gfp_mask) { - pmd_t *new = pmd_alloc_one(mm, address); + pmd_t *new = __pmd_alloc_one(mm, address, gfp_mask); if (!new) return -ENOMEM; diff --git a/mm/vmalloc.c b/mm/vmalloc.c index f9b1667..3df33fb 100644 --- a/mm/vmalloc.c +++ b/mm/vmalloc.c @@ -87,8 +87,8 @@ static void vunmap_page_range(unsigned long addr, unsigned long end) } while (pgd++, addr = next, addr != end); } -static int vmap_pte_range(pmd_t *pmd, unsigned long addr, - unsigned long end, pgprot_t prot, struct page **pages, int *nr) +static int vmap_pte_range(pmd_t *pmd, unsigned long addr, unsigned long end, + pgprot_t prot, struct page **pages, int *nr, gfp_t gfp_mask) { pte_t *pte; @@ -97,7 +97,7 @@ static int vmap_pte_range(pmd_t *pmd, unsigned long addr, * callers keep track of where we're up to. */ - pte = pte_alloc_kernel(pmd, addr); + pte = pte_alloc_kernel_with_mask(pmd, addr, gfp_mask); if (!pte) return -ENOMEM; do { @@ -114,34 +114,34 @@ static int vmap_pte_range(pmd_t *pmd, unsigned long addr, } static int vmap_pmd_range(pud_t *pud, unsigned long addr, - unsigned long end, pgprot_t prot, struct page **pages, int *nr) + unsigned long end, pgprot_t prot, struct page **pages, int *nr, gfp_t gfp_mask) { pmd_t *pmd; unsigned long next; - pmd = pmd_alloc(&init_mm, pud, addr); + pmd = pmd_alloc_with_mask(&init_mm, pud, addr, gfp_mask); if (!pmd) return -ENOMEM; do { next = pmd_addr_end(addr, end); - if (vmap_pte_range(pmd, addr, next, prot, pages, nr)) + if (vmap_pte_range(pmd, addr, next, prot, pages, nr, gfp_mask)) return -ENOMEM; } while (pmd++, addr = next, addr != end); return 0; } -static int vmap_pud_range(pgd_t *pgd, unsigned long addr, - unsigned long end, pgprot_t prot, struct page **pages, int *nr) +static int vmap_pud_range(pgd_t *pgd, unsigned long addr, unsigned long end, + pgprot_t prot, struct page **pages, int *nr, gfp_t gfp_mask) { pud_t *pud; unsigned long next; - pud = pud_alloc(&init_mm, pgd, addr); + pud = pud_alloc_with_mask(&init_mm, pgd, addr, gfp_mask); if (!pud) return -ENOMEM; do { next = pud_addr_end(addr, end); - if (vmap_pmd_range(pud, addr, next, prot, pages, nr)) + if (vmap_pmd_range(pud, addr, next, prot, pages, nr, gfp_mask)) return -ENOMEM; } while (pud++, addr = next, addr != end); return 0; @@ -153,8 +153,8 @@ static int vmap_pud_range(pgd_t *pgd, unsigned long addr, * * Ie. pte at addr+N*PAGE_SIZE shall point to pfn corresponding to pages[N] */ -static int vmap_page_range_noflush(unsigned long start, unsigned long end, - pgprot_t prot, struct page **pages) +static int __vmap_page_range_noflush(unsigned long start, unsigned long end, + pgprot_t prot, struct page **pages, gfp_t gfp_mask) { pgd_t *pgd; unsigned long next; @@ -166,7 +166,7 @@ static int vmap_page_range_noflush(unsigned long start, unsigned long end, pgd = pgd_offset_k(addr); do { next = pgd_addr_end(addr, end); - err = vmap_pud_range(pgd, addr, next, prot, pages, &nr); + err = vmap_pud_range(pgd, addr, next, prot, pages, &nr, gfp_mask); if (err) return err; } while (pgd++, addr = next, addr != end); @@ -174,16 +174,29 @@ static int vmap_page_range_noflush(unsigned long start, unsigned long end, return nr; } -static int vmap_page_range(unsigned long start, unsigned long end, - pgprot_t prot, struct page **pages) + +static int vmap_page_range_noflush(unsigned long start, unsigned long end, + pgprot_t prot, struct page **pages) +{ + return __vmap_page_range_noflush(start, end, prot, pages, GFP_KERNEL); +} + +static int __vmap_page_range(unsigned long start, unsigned long end, + pgprot_t prot, struct page **pages, gfp_t gfp_mask) { int ret; - ret = vmap_page_range_noflush(start, end, prot, pages); + ret = __vmap_page_range_noflush(start, end, prot, pages, gfp_mask); flush_cache_vmap(start, end); return ret; } +static int vmap_page_range(unsigned long start, unsigned long end, + pgprot_t prot, struct page **pages) +{ + return __vmap_page_range(start, end, prot, pages, GFP_KERNEL); +} + int is_vmalloc_or_module_addr(const void *x) { /* @@ -1194,13 +1207,14 @@ void unmap_kernel_range(unsigned long addr, unsigned long size) flush_tlb_kernel_range(addr, end); } -int map_vm_area(struct vm_struct *area, pgprot_t prot, struct page ***pages) +int __map_vm_area(struct vm_struct *area, pgprot_t prot, + struct page ***pages, gfp_t gfp_mask) { unsigned long addr = (unsigned long)area->addr; unsigned long end = addr + area->size - PAGE_SIZE; int err; - err = vmap_page_range(addr, end, prot, *pages); + err = __vmap_page_range(addr, end, prot, *pages, gfp_mask); if (err > 0) { *pages += err; err = 0; @@ -1208,6 +1222,11 @@ int map_vm_area(struct vm_struct *area, pgprot_t prot, struct page ***pages) return err; } + +int map_vm_area(struct vm_struct *area, pgprot_t prot, struct page ***pages) +{ + return __map_vm_area(area, prot, pages, GFP_KERNEL); +} EXPORT_SYMBOL_GPL(map_vm_area); /*** Old vmalloc interfaces ***/ @@ -1522,7 +1541,7 @@ static void *__vmalloc_area_node(struct vm_struct *area, gfp_t gfp_mask, area->pages[i] = page; } - if (map_vm_area(area, prot, &pages)) + if (__map_vm_area(area, prot, &pages, gfp_mask)) goto fail; return area->addr; From jayachandranc@netlogicmicro.com Wed Mar 16 12:51:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 12:51:10 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:3898 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491057Ab1CPLvD (ORCPT ); Wed, 16 Mar 2011 12:51:03 +0100 X-TM-IMSS-Message-ID: <248c350900013bf3@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 248c350900013bf3 ; Wed, 16 Mar 2011 04:50:55 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 04:51:35 -0700 Date: Wed, 16 Mar 2011 17:26:38 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 0/7] Support for Netlogic XLR/XLS processors. Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 11:51:35.0618 (UTC) FILETIME=[80588A20:01CBE3D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29382 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips [Sending this again, this time split into multiple patches and in git patch mail format.] These set of patches add support for the XLR and XLS multi-core MIPS64 SoCs from Netlogic Microsystems. These changes enable us to boot linux-mips on Netlogic evaluation boards from the netlogic bootloader. Comments on code or licenses welcome. Jayachandran C (7): Netlogic XLR/XLS processor IDs. mach-netlogic include directory and files Add XLR/XLS cache and TLB support Add XLR to asm/module.h Platform files for XLR/XLS processor support Kconfig and Makefile update for Netlogic XLR/XLS Add default configuration for XLR/XLS processors arch/mips/Kconfig | 42 + arch/mips/Makefile | 12 + arch/mips/configs/nlm_xlr_defconfig | 1699 ++++++++++++++++++++ arch/mips/include/asm/cpu-features.h | 3 + arch/mips/include/asm/cpu.h | 27 + .../asm/mach-netlogic/cpu-feature-overrides.h | 9 + arch/mips/include/asm/mach-netlogic/irq.h | 14 + arch/mips/include/asm/mach-netlogic/war.h | 26 + arch/mips/include/asm/module.h | 2 + arch/mips/include/asm/netlogic/interrupt.h | 39 + arch/mips/include/asm/netlogic/mips-extns.h | 69 + arch/mips/include/asm/netlogic/psb-bootinfo.h | 103 ++ arch/mips/include/asm/netlogic/xlr/gpio.h | 67 + arch/mips/include/asm/netlogic/xlr/iomap.h | 125 ++ arch/mips/include/asm/netlogic/xlr/pic.h | 225 +++ arch/mips/include/asm/netlogic/xlr/xlr.h | 20 + arch/mips/kernel/Makefile | 1 + arch/mips/kernel/cpu-probe.c | 55 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/mm/c-netlogic.c | 450 ++++++ arch/mips/mm/cache.c | 5 + arch/mips/mm/tlbex.c | 1 + arch/mips/netlogic/Kconfig | 6 + arch/mips/netlogic/xlr/Makefile | 5 + arch/mips/netlogic/xlr/irq.c | 281 ++++ arch/mips/netlogic/xlr/platform.c | 99 ++ arch/mips/netlogic/xlr/setup.c | 181 +++ arch/mips/netlogic/xlr/smp.c | 219 +++ arch/mips/netlogic/xlr/smpboot.S | 88 + arch/mips/netlogic/xlr/time.c | 45 + arch/mips/netlogic/xlr/xlr_console.c | 40 + 32 files changed, 3960 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/mm/c-netlogic.c create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Wed Mar 16 12:52:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 12:52:05 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4776 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491057Ab1CPLwC (ORCPT ); Wed, 16 Mar 2011 12:52:02 +0100 X-TM-IMSS-Message-ID: <248d20c100013bfe@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 248d20c100013bfe ; Wed, 16 Mar 2011 04:51:55 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 04:52:26 -0700 Date: Wed, 16 Mar 2011 17:27:29 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 2/7] mach-netlogic include directory and files Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 11:52:26.0790 (UTC) FILETIME=[9ED8C460:01CBE3D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29383 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add war.h and irq.h with XLR/XLS definitions. Signed-off-by: Jayachandran C --- arch/mips/include/asm/mach-netlogic/irq.h | 14 ++++++++++++++ arch/mips/include/asm/mach-netlogic/war.h | 26 ++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h new file mode 100644 index 0000000..b590245 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/irq.h @@ -0,0 +1,14 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + */ +#ifndef __ASM_NETLOGIC_IRQ_H +#define __ASM_NETLOGIC_IRQ_H + +#define NR_IRQS 64 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* __ASM_NETLOGIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h new file mode 100644 index 0000000..22da893 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/war.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_NLM_WAR_H +#define __ASM_MIPS_MACH_NLM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_NLM_WAR_H */ -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Wed Mar 16 12:52:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 12:52:30 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4774 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491066Ab1CPLwD (ORCPT ); Wed, 16 Mar 2011 12:52:03 +0100 X-TM-IMSS-Message-ID: <248d205300013bfd@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 248d205300013bfd ; Wed, 16 Mar 2011 04:51:55 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 04:52:05 -0700 Date: Wed, 16 Mar 2011 17:27:08 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 1/7] Netlogic XLR/XLS processor IDs. Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 11:52:05.0899 (UTC) FILETIME=[92650DB0:01CBE3D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29384 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add Netlogic Microsystems company ID and processor IDs for XLR and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. Signed-off-by: Jayachandran C --- arch/mips/include/asm/cpu.h | 27 ++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..34c0d3c 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 @@ -142,6 +143,31 @@ #define PRID_IMP_JZRISC 0x0200 /* + * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC + */ +#define PRID_IMP_NETLOGIC_XLR732 0x0000 +#define PRID_IMP_NETLOGIC_XLR716 0x0200 +#define PRID_IMP_NETLOGIC_XLR532 0x0900 +#define PRID_IMP_NETLOGIC_XLR308 0x0600 +#define PRID_IMP_NETLOGIC_XLR532C 0x0800 +#define PRID_IMP_NETLOGIC_XLR516C 0x0a00 +#define PRID_IMP_NETLOGIC_XLR508C 0x0b00 +#define PRID_IMP_NETLOGIC_XLR308C 0x0f00 +#define PRID_IMP_NETLOGIC_XLS608 0x8000 +#define PRID_IMP_NETLOGIC_XLS408 0x8800 +#define PRID_IMP_NETLOGIC_XLS404 0x8c00 +#define PRID_IMP_NETLOGIC_XLS208 0x8e00 +#define PRID_IMP_NETLOGIC_XLS204 0x8f00 +#define PRID_IMP_NETLOGIC_XLS108 0xce00 +#define PRID_IMP_NETLOGIC_XLS104 0xcf00 +#define PRID_IMP_NETLOGIC_XLS616B 0x4000 +#define PRID_IMP_NETLOGIC_XLS608B 0x4a00 +#define PRID_IMP_NETLOGIC_XLS416B 0x4400 +#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 +#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 +#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 + +/* * Definitions for 7:0 on legacy processors */ @@ -234,6 +260,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, + CPU_XLR, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..a995d56 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + c->options = (MIPS_CPU_TLB | + MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | + MIPS_CPU_WATCH | + MIPS_CPU_EJTAG | + MIPS_CPU_LLSC); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_NETLOGIC_XLR732: + case PRID_IMP_NETLOGIC_XLR716: + case PRID_IMP_NETLOGIC_XLR532: + case PRID_IMP_NETLOGIC_XLR308: + case PRID_IMP_NETLOGIC_XLR532C: + case PRID_IMP_NETLOGIC_XLR516C: + case PRID_IMP_NETLOGIC_XLR508C: + case PRID_IMP_NETLOGIC_XLR308C: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLR"; + break; + + case PRID_IMP_NETLOGIC_XLS608: + case PRID_IMP_NETLOGIC_XLS408: + case PRID_IMP_NETLOGIC_XLS404: + case PRID_IMP_NETLOGIC_XLS208: + case PRID_IMP_NETLOGIC_XLS204: + case PRID_IMP_NETLOGIC_XLS108: + case PRID_IMP_NETLOGIC_XLS104: + case PRID_IMP_NETLOGIC_XLS616B: + case PRID_IMP_NETLOGIC_XLS608B: + case PRID_IMP_NETLOGIC_XLS416B: + case PRID_IMP_NETLOGIC_XLS412B: + case PRID_IMP_NETLOGIC_XLS408B: + case PRID_IMP_NETLOGIC_XLS404B: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLS"; + break; + + default: + printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", + c->processor_id); + c->cputype = CPU_XLR; + break; + } + + c->isa_level = MIPS_CPU_ISA_M64R1; + c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; +} + #ifdef CONFIG_64BIT /* For use by uaccess.h */ u64 __ua_limit; @@ -1034,6 +1087,8 @@ __cpuinit void cpu_probe(void) break; case PRID_COMP_INGENIC: cpu_probe_ingenic(c, cpu); + case PRID_COMP_NETLOGIC: + cpu_probe_netlogic(c, cpu); break; } -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Wed Mar 16 12:52:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 12:52:54 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4775 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491052Ab1CPLwD (ORCPT ); Wed, 16 Mar 2011 12:52:03 +0100 X-TM-IMSS-Message-ID: <248d21ab00013c00@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 248d21ab00013c00 ; Wed, 16 Mar 2011 04:51:55 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 04:52:47 -0700 Date: Wed, 16 Mar 2011 17:27:49 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 3/7] Add XLR/XLS cache and TLB support Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 11:52:48.0228 (UTC) FILETIME=[AB9FF240:01CBE3D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29385 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add c-netlogic.c for XLR/XLS cache operations. New cache type cpu_has_netlogic_cache in asm/cpu-features.h asm/mach-netlogic/cpu-feature-overrides.h for cache CPU_XLR case added to mm/tlbex.c Signed-off-by: Jayachandran C --- arch/mips/include/asm/cpu-features.h | 3 + .../asm/mach-netlogic/cpu-feature-overrides.h | 9 + arch/mips/mm/c-netlogic.c | 450 ++++++++++++++++++++ arch/mips/mm/cache.c | 5 + arch/mips/mm/tlbex.c | 1 + 5 files changed, 468 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/mm/c-netlogic.c diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7..bbf8f35 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -41,6 +41,9 @@ #ifndef cpu_has_octeon_cache #define cpu_has_octeon_cache 0 #endif +#ifndef cpu_has_netlogic_cache +#define cpu_has_netlogic_cache 0 +#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h new file mode 100644 index 0000000..7740401 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H + +/* + * Most of the properties are in cpu->options + */ +#define cpu_has_netlogic_cache 1 + +#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/mm/c-netlogic.c b/arch/mips/mm/c-netlogic.c new file mode 100644 index 0000000..27a0067 --- /dev/null +++ b/arch/mips/mm/c-netlogic.c @@ -0,0 +1,450 @@ +/* + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2011 Netlogic Microsystems. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int icache_linesz; +static unsigned int icache_lines; + +#define cacheop(op, base) \ + __asm__ __volatile__ ( \ + " .set push\n" \ + " .set mips4\n" \ + " cache %0, 0(%1)\n" \ + " .set pop\n" \ + : : "i"(op), "r"(base)) + +#define cacheop_extable(op, base) do { \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set noreorder\n" \ + " .set mips4\n" \ + "1: cache %0, 0(%1)\n" \ + "2: .set pop\n" \ + " .section __ex_table,\"a\"\n"\ + STR(PTR)" 1b, 2b\n" \ + " .previous\n" \ + : : "i" (op), "r" (base)); \ + } while (0) + +static inline void sync_istream(void) +{ + __asm__ __volatile__ ( + " .set push\n" + " .set noreorder\n" + " nop;nop;nop;nop;nop\n" + " nop;nop;nop;nop;nop\n" + " .set pop\n" + ); +} + +static inline void cacheop_hazard(void) +{ + __asm__ __volatile__ ( + " .set push\n" + " .set noreorder\n" + " nop;nop;nop;nop\n" + " nop;nop;nop;nop\n" + " .set pop\n" + ); +} + +static inline void cacheop_sync_istream(void) +{ + cacheop_hazard(); + sync_istream(); +} + +extern unsigned long nlm_common_ebase; +/* + * These routines support Generic Kernel cache flush requirements + */ +void nlm_common_flush_dcache_page(struct page *page) +{ + ClearPageDcacheDirty(page); +} + +static void nlm_common_local_flush_icache_range(unsigned long start, + unsigned long end) +{ + unsigned long addr; + + for (addr = (start & ~((unsigned long)(icache_linesz - 1))); + addr < end; addr += icache_linesz) { + cacheop_extable(Hit_Invalidate_I, addr); + } + cacheop_sync_istream(); +} + +struct flush_icache_range_args { + unsigned long start; + unsigned long end; +}; + +struct flush_icache_range_args_paddr { + phys_t start; + phys_t end; +}; + +static void nlm_common_flush_icache_range_ipi(void *info) +{ + struct flush_icache_range_args *args = info; + + nlm_common_local_flush_icache_range(args->start, args->end); +} + +void nlm_common_flush_icache_range(unsigned long start, unsigned long end) +{ + struct flush_icache_range_args args; + + if ((end - start) > PAGE_SIZE) + pr_info("flushing more than page size of icache addresses" + " starting @ %lx\n", start); + + args.start = start; + args.end = end; + on_each_cpu(nlm_common_flush_icache_range_ipi, &args, 1); +} + +static void nlm_common_flush_cache_sigtramp_ipi(void *info) +{ + unsigned long addr = (unsigned long)info; + + addr = addr & ~(icache_linesz - 1); + cacheop_extable(Hit_Invalidate_I, addr); + cacheop_sync_istream(); +} + +static void nlm_common_flush_cache_sigtramp(unsigned long addr) +{ + on_each_cpu(nlm_common_flush_cache_sigtramp_ipi, (void *)addr, 1); +} + +/* + * These routines support MIPS specific cache flush requirements. + * These are called only during bootup or special system calls + */ + +static void nlm_common_local_flush_icache(void) +{ + int i = 0; + unsigned long base = CKSEG0; + + /* Index Invalidate all the lines and the ways */ + for (i = 0; i < icache_lines; i++) { + cacheop(Index_Invalidate_I, base); + base += icache_linesz; + } + + cacheop_sync_istream(); +} + +static void nlm_common_local_flush_dcache(void) +{ + int i = 0; + unsigned long base = CKSEG0; + unsigned int lines; + + lines = current_cpu_data.dcache.ways * current_cpu_data.dcache.sets; + + /* Index Invalidate all the lines and the ways */ + for (i = 0; i < lines; i++) { + cacheop(Index_Writeback_Inv_D, base); + base += current_cpu_data.dcache.linesz; + } + + cacheop_hazard(); +} + +#ifdef CONFIG_KGDB +void nlm_common_flush_l1_icache_ipi(void *info) +{ + nlm_common_local_flush_icache(); +} +#endif + +#ifdef CONFIG_KGDB +void nlm_common_flush_l1_caches_ipi(void *info) +#else +static void nlm_common_flush_l1_caches_ipi(void *info) +#endif +{ + nlm_common_local_flush_dcache(); + nlm_common_local_flush_icache(); +} + +static void nlm_common_flush_l1_caches(void) +{ + pr_err("CACHE FLUSH: flushing L1 caches on all cpus!\n"); + on_each_cpu(nlm_common_flush_l1_caches_ipi, (void *)NULL, 1); +} + +static void nlm_common_noflush(void) {/* do nothing */} + +static __init void probe_l1_cache(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config1 = read_c0_config1(); + int lsize, icache_size, dcache_size; + + lsize = (config1 >> 19) & 7; + if (lsize != 0) + c->icache.linesz = 2 << lsize; + else + c->icache.linesz = lsize; + c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + + icache_size = c->icache.sets * + c->icache.ways * c->icache.linesz; + c->icache.waybit = ffs(icache_size/c->icache.ways) - 1; + + c->dcache.flags = 0; + + lsize = (config1 >> 10) & 7; + if (lsize != 0) + c->dcache.linesz = 2 << lsize; + else + c->dcache.linesz = lsize; + c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.ways = 1 + ((config1 >> 7) & 7); + + dcache_size = c->dcache.sets * + c->dcache.ways * c->dcache.linesz; + c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1; + + if (smp_processor_id() == 0) { + pr_info("Primary instruction cache %dkB, %d-way, linesize" + " %d bytes.\n", icache_size >> 10, c->icache.ways, + c->icache.linesz); + pr_info("Primary data cache %dkB %d-way, linesize %d bytes.\n", + dcache_size >> 10, c->dcache.ways, c->dcache.linesz); + } +} + +static inline void install_cerr_handler(void) +{ + extern char except_vec2_generic; + + memcpy((void *)(nlm_common_ebase + 0x100), &except_vec2_generic, 0x80); +} + +static void update_kseg0_coherency(void) +{ + int attr = read_c0_config() & CONF_CM_CMASK; + + if (attr != 0x3) { + nlm_common_local_flush_dcache(); + nlm_common_local_flush_icache(); + + change_c0_config(CONF_CM_CMASK, 0x3); + sync_istream(); + } + _page_cachable_default = (0x3 << _CACHE_SHIFT); +} + +void nlm_cache_init(void) +{ + extern void build_clear_page(void); + extern void build_copy_page(void); + /* update cpu_data */ + + probe_l1_cache(); + if (smp_processor_id() != 0) { + nlm_common_local_flush_icache(); + update_kseg0_coherency(); + return; + } + + /* These values are assumed to be the same for all cores */ + icache_lines = current_cpu_data.icache.ways * + current_cpu_data.icache.sets; + icache_linesz = current_cpu_data.icache.linesz; + + /* + * When does this function get called? Looks like MIPS has some syscalls + * to flush the caches. + */ + __flush_cache_all = nlm_common_flush_l1_caches; + + /* flush_cache_all: makes all kernel data coherent. + * This gets called just before changing or removing + * a mapping in the page-table-mapped kernel segment (kmap). + * Physical Cache -> do nothing + */ + flush_cache_all = nlm_common_noflush; + + /* flush_icache_range: makes the range of addresses coherent w.r.t + * I-cache and D-cache. This gets called after the instructions are + * written to memory. All addresses are valid kernel or mapped + * user-space virtual addresses + */ + flush_icache_range = nlm_common_flush_icache_range; + + /* flush_cache_{mm, range, page}: make these memory locations, that + * may have been written by a user process, coherent. These get called + * when virtual->physical translation of a user address space is about + * to be changed. These are closely related to TLB coherency + * (flush_tlb_{mm, range, page}) + */ + flush_cache_mm = (void (*)(struct mm_struct *))nlm_common_noflush; + flush_cache_range = (void *) nlm_common_noflush; + flush_cache_page = (void *) nlm_common_noflush; + + /* + * flush_icache_page: flush_dcache_page + update_mmu_cache takes care + * of this + */ + flush_data_cache_page = (void *) nlm_common_noflush; + + /* + * flush_cache_sigtramp: flush the single I-cache line with the proper + * fixup code + */ + flush_cache_sigtramp = nlm_common_flush_cache_sigtramp; + + /* + * flush_icache_all: This should get called only for Virtuall Tagged + * I-Caches + */ + flush_icache_all = (void *)nlm_common_noflush; + + local_flush_icache_range = nlm_common_local_flush_icache_range; + local_flush_data_cache_page = (void *)nlm_common_noflush; + + __flush_cache_vmap = (void *)nlm_common_noflush; + __flush_cache_vunmap = (void *)nlm_common_noflush; + + install_cerr_handler(); + + build_clear_page(); + build_copy_page(); + + nlm_common_local_flush_icache(); + + update_kseg0_coherency(); +} + +#ifdef CONFIG_64BIT +#define cacheop_paddr(op, base) \ + __asm__ __volatile__ ( \ + " .set push\n" \ + " .set mips64\n" \ + " cache %0, 0($8)\n" \ + " .set pop\n" \ + : : "i"(op), "r"((base) | 0x9800000000000000ULL)) + +#else +#define cacheop_paddr(op, base) \ + do { \ + uint32_t msb, lsb; \ + \ + msb = 0; \ + if (sizeof(base) == 8) \ + msb = ((base) >> 32); \ + msb |= 0x98000000U; \ + lsb = ((base) & 0xffffffff); \ + \ + __asm__ volatile( \ + " .set push\n" \ + " .set noreorder\n" \ + " .set mips64\n" \ + " dsll32 $8, %1, 0\n" \ + " dsll32 $9, %2, 0\n" \ + " dsrl32 $9, $9, 0\n" \ + " or $8, $8, $9\n" \ + " cache %0, 0($8)\n" \ + " .set pop\n" \ + : : "i"(op), "r"(msb), "r"(lsb) \ + : "$8", "$9"); \ + } while (0) +#endif + +#define c0_enable_kx(flags) \ + do { \ + preempt_disable(); \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set noreorder\n" \ + " mfc0 %0, $12\n" \ + " ori $8, %0, 0x81\n" \ + " xori $8, 1\n" \ + " mtc0 $8, $12\n" \ + " .set pop\n" \ + : "=r"(flags) \ + : : "$8"); \ + preempt_enable(); \ + } while (0) + +#define c0_restore_kx(flags) \ + __asm__ __volatile__ ( \ + " mtc0 %0, $12\n" \ + : : "r"(flags) \ + ) + +#define SETS_PER_WAY_SHIFT 22 +#define SETS_PER_WAY_MASK 0x7 +#define CACHELINE_SIZE_BITS 5 + +static void nlm_common_local_flush_icache_range_paddr(phys_t start, phys_t end) +{ + phys_t addr; +#ifdef CONFIG_32BIT + unsigned long flags; +#endif + +#ifdef CONFIG_32BIT + c0_enable_kx(flags); +#endif + for (addr = (start & ~(phys_t)(icache_linesz - 1)); addr < end; + addr += icache_linesz) { + cacheop_paddr(Hit_Invalidate_I, addr); + } + +#ifdef CONFIG_32BIT + c0_restore_kx(flags); +#endif + cacheop_sync_istream(); +} + +static void nlm_common_flush_icache_range_paddr_ipi(void *info) +{ + struct flush_icache_range_args_paddr *args = info; + + nlm_common_local_flush_icache_range_paddr(args->start, args->end); +} + +void nlm_common_flush_icache_range_paddr(phys_t start) +{ + struct flush_icache_range_args_paddr args; + + args.start = start; + args.end = start + PAGE_SIZE; + on_each_cpu(nlm_common_flush_icache_range_paddr_ipi, &args, 1); +} diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 12af739..b8186ae 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -209,6 +209,11 @@ void __cpuinit cpu_cache_init(void) octeon_cache_init(); } + if (cpu_has_netlogic_cache) { + extern void __weak nlm_cache_init(void); + + nlm_cache_init(); + } setup_protection_map(); } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 04f9e17..c9f9e27 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: + case CPU_XLR: uasm_i_nop(p); tlbw(p); break; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Wed Mar 16 12:53:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 12:53:16 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4307 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491057Ab1CPLxD (ORCPT ); Wed, 16 Mar 2011 12:53:03 +0100 X-TM-IMSS-Message-ID: <248e0ce600013c0f@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 248e0ce600013c0f ; Wed, 16 Mar 2011 04:52:55 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 04:53:11 -0700 Date: Wed, 16 Mar 2011 17:28:13 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 4/7] Add XLR to asm/module.h Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 11:53:11.0275 (UTC) FILETIME=[B95CA3B0:01CBE3D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29386 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Signed-off-by: Jayachandran C --- arch/mips/include/asm/module.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index d94085a..bc01a02 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON2 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " +#elif defined CONFIG_CPU_XLR +#define MODULE_PROC_FAMILY "XLR " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Wed Mar 16 12:53:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 12:53:44 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4306 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491063Ab1CPLxE (ORCPT ); Wed, 16 Mar 2011 12:53:04 +0100 X-TM-IMSS-Message-ID: <248e0d5300013c10@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 248e0d5300013c10 ; Wed, 16 Mar 2011 04:52:56 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 04:53:40 -0700 Date: Wed, 16 Mar 2011 17:28:43 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 5/7] Platform files for XLR/XLS processor support Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 11:53:41.0056 (UTC) FILETIME=[CB1CDC00:01CBE3D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29387 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips asm/netlogic added with files common for all Netlogic processors (including XLP which will be added later) asm/netlogic/xlr for XLR/XLS chip specific files netlogic/xlr for XLR/XLS platform files Signed-off-by: Jayachandran C --- arch/mips/include/asm/netlogic/interrupt.h | 39 ++++ arch/mips/include/asm/netlogic/mips-extns.h | 69 ++++++ arch/mips/include/asm/netlogic/psb-bootinfo.h | 103 +++++++++ arch/mips/include/asm/netlogic/xlr/gpio.h | 67 ++++++ arch/mips/include/asm/netlogic/xlr/iomap.h | 125 +++++++++++ arch/mips/include/asm/netlogic/xlr/pic.h | 225 ++++++++++++++++++++ arch/mips/include/asm/netlogic/xlr/xlr.h | 20 ++ arch/mips/netlogic/xlr/irq.c | 281 +++++++++++++++++++++++++ arch/mips/netlogic/xlr/platform.c | 99 +++++++++ arch/mips/netlogic/xlr/setup.c | 181 ++++++++++++++++ arch/mips/netlogic/xlr/smp.c | 219 +++++++++++++++++++ arch/mips/netlogic/xlr/smpboot.S | 88 ++++++++ arch/mips/netlogic/xlr/time.c | 45 ++++ arch/mips/netlogic/xlr/xlr_console.c | 40 ++++ 14 files changed, 1601 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h new file mode 100644 index 0000000..433f7e2 --- /dev/null +++ b/arch/mips/include/asm/netlogic/interrupt.h @@ -0,0 +1,39 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_INTERRUPT_H +#define _ASM_NLM_INTERRUPT_H + +/* Defines for the IRQ numbers */ + +#define IRQ_IPI_SMP_FUNCTION 3 +#define IRQ_IPI_SMP_RESCHEDULE 4 +#define IRQ_MSGRING 6 +#define IRQ_TIMER 7 + +#endif diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h new file mode 100644 index 0000000..d08359a --- /dev/null +++ b/arch/mips/include/asm/netlogic/mips-extns.h @@ -0,0 +1,69 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _ASM_NLM_MIPS_EXTS_H +#define _ASM_NLM_MIPS_EXTS_H + +/* + * XLR and XLP interrupt request and interrupt mask registers + */ +#define read_c0_eirr() __read_64bit_c0_register($9, 6) +#define read_c0_eimr() __read_64bit_c0_register($9, 7) +#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val) + +/* + * Writing EIMR in 32 bit is a special case, the lower 8 bit of the + * EIMR is shadowed in the status register, so we cannot save and + * restore status register for split read. + */ +#define write_c0_eimr(val) \ +do { \ + if (sizeof(unsigned long) == 4) { \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, $9, 7\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\ + local_irq_restore(__flags); \ + } else \ + __write_64bit_c0_register($9, 7, (val)); \ +} while (0) + +static inline int hard_smp_processor_id(void) +{ + return __read_32bit_c0_register($15, 1) & 0x3ff; +} + +#endif /*_ASM_NLM_MIPS_EXTS_H */ diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h new file mode 100644 index 0000000..8283f03 --- /dev/null +++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h @@ -0,0 +1,103 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NETLOGIC_BOOTINFO_H +#define _ASM_NETLOGIC_BOOTINFO_H + +struct psb_info { + uint64_t boot_level; + uint64_t io_base; + uint64_t output_device; + uint64_t uart_print; + uint64_t led_output; + uint64_t init; + uint64_t exit; + uint64_t warm_reset; + uint64_t wakeup; + uint64_t online_cpu_map; + uint64_t master_reentry_sp; + uint64_t master_reentry_gp; + uint64_t master_reentry_fn; + uint64_t slave_reentry_fn; + uint64_t magic_dword; + uint64_t uart_putchar; + uint64_t size; + uint64_t uart_getchar; + uint64_t nmi_handler; + uint64_t psb_version; + uint64_t mac_addr; + uint64_t cpu_frequency; + uint64_t board_version; + uint64_t malloc; + uint64_t free; + uint64_t global_shmem_addr; + uint64_t global_shmem_size; + uint64_t psb_os_cpu_map; + uint64_t userapp_cpu_map; + uint64_t wakeup_os; + uint64_t psb_mem_map; + uint64_t board_major_version; + uint64_t board_minor_version; + uint64_t board_manf_revision; + uint64_t board_serial_number; + uint64_t psb_physaddr_map; + uint64_t xlr_loaderip_config; + uint64_t bldr_envp; + uint64_t avail_mem_map; +}; + +enum { + NETLOGIC_IO_SPACE = 0x10, + PCIX_IO_SPACE, + PCIX_CFG_SPACE, + PCIX_MEMORY_SPACE, + HT_IO_SPACE, + HT_CFG_SPACE, + HT_MEMORY_SPACE, + SRAM_SPACE, + FLASH_CONTROLLER_SPACE +}; + +#define NLM_MAX_ARGS 64 +#define NLM_MAX_ENVS 32 + +/* This is what netlboot passes and linux boot_mem_map is subtly different */ +#define NLM_BOOT_MEM_MAP_MAX 32 +struct nlm_boot_mem_map { + int nr_map; + struct nlm_boot_mem_map_entry { + uint64_t addr; /* start of memory segment */ + uint64_t size; /* size of memory segment */ + uint32_t type; /* type of memory segment */ + } map[NLM_BOOT_MEM_MAP_MAX]; +}; + +/* Pointer to saved boot loader info */ +extern struct psb_info nlm_prom_info; + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h new file mode 100644 index 0000000..2782c97 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/gpio.h @@ -0,0 +1,67 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_GPIO_H +#define _ASM_NLM_GPIO_H + +#define NETLOGIC_GPIO_INT_EN_REG 0 +#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 +#define NETLOGIC_GPIO_IO_DIR_REG 2 +#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 +#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 + +#define NETLOGIC_GPIO_SWRESET_REG 8 +#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 +#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 +#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 +#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 +#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 +#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 +#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 +#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 + +#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 +#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 +#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 +#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 + +#define NETLOGIC_GPIO_FUSE_BANK_REG 35 +#define NETLOGIC_GPIO_CPU_RESET_REG 40 +#define NETLOGIC_GPIO_RNG_REG 43 + +#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 +#define NETLOGIC_GPIO_LED_BITMAP 0x1700000 +#define NETLOGIC_GPIO_LED_0_SHIFT 20 +#define NETLOGIC_GPIO_LED_1_SHIFT 24 + +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 +#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 + +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h new file mode 100644 index 0000000..79d2a16 --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/iomap.h @@ -0,0 +1,125 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_IOMAP_H +#define _ASM_NLM_IOMAP_H + +#define DEFAULT_NETLOGIC_IO_BASE KSEG1ADDR(0x1ef00000) +#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 +#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 +#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 +#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 +#define NETLOGIC_IO_PIC_OFFSET 0x08000 +#define NETLOGIC_IO_UART_0_OFFSET 0x14000 +#define NETLOGIC_IO_UART_1_OFFSET 0x15100 + +#define NETLOGIC_IO_SIZE 0x1000 + +#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 + +#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 +#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 + +#define NETLOGIC_IO_SRAM_OFFSET 0x07000 + +#define NETLOGIC_IO_PCIX_OFFSET 0x09000 +#define NETLOGIC_IO_HT_OFFSET 0x0A000 + +#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 + +#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 +#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 +#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 +#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 + +/* XLS devices */ +#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 +#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 +#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 +#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 + +#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 +#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 +#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 +#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 + +#define NETLOGIC_IO_USB_0_OFFSET 0x24000 +#define NETLOGIC_IO_USB_1_OFFSET 0x25000 + +#define NETLOGIC_IO_COMP_OFFSET 0x1D000 +/* end XLS devices */ + +/* XLR devices */ +#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 +#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 +#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 +#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 +/* end XLR devices */ + +#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 +#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 + +#define NETLOGIC_IO_GPIO_OFFSET 0x18000 +#define NETLOGIC_IO_FLASH_OFFSET 0x19000 +#define NETLOGIC_IO_TB_OFFSET 0x1C000 + +#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) + +/* + * Base Address (Virtual) of the PCI Config address space + * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28) + * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes + * ie 1<<24 = 16M + */ +#define DEFAULT_PCI_CONFIG_BASE 0x18000000 +#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 +#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 + +#ifndef __ASSEMBLY__ +#include +#include + +typedef volatile __u32 nlm_reg_t; +extern unsigned long netlogic_io_base; + +/* FIXME read once in write_reg */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define netlogic_read_reg(base, offset) ((base)[(offset)]) +#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value)) +#else +#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)])) +#define netlogic_write_reg(base, offset, value) \ + ((base)[(offset)] = cpu_to_be32((value))) +#endif + +#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)])) +#define netlogic_write_reg_le32(base, offset, value) \ + ((base)[(offset)] = cpu_to_le32((value))) +#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset))) +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h new file mode 100644 index 0000000..61da78d --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -0,0 +1,225 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASM_NLM_XLR_PIC_H +#define _ASM_NLM_XLR_PIC_H + +#define PIC_CLKS_PER_SEC 66666666ULL +/* PIC hardware interrupt numbers */ +#define PIC_IRT_WD_INDEX 0 +#define PIC_IRT_TIMER_0_INDEX 1 +#define PIC_IRT_TIMER_1_INDEX 2 +#define PIC_IRT_TIMER_2_INDEX 3 +#define PIC_IRT_TIMER_3_INDEX 4 +#define PIC_IRT_TIMER_4_INDEX 5 +#define PIC_IRT_TIMER_5_INDEX 6 +#define PIC_IRT_TIMER_6_INDEX 7 +#define PIC_IRT_TIMER_7_INDEX 8 +#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX +#define PIC_IRT_UART_0_INDEX 9 +#define PIC_IRT_UART_1_INDEX 10 +#define PIC_IRT_I2C_0_INDEX 11 +#define PIC_IRT_I2C_1_INDEX 12 +#define PIC_IRT_PCMCIA_INDEX 13 +#define PIC_IRT_GPIO_INDEX 14 +#define PIC_IRT_HYPER_INDEX 15 +#define PIC_IRT_PCIX_INDEX 16 +/* XLS */ +#define PIC_IRT_CDE_INDEX 15 +#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16 +/* XLS */ +#define PIC_IRT_GMAC0_INDEX 17 +#define PIC_IRT_GMAC1_INDEX 18 +#define PIC_IRT_GMAC2_INDEX 19 +#define PIC_IRT_GMAC3_INDEX 20 +#define PIC_IRT_XGS0_INDEX 21 +#define PIC_IRT_XGS1_INDEX 22 +#define PIC_IRT_HYPER_FATAL_INDEX 23 +#define PIC_IRT_PCIX_FATAL_INDEX 24 +#define PIC_IRT_BRIDGE_AERR_INDEX 25 +#define PIC_IRT_BRIDGE_BERR_INDEX 26 +#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27 +#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28 +/* XLS */ +#define PIC_IRT_GMAC4_INDEX 21 +#define PIC_IRT_GMAC5_INDEX 22 +#define PIC_IRT_GMAC6_INDEX 23 +#define PIC_IRT_GMAC7_INDEX 24 +#define PIC_IRT_BRIDGE_ERR_INDEX 25 +#define PIC_IRT_PCIE_LINK0_INDEX 26 +#define PIC_IRT_PCIE_LINK1_INDEX 27 +#define PIC_IRT_PCIE_LINK2_INDEX 23 +#define PIC_IRT_PCIE_LINK3_INDEX 24 +#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28 +#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29 +#define PIC_IRT_SRIO_LINK0_INDEX 26 +#define PIC_IRT_SRIO_LINK1_INDEX 27 +#define PIC_IRT_SRIO_LINK2_INDEX 28 +#define PIC_IRT_SRIO_LINK3_INDEX 29 +#define PIC_IRT_PCIE_INT_INDEX 28 +#define PIC_IRT_PCIE_FATAL_INDEX 29 +#define PIC_IRT_GPIO_B_INDEX 30 +#define PIC_IRT_USB_INDEX 31 +/* XLS */ +#define PIC_NUM_IRTS 32 + + +#define PIC_CLOCK_TIMER 7 + +/* PIC Registers */ +#define PIC_CTRL 0x00 +#define PIC_IPI 0x04 +#define PIC_INT_ACK 0x06 + +#define WD_MAX_VAL_0 0x08 +#define WD_MAX_VAL_1 0x09 +#define WD_MASK_0 0x0a +#define WD_MASK_1 0x0b +#define WD_HEARBEAT_0 0x0c +#define WD_HEARBEAT_1 0x0d + +#define PIC_IRT_0_BASE 0x40 +#define PIC_IRT_1_BASE 0x80 +#define PIC_TIMER_MAXVAL_0_BASE 0x100 +#define PIC_TIMER_MAXVAL_1_BASE 0x110 +#define PIC_TIMER_COUNT_0_BASE 0x120 +#define PIC_TIMER_COUNT_1_BASE 0x130 + +#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) +#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) + +#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) +#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i)) +#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i)) +#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i)) + +/* + * Mapping between hardware interrupt numbers and IRQs on CPU + * we use a simple scheme to map PIC interrupts 0-31 to IRQs + * 8-39. This leaves the IRQ 0-7 for cpu interrupts like + * count/compare and FMN + */ +#define PIC_IRQ_BASE 8 +#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) +#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) + +#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE +#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) +#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX) +#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX) +#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX) +#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX) +#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX) +#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX) +#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX) +#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX) +#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ) +#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX) +#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX) +#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX) +#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX) +#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX) +#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX) +#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX) +#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX) +/* XLS */ +#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX) +#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX) +/* end XLS */ +#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX) +#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX) +#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX) +#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX) +#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX) +#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX) +#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX) +#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX) +#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) +#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) +#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) +#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) +/* XLS defines */ +#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) +#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) +#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX) +#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX) +#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX) +#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX) +#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX) +#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX) +#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX) +#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX) +#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX) +#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX) +#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX) +#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX) +#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX) +#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX) +#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX) +#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX) +#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX) +#define PIC_IRT_LAST_IRQ PIC_USB_IRQ +/* end XLS */ + +#ifndef __ASSEMBLY__ +static inline void pic_send_ipi(u32 ipi) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_IPI, ipi); +} + +static inline u32 pic_read_control(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + return netlogic_read_reg(mmio, PIC_CTRL); +} + +static inline void pic_write_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, control); +} + +static inline void pic_update_control(u32 control) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + + netlogic_write_reg(mmio, PIC_CTRL, + (control | netlogic_read_reg(mmio, PIC_CTRL))); +} + +#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ + ((irq) <= PIC_TIMER_7_IRQ)) +#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ + ((irq) <= PIC_IRT_LAST_IRQ)) +#endif + +#endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h new file mode 100644 index 0000000..174bbdd --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -0,0 +1,20 @@ +#ifndef _ASM_NLM_XLR_H +#define _ASM_NLM_XLR_H + +/* Platform UART functions */ +struct uart_port; +unsigned int nlm_xlr_uart_in(struct uart_port *, int); +void nlm_xlr_uart_out(struct uart_port *, int, int); + +/* SMP support functions */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); +int nlm_wakeup_secondary_cpus(u32 wakeup_mask); +void nlm_smp_irq_init(void); +void nlm_boot_smp_nmi(void); +void prom_pre_boot_secondary_cpus(void); + +extern struct plat_smp_ops nlm_smp_ops; +extern unsigned long nlm_common_ebase; + +#endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c new file mode 100644 index 0000000..6d2b4ff --- /dev/null +++ b/arch/mips/netlogic/xlr/irq.c @@ -0,0 +1,281 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +static u64 nlm_irq_mask; +static DEFINE_SPINLOCK(nlm_pic_lock); + +static void pic_unmask(unsigned int irq) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + unsigned long flags; + nlm_reg_t reg; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + reg | (1 << 6) | (1 << 30) | (1 << 31)); + spin_unlock_irqrestore(&nlm_pic_lock, flags); + + return; +} + +static void pic_ack(unsigned int irq) +{ + unsigned long flags; + nlm_reg_t *mmio; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static void pic_end(unsigned int irq) +{ + unsigned long flags; + nlm_reg_t *mmio; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + if (PIC_IRQ_IS_EDGE_TRIGGERED(irq)) + return; + + /* If level triggered, ack it after the device condition is cleared */ + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static void pic_shutdown(unsigned int irq) +{ + nlm_reg_t *mmio; + unsigned long flags; + nlm_reg_t reg; + + if (!PIC_IRQ_IS_IRT(irq)) + return; + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); + netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, + (reg & ~(1 << 31))); + spin_unlock_irqrestore(&nlm_pic_lock, flags); +} + +static int pic_set_affinity(unsigned int irq, const struct cpumask *mask) +{ + nlm_reg_t *mmio; + unsigned long flags; + + if (!PIC_IRQ_IS_IRT(irq)) + return -1; + + mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + spin_lock_irqsave(&nlm_pic_lock, flags); + netlogic_write_reg(mmio, PIC_IRT_0_BASE + irq - PIC_IRQ_BASE, + (uint32_t)(mask->bits[0])); + spin_unlock_irqrestore(&nlm_pic_lock, flags); + + return 0; +} + +static struct irq_chip xlr_pic = { + .name = "XLR-PIC", + .unmask = pic_unmask, + .mask = pic_shutdown, + .ack = pic_ack, + .end = pic_end, + .set_affinity = pic_set_affinity +}; + +static void rsvd_pic_handler_1(unsigned int irq) +{ + WARN_ON(irq >= PIC_IRQ_BASE); + return; +} + +static int rsvd_pic_handler_2(unsigned int irq, const struct cpumask *mask) +{ + if (irq < PIC_IRQ_BASE) + return -1; + + BUG(); + return 0; +} + +struct irq_chip nlm_rsvd_pic = { + .name = "XLR-RSVD-PIC", + .unmask = rsvd_pic_handler_1, + .mask = rsvd_pic_handler_1, + .ack = rsvd_pic_handler_1, + .end = rsvd_pic_handler_1, + .set_affinity = rsvd_pic_handler_2 +}; + +static irqreturn_t nlm_rsvd_irq_handler(int irq, void *dev_id) +{ + if (irq == IRQ_TIMER) + return IRQ_HANDLED; + BUG(); + return IRQ_NONE; +} + +struct irqaction xlr_rsvd_action = { + .handler = nlm_rsvd_irq_handler, + .flags = 0, + .name = "xlr_rsvd_action", + .dev_id = 0, + .next = 0 +}; + +void __init init_xlr_irqs(void) +{ + nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + uint32_t thread_mask = 1; + int level, i; + + pr_info("Interrupt thread mask [%x]\n", thread_mask); + for (i = 0; i < PIC_NUM_IRTS; i++) { + level = PIC_IRQ_IS_EDGE_TRIGGERED(i); + + /* Bind all PIC irqs to boot cpu */ + netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask); + + /* + * Use local scheduling and high polarity for all IRTs + * Invalidate all IRTs, by default + */ + netlogic_write_reg(mmio, PIC_IRT_1_BASE + i, + (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i)); + } + + /* Make all IRQs as level triggered by default */ + for (i = 0; i < NR_IRQS; i++) { + set_irq_chip(i, &xlr_pic); + set_irq_handler(i, handle_level_irq); + } + +#ifdef CONFIG_SMP + irq_desc[IRQ_IPI_SMP_FUNCTION].chip = &nlm_rsvd_pic; + irq_desc[IRQ_IPI_SMP_FUNCTION].action = &xlr_rsvd_action; + set_irq_handler(IRQ_IPI_SMP_FUNCTION, nlm_smp_function_ipi_handler); + + irq_desc[IRQ_IPI_SMP_RESCHEDULE].chip = &nlm_rsvd_pic; + irq_desc[IRQ_IPI_SMP_RESCHEDULE].action = &xlr_rsvd_action; + set_irq_handler(IRQ_IPI_SMP_RESCHEDULE, nlm_smp_resched_ipi_handler); + + nlm_irq_mask |= + ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE)); +#endif + +#ifdef notyet /* message ring driver not enabled yet */ + /* msgring interrupt */ + irq_desc[IRQ_MSGRING].chip = &nlm_rsvd_pic; + irq_desc[IRQ_MSGRING].action = &xlr_rsvd_action; + nlm_irq_mask |= (1ULL << IRQ_MSGRING); + set_irq_handler(IRQ_MSGRING, nlm_msgring_int_handler); +#endif + + /* unmask all PIC related interrupts. If no handler is installed by the + * drivers, it'll just ack the interrupt and return + */ + for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) + nlm_irq_mask |= (1ULL << i); + + nlm_irq_mask |= (1ULL << IRQ_TIMER); +} + +void __init arch_init_irq(void) +{ + /* Initialize the irq descriptors */ + init_xlr_irqs(); + write_c0_eimr(nlm_irq_mask); +} + +void __cpuinit nlm_smp_irq_init(void) +{ + /* set interrupt mask for non-zero cpus */ + write_c0_eimr(nlm_irq_mask); +} + +asmlinkage void plat_irq_dispatch(void) +{ + uint64_t eirr; + int i; + + eirr = read_c0_eirr() & read_c0_eimr(); + if (!eirr) + return; + + /* no need of EIRR here, writing compare clears interrupt */ + if (eirr & (1 << IRQ_TIMER)) { + do_IRQ(IRQ_TIMER); + return; + } + + /* TODO use dcltz: optimize below code */ + for (i = 63; i != -1; i--) { + if (eirr & (1ULL << i)) + break; + } + if (i == -1) { + pr_err("no interrupt !!\n"); + return; + } + + /* Ack eirr */ + write_c0_eirr(1ULL << i); + + do_IRQ(i); + return; +} diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c new file mode 100644 index 0000000..09d484d --- /dev/null +++ b/arch/mips/netlogic/xlr/platform.c @@ -0,0 +1,99 @@ +/* + * Copyright 2011, Netlogic Microsystems. + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) +{ + nlm_reg_t *mmio; + unsigned int value; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + value = netlogic_read_reg(mmio, 0); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + return value; +} + +void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) +{ + nlm_reg_t *mmio; + + /* XLR uart does not need any mapping of regs */ + mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); + + /* See XLR/XLS errata */ + if (offset == UART_MSR) + value ^= 0xF0; + else if (offset == UART_MCR) + value ^= 0x3; + + netlogic_write_reg(mmio, 0, value); +} + +#define PORT(_irq) \ + { \ + .irq = _irq, \ + .regshift = 2, \ + .iotype = UPIO_MEM32, \ + .flags = (UPF_SKIP_TEST | \ + UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\ + .uartclk = PIC_CLKS_PER_SEC, \ + .type = PORT_16550A, \ + .serial_in = nlm_xlr_uart_in, \ + .serial_out = nlm_xlr_uart_out, \ + } + +static struct plat_serial8250_port xlr_uart_data[] = { + PORT(PIC_UART_0_IRQ), + PORT(PIC_UART_1_IRQ), + {}, +}; + +static struct platform_device uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = xlr_uart_data, + }, +}; + +static int __init nlm_uart_init(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + xlr_uart_data[0].iobase = (unsigned long)mmio; + xlr_uart_data[0].membase = (void __iomem *)mmio; + xlr_uart_data[0].mapbase = (unsigned long)mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); + xlr_uart_data[1].iobase = (unsigned long)mmio; + xlr_uart_data[1].membase = (void __iomem *)mmio; + xlr_uart_data[1].mapbase = (unsigned long)mmio; + + return platform_device_register(&uart_device); +} + +arch_initcall(nlm_uart_init); diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c new file mode 100644 index 0000000..db42568 --- /dev/null +++ b/arch/mips/netlogic/xlr/setup.c @@ -0,0 +1,181 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); +unsigned long nlm_common_ebase = 0x0; +struct psb_info nlm_prom_info; + +static void nlm_early_serial_setup(void) +{ + struct uart_port s; + nlm_reg_t *uart_base; + + uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + memset(&s, 0, sizeof(s)); + s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + s.iotype = UPIO_MEM32; + s.regshift = 2; + s.irq = PIC_UART_0_IRQ; + s.uartclk = PIC_CLKS_PER_SEC; + s.serial_in = nlm_xlr_uart_in; + s.serial_out = nlm_xlr_uart_out; + s.mapbase = (unsigned long)uart_base; + s.membase = (unsigned char __iomem *)uart_base; + early_serial_setup(&s); +} + +static void nlm_linux_exit(void) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); + /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ + netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); + for ( ; ; ) + cpu_wait(); +} + +void __init plat_mem_setup(void) +{ + panic_timeout = 5; + _machine_restart = (void (*)(char *))nlm_linux_exit; + _machine_halt = nlm_linux_exit; + pm_power_off = nlm_linux_exit; +} + +const char *get_system_type(void) +{ + return "Netlogic XLR/XLS Series"; +} + +void __init prom_free_prom_memory(void) +{ + /* Nothing yet */ +} + +static void build_arcs_cmdline(char **argv) +{ + int i, remain, len; + char *arg; + + remain = sizeof(arcs_cmdline) - 1; + arcs_cmdline[0] = '\0'; + for (i = 0; argv[i] != NULL; i++) { + arg = argv[i]; + len = strlen(arg); + if (len + 1 > remain) + break; + strcat(arcs_cmdline, arg); + strcat(arcs_cmdline, " "); + remain -= len + 1; + } + + /* Add the default options here */ + if ((strstr(arcs_cmdline, "console=")) == NULL) { + arg = "console=ttyS0,38400 "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#ifdef CONFIG_BLK_DEV_INITRD + if ((strstr(arcs_cmdline, "rdinit=")) == NULL) { + arg = "rdinit=/sbin/init "; + len = strlen(arg); + if (len > remain) + goto fail; + strcat(arcs_cmdline, arg); + remain -= len; + } +#endif + return; +fail: + panic("Cannot add %s, command line too big!", arg); +} + +static void prom_add_memory(void) +{ + struct nlm_boot_mem_map *bootm; + u64 start, size; + u64 pref_backup = 512; /* avoid pref walking beyond end */ + int i; + + bootm = (void *)(unsigned long)nlm_prom_info.psb_mem_map; + for (i = 0; i < bootm->nr_map; i++) { + if (bootm->map[i].type != BOOT_MEM_RAM) + continue; + start = bootm->map[i].addr; + size = bootm->map[i].size; + + /* Work around for using bootloader mem */ + if (i == 0 && start == 0 && size == 0x0c000000) + size = 0x0ff00000; + + add_memory_region(start, size - pref_backup, BOOT_MEM_RAM); + } +} + +void __init prom_init(void) +{ + char **argv, **envp; + struct psb_info *prom_infop; + + argv = (char **)(int)fw_arg1; + envp = (char **)(int)fw_arg2; + prom_infop = (struct psb_info *)(int)fw_arg3; + + nlm_prom_info = *prom_infop; + + nlm_early_serial_setup(); + build_arcs_cmdline(argv); + nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); + prom_add_memory(); + +#ifdef CONFIG_SMP + nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map); + register_smp_ops(&nlm_smp_ops); +#endif +} diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c new file mode 100644 index 0000000..0c3b6d0 --- /dev/null +++ b/arch/mips/netlogic/xlr/smp.c @@ -0,0 +1,219 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +void core_send_ipi(int logical_cpu, unsigned int action) +{ + int cpu = cpu_logical_map(logical_cpu); + u32 tid = cpu & 0x3; + u32 pid = (cpu >> 2) & 0x07; + u32 ipi = (tid << 16) | (pid << 20); + + if (action & SMP_CALL_FUNCTION) + ipi |= IRQ_IPI_SMP_FUNCTION; + else if (action & SMP_RESCHEDULE_YOURSELF) + ipi |= IRQ_IPI_SMP_RESCHEDULE; + else + return; + + pic_send_ipi(ipi); +} + +void nlm_send_ipi_single(int cpu, unsigned int action) +{ + core_send_ipi(cpu, action); +} + +void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + int cpu; + + for_each_cpu(cpu, mask) { + core_send_ipi(cpu, action); + } +} + +/* IRQ_IPI_SMP_FUNCTION Handler */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + smp_call_function_interrupt(); +} + +/* IRQ_IPI_SMP_RESCHEDULE handler */ +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + set_need_resched(); +} + +void nlm_common_ipi_handler(int irq, struct pt_regs *regs) +{ + if (irq == IRQ_IPI_SMP_FUNCTION) { + smp_call_function_interrupt(); + } else { + /* Announce that we are for reschduling */ + set_need_resched(); + } +} + +/* + * Called before going into mips code, early cpu init + */ +void nlm_early_init_secondary(void) +{ + write_c0_ebase((uint32_t)nlm_common_ebase); + /* TLB partition here later */ +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit nlm_init_secondary(void) +{ + nlm_smp_irq_init(); +} + +void nlm_smp_finish(void) +{ +#ifdef notyet + nlm_common_msgring_cpu_init(); +#endif +} + +void nlm_cpus_done(void) +{ +} + +/* + * Boot all other cpus in the system, initialize them, and bring them into + * the boot function + */ +int nlm_cpu_unblock[NR_CPUS]; +int nlm_cpu_ready[NR_CPUS]; +unsigned long nlm_next_gp; +unsigned long nlm_next_sp; +cpumask_t phys_cpu_present_map; + +void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long)task_thread_info(idle); + unsigned long sp = (unsigned long)__KSTK_TOS(idle); + int cpu = cpu_logical_map(logical_cpu); + + nlm_next_sp = sp; + nlm_next_gp = gp; + + /* barrier */ + __sync(); + nlm_cpu_unblock[cpu] = 1; +} + +void __init nlm_smp_setup(void) +{ + unsigned int boot_cpu; + int num_cpus, i; + + boot_cpu = hard_smp_processor_id(); + cpus_clear(phys_cpu_present_map); + + cpu_set(boot_cpu, phys_cpu_present_map); + __cpu_number_map[boot_cpu] = 0; + __cpu_logical_map[0] = boot_cpu; + cpu_set(0, cpu_possible_map); + + num_cpus = 1; + for (i = 0; i < NR_CPUS; i++) { + if (nlm_cpu_ready[i]) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = num_cpus; + __cpu_logical_map[num_cpus] = i; + cpu_set(num_cpus, cpu_possible_map); + ++num_cpus; + } + } + + pr_info("Phys CPU present map: %lx, possible map %lx\n", + (unsigned long)phys_cpu_present_map.bits[0], + (unsigned long)cpu_possible_map.bits[0]); + + pr_info("Detected %i Slave CPU(s)\n", num_cpus); +} + +void nlm_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops nlm_smp_ops = { + .send_ipi_single = nlm_send_ipi_single, + .send_ipi_mask = nlm_send_ipi_mask, + .init_secondary = nlm_init_secondary, + .smp_finish = nlm_smp_finish, + .cpus_done = nlm_cpus_done, + .boot_secondary = nlm_boot_secondary, + .smp_setup = nlm_smp_setup, + .prepare_cpus = nlm_prepare_cpus, +}; + +unsigned long secondary_entry_point; + +int nlm_wakeup_secondary_cpus(u32 wakeup_mask) +{ + unsigned int tid, pid, ipi, i, boot_cpu; + void *reset_vec; + + secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus; + reset_vec = (void *)CKSEG1ADDR(0x1fc00000); + memcpy(reset_vec, nlm_boot_smp_nmi, 0x80); + boot_cpu = hard_smp_processor_id(); + + for (i = 0; i < NR_CPUS; i++) { + if (i == boot_cpu) + continue; + if (wakeup_mask & (1u << i)) { + tid = i & 0x3; + pid = (i >> 2) & 0x7; + ipi = (tid << 16) | (pid << 20) | (1 << 8); + pic_send_ipi(ipi); + } + } + + return 0; +} diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S new file mode 100644 index 0000000..0ccbc75 --- /dev/null +++ b/arch/mips/netlogic/xlr/smpboot.S @@ -0,0 +1,88 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/* Don't jump to linux function from Bootloader stack. Change it + * here. Kernel might allocate bootloader memory before all the CPUs are + * brought up (eg: Inode cache region) and we better don't overwrite this + * memory + */ +NESTED(prom_pre_boot_secondary_cpus, 16, sp) + .set mips64 + mfc0 t0, $15, 1 # read ebase + andi t0, 0x1f # t0 has the processor_id() + sll t0, 2 # offset in cpu array + + PTR_LA t1, nlm_cpu_ready # mark CPU ready + PTR_ADDU t1, t0 + li t2, 1 + sw t2, 0(t1) + + PTR_LA t1, nlm_cpu_unblock + PTR_ADDU t1, t0 +1: lw t2, 0(t1) # wait till unblocked + beqz t2, 1b + nop + + PTR_LA t1, nlm_next_sp + PTR_L sp, 0(t1) + PTR_LA t1, nlm_next_gp + PTR_L gp, 0(t1) + + PTR_LA t0, nlm_early_init_secondary + jalr t0 + nop + + PTR_LA t0, smp_bootstrap + jr t0 + nop +END(prom_pre_boot_secondary_cpus) + +NESTED(nlm_boot_smp_nmi, 0, sp) + .set push + .set noat + .set mips64 + .set noreorder + + /* Clear the NMI and BEV bits */ + MFC0 k0, CP0_STATUS + li k1, 0xffb7ffff + and k0, k0, k1 + MTC0 k0, CP0_STATUS + + PTR_LA k1, secondary_entry_point + PTR_L k0, 0(k1) + jr k0 + nop + .set pop +END(nlm_boot_smp_nmi) diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c new file mode 100644 index 0000000..896b398 --- /dev/null +++ b/arch/mips/netlogic/xlr/time.c @@ -0,0 +1,45 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return IRQ_TIMER; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = nlm_prom_info.cpu_frequency; + pr_info("MIPS counter frequency [%ld]\n", + (unsigned long)mips_hpt_frequency); +} diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/xlr_console.c new file mode 100644 index 0000000..cf8e128 --- /dev/null +++ b/arch/mips/netlogic/xlr/xlr_console.c @@ -0,0 +1,40 @@ +/* + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +void prom_putchar(char c) +{ + nlm_reg_t *mmio; + + mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); + while (netlogic_read_reg(mmio, 0x5) == 0) + ; + netlogic_write_reg(mmio, 0x0, c); +} -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Wed Mar 16 12:54:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 12:54:11 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1187 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491082Ab1CPLyD (ORCPT ); Wed, 16 Mar 2011 12:54:03 +0100 X-TM-IMSS-Message-ID: <248ef96900013c1d@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 248ef96900013c1d ; Wed, 16 Mar 2011 04:53:56 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 04:54:02 -0700 Date: Wed, 16 Mar 2011 17:29:04 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 6/7] Kconfig and Makefile update for Netlogic XLR/XLS Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 11:54:02.0416 (UTC) FILETIME=[D7D82300:01CBE3D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29388 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add NLM_XLR_BOARD, CPU_XLR and other config options Makefile updates, mostly based on r4k Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 42 +++++++++++++++++++++++++++++++++++++++ arch/mips/Makefile | 12 +++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/netlogic/Kconfig | 6 +++++ arch/mips/netlogic/xlr/Makefile | 5 ++++ 7 files changed, 68 insertions(+), 0 deletions(-) create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d889835..a955ced 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -735,6 +735,33 @@ config CAVIUM_OCTEON_REFERENCE_BOARD Hikari Say Y here for most Octeon reference boards. +config NLM_XLR_BOARD + bool "Netlogic XLR/XLS based systems" + depends on EXPERIMENTAL + select BOOT_ELF32 + select NLM_COMMON + select NLM_XLR + select SYS_HAS_CPU_XLR + select SYS_SUPPORTS_SMP + select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select 64BIT_PHYS_ADDR + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select DMA_COHERENT + select NR_CPUS_DEFAULT_32 + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select ZONE_DMA if 64BIT + select SYNC_R4K + select SYS_HAS_EARLY_PRINTK + help + Support for systems based on Netlogic XLR and XLS processors. + Say Y here if you have a XLR or XLS based board. + endchoice source "arch/mips/alchemy/Kconfig" @@ -751,6 +778,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/netlogic/Kconfig" endmenu @@ -1417,6 +1445,17 @@ config CPU_BMIPS5000 help Broadcom BMIPS5000 processors. +config CPU_XLR + bool "Netlogic XLR SoC" + depends on SYS_HAS_CPU_XLR + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select CPU_SUPPORTS_HUGEPAGES + help + Netlogic Microsystems XLR/XLS processors. endchoice if CPU_LOONGSON2F @@ -1547,6 +1586,9 @@ config SYS_HAS_CPU_BMIPS4380 config SYS_HAS_CPU_BMIPS5000 bool +config SYS_HAS_CPU_XLR + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7c1102e..63182c9 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -191,6 +191,18 @@ endif # include $(srctree)/arch/mips/Kbuild.platforms +# +# NETLOGIC SOC Common (common) +# +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic + +# +# NETLOGIC XLR/XLS SoC, Simulator and boards +# +core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ +load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 + cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cedee2b..83bba33 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o +obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 2adead5..b2cad4f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o +obj-$(CONFIG_CPU_XLR) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index d679c77..7fea5ff 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o +obj-$(CONFIG_CPU_XLR) += c-netlogic.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig new file mode 100644 index 0000000..8ab46ee --- /dev/null +++ b/arch/mips/netlogic/Kconfig @@ -0,0 +1,6 @@ +config NLM_COMMON + bool + +config NLM_XLR + bool + diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile new file mode 100644 index 0000000..9bd3f73 --- /dev/null +++ b/arch/mips/netlogic/xlr/Makefile @@ -0,0 +1,5 @@ +obj-y += setup.o platform.o irq.o setup.o time.o +obj-$(CONFIG_SMP) += smp.o smpboot.o +obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o + +EXTRA_CFLAGS += -Werror -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Wed Mar 16 12:54:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 12:54:37 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1186 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491068Ab1CPLyE (ORCPT ); Wed, 16 Mar 2011 12:54:04 +0100 X-TM-IMSS-Message-ID: <248ef9e600013c1e@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 248ef9e600013c1e ; Wed, 16 Mar 2011 04:53:56 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 04:54:28 -0700 Date: Wed, 16 Mar 2011 17:29:31 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 7/7] Add default configuration for XLR/XLS processors Message-ID: <32800a3159f889faa1d35bd41c904c61b85a17db.1300275485.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 11:54:29.0057 (UTC) FILETIME=[E7B93B10:01CBE3D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29389 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Cross compiled, built in rootfs with initrams, SMP enabled Signed-off-by: Jayachandran C --- arch/mips/configs/nlm_xlr_defconfig | 1699 +++++++++++++++++++++++++++++++++++ 1 files changed, 1699 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig new file mode 100644 index 0000000..967ed22 --- /dev/null +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -0,0 +1,1699 @@ +# +# Automatically generated make config: don't edit +# Linux/mips 2.6.38 Kernel Configuration +# Wed Mar 16 16:22:35 2011 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_NLM_XLR_BOARD=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_NLM_COMMON=y +CONFIG_NLM_XLR=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYNC_R4K=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_XLR=y +CONFIG_SYS_HAS_CPU_XLR=y +CONFIG_WEAK_ORDERING=y +CONFIG_WEAK_REORDERING_BEYOND_LLSC=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_SMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_32=y +CONFIG_NR_CPUS=32 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_KEXEC=y +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED is not set +# CONFIG_HAVE_SPARSE_IRQ is not set +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_PENDING_IRQ is not set +# CONFIG_AUTO_IRQ_AFFINITY is not set +CONFIG_IRQ_PER_CPU=y +# CONFIG_HARDIRQS_SW_RESEND is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +# CONFIG_EMBEDDED is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_VERBOSE is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM_OPS=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +# CONFIG_IP_VS_PE_SIP is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +CONFIG_PHONET=m +# CONFIG_PHONET_PIPECTRLR is not set +CONFIG_IEEE802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_RPS=y +CONFIG_XPS=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=y +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FC_TGT_ATTRS=y +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +# CONFIG_ISCSI_BOOT_SYSFS is not set +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_N_HDLC=m +# CONFIG_N_GSM is not set +CONFIG_RISCOM8=m +CONFIG_SPECIALIX=m +CONFIG_STALDRV=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +# CONFIG_TTY_PRINTK is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=m +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XZ is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EXOFS_FS=m +# CONFIG_EXOFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_NEW_IDMAPPER is not set +CONFIG_NFSD=m +CONFIG_NFSD_DEPRECATED=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_ACL is not set +CONFIG_CIFS_EXPERIMENTAL=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +# CONFIG_NCPFS_SMALLDOS is not set +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +# CONFIG_AFS_DEBUG is not set +# CONFIG_AFS_FSCACHE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +# CONFIG_ACORN_PARTITION_CUMANA is not set +# CONFIG_ACORN_PARTITION_EESOX is not set +CONFIG_ACORN_PARTITION_ICS=y +# CONFIG_ACORN_PARTITION_ADFS is not set +# CONFIG_ACORN_PARTITION_POWERTEC is not set +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +CONFIG_BKL=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_DETECTOR_RUNNABLE=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +# CONFIG_KGDB_LOW_LEVEL_TRAP is not set +# CONFIG_KGDB_KDB is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_TOMOYO=y +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_IMA is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=m +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_VIRTUALIZATION is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From sshtylyov@mvista.com Wed Mar 16 13:02:54 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 13:02:56 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:57562 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491052Ab1CPMCy (ORCPT ); Wed, 16 Mar 2011 13:02:54 +0100 Received: by wyb28 with SMTP id 28so1608098wyb.36 for ; Wed, 16 Mar 2011 05:02:48 -0700 (PDT) Received: by 10.227.21.145 with SMTP id j17mr741422wbb.33.1300276967739; Wed, 16 Mar 2011 05:02:47 -0700 (PDT) Received: from [192.168.2.2] ([91.79.96.124]) by mx.google.com with ESMTPS id h39sm538744wes.5.2011.03.16.05.02.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 16 Mar 2011 05:02:46 -0700 (PDT) Message-ID: <4D80A691.2020902@mvista.com> Date: Wed, 16 Mar 2011 15:01:21 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 MIME-Version: 1.0 To: Jayachandran C CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 1/7] Netlogic XLR/XLS processor IDs. References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 16-03-2011 14:57, Jayachandran C wrote: > Add Netlogic Microsystems company ID and processor IDs for XLR > and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. > Signed-off-by: Jayachandran C [...] > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index f65d4c8..a995d56 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) > } > } > > +static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) > +{ > + decode_configs(c); > + > + c->options = (MIPS_CPU_TLB | > + MIPS_CPU_4KEX | > + MIPS_CPU_COUNTER | > + MIPS_CPU_DIVEC | > + MIPS_CPU_WATCH | > + MIPS_CPU_EJTAG | > + MIPS_CPU_LLSC); > + > + switch (c->processor_id& 0xff00) { > + case PRID_IMP_NETLOGIC_XLR732: > + case PRID_IMP_NETLOGIC_XLR716: > + case PRID_IMP_NETLOGIC_XLR532: > + case PRID_IMP_NETLOGIC_XLR308: > + case PRID_IMP_NETLOGIC_XLR532C: > + case PRID_IMP_NETLOGIC_XLR516C: > + case PRID_IMP_NETLOGIC_XLR508C: > + case PRID_IMP_NETLOGIC_XLR308C: > + c->cputype = CPU_XLR; > + __cpu_name[cpu] = "Netlogic XLR"; > + break; > + > + case PRID_IMP_NETLOGIC_XLS608: > + case PRID_IMP_NETLOGIC_XLS408: > + case PRID_IMP_NETLOGIC_XLS404: > + case PRID_IMP_NETLOGIC_XLS208: > + case PRID_IMP_NETLOGIC_XLS204: > + case PRID_IMP_NETLOGIC_XLS108: > + case PRID_IMP_NETLOGIC_XLS104: > + case PRID_IMP_NETLOGIC_XLS616B: > + case PRID_IMP_NETLOGIC_XLS608B: > + case PRID_IMP_NETLOGIC_XLS416B: > + case PRID_IMP_NETLOGIC_XLS412B: > + case PRID_IMP_NETLOGIC_XLS408B: > + case PRID_IMP_NETLOGIC_XLS404B: > + c->cputype = CPU_XLR; > + __cpu_name[cpu] = "Netlogic XLS"; > + break; > + > + default: > + printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", > + c->processor_id); > + c->cputype = CPU_XLR; Why repeat this assignemnt in every case? Do it once only. WBR, Sergei From jayachandranc@netlogicmicro.com Wed Mar 16 14:27:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 14:27:53 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:3737 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491063Ab1CPN1u (ORCPT ); Wed, 16 Mar 2011 14:27:50 +0100 X-TM-IMSS-Message-ID: <24e4c43d00014081@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 24e4c43d00014081 ; Wed, 16 Mar 2011 06:27:39 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 06:19:37 -0700 Date: Wed, 16 Mar 2011 18:54:43 +0530 From: "Jayachandran C." To: Sergei Shtylyov Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 1/7] Netlogic XLR/XLS processor IDs. Message-ID: <20110316132442.GB15774@jayachandranc.netlogicmicro.com> References: <4D80A691.2020902@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D80A691.2020902@mvista.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 13:19:37.0558 (UTC) FILETIME=[CCA09F60:01CBE3DC] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips On Wed, Mar 16, 2011 at 03:01:21PM +0300, Sergei Shtylyov wrote: > Hello. > > On 16-03-2011 14:57, Jayachandran C wrote: > > >Add Netlogic Microsystems company ID and processor IDs for XLR > >and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. > > >Signed-off-by: Jayachandran C > [...] > > >diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > >index f65d4c8..a995d56 100644 > >--- a/arch/mips/kernel/cpu-probe.c > >+++ b/arch/mips/kernel/cpu-probe.c > >@@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) > > } > > } > > > >+static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) > >+{ > >+ decode_configs(c); > >+ > >+ c->options = (MIPS_CPU_TLB | > >+ MIPS_CPU_4KEX | > >+ MIPS_CPU_COUNTER | > >+ MIPS_CPU_DIVEC | > >+ MIPS_CPU_WATCH | > >+ MIPS_CPU_EJTAG | > >+ MIPS_CPU_LLSC); > >+ > >+ switch (c->processor_id& 0xff00) { > >+ case PRID_IMP_NETLOGIC_XLR732: > >+ case PRID_IMP_NETLOGIC_XLR716: > >+ case PRID_IMP_NETLOGIC_XLR532: > >+ case PRID_IMP_NETLOGIC_XLR308: > >+ case PRID_IMP_NETLOGIC_XLR532C: > >+ case PRID_IMP_NETLOGIC_XLR516C: > >+ case PRID_IMP_NETLOGIC_XLR508C: > >+ case PRID_IMP_NETLOGIC_XLR308C: > >+ c->cputype = CPU_XLR; > >+ __cpu_name[cpu] = "Netlogic XLR"; > >+ break; > >+ > >+ case PRID_IMP_NETLOGIC_XLS608: > >+ case PRID_IMP_NETLOGIC_XLS408: > >+ case PRID_IMP_NETLOGIC_XLS404: > >+ case PRID_IMP_NETLOGIC_XLS208: > >+ case PRID_IMP_NETLOGIC_XLS204: > >+ case PRID_IMP_NETLOGIC_XLS108: > >+ case PRID_IMP_NETLOGIC_XLS104: > >+ case PRID_IMP_NETLOGIC_XLS616B: > >+ case PRID_IMP_NETLOGIC_XLS608B: > >+ case PRID_IMP_NETLOGIC_XLS416B: > >+ case PRID_IMP_NETLOGIC_XLS412B: > >+ case PRID_IMP_NETLOGIC_XLS408B: > >+ case PRID_IMP_NETLOGIC_XLS404B: > >+ c->cputype = CPU_XLR; > >+ __cpu_name[cpu] = "Netlogic XLS"; > >+ break; > >+ > >+ default: > >+ printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", > >+ c->processor_id); > >+ c->cputype = CPU_XLR; > > Why repeat this assignemnt in every case? Do it once only. We will need to add new cases for c->cputype CPU_XLP in the next series of patches. So it reduces a few lines in the next patchset.... -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From David.Daney@caviumnetworks.com Wed Mar 16 17:49:11 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 17:49:14 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17294 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491109Ab1CPQtL (ORCPT ); Wed, 16 Mar 2011 17:49:11 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 16 Mar 2011 09:50:02 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 16 Mar 2011 09:49:06 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 16 Mar 2011 09:49:06 -0700 Message-ID: <4D80EA02.9030605@caviumnetworks.com> Date: Wed, 16 Mar 2011 09:49:06 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Jayachandran C CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 3/7] Add XLR/XLS cache and TLB support References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 16 Mar 2011 16:49:06.0635 (UTC) FILETIME=[106191B0:01CBE3FA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 03/16/2011 04:57 AM, Jayachandran C wrote: [...] > diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h > new file mode 100644 > index 0000000..7740401 > --- /dev/null > +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h > @@ -0,0 +1,9 @@ > +#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H > +#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H > + > +/* > + * Most of the properties are in cpu->options > + */ > +#define cpu_has_netlogic_cache 1 > + > +#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ Although this will probably work, you will likely get better performance if you supply static default values for as many overrides as possible. David Daney From jayachandranc@netlogicmicro.com Wed Mar 16 18:16:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Mar 2011 18:16:40 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:3055 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491109Ab1CPRQh (ORCPT ); Wed, 16 Mar 2011 18:16:37 +0100 X-TM-IMSS-Message-ID: <25b6493300014da2@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 25b6493300014da2 ; Wed, 16 Mar 2011 10:16:30 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Mar 2011 10:17:26 -0700 Date: Wed, 16 Mar 2011 22:52:33 +0530 From: "Jayachandran C." To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 3/7] Add XLR/XLS cache and TLB support Message-ID: <20110316172232.GG15774@jayachandranc.netlogicmicro.com> References: <4D80EA02.9030605@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D80EA02.9030605@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 16 Mar 2011 17:17:26.0679 (UTC) FILETIME=[05AFB270:01CBE3FE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips On Wed, Mar 16, 2011 at 09:49:06AM -0700, David Daney wrote: > On 03/16/2011 04:57 AM, Jayachandran C wrote: > [...] > >diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h > >new file mode 100644 > >index 0000000..7740401 > >--- /dev/null > >+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h > >@@ -0,0 +1,9 @@ > >+#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H > >+#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H > >+ > >+/* > >+ * Most of the properties are in cpu->options > >+ */ > >+#define cpu_has_netlogic_cache 1 > >+ > >+#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ > > Although this will probably work, you will likely get better > performance if you supply static default values for as many > overrides as possible. True, we will miss possible compile-time optimizations, will look at this. Thanks! JC. -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From greg@kroah.com Thu Mar 17 22:46:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Mar 2011 22:46:48 +0100 (CET) Received: from kroah.org ([198.145.64.141]:54897 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491167Ab1CQVqo (ORCPT ); Thu, 17 Mar 2011 22:46:44 +0100 Received: from localhost (c-76-121-69-168.hsd1.wa.comcast.net [76.121.69.168]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id 99E824896A; Thu, 17 Mar 2011 14:46:42 -0700 (PDT) X-Mailbox-Line: From gregkh@clark.kroah.org Thu Mar 17 14:29:27 2011 Message-Id: <20110317212927.798598536@clark.kroah.org> User-Agent: quilt/0.48-16.4 Date: Thu, 17 Mar 2011 14:28:00 -0700 From: Greg KH To: stable-review@kernel.org, linux-mips@linux-mips.org Cc: Florian Fainelli , Ralf Baechle Subject: [430/474] MIPS: MTX-1: Make au1000_eth probe all PHY addresses In-Reply-To: <20110317213822.GA27980@kroah.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips 2.6.33-longterm review patch. If anyone has any objections, please let us know. ------------------ Content-Length: 1478 Lines: 50 From: Florian Fainelli commit bf3a1eb85967dcbaae42f4fcb53c2392cec32677 upstream. When au1000_eth probes the MII bus for PHY address, if we do not set au1000_eth platform data's phy_search_highest_address, the MII probing logic will exit early and will assume a valid PHY is found at address 0. For MTX-1, the PHY is at address 31, and without this patch, the link detection/speed/duplex would not work correctly. Signed-off-by: Florian Fainelli To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2111/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/alchemy/mtx-1/platform.c | 9 +++++++++ 1 file changed, 9 insertions(+) --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/mtx-1/platform.c @@ -28,6 +28,8 @@ #include #include +#include + static struct gpio_keys_button mtx1_gpio_button[] = { { .gpio = 207, @@ -140,10 +142,17 @@ static struct __initdata platform_device &mtx1_mtd, }; +static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = { + .phy_search_highest_addr = 1, + .phy1_search_mac0 = 1, +}; + static int __init mtx1_register_devices(void) { int rc; + au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata); + rc = gpio_request(mtx1_gpio_button[0].gpio, mtx1_gpio_button[0].desc); if (rc < 0) { From wuzhangjin@gmail.com Fri Mar 18 04:26:12 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 04:26:15 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:62484 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490947Ab1CRD0L convert rfc822-to-8bit (ORCPT ); Fri, 18 Mar 2011 04:26:11 +0100 Received: by ywa8 with SMTP id 8so1512897ywa.36 for ; Thu, 17 Mar 2011 20:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=bIiQKlWKc6wKg7HdOs3k5fVhDQLq2bmJc+4ygoRk4cc=; b=fm5DrrG4RxdM4dVILM9E2DBWQUcaRrSwHzFiJwuJj4WvfIRt3PSqwyjcBToIyKdOH4 V+gxI0Q21KV/BJMTVI3q9YbiO7Vmqdkje3SFrggh2aQcdDKyyvi1RHXDq6Ij2baW6pkX aT+Pq2q1ejMlgmXyqNZrmJiaE1p4KIK0n1el8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=bqXmcjVv5OIiflp9lNH9x6Z5ZtWTcl3h0QzLDju5ml9e7KAQev5QfLidb35MuxINB3 XqMsH+F9pf7YB5Cbq27r4zooYoJk3eiwZh1DF7Q3Ua9vqFBBAq6uMv9Uz/0+kb3U0w5w C6pFoBOoqbOakWOg8833hlDxxq6CwWKnwwI8w= MIME-Version: 1.0 Received: by 10.146.144.8 with SMTP id r8mr600683yad.9.1300418765086; Thu, 17 Mar 2011 20:26:05 -0700 (PDT) Received: by 10.147.82.6 with HTTP; Thu, 17 Mar 2011 20:26:05 -0700 (PDT) In-Reply-To: <20110314142927.GA18480@jayachandranc.netlogicmicro.com> References: <20110312182714.GC2217@jayachandranc.netlogicmicro.com> <20110314142927.GA18480@jayachandranc.netlogicmicro.com> Date: Fri, 18 Mar 2011 11:26:05 +0800 Message-ID: Subject: Re: [PATCH] Support for Netlogic XLR/XLS processors From: wu zhangjin To: "Jayachandran C." Cc: "wilbur.chan" , Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Mon, Mar 14, 2011 at 10:29 PM, Jayachandran C. wrote: > On Mon, Mar 14, 2011 at 08:19:22PM +0800, wilbur.chan wrote: >> Will kexec be supported on XLS/XLR/XLP ? > > The patches I have does not support it. I haven't really looked at what > is needed in XLR platform code to support kexec, so I'm not sure what it > takes to support it for XLR either. Any pointers? You can get some information here: http://dev.lemote.com/code/linux-loongson-community/wiki/kexec-loongson And here: http://patchwork.linux-mips.org/project/linux-mips/list/?q=kexec BTW: what about the cpu hotplug support for XL{R, S, P} ? Regards, Wu Zhangjin > > JC. > -- > Jayachandran C. > jayachandranc@netlogicmicro.com (Netlogic Microsystems) > jchandra@freebsd.org (The FreeBSD Project) > > From admin@heiher.info Fri Mar 18 05:59:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 05:59:51 +0100 (CET) Received: from mail-qw0-f49.google.com ([209.85.216.49]:35165 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490980Ab1CRE7s (ORCPT ); Fri, 18 Mar 2011 05:59:48 +0100 Received: by qwi2 with SMTP id 2so2724600qwi.36 for ; Thu, 17 Mar 2011 21:59:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.63.229 with SMTP id c37mr535291qci.212.1300424380685; Thu, 17 Mar 2011 21:59:40 -0700 (PDT) Received: by 10.229.27.70 with HTTP; Thu, 17 Mar 2011 21:59:40 -0700 (PDT) X-Originating-IP: [74.117.61.21] Date: Fri, 18 Mar 2011 12:59:40 +0800 Message-ID: Subject: [PATCH] Fixup personality in different ABI. From: Heiher To: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: admin@heiher.info Precedence: bulk X-list: linux-mips Hello, From bf3637153bc5e3d0e3f1c2982c323057a8e04801 Mon Sep 17 00:00:00 2001 From: Heiher Date: Fri, 18 Mar 2011 12:51:08 +0800 Subject: [PATCH] Fixup personality in different ABI. * 'arch' output: o32 : mips n32 : mips64 64 : mips64 --- arch/mips/include/asm/elf.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index 455c0ac..01510d4 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -262,6 +262,7 @@ do { \ #ifdef CONFIG_MIPS32_N32 #define __SET_PERSONALITY32_N32() \ do { \ + set_personality(PER_LINUX); \ set_thread_flag(TIF_32BIT_ADDR); \ current->thread.abi = &mips_abi_n32; \ } while (0) @@ -273,6 +274,7 @@ do { \ #ifdef CONFIG_MIPS32_O32 #define __SET_PERSONALITY32_O32() \ do { \ + set_personality(PER_LINUX32); \ set_thread_flag(TIF_32BIT_REGS); \ set_thread_flag(TIF_32BIT_ADDR); \ current->thread.abi = &mips_abi_32; \ @@ -305,7 +307,10 @@ do { \ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ __SET_PERSONALITY32(ex); \ else \ + { \ + set_personality(PER_LINUX); \ current->thread.abi = &mips_abi; \ + } \ \ p = personality(current->personality); \ if (p != PER_LINUX32 && p != PER_LINUX) \ -- 1.7.4.1.225.g83c3c -- Best regards! Heiher From jayachandranc@netlogicmicro.com Fri Mar 18 10:01:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 10:01:10 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:1320 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491116Ab1CRJBG (ORCPT ); Fri, 18 Mar 2011 10:01:06 +0100 X-TM-IMSS-Message-ID: <2e3d47930001a26f@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2e3d47930001a26f ; Fri, 18 Mar 2011 02:00:56 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Mar 2011 02:01:17 -0700 Date: Fri, 18 Mar 2011 14:36:32 +0530 From: "Jayachandran C." To: wu zhangjin Cc: "wilbur.chan" , Linux MIPS Mailing List Subject: Re: [PATCH] Support for Netlogic XLR/XLS processors Message-ID: <20110318090631.GA8628@jayachandranc.netlogicmicro.com> References: <20110312182714.GC2217@jayachandranc.netlogicmicro.com> <20110314142927.GA18480@jayachandranc.netlogicmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 18 Mar 2011 09:01:17.0396 (UTC) FILETIME=[0AA31940:01CBE54B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips On Fri, Mar 18, 2011 at 11:26:05AM +0800, wu zhangjin wrote: > On Mon, Mar 14, 2011 at 10:29 PM, Jayachandran C. > wrote: > > On Mon, Mar 14, 2011 at 08:19:22PM +0800, wilbur.chan wrote: > >> Will kexec be supported on XLS/XLR/XLP ? > > > > The patches I have does not support it. I haven't really looked at what > > is needed in XLR platform code to support kexec, so I'm not sure what it > > takes to support it for XLR either. Any pointers? > > You can get some information here: > > http://dev.lemote.com/code/linux-loongson-community/wiki/kexec-loongson > > And here: > > http://patchwork.linux-mips.org/project/linux-mips/list/?q=kexec Will look at this. > BTW: what about the cpu hotplug support for XL{R, S, P} ? Not right now. My intial goal for Linux/MIPS is hardware support, i.e. processor support and then drivers. I can start thinking of feature support once we have reasonable hardware support in the kernel... -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From sshtylyov@mvista.com Fri Mar 18 11:18:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 11:18:24 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:59293 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491146Ab1CRKSU (ORCPT ); Fri, 18 Mar 2011 11:18:20 +0100 Received: by wwb17 with SMTP id 17so4107960wwb.24 for ; Fri, 18 Mar 2011 03:18:14 -0700 (PDT) Received: by 10.227.177.199 with SMTP id bj7mr1005366wbb.140.1300443494796; Fri, 18 Mar 2011 03:18:14 -0700 (PDT) Received: from [192.168.2.2] ([91.79.74.94]) by mx.google.com with ESMTPS id bd8sm1251521wbb.18.2011.03.18.03.18.12 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 18 Mar 2011 03:18:13 -0700 (PDT) Message-ID: <4D833110.8020306@mvista.com> Date: Fri, 18 Mar 2011 13:16:48 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 MIME-Version: 1.0 To: Heiher CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Fixup personality in different ABI. References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 18-03-2011 7:59, Heiher wrote: > Hello, > From bf3637153bc5e3d0e3f1c2982c323057a8e04801 Mon Sep 17 00:00:00 2001 > From: Heiher > Date: Fri, 18 Mar 2011 12:51:08 +0800 > Subject: [PATCH] Fixup personality in different ABI. This header (and "Hello") should be omitted, or the maintainer will have to hand edit it out of the patch... > * 'arch' output: > o32 : mips > n32 : mips64 > 64 : mips64 You should sign off the patch (with your real name) for it to be applied. > diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h > index 455c0ac..01510d4 100644 > --- a/arch/mips/include/asm/elf.h > +++ b/arch/mips/include/asm/elf.h [...] > @@ -305,7 +307,10 @@ do { \ > if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ > __SET_PERSONALITY32(ex); \ > else \ > + { \ { should be on the same line with *else*. WBR, Sergei From jayachandranc@netlogicmicro.com Fri Mar 18 14:27:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 14:27:48 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4554 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491819Ab1CRN1o (ORCPT ); Fri, 18 Mar 2011 14:27:44 +0100 X-TM-IMSS-Message-ID: <2f3161520001a99d@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2f3161520001a99d ; Fri, 18 Mar 2011 06:27:33 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Mar 2011 06:22:45 -0700 Date: Fri, 18 Mar 2011 18:58:02 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 1/7] Netlogic XLR/XLS processor IDs. Message-ID: <82409e0e9e91d1589afa1d6fb1375da89b8854b3.1300452150.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 18 Mar 2011 13:22:46.0035 (UTC) FILETIME=[91CB6E30:01CBE56F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add Netlogic Microsystems company ID and processor IDs for XLR and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum. Signed-off-by: Jayachandran C --- arch/mips/include/asm/cpu.h | 27 ++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..34c0d3c 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 @@ -142,6 +143,31 @@ #define PRID_IMP_JZRISC 0x0200 /* + * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC + */ +#define PRID_IMP_NETLOGIC_XLR732 0x0000 +#define PRID_IMP_NETLOGIC_XLR716 0x0200 +#define PRID_IMP_NETLOGIC_XLR532 0x0900 +#define PRID_IMP_NETLOGIC_XLR308 0x0600 +#define PRID_IMP_NETLOGIC_XLR532C 0x0800 +#define PRID_IMP_NETLOGIC_XLR516C 0x0a00 +#define PRID_IMP_NETLOGIC_XLR508C 0x0b00 +#define PRID_IMP_NETLOGIC_XLR308C 0x0f00 +#define PRID_IMP_NETLOGIC_XLS608 0x8000 +#define PRID_IMP_NETLOGIC_XLS408 0x8800 +#define PRID_IMP_NETLOGIC_XLS404 0x8c00 +#define PRID_IMP_NETLOGIC_XLS208 0x8e00 +#define PRID_IMP_NETLOGIC_XLS204 0x8f00 +#define PRID_IMP_NETLOGIC_XLS108 0xce00 +#define PRID_IMP_NETLOGIC_XLS104 0xcf00 +#define PRID_IMP_NETLOGIC_XLS616B 0x4000 +#define PRID_IMP_NETLOGIC_XLS608B 0x4a00 +#define PRID_IMP_NETLOGIC_XLS416B 0x4400 +#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 +#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 +#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 + +/* * Definitions for 7:0 on legacy processors */ @@ -234,6 +260,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, + CPU_XLR, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f65d4c8..a995d56 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -988,6 +988,59 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + c->options = (MIPS_CPU_TLB | + MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | + MIPS_CPU_WATCH | + MIPS_CPU_EJTAG | + MIPS_CPU_LLSC); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_NETLOGIC_XLR732: + case PRID_IMP_NETLOGIC_XLR716: + case PRID_IMP_NETLOGIC_XLR532: + case PRID_IMP_NETLOGIC_XLR308: + case PRID_IMP_NETLOGIC_XLR532C: + case PRID_IMP_NETLOGIC_XLR516C: + case PRID_IMP_NETLOGIC_XLR508C: + case PRID_IMP_NETLOGIC_XLR308C: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLR"; + break; + + case PRID_IMP_NETLOGIC_XLS608: + case PRID_IMP_NETLOGIC_XLS408: + case PRID_IMP_NETLOGIC_XLS404: + case PRID_IMP_NETLOGIC_XLS208: + case PRID_IMP_NETLOGIC_XLS204: + case PRID_IMP_NETLOGIC_XLS108: + case PRID_IMP_NETLOGIC_XLS104: + case PRID_IMP_NETLOGIC_XLS616B: + case PRID_IMP_NETLOGIC_XLS608B: + case PRID_IMP_NETLOGIC_XLS416B: + case PRID_IMP_NETLOGIC_XLS412B: + case PRID_IMP_NETLOGIC_XLS408B: + case PRID_IMP_NETLOGIC_XLS404B: + c->cputype = CPU_XLR; + __cpu_name[cpu] = "Netlogic XLS"; + break; + + default: + printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", + c->processor_id); + c->cputype = CPU_XLR; + break; + } + + c->isa_level = MIPS_CPU_ISA_M64R1; + c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; +} + #ifdef CONFIG_64BIT /* For use by uaccess.h */ u64 __ua_limit; @@ -1034,6 +1087,8 @@ __cpuinit void cpu_probe(void) break; case PRID_COMP_INGENIC: cpu_probe_ingenic(c, cpu); + case PRID_COMP_NETLOGIC: + cpu_probe_netlogic(c, cpu); break; } -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Mar 18 14:28:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 14:28:13 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4557 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491889Ab1CRN1o (ORCPT ); Fri, 18 Mar 2011 14:27:44 +0100 X-TM-IMSS-Message-ID: <2f3162aa0001a9a0@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2f3162aa0001a9a0 ; Fri, 18 Mar 2011 06:27:34 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Mar 2011 06:23:59 -0700 Date: Fri, 18 Mar 2011 18:59:15 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 4/7] Add XLR to asm/module.h Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 18 Mar 2011 13:23:59.0567 (UTC) FILETIME=[BD9F85F0:01CBE56F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Signed-off-by: Jayachandran C --- arch/mips/include/asm/module.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index d94085a..bc01a02 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON2 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " +#elif defined CONFIG_CPU_XLR +#define MODULE_PROC_FAMILY "XLR " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Mar 18 14:28:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 14:28:39 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4555 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491879Ab1CRN1o (ORCPT ); Fri, 18 Mar 2011 14:27:44 +0100 X-TM-IMSS-Message-ID: <2f3160d50001a99c@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2f3160d50001a99c ; Fri, 18 Mar 2011 06:27:33 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Mar 2011 06:22:00 -0700 Date: Fri, 18 Mar 2011 18:57:17 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 0/7] Support for Netlogic XLR/XLS processors Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 18 Mar 2011 13:22:00.0941 (UTC) FILETIME=[76EAA1D0:01CBE56F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Updated patchset for Netlogic processor support. Changes from last version: * Remove c-netlogic.c for now, c-r4k works well enough for the first cut, so the custom cache handler can be considered later. * More elaborate asm/mach-netlogic/cpu-feature-overrides.h (noted by David Daney) These set of patches add support for the XLR and XLS multi-core MIPS64 SoCs from Netlogic Microsystems. These changes enable us to boot Linux/MIPS on Netlogic evaluation boards from the netlogic bootloader. As always, comments on code and licenses welcome. Jayachandran C (7): Netlogic XLR/XLS processor IDs. mach-netlogic include directory and files Cache, TLB support, and feature overrides for XLR Add XLR to asm/module.h Platform files for XLR/XLS processor support Kconfig and Makefile update for Netlogic XLR/XLS Add default configuration for XLR/XLS processors arch/mips/Kconfig | 42 + arch/mips/Makefile | 12 + arch/mips/configs/nlm_xlr_defconfig | 1698 ++++++++++++++++++++ arch/mips/include/asm/cpu.h | 27 + .../asm/mach-netlogic/cpu-feature-overrides.h | 47 + arch/mips/include/asm/mach-netlogic/irq.h | 14 + arch/mips/include/asm/mach-netlogic/war.h | 26 + arch/mips/include/asm/module.h | 2 + arch/mips/include/asm/netlogic/interrupt.h | 39 + arch/mips/include/asm/netlogic/mips-extns.h | 69 + arch/mips/include/asm/netlogic/psb-bootinfo.h | 103 ++ arch/mips/include/asm/netlogic/xlr/gpio.h | 67 + arch/mips/include/asm/netlogic/xlr/iomap.h | 125 ++ arch/mips/include/asm/netlogic/xlr/pic.h | 225 +++ arch/mips/include/asm/netlogic/xlr/xlr.h | 20 + arch/mips/kernel/Makefile | 1 + arch/mips/kernel/cpu-probe.c | 55 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + arch/mips/netlogic/Kconfig | 5 + arch/mips/netlogic/xlr/Makefile | 5 + arch/mips/netlogic/xlr/irq.c | 281 ++++ arch/mips/netlogic/xlr/platform.c | 99 ++ arch/mips/netlogic/xlr/setup.c | 181 +++ arch/mips/netlogic/xlr/smp.c | 219 +++ arch/mips/netlogic/xlr/smpboot.S | 88 + arch/mips/netlogic/xlr/time.c | 45 + arch/mips/netlogic/xlr/xlr_console.c | 40 + 30 files changed, 3539 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h create mode 100644 arch/mips/include/asm/netlogic/interrupt.h create mode 100644 arch/mips/include/asm/netlogic/mips-extns.h create mode 100644 arch/mips/include/asm/netlogic/psb-bootinfo.h create mode 100644 arch/mips/include/asm/netlogic/xlr/gpio.h create mode 100644 arch/mips/include/asm/netlogic/xlr/iomap.h create mode 100644 arch/mips/include/asm/netlogic/xlr/pic.h create mode 100644 arch/mips/include/asm/netlogic/xlr/xlr.h create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile create mode 100644 arch/mips/netlogic/xlr/irq.c create mode 100644 arch/mips/netlogic/xlr/platform.c create mode 100644 arch/mips/netlogic/xlr/setup.c create mode 100644 arch/mips/netlogic/xlr/smp.c create mode 100644 arch/mips/netlogic/xlr/smpboot.S create mode 100644 arch/mips/netlogic/xlr/time.c create mode 100644 arch/mips/netlogic/xlr/xlr_console.c -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Mar 18 14:28:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 14:29:05 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4559 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491870Ab1CRN1o (ORCPT ); Fri, 18 Mar 2011 14:27:44 +0100 X-TM-IMSS-Message-ID: <2f3165f60001a9a4@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2f3165f60001a9a4 ; Fri, 18 Mar 2011 06:27:34 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Mar 2011 06:25:20 -0700 Date: Fri, 18 Mar 2011 19:00:36 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 6/7] Kconfig and Makefile update for Netlogic XLR/XLS Message-ID: <969894be65246b6ca932d968cdaa6accb9870699.1300452150.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 18 Mar 2011 13:25:20.0286 (UTC) FILETIME=[EDBC43E0:01CBE56F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add NLM_XLR_BOARD, CPU_XLR and other config options Makefile updates, mostly based on r4k Signed-off-by: Jayachandran C --- arch/mips/Kconfig | 42 +++++++++++++++++++++++++++++++++++++++ arch/mips/Makefile | 12 +++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/lib/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/netlogic/Kconfig | 5 ++++ arch/mips/netlogic/xlr/Makefile | 5 ++++ 7 files changed, 67 insertions(+), 0 deletions(-) create mode 100644 arch/mips/netlogic/Kconfig create mode 100644 arch/mips/netlogic/xlr/Makefile diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d889835..a955ced 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -735,6 +735,33 @@ config CAVIUM_OCTEON_REFERENCE_BOARD Hikari Say Y here for most Octeon reference boards. +config NLM_XLR_BOARD + bool "Netlogic XLR/XLS based systems" + depends on EXPERIMENTAL + select BOOT_ELF32 + select NLM_COMMON + select NLM_XLR + select SYS_HAS_CPU_XLR + select SYS_SUPPORTS_SMP + select HW_HAS_PCI + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select 64BIT_PHYS_ADDR + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select DMA_COHERENT + select NR_CPUS_DEFAULT_32 + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select ZONE_DMA if 64BIT + select SYNC_R4K + select SYS_HAS_EARLY_PRINTK + help + Support for systems based on Netlogic XLR and XLS processors. + Say Y here if you have a XLR or XLS based board. + endchoice source "arch/mips/alchemy/Kconfig" @@ -751,6 +778,7 @@ source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/netlogic/Kconfig" endmenu @@ -1417,6 +1445,17 @@ config CPU_BMIPS5000 help Broadcom BMIPS5000 processors. +config CPU_XLR + bool "Netlogic XLR SoC" + depends on SYS_HAS_CPU_XLR + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select CPU_SUPPORTS_HUGEPAGES + help + Netlogic Microsystems XLR/XLS processors. endchoice if CPU_LOONGSON2F @@ -1547,6 +1586,9 @@ config SYS_HAS_CPU_BMIPS4380 config SYS_HAS_CPU_BMIPS5000 bool +config SYS_HAS_CPU_XLR + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7c1102e..63182c9 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -191,6 +191,18 @@ endif # include $(srctree)/arch/mips/Kbuild.platforms +# +# NETLOGIC SOC Common (common) +# +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic +cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic + +# +# NETLOGIC XLR/XLS SoC, Simulator and boards +# +core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ +load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 + cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cedee2b..83bba33 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o +obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 2adead5..b2cad4f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o +obj-$(CONFIG_CPU_XLR) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index d679c77..eb44636 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o +obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig new file mode 100644 index 0000000..a5ca743 --- /dev/null +++ b/arch/mips/netlogic/Kconfig @@ -0,0 +1,5 @@ +config NLM_COMMON + bool + +config NLM_XLR + bool diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile new file mode 100644 index 0000000..9bd3f73 --- /dev/null +++ b/arch/mips/netlogic/xlr/Makefile @@ -0,0 +1,5 @@ +obj-y += setup.o platform.o irq.o setup.o time.o +obj-$(CONFIG_SMP) += smp.o smpboot.o +obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o + +EXTRA_CFLAGS += -Werror -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Mar 18 14:29:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 14:29:28 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4558 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491885Ab1CRN1o (ORCPT ); Fri, 18 Mar 2011 14:27:44 +0100 X-TM-IMSS-Message-ID: <2f3161cf0001a99e@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2f3161cf0001a99e ; Fri, 18 Mar 2011 06:27:33 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Mar 2011 06:23:08 -0700 Date: Fri, 18 Mar 2011 18:58:24 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 2/7] mach-netlogic include directory and files Message-ID: <76a3a392f729e484cb20900d1934a0cb145a6645.1300452150.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 18 Mar 2011 13:23:08.0551 (UTC) FILETIME=[9F371970:01CBE56F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Add war.h and irq.h with XLR/XLS definitions. Signed-off-by: Jayachandran C --- arch/mips/include/asm/mach-netlogic/irq.h | 14 ++++++++++++++ arch/mips/include/asm/mach-netlogic/war.h | 26 ++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-netlogic/irq.h create mode 100644 arch/mips/include/asm/mach-netlogic/war.h diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h new file mode 100644 index 0000000..b590245 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/irq.h @@ -0,0 +1,14 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + */ +#ifndef __ASM_NETLOGIC_IRQ_H +#define __ASM_NETLOGIC_IRQ_H + +#define NR_IRQS 64 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* __ASM_NETLOGIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h new file mode 100644 index 0000000..22da893 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/war.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems. + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_NLM_WAR_H +#define __ASM_MIPS_MACH_NLM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_NLM_WAR_H */ -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Mar 18 14:29:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 14:29:56 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4556 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491882Ab1CRN1o (ORCPT ); Fri, 18 Mar 2011 14:27:44 +0100 X-TM-IMSS-Message-ID: <2f31622d0001a99f@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2f31622d0001a99f ; Fri, 18 Mar 2011 06:27:33 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Mar 2011 06:23:42 -0700 Date: Fri, 18 Mar 2011 18:58:58 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 3/7] Cache, TLB support, and feature overrides for XLR Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 18 Mar 2011 13:23:42.0332 (UTC) FILETIME=[B359ABC0:01CBE56F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips CPU_XLR case added to mm/tlbex.c CPU_XLR case added to mm/c-r4k.c for PINDEX attribute Feature overrides for XLR cpu. Signed-off-by: Jayachandran C --- .../asm/mach-netlogic/cpu-feature-overrides.h | 47 ++++++++++++++++++++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 3 files changed, 49 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h new file mode 100644 index 0000000..343926b --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011 Netlogic Microsystems + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_counter 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_icache_snoops_remote_store 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index b4923a7..1ee251f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1006,6 +1006,7 @@ static void __cpuinit probe_pcache(void) case CPU_25KF: case CPU_SB1: case CPU_SB1A: + case CPU_XLR: c->dcache.flags |= MIPS_CACHE_PINDEX; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 04f9e17..c9f9e27 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: + case CPU_XLR: uasm_i_nop(p); tlbw(p); break; -- 1.7.1 -- Jayachandran C. jayachandranc@netlogicmicro.com (Netlogic Microsystems) jchandra@freebsd.org (The FreeBSD Project) From jayachandranc@netlogicmicro.com Fri Mar 18 14:30:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Mar 2011 14:30:21 +0100 (CET) Received: from mx1.netlogicmicro.com ([12.49.93.86]:4560 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491871Ab1CRN1p (ORCPT ); Fri, 18 Mar 2011 14:27:45 +0100 X-TM-IMSS-Message-ID: <2f3166630001a9a5@netlogicmicro.com> Received: from orion8.netlogicmicro.com ([10.10.16.60]) by netlogicmicro.com ([10.10.16.19]) with ESMTP (TREND IMSS SMTP Service 7.0) id 2f3166630001a9a5 ; Fri, 18 Mar 2011 06:27:34 -0700 Received: from jayachandranc.netlogicmicro.com ([10.7.0.77]) by orion8.netlogicmicro.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Mar 2011 06:25:39 -0700 Date: Fri, 18 Mar 2011 19:00:56 +0530 From: Jayachandran C To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH 7/7] Add default configuration for XLR/XLS processors Message-ID: <8d529c891ef2a2dbe01120ef14f3252dc6e0478c.1300452150.git.jayachandranc@netlogicmicro.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 18 Mar 2011 13:25:39.0833 (UTC) FILETIME=[F962E690:01CBE56F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayachandranc@netlogicmicro.com Precedence: bulk X-list: linux-mips Enable XLR CPU support, SMP, initramfs based root filesystem etc. Signed-off-by: Jayachandran C --- arch/mips/configs/nlm_xlr_defconfig | 1698 +++++++++++++++++++++++++++++++++++ 1 files changed, 1698 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/nlm_xlr_defconfig diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig new file mode 100644 index 0000000..d1a4be6 --- /dev/null +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -0,0 +1,1698 @@ +# +# Automatically generated make config: don't edit +# Linux/mips 2.6.38 Kernel Configuration +# Fri Mar 18 16:12:16 2011 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_NLM_XLR_BOARD=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_NLM_COMMON=y +CONFIG_NLM_XLR=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYNC_R4K=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_XLR=y +CONFIG_SYS_HAS_CPU_XLR=y +CONFIG_WEAK_ORDERING=y +CONFIG_WEAK_REORDERING_BEYOND_LLSC=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_SMP=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_32=y +CONFIG_NR_CPUS=32 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_KEXEC=y +CONFIG_SECCOMP=y +# CONFIG_USE_OF is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +# CONFIG_EMBEDDED is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_VERBOSE is not set +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=m +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_IP_SET is not set +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +# CONFIG_IP_VS_PE_SIP is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +CONFIG_PHONET=m +CONFIG_IEEE802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# C