From EChew@ixiacom.com Tue Feb 1 01:41:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Feb 2011 01:41:35 +0100 (CET) Received: from ixqw-mail-out.ixiacom.com ([66.77.12.12]:26688 "EHLO ixqw-mail-out.ixiacom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491926Ab1BAAlc (ORCPT ); Tue, 1 Feb 2011 01:41:32 +0100 Received: from [10.64.33.43] (10.64.33.43) by IXCA-HC1.ixiacom.com (10.200.2.55) with Microsoft SMTP Server (TLS) id 8.1.358.0; Mon, 31 Jan 2011 16:41:25 -0800 Message-ID: <4D4756B5.4010100@ixiacom.com> Date: Mon, 31 Jan 2011 16:41:25 -0800 From: Earl Chew User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: "linux-mips@linux-mips.org" Subject: Filling in struct mips64_watch_regs from a 32 bit process Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29118 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: echew@ixiacom.com Precedence: bulk X-list: linux-mips I notice that a 32 bit process running on a 64 bit kernel is expected to know that it should fill in mips64_watch_regs --- even though it is running against a 32 bit ABI. Is this an oversight, or am I missing something ? [ That same 32 bit process must fill in mips32_watch_regs when running on a 32 bit kernel. ] In arch/mips/include/asm/ptrace.h: struct mips32_watch_regs { unsigned int watchlo[8]; ... }; and struct mips64_watch_regs { unsigned long long watchlo[8]; ... }; These are used in a union, but sizeof(mips64_watch_regs.watchlo) will not match sizeof(mips32_watch_regs.watchlo). For a 64 bit kernel, the code in arch/mips/kernel/ptrace.c reads: /* Check the values. */ for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) { __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]); #ifdef CONFIG_32BIT if (lt[i] & __UA_LIMIT) return -EINVAL; #else if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) { if (lt[i] & 0xffffffff80000000UL) return -EINVAL; } else { if (lt[i] & __UA_LIMIT) return -EINVAL; } #endif Thus for a 64 bit kernel, WATCH_STYLE is defined to be mips64, and the code goes on to obtain: addr->mips64.watchlo[i] and to verify it based on TIF_32BIT_ADDR. In other words, the 32 bit process is expected to fill in mips64_watch_regs when it is running on a 64 bit kernel, and mips32_watch_regs when it is running on a 32 bit kernel. Earl From David.Daney@caviumnetworks.com Tue Feb 1 02:03:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Feb 2011 02:03:19 +0100 (CET) Received: from [12.108.191.235] ([12.108.191.235]:17121 "EHLO mail3.caviumnetworks.com" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491926Ab1BABDQ (ORCPT ); Tue, 1 Feb 2011 02:03:16 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 31 Jan 2011 17:04:03 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 31 Jan 2011 17:03:13 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 31 Jan 2011 17:03:12 -0800 Message-ID: <4D475BCB.9050403@caviumnetworks.com> Date: Mon, 31 Jan 2011 17:03:07 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Earl Chew CC: "linux-mips@linux-mips.org" Subject: Re: Filling in struct mips64_watch_regs from a 32 bit process References: <4D4756B5.4010100@ixiacom.com> In-Reply-To: <4D4756B5.4010100@ixiacom.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Feb 2011 01:03:12.0998 (UTC) FILETIME=[CCD09060:01CBC1AB] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29119 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 01/31/2011 04:41 PM, Earl Chew wrote: > I notice that a 32 bit process running on a 64 bit kernel is expected to > know that it should fill in mips64_watch_regs --- even though it is running > against a 32 bit ABI. > > Is this an oversight, or am I missing something ? It is intentional. > > [ That same 32 bit process must fill in mips32_watch_regs when running on > a 32 bit kernel. ] > > > In arch/mips/include/asm/ptrace.h: > > struct mips32_watch_regs { > unsigned int watchlo[8]; > ... > }; > > and > > struct mips64_watch_regs { > unsigned long long watchlo[8]; > ... > }; > > These are used in a union, but sizeof(mips64_watch_regs.watchlo) will not > match sizeof(mips32_watch_regs.watchlo). > The sizes are different and thus are ... different. struct pt_watch_regs however, has a well defined size. The important thing is that the style element of struct pt_watch_regs is always in the same place. > > > For a 64 bit kernel, the code in arch/mips/kernel/ptrace.c reads: > > > /* Check the values. */ > for (i = 0; i< current_cpu_data.watch_reg_use_cnt; i++) { > __get_user(lt[i],&addr->WATCH_STYLE.watchlo[i]); > #ifdef CONFIG_32BIT > if (lt[i]& __UA_LIMIT) > return -EINVAL; > #else > if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) { > if (lt[i]& 0xffffffff80000000UL) > return -EINVAL; > } else { > if (lt[i]& __UA_LIMIT) > return -EINVAL; > } > #endif > > > Thus for a 64 bit kernel, WATCH_STYLE is defined to be mips64, and the code > goes on to obtain: > > addr->mips64.watchlo[i] > > and to verify it based on TIF_32BIT_ADDR. > > > In other words, the 32 bit process is expected to fill in mips64_watch_regs > when it is running on a 64 bit kernel, and mips32_watch_regs when it is running > on a 32 bit kernel. > Yes. The debugging agent must check struct pt_watch_regs style to determine which type of watch registers the hardware is using. Take a look at how GDB handles this in mips-linux-nat.c. David Daney From EChew@ixiacom.com Tue Feb 1 02:12:36 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Feb 2011 02:12:38 +0100 (CET) Received: from ixqw-mail-out.ixiacom.com ([66.77.12.12]:28764 "EHLO ixqw-mail-out.ixiacom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491926Ab1BABMf (ORCPT ); Tue, 1 Feb 2011 02:12:35 +0100 Received: from [10.64.33.43] (10.64.33.43) by IXCA-HC1.ixiacom.com (10.200.2.55) with Microsoft SMTP Server (TLS) id 8.1.358.0; Mon, 31 Jan 2011 17:12:28 -0800 Message-ID: <4D475DFC.1040401@ixiacom.com> Date: Mon, 31 Jan 2011 17:12:28 -0800 From: Earl Chew User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: David Daney CC: "linux-mips@linux-mips.org" Subject: Re: Filling in struct mips64_watch_regs from a 32 bit process References: <4D4756B5.4010100@ixiacom.com> <4D475BCB.9050403@caviumnetworks.com> In-Reply-To: <4D475BCB.9050403@caviumnetworks.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29120 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: echew@ixiacom.com Precedence: bulk X-list: linux-mips >> I notice that a 32 bit process running on a 64 bit kernel is expected to >> know that it should fill in mips64_watch_regs --- even though it is running >> against a 32 bit ABI. >> >> Is this an oversight, or am I missing something ? > > It is intentional. Oh I see ... I have to call PTRACE_SET_WATCH_REGS first in order to figure out whether the kernel is expecting me to use pt_watch_style_mips32 or pt_watch_style_mips64. Thanks. Earl From David.Daney@caviumnetworks.com Tue Feb 1 02:24:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Feb 2011 02:25:00 +0100 (CET) Received: from [12.108.191.235] ([12.108.191.235]:17486 "EHLO mail3.caviumnetworks.com" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491926Ab1BABY5 (ORCPT ); Tue, 1 Feb 2011 02:24:57 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 31 Jan 2011 17:25:45 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 31 Jan 2011 17:24:55 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 31 Jan 2011 17:24:55 -0800 Message-ID: <4D4760E1.9000400@caviumnetworks.com> Date: Mon, 31 Jan 2011 17:24:49 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Earl Chew CC: "linux-mips@linux-mips.org" Subject: Re: Filling in struct mips64_watch_regs from a 32 bit process References: <4D4756B5.4010100@ixiacom.com> <4D475BCB.9050403@caviumnetworks.com> <4D475DFC.1040401@ixiacom.com> In-Reply-To: <4D475DFC.1040401@ixiacom.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Feb 2011 01:24:55.0194 (UTC) FILETIME=[D4FBE7A0:01CBC1AE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29121 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 01/31/2011 05:12 PM, Earl Chew wrote: >>> I notice that a 32 bit process running on a 64 bit kernel is expected to >>> know that it should fill in mips64_watch_regs --- even though it is running >>> against a 32 bit ABI. >>> >>> Is this an oversight, or am I missing something ? >> >> It is intentional. > > Oh I see ... I have to call PTRACE_SET_WATCH_REGS first in order to figure > out whether the kernel is expecting me to use pt_watch_style_mips32 or > pt_watch_style_mips64. > That would be PTRACE_GET_WATCH_REGS. It will tell you the width of the registers as well as how many are available (in the num_valid field) and the properties of each (in the watch_masks[] fields). Fill in watchlo[] and watchhi[], write them back with PTRACE_SET_WATCH_REGS, then sit back and wait for SIGTRAP. David Daney From EChew@ixiacom.com Tue Feb 1 02:26:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Feb 2011 02:26:25 +0100 (CET) Received: from ixqw-mail-out.ixiacom.com ([66.77.12.12]:29516 "EHLO ixqw-mail-out.ixiacom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491926Ab1BAB0W (ORCPT ); Tue, 1 Feb 2011 02:26:22 +0100 Received: from [10.64.33.43] (10.64.33.43) by IXCA-HC1.ixiacom.com (10.200.2.55) with Microsoft SMTP Server (TLS) id 8.1.358.0; Mon, 31 Jan 2011 17:26:16 -0800 Message-ID: <4D476137.8050108@ixiacom.com> Date: Mon, 31 Jan 2011 17:26:15 -0800 From: Earl Chew User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: David Daney CC: "linux-mips@linux-mips.org" Subject: Re: Filling in struct mips64_watch_regs from a 32 bit process References: <4D4756B5.4010100@ixiacom.com> <4D475BCB.9050403@caviumnetworks.com> <4D475DFC.1040401@ixiacom.com> <4D4760E1.9000400@caviumnetworks.com> In-Reply-To: <4D4760E1.9000400@caviumnetworks.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29122 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: echew@ixiacom.com Precedence: bulk X-list: linux-mips > That would be PTRACE_GET_WATCH_REGS. Yes, that's what I thought I typed :-( Earl From yad.naveen@gmail.com Fri Feb 4 04:24:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Feb 2011 04:24:51 +0100 (CET) Received: from mail-qw0-f49.google.com ([209.85.216.49]:55553 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490961Ab1BDDYr convert rfc822-to-8bit (ORCPT ); Fri, 4 Feb 2011 04:24:47 +0100 Received: by qwj9 with SMTP id 9so1461958qwj.36 for ; Thu, 03 Feb 2011 19:24:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=0ANHv8SJTJXJNAToirr7L5FRoJx+b9m/H+fREj0Xl3o=; b=aK3wQJo/tOTMiYe1q9j+BTMwLrhbrJvUCIUMjxwgRspegH547b7WcuH4Zxb1iEvqsq p+DEyBUy7dJNFI+M4DWxPXHEIq23jfJWcHRTOojWFM/4KQqyDAjKRpZF7zB/ZtAHR69Q Tv9d6qDUnFhlXY8JOwqVeIWNYXJi09JzckDFE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Lt17TyrU8MyYowcZezakovfORvKROmxPPV9JNGq41rpVVbuFvOcUDc2w5ecGH+k8Wp Po2lXqqGV3D1xHP8IOgq5WcUfXoOMoTKzscorsGrnCerENb0irgcFP0UCjzzZrDKizGi xD2i7WzU8EwJmUZYyxMJOJMFgC5R3fgFmhLHs= MIME-Version: 1.0 Received: by 10.229.235.201 with SMTP id kh9mr9744448qcb.240.1296789881588; Thu, 03 Feb 2011 19:24:41 -0800 (PST) Received: by 10.229.98.5 with HTTP; Thu, 3 Feb 2011 19:24:41 -0800 (PST) In-Reply-To: <20110131130820.GB26217@linux-mips.org> References: <4D3DCB5A.6060107@caviumnetworks.com> <20110131130820.GB26217@linux-mips.org> Date: Fri, 4 Feb 2011 08:54:41 +0530 Message-ID: Subject: Re: page size change on MIPS From: naveen yadav To: Ralf Baechle Cc: Himanshu Aggarwal , David Daney , kernelnewbies@nl.linux.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29123 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips thanaks a lot for your suggestion .. I debug this issue further, and here is my observations: 1. If I replace init with simple static link executable binary, this can be executed. 2. In case of busy-box, I debug the reason why init fails to excute. When I execute init command from busybox the control goes in main() function of busybox(appletlib.c) with argv value as the command you are suppose to execute, which in our case is init. But when i check argv is coming null when page size is 64KB and it comes init when page size is 16KB. This behaviour is very strange and i am still debugging this issue. I have check in Glibc, the max_page size it support is 64 KB in codesourcercy toolchain 4.4.1 How can I check alignment issue as mention by Mr. Ralf Baechle. Kind regards On Mon, Jan 31, 2011 at 6:38 PM, Ralf Baechle wrote: > On Sun, Jan 30, 2011 at 08:32:43PM +0530, Himanshu Aggarwal wrote: > >> Why should the application or the toolchains depend on pagesize? I am >> not very clear on this. Can someone explain it? > > To allow loading directly with mmap the executable file's layout must > be such that it's it's segments are on offsets that are a multiple of > the page size so in turn the linker must know that alignment. > >  Ralf > From yad.naveen@gmail.com Fri Feb 4 05:16:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Feb 2011 05:16:38 +0100 (CET) Received: from mail-qy0-f170.google.com ([209.85.216.170]:52708 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491028Ab1BDEQf convert rfc822-to-8bit (ORCPT ); Fri, 4 Feb 2011 05:16:35 +0100 Received: by qyk10 with SMTP id 10so8180378qyk.15 for ; Thu, 03 Feb 2011 20:16:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Y1bdS1MWuKnnmTDKUjWKv6OzOYsZ85uJbNlWYXsaYPg=; b=BLNdhHqCBMP69M9HFQUyqT0/v4GB2CZurytC5964NF7YmP6J5TmHDHRh9CKw+CsFlM Axyc2z9im7sKudKA4dzw6+IYKPpzxXhOQSfol40rvQwxaTLiaGB+AIAyQJdXaBfA7LGz GzwuOjOCf+kD6LPv9gr6VZjy0limoCU/UYpFA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=dxVbclfeastaYFjUsOAzAO2oeyT71ZLkZLaRDkNiONmvnMnA9mjFSnAF7OqKOZQbtM ukqsEyO2NzuZ0GnSgzdnfcmZyt6JFoBnmSv0XWb0nQebiAgTPYhFPKAh3EQIXrYPm7Jh UH0tOukUKHrXKbzYyOavVXehLJyoOPFHrDpaM= MIME-Version: 1.0 Received: by 10.229.223.195 with SMTP id il3mr8020136qcb.278.1296792987110; Thu, 03 Feb 2011 20:16:27 -0800 (PST) Received: by 10.229.98.5 with HTTP; Thu, 3 Feb 2011 20:16:27 -0800 (PST) In-Reply-To: References: <4D3DCB5A.6060107@caviumnetworks.com> <20110131130820.GB26217@linux-mips.org> Date: Fri, 4 Feb 2011 09:46:27 +0530 Message-ID: Subject: Re: page size change on MIPS From: naveen yadav To: Ralf Baechle Cc: Himanshu Aggarwal , David Daney , kernelnewbies@nl.linux.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29124 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Hi, I am adding readelf info also . mips-linux-gnu-readelf -S squashfs-root/bin/busybox There are 35 section headers, starting at offset 0x174290: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .note.ABI-tag NOTE 004000d4 0000d4 000020 00 A 0 0 4 [ 2] .reginfo MIPS_REGINFO 004000f4 0000f4 000018 18 A 0 0 4 [ 3] .rel.dyn REL 0040010c 00010c 000010 08 A 0 0 4 [ 4] .init PROGBITS 0040011c 00011c 00005c 00 AX 0 0 4 [ 5] .text PROGBITS 00400180 000180 11d2b0 00 AX 0 0 16 [ 6] __libc_freeres_fn PROGBITS 0051d430 11d430 001368 00 AX 0 0 4 [ 7] __libc_thread_fre PROGBITS 0051e798 11e798 000148 00 AX 0 0 4 [ 8] .fini PROGBITS 0051e8e0 11e8e0 000034 00 AX 0 0 4 [ 9] .rodata PROGBITS 0051e920 11e920 02d560 00 A 0 0 16 [10] __libc_subfreeres PROGBITS 0054be80 14be80 000058 00 A 0 0 4 [11] __libc_atexit PROGBITS 0054bed8 14bed8 000004 00 A 0 0 4 [12] __libc_thread_sub PROGBITS 0054bedc 14bedc 000008 00 A 0 0 4 [13] .gcc_except_table PROGBITS 0054bee4 14bee4 0001fb 00 A 0 0 1 [14] .eh_frame PROGBITS 0055c0e0 14c0e0 002464 00 WA 0 0 4 [15] .tdata PROGBITS 0055e544 14e544 000018 00 WAT 0 0 4 [16] .tbss NOBITS 0055e55c 14e55c 000034 00 WAT 0 0 4 [17] .ctors PROGBITS 0055e55c 14e55c 000008 00 WA 0 0 4 [18] .dtors PROGBITS 0055e564 14e564 00000c 00 WA 0 0 4 [19] .jcr PROGBITS 0055e570 14e570 000004 00 WA 0 0 4 [20] .data.rel.ro PROGBITS 0055e574 14e574 000030 00 WA 0 0 4 [21] .data PROGBITS 0055e5b0 14e5b0 000b30 00 WA 0 0 16 [22] .got PROGBITS 0055f0e0 14f0e0 000148 04 WAp 0 0 16 [23] .sdata PROGBITS 0055f228 14f228 000004 00 WAp 0 0 4 [24] .sbss NOBITS 0055f230 14f22c 000184 00 WAp 0 0 8 [25] .bss NOBITS 0055f3c0 14f22c 00516c 00 WA 0 0 16 [26] __libc_freeres_pt NOBITS 0056452c 14f22c 000040 00 WA 0 0 4 [27] .pdr PROGBITS 00000000 14f22c 016880 00 0 0 4 [28] .comment PROGBITS 00000000 165aac 0027e0 00 0 0 1 [29] .debug_frame MIPS_DWARF 00000000 16828c 00be88 00 0 0 4 [30] .gnu.attributes LOOS+ffffff5 00000000 174114 000010 00 0 0 1 [31] .mdebug.abi32 PROGBITS 000030c0 174124 000000 00 0 0 1 [32] .shstrtab STRTAB 00000000 174124 00016c 00 0 0 1 [33] .symtab SYMTAB 00000000 174808 015320 10 34 2843 4 [34] .strtab STRTAB 00000000 189b28 012f65 00 0 0 1 Key to Flags: W (write), A (alloc), X (execute), M (merge), S (strings) I (info), L (link order), G (group), x (unknown) O (extra OS processing required) o (OS specific), p (processor specific) On Fri, Feb 4, 2011 at 8:54 AM, naveen yadav wrote: > thanaks a lot for your suggestion .. > > > I debug this issue further, and here is my observations: > > 1. If I replace init with simple static link executable binary, this > can be executed. > 2. In case of busy-box, I debug the reason why init fails to excute. > > When I execute init command from busybox the control goes in main() > function of busybox(appletlib.c) with argv value > as the command you are suppose to execute, which in our case is init. > > But when i check argv is coming null when page size is 64KB and it > comes init when page size is 16KB. > > This behaviour is very strange and i am still debugging this issue. > > > I have check in Glibc, the max_page size it support is 64 KB in > codesourcercy toolchain 4.4.1 > > How can I check alignment issue as mention by Mr. Ralf Baechle. > > > > Kind regards > > > > > On Mon, Jan 31, 2011 at 6:38 PM, Ralf Baechle wrote: >> On Sun, Jan 30, 2011 at 08:32:43PM +0530, Himanshu Aggarwal wrote: >> >>> Why should the application or the toolchains depend on pagesize? I am >>> not very clear on this. Can someone explain it? >> >> To allow loading directly with mmap the executable file's layout must >> be such that it's it's segments are on offsets that are a multiple of >> the page size so in turn the linker must know that alignment. >> >>  Ralf >> > From David.Daney@caviumnetworks.com Fri Feb 4 18:25:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Feb 2011 18:25:26 +0100 (CET) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:11210 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491179Ab1BDRZS (ORCPT ); Fri, 4 Feb 2011 18:25:18 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by smtp2.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Feb 2011 12:25:22 -0500 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Feb 2011 09:25:11 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 4 Feb 2011 09:25:11 -0800 Message-ID: <4D4C3676.50802@caviumnetworks.com> Date: Fri, 04 Feb 2011 09:25:10 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: naveen yadav CC: Ralf Baechle , Himanshu Aggarwal , kernelnewbies@nl.linux.org, linux-mips@linux-mips.org Subject: Re: page size change on MIPS References: <4D3DCB5A.6060107@caviumnetworks.com> <20110131130820.GB26217@linux-mips.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 04 Feb 2011 17:25:11.0159 (UTC) FILETIME=[7A03B870:01CBC490] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29125 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/03/2011 08:16 PM, naveen yadav wrote: > Hi, I am adding readelf info also . > > mips-linux-gnu-readelf -S squashfs-root/bin/busybox > There are 35 section headers, starting at offset 0x174290: > Section headers are not relevant to any of this. You need to look at the program headers. Try 'readelf -l' David Daney [...] >> >> >> On Mon, Jan 31, 2011 at 6:38 PM, Ralf Baechle wrote: >>> On Sun, Jan 30, 2011 at 08:32:43PM +0530, Himanshu Aggarwal wrote: >>> >>>> Why should the application or the toolchains depend on pagesize? I am >>>> not very clear on this. Can someone explain it? >>> >>> To allow loading directly with mmap the executable file's layout must >>> be such that it's it's segments are on offsets that are a multiple of >>> the page size so in turn the linker must know that alignment. >>> >>> Ralf >>> >> > From greg@kroah.com Fri Feb 4 20:59:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Feb 2011 20:59:19 +0100 (CET) Received: from kroah.org ([198.145.64.141]:39905 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491179Ab1BDT7O (ORCPT ); Fri, 4 Feb 2011 20:59:14 +0100 Received: from localhost (c-71-227-141-191.hsd1.wa.comcast.net [71.227.141.191]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id 92EAF486CE; Fri, 4 Feb 2011 11:59:09 -0800 (PST) Date: Fri, 4 Feb 2011 11:56:24 -0800 From: Greg KH To: "Anoop P.A" Cc: gregkh@suse.de, dbrownell@users.sourceforge.net, ust@denx.de, pkondeti@codeaurora.org, stern@rowland.harvard.edu, gadiyar@ti.com, alek.du@intel.com, jacob.jun.pan@intel.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v3] EHCI bus glue for on-chip PMC MSP USB controller. Message-ID: <20110204195624.GA27680@kroah.com> References: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29126 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: greg@kroah.com Precedence: bulk X-list: linux-mips On Thu, Jan 27, 2011 at 04:58:56PM +0530, Anoop P.A wrote: > From: Anoop P A > > Signed-off-by: Anoop P A > Tested-by: Shane McDonald Care to provide a "real" changelog comment for this patch? We need something here. > --- > drivers/usb/host/Kconfig | 15 +- > drivers/usb/host/ehci-hcd.c | 7 + > drivers/usb/host/ehci-pmcmsp.c | 552 ++++++++++++++++++++++++++++++++++++++++ > drivers/usb/host/ehci.h | 3 + > 4 files changed, 575 insertions(+), 2 deletions(-) > create mode 100644 drivers/usb/host/ehci-pmcmsp.c > > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig > index 24046c0..1f73127 100644 > --- a/drivers/usb/host/Kconfig > +++ b/drivers/usb/host/Kconfig > @@ -91,17 +91,28 @@ config USB_EHCI_TT_NEWSCHED > > If unsure, say Y. > > +config USB_EHCI_HCD_PMC_MSP > + tristate "EHCI support for on-chip PMC MSP USB controller" > + depends on USB_EHCI_HCD && MSP_HAS_USB > + default y > + select USB_EHCI_BIG_ENDIAN_DESC > + select USB_EHCI_BIG_ENDIAN_MMIO > + ---help--- > + Enables support for the onchip USB controller on the PMC_MSP7100 Family SoC's. > + If unsure, say N. > + > config USB_EHCI_BIG_ENDIAN_MMIO > bool > depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ > ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ > - PPC_MPC512x || CPU_CAVIUM_OCTEON) > + PPC_MPC512x || CPU_CAVIUM_OCTEON || \ > + PMC_MSP) > default y > > config USB_EHCI_BIG_ENDIAN_DESC > bool > depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ > - PPC_MPC512x) > + PPC_MPC512x || PMC_MSP) > default y > > config XPS_USB_HCD_XILINX > diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c > index 6fee3cd..a591890 100644 > --- a/drivers/usb/host/ehci-hcd.c > +++ b/drivers/usb/host/ehci-hcd.c > @@ -262,6 +262,8 @@ static void tdi_reset (struct ehci_hcd *ehci) > if (ehci_big_endian_mmio(ehci)) > tmp |= USBMODE_BE; > ehci_writel(ehci, tmp, reg_ptr); > + if (ehci->pmc_msp_tdi) > + usb_hcd_tdi_set_mode(ehci); > } > > /* reset a non-running (STS_HALT == 1) controller */ > @@ -1249,6 +1251,11 @@ MODULE_LICENSE ("GPL"); > #define PLATFORM_DRIVER ehci_msm_driver > #endif > > +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP > +#include "ehci-pmcmsp.c" > +#define PLATFORM_DRIVER ehci_hcd_msp_driver > +#endif > + > #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ > !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ > !defined(XILINX_OF_PLATFORM_DRIVER) > diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c > new file mode 100644 > index 0000000..28dd26c > --- /dev/null > +++ b/drivers/usb/host/ehci-pmcmsp.c > @@ -0,0 +1,552 @@ > +/* > + * PMC MSP EHCI (Host Controller Driver) for USB. > + * > + * (C) Copyright 2006-2010 PMC-Sierra Inc > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. Are you sure about "any later version"? Is this acceptable to your company lawyers? > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. These two paragraphs are not needed, please remove them. > + */ > + > +#include > +#include > +#include > + > +/* includes */ Um, includes for what? Are we writing comments for the previous lines? > +#define USB_CTRL_MODE_HOST 0x3 > + /* host mode */ > +#define USB_CTRL_MODE_BIG_ENDIAN 0x4 > + /* big endian */ > +#define USB_CTRL_MODE_STREAM_DISABLE 0x10 > + /* stream disable*/ > +#define USB_CTRL_FIFO_THRESH 0x00300000 > + /* thresh hold */ > +#define USB_EHCI_REG_USB_MODE 0x68 > + /* register offset for usb_mode */ > +#define USB_EHCI_REG_USB_FIFO 0x24 > + /* register offset for usb fifo */ > +#define USB_EHCI_REG_USB_STATUS 0x44 > + /* register offset for usb status */ > +#define USB_EHCI_REG_BIT_STAT_STS (1<<29) > + /* serial/parallel transceiver */ > +#define MSP_PIN_USB0_HOST_DEV 49 > + /* TWI USB0 host device pin */ > +#define MSP_PIN_USB1_HOST_DEV 50 > + /* TWI USB1 host device pin */ Ok, I see we are. That's horrible, please fix it up. > + > +extern int usb_disabled(void); Why is this in a .c file? externs should never be in a .c file. > + > +void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) > +{ > + u8 *base; > + u8 *statreg; > + u8 *fiforeg; > + u32 val; > + struct ehci_regs *reg_base = ehci->regs; > + > + /* get register base */ > + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; > + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; > + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; > + > + /* set the controller to host mode and BIG ENDIAN */ > + ehci_writel(ehci, (USB_CTRL_MODE_HOST | USB_CTRL_MODE_BIG_ENDIAN > + | USB_CTRL_MODE_STREAM_DISABLE), (u32 *)base); > + > + /* clear STS to select parallel transceiver interface */ > + val = ehci_readl(ehci, (u32 *)statreg); > + val = val & ~USB_EHCI_REG_BIT_STAT_STS; > + ehci_writel(ehci, val, (u32 *)statreg); > + > + /* write to set the proper fifo threshold */ > + ehci_writel(ehci, USB_CTRL_FIFO_THRESH, (u32 *)fiforeg); > + > + /* set TWI GPIO USB_HOST_DEV pin high */ > + gpio_direction_output(MSP_PIN_USB0_HOST_DEV, 1); > +#ifdef CONFIG_MSP_HAS_DUAL_USB > + gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1); > +#endif Please don't put #defines in .c files. > +} > + > +/* called after powerup, by probe or system-pm "wakeup" */ > +static int ehci_msp_reinit(struct ehci_hcd *ehci) > +{ > + ehci_port_power(ehci, 0); > + > + return 0; > +} > + > +/* called during probe() after chip reset completes */ > +static int ehci_msp_setup(struct usb_hcd *hcd) > +{ > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + u32 temp; > + int retval; > + ehci->big_endian_mmio = 1; > + ehci->big_endian_desc = 1; > + ehci->pmc_msp_tdi = 1; > + > + ehci->caps = hcd->regs; > + ehci->regs = hcd->regs + > + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); > + dbg_hcs_params(ehci, "reset"); > + dbg_hcc_params(ehci, "reset"); > + > + /* cache this readonly data; minimize chip reads */ > + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); > + hcd->has_tt = 1; > + tdi_reset(ehci); > + > + retval = ehci_halt(ehci); > + if (retval) > + return retval; > + > + ehci_reset(ehci); > + > + /* data structure init */ > + retval = ehci_init(hcd); > + if (retval) > + return retval; > + > + temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); > + temp &= 0x0f; > + if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { > + ehci_dbg(ehci, "bogus port configuration: " > + "cc=%d x pcc=%d < ports=%d\n", > + HCS_N_CC(ehci->hcs_params), > + HCS_N_PCC(ehci->hcs_params), > + HCS_N_PORTS(ehci->hcs_params)); > + } > + > + retval = ehci_msp_reinit(ehci); > + > + return retval; > +} > + > +/*-------------------------------------------------------------------------*/ > + > +static void msp_start_hc(struct platform_device *dev) > +{ > + printk(KERN_DEBUG __FILE__ > + ": starting PMC MSP EHCI USB Controller\n"); Why? Who really cares? And, if you _really_ want to do this, please use a dev_dbg() call instead, which ties it properly into the dynamic printk system _and_ properly identifies this deivce. > + > + /* > + * Now, carefully enable the USB clock, and take > + * the USB host controller out of reset. > + */ > + printk(KERN_DEBUG __FILE__ > + ": Clock to USB host has been enabled\n"); > +} You never enabled anything, yet you said you did? Somethings wrong here. > + > +static void msp_stop_hc(struct platform_device *dev) > +{ > + printk(KERN_DEBUG __FILE__ > + ": stopping PMC MSP EHCI USB Controller\n"); > +} Same for this printk, you didn't stop anything. Also fix it up and don't use printk, see above. > + > + > +/*-------------------------------------------------------------------------*/ > + > +/*-------------------------------------------------------------------------*/ > + > +#ifdef CONFIG_PM > + > +/* suspend/resume, section 4.3 */ > + > +/* These routines rely on the bus glue > + * to handle powerdown and wakeup, and currently also on > + * transceivers that don't need any software attention to set up > + * the right sort of wakeup. > + * Also they depend on separate root hub suspend/resume. > + */ > +static int ehci_msp_suspend(struct device *dev) > +{ > + struct usb_hcd *hcd = dev_get_drvdata(dev); > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + unsigned long flags; > + int rc; > + > + return 0; > + rc = 0; > + > + if (time_before(jiffies, ehci->next_statechange)) > + msleep(10); Short sleep, why? > + > + /* Root hub was already suspended. Disable irq emission and > + * mark HW unaccessible. The PM and USB cores make sure that > + * the root hub is either suspended or stopped. > + */ > + spin_lock_irqsave(&ehci->lock, flags); > + ehci_prepare_ports_for_controller_suspend(ehci, device_may_wakeup(dev)); > + ehci_writel(ehci, 0, &ehci->regs->intr_enable); > + (void)ehci_readl(ehci, &ehci->regs->intr_enable); > + > + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); > + spin_unlock_irqrestore(&ehci->lock, flags); > + > + /* could save FLADJ in case of Vaux power loss > + ... we'd only use it to handle clock skew */ Huh? > + > + return rc; > +} > + > +static int ehci_msp_resume(struct device *dev) > +{ > + struct usb_hcd *hcd = dev_get_drvdata(dev); > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + > + > + /* maybe restore FLADJ */ Don't you know? > + > + if (time_before(jiffies, ehci->next_statechange)) > + msleep(100); That's a long sleep, are you sure that's ok on the resume path? > + > + /* Mark hardware accessible again as we are out of D3 state by now */ > + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); > + > + /* If CF is still set, we maintained PCI Vaux power. > + * Just undo the effect of ehci_pci_suspend(). > + */ > + if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) { > + int mask = INTR_MASK; > + > + ehci_prepare_ports_for_controller_resume(ehci); > + if (!hcd->self.root_hub->do_remote_wakeup) > + mask &= ~STS_PCD; > + ehci_writel(ehci, mask, &ehci->regs->intr_enable); > + ehci_readl(ehci, &ehci->regs->intr_enable); > + return 0; > + } > + > + ehci_dbg(ehci, "lost power, restarting\n"); > + usb_root_hub_lost_power(hcd->self.root_hub); > + > + /* Else reset, to cope with power loss or flush-to-storage > + * style "resume" having let BIOS kick in during reboot. > + */ > + (void) ehci_halt(ehci); > + (void) ehci_reset(ehci); > + (void) ehci_msp_reinit(ehci); > + > + /* emptying the schedule aborts any urbs */ > + spin_lock_irq(&ehci->lock); > + if (ehci->reclaim) > + end_unlink_async(ehci); > + ehci_work(ehci); > + spin_unlock_irq(&ehci->lock); > + > + ehci_writel(ehci, ehci->command, &ehci->regs->command); > + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); > + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ > + > + /* here we "know" root ports should always stay powered */ > + ehci_port_power(ehci, 1); > + > + hcd->state = HC_STATE_SUSPENDED; > + > + return 0; > +} > + > +static const struct dev_pm_ops ehci_msp_pmops = { > + .suspend = ehci_msp_suspend, > + .resume = ehci_msp_resume, > +}; > +#endif > + > + > +/* configure so an HC device and id are always provided */ > +/* always called with process context; sleeping is OK */ > + > +static int usb_hcd_msp_map_regs(struct mspusb_device *dev) > +{ > + struct resource *res; > + struct platform_device *pdev = &dev->dev; > + u32 res_len; > + int retval; > + > + /* MAB register space */ > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > + if (res == NULL) > + return -ENOMEM; > + res_len = res->end - res->start + 1; > + if (!request_mem_region(res->start, res_len, "mab regs")) > + return -EBUSY; > + > + dev->mab_regs = ioremap_nocache(res->start, res_len); > + if (dev->mab_regs == NULL) { > + retval = -ENOMEM; > + goto err1; > + } > + > + /* MSP USB register space */ > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > + if (res == NULL) { > + retval = -ENOMEM; > + goto err2; > + } > + res_len = res->end - res->start + 1; > + if (!request_mem_region(res->start, res_len, "usbid regs")) { > + retval = -EBUSY; > + goto err2; > + } > + dev->usbid_regs = ioremap_nocache(res->start, res_len); > + if (dev->usbid_regs == NULL) { > + retval = -ENOMEM; > + goto err3; > + } > + > + return 0; > +err3: > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > + res_len = res->end - res->start + 1; > + release_mem_region(res->start, res_len); > +err2: > + iounmap(dev->mab_regs); > +err1: > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > + res_len = res->end - res->start + 1; > + release_mem_region(res->start, res_len); > + dev_err(&pdev->dev, "Failed to map non-EHCI regs.\n"); > + return retval; > +} > + > +/** > + * usb_hcd_msp_probe - initialize PMC MSP-based HCDs > + * Context: !in_interrupt() > + * > + * Allocates basic resources for this USB host controller, and > + * then invokes the start() method for the HCD associated with it > + * through the hotplug entry's driver_data. > + * > + */ > +int usb_hcd_msp_probe(const struct hc_driver *driver, > + struct platform_device *dev) > +{ > + int retval; > + struct usb_hcd *hcd; > + struct resource *res; > + struct ehci_hcd *ehci ; > + > + hcd = usb_create_hcd(driver, &dev->dev, "pmcmsp"); > + if (!hcd) > + return -ENOMEM; > + > + res = platform_get_resource(dev, IORESOURCE_MEM, 0); > + if (res == NULL) { > + pr_debug("No IOMEM resource info for %s.\n", dev->name); > + retval = -ENOMEM; > + goto err1; > + } > + hcd->rsrc_start = res->start; > + hcd->rsrc_len = res->end - res->start + 1; > + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, dev->name)) { > + retval = -EBUSY; > + goto err1; > + } > + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); > + if (!hcd->regs) { > + pr_debug("ioremap failed"); > + retval = -ENOMEM; > + goto err2; > + } > + msp_start_hc(dev); > + > + res = platform_get_resource(dev, IORESOURCE_IRQ, 0); > + if (res == NULL) { > + dev_err(&dev->dev, "No IRQ resource info for %s.\n", dev->name); > + retval = -ENOMEM; > + goto err3; > + } > + > + /* Map non-EHCI register spaces */ > + retval = usb_hcd_msp_map_regs(to_mspusb_device(dev)); > + if (retval != 0) > + goto err3; > + > + ehci = hcd_to_ehci(hcd); > + ehci->big_endian_mmio = 1; > + ehci->big_endian_desc = 1; > + > + > + retval = usb_add_hcd(hcd, res->start, IRQF_SHARED); > + if (retval == 0) > + return 0; > + > + usb_remove_hcd(hcd); > +err3: > + msp_stop_hc(dev); > + iounmap(hcd->regs); > +err2: > + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); > +err1: > + usb_put_hcd(hcd); > + > + return retval; > +} > + > + > +/* may be called without controller electrically present */ > +/* may be called with controller, bus, and devices active */ > + What may be called? > +/** > + * usb_hcd_msp_remove - shutdown processing for PMC MSP-based HCDs > + * @dev: USB Host Controller being removed > + * Context: !in_interrupt() > + * > + * Reverses the effect of usb_hcd_msp_probe(), first invoking > + * the HCD's stop() method. It is always called from a thread > + * context, normally "rmmod", "apmd", or something similar. > + * > + */ > +void usb_hcd_msp_remove(struct usb_hcd *hcd, struct platform_device *dev) > +{ > + usb_remove_hcd(hcd); > + msp_stop_hc(dev); > + iounmap(hcd->regs); > + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); > + usb_put_hcd(hcd); > +} > + > +#ifdef CONFIG_MSP_HAS_DUAL_USB > +/*-------------------------------------------------------------------------*/ > +/* > + * Wrapper around the main ehci_irq. Since both USB host controllers are > + * sharing the same IRQ, need to first determine whether we're the intended > + * recipient of this interrupt. > + */ > +static irqreturn_t ehci_msp_irq(struct usb_hcd *hcd) > +{ > + u32 int_src; > + struct device *dev = hcd->self.controller; > + struct platform_device *pdev; > + struct mspusb_device *mdev; > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + > + /* need to reverse-map a couple of containers to get our device */ > + pdev = to_platform_device(dev); > + mdev = to_mspusb_device(pdev); > + > + /* Check to see if this interrupt is for this host controller */ > + int_src = ehci_readl(ehci, &mdev->mab_regs->int_stat); > + if (int_src & (1 << pdev->id)) > + return ehci_irq(hcd); > + > + /* Not for this device */ > + return IRQ_NONE; > +} > +/*-------------------------------------------------------------------------*/ > +#endif /* DUAL_USB */ > + > +static const struct hc_driver ehci_msp_hc_driver = { > + .description = hcd_name, > + .product_desc = "PMC MSP EHCI", > + .hcd_priv_size = sizeof(struct ehci_hcd), > + > + /* > + * generic hardware linkage > + */ > +#ifdef CONFIG_MSP_HAS_DUAL_USB > + .irq = ehci_msp_irq, > +#else > + .irq = ehci_irq, > +#endif > + .flags = HCD_MEMORY | HCD_USB2, > + > + /* > + * basic lifecycle operations > + */ > + .reset = ehci_msp_setup, > + .start = ehci_run, > + .shutdown = ehci_shutdown, > + .start = ehci_run, > + .stop = ehci_stop, > + > + /* > + * managing i/o requests and associated device resources > + */ > + .urb_enqueue = ehci_urb_enqueue, > + .urb_dequeue = ehci_urb_dequeue, > + .endpoint_disable = ehci_endpoint_disable, > + .endpoint_reset = ehci_endpoint_reset, > + > + /* > + * scheduling support > + */ > + .get_frame_number = ehci_get_frame, > + > + /* > + * root hub support > + */ > + .hub_status_data = ehci_hub_status_data, > + .hub_control = ehci_hub_control, > + .bus_suspend = ehci_bus_suspend, > + .bus_resume = ehci_bus_resume, > + .relinquish_port = ehci_relinquish_port, > + .port_handed_over = ehci_port_handed_over, > + > + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, > +}; > + > +static int ehci_hcd_msp_drv_probe(struct platform_device *pdev) > +{ > + int ret; > + > + pr_debug("In ehci_hcd_msp_drv_probe"); > + > + if (usb_disabled()) > + return -ENODEV; > + > + gpio_request(MSP_PIN_USB0_HOST_DEV, "USB0_HOST_DEV_GPIO"); > +#ifdef CONFIG_MSP_HAS_DUAL_USB > + gpio_request(MSP_PIN_USB1_HOST_DEV, "USB1_HOST_DEV_GPIO"); > +#endif > + > + ret = usb_hcd_msp_probe(&ehci_msp_hc_driver, pdev); > + > + return ret; > +} > + > +static int ehci_hcd_msp_drv_remove(struct platform_device *pdev) > +{ > + struct usb_hcd *hcd = platform_get_drvdata(pdev); > + > + usb_hcd_msp_remove(hcd, pdev); > + > + /* free TWI GPIO USB_HOST_DEV pin */ > + gpio_free(MSP_PIN_USB0_HOST_DEV); > +#ifdef CONFIG_MSP_HAS_DUAL_USB > + gpio_free(MSP_PIN_USB1_HOST_DEV); > +#endif > + > + return 0; > +} > + > +MODULE_ALIAS("pmcmsp-ehci"); > + > +static struct platform_driver ehci_hcd_msp_driver = { > + .probe = ehci_hcd_msp_drv_probe, > + .remove = ehci_hcd_msp_drv_remove, > + .driver = { > + .name = "pmcmsp-ehci", > + .owner = THIS_MODULE, > +#ifdef CONFIG_PM > + .pm = &ehci_msp_pmops, > +#endif > + }, > +}; > diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h > index 799ac16..1b71d6a 100644 > --- a/drivers/usb/host/ehci.h > +++ b/drivers/usb/host/ehci.h > @@ -134,6 +134,7 @@ struct ehci_hcd { /* one per controller */ > unsigned amd_l1_fix:1; > unsigned fs_i_thresh:1; /* Intel iso scheduling */ > unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ > + unsigned pmc_msp_tdi:1; /* PMC MSP tdi quirk*/ This part of the patch doesn't apply cleanly anymore, care to refresh it against linux-next, and make all of the other fixes and resend it? thanks, greg k-h From benh@kernel.crashing.org Mon Feb 7 00:29:13 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Feb 2011 00:29:16 +0100 (CET) Received: from gate.crashing.org ([63.228.1.57]:40023 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491843Ab1BFX3N (ORCPT ); Mon, 7 Feb 2011 00:29:13 +0100 Received: from [IPv6:::1] (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p16NQXoc023703; Sun, 6 Feb 2011 17:26:35 -0600 Subject: Re: [PATCH] sched: provide scheduler_ipi() callback in response to smp_send_reschedule() From: Benjamin Herrenschmidt To: Peter Zijlstra Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Mike Frysinger , Mikael Starvik , Jesper Nilsson , Tony Luck , Fenghua Yu , Hirokazu Takata , Ralf Baechle , David Howells , Koichi Yasutake , Kyle McMartin , Helge Deller , "James E.J. Bottomley" , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Chris Metcalf , Jeff Dike , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Jeremy Fitzhardinge , Konrad Rzeszutek Wilk , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, xen-devel@lists.xensource.com, virtualization@lists.osdl.org, Linux-Arch In-Reply-To: <1295262433.30950.53.camel@laptop> References: <1295262433.30950.53.camel@laptop> Content-Type: text/plain; charset="UTF-8" Date: Mon, 07 Feb 2011 10:26:32 +1100 Message-ID: <1297034792.14982.10.camel@pasglop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29127 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: benh@kernel.crashing.org Precedence: bulk X-list: linux-mips On Mon, 2011-01-17 at 12:07 +0100, Peter Zijlstra wrote: > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c > index 68034bb..7ee0fc3 100644 > --- a/arch/powerpc/kernel/smp.c > +++ b/arch/powerpc/kernel/smp.c > @@ -128,6 +128,7 @@ static irqreturn_t call_function_action(int irq, void *data) > static irqreturn_t reschedule_action(int irq, void *data) > { > /* we just need the return path side effect of checking need_resched */ > + scheduler_ipi(); > return IRQ_HANDLED; > } > You missed: diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 9813605..467d122 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -98,6 +98,7 @@ void smp_message_recv(int msg) break; case PPC_MSG_RESCHEDULE: /* we notice need_resched on exit */ + scheduler_ipi(); break; case PPC_MSG_CALL_FUNC_SINGLE: generic_smp_call_function_single_interrupt(); Fold that in and add: Acked-by: Benjamin Herrenschmidt (We have two variants of the IPIs) Cheers, Ben. From yyuasa@gmail.com Mon Feb 7 03:31:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Feb 2011 03:31:51 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:33318 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491851Ab1BGCbs (ORCPT ); Mon, 7 Feb 2011 03:31:48 +0100 Received: by yxd30 with SMTP id 30so1618117yxd.36 for ; Sun, 06 Feb 2011 18:31:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:date:from:to:cc:subject:message-id :x-mailer:mime-version:content-type:content-transfer-encoding; bh=A+H0c80Ljkdhh6hKRHCd5xseh/v3LeAGVzpJS37j0Qk=; b=dDN9FkjyEo2rzcFAY3Se8JD+XPiiSeekpm+1V9Uf+V4xHRJFrB1FPM7/QWgWEx3wX1 Y4ja3CCG+FMMWBMyFc+ze+fZxrHuuBKUDMMSmRxfkg8l4DyCGLYG5urb/5TOhGJOSi0+ FzXRcDJaHwt+icWN/1gA5a3n3E8JB867qaHr4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=S/6lvSUdEjbvou6d/AGZXnD0GlV1gVR9683ilLE+aAbn1eLK1dNxDah94JBN/KYQQd Z+FRgdR8JErKSemaqz45163Z/xqwLO74n9SUGE1zBTF15IEAIQC6Nlg5xjmvojGJAghE ITIBjpBFQIi1tOge8rY4ufae5ai3plPqVvAUc= Received: by 10.236.109.131 with SMTP id s3mr28855637yhg.92.1297045902012; Sun, 06 Feb 2011 18:31:42 -0800 (PST) Received: from stratos (sannin29007.nirai.ne.jp [203.160.29.7]) by mx.google.com with ESMTPS id a11sm2515618yhd.36.2011.02.06.18.31.39 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 06 Feb 2011 18:31:41 -0800 (PST) Date: Mon, 7 Feb 2011 11:31:36 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH] MIPS: fix always CONFIG_LOONGSON_UART_BASE=y Message-Id: <20110207113136.2179ffc9.yuasa@linux-mips.org> X-Mailer: Sylpheed 3.1.0beta7 (GTK+ 2.22.0; x86_64-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29128 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/loongson/Kconfig | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 6e1b77f..aca93ee 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -1,6 +1,7 @@ +if MACH_LOONGSON + choice prompt "Machine Type" - depends on MACH_LOONGSON config LEMOTE_FULOONG2E bool "Lemote Fuloong(2e) mini-PC" @@ -87,3 +88,5 @@ config LOONGSON_UART_BASE config LOONGSON_MC146818 bool default n + +endif # MACH_LOONGSON -- 1.7.4 From mikael.starvik@axis.com Mon Feb 7 10:02:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Feb 2011 10:02:52 +0100 (CET) Received: from anubis.se.axis.com ([195.60.68.12]:42696 "EHLO anubis.se.axis.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491067Ab1BGJCt convert rfc822-to-8bit (ORCPT ); Mon, 7 Feb 2011 10:02:49 +0100 Received: from localhost (localhost [127.0.0.1]) by anubis.se.axis.com (Postfix) with ESMTP id CAF2E19D07 for ; Mon, 7 Feb 2011 10:02:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at anubis.se.axis.com Received: from anubis.se.axis.com ([127.0.0.1]) by localhost (anubis.se.axis.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id Yzgdgj3apTi5 for ; Mon, 7 Feb 2011 10:02:41 +0100 (CET) Received: from thoth.se.axis.com (thoth.se.axis.com [10.0.2.173]) by anubis.se.axis.com (Postfix) with ESMTP id 932C619D00 for ; Mon, 7 Feb 2011 10:02:40 +0100 (CET) Received: from xmail3.se.axis.com (xmail3.se.axis.com [10.0.5.75]) by thoth.se.axis.com (Postfix) with ESMTP id 9924534145 for ; Mon, 7 Feb 2011 10:02:40 +0100 (CET) Received: from xmail3.se.axis.com ([10.0.5.75]) by xmail3.se.axis.com ([10.0.5.75]) with mapi; Mon, 7 Feb 2011 10:02:40 +0100 From: Mikael Starvik To: "linux-mips@linux-mips.org" Date: Mon, 7 Feb 2011 10:02:34 +0100 Subject: Highmem in architechtures with cache alias Thread-Topic: Highmem in architechtures with cache alias Thread-Index: AcvGpcKiS+6S2cZ3S+WKJ2QF7+g/MQ== Message-ID: <4BEA3FF3CAA35E408EA55C7BE2E61D055C60823A4F@xmail3.se.axis.com> Accept-Language: sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-cr-puzzleid: {5A2D5031-25B1-4079-8637-0D4F4D2DB8D9} x-cr-hashedpuzzle: B0Q= Anrj Arms Bb8N CzOs DCBG F8dQ GiMm G2Lf HXhh Hcbo HnSG H0ZZ IPfT I+Ku KnM+;1;bABpAG4AdQB4AC0AbQBpAHAAcwBAAGwAaQBuAHUAeAAtAG0AaQBwAHMALgBvAHIAZwA=;Sosha1_v1;7;{5A2D5031-25B1-4079-8637-0D4F4D2DB8D9};bQBpAGsAYQBlAGwALgBzAHQAYQByAHYAaQBrAEAAYQB4AGkAcwAuAGMAbwBtAA==;Mon, 07 Feb 2011 09:02:34 GMT;SABpAGcAaABtAGUAbQAgAGkAbgAgAGEAcgBjAGgAaQB0AGUAYwBoAHQAdQByAGUAcwAgAHcAaQB0AGgAIABjAGEAYwBoAGUAIABhAGwAaQBhAHMA acceptlanguage: sv-SE Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29129 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mikael.starvik@axis.com Precedence: bulk X-list: linux-mips Hi! It is clearly stated in http://www.linux-mips.org/wiki/Highmem that the MIPS kernel can´t user highmem on machines with cache aliasing and I understand the reason. So, what is the solution here? Switch to 16k pages? Or are there other ways to get more memory on a machine with cache aliases? /Mikael From peterz@infradead.org Mon Feb 7 14:53:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Feb 2011 14:53:40 +0100 (CET) Received: from casper.infradead.org ([85.118.1.10]:34955 "EHLO casper.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491092Ab1BGNxe (ORCPT ); Mon, 7 Feb 2011 14:53:34 +0100 Received: from j77219.upc-j.chello.nl ([24.132.77.219] helo=dyad.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.72 #1 (Red Hat Linux)) id 1PmRX2-00068z-S8 for linux-mips@linux-mips.org; Mon, 07 Feb 2011 13:53:32 +0000 Received: by dyad.programming.kicks-ass.net (Postfix, from userid 65534) id AE9CA2425A; Mon, 7 Feb 2011 14:56:49 +0100 (CET) Received: from [IPv6:::1] (dyad [192.168.0.60]) by dyad.programming.kicks-ass.net (Postfix) with ESMTP id 4C95C2424A; Mon, 7 Feb 2011 14:56:28 +0100 (CET) Subject: Re: [PATCH] sched: provide scheduler_ipi() callback in response to smp_send_reschedule() From: Peter Zijlstra To: Benjamin Herrenschmidt Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Mike Frysinger , Mikael Starvik , Jesper Nilsson , Tony Luck , Fenghua Yu , Hirokazu Takata , Ralf Baechle , David Howells , Koichi Yasutake , Kyle McMartin , Helge Deller , "James E.J. Bottomley" , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Chris Metcalf , Jeff Dike , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Jeremy Fitzhardinge , Konrad Rzeszutek Wilk , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, xen-devel@lists.xensource.com, virtualization@lists.osdl.org, Linux-Arch In-Reply-To: <1297034792.14982.10.camel@pasglop> References: <1295262433.30950.53.camel@laptop> <1297034792.14982.10.camel@pasglop> Content-Type: text/plain; charset="UTF-8" Date: Mon, 07 Feb 2011 14:54:19 +0100 Message-ID: <1297086859.13327.16.camel@laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29130 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: peterz@infradead.org Precedence: bulk X-list: linux-mips On Mon, 2011-02-07 at 10:26 +1100, Benjamin Herrenschmidt wrote: > You missed: > > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c > index 9813605..467d122 100644 > --- a/arch/powerpc/kernel/smp.c > +++ b/arch/powerpc/kernel/smp.c > @@ -98,6 +98,7 @@ void smp_message_recv(int msg) > break; > case PPC_MSG_RESCHEDULE: > /* we notice need_resched on exit */ > + scheduler_ipi(); > break; > case PPC_MSG_CALL_FUNC_SINGLE: > generic_smp_call_function_single_interrupt(); > > Fold that in and add: > > Acked-by: Benjamin Herrenschmidt Thanks Ben! From lars@metafoo.de Tue Feb 8 03:33:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Feb 2011 03:33:26 +0100 (CET) Received: from smtp-out-214.synserver.de ([212.40.185.214]:1082 "HELO smtp-out-214.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492000Ab1BHCdU (ORCPT ); Tue, 8 Feb 2011 03:33:20 +0100 Received: (qmail 4974 invoked by uid 0); 8 Feb 2011 02:33:18 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 4605 Received: from e177158163.adsl.alicedsl.de (HELO lars-laptop.nons.lan) [85.177.158.163] by 217.119.54.81 with SMTP; 8 Feb 2011 02:33:18 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH 2/2] MIPS: JZ4740: GPIO: Use shared irq chip for all gpios Date: Tue, 8 Feb 2011 03:34:18 +0100 Message-Id: <1297132458-16883-2-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297132458-16883-1-git-send-email-lars@metafoo.de> References: <1297132458-16883-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29131 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Currently there is one irq_chip per gpio_chip with the only difference being the name. Since the information whether the irq belong to GPIO bank A, B, C or D is not that important rewrite the code to simply use a single irq_chip for all gpio_chips. Signed-off-by: Lars-Peter Clausen --- arch/mips/jz4740/gpio.c | 25 +++++++++++++------------ 1 files changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c index 1e28b75..9bb0770 100644 --- a/arch/mips/jz4740/gpio.c +++ b/arch/mips/jz4740/gpio.c @@ -86,7 +86,6 @@ struct jz_gpio_chip { spinlock_t lock; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; struct sys_device sysdev; }; @@ -435,6 +434,17 @@ static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static struct irq_chip jz_gpio_irq_chip = { + .name = "GPIO", + .irq_mask = jz_gpio_irq_mask, + .irq_unmask = jz_gpio_irq_unmask, + .irq_ack = jz_gpio_irq_ack, + .irq_startup = jz_gpio_irq_startup, + .irq_shutdown = jz_gpio_irq_shutdown, + .irq_set_type = jz_gpio_irq_set_type, + .irq_set_wake = jz_gpio_irq_set_wake, +}; + /* * This lock class tells lockdep that GPIO irqs are in a different * category than their parents, so it won't report false recursion. @@ -453,16 +463,6 @@ static struct lock_class_key gpio_lock_class; .base = JZ4740_GPIO_BASE_ ## _bank, \ .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ }, \ - .irq_chip = { \ - .name = "GPIO Bank " # _bank, \ - .irq_mask = jz_gpio_irq_mask, \ - .irq_unmask = jz_gpio_irq_unmask, \ - .irq_ack = jz_gpio_irq_ack, \ - .irq_startup = jz_gpio_irq_startup, \ - .irq_shutdown = jz_gpio_irq_shutdown, \ - .irq_set_type = jz_gpio_irq_set_type, \ - .irq_set_wake = jz_gpio_irq_set_wake, \ - }, \ } static struct jz_gpio_chip jz4740_gpio_chips[] = { @@ -529,7 +529,8 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class); set_irq_chip_data(irq, chip); - set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq); + set_irq_chip_and_handler(irq, &jz_gpio_irq_chip, + handle_level_irq); } return 0; -- 1.7.2.3 From lars@metafoo.de Tue Feb 8 03:33:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Feb 2011 03:33:52 +0100 (CET) Received: from smtp-out-214.synserver.de ([212.40.185.214]:1184 "HELO smtp-out-214.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492001Ab1BHCdX (ORCPT ); Tue, 8 Feb 2011 03:33:23 +0100 Received: (qmail 4948 invoked by uid 0); 8 Feb 2011 02:33:17 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 4605 Received: from e177158163.adsl.alicedsl.de (HELO lars-laptop.nons.lan) [85.177.158.163] by 217.119.54.81 with SMTP; 8 Feb 2011 02:33:17 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH 1/2] MIPS: JZ4740: Convert to new irq functions Date: Tue, 8 Feb 2011 03:34:17 +0100 Message-Id: <1297132458-16883-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29132 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Convert the JZ4740 intc and gpio irq chips to use newstyle irq functions. Signed-off-by: Lars-Peter Clausen --- arch/mips/jz4740/gpio.c | 93 ++++++++++++++++++++++++----------------------- arch/mips/jz4740/irq.c | 32 ++++++++++------ 2 files changed, 67 insertions(+), 58 deletions(-) diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c index 88e6aed..1e28b75 100644 --- a/arch/mips/jz4740/gpio.c +++ b/arch/mips/jz4740/gpio.c @@ -102,9 +102,9 @@ static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *g return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip); } -static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq) +static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data) { - return get_irq_chip_data(irq); + return irq_data_get_irq_chip_data(data); } static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) @@ -325,62 +325,63 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(gpio_irq); }; -static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg) +static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); - writel(IRQ_TO_BIT(irq), chip->base + reg); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + writel(IRQ_TO_BIT(data->irq), chip->base + reg); } -static void jz_gpio_irq_mask(unsigned int irq) +static void jz_gpio_irq_mask(struct irq_data *data) { - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET); }; -static void jz_gpio_irq_unmask(unsigned int irq) +static void jz_gpio_irq_unmask(struct irq_data *data) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); - jz_gpio_check_trigger_both(chip, irq); + jz_gpio_check_trigger_both(chip, data->irq); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR); }; /* TODO: Check if function is gpio */ -static unsigned int jz_gpio_irq_startup(unsigned int irq) +static unsigned int jz_gpio_irq_startup(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); + struct irq_desc *desc = irq_to_desc(data->irq); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET); desc->status &= ~IRQ_MASKED; - jz_gpio_irq_unmask(irq); + jz_gpio_irq_unmask(data); return 0; } -static void jz_gpio_irq_shutdown(unsigned int irq) +static void jz_gpio_irq_shutdown(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); + struct irq_desc *desc = irq_to_desc(data->irq); - jz_gpio_irq_mask(irq); + jz_gpio_irq_mask(data); desc->status |= IRQ_MASKED; /* Set direction to input */ - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR); } -static void jz_gpio_irq_ack(unsigned int irq) +static void jz_gpio_irq_ack(struct irq_data *data) { - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR); }; -static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); - struct irq_desc *desc = irq_to_desc(irq); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + struct irq_desc *desc = irq_to_desc(data->irq); + unsigned int irq = data->irq; - jz_gpio_irq_mask(irq); + jz_gpio_irq_mask(data); if (flow_type == IRQ_TYPE_EDGE_BOTH) { uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); @@ -395,39 +396,39 @@ static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) switch (flow_type) { case IRQ_TYPE_EDGE_RISING: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); break; case IRQ_TYPE_EDGE_FALLING: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); break; case IRQ_TYPE_LEVEL_HIGH: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); break; case IRQ_TYPE_LEVEL_LOW: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); break; default: return -EINVAL; } if (!(desc->status & IRQ_MASKED)) - jz_gpio_irq_unmask(irq); + jz_gpio_irq_unmask(data); return 0; } -static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); spin_lock(&chip->lock); if (on) - chip->wakeup |= IRQ_TO_BIT(irq); + chip->wakeup |= IRQ_TO_BIT(data->irq); else - chip->wakeup &= ~IRQ_TO_BIT(irq); + chip->wakeup &= ~IRQ_TO_BIT(data->irq); spin_unlock(&chip->lock); set_irq_wake(chip->irq, on); @@ -454,13 +455,13 @@ static struct lock_class_key gpio_lock_class; }, \ .irq_chip = { \ .name = "GPIO Bank " # _bank, \ - .mask = jz_gpio_irq_mask, \ - .unmask = jz_gpio_irq_unmask, \ - .ack = jz_gpio_irq_ack, \ - .startup = jz_gpio_irq_startup, \ - .shutdown = jz_gpio_irq_shutdown, \ - .set_type = jz_gpio_irq_set_type, \ - .set_wake = jz_gpio_irq_set_wake, \ + .irq_mask = jz_gpio_irq_mask, \ + .irq_unmask = jz_gpio_irq_unmask, \ + .irq_ack = jz_gpio_irq_ack, \ + .irq_startup = jz_gpio_irq_startup, \ + .irq_shutdown = jz_gpio_irq_shutdown, \ + .irq_set_type = jz_gpio_irq_set_type, \ + .irq_set_wake = jz_gpio_irq_set_wake, \ }, \ } diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c index 7d33ff8..dcc5593 100644 --- a/arch/mips/jz4740/irq.c +++ b/arch/mips/jz4740/irq.c @@ -43,32 +43,37 @@ static uint32_t jz_intc_saved; #define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE) -static void intc_irq_unmask(unsigned int irq) +static inline unsigned long intc_irq_bit(struct irq_data *data) { - writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); + return (unsigned long)irq_data_get_irq_chip_data(data); } -static void intc_irq_mask(unsigned int irq) +static void intc_irq_unmask(struct irq_data *data) { - writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK); + writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); } -static int intc_irq_set_wake(unsigned int irq, unsigned int on) +static void intc_irq_mask(struct irq_data *data) +{ + writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK); +} + +static int intc_irq_set_wake(struct irq_data *data, unsigned int on) { if (on) - jz_intc_wakeup |= IRQ_BIT(irq); + jz_intc_wakeup |= intc_irq_bit(data); else - jz_intc_wakeup &= ~IRQ_BIT(irq); + jz_intc_wakeup &= ~intc_irq_bit(data); return 0; } static struct irq_chip intc_irq_type = { .name = "INTC", - .mask = intc_irq_mask, - .mask_ack = intc_irq_mask, - .unmask = intc_irq_unmask, - .set_wake = intc_irq_set_wake, + .irq_mask = intc_irq_mask, + .irq_mask_ack = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_set_wake = intc_irq_set_wake, }; static irqreturn_t jz4740_cascade(int irq, void *data) @@ -95,8 +100,11 @@ void __init arch_init_irq(void) jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); + /* Mask all irqs */ + writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); + for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { - intc_irq_mask(i); + set_irq_chip_data(i, (void *)IRQ_BIT(i)); set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); } -- 1.7.2.3 From lars@metafoo.de Tue Feb 8 03:42:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Feb 2011 03:42:36 +0100 (CET) Received: from smtp-out-214.synserver.de ([212.40.185.214]:1078 "EHLO smtp-out-214.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491996Ab1BHCmc (ORCPT ); Tue, 8 Feb 2011 03:42:32 +0100 Received: (qmail 13092 invoked by uid 0); 8 Feb 2011 02:42:27 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 12918 Received: from e177158163.adsl.alicedsl.de (HELO lars-laptop.nons.lan) [85.177.158.163] by 217.119.54.87 with SMTP; 8 Feb 2011 02:42:27 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH] MIPS: JZ4740: qi_lb60: Add gpio-charger device Date: Tue, 8 Feb 2011 03:43:53 +0100 Message-Id: <1297133034-17586-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.7.2.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29133 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Register the gpio-charger device which reports whether device is currently charging or not. Signed-off-by: Lars-Peter Clausen --- arch/mips/jz4740/board-qi_lb60.c | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-) diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 3e33264..e3f21ba 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -395,6 +396,28 @@ static struct platform_device qi_lb60_pwm_beeper = { }, }; +/* charger */ +static char *qi_lb60_batteries[] = { + "battery", +}; + +static struct gpio_charger_platform_data qi_lb60_charger_pdata = { + .name = "usb", + .type = POWER_SUPPLY_TYPE_USB, + .gpio = JZ_GPIO_PORTD(28), + .gpio_active_low = 1, + .supplied_to = qi_lb60_batteries, + .num_supplicants = ARRAY_SIZE(qi_lb60_batteries), +}; + +static struct platform_device qi_lb60_charger_device = { + .name = "gpio-charger", + .dev = { + .platform_data = &qi_lb60_charger_pdata, + }, +}; + + static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_udc_device, &jz4740_mmc_device, @@ -409,6 +432,7 @@ static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_adc_device, &qi_lb60_gpio_keys, &qi_lb60_pwm_beeper, + &qi_lb60_charger_device, }; static void __init board_gpio_setup(void) -- 1.7.2.3 From lars@metafoo.de Tue Feb 8 03:42:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Feb 2011 03:43:00 +0100 (CET) Received: from smtp-out-214.synserver.de ([212.40.185.214]:1151 "EHLO smtp-out-214.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492001Ab1BHCmd (ORCPT ); Tue, 8 Feb 2011 03:42:33 +0100 Received: (qmail 13152 invoked by uid 0); 8 Feb 2011 02:42:28 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 12918 Received: from e177158163.adsl.alicedsl.de (HELO lars-laptop.nons.lan) [85.177.158.163] by 217.119.54.87 with SMTP; 8 Feb 2011 02:42:28 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH] MIPS: JZ4740: Set nand ecc offsets for the qi_lb60 board Date: Tue, 8 Feb 2011 03:43:54 +0100 Message-Id: <1297133034-17586-2-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297133034-17586-1-git-send-email-lars@metafoo.de> References: <1297133034-17586-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29134 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips The jz4740 nand driver now requires that the ecc offsets are set. Signed-off-by: Lars-Peter Clausen --- This should go into 2.6.38 --- arch/mips/jz4740/board-qi_lb60.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index e3f21ba..34f5227 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -50,14 +50,14 @@ static bool is_avt2; /* NAND */ static struct nand_ecclayout qi_lb60_ecclayout_1gb = { -/* .eccbytes = 36, + .eccbytes = 36, .eccpos = { 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 - },*/ + }, .oobfree = { { .offset = 2, .length = 4 }, { .offset = 42, .length = 22 } @@ -86,7 +86,7 @@ static struct mtd_partition qi_lb60_partitions_1gb[] = { }; static struct nand_ecclayout qi_lb60_ecclayout_2gb = { -/* .eccbytes = 72, + .eccbytes = 72, .eccpos = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, @@ -97,7 +97,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_2gb = { 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83 - },*/ + }, .oobfree = { { .offset = 2, .length = 10 }, { .offset = 84, .length = 44 }, -- 1.7.2.3 From maksim.rayskiy@gmail.com Wed Feb 9 01:20:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 01:21:00 +0100 (CET) Received: from mms3.broadcom.com ([216.31.210.19]:2019 "EHLO MMS3.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491914Ab1BIAU4 (ORCPT ); Wed, 9 Feb 2011 01:20:56 +0100 Received: from [10.9.200.131] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Tue, 08 Feb 2011 16:20:04 -0800 X-Server-Uuid: B55A25B1-5D7D-41F8-BC53-C57E7AD3C201 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Tue, 8 Feb 2011 16:18:19 -0800 Received: from stb-bld-00.broadcom.com (stb-bld-00 [10.13.134.27]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 8A46874D03; Tue, 8 Feb 2011 16:18:19 -0800 (PST) From: maksim.rayskiy@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org cc: "Maksim Rayskiy" Subject: [PATCH] MIPS: clear idle task mm pointer when hotplugging cpu Date: Tue, 8 Feb 2011 16:18:07 -0800 Message-ID: <1297210687-14589-1-git-send-email-maksim.rayskiy@gmail.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 X-WSS-ID: 614F023E0604167947-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29135 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maksim.rayskiy@gmail.com Precedence: bulk X-list: linux-mips From: Maksim Rayskiy If kernel starts with maxcpus= option which does not bring all available cpus online at boot time, idle tasks for offline cpus are not created. If later offline cpus are hotplugged through sysfs, __cpu_up is called in the context of the user task, and fork_idle copies its non-zero mm pointer. This causes BUG() in per_cpu_trap_init. To avoid this, release mm for idle task and reset the pointer after fork_idle(). Signed-off-by: Maksim Rayskiy --- arch/mips/kernel/smp.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 383aeb9..4593916 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -208,6 +208,11 @@ int __cpuinit __cpu_up(unsigned int cpu) if (IS_ERR(idle)) panic(KERN_ERR "Fork failed for CPU %d", cpu); + + if (idle->mm) { + mmput(idle->mm); + idle->mm = NULL; + } } else { idle = cpu_idle_thread[cpu]; init_idle(idle, cpu); -- 1.7.3.2 From benh@kernel.crashing.org Wed Feb 9 07:17:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 07:17:23 +0100 (CET) Received: from gate.crashing.org ([63.228.1.57]:48518 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491013Ab1BIGRQ (ORCPT ); Wed, 9 Feb 2011 07:17:16 +0100 Received: from [IPv6:::1] (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p196EF5o023345; Wed, 9 Feb 2011 00:14:16 -0600 Subject: Re: [PATCH] sched: provide scheduler_ipi() callback in response to smp_send_reschedule() From: Benjamin Herrenschmidt To: Peter Zijlstra Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Mike Frysinger , Mikael Starvik , Jesper Nilsson , Tony Luck , Fenghua Yu , Hirokazu Takata , Ralf Baechle , David Howells , Koichi Yasutake , Kyle McMartin , Helge Deller , "James E.J. Bottomley" , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Chris Metcalf , Jeff Dike , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Jeremy Fitzhardinge , Konrad Rzeszutek Wilk , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, xen-devel@lists.xensource.com, virtualization@lists.osdl.org, Linux-Arch In-Reply-To: <1297086859.13327.16.camel@laptop> References: <1295262433.30950.53.camel@laptop> <1297034792.14982.10.camel@pasglop> <1297086859.13327.16.camel@laptop> Content-Type: text/plain; charset="UTF-8" Date: Wed, 09 Feb 2011 17:14:14 +1100 Message-ID: <1297232054.14982.346.camel@pasglop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29136 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: benh@kernel.crashing.org Precedence: bulk X-list: linux-mips On Mon, 2011-02-07 at 14:54 +0100, Peter Zijlstra wrote: > On Mon, 2011-02-07 at 10:26 +1100, Benjamin Herrenschmidt wrote: > > You missed: > > > > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c > > index 9813605..467d122 100644 > > --- a/arch/powerpc/kernel/smp.c > > +++ b/arch/powerpc/kernel/smp.c > > @@ -98,6 +98,7 @@ void smp_message_recv(int msg) > > break; > > case PPC_MSG_RESCHEDULE: > > /* we notice need_resched on exit */ > > + scheduler_ipi(); > > break; > > case PPC_MSG_CALL_FUNC_SINGLE: > > generic_smp_call_function_single_interrupt(); > > > > Fold that in and add: > > > > Acked-by: Benjamin Herrenschmidt > > Thanks Ben! BTW. I we lurking at some of our CPU hotplug code and I think I cannot totally guarantee that this won't be called on an offline CPU. If that's a problem, you may want to add a test for that. IE. The call function IPIs are normally not going to be sent to an offlined CPU, and stop_machine should be a good enough fence here, but we do abuse reschedule for a number of things (including in some case to wake up a sleeping CPU that was pseudo-offlined :-) Cheers, Ben. From peterz@infradead.org Wed Feb 9 10:36:48 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 10:36:52 +0100 (CET) Received: from bombadil.infradead.org ([18.85.46.34]:39568 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491146Ab1BIJgs (ORCPT ); Wed, 9 Feb 2011 10:36:48 +0100 Received: from canuck.infradead.org ([2001:4978:20e::1]) by bombadil.infradead.org with esmtps (Exim 4.72 #1 (Red Hat Linux)) id 1Pn6Tc-0005eU-I7 for linux-mips@linux-mips.org; Wed, 09 Feb 2011 09:36:45 +0000 Received: from j77219.upc-j.chello.nl ([24.132.77.219] helo=dyad.programming.kicks-ass.net) by canuck.infradead.org with esmtpsa (Exim 4.72 #1 (Red Hat Linux)) id 1Pn6Ta-0000uw-1p for linux-mips@linux-mips.org; Wed, 09 Feb 2011 09:36:42 +0000 Received: by dyad.programming.kicks-ass.net (Postfix, from userid 65534) id 2027524256; Wed, 9 Feb 2011 10:39:56 +0100 (CET) Received: from [IPv6:::1] (dyad [192.168.0.60]) by dyad.programming.kicks-ass.net (Postfix) with ESMTP id EDEF72424A; Wed, 9 Feb 2011 10:39:31 +0100 (CET) Subject: Re: [PATCH] sched: provide scheduler_ipi() callback in response to smp_send_reschedule() From: Peter Zijlstra To: Benjamin Herrenschmidt Cc: Richard Henderson , Ivan Kokshaysky , Matt Turner , Russell King , Mike Frysinger , Mikael Starvik , Jesper Nilsson , Tony Luck , Fenghua Yu , Hirokazu Takata , Ralf Baechle , David Howells , Koichi Yasutake , Kyle McMartin , Helge Deller , "James E.J. Bottomley" , Paul Mackerras , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, Paul Mundt , "David S. Miller" , Chris Metcalf , Jeff Dike , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Jeremy Fitzhardinge , Konrad Rzeszutek Wilk , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, uclinux-dist-devel@blackfin.uclinux.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m32r-ja@ml.linux-m32r.org, linux-mips@linux-mips.org, linux-am33-list@redhat.com, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, xen-devel@lists.xensource.com, virtualization@lists.osdl.org, Linux-Arch In-Reply-To: <1297232054.14982.346.camel@pasglop> References: <1295262433.30950.53.camel@laptop> <1297034792.14982.10.camel@pasglop> <1297086859.13327.16.camel@laptop> <1297232054.14982.346.camel@pasglop> Content-Type: text/plain; charset="UTF-8" Date: Wed, 09 Feb 2011 10:37:24 +0100 Message-ID: <1297244244.13327.147.camel@laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29137 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: peterz@infradead.org Precedence: bulk X-list: linux-mips On Wed, 2011-02-09 at 17:14 +1100, Benjamin Herrenschmidt wrote: > On Mon, 2011-02-07 at 14:54 +0100, Peter Zijlstra wrote: > > On Mon, 2011-02-07 at 10:26 +1100, Benjamin Herrenschmidt wrote: > > > You missed: > > > > > > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c > > > index 9813605..467d122 100644 > > > --- a/arch/powerpc/kernel/smp.c > > > +++ b/arch/powerpc/kernel/smp.c > > > @@ -98,6 +98,7 @@ void smp_message_recv(int msg) > > > break; > > > case PPC_MSG_RESCHEDULE: > > > /* we notice need_resched on exit */ > > > + scheduler_ipi(); > > > break; > > > case PPC_MSG_CALL_FUNC_SINGLE: > > > generic_smp_call_function_single_interrupt(); > > > > > > Fold that in and add: > > > > > > Acked-by: Benjamin Herrenschmidt > > > > Thanks Ben! > > BTW. I we lurking at some of our CPU hotplug code and I think I cannot > totally guarantee that this won't be called on an offline CPU. If that's > a problem, you may want to add a test for that. > > IE. The call function IPIs are normally not going to be sent to an > offlined CPU, and stop_machine should be a good enough fence here, but > we do abuse reschedule for a number of things (including in some case > to wake up a sleeping CPU that was pseudo-offlined :-) Hmm, I _think_ that should all work out nicely, but we'll see, if when this stuff hits the tree powerpc machines start falling over we'd better put that check in ;-) Meanwhile I'm going to preserve this comment in the changelog of this patch so we don't forget. From ralf@duck.linux-mips.net Wed Feb 9 13:01:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 13:01:49 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36853 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491778Ab1BIMBq (ORCPT ); Wed, 9 Feb 2011 13:01:46 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p19C2BLp031727; Wed, 9 Feb 2011 13:02:12 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p19C292J031723; Wed, 9 Feb 2011 13:02:09 +0100 Date: Wed, 9 Feb 2011 13:02:09 +0100 From: Ralf Baechle To: maksim.rayskiy@gmail.com Cc: linux-mips@linux-mips.org, Maksim Rayskiy Subject: Re: [PATCH] MIPS: clear idle task mm pointer when hotplugging cpu Message-ID: <20110209120209.GA21796@linux-mips.org> References: <1297210687-14589-1-git-send-email-maksim.rayskiy@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1297210687-14589-1-git-send-email-maksim.rayskiy@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29138 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 08, 2011 at 04:18:07PM -0800, maksim.rayskiy@gmail.com wrote: > If kernel starts with maxcpus= option which does not bring all > available cpus online at boot time, idle tasks for offline cpus > are not created. If later offline cpus are hotplugged through sysfs, > __cpu_up is called in the context of the user task, and fork_idle > copies its non-zero mm pointer. This causes BUG() in per_cpu_trap_init. > > To avoid this, release mm for idle task and reset the pointer after > fork_idle(). Nice catch, applied. x86 avoid this problem by forking the idle threads in a worker thread which also avoids other potencial issues; we probably should take the same path. Ralf From anoop.pa@gmail.com Wed Feb 9 14:52:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 14:52:51 +0100 (CET) Received: from mail-vx0-f177.google.com ([209.85.220.177]:59039 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491773Ab1BINwr (ORCPT ); Wed, 9 Feb 2011 14:52:47 +0100 Received: by vxd2 with SMTP id 2so72721vxd.36 for ; Wed, 09 Feb 2011 05:52:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:to:cc:in-reply-to:references :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=HQwoiHEHGkfYrZtCo/kUj/bewVhTthQ27748u8vCqCM=; b=F5Ldl84Z6Ox2DudTd1ASv/BF2SW/efFitUXprdNz34w9vHzFJkPug53IkXN6Z0tDql c/+94slVh6wj9jVTCGyXHr65Cuq+CGmmy97PbCieCQcBqUGc3t8VEczrdIFDU1C4zMP1 xbKCW7Pc7xHEf2WK41kZfPAkz2JDsaN1WJfuI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=YeWsmdc4tSfQHcLxhTz15Z7aiDoAB5KYO0LNu6YJvJ/l/vkhuQaWcFTBNHaH+mBY7V yAKiZTWo3vOqD+H4mrmT37ktwLPqH1b1ShmZe/WDyOaUNYgdfJ+c/dK+WcsrXJbJPXUt XxCEXzAAYQoYN6dESqEd72epb4xz9Pl3XVgQI= Received: by 10.220.70.211 with SMTP id e19mr5023586vcj.204.1297259560488; Wed, 09 Feb 2011 05:52:40 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id l6sm65215vcp.38.2011.02.09.05.52.31 (version=SSLv3 cipher=RC4-MD5); Wed, 09 Feb 2011 05:52:37 -0800 (PST) Subject: Re: [PATCH v3] EHCI bus glue for on-chip PMC MSP USB controller. From: Anoop P A To: Greg KH Cc: gregkh@suse.de, dbrownell@users.sourceforge.net, ust@denx.de, pkondeti@codeaurora.org, stern@rowland.harvard.edu, gadiyar@ti.com, alek.du@intel.com, jacob.jun.pan@intel.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org In-Reply-To: <20110204195624.GA27680@kroah.com> References: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> <20110204195624.GA27680@kroah.com> Content-Type: text/plain; charset="UTF-8" Date: Wed, 09 Feb 2011 19:42:33 +0530 Message-ID: <1297260753.29250.20.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29139 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2011-02-04 at 11:56 -0800, Greg KH wrote: > On Thu, Jan 27, 2011 at 04:58:56PM +0530, Anoop P.A wrote: > > From: Anoop P A > > > > Signed-off-by: Anoop P A > > Tested-by: Shane McDonald > > Care to provide a "real" changelog comment for this patch? We need > something here. Will do. > > > --- > > drivers/usb/host/Kconfig | 15 +- > > + * PMC MSP EHCI (Host Controller Driver) for USB. > > + * > > + * (C) Copyright 2006-2010 PMC-Sierra Inc > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms of the GNU General Public License as published by the > > + * Free Software Foundation; either version 2 of the License, or (at your > > + * option) any later version. > > Are you sure about "any later version"? Is this acceptable to your > company lawyers? > Will fix it. > > + * > > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > > + * > > + * You should have received a copy of the GNU General Public License along > > + * with this program; if not, write to the Free Software Foundation, Inc., > > + * 675 Mass Ave, Cambridge, MA 02139, USA. > > These two paragraphs are not needed, please remove them. > Ok. > > + */ > > + > > +#include > > +#include > > +#include > > + > > +/* includes */ > > Um, includes for what? Are we writing comments for the previous lines? > > > +#define USB_CTRL_MODE_HOST 0x3 > > + /* host mode */ > > +#define USB_CTRL_MODE_BIG_ENDIAN 0x4 > > + /* big endian */ > > +#define USB_CTRL_MODE_STREAM_DISABLE 0x10 > > + /* stream disable*/ > > +#define USB_CTRL_FIFO_THRESH 0x00300000 > > + /* thresh hold */ > > +#define USB_EHCI_REG_USB_MODE 0x68 > > + /* register offset for usb_mode */ > > +#define USB_EHCI_REG_USB_FIFO 0x24 > > + /* register offset for usb fifo */ > > +#define USB_EHCI_REG_USB_STATUS 0x44 > > + /* register offset for usb status */ > > +#define USB_EHCI_REG_BIT_STAT_STS (1<<29) > > + /* serial/parallel transceiver */ > > +#define MSP_PIN_USB0_HOST_DEV 49 > > + /* TWI USB0 host device pin */ > > +#define MSP_PIN_USB1_HOST_DEV 50 > > + /* TWI USB1 host device pin */ > > Ok, I see we are. That's horrible, please fix it up. Ok. > > > + > > +extern int usb_disabled(void); > > Why is this in a .c file? externs should never be in a .c file. > Ok > > > + > > +void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) > > +{ > > + u8 *base; > > + u8 *statreg; > > + u8 *fiforeg; > > + u32 val; > > + struct ehci_regs *reg_base = ehci->regs; > > + > > + /* get register base */ > > + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; > > + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; > > + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; > > + > > + /* set the controller to host mode and BIG ENDIAN */ > > + ehci_writel(ehci, (USB_CTRL_MODE_HOST | USB_CTRL_MODE_BIG_ENDIAN > > + | USB_CTRL_MODE_STREAM_DISABLE), (u32 *)base); > > + > > + /* clear STS to select parallel transceiver interface */ > > + val = ehci_readl(ehci, (u32 *)statreg); > > + val = val & ~USB_EHCI_REG_BIT_STAT_STS; > > + ehci_writel(ehci, val, (u32 *)statreg); > > + > > + /* write to set the proper fifo threshold */ > > + ehci_writel(ehci, USB_CTRL_FIFO_THRESH, (u32 *)fiforeg); > > + > > + /* set TWI GPIO USB_HOST_DEV pin high */ > > + gpio_direction_output(MSP_PIN_USB0_HOST_DEV, 1); > > +#ifdef CONFIG_MSP_HAS_DUAL_USB > > + gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1); > > +#endif > > Please don't put #defines in .c files. You mean #ifdef ??? > > > +} > > + > > +/* called after powerup, by probe or system-pm "wakeup" */ > > +static int ehci_msp_reinit(struct ehci_hcd *ehci) > > +{ > > + ehci_port_power(ehci, 0); > > + > > + return 0; > > +} > > + > > +/* called during probe() after chip reset completes */ > > +static int ehci_msp_setup(struct usb_hcd *hcd) > > +{ > > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > + u32 temp; > > + int retval; > > + ehci->big_endian_mmio = 1; > > + ehci->big_endian_desc = 1; > > + ehci->pmc_msp_tdi = 1; > > + > > + ehci->caps = hcd->regs; > > + ehci->regs = hcd->regs + > > + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); > > + dbg_hcs_params(ehci, "reset"); > > + dbg_hcc_params(ehci, "reset"); > > + > > + /* cache this readonly data; minimize chip reads */ > > + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); > > + hcd->has_tt = 1; > > + tdi_reset(ehci); > > + > > + retval = ehci_halt(ehci); > > + if (retval) > > + return retval; > > + > > + ehci_reset(ehci); > > + > > + /* data structure init */ > > + retval = ehci_init(hcd); > > + if (retval) > > + return retval; > > + > > + temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); > > + temp &= 0x0f; > > + if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { > > + ehci_dbg(ehci, "bogus port configuration: " > > + "cc=%d x pcc=%d < ports=%d\n", > > + HCS_N_CC(ehci->hcs_params), > > + HCS_N_PCC(ehci->hcs_params), > > + HCS_N_PORTS(ehci->hcs_params)); > > + } > > + > > + retval = ehci_msp_reinit(ehci); > > + > > + return retval; > > +} > > + > > +/*-------------------------------------------------------------------------*/ > > + > > +static void msp_start_hc(struct platform_device *dev) > > +{ > > + printk(KERN_DEBUG __FILE__ > > + ": starting PMC MSP EHCI USB Controller\n"); > > Why? Who really cares? And, if you _really_ want to do this, please > use a dev_dbg() call instead, which ties it properly into the dynamic > printk system _and_ properly identifies this deivce. OK. > > > + > > + /* > > + * Now, carefully enable the USB clock, and take > > + * the USB host controller out of reset. > > + */ > > + printk(KERN_DEBUG __FILE__ > > + ": Clock to USB host has been enabled\n"); > > +} > > > You never enabled anything, yet you said you did? Somethings wrong > here. Forget to remove those comments. > > > + > > +static void msp_stop_hc(struct platform_device *dev) > > +{ > > + printk(KERN_DEBUG __FILE__ > > + ": stopping PMC MSP EHCI USB Controller\n"); > > +} > > Same for this printk, you didn't stop anything. > > Also fix it up and don't use printk, see above. Ok. > > > + > > + > > +/*-------------------------------------------------------------------------*/ > > + > > +/*-------------------------------------------------------------------------*/ > > + > > +#ifdef CONFIG_PM > > + > > +/* suspend/resume, section 4.3 */ > > + > > +/* These routines rely on the bus glue > > + * to handle powerdown and wakeup, and currently also on > > + * transceivers that don't need any software attention to set up > > + * the right sort of wakeup. > > + * Also they depend on separate root hub suspend/resume. > > + */ > > +static int ehci_msp_suspend(struct device *dev) > > +{ > > + struct usb_hcd *hcd = dev_get_drvdata(dev); > > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > + unsigned long flags; > > + int rc; > > + > > + return 0; > > + rc = 0; > > + > > + if (time_before(jiffies, ehci->next_statechange)) > > + msleep(10); > > Short sleep, why? I am not very sure. Person who originally wrote this driver is unreachable.Any potential issues?? > > > + > > + /* Root hub was already suspended. Disable irq emission and > > + * mark HW unaccessible. The PM and USB cores make sure that > > + * the root hub is either suspended or stopped. > > + */ > > + spin_lock_irqsave(&ehci->lock, flags); > > + ehci_prepare_ports_for_controller_suspend(ehci, device_may_wakeup(dev)); > > + ehci_writel(ehci, 0, &ehci->regs->intr_enable); > > + (void)ehci_readl(ehci, &ehci->regs->intr_enable); > > + > > + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); > > + spin_unlock_irqrestore(&ehci->lock, flags); > > + > > + /* could save FLADJ in case of Vaux power loss > > + ... we'd only use it to handle clock skew */ > > Huh? Looks like some comments missed while cleaning up > > > + > > + return rc; > > +} > > + > > +static int ehci_msp_resume(struct device *dev) > > +{ > > + struct usb_hcd *hcd = dev_get_drvdata(dev); > > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > + > > + > > + /* maybe restore FLADJ */ > > Don't you know? Not really :) > > > + > > + if (time_before(jiffies, ehci->next_statechange)) > > + msleep(100); > > That's a long sleep, are you sure that's ok on the resume path? > Again any potential issue you can guess ? > > + > > + /* Mark hardware accessible again as we are out of D3 state by now */ > > + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); > > + > > + /* If CF is still set, we maintained PCI Vaux power. > > + * Just undo the effect of ehci_pci_suspend(). > > + */ > > + if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) { > > + int mask = INTR_MASK; > > + > > + ehci_prepare_ports_for_controller_resume(ehci); > > + if (!hcd->self.root_hub->do_remote_wakeup) > > + mask &= ~STS_PCD; > > + ehci_writel(ehci, mask, &ehci->regs->intr_enable); > > + ehci_readl(ehci, &ehci->regs->intr_enable); > > + return 0; > > + } > > + > > + ehci_dbg(ehci, "lost power, restarting\n"); > > + usb_root_hub_lost_power(hcd->self.root_hub); > > + > > + /* Else reset, to cope with power loss or flush-to-storage > > + * style "resume" having let BIOS kick in during reboot. > > + */ > > + (void) ehci_halt(ehci); > > + (void) ehci_reset(ehci); > > + (void) ehci_msp_reinit(ehci); > > + > > + /* emptying the schedule aborts any urbs */ > > + spin_lock_irq(&ehci->lock); > > + if (ehci->reclaim) > > + end_unlink_async(ehci); > > + ehci_work(ehci); > > + spin_unlock_irq(&ehci->lock); > > + > > + ehci_writel(ehci, ehci->command, &ehci->regs->command); > > + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); > > + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ > > + > > + /* here we "know" root ports should always stay powered */ > > + ehci_port_power(ehci, 1); > > + > > + hcd->state = HC_STATE_SUSPENDED; > > + > > + return 0; > > +} > > + > > +static const struct dev_pm_ops ehci_msp_pmops = { > > + .suspend = ehci_msp_suspend, > > + .resume = ehci_msp_resume, > > +}; > > +#endif > > + > > + > > +/* configure so an HC device and id are always provided */ > > +/* always called with process context; sleeping is OK */ > > + > > +static int usb_hcd_msp_map_regs(struct mspusb_device *dev) > > +{ > > + struct resource *res; > > + struct platform_device *pdev = &dev->dev; > > + u32 res_len; > > + int retval; > > + > > + /* MAB register space */ > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > > + if (res == NULL) > > + return -ENOMEM; > > + res_len = res->end - res->start + 1; > > + if (!request_mem_region(res->start, res_len, "mab regs")) > > + return -EBUSY; > > + > > + dev->mab_regs = ioremap_nocache(res->start, res_len); > > + if (dev->mab_regs == NULL) { > > + retval = -ENOMEM; > > + goto err1; > > + } > > + > > + /* MSP USB register space */ > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > > + if (res == NULL) { > > + retval = -ENOMEM; > > + goto err2; > > + } > > + res_len = res->end - res->start + 1; > > + if (!request_mem_region(res->start, res_len, "usbid regs")) { > > + retval = -EBUSY; > > + goto err2; > > + } > > + dev->usbid_regs = ioremap_nocache(res->start, res_len); > > + if (dev->usbid_regs == NULL) { > > + retval = -ENOMEM; > > + goto err3; > > + } > > + > > + return 0; > > +err3: > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > > + res_len = res->end - res->start + 1; > > + release_mem_region(res->start, res_len); > > +err2: > > + iounmap(dev->mab_regs); > > +err1: > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > > + res_len = res->end - res->start + 1; > > + release_mem_region(res->start, res_len); > > + dev_err(&pdev->dev, "Failed to map non-EHCI regs.\n"); > > + return retval; > > +} > > + > > +/** > > + * usb_hcd_msp_probe - initialize PMC MSP-based HCDs > > + * Context: !in_interrupt() > > + * > > + * Allocates basic resources for this USB host controller, and > > + * then invokes the start() method for the HCD associated with it > > + * through the hotplug entry's driver_data. > > + * > > + */ > > +int usb_hcd_msp_probe(const struct hc_driver *driver, > > + struct platform_device *dev) > > +{ > > + int retval; > > + struct usb_hcd *hcd; > > + struct resource *res; > > + struct ehci_hcd *ehci ; > > + > > + hcd = usb_create_hcd(driver, &dev->dev, "pmcmsp"); > > + if (!hcd) > > + return -ENOMEM; > > + > > + res = platform_get_resource(dev, IORESOURCE_MEM, 0); > > + if (res == NULL) { > > + pr_debug("No IOMEM resource info for %s.\n", dev->name); > > + retval = -ENOMEM; > > + goto err1; > > + } > > + hcd->rsrc_start = res->start; > > + hcd->rsrc_len = res->end - res->start + 1; > > + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, dev->name)) { > > + retval = -EBUSY; > > + goto err1; > > + } > > + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); > > + if (!hcd->regs) { > > + pr_debug("ioremap failed"); > > + retval = -ENOMEM; > > + goto err2; > > + } > > + msp_start_hc(dev); > > + > > + res = platform_get_resource(dev, IORESOURCE_IRQ, 0); > > + if (res == NULL) { > > + dev_err(&dev->dev, "No IRQ resource info for %s.\n", dev->name); > > + retval = -ENOMEM; > > + goto err3; > > + } > > + > > + /* Map non-EHCI register spaces */ > > + retval = usb_hcd_msp_map_regs(to_mspusb_device(dev)); > > + if (retval != 0) > > + goto err3; > > + > > + ehci = hcd_to_ehci(hcd); > > + ehci->big_endian_mmio = 1; > > + ehci->big_endian_desc = 1; > > + > > + > > + retval = usb_add_hcd(hcd, res->start, IRQF_SHARED); > > + if (retval == 0) > > + return 0; > > + > > + usb_remove_hcd(hcd); > > +err3: > > + msp_stop_hc(dev); > > + iounmap(hcd->regs); > > +err2: > > + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); > > +err1: > > + usb_put_hcd(hcd); > > + > > + return retval; > > +} > > + > > + > > +/* may be called without controller electrically present */ > > +/* may be called with controller, bus, and devices active */ > > + > > What may be called? may be usb_hcd_msp_remove :) > > > +/** > > + * usb_hcd_msp_remove - shutdown processing for PMC MSP-based HCDs > > + * @dev: USB Host Controller being removed > > + * Context: !in_interrupt() > > + * > > + * Reverses the effect of usb_hcd_msp_probe(), first invoking > > + * the HCD's stop() method. It is always called from a thread > > + * context, normally "rmmod", "apmd", or something similar. > > + * > > + */ > > +void usb_hcd_msp_remove(struct usb_hcd *hcd, struct platform_device *dev) > > +{ > > + usb_remove_hcd(hcd); > > + msp_stop_hc(dev); > > + iounmap(hcd->regs); > > + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); > > + usb_put_hcd(hcd); > > +} > > + > > +#ifdef CONFIG_MSP_HAS_DUAL_USB > > +/*-------------------------------------------------------------------------*/ > > +/* > > + * Wrapper around the main ehci_irq. Since both USB host controllers are > > + * sharing the same IRQ, need to first determine whether we're the intended > > + * recipient of this interrupt. > > + */ > > +static irqreturn_t ehci_msp_irq(struct usb_hcd *hcd) > > +{ > > + u32 int_src; > > + struct device *dev = hcd->self.controller; > > + struct platform_device *pdev; > > + struct mspusb_device *mdev; > > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > + > > + /* need to reverse-map a couple of containers to get our device */ > > + pdev = to_platform_device(dev); > > + mdev = to_mspusb_device(pdev); > > + > > + /* Check to see if this interrupt is for this host controller */ > > + int_src = ehci_readl(ehci, &mdev->mab_regs->int_stat); > > + if (int_src & (1 << pdev->id)) > > + return ehci_irq(hcd); > > + > > + /* Not for this device */ > > + return IRQ_NONE; > > +} > > +/*-------------------------------------------------------------------------*/ > > +#endif /* DUAL_USB */ > > + > > +static const struct hc_driver ehci_msp_hc_driver = { > > + .description = hcd_name, > > + .product_desc = "PMC MSP EHCI", > > + .hcd_priv_size = sizeof(struct ehci_hcd), > > + > > + /* > > + * generic hardware linkage > > + */ > > +#ifdef CONFIG_MSP_HAS_DUAL_USB > > + .irq = ehci_msp_irq, > > +#else > > + .irq = ehci_irq, > > +#endif > > + .flags = HCD_MEMORY | HCD_USB2, > > + > > + /* > > + * basic lifecycle operations > > + */ > > + .reset = ehci_msp_setup, > > + .start = ehci_run, > > + .shutdown = ehci_shutdown, > > + .start = ehci_run, > > + .stop = ehci_stop, > > + > > + /* > > + * managing i/o requests and associated device resources > > + */ > > + .urb_enqueue = ehci_urb_enqueue, > > + .urb_dequeue = ehci_urb_dequeue, > > + .endpoint_disable = ehci_endpoint_disable, > > + .endpoint_reset = ehci_endpoint_reset, > > + > > + /* > > + * scheduling support > > + */ > > + .get_frame_number = ehci_get_frame, > > + > > + /* > > + * root hub support > > + */ > > + .hub_status_data = ehci_hub_status_data, > > + .hub_control = ehci_hub_control, > > + .bus_suspend = ehci_bus_suspend, > > + .bus_resume = ehci_bus_resume, > > + .relinquish_port = ehci_relinquish_port, > > + .port_handed_over = ehci_port_handed_over, > > + > > + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, > > +}; > > + > > +static int ehci_hcd_msp_drv_probe(struct platform_device *pdev) > > +{ > > + int ret; > > + > > + pr_debug("In ehci_hcd_msp_drv_probe"); > > + > > + if (usb_disabled()) > > + return -ENODEV; > > + > > + gpio_request(MSP_PIN_USB0_HOST_DEV, "USB0_HOST_DEV_GPIO"); > > +#ifdef CONFIG_MSP_HAS_DUAL_USB > > + gpio_request(MSP_PIN_USB1_HOST_DEV, "USB1_HOST_DEV_GPIO"); > > +#endif > > + > > + ret = usb_hcd_msp_probe(&ehci_msp_hc_driver, pdev); > > + > > + return ret; > > +} > > + > > +static int ehci_hcd_msp_drv_remove(struct platform_device *pdev) > > +{ > > + struct usb_hcd *hcd = platform_get_drvdata(pdev); > > + > > + usb_hcd_msp_remove(hcd, pdev); > > + > > + /* free TWI GPIO USB_HOST_DEV pin */ > > + gpio_free(MSP_PIN_USB0_HOST_DEV); > > +#ifdef CONFIG_MSP_HAS_DUAL_USB > > + gpio_free(MSP_PIN_USB1_HOST_DEV); > > +#endif > > + > > + return 0; > > +} > > + > > +MODULE_ALIAS("pmcmsp-ehci"); > > + > > +static struct platform_driver ehci_hcd_msp_driver = { > > + .probe = ehci_hcd_msp_drv_probe, > > + .remove = ehci_hcd_msp_drv_remove, > > + .driver = { > > + .name = "pmcmsp-ehci", > > + .owner = THIS_MODULE, > > +#ifdef CONFIG_PM > > + .pm = &ehci_msp_pmops, > > +#endif > > + }, > > +}; > > diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h > > index 799ac16..1b71d6a 100644 > > --- a/drivers/usb/host/ehci.h > > +++ b/drivers/usb/host/ehci.h > > @@ -134,6 +134,7 @@ struct ehci_hcd { /* one per controller */ > > unsigned amd_l1_fix:1; > > unsigned fs_i_thresh:1; /* Intel iso scheduling */ > > unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ > > + unsigned pmc_msp_tdi:1; /* PMC MSP tdi quirk*/ > > This part of the patch doesn't apply cleanly anymore, care to refresh it > against linux-next, and make all of the other fixes and resend it? Ok. originally created against linux-mips git head. Will resend the revised patch once I fix issues you have pointed > > thanks, > > greg k-h From ralf@duck.linux-mips.net Wed Feb 9 16:01:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 16:01:07 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39446 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491778Ab1BIPBE (ORCPT ); Wed, 9 Feb 2011 16:01:04 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p19F1Xbq017759; Wed, 9 Feb 2011 16:01:33 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p19F1XbV017757; Wed, 9 Feb 2011 16:01:33 +0100 Date: Wed, 9 Feb 2011 16:01:32 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH] MIPS: fix always CONFIG_LOONGSON_UART_BASE=y Message-ID: <20110209150132.GA17294@linux-mips.org> References: <20110207113136.2179ffc9.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110207113136.2179ffc9.yuasa@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29140 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 07, 2011 at 11:31:36AM +0900, Yoichi Yuasa wrote: Thanks, applied. Ralf From matthieu.castet@parrot.com Wed Feb 9 16:11:14 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 16:11:17 +0100 (CET) Received: from co202.xi-lite.net ([149.6.83.202]:48318 "EHLO co202.xi-lite.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491773Ab1BIPLO (ORCPT ); Wed, 9 Feb 2011 16:11:14 +0100 Received: from ONYX.xi-lite.lan (unknown [193.34.35.244]) by co202.xi-lite.net (Postfix) with ESMTPS id 6C2842602B6; Wed, 9 Feb 2011 17:19:09 +0100 (CET) Received: from [172.20.223.18] (84.14.91.202) by mail.xi-lite.com (193.34.32.105) with Microsoft SMTP Server (TLS) id 8.1.336.0; Wed, 9 Feb 2011 15:16:26 +0000 Message-ID: <4D52AE7E.8000907@parrot.com> Date: Wed, 9 Feb 2011 16:10:54 +0100 From: Matthieu CASTET User-Agent: Thunderbird 2.0.0.24 (X11/20100228) MIME-Version: 1.0 To: Anoop P.A CC: "gregkh@suse.de" , "dbrownell@users.sourceforge.net" , "ust@denx.de" , "pkondeti@codeaurora.org" , "stern@rowland.harvard.edu" , "gadiyar@ti.com" , "alek.du@intel.com" , "jacob.jun.pan@intel.com" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" Subject: Re: [PATCH v3] EHCI bus glue for on-chip PMC MSP USB controller. References: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> In-Reply-To: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29141 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matthieu.castet@parrot.com Precedence: bulk X-list: linux-mips Anoop P.A a écrit : > config XPS_USB_HCD_XILINX > diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c > index 6fee3cd..a591890 100644 > --- a/drivers/usb/host/ehci-hcd.c > +++ b/drivers/usb/host/ehci-hcd.c > @@ -262,6 +262,8 @@ static void tdi_reset (struct ehci_hcd *ehci) > if (ehci_big_endian_mmio(ehci)) > tmp |= USBMODE_BE; > ehci_writel(ehci, tmp, reg_ptr); > + if (ehci->pmc_msp_tdi) > + usb_hcd_tdi_set_mode(ehci); > } This is ugly to add callback to your driver here. How this will build on other platform, usb_hcd_tdi_set_mode is only defined on ehci-pmcmsp.c > +void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) > +{ > + u8 *base; > + u8 *statreg; > + u8 *fiforeg; > + u32 val; > + struct ehci_regs *reg_base = ehci->regs; > + > + /* get register base */ > + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; > + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; > + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; > + > + /* set the controller to host mode and BIG ENDIAN */ > + ehci_writel(ehci, (USB_CTRL_MODE_HOST | USB_CTRL_MODE_BIG_ENDIAN > + | USB_CTRL_MODE_STREAM_DISABLE), (u32 *)base); > + We have done that in tdi_reset, why do you do it again ? Matthieu From anoop.pa@gmail.com Wed Feb 9 16:25:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 16:25:13 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:36552 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491779Ab1BIPZK (ORCPT ); Wed, 9 Feb 2011 16:25:10 +0100 Received: by eyd9 with SMTP id 9so138215eyd.36 for ; Wed, 09 Feb 2011 07:25:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:to:cc:in-reply-to:references :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=+J0VW9KmvbHhZPSA1E7OOlfwaPHCz5ZqWh7CoO1d8Bo=; b=T2p67478xTowl2tS+W6UTT1lX52QjfAu1FFwzH1ZGc0VkfMSM8NJK3+Nt9hNKBZW1b NcTCXNZetlXByijbqVflC8mxFR9aMGjn/5AzsJBIBquRfkHhmCp5SsQqxNsTWm9k/SML 74/w/26NSUKeErXT/vtHHmHurCQeK8yb0Obn8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=Q4dmV5HavU17ldy3osWUuQqHst4IOSgRNTygkVD+RgeeWV5K6pxPGOCZn+fOuj9PdS I4cbRiV/30YT2K5ekcth49dsnwU+fyewqqObC61eKGJpewuQN/5M80mOpBiNBA8FDvbV nDI//EBMuCoWgcLB6DmOh7uMkToReT5UnhwNQ= Received: by 10.223.96.198 with SMTP id i6mr12106912fan.10.1297265103869; Wed, 09 Feb 2011 07:25:03 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id n2sm203790fam.28.2011.02.09.07.24.54 (version=SSLv3 cipher=RC4-MD5); Wed, 09 Feb 2011 07:25:02 -0800 (PST) Subject: Re: [PATCH v3] EHCI bus glue for on-chip PMC MSP USB controller. From: Anoop P A To: Matthieu CASTET Cc: "gregkh@suse.de" , "dbrownell@users.sourceforge.net" , "ust@denx.de" , "pkondeti@codeaurora.org" , "stern@rowland.harvard.edu" , "gadiyar@ti.com" , "alek.du@intel.com" , "jacob.jun.pan@intel.com" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "ralf@linux-mips.org" In-Reply-To: <4D52AE7E.8000907@parrot.com> References: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> <4D52AE7E.8000907@parrot.com> Content-Type: text/plain; charset="UTF-8" Date: Wed, 09 Feb 2011 21:14:56 +0530 Message-ID: <1297266296.29250.69.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29142 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2011-02-09 at 16:10 +0100, Matthieu CASTET wrote: > Anoop P.A a écrit : > > > config XPS_USB_HCD_XILINX > > diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c > > index 6fee3cd..a591890 100644 > > --- a/drivers/usb/host/ehci-hcd.c > > +++ b/drivers/usb/host/ehci-hcd.c > > @@ -262,6 +262,8 @@ static void tdi_reset (struct ehci_hcd *ehci) > > if (ehci_big_endian_mmio(ehci)) > > tmp |= USBMODE_BE; > > ehci_writel(ehci, tmp, reg_ptr); > > + if (ehci->pmc_msp_tdi) > > + usb_hcd_tdi_set_mode(ehci); > > } > This is ugly to add callback to your driver here. > How this will build on other platform, usb_hcd_tdi_set_mode is only > defined on ehci-pmcmsp.c I got that will remove it from patch and resend.the patch got carried from an older kernel :( . Thanks > > > > +void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) > > +{ > > + u8 *base; > > + u8 *statreg; > > + u8 *fiforeg; > > + u32 val; > > + struct ehci_regs *reg_base = ehci->regs; > > + > > + /* get register base */ > > + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; > > + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; > > + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; > > + > > + /* set the controller to host mode and BIG ENDIAN */ > > + ehci_writel(ehci, (USB_CTRL_MODE_HOST | USB_CTRL_MODE_BIG_ENDIAN > > + | USB_CTRL_MODE_STREAM_DISABLE), (u32 *)base); > > + > We have done that in tdi_reset, why do you do it again ? > > > Matthieu From greg@kroah.com Wed Feb 9 18:26:59 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Feb 2011 18:27:03 +0100 (CET) Received: from kroah.org ([198.145.64.141]:60232 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491785Ab1BIR07 (ORCPT ); Wed, 9 Feb 2011 18:26:59 +0100 Received: from localhost (c-71-227-141-191.hsd1.wa.comcast.net [71.227.141.191]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id 6C5EC48918; Wed, 9 Feb 2011 09:26:54 -0800 (PST) Date: Wed, 9 Feb 2011 09:20:37 -0800 From: Greg KH To: Anoop P A Cc: gregkh@suse.de, dbrownell@users.sourceforge.net, ust@denx.de, pkondeti@codeaurora.org, stern@rowland.harvard.edu, gadiyar@ti.com, alek.du@intel.com, jacob.jun.pan@intel.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v3] EHCI bus glue for on-chip PMC MSP USB controller. Message-ID: <20110209172037.GA30950@kroah.com> References: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> <20110204195624.GA27680@kroah.com> <1297260753.29250.20.camel@paanoop1-desktop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1297260753.29250.20.camel@paanoop1-desktop> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29143 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: greg@kroah.com Precedence: bulk X-list: linux-mips On Wed, Feb 09, 2011 at 07:42:33PM +0530, Anoop P A wrote: > > > +#ifdef CONFIG_MSP_HAS_DUAL_USB > > > + gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1); > > > +#endif > > > > Please don't put #defines in .c files. > You mean #ifdef ??? Yes, sorry. > > > +static int ehci_msp_suspend(struct device *dev) > > > +{ > > > + struct usb_hcd *hcd = dev_get_drvdata(dev); > > > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > > + unsigned long flags; > > > + int rc; > > > + > > > + return 0; > > > + rc = 0; > > > + > > > + if (time_before(jiffies, ehci->next_statechange)) > > > + msleep(10); > > > > Short sleep, why? > I am not very sure. Person who originally wrote this driver is > unreachable.Any potential issues?? Yes, suspend/resume time delays are not nice for some systems. I would verify that this really is necessary, and, as you are going to be the one maintaining and responsible for the code, it would be good for you to figure out exactly what it is doing, and why. > > > +static int ehci_msp_resume(struct device *dev) > > > +{ > > > + struct usb_hcd *hcd = dev_get_drvdata(dev); > > > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > > + > > > + > > > + /* maybe restore FLADJ */ > > > > Don't you know? > Not really :) Heh, you should. > > > +/* may be called without controller electrically present */ > > > +/* may be called with controller, bus, and devices active */ > > > + > > > > What may be called? > may be usb_hcd_msp_remove :) Then put it in the comment block for that function, not above it, with an extra space between it, that just causes confusion. thanks, greg k-h From ralf@duck.linux-mips.net Thu Feb 10 02:14:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 02:14:23 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39995 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491814Ab1BJBOU (ORCPT ); Thu, 10 Feb 2011 02:14:20 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1A1Elpu000308; Thu, 10 Feb 2011 02:14:47 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1A1EfKF000300; Thu, 10 Feb 2011 02:14:41 +0100 Date: Thu, 10 Feb 2011 02:14:40 +0100 From: Ralf Baechle To: Deng-Cheng Zhu Cc: a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, matt@console-pimps.org, sshtylyov@mvista.com, ddaney@caviumnetworks.com Subject: Re: [PATCH v4 1/5] MIPS/Perf-events: Work with irq_work Message-ID: <20110210011440.GA29705@linux-mips.org> References: <1295597961-7565-1-git-send-email-dengcheng.zhu@gmail.com> <1295597961-7565-2-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295597961-7565-2-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29144 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From ralf@duck.linux-mips.net Thu Feb 10 02:14:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 02:14:46 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40016 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491858Ab1BJBOe (ORCPT ); Thu, 10 Feb 2011 02:14:34 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1A1F2DT000331; Thu, 10 Feb 2011 02:15:02 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1A1F217000330; Thu, 10 Feb 2011 02:15:02 +0100 Date: Thu, 10 Feb 2011 02:15:02 +0100 From: Ralf Baechle To: Deng-Cheng Zhu Cc: a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, matt@console-pimps.org, sshtylyov@mvista.com, ddaney@caviumnetworks.com Subject: Re: [PATCH v4 2/5] MIPS/Perf-events: Work with the new PMU interface Message-ID: <20110210011502.GB29705@linux-mips.org> References: <1295597961-7565-1-git-send-email-dengcheng.zhu@gmail.com> <1295597961-7565-3-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295597961-7565-3-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29145 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From ralf@duck.linux-mips.net Thu Feb 10 02:15:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 02:15:12 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40180 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491886Ab1BJBO6 (ORCPT ); Thu, 10 Feb 2011 02:14:58 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1A1FKfD000356; Thu, 10 Feb 2011 02:15:20 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1A1FKE0000354; Thu, 10 Feb 2011 02:15:20 +0100 Date: Thu, 10 Feb 2011 02:15:20 +0100 From: Ralf Baechle To: Deng-Cheng Zhu Cc: a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, matt@console-pimps.org, sshtylyov@mvista.com, ddaney@caviumnetworks.com Subject: Re: [PATCH v4 3/5] MIPS/Perf-events: Fix event check in validate_event() Message-ID: <20110210011520.GC29705@linux-mips.org> References: <1295597961-7565-1-git-send-email-dengcheng.zhu@gmail.com> <1295597961-7565-4-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295597961-7565-4-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29146 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From ralf@duck.linux-mips.net Thu Feb 10 02:15:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 02:15:36 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40235 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491893Ab1BJBPH (ORCPT ); Thu, 10 Feb 2011 02:15:07 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1A1FZSa000386; Thu, 10 Feb 2011 02:15:35 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1A1FZIM000384; Thu, 10 Feb 2011 02:15:35 +0100 Date: Thu, 10 Feb 2011 02:15:35 +0100 From: Ralf Baechle To: Deng-Cheng Zhu Cc: a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, matt@console-pimps.org, sshtylyov@mvista.com, ddaney@caviumnetworks.com Subject: Re: [PATCH v4 4/5] MIPS/Perf-events: Work with the new callchain interface Message-ID: <20110210011534.GD29705@linux-mips.org> References: <1295597961-7565-1-git-send-email-dengcheng.zhu@gmail.com> <1295597961-7565-5-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295597961-7565-5-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29147 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From ralf@duck.linux-mips.net Thu Feb 10 02:15:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 02:16:00 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40417 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491990Ab1BJBPU (ORCPT ); Thu, 10 Feb 2011 02:15:20 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1A1FnMY000430; Thu, 10 Feb 2011 02:15:49 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1A1FmSo000428; Thu, 10 Feb 2011 02:15:48 +0100 Date: Thu, 10 Feb 2011 02:15:48 +0100 From: Ralf Baechle To: Deng-Cheng Zhu Cc: a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, matt@console-pimps.org, sshtylyov@mvista.com, ddaney@caviumnetworks.com Subject: Re: [PATCH v4 5/5] MIPS/Perf-events: Use unsigned delta for right shift in event update Message-ID: <20110210011548.GE29705@linux-mips.org> References: <1295597961-7565-1-git-send-email-dengcheng.zhu@gmail.com> <1295597961-7565-6-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295597961-7565-6-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29148 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From manuel.lauss@googlemail.com Thu Feb 10 10:07:12 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 10:07:15 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:53066 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490993Ab1BJJHM (ORCPT ); Thu, 10 Feb 2011 10:07:12 +0100 Received: by bwz5 with SMTP id 5so1758145bwz.36 for ; Thu, 10 Feb 2011 01:07:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=1DTO9EvcojE48iUKGD2x1kGcjLFKY9PXypjQei2Ij3s=; b=O90ZM5y3vZMTwoSOimOBMhSA/66olPzPbGmquUCh8PhFZ41RH7h4eIrRfRSBtFPG7H Or2PEmbr59o6dz8bmrANJa8tB8efwt/0/9ZXghVZfXFs6RVly50tVwy1slCR4rsxwQNb fORUHf1+kuH853dADcTFinbzls2UMmIvEcauk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=DkAm6dMJBFjn4qj8tRQcHMUZJaNAt3/2D+UYCD04jsb4HZJZx/0W6xiSZ5JGAflUJY Cwm8llTzasH+WuKxnicBgC9sZsGfyFwuXMNklCQxR44wrPVFW4Bp2+ot/0v6lJjd38Wa A2pNpTxMppFyNENZFNigPixbfr8Pa5BJ3gBi0= Received: by 10.204.100.70 with SMTP id x6mr6287750bkn.0.1297328826543; Thu, 10 Feb 2011 01:07:06 -0800 (PST) Received: from localhost.localdomain (178-191-14-1.adsl.highway.telekom.at [178.191.14.1]) by mx.google.com with ESMTPS id v1sm817617bkt.5.2011.02.10.01.07.05 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 10 Feb 2011 01:07:05 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: =?UTF-8?q?Ralf=20B=E4chle?= , Manuel Lauss Subject: [PATCH 0/2] Alchemy: use new irq methods Date: Thu, 10 Feb 2011 10:07:00 +0100 Message-Id: <1297328822-4621-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29149 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips These 2 patches change the core MIPS and Alchmey irq code to use the new .irq_xxx methods. The first patch is a prerequisite to turn on GENERIC_HARDIRQS_NO_DEPRECATED. I have tested it with the C0 timer and it seems to run well, however the MIPS-MT bits I cannot test. Someone with capable hardware please test! Thank you! The second patch changes the core alchemy and DB1200 board irq functions over to the new .irq_xxx ones. Run-tested on the DB1200. Manuel Lauss (2): MIPS: Convert to new irq methods. Alchemy: Convert to new irq methods. arch/mips/Kconfig | 1 + arch/mips/alchemy/common/irq.c | 83 +++++++++++++++++++----------------- arch/mips/alchemy/devboards/bcsr.c | 18 ++++---- arch/mips/kernel/irq.c | 12 ++++- arch/mips/kernel/irq_cpu.c | 42 +++++++++--------- 5 files changed, 85 insertions(+), 71 deletions(-) -- 1.7.4 From manuel.lauss@googlemail.com Thu Feb 10 10:07:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 10:07:43 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:42096 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491005Ab1BJJHM (ORCPT ); Thu, 10 Feb 2011 10:07:12 +0100 Received: by bwz5 with SMTP id 5so1758163bwz.36 for ; Thu, 10 Feb 2011 01:07:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=2o+EeHl3eo/R7IbB0zi+FPCDM55+v/NdBtMel1WlCRU=; b=ovBTtAcA38/MHmgy7J2cVjImvN4wO3HfJ/ItA6Rs5gynty4sbKB/xRI4IlTo8nn2c+ Rltx4jWpV3W4TuIZwPNym3pa5XJ/VOekFH9HoEDGWRS+rT+I7IiqSKU/YKFJ5YmQQIS4 BFpeJQ9BVeXou/QrdGFv5F0zkbhGCXp+OLRbM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=JZVjsuPFte4c3nhrB0zPHNCrvofXTq0byNAV7+v2BK93s9+xfXUBDpvfcaP5F7G3ps N+7S/ypi4xtEINAUTvBRT4xfu0OQZw1ADon9pnYKHMuQw2JGuTw1atWCpmEquiZiwFnA rNX5b6aOpbuZgvSoZiMKyBnwwFvbNX4m2kFMk= Received: by 10.204.14.14 with SMTP id e14mr1279156bka.4.1297328827490; Thu, 10 Feb 2011 01:07:07 -0800 (PST) Received: from localhost.localdomain (178-191-14-1.adsl.highway.telekom.at [178.191.14.1]) by mx.google.com with ESMTPS id v1sm817617bkt.5.2011.02.10.01.07.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 10 Feb 2011 01:07:07 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: =?UTF-8?q?Ralf=20B=E4chle?= , Manuel Lauss Subject: [PATCH 1/2] MIPS: Convert to new irq methods. Date: Thu, 10 Feb 2011 10:07:01 +0100 Message-Id: <1297328822-4621-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 In-Reply-To: <1297328822-4621-1-git-send-email-manuel.lauss@googlemail.com> References: <1297328822-4621-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29150 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Convert the core MIPS irq code to use the new .irq_xxx methods. Signed-off-by: Manuel Lauss --- Tested on DB1200 with C0 timer. The MIPS-MT bits are untested since I don't have capable hardware. arch/mips/kernel/irq.c | 12 ++++++++++-- arch/mips/kernel/irq_cpu.c | 42 +++++++++++++++++++++--------------------- 2 files changed, 31 insertions(+), 23 deletions(-) diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 4f93db5..b8112cf 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -89,6 +89,9 @@ int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, j; struct irqaction * action; + struct irq_desc *desc; + struct irq_data *data; + struct irq_chip *chip; unsigned long flags; if (i == 0) { @@ -100,9 +103,14 @@ int show_interrupts(struct seq_file *p, void *v) if (i < NR_IRQS) { raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + desc = irq_to_desc(i); + if (!desc) + goto skip; + action = desc->action; if (!action) goto skip; + data = irq_get_irq_data(i); + chip = irq_data_get_irq_chip(data); seq_printf(p, "%3d: ", i); #ifndef CONFIG_SMP seq_printf(p, "%10u ", kstat_irqs(i)); @@ -110,7 +118,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 0262abe..91a8689 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -37,25 +37,25 @@ #include #include -static inline void unmask_mips_irq(unsigned int irq) +static inline void unmask_mips_irq(struct irq_data *d) { - set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); irq_enable_hazard(); } -static inline void mask_mips_irq(unsigned int irq) +static inline void mask_mips_irq(struct irq_data *d) { - clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); irq_disable_hazard(); } static struct irq_chip mips_cpu_irq_controller = { .name = "MIPS", - .ack = mask_mips_irq, - .mask = mask_mips_irq, - .mask_ack = mask_mips_irq, - .unmask = unmask_mips_irq, - .eoi = unmask_mips_irq, + .irq_ack = mask_mips_irq, + .irq_mask = mask_mips_irq, + .irq_mask_ack = mask_mips_irq, + .irq_unmask = unmask_mips_irq, + .irq_eoi = unmask_mips_irq, }; /* @@ -65,13 +65,13 @@ static struct irq_chip mips_cpu_irq_controller = { #define unmask_mips_mt_irq unmask_mips_irq #define mask_mips_mt_irq mask_mips_irq -static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) +static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); evpe(vpflags); - unmask_mips_mt_irq(irq); + unmask_mips_mt_irq(d); return 0; } @@ -80,22 +80,22 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) * While we ack the interrupt interrupts are disabled and thus we don't need * to deal with concurrency issues. Same for mips_cpu_irq_end. */ -static void mips_mt_cpu_irq_ack(unsigned int irq) +static void mips_mt_cpu_irq_ack(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); evpe(vpflags); - mask_mips_mt_irq(irq); + mask_mips_mt_irq(d); } static struct irq_chip mips_mt_cpu_irq_controller = { .name = "MIPS", - .startup = mips_mt_cpu_irq_startup, - .ack = mips_mt_cpu_irq_ack, - .mask = mask_mips_mt_irq, - .mask_ack = mips_mt_cpu_irq_ack, - .unmask = unmask_mips_mt_irq, - .eoi = unmask_mips_mt_irq, + .irq_startup = mips_mt_cpu_irq_startup, + .irq_ack = mips_mt_cpu_irq_ack, + .irq_mask = mask_mips_mt_irq, + .irq_mask_ack = mips_mt_cpu_irq_ack, + .irq_unmask = unmask_mips_mt_irq, + .irq_eoi = unmask_mips_mt_irq, }; void __init mips_cpu_irq_init(void) -- 1.7.4 From manuel.lauss@googlemail.com Thu Feb 10 10:08:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 10:08:08 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:58517 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491009Ab1BJJHO (ORCPT ); Thu, 10 Feb 2011 10:07:14 +0100 Received: by bwz5 with SMTP id 5so1758181bwz.36 for ; Thu, 10 Feb 2011 01:07:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=hu//ZVmo3mzMJjdgUFPEC0g1/PRPDmo2C38deEz9f0M=; b=bc8iFK7r19Swr7lB2QJeyyw8jUqZ3id7CT6XWbR9ZyyLbIGUGSTcxSBb/ziXItIrm5 A2yCzIyGv73+4dD6T/K1Y9XF94gxhibD8KHMOgLWFMZqDAGd5ZFJW2a66Jv/TxgHiXIZ nDnuLR/rQCFZboovdt+l5kq78g4cjPbsABRyM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=gbKoY5yEub1z4Vcl/8Xv8lQ+lyRMx56EZiQl++6GSmpcDa842Yzzu1CGywwJViQZ/s NM/dObZUWlPxOMs/8CP+OpvZQ5RtptqGRTr70fkB+5qzAzJRGh93fsGz7a3BdRJQB3yC Uct/xyWP0NolygpKsQy/7rg3ax02bmUfzReeE= Received: by 10.204.61.199 with SMTP id u7mr1677607bkh.6.1297328828663; Thu, 10 Feb 2011 01:07:08 -0800 (PST) Received: from localhost.localdomain (178-191-14-1.adsl.highway.telekom.at [178.191.14.1]) by mx.google.com with ESMTPS id v1sm817617bkt.5.2011.02.10.01.07.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 10 Feb 2011 01:07:08 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: =?UTF-8?q?Ralf=20B=E4chle?= , Manuel Lauss Subject: [PATCH 2/2] Alchemy: Convert to new irq methods. Date: Thu, 10 Feb 2011 10:07:02 +0100 Message-Id: <1297328822-4621-3-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 In-Reply-To: <1297328822-4621-1-git-send-email-manuel.lauss@googlemail.com> References: <1297328822-4621-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29151 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Convert Alchmey core and board code to use new .irq_xxx methods. Signed-off-by: Manuel Lauss --- Run-tested on DB1200. arch/mips/Kconfig | 1 + arch/mips/alchemy/common/irq.c | 83 +++++++++++++++++++----------------- arch/mips/alchemy/devboards/bcsr.c | 18 ++++---- 3 files changed, 54 insertions(+), 48 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f5ecc05..401fc8f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -44,6 +44,7 @@ config MIPS_ALCHEMY select GENERIC_GPIO select ARCH_WANT_OPTIONAL_GPIOLIB select SYS_SUPPORTS_ZBOOT + select GENERIC_HARDIRQS_NO_DEPRECATED config AR7 bool "Texas Instruments AR7" diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 9f78ada..baef9a5 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -39,7 +39,7 @@ #include #endif -static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); +static int ic_settype(unsigned int irq, unsigned int flow_type); /* NOTE on interrupt priorities: The original writers of this code said: * @@ -218,17 +218,17 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { }; -static void au1x_ic0_unmask(unsigned int irq_nr) +static void alchemy_ic0_unmask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_MASKSET); au_writel(1 << bit, IC0_WAKESET); au_sync(); } -static void au1x_ic1_unmask(unsigned int irq_nr) +static void alchemy_ic1_unmask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_MASKSET); au_writel(1 << bit, IC1_WAKESET); @@ -236,31 +236,31 @@ static void au1x_ic1_unmask(unsigned int irq_nr) * nowhere in the current kernel sources is it disabled. --mlau */ #if defined(CONFIG_MIPS_PB1000) - if (irq_nr == AU1000_GPIO15_INT) + if (d->irq == AU1000_GPIO15_INT) au_writel(0x4000, PB1000_MDR); /* enable int */ #endif au_sync(); } -static void au1x_ic0_mask(unsigned int irq_nr) +static void alchemy_ic0_mask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_MASKCLR); au_writel(1 << bit, IC0_WAKECLR); au_sync(); } -static void au1x_ic1_mask(unsigned int irq_nr) +static void alchemy_ic1_mask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_MASKCLR); au_writel(1 << bit, IC1_WAKECLR); au_sync(); } -static void au1x_ic0_ack(unsigned int irq_nr) +static void alchemy_ic0_ack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; /* * This may assume that we don't get interrupts from @@ -271,9 +271,9 @@ static void au1x_ic0_ack(unsigned int irq_nr) au_sync(); } -static void au1x_ic1_ack(unsigned int irq_nr) +static void alchemy_ic1_ack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; /* * This may assume that we don't get interrupts from @@ -284,9 +284,9 @@ static void au1x_ic1_ack(unsigned int irq_nr) au_sync(); } -static void au1x_ic0_maskack(unsigned int irq_nr) +static void alchemy_ic0_maskack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_WAKECLR); au_writel(1 << bit, IC0_MASKCLR); @@ -295,9 +295,9 @@ static void au1x_ic0_maskack(unsigned int irq_nr) au_sync(); } -static void au1x_ic1_maskack(unsigned int irq_nr) +static void alchemy_ic1_maskack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_WAKECLR); au_writel(1 << bit, IC1_MASKCLR); @@ -306,9 +306,9 @@ static void au1x_ic1_maskack(unsigned int irq_nr) au_sync(); } -static int au1x_ic1_setwake(unsigned int irq, unsigned int on) +static int alchemy_ic1_setwake(struct irq_data *d, unsigned int on) { - int bit = irq - AU1000_INTC1_INT_BASE; + int bit = d->irq - AU1000_INTC1_INT_BASE; unsigned long wakemsk, flags; /* only GPIO 0-7 can act as wakeup source. Fortunately these @@ -330,30 +330,35 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) return 0; } +static int alchemy_ic_settype(struct irq_data *d, unsigned int flow_type) +{ + return ic_settype(d->irq, flow_type); +} + /* * irq_chips for both ICs; this way the mask handlers can be * as short as possible. */ -static struct irq_chip au1x_ic0_chip = { +static struct irq_chip alchemy_ic0_chip = { .name = "Alchemy-IC0", - .ack = au1x_ic0_ack, - .mask = au1x_ic0_mask, - .mask_ack = au1x_ic0_maskack, - .unmask = au1x_ic0_unmask, - .set_type = au1x_ic_settype, + .irq_ack = alchemy_ic0_ack, + .irq_mask = alchemy_ic0_mask, + .irq_mask_ack = alchemy_ic0_maskack, + .irq_unmask = alchemy_ic0_unmask, + .irq_set_type = alchemy_ic_settype, }; -static struct irq_chip au1x_ic1_chip = { +static struct irq_chip alchemy_ic1_chip = { .name = "Alchemy-IC1", - .ack = au1x_ic1_ack, - .mask = au1x_ic1_mask, - .mask_ack = au1x_ic1_maskack, - .unmask = au1x_ic1_unmask, - .set_type = au1x_ic_settype, - .set_wake = au1x_ic1_setwake, + .irq_ack = alchemy_ic1_ack, + .irq_mask = alchemy_ic1_mask, + .irq_mask_ack = alchemy_ic1_maskack, + .irq_unmask = alchemy_ic1_unmask, + .irq_set_type = alchemy_ic_settype, + .irq_set_wake = alchemy_ic1_setwake, }; -static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) +static int ic_settype(unsigned int irq, unsigned int flow_type) { struct irq_chip *chip; unsigned long icr[6]; @@ -362,11 +367,11 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) if (irq >= AU1000_INTC1_INT_BASE) { bit = irq - AU1000_INTC1_INT_BASE; - chip = &au1x_ic1_chip; + chip = &alchemy_ic1_chip; ic = 1; } else { bit = irq - AU1000_INTC0_INT_BASE; - chip = &au1x_ic0_chip; + chip = &alchemy_ic0_chip; ic = 0; } @@ -504,11 +509,11 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) */ for (i = AU1000_INTC0_INT_BASE; (i < AU1000_INTC0_INT_BASE + 32); i++) - au1x_ic_settype(i, IRQ_TYPE_NONE); + ic_settype(i, IRQ_TYPE_NONE); for (i = AU1000_INTC1_INT_BASE; (i < AU1000_INTC1_INT_BASE + 32); i++) - au1x_ic_settype(i, IRQ_TYPE_NONE); + ic_settype(i, IRQ_TYPE_NONE); /* * Initialize IC0, which is fixed per processor. @@ -526,7 +531,7 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) au_writel(1 << bit, IC0_ASSIGNSET); } - au1x_ic_settype(irq_nr, map->im_type); + ic_settype(irq_nr, map->im_type); ++map; } diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index c52af88..f91c43a 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -97,26 +97,26 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) * CPLD generates tons of spurious interrupts (at least on my DB1200). * -- mlau */ -static void bcsr_irq_mask(unsigned int irq_nr) +static void bcsr_irq_mask(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); wmb(); } -static void bcsr_irq_maskack(unsigned int irq_nr) +static void bcsr_irq_maskack(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ wmb(); } -static void bcsr_irq_unmask(unsigned int irq_nr) +static void bcsr_irq_unmask(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTSET); __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); wmb(); @@ -124,9 +124,9 @@ static void bcsr_irq_unmask(unsigned int irq_nr) static struct irq_chip bcsr_irq_type = { .name = "CPLD", - .mask = bcsr_irq_mask, - .mask_ack = bcsr_irq_maskack, - .unmask = bcsr_irq_unmask, + .irq_mask = bcsr_irq_mask, + .irq_mask_ack = bcsr_irq_maskack, + .irq_unmask = bcsr_irq_unmask, }; void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) -- 1.7.4 From manuel.lauss@googlemail.com Thu Feb 10 15:17:18 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 15:17:21 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:42041 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491025Ab1BJORS (ORCPT ); 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Thu, 10 Feb 2011 06:17:12 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH RESEND] MIPS: Alchemy: update inlinable GPIO API Date: Thu, 10 Feb 2011 15:17:07 +0100 Message-Id: <1297347429-18215-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29152 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The GPIO API has grown a few new functions, add the missing ones to the other inlinables. Signed-off-by: Manuel Lauss --- arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 35 +++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 62d2f13..f26bfe7 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -556,6 +556,16 @@ static inline void gpio_set_value(int gpio, int v) alchemy_gpio_set_value(gpio, v); } +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + static inline int gpio_is_valid(int gpio) { return alchemy_gpio_is_valid(gpio); @@ -585,6 +595,31 @@ static inline void gpio_free(unsigned gpio) { } +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ -- 1.7.4 From manuel.lauss@googlemail.com Thu Feb 10 15:17:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 15:17:44 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:47832 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491814Ab1BJORV (ORCPT ); Thu, 10 Feb 2011 15:17:21 +0100 Received: by fxm19 with SMTP id 19so1501541fxm.36 for ; Thu, 10 Feb 2011 06:17:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=8gk8PV5Q2SillZvZ8W98zFlyBu0r1L9d5dUB+Y/tWmk=; b=A5Jy8uI2WKO4OtFy0nn3mJh4a5zwPaensWWGWqwPw50GMW11FISmGDmnq/u/m73CV3 suok6QB49X8R4i/HrgTMI7oR0W1QVmcsNP5lv+DVyfc1LJnCAZ786Kss4EMSg/fmkiLF 5IvKxA5VLWCCj8BpEZ37NFPxoKVQfhUHoL9s0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=LJrGOa6nkLK5Lw3A0ExNCVYrA5YHGMmI/D/Fk02seqycPMZjjn7WuJsF8wPMupep/2 KyBWUwSN7bnwdZoFm77ZMQoNvWETTmxwphkA6CZSZ6z7j4/fKDttFA03Ve5ihHrcn95x CV4PfN0b6qhLeSlkVeLCypTjnJWjxLnAbqukE= Received: by 10.223.107.133 with SMTP id b5mr4169209fap.87.1297347435214; Thu, 10 Feb 2011 06:17:15 -0800 (PST) Received: from localhost.localdomain (178-191-11-137.adsl.highway.telekom.at [178.191.11.137]) by mx.google.com with ESMTPS id n1sm36732fam.16.2011.02.10.06.17.13 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Feb 2011 06:17:14 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: DB1200: Set Config_OD for improved stability. Date: Thu, 10 Feb 2011 15:17:08 +0100 Message-Id: <1297347429-18215-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 In-Reply-To: <1297347429-18215-1-git-send-email-manuel.lauss@googlemail.com> References: <1297347429-18215-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29153 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Setting Config_OD gets rid of a _LOT_ of spurious CPLD interrupts, but also decreases overall performance a bit. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/db1200/setup.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index 8876195..a3729c9 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -23,6 +23,13 @@ void __init board_setup(void) unsigned long freq0, clksrc, div, pfc; unsigned short whoami; + /* Set Config_OD (disable overlapping bus transaction): + * This gets rid of a _lot_ of spurious interrupts (especially + * wrt. IDE); but incurs ~10% performance hit in some + * cpu-bound applications. + */ + set_c0_config(1 << 19); + bcsr_init(DB1200_BCSR_PHYS_ADDR, DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); -- 1.7.4 From manuel.lauss@googlemail.com Thu Feb 10 15:18:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 15:18:09 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:42041 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491833Ab1BJORW (ORCPT ); Thu, 10 Feb 2011 15:17:22 +0100 Received: by mail-fx0-f49.google.com with SMTP id 19so1501515fxm.36 for ; Thu, 10 Feb 2011 06:17:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=Ru8O+rCIZ8AaJyUVKIiPGFWHoYK9T1SQmLnfl4sr9KA=; b=WuUY6Lm0oyfFukpC5HEUp/T1p/XmMcI4J/pX0Ds9rt7+vVl+jC44N2fqAEW/RaXEO1 SBqMoEhDm9aCtrWZfO4TH2mIYiYYKRjeCz/pUo3nVd8uLPjlaPKks29BMyoCVuyECEqn e7STvWdZ63/NhBrsQljYsk9w5HbLcwBu/+TAk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=O02H6+tFeEMoMoOAK8f0imqnxJHhofcPjT/wXM3bCNa/u6IFfI2BPuosvq6KVtzRER l982jAkLQ/UfDriIffsCHagcJHK8QI2GE8OeXzSgxrwp8vBEhMYGmBdZm7f60s7urafJ DlK74wxQU+zysp17tP0ZMYwkkGemhd8u0kWQs= Received: by 10.223.72.9 with SMTP id k9mr10889444faj.93.1297347437467; Thu, 10 Feb 2011 06:17:17 -0800 (PST) Received: from localhost.localdomain (178-191-11-137.adsl.highway.telekom.at [178.191.11.137]) by mx.google.com with ESMTPS id n1sm36732fam.16.2011.02.10.06.17.15 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Feb 2011 06:17:16 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] Alchemy: irq: replace au_readl/writel accessors. Date: Thu, 10 Feb 2011 15:17:09 +0100 Message-Id: <1297347429-18215-3-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 In-Reply-To: <1297347429-18215-1-git-send-email-manuel.lauss@googlemail.com> References: <1297347429-18215-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29154 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips replace au_readl/au_writel with __raw_readl/__raw_writel; this also gives the opportunity to clean up the IC-related #defines a bit. Signed-off-by: Manuel Lauss --- Depends on patch "Alchemy: Convert to new irq methods". arch/mips/alchemy/common/irq.c | 249 +++++++++++++++------------- arch/mips/include/asm/mach-au1x00/au1000.h | 120 +------------- 2 files changed, 138 insertions(+), 231 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index baef9a5..28a86fb 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -39,6 +39,36 @@ #include #endif +/* Interrupt Controller register offsets */ +#define IC_CFG0RD 0x40 +#define IC_CFG0SET 0x40 +#define IC_CFG0CLR 0x44 +#define IC_CFG1RD 0x48 +#define IC_CFG1SET 0x48 +#define IC_CFG1CLR 0x4C +#define IC_CFG2RD 0x50 +#define IC_CFG2SET 0x50 +#define IC_CFG2CLR 0x54 +#define IC_REQ0INT 0x54 +#define IC_SRCRD 0x58 +#define IC_SRCSET 0x58 +#define IC_SRCCLR 0x5C +#define IC_REQ1INT 0x5C +#define IC_ASSIGNRD 0x60 +#define IC_ASSIGNSET 0x60 +#define IC_ASSIGNCLR 0x64 +#define IC_WAKERD 0x68 +#define IC_WAKESET 0x68 +#define IC_WAKECLR 0x6C +#define IC_MASKRD 0x70 +#define IC_MASKSET 0x70 +#define IC_MASKCLR 0x74 +#define IC_RISINGRD 0x78 +#define IC_RISINGCLR 0x78 +#define IC_FALLINGRD 0x7C +#define IC_FALLINGCLR 0x7C +#define IC_TESTBIT 0x80 + static int ic_settype(unsigned int irq, unsigned int flow_type); /* NOTE on interrupt priorities: The original writers of this code said: @@ -221,89 +251,101 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { static void alchemy_ic0_unmask(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; - au_writel(1 << bit, IC0_MASKSET); - au_writel(1 << bit, IC0_WAKESET); - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); + + __raw_writel(1 << bit, base + IC_MASKSET); + __raw_writel(1 << bit, base + IC_WAKESET); + wmb(); } static void alchemy_ic1_unmask(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; - au_writel(1 << bit, IC1_MASKSET); - au_writel(1 << bit, IC1_WAKESET); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); + + __raw_writel(1 << bit, base + IC_MASKSET); + __raw_writel(1 << bit, base + IC_WAKESET); /* very hacky. does the pb1000 cpld auto-disable this int? * nowhere in the current kernel sources is it disabled. --mlau */ #if defined(CONFIG_MIPS_PB1000) if (d->irq == AU1000_GPIO15_INT) - au_writel(0x4000, PB1000_MDR); /* enable int */ + __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */ #endif - au_sync(); + wmb(); } static void alchemy_ic0_mask(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; - au_writel(1 << bit, IC0_MASKCLR); - au_writel(1 << bit, IC0_WAKECLR); - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); + + __raw_writel(1 << bit, base + IC_MASKCLR); + __raw_writel(1 << bit, base + IC_WAKECLR); + wmb(); } static void alchemy_ic1_mask(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; - au_writel(1 << bit, IC1_MASKCLR); - au_writel(1 << bit, IC1_WAKECLR); - au_sync(); + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); + + __raw_writel(1 << bit, base + IC_MASKCLR); + __raw_writel(1 << bit, base + IC_WAKECLR); + wmb(); } static void alchemy_ic0_ack(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); /* * This may assume that we don't get interrupts from * both edges at once, or if we do, that we don't care. */ - au_writel(1 << bit, IC0_FALLINGCLR); - au_writel(1 << bit, IC0_RISINGCLR); - au_sync(); + __raw_writel(1 << bit, base + IC_FALLINGCLR); + __raw_writel(1 << bit, base + IC_RISINGCLR); + wmb(); } static void alchemy_ic1_ack(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); /* * This may assume that we don't get interrupts from * both edges at once, or if we do, that we don't care. */ - au_writel(1 << bit, IC1_FALLINGCLR); - au_writel(1 << bit, IC1_RISINGCLR); - au_sync(); + __raw_writel(1 << bit, base + IC_FALLINGCLR); + __raw_writel(1 << bit, base + IC_RISINGCLR); + wmb(); } static void alchemy_ic0_maskack(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); - au_writel(1 << bit, IC0_WAKECLR); - au_writel(1 << bit, IC0_MASKCLR); - au_writel(1 << bit, IC0_RISINGCLR); - au_writel(1 << bit, IC0_FALLINGCLR); - au_sync(); + __raw_writel(1 << bit, base + IC_WAKECLR); + __raw_writel(1 << bit, base + IC_MASKCLR); + __raw_writel(1 << bit, base + IC_RISINGCLR); + __raw_writel(1 << bit, base + IC_FALLINGCLR); + wmb(); } static void alchemy_ic1_maskack(struct irq_data *d) { unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); - au_writel(1 << bit, IC1_WAKECLR); - au_writel(1 << bit, IC1_MASKCLR); - au_writel(1 << bit, IC1_RISINGCLR); - au_writel(1 << bit, IC1_FALLINGCLR); - au_sync(); + __raw_writel(1 << bit, base + IC_WAKECLR); + __raw_writel(1 << bit, base + IC_MASKCLR); + __raw_writel(1 << bit, base + IC_RISINGCLR); + __raw_writel(1 << bit, base + IC_FALLINGCLR); + wmb(); } static int alchemy_ic1_setwake(struct irq_data *d, unsigned int on) @@ -318,13 +360,13 @@ static int alchemy_ic1_setwake(struct irq_data *d, unsigned int on) return -EINVAL; local_irq_save(flags); - wakemsk = au_readl(SYS_WAKEMSK); + wakemsk = __raw_readl((void __iomem *)SYS_WAKEMSK); if (on) wakemsk |= 1 << bit; else wakemsk &= ~(1 << bit); - au_writel(wakemsk, SYS_WAKEMSK); - au_sync(); + __raw_writel(wakemsk, (void __iomem *)SYS_WAKEMSK); + wmb(); local_irq_restore(flags); return 0; @@ -361,79 +403,72 @@ static struct irq_chip alchemy_ic1_chip = { static int ic_settype(unsigned int irq, unsigned int flow_type) { struct irq_chip *chip; - unsigned long icr[6]; - unsigned int bit, ic; + unsigned int bit; + void __iomem *base; int ret; if (irq >= AU1000_INTC1_INT_BASE) { bit = irq - AU1000_INTC1_INT_BASE; chip = &alchemy_ic1_chip; - ic = 1; + base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); } else { bit = irq - AU1000_INTC0_INT_BASE; chip = &alchemy_ic0_chip; - ic = 0; + base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); } if (bit > 31) return -EINVAL; - icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET; - icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET; - icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET; - icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR; - icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR; - icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR; - ret = 0; switch (flow_type) { /* cfgregs 2:1:0 */ case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[0]); + __raw_writel(1 << bit, base + IC_CFG2CLR); + __raw_writel(1 << bit, base + IC_CFG1CLR); + __raw_writel(1 << bit, base + IC_CFG0SET); set_irq_chip_and_handler_name(irq, chip, handle_edge_irq, "riseedge"); break; case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[3]); + __raw_writel(1 << bit, base + IC_CFG2CLR); + __raw_writel(1 << bit, base + IC_CFG1SET); + __raw_writel(1 << bit, base + IC_CFG0CLR); set_irq_chip_and_handler_name(irq, chip, handle_edge_irq, "falledge"); break; case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[0]); + __raw_writel(1 << bit, base + IC_CFG2CLR); + __raw_writel(1 << bit, base + IC_CFG1SET); + __raw_writel(1 << bit, base + IC_CFG0SET); set_irq_chip_and_handler_name(irq, chip, handle_edge_irq, "bothedge"); break; case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ - au_writel(1 << bit, icr[2]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[0]); + __raw_writel(1 << bit, base + IC_CFG2SET); + __raw_writel(1 << bit, base + IC_CFG1CLR); + __raw_writel(1 << bit, base + IC_CFG0SET); set_irq_chip_and_handler_name(irq, chip, handle_level_irq, "hilevel"); break; case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ - au_writel(1 << bit, icr[2]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[3]); + __raw_writel(1 << bit, base + IC_CFG2SET); + __raw_writel(1 << bit, base + IC_CFG1SET); + __raw_writel(1 << bit, base + IC_CFG0CLR); set_irq_chip_and_handler_name(irq, chip, handle_level_irq, "lowlevel"); break; case IRQ_TYPE_NONE: /* 0:0:0 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[3]); + __raw_writel(1 << bit, base + IC_CFG2CLR); + __raw_writel(1 << bit, base + IC_CFG1CLR); + __raw_writel(1 << bit, base + IC_CFG0CLR); /* set at least chip so we can call set_irq_type() on it */ set_irq_chip(irq, chip); break; default: ret = -EINVAL; } - au_sync(); + wmb(); return ret; } @@ -447,21 +482,21 @@ asmlinkage void plat_irq_dispatch(void) off = MIPS_CPU_IRQ_BASE + 7; goto handle; } else if (pending & CAUSEF_IP2) { - s = IC0_REQ0INT; + s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT; off = AU1000_INTC0_INT_BASE; } else if (pending & CAUSEF_IP3) { - s = IC0_REQ1INT; + s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT; off = AU1000_INTC0_INT_BASE; } else if (pending & CAUSEF_IP4) { - s = IC1_REQ0INT; + s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT; off = AU1000_INTC1_INT_BASE; } else if (pending & CAUSEF_IP5) { - s = IC1_REQ1INT; + s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT; off = AU1000_INTC1_INT_BASE; } else goto spurious; - s = au_readl(s); + s = __raw_readl((void __iomem *)s); if (unlikely(!s)) { spurious: spurious_interrupt(); @@ -472,48 +507,41 @@ handle: do_IRQ(off); } +static inline void ic_init(void __iomem *base) +{ + /* initialize interrupt controller to a safe state */ + __raw_writel(0xffffffff, base + IC_CFG0CLR); + __raw_writel(0xffffffff, base + IC_CFG1CLR); + __raw_writel(0xffffffff, base + IC_CFG2CLR); + __raw_writel(0xffffffff, base + IC_MASKCLR); + __raw_writel(0xffffffff, base + IC_ASSIGNCLR); + __raw_writel(0xffffffff, base + IC_WAKECLR); + __raw_writel(0xffffffff, base + IC_SRCSET); + __raw_writel(0xffffffff, base + IC_FALLINGCLR); + __raw_writel(0xffffffff, base + IC_RISINGCLR); + __raw_writel(0x00000000, base + IC_TESTBIT); + wmb(); +} + static void __init au1000_init_irq(struct au1xxx_irqmap *map) { unsigned int bit, irq_nr; - int i; - - /* - * Initialize interrupt controllers to a safe state. - */ - au_writel(0xffffffff, IC0_CFG0CLR); - au_writel(0xffffffff, IC0_CFG1CLR); - au_writel(0xffffffff, IC0_CFG2CLR); - au_writel(0xffffffff, IC0_MASKCLR); - au_writel(0xffffffff, IC0_ASSIGNCLR); - au_writel(0xffffffff, IC0_WAKECLR); - au_writel(0xffffffff, IC0_SRCSET); - au_writel(0xffffffff, IC0_FALLINGCLR); - au_writel(0xffffffff, IC0_RISINGCLR); - au_writel(0x00000000, IC0_TESTBIT); - - au_writel(0xffffffff, IC1_CFG0CLR); - au_writel(0xffffffff, IC1_CFG1CLR); - au_writel(0xffffffff, IC1_CFG2CLR); - au_writel(0xffffffff, IC1_MASKCLR); - au_writel(0xffffffff, IC1_ASSIGNCLR); - au_writel(0xffffffff, IC1_WAKECLR); - au_writel(0xffffffff, IC1_SRCSET); - au_writel(0xffffffff, IC1_FALLINGCLR); - au_writel(0xffffffff, IC1_RISINGCLR); - au_writel(0x00000000, IC1_TESTBIT); + void __iomem *base; + ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); + ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); mips_cpu_irq_init(); /* register all 64 possible IC0+IC1 irq sources as type "none". * Use set_irq_type() to set edge/level behaviour at runtime. */ - for (i = AU1000_INTC0_INT_BASE; - (i < AU1000_INTC0_INT_BASE + 32); i++) - ic_settype(i, IRQ_TYPE_NONE); + for (irq_nr = AU1000_INTC0_INT_BASE; + (irq_nr < AU1000_INTC0_INT_BASE + 32); irq_nr++) + ic_settype(irq_nr, IRQ_TYPE_NONE); - for (i = AU1000_INTC1_INT_BASE; - (i < AU1000_INTC1_INT_BASE + 32); i++) - ic_settype(i, IRQ_TYPE_NONE); + for (irq_nr = AU1000_INTC1_INT_BASE; + (irq_nr < AU1000_INTC1_INT_BASE + 32); irq_nr++) + ic_settype(irq_nr, IRQ_TYPE_NONE); /* * Initialize IC0, which is fixed per processor. @@ -523,13 +551,13 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) if (irq_nr >= AU1000_INTC1_INT_BASE) { bit = irq_nr - AU1000_INTC1_INT_BASE; - if (map->im_request) - au_writel(1 << bit, IC1_ASSIGNSET); + base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); } else { bit = irq_nr - AU1000_INTC0_INT_BASE; - if (map->im_request) - au_writel(1 << bit, IC0_ASSIGNSET); + base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); } + if (map->im_request) + __raw_writel(1 << bit, base + IC_ASSIGNSET); ic_settype(irq_nr, map->im_type); ++map; @@ -586,17 +614,8 @@ static int alchemy_ic_resume(struct sys_device *dev) struct alchemy_ic_sysdev *icdev = container_of(dev, struct alchemy_ic_sysdev, sysdev); - __raw_writel(0xffffffff, icdev->base + IC_MASKCLR); - __raw_writel(0xffffffff, icdev->base + IC_CFG0CLR); - __raw_writel(0xffffffff, icdev->base + IC_CFG1CLR); - __raw_writel(0xffffffff, icdev->base + IC_CFG2CLR); - __raw_writel(0xffffffff, icdev->base + IC_SRCCLR); - __raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR); - __raw_writel(0xffffffff, icdev->base + IC_WAKECLR); - __raw_writel(0xffffffff, icdev->base + IC_RISINGCLR); - __raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR); - __raw_writel(0x00000000, icdev->base + IC_TESTBIT); - wmb(); + ic_init(icdev->base); + __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET); __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET); __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET); @@ -620,7 +639,7 @@ static struct sysdev_class alchemy_ic_sysdev_class = { static int __init alchemy_ic_sysdev_init(void) { struct alchemy_ic_sysdev *icdev; - unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR }; + unsigned long icbase[2] = { AU1000_IC0_PHYS_ADDR, AU1000_IC1_PHYS_ADDR }; int err, i; err = sysdev_class_register(&alchemy_ic_sysdev_class); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index a697661..f11e9d9 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -632,6 +632,10 @@ enum soc_au1200_ints { * Physical base addresses for integrated peripherals */ +#define AU1000_IC0_PHYS_ADDR 0x10400000 +#define AU1000_IC1_PHYS_ADDR 0x11800000 + + #ifdef CONFIG_SOC_AU1000 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 @@ -643,8 +647,6 @@ enum soc_au1200_ints { #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 @@ -680,8 +682,6 @@ enum soc_au1200_ints { #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 @@ -718,10 +718,8 @@ enum soc_au1200_ints { #define DMA5_PHYS_ADDR 0x14002500 #define DMA6_PHYS_ADDR 0x14002600 #define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 #define SD0_PHYS_ADDR 0x10600000 #define SD1_PHYS_ADDR 0x10680000 -#define IC1_PHYS_ADDR 0x11800000 #define AC97_PHYS_ADDR 0x10000000 #define USBH_PHYS_ADDR 0x10100000 #define USBD_PHYS_ADDR 0x10200000 @@ -749,8 +747,6 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1550 #define MEM_PHYS_ADDR 0x14000000 #define STATIC_MEM_PHYS_ADDR 0x14001000 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 #define USBH_PHYS_ADDR 0x14020000 #define USBD_PHYS_ADDR 0x10200000 #define PCI_PHYS_ADDR 0x14005000 @@ -786,8 +782,6 @@ enum soc_au1200_ints { #define STATIC_MEM_PHYS_ADDR 0x14001000 #define AES_PHYS_ADDR 0x10300000 #define CIM_PHYS_ADDR 0x14004000 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 #define USBM_PHYS_ADDR 0x14020000 #define USBH_PHYS_ADDR 0x14020100 #define UART0_PHYS_ADDR 0x11100000 @@ -835,112 +829,6 @@ enum soc_au1200_ints { #endif -/* Interrupt Controller register offsets */ -#define IC_CFG0RD 0x40 -#define IC_CFG0SET 0x40 -#define IC_CFG0CLR 0x44 -#define IC_CFG1RD 0x48 -#define IC_CFG1SET 0x48 -#define IC_CFG1CLR 0x4C -#define IC_CFG2RD 0x50 -#define IC_CFG2SET 0x50 -#define IC_CFG2CLR 0x54 -#define IC_REQ0INT 0x54 -#define IC_SRCRD 0x58 -#define IC_SRCSET 0x58 -#define IC_SRCCLR 0x5C -#define IC_REQ1INT 0x5C -#define IC_ASSIGNRD 0x60 -#define IC_ASSIGNSET 0x60 -#define IC_ASSIGNCLR 0x64 -#define IC_WAKERD 0x68 -#define IC_WAKESET 0x68 -#define IC_WAKECLR 0x6C -#define IC_MASKRD 0x70 -#define IC_MASKSET 0x70 -#define IC_MASKCLR 0x74 -#define IC_RISINGRD 0x78 -#define IC_RISINGCLR 0x78 -#define IC_FALLINGRD 0x7C -#define IC_FALLINGCLR 0x7C -#define IC_TESTBIT 0x80 - - -/* Interrupt Controller 0 */ -#define IC0_CFG0RD 0xB0400040 -#define IC0_CFG0SET 0xB0400040 -#define IC0_CFG0CLR 0xB0400044 - -#define IC0_CFG1RD 0xB0400048 -#define IC0_CFG1SET 0xB0400048 -#define IC0_CFG1CLR 0xB040004C - -#define IC0_CFG2RD 0xB0400050 -#define IC0_CFG2SET 0xB0400050 -#define IC0_CFG2CLR 0xB0400054 - -#define IC0_REQ0INT 0xB0400054 -#define IC0_SRCRD 0xB0400058 -#define IC0_SRCSET 0xB0400058 -#define IC0_SRCCLR 0xB040005C -#define IC0_REQ1INT 0xB040005C - -#define IC0_ASSIGNRD 0xB0400060 -#define IC0_ASSIGNSET 0xB0400060 -#define IC0_ASSIGNCLR 0xB0400064 - -#define IC0_WAKERD 0xB0400068 -#define IC0_WAKESET 0xB0400068 -#define IC0_WAKECLR 0xB040006C - -#define IC0_MASKRD 0xB0400070 -#define IC0_MASKSET 0xB0400070 -#define IC0_MASKCLR 0xB0400074 - -#define IC0_RISINGRD 0xB0400078 -#define IC0_RISINGCLR 0xB0400078 -#define IC0_FALLINGRD 0xB040007C -#define IC0_FALLINGCLR 0xB040007C - -#define IC0_TESTBIT 0xB0400080 - -/* Interrupt Controller 1 */ -#define IC1_CFG0RD 0xB1800040 -#define IC1_CFG0SET 0xB1800040 -#define IC1_CFG0CLR 0xB1800044 - -#define IC1_CFG1RD 0xB1800048 -#define IC1_CFG1SET 0xB1800048 -#define IC1_CFG1CLR 0xB180004C - -#define IC1_CFG2RD 0xB1800050 -#define IC1_CFG2SET 0xB1800050 -#define IC1_CFG2CLR 0xB1800054 - -#define IC1_REQ0INT 0xB1800054 -#define IC1_SRCRD 0xB1800058 -#define IC1_SRCSET 0xB1800058 -#define IC1_SRCCLR 0xB180005C -#define IC1_REQ1INT 0xB180005C - -#define IC1_ASSIGNRD 0xB1800060 -#define IC1_ASSIGNSET 0xB1800060 -#define IC1_ASSIGNCLR 0xB1800064 - -#define IC1_WAKERD 0xB1800068 -#define IC1_WAKESET 0xB1800068 -#define IC1_WAKECLR 0xB180006C - -#define IC1_MASKRD 0xB1800070 -#define IC1_MASKSET 0xB1800070 -#define IC1_MASKCLR 0xB1800074 - -#define IC1_RISINGRD 0xB1800078 -#define IC1_RISINGCLR 0xB1800078 -#define IC1_FALLINGRD 0xB180007C -#define IC1_FALLINGCLR 0xB180007C - -#define IC1_TESTBIT 0xB1800080 /* Au1000 */ -- 1.7.4 From sshtylyov@mvista.com Thu Feb 10 19:16:26 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 19:16:29 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:33078 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491123Ab1BJSQ0 (ORCPT ); Thu, 10 Feb 2011 19:16:26 +0100 Received: by bwz5 with SMTP id 5so2237619bwz.36 for ; Thu, 10 Feb 2011 10:16:20 -0800 (PST) Received: by 10.204.72.199 with SMTP id n7mr14301227bkj.8.1297361780476; Thu, 10 Feb 2011 10:16:20 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id v25sm205978bkt.6.2011.02.10.10.16.18 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Feb 2011 10:16:19 -0800 (PST) Message-ID: <4D542B1D.1060407@mvista.com> Date: Thu, 10 Feb 2011 21:14:53 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Manuel Lauss CC: Linux-MIPS Subject: Re: [PATCH] MIPS: DB1200: Set Config_OD for improved stability. References: <1297347429-18215-1-git-send-email-manuel.lauss@googlemail.com> <1297347429-18215-2-git-send-email-manuel.lauss@googlemail.com> In-Reply-To: <1297347429-18215-2-git-send-email-manuel.lauss@googlemail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29155 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Manuel Lauss wrote: > Setting Config_OD gets rid of a _LOT_ of spurious CPLD interrupts, > but also decreases overall performance a bit. > Signed-off-by: Manuel Lauss [...] > diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c > index 8876195..a3729c9 100644 > --- a/arch/mips/alchemy/devboards/db1200/setup.c > +++ b/arch/mips/alchemy/devboards/db1200/setup.c > @@ -23,6 +23,13 @@ void __init board_setup(void) > unsigned long freq0, clksrc, div, pfc; > unsigned short whoami; > > + /* Set Config_OD (disable overlapping bus transaction): The bit is called Config[OD] by other Alchemy code. You just should add your Au1200 revision to au1xxx_cpu_needs_config_od() in so that plat_mem_setup() automatically sets the bit (just after it calls board_setup()); Au1200 rev. AC should have it set already... > + * This gets rid of a _lot_ of spurious interrupts (especially > + * wrt. IDE); but incurs ~10% performance hit in some > + * cpu-bound applications. > + */ > + set_c0_config(1 << 19); > + > bcsr_init(DB1200_BCSR_PHYS_ADDR, > DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); > WBR, Sergei From sshtylyov@mvista.com Thu Feb 10 19:27:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Feb 2011 19:27:12 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:64255 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491123Ab1BJS1J (ORCPT ); Thu, 10 Feb 2011 19:27:09 +0100 Received: by bwz5 with SMTP id 5so2246801bwz.36 for ; Thu, 10 Feb 2011 10:27:04 -0800 (PST) Received: by 10.204.102.19 with SMTP id e19mr14519203bko.35.1297362423959; Thu, 10 Feb 2011 10:27:03 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id u23sm208798bkw.21.2011.02.10.10.27.02 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Feb 2011 10:27:02 -0800 (PST) Message-ID: <4D542DA1.5020705@mvista.com> Date: Thu, 10 Feb 2011 21:25:37 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Manuel Lauss CC: Linux-MIPS Subject: Re: [PATCH] MIPS: DB1200: Set Config_OD for improved stability. References: <1297347429-18215-1-git-send-email-manuel.lauss@googlemail.com> <1297347429-18215-2-git-send-email-manuel.lauss@googlemail.com> <4D542B1D.1060407@mvista.com> In-Reply-To: <4D542B1D.1060407@mvista.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29156 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips I wrote: >> Setting Config_OD gets rid of a _LOT_ of spurious CPLD interrupts, >> but also decreases overall performance a bit. >> Signed-off-by: Manuel Lauss > [...] >> diff --git a/arch/mips/alchemy/devboards/db1200/setup.c >> b/arch/mips/alchemy/devboards/db1200/setup.c >> index 8876195..a3729c9 100644 >> --- a/arch/mips/alchemy/devboards/db1200/setup.c >> +++ b/arch/mips/alchemy/devboards/db1200/setup.c >> @@ -23,6 +23,13 @@ void __init board_setup(void) >> unsigned long freq0, clksrc, div, pfc; >> unsigned short whoami; >> >> + /* Set Config_OD (disable overlapping bus transaction): > The bit is called Config[OD] by other Alchemy code. > You just should add your Au1200 revision to > au1xxx_cpu_needs_config_od() in so that > plat_mem_setup() automatically sets the bit (just after it calls > board_setup()); Au1200 rev. AC should have it set already... Forgot to add that if you don't do it, the code in plat_mem_setup() will clear the bit after you've set it. WBR, Sergei From ralf@duck.linux-mips.net Fri Feb 11 00:23:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 00:23:05 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47599 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491172Ab1BJXXC (ORCPT ); Fri, 11 Feb 2011 00:23:02 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1ANNgM4017865; Fri, 11 Feb 2011 00:23:42 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1ANNfOJ017861; Fri, 11 Feb 2011 00:23:41 +0100 Date: Fri, 11 Feb 2011 00:23:40 +0100 From: Ralf Baechle To: Mikael Starvik Cc: "linux-mips@linux-mips.org" Subject: Re: Highmem in architechtures with cache alias Message-ID: <20110210232340.GA13731@linux-mips.org> References: <4BEA3FF3CAA35E408EA55C7BE2E61D055C60823A4F@xmail3.se.axis.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4BEA3FF3CAA35E408EA55C7BE2E61D055C60823A4F@xmail3.se.axis.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29157 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 07, 2011 at 10:02:34AM +0100, Mikael Starvik wrote: > It is clearly stated in http://www.linux-mips.org/wiki/Highmem that the > MIPS kernel can´t user highmem on machines with cache aliasing and I > understand the reason. So, what is the solution here? Switch to 16k > pages? Or are there other ways to get more memory on a machine with cache > aliases? This is an implementation restriction. I did the original MIPS highmem work in early 2002 for a company which didn't want to be the first through the 64-bit minefield; I was using a Sibyte Swarm evaluation board back then and its SB1 cores happen not to have aliases so I was able to take a few short cuts. For many years after this virtually everybody was wise enough to go for 64-bit hardware and kernel for large memory systems so interest in removing this restriction only came up like last year. 16k pages are probably a good idea anyway; in most cases they provide a significant performance boost. Details depend on the exact workload. However I should mention that the combination of page sizes other than 4k with highmem also is untested afaics. The solution for the alias problem is the right mix of cacheflushes at the right places and a strategy to avoid aliases where possible - business as usual. ARM already supports highmem with aliases. Ralf From manuel.lauss@googlemail.com Fri Feb 11 09:47:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 09:47:58 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:45137 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491001Ab1BKIrz (ORCPT ); Fri, 11 Feb 2011 09:47:55 +0100 Received: by bwz5 with SMTP id 5so2803118bwz.36 for ; Fri, 11 Feb 2011 00:47:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=2o+EeHl3eo/R7IbB0zi+FPCDM55+v/NdBtMel1WlCRU=; b=BaLkHWJQH5+aaSi7/A2IcGYUmizBYuq1e9pH83fLQlJYXHNLdyVWKW9dr4flY7Us3o pY++5bHtqcijJH8gBg5jzINTgI2ooNSMSXXNotpNnkZrct6xL65bmJ4kCkYSFNcAx4Id Ofzln5BvXCslferEenOAfG/nn9nL2wCKFkRrs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=HqtvFSGVUMRXEZfwoxroV+Hf2/wJD7Ci4CsXzmxvE+KU0bPQXwo2erofOJp5u4AmG9 RkYCqPZ98sRNiFByt3nhhVfiVfSyAuXLwEwEqHFmHWslvSnJ9s7pjTtY7Pnk7Mgw075g EDpuob/NSPMQkACBk1lUZqTYm0UhClEmebS9E= Received: by 10.204.70.136 with SMTP id d8mr2417117bkj.96.1297414069393; Fri, 11 Feb 2011 00:47:49 -0800 (PST) Received: from localhost.localdomain (188-22-147-70.adsl.highway.telekom.at [188.22.147.70]) by mx.google.com with ESMTPS id v25sm290909bkt.18.2011.02.11.00.47.48 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Feb 2011 00:47:49 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Ralf Baechle , Manuel Lauss Subject: [PATCH RESEND 1/2] MIPS: Convert to new irq methods. Date: Fri, 11 Feb 2011 09:47:43 +0100 Message-Id: <1297414064-3446-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 In-Reply-To: <1297414064-3446-1-git-send-email-manuel.lauss@googlemail.com> References: <1297414064-3446-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29158 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Convert the core MIPS irq code to use the new .irq_xxx methods. Signed-off-by: Manuel Lauss --- Tested on DB1200 with C0 timer. The MIPS-MT bits are untested since I don't have capable hardware. arch/mips/kernel/irq.c | 12 ++++++++++-- arch/mips/kernel/irq_cpu.c | 42 +++++++++++++++++++++--------------------- 2 files changed, 31 insertions(+), 23 deletions(-) diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 4f93db5..b8112cf 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -89,6 +89,9 @@ int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, j; struct irqaction * action; + struct irq_desc *desc; + struct irq_data *data; + struct irq_chip *chip; unsigned long flags; if (i == 0) { @@ -100,9 +103,14 @@ int show_interrupts(struct seq_file *p, void *v) if (i < NR_IRQS) { raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + desc = irq_to_desc(i); + if (!desc) + goto skip; + action = desc->action; if (!action) goto skip; + data = irq_get_irq_data(i); + chip = irq_data_get_irq_chip(data); seq_printf(p, "%3d: ", i); #ifndef CONFIG_SMP seq_printf(p, "%10u ", kstat_irqs(i)); @@ -110,7 +118,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 0262abe..91a8689 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -37,25 +37,25 @@ #include #include -static inline void unmask_mips_irq(unsigned int irq) +static inline void unmask_mips_irq(struct irq_data *d) { - set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); irq_enable_hazard(); } -static inline void mask_mips_irq(unsigned int irq) +static inline void mask_mips_irq(struct irq_data *d) { - clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); irq_disable_hazard(); } static struct irq_chip mips_cpu_irq_controller = { .name = "MIPS", - .ack = mask_mips_irq, - .mask = mask_mips_irq, - .mask_ack = mask_mips_irq, - .unmask = unmask_mips_irq, - .eoi = unmask_mips_irq, + .irq_ack = mask_mips_irq, + .irq_mask = mask_mips_irq, + .irq_mask_ack = mask_mips_irq, + .irq_unmask = unmask_mips_irq, + .irq_eoi = unmask_mips_irq, }; /* @@ -65,13 +65,13 @@ static struct irq_chip mips_cpu_irq_controller = { #define unmask_mips_mt_irq unmask_mips_irq #define mask_mips_mt_irq mask_mips_irq -static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) +static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); evpe(vpflags); - unmask_mips_mt_irq(irq); + unmask_mips_mt_irq(d); return 0; } @@ -80,22 +80,22 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) * While we ack the interrupt interrupts are disabled and thus we don't need * to deal with concurrency issues. Same for mips_cpu_irq_end. */ -static void mips_mt_cpu_irq_ack(unsigned int irq) +static void mips_mt_cpu_irq_ack(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); evpe(vpflags); - mask_mips_mt_irq(irq); + mask_mips_mt_irq(d); } static struct irq_chip mips_mt_cpu_irq_controller = { .name = "MIPS", - .startup = mips_mt_cpu_irq_startup, - .ack = mips_mt_cpu_irq_ack, - .mask = mask_mips_mt_irq, - .mask_ack = mips_mt_cpu_irq_ack, - .unmask = unmask_mips_mt_irq, - .eoi = unmask_mips_mt_irq, + .irq_startup = mips_mt_cpu_irq_startup, + .irq_ack = mips_mt_cpu_irq_ack, + .irq_mask = mask_mips_mt_irq, + .irq_mask_ack = mips_mt_cpu_irq_ack, + .irq_unmask = unmask_mips_mt_irq, + .irq_eoi = unmask_mips_mt_irq, }; void __init mips_cpu_irq_init(void) -- 1.7.4 From manuel.lauss@googlemail.com Fri Feb 11 09:48:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 09:48:22 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:60562 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490984Ab1BKIrz (ORCPT ); Fri, 11 Feb 2011 09:47:55 +0100 Received: by bwz5 with SMTP id 5so2803112bwz.36 for ; Fri, 11 Feb 2011 00:47:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=O7xd5JFOsBowJAYbKwjhGdpeYS6QHvKXh4zGoS7Y9Sw=; b=LZq9RKcgSVyJIxoNarmGt6pVe6rc+T9C+BXRxIrdhz0oEQBJVMWJIw/pHwIAWt69WE gVXuV0viz9leuPHbWCb7WjDXqolPsdMv58NJwrqUGz7CZxY5Rb1KeNE1ydrW9IyMjubn PEWG1mbP5w4DmKf5s9Hc/yDnpm+70wYLjvA3U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=A1QUPKJAnUzfRrM0aIWQYdwWu7Yl4PQ/bTdbQ3uv2U55wrIXsCvHYN2IjhvaClYdHu YstIwYAwyILsNW2d98D21eKouC+eqXgN+VuLgE5K9k0WTbZTnzNa6puWplML0/jA4c8C CNnU1b4S2tyeqyiNHcL7YSg2E33EfFZiOWi18= Received: by 10.204.121.142 with SMTP id h14mr21988176bkr.93.1297414068394; Fri, 11 Feb 2011 00:47:48 -0800 (PST) Received: from localhost.localdomain (188-22-147-70.adsl.highway.telekom.at [188.22.147.70]) by mx.google.com with ESMTPS id v25sm290909bkt.18.2011.02.11.00.47.47 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Feb 2011 00:47:47 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Ralf Baechle , Manuel Lauss Subject: [PATCH RESEND 0/2] Alchemy: use new irq methods Date: Fri, 11 Feb 2011 09:47:42 +0100 Message-Id: <1297414064-3446-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29159 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips [Resending without the umlaut in Ralf's surname] These 2 patches change the core MIPS and Alchmey irq code to use the new .irq_xxx methods. The first patch is a prerequisite to turn on GENERIC_HARDIRQS_NO_DEPRECATED. I have tested it with the C0 timer and it seems to run well, however the MIPS-MT bits I cannot test. Someone with capable hardware please test! Thank you! The second patch changes the core alchemy and DB1200 board irq functions over to the new .irq_xxx ones. Run-tested on the DB1200. Manuel Lauss (2): MIPS: Convert to new irq methods. Alchemy: Convert to new irq methods. arch/mips/Kconfig | 1 + arch/mips/alchemy/common/irq.c | 83 +++++++++++++++++++----------------- arch/mips/alchemy/devboards/bcsr.c | 18 ++++---- arch/mips/kernel/irq.c | 12 ++++- arch/mips/kernel/irq_cpu.c | 42 +++++++++--------- 5 files changed, 85 insertions(+), 71 deletions(-) -- 1.7.4 From manuel.lauss@googlemail.com Fri Feb 11 09:48:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 09:48:47 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:44213 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491041Ab1BKIrz (ORCPT ); Fri, 11 Feb 2011 09:47:55 +0100 Received: by bwz5 with SMTP id 5so2803132bwz.36 for ; Fri, 11 Feb 2011 00:47:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=9Jr8jpOeo6YaZVHmgw/+RWXEnK/fbARf71R+z069eB0=; b=MV6HgYmubfV9sLZKldsYbvnypU51KpP7D9VoUCRwBeo3Sb99G54ypIuy5Wiu1vLFag HWEUK12uZMIvOgaF5UQsJkRCwrJ7pIjaaw5fuHUcPznzS72lmC1qkiNEemfDsKL9e1QE WnIlZs+zitoRsqI+eSVq4igF5Zvnr8NRSxU1A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=vqRaG/anrTWJRLgIiNIeRHst/hm7jCFwkPdopFhO5uPGPGahdtIPk9urw622sLwpID fochgAAgberqD7y5S8jbChh3k05EE4VgGAO1ZK/I8JIRfXhCvdZ5YYacf5yuyf1nvr3q HwyzHsiW3N15F6K7MclrtlbU0UJbIAV3NyRvM= Received: by 10.204.64.139 with SMTP id e11mr22399416bki.97.1297414070379; Fri, 11 Feb 2011 00:47:50 -0800 (PST) Received: from localhost.localdomain (188-22-147-70.adsl.highway.telekom.at [188.22.147.70]) by mx.google.com with ESMTPS id v25sm290909bkt.18.2011.02.11.00.47.49 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Feb 2011 00:47:50 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Ralf Baechle , Manuel Lauss Subject: [PATCH RESEND 2/2] Alchemy: Convert to new irq methods. Date: Fri, 11 Feb 2011 09:47:44 +0100 Message-Id: <1297414064-3446-3-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 In-Reply-To: <1297414064-3446-1-git-send-email-manuel.lauss@googlemail.com> References: <1297414064-3446-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29160 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Convert Alchemy core and board code to use new .irq_xxx methods. Signed-off-by: Manuel Lauss --- Run-tested on DB1200. arch/mips/Kconfig | 1 + arch/mips/alchemy/common/irq.c | 83 +++++++++++++++++++----------------- arch/mips/alchemy/devboards/bcsr.c | 18 ++++---- 3 files changed, 54 insertions(+), 48 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f5ecc05..401fc8f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -44,6 +44,7 @@ config MIPS_ALCHEMY select GENERIC_GPIO select ARCH_WANT_OPTIONAL_GPIOLIB select SYS_SUPPORTS_ZBOOT + select GENERIC_HARDIRQS_NO_DEPRECATED config AR7 bool "Texas Instruments AR7" diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 9f78ada..baef9a5 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -39,7 +39,7 @@ #include #endif -static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); +static int ic_settype(unsigned int irq, unsigned int flow_type); /* NOTE on interrupt priorities: The original writers of this code said: * @@ -218,17 +218,17 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { }; -static void au1x_ic0_unmask(unsigned int irq_nr) +static void alchemy_ic0_unmask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_MASKSET); au_writel(1 << bit, IC0_WAKESET); au_sync(); } -static void au1x_ic1_unmask(unsigned int irq_nr) +static void alchemy_ic1_unmask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_MASKSET); au_writel(1 << bit, IC1_WAKESET); @@ -236,31 +236,31 @@ static void au1x_ic1_unmask(unsigned int irq_nr) * nowhere in the current kernel sources is it disabled. --mlau */ #if defined(CONFIG_MIPS_PB1000) - if (irq_nr == AU1000_GPIO15_INT) + if (d->irq == AU1000_GPIO15_INT) au_writel(0x4000, PB1000_MDR); /* enable int */ #endif au_sync(); } -static void au1x_ic0_mask(unsigned int irq_nr) +static void alchemy_ic0_mask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_MASKCLR); au_writel(1 << bit, IC0_WAKECLR); au_sync(); } -static void au1x_ic1_mask(unsigned int irq_nr) +static void alchemy_ic1_mask(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_MASKCLR); au_writel(1 << bit, IC1_WAKECLR); au_sync(); } -static void au1x_ic0_ack(unsigned int irq_nr) +static void alchemy_ic0_ack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; /* * This may assume that we don't get interrupts from @@ -271,9 +271,9 @@ static void au1x_ic0_ack(unsigned int irq_nr) au_sync(); } -static void au1x_ic1_ack(unsigned int irq_nr) +static void alchemy_ic1_ack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; /* * This may assume that we don't get interrupts from @@ -284,9 +284,9 @@ static void au1x_ic1_ack(unsigned int irq_nr) au_sync(); } -static void au1x_ic0_maskack(unsigned int irq_nr) +static void alchemy_ic0_maskack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; au_writel(1 << bit, IC0_WAKECLR); au_writel(1 << bit, IC0_MASKCLR); @@ -295,9 +295,9 @@ static void au1x_ic0_maskack(unsigned int irq_nr) au_sync(); } -static void au1x_ic1_maskack(unsigned int irq_nr) +static void alchemy_ic1_maskack(struct irq_data *d) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; au_writel(1 << bit, IC1_WAKECLR); au_writel(1 << bit, IC1_MASKCLR); @@ -306,9 +306,9 @@ static void au1x_ic1_maskack(unsigned int irq_nr) au_sync(); } -static int au1x_ic1_setwake(unsigned int irq, unsigned int on) +static int alchemy_ic1_setwake(struct irq_data *d, unsigned int on) { - int bit = irq - AU1000_INTC1_INT_BASE; + int bit = d->irq - AU1000_INTC1_INT_BASE; unsigned long wakemsk, flags; /* only GPIO 0-7 can act as wakeup source. Fortunately these @@ -330,30 +330,35 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) return 0; } +static int alchemy_ic_settype(struct irq_data *d, unsigned int flow_type) +{ + return ic_settype(d->irq, flow_type); +} + /* * irq_chips for both ICs; this way the mask handlers can be * as short as possible. */ -static struct irq_chip au1x_ic0_chip = { +static struct irq_chip alchemy_ic0_chip = { .name = "Alchemy-IC0", - .ack = au1x_ic0_ack, - .mask = au1x_ic0_mask, - .mask_ack = au1x_ic0_maskack, - .unmask = au1x_ic0_unmask, - .set_type = au1x_ic_settype, + .irq_ack = alchemy_ic0_ack, + .irq_mask = alchemy_ic0_mask, + .irq_mask_ack = alchemy_ic0_maskack, + .irq_unmask = alchemy_ic0_unmask, + .irq_set_type = alchemy_ic_settype, }; -static struct irq_chip au1x_ic1_chip = { +static struct irq_chip alchemy_ic1_chip = { .name = "Alchemy-IC1", - .ack = au1x_ic1_ack, - .mask = au1x_ic1_mask, - .mask_ack = au1x_ic1_maskack, - .unmask = au1x_ic1_unmask, - .set_type = au1x_ic_settype, - .set_wake = au1x_ic1_setwake, + .irq_ack = alchemy_ic1_ack, + .irq_mask = alchemy_ic1_mask, + .irq_mask_ack = alchemy_ic1_maskack, + .irq_unmask = alchemy_ic1_unmask, + .irq_set_type = alchemy_ic_settype, + .irq_set_wake = alchemy_ic1_setwake, }; -static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) +static int ic_settype(unsigned int irq, unsigned int flow_type) { struct irq_chip *chip; unsigned long icr[6]; @@ -362,11 +367,11 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) if (irq >= AU1000_INTC1_INT_BASE) { bit = irq - AU1000_INTC1_INT_BASE; - chip = &au1x_ic1_chip; + chip = &alchemy_ic1_chip; ic = 1; } else { bit = irq - AU1000_INTC0_INT_BASE; - chip = &au1x_ic0_chip; + chip = &alchemy_ic0_chip; ic = 0; } @@ -504,11 +509,11 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) */ for (i = AU1000_INTC0_INT_BASE; (i < AU1000_INTC0_INT_BASE + 32); i++) - au1x_ic_settype(i, IRQ_TYPE_NONE); + ic_settype(i, IRQ_TYPE_NONE); for (i = AU1000_INTC1_INT_BASE; (i < AU1000_INTC1_INT_BASE + 32); i++) - au1x_ic_settype(i, IRQ_TYPE_NONE); + ic_settype(i, IRQ_TYPE_NONE); /* * Initialize IC0, which is fixed per processor. @@ -526,7 +531,7 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) au_writel(1 << bit, IC0_ASSIGNSET); } - au1x_ic_settype(irq_nr, map->im_type); + ic_settype(irq_nr, map->im_type); ++map; } diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index c52af88..f91c43a 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -97,26 +97,26 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) * CPLD generates tons of spurious interrupts (at least on my DB1200). * -- mlau */ -static void bcsr_irq_mask(unsigned int irq_nr) +static void bcsr_irq_mask(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); wmb(); } -static void bcsr_irq_maskack(unsigned int irq_nr) +static void bcsr_irq_maskack(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ wmb(); } -static void bcsr_irq_unmask(unsigned int irq_nr) +static void bcsr_irq_unmask(struct irq_data *d) { - unsigned short v = 1 << (irq_nr - bcsr_csc_base); + unsigned short v = 1 << (d->irq - bcsr_csc_base); __raw_writew(v, bcsr_virt + BCSR_REG_INTSET); __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); wmb(); @@ -124,9 +124,9 @@ static void bcsr_irq_unmask(unsigned int irq_nr) static struct irq_chip bcsr_irq_type = { .name = "CPLD", - .mask = bcsr_irq_mask, - .mask_ack = bcsr_irq_maskack, - .unmask = bcsr_irq_unmask, + .irq_mask = bcsr_irq_mask, + .irq_mask_ack = bcsr_irq_maskack, + .irq_unmask = bcsr_irq_unmask, }; void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) -- 1.7.4 From manuel.lauss@googlemail.com Fri Feb 11 10:02:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 10:02:59 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:61072 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491041Ab1BKJC4 (ORCPT ); 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Fri, 11 Feb 2011 01:02:50 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH V2] MIPS/DB1200: Set Config[OD] for improved stability. Date: Fri, 11 Feb 2011 10:02:46 +0100 Message-Id: <1297414966-3805-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29161 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Setting Config[OD] gets rid of a _LOT_ of spurious CPLD interrupts, but also decreases overall performance a bit. Signed-off-by: Manuel Lauss --- v2: improvements and fixes, thanks to Sergei Shtylyov. arch/mips/alchemy/common/setup.c | 4 ++-- arch/mips/alchemy/devboards/db1200/setup.c | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 561e5da..1b887c8 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -52,8 +52,6 @@ void __init plat_mem_setup(void) /* this is faster than wasting cycles trying to approximate it */ preset_lpj = (est_freq >> 1) / HZ; - board_setup(); /* board specific setup */ - if (au1xxx_cpu_needs_config_od()) /* Various early Au1xx0 errata corrected by this */ set_c0_config(1 << 19); /* Set Config[OD] */ @@ -61,6 +59,8 @@ void __init plat_mem_setup(void) /* Clear to obtain best system bus performance */ clear_c0_config(1 << 19); /* Clear Config[OD] */ + board_setup(); /* board specific setup */ + /* IO/MEM resources. */ set_io_port_base(0); ioport_resource.start = IOPORT_RESOURCE_START; diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index 8876195..be788c8 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -23,6 +23,13 @@ void __init board_setup(void) unsigned long freq0, clksrc, div, pfc; unsigned short whoami; + /* Set Config[OD] (disable overlapping bus transaction): + * This gets rid of a _lot_ of spurious interrupts (especially + * wrt. IDE); but incurs ~10% performance hit in some + * cpu-bound applications. + */ + set_c0_config(1 << 19); + bcsr_init(DB1200_BCSR_PHYS_ADDR, DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); -- 1.7.4 From ralf@duck.linux-mips.net Fri Feb 11 15:05:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 15:05:18 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36592 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491041Ab1BKOFP (ORCPT ); Fri, 11 Feb 2011 15:05:15 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1BE61sW004023; Fri, 11 Feb 2011 15:06:01 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1BE60If004019; Fri, 11 Feb 2011 15:06:00 +0100 Date: Fri, 11 Feb 2011 15:06:00 +0100 From: Ralf Baechle To: "Anoop P.A" Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/6] Platform support MSP onchip USB controller. Message-ID: <20110211140600.GA23348@linux-mips.org> References: <1295943725-20308-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295943725-20308-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29162 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jan 25, 2011 at 01:52:05PM +0530, Anoop P.A wrote: > +#ifdef CONFIG_MSP_HAS_DUAL_USB > +#define NUM_USB_DEVS 2 > +#else > +#define NUM_USB_DEVS 1 > +#endif I thought you meant to replace CONFIG_MSP_HAS_DUAL_USB with a runtime check? Ralf From ralf@duck.linux-mips.net Fri Feb 11 15:53:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 15:53:37 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:38710 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491059Ab1BKOxe (ORCPT ); Fri, 11 Feb 2011 15:53:34 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1BEsLrL008701; Fri, 11 Feb 2011 15:54:21 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1BEsKwq008699; Fri, 11 Feb 2011 15:54:20 +0100 Date: Fri, 11 Feb 2011 15:54:20 +0100 From: Ralf Baechle To: Anoop P A Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 1/6] set up MSP VPE1 timer. Message-ID: <20110211145420.GB23348@linux-mips.org> References: <1295943561-20000-1-git-send-email-anoop.pa@gmail.com> <1295978896.27661.567.camel@paanoop1-desktop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295978896.27661.567.camel@paanoop1-desktop> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29163 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jan 25, 2011 at 11:38:16PM +0530, Anoop P A wrote: Queued for 2.6.39 - but you really should run your patches through checkpatch.pl before posting them. Ralf From ralf@duck.linux-mips.net Fri Feb 11 15:54:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 15:54:05 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:38785 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491059Ab1BKOyB (ORCPT ); Fri, 11 Feb 2011 15:54:01 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1BEsmrT008737; Fri, 11 Feb 2011 15:54:48 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1BEsm2c008735; Fri, 11 Feb 2011 15:54:48 +0100 Date: Fri, 11 Feb 2011 15:54:47 +0100 From: Ralf Baechle To: "Anoop P.A" Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, dhowells@redhat.com Subject: Re: [PATCH 2/6] Vectored interrupt support. Message-ID: <20110211145447.GC23348@linux-mips.org> References: <1295943610-20099-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295943610-20099-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29164 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.39 - but you really should run your patches through checkpatch.pl before posting them. Ralf From ralf@duck.linux-mips.net Fri Feb 11 15:55:03 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 15:55:06 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39093 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491059Ab1BKOzD (ORCPT ); Fri, 11 Feb 2011 15:55:03 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1BEtoXL008813; Fri, 11 Feb 2011 15:55:50 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1BEtonP008811; Fri, 11 Feb 2011 15:55:50 +0100 Date: Fri, 11 Feb 2011 15:55:50 +0100 From: Ralf Baechle To: "Anoop P.A" Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/6] MIPS MT kernel modes ( VSMP/SMTC ) support for MSP platforms. Message-ID: <20110211145550.GD23348@linux-mips.org> References: <1295943663-20192-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295943663-20192-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29165 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.39 - but you really should run your patches through checkpatch.pl before posting them. I also removed the inclusion of sched.h which appeared unnecessary. Ralf From ralf@duck.linux-mips.net Fri Feb 11 15:56:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 15:56:42 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39283 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491059Ab1BKO4j (ORCPT ); Fri, 11 Feb 2011 15:56:39 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1BEvQ2q008929; Fri, 11 Feb 2011 15:57:26 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1BEvQ1a008926; Fri, 11 Feb 2011 15:57:26 +0100 Date: Fri, 11 Feb 2011 15:57:26 +0100 From: Ralf Baechle To: "Anoop P.A" Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/6] Platform support MSP onchip USB controller. Message-ID: <20110211145726.GE23348@linux-mips.org> References: <1295943725-20308-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295943725-20308-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29166 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jan 25, 2011 at 01:52:05PM +0530, Anoop P.A wrote: I put this one into the 2.6.39 queue for now but I still wonder what your plan about CONFIG_MSP_HAS_DUAL_USB is. Ralf From ralf@duck.linux-mips.net Fri Feb 11 15:58:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 15:58:30 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:48975 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491059Ab1BKO61 (ORCPT ); Fri, 11 Feb 2011 15:58:27 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1BExFnF009059; Fri, 11 Feb 2011 15:59:15 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1BExEVa009057; Fri, 11 Feb 2011 15:59:14 +0100 Date: Fri, 11 Feb 2011 15:59:14 +0100 From: Ralf Baechle To: "Anoop P.A" Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 5/6] Platform support for On-chip MSP ethernet devices. Message-ID: <20110211145914.GF23348@linux-mips.org> References: <1295951309-4444-1-git-send-email-anoop.pa@gmail.com> <1295978049-30605-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295978049-30605-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29167 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.39. I killed all typedefs in this patch. Thanks, Ralf From ralf@duck.linux-mips.net Fri Feb 11 16:03:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 16:03:20 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:57547 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491059Ab1BKPDQ (ORCPT ); Fri, 11 Feb 2011 16:03:16 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1BF447w009416; Fri, 11 Feb 2011 16:04:04 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1BF43qL009413; Fri, 11 Feb 2011 16:04:03 +0100 Date: Fri, 11 Feb 2011 16:04:03 +0100 From: Ralf Baechle To: "Anoop P.A" Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/6] Cpu features overrides for msp platforms. Message-ID: <20110211150403.GG23348@linux-mips.org> References: <1295943797-20467-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295943797-20467-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29168 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.39, thanks! But: this is a rather short cpu-feature-overrides.h file. You can shrink the kernel significantly and get a little performance boost by further defines in that file. In particular defining the symbols for cache and TLB properties such as the cpu_dcache_line_size and cpu_icache_line_size are very effective. Ralf From anoop.pa@gmail.com Fri Feb 11 16:09:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 16:09:08 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:64677 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491842Ab1BKPJE (ORCPT ); Fri, 11 Feb 2011 16:09:04 +0100 Received: by fxm19 with SMTP id 19so2869406fxm.36 for ; Fri, 11 Feb 2011 07:08:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:to:cc:in-reply-to:references :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=7U9WCNaUDeIwDmGkV8ZoG/M4DBGZGi2W2Ut2c19CSzQ=; b=yB3ArXbKt5vcVqGoLXpsBOejVaFr5qhN0Xuy/wSvhW5d7YDnHaWQKwIvHip4FNd/8w 5DhMXxr/avGOcJdbDb5W1QRxyxC/Y1DBjKmNRWhljgn0k++u8hMu8ByW+G/q0bcZOp5a lZxyeA+CGAkroywa7qzzeoMn+4A9Cx4h2Vvt4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=v5D7z0CQADiohENIdgG6Qw3pfcDCg+m67VWS9pfK3eV0LCC+nJ46PqBKELGgajM6/t HSc1wLVDN2ArBG1X1ffFmvFRZY7h6Lg4Mylk3UcmrAgkUMHrtrdMk9YgN5I2c4/IT5zy 4NsiWnnBMAOtqOzbMT4hOkpTwoQb7jm2cTqJo= Received: by 10.223.100.16 with SMTP id w16mr610761fan.85.1297436939258; Fri, 11 Feb 2011 07:08:59 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id y1sm405445fak.39.2011.02.11.07.08.56 (version=SSLv3 cipher=OTHER); Fri, 11 Feb 2011 07:08:58 -0800 (PST) Subject: Re: [PATCH 4/6] Platform support MSP onchip USB controller. From: Anoop P A To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org In-Reply-To: <20110211140600.GA23348@linux-mips.org> References: <1295943725-20308-1-git-send-email-anoop.pa@gmail.com> <20110211140600.GA23348@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Fri, 11 Feb 2011 20:59:27 +0530 Message-ID: <1297438167.29250.72.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29169 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2011-02-11 at 15:06 +0100, Ralf Baechle wrote: > On Tue, Jan 25, 2011 at 01:52:05PM +0530, Anoop P.A wrote: > > > +#ifdef CONFIG_MSP_HAS_DUAL_USB > > +#define NUM_USB_DEVS 2 > > +#else > > +#define NUM_USB_DEVS 1 > > +#endif > > I thought you meant to replace CONFIG_MSP_HAS_DUAL_USB with a runtime > check? No. I added that as an configuration option will be used in future. > > Ralf From anoop.pa@gmail.com Fri Feb 11 16:10:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 11 Feb 2011 16:11:00 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:60735 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491008Ab1BKPK5 (ORCPT ); Fri, 11 Feb 2011 16:10:57 +0100 Received: by ewy20 with SMTP id 20so1290232ewy.36 for ; Fri, 11 Feb 2011 07:10:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:to:cc:in-reply-to:references :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=AaTELkS8wascqy7RHWheT+rb/vKhU8A2wXQvy2T0mcM=; b=kZr7oXXF6mbAofw2Xqa8foaf2nFpsUqdLA68B9tv+u2ugbzT0xmbqVTwBTxxBHpHPw 0I/PZ+j8sMOFlkluQbWKwbW7gzezNTo/H1y097JyxcrgFxcXcCpVkDBuslzqODeBlk7T Cxk7mrThC9YxMMYVYR+bRJOT4EVlbgORAOcks= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=N+SyU5zsRYZnlNRLc6YuNwf85TBg4H1+5E9kl/YFvbLYXsdiNGatIHP26v60lpb+wf AT1h7KtII8lzaM1nS7he0JYoj3axNmyly5A1/3GqhibHchqIPEWTlZ9rw7IahBFu0jj+ rba63EMRjgv8bTSlPUhNLLpDUSvuwTQheqdbA= Received: by 10.102.244.8 with SMTP id r8mr379738muh.4.1297437051952; Fri, 11 Feb 2011 07:10:51 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id l3sm414576fan.0.2011.02.11.07.10.49 (version=SSLv3 cipher=OTHER); Fri, 11 Feb 2011 07:10:51 -0800 (PST) Subject: Re: [PATCH 6/6] Cpu features overrides for msp platforms. From: Anoop P A To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org In-Reply-To: <20110211150403.GG23348@linux-mips.org> References: <1295943797-20467-1-git-send-email-anoop.pa@gmail.com> <20110211150403.GG23348@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Fri, 11 Feb 2011 21:01:20 +0530 Message-ID: <1297438280.29250.74.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29170 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2011-02-11 at 16:04 +0100, Ralf Baechle wrote: > Queued for 2.6.39, thanks! > > But: this is a rather short cpu-feature-overrides.h file. You can shrink > the kernel significantly and get a little performance boost by further > defines in that file. In particular defining the symbols for cache and > TLB properties such as the cpu_dcache_line_size and cpu_icache_line_size > are very effective. Can you point me to reference file ?. > > Ralf From maksim.rayskiy@gmail.com Sat Feb 12 04:22:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Feb 2011 04:22:46 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:3498 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490997Ab1BLDWn (ORCPT ); Sat, 12 Feb 2011 04:22:43 +0100 Received: from [10.9.200.131] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Fri, 11 Feb 2011 19:24:23 -0800 X-Server-Uuid: 02CED230-5797-4B57-9875-D5D2FEE4708A Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.2.247.2; Fri, 11 Feb 2011 19:22:27 -0800 Received: from stb-bld-00.broadcom.com (stb-bld-00 [10.13.134.27]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 7D81B74D03; Fri, 11 Feb 2011 19:22:27 -0800 (PST) From: maksim.rayskiy@gmail.com To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: "Maksim Rayskiy" Subject: [PATCH] MIPS: move idle task creation to work queue Date: Fri, 11 Feb 2011 19:22:26 -0800 Message-ID: <1297480946-28053-1-git-send-email-maksim.rayskiy@gmail.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 X-WSS-ID: 614B22ED3DG6844193-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29171 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maksim.rayskiy@gmail.com Precedence: bulk X-list: linux-mips From: Maksim Rayskiy To avoid forking usertask when creating an idle task, move fork_idle to a work queue. This is a small improvement to previous commit 467f0b8. Signed-off-by: Maksim Rayskiy --- Ralf, this is per your suggestion. The code is mostly copy-pasted from arch/x86/kernel/smpboot.c arch/mips/kernel/smp.c | 32 ++++++++++++++++++++++++++------ 1 files changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 4593916..98bd504 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -193,6 +193,21 @@ void __devinit smp_prepare_boot_cpu(void) */ static struct task_struct *cpu_idle_thread[NR_CPUS]; +struct create_idle { + struct work_struct work; + struct task_struct *idle; + struct completion done; + int cpu; +}; + +static void __cpuinit do_fork_idle(struct work_struct *work) +{ + struct create_idle *c_idle = + container_of(work, struct create_idle, work); + c_idle->idle = fork_idle(c_idle->cpu); + complete(&c_idle->done); +} + int __cpuinit __cpu_up(unsigned int cpu) { struct task_struct *idle; @@ -203,16 +218,21 @@ int __cpuinit __cpu_up(unsigned int cpu) * Linux can schedule processes on this slave. */ if (!cpu_idle_thread[cpu]) { - idle = fork_idle(cpu); - cpu_idle_thread[cpu] = idle; + /* Schedule work item to avoid forking user task. + Ported from x86 */ + struct create_idle c_idle = { + .cpu = cpu, + .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), + }; + + INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); + schedule_work(&c_idle.work); + wait_for_completion(&c_idle.done); + idle = cpu_idle_thread[cpu] = c_idle.idle; if (IS_ERR(idle)) panic(KERN_ERR "Fork failed for CPU %d", cpu); - if (idle->mm) { - mmput(idle->mm); - idle->mm = NULL; - } } else { idle = cpu_idle_thread[cpu]; init_idle(idle, cpu); -- 1.7.3.2 From sshtylyov@mvista.com Sat Feb 12 14:52:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Feb 2011 14:52:26 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:55744 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491069Ab1BLNwW (ORCPT ); Sat, 12 Feb 2011 14:52:22 +0100 Received: by bwz5 with SMTP id 5so3880905bwz.36 for ; Sat, 12 Feb 2011 05:52:16 -0800 (PST) Received: by 10.204.66.65 with SMTP id m1mr551659bki.71.1297518736228; Sat, 12 Feb 2011 05:52:16 -0800 (PST) Received: from [192.168.2.2] ([91.79.98.123]) by mx.google.com with ESMTPS id q18sm329969bka.3.2011.02.12.05.52.13 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 12 Feb 2011 05:52:14 -0800 (PST) Message-ID: <4D569044.5070801@mvista.com> Date: Sat, 12 Feb 2011 16:51:00 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: maksim.rayskiy@gmail.com CC: ralf@linux-mips.org, linux-mips@linux-mips.org, Maksim Rayskiy Subject: Re: [PATCH] MIPS: move idle task creation to work queue References: <1297480946-28053-1-git-send-email-maksim.rayskiy@gmail.com> In-Reply-To: <1297480946-28053-1-git-send-email-maksim.rayskiy@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29172 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 12-02-2011 6:22, maksim.rayskiy@gmail.com wrote: > From: Maksim Rayskiy > To avoid forking usertask when creating an idle task, move fork_idle > to a work queue. > This is a small improvement to previous commit 467f0b8. Linus akss to also specify the commit summary in parens. > Signed-off-by: Maksim Rayskiy [...] > diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c > index 4593916..98bd504 100644 > --- a/arch/mips/kernel/smp.c > +++ b/arch/mips/kernel/smp.c > @@ -193,6 +193,21 @@ void __devinit smp_prepare_boot_cpu(void) > */ > static struct task_struct *cpu_idle_thread[NR_CPUS]; > > +struct create_idle { > + struct work_struct work; > + struct task_struct *idle; > + struct completion done; > + int cpu; > +}; > + > +static void __cpuinit do_fork_idle(struct work_struct *work) > +{ > + struct create_idle *c_idle = > + container_of(work, struct create_idle, work); Empty line wouldn't hurt here... > + c_idle->idle = fork_idle(c_idle->cpu); > + complete(&c_idle->done); > +} > + > int __cpuinit __cpu_up(unsigned int cpu) > { > struct task_struct *idle; > @@ -203,16 +218,21 @@ int __cpuinit __cpu_up(unsigned int cpu) > * Linux can schedule processes on this slave. > */ > if (!cpu_idle_thread[cpu]) { > - idle = fork_idle(cpu); > - cpu_idle_thread[cpu] = idle; > + /* Schedule work item to avoid forking user task. > + Ported from x86 */ The preferred style of multi-line comments is this: /* * bla * bla */ WBR, Sergei From maksim.rayskiy@gmail.com Sat Feb 12 19:22:01 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 12 Feb 2011 19:22:04 +0100 (CET) Received: from mms1.broadcom.com ([216.31.210.17]:3611 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491117Ab1BLSWB (ORCPT ); Sat, 12 Feb 2011 19:22:01 +0100 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Sat, 12 Feb 2011 10:23:38 -0800 X-Server-Uuid: 02CED230-5797-4B57-9875-D5D2FEE4708A Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Sat, 12 Feb 2011 10:21:41 -0800 Received: from stb-bld-00.broadcom.com (stb-bld-00 [10.13.134.27]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id BC2C274D05; Sat, 12 Feb 2011 10:21:41 -0800 (PST) From: maksim.rayskiy@gmail.com To: ralf@linux-mips.org, linux-mips@linux-mips.org cc: "Maksim Rayskiy" Subject: [PATCH v2] MIPS: move idle task creation to work queue Date: Sat, 12 Feb 2011 10:21:32 -0800 Message-ID: <1297534892-29952-1-git-send-email-maksim.rayskiy@gmail.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 X-WSS-ID: 61480FA03DG7319926-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29173 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maksim.rayskiy@gmail.com Precedence: bulk X-list: linux-mips From: Maksim Rayskiy To avoid forking usermode thread when creating an idle task, move fork_idle to a work queue. This is a small improvement to 467f0b8e708390052ada48b28d1a56d20fe8b3de [ MIPS: Clear idle task mm pointer when hotplugging cpu ] Signed-off-by: Maksim Rayskiy --- Style improvements per Sergei's suggestions. arch/mips/kernel/smp.c | 35 +++++++++++++++++++++++++++++------ 1 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 4593916..635484d 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -193,6 +193,22 @@ void __devinit smp_prepare_boot_cpu(void) */ static struct task_struct *cpu_idle_thread[NR_CPUS]; +struct create_idle { + struct work_struct work; + struct task_struct *idle; + struct completion done; + int cpu; +}; + +static void __cpuinit do_fork_idle(struct work_struct *work) +{ + struct create_idle *c_idle = + container_of(work, struct create_idle, work); + + c_idle->idle = fork_idle(c_idle->cpu); + complete(&c_idle->done); +} + int __cpuinit __cpu_up(unsigned int cpu) { struct task_struct *idle; @@ -203,16 +219,23 @@ int __cpuinit __cpu_up(unsigned int cpu) * Linux can schedule processes on this slave. */ if (!cpu_idle_thread[cpu]) { - idle = fork_idle(cpu); - cpu_idle_thread[cpu] = idle; + /* + * Schedule work item to avoid forking user task + * Ported from arch/x86/kernel/smpboot.c + */ + struct create_idle c_idle = { + .cpu = cpu, + .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), + }; + + INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); + schedule_work(&c_idle.work); + wait_for_completion(&c_idle.done); + idle = cpu_idle_thread[cpu] = c_idle.idle; if (IS_ERR(idle)) panic(KERN_ERR "Fork failed for CPU %d", cpu); - if (idle->mm) { - mmput(idle->mm); - idle->mm = NULL; - } } else { idle = cpu_idle_thread[cpu]; init_idle(idle, cpu); -- 1.7.3.2 From kais58@sucs.org Mon Feb 14 05:48:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Feb 2011 05:48:25 +0100 (CET) Received: from silver.sucs.swan.ac.uk ([137.44.10.1]:52549 "EHLO silver.sucs.swan.ac.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491002Ab1BNEsW (ORCPT ); Mon, 14 Feb 2011 05:48:22 +0100 Received: from [137.44.122.83] (helo=[127.0.0.1]) by silver.sucs.swan.ac.uk with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1PoqMB-000644-3x for linux-mips@linux-mips.org; Mon, 14 Feb 2011 04:48:15 +0000 Message-ID: <4D58B3F8.6000902@sucs.org> Date: Mon, 14 Feb 2011 04:47:52 +0000 From: Callum Massey User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: SGI Onyx4 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110213-1, 13/02/2011), Outbound message X-Antivirus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29174 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kais58@sucs.org Precedence: bulk X-list: linux-mips Dear all, Swansea University Computer Society is currently in possesion of an SGI Onyx4 and are willing to offer essentially complete access to the machine to help in the creation of a MIPS IP35 Linux, if so let me know and It's currently running OpenBSD. Callum Massey, SUCS President http://sucs.org From robo@dare.nl Mon Feb 14 09:27:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Feb 2011 09:27:11 +0100 (CET) Received: from cpsmtp-fia02.kpnxchange.com ([195.121.247.5]:1207 "EHLO cpsmtp-fia02.kpnxchange.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491177Ab1BNI1I (ORCPT ); Mon, 14 Feb 2011 09:27:08 +0100 Received: from mouse.matrix.dare.nl ([217.166.125.17]) by cpsmtp-fia02.kpnxchange.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 14 Feb 2011 09:26:58 +0100 Received: from localhost (localhost [127.0.0.1]) by mouse.matrix.dare.nl (Postfix) with ESMTP id 34363AA1F8 for ; Mon, 14 Feb 2011 09:26:53 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at dare.nl Received: from mouse.matrix.dare.nl ([127.0.0.1]) by localhost (mouse.matrix.dare.nl [127.0.0.1]) (amavisd-new, port 10024) with SMTP id Q6FSrSCeeaDg for ; Mon, 14 Feb 2011 09:26:44 +0100 (CET) Received: from [192.168.8.199] (id6721.matrix.dare.nl [192.168.8.199]) by mouse.matrix.dare.nl (Postfix) with ESMTP id 834BAAA1DF for ; Mon, 14 Feb 2011 09:26:44 +0100 (CET) Message-ID: <4D58E745.9090003@dare.nl> Date: Mon, 14 Feb 2011 09:26:45 +0100 From: Robert Bon Organization: D.A.R.E!! Development User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 To: linux-mips Subject: alchemy au1100 where is the MMC card Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 14 Feb 2011 08:26:58.0357 (UTC) FILETIME=[F222AE50:01CBCC20] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29175 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robo@dare.nl Precedence: bulk X-list: linux-mips Hello, Kernel 2.6.37 Where is the support for a MMC card for the Alchemy AU1100 processor? Is is only supported for the AU1200? See file: "drivers/mmc/host/Kconfig config MMC_AU1X tristate "Alchemy AU1XX0 MMC Card Interface support" depends on SOC_AU1200 Robert Bon __________ Information from ESET NOD32 Antivirus, version of virus signature database 5871 (20110213) __________ The message was checked by ESET NOD32 Antivirus. http://www.eset.com From manuel.lauss@googlemail.com Mon Feb 14 09:33:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Feb 2011 09:33:37 +0100 (CET) Received: from mail-ww0-f41.google.com ([74.125.82.41]:56590 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491014Ab1BNIde convert rfc822-to-8bit (ORCPT ); Mon, 14 Feb 2011 09:33:34 +0100 Received: by wwi18 with SMTP id 18so1593144wwi.0 for ; Mon, 14 Feb 2011 00:33:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=zb/UmS/j6Ff98I2FVbSg3QySeW1rTE651z/10pRxYeQ=; b=KvshwIxSO8IVzqzXcshBWPSMas6CDeCZNeBIc8zcfH5p2utGtvVv5UmjymV58GpISj lEDzz9ZK//zv97p65S0UVa0bhMVbwzoLMqWIXzhf6H46vSE5KO3lxQhhY0Fi7zHzxRc5 NRa9WiFYNC4/+jFuzy7Fd5DZfRUmXT6qk2Ig4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=JV9tPj2SSyNhPLmlAt33x98i4LatBtXhbgPSbz0C/L1bjjStL36WpE9crSvLu7B+3K pBj0YST4JCfJttj1tLD4TRNlSV0FAviqiBxy7IRvzvF5ZfdvgIFMoEg0E57wwuKQEVnA +Lj1qHoCz453xoGlBDClIiun05pufDcZFYwzs= MIME-Version: 1.0 Received: by 10.216.71.13 with SMTP id q13mr2962797wed.21.1297672408143; Mon, 14 Feb 2011 00:33:28 -0800 (PST) Received: by 10.216.193.195 with HTTP; Mon, 14 Feb 2011 00:33:28 -0800 (PST) In-Reply-To: <4D58E745.9090003@dare.nl> References: <4D58E745.9090003@dare.nl> Date: Mon, 14 Feb 2011 09:33:28 +0100 Message-ID: Subject: Re: alchemy au1100 where is the MMC card From: Manuel Lauss To: Robert Bon Cc: linux-mips Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29176 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Hi Robert, On Mon, Feb 14, 2011 at 9:26 AM, Robert Bon wrote: > Kernel 2.6.37 > Where is the support for a MMC card for the Alchemy AU1100 processor? > Is is only supported  for the AU1200? > > See file: "drivers/mmc/host/Kconfig > config MMC_AU1X >  tristate "Alchemy AU1XX0 MMC Card Interface support" >  depends on SOC_AU1200 The driver code seems to support the Au1100, however I doubt anyone has actually ever tested it on real hardware. Tell us how it goes... Manuel From David.Daney@caviumnetworks.com Mon Feb 14 21:29:29 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 14 Feb 2011 21:29:32 +0100 (CET) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:3896 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491187Ab1BNU33 (ORCPT ); Mon, 14 Feb 2011 21:29:29 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by smtp2.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 14 Feb 2011 15:29:34 -0500 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 14 Feb 2011 12:29:25 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 14 Feb 2011 12:29:25 -0800 Message-ID: <4D5990A4.2050308@caviumnetworks.com> Date: Mon, 14 Feb 2011 12:29:24 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: linux-mips , GCC , binutils , Prasun Kapoor Subject: RFC: A new MIPS64 ABI Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 14 Feb 2011 20:29:25.0308 (UTC) FILETIME=[DEEE7FC0:01CBCC85] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29177 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Background: Current MIPS 32-bit ABIs (both o32 and n32) are restricted to 2GB of user virtual memory space. This is due the way MIPS32 memory space is segmented. Only the range from 0..2^31-1 is available. Pointer values are always sign extended. Because there are not already enough MIPS ABIs, I present the ... Proposal: A new ABI to support 4GB of address space with 32-bit pointers. The proposed new ABI would only be available on MIPS64 platforms. It would be identical to the current MIPS n32 ABI *except* that pointers would be zero-extended rather than sign-extended when resident in registers. In the remainder of this document I will call it 'n32-big'. As a result, applications would have access to a full 4GB of virtual address space. The operating environment would be configured such that the entire lower 4GB of the virtual address space was available to the program. At a low level here is how it would work: 1) Load a pointer to a register from memory: n32: LW $reg, offset($reg) n32-big: LWU $reg, offset($reg) 2) Load an address constant into a register: n32: LUI $reg, high_part ORI $reg, low_part n32-big: ORI $reg, high_part DSLL $reg, $reg, 16 ORI $reg, low_part Q: What would have to change to make this work? o A new ELF header flag to denote the ABI. o Linker support to use proper library search paths, and linker scrips to set the INTERP program header, etc. o GCC has to emit code for the new ABI. o Could all existing n32 relocation types be used? I think so. o Runtime libraries would have to be placed in a new location (/lib32big, /usr/lib32big ...) o The C library's ld.so would have to use a distinct LD_LIBRARY_PATH for n32-big code. o What would the Linux system call interface be? I would propose using the existing Linux n32 system call interface. Most system calls would just work. Some, that pass pointers in in-memory structures, might require kernel modifications (sigaction() for example). From anoop.pa@gmail.com Tue Feb 15 11:22:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 11:22:41 +0100 (CET) Received: from mail-yi0-f49.google.com ([209.85.218.49]:51449 "EHLO mail-yi0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490990Ab1BOKWh (ORCPT ); Tue, 15 Feb 2011 11:22:37 +0100 Received: by yib2 with SMTP id 2so2426707yib.36 for ; Tue, 15 Feb 2011 02:22:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=vmBTkyyYcEIcxKYNE/cRv5fqcBjknwEvkihq7rlnFEc=; b=TXjHyRmPzJ32r5D20dTHXuji3YK0ACD4u9IctPHrpzx7907NGTJqLaHUbh+Ks6QDca RlVecdpo6sgMGZVVHjxrGDnRRGZBJH30cPjBFHiCh0+9E6EPh74SS+coXFvTYcwr1OtY gA1WG2huN6H/II75wUkWID1Q2jtOuSIT2xBDU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=jYF3bFM24bxCxgomrtu4yH59PFYqwdOvq/TVBKDCWCV0Krq68okNQWR9v5YDJavMhw h+zmiZHnoMNLkXVHpvqaKl16ZEjvzsqb9GdfOeo6R2CFl2SfHzstkmQ5LUnBg0eS2ZFA BGwaH23HfZPNeRsNG7/xuBQKV5fpLRus6nZOs= Received: by 10.100.107.1 with SMTP id f1mr2061924anc.187.1297765349797; Tue, 15 Feb 2011 02:22:29 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id c39sm4835322anc.27.2011.02.15.02.22.23 (version=SSLv3 cipher=OTHER); Tue, 15 Feb 2011 02:22:28 -0800 (PST) From: "Anoop P.A" To: gregkh@suse.de, dbrownell@users.sourceforge.net, stern@rowland.harvard.edu, pkondeti@codeaurora.org, jacob.jun.pan@intel.com, linux-usb@vger.kernel.org, alek.du@intel.com, linux-kernel@vger.kernel.org, gadiyar@ti.com, ralf@linux-mips.org, linux-mips@linux-mips.org, Greg KH Cc: anoop.pa@gmail.com Subject: [PATCH v4] EHCI bus glue for on-chip PMC MSP USB controller Date: Tue, 15 Feb 2011 16:13:11 +0530 Message-Id: <1297766591-11919-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> References: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29178 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop This patch add bus glue for USB controller commonly found in PMC-Sierra MSP71xx family of SoC's. Patch includes a tdi reset quirk as well . Signed-off-by: Anoop P A Tested-by: Shane McDonald --- Changes. ehci-pmcmsp.c is based on latest ehci-pci.c.Addressed some stylistic issue pointed by Greg. Addressed review comments of Matthieu CASTET. drivers/usb/host/Kconfig | 15 +- drivers/usb/host/ehci-hcd.c | 7 + drivers/usb/host/ehci-pmcmsp.c | 530 ++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci.h | 8 + 4 files changed, 558 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/host/ehci-pmcmsp.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0e6afa2..1b01c99 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -91,17 +91,28 @@ config USB_EHCI_TT_NEWSCHED If unsure, say Y. +config USB_EHCI_HCD_PMC_MSP + tristate "EHCI support for on-chip PMC MSP USB controller" + depends on USB_EHCI_HCD && MSP_HAS_USB + default y + select USB_EHCI_BIG_ENDIAN_DESC + select USB_EHCI_BIG_ENDIAN_MMIO + ---help--- + Enables support for the onchip USB controller on the PMC_MSP7100 Family SoC's. + If unsure, say N. + config USB_EHCI_BIG_ENDIAN_MMIO bool depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ - PPC_MPC512x || CPU_CAVIUM_OCTEON) + PPC_MPC512x || CPU_CAVIUM_OCTEON || \ + PMC_MSP) default y config USB_EHCI_BIG_ENDIAN_DESC bool depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ - PPC_MPC512x) + PPC_MPC512x || PMC_MSP) default y config XPS_USB_HCD_XILINX diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index cbf451a..913e7df 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -260,6 +260,8 @@ static void tdi_reset (struct ehci_hcd *ehci) if (ehci_big_endian_mmio(ehci)) tmp |= USBMODE_BE; ehci_writel(ehci, tmp, reg_ptr); + if (ehci->pmc_msp_tdi) + usb_hcd_tdi_set_mode(ehci); } /* reset a non-running (STS_HALT == 1) controller */ @@ -1250,6 +1252,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_msm_driver #endif +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP +#include "ehci-pmcmsp.c" +#define PLATFORM_DRIVER ehci_hcd_msp_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c new file mode 100644 index 0000000..dff3d92 --- /dev/null +++ b/drivers/usb/host/ehci-pmcmsp.c @@ -0,0 +1,530 @@ +/* + * PMC MSP EHCI (Host Controller Driver) for USB. + * + * (C) Copyright 2006-2010 PMC-Sierra Inc + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +/* includes */ +#include +#include +#include +#include + +/* host mode */ +#define USB_CTRL_MODE_HOST 0x3 + +/* big endian */ +#define USB_CTRL_MODE_BIG_ENDIAN 0x4 + +/* stream disable*/ +#define USB_CTRL_MODE_STREAM_DISABLE 0x10 + +/* thresh hold */ +#define USB_CTRL_FIFO_THRESH 0x00300000 + +/* register offset for usb_mode */ +#define USB_EHCI_REG_USB_MODE 0x68 + +/* register offset for usb fifo */ +#define USB_EHCI_REG_USB_FIFO 0x24 + +/* register offset for usb status */ +#define USB_EHCI_REG_USB_STATUS 0x44 + +/* serial/parallel transceiver */ +#define USB_EHCI_REG_BIT_STAT_STS (1<<29) + +/* TWI USB0 host device pin */ +#define MSP_PIN_USB0_HOST_DEV 49 + +/* TWI USB1 host device pin */ +#define MSP_PIN_USB1_HOST_DEV 50 + + +void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) +{ + u8 *base; + u8 *statreg; + u8 *fiforeg; + u32 val; + struct ehci_regs *reg_base = ehci->regs; + + /* get register base */ + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; + + /* Disable controller mode stream */ + val = ehci_readl(ehci, (u32 *)base); + ehci_writel(ehci, (val | USB_CTRL_MODE_STREAM_DISABLE), + (u32 *)base); + + /* clear STS to select parallel transceiver interface */ + val = ehci_readl(ehci, (u32 *)statreg); + val = val & ~USB_EHCI_REG_BIT_STAT_STS; + ehci_writel(ehci, val, (u32 *)statreg); + + /* write to set the proper fifo threshold */ + ehci_writel(ehci, USB_CTRL_FIFO_THRESH, (u32 *)fiforeg); + + /* set TWI GPIO USB_HOST_DEV pin high */ + gpio_direction_output(MSP_PIN_USB0_HOST_DEV, 1); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1); +#endif +} + +/* called after powerup, by probe or system-pm "wakeup" */ +static int ehci_msp_reinit(struct ehci_hcd *ehci) +{ + ehci_port_power(ehci, 0); + + return 0; +} + +/* called during probe() after chip reset completes */ +static int ehci_msp_setup(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 temp; + int retval; + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; + ehci->pmc_msp_tdi = 1; + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + hcd->has_tt = 1; + tdi_reset(ehci); + + retval = ehci_halt(ehci); + if (retval) + return retval; + + ehci_reset(ehci); + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); + temp &= 0x0f; + if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { + ehci_dbg(ehci, "bogus port configuration: " + "cc=%d x pcc=%d < ports=%d\n", + HCS_N_CC(ehci->hcs_params), + HCS_N_PCC(ehci->hcs_params), + HCS_N_PORTS(ehci->hcs_params)); + } + + retval = ehci_msp_reinit(ehci); + + return retval; +} + +/*-------------------------------------------------------------------------*/ + +static void msp_start_hc(struct platform_device *dev) +{ +} + +static void msp_stop_hc(struct platform_device *dev) +{ +} + + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_PM + +/* suspend/resume, section 4.3 */ + +/* These routines rely on the bus glue + * to handle powerdown and wakeup, and currently also on + * transceivers that don't need any software attention to set up + * the right sort of wakeup. + * Also they depend on separate root hub suspend/resume. + */ +static int ehci_msp_suspend(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + unsigned long flags; + int rc; + + return 0; + rc = 0; + + if (time_before(jiffies, ehci->next_statechange)) + msleep(10); + + /* Root hub was already suspended. Disable irq emission and + * mark HW unaccessible. The PM and USB cores make sure that + * the root hub is either suspended or stopped. + */ + spin_lock_irqsave(&ehci->lock, flags); + ehci_prepare_ports_for_controller_suspend(ehci, device_may_wakeup(dev)); + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + (void)ehci_readl(ehci, &ehci->regs->intr_enable); + + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + spin_unlock_irqrestore(&ehci->lock, flags); + + return rc; +} + +static int ehci_msp_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + + if (time_before(jiffies, ehci->next_statechange)) + msleep(100); + + /* Mark hardware accessible again as we are out of D3 state by now */ + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + /* If CF is still set, we maintained PCI Vaux power. + * Just undo the effect of ehci_pci_suspend(). + */ + if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) { + int mask = INTR_MASK; + + ehci_prepare_ports_for_controller_resume(ehci); + if (!hcd->self.root_hub->do_remote_wakeup) + mask &= ~STS_PCD; + ehci_writel(ehci, mask, &ehci->regs->intr_enable); + ehci_readl(ehci, &ehci->regs->intr_enable); + return 0; + } + + ehci_dbg(ehci, "lost power, restarting\n"); + usb_root_hub_lost_power(hcd->self.root_hub); + + /* Else reset, to cope with power loss or flush-to-storage + * style "resume" having let BIOS kick in during reboot. + */ + (void) ehci_halt(ehci); + (void) ehci_reset(ehci); + (void) ehci_msp_reinit(ehci); + + /* emptying the schedule aborts any urbs */ + spin_lock_irq(&ehci->lock); + if (ehci->reclaim) + end_unlink_async(ehci); + ehci_work(ehci); + spin_unlock_irq(&ehci->lock); + + ehci_writel(ehci, ehci->command, &ehci->regs->command); + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ + + /* here we "know" root ports should always stay powered */ + ehci_port_power(ehci, 1); + + hcd->state = HC_STATE_SUSPENDED; + + return 0; +} + +static const struct dev_pm_ops ehci_msp_pmops = { + .suspend = ehci_msp_suspend, + .resume = ehci_msp_resume, +}; +#endif + + +/* configure so an HC device and id are always provided */ +/* always called with process context; sleeping is OK */ + +static int usb_hcd_msp_map_regs(struct mspusb_device *dev) +{ + struct resource *res; + struct platform_device *pdev = &dev->dev; + u32 res_len; + int retval; + + /* MAB register space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res == NULL) + return -ENOMEM; + res_len = res->end - res->start + 1; + if (!request_mem_region(res->start, res_len, "mab regs")) + return -EBUSY; + + dev->mab_regs = ioremap_nocache(res->start, res_len); + if (dev->mab_regs == NULL) { + retval = -ENOMEM; + goto err1; + } + + /* MSP USB register space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (res == NULL) { + retval = -ENOMEM; + goto err2; + } + res_len = res->end - res->start + 1; + if (!request_mem_region(res->start, res_len, "usbid regs")) { + retval = -EBUSY; + goto err2; + } + dev->usbid_regs = ioremap_nocache(res->start, res_len); + if (dev->usbid_regs == NULL) { + retval = -ENOMEM; + goto err3; + } + + return 0; +err3: + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + res_len = res->end - res->start + 1; + release_mem_region(res->start, res_len); +err2: + iounmap(dev->mab_regs); +err1: + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + res_len = res->end - res->start + 1; + release_mem_region(res->start, res_len); + dev_err(&pdev->dev, "Failed to map non-EHCI regs.\n"); + return retval; +} + +/** + * usb_hcd_msp_probe - initialize PMC MSP-based HCDs + * Context: !in_interrupt() + * + * Allocates basic resources for this USB host controller, and + * then invokes the start() method for the HCD associated with it + * through the hotplug entry's driver_data. + * + */ +int usb_hcd_msp_probe(const struct hc_driver *driver, + struct platform_device *dev) +{ + int retval; + struct usb_hcd *hcd; + struct resource *res; + struct ehci_hcd *ehci ; + + hcd = usb_create_hcd(driver, &dev->dev, "pmcmsp"); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (res == NULL) { + pr_debug("No IOMEM resource info for %s.\n", dev->name); + retval = -ENOMEM; + goto err1; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, dev->name)) { + retval = -EBUSY; + goto err1; + } + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed"); + retval = -ENOMEM; + goto err2; + } + msp_start_hc(dev); + + res = platform_get_resource(dev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&dev->dev, "No IRQ resource info for %s.\n", dev->name); + retval = -ENOMEM; + goto err3; + } + + /* Map non-EHCI register spaces */ + retval = usb_hcd_msp_map_regs(to_mspusb_device(dev)); + if (retval != 0) + goto err3; + + ehci = hcd_to_ehci(hcd); + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; + + + retval = usb_add_hcd(hcd, res->start, IRQF_SHARED); + if (retval == 0) + return 0; + + usb_remove_hcd(hcd); +err3: + msp_stop_hc(dev); + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + + return retval; +} + + + +/** + * usb_hcd_msp_remove - shutdown processing for PMC MSP-based HCDs + * @dev: USB Host Controller being removed + * Context: !in_interrupt() + * + * Reverses the effect of usb_hcd_msp_probe(), first invoking + * the HCD's stop() method. It is always called from a thread + * context, normally "rmmod", "apmd", or something similar. + * + * may be called without controller electrically present + * may be called with controller, bus, and devices active + */ +void usb_hcd_msp_remove(struct usb_hcd *hcd, struct platform_device *dev) +{ + usb_remove_hcd(hcd); + msp_stop_hc(dev); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); +} + +#ifdef CONFIG_MSP_HAS_DUAL_USB +/*-------------------------------------------------------------------------*/ +/* + * Wrapper around the main ehci_irq. Since both USB host controllers are + * sharing the same IRQ, need to first determine whether we're the intended + * recipient of this interrupt. + */ +static irqreturn_t ehci_msp_irq(struct usb_hcd *hcd) +{ + u32 int_src; + struct device *dev = hcd->self.controller; + struct platform_device *pdev; + struct mspusb_device *mdev; + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + /* need to reverse-map a couple of containers to get our device */ + pdev = to_platform_device(dev); + mdev = to_mspusb_device(pdev); + + /* Check to see if this interrupt is for this host controller */ + int_src = ehci_readl(ehci, &mdev->mab_regs->int_stat); + if (int_src & (1 << pdev->id)) + return ehci_irq(hcd); + + /* Not for this device */ + return IRQ_NONE; +} +/*-------------------------------------------------------------------------*/ +#endif /* DUAL_USB */ + +static const struct hc_driver ehci_msp_hc_driver = { + .description = hcd_name, + .product_desc = "PMC MSP EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ +#ifdef CONFIG_MSP_HAS_DUAL_USB + .irq = ehci_msp_irq, +#else + .irq = ehci_irq, +#endif + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + */ + .reset = ehci_msp_setup, + .start = ehci_run, + .shutdown = ehci_shutdown, + .start = ehci_run, + .stop = ehci_stop, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_hcd_msp_drv_probe(struct platform_device *pdev) +{ + int ret; + + pr_debug("In ehci_hcd_msp_drv_probe"); + + if (usb_disabled()) + return -ENODEV; + + gpio_request(MSP_PIN_USB0_HOST_DEV, "USB0_HOST_DEV_GPIO"); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_request(MSP_PIN_USB1_HOST_DEV, "USB1_HOST_DEV_GPIO"); +#endif + + ret = usb_hcd_msp_probe(&ehci_msp_hc_driver, pdev); + + return ret; +} + +static int ehci_hcd_msp_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_hcd_msp_remove(hcd, pdev); + + /* free TWI GPIO USB_HOST_DEV pin */ + gpio_free(MSP_PIN_USB0_HOST_DEV); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_free(MSP_PIN_USB1_HOST_DEV); +#endif + + return 0; +} + +MODULE_ALIAS("pmcmsp-ehci"); + +static struct platform_driver ehci_hcd_msp_driver = { + .probe = ehci_hcd_msp_drv_probe, + .remove = ehci_hcd_msp_drv_remove, + .driver = { + .name = "pmcmsp-ehci", + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &ehci_msp_pmops, +#endif + }, +}; diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index f86d3fa..be739b9 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -134,6 +134,7 @@ struct ehci_hcd { /* one per controller */ unsigned amd_pll_fix:1; unsigned fs_i_thresh:1; /* Intel iso scheduling */ unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ + unsigned pmc_msp_tdi:1; /* PMC MSP tdi quirk*/ /* required for usb32 quirk */ #define OHCI_CTRL_HCFS (3 << 6) @@ -162,6 +163,13 @@ struct ehci_hcd { /* one per controller */ #endif }; +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP +extern void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci); +#else +static inline void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) +{ } +#endif + /* convert between an HCD pointer and the corresponding EHCI_HCD */ static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) { -- 1.7.0.4 From kumba@gentoo.org Tue Feb 15 12:40:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 12:40:05 +0100 (CET) Received: from qmta05.emeryville.ca.mail.comcast.net ([76.96.30.48]:52050 "EHLO qmta05.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491003Ab1BOLkC (ORCPT ); Tue, 15 Feb 2011 12:40:02 +0100 Received: from omta07.emeryville.ca.mail.comcast.net ([76.96.30.59]) by qmta05.emeryville.ca.mail.comcast.net with comcast id 8Bep1g0021GXsucA5Bftn9; Tue, 15 Feb 2011 11:39:53 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta07.emeryville.ca.mail.comcast.net with comcast id 8Bf61g0023XYSBH8UBfrpT; Tue, 15 Feb 2011 11:39:53 +0000 Message-ID: <4D5A65A2.7040101@gentoo.org> Date: Tue, 15 Feb 2011 06:38:10 -0500 From: Kumba User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Linux MIPS List Subject: [PATCH 0/2]: Add support for Dallas/Maxim DS1685/1687 RTC Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29179 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Okay, it's been a while since I last did this, so bear with me if I make any mistakes. Following this are two parts of a patch to add an RTC class driver for the Dallas/Maxim DS1685/1687 RTC chip. I'm routing it through this ML because A) I don't know any better and B) only the SGI O2 currently makes use of it. Plus people here have a really keen eye for things and can tell me if I need to do something better. The first patch is derived from an older version of the DS1685 driver I found on Google. That patch apparently made it up to akpm's -mm branch, but never made it into a -mm release and as far as I can tell, died at some undetermined point. I haven't tried contacting the original author, either. I just used the DS1685 data sheet, O2's original CMOS RTC driver, and the old code for the IP30 (Octane) RTC driver (which is the same chip) to get this working. The second patch adds in the IP32-specific bits. I can't think of a sane way to avoid mixing arch-specific code with generic code, but the register padding that IP32 needs is, as far as I can tell, unavoidable. The second patch also adds in minor differences for the DS17285/17287 RTC, which is extremely similar to the 1685. IRIX suggests IP32 is supposed to have the 17287 chips by default, but I examined four separate O2 boards and all of them have DS1687-5 chips. Even two of my Octane system boards had DS1687-5 chips. But the differences were minor enough, that they can be enabled by flipping a menuconfig item. You can even run them w/ a 1687-5 chip with no ill effects. Also, the second patch removes the old RTC access code from IP32, but it does NOT touch the power down code. That can be modified to include the ds1685.h file and allow for the deletion of 17287rtc.h down the road. The current RTC framework doesn't appear to support the extended registers used for power down anyways, so there's no way to build this into the driver itself. Though it wouldn't be very hard to add it once the base RTC class code picks up the support. Thoughts? -- Joshua Kinard Gentoo/MIPS kumba@gentoo.org "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." --Emperor Turhan, Centauri Republic From kumba@gentoo.org Tue Feb 15 12:40:24 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 12:40:32 +0100 (CET) Received: from qmta06.emeryville.ca.mail.comcast.net ([76.96.30.56]:44477 "EHLO qmta06.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491009Ab1BOLkU (ORCPT ); Tue, 15 Feb 2011 12:40:20 +0100 Received: from omta18.emeryville.ca.mail.comcast.net ([76.96.30.74]) by qmta06.emeryville.ca.mail.comcast.net with comcast id 8BgD1g0031bwxycA6BgDDq; Tue, 15 Feb 2011 11:40:13 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta18.emeryville.ca.mail.comcast.net with comcast id 8BgB1g0073XYSBH8eBgCKv; Tue, 15 Feb 2011 11:40:13 +0000 Message-ID: <4D5A65E3.1050707@gentoo.org> Date: Tue, 15 Feb 2011 06:39:15 -0500 From: Kumba User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Linux MIPS List Subject: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29180 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Add Dallas/Maxim DS1685/1687 RTC Support. Signed-off-by: Joshua Kinard --- drivers/rtc/Kconfig | 13 drivers/rtc/Makefile | 1 drivers/rtc/rtc-ds1685.c | 875 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/rtc/ds1685.h | 401 ++++++++++++++++++++ 4 files changed, 1290 insertions(+) diff -Naurp linux-2.6.37.orig/drivers/rtc/Kconfig linux-2.6.37.rtc-ds1685/drivers/rtc/Kconfig --- linux-2.6.37.orig/drivers/rtc/Kconfig 2011-02-15 02:58:36.512076002 -0500 +++ linux-2.6.37.rtc-ds1685/drivers/rtc/Kconfig 2011-02-15 04:20:59.932076001 -0500 @@ -499,6 +499,19 @@ config RTC_DRV_DS1553 This driver can also be built as a module. If so, the module will be called rtc-ds1553. +config RTC_DRV_DS1685 + tristate "Dallas/Maxim DS1685/DS1687" + depends on I2C + help + If you say yes here you get support for the Dallas/Maxim + DS1685/DS1687 timekeeping chip. + + Systems that use this chip include EPPC-405-UC modules, by + electronic system design GmbH. + + This driver can also be built as a module. If so, the module + will be called rtc-ds1685. + config RTC_DRV_DS1742 tristate "Maxim/Dallas DS1742/1743" help diff -Naurp linux-2.6.37.orig/drivers/rtc/Makefile linux-2.6.37.rtc-ds1685/drivers/rtc/Makefile --- linux-2.6.37.orig/drivers/rtc/Makefile 2011-02-15 02:58:36.512076002 -0500 +++ linux-2.6.37.rtc-ds1685/drivers/rtc/Makefile 2011-02-15 04:17:15.372075999 -0500 @@ -40,6 +40,7 @@ obj-$(CONFIG_RTC_DRV_DS1390) += rtc-ds13 obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o +obj-$(CONFIG_RTC_DRV_DS1685) += rtc-ds1685.o obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o diff -Naurp linux-2.6.37.orig/drivers/rtc/rtc-ds1685.c linux-2.6.37.rtc-ds1685/drivers/rtc/rtc-ds1685.c --- linux-2.6.37.orig/drivers/rtc/rtc-ds1685.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.37.rtc-ds1685/drivers/rtc/rtc-ds1685.c 2011-02-15 04:22:50.032076002 -0500 @@ -0,0 +1,875 @@ +/* + * An rtc driver for the Dallas DS1685/DS1687. + * + * Copyright (C) 2009 Matthias Fuchs . + * Copyright (C) 2010 Joshua Kinard . + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_PROC_FS +#include +#endif + +#define DRV_VERSION "0.3" + +static int +ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned long flags, start = jiffies; + unsigned int data; + unsigned int ctrlb, century; + unsigned int seconds, minutes, hours, wday, mday, month, years; + + /* Fetch the time info from the RTC registers. */ + ds1685_rtc_begin_data_access; + seconds = readb(®s->time.sec); + minutes = readb(®s->time.min); + hours = readb(®s->time.hour); + wday = readb(®s->time.wday); + mday = readb(®s->time.mday); + month = readb(®s->time.month); + years = readb(®s->time.year); + century = readb(®s->bank1.century); + ctrlb = readb(®s->time.ctrlb); + ds1685_rtc_end_data_access; + + /* Convert to Binary, perform fixups, and store to rtc_time. */ + tm->tm_sec = bcd2bin(seconds); + tm->tm_min = bcd2bin(minutes); + tm->tm_hour = bcd2bin(hours); + tm->tm_wday = (bcd2bin(wday) - 1); + tm->tm_mday = bcd2bin(mday); + tm->tm_mon = (bcd2bin(month) - 1); + tm->tm_year = ((bcd2bin(years) + (bcd2bin(century) * 100)) - 1900); + tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); + tm->tm_isdst = ((ctrlb & RTC_CTRL_B_DSE) ? 1 : 0); + + /* Make sure valid time was received. */ + if (rtc_valid_tm(tm) < 0) { + dev_err(dev, "retrieved date/time is not valid.\n"); + rtc_time_to_tm(0, tm); + } + return 0; +} + +static int +ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int data; + unsigned long flags, start = jiffies; + unsigned int seconds, minutes, hours, wday, mday, month, years; + unsigned int century; + + /* Fetch the time info from rtc_time. */ + seconds = bin2bcd(tm->tm_sec); + minutes = bin2bcd(tm->tm_min); + hours = bin2bcd(tm->tm_hour); + wday = bin2bcd(tm->tm_wday + 1); + mday = bin2bcd(tm->tm_mday); + month = bin2bcd(tm->tm_mon + 1); + years = bin2bcd(tm->tm_year % 100); + century = bin2bcd((tm->tm_year + 1900) / 100); + + /* + * Perform Sanity Checks: + * - Months: !> 12, Month Day != 0. + * - Month Day !> Max days in current month. + * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. + */ + if ((month > 12) || (mday == 0)) + return -EDOM; + + if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) + return -EDOM; + + if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || (tm->tm_sec >= 60) || + (wday > 7)) + return -EDOM; + + /* + * Force datamode to BCD (DM=0) and store the time values in the + * RTC registers. + */ + ds1685_rtc_begin_data_access; + data = readb(®s->time.ctrlb) & ~(RTC_CTRL_B_DM); + writeb(data, ®s->time.ctrlb); + writeb(seconds, ®s->time.sec); + writeb(minutes, ®s->time.min); + writeb(hours, ®s->time.hour); + writeb(wday, ®s->time.wday); + writeb(mday, ®s->time.mday); + writeb(month, ®s->time.month); + writeb(years, ®s->time.year); + writeb(century, ®s->bank1.century); + ds1685_rtc_end_data_access; + + return 0; +} + +static int +ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int data; + unsigned long flags, start = jiffies; + unsigned int seconds, minutes, hours, mday; + + /* Fetch the alarm info from the RTC alarm registers. */ + ds1685_rtc_begin_data_access; + seconds = readb(®s->time.sec_alrm); + minutes = readb(®s->time.min_alrm); + hours = readb(®s->time.hour_alrm); + mday = readb(®s->bank1.mday_alrm); + ds1685_rtc_end_data_access; + + /* Convert to Binary format and store in rtc_wkalrm. */ + alrm->time.tm_sec = bcd2bin(seconds); + alrm->time.tm_min = bcd2bin(minutes); + alrm->time.tm_hour = bcd2bin(hours); + alrm->time.tm_mday = bcd2bin(mday); + + return 0; +} + +static int +ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int data; + unsigned long flags, start = jiffies; + unsigned int seconds, minutes, hours, mday; + + /* Fetch the alarm info and convert to BCD. */ + seconds = bin2bcd(alrm->time.tm_sec); + minutes = bin2bcd(alrm->time.tm_min); + hours = bin2bcd(alrm->time.tm_hour); + mday = bin2bcd(alrm->time.tm_mday); + + /* Write to the four RTC alarm registers. */ + ds1685_rtc_begin_data_access; + writeb(seconds, ®s->time.sec_alrm); + writeb(minutes, ®s->time.min_alrm); + writeb(hours, ®s->time.hour_alrm); + writeb(mday, ®s->bank1.mday_alrm); + ds1685_rtc_end_data_access; + + return 0; +} + +#ifdef CONFIG_RTC_INTF_DEV +/* + * This function enables/disables an interrupt, depending on what is passed + * in irq_bit. PIE/AIE/UIE are read/written in Ctrl B, and RIE/WIE/KSE in + * Ctrl 4B. + * + * XXX: Only handles PIE/AIE/UIE at present. + */ +static inline void +ds1685_rtc_irq_ctrl(volatile unsigned char *reg, spinlock_t *lock, + const unsigned int *enabled, const unsigned int irq_bit) +{ + unsigned long flags; + + if (*enabled) { + spin_lock_irqsave(lock, flags); + writeb((readb(reg) | irq_bit), reg); + spin_unlock_irqrestore(lock, flags); + } else { + spin_lock_irqsave(lock, flags); + writeb((readb(reg) & ~(irq_bit)), reg); + spin_unlock_irqrestore(lock, flags); + } +} + +/* Replaces ioctl() RTC_PIE on/off. */ +/* 2nd arg should be 'unsigned int', but needs fix in RTC core. */ +static int +ds1685_rtc_periodic_irq_enable(struct device *dev, int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + + ds1685_rtc_irq_ctrl(&rtc->regs->time.ctrlb, &rtc->lock, + &enabled, RTC_CTRL_B_PIE); + + rtc->p_intr = enabled; + + return 0; +} + +/* Replaces ioctl() RTC_AIE on/off. */ +static int +ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + + ds1685_rtc_irq_ctrl(&rtc->regs->time.ctrlb, &rtc->lock, + &enabled, RTC_CTRL_B_AIE); + + rtc->a_intr = enabled; + + return 0; +} + +/* Replaces ioctl() RTC_UIE on/off. */ +static int +ds1685_rtc_update_irq_enable(struct device *dev, unsigned int enabled) +{ + struct ds1685_priv *rtc = dev_get_drvdata(dev); + + ds1685_rtc_irq_ctrl(&rtc->regs->time.ctrlb, &rtc->lock, + &enabled, RTC_CTRL_B_UIE); + + rtc->u_intr = enabled; + + return 0; +} + +/* + * Defunct; Will be fully replaced by IRQ API above once RTC Core is modified + * to handle RIE/WIE/KSE. + */ +static int +ds1685_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int data; + unsigned long flags; + + switch (cmd) { + case RTC_WIE_ON: + /* Allow Wake-up Alarm Interrupts */ + ds1685_rtc_begin_ctrl_access; + data = readb(®s->bank1.ctrl4b) | RTC_CTRL_4B_WIE; + writeb(data, ®s->bank1.ctrl4b); + ds1685_rtc_end_ctrl_access; + break; + + case RTC_WIE_OFF: + /* Disable Wake-up Alarm Interrupts */ + ds1685_rtc_begin_ctrl_access; + data = readb(®s->bank1.ctrl4b) & ~(RTC_CTRL_4B_WIE); + writeb(data, ®s->bank1.ctrl4b); + ds1685_rtc_end_ctrl_access; + break; + + default: + return -ENOIOCTLCMD; + } + + return 0; +} +#else +#define ds1685_ioctl NULL +#define ds1685_rtc_periodic_irq_enable NULL +#define ds1685_rtc_alarm_irq_enable NULL +#define ds1685_rtc_update_irq_enable NULL +#endif /* CONFIG_RTC_INTF_DEV */ + +static irqreturn_t +ds1685_rtc_irq_handler(int irq, void *dev_id) +{ + struct platform_device *pdev = dev_id; + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int data; + unsigned int ctrlb, ctrlc; +#if 0 + /* XXX: Ctrl4a/Ctrl4b info unused; needs support in RTC core. */ + unsigned int ctrl4a, ctrl4b; +#endif + unsigned long flags, events = RTC_IRQF; + unsigned int num_irqs = 0; + + /* Fetch data from the four registers holding IRQ info. */ + ds1685_rtc_begin_ctrl_access; + ctrlb = readb(®s->time.ctrlb); + ctrlc = readb(®s->time.ctrlc); +#if 0 + /* XXX: Ctrl4a/Ctrl4b info unused; needs support in RTC core. */ + ctrl4a = readb(®s->bank1.ctrl4a); + ctrl4b = readb(®s->bank1.ctrl4b); +#endif + ds1685_rtc_end_ctrl_access; + + /* Check to see if the IRQF bit is set. */ + if (!(ctrlc & RTC_CTRL_C_IRQF)) + return IRQ_NONE; + + /* Check for alarm interrupts. */ + if ((ctrlc & RTC_CTRL_C_AF) && + (ctrlb & RTC_CTRL_B_AIE)) { + events |= RTC_AF; + num_irqs++; + } + + /* Check for timer interrupts. */ + else if ((ctrlc & RTC_CTRL_C_UF) && + (ctrlb & RTC_CTRL_B_UIE)) { + events |= RTC_UF; + num_irqs++; + } + + /* Check for periodic interrupts. */ + else if ((ctrlc & RTC_CTRL_C_PF) && + (ctrlb & RTC_CTRL_B_PIE)) { + events |= RTC_PF; + num_irqs++; + } + + rtc_update_irq(pdata->rtc, num_irqs, events); + return IRQ_HANDLED; +} + +#ifdef CONFIG_PROC_FS +#define NUM_REGS 8 +#define NUM_SPACES 4 + +/* + * This prints out the flags of the registers for ds1685_rtc_proc. + * It's basically a hex --> binary function, just with extra spacing between + * the binary digits. It only works on single-byte hex values (8 bits), + * which is all that we need. + */ +static char* +print_regs(unsigned int *hex, char *dest) +{ + unsigned int i, j; + char *tmp = dest; + + for(i = 0; i < NUM_REGS; i++) { + *tmp++ = ((*hex & 0x80) !=0 ? '1' : '0'); + for (j = 0; j < NUM_SPACES; j++) + *tmp++ = ' '; + *hex <<= 1; + } + *tmp++ = '\0'; + + return dest; +} + +static int +ds1685_rtc_proc(struct device *dev, struct seq_file *seq) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int data; + unsigned long flags; + unsigned int ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b; + char bits[NUM_REGS][(NUM_REGS * NUM_SPACES) + NUM_REGS + 1]; + u8 ssn[8]; + + ds1685_rtc_begin_ctrl_access; + ds1685_rtc_get_ssn; + ctrla = readb(®s->time.ctrla); + ctrlb = readb(®s->time.ctrlb); + ctrlc = readb(®s->time.ctrlc); + ctrld = readb(®s->time.ctrld); + ctrl4a = readb(®s->bank1.ctrl4a); + ctrl4b = readb(®s->bank1.ctrl4b); + ds1685_rtc_end_ctrl_access; + + seq_printf(seq, + "Oscillator\t: %s\n" + "12/24hr\t\t: %s\n" + "DST\t\t: %s\n" + "Data mode\t: %s\n" + "Battery\t\t: %s\n" + "Aux batt\t: %s\n" + "Periodic IRQ\t: %s\n" + "SQW Freq\t: %s\n" + "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n" + "Register Status\t:\n" + " Ctrl A\t: " + "UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n\t\t: %s\n" + " Ctrl B\t: " + "SET PIE AIE UIE SQWE DM 24hr DSE\n\t\t: %s\n" + " Ctrl C\t: " + "IRQF PF AF UF --- --- --- ---\n\t\t: %s\n" + " Ctrl D\t: " + "VRT --- --- --- --- --- --- ---\n\t\t: %s\n" + " Ctrl 4A\t: " + "VRT2 INCR BME --- PAB RF WF KF\n\t\t: %s\n" + " Ctrl 4B\t: " + "ABE E32k CS RCE PRS RIE WIE KSE\n\t\t: %s\n", + ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), + ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), + ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), + ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), + ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), + ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), + (!(ctrl4b & RTC_CTRL_4B_E32K) ? + pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "*"), + (!((ctrl4b & RTC_CTRL_4B_E32K)) ? + sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32.768kHz"), + ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], + ssn[6], ssn[7], + print_regs(&ctrla, bits[0]), + print_regs(&ctrlb, bits[1]), + print_regs(&ctrlc, bits[2]), + print_regs(&ctrld, bits[3]), + print_regs(&ctrl4a, bits[4]), + print_regs(&ctrl4b, bits[5])); + + return 0; +} +#else +#define ds1685_rtc_proc NULL +#endif /* CONFIG_PROC_FS */ + +static const struct rtc_class_ops ds1685_rtc_ops = { + .ioctl = ds1685_ioctl, + .proc = ds1685_rtc_proc, + .read_time = ds1685_rtc_read_time, + .set_time = ds1685_rtc_set_time, + .read_alarm = ds1685_rtc_read_alarm, + .set_alarm = ds1685_rtc_set_alarm, + .irq_set_state = ds1685_rtc_periodic_irq_enable, + .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, + .update_irq_enable = ds1685_rtc_update_irq_enable, +}; + +#ifdef CONFIG_SYSFS +static ssize_t +ds1685_nvram_read(struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t pos, size_t size) +{ + struct platform_device *pdev = + to_platform_device(container_of(kobj, struct device, kobj)); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + ssize_t count; + unsigned int data; + unsigned long flags; + + spin_lock_irqsave(&pdata->lock, flags); + ds1685_rtc_switch_to_bank0; + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; + count++, size--) + if (count < NVRAM_SZ_TIME) + *buf++ = readb(®s->time.nvram1 + pos++); + else + *buf++ = readb(®s->bank0.nvram2 + pos++); + + if (size > 0) { + ds1685_rtc_switch_to_bank1; + + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; + count++, size--) { + writeb((pos - NVRAM_TOTAL_SZ_BANK0), + ®s->bank1.ext_nvram_addr); + *buf++ = readb(®s->bank1.ext_nvram_dport); + pos++; + } + + ds1685_rtc_switch_to_bank0; + } + spin_unlock_irqrestore(&pdata->lock, flags); + return count; +} + +static ssize_t +ds1685_nvram_write(struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t pos, size_t size) +{ + struct platform_device *pdev = + to_platform_device(container_of(kobj, struct device, kobj)); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + ssize_t count; + unsigned int data; + unsigned long flags; + + spin_lock_irqsave(&pdata->lock, flags); + ds1685_rtc_switch_to_bank0; + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; + count++, size--) + if (count < NVRAM_SZ_TIME) + writeb(*buf++, ®s->time.nvram1 + pos++); + else + writeb(*buf++, ®s->bank0.nvram2 + pos++); + + if (size > 0) { + ds1685_rtc_switch_to_bank1; + + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; + count++, size--) { + writeb((pos - NVRAM_TOTAL_SZ_BANK0), + ®s->bank1.ext_nvram_addr); + writeb(*buf++, ®s->bank1.ext_nvram_dport); + pos++; + } + + ds1685_rtc_switch_to_bank0; + } + spin_unlock_irqrestore(&pdata->lock, flags); + + return count; +} + +static struct bin_attribute ds1685_nvram_attr = { + .attr = { + .name = "nvram", + .mode = S_IRUGO | S_IWUSR, + }, + .read = ds1685_nvram_read, + .write = ds1685_nvram_write, + .size = NVRAM_TOTAL_SZ +}; + +static ssize_t +ds1685_sysfs_show_battery(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int data; + unsigned long flags; + + ds1685_rtc_begin_ctrl_access; + data = readb(®s->time.ctrld); + ds1685_rtc_end_ctrl_access; + + return sprintf(buf, "%s\n", + (data & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"); +} + +static DEVICE_ATTR(battery, S_IRUGO, ds1685_sysfs_show_battery, NULL); + +static ssize_t +ds1685_sysfs_show_auxbatt(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int data; + unsigned long flags; + + ds1685_rtc_begin_ctrl_access; + data = readb(®s->bank1.ctrl4a); + ds1685_rtc_end_ctrl_access; + + return sprintf(buf, "%s\n", + (data & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"); +} + +static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_sysfs_show_auxbatt, NULL); + +static ssize_t +ds1685_sysfs_show_serial(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + u8 ssn[8]; + unsigned int data; + unsigned long flags; + + ds1685_rtc_begin_ctrl_access; + ds1685_rtc_get_ssn; + ds1685_rtc_end_ctrl_access; + + return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", + ssn[0], ssn[1], ssn[2], ssn[3], + ssn[4], ssn[5], ssn[6], ssn[7]); + + return 0; +} + +static DEVICE_ATTR(serial, S_IRUGO, ds1685_sysfs_show_serial, NULL); + +static int +ds1685_sysfs_register(struct device *dev) +{ + int err; + + err = sysfs_create_bin_file(&dev->kobj, &ds1685_nvram_attr); + if (err) + return err; + + err = device_create_file(dev, &dev_attr_battery); + if (err) { + device_remove_file(dev, &dev_attr_battery); + goto out; + } + + err = device_create_file(dev, &dev_attr_auxbatt); + if (err) { + device_remove_file(dev, &dev_attr_auxbatt); + goto out; + } + + err = device_create_file(dev, &dev_attr_serial); + if (err) { + device_remove_file(dev, &dev_attr_serial); + goto out; + } + + return 0; + +out: + sysfs_remove_bin_file(&dev->kobj, &ds1685_nvram_attr); + return err; +} + +static int +ds1685_sysfs_unregister(struct device *dev) +{ + sysfs_remove_bin_file(&dev->kobj, &ds1685_nvram_attr); + device_remove_file(dev, &dev_attr_battery); + device_remove_file(dev, &dev_attr_auxbatt); + device_remove_file(dev, &dev_attr_serial); + + return 0; +} +#endif /* CONFIG_SYSFS */ + +static int __devinit +ds1685_rtc_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc = NULL; + struct device *dev = NULL; + struct resource *res = NULL; + struct ds1685_priv *pdata = NULL; + struct ds1685_rtc_regs __iomem *regs = NULL; + int ret = 0; + unsigned int data, ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b; + unsigned long flags; + + /* Get the platform resources. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENXIO; + + /* Kzalloc() some memory for the rtc device structure. */ + pdata = kzalloc(sizeof(struct ds1685_priv), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + pdata->size = res->end - res->start + 1; + + /* Request a memory region. */ + if (!request_mem_region(res->start, pdata->size, pdev->name)) { + ret = -EBUSY; + goto out; + } + + /* Set the base address for the rtc, and ioremap() its registers. */ + pdata->baseaddr = res->start; + pdata->regs = ioremap(pdata->baseaddr, pdata->size); + if (!pdata->regs) { + ret = -ENOMEM; + goto out; + } + + /* Fetch the assigned IRQ, and init the spinlock. */ + pdata->irq = platform_get_irq(pdev, 0); + spin_lock_init(&pdata->lock); + + /* Begin the RTC setup. */ + regs = pdata->regs; + dev = &pdev->dev; + ds1685_rtc_begin_ctrl_access; + + /* + * Turn the RTC on, if it was not already on and/or Enable the + * countdown chain. + */ + ctrla = readb(®s->time.ctrla); + if (!(ctrla & RTC_CTRL_A_DV1)) { + dev_warn(&pdev->dev, + "oscillator stop detected - enabled!\n"); + ctrla |= RTC_CTRL_A_DV1; + } + ctrla &= ~RTC_CTRL_A_DV2; + writeb(ctrla, ®s->time.ctrla); + + /* Prefer BCD mode (DM = 0). */ + ctrlb = readb(®s->time.ctrlb); + if (ctrlb & RTC_CTRL_B_DM) { + dev_info(&pdev->dev, "Setting data mode to BCD\n"); + ctrlb &= ~RTC_CTRL_B_DM; + writeb(ctrlb, ®s->time.ctrlb); + } + + /* Check the batteries. There can be a main and/or an aux battery. */ + ctrld = readb(®s->time.ctrld); + if (!(ctrld & RTC_CTRL_D_VRT)) + dev_warn(&pdev->dev, + "Main battery is exhausted or not available.\n"); + ctrl4a = readb(®s->bank1.ctrl4a); + if (!(ctrl4a & RTC_CTRL_4A_VRT2)) + dev_warn(&pdev->dev, + "Aux battery is exhausted or not available.\n"); + + /* Setup the interrupt handler. */ + if (pdata->irq > 0) { + /* Read Ctrl B and clear PIE/AIE/UIE. */ + ctrlb = readb(®s->time.ctrlb); + ctrlb &= ~(RTC_CTRL_B_PIE & RTC_CTRL_B_AIE & RTC_CTRL_B_UIE); + writeb(ctrlb, ®s->time.ctrlb); + + /* Reading Ctrl C auto-clears PF/AF/UF. */ + ctrlc = readb(®s->time.ctrlc); + + /* Read Ctrl 4B and clear RIE/WIE/KSE. */ + ctrl4b = readb(®s->bank1.ctrl4b); + ctrl4b &= ~(RTC_CTRL_4B_RIE & RTC_CTRL_4B_WIE & RTC_CTRL_4B_KSE); + writeb(ctrl4b, ®s->bank1.ctrl4b); + + /* Manually clear RF/WF/KF in Ctrl 4A. */ + ctrl4a = readb(®s->bank1.ctrl4a); + ctrl4a &= ~(RTC_CTRL_4A_RF & RTC_CTRL_4A_WF & RTC_CTRL_4A_KF); + writeb(ctrl4a, ®s->bank1.ctrl4a); + + /* Request an IRQ. */ + ret = request_irq(pdata->irq, ds1685_rtc_irq_handler, + IRQF_SHARED, pdev->name, pdev); + + /* Check to see if something came back. */ + if (unlikely(ret)) { + dev_warn(&pdev->dev, "RTC interrupt not available\n"); + pdata->irq = 0; + } + } + + /* Setup complete. */ + ds1685_rtc_end_ctrl_access; + + /* Register the device as an RTC. */ + rtc = rtc_device_register(pdev->name, &pdev->dev, + &ds1685_rtc_ops, THIS_MODULE); + + /* Success? */ + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto out; + } + pdata->rtc = rtc; + + /* Set driver data, register w/ sysfs. */ + platform_set_drvdata(pdev, pdata); + ret = ds1685_sysfs_register(&pdev->dev); + if (ret) { + goto out; + } + + /* Done! */ + return 0; + + + out: + /* If error, clean up. */ + if (pdata->rtc) + rtc_device_unregister(pdata->rtc); + if (pdata->irq > 0) + free_irq(pdata->irq, pdev); + if (pdata->regs) + iounmap(pdata->regs); + if (pdata->baseaddr) + release_mem_region(pdata->baseaddr, pdata->size); + kfree(pdata); + + return ret; +} + +static int __devexit +ds1685_rtc_remove(struct platform_device *pdev) +{ + struct ds1685_priv *pdata = platform_get_drvdata(pdev); + struct ds1685_rtc_regs __iomem *regs = pdata->regs; + unsigned int ctrlb, ctrlc, ctrl4a, ctrl4b; + + ds1685_sysfs_unregister(&pdev->dev); + rtc_device_unregister(pdata->rtc); + if (pdata->irq > 0) { + /* Read Ctrl B and clear PIE/AIE/UIE. */ + ctrlb = readb(®s->time.ctrlb); + ctrlb &= ~(RTC_CTRL_B_PIE & RTC_CTRL_B_AIE & RTC_CTRL_B_UIE); + writeb(ctrlb, ®s->time.ctrlb); + + /* Reading Ctrl C auto-clears PF/AF/UF. */ + ctrlc = readb(®s->time.ctrlc); + + /* Read Ctrl 4B and clear RIE/WIE/KSE. */ + ctrl4b = readb(®s->bank1.ctrl4b); + ctrl4b &= ~(RTC_CTRL_4B_RIE & RTC_CTRL_4B_WIE & RTC_CTRL_4B_KSE); + writeb(ctrl4b, ®s->bank1.ctrl4b); + + /* Manually clear RF/WF/KF in Ctrl 4A. */ + ctrl4a = readb(®s->bank1.ctrl4a); + ctrl4a &= ~(RTC_CTRL_4A_RF & RTC_CTRL_4A_WF & RTC_CTRL_4A_KF); + writeb(ctrl4a, ®s->bank1.ctrl4a); + + /* Free the IRQ. */ + free_irq(pdata->irq, pdev); + } + + iounmap(pdata->regs); + + release_mem_region(pdata->baseaddr, pdata->size); + kfree(pdata); + + return 0; +} + +static struct platform_driver ds1685_rtc_driver = { + .driver = { + .name = "rtc-ds1685", + .owner = THIS_MODULE, + }, + .probe = ds1685_rtc_probe, + .remove = __devexit_p(ds1685_rtc_remove), +}; + +static __init +int ds1685_init(void) +{ + return platform_driver_register(&ds1685_rtc_driver); +} + +static __exit +void ds1685_exit(void) +{ + platform_driver_unregister(&ds1685_rtc_driver); +} + + +module_init(ds1685_init); +module_exit(ds1685_exit); + +MODULE_AUTHOR("Matthias Fuchs , " + "Joshua Kinard "); +MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687 RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:rtc-ds1685"); diff -Naurp linux-2.6.37.orig/include/linux/rtc/ds1685.h linux-2.6.37.rtc-ds1685/include/linux/rtc/ds1685.h --- linux-2.6.37.orig/include/linux/rtc/ds1685.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.37.rtc-ds1685/include/linux/rtc/ds1685.h 2011-02-15 04:28:04.582076001 -0500 @@ -0,0 +1,401 @@ +/* + * include/linux/rtc/ds1685.h + * + * Definitions for the control registers and platform data of the + * DS1685/DS1687 RTC chip driver. + * + * Copyright (C) 2009 Matthias Fuchs + * Copyright (C) 2010 Joshua Kinard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_RTC_DS1685_H_ +#define _LINUX_RTC_DS1685_H_ + +/* + * Found in the original RTC driver for SGI IP30 (Octane) systems, it is used + * in the ds1685_begin_access macro while loop to avoid RTC access lockouts. + */ +#define DS1685_MAGIC 137 + + +/* + * NVRAM. + * - 50 bytes of NVRAM are available just past the clock registers. + * - 64 additional bytes are available in Bank0. + * - 128 additional bytes are available in Bank1. + */ +#define NVRAM_SZ_TIME 50 +#define NVRAM_SZ_BANK0 64 +#define NVRAM_SZ_BANK1 128 +#define NVRAM_TOTAL_SZ_BANK0 (NVRAM_SZ_TIME + NVRAM_SZ_BANK0) +#define NVRAM_TOTAL_SZ (NVRAM_TOTAL_SZ_BANK0 + NVRAM_SZ_BANK1) + + +/* + * Some of the register names below are not used in the actual code, but + * are made available per the DS1685/DS1687 documentation for possible + * future use if the need arises. + */ +#define RTC_SECONDS 0x00 +#define RTC_SECONDS_ALARM 0x01 +#define RTC_MINUTES 0x02 +#define RTC_MINUTES_ALARM 0x03 +#define RTC_HOURS 0x04 +#define RTC_HOURS_ALARM 0x05 +#define RTC_DAY 0x06 +#define RTC_DATE 0x07 +#define RTC_MONTH 0x08 +#define RTC_YEAR 0x09 + +#define RTC_CTRL_A 0x0a /* Control Register A */ +#define RTC_CTRL_B 0x0b /* Control Register B */ +#define RTC_CTRL_C 0x0c /* Control Register C */ +#define RTC_CTRL_D 0x0d /* Control Register D */ +#define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */ +#define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */ +#define RTC_NVRAM_START_B0 0x0e +#define RTC_NVRAM_BANK1_BASE 0x3f00 + + +/* + * Values of the RTC bits. + */ +#define BIT_0 0x01 +#define BIT_1 0x02 +#define BIT_2 0x04 +#define BIT_3 0x08 +#define BIT_4 0x10 +#define BIT_5 0x20 +#define BIT_6 0x40 +#define BIT_7 0x80 + +/* + * Bit names in Control Register A. + */ +#define RTC_CTRL_A_RS0 BIT_0 /* Rate-Selection Bit 0 */ +#define RTC_CTRL_A_RS1 BIT_1 /* Rate-Selection Bit 1 */ +#define RTC_CTRL_A_RS2 BIT_2 /* Rate-Selection Bit 2 */ +#define RTC_CTRL_A_RS3 BIT_3 /* Rate-Selection Bit 3 */ +#define RTC_CTRL_A_DV0 BIT_4 /* Bank Select */ +#define RTC_CTRL_A_DV1 BIT_5 /* Oscillator Enable */ +#define RTC_CTRL_A_DV2 BIT_6 /* Countdown Chain */ +#define RTC_CTRL_A_UIP BIT_7 /* Update In Progress */ +#define RTC_CTRL_A_RS_MASK (RTC_CTRL_A_RS0 + RTC_CTRL_A_RS1 + \ + RTC_CTRL_A_RS2 + RTC_CTRL_A_RS3) + +/* + * Bit names in Control Register B. + */ +#define RTC_CTRL_B_DSE BIT_0 /* Daylight Savings Enable */ +#define RTC_CTRL_B_2412 BIT_1 /* 12-Hr/24-Hr Mode */ +#define RTC_CTRL_B_DM BIT_2 /* Data Mode */ +#define RTC_CTRL_B_SQWE BIT_3 /* Square-Wave Enable */ +#define RTC_CTRL_B_UIE BIT_4 /* Update-Ended Interrupt-Enable */ +#define RTC_CTRL_B_AIE BIT_5 /* Alarm-Interrupt Enable */ +#define RTC_CTRL_B_PIE BIT_6 /* Periodic-Interrupt Enable */ +#define RTC_CTRL_B_SET BIT_7 /* SET Bit */ + + +/* + * Bit names in Control Register C. + * + * BIT_0, BIT_1, BIT_2, & BIT_3 are unused, always return 0, and cannot be + * written to. + */ +#define RTC_CTRL_C_UF BIT_4 /* Update-Ended Interrupt Flag */ +#define RTC_CTRL_C_AF BIT_5 /* Alarm-Interrupt Flag */ +#define RTC_CTRL_C_PF BIT_6 /* Periodic-Interrupt Flag */ +#define RTC_CTRL_C_IRQF BIT_7 /* Interrupt-Request Flag */ + + +/* + * Bit names in Control Register D. + * + * BIT_0 through BIT_6 are unused, always return 0, and cannot be written to. + */ +#define RTC_CTRL_D_VRT BIT_7 /* Valid RAM and Time */ + + +/* + * Bit names in Extended Control Register 4A. + * + * BIT_4 and BIT_5 are reserved for future use. They can be read from and + * written to, but have no effect on the RTC's operation. + */ +#define RTC_CTRL_4A_KF BIT_0 /* Kickstart Flag */ +#define RTC_CTRL_4A_WF BIT_1 /* Wake-Up Alarm Flag */ +#define RTC_CTRL_4A_RF BIT_2 /* RAM Clear Flag */ +#define RTC_CTRL_4A_PAB BIT_3 /* Power-Active Bar Control */ +#define RTC_CTRL_4A_INCR BIT_6 /* Increment-in-Progress Status */ +#define RTC_CTRL_4A_VRT2 BIT_7 /* Auxillary Battery Status */ + + +/* + * Bit names in Extended Control Register 4B. + */ +#define RTC_CTRL_4B_KSE BIT_0 /* Kickstart Interrupt-Enable */ +#define RTC_CTRL_4B_WIE BIT_1 /* Wake-Up Alarm-Interrupt Enable */ +#define RTC_CTRL_4B_RIE BIT_2 /* RAM Clear-Interrupt Enable */ +#define RTC_CTRL_4B_PRS BIT_3 /* PAB Reset-Select */ +#define RTC_CTRL_4B_RCE BIT_4 /* RAM Clear-Enable */ +#define RTC_CTRL_4B_CS BIT_5 /* Crystal Select */ +#define RTC_CTRL_4B_E32K BIT_6 /* Enable 32.768Hz Output on SQW Pin */ +#define RTC_CTRL_4B_ABE BIT_7 /* Auxillary Battery Enable */ + + +/* + * Register names in Bank 1. + * + * The DV0 bit in Control Register A must be set to 1 for these registers + * to become available, including Extended Control Registers 4A & 4B. + */ +#define RTC_BANK1_MODEL 0x40 /* Model Number */ +#define RTC_BANK1_SERIAL_BYTE_1 0x41 /* 1st Byte of Serial Number */ +#define RTC_BANK1_SERIAL_BYTE_2 0x42 /* 2nd Byte of Serial Number */ +#define RTC_BANK1_SERIAL_BYTE_3 0x43 /* 3rd Byte of Serial Number */ +#define RTC_BANK1_SERIAL_BYTE_4 0x44 /* 4th Byte of Serial Number */ +#define RTC_BANK1_SERIAL_BYTE_5 0x45 /* 5th Byte of Serial Number */ +#define RTC_BANK1_SERIAL_BYTE_6 0x46 /* 6th Byte of Serial Number */ +#define RTC_BANK1_SERIAL_CRC 0x47 /* Serial CRC Byte */ +#define RTC_BANK1_CENTURY 0x48 /* Century Counter */ +#define RTC_BANK1_DATE_ALARM 0x49 /* Date Alarm */ +#define RTC_BANK1_RAM_ADDR 0x50 /* RAM Address */ +#define RTC_BANK1_RAM_DATA_PORT 0x53 /* RAM Data Port */ + + +#ifdef CONFIG_PROC_FS +/* + * Periodic Interrupt Rates. A static character array is used for displaying + * these values in /proc when procfs is enabled. + */ +static const char *pirq_rate[16] = { + "none", "3.90625ms", "7.8125ms", "122.070µs", "244.141µs", + "488.281µs", "976.5625µs", "1.953125ms", "3.90625ms", "7.8125ms", + "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" +}; + +/* + * Square-Wave Output Frequencies. A static character array is used for + * displaying these values in /proc when procfs is enabled. + */ +static const char *sqw_freq[16] = { + "none", "256Hz", "128Hz", "8.192kHz", "4.096kHz", "2.048kHz", + "1.024kHz", "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", + "8Hz", "4Hz", "2Hz" +}; +#endif /* CONFIG_PROC_FS */ + + +#define DS1685_REG(r) volatile unsigned char r; + + +/* + * This structure defines the standard DS1286-style time registers + * that exist in both bank0 and bank1. + */ +struct ds1685_time_regs { + DS1685_REG(sec); /* Seconds */ + DS1685_REG(sec_alrm); /* Seconds Alarm */ + DS1685_REG(min); /* Minutes */ + DS1685_REG(min_alrm); /* Minutes Alarm */ + DS1685_REG(hour); /* Hours */ + DS1685_REG(hour_alrm); /* Hours Alarm */ + DS1685_REG(wday); /* Day of the Week */ + DS1685_REG(mday); /* Day of the Month */ + DS1685_REG(month); /* Current Month */ + DS1685_REG(year); /* Current Year */ + DS1685_REG(ctrla); /* Control Register A */ + DS1685_REG(ctrlb); /* Control Register B */ + DS1685_REG(ctrlc); /* Control Register C */ + DS1685_REG(ctrld); /* Control Register D */ + volatile unsigned char nvram1[NVRAM_SZ_TIME]; +}; + + +/* + * Bank0-specific registers. This is usually NVRAM. + */ +struct ds1685_bank0_regs { + volatile unsigned char nvram2[NVRAM_SZ_BANK0]; +}; + + +/* + * Bank1-specific registers. These access extended capabilities present + * in the DS1685. The DS17285/DS17287 has minor differences, including an + * RTC write counter, and two extended NVRAM address registers, for MSB + * or LSB forms of the address. + */ +struct ds1685_bank1_regs { + DS1685_REG(model); /* Model Number */ + DS1685_REG(ssn1); /* 1st Byte of Serial Number */ + DS1685_REG(ssn2); /* 2nd Byte of Serial Number */ + DS1685_REG(ssn3); /* 3rd Byte of Serial Number */ + DS1685_REG(ssn4); /* 4th Byte of Serial Number */ + DS1685_REG(ssn5); /* 5th Byte of Serial Number */ + DS1685_REG(ssn6); /* 6th Byte of Serial Number */ + DS1685_REG(crc); /* Serial # CRC Byte */ + DS1685_REG(century); /* Current Century */ + DS1685_REG(mday_alrm); /* Day of the Month Alarm */ + DS1685_REG(ctrl4a); /* Ext. Control Register 4A */ + DS1685_REG(ctrl4b); /* Ext. Control Register 4B */ + DS1685_REG(rsvrd1); /* Reserved; provides SMI */ + DS1685_REG(rsvrd2); /* Recovery Stack. Holds last */ + DS1685_REG(rtc_addr2); /* four RTC addresses for the */ + DS1685_REG(rtc_addr3); /* BIOS to recover from an SMI. */ + DS1685_REG(ext_nvram_addr); /* Ext. NVRAM Addr; DS1685/7 */ + DS1685_REG(rsvrd3); /* Reserved */ + DS1685_REG(rsvrd4); /* Reserved */ + DS1685_REG(ext_nvram_dport); /* Ext. NVRAM Data Port */ +}; + + +/* + * The actual register struct. Uses a union to combine bank0 and bank1, + * since both use the same address space, but are accessed depending on the + * state of the DV0 bit in Control Register A. + */ +struct ds1685_rtc_regs { + struct ds1685_time_regs time; + union { + struct ds1685_bank0_regs bank0; + struct ds1685_bank1_regs bank1; + }; +}; + + +/* + * DS1685/1687 data structure. + */ +struct ds1685_priv { + struct rtc_device *rtc; /* RTC device pointer */ + struct ds1685_rtc_regs __iomem *regs; /* RTC Registers */ + resource_size_t baseaddr; /* Resource base address */ + size_t size; /* Resource size */ + spinlock_t lock; /* Spinlock struct */ + int irq; /* RTC IRQ # */ + unsigned int p_intr; /* Periodic IRQ status */ + unsigned int a_intr; /* Alarm IRQ status */ + unsigned int u_intr; /* Update IRQ status */ +#if 0 /* Not used just yet; See comments in rtc-ds1685.c */ + unsigned int r_intr; /* RAM-Clear IRQ status */ + unsigned int w_intr; /* Watchdog IRQ status */ + unsigned int k_intr; /* Kickstart IRQ status */ +#endif +}; + + +/* + * These two macros set and unset the SET bit in Control Register B. The + * SET bit inhibits update transfers and allows a safe read/write of the + * time and calendar bits. + */ +#define ds1685_rtc_set_set_bit \ + data = readb(®s->time.ctrlb) | RTC_CTRL_B_SET; \ + writeb(data, ®s->time.ctrlb) + +#define ds1685_rtc_clear_set_bit \ + data = readb(®s->time.ctrlb) & ~(RTC_CTRL_B_SET); \ + writeb(data, ®s->time.ctrlb) + + +/* + * These two macros switch between bank0 and bank1. Bank0 provides access + * to the standard RTC capabilities originally defined with the DS1286 RTC. + * Bank1 provides access to extended capabilities, including extended + * control registers, silicon serial number, century counter, aux battery + * capabilities, wake-up/kick-start features and additional amounts of nvram. + */ +#define ds1685_rtc_switch_to_bank0 \ + data = readb(®s->time.ctrla) & ~(RTC_CTRL_A_DV0); \ + writeb(data, ®s->time.ctrla) + +#define ds1685_rtc_switch_to_bank1 \ + data = readb(®s->time.ctrla) | RTC_CTRL_A_DV0; \ + writeb(data, ®s->time.ctrla) + + +/* + * This begins the RTC data access, such as reading/writing clock/alarm + * registers. It performs several steps in a common block of code that is + * used quite frequently: + * + * - Sets a spinlock on the IRQ. + * - Sets the SET bit in Control Register B. + * - Reads Control Register A. + * - Checks the UIP bit in Control Register A. If UIP is active, + * a delay is forced and a check is run to see if RTC access was + * locked out. The loop runs until UIP is not set. + * - A switch to bank1 occurs. This allows access to all the relevant + * time data, since the time registers are available regardless of + * which bank is currently selected. + */ +#define ds1685_rtc_begin_data_access \ + spin_lock_irqsave(&pdata->lock, flags); \ + ds1685_rtc_set_set_bit; \ + data = readb(®s->time.ctrla); \ + while (data & RTC_CTRL_A_UIP) { \ + udelay(10); \ + if (jiffies > start + DS1685_MAGIC) { \ + dev_err(dev, "Access lockout!\n"); \ + return 1; \ + } \ + data = readb(®s->time.ctrla); \ + } \ + ds1685_rtc_switch_to_bank1 + +/* + * This ends the RTC data access: + * - It switches back to bank0. + * - It clears the SET bit in Control Register B. + * - It unsets the spinlock on the IRQ. + */ +#define ds1685_rtc_end_data_access \ + ds1685_rtc_switch_to_bank0; \ + ds1685_rtc_clear_set_bit; \ + spin_unlock_irqrestore(&pdata->lock, flags) + + +/* + * This begins the RTC access to the control registers only. Such + * accesses need far less handling, just a spinlock and a switch to + * bank1. + */ +#define ds1685_rtc_begin_ctrl_access \ + spin_lock_irqsave(&pdata->lock, flags); \ + ds1685_rtc_switch_to_bank1 + +/* + * This ends the RTC ctrl access: + * - It switches back to bank0. + * - It unsets the spinlock on the IRQ. + */ +#define ds1685_rtc_end_ctrl_access \ + ds1685_rtc_switch_to_bank0; \ + spin_unlock_irqrestore(&pdata->lock, flags) + + +/* + * This fetches the Silicon Serial Number, a unique ID specific to every + * DS1685/1687. + * + * This number starts at 0x40, and is 8-bytes long, ending at 0x47. + * The first byte is the model #, the next six bytes are the serial + * number digits, and the final byte is a CRC check byte. Together, + * they form the SSN of the RTC. + */ +#define ds1685_rtc_get_ssn \ + ssn[0] = readb(®s->bank1.model); \ + ssn[1] = readb(®s->bank1.ssn1); \ + ssn[2] = readb(®s->bank1.ssn2); \ + ssn[3] = readb(®s->bank1.ssn3); \ + ssn[4] = readb(®s->bank1.ssn4); \ + ssn[5] = readb(®s->bank1.ssn5); \ + ssn[6] = readb(®s->bank1.ssn6); \ + ssn[7] = readb(®s->bank1.crc) + +#endif /* _LINUX_RTC_DS1685_H_ */ From kumba@gentoo.org Tue Feb 15 12:40:50 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 12:40:57 +0100 (CET) Received: from qmta03.emeryville.ca.mail.comcast.net ([76.96.30.32]:56830 "EHLO qmta03.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491012Ab1BOLkf (ORCPT ); Tue, 15 Feb 2011 12:40:35 +0100 Received: from omta15.emeryville.ca.mail.comcast.net ([76.96.30.71]) by qmta03.emeryville.ca.mail.comcast.net with comcast id 8BT51g0031Y3wxoA3BgUhT; Tue, 15 Feb 2011 11:40:28 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta15.emeryville.ca.mail.comcast.net with comcast id 8BgS1g00U3XYSBH8bBgTHs; Tue, 15 Feb 2011 11:40:28 +0000 Message-ID: <4D5A65F3.8080107@gentoo.org> Date: Tue, 15 Feb 2011 06:39:31 -0500 From: Kumba User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Linux MIPS List Subject: [PATCH 2/2]: Add support for Dallas/Maxim DS1685/1687 RTC Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29181 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Wire SGI O2 (IP32) to use the rtc-ds1685 driver as its RTC. Signed-off-by: Joshua Kinard --- arch/mips/sgi-ip32/ip32-platform.c | 25 ++++++++++----- arch/mips/sgi-ip32/ip32-reset.c | 53 --------------------------------- drivers/rtc/Kconfig | 17 +++++++++- include/linux/rtc/ds1685.h | 58 +++++++++++++++++++++++++++++++++++-- 4 files changed, 88 insertions(+), 65 deletions(-) diff -Naurp linux-2.6.37.rtc-ds1685/arch/mips/sgi-ip32/ip32-platform.c linux-2.6.37.rtc-ds1685.ip32/arch/mips/sgi-ip32/ip32-platform.c --- linux-2.6.37.rtc-ds1685/arch/mips/sgi-ip32/ip32-platform.c 2011-02-15 04:19:45.882076002 -0500 +++ linux-2.6.37.rtc-ds1685.ip32/arch/mips/sgi-ip32/ip32-platform.c 2011-02-15 04:31:46.972076001 -0500 @@ -90,21 +90,30 @@ static __init int sgio2btns_devinit(void device_initcall(sgio2btns_devinit); -static struct resource sgio2_cmos_rsrc[] = { +#define MACE_RTC_RES_START (MACE_BASE + offsetof(struct sgi_mace, isa.rtc)) +#define MACE_RTC_RES_END (MACE_RTC_RES_START + 32767) + +static struct resource ip32_rtc_resources[] = { { - .start = 0x70, - .end = 0x71, - .flags = IORESOURCE_IO + .start = MACEISA_RTC_IRQ, + .end = MACEISA_RTC_IRQ, + .flags = IORESOURCE_IRQ + }, { + .start = MACE_RTC_RES_START, + .end = MACE_RTC_RES_END, + .flags = IORESOURCE_MEM, } }; -static __init int sgio2_cmos_devinit(void) + + +static __init int sgio2_rtc_devinit(void) { - return IS_ERR(platform_device_register_simple("rtc_cmos", -1, - sgio2_cmos_rsrc, 1)); + return IS_ERR(platform_device_register_simple("rtc-ds1685", -1, + ip32_rtc_resources, ARRAY_SIZE(ip32_rtc_resources))); } -device_initcall(sgio2_cmos_devinit); +device_initcall(sgio2_rtc_devinit); MODULE_AUTHOR("Ralf Baechle "); MODULE_LICENSE("GPL"); diff -Naurp linux-2.6.37.rtc-ds1685/arch/mips/sgi-ip32/ip32-reset.c linux-2.6.37.rtc-ds1685.ip32/arch/mips/sgi-ip32/ip32-reset.c --- linux-2.6.37.rtc-ds1685/arch/mips/sgi-ip32/ip32-reset.c 2011-02-15 04:19:45.882076002 -0500 +++ linux-2.6.37.rtc-ds1685.ip32/arch/mips/sgi-ip32/ip32-reset.c 2011-02-15 04:58:46.582076001 -0500 @@ -33,7 +33,7 @@ #define POWERDOWN_FREQ (HZ / 4) #define PANIC_FREQ (HZ / 8) -static struct timer_list power_timer, blink_timer, debounce_timer; +static struct timer_list power_timer, blink_timer; static int has_panicked, shuting_down; static void ip32_machine_restart(char *command) __attribute__((noreturn)); @@ -89,33 +89,6 @@ static void blink_timeout(unsigned long mod_timer(&blink_timer, jiffies + data); } -static void debounce(unsigned long data) -{ - unsigned char reg_a, reg_c, xctrl_a; - - reg_c = CMOS_READ(RTC_INTR_FLAGS); - reg_a = CMOS_READ(RTC_REG_A); - CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); - wbflush(); - xctrl_a = CMOS_READ(DS_B1_XCTRL4A); - if ((xctrl_a & DS_XCTRL4A_IFS) || (reg_c & RTC_IRQF )) { - /* Interrupt still being sent. */ - debounce_timer.expires = jiffies + 50; - add_timer(&debounce_timer); - - /* clear interrupt source */ - CMOS_WRITE(xctrl_a & ~DS_XCTRL4A_IFS, DS_B1_XCTRL4A); - CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); - return; - } - CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); - - if (has_panicked) - ip32_machine_restart(NULL); - - enable_irq(MACEISA_RTC_IRQ); -} - static inline void ip32_power_button(void) { if (has_panicked) @@ -136,27 +109,6 @@ static inline void ip32_power_button(voi add_timer(&power_timer); } -static irqreturn_t ip32_rtc_int(int irq, void *dev_id) -{ - unsigned char reg_c; - - reg_c = CMOS_READ(RTC_INTR_FLAGS); - if (!(reg_c & RTC_IRQF)) { - printk(KERN_WARNING - "%s: RTC IRQ without RTC_IRQF\n", __func__); - } - /* Wait until interrupt goes away */ - disable_irq_nosync(MACEISA_RTC_IRQ); - init_timer(&debounce_timer); - debounce_timer.function = debounce; - debounce_timer.expires = jiffies + 50; - add_timer(&debounce_timer); - - printk(KERN_DEBUG "Power button pressed\n"); - ip32_power_button(); - return IRQ_HANDLED; -} - static int panic_event(struct notifier_block *this, unsigned long event, void *ptr) { @@ -196,9 +148,6 @@ static __init int ip32_reboot_setup(void blink_timer.function = blink_timeout; atomic_notifier_chain_register(&panic_notifier_list, &panic_block); - if (request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL)) - panic("Can't allocate MACEISA RTC IRQ"); - return 0; } diff -Naurp linux-2.6.37.rtc-ds1685/drivers/rtc/Kconfig linux-2.6.37.rtc-ds1685.ip32/drivers/rtc/Kconfig --- linux-2.6.37.rtc-ds1685/drivers/rtc/Kconfig 2011-02-15 04:56:37.322076002 -0500 +++ linux-2.6.37.rtc-ds1685.ip32/drivers/rtc/Kconfig 2011-02-15 04:36:20.372076000 -0500 @@ -501,17 +501,30 @@ config RTC_DRV_DS1553 config RTC_DRV_DS1685 tristate "Dallas/Maxim DS1685/DS1687" - depends on I2C + depends on (I2C || SGI_IP32) help If you say yes here you get support for the Dallas/Maxim DS1685/DS1687 timekeeping chip. Systems that use this chip include EPPC-405-UC modules, by - electronic system design GmbH. + electronic system design GmbH, and the SGI O2 (IP32). + + This module also supports the DS17285/DS17287 timekeeping chips + that are sometimes found in place of the DS1685/DS1687 in some + SGI O2 systems. This driver can also be built as a module. If so, the module will be called rtc-ds1685. +config RTC_DRV_DS17285 + bool "Enable DS17285/DS17287 Differences" + depends on (SGI_IP32 && RTC_DRV_DS1685) + help + If your SGI O2 has one of these RTC chips instead of the more + common DS1687-5 chip, say Y here to enable the minor differences + this particular chip has. For more information, refer to the + Dallas/Maxim datasheet for the DS17285/DS17287 chip. + config RTC_DRV_DS1742 tristate "Maxim/Dallas DS1742/1743" help diff -Naurp linux-2.6.37.rtc-ds1685/include/linux/rtc/ds1685.h linux-2.6.37.rtc-ds1685.ip32/include/linux/rtc/ds1685.h --- linux-2.6.37.rtc-ds1685/include/linux/rtc/ds1685.h 2011-02-15 04:28:04.582076001 -0500 +++ linux-2.6.37.rtc-ds1685.ip32/include/linux/rtc/ds1685.h 2011-02-15 04:54:04.612076002 -0500 @@ -16,6 +16,19 @@ #define _LINUX_RTC_DS1685_H_ /* + * Note: IP32 documentation hints that IP32 systems actually have a DS17287 + * RTC chip. Having checked four different O2 systems myself, I have only + * observed DS1687-5 chips, same as in SGI Octane systems (IP30). + * + * That said, the DS17287 has some minor differences, so this driver can be + * built to support these small differences if their functionality is really + * needed. Due to the lack of actually seeing one, however, these differences + * are not tested, but follow the information provided in the DS17285/DS17287 + * data sheet. + */ + + +/* * Found in the original RTC driver for SGI IP30 (Octane) systems, it is used * in the ds1685_begin_access macro while loop to avoid RTC access lockouts. */ @@ -190,7 +203,29 @@ static const char *sqw_freq[16] = { #endif /* CONFIG_PROC_FS */ -#define DS1685_REG(r) volatile unsigned char r; +/* + * SGI O2 (IP32) Systems need 1 byte of padding between the registers in + * order for the driver to function properly. O2's should be using DS17287 + * RTC chips, but most have DS1687-5 modules instead. The differences + * between the two are minor, but accounted for anyways. + */ +#ifdef CONFIG_SGI_IP32 + #define DS1685_PAD 0xff + #define DS1685_REG(r) \ + volatile unsigned char r; \ + unsigned char r##_pad[DS1685_PAD] + #define DS1685_NVRAM1_PAD 0x31ce + #define DS1685_NVRAM2_PAD 0x7fbf + + #ifdef CONFIG_RTC_DS17285 + #define DS17285_RSVRD_PAD 0xa00 + #else + #define DS17285_RSVRD_PAD 0x2c00 + #endif +#else + #define DS1685_REG(r) \ + volatile unsigned char r; +#endif /* @@ -213,6 +248,9 @@ struct ds1685_time_regs { DS1685_REG(ctrlc); /* Control Register C */ DS1685_REG(ctrld); /* Control Register D */ volatile unsigned char nvram1[NVRAM_SZ_TIME]; +#ifdef CONFIG_SGI_IP32 + unsigned char nvram1_pad[DS1685_NVRAM1_PAD]; +#endif }; @@ -221,6 +259,9 @@ struct ds1685_time_regs { */ struct ds1685_bank0_regs { volatile unsigned char nvram2[NVRAM_SZ_BANK0]; +#ifdef CONFIG_SGI_IP32 + unsigned char nvram2_pad[DS1685_NVRAM2_PAD]; +#endif }; @@ -247,10 +288,21 @@ struct ds1685_bank1_regs { DS1685_REG(rsvrd2); /* Recovery Stack. Holds last */ DS1685_REG(rtc_addr2); /* four RTC addresses for the */ DS1685_REG(rtc_addr3); /* BIOS to recover from an SMI. */ +#ifdef CONFIG_RTC_DS17285 + DS1685_REG(ext_nvram_addr_lsb); /* LSB of NVRAM Addr; DS17285/7 */ + DS1685_REG(ext_nvram_addr_msb); /* MSB of NVRAM Addr; DS17285/7 */ +#else DS1685_REG(ext_nvram_addr); /* Ext. NVRAM Addr; DS1685/7 */ DS1685_REG(rsvrd3); /* Reserved */ +#endif DS1685_REG(rsvrd4); /* Reserved */ DS1685_REG(ext_nvram_dport); /* Ext. NVRAM Data Port */ +#ifdef CONFIG_SGI_IP32 + volatile unsigned char rsvrd_pad[DS17285_RSVRD_PAD]; +#endif +#ifdef CONFIG_RTC_DS17285 + DS1685_REG(rtc_write_cnt); /* RTC Write Counter; DS17285/7 */ +#endif }; @@ -269,7 +321,7 @@ struct ds1685_rtc_regs { /* - * DS1685/1687 data structure. + * DS1685/1687/17285/17287 data structure. */ struct ds1685_priv { struct rtc_device *rtc; /* RTC device pointer */ @@ -381,7 +433,7 @@ struct ds1685_priv { /* * This fetches the Silicon Serial Number, a unique ID specific to every - * DS1685/1687. + * DS1685/1687/17285/17287. * * This number starts at 0x40, and is 8-bytes long, ending at 0x47. * The first byte is the model #, the next six bytes are the serial From anoop.pa@gmail.com Tue Feb 15 14:51:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 14:51:24 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:55694 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491009Ab1BONvV (ORCPT ); Tue, 15 Feb 2011 14:51:21 +0100 Received: by fxm19 with SMTP id 19so197672fxm.36 for ; Tue, 15 Feb 2011 05:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=OYhG1nW4wRookKr3uunVQTqGO3hIjX+ROnZBUJgjUMw=; b=dgmmhrZpiYCNSPmgw9ueRkHpDt7xu7emlfdvjRAG1RBpO/5vB4xatCNx0oRfvLpask oswgzkVYkmdtNM6rLMJSc721afy7bDgF/twlTUhjabSfYJ03zRPAS3pRZ0ucdSBdT1Sx 6ZSerE+NxVTFRlZcSN8OkFiIlti8yo1VqSjHk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=OMBYNB2dcdGx7qFL4LWHmooCexcAg5N/b87AihmDQpzHs1ktRs6Y2yXjc+75kHryTb +YbBxE593GAMwEtj2Ly3J0yjevddMxkNK16LYdmrxnsF8/qn3Dehalubyd1Ss/S+9XIa rJj7T8hsCQ+YhoZflF4nOLqWd8yr8kkMSgSSk= Received: by 10.223.101.140 with SMTP id c12mr2776360fao.16.1297777876594; Tue, 15 Feb 2011 05:51:16 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id z1sm1650341fau.45.2011.02.15.05.51.13 (version=SSLv3 cipher=OTHER); Tue, 15 Feb 2011 05:51:15 -0800 (PST) From: "Anoop P.A" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Anoop P A Subject: [PATCH 0/2] Minor improvements to MSP pci support. Date: Tue, 15 Feb 2011 19:42:31 +0530 Message-Id: <1297779151-26595-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29182 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop P A Following set of patch created againt linux-queue head . Ignoring checkpatch warning (usage of volatile). Anoop P A (2): Introduce MSP_HAS_PCI config option. Fix pci id check. arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h | 6 +++++- arch/mips/pci/Makefile | 4 +--- arch/mips/pci/ops-pmcmsp.c | 16 +++++++++------- arch/mips/pmc-sierra/Kconfig | 12 +++++++++--- 4 files changed, 24 insertions(+), 14 deletions(-) From anoop.pa@gmail.com Tue Feb 15 14:52:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 14:52:09 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:50684 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491009Ab1BONwF (ORCPT ); Tue, 15 Feb 2011 14:52:05 +0100 Received: by ewy20 with SMTP id 20so57772ewy.36 for ; Tue, 15 Feb 2011 05:51:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=X799rDE5s2XFj1GOPajH9WnN2M41fDbmEhF3iC0H1WA=; b=iNt8SSyAN+q3+SywuKYjQffIQs8GkQKum51mSVVJoiD72ejI2qK66cN711tvSp3QAJ rbTSU2IjapPU91Nik50XbTgHIH2ZWZKH+iVyUcZlCnyo5272ZsdmV8ubkcGF/k1ck1hy wfRDTNX7UZfiE0xA0MZEUXVbi8pylORdng384= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Lo0UgbNB6359LM69mPq+n8nmzuOmFO22YVAHo3fMH70p8ohacVM3ePpE48NRtiW5Ph 1NMCtgz7U6X+3SsAkPNkhhbWaee5RwiKqL2W5xpDpkds93/8hU7aINKvdyNlZP/GbYhw 6Oydu3DjxjmKj/Zl2qR5ponAbV8mRMoUGW9WU= Received: by 10.223.101.136 with SMTP id c8mr6311911fao.100.1297777919679; Tue, 15 Feb 2011 05:51:59 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id n26sm1651004fam.37.2011.02.15.05.51.56 (version=SSLv3 cipher=OTHER); Tue, 15 Feb 2011 05:51:58 -0800 (PST) From: "Anoop P.A" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Anoop P A Subject: [PATCH 1/2] Introduce MSP_HAS_PCI config option. Date: Tue, 15 Feb 2011 19:43:17 +0530 Message-Id: <1297779197-26710-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1297779151-26595-1-git-send-email-anoop.pa@gmail.com> References: <1297779151-26595-1-git-send-email-anoop.pa@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29183 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop P A Various chips in MSP family shares PCI block. Following patch introduce MSP_HAS_PCI config option so that we can avoid adding seperate entries in arch/mips/pci/Makefile. Also getrid off SoC specific flags from ops-pmcmsp.c Signed-off-by: Anoop P A --- arch/mips/pci/Makefile | 4 +--- arch/mips/pci/ops-pmcmsp.c | 12 +++++++----- arch/mips/pmc-sierra/Kconfig | 12 +++++++++--- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c9209ca..2dd8845 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -30,9 +30,7 @@ obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o -obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o -obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o -obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o +obj-$(CONFIG_MSP_HAS_PCI) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ pci-yosemite.o obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c index 68798f8..caedf9a 100644 --- a/arch/mips/pci/ops-pmcmsp.c +++ b/arch/mips/pci/ops-pmcmsp.c @@ -31,7 +31,7 @@ #include #include -#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) +#ifdef CONFIG_MIPS_MT #include #endif @@ -206,7 +206,9 @@ static void pci_proc_init(void) } #endif /* CONFIG_PROC_FS && PCI_COUNTERS */ +#ifndef CONFIG_MIPS_MT static DEFINE_SPINLOCK(bpci_lock); +#endif /***************************************************************************** * @@ -386,7 +388,7 @@ int msp_pcibios_config_access(unsigned char access_type, unsigned long value; static char pciirqflag; int ret; -#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) +#ifdef CONFIG_MIPS_MT unsigned int vpe_status; #endif @@ -413,7 +415,7 @@ int msp_pcibios_config_access(unsigned char access_type, pciirqflag = ~0; } -#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) +#ifdef CONFIG_MIPS_MT local_irq_save(flags); vpe_status = dvpe(); #else @@ -468,7 +470,7 @@ int msp_pcibios_config_access(unsigned char access_type, /* Clear status bits */ preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F); -#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) +#ifdef CONFIG_MIPS_MT evpe(vpe_status); local_irq_restore(flags); #else @@ -478,7 +480,7 @@ int msp_pcibios_config_access(unsigned char access_type, return -1; } -#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) +#ifdef CONFIG_MIPS_MT evpe(vpe_status); local_irq_restore(flags); #else diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig index bbd7608..d4984c3 100644 --- a/arch/mips/pmc-sierra/Kconfig +++ b/arch/mips/pmc-sierra/Kconfig @@ -16,13 +16,13 @@ config PMC_MSP7120_EVAL bool "PMC-Sierra MSP7120 Eval Board" select SYS_SUPPORTS_MULTITHREADING select IRQ_MSP_CIC - select HW_HAS_PCI + select MSP_HAS_PCI config PMC_MSP7120_GW bool "PMC-Sierra MSP7120 Residential Gateway" select SYS_SUPPORTS_MULTITHREADING select IRQ_MSP_CIC - select HW_HAS_PCI + select MSP_HAS_PCI select MSP_HAS_USB select MSP_ETH @@ -30,7 +30,7 @@ config PMC_MSP7120_FPGA bool "PMC-Sierra MSP7120 FPGA" select SYS_SUPPORTS_MULTITHREADING select IRQ_MSP_CIC - select HW_HAS_PCI + select MSP_HAS_PCI endchoice @@ -50,3 +50,9 @@ config MSP_ETH config MSP_HAS_MAC boolean depends on PMC_MSP + +config MSP_HAS_PCI + boolean + select HW_HAS_PCI + depends on PMC_MSP + -- 1.7.0.4 From anoop.pa@gmail.com Tue Feb 15 14:52:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 14:52:58 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:49129 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491031Ab1BONwz (ORCPT ); Tue, 15 Feb 2011 14:52:55 +0100 Received: by fxm19 with SMTP id 19so198866fxm.36 for ; Tue, 15 Feb 2011 05:52:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=kmDjV50ss6vUMQ6w9RGNH1IkyyuDO9DHio39vh5Nr24=; b=Gt9TiBfE0anK1txlBeVpnWnYt31YRfB9SRREzjkQcX/dpjTCXRy+xO1tskKkeMc92w PFuBQSlIgGNr71/YEg8Z1y8JV51etpXTftZ8mR+Km+0qkAclRvbhRoPVx/O6txC1/EC6 Q3rQomc3IJQGjWwHfffjGwzbHy0k+7t91OeoM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=ovZGr7FLvtLqzdog3W/WfEil7u12HV9upvPMb9n4ACjtF6R6OOySzjbeMn1vC+V+b1 +c+0XthU+xpq6rrqCrMeeleLauMpvmAE5bdKU2KPSBd4dHkLnD5rMyFn4ehnr/ezLq+K nQ7F11zx4rh8lErQUdQeRsPq4Pi1ehAEQUJBo= Received: by 10.223.114.203 with SMTP id f11mr3925413faq.20.1297777969858; Tue, 15 Feb 2011 05:52:49 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id r24sm1652949fax.3.2011.02.15.05.52.45 (version=SSLv3 cipher=OTHER); Tue, 15 Feb 2011 05:52:48 -0800 (PST) From: "Anoop P.A" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Anoop P A Subject: [PATCH 2/2] Fix pci id check. Date: Tue, 15 Feb 2011 19:44:10 +0530 Message-Id: <1297779250-26798-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1297779151-26595-1-git-send-email-anoop.pa@gmail.com> References: <1297779151-26595-1-git-send-email-anoop.pa@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29184 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop P A Pci id check was failing on most of the evaluation boards. Signed-off-by: Anoop P A --- arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h | 6 +++++- arch/mips/pci/ops-pmcmsp.c | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h index 4156069..c74daca 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h @@ -26,7 +26,11 @@ #ifndef _MSP_PCI_H_ #define _MSP_PCI_H_ -#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) +#define MSP_HAS_PCI(ID) ((((u32)(ID) <= (0x4236)) && \ + ((u32)(ID) >= (0x4220))) || \ + ((u32)(ID) == (0x7140))) +#define MSP_PCI_READ_REG32(base, byte_offset) \ + (*((volatile u32 *)((u8 *)(base) + (byte_offset)))) /* * It is convenient to program the OATRAN register so that diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c index caedf9a..8d5c2e6 100644 --- a/arch/mips/pci/ops-pmcmsp.c +++ b/arch/mips/pci/ops-pmcmsp.c @@ -966,9 +966,9 @@ void __init msp_pci_init(void) u32 id; /* Extract Device ID */ - id = read_reg32(PCI_JTAG_DEVID_REG, 0xFFFF) >> 12; + id = (MSP_PCI_READ_REG32(PCI_JTAG_DEVID_REG, 0) >> 12) & 0x0FFFF; - /* Check if JTAG ID identifies MSP7120 */ + /* Check if JTAG ID identifies MSP71xx */ if (!MSP_HAS_PCI(id)) { printk(KERN_WARNING "PCI: No PCI; id reads as %x\n", id); goto no_pci; -- 1.7.0.4 From matthieu.castet@parrot.com Tue Feb 15 18:44:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 18:44:54 +0100 (CET) Received: from co202.xi-lite.net ([149.6.83.202]:54959 "EHLO co202.xi-lite.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491009Ab1BORov (ORCPT ); Tue, 15 Feb 2011 18:44:51 +0100 Received: from ONYX.xi-lite.lan (unknown [193.34.35.244]) by co202.xi-lite.net (Postfix) with ESMTPS id 82800260289; Tue, 15 Feb 2011 19:54:53 +0100 (CET) Received: from [172.20.223.18] (84.14.91.202) by mail.xi-lite.com (193.34.32.105) with Microsoft SMTP Server (TLS) id 8.1.336.0; Tue, 15 Feb 2011 17:43:40 +0000 Message-ID: <4D5ABB65.3090101@parrot.com> Date: Tue, 15 Feb 2011 18:44:05 +0100 From: Matthieu CASTET User-Agent: Thunderbird 2.0.0.24 (X11/20100228) MIME-Version: 1.0 To: Anoop P.A CC: "gregkh@suse.de" , "dbrownell@users.sourceforge.net" , "stern@rowland.harvard.edu" , "pkondeti@codeaurora.org" , "jacob.jun.pan@intel.com" , "linux-usb@vger.kernel.org" , "alek.du@intel.com" , "linux-kernel@vger.kernel.org" , "gadiyar@ti.com" , "ralf@linux-mips.org" , "linux-mips@linux-mips.org" , Greg KH Subject: Re: [PATCH v4] EHCI bus glue for on-chip PMC MSP USB controller References: <1296127736-28208-1-git-send-email-anoop.pa@gmail.com> <1297766591-11919-1-git-send-email-anoop.pa@gmail.com> In-Reply-To: <1297766591-11919-1-git-send-email-anoop.pa@gmail.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29185 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matthieu.castet@parrot.com Precedence: bulk X-list: linux-mips Anoop P.A a écrit : > From: Anoop > > This patch add bus glue for USB controller commonly found in PMC-Sierra MSP71xx family of SoC's. > Patch includes a tdi reset quirk as well . > > Signed-off-by: Anoop P A > Tested-by: Shane McDonald > --- > Changes. > ehci-pmcmsp.c is based on latest ehci-pci.c.Addressed some stylistic issue pointed by Greg. > Addressed review comments of Matthieu CASTET. > > config XPS_USB_HCD_XILINX > diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c > index cbf451a..913e7df 100644 > --- a/drivers/usb/host/ehci-hcd.c > +++ b/drivers/usb/host/ehci-hcd.c > @@ -260,6 +260,8 @@ static void tdi_reset (struct ehci_hcd *ehci) > if (ehci_big_endian_mmio(ehci)) > tmp |= USBMODE_BE; > ehci_writel(ehci, tmp, reg_ptr); > + if (ehci->pmc_msp_tdi) > + usb_hcd_tdi_set_mode(ehci); > } > > +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP > +extern void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci); > +#else > +static inline void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) > +{ } > +#endif > + > /* convert between an HCD pointer and the corresponding EHCI_HCD */ > static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) > { > -- This won't work it you build CONFIG_USB_EHCI_HCD_PMC_MSP and other ehci controller. A better alternative could something like : http://article.gmane.org/gmane.linux.usb.general/42624 > + > +/* host mode */ > +#define USB_CTRL_MODE_HOST 0x3 > + > +/* big endian */ > +#define USB_CTRL_MODE_BIG_ENDIAN 0x4 > + > +/* stream disable*/ > +#define USB_CTRL_MODE_STREAM_DISABLE 0x10 > + This doesn't seem to be used anymore. Matthieu From aoliva@redhat.com Tue Feb 15 18:56:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 18:56:47 +0100 (CET) Received: from mx1.redhat.com ([209.132.183.28]:42136 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491022Ab1BOR4n (ORCPT ); Tue, 15 Feb 2011 18:56:43 +0100 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p1FHuPLJ030148 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 15 Feb 2011 12:56:25 -0500 Received: from freie.oliva.athome.lsd.ic.unicamp.br (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p1FHuJHf002850 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 15 Feb 2011 12:56:25 -0500 Received: from livre.localdomain (livre-to-gw.oliva.athome.lsd.ic.unicamp.br [172.31.160.19]) by freie.oliva.athome.lsd.ic.unicamp.br (8.14.4/8.14.4) with ESMTP id p1FHuGaI022833; Tue, 15 Feb 2011 15:56:16 -0200 Received: from livre.localdomain (aoliva@localhost.localdomain [127.0.0.1]) by livre.localdomain (8.14.3/8.14.3/Debian-5+lenny1) with ESMTP id p1FHuC2x026366; Tue, 15 Feb 2011 15:56:12 -0200 Received: (from aoliva@localhost) by livre.localdomain (8.14.3/8.14.3/Submit) id p1FHu5pE026360; Tue, 15 Feb 2011 15:56:06 -0200 X-Authentication-Warning: livre.localdomain: aoliva set sender to aoliva@redhat.com using -f From: Alexandre Oliva To: David Daney Cc: linux-mips , GCC , binutils , Prasun Kapoor Subject: Re: RFC: A new MIPS64 ABI Organization: Free thinker, does not speak for Red Hat or its Operating System Tools Group References: <4D5990A4.2050308@caviumnetworks.com> Date: Tue, 15 Feb 2011 15:56:01 -0200 In-Reply-To: <4D5990A4.2050308@caviumnetworks.com> (David Daney's message of "Mon, 14 Feb 2011 12:29:24 -0800") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29186 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aoliva@redhat.com Precedence: bulk X-list: linux-mips On Feb 14, 2011, David Daney wrote: > Current MIPS 32-bit ABIs (both o32 and n32) are restricted to 2GB of > user virtual memory space. This is due the way MIPS32 memory space is > segmented. Only the range from 0..2^31-1 is available. Pointer > values are always sign extended. > The proposed new ABI would only be available on MIPS64 platforms. It > would be identical to the current MIPS n32 ABI *except* that pointers > would be zero-extended rather than sign-extended when resident in > registers. FTR, I don't really know why my Yeeloong is limited to 31-bit addresses, and I kind of hoped an n32 userland would improve that WRT o32, without wasting memory with longer pointers like n64 would. So, sorry if this is a dumb question, but wouldn't it be much easier to keep on using sign-extended addresses, and just make sure the kernel never allocates a virtual memory range that crosses a sign-bit change, or whatever other reason there is for addresses to be limited to the positive 2GB range in n32? -- Alexandre Oliva, freedom fighter http://FSFLA.org/~lxoliva/ You must be the change you wish to see in the world. -- Gandhi Be Free! -- http://FSFLA.org/ FSF Latin America board member Free Software Evangelist Red Hat Brazil Compiler Engineer From David.Daney@caviumnetworks.com Tue Feb 15 19:08:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 19:08:51 +0100 (CET) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:14485 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491031Ab1BOSIt (ORCPT ); Tue, 15 Feb 2011 19:08:49 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by smtp2.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 15 Feb 2011 13:08:53 -0500 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 15 Feb 2011 10:08:46 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 15 Feb 2011 10:08:46 -0800 Message-ID: <4D5AC12D.3080108@caviumnetworks.com> Date: Tue, 15 Feb 2011 10:08:45 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Alexandre Oliva CC: linux-mips , GCC , binutils , Prasun Kapoor Subject: Re: RFC: A new MIPS64 ABI References: <4D5990A4.2050308@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 15 Feb 2011 18:08:46.0219 (UTC) FILETIME=[634175B0:01CBCD3B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29187 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/15/2011 09:56 AM, Alexandre Oliva wrote: > On Feb 14, 2011, David Daney wrote: > >> Current MIPS 32-bit ABIs (both o32 and n32) are restricted to 2GB of >> user virtual memory space. This is due the way MIPS32 memory space is >> segmented. Only the range from 0..2^31-1 is available. Pointer >> values are always sign extended. > >> The proposed new ABI would only be available on MIPS64 platforms. It >> would be identical to the current MIPS n32 ABI *except* that pointers >> would be zero-extended rather than sign-extended when resident in >> registers. > > FTR, I don't really know why my Yeeloong is limited to 31-bit addresses, > and I kind of hoped an n32 userland would improve that WRT o32, without > wasting memory with longer pointers like n64 would. > > So, sorry if this is a dumb question, but wouldn't it be much easier to > keep on using sign-extended addresses, and just make sure the kernel > never allocates a virtual memory range that crosses a sign-bit change, > or whatever other reason there is for addresses to be limited to the > positive 2GB range in n32? > No, it is not possible. The MIPS (and MIPS64) hardware architecture does not allow userspace access to addresses with the high bit (two bits for mips64) set. Your complaint is a good summary of why I am thinking about n32-big. David Daney From jirislaby@gmail.com Tue Feb 15 23:16:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 23:16:40 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:33537 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491060Ab1BOWQh (ORCPT ); Tue, 15 Feb 2011 23:16:37 +0100 Received: by bwz5 with SMTP id 5so926403bwz.36 for ; Tue, 15 Feb 2011 14:16:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:x-enigmail-version:content-type :content-transfer-encoding; bh=PEplgnLS1fXrsaKRy99CZkvG2sTcsdwhyYkNzRt8eOY=; b=PFnTnjHyNy2DwJaAZVLOgC40r21ooQUZbLTtBOSD2wLdZxh80O4BWI7jnYo4n8Mw4W +Ct5i4YXVrGQhZA/srNXrfuJHQBhqGpT4yzlNmY1bFNRkjwE+gcVLi5DWL40tjzWXtog k2o/Sjf7neuUoygUQRXqErWaVKWi08phzJwiE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:x-enigmail-version:content-type :content-transfer-encoding; b=jj+w2h3+xC8ayFIAc62tWgE3oroeoVZpil/s7pjXavnp4M0Tir0hQXIaGEb6Vwv3h1 qDs/tdswXqMns5wh05Y+GqNV6Zfq1Xq9vNcXr59cKtp345tKK5YTIr8o6fOXN8PjRdqw fa4Jvy0g1vXgsfTIfR1sUkgcD769xoR7KpgWU= Received: by 10.204.121.73 with SMTP id g9mr5019570bkr.37.1297808191876; Tue, 15 Feb 2011 14:16:31 -0800 (PST) Received: from [192.168.2.129] ([217.66.174.142]) by mx.google.com with ESMTPS id u23sm2975855bkw.9.2011.02.15.14.16.29 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 15 Feb 2011 14:16:31 -0800 (PST) Message-ID: <4D5AFB3B.6080407@gmail.com> Date: Tue, 15 Feb 2011 23:16:27 +0100 From: Jiri Slaby User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; cs-CZ; rv:1.9.2.13) Gecko/20101206 SUSE/3.1.7 Thunderbird/3.1.7 MIME-Version: 1.0 To: Nikolay Ledovskikh CC: "John W. Linville" , linux-wireless@vger.kernel.org, lrodriguez@atheros.com, mickflemm@gmail.com, me@bobcopeland.com, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] ath5k: Use mips generic dma-mapping functions to avoid seqfault on AHB chips References: <20110215220929.1cc6e9d4.nledovskikh@gmail.com> <4D5AD6A6.8090505@gmail.com> <4D5AE52B.80002@gmail.com> In-Reply-To: X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29188 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jirislaby@gmail.com Precedence: bulk X-list: linux-mips On 02/15/2011 10:39 PM, Nikolay Ledovskikh wrote: >> Maybe the address you got from the platform side was already ored by >> KSEG1... > > I took a look at openwrt atheros platform code and suppose you are right. > So what we should do for now? Add pointer cast (void __iomem *)? > Because ioremap_nocache doesn't work as expected. I think it's better > to rewrote the openwrt > code, but not now. So I've found: http://www.google.com/codesearch/p?hl=en#sayuPQDVf4c/trunk/openwrt/target/linux/atheros/patches-2.6.32/100-board.patch&q=ar231x-wmac&sa=N&cd=4&ct=rc There, the res->start may be either of the following: AR531X_WLAN0 .. 0x18000000 AR531X_WLAN1 .. 0x18500000 AR2315_WLAN0 .. 0xB0000000 I suppose you have the 3rd otherwise it should die without ORing KSEG1? Or maybe MIPS guys will correct me? (The problem is that ioremap of one of the addresses above kills the box. If Nikolaj removes the ioremap and uses the address directly, it works for him. I'm saying it will die for the first 2 addresses if we remove ioremap completely -- from what I found in MIPS specs.) I _think_ there should be (instead of ioremap): sc->iobase = (void __iomem *)KSEG1ADDR(res->start); Then we do readl(sc->iobase) et al. in ath5k. thanks, -- js From jirislaby@gmail.com Tue Feb 15 23:19:00 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 15 Feb 2011 23:19:02 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:52519 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491060Ab1BOWTA (ORCPT ); Tue, 15 Feb 2011 23:19:00 +0100 Received: by bwz5 with SMTP id 5so929275bwz.36 for ; Tue, 15 Feb 2011 14:18:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:x-enigmail-version:content-type :content-transfer-encoding; bh=h6r3YEZJp2n6U6qDMjnnXhnUPK5O10wuvX2iHnsyczY=; b=CnnBbQ3VTWKrQoMnEzJO59IjUg3IXLTsaFB3QB71EJJlq2YSpNhhbSFLQiun/jyKdJ +nl/H4HrjsJihcco2Bg8kmglOInozfRcbDDOMlFNC/sidshoTWe6YZG1zSo5P9kzBQZX QXxoZFGrtrPaYSzYcQCo3pzMTO4h/th60aqyA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:x-enigmail-version:content-type :content-transfer-encoding; b=QT/e9m+m4FqyWIiylJOdOrWknDGdVusvMgSn2VyayVsFJOFpUfLDyAcfdYgW4H10jD DaYiSF4nKF05mFtJyRmsTyBpqLgPKZ0aIqkP7VLVUYGSbZZLJ12TVH6ePWSW6aRZ0rgD FUUntLeuebZ1pI+EkxDHHARMsQy9/9kbS8Gp0= Received: by 10.204.46.154 with SMTP id j26mr26567816bkf.134.1297808334658; Tue, 15 Feb 2011 14:18:54 -0800 (PST) Received: from [192.168.2.129] ([217.66.174.142]) by mx.google.com with ESMTPS id v25sm2976704bkt.18.2011.02.15.14.18.52 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 15 Feb 2011 14:18:53 -0800 (PST) Message-ID: <4D5AFBCB.1090907@gmail.com> Date: Tue, 15 Feb 2011 23:18:51 +0100 From: Jiri Slaby User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; cs-CZ; rv:1.9.2.13) Gecko/20101206 SUSE/3.1.7 Thunderbird/3.1.7 MIME-Version: 1.0 To: Nikolay Ledovskikh CC: "John W. Linville" , linux-wireless@vger.kernel.org, lrodriguez@atheros.com, mickflemm@gmail.com, me@bobcopeland.com, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] ath5k: Use mips generic dma-mapping functions to avoid seqfault on AHB chips References: <20110215220929.1cc6e9d4.nledovskikh@gmail.com> <4D5AD6A6.8090505@gmail.com> <4D5AE52B.80002@gmail.com> <4D5AFB3B.6080407@gmail.com> In-Reply-To: <4D5AFB3B.6080407@gmail.com> X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29189 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jirislaby@gmail.com Precedence: bulk X-list: linux-mips On 02/15/2011 11:16 PM, Jiri Slaby wrote: > On 02/15/2011 10:39 PM, Nikolay Ledovskikh wrote: >>> Maybe the address you got from the platform side was already ored by >>> KSEG1... >> >> I took a look at openwrt atheros platform code and suppose you are right. >> So what we should do for now? Add pointer cast (void __iomem *)? >> Because ioremap_nocache doesn't work as expected. I think it's better >> to rewrote the openwrt >> code, but not now. > > So I've found: > http://www.google.com/codesearch/p?hl=en#sayuPQDVf4c/trunk/openwrt/target/linux/atheros/patches-2.6.32/100-board.patch&q=ar231x-wmac&sa=N&cd=4&ct=rc > > There, the res->start may be either of the following: > AR531X_WLAN0 .. 0x18000000 > AR531X_WLAN1 .. 0x18500000 > AR2315_WLAN0 .. 0xB0000000 Or maybe this should be 0x10000000 in openwrt in the first place? Then ioremap should do the right thing, right? > I suppose you have the 3rd otherwise it should die without ORing KSEG1? > > Or maybe MIPS guys will correct me? (The problem is that ioremap of one > of the addresses above kills the box. If Nikolaj removes the ioremap and > uses the address directly, it works for him. I'm saying it will die for > the first 2 addresses if we remove ioremap completely -- from what I > found in MIPS specs.) > > I _think_ there should be (instead of ioremap): > sc->iobase = (void __iomem *)KSEG1ADDR(res->start); > > Then we do readl(sc->iobase) et al. in ath5k. > > thanks, -- js From ralf@duck.linux-mips.net Wed Feb 16 02:12:19 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Feb 2011 02:12:22 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:33833 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491083Ab1BPBMS (ORCPT ); Wed, 16 Feb 2011 02:12:18 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.4) with ESMTP id p1G1C7sk011909; Wed, 16 Feb 2011 02:12:07 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1G1C4oi011903; Wed, 16 Feb 2011 02:12:04 +0100 Date: Wed, 16 Feb 2011 02:12:03 +0100 From: Ralf Baechle To: Jiri Slaby Cc: Nikolay Ledovskikh , "John W. Linville" , linux-wireless@vger.kernel.org, lrodriguez@atheros.com, mickflemm@gmail.com, me@bobcopeland.com, linux-mips@linux-mips.org Subject: Re: [PATCH] ath5k: Use mips generic dma-mapping functions to avoid seqfault on AHB chips Message-ID: <20110216011203.GA5773@linux-mips.org> References: <20110215220929.1cc6e9d4.nledovskikh@gmail.com> <4D5AD6A6.8090505@gmail.com> <4D5AE52B.80002@gmail.com> <4D5AFB3B.6080407@gmail.com> <4D5AFBCB.1090907@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D5AFBCB.1090907@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29190 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 15, 2011 at 11:18:51PM +0100, Jiri Slaby wrote: > > There, the res->start may be either of the following: > > AR531X_WLAN0 .. 0x18000000 > > AR531X_WLAN1 .. 0x18500000 > > > > AR2315_WLAN0 .. 0xB0000000 > > Or maybe this should be 0x10000000 in openwrt in the first place? Then > ioremap should do the right thing, right? Yes - 0xb0000000 looks like it's a virtual address which is wrong. Rule #1: Put physical addresses in headers and code only. Rule #2: If using one of the KSEG address and address conversion macros, get rid of them, use ioremap. The KSEG macros are for use by arch core code only; for use anywhere else I reject patches these days. Ralf From nledovskikh@gmail.com Wed Feb 16 11:27:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Feb 2011 11:27:05 +0100 (CET) Received: from mail-qw0-f49.google.com ([209.85.216.49]:37566 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491000Ab1BPK1C (ORCPT ); Wed, 16 Feb 2011 11:27:02 +0100 Received: by qwj9 with SMTP id 9so1088913qwj.36 for ; Wed, 16 Feb 2011 02:26:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=zEdiJweVd+rTvAK4pRLeM8dTfaoxhDkmNctL+0ZcT84=; b=bHHB5HpzS3oT6gBOyQvgNYTqOLqOICSt20/ksmLKSq4nglu3EUT5RfTKih7SiDk+bA nfjjEBwbK/j8pWPgj2oq3HcTkJ3mM1dFBjcAPeGgDEUFpS1W/lP9oUBXama+WOO/h6Qp 6nur7142pHK6miyYOe5vO62wM+Y/sGCaax7KA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=ERHXk3ntjzsqpCGXeRBfHjPQv6Pimn04m7adKzkPbhaOUi0M0r9vdS7qNhPkWI/u8M j4wY6pLaldgA6f++hEaOA31LDCpxeqAfP/yfTv1F+RseK/mf0IhgIBJToKjTDtIdBtXg Ty60QP7BfyUPpx4BnM09LRoCBA0LxNwCVpSUM= MIME-Version: 1.0 Received: by 10.229.212.133 with SMTP id gs5mr464563qcb.192.1297852015851; Wed, 16 Feb 2011 02:26:55 -0800 (PST) Received: by 10.229.36.193 with HTTP; Wed, 16 Feb 2011 02:26:55 -0800 (PST) In-Reply-To: <20110216011203.GA5773@linux-mips.org> References: <20110215220929.1cc6e9d4.nledovskikh@gmail.com> <4D5AD6A6.8090505@gmail.com> <4D5AE52B.80002@gmail.com> <4D5AFB3B.6080407@gmail.com> <4D5AFBCB.1090907@gmail.com> <20110216011203.GA5773@linux-mips.org> Date: Wed, 16 Feb 2011 10:26:55 +0000 Message-ID: Subject: Re: [PATCH] ath5k: Use mips generic dma-mapping functions to avoid seqfault on AHB chips From: Nikolay Ledovskikh To: Ralf Baechle Cc: Jiri Slaby , "John W. Linville" , linux-wireless@vger.kernel.org, lrodriguez@atheros.com, mickflemm@gmail.com, me@bobcopeland.com, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29191 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nledovskikh@gmail.com Precedence: bulk X-list: linux-mips So, the problems are in openwrt platform patches that should be rewriten: 1. Changes needed to avoid using code like "mem=res->start" without ioremap. 2. Changes needed to avoid using NULL in first argument of dma_alloc_coherent and others. Without these changes ahb patch won't get into the kernel and we'll be lack of wisoc devices support? Is there any chance for the patch to get into the kernel and what should be done for it? (PS: Sorry for my english.) From anoop.pa@gmail.com Wed Feb 16 15:34:55 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Feb 2011 15:34:58 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:44002 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491054Ab1BPOez (ORCPT ); Wed, 16 Feb 2011 15:34:55 +0100 Received: by fxm19 with SMTP id 19so1413561fxm.36 for ; Wed, 16 Feb 2011 06:34:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=afdZGnuovKBtah44yxYrwDykYjHMBanZqAHLayrkMp0=; b=h/u3FEvDUpOIfcEE6tSLxEr4FtdYj1i2/f57zhziKBMUMpXMkbb5wJu+EHgvfYVsWq iiqWqnOUKLM0Qgld+wUlnntZj/DPZJgUwAJmBTNO73E0/Ur9ua4fhZkGXYDPMeuTbHMw eCpbkAmaTZJhsoJrNNkO5FVVp9yHCrC+b3Vx8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=xx3/G38sV7R2DtvJNgAY/XVMCOfID4akV9KZiGHx9t9D6MGjsVoIueIPboA2XOMn57 nLjBTeg3BDWM8gMUSdKo2o9RftEPhagnbtbv78yHwBiuMBLWIa+a5zbJ8BmMLZn9UFzw z89MlmyNkaZ4s3n1T9JJdH46Hi1zT0BfZJqgI= Received: by 10.223.54.132 with SMTP id q4mr822580fag.117.1297866889356; Wed, 16 Feb 2011 06:34:49 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id 5sm57423fak.23.2011.02.16.06.34.39 (version=SSLv3 cipher=OTHER); Wed, 16 Feb 2011 06:34:42 -0800 (PST) From: "Anoop P.A" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Anoop P A Subject: [PATCH] Include asm/time.h in cevt-r4k.h Date: Wed, 16 Feb 2011 20:26:07 +0530 Message-Id: <1297868167-26738-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29192 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop P A Following error occurs when compiling files which includes asm/cevt-r4k.h arch/mips/include/asm/cevt-r4k.h:21:56: error: 'enum clock_event_mode' declared inside parameter list arch/mips/include/asm/cevt-r4k.h:21:56: error: its scope is only this definition or declaration, which is probably not what you want This left unnoticed since we will not see this error if we include time.h before cevt-r4k.h . Signed-off-by: Anoop P A --- arch/mips/include/asm/cevt-r4k.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cevt-r4k.h b/arch/mips/include/asm/cevt-r4k.h index fa4328f..ae06b7f 100644 --- a/arch/mips/include/asm/cevt-r4k.h +++ b/arch/mips/include/asm/cevt-r4k.h @@ -14,6 +14,8 @@ #ifndef __ASM_CEVT_R4K_H #define __ASM_CEVT_R4K_H +#include + DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); void mips_event_handler(struct clock_event_device *dev); -- 1.7.0.4 From ralf@linux-mips.org Wed Feb 16 17:58:39 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 16 Feb 2011 17:58:43 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47932 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491113Ab1BPQ6j (ORCPT ); Wed, 16 Feb 2011 17:58:39 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p1GGwPhc032495; Wed, 16 Feb 2011 17:58:25 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1GGwNAa032492; Wed, 16 Feb 2011 17:58:23 +0100 Date: Wed, 16 Feb 2011 17:58:23 +0100 From: Ralf Baechle To: maksim.rayskiy@gmail.com Cc: linux-mips@linux-mips.org, Maksim Rayskiy Subject: Re: [PATCH v2] MIPS: move idle task creation to work queue Message-ID: <20110216165823.GA28595@linux-mips.org> References: <1297534892-29952-1-git-send-email-maksim.rayskiy@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1297534892-29952-1-git-send-email-maksim.rayskiy@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29193 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Feb 12, 2011 at 10:21:32AM -0800, maksim.rayskiy@gmail.com wrote: Thanks Maksim, applied. This solves all the problems at once and is barely more complex! Ralf From lars@metafoo.de Thu Feb 17 00:23:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 00:23:48 +0100 (CET) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:43699 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491093Ab1BPXXl (ORCPT ); Thu, 17 Feb 2011 00:23:41 +0100 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 0EA59C6D; Thu, 17 Feb 2011 00:23:34 +0100 (CET) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 2wkwkzQP5UhF; Thu, 17 Feb 2011 00:23:33 +0100 (CET) Received: from [192.168.88.141] (unknown [213.172.107.226]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 3E4BBC6C; Thu, 17 Feb 2011 00:23:28 +0100 (CET) Message-ID: <4D5C5C66.6060205@metafoo.de> Date: Thu, 17 Feb 2011 00:23:18 +0100 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20101226 Icedove/3.0.11 MIME-Version: 1.0 To: Kumba CC: Linux MIPS List , rtc-linux@googlegroups.com Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC References: <4D5A65E3.1050707@gentoo.org> In-Reply-To: <4D5A65E3.1050707@gentoo.org> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29194 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips On 02/15/2011 12:39 PM, Kumba wrote: > Add Dallas/Maxim DS1685/1687 RTC Support. > > Signed-off-by: Joshua Kinard > --- > drivers/rtc/Kconfig | 13 > drivers/rtc/Makefile | 1 > drivers/rtc/rtc-ds1685.c | 875 > +++++++++++++++++++++++++++++++++++++++++++++ > include/linux/rtc/ds1685.h | 401 ++++++++++++++++++++ > 4 files changed, 1290 insertions(+) > > diff -Naurp linux-2.6.37.orig/drivers/rtc/Kconfig > linux-2.6.37.rtc-ds1685/drivers/rtc/Kconfig > --- linux-2.6.37.orig/drivers/rtc/Kconfig 2011-02-15 > 02:58:36.512076002 -0500 > +++ linux-2.6.37.rtc-ds1685/drivers/rtc/Kconfig 2011-02-15 > 04:20:59.932076001 -0500 > @@ -499,6 +499,19 @@ config RTC_DRV_DS1553 > This driver can also be built as a module. If so, the module > will be called rtc-ds1553. > > +config RTC_DRV_DS1685 > + tristate "Dallas/Maxim DS1685/DS1687" > + depends on I2C The driver does not use any i2c functions. > + help > + If you say yes here you get support for the Dallas/Maxim > + DS1685/DS1687 timekeeping chip. > + > + Systems that use this chip include EPPC-405-UC modules, by > + electronic system design GmbH. > + > + This driver can also be built as a module. If so, the module > + will be called rtc-ds1685. > + > config RTC_DRV_DS1742 > tristate "Maxim/Dallas DS1742/1743" > help > diff -Naurp linux-2.6.37.orig/drivers/rtc/Makefile > linux-2.6.37.rtc-ds1685/drivers/rtc/Makefile > --- linux-2.6.37.orig/drivers/rtc/Makefile 2011-02-15 > 02:58:36.512076002 -0500 > +++ linux-2.6.37.rtc-ds1685/drivers/rtc/Makefile 2011-02-15 > 04:17:15.372075999 -0500 > @@ -40,6 +40,7 @@ obj-$(CONFIG_RTC_DRV_DS1390) += rtc-ds13 > obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o > obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o > obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o > +obj-$(CONFIG_RTC_DRV_DS1685) += rtc-ds1685.o > obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o > obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o > obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o > diff -Naurp linux-2.6.37.orig/drivers/rtc/rtc-ds1685.c > linux-2.6.37.rtc-ds1685/drivers/rtc/rtc-ds1685.c > --- linux-2.6.37.orig/drivers/rtc/rtc-ds1685.c 1969-12-31 > 19:00:00.000000000 -0500 > +++ linux-2.6.37.rtc-ds1685/drivers/rtc/rtc-ds1685.c 2011-02-15 > 04:22:50.032076002 -0500 > @@ -0,0 +1,875 @@ > +/* > + * An rtc driver for the Dallas DS1685/DS1687. > + * > + * Copyright (C) 2009 Matthias Fuchs . > + * Copyright (C) 2010 Joshua Kinard . > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#ifdef CONFIG_PROC_FS > +#include > +#endif > + > +#define DRV_VERSION "0.3" > + > +static int > +ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned long flags, start = jiffies; > + unsigned int data; > + unsigned int ctrlb, century; > + unsigned int seconds, minutes, hours, wday, mday, month, years; > + > + /* Fetch the time info from the RTC registers. */ > + ds1685_rtc_begin_data_access; > + seconds = readb(®s->time.sec); > + minutes = readb(®s->time.min); > + hours = readb(®s->time.hour); > + wday = readb(®s->time.wday); > + mday = readb(®s->time.mday); > + month = readb(®s->time.month); > + years = readb(®s->time.year); > + century = readb(®s->bank1.century); > + ctrlb = readb(®s->time.ctrlb); > + ds1685_rtc_end_data_access; > + > + /* Convert to Binary, perform fixups, and store to rtc_time. */ > + tm->tm_sec = bcd2bin(seconds); > + tm->tm_min = bcd2bin(minutes); > + tm->tm_hour = bcd2bin(hours); > + tm->tm_wday = (bcd2bin(wday) - 1); > + tm->tm_mday = bcd2bin(mday); > + tm->tm_mon = (bcd2bin(month) - 1); > + tm->tm_year = ((bcd2bin(years) + (bcd2bin(century) * 100)) - 1900); > + tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); > + tm->tm_isdst = ((ctrlb & RTC_CTRL_B_DSE) ? 1 : 0); > + > + /* Make sure valid time was received. */ > + if (rtc_valid_tm(tm) < 0) { > + dev_err(dev, "retrieved date/time is not valid.\n"); > + rtc_time_to_tm(0, tm); > + } Just pass the error up to rtc core. > + return 0; > +} > + > +static int > +ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int data; > + unsigned long flags, start = jiffies; > + unsigned int seconds, minutes, hours, wday, mday, month, years; > + unsigned int century; > + > + /* Fetch the time info from rtc_time. */ > + seconds = bin2bcd(tm->tm_sec); > + minutes = bin2bcd(tm->tm_min); > + hours = bin2bcd(tm->tm_hour); > + wday = bin2bcd(tm->tm_wday + 1); > + mday = bin2bcd(tm->tm_mday); > + month = bin2bcd(tm->tm_mon + 1); > + years = bin2bcd(tm->tm_year % 100); > + century = bin2bcd((tm->tm_year + 1900) / 100); > + > + /* > + * Perform Sanity Checks: > + * - Months: !> 12, Month Day != 0. > + * - Month Day !> Max days in current month. > + * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. > + */ > + if ((month > 12) || (mday == 0)) > + return -EDOM; > + > + if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) > + return -EDOM; > + > + if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || (tm->tm_sec >= 60) || > + (wday > 7)) > + return -EDOM; There is no need for theese checks the core takes care that the values are valid. > + > + /* > + * Force datamode to BCD (DM=0) and store the time values in the > + * RTC registers. > + */ > + ds1685_rtc_begin_data_access; > + data = readb(®s->time.ctrlb) & ~(RTC_CTRL_B_DM); > + writeb(data, ®s->time.ctrlb); > + writeb(seconds, ®s->time.sec); > + writeb(minutes, ®s->time.min); > + writeb(hours, ®s->time.hour); > + writeb(wday, ®s->time.wday); > + writeb(mday, ®s->time.mday); > + writeb(month, ®s->time.month); > + writeb(years, ®s->time.year); > + writeb(century, ®s->bank1.century); > + ds1685_rtc_end_data_access; > + > + return 0; > +} > + > +static int > +ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int data; > + unsigned long flags, start = jiffies; > + unsigned int seconds, minutes, hours, mday; > + > + /* Fetch the alarm info from the RTC alarm registers. */ > + ds1685_rtc_begin_data_access; > + seconds = readb(®s->time.sec_alrm); > + minutes = readb(®s->time.min_alrm); > + hours = readb(®s->time.hour_alrm); > + mday = readb(®s->bank1.mday_alrm); > + ds1685_rtc_end_data_access; > + > + /* Convert to Binary format and store in rtc_wkalrm. */ > + alrm->time.tm_sec = bcd2bin(seconds); > + alrm->time.tm_min = bcd2bin(minutes); > + alrm->time.tm_hour = bcd2bin(hours); > + alrm->time.tm_mday = bcd2bin(mday); > + return rtc_valid_tm(&arlm->time); > + return 0; > +} > + > +static int > +ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int data; > + unsigned long flags, start = jiffies; > + unsigned int seconds, minutes, hours, mday; > + > + /* Fetch the alarm info and convert to BCD. */ > + seconds = bin2bcd(alrm->time.tm_sec); > + minutes = bin2bcd(alrm->time.tm_min); > + hours = bin2bcd(alrm->time.tm_hour); > + mday = bin2bcd(alrm->time.tm_mday); > + > + /* Write to the four RTC alarm registers. */ > + ds1685_rtc_begin_data_access; > + writeb(seconds, ®s->time.sec_alrm); > + writeb(minutes, ®s->time.min_alrm); > + writeb(hours, ®s->time.hour_alrm); > + writeb(mday, ®s->bank1.mday_alrm); > + ds1685_rtc_end_data_access; > + > + return 0; > +} > + > +#ifdef CONFIG_RTC_INTF_DEV > +/* > + * This function enables/disables an interrupt, depending on what is > passed > + * in irq_bit. PIE/AIE/UIE are read/written in Ctrl B, and RIE/WIE/KSE in > + * Ctrl 4B. > + * > + * XXX: Only handles PIE/AIE/UIE at present. > + */ > +static inline void > +ds1685_rtc_irq_ctrl(volatile unsigned char *reg, spinlock_t *lock, void __iomem *reg, > + const unsigned int *enabled, const unsigned int irq_bit) Why has 'enabled' to be a pointer? > +{ > + unsigned long flags; > + > + if (*enabled) { > + spin_lock_irqsave(lock, flags); > + writeb((readb(reg) | irq_bit), reg); > + spin_unlock_irqrestore(lock, flags); > + } else { > + spin_lock_irqsave(lock, flags); > + writeb((readb(reg) & ~(irq_bit)), reg); > + spin_unlock_irqrestore(lock, flags); > + } > +} > + > +/* Replaces ioctl() RTC_PIE on/off. */ > +/* 2nd arg should be 'unsigned int', but needs fix in RTC core. */ > +static int > +ds1685_rtc_periodic_irq_enable(struct device *dev, int enabled) > +{ > + struct ds1685_priv *rtc = dev_get_drvdata(dev); > + > + ds1685_rtc_irq_ctrl(&rtc->regs->time.ctrlb, &rtc->lock, > + &enabled, RTC_CTRL_B_PIE); > + > + rtc->p_intr = enabled; > + > + return 0; > +} > + > +/* Replaces ioctl() RTC_AIE on/off. */ > +static int > +ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) > +{ > + struct ds1685_priv *rtc = dev_get_drvdata(dev); > + > + ds1685_rtc_irq_ctrl(&rtc->regs->time.ctrlb, &rtc->lock, > + &enabled, RTC_CTRL_B_AIE); > + > + rtc->a_intr = enabled; > + > + return 0; > +} > + > +/* Replaces ioctl() RTC_UIE on/off. */ > +static int > +ds1685_rtc_update_irq_enable(struct device *dev, unsigned int enabled) > +{ > + struct ds1685_priv *rtc = dev_get_drvdata(dev); > + > + ds1685_rtc_irq_ctrl(&rtc->regs->time.ctrlb, &rtc->lock, > + &enabled, RTC_CTRL_B_UIE); > + > + rtc->u_intr = enabled; > + > + return 0; > +} > + > +/* > + * Defunct; Will be fully replaced by IRQ API above once RTC Core is > modified > + * to handle RIE/WIE/KSE. > + */ > +static int > +ds1685_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int data; > + unsigned long flags; > + > + switch (cmd) { > + case RTC_WIE_ON: > + /* Allow Wake-up Alarm Interrupts */ > + ds1685_rtc_begin_ctrl_access; > + data = readb(®s->bank1.ctrl4b) | RTC_CTRL_4B_WIE; > + writeb(data, ®s->bank1.ctrl4b); > + ds1685_rtc_end_ctrl_access; > + break; > + > + case RTC_WIE_OFF: > + /* Disable Wake-up Alarm Interrupts */ > + ds1685_rtc_begin_ctrl_access; > + data = readb(®s->bank1.ctrl4b) & ~(RTC_CTRL_4B_WIE); > + writeb(data, ®s->bank1.ctrl4b); > + ds1685_rtc_end_ctrl_access; > + break; > + > + default: > + return -ENOIOCTLCMD; > + } > + > + return 0; > +} > +#else > +#define ds1685_ioctl NULL > +#define ds1685_rtc_periodic_irq_enable NULL > +#define ds1685_rtc_alarm_irq_enable NULL > +#define ds1685_rtc_update_irq_enable NULL > +#endif /* CONFIG_RTC_INTF_DEV */ > + > +static irqreturn_t > +ds1685_rtc_irq_handler(int irq, void *dev_id) > +{ > + struct platform_device *pdev = dev_id; > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int data; > + unsigned int ctrlb, ctrlc; > +#if 0 > + /* XXX: Ctrl4a/Ctrl4b info unused; needs support in RTC core. */ > + unsigned int ctrl4a, ctrl4b; > +#endif > + unsigned long flags, events = RTC_IRQF; > + unsigned int num_irqs = 0; > + > + /* Fetch data from the four registers holding IRQ info. */ > + ds1685_rtc_begin_ctrl_access; > + ctrlb = readb(®s->time.ctrlb); > + ctrlc = readb(®s->time.ctrlc); > +#if 0 > + /* XXX: Ctrl4a/Ctrl4b info unused; needs support in RTC core. */ > + ctrl4a = readb(®s->bank1.ctrl4a); > + ctrl4b = readb(®s->bank1.ctrl4b); > +#endif > + ds1685_rtc_end_ctrl_access; > + > + /* Check to see if the IRQF bit is set. */ > + if (!(ctrlc & RTC_CTRL_C_IRQF)) > + return IRQ_NONE; > + > + /* Check for alarm interrupts. */ > + if ((ctrlc & RTC_CTRL_C_AF) && > + (ctrlb & RTC_CTRL_B_AIE)) { > + events |= RTC_AF; > + num_irqs++; > + } > + > + /* Check for timer interrupts. */ > + else if ((ctrlc & RTC_CTRL_C_UF) && > + (ctrlb & RTC_CTRL_B_UIE)) { > + events |= RTC_UF; > + num_irqs++; > + } > + > + /* Check for periodic interrupts. */ > + else if ((ctrlc & RTC_CTRL_C_PF) && > + (ctrlb & RTC_CTRL_B_PIE)) { > + events |= RTC_PF; > + num_irqs++; > + } > + > + rtc_update_irq(pdata->rtc, num_irqs, events); > + return IRQ_HANDLED; > +} > + > +#ifdef CONFIG_PROC_FS > +#define NUM_REGS 8 > +#define NUM_SPACES 4 > + > +/* > + * This prints out the flags of the registers for ds1685_rtc_proc. > + * It's basically a hex --> binary function, just with extra spacing > between > + * the binary digits. It only works on single-byte hex values (8 bits), > + * which is all that we need. > + */ > +static char* > +print_regs(unsigned int *hex, char *dest) > +{ > + unsigned int i, j; > + char *tmp = dest; > + > + for(i = 0; i < NUM_REGS; i++) { > + *tmp++ = ((*hex & 0x80) !=0 ? '1' : '0'); > + for (j = 0; j < NUM_SPACES; j++) > + *tmp++ = ' '; > + *hex <<= 1; > + } > + *tmp++ = '\0'; > + > + return dest; > +} > + > +static int > +ds1685_rtc_proc(struct device *dev, struct seq_file *seq) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int data; > + unsigned long flags; > + unsigned int ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b; > + char bits[NUM_REGS][(NUM_REGS * NUM_SPACES) + NUM_REGS + 1]; > + u8 ssn[8]; > + > + ds1685_rtc_begin_ctrl_access; > + ds1685_rtc_get_ssn; > + ctrla = readb(®s->time.ctrla); > + ctrlb = readb(®s->time.ctrlb); > + ctrlc = readb(®s->time.ctrlc); > + ctrld = readb(®s->time.ctrld); > + ctrl4a = readb(®s->bank1.ctrl4a); > + ctrl4b = readb(®s->bank1.ctrl4b); > + ds1685_rtc_end_ctrl_access; > + > + seq_printf(seq, > + "Oscillator\t: %s\n" > + "12/24hr\t\t: %s\n" > + "DST\t\t: %s\n" > + "Data mode\t: %s\n" > + "Battery\t\t: %s\n" > + "Aux batt\t: %s\n" > + "Periodic IRQ\t: %s\n" > + "SQW Freq\t: %s\n" > + "Serial #\t: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n" > + "Register Status\t:\n" > + " Ctrl A\t: " > + "UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n\t\t: %s\n" > + " Ctrl B\t: " > + "SET PIE AIE UIE SQWE DM 24hr DSE\n\t\t: %s\n" > + " Ctrl C\t: " > + "IRQF PF AF UF --- --- --- ---\n\t\t: %s\n" > + " Ctrl D\t: " > + "VRT --- --- --- --- --- --- ---\n\t\t: %s\n" > + " Ctrl 4A\t: " > + "VRT2 INCR BME --- PAB RF WF KF\n\t\t: %s\n" > + " Ctrl 4B\t: " > + "ABE E32k CS RCE PRS RIE WIE KSE\n\t\t: %s\n", > + ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), > + ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), > + ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), > + ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), > + ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), > + ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), > + (!(ctrl4b & RTC_CTRL_4B_E32K) ? > + pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "*"), > + (!((ctrl4b & RTC_CTRL_4B_E32K)) ? > + sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32.768kHz"), > + ssn[0], ssn[1], ssn[2], ssn[3], ssn[4], ssn[5], > + ssn[6], ssn[7], > + print_regs(&ctrla, bits[0]), > + print_regs(&ctrlb, bits[1]), > + print_regs(&ctrlc, bits[2]), > + print_regs(&ctrld, bits[3]), > + print_regs(&ctrl4a, bits[4]), > + print_regs(&ctrl4b, bits[5])); > + > + return 0; > +} > +#else > +#define ds1685_rtc_proc NULL > +#endif /* CONFIG_PROC_FS */ > + > +static const struct rtc_class_ops ds1685_rtc_ops = { > + .ioctl = ds1685_ioctl, > + .proc = ds1685_rtc_proc, > + .read_time = ds1685_rtc_read_time, > + .set_time = ds1685_rtc_set_time, > + .read_alarm = ds1685_rtc_read_alarm, > + .set_alarm = ds1685_rtc_set_alarm, > + .irq_set_state = ds1685_rtc_periodic_irq_enable, > + .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, > + .update_irq_enable = ds1685_rtc_update_irq_enable, > +}; > + > +#ifdef CONFIG_SYSFS > +static ssize_t > +ds1685_nvram_read(struct kobject *kobj, > + struct bin_attribute *bin_attr, > + char *buf, loff_t pos, size_t size) > +{ > + struct platform_device *pdev = > + to_platform_device(container_of(kobj, struct device, kobj)); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + ssize_t count; > + unsigned int data; > + unsigned long flags; > + > + spin_lock_irqsave(&pdata->lock, flags); > + ds1685_rtc_switch_to_bank0; > + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; > + count++, size--) > + if (count < NVRAM_SZ_TIME) > + *buf++ = readb(®s->time.nvram1 + pos++); > + else > + *buf++ = readb(®s->bank0.nvram2 + pos++); > + > + if (size > 0) { > + ds1685_rtc_switch_to_bank1; > + > + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; > + count++, size--) { > + writeb((pos - NVRAM_TOTAL_SZ_BANK0), > + ®s->bank1.ext_nvram_addr); > + *buf++ = readb(®s->bank1.ext_nvram_dport); > + pos++; > + } > + > + ds1685_rtc_switch_to_bank0; > + } > + spin_unlock_irqrestore(&pdata->lock, flags); > + return count; > +} > + > +static ssize_t > +ds1685_nvram_write(struct kobject *kobj, > + struct bin_attribute *bin_attr, > + char *buf, loff_t pos, size_t size) > +{ > + struct platform_device *pdev = > + to_platform_device(container_of(kobj, struct device, kobj)); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + ssize_t count; > + unsigned int data; > + unsigned long flags; > + > + spin_lock_irqsave(&pdata->lock, flags); > + ds1685_rtc_switch_to_bank0; > + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; > + count++, size--) > + if (count < NVRAM_SZ_TIME) > + writeb(*buf++, ®s->time.nvram1 + pos++); > + else > + writeb(*buf++, ®s->bank0.nvram2 + pos++); > + > + if (size > 0) { > + ds1685_rtc_switch_to_bank1; > + > + for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; > + count++, size--) { > + writeb((pos - NVRAM_TOTAL_SZ_BANK0), > + ®s->bank1.ext_nvram_addr); > + writeb(*buf++, ®s->bank1.ext_nvram_dport); > + pos++; > + } > + > + ds1685_rtc_switch_to_bank0; > + } > + spin_unlock_irqrestore(&pdata->lock, flags); > + > + return count; > +} > + > +static struct bin_attribute ds1685_nvram_attr = { > + .attr = { > + .name = "nvram", > + .mode = S_IRUGO | S_IWUSR, > + }, > + .read = ds1685_nvram_read, > + .write = ds1685_nvram_write, > + .size = NVRAM_TOTAL_SZ > +}; > + > +static ssize_t > +ds1685_sysfs_show_battery(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int data; > + unsigned long flags; > + > + ds1685_rtc_begin_ctrl_access; > + data = readb(®s->time.ctrld); > + ds1685_rtc_end_ctrl_access; > + > + return sprintf(buf, "%s\n", > + (data & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"); > +} > + > +static DEVICE_ATTR(battery, S_IRUGO, ds1685_sysfs_show_battery, NULL); > + > +static ssize_t > +ds1685_sysfs_show_auxbatt(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int data; > + unsigned long flags; > + > + ds1685_rtc_begin_ctrl_access; > + data = readb(®s->bank1.ctrl4a); > + ds1685_rtc_end_ctrl_access; > + > + return sprintf(buf, "%s\n", > + (data & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"); > +} > + > +static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_sysfs_show_auxbatt, NULL); > + > +static ssize_t > +ds1685_sysfs_show_serial(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + u8 ssn[8]; > + unsigned int data; > + unsigned long flags; > + > + ds1685_rtc_begin_ctrl_access; > + ds1685_rtc_get_ssn; > + ds1685_rtc_end_ctrl_access; > + > + return sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", > + ssn[0], ssn[1], ssn[2], ssn[3], > + ssn[4], ssn[5], ssn[6], ssn[7]); > + > + return 0; > +} > + > +static DEVICE_ATTR(serial, S_IRUGO, ds1685_sysfs_show_serial, NULL); > + > +static int > +ds1685_sysfs_register(struct device *dev) > +{ > + int err; > + > + err = sysfs_create_bin_file(&dev->kobj, &ds1685_nvram_attr); > + if (err) > + return err; > + > + err = device_create_file(dev, &dev_attr_battery); > + if (err) { > + device_remove_file(dev, &dev_attr_battery); > + goto out; > + } > + > + err = device_create_file(dev, &dev_attr_auxbatt); > + if (err) { > + device_remove_file(dev, &dev_attr_auxbatt); > + goto out; > + } > + > + err = device_create_file(dev, &dev_attr_serial); > + if (err) { > + device_remove_file(dev, &dev_attr_serial); > + goto out; > + } > + > + return 0; > + > +out: > + sysfs_remove_bin_file(&dev->kobj, &ds1685_nvram_attr); > + return err; > +} > + > +static int > +ds1685_sysfs_unregister(struct device *dev) > +{ > + sysfs_remove_bin_file(&dev->kobj, &ds1685_nvram_attr); > + device_remove_file(dev, &dev_attr_battery); > + device_remove_file(dev, &dev_attr_auxbatt); > + device_remove_file(dev, &dev_attr_serial); > + > + return 0; > +} > +#endif /* CONFIG_SYSFS */ > + > +static int __devinit > +ds1685_rtc_probe(struct platform_device *pdev) > +{ > + struct rtc_device *rtc = NULL; > + struct device *dev = NULL; > + struct resource *res = NULL; > + struct ds1685_priv *pdata = NULL; > + struct ds1685_rtc_regs __iomem *regs = NULL; > + int ret = 0; > + unsigned int data, ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b; > + unsigned long flags; > + > + /* Get the platform resources. */ > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) > + return -ENXIO; > + > + /* Kzalloc() some memory for the rtc device structure. */ > + pdata = kzalloc(sizeof(struct ds1685_priv), GFP_KERNEL); > + if (!pdata) > + return -ENOMEM; > + pdata->size = res->end - res->start + 1; resource_size(res) instead of res->end - res->start + 1 and it would be easier to just save the pointer to res instead of saving both size and start; > + > + /* Request a memory region. */ > + if (!request_mem_region(res->start, pdata->size, pdev->name)) { > + ret = -EBUSY; > + goto out; > + } > + > + /* Set the base address for the rtc, and ioremap() its registers. */ > + pdata->baseaddr = res->start; > + pdata->regs = ioremap(pdata->baseaddr, pdata->size); > + if (!pdata->regs) { > + ret = -ENOMEM; > + goto out; > + } > + > + /* Fetch the assigned IRQ, and init the spinlock. */ > + pdata->irq = platform_get_irq(pdev, 0); > + spin_lock_init(&pdata->lock); > + > + /* Begin the RTC setup. */ > + regs = pdata->regs; > + dev = &pdev->dev; > + ds1685_rtc_begin_ctrl_access; > + > + /* > + * Turn the RTC on, if it was not already on and/or Enable the > + * countdown chain. > + */ > + ctrla = readb(®s->time.ctrla); > + if (!(ctrla & RTC_CTRL_A_DV1)) { > + dev_warn(&pdev->dev, > + "oscillator stop detected - enabled!\n"); > + ctrla |= RTC_CTRL_A_DV1; > + } > + ctrla &= ~RTC_CTRL_A_DV2; > + writeb(ctrla, ®s->time.ctrla); > + > + /* Prefer BCD mode (DM = 0). */ > + ctrlb = readb(®s->time.ctrlb); > + if (ctrlb & RTC_CTRL_B_DM) { > + dev_info(&pdev->dev, "Setting data mode to BCD\n"); > + ctrlb &= ~RTC_CTRL_B_DM; > + writeb(ctrlb, ®s->time.ctrlb); > + } > + > + /* Check the batteries. There can be a main and/or an aux battery. */ > + ctrld = readb(®s->time.ctrld); > + if (!(ctrld & RTC_CTRL_D_VRT)) > + dev_warn(&pdev->dev, > + "Main battery is exhausted or not available.\n"); > + ctrl4a = readb(®s->bank1.ctrl4a); > + if (!(ctrl4a & RTC_CTRL_4A_VRT2)) > + dev_warn(&pdev->dev, > + "Aux battery is exhausted or not available.\n"); > + > + /* Setup the interrupt handler. */ > + if (pdata->irq > 0) { > + /* Read Ctrl B and clear PIE/AIE/UIE. */ > + ctrlb = readb(®s->time.ctrlb); > + ctrlb &= ~(RTC_CTRL_B_PIE & RTC_CTRL_B_AIE & RTC_CTRL_B_UIE); > + writeb(ctrlb, ®s->time.ctrlb); > + > + /* Reading Ctrl C auto-clears PF/AF/UF. */ > + ctrlc = readb(®s->time.ctrlc); > + > + /* Read Ctrl 4B and clear RIE/WIE/KSE. */ > + ctrl4b = readb(®s->bank1.ctrl4b); > + ctrl4b &= ~(RTC_CTRL_4B_RIE & RTC_CTRL_4B_WIE & RTC_CTRL_4B_KSE); > + writeb(ctrl4b, ®s->bank1.ctrl4b); > + > + /* Manually clear RF/WF/KF in Ctrl 4A. */ > + ctrl4a = readb(®s->bank1.ctrl4a); > + ctrl4a &= ~(RTC_CTRL_4A_RF & RTC_CTRL_4A_WF & RTC_CTRL_4A_KF); > + writeb(ctrl4a, ®s->bank1.ctrl4a); > + > + /* Request an IRQ. */ > + ret = request_irq(pdata->irq, ds1685_rtc_irq_handler, > + IRQF_SHARED, pdev->name, pdev); > + > + /* Check to see if something came back. */ > + if (unlikely(ret)) { > + dev_warn(&pdev->dev, "RTC interrupt not available\n"); > + pdata->irq = 0; > + } > + } > + > + /* Setup complete. */ > + ds1685_rtc_end_ctrl_access; > + > + /* Register the device as an RTC. */ > + rtc = rtc_device_register(pdev->name, &pdev->dev, > + &ds1685_rtc_ops, THIS_MODULE); > + > + /* Success? */ > + if (IS_ERR(rtc)) { > + ret = PTR_ERR(rtc); > + goto out; > + } > + pdata->rtc = rtc; > + > + /* Set driver data, register w/ sysfs. */ > + platform_set_drvdata(pdev, pdata); > + ret = ds1685_sysfs_register(&pdev->dev); If CONFIG_SYSFS is not defined you'll get an compile error. > + if (ret) { > + goto out; > + } > + > + /* Done! */ > + return 0; > + > + > + out: > + /* If error, clean up. */ > + if (pdata->rtc) > + rtc_device_unregister(pdata->rtc); > + if (pdata->irq > 0) > + free_irq(pdata->irq, pdev); > + if (pdata->regs) > + iounmap(pdata->regs); > + if (pdata->baseaddr) > + release_mem_region(pdata->baseaddr, pdata->size); > + kfree(pdata); > + > + return ret; > +} > + > +static int __devexit > +ds1685_rtc_remove(struct platform_device *pdev) > +{ > + struct ds1685_priv *pdata = platform_get_drvdata(pdev); > + struct ds1685_rtc_regs __iomem *regs = pdata->regs; > + unsigned int ctrlb, ctrlc, ctrl4a, ctrl4b; > + > + ds1685_sysfs_unregister(&pdev->dev); > + rtc_device_unregister(pdata->rtc); > + if (pdata->irq > 0) { > + /* Read Ctrl B and clear PIE/AIE/UIE. */ > + ctrlb = readb(®s->time.ctrlb); > + ctrlb &= ~(RTC_CTRL_B_PIE & RTC_CTRL_B_AIE & RTC_CTRL_B_UIE); > + writeb(ctrlb, ®s->time.ctrlb); > + > + /* Reading Ctrl C auto-clears PF/AF/UF. */ > + ctrlc = readb(®s->time.ctrlc); > + > + /* Read Ctrl 4B and clear RIE/WIE/KSE. */ > + ctrl4b = readb(®s->bank1.ctrl4b); > + ctrl4b &= ~(RTC_CTRL_4B_RIE & RTC_CTRL_4B_WIE & RTC_CTRL_4B_KSE); > + writeb(ctrl4b, ®s->bank1.ctrl4b); > + > + /* Manually clear RF/WF/KF in Ctrl 4A. */ > + ctrl4a = readb(®s->bank1.ctrl4a); > + ctrl4a &= ~(RTC_CTRL_4A_RF & RTC_CTRL_4A_WF & RTC_CTRL_4A_KF); > + writeb(ctrl4a, ®s->bank1.ctrl4a); > + > + /* Free the IRQ. */ > + free_irq(pdata->irq, pdev); Since the irq handler references the rtc device it should be freed before the rtc device. > + } > + > + iounmap(pdata->regs); > + > + release_mem_region(pdata->baseaddr, pdata->size); > + kfree(pdata); > + > + return 0; > +} > + > +static struct platform_driver ds1685_rtc_driver = { > + .driver = { > + .name = "rtc-ds1685", > + .owner = THIS_MODULE, > + }, > + .probe = ds1685_rtc_probe, > + .remove = __devexit_p(ds1685_rtc_remove), > +}; > + > +static __init > +int ds1685_init(void) > +{ > + return platform_driver_register(&ds1685_rtc_driver); > +} > + > +static __exit > +void ds1685_exit(void) > +{ > + platform_driver_unregister(&ds1685_rtc_driver); > +} > + > + > +module_init(ds1685_init); > +module_exit(ds1685_exit); > + > +MODULE_AUTHOR("Matthias Fuchs , " > + "Joshua Kinard "); > +MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687 RTC driver"); > +MODULE_LICENSE("GPL"); > +MODULE_VERSION(DRV_VERSION); > +MODULE_ALIAS("platform:rtc-ds1685"); > diff -Naurp linux-2.6.37.orig/include/linux/rtc/ds1685.h > linux-2.6.37.rtc-ds1685/include/linux/rtc/ds1685.h > --- linux-2.6.37.orig/include/linux/rtc/ds1685.h 1969-12-31 > 19:00:00.000000000 -0500 > +++ linux-2.6.37.rtc-ds1685/include/linux/rtc/ds1685.h 2011-02-15 > 04:28:04.582076001 -0500 > @@ -0,0 +1,401 @@ There doesn't seem to be any code inside this file which is used outside of ds1685.c so it might be a good idea to merge the two files, or at least move this file to drivers/rtc/ > +/* > + * include/linux/rtc/ds1685.h > + * > + * Definitions for the control registers and platform data of the > + * DS1685/DS1687 RTC chip driver. > + * > + * Copyright (C) 2009 Matthias Fuchs > + * Copyright (C) 2010 Joshua Kinard > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#ifndef _LINUX_RTC_DS1685_H_ > +#define _LINUX_RTC_DS1685_H_ > + > +/* > + * Found in the original RTC driver for SGI IP30 (Octane) systems, it > is used > + * in the ds1685_begin_access macro while loop to avoid RTC access > lockouts. > + */ > +#define DS1685_MAGIC 137 > + > + > +/* > + * NVRAM. > + * - 50 bytes of NVRAM are available just past the clock registers. > + * - 64 additional bytes are available in Bank0. > + * - 128 additional bytes are available in Bank1. > + */ > +#define NVRAM_SZ_TIME 50 > +#define NVRAM_SZ_BANK0 64 > +#define NVRAM_SZ_BANK1 128 > +#define NVRAM_TOTAL_SZ_BANK0 (NVRAM_SZ_TIME + NVRAM_SZ_BANK0) > +#define NVRAM_TOTAL_SZ (NVRAM_TOTAL_SZ_BANK0 + NVRAM_SZ_BANK1) > + > + > +/* > + * Some of the register names below are not used in the actual code, but > + * are made available per the DS1685/DS1687 documentation for possible > + * future use if the need arises. > + */ > +#define RTC_SECONDS 0x00 > +#define RTC_SECONDS_ALARM 0x01 > +#define RTC_MINUTES 0x02 > +#define RTC_MINUTES_ALARM 0x03 > +#define RTC_HOURS 0x04 > +#define RTC_HOURS_ALARM 0x05 > +#define RTC_DAY 0x06 > +#define RTC_DATE 0x07 > +#define RTC_MONTH 0x08 > +#define RTC_YEAR 0x09 > + > +#define RTC_CTRL_A 0x0a /* Control Register A */ > +#define RTC_CTRL_B 0x0b /* Control Register B */ > +#define RTC_CTRL_C 0x0c /* Control Register C */ > +#define RTC_CTRL_D 0x0d /* Control Register D */ > +#define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */ > +#define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */ > +#define RTC_NVRAM_START_B0 0x0e > +#define RTC_NVRAM_BANK1_BASE 0x3f00 > + > + > +/* > + * Values of the RTC bits. > + */ > +#define BIT_0 0x01 > +#define BIT_1 0x02 > +#define BIT_2 0x04 > +#define BIT_3 0x08 > +#define BIT_4 0x10 > +#define BIT_5 0x20 > +#define BIT_6 0x40 > +#define BIT_7 0x80 Just use BIT(x) instead of adding these defines > + > +/* > + * Bit names in Control Register A. > + */ > +#define RTC_CTRL_A_RS0 BIT_0 /* Rate-Selection Bit 0 */ > +#define RTC_CTRL_A_RS1 BIT_1 /* Rate-Selection Bit 1 */ > +#define RTC_CTRL_A_RS2 BIT_2 /* Rate-Selection Bit 2 */ > +#define RTC_CTRL_A_RS3 BIT_3 /* Rate-Selection Bit 3 */ > +#define RTC_CTRL_A_DV0 BIT_4 /* Bank Select */ > +#define RTC_CTRL_A_DV1 BIT_5 /* Oscillator Enable */ > +#define RTC_CTRL_A_DV2 BIT_6 /* Countdown Chain */ > +#define RTC_CTRL_A_UIP BIT_7 /* Update In Progress */ > +#define RTC_CTRL_A_RS_MASK (RTC_CTRL_A_RS0 + RTC_CTRL_A_RS1 + \ > + RTC_CTRL_A_RS2 + RTC_CTRL_A_RS3) > + > +/* > + * Bit names in Control Register B. > + */ > +#define RTC_CTRL_B_DSE BIT_0 /* Daylight Savings Enable */ > +#define RTC_CTRL_B_2412 BIT_1 /* 12-Hr/24-Hr Mode */ > +#define RTC_CTRL_B_DM BIT_2 /* Data Mode */ > +#define RTC_CTRL_B_SQWE BIT_3 /* Square-Wave Enable */ > +#define RTC_CTRL_B_UIE BIT_4 /* Update-Ended Interrupt-Enable */ > +#define RTC_CTRL_B_AIE BIT_5 /* Alarm-Interrupt Enable */ > +#define RTC_CTRL_B_PIE BIT_6 /* Periodic-Interrupt Enable */ > +#define RTC_CTRL_B_SET BIT_7 /* SET Bit */ > + > + > +/* > + * Bit names in Control Register C. > + * > + * BIT_0, BIT_1, BIT_2, & BIT_3 are unused, always return 0, and cannot be > + * written to. > + */ > +#define RTC_CTRL_C_UF BIT_4 /* Update-Ended Interrupt Flag */ > +#define RTC_CTRL_C_AF BIT_5 /* Alarm-Interrupt Flag */ > +#define RTC_CTRL_C_PF BIT_6 /* Periodic-Interrupt Flag */ > +#define RTC_CTRL_C_IRQF BIT_7 /* Interrupt-Request Flag */ > + > + > +/* > + * Bit names in Control Register D. > + * > + * BIT_0 through BIT_6 are unused, always return 0, and cannot be > written to. > + */ > +#define RTC_CTRL_D_VRT BIT_7 /* Valid RAM and Time */ > + > + > +/* > + * Bit names in Extended Control Register 4A. > + * > + * BIT_4 and BIT_5 are reserved for future use. They can be read from and > + * written to, but have no effect on the RTC's operation. > + */ > +#define RTC_CTRL_4A_KF BIT_0 /* Kickstart Flag */ > +#define RTC_CTRL_4A_WF BIT_1 /* Wake-Up Alarm Flag */ > +#define RTC_CTRL_4A_RF BIT_2 /* RAM Clear Flag */ > +#define RTC_CTRL_4A_PAB BIT_3 /* Power-Active Bar Control */ > +#define RTC_CTRL_4A_INCR BIT_6 /* Increment-in-Progress Status */ > +#define RTC_CTRL_4A_VRT2 BIT_7 /* Auxillary Battery Status */ > + > + > +/* > + * Bit names in Extended Control Register 4B. > + */ > +#define RTC_CTRL_4B_KSE BIT_0 /* Kickstart Interrupt-Enable */ > +#define RTC_CTRL_4B_WIE BIT_1 /* Wake-Up Alarm-Interrupt > Enable */ > +#define RTC_CTRL_4B_RIE BIT_2 /* RAM Clear-Interrupt Enable */ > +#define RTC_CTRL_4B_PRS BIT_3 /* PAB Reset-Select */ > +#define RTC_CTRL_4B_RCE BIT_4 /* RAM Clear-Enable */ > +#define RTC_CTRL_4B_CS BIT_5 /* Crystal Select */ > +#define RTC_CTRL_4B_E32K BIT_6 /* Enable 32.768Hz Output on SQW > Pin */ > +#define RTC_CTRL_4B_ABE BIT_7 /* Auxillary Battery Enable */ > + > + > +/* > + * Register names in Bank 1. > + * > + * The DV0 bit in Control Register A must be set to 1 for these registers > + * to become available, including Extended Control Registers 4A & 4B. > + */ > +#define RTC_BANK1_MODEL 0x40 /* Model Number */ > +#define RTC_BANK1_SERIAL_BYTE_1 0x41 /* 1st Byte of Serial Number */ > +#define RTC_BANK1_SERIAL_BYTE_2 0x42 /* 2nd Byte of Serial Number */ > +#define RTC_BANK1_SERIAL_BYTE_3 0x43 /* 3rd Byte of Serial Number */ > +#define RTC_BANK1_SERIAL_BYTE_4 0x44 /* 4th Byte of Serial Number */ > +#define RTC_BANK1_SERIAL_BYTE_5 0x45 /* 5th Byte of Serial Number */ > +#define RTC_BANK1_SERIAL_BYTE_6 0x46 /* 6th Byte of Serial Number */ > +#define RTC_BANK1_SERIAL_CRC 0x47 /* Serial CRC Byte */ > +#define RTC_BANK1_CENTURY 0x48 /* Century Counter */ > +#define RTC_BANK1_DATE_ALARM 0x49 /* Date Alarm */ > +#define RTC_BANK1_RAM_ADDR 0x50 /* RAM Address */ > +#define RTC_BANK1_RAM_DATA_PORT 0x53 /* RAM Data Port */ > + > + > +#ifdef CONFIG_PROC_FS > +/* > + * Periodic Interrupt Rates. A static character array is used for > displaying > + * these values in /proc when procfs is enabled. > + */ > +static const char *pirq_rate[16] = { > + "none", "3.90625ms", "7.8125ms", "122.070µs", "244.141µs", > + "488.281µs", "976.5625µs", "1.953125ms", "3.90625ms", "7.8125ms", > + "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" > +}; > + > +/* > + * Square-Wave Output Frequencies. A static character array is used for > + * displaying these values in /proc when procfs is enabled. > + */ > +static const char *sqw_freq[16] = { > + "none", "256Hz", "128Hz", "8.192kHz", "4.096kHz", "2.048kHz", > + "1.024kHz", "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", > + "8Hz", "4Hz", "2Hz" > +}; > +#endif /* CONFIG_PROC_FS */ > + > + > +#define DS1685_REG(r) volatile unsigned char r; > + I think you should really use readb(pdata->regs + REG) instead of the following structs. Maybe add a helper function in the form of: static uint8_t ds1685_read(struct ds1685_priv *ds1685, unsigned int reg) { return readb(pdata->regs + REG); } That should also help with the different paddings introduced in patch 2. > + > +/* > + * This structure defines the standard DS1286-style time registers > + * that exist in both bank0 and bank1. > + */ > +struct ds1685_time_regs { > + DS1685_REG(sec); /* Seconds */ > + DS1685_REG(sec_alrm); /* Seconds Alarm */ > + DS1685_REG(min); /* Minutes */ > + DS1685_REG(min_alrm); /* Minutes Alarm */ > + DS1685_REG(hour); /* Hours */ > + DS1685_REG(hour_alrm); /* Hours Alarm */ > + DS1685_REG(wday); /* Day of the Week */ > + DS1685_REG(mday); /* Day of the Month */ > + DS1685_REG(month); /* Current Month */ > + DS1685_REG(year); /* Current Year */ > + DS1685_REG(ctrla); /* Control Register A */ > + DS1685_REG(ctrlb); /* Control Register B */ > + DS1685_REG(ctrlc); /* Control Register C */ > + DS1685_REG(ctrld); /* Control Register D */ > + volatile unsigned char nvram1[NVRAM_SZ_TIME]; > +}; > + > + > +/* > + * Bank0-specific registers. This is usually NVRAM. > + */ > +struct ds1685_bank0_regs { > + volatile unsigned char nvram2[NVRAM_SZ_BANK0]; > +}; > + > + > +/* > + * Bank1-specific registers. These access extended capabilities present > + * in the DS1685. The DS17285/DS17287 has minor differences, including an > + * RTC write counter, and two extended NVRAM address registers, for MSB > + * or LSB forms of the address. > + */ > +struct ds1685_bank1_regs { > + DS1685_REG(model); /* Model Number */ > + DS1685_REG(ssn1); /* 1st Byte of Serial Number */ > + DS1685_REG(ssn2); /* 2nd Byte of Serial Number */ > + DS1685_REG(ssn3); /* 3rd Byte of Serial Number */ > + DS1685_REG(ssn4); /* 4th Byte of Serial Number */ > + DS1685_REG(ssn5); /* 5th Byte of Serial Number */ > + DS1685_REG(ssn6); /* 6th Byte of Serial Number */ > + DS1685_REG(crc); /* Serial # CRC Byte */ > + DS1685_REG(century); /* Current Century */ > + DS1685_REG(mday_alrm); /* Day of the Month Alarm */ > + DS1685_REG(ctrl4a); /* Ext. Control Register 4A */ > + DS1685_REG(ctrl4b); /* Ext. Control Register 4B */ > + DS1685_REG(rsvrd1); /* Reserved; provides SMI */ > + DS1685_REG(rsvrd2); /* Recovery Stack. Holds last */ > + DS1685_REG(rtc_addr2); /* four RTC addresses for the */ > + DS1685_REG(rtc_addr3); /* BIOS to recover from an SMI. */ > + DS1685_REG(ext_nvram_addr); /* Ext. NVRAM Addr; DS1685/7 */ > + DS1685_REG(rsvrd3); /* Reserved */ > + DS1685_REG(rsvrd4); /* Reserved */ > + DS1685_REG(ext_nvram_dport); /* Ext. NVRAM Data Port */ > +}; > + > + > +/* > + * The actual register struct. Uses a union to combine bank0 and bank1, > + * since both use the same address space, but are accessed depending on > the > + * state of the DV0 bit in Control Register A. > + */ > +struct ds1685_rtc_regs { > + struct ds1685_time_regs time; > + union { > + struct ds1685_bank0_regs bank0; > + struct ds1685_bank1_regs bank1; > + }; > +}; > + > + > +/* > + * DS1685/1687 data structure. > + */ > +struct ds1685_priv { > + struct rtc_device *rtc; /* RTC device pointer */ > + struct ds1685_rtc_regs __iomem *regs; /* RTC Registers */ > + resource_size_t baseaddr; /* Resource base address */ > + size_t size; /* Resource size */ > + spinlock_t lock; /* Spinlock struct */ > + int irq; /* RTC IRQ # */ > + unsigned int p_intr; /* Periodic IRQ status */ > + unsigned int a_intr; /* Alarm IRQ status */ > + unsigned int u_intr; /* Update IRQ status */ > +#if 0 /* Not used just yet; See comments in rtc-ds1685.c */ > + unsigned int r_intr; /* RAM-Clear IRQ status */ > + unsigned int w_intr; /* Watchdog IRQ status */ > + unsigned int k_intr; /* Kickstart IRQ status */ > +#endif > +}; > + > + All these macros that follow should really be functions. > +/* > + * These two macros set and unset the SET bit in Control Register B. The > + * SET bit inhibits update transfers and allows a safe read/write of the > + * time and calendar bits. > + */ > +#define ds1685_rtc_set_set_bit \ > + data = readb(®s->time.ctrlb) | RTC_CTRL_B_SET; \ > + writeb(data, ®s->time.ctrlb) > + > +#define ds1685_rtc_clear_set_bit \ > + data = readb(®s->time.ctrlb) & ~(RTC_CTRL_B_SET); \ > + writeb(data, ®s->time.ctrlb) > + > + > +/* > + * These two macros switch between bank0 and bank1. Bank0 provides access > + * to the standard RTC capabilities originally defined with the DS1286 > RTC. > + * Bank1 provides access to extended capabilities, including extended > + * control registers, silicon serial number, century counter, aux battery > + * capabilities, wake-up/kick-start features and additional amounts of > nvram. > + */ > +#define ds1685_rtc_switch_to_bank0 \ > + data = readb(®s->time.ctrla) & ~(RTC_CTRL_A_DV0); \ > + writeb(data, ®s->time.ctrla) > + > +#define ds1685_rtc_switch_to_bank1 \ > + data = readb(®s->time.ctrla) | RTC_CTRL_A_DV0; \ > + writeb(data, ®s->time.ctrla) > + > + > +/* > + * This begins the RTC data access, such as reading/writing clock/alarm > + * registers. It performs several steps in a common block of code that is > + * used quite frequently: > + * > + * - Sets a spinlock on the IRQ. > + * - Sets the SET bit in Control Register B. > + * - Reads Control Register A. > + * - Checks the UIP bit in Control Register A. If UIP is active, > + * a delay is forced and a check is run to see if RTC access was > + * locked out. The loop runs until UIP is not set. > + * - A switch to bank1 occurs. This allows access to all the relevant > + * time data, since the time registers are available regardless of > + * which bank is currently selected. > + */ > +#define ds1685_rtc_begin_data_access \ > + spin_lock_irqsave(&pdata->lock, flags); \ > + ds1685_rtc_set_set_bit; \ > + data = readb(®s->time.ctrla); \ > + while (data & RTC_CTRL_A_UIP) { \ > + udelay(10); \ > + if (jiffies > start + DS1685_MAGIC) { \ > + dev_err(dev, "Access lockout!\n"); \ > + return 1; \ > + } \ > + data = readb(®s->time.ctrla); \ > + } \ > + ds1685_rtc_switch_to_bank1 > + > +/* > + * This ends the RTC data access: > + * - It switches back to bank0. > + * - It clears the SET bit in Control Register B. > + * - It unsets the spinlock on the IRQ. > + */ > +#define ds1685_rtc_end_data_access \ > + ds1685_rtc_switch_to_bank0; \ > + ds1685_rtc_clear_set_bit; \ > + spin_unlock_irqrestore(&pdata->lock, flags) > + > + > +/* > + * This begins the RTC access to the control registers only. Such > + * accesses need far less handling, just a spinlock and a switch to > + * bank1. > + */ > +#define ds1685_rtc_begin_ctrl_access \ > + spin_lock_irqsave(&pdata->lock, flags); \ > + ds1685_rtc_switch_to_bank1 > + > +/* > + * This ends the RTC ctrl access: > + * - It switches back to bank0. > + * - It unsets the spinlock on the IRQ. > + */ > +#define ds1685_rtc_end_ctrl_access \ > + ds1685_rtc_switch_to_bank0; \ > + spin_unlock_irqrestore(&pdata->lock, flags) > + > + > +/* > + * This fetches the Silicon Serial Number, a unique ID specific to every > + * DS1685/1687. > + * > + * This number starts at 0x40, and is 8-bytes long, ending at 0x47. > + * The first byte is the model #, the next six bytes are the serial > + * number digits, and the final byte is a CRC check byte. Together, > + * they form the SSN of the RTC. > + */ > +#define ds1685_rtc_get_ssn \ > + ssn[0] = readb(®s->bank1.model); \ > + ssn[1] = readb(®s->bank1.ssn1); \ > + ssn[2] = readb(®s->bank1.ssn2); \ > + ssn[3] = readb(®s->bank1.ssn3); \ > + ssn[4] = readb(®s->bank1.ssn4); \ > + ssn[5] = readb(®s->bank1.ssn5); \ > + ssn[6] = readb(®s->bank1.ssn6); \ > + ssn[7] = readb(®s->bank1.crc) > + > +#endif /* _LINUX_RTC_DS1685_H_ */ > > From kumba@gentoo.org Thu Feb 17 06:45:49 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 06:45:52 +0100 (CET) Received: from qmta04.emeryville.ca.mail.comcast.net ([76.96.30.40]:33642 "EHLO qmta04.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491044Ab1BQFpt (ORCPT ); Thu, 17 Feb 2011 06:45:49 +0100 Received: from omta02.emeryville.ca.mail.comcast.net ([76.96.30.19]) by qmta04.emeryville.ca.mail.comcast.net with comcast id 8tlZ1g0030QkzPwA4tlh4t; Thu, 17 Feb 2011 05:45:41 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta02.emeryville.ca.mail.comcast.net with comcast id 8tld1g00P3XYSBH8NtlfcU; Thu, 17 Feb 2011 05:45:41 +0000 Message-ID: <4D5CB5FB.20305@gentoo.org> Date: Thu, 17 Feb 2011 00:45:31 -0500 From: Kumba User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Lars-Peter Clausen CC: Linux MIPS List , rtc-linux@googlegroups.com Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC References: <4D5A65E3.1050707@gentoo.org> <4D5C5C66.6060205@metafoo.de> In-Reply-To: <4D5C5C66.6060205@metafoo.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29195 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips On 02/16/2011 18:23, Lars-Peter Clausen wrote: > I think you should really use readb(pdata->regs + REG) instead of the following > structs. Maybe add a helper function in the form of: > static uint8_t ds1685_read(struct ds1685_priv *ds1685, unsigned int reg) { > return readb(pdata->regs + REG); > } > > That should also help with the different paddings introduced in patch 2. Lots of good feedback, thanks! Ralf already suggested using offsets instead of a struct. I'm tinkering now with getting this to work, as I have to have this done before I can address many of your other points. I have determined the following formula specific to the SGI O2 to read the RTC registers: readb(pdata->regs + RTC_ * 0x100); is equivalent to readb(pdata->regs.time.); I'll assume writeb() changes are the same. The question is, how do I wire in the 0x100 padding value in such a way that I keep the IP32-specific bits out of generic code? Ralf mentioned using some field in platform_data, but I haven't quite learned the platform stuff (this is my first real attempt at a kernle driver). Also, one thing I can quickly address, I put the ds1685.h file under include/linux/rtc because I saw that folder as already existing. I figured that's where rtc header files went. Right now, nothing outside of the driver uses it, but SGI O2 will need to eventually, as it uses the RTC to trigger a system poweroff by accessing a few of the extended control registers. It currently uses similarly-duplicated #defines in a local header file, but I figured, if I can get this driver fully working, and other platforms could theoretically use the same trick, would not include/linux/rtc be the best place for the header? If there's a better place, please let me know! Thanks, -- Joshua Kinard Gentoo/MIPS kumba@gentoo.org "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." --Emperor Turhan, Centauri Republic From manuel.lauss@googlemail.com Thu Feb 17 08:31:51 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 08:31:54 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:52699 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491101Ab1BQHbu convert rfc822-to-8bit (ORCPT ); Thu, 17 Feb 2011 08:31:50 +0100 Received: by wyf22 with SMTP id 22so2068881wyf.36 for ; Wed, 16 Feb 2011 23:31:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=H+OJCV+lx/859o0f9JiI/cJK5Ns6sSsh5n7l5s7+8fg=; b=mTGK8tJ/b4gsoY2ugeCqo0RsznqYTCldoHDBZf1G2glA4LiwR70h5q1mcqDBccmSuC O3MVul/HkEjEf2ui2etyiqmpw1l4GtLiacqM4brUDiJTwrN4JT4wrDHcoSr5Dd5BWF0K +Od/+M4lRfqJZ/Clu/jAyaqs58sS/ANnUMhXE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Obs/IDRIQ2jJLiWMoof0JF4lYTUgT+iRPRUh4IeqZB9QbuDdDGP3R9p+lboByFKbHW 5I6NQ2Ril1BtiaVoIXqD1TZAM+Mm3wI6Hckynud6f9AM2OA4uHNNHgIJnU87zsQoXOjI 4YsNFam7eoBegQL/OLckUYi1AzV7y0wSkunMI= MIME-Version: 1.0 Received: by 10.216.17.202 with SMTP id j52mr10884wej.36.1297927905259; Wed, 16 Feb 2011 23:31:45 -0800 (PST) Received: by 10.216.193.195 with HTTP; Wed, 16 Feb 2011 23:31:45 -0800 (PST) In-Reply-To: <4D5CB5FB.20305@gentoo.org> References: <4D5A65E3.1050707@gentoo.org> <4D5C5C66.6060205@metafoo.de> <4D5CB5FB.20305@gentoo.org> Date: Thu, 17 Feb 2011 08:31:45 +0100 Message-ID: Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC From: Manuel Lauss To: Kumba Cc: Lars-Peter Clausen , Linux MIPS List , rtc-linux@googlegroups.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29196 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips > I have determined the following formula specific to the SGI O2 to read the > RTC registers: > > readb(pdata->regs + RTC_ * 0x100); > > is equivalent to > > readb(pdata->regs.time.); > > I'll assume writeb() changes are the same.  The question is, how do I wire > in the 0x100 padding value in such a way that I keep the IP32-specific bits > out of generic code?  Ralf mentioned using some field in platform_data, but > I haven't quite learned the platform stuff (this is my first real attempt at > a kernle driver). Have a look at i2c-ocores.c: Basically you use platform_data to specify register spacing on the bus. Manuel From antonynpavlov@gmail.com Thu Feb 17 09:17:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 09:17:50 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:38808 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491101Ab1BQIRr (ORCPT ); Thu, 17 Feb 2011 09:17:47 +0100 Received: by bwz5 with SMTP id 5so2303258bwz.36 for ; Thu, 17 Feb 2011 00:17:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=JDHCV/N5Y74wXxAkogU9yT1HdzOAnJYvgmg+/Lftrts=; b=kKjokFwWh4rpf3lmruS9YKtU6H1fbOeB++iaG6AJo80MqMhxU9Op9triuS1YuUCyfQ 5maX/Ic6awSF5p9Zjeh+TYLfQnI3gfcgcgS4Y6pRiRNJx3CMRgyacvJkZWawegcJ7DdB YKK8DQ5Pa2VFfMtJVCie3UMnqKRCwFROVfmIA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=pH2pUdL1SbQ0eWwz7EvVTRO7pYe6irvvg2vZo1G+HnYo+vWNOlR/Jk2C1jEmvO2qJH z12xp9y1/N6TjdP3tGqMz4rhF2cIOnoraFUDKDmg8Cr9BPPSLIJBm3hvdr7L9bQMIezN sdngxJZ9hokOaVZCGKcR8g4D7LXP5FjZRBA/o= Received: by 10.204.70.134 with SMTP id d6mr1378559bkj.21.1297930661265; Thu, 17 Feb 2011 00:17:41 -0800 (PST) Received: from localhost.localdomain (t35.niisi.ras.ru [193.232.173.35]) by mx.google.com with ESMTPS id q18sm447859bka.15.2011.02.17.00.17.40 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 17 Feb 2011 00:17:40 -0800 (PST) From: Antony Pavlov To: Ralf Baechle Cc: linux-mips@linux-mips.org, Antony Pavlov , Antony Pavlov Subject: [PATCH] MIPS: Loongson: Kconfig: add MACH_LOONGSON dependency Date: Thu, 17 Feb 2011 11:26:06 +0300 Message-Id: <1297931166-23957-1-git-send-email-antonynpavlov@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29197 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: antonynpavlov@gmail.com Precedence: bulk X-list: linux-mips From: Antony Pavlov The options LOONGSON_SUSPEND, LOONGSON_UART_BASE et al. don't depend on MACH_LOONGSON option. So my configuration file (.config) for MIPS Malta board contains # CONFIG_MACH_LOONGSON is not set CONFIG_MIPS_MALTA=y ... CONFIG_LOONGSON_UART_BASE=y Signed-off-by: Antony Pavlov --- arch/mips/loongson/Kconfig | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 6e1b77f..4f2cf08 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -61,6 +61,7 @@ endchoice config CS5536 bool + depends on MACH_LOONGSON config CS5536_MFGPT bool "CS5536 MFGPT Timer" @@ -77,13 +78,14 @@ config CS5536_MFGPT config LOONGSON_SUSPEND bool default y - depends on CPU_SUPPORTS_CPUFREQ && SUSPEND + depends on MACH_LOONGSON && CPU_SUPPORTS_CPUFREQ && SUSPEND config LOONGSON_UART_BASE bool default y - depends on EARLY_PRINTK || SERIAL_8250 + depends on MACH_LOONGSON && (EARLY_PRINTK || SERIAL_8250) config LOONGSON_MC146818 bool default n + depends on MACH_LOONGSON -- 1.7.1 From kumba@gentoo.org Thu Feb 17 09:18:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 09:18:12 +0100 (CET) Received: from qmta12.emeryville.ca.mail.comcast.net ([76.96.27.227]:33269 "EHLO qmta12.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491103Ab1BQISD (ORCPT ); Thu, 17 Feb 2011 09:18:03 +0100 Received: from omta13.emeryville.ca.mail.comcast.net ([76.96.30.52]) by qmta12.emeryville.ca.mail.comcast.net with comcast id 8wHi1g00517UAYkACwHv8l; Thu, 17 Feb 2011 08:17:55 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta13.emeryville.ca.mail.comcast.net with comcast id 8wHq1g0053XYSBH8ZwHsFR; Thu, 17 Feb 2011 08:17:54 +0000 Message-ID: <4D5CD99E.6030300@gentoo.org> Date: Thu, 17 Feb 2011 03:17:34 -0500 From: Kumba User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Manuel Lauss CC: Lars-Peter Clausen , Linux MIPS List , rtc-linux@googlegroups.com Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC References: <4D5A65E3.1050707@gentoo.org> <4D5C5C66.6060205@metafoo.de> <4D5CB5FB.20305@gentoo.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29198 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips On 02/17/2011 02:31, Manuel Lauss wrote: > > Have a look at i2c-ocores.c: Basically you use platform_data to specify > register spacing on the bus. > > Manuel I think I get most of it here. i2c-ocores.c defines `struct ocores_i2c`, which has regstep in it. I assume the equivalent to this in the RTC driver is going to be ds1685_priv. But in i2c_ocores.h, `struct ocores_i2c_platform_data` is defined, which also carries a regstep. In i2c-ocores.c, this struct becomes *pdata while ocores_i2c becomes *i2c, and *i2c is used to access the registers. I don't think I have an equivalent to either of these two with the way the driver was originally written and how I modified it. The ds1685_priv kinda does both right now. I assume platform_data is not really defined...I have to implement one specific to this RTC driver, giving it specific variables that need to be customizable at the platform level, and then set those in the machine-specific areas, i.e., somewhere in IP32's platform file. Sound correct? -- Joshua Kinard Gentoo/MIPS kumba@gentoo.org "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." --Emperor Turhan, Centauri Republic From manuel.lauss@googlemail.com Thu Feb 17 09:39:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 09:39:46 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:65150 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491101Ab1BQIjn convert rfc822-to-8bit (ORCPT ); Thu, 17 Feb 2011 09:39:43 +0100 Received: by wwi17 with SMTP id 17so2161611wwi.24 for ; Thu, 17 Feb 2011 00:39:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=uBGbesRT3AmxjIYyfe4f/CxTtpcN2dL5g8qt3RbudQM=; b=AYbTuwuFgtVXkDvV3ygAv2N9B/+aNrg5+nKklt0oVpK4JfhAicXEBbF8yekIy13JEy bcEr38uN/SRREP5ba8m/tsMpigba2VJlrMnne06AwwqIl5dgeDoJdNxTSuzoIOwrLDt3 7i8G10lhkLSC2+n/EjhYgcI50uF5+HR+AGx3s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=UfNthOvxuwZt0J2UeBeXeucz2Q4YRNrM56IMkdXCNF68XoxrQruEWlUT/h81FYlHB4 p0ALoY49dRWgTUMOBoyKIZ+fr4Vttn1cCLv4Bo2VAg9MGiojrVRNQMqP3qrQ4I7TgMIJ 6z6qY7fDM+Ku5on16SCzaVN/GRQTYKGbb2eK0= MIME-Version: 1.0 Received: by 10.216.17.202 with SMTP id j52mr67452wej.36.1297931977850; Thu, 17 Feb 2011 00:39:37 -0800 (PST) Received: by 10.216.193.195 with HTTP; Thu, 17 Feb 2011 00:39:37 -0800 (PST) In-Reply-To: <4D5CD99E.6030300@gentoo.org> References: <4D5A65E3.1050707@gentoo.org> <4D5C5C66.6060205@metafoo.de> <4D5CB5FB.20305@gentoo.org> <4D5CD99E.6030300@gentoo.org> Date: Thu, 17 Feb 2011 09:39:37 +0100 Message-ID: Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC From: Manuel Lauss To: Kumba Cc: Lars-Peter Clausen , Linux MIPS List , rtc-linux@googlegroups.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29199 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Thu, Feb 17, 2011 at 9:17 AM, Kumba wrote: > On 02/17/2011 02:31, Manuel Lauss wrote: >> >> Have a look at i2c-ocores.c:    Basically you use platform_data to specify >> register spacing on the bus. >> >> Manuel > > I think I get most of it here.  i2c-ocores.c defines `struct ocores_i2c`, > which has regstep in it.  I assume the equivalent to this in the RTC driver > is going to be ds1685_priv.  But in i2c_ocores.h, `struct > ocores_i2c_platform_data` is defined, which also carries a regstep.  In > i2c-ocores.c, this struct becomes *pdata while ocores_i2c becomes *i2c, and > *i2c is used to access the registers. > > I don't think I have an equivalent to either of these two with the way the > driver was originally written and how I modified it.  The ds1685_priv kinda > does both right now.  I assume platform_data is not really defined...I have > to implement one specific to this RTC driver, giving it specific variables > that need to be customizable at the platform level, and then set those in > the machine-specific areas, i.e., somewhere in IP32's platform file. > > Sound correct? Yep. Manuel From antonynpavlov@gmail.com Thu Feb 17 10:47:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 10:47:05 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:61335 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491075Ab1BQJrC (ORCPT ); Thu, 17 Feb 2011 10:47:02 +0100 Received: by wyf22 with SMTP id 22so2162227wyf.36 for ; Thu, 17 Feb 2011 01:46:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=aprv5tCK4uqXmtfan0pY1IWK6XZnYhYGgzNgrH8qLz0=; b=H/qgx/ilhafyeIanG0GfcfcrnIOIP2kRl3fwlQebONm8NyBEab3NWK3KNmtfWCc/2Y eeMZQFcDKvdCkNIY2EpSaehzX8Z99ddwOgx/AK4XRHXtZ0cwqIYD0iCrO4ubMUyymxu3 ku75wSRyFGlltNzrwH+q7Ph8/Ecb9Vm8Ft6wQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=tN+7o0tp/AAUt/GXsr0BcVU2v4pitRwDNtQTy8hy611wakOOuV4ThSK9S02J8tcqUI mgdwl77vw4YYHpS0neioIhsYurAv5qVVNLKgc/xpgfo/hHgp7oncf8sav1kmDq1KBFeM y9YdyZLRzxNUmAQxw87nKLU0YLbdIN9Lc8KdY= MIME-Version: 1.0 Received: by 10.216.166.68 with SMTP id f46mr120089wel.26.1297936016937; Thu, 17 Feb 2011 01:46:56 -0800 (PST) Received: by 10.216.220.199 with HTTP; Thu, 17 Feb 2011 01:46:56 -0800 (PST) In-Reply-To: <1297931166-23957-1-git-send-email-antonynpavlov@gmail.com> References: <1297931166-23957-1-git-send-email-antonynpavlov@gmail.com> Date: Thu, 17 Feb 2011 12:46:56 +0300 Message-ID: Subject: Re: [PATCH] MIPS: Loongson: Kconfig: add MACH_LOONGSON dependency From: =?KOI8-R?B?4c7Uz84g8MHXzM/X?= To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29200 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: antonynpavlov@gmail.com Precedence: bulk X-list: linux-mips Sorry, the mail adresses in fields "From" and "Signed-off-by" are different. I shall resend the patch in a few minutes. 2011/2/17, Antony Pavlov : > From: Antony Pavlov > > The options LOONGSON_SUSPEND, LOONGSON_UART_BASE et al. don't depend > on MACH_LOONGSON option. > So my configuration file (.config) for MIPS Malta board contains > > # CONFIG_MACH_LOONGSON is not set > CONFIG_MIPS_MALTA=y > > ... > > CONFIG_LOONGSON_UART_BASE=y > > Signed-off-by: Antony Pavlov > --- > arch/mips/loongson/Kconfig | 6 ++++-- > 1 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig > index 6e1b77f..4f2cf08 100644 > --- a/arch/mips/loongson/Kconfig > +++ b/arch/mips/loongson/Kconfig > @@ -61,6 +61,7 @@ endchoice > > config CS5536 > bool > + depends on MACH_LOONGSON > > config CS5536_MFGPT > bool "CS5536 MFGPT Timer" > @@ -77,13 +78,14 @@ config CS5536_MFGPT > config LOONGSON_SUSPEND > bool > default y > - depends on CPU_SUPPORTS_CPUFREQ && SUSPEND > + depends on MACH_LOONGSON && CPU_SUPPORTS_CPUFREQ && SUSPEND > > config LOONGSON_UART_BASE > bool > default y > - depends on EARLY_PRINTK || SERIAL_8250 > + depends on MACH_LOONGSON && (EARLY_PRINTK || SERIAL_8250) > > config LOONGSON_MC146818 > bool > default n > + depends on MACH_LOONGSON > -- > 1.7.1 > > From antonynpavlov@gmail.com Thu Feb 17 10:47:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 10:47:30 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:53170 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491075Ab1BQJr0 (ORCPT ); Thu, 17 Feb 2011 10:47:26 +0100 Received: by bwz5 with SMTP id 5so2354778bwz.36 for ; Thu, 17 Feb 2011 01:47:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=D5tgj5KzTIb6DOk3FRF4Cc1IijZ85NxWILc0uwe0LE0=; b=i2tFK7gBOl5XRYgMA/Mnbfz5cGgOkKetdQ9xlWzO0049vv9Xx/2XOM5M/RUfHaYahd /srh4PQIUXg3Er+2eADT0TYXljUeqaqg6npjC2zNuiNJuGaXuzktqw8kbsNt/uT7UbXW I8csqc/m24epYmslhBxo00rAJh6WpuRAtgYTQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=CaaJet74ZidobqEcIWR7udtcbrbz+hLcnTuqDqbQ/9gKrikGgMQpYgyKgx5yPMP3Pe rnlnPziI2pmdv1jZcMLHALii3akwMnJlZDv3iJhez3vClp+KVR7HNUx40Ti/3eHy1wjK MtVImI7n3ReOxXYmOKHInPE9wKQoOCb+dEyPE= Received: by 10.204.101.81 with SMTP id b17mr1447273bko.126.1297936041147; Thu, 17 Feb 2011 01:47:21 -0800 (PST) Received: from localhost.localdomain (t35.niisi.ras.ru [193.232.173.35]) by mx.google.com with ESMTPS id w3sm509983bkt.5.2011.02.17.01.47.19 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 17 Feb 2011 01:47:20 -0800 (PST) From: Antony Pavlov To: Ralf Baechle Cc: linux-mips@linux-mips.org, Antony Pavlov Subject: [PATCH] MIPS: Loongson: Kconfig: add MACH_LOONGSON dependency Date: Thu, 17 Feb 2011 12:55:44 +0300 Message-Id: <1297936544-24369-1-git-send-email-antonynpavlov@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29201 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: antonynpavlov@gmail.com Precedence: bulk X-list: linux-mips The options LOONGSON_SUSPEND, LOONGSON_UART_BASE et al. don't depend on MACH_LOONGSON option. So my configuration file (.config) for MIPS Malta board contains # CONFIG_MACH_LOONGSON is not set CONFIG_MIPS_MALTA=y ... CONFIG_LOONGSON_UART_BASE=y Signed-off-by: Antony Pavlov --- arch/mips/loongson/Kconfig | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 6e1b77f..4f2cf08 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -61,6 +61,7 @@ endchoice config CS5536 bool + depends on MACH_LOONGSON config CS5536_MFGPT bool "CS5536 MFGPT Timer" @@ -77,13 +78,14 @@ config CS5536_MFGPT config LOONGSON_SUSPEND bool default y - depends on CPU_SUPPORTS_CPUFREQ && SUSPEND + depends on MACH_LOONGSON && CPU_SUPPORTS_CPUFREQ && SUSPEND config LOONGSON_UART_BASE bool default y - depends on EARLY_PRINTK || SERIAL_8250 + depends on MACH_LOONGSON && (EARLY_PRINTK || SERIAL_8250) config LOONGSON_MC146818 bool default n + depends on MACH_LOONGSON -- 1.7.1 From kumba@gentoo.org Thu Feb 17 10:57:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 10:57:38 +0100 (CET) Received: from qmta12.westchester.pa.mail.comcast.net ([76.96.59.227]:46355 "EHLO qmta12.westchester.pa.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491075Ab1BQJ5f (ORCPT ); Thu, 17 Feb 2011 10:57:35 +0100 Received: from omta04.westchester.pa.mail.comcast.net ([76.96.62.35]) by qmta12.westchester.pa.mail.comcast.net with comcast id 8xx61g0010ldTLk5CxxTRU; Thu, 17 Feb 2011 09:57:27 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta04.westchester.pa.mail.comcast.net with comcast id 8xxR1g00H3XYSBH3QxxSuK; Thu, 17 Feb 2011 09:57:27 +0000 Message-ID: <4D5CF0EE.7000308@gentoo.org> Date: Thu, 17 Feb 2011 04:57:02 -0500 From: Kumba User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Lars-Peter Clausen CC: Linux MIPS List , rtc-linux@googlegroups.com Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC References: <4D5A65E3.1050707@gentoo.org> <4D5C5C66.6060205@metafoo.de> In-Reply-To: <4D5C5C66.6060205@metafoo.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29202 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips On 02/16/2011 18:23, Lars-Peter Clausen wrote: > Just pass the error up to rtc core. How? I looked at a few other drivers, but they, too, call dev_err() or dev_dbg(). Others don't appear to send any kind of string-based error value anywhere, they just return a -E* value. > There is no need for these checks the core takes care that the values are valid. I've seen a few other RTC drivers implement these checks. It's really hard to tell what drivers are, I guess, "right" and which ones are "wrong" in their approach when you've got already-accepted drivers in the tree doing things that I'm trying to fix in this driver. That said, how is the core running these checks when I quickly turn around and write the values back to the RTC? > return rtc_valid_tm(&arlm->time); Noted -- Probably form when I copied one of the time read functions or such. Alarm support wasn't in the original version of this driver when I found it. > Why has 'enabled' to be a pointer? No idea to be honest. I think I copied it from another driver. I'll re-review it when I get to that point in fixing things. > resource_size(res) instead of res->end - res->start + 1 > and it would be easier to just save the pointer to res instead of saving both > size and start; Noted, I see a few drivers using this syntax, so I'll adapt to it. > If CONFIG_SYSFS is not defined you'll get an compile error. Noted, thanks! > Since the irq handler references the rtc device it should be freed before the > rtc device. Noted, thanks! > There doesn't seem to be any code inside this file which is used outside of > ds1685.c so it might be a good idea to merge the two files, or at least move > this file to drivers/rtc/ I wasn't quite sure where headers typically went. include/linux/rtc already existed, so I thought it was created at some point for holding .h files for RTC drivers. IP32 will need to reference this header down the road anyways. No harm if it has to look into drivers/rtc? > Just use BIT(x) instead of adding these defines Noted, will research. > I think you should really use readb(pdata->regs + REG) instead of the following > structs. Maybe add a helper function in the form of: > static uint8_t ds1685_read(struct ds1685_priv *ds1685, unsigned int reg) { > return readb(pdata->regs + REG); > } > > That should also help with the different paddings introduced in patch 2. Working on this now. Ran into some road blocks with gcc and inlining, but I worked around it. > All these macros that follow should really be functions. Even the large ds1685_begin_data_access macro? I can stick it into a inlined function, but I thought a macro was better. Or am I trying to outfox the compiler by doing so? If I do inline it, I need a fix for passing errors back to the RTC core. I can't use dev_err() because it needs the device struct to work with, and I want to avoid passing too many arguments to an inlinable function. Thoughts? The rest should be easy to convert into inlined functions. Thanks!, -- Joshua Kinard Gentoo/MIPS kumba@gentoo.org "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." --Emperor Turhan, Centauri Republic From dengcheng.zhu@gmail.com Thu Feb 17 11:46:45 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 11:46:49 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:35352 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491075Ab1BQKqp convert rfc822-to-8bit (ORCPT ); Thu, 17 Feb 2011 11:46:45 +0100 Received: by yxd30 with SMTP id 30so1031536yxd.36 for ; Thu, 17 Feb 2011 02:46:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=7+Iv33eDGIqd56LY4t8zINVZHptzazasEyezLvA7ghs=; b=Lcl2fwL32sDNLfczZl/EAaoEXFqtZ1sfdhQ3FH2zomBp+hfdvNyshnuWHnZrDRNtqP PiYv26oqaS3biEnqjysx4fohBYRvts3KxRdHFKlca9TtQguTxEnoEHNwHIh4Eps1R8u+ zGUgzyel/ra2KG460Z59459kYtOSoDC6ann4g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=DjFcniCO7jiAQGiubJbJO6lnUULqPHFwF6oKOML7aA4EYw/d83vpS7UpH2KgDI2OeF 5W60pfOCb/oULy4zwIM+HeM3578dVMVqYVJ2OG/w6m4Lc4pOqOgoPd3t4z24ZrqJjRGZ gmeJX7MEU78dG9CR5He4lKkNOW+dmeltJotjs= MIME-Version: 1.0 Received: by 10.151.149.8 with SMTP id b8mr2161116ybo.300.1297939599158; Thu, 17 Feb 2011 02:46:39 -0800 (PST) Received: by 10.147.41.7 with HTTP; Thu, 17 Feb 2011 02:46:39 -0800 (PST) In-Reply-To: References: <1295650776-28444-1-git-send-email-ddaney@caviumnetworks.com> <1295650776-28444-5-git-send-email-ddaney@caviumnetworks.com> <4D3F68BE.5080803@caviumnetworks.com> <4D41BC6B.8010408@caviumnetworks.com> Date: Thu, 17 Feb 2011 18:46:39 +0800 Message-ID: Subject: Re: [PATCH v2 4/4] MIPS: perf: Add support for 64-bit perf counters. From: Deng-Cheng Zhu To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29203 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Hi, David The reason of the perf-record failure on 32bit platforms is that the 32bit counter read function mipsxx_pmu_read_counter() returns wrong 64bit values. For example, the counter value 0x12345678 will be returned as 0xffffffff12345678. So in mipspmu_event_update(), the delta will be wrong. So here's a possible fix for your reference: --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -184,19 +184,21 @@ static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx) return idx; } +#define U32_MASK 0xffffffff + static u64 mipsxx_pmu_read_counter(unsigned int idx) { idx = mipsxx_pmu_swizzle_perf_idx(idx); switch (idx) { case 0: - return read_c0_perfcntr0(); + return read_c0_perfcntr0() & U32_MASK; case 1: - return read_c0_perfcntr1(); + return read_c0_perfcntr1() & U32_MASK; case 2: - return read_c0_perfcntr2(); + return read_c0_perfcntr2() & U32_MASK; case 3: - return read_c0_perfcntr3(); + return read_c0_perfcntr3() & U32_MASK; default: WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); return 0; In addition, since you removed the use of cpuc->msbs, some code relative to this logic can be removed: @@ -370,7 +372,6 @@ static int mipspmu_event_set_period(struct perf_event *event, u64 left = local64_read(&hwc->period_left); u64 period = hwc->sample_period; int ret = 0; - unsigned long flags; if (unlikely((left + period) & (1ULL << 63))) { /* left underflowed by more than period. */ @@ -393,9 +394,7 @@ static int mipspmu_event_set_period(struct perf_event *event, local64_set(&hwc->prev_count, mipspmu.overflow - left); - local_irq_save(flags); mipspmu.write_counter(idx, mipspmu.overflow - left); - local_irq_restore(flags); perf_event_update_userpage(event); @@ -406,16 +405,12 @@ static void mipspmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, int idx) { - unsigned long flags; u64 prev_raw_count, new_raw_count; u64 delta; again: prev_raw_count = local64_read(&hwc->prev_count); - local_irq_save(flags); - /* Make the counter value be a "real" one. */ new_raw_count = mipspmu.read_counter(idx); - local_irq_restore(flags); if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, new_raw_count) != prev_raw_count) And here's a general comment: You are putting the majority of the implementation in perf_event_mipsxx.c. This will require other CPUs like Loongson2 to replicate quite a lot code in their corresponding files. I personally think the original "skeleton + #include perf_event_$cpu.c" is a better choice. I understand you prefer not using code like "#if defined(CONFIG_CPU_MIPS32)" on the top of perf_event_$cpu.c, but that is what other architectures (X86/ARM etc) are doing. Deng-Cheng 2011/1/28 Deng-Cheng Zhu : > OK. I'll try to use tracing when needed. > > The hardware I was using for the test was Malta-R with 34K bitfile > programed into the FPGA. The CPU frequency is 50MHz. > > > Deng-Cheng > > > 2011/1/28 David Daney : >> On 01/26/2011 10:24 PM, Deng-Cheng Zhu wrote: >>> >>> Using your attached patch, I experimented -c and -F by 'ls /'. The numbers >>> I used are 10, 1000 and 100000 for both -c and -F. >>> >>> The number of samples I got was 24 all the way. That means the event >>> period >>> to sample and the profiling frequency do not affect the results on MIPS32 >>> platform. While working on the old code, the system had the following >>> results: >>> >>> -c 10: The system seems busy dealing with interrupts. And the following >>> log >>>        was printed out: >>>        ================================================ >>>        hda: ide_dma_sff_timer_expiry: DMA status (0x24) >>>        hda: DMA interrupt recovery >>>        hda: lost interrupt >>>        ================================================ >>>        This does need to be fixed later on. >>> -c 1000: ~11085 samples >>> -c 100000: ~48 samples ('perf report' still showed some data.) >>> -F 10: ~118 samples >>> -F 1000: ~352 samples >>> -F 100000: ~379 samples >>> >>> I'll try to take time to look into the patch to see if anything can be >>> changed. >>> >> >> I have found it useful to enable tracing, and then placing trace_printk() in >> mipspmu_event_set_period() to look at the values of: >> >> sample_period, period_left that are being used. >> >> Also you could use a trace_printk() in mipsxx_pmu_write_counter() to check >> the value being written to the register. >> >> What hardware are you using to test this?  I wonder if there is a board with >> a 32-bit CPU that I could get access to. >> >> David Daney >> >> >>> >>> Deng-Cheng >>> >>> >>> 2011/1/26 David Daney: >>>> >>>> On 01/24/2011 07:42 PM, Deng-Cheng Zhu wrote: >>>>> >>>>> Hi, David >>>>> >>>>> >>>>> This version does fix the problem with 'perf stat'. However, when >>>>> working >>>>> with 'perf record', the following happened: >>>>> >>>>> -sh-4.0# perf record -f -e cycles -e instructions -e branches \ >>>>>> >>>>>> -e branch-misses -e r12 find / -name "*sys*">/dev/null >>>>> >>>>> [ perf record: Woken up 1 times to write data ] >>>>> [ perf record: Captured and wrote 0.001 MB perf.data (~53 samples) ] >>>> >>>> >>>> I get the same thing.  What happens if you supply either '-c xxx' or '-f >>>> xxx'? >>>> >>>> I get:octeon:~/linux/tools/perf# ./perf record -e cycles /bin/ls -l / >>>> total 100 >>>> drwxr-xr-x   2 root root  4096 2010-11-12 11:39 bin >>>> [...] >>>> drwxr-xr-x  13 root root  4096 2007-05-25 12:28 var >>>> [ perf record: Woken up 1 times to write data ] >>>> [ perf record: Captured and wrote 0.002 MB perf.data (~82 samples) ] >>>> >>>> Almost no samples as you got. >>>> >>>> But if I do: >>>> >>>> octeon:~/linux/tools/perf# ./perf record -F 100000 -e cycles /bin/ls -l / >>>> total 100 >>>> drwxr-xr-x   2 root root  4096 2010-11-12 11:39 bin >>>> [...] >>>> drwxr-xr-x  13 root root  4096 2007-05-25 12:28 var >>>> [ perf record: Woken up 1 times to write data ] >>>> [ perf record: Captured and wrote 0.404 MB perf.data (~17653 samples) ] >>>> >>>> Look many more samples! >>>> >>>> The question is, what is it supposed to do? >>>> >>>> If you can get a reasonable number of samples out if you supply -c or >>>> -F, then I would argue that it is working and the default settings for >>>> -F are not a good fit for your test case. >>>> >>>> I have slightly changed the patch.  You could try the attached version >>>> instead and tell me the results. >>>> >>>> >>>> David Daney >>>> >>>> >>>> >>> >> >> > From ralf@linux-mips.org Thu Feb 17 12:38:37 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 12:38:40 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:53764 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491104Ab1BQLih (ORCPT ); Thu, 17 Feb 2011 12:38:37 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p1HBcK9J010905; Thu, 17 Feb 2011 12:38:21 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1HBcK3g010902; Thu, 17 Feb 2011 12:38:20 +0100 Date: Thu, 17 Feb 2011 12:38:20 +0100 From: Ralf Baechle To: Antony Pavlov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Loongson: Kconfig: add MACH_LOONGSON dependency Message-ID: <20110217113820.GA6707@linux-mips.org> References: <1297936544-24369-1-git-send-email-antonynpavlov@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1297936544-24369-1-git-send-email-antonynpavlov@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29204 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Feb 17, 2011 at 12:55:44PM +0300, Antony Pavlov wrote: > The options LOONGSON_SUSPEND, LOONGSON_UART_BASE et al. don't depend > on MACH_LOONGSON option. > So my configuration file (.config) for MIPS Malta board contains > > # CONFIG_MACH_LOONGSON is not set > CONFIG_MIPS_MALTA=y > > ... > > CONFIG_LOONGSON_UART_BASE=y Patch is looking good but commit 3a1f2f05e1759dd6a0876a7998408438d59d4a39 [ MIPS: Fix always CONFIG_LOONGSON_UART_BASE=y ] already fixes the issue. Thanks! Ralf From lars@metafoo.de Thu Feb 17 12:44:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 12:44:33 +0100 (CET) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:43421 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491075Ab1BQLoa (ORCPT ); Thu, 17 Feb 2011 12:44:30 +0100 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id B4E022BE; Thu, 17 Feb 2011 12:44:20 +0100 (CET) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id wL3PQOQCSVle; Thu, 17 Feb 2011 12:44:20 +0100 (CET) Received: from [192.168.88.141] (unknown [213.172.107.226]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id CC7622BB; Thu, 17 Feb 2011 12:44:09 +0100 (CET) Message-ID: <4D5D09FF.6010005@metafoo.de> Date: Thu, 17 Feb 2011 12:43:59 +0100 From: Lars-Peter Clausen User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.16) Gecko/20101226 Icedove/3.0.11 MIME-Version: 1.0 To: Kumba CC: Linux MIPS List , rtc-linux@googlegroups.com Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC References: <4D5A65E3.1050707@gentoo.org> <4D5C5C66.6060205@metafoo.de> <4D5CF0EE.7000308@gentoo.org> In-Reply-To: <4D5CF0EE.7000308@gentoo.org> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29205 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips On 02/17/2011 10:57 AM, Kumba wrote: > On 02/16/2011 18:23, Lars-Peter Clausen wrote: > >> Just pass the error up to rtc core. > > How? I looked at a few other drivers, but they, too, call dev_err() or > dev_dbg(). Others don't appear to send any kind of string-based error > value anywhere, they just return a -E* value. That is what I meant. Pass the return value of rtc_valid_tm on, instead of setting the time to 0 and pretend everything went fine. You can still keep the dev_err though, no problem with that. > > >> There is no need for these checks the core takes care that the values >> are valid. > > I've seen a few other RTC drivers implement these checks. It's really > hard to tell what drivers are, I guess, "right" and which ones are > "wrong" in their approach when you've got already-accepted drivers in > the tree doing things that I'm trying to fix in this driver. > > That said, how is the core running these checks when I quickly turn > around and write the values back to the RTC? > What do you mean by 'quickly turning around and writing the values back'? The rtc_time struct passed to the set_time callback is supposed to contain only valid values. > > >> There doesn't seem to be any code inside this file which is used >> outside of >> ds1685.c so it might be a good idea to merge the two files, or at >> least move >> this file to drivers/rtc/ > > I wasn't quite sure where headers typically went. include/linux/rtc > already existed, so I thought it was created at some point for holding > .h files for RTC drivers. IP32 will need to reference this header down > the road anyways. No harm if it has to look into drivers/rtc? Well, if it is going to be shared it should probably remain somewhere in include/, but everything thats not shared should be moved to rtc-ds1685.c like for example ds1685_priv. > > >> Just use BIT(x) instead of adding these defines > > Noted, will research. > > >> I think you should really use readb(pdata->regs + REG) instead of the >> following >> structs. Maybe add a helper function in the form of: >> static uint8_t ds1685_read(struct ds1685_priv *ds1685, unsigned int >> reg) { >> return readb(pdata->regs + REG); >> } >> >> That should also help with the different paddings introduced in patch 2. > > Working on this now. Ran into some road blocks with gcc and inlining, > but I worked around it. > > >> All these macros that follow should really be functions. > > Even the large ds1685_begin_data_access macro? I can stick it into a > inlined function, but I thought a macro was better. Or am I trying to > outfox the compiler by doing so? I don't know what you are trying to do, but the current code is extremely unreadable. You have all those variables declared in your functions which are on first sight not used, because they are only referenced from the macros. Furthermore the invocation of the macro has not the syntax of a function call, although semantically that is what it is. And especially ds1685_rtc_begin_data_access is dangerous, because of the 'return 1', there is no indication when you read the code that a function could magically exit upon invoking that macro. > > If I do inline it, I need a fix for passing errors back to the RTC > core. I can't use dev_err() because it needs the device struct to work > with, and I want to avoid passing too many arguments to an inlinable > function. Why? The compiled code will probably be exactly the same as now. > > Thoughts? The rest should be easy to convert into inlined functions. > > > Thanks!, > From ralf@linux-mips.org Thu Feb 17 14:36:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 14:36:26 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59135 "EHLO duck.linux-mips.net" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491115Ab1BQNgX (ORCPT ); Thu, 17 Feb 2011 14:36:23 +0100 Received: from duck.linux-mips.net (localhost.localdomain [127.0.0.1]) by duck.linux-mips.net (8.14.4/8.14.3) with ESMTP id p1HDa30g021423; Thu, 17 Feb 2011 14:36:03 +0100 Received: (from ralf@localhost) by duck.linux-mips.net (8.14.4/8.14.4/Submit) id p1HDa0aM021419; Thu, 17 Feb 2011 14:36:00 +0100 Date: Thu, 17 Feb 2011 14:36:00 +0100 From: Ralf Baechle To: Deng-Cheng Zhu Cc: David Daney , linux-mips@linux-mips.org, Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo Subject: Re: [PATCH v2 4/4] MIPS: perf: Add support for 64-bit perf counters. Message-ID: <20110217133559.GA12732@linux-mips.org> References: <1295650776-28444-1-git-send-email-ddaney@caviumnetworks.com> <1295650776-28444-5-git-send-email-ddaney@caviumnetworks.com> <4D3F68BE.5080803@caviumnetworks.com> <4D41BC6B.8010408@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29206 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Feb 17, 2011 at 06:46:39PM +0800, Deng-Cheng Zhu wrote: > The reason of the perf-record failure on 32bit platforms is that the 32bit > counter read function mipsxx_pmu_read_counter() returns wrong 64bit values. > For example, the counter value 0x12345678 will be returned as > 0xffffffff12345678. So in mipspmu_event_update(), the delta will be wrong. > So here's a possible fix for your reference: > > --- a/arch/mips/kernel/perf_event_mipsxx.c > +++ b/arch/mips/kernel/perf_event_mipsxx.c > @@ -184,19 +184,21 @@ static unsigned int > mipsxx_pmu_swizzle_perf_idx(unsigned int idx) > return idx; > } > > +#define U32_MASK 0xffffffff > + > static u64 mipsxx_pmu_read_counter(unsigned int idx) > { > idx = mipsxx_pmu_swizzle_perf_idx(idx); > > switch (idx) { > case 0: > - return read_c0_perfcntr0(); > + return read_c0_perfcntr0() & U32_MASK; > case 1: > - return read_c0_perfcntr1(); > + return read_c0_perfcntr1() & U32_MASK; > case 2: > - return read_c0_perfcntr2(); > + return read_c0_perfcntr2() & U32_MASK; > case 3: > - return read_c0_perfcntr3(); > + return read_c0_perfcntr3() & U32_MASK; read_c0_perfctrl0 etc. are defined in mipsregs.h as 32-bit reads returning a signed int. That was ok on 32-bit kernels. To support the optional 64-bit counters the code will have to be changed to something like: static u64 mipsxx_pmu_read_counter(unsigned int idx) { idx = mipsxx_pmu_swizzle_perf_idx(idx); switch (idx) { case 0: if (read_c0_perfctrl0() & M_PERFCTL_WIDE) return read_c0_64_bit_perfcntr0(); else return read_c0_32_bit_perfcntr0(); case 1: if (read_c0_perfctrl1() & M_PERFCTL_WIDE) return read_c0_64_bit_perfcntr1(); else return read_c0_32_bit_perfcntr1(); ... And read_c0_32_bit_perfcntrX need to zero-extend their return value. Ralf From antonynpavlov@gmail.com Thu Feb 17 15:20:04 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 15:20:07 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:38101 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491104Ab1BQOUE (ORCPT ); Thu, 17 Feb 2011 15:20:04 +0100 Received: by fxm19 with SMTP id 19so2569401fxm.36 for ; Thu, 17 Feb 2011 06:19:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=8VbqB4HUwSSNGrjWF7nh4WuLZOEbYgMoAYnui4kVdEE=; b=Sph+3jcV5N8ywFwgVywWwA2uV5d0s8jykH88jXP6jpCqb4MzUFiSfJX7qlyfsPT4Fp +fLdp8rERrUT+dYK/YZcyRBTIl+xKoNxc7XeXbqWRMQUaZqctf5uDP4Hwx1A/fEg0CfP y/2u0JBBtMU4kWXGJKIiGWPe46kXvCpSkHEfY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=Ubn7TXXYk1LdoEdaSvsSanzKm+ZL/nimrjm8IXNC/Pm3I0hMmRcUVCiaSoRkvWRXxa z95xzThK+Xvv9xZ3Pbv5sx6hkKQsMkNzutiSyiHsGuOuxWm0vpSoZYSvuVEPPNdjKni2 7mE80UHl9/aZxRPhkzLTaFKJdWUclbA7ScWVA= Received: by 10.223.83.208 with SMTP id g16mr2462370fal.52.1297952398899; Thu, 17 Feb 2011 06:19:58 -0800 (PST) Received: from localhost.localdomain (t35.niisi.ras.ru [193.232.173.35]) by mx.google.com with ESMTPS id n1sm459498fam.40.2011.02.17.06.19.57 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 17 Feb 2011 06:19:58 -0800 (PST) From: Antony Pavlov To: Ralf Baechle Cc: linux-mips@linux-mips.org, Antony Pavlov Subject: [PATCH] MIPS: Octeon: Kconfig: fix helper dependency Date: Thu, 17 Feb 2011 17:28:26 +0300 Message-Id: <1297952906-1099-1-git-send-email-antonynpavlov@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29207 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: antonynpavlov@gmail.com Precedence: bulk X-list: linux-mips The option CAVIUM_OCTEON_HELPER does not depend on CPU_CAVIUM_OCTEON option. So my .config file for MIPS Malta board contains CONFIG_MIPS_MALTA=y ... # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set ... CONFIG_CAVIUM_OCTEON_HELPER=y Signed-off-by: Antony Pavlov --- arch/mips/cavium-octeon/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index caae228..a6a2f3c 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -97,7 +97,7 @@ config ARCH_SPARSEMEM_ENABLE config CAVIUM_OCTEON_HELPER def_bool y - depends on OCTEON_ETHERNET || PCI + depends on CPU_CAVIUM_OCTEON && (OCTEON_ETHERNET || PCI) config IOMMU_HELPER bool -- 1.7.1 From dengcheng.zhu@gmail.com Thu Feb 17 16:26:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 16:26:39 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:35509 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491104Ab1BQP0e convert rfc822-to-8bit (ORCPT ); Thu, 17 Feb 2011 16:26:34 +0100 Received: by gxk21 with SMTP id 21so1022001gxk.36 for ; Thu, 17 Feb 2011 07:26:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=tAiq91hXcOVrPgC/BCUMoiUCLW5yUJPx5jcN/zFcZOE=; b=QNFjEfqYl6U3OvoGBAcvIBhhbHA1yOpOoul84GRjr6xO4dJvduxy+JrH1FEKFxSqND 0FXdyznzvFsmRRMf4Ps78cud8UrmQ01HibhU6gAG+LvujdlqWAJBdjyRHeNiYJotKxdq sdGG3Kf47kaiZ9V8ynopPfOHlmtDvplDc6vys= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=KaNHRxBcAN19I92MZHngNZAhjv7TuXfEBGZMqtv2sEXMwg/YyRhQuahcIiz1Q0ACYA EbS4xk1B6d5aFE+tRObv52KcjmSQ4JSfmPqzV2LENZIXzIS1wn82jha0z5xoloLyduSG vMitw/vufAaXRVt1ljV0fpqkPUTIcW+kgycWE= MIME-Version: 1.0 Received: by 10.151.158.14 with SMTP id k14mr2449360ybo.357.1297956387884; Thu, 17 Feb 2011 07:26:27 -0800 (PST) Received: by 10.147.124.7 with HTTP; Thu, 17 Feb 2011 07:26:27 -0800 (PST) In-Reply-To: <20110217133559.GA12732@linux-mips.org> References: <1295650776-28444-1-git-send-email-ddaney@caviumnetworks.com> <1295650776-28444-5-git-send-email-ddaney@caviumnetworks.com> <4D3F68BE.5080803@caviumnetworks.com> <4D41BC6B.8010408@caviumnetworks.com> <20110217133559.GA12732@linux-mips.org> Date: Thu, 17 Feb 2011 23:26:27 +0800 Message-ID: Subject: [PATCH v2 4/4] MIPS: perf: Add support for 64-bit perf counters. From: Deng-Cheng Zhu To: Ralf Baechle Cc: David Daney , "linux-mips@linux-mips.org" , Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo Content-Type: text/plain; charset=GB2312 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29208 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Since another function mipsxx_pmu_read_counter_64() has already been defined, the counter wide judgement should not be needed here. And yes, U32_MASK is right here to zero out the upper 32 bits of the 64-bit return value. Deng-Cheng ÔÚ 2011Äê2ÔÂ17ÈÕÐÇÆÚËÄ£¬Ralf Baechle дµÀ£º > On Thu, Feb 17, 2011 at 06:46:39PM +0800, Deng-Cheng Zhu wrote: > >> The reason of the perf-record failure on 32bit platforms is that the 32bit >> counter read function mipsxx_pmu_read_counter() returns wrong 64bit values. >> For example, the counter value 0x12345678 will be returned as >> 0xffffffff12345678. So in mipspmu_event_update(), the delta will be wrong. >> So here's a possible fix for your reference: >> >> --- a/arch/mips/kernel/perf_event_mipsxx.c >> +++ b/arch/mips/kernel/perf_event_mipsxx.c >> @@ -184,19 +184,21 @@ static unsigned int >> mipsxx_pmu_swizzle_perf_idx(unsigned int idx) >> return idx; >> } >> >> +#define U32_MASK 0xffffffff >> + >> static u64 mipsxx_pmu_read_counter(unsigned int idx) >> { >> idx = mipsxx_pmu_swizzle_perf_idx(idx); >> >> switch (idx) { >> case 0: >> - return read_c0_perfcntr0(); >> + return read_c0_perfcntr0() & U32_MASK; >> case 1: >> - return read_c0_perfcntr1(); >> + return read_c0_perfcntr1() & U32_MASK; >> case 2: >> - return read_c0_perfcntr2(); >> + return read_c0_perfcntr2() & U32_MASK; >> case 3: >> - return read_c0_perfcntr3(); >> + return read_c0_perfcntr3() & U32_MASK; > > read_c0_perfctrl0 etc. are defined in mipsregs.h as 32-bit reads returning > a signed int. That was ok on 32-bit kernels. To support the optional > 64-bit counters the code will have to be changed to something like: > > static u64 mipsxx_pmu_read_counter(unsigned int idx) > { > idx = mipsxx_pmu_swizzle_perf_idx(idx); > > switch (idx) { > case 0: > if (read_c0_perfctrl0() & M_PERFCTL_WIDE) > return read_c0_64_bit_perfcntr0(); > else > return read_c0_32_bit_perfcntr0(); > case 1: > if (read_c0_perfctrl1() & M_PERFCTL_WIDE) > return read_c0_64_bit_perfcntr1(); > else > return read_c0_32_bit_perfcntr1(); > ... > > And read_c0_32_bit_perfcntrX need to zero-extend their return value. > > Ralf > From David.Daney@caviumnetworks.com Thu Feb 17 18:26:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 18:26:28 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:18279 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491087Ab1BQR0X (ORCPT ); Thu, 17 Feb 2011 18:26:23 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 09:27:10 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 09:26:18 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 09:26:18 -0800 Message-ID: <4D5D5A39.5040905@caviumnetworks.com> Date: Thu, 17 Feb 2011 09:26:17 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Deng-Cheng Zhu , ralf@linux-mips.org CC: linux-mips@linux-mips.org, Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo Subject: Re: [PATCH v2 4/4] MIPS: perf: Add support for 64-bit perf counters. References: <1295650776-28444-1-git-send-email-ddaney@caviumnetworks.com> <1295650776-28444-5-git-send-email-ddaney@caviumnetworks.com> <4D3F68BE.5080803@caviumnetworks.com> <4D41BC6B.8010408@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 17 Feb 2011 17:26:18.0026 (UTC) FILETIME=[C93D90A0:01CBCEC7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29209 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/17/2011 02:46 AM, Deng-Cheng Zhu wrote: > Hi, David > > > The reason of the perf-record failure on 32bit platforms is that the 32bit > counter read function mipsxx_pmu_read_counter() returns wrong 64bit values. > For example, the counter value 0x12345678 will be returned as > 0xffffffff12345678. So in mipspmu_event_update(), the delta will be wrong. > So here's a possible fix for your reference: > Thanks for the excellent detective work. I will generate a fixed patch set. I think we are getting close to something that will work here. David Daney > --- a/arch/mips/kernel/perf_event_mipsxx.c > +++ b/arch/mips/kernel/perf_event_mipsxx.c > @@ -184,19 +184,21 @@ static unsigned int > mipsxx_pmu_swizzle_perf_idx(unsigned int idx) > return idx; > } > > +#define U32_MASK 0xffffffff > + > static u64 mipsxx_pmu_read_counter(unsigned int idx) > { > idx = mipsxx_pmu_swizzle_perf_idx(idx); > > switch (idx) { > case 0: > - return read_c0_perfcntr0(); > + return read_c0_perfcntr0()& U32_MASK; > case 1: > - return read_c0_perfcntr1(); > + return read_c0_perfcntr1()& U32_MASK; > case 2: > - return read_c0_perfcntr2(); > + return read_c0_perfcntr2()& U32_MASK; > case 3: > - return read_c0_perfcntr3(); > + return read_c0_perfcntr3()& U32_MASK; > default: > WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); > return 0; > > In addition, since you removed the use of cpuc->msbs, some code relative to > this logic can be removed: > > @@ -370,7 +372,6 @@ static int mipspmu_event_set_period(struct > perf_event *event, > u64 left = local64_read(&hwc->period_left); > u64 period = hwc->sample_period; > int ret = 0; > - unsigned long flags; > > if (unlikely((left + period)& (1ULL<< 63))) { > /* left underflowed by more than period. */ > @@ -393,9 +394,7 @@ static int mipspmu_event_set_period(struct > perf_event *event, > > local64_set(&hwc->prev_count, mipspmu.overflow - left); > > - local_irq_save(flags); > mipspmu.write_counter(idx, mipspmu.overflow - left); > - local_irq_restore(flags); > > perf_event_update_userpage(event); > > @@ -406,16 +405,12 @@ static void mipspmu_event_update(struct perf_event *event, > struct hw_perf_event *hwc, > int idx) > { > - unsigned long flags; > u64 prev_raw_count, new_raw_count; > u64 delta; > > again: > prev_raw_count = local64_read(&hwc->prev_count); > - local_irq_save(flags); > - /* Make the counter value be a "real" one. */ > new_raw_count = mipspmu.read_counter(idx); > - local_irq_restore(flags); > > if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, > new_raw_count) != prev_raw_count) > > And here's a general comment: You are putting the majority of the > implementation in perf_event_mipsxx.c. This will require other CPUs like > Loongson2 to replicate quite a lot code in their corresponding files. I > personally think the original "skeleton + #include perf_event_$cpu.c" is a > better choice. I understand you prefer not using code like > "#if defined(CONFIG_CPU_MIPS32)" on the top of perf_event_$cpu.c, but that > is what other architectures (X86/ARM etc) are doing. > > > Deng-Cheng > > > 2011/1/28 Deng-Cheng Zhu: >> OK. I'll try to use tracing when needed. >> >> The hardware I was using for the test was Malta-R with 34K bitfile >> programed into the FPGA. The CPU frequency is 50MHz. >> >> >> Deng-Cheng >> >> >> 2011/1/28 David Daney: >>> On 01/26/2011 10:24 PM, Deng-Cheng Zhu wrote: >>>> >>>> Using your attached patch, I experimented -c and -F by 'ls /'. The numbers >>>> I used are 10, 1000 and 100000 for both -c and -F. >>>> >>>> The number of samples I got was 24 all the way. That means the event >>>> period >>>> to sample and the profiling frequency do not affect the results on MIPS32 >>>> platform. While working on the old code, the system had the following >>>> results: >>>> >>>> -c 10: The system seems busy dealing with interrupts. And the following >>>> log >>>> was printed out: >>>> ================================================ >>>> hda: ide_dma_sff_timer_expiry: DMA status (0x24) >>>> hda: DMA interrupt recovery >>>> hda: lost interrupt >>>> ================================================ >>>> This does need to be fixed later on. >>>> -c 1000: ~11085 samples >>>> -c 100000: ~48 samples ('perf report' still showed some data.) >>>> -F 10: ~118 samples >>>> -F 1000: ~352 samples >>>> -F 100000: ~379 samples >>>> >>>> I'll try to take time to look into the patch to see if anything can be >>>> changed. >>>> >>> >>> I have found it useful to enable tracing, and then placing trace_printk() in >>> mipspmu_event_set_period() to look at the values of: >>> >>> sample_period, period_left that are being used. >>> >>> Also you could use a trace_printk() in mipsxx_pmu_write_counter() to check >>> the value being written to the register. >>> >>> What hardware are you using to test this? I wonder if there is a board with >>> a 32-bit CPU that I could get access to. >>> >>> David Daney >>> >>> >>>> >>>> Deng-Cheng >>>> >>>> >>>> 2011/1/26 David Daney: >>>>> >>>>> On 01/24/2011 07:42 PM, Deng-Cheng Zhu wrote: >>>>>> >>>>>> Hi, David >>>>>> >>>>>> >>>>>> This version does fix the problem with 'perf stat'. However, when >>>>>> working >>>>>> with 'perf record', the following happened: >>>>>> >>>>>> -sh-4.0# perf record -f -e cycles -e instructions -e branches \ >>>>>>> >>>>>>> -e branch-misses -e r12 find / -name "*sys*">/dev/null >>>>>> >>>>>> [ perf record: Woken up 1 times to write data ] >>>>>> [ perf record: Captured and wrote 0.001 MB perf.data (~53 samples) ] >>>>> >>>>> >>>>> I get the same thing. What happens if you supply either '-c xxx' or '-f >>>>> xxx'? >>>>> >>>>> I get:octeon:~/linux/tools/perf# ./perf record -e cycles /bin/ls -l / >>>>> total 100 >>>>> drwxr-xr-x 2 root root 4096 2010-11-12 11:39 bin >>>>> [...] >>>>> drwxr-xr-x 13 root root 4096 2007-05-25 12:28 var >>>>> [ perf record: Woken up 1 times to write data ] >>>>> [ perf record: Captured and wrote 0.002 MB perf.data (~82 samples) ] >>>>> >>>>> Almost no samples as you got. >>>>> >>>>> But if I do: >>>>> >>>>> octeon:~/linux/tools/perf# ./perf record -F 100000 -e cycles /bin/ls -l / >>>>> total 100 >>>>> drwxr-xr-x 2 root root 4096 2010-11-12 11:39 bin >>>>> [...] >>>>> drwxr-xr-x 13 root root 4096 2007-05-25 12:28 var >>>>> [ perf record: Woken up 1 times to write data ] >>>>> [ perf record: Captured and wrote 0.404 MB perf.data (~17653 samples) ] >>>>> >>>>> Look many more samples! >>>>> >>>>> The question is, what is it supposed to do? >>>>> >>>>> If you can get a reasonable number of samples out if you supply -c or >>>>> -F, then I would argue that it is working and the default settings for >>>>> -F are not a good fit for your test case. >>>>> >>>>> I have slightly changed the patch. You could try the attached version >>>>> instead and tell me the results. >>>>> >>>>> >>>>> David Daney >>>>> >>>>> >>>>> >>>> >>> >>> >> > From David.Daney@caviumnetworks.com Thu Feb 17 19:01:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 19:01:09 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19927 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491109Ab1BQSBG (ORCPT ); Thu, 17 Feb 2011 19:01:06 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 10:01:55 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 10:01:03 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 10:01:03 -0800 Message-ID: <4D5D625E.2000503@caviumnetworks.com> Date: Thu, 17 Feb 2011 10:01:02 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Antony Pavlov CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: Kconfig: fix helper dependency References: <1297952906-1099-1-git-send-email-antonynpavlov@gmail.com> In-Reply-To: <1297952906-1099-1-git-send-email-antonynpavlov@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 17 Feb 2011 18:01:03.0095 (UTC) FILETIME=[A409D870:01CBCECC] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29210 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/17/2011 06:28 AM, Antony Pavlov wrote: > The option CAVIUM_OCTEON_HELPER does not depend > on CPU_CAVIUM_OCTEON option. > So my .config file for MIPS Malta board contains > > CONFIG_MIPS_MALTA=y > ... > # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set > # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set > ... > CONFIG_CAVIUM_OCTEON_HELPER=y > > Signed-off-by: Antony Pavlov NAK. I have a patch that takes a different approach. David Daney > --- > arch/mips/cavium-octeon/Kconfig | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig > index caae228..a6a2f3c 100644 > --- a/arch/mips/cavium-octeon/Kconfig > +++ b/arch/mips/cavium-octeon/Kconfig > @@ -97,7 +97,7 @@ config ARCH_SPARSEMEM_ENABLE > > config CAVIUM_OCTEON_HELPER > def_bool y > - depends on OCTEON_ETHERNET || PCI > + depends on CPU_CAVIUM_OCTEON&& (OCTEON_ETHERNET || PCI) > > config IOMMU_HELPER > bool From David.Daney@caviumnetworks.com Thu Feb 17 19:02:12 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 19:02:15 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19978 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491109Ab1BQSCM (ORCPT ); Thu, 17 Feb 2011 19:02:12 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 10:03:03 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 10:02:10 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 10:02:10 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HI265Y026093; Thu, 17 Feb 2011 10:02:06 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HI25lB026091; Thu, 17 Feb 2011 10:02:05 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Antony Pavlov Subject: [PATCH] MIPS: Only include arch/mips/cavium-octeon/Kconfig if CPU_CAVIUM_OCTEON Date: Thu, 17 Feb 2011 10:02:03 -0800 Message-Id: <1297965723-26059-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 17 Feb 2011 18:02:10.0753 (UTC) FILETIME=[CC5DA310:01CBCECC] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29211 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Instead of making each Octeon specific option depend on CPU_CAVIUM_OCTEON, just quit including cavium-octeon/Kconfig if it is not applicable. Signed-off-by: David Daney Cc: Antony Pavlov --- arch/mips/Kconfig | 4 ++++ arch/mips/cavium-octeon/Kconfig | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bd7b64d..b0a1cb3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -748,7 +748,11 @@ source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" + +if CPU_CAVIUM_OCTEON source "arch/mips/cavium-octeon/Kconfig" +endif + source "arch/mips/loongson/Kconfig" endmenu diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index caae228..3dab0ec 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -1,6 +1,5 @@ config CAVIUM_OCTEON_SPECIFIC_OPTIONS bool "Enable Octeon specific options" - depends on CPU_CAVIUM_OCTEON default "y" config CAVIUM_CN63XXP1 @@ -93,7 +92,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC - depends on CPU_CAVIUM_OCTEON config CAVIUM_OCTEON_HELPER def_bool y @@ -107,6 +105,5 @@ config NEED_SG_DMA_LENGTH config SWIOTLB def_bool y - depends on CPU_CAVIUM_OCTEON select IOMMU_HELPER select NEED_SG_DMA_LENGTH -- 1.7.2.3 From kumba@gentoo.org Thu Feb 17 19:47:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 19:47:45 +0100 (CET) Received: from qmta13.westchester.pa.mail.comcast.net ([76.96.59.243]:46948 "EHLO qmta13.westchester.pa.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491109Ab1BQSrm (ORCPT ); Thu, 17 Feb 2011 19:47:42 +0100 Received: from omta24.westchester.pa.mail.comcast.net ([76.96.62.76]) by qmta13.westchester.pa.mail.comcast.net with comcast id 96281g0041ei1Bg5D6nbeB; Thu, 17 Feb 2011 18:47:35 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta24.westchester.pa.mail.comcast.net with comcast id 96nY1g01Z3XYSBH3k6nZ29; Thu, 17 Feb 2011 18:47:34 +0000 Message-ID: <4D5D6D2D.2080309@gentoo.org> Date: Thu, 17 Feb 2011 13:47:09 -0500 From: Kumba User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Lars-Peter Clausen CC: Linux MIPS List , rtc-linux@googlegroups.com Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC References: <4D5A65E3.1050707@gentoo.org> <4D5C5C66.6060205@metafoo.de> <4D5CF0EE.7000308@gentoo.org> <4D5D09FF.6010005@metafoo.de> In-Reply-To: <4D5D09FF.6010005@metafoo.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29212 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips On 02/17/2011 06:43, Lars-Peter Clausen wrote: > That is what I meant. Pass the return value of rtc_valid_tm on, instead of > setting the time to 0 and pretend everything went fine. > You can still keep the dev_err though, no problem with that. Well, that particular return is in the while loop to check for an access lockout. I'll be honest, I got that little bit out of a driver originally written for SGI Octane systems running Linux (an unofficial patch that has since suffered severe bitrot). I know what bit to check to avoid an access lockout, but the DS1685 manual offers several options, and not being a hardware person, I'm not real sure how to represent them in code. Here's what it says: > There are three methods that can handle access of the RTC that avoid any > possibility of accessing inconsistent time and calendar data. The first method > uses the update-ended interrupt. If enabled, an interrupt occurs after every > update cycle that indicates that over 999ms is available to read valid time and > date information. If this interrupt is used, the IRQF bit in Register C should > be cleared before leaving the interrupt routine. > > A second method uses the UIP bit in Register A to determine if the update cycle > is in progress. The UIP bit pulses once per second. After the UIP bit goes > high, the update transfer occurs 244μs later. If a low is read on the UIP bit, > the user has at least 244μs before the time/calendar data is changed. > Therefore, the user should avoid interrupt service routines that would cause > the time needed to read valid time/calendar data to exceed 244μs. > > The third method uses a periodic interrupt to determine if an update cycle is > in progress. The UIP bit in Register A is set high between the setting of the > PF bit in Register C (Figure 4). Periodic interrupts that occur at a rate of > greater than tBUC allow valid time and date information to be reached at each > occurrence of the periodic interrupt. The reads should be complete within > (tPI / 2 + tBUC) to ensure that data is not read during the update cycle. I believe the driver is currently using #2. Other drivers (rtc-sh.c) appear to use a do/while loop and check a bit that I assume is functionally equivalent to UIP here, but I'm not sure if that is accurate or not (and I have not dug up the manual for whatever chip rtc-sh.c touches). What's the best approach to use here to avoid an access lockout? Should I run into an access lockout, what's the best way to handle that? > What do you mean by 'quickly turning around and writing the values back'? > The rtc_time struct passed to the set_time callback is supposed to contain only > valid values. The way I wrote ds1685_rtc_set_time copies the values from rtc_time out to local variables, runs the checks you say I need to remove, then if those pass, writes those values to the RTC registers. I guess what your saying is that the checks are unnecessary because rtc_time has already been checked, so I'm just duplicating work and can write the values straight to the RTC registers? > Well, if it is going to be shared it should probably remain somewhere in > include/, but everything thats not shared should be moved to rtc-ds1685.c like > for example ds1685_priv. I think for now, moving everything into drivers/rtc works best. I'll work from the linux-mips end on how IP32 needs to access this header file when I get that far. > I don't know what you are trying to do, but the current code is extremely > unreadable. > You have all those variables declared in your functions which are on first > sight not used, because they are only referenced from the macros. Furthermore > the invocation of the macro has not the syntax of a function call, although > semantically that is what it is. > And especially ds1685_rtc_begin_data_access is dangerous, because of the > 'return 1', there is no indication when you read the code that a function could > magically exit upon invoking that macro. Well, I thought I was being fancy and cute, but that's what code review is all about. I'm working on breaking these up into inlinable functions and leave that bit of work up to the compiler. > Why? The compiled code will probably be exactly the same as now. Per above, if I can re-work the RTC access loop, I can eliminate this one bit and then this concern becomes moot. Thanks!, -- Joshua Kinard Gentoo/MIPS kumba@gentoo.org "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." --Emperor Turhan, Centauri Republic From David.Daney@caviumnetworks.com Thu Feb 17 20:23:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 20:24:00 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4300 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491109Ab1BQTX5 (ORCPT ); Thu, 17 Feb 2011 20:23:57 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 11:24:44 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 11:23:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 11:23:52 -0800 Message-ID: <4D5D75C7.8020302@caviumnetworks.com> Date: Thu, 17 Feb 2011 11:23:51 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Deng-Cheng Zhu CC: linux-mips@linux-mips.org, ralf@linux-mips.org, Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo Subject: Re: [PATCH v2 4/4] MIPS: perf: Add support for 64-bit perf counters. References: <1295650776-28444-1-git-send-email-ddaney@caviumnetworks.com> <1295650776-28444-5-git-send-email-ddaney@caviumnetworks.com> <4D3F68BE.5080803@caviumnetworks.com> <4D41BC6B.8010408@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 17 Feb 2011 19:23:52.0469 (UTC) FILETIME=[36042450:01CBCED8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29213 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/17/2011 02:46 AM, Deng-Cheng Zhu wrote: > Hi, David [...] > > And here's a general comment: You are putting the majority of the > implementation in perf_event_mipsxx.c. This will require other CPUs like > Loongson2 to replicate quite a lot code in their corresponding files. There is no such implementation. But if someone were to create one, I would suggest they move common code to a separate file that would be shared among the implementations that need it. > I > personally think the original "skeleton + #include perf_event_$cpu.c" is a > better choice. I understand you prefer not using code like > "#if defined(CONFIG_CPU_MIPS32)" on the top of perf_event_$cpu.c, but that > is what other architectures (X86/ARM etc) are doing. > Existing poor practice is not a good reason to do this. David Daney From David.Daney@caviumnetworks.com Thu Feb 17 22:33:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 22:34:02 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8730 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491116Ab1BQVd5 (ORCPT ); Thu, 17 Feb 2011 22:33:57 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 13:34:45 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:33:53 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:33:53 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HLXjb5025348; Thu, 17 Feb 2011 13:33:46 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HLXfhN025345; Thu, 17 Feb 2011 13:33:41 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo , Dezhong Diao , Gabor Juhos , Grant Likely , Deng-Cheng Zhu Subject: [PATCH v3 0/4] MIPS: perf: Add support for 64-bit MIPS hardware counters. Date: Thu, 17 Feb 2011 13:33:35 -0800 Message-Id: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 17 Feb 2011 21:33:53.0191 (UTC) FILETIME=[5F9BDB70:01CBCEEA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29214 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips MIPS hardware performance counters may have either 32-bit or 64-bit wide counter registers. The current implementation only supports the 32-bit variety. These patches aim to add support for 64-bit wide counters while mantaining support for 32-bit. Changes from v2: o Quit sign extending 32-bit counter values. o Remove usless local_irq_save() in several places. Changes from v1: o Removed Octeon processor support to a separate patch set. o Rebased against v5 of Deng-Cheng Zhu's cleanups: http://patchwork.linux-mips.org/patch/2011/ http://patchwork.linux-mips.org/patch/2012/ http://patchwork.linux-mips.org/patch/2013/ http://patchwork.linux-mips.org/patch/2014/ http://patchwork.linux-mips.org/patch/2015/ o Tried to fix problem where 32-bit counters generated way too many interrupts. David Daney (4): MIPS: Add accessor macros for 64-bit performance counter registers. MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c MIPS: perf: Reorganize contents of perf support files. MIPS: perf: Add support for 64-bit perf counters. arch/mips/Kconfig | 2 +- arch/mips/include/asm/mipsregs.h | 8 + arch/mips/kernel/Makefile | 5 +- arch/mips/kernel/perf_event.c | 521 +---------------- arch/mips/kernel/perf_event_mipsxx.c | 1100 +++++++++++++++++++++++----------- 5 files changed, 778 insertions(+), 858 deletions(-) Cc: Peter Zijlstra Cc: Paul Mackerras Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Dezhong Diao Cc: Gabor Juhos Cc: Grant Likely Cc: Deng-Cheng Zhu -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 22:34:20 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 22:34:23 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8729 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491115Ab1BQVd5 (ORCPT ); Thu, 17 Feb 2011 22:33:57 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 13:34:45 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:33:53 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:33:53 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HLXnaJ025361; Thu, 17 Feb 2011 13:33:49 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HLXnl5025360; Thu, 17 Feb 2011 13:33:49 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v3 1/4] MIPS: Add accessor macros for 64-bit performance counter registers. Date: Thu, 17 Feb 2011 13:33:36 -0800 Message-Id: <1297978419-25309-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> References: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 17 Feb 2011 21:33:53.0191 (UTC) FILETIME=[5F9BDB70:01CBCEEA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29215 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/include/asm/mipsregs.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index d5c9eaa..86c7ec1 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1019,18 +1019,26 @@ do { \ #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) +#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) +#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) +#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) +#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) +#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) +#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) +#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) +#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) /* RM9000 PerfCount performance counter register */ #define read_c0_perfcount() __read_64bit_c0_register($25, 0) -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 22:34:42 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 22:34:48 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8735 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491118Ab1BQVeA (ORCPT ); Thu, 17 Feb 2011 22:34:00 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 13:34:50 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:33:58 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:33:58 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HLXqt3025365; Thu, 17 Feb 2011 13:33:52 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HLXp3c025364; Thu, 17 Feb 2011 13:33:51 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo , Deng-Cheng Zhu Subject: [PATCH v3 2/4] MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c Date: Thu, 17 Feb 2011 13:33:37 -0800 Message-Id: <1297978419-25309-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> References: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 17 Feb 2011 21:33:58.0160 (UTC) FILETIME=[62921100:01CBCEEA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29216 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Get rid of a bunch of useless inline declarations, and join a bunch of improperly split lines. Signed-off-by: David Daney Cc: Peter Zijlstra Cc: Paul Mackerras Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Deng-Cheng Zhu --- arch/mips/kernel/perf_event.c | 26 +++++------- arch/mips/kernel/perf_event_mipsxx.c | 68 +++++++++++++--------------------- 2 files changed, 37 insertions(+), 57 deletions(-) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index a824485..931d957 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -118,10 +118,9 @@ struct mips_pmu { static const struct mips_pmu *mipspmu; -static int -mipspmu_event_set_period(struct perf_event *event, - struct hw_perf_event *hwc, - int idx) +static int mipspmu_event_set_period(struct perf_event *event, + struct hw_perf_event *hwc, + int idx) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); s64 left = local64_read(&hwc->period_left); @@ -162,8 +161,8 @@ mipspmu_event_set_period(struct perf_event *event, } static void mipspmu_event_update(struct perf_event *event, - struct hw_perf_event *hwc, - int idx) + struct hw_perf_event *hwc, + int idx) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); unsigned long flags; @@ -422,8 +421,7 @@ static struct pmu pmu = { .read = mipspmu_read, }; -static inline unsigned int -mipspmu_perf_event_encode(const struct mips_perf_event *pev) +static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) { /* * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for @@ -439,8 +437,7 @@ mipspmu_perf_event_encode(const struct mips_perf_event *pev) #endif } -static const struct mips_perf_event * -mipspmu_map_general_event(int idx) +static const struct mips_perf_event *mipspmu_map_general_event(int idx) { const struct mips_perf_event *pev; @@ -451,8 +448,7 @@ mipspmu_map_general_event(int idx) return pev; } -static const struct mips_perf_event * -mipspmu_map_cache_event(u64 config) +static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) { unsigned int cache_type, cache_op, cache_result; const struct mips_perf_event *pev; @@ -515,9 +511,9 @@ static int validate_group(struct perf_event *event) } /* This is needed by specific irq handlers in perf_event_*.c */ -static void -handle_associated_event(struct cpu_hw_events *cpuc, - int idx, struct perf_sample_data *data, struct pt_regs *regs) +static void handle_associated_event(struct cpu_hw_events *cpuc, + int idx, struct perf_sample_data *data, + struct pt_regs *regs) { struct perf_event *event = cpuc->events[idx]; struct hw_perf_event *hwc = &event->hw; diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index d9a7db7..72cd2e1 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -49,37 +49,32 @@ static int cpu_has_mipsmt_pertccounters; #endif /* Copied from op_model_mipsxx.c */ -static inline unsigned int vpe_shift(void) +static unsigned int vpe_shift(void) { if (num_possible_cpus() > 1) return 1; return 0; } -#else /* !CONFIG_MIPS_MT_SMP */ -#define vpe_id() 0 - -static inline unsigned int vpe_shift(void) -{ - return 0; -} -#endif /* CONFIG_MIPS_MT_SMP */ -static inline unsigned int -counters_total_to_per_cpu(unsigned int counters) +static unsigned int counters_total_to_per_cpu(unsigned int counters) { return counters >> vpe_shift(); } -static inline unsigned int -counters_per_cpu_to_total(unsigned int counters) +static unsigned int counters_per_cpu_to_total(unsigned int counters) { return counters << vpe_shift(); } +#else /* !CONFIG_MIPS_MT_SMP */ +#define vpe_id() 0 + +#endif /* CONFIG_MIPS_MT_SMP */ + #define __define_perf_accessors(r, n, np) \ \ -static inline unsigned int r_c0_ ## r ## n(void) \ +static unsigned int r_c0_ ## r ## n(void) \ { \ unsigned int cpu = vpe_id(); \ \ @@ -94,7 +89,7 @@ static inline unsigned int r_c0_ ## r ## n(void) \ return 0; \ } \ \ -static inline void w_c0_ ## r ## n(unsigned int value) \ +static void w_c0_ ## r ## n(unsigned int value) \ { \ unsigned int cpu = vpe_id(); \ \ @@ -121,7 +116,7 @@ __define_perf_accessors(perfctrl, 1, 3) __define_perf_accessors(perfctrl, 2, 0) __define_perf_accessors(perfctrl, 3, 1) -static inline int __n_counters(void) +static int __n_counters(void) { if (!(read_c0_config1() & M_CONFIG1_PC)) return 0; @@ -135,7 +130,7 @@ static inline int __n_counters(void) return 4; } -static inline int n_counters(void) +static int n_counters(void) { int counters; @@ -175,8 +170,7 @@ static void reset_counters(void *arg) } } -static inline u64 -mipsxx_pmu_read_counter(unsigned int idx) +static u64 mipsxx_pmu_read_counter(unsigned int idx) { switch (idx) { case 0: @@ -193,8 +187,7 @@ mipsxx_pmu_read_counter(unsigned int idx) } } -static inline void -mipsxx_pmu_write_counter(unsigned int idx, u64 val) +static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) { switch (idx) { case 0: @@ -212,8 +205,7 @@ mipsxx_pmu_write_counter(unsigned int idx, u64 val) } } -static inline unsigned int -mipsxx_pmu_read_control(unsigned int idx) +static unsigned int mipsxx_pmu_read_control(unsigned int idx) { switch (idx) { case 0: @@ -230,8 +222,7 @@ mipsxx_pmu_read_control(unsigned int idx) } } -static inline void -mipsxx_pmu_write_control(unsigned int idx, unsigned int val) +static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) { switch (idx) { case 0: @@ -483,9 +474,8 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map }; #ifdef CONFIG_MIPS_MT_SMP -static void -check_and_calc_range(struct perf_event *event, - const struct mips_perf_event *pev) +static void check_and_calc_range(struct perf_event *event, + const struct mips_perf_event *pev) { struct hw_perf_event *hwc = &event->hw; @@ -508,9 +498,8 @@ check_and_calc_range(struct perf_event *event, hwc->config_base |= M_TC_EN_ALL; } #else -static void -check_and_calc_range(struct perf_event *event, - const struct mips_perf_event *pev) +static void check_and_calc_range(struct perf_event *event, + const struct mips_perf_event *pev) { } #endif @@ -705,8 +694,7 @@ static int mipsxx_pmu_handle_shared_irq(void) return handled; } -static irqreturn_t -mipsxx_pmu_handle_irq(int irq, void *dev) +static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) { return mipsxx_pmu_handle_shared_irq(); } @@ -738,9 +726,8 @@ static void mipsxx_pmu_stop(void) #endif } -static int -mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, - struct hw_perf_event *hwc) +static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, + struct hw_perf_event *hwc) { int i; @@ -769,8 +756,7 @@ mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, return -EAGAIN; } -static void -mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) +static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); unsigned long flags; @@ -788,8 +774,7 @@ mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) local_irq_restore(flags); } -static void -mipsxx_pmu_disable_event(int idx) +static void mipsxx_pmu_disable_event(int idx) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); unsigned long flags; @@ -864,8 +849,7 @@ mipsxx_pmu_disable_event(int idx) * then 128 needs to be added to 15 as the input for the event config, * i.e., 143 (0x8F) to be used. */ -static const struct mips_perf_event * -mipsxx_pmu_map_raw_event(u64 config) +static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) { unsigned int raw_id = config & 0xff; unsigned int base_id = raw_id & 0x7f; -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 22:35:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 22:35:17 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8745 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491120Ab1BQVeB (ORCPT ); Thu, 17 Feb 2011 22:34:01 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 13:34:50 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:33:58 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:33:58 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HLXsjf025369; Thu, 17 Feb 2011 13:33:55 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HLXrxc025368; Thu, 17 Feb 2011 13:33:53 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo , Dezhong Diao , Gabor Juhos , Deng-Cheng Zhu Subject: [PATCH v3 3/4] MIPS: perf: Reorganize contents of perf support files. Date: Thu, 17 Feb 2011 13:33:38 -0800 Message-Id: <1297978419-25309-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> References: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 17 Feb 2011 21:33:58.0160 (UTC) FILETIME=[62921100:01CBCEEA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29217 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The contents of arch/mips/kernel/perf_event.c and arch/mips/kernel/perf_event_mipsxx.c were divided in a seemingly ad hoc manner, with the first including the second. I moved all the hardware counter support code to perf_event_mipsxx.c and removed the gating #ifdefs to the Kconfig and Makefile. Now perf_event.c contains only the callchain support, everything else is in perf_event_mipsxx.c There are no code changes, only moving of functions from one file to the other, or removing empty unneeded functions. Signed-off-by: David Daney Cc: Peter Zijlstra Cc: Paul Mackerras Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Dezhong Diao Cc: Gabor Juhos Cc: Deng-Cheng Zhu --- arch/mips/Kconfig | 2 +- arch/mips/kernel/Makefile | 5 +- arch/mips/kernel/perf_event.c | 517 +--------------------------------- arch/mips/kernel/perf_event_mipsxx.c | 532 +++++++++++++++++++++++++++++++++- 4 files changed, 534 insertions(+), 522 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b0a1cb3..e89b416 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2036,7 +2036,7 @@ config NODES_SHIFT config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32 + depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1) default y help Enable hardware performance counter support for perf events. If diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index cedee2b..753b421 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -11,6 +11,8 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ ifdef CONFIG_FUNCTION_TRACER CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_early_printk.o = -pg +CFLAGS_REMOVE_perf_event.o = -pg +CFLAGS_REMOVE_perf_event_mipsxx.o = -pg endif obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o @@ -105,7 +107,8 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/ -obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index 931d957..c1cf9c6 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -14,531 +14,16 @@ * published by the Free Software Foundation. */ -#include -#include -#include -#include #include -#include -#include -#include #include -#include /* For perf_irq */ - -/* These are for 32bit counters. For 64bit ones, define them accordingly. */ -#define MAX_PERIOD ((1ULL << 32) - 1) -#define VALID_COUNT 0x7fffffff -#define TOTAL_BITS 32 -#define HIGHEST_BIT 31 - -#define MIPS_MAX_HWEVENTS 4 - -struct cpu_hw_events { - /* Array of events on this cpu. */ - struct perf_event *events[MIPS_MAX_HWEVENTS]; - - /* - * Set the bit (indexed by the counter number) when the counter - * is used for an event. - */ - unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; - - /* - * The borrowed MSB for the performance counter. A MIPS performance - * counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit - * counters) as a factor of determining whether a counter overflow - * should be signaled. So here we use a separate MSB for each - * counter to make things easy. - */ - unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; - - /* - * Software copy of the control register for each performance counter. - * MIPS CPUs vary in performance counters. They use this differently, - * and even may not use it. - */ - unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; -}; -DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { - .saved_ctrl = {0}, -}; - -/* The description of MIPS performance events. */ -struct mips_perf_event { - unsigned int event_id; - /* - * MIPS performance counters are indexed starting from 0. - * CNTR_EVEN indicates the indexes of the counters to be used are - * even numbers. - */ - unsigned int cntr_mask; - #define CNTR_EVEN 0x55555555 - #define CNTR_ODD 0xaaaaaaaa -#ifdef CONFIG_MIPS_MT_SMP - enum { - T = 0, - V = 1, - P = 2, - } range; -#else - #define T - #define V - #define P -#endif -}; - -static struct mips_perf_event raw_event; -static DEFINE_MUTEX(raw_event_mutex); - -#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff -#define C(x) PERF_COUNT_HW_CACHE_##x - -struct mips_pmu { - const char *name; - int irq; - irqreturn_t (*handle_irq)(int irq, void *dev); - int (*handle_shared_irq)(void); - void (*start)(void); - void (*stop)(void); - int (*alloc_counter)(struct cpu_hw_events *cpuc, - struct hw_perf_event *hwc); - u64 (*read_counter)(unsigned int idx); - void (*write_counter)(unsigned int idx, u64 val); - void (*enable_event)(struct hw_perf_event *evt, int idx); - void (*disable_event)(int idx); - const struct mips_perf_event *(*map_raw_event)(u64 config); - const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; - const struct mips_perf_event (*cache_event_map) - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX]; - unsigned int num_counters; -}; - -static const struct mips_pmu *mipspmu; - -static int mipspmu_event_set_period(struct perf_event *event, - struct hw_perf_event *hwc, - int idx) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - s64 left = local64_read(&hwc->period_left); - s64 period = hwc->sample_period; - int ret = 0; - u64 uleft; - unsigned long flags; - - if (unlikely(left <= -period)) { - left = period; - local64_set(&hwc->period_left, left); - hwc->last_period = period; - ret = 1; - } - - if (unlikely(left <= 0)) { - left += period; - local64_set(&hwc->period_left, left); - hwc->last_period = period; - ret = 1; - } - - if (left > (s64)MAX_PERIOD) - left = MAX_PERIOD; - - local64_set(&hwc->prev_count, (u64)-left); - - local_irq_save(flags); - uleft = (u64)(-left) & MAX_PERIOD; - uleft > VALID_COUNT ? - set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs); - mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT); - local_irq_restore(flags); - - perf_event_update_userpage(event); - - return ret; -} - -static void mipspmu_event_update(struct perf_event *event, - struct hw_perf_event *hwc, - int idx) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - unsigned long flags; - int shift = 64 - TOTAL_BITS; - s64 prev_raw_count, new_raw_count; - u64 delta; - -again: - prev_raw_count = local64_read(&hwc->prev_count); - local_irq_save(flags); - /* Make the counter value be a "real" one. */ - new_raw_count = mipspmu->read_counter(idx); - if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) { - new_raw_count &= VALID_COUNT; - clear_bit(idx, cpuc->msbs); - } else - new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT); - local_irq_restore(flags); - - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - new_raw_count) != prev_raw_count) - goto again; - - delta = (new_raw_count << shift) - (prev_raw_count << shift); - delta >>= shift; - - local64_add(delta, &event->count); - local64_sub(delta, &hwc->period_left); - - return; -} - -static void mipspmu_start(struct perf_event *event, int flags) -{ - struct hw_perf_event *hwc = &event->hw; - - if (!mipspmu) - return; - - if (flags & PERF_EF_RELOAD) - WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); - - hwc->state = 0; - - /* Set the period for the event. */ - mipspmu_event_set_period(event, hwc, hwc->idx); - - /* Enable the event. */ - mipspmu->enable_event(hwc, hwc->idx); -} - -static void mipspmu_stop(struct perf_event *event, int flags) -{ - struct hw_perf_event *hwc = &event->hw; - - if (!mipspmu) - return; - - if (!(hwc->state & PERF_HES_STOPPED)) { - /* We are working on a local event. */ - mipspmu->disable_event(hwc->idx); - barrier(); - mipspmu_event_update(event, hwc, hwc->idx); - hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; - } -} - -static int mipspmu_add(struct perf_event *event, int flags) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - struct hw_perf_event *hwc = &event->hw; - int idx; - int err = 0; - - perf_pmu_disable(event->pmu); - - /* To look for a free counter for this event. */ - idx = mipspmu->alloc_counter(cpuc, hwc); - if (idx < 0) { - err = idx; - goto out; - } - - /* - * If there is an event in the counter we are going to use then - * make sure it is disabled. - */ - event->hw.idx = idx; - mipspmu->disable_event(idx); - cpuc->events[idx] = event; - - hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; - if (flags & PERF_EF_START) - mipspmu_start(event, PERF_EF_RELOAD); - - /* Propagate our changes to the userspace mapping. */ - perf_event_update_userpage(event); - -out: - perf_pmu_enable(event->pmu); - return err; -} - -static void mipspmu_del(struct perf_event *event, int flags) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - WARN_ON(idx < 0 || idx >= mipspmu->num_counters); - - mipspmu_stop(event, PERF_EF_UPDATE); - cpuc->events[idx] = NULL; - clear_bit(idx, cpuc->used_mask); - - perf_event_update_userpage(event); -} - -static void mipspmu_read(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - - /* Don't read disabled counters! */ - if (hwc->idx < 0) - return; - - mipspmu_event_update(event, hwc, hwc->idx); -} - -static void mipspmu_enable(struct pmu *pmu) -{ - if (mipspmu) - mipspmu->start(); -} - -static void mipspmu_disable(struct pmu *pmu) -{ - if (mipspmu) - mipspmu->stop(); -} - -static atomic_t active_events = ATOMIC_INIT(0); -static DEFINE_MUTEX(pmu_reserve_mutex); -static int (*save_perf_irq)(void); - -static int mipspmu_get_irq(void) -{ - int err; - - if (mipspmu->irq >= 0) { - /* Request my own irq handler. */ - err = request_irq(mipspmu->irq, mipspmu->handle_irq, - IRQF_DISABLED | IRQF_NOBALANCING, - "mips_perf_pmu", NULL); - if (err) { - pr_warning("Unable to request IRQ%d for MIPS " - "performance counters!\n", mipspmu->irq); - } - } else if (cp0_perfcount_irq < 0) { - /* - * We are sharing the irq number with the timer interrupt. - */ - save_perf_irq = perf_irq; - perf_irq = mipspmu->handle_shared_irq; - err = 0; - } else { - pr_warning("The platform hasn't properly defined its " - "interrupt controller.\n"); - err = -ENOENT; - } - - return err; -} - -static void mipspmu_free_irq(void) -{ - if (mipspmu->irq >= 0) - free_irq(mipspmu->irq, NULL); - else if (cp0_perfcount_irq < 0) - perf_irq = save_perf_irq; -} - -/* - * mipsxx/rm9000/loongson2 have different performance counters, they have - * specific low-level init routines. - */ -static void reset_counters(void *arg); -static int __hw_perf_event_init(struct perf_event *event); - -static void hw_perf_event_destroy(struct perf_event *event) -{ - if (atomic_dec_and_mutex_lock(&active_events, - &pmu_reserve_mutex)) { - /* - * We must not call the destroy function with interrupts - * disabled. - */ - on_each_cpu(reset_counters, - (void *)(long)mipspmu->num_counters, 1); - mipspmu_free_irq(); - mutex_unlock(&pmu_reserve_mutex); - } -} - -static int mipspmu_event_init(struct perf_event *event) -{ - int err = 0; - - switch (event->attr.type) { - case PERF_TYPE_RAW: - case PERF_TYPE_HARDWARE: - case PERF_TYPE_HW_CACHE: - break; - - default: - return -ENOENT; - } - - if (!mipspmu || event->cpu >= nr_cpumask_bits || - (event->cpu >= 0 && !cpu_online(event->cpu))) - return -ENODEV; - - if (!atomic_inc_not_zero(&active_events)) { - if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) { - atomic_dec(&active_events); - return -ENOSPC; - } - - mutex_lock(&pmu_reserve_mutex); - if (atomic_read(&active_events) == 0) - err = mipspmu_get_irq(); - - if (!err) - atomic_inc(&active_events); - mutex_unlock(&pmu_reserve_mutex); - } - - if (err) - return err; - - err = __hw_perf_event_init(event); - if (err) - hw_perf_event_destroy(event); - - return err; -} - -static struct pmu pmu = { - .pmu_enable = mipspmu_enable, - .pmu_disable = mipspmu_disable, - .event_init = mipspmu_event_init, - .add = mipspmu_add, - .del = mipspmu_del, - .start = mipspmu_start, - .stop = mipspmu_stop, - .read = mipspmu_read, -}; - -static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) -{ -/* - * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for - * event_id. - */ -#ifdef CONFIG_MIPS_MT_SMP - return ((unsigned int)pev->range << 24) | - (pev->cntr_mask & 0xffff00) | - (pev->event_id & 0xff); -#else - return (pev->cntr_mask & 0xffff00) | - (pev->event_id & 0xff); -#endif -} - -static const struct mips_perf_event *mipspmu_map_general_event(int idx) -{ - const struct mips_perf_event *pev; - - pev = ((*mipspmu->general_event_map)[idx].event_id == - UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) : - &(*mipspmu->general_event_map)[idx]); - - return pev; -} - -static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) -{ - unsigned int cache_type, cache_op, cache_result; - const struct mips_perf_event *pev; - - cache_type = (config >> 0) & 0xff; - if (cache_type >= PERF_COUNT_HW_CACHE_MAX) - return ERR_PTR(-EINVAL); - - cache_op = (config >> 8) & 0xff; - if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) - return ERR_PTR(-EINVAL); - - cache_result = (config >> 16) & 0xff; - if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) - return ERR_PTR(-EINVAL); - - pev = &((*mipspmu->cache_event_map) - [cache_type] - [cache_op] - [cache_result]); - - if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID) - return ERR_PTR(-EOPNOTSUPP); - - return pev; - -} - -static int validate_event(struct cpu_hw_events *cpuc, - struct perf_event *event) -{ - struct hw_perf_event fake_hwc = event->hw; - - /* Allow mixed event group. So return 1 to pass validation. */ - if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) - return 1; - - return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; -} - -static int validate_group(struct perf_event *event) -{ - struct perf_event *sibling, *leader = event->group_leader; - struct cpu_hw_events fake_cpuc; - - memset(&fake_cpuc, 0, sizeof(fake_cpuc)); - - if (!validate_event(&fake_cpuc, leader)) - return -ENOSPC; - - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { - if (!validate_event(&fake_cpuc, sibling)) - return -ENOSPC; - } - - if (!validate_event(&fake_cpuc, event)) - return -ENOSPC; - - return 0; -} - -/* This is needed by specific irq handlers in perf_event_*.c */ -static void handle_associated_event(struct cpu_hw_events *cpuc, - int idx, struct perf_sample_data *data, - struct pt_regs *regs) -{ - struct perf_event *event = cpuc->events[idx]; - struct hw_perf_event *hwc = &event->hw; - - mipspmu_event_update(event, hwc, idx); - data->period = event->hw.last_period; - if (!mipspmu_event_set_period(event, hwc, idx)) - return; - - if (perf_event_overflow(event, 0, data, regs)) - mipspmu->disable_event(idx); -} - -#include "perf_event_mipsxx.c" /* Callchain handling code. */ /* * Leave userspace callchain empty for now. When we find a way to trace - * the user stack callchains, we add here. + * the user stack callchains, we will add it here. */ -void perf_callchain_user(struct perf_callchain_entry *entry, - struct pt_regs *regs) -{ -} static void save_raw_perf_callchain(struct perf_callchain_entry *entry, unsigned long reg29) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 72cd2e1..409207d 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1,5 +1,531 @@ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \ - defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1) +/* + * Linux performance counter support for MIPS. + * + * Copyright (C) 2010 MIPS Technologies, Inc. + * Author: Deng-Cheng Zhu + * + * This code is based on the implementation for ARM, which is in turn + * based on the sparc64 perf event code and the x86 code. Performance + * counter access is based on the MIPS Oprofile code. And the callchain + * support references the code of MIPS stacktrace.c. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include /* For perf_irq */ + +/* These are for 32bit counters. For 64bit ones, define them accordingly. */ +#define MAX_PERIOD ((1ULL << 32) - 1) +#define VALID_COUNT 0x7fffffff +#define TOTAL_BITS 32 +#define HIGHEST_BIT 31 + +#define MIPS_MAX_HWEVENTS 4 + +struct cpu_hw_events { + /* Array of events on this cpu. */ + struct perf_event *events[MIPS_MAX_HWEVENTS]; + + /* + * Set the bit (indexed by the counter number) when the counter + * is used for an event. + */ + unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; + + /* + * The borrowed MSB for the performance counter. A MIPS performance + * counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit + * counters) as a factor of determining whether a counter overflow + * should be signaled. So here we use a separate MSB for each + * counter to make things easy. + */ + unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; + + /* + * Software copy of the control register for each performance counter. + * MIPS CPUs vary in performance counters. They use this differently, + * and even may not use it. + */ + unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; +}; +DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { + .saved_ctrl = {0}, +}; + +/* The description of MIPS performance events. */ +struct mips_perf_event { + unsigned int event_id; + /* + * MIPS performance counters are indexed starting from 0. + * CNTR_EVEN indicates the indexes of the counters to be used are + * even numbers. + */ + unsigned int cntr_mask; + #define CNTR_EVEN 0x55555555 + #define CNTR_ODD 0xaaaaaaaa +#ifdef CONFIG_MIPS_MT_SMP + enum { + T = 0, + V = 1, + P = 2, + } range; +#else + #define T + #define V + #define P +#endif +}; + +static struct mips_perf_event raw_event; +static DEFINE_MUTEX(raw_event_mutex); + +#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff +#define C(x) PERF_COUNT_HW_CACHE_##x + +struct mips_pmu { + const char *name; + int irq; + irqreturn_t (*handle_irq)(int irq, void *dev); + int (*handle_shared_irq)(void); + void (*start)(void); + void (*stop)(void); + int (*alloc_counter)(struct cpu_hw_events *cpuc, + struct hw_perf_event *hwc); + u64 (*read_counter)(unsigned int idx); + void (*write_counter)(unsigned int idx, u64 val); + void (*enable_event)(struct hw_perf_event *evt, int idx); + void (*disable_event)(int idx); + const struct mips_perf_event *(*map_raw_event)(u64 config); + const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; + const struct mips_perf_event (*cache_event_map) + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + unsigned int num_counters; +}; + +static const struct mips_pmu *mipspmu; + +static int mipspmu_event_set_period(struct perf_event *event, + struct hw_perf_event *hwc, + int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + s64 left = local64_read(&hwc->period_left); + s64 period = hwc->sample_period; + int ret = 0; + u64 uleft; + unsigned long flags; + + if (unlikely(left <= -period)) { + left = period; + local64_set(&hwc->period_left, left); + hwc->last_period = period; + ret = 1; + } + + if (unlikely(left <= 0)) { + left += period; + local64_set(&hwc->period_left, left); + hwc->last_period = period; + ret = 1; + } + + if (left > (s64)MAX_PERIOD) + left = MAX_PERIOD; + + local64_set(&hwc->prev_count, (u64)-left); + + local_irq_save(flags); + uleft = (u64)(-left) & MAX_PERIOD; + uleft > VALID_COUNT ? + set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs); + mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT); + local_irq_restore(flags); + + perf_event_update_userpage(event); + + return ret; +} + +static void mipspmu_event_update(struct perf_event *event, + struct hw_perf_event *hwc, + int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + int shift = 64 - TOTAL_BITS; + s64 prev_raw_count, new_raw_count; + u64 delta; + +again: + prev_raw_count = local64_read(&hwc->prev_count); + local_irq_save(flags); + /* Make the counter value be a "real" one. */ + new_raw_count = mipspmu->read_counter(idx); + if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) { + new_raw_count &= VALID_COUNT; + clear_bit(idx, cpuc->msbs); + } else + new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT); + local_irq_restore(flags); + + if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, + new_raw_count) != prev_raw_count) + goto again; + + delta = (new_raw_count << shift) - (prev_raw_count << shift); + delta >>= shift; + + local64_add(delta, &event->count); + local64_sub(delta, &hwc->period_left); + + return; +} + +static void mipspmu_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc = &event->hw; + + if (!mipspmu) + return; + + if (flags & PERF_EF_RELOAD) + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); + + hwc->state = 0; + + /* Set the period for the event. */ + mipspmu_event_set_period(event, hwc, hwc->idx); + + /* Enable the event. */ + mipspmu->enable_event(hwc, hwc->idx); +} + +static void mipspmu_stop(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc = &event->hw; + + if (!mipspmu) + return; + + if (!(hwc->state & PERF_HES_STOPPED)) { + /* We are working on a local event. */ + mipspmu->disable_event(hwc->idx); + barrier(); + mipspmu_event_update(event, hwc, hwc->idx); + hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; + } +} + +static int mipspmu_add(struct perf_event *event, int flags) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct hw_perf_event *hwc = &event->hw; + int idx; + int err = 0; + + perf_pmu_disable(event->pmu); + + /* To look for a free counter for this event. */ + idx = mipspmu->alloc_counter(cpuc, hwc); + if (idx < 0) { + err = idx; + goto out; + } + + /* + * If there is an event in the counter we are going to use then + * make sure it is disabled. + */ + event->hw.idx = idx; + mipspmu->disable_event(idx); + cpuc->events[idx] = event; + + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; + if (flags & PERF_EF_START) + mipspmu_start(event, PERF_EF_RELOAD); + + /* Propagate our changes to the userspace mapping. */ + perf_event_update_userpage(event); + +out: + perf_pmu_enable(event->pmu); + return err; +} + +static void mipspmu_del(struct perf_event *event, int flags) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + mipspmu_stop(event, PERF_EF_UPDATE); + cpuc->events[idx] = NULL; + clear_bit(idx, cpuc->used_mask); + + perf_event_update_userpage(event); +} + +static void mipspmu_read(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + + /* Don't read disabled counters! */ + if (hwc->idx < 0) + return; + + mipspmu_event_update(event, hwc, hwc->idx); +} + +static void mipspmu_enable(struct pmu *pmu) +{ + if (mipspmu) + mipspmu->start(); +} + +static void mipspmu_disable(struct pmu *pmu) +{ + if (mipspmu) + mipspmu->stop(); +} + +static atomic_t active_events = ATOMIC_INIT(0); +static DEFINE_MUTEX(pmu_reserve_mutex); +static int (*save_perf_irq)(void); + +static int mipspmu_get_irq(void) +{ + int err; + + if (mipspmu->irq >= 0) { + /* Request my own irq handler. */ + err = request_irq(mipspmu->irq, mipspmu->handle_irq, + IRQF_DISABLED | IRQF_NOBALANCING, + "mips_perf_pmu", NULL); + if (err) { + pr_warning("Unable to request IRQ%d for MIPS " + "performance counters!\n", mipspmu->irq); + } + } else if (cp0_perfcount_irq < 0) { + /* + * We are sharing the irq number with the timer interrupt. + */ + save_perf_irq = perf_irq; + perf_irq = mipspmu->handle_shared_irq; + err = 0; + } else { + pr_warning("The platform hasn't properly defined its " + "interrupt controller.\n"); + err = -ENOENT; + } + + return err; +} + +static void mipspmu_free_irq(void) +{ + if (mipspmu->irq >= 0) + free_irq(mipspmu->irq, NULL); + else if (cp0_perfcount_irq < 0) + perf_irq = save_perf_irq; +} + +/* + * mipsxx/rm9000/loongson2 have different performance counters, they have + * specific low-level init routines. + */ +static void reset_counters(void *arg); +static int __hw_perf_event_init(struct perf_event *event); + +static void hw_perf_event_destroy(struct perf_event *event) +{ + if (atomic_dec_and_mutex_lock(&active_events, + &pmu_reserve_mutex)) { + /* + * We must not call the destroy function with interrupts + * disabled. + */ + on_each_cpu(reset_counters, + (void *)(long)mipspmu->num_counters, 1); + mipspmu_free_irq(); + mutex_unlock(&pmu_reserve_mutex); + } +} + +static int mipspmu_event_init(struct perf_event *event) +{ + int err = 0; + + switch (event->attr.type) { + case PERF_TYPE_RAW: + case PERF_TYPE_HARDWARE: + case PERF_TYPE_HW_CACHE: + break; + + default: + return -ENOENT; + } + + if (!mipspmu || event->cpu >= nr_cpumask_bits || + (event->cpu >= 0 && !cpu_online(event->cpu))) + return -ENODEV; + + if (!atomic_inc_not_zero(&active_events)) { + if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) { + atomic_dec(&active_events); + return -ENOSPC; + } + + mutex_lock(&pmu_reserve_mutex); + if (atomic_read(&active_events) == 0) + err = mipspmu_get_irq(); + + if (!err) + atomic_inc(&active_events); + mutex_unlock(&pmu_reserve_mutex); + } + + if (err) + return err; + + err = __hw_perf_event_init(event); + if (err) + hw_perf_event_destroy(event); + + return err; +} + +static struct pmu pmu = { + .pmu_enable = mipspmu_enable, + .pmu_disable = mipspmu_disable, + .event_init = mipspmu_event_init, + .add = mipspmu_add, + .del = mipspmu_del, + .start = mipspmu_start, + .stop = mipspmu_stop, + .read = mipspmu_read, +}; + +static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) +{ +/* + * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for + * event_id. + */ +#ifdef CONFIG_MIPS_MT_SMP + return ((unsigned int)pev->range << 24) | + (pev->cntr_mask & 0xffff00) | + (pev->event_id & 0xff); +#else + return (pev->cntr_mask & 0xffff00) | + (pev->event_id & 0xff); +#endif +} + +static const struct mips_perf_event *mipspmu_map_general_event(int idx) +{ + const struct mips_perf_event *pev; + + pev = ((*mipspmu->general_event_map)[idx].event_id == + UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) : + &(*mipspmu->general_event_map)[idx]); + + return pev; +} + +static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) +{ + unsigned int cache_type, cache_op, cache_result; + const struct mips_perf_event *pev; + + cache_type = (config >> 0) & 0xff; + if (cache_type >= PERF_COUNT_HW_CACHE_MAX) + return ERR_PTR(-EINVAL); + + cache_op = (config >> 8) & 0xff; + if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) + return ERR_PTR(-EINVAL); + + cache_result = (config >> 16) & 0xff; + if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) + return ERR_PTR(-EINVAL); + + pev = &((*mipspmu->cache_event_map) + [cache_type] + [cache_op] + [cache_result]); + + if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID) + return ERR_PTR(-EOPNOTSUPP); + + return pev; + +} + +static int validate_event(struct cpu_hw_events *cpuc, + struct perf_event *event) +{ + struct hw_perf_event fake_hwc = event->hw; + + /* Allow mixed event group. So return 1 to pass validation. */ + if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) + return 1; + + return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; +} + +static int validate_group(struct perf_event *event) +{ + struct perf_event *sibling, *leader = event->group_leader; + struct cpu_hw_events fake_cpuc; + + memset(&fake_cpuc, 0, sizeof(fake_cpuc)); + + if (!validate_event(&fake_cpuc, leader)) + return -ENOSPC; + + list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + if (!validate_event(&fake_cpuc, sibling)) + return -ENOSPC; + } + + if (!validate_event(&fake_cpuc, event)) + return -ENOSPC; + + return 0; +} + +/* This is needed by specific irq handlers in perf_event_*.c */ +static void handle_associated_event(struct cpu_hw_events *cpuc, + int idx, struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc = &event->hw; + + mipspmu_event_update(event, hwc, idx); + data->period = event->hw.last_period; + if (!mipspmu_event_set_period(event, hwc, idx)) + return; + + if (perf_event_overflow(event, 0, data, regs)) + mipspmu->disable_event(idx); +} #define M_CONFIG1_PC (1 << 4) @@ -1034,5 +1560,3 @@ init_hw_perf_events(void) return 0; } early_initcall(init_hw_perf_events); - -#endif /* defined(CONFIG_CPU_MIPS32)... */ -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 22:35:35 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 22:35:45 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8763 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491122Ab1BQVeF (ORCPT ); Thu, 17 Feb 2011 22:34:05 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 13:34:55 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:34:02 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:34:02 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HLXvM3025373; Thu, 17 Feb 2011 13:33:57 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HLXuZG025372; Thu, 17 Feb 2011 13:33:56 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo , Deng-Cheng Zhu Subject: [PATCH v3 4/4] MIPS: perf: Add support for 64-bit perf counters. Date: Thu, 17 Feb 2011 13:33:39 -0800 Message-Id: <1297978419-25309-5-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> References: <1297978419-25309-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 17 Feb 2011 21:34:02.0676 (UTC) FILETIME=[65432740:01CBCEEA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29218 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The hard coded constants are moved to struct mips_pmu. All counter register access move to the read_counter and write_counter function pointers, which are set to either 32-bit or 64-bit access methods at initialization time. Many of the function pointers in struct mips_pmu were not needed as there was only a single implementation, these were removed. I couldn't figure out what made struct cpu_hw_events.msbs[] at all useful, so I removed it too. Some functions and other declarations were reordered to reduce the need for forward declarations. Signed-off-by: David Daney Cc: Peter Zijlstra Cc: Paul Mackerras Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Deng-Cheng Zhu --- arch/mips/kernel/perf_event_mipsxx.c | 858 +++++++++++++++------------------- 1 files changed, 389 insertions(+), 469 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 409207d..4957973 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -2,6 +2,7 @@ * Linux performance counter support for MIPS. * * Copyright (C) 2010 MIPS Technologies, Inc. + * Copyright (C) 2011 Cavium Networks, Inc. * Author: Deng-Cheng Zhu * * This code is based on the implementation for ARM, which is in turn @@ -26,12 +27,6 @@ #include #include /* For perf_irq */ -/* These are for 32bit counters. For 64bit ones, define them accordingly. */ -#define MAX_PERIOD ((1ULL << 32) - 1) -#define VALID_COUNT 0x7fffffff -#define TOTAL_BITS 32 -#define HIGHEST_BIT 31 - #define MIPS_MAX_HWEVENTS 4 struct cpu_hw_events { @@ -45,15 +40,6 @@ struct cpu_hw_events { unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; /* - * The borrowed MSB for the performance counter. A MIPS performance - * counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit - * counters) as a factor of determining whether a counter overflow - * should be signaled. So here we use a separate MSB for each - * counter to make things easy. - */ - unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; - - /* * Software copy of the control register for each performance counter. * MIPS CPUs vary in performance counters. They use this differently, * and even may not use it. @@ -75,6 +61,7 @@ struct mips_perf_event { unsigned int cntr_mask; #define CNTR_EVEN 0x55555555 #define CNTR_ODD 0xaaaaaaaa + #define CNTR_ALL 0xffffffff #ifdef CONFIG_MIPS_MT_SMP enum { T = 0, @@ -95,18 +82,13 @@ static DEFINE_MUTEX(raw_event_mutex); #define C(x) PERF_COUNT_HW_CACHE_##x struct mips_pmu { + u64 max_period; + u64 valid_count; + u64 overflow; const char *name; int irq; - irqreturn_t (*handle_irq)(int irq, void *dev); - int (*handle_shared_irq)(void); - void (*start)(void); - void (*stop)(void); - int (*alloc_counter)(struct cpu_hw_events *cpuc, - struct hw_perf_event *hwc); u64 (*read_counter)(unsigned int idx); void (*write_counter)(unsigned int idx, u64 val); - void (*enable_event)(struct hw_perf_event *evt, int idx); - void (*disable_event)(int idx); const struct mips_perf_event *(*map_raw_event)(u64 config); const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; const struct mips_perf_event (*cache_event_map) @@ -116,44 +98,302 @@ struct mips_pmu { unsigned int num_counters; }; -static const struct mips_pmu *mipspmu; +static struct mips_pmu mipspmu; + +#define M_CONFIG1_PC (1 << 4) + +#define M_PERFCTL_EXL (1 << 0) +#define M_PERFCTL_KERNEL (1 << 1) +#define M_PERFCTL_SUPERVISOR (1 << 2) +#define M_PERFCTL_USER (1 << 3) +#define M_PERFCTL_INTERRUPT_ENABLE (1 << 4) +#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) +#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) +#define M_PERFCTL_MT_EN(filter) ((filter) << 20) +#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) +#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) +#define M_TC_EN_TC M_PERFCTL_MT_EN(2) +#define M_PERFCTL_TCID(tcid) ((tcid) << 22) +#define M_PERFCTL_WIDE (1 << 30) +#define M_PERFCTL_MORE (1 << 31) + +#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ + M_PERFCTL_KERNEL | \ + M_PERFCTL_USER | \ + M_PERFCTL_SUPERVISOR | \ + M_PERFCTL_INTERRUPT_ENABLE) + +#ifdef CONFIG_MIPS_MT_SMP +#define M_PERFCTL_CONFIG_MASK 0x3fff801f +#else +#define M_PERFCTL_CONFIG_MASK 0x1f +#endif +#define M_PERFCTL_EVENT_MASK 0xfe0 + + +#ifdef CONFIG_MIPS_MT_SMP +static int cpu_has_mipsmt_pertccounters; + +static DEFINE_RWLOCK(pmuint_rwlock); + +/* + * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because + * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. + */ +#if defined(CONFIG_HW_PERF_EVENTS) +#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ + 0 : smp_processor_id()) +#else +#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ + 0 : cpu_data[smp_processor_id()].vpe_id) +#endif + +/* Copied from op_model_mipsxx.c */ +static unsigned int vpe_shift(void) +{ + if (num_possible_cpus() > 1) + return 1; + + return 0; +} + +static unsigned int counters_total_to_per_cpu(unsigned int counters) +{ + return counters >> vpe_shift(); +} + +static unsigned int counters_per_cpu_to_total(unsigned int counters) +{ + return counters << vpe_shift(); +} + +#else /* !CONFIG_MIPS_MT_SMP */ +#define vpe_id() 0 + +#endif /* CONFIG_MIPS_MT_SMP */ + +static void resume_local_counters(void); +static void pause_local_counters(void); +static irqreturn_t mipsxx_pmu_handle_irq(int, void *); +static int mipsxx_pmu_handle_shared_irq(void); + +static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx) +{ + if (vpe_id() == 1) + idx = (idx + 2) & 3; + return idx; +} + +static u64 mipsxx_pmu_read_counter(unsigned int idx) +{ + idx = mipsxx_pmu_swizzle_perf_idx(idx); + + switch (idx) { + case 0: + /* + * The counters are unsigned, we must cast to truncate + * off the high bits. + */ + return (u32)read_c0_perfcntr0(); + case 1: + return (u32)read_c0_perfcntr1(); + case 2: + return (u32)read_c0_perfcntr2(); + case 3: + return (u32)read_c0_perfcntr3(); + default: + WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); + return 0; + } +} + +static u64 mipsxx_pmu_read_counter_64(unsigned int idx) +{ + idx = mipsxx_pmu_swizzle_perf_idx(idx); + + switch (idx) { + case 0: + return read_c0_perfcntr0_64(); + case 1: + return read_c0_perfcntr1_64(); + case 2: + return read_c0_perfcntr2_64(); + case 3: + return read_c0_perfcntr3_64(); + default: + WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); + return 0; + } +} + +static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) +{ + idx = mipsxx_pmu_swizzle_perf_idx(idx); + + switch (idx) { + case 0: + write_c0_perfcntr0(val); + return; + case 1: + write_c0_perfcntr1(val); + return; + case 2: + write_c0_perfcntr2(val); + return; + case 3: + write_c0_perfcntr3(val); + return; + } +} + +static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val) +{ + idx = mipsxx_pmu_swizzle_perf_idx(idx); + + switch (idx) { + case 0: + write_c0_perfcntr0_64(val); + return; + case 1: + write_c0_perfcntr1_64(val); + return; + case 2: + write_c0_perfcntr2_64(val); + return; + case 3: + write_c0_perfcntr3_64(val); + return; + } +} + +static unsigned int mipsxx_pmu_read_control(unsigned int idx) +{ + idx = mipsxx_pmu_swizzle_perf_idx(idx); + + switch (idx) { + case 0: + return read_c0_perfctrl0(); + case 1: + return read_c0_perfctrl1(); + case 2: + return read_c0_perfctrl2(); + case 3: + return read_c0_perfctrl3(); + default: + WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); + return 0; + } +} + +static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) +{ + idx = mipsxx_pmu_swizzle_perf_idx(idx); + + switch (idx) { + case 0: + write_c0_perfctrl0(val); + return; + case 1: + write_c0_perfctrl1(val); + return; + case 2: + write_c0_perfctrl2(val); + return; + case 3: + write_c0_perfctrl3(val); + return; + } +} + +static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, + struct hw_perf_event *hwc) +{ + int i; + + /* + * We only need to care the counter mask. The range has been + * checked definitely. + */ + unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; + + for (i = mipspmu.num_counters - 1; i >= 0; i--) { + /* + * Note that some MIPS perf events can be counted by both + * even and odd counters, wheresas many other are only by + * even _or_ odd counters. This introduces an issue that + * when the former kind of event takes the counter the + * latter kind of event wants to use, then the "counter + * allocation" for the latter event will fail. In fact if + * they can be dynamically swapped, they both feel happy. + * But here we leave this issue alone for now. + */ + if (test_bit(i, &cntr_mask) && + !test_and_set_bit(i, cpuc->used_mask)) + return i; + } + + return -EAGAIN; +} + +static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + + WARN_ON(idx < 0 || idx >= mipspmu.num_counters); + + cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | + (evt->config_base & M_PERFCTL_CONFIG_MASK) | + /* Make sure interrupt enabled. */ + M_PERFCTL_INTERRUPT_ENABLE; + /* + * We do not actually let the counter run. Leave it until start(). + */ +} + +static void mipsxx_pmu_disable_event(int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + WARN_ON(idx < 0 || idx >= mipspmu.num_counters); + + local_irq_save(flags); + cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & + ~M_PERFCTL_COUNT_EVENT_WHENEVER; + mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); + local_irq_restore(flags); +} static int mipspmu_event_set_period(struct perf_event *event, struct hw_perf_event *hwc, int idx) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - s64 left = local64_read(&hwc->period_left); - s64 period = hwc->sample_period; + u64 left = local64_read(&hwc->period_left); + u64 period = hwc->sample_period; int ret = 0; - u64 uleft; - unsigned long flags; - if (unlikely(left <= -period)) { + if (unlikely((left + period) & (1ULL << 63))) { + /* left underflowed by more than period. */ left = period; local64_set(&hwc->period_left, left); hwc->last_period = period; ret = 1; - } - - if (unlikely(left <= 0)) { + } else if (unlikely((left + period) <= period)) { + /* left underflowed by less than period. */ left += period; local64_set(&hwc->period_left, left); hwc->last_period = period; ret = 1; } - if (left > (s64)MAX_PERIOD) - left = MAX_PERIOD; + if (left > mipspmu.max_period) { + left = mipspmu.max_period; + local64_set(&hwc->period_left, left); + } - local64_set(&hwc->prev_count, (u64)-left); + local64_set(&hwc->prev_count, mipspmu.overflow - left); - local_irq_save(flags); - uleft = (u64)(-left) & MAX_PERIOD; - uleft > VALID_COUNT ? - set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs); - mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT); - local_irq_restore(flags); + mipspmu.write_counter(idx, mipspmu.overflow - left); perf_event_update_userpage(event); @@ -164,30 +404,18 @@ static void mipspmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, int idx) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - unsigned long flags; - int shift = 64 - TOTAL_BITS; - s64 prev_raw_count, new_raw_count; + u64 prev_raw_count, new_raw_count; u64 delta; again: prev_raw_count = local64_read(&hwc->prev_count); - local_irq_save(flags); - /* Make the counter value be a "real" one. */ - new_raw_count = mipspmu->read_counter(idx); - if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) { - new_raw_count &= VALID_COUNT; - clear_bit(idx, cpuc->msbs); - } else - new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT); - local_irq_restore(flags); + new_raw_count = mipspmu.read_counter(idx); if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, new_raw_count) != prev_raw_count) goto again; - delta = (new_raw_count << shift) - (prev_raw_count << shift); - delta >>= shift; + delta = new_raw_count - prev_raw_count; local64_add(delta, &event->count); local64_sub(delta, &hwc->period_left); @@ -199,9 +427,6 @@ static void mipspmu_start(struct perf_event *event, int flags) { struct hw_perf_event *hwc = &event->hw; - if (!mipspmu) - return; - if (flags & PERF_EF_RELOAD) WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); @@ -211,19 +436,16 @@ static void mipspmu_start(struct perf_event *event, int flags) mipspmu_event_set_period(event, hwc, hwc->idx); /* Enable the event. */ - mipspmu->enable_event(hwc, hwc->idx); + mipsxx_pmu_enable_event(hwc, hwc->idx); } static void mipspmu_stop(struct perf_event *event, int flags) { struct hw_perf_event *hwc = &event->hw; - if (!mipspmu) - return; - if (!(hwc->state & PERF_HES_STOPPED)) { /* We are working on a local event. */ - mipspmu->disable_event(hwc->idx); + mipsxx_pmu_disable_event(hwc->idx); barrier(); mipspmu_event_update(event, hwc, hwc->idx); hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; @@ -240,7 +462,7 @@ static int mipspmu_add(struct perf_event *event, int flags) perf_pmu_disable(event->pmu); /* To look for a free counter for this event. */ - idx = mipspmu->alloc_counter(cpuc, hwc); + idx = mipsxx_pmu_alloc_counter(cpuc, hwc); if (idx < 0) { err = idx; goto out; @@ -251,7 +473,7 @@ static int mipspmu_add(struct perf_event *event, int flags) * make sure it is disabled. */ event->hw.idx = idx; - mipspmu->disable_event(idx); + mipsxx_pmu_disable_event(idx); cpuc->events[idx] = event; hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; @@ -272,7 +494,7 @@ static void mipspmu_del(struct perf_event *event, int flags) struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; - WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + WARN_ON(idx < 0 || idx >= mipspmu.num_counters); mipspmu_stop(event, PERF_EF_UPDATE); cpuc->events[idx] = NULL; @@ -294,14 +516,29 @@ static void mipspmu_read(struct perf_event *event) static void mipspmu_enable(struct pmu *pmu) { - if (mipspmu) - mipspmu->start(); +#ifdef CONFIG_MIPS_MT_SMP + write_unlock(&pmuint_rwlock); +#endif + resume_local_counters(); } +/* + * MIPS performance counters can be per-TC. The control registers can + * not be directly accessed accross CPUs. Hence if we want to do global + * control, we need cross CPU calls. on_each_cpu() can help us, but we + * can not make sure this function is called with interrupts enabled. So + * here we pause local counters and then grab a rwlock and leave the + * counters on other CPUs alone. If any counter interrupt raises while + * we own the write lock, simply pause local counters on that CPU and + * spin in the handler. Also we know we won't be switched to another + * CPU after pausing local counters and before grabbing the lock. + */ static void mipspmu_disable(struct pmu *pmu) { - if (mipspmu) - mipspmu->stop(); + pause_local_counters(); +#ifdef CONFIG_MIPS_MT_SMP + write_lock(&pmuint_rwlock); +#endif } static atomic_t active_events = ATOMIC_INIT(0); @@ -312,21 +549,21 @@ static int mipspmu_get_irq(void) { int err; - if (mipspmu->irq >= 0) { + if (mipspmu.irq >= 0) { /* Request my own irq handler. */ - err = request_irq(mipspmu->irq, mipspmu->handle_irq, - IRQF_DISABLED | IRQF_NOBALANCING, + err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, + IRQF_PERCPU | IRQF_NOBALANCING, "mips_perf_pmu", NULL); if (err) { pr_warning("Unable to request IRQ%d for MIPS " - "performance counters!\n", mipspmu->irq); + "performance counters!\n", mipspmu.irq); } } else if (cp0_perfcount_irq < 0) { /* * We are sharing the irq number with the timer interrupt. */ save_perf_irq = perf_irq; - perf_irq = mipspmu->handle_shared_irq; + perf_irq = mipsxx_pmu_handle_shared_irq; err = 0; } else { pr_warning("The platform hasn't properly defined its " @@ -339,8 +576,8 @@ static int mipspmu_get_irq(void) static void mipspmu_free_irq(void) { - if (mipspmu->irq >= 0) - free_irq(mipspmu->irq, NULL); + if (mipspmu.irq >= 0) + free_irq(mipspmu.irq, NULL); else if (cp0_perfcount_irq < 0) perf_irq = save_perf_irq; } @@ -361,7 +598,7 @@ static void hw_perf_event_destroy(struct perf_event *event) * disabled. */ on_each_cpu(reset_counters, - (void *)(long)mipspmu->num_counters, 1); + (void *)(long)mipspmu.num_counters, 1); mipspmu_free_irq(); mutex_unlock(&pmu_reserve_mutex); } @@ -381,8 +618,8 @@ static int mipspmu_event_init(struct perf_event *event) return -ENOENT; } - if (!mipspmu || event->cpu >= nr_cpumask_bits || - (event->cpu >= 0 && !cpu_online(event->cpu))) + if (event->cpu >= nr_cpumask_bits || + (event->cpu >= 0 && !cpu_online(event->cpu))) return -ENODEV; if (!atomic_inc_not_zero(&active_events)) { @@ -441,9 +678,9 @@ static const struct mips_perf_event *mipspmu_map_general_event(int idx) { const struct mips_perf_event *pev; - pev = ((*mipspmu->general_event_map)[idx].event_id == + pev = ((*mipspmu.general_event_map)[idx].event_id == UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) : - &(*mipspmu->general_event_map)[idx]); + &(*mipspmu.general_event_map)[idx]); return pev; } @@ -465,7 +702,7 @@ static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) return ERR_PTR(-EINVAL); - pev = &((*mipspmu->cache_event_map) + pev = &((*mipspmu.cache_event_map) [cache_type] [cache_op] [cache_result]); @@ -486,7 +723,7 @@ static int validate_event(struct cpu_hw_events *cpuc, if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) return 1; - return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; + return mipsxx_pmu_alloc_counter(cpuc, &fake_hwc) >= 0; } static int validate_group(struct perf_event *event) @@ -524,123 +761,9 @@ static void handle_associated_event(struct cpu_hw_events *cpuc, return; if (perf_event_overflow(event, 0, data, regs)) - mipspmu->disable_event(idx); + mipsxx_pmu_disable_event(idx); } -#define M_CONFIG1_PC (1 << 4) - -#define M_PERFCTL_EXL (1UL << 0) -#define M_PERFCTL_KERNEL (1UL << 1) -#define M_PERFCTL_SUPERVISOR (1UL << 2) -#define M_PERFCTL_USER (1UL << 3) -#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) -#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) -#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) -#define M_PERFCTL_MT_EN(filter) ((filter) << 20) -#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) -#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) -#define M_TC_EN_TC M_PERFCTL_MT_EN(2) -#define M_PERFCTL_TCID(tcid) ((tcid) << 22) -#define M_PERFCTL_WIDE (1UL << 30) -#define M_PERFCTL_MORE (1UL << 31) - -#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ - M_PERFCTL_KERNEL | \ - M_PERFCTL_USER | \ - M_PERFCTL_SUPERVISOR | \ - M_PERFCTL_INTERRUPT_ENABLE) - -#ifdef CONFIG_MIPS_MT_SMP -#define M_PERFCTL_CONFIG_MASK 0x3fff801f -#else -#define M_PERFCTL_CONFIG_MASK 0x1f -#endif -#define M_PERFCTL_EVENT_MASK 0xfe0 - -#define M_COUNTER_OVERFLOW (1UL << 31) - -#ifdef CONFIG_MIPS_MT_SMP -static int cpu_has_mipsmt_pertccounters; - -/* - * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because - * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. - */ -#if defined(CONFIG_HW_PERF_EVENTS) -#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ - 0 : smp_processor_id()) -#else -#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ - 0 : cpu_data[smp_processor_id()].vpe_id) -#endif - -/* Copied from op_model_mipsxx.c */ -static unsigned int vpe_shift(void) -{ - if (num_possible_cpus() > 1) - return 1; - - return 0; -} - -static unsigned int counters_total_to_per_cpu(unsigned int counters) -{ - return counters >> vpe_shift(); -} - -static unsigned int counters_per_cpu_to_total(unsigned int counters) -{ - return counters << vpe_shift(); -} - -#else /* !CONFIG_MIPS_MT_SMP */ -#define vpe_id() 0 - -#endif /* CONFIG_MIPS_MT_SMP */ - -#define __define_perf_accessors(r, n, np) \ - \ -static unsigned int r_c0_ ## r ## n(void) \ -{ \ - unsigned int cpu = vpe_id(); \ - \ - switch (cpu) { \ - case 0: \ - return read_c0_ ## r ## n(); \ - case 1: \ - return read_c0_ ## r ## np(); \ - default: \ - BUG(); \ - } \ - return 0; \ -} \ - \ -static void w_c0_ ## r ## n(unsigned int value) \ -{ \ - unsigned int cpu = vpe_id(); \ - \ - switch (cpu) { \ - case 0: \ - write_c0_ ## r ## n(value); \ - return; \ - case 1: \ - write_c0_ ## r ## np(value); \ - return; \ - default: \ - BUG(); \ - } \ - return; \ -} \ - -__define_perf_accessors(perfcntr, 0, 2) -__define_perf_accessors(perfcntr, 1, 3) -__define_perf_accessors(perfcntr, 2, 0) -__define_perf_accessors(perfcntr, 3, 1) - -__define_perf_accessors(perfctrl, 0, 2) -__define_perf_accessors(perfctrl, 1, 3) -__define_perf_accessors(perfctrl, 2, 0) -__define_perf_accessors(perfctrl, 3, 1) static int __n_counters(void) { @@ -682,94 +805,20 @@ static void reset_counters(void *arg) int counters = (int)(long)arg; switch (counters) { case 4: - w_c0_perfctrl3(0); - w_c0_perfcntr3(0); - case 3: - w_c0_perfctrl2(0); - w_c0_perfcntr2(0); - case 2: - w_c0_perfctrl1(0); - w_c0_perfcntr1(0); - case 1: - w_c0_perfctrl0(0); - w_c0_perfcntr0(0); - } -} - -static u64 mipsxx_pmu_read_counter(unsigned int idx) -{ - switch (idx) { - case 0: - return r_c0_perfcntr0(); - case 1: - return r_c0_perfcntr1(); - case 2: - return r_c0_perfcntr2(); - case 3: - return r_c0_perfcntr3(); - default: - WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); - return 0; - } -} - -static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) -{ - switch (idx) { - case 0: - w_c0_perfcntr0(val); - return; - case 1: - w_c0_perfcntr1(val); - return; - case 2: - w_c0_perfcntr2(val); - return; + mipsxx_pmu_write_control(3, 0); + mipspmu.write_counter(3, 0); case 3: - w_c0_perfcntr3(val); - return; - } -} - -static unsigned int mipsxx_pmu_read_control(unsigned int idx) -{ - switch (idx) { - case 0: - return r_c0_perfctrl0(); - case 1: - return r_c0_perfctrl1(); + mipsxx_pmu_write_control(2, 0); + mipspmu.write_counter(2, 0); case 2: - return r_c0_perfctrl2(); - case 3: - return r_c0_perfctrl3(); - default: - WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); - return 0; - } -} - -static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) -{ - switch (idx) { - case 0: - w_c0_perfctrl0(val); - return; + mipsxx_pmu_write_control(1, 0); + mipspmu.write_counter(1, 0); case 1: - w_c0_perfctrl1(val); - return; - case 2: - w_c0_perfctrl2(val); - return; - case 3: - w_c0_perfctrl3(val); - return; + mipsxx_pmu_write_control(0, 0); + mipspmu.write_counter(0, 0); } } -#ifdef CONFIG_MIPS_MT_SMP -static DEFINE_RWLOCK(pmuint_rwlock); -#endif - /* 24K/34K/1004K cores can share the same event map. */ static const struct mips_perf_event mipsxxcore_event_map [PERF_COUNT_HW_MAX] = { @@ -1047,7 +1096,7 @@ static int __hw_perf_event_init(struct perf_event *event) } else if (PERF_TYPE_RAW == event->attr.type) { /* We are working on the global raw event. */ mutex_lock(&raw_event_mutex); - pev = mipspmu->map_raw_event(event->attr.config); + pev = mipspmu.map_raw_event(event->attr.config); } else { /* The event type is not (yet) supported. */ return -EOPNOTSUPP; @@ -1092,7 +1141,7 @@ static int __hw_perf_event_init(struct perf_event *event) hwc->config = 0; if (!hwc->sample_period) { - hwc->sample_period = MAX_PERIOD; + hwc->sample_period = mipspmu.max_period; hwc->last_period = hwc->sample_period; local64_set(&hwc->period_left, hwc->sample_period); } @@ -1105,70 +1154,47 @@ static int __hw_perf_event_init(struct perf_event *event) } event->destroy = hw_perf_event_destroy; - return err; } static void pause_local_counters(void) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - int counters = mipspmu->num_counters; + int ctr = mipspmu.num_counters; unsigned long flags; local_irq_save(flags); - switch (counters) { - case 4: - cpuc->saved_ctrl[3] = r_c0_perfctrl3(); - w_c0_perfctrl3(cpuc->saved_ctrl[3] & - ~M_PERFCTL_COUNT_EVENT_WHENEVER); - case 3: - cpuc->saved_ctrl[2] = r_c0_perfctrl2(); - w_c0_perfctrl2(cpuc->saved_ctrl[2] & - ~M_PERFCTL_COUNT_EVENT_WHENEVER); - case 2: - cpuc->saved_ctrl[1] = r_c0_perfctrl1(); - w_c0_perfctrl1(cpuc->saved_ctrl[1] & - ~M_PERFCTL_COUNT_EVENT_WHENEVER); - case 1: - cpuc->saved_ctrl[0] = r_c0_perfctrl0(); - w_c0_perfctrl0(cpuc->saved_ctrl[0] & - ~M_PERFCTL_COUNT_EVENT_WHENEVER); - } + do { + ctr--; + cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr); + mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + } while (ctr > 0); local_irq_restore(flags); } static void resume_local_counters(void) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - int counters = mipspmu->num_counters; - unsigned long flags; + int ctr = mipspmu.num_counters; - local_irq_save(flags); - switch (counters) { - case 4: - w_c0_perfctrl3(cpuc->saved_ctrl[3]); - case 3: - w_c0_perfctrl2(cpuc->saved_ctrl[2]); - case 2: - w_c0_perfctrl1(cpuc->saved_ctrl[1]); - case 1: - w_c0_perfctrl0(cpuc->saved_ctrl[0]); - } - local_irq_restore(flags); + do { + ctr--; + mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); + } while (ctr > 0); } static int mipsxx_pmu_handle_shared_irq(void) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct perf_sample_data data; - unsigned int counters = mipspmu->num_counters; - unsigned int counter; + unsigned int counters = mipspmu.num_counters; + u64 counter; int handled = IRQ_NONE; struct pt_regs *regs; if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) return handled; - /* * First we pause the local counters, so that when we are locked * here, the counters are all paused. When it gets locked due to @@ -1189,13 +1215,9 @@ static int mipsxx_pmu_handle_shared_irq(void) #define HANDLE_COUNTER(n) \ case n + 1: \ if (test_bit(n, cpuc->used_mask)) { \ - counter = r_c0_perfcntr ## n(); \ - if (counter & M_COUNTER_OVERFLOW) { \ - w_c0_perfcntr ## n(counter & \ - VALID_COUNT); \ - if (test_and_change_bit(n, cpuc->msbs)) \ - handle_associated_event(cpuc, \ - n, &data, regs); \ + counter = mipspmu.read_counter(n); \ + if (counter & mipspmu.overflow) { \ + handle_associated_event(cpuc, n, &data, regs); \ handled = IRQ_HANDLED; \ } \ } @@ -1225,95 +1247,6 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) return mipsxx_pmu_handle_shared_irq(); } -static void mipsxx_pmu_start(void) -{ -#ifdef CONFIG_MIPS_MT_SMP - write_unlock(&pmuint_rwlock); -#endif - resume_local_counters(); -} - -/* - * MIPS performance counters can be per-TC. The control registers can - * not be directly accessed accross CPUs. Hence if we want to do global - * control, we need cross CPU calls. on_each_cpu() can help us, but we - * can not make sure this function is called with interrupts enabled. So - * here we pause local counters and then grab a rwlock and leave the - * counters on other CPUs alone. If any counter interrupt raises while - * we own the write lock, simply pause local counters on that CPU and - * spin in the handler. Also we know we won't be switched to another - * CPU after pausing local counters and before grabbing the lock. - */ -static void mipsxx_pmu_stop(void) -{ - pause_local_counters(); -#ifdef CONFIG_MIPS_MT_SMP - write_lock(&pmuint_rwlock); -#endif -} - -static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, - struct hw_perf_event *hwc) -{ - int i; - - /* - * We only need to care the counter mask. The range has been - * checked definitely. - */ - unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; - - for (i = mipspmu->num_counters - 1; i >= 0; i--) { - /* - * Note that some MIPS perf events can be counted by both - * even and odd counters, wheresas many other are only by - * even _or_ odd counters. This introduces an issue that - * when the former kind of event takes the counter the - * latter kind of event wants to use, then the "counter - * allocation" for the latter event will fail. In fact if - * they can be dynamically swapped, they both feel happy. - * But here we leave this issue alone for now. - */ - if (test_bit(i, &cntr_mask) && - !test_and_set_bit(i, cpuc->used_mask)) - return i; - } - - return -EAGAIN; -} - -static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - unsigned long flags; - - WARN_ON(idx < 0 || idx >= mipspmu->num_counters); - - local_irq_save(flags); - cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | - (evt->config_base & M_PERFCTL_CONFIG_MASK) | - /* Make sure interrupt enabled. */ - M_PERFCTL_INTERRUPT_ENABLE; - /* - * We do not actually let the counter run. Leave it until start(). - */ - local_irq_restore(flags); -} - -static void mipsxx_pmu_disable_event(int idx) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - unsigned long flags; - - WARN_ON(idx < 0 || idx >= mipspmu->num_counters); - - local_irq_save(flags); - cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & - ~M_PERFCTL_COUNT_EVENT_WHENEVER; - mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); - local_irq_restore(flags); -} - /* 24K */ #define IS_UNSUPPORTED_24K_EVENT(r, b) \ ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \ @@ -1452,40 +1385,11 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) return &raw_event; } -static struct mips_pmu mipsxxcore_pmu = { - .handle_irq = mipsxx_pmu_handle_irq, - .handle_shared_irq = mipsxx_pmu_handle_shared_irq, - .start = mipsxx_pmu_start, - .stop = mipsxx_pmu_stop, - .alloc_counter = mipsxx_pmu_alloc_counter, - .read_counter = mipsxx_pmu_read_counter, - .write_counter = mipsxx_pmu_write_counter, - .enable_event = mipsxx_pmu_enable_event, - .disable_event = mipsxx_pmu_disable_event, - .map_raw_event = mipsxx_pmu_map_raw_event, - .general_event_map = &mipsxxcore_event_map, - .cache_event_map = &mipsxxcore_cache_map, -}; - -static struct mips_pmu mipsxx74Kcore_pmu = { - .handle_irq = mipsxx_pmu_handle_irq, - .handle_shared_irq = mipsxx_pmu_handle_shared_irq, - .start = mipsxx_pmu_start, - .stop = mipsxx_pmu_stop, - .alloc_counter = mipsxx_pmu_alloc_counter, - .read_counter = mipsxx_pmu_read_counter, - .write_counter = mipsxx_pmu_write_counter, - .enable_event = mipsxx_pmu_enable_event, - .disable_event = mipsxx_pmu_disable_event, - .map_raw_event = mipsxx_pmu_map_raw_event, - .general_event_map = &mipsxx74Kcore_event_map, - .cache_event_map = &mipsxx74Kcore_cache_map, -}; - static int __init init_hw_perf_events(void) { int counters, irq; + int counter_bits; pr_info("Performance counters: "); @@ -1517,32 +1421,28 @@ init_hw_perf_events(void) } #endif - on_each_cpu(reset_counters, (void *)(long)counters, 1); + mipspmu.map_raw_event = mipsxx_pmu_map_raw_event; switch (current_cpu_type()) { case CPU_24K: - mipsxxcore_pmu.name = "mips/24K"; - mipsxxcore_pmu.num_counters = counters; - mipsxxcore_pmu.irq = irq; - mipspmu = &mipsxxcore_pmu; + mipspmu.name = "mips/24K"; + mipspmu.general_event_map = &mipsxxcore_event_map; + mipspmu.cache_event_map = &mipsxxcore_cache_map; break; case CPU_34K: - mipsxxcore_pmu.name = "mips/34K"; - mipsxxcore_pmu.num_counters = counters; - mipsxxcore_pmu.irq = irq; - mipspmu = &mipsxxcore_pmu; + mipspmu.name = "mips/34K"; + mipspmu.general_event_map = &mipsxxcore_event_map; + mipspmu.cache_event_map = &mipsxxcore_cache_map; break; case CPU_74K: - mipsxx74Kcore_pmu.name = "mips/74K"; - mipsxx74Kcore_pmu.num_counters = counters; - mipsxx74Kcore_pmu.irq = irq; - mipspmu = &mipsxx74Kcore_pmu; + mipspmu.name = "mips/74K"; + mipspmu.general_event_map = &mipsxx74Kcore_event_map; + mipspmu.cache_event_map = &mipsxx74Kcore_cache_map; break; case CPU_1004K: - mipsxxcore_pmu.name = "mips/1004K"; - mipsxxcore_pmu.num_counters = counters; - mipsxxcore_pmu.irq = irq; - mipspmu = &mipsxxcore_pmu; + mipspmu.name = "mips/1004K"; + mipspmu.general_event_map = &mipsxxcore_event_map; + mipspmu.cache_event_map = &mipsxxcore_cache_map; break; default: pr_cont("Either hardware does not support performance " @@ -1550,10 +1450,30 @@ init_hw_perf_events(void) return -ENODEV; } - if (mipspmu) - pr_cont("%s PMU enabled, %d counters available to each " - "CPU, irq %d%s\n", mipspmu->name, counters, irq, - irq < 0 ? " (share with timer interrupt)" : ""); + mipspmu.num_counters = counters; + mipspmu.irq = irq; + + if (read_c0_perfctrl0() & M_PERFCTL_WIDE) { + mipspmu.max_period = (1ULL << 63) - 1; + mipspmu.valid_count = (1ULL << 63) - 1; + mipspmu.overflow = 1ULL << 63; + mipspmu.read_counter = mipsxx_pmu_read_counter_64; + mipspmu.write_counter = mipsxx_pmu_write_counter_64; + counter_bits = 64; + } else { + mipspmu.max_period = (1ULL << 31) - 1; + mipspmu.valid_count = (1ULL << 31) - 1; + mipspmu.overflow = 1ULL << 31; + mipspmu.read_counter = mipsxx_pmu_read_counter; + mipspmu.write_counter = mipsxx_pmu_write_counter; + counter_bits = 32; + } + + on_each_cpu(reset_counters, (void *)(long)counters, 1); + + pr_cont("%s PMU enabled, %d %d-bit counters available to each " + "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq, + irq < 0 ? " (share with timer interrupt)" : ""); perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 22:58:02 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 22:58:05 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9329 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491115Ab1BQV6C (ORCPT ); Thu, 17 Feb 2011 22:58:02 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 13:58:52 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:57:59 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 13:57:59 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HLvvnp025771; Thu, 17 Feb 2011 13:57:57 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HLvvjc025770; Thu, 17 Feb 2011 13:57:57 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Chandrakala Chavva , David Daney Subject: [PATCH] MIPS: Octeon: Fix interrupt irq settings for performance counters. Date: Thu, 17 Feb 2011 13:57:52 -0800 Message-Id: <1297979872-25738-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 17 Feb 2011 21:57:59.0869 (UTC) FILETIME=[BDE566D0:01CBCEED] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29219 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips From: Chandrakala Chavva Octeon uses different interrupt irq for timer and performance counters. Set CvmCtl[IPPCI] to correct irq value very early. Signed-off-by: Chandrakala Chavva Signed-off-by: David Daney --- arch/mips/cavium-octeon/setup.c | 7 ------- .../asm/mach-cavium-octeon/kernel-entry-init.h | 5 +++++ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index b0c3686..26e9bb3 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -288,7 +288,6 @@ void octeon_user_io_init(void) union octeon_cvmemctl cvmmemctl; union cvmx_iob_fau_timeout fau_timeout; union cvmx_pow_nw_tim nm_tim; - uint64_t cvmctl; /* Get the current settings for CP0_CVMMEMCTL_REG */ cvmmemctl.u64 = read_c0_cvmmemctl(); @@ -392,12 +391,6 @@ void octeon_user_io_init(void) CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); - /* Move the performance counter interrupts to IRQ 6 */ - cvmctl = read_c0_cvmctl(); - cvmctl &= ~(7 << 7); - cvmctl |= 6 << 7; - write_c0_cvmctl(cvmctl); - /* Set a default for the hardware timeouts */ fau_timeout.u64 = 0; fau_timeout.s.tout_val = 0xfff; diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h index 0b2b5eb..dedef7d 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h @@ -63,6 +63,11 @@ # CN30XX Disable instruction prefetching or v0, v0, 0x2000 skip: + # First clear off CvmCtl[IPPCI] bit and move the performance + # counters interrupt to IRQ 6 + li v1, ~(7 << 7) + and v0, v0, v1 + ori v0, v0, (6 << 7) # Write the cavium control register dmtc0 v0, CP0_CVMCTL_REG sync -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 23:04:47 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 23:04:51 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9497 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491115Ab1BQWEr (ORCPT ); Thu, 17 Feb 2011 23:04:47 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 14:05:31 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:04:39 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:04:39 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HM4aXv025954; Thu, 17 Feb 2011 14:04:36 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HM4aor025952; Thu, 17 Feb 2011 14:04:36 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Octeon: Cleanup Kconfig IRQ_CPU* symbols. Date: Thu, 17 Feb 2011 14:04:33 -0800 Message-Id: <1297980273-25920-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 17 Feb 2011 22:04:39.0269 (UTC) FILETIME=[ABF50150:01CBCEEE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29220 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Octeon doesn't use IRQ_CPU, so don't select it. IRQ_CPU_OCTEON is a completely unused symbol, remove it completely. Signed-off-by: David Daney --- arch/mips/Kconfig | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e89b416..89eff23 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -992,9 +992,6 @@ config IRQ_GT641XX config IRQ_GIC bool -config IRQ_CPU_OCTEON - bool - config MIPS_BOARDS_GEN bool @@ -1354,8 +1351,6 @@ config CPU_SB1 config CPU_CAVIUM_OCTEON bool "Cavium Octeon processor" depends on SYS_HAS_CPU_CAVIUM_OCTEON - select IRQ_CPU - select IRQ_CPU_OCTEON select CPU_HAS_PREFETCH select CPU_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_SMP -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 23:08:40 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 23:08:42 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9593 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491115Ab1BQWIj (ORCPT ); Thu, 17 Feb 2011 23:08:39 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 14:09:29 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:08:36 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:08:35 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HM8V3W026089; Thu, 17 Feb 2011 14:08:32 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HM8Uu3026088; Thu, 17 Feb 2011 14:08:30 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Thomas Gleixner Subject: [PATCH] MIPS: Fix show_interrupts() for CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED. Date: Thu, 17 Feb 2011 14:08:29 -0800 Message-Id: <1297980509-26056-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 17 Feb 2011 22:08:35.0947 (UTC) FILETIME=[390733B0:01CBCEEF] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29221 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips When GENERIC_HARDIRQS_NO_DEPRECATED is selected, the 'chip' field of the irq descriptor is absent. Fix up show_interrupts() to handle this case. Signed-off-by: David Daney Cc: Thomas Gleixner --- arch/mips/kernel/irq.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 4f93db5..10f0b9c 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -99,9 +99,11 @@ int show_interrupts(struct seq_file *p, void *v) } if (i < NR_IRQS) { + struct irq_chip *chip; raw_spin_lock_irqsave(&irq_desc[i].lock, flags); action = irq_desc[i].action; - if (!action) + chip = get_irq_chip(i); + if (!action || !chip) goto skip; seq_printf(p, "%3d: ", i); #ifndef CONFIG_SMP @@ -110,7 +112,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 23:21:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 23:22:00 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9869 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491121Ab1BQWVx (ORCPT ); Thu, 17 Feb 2011 23:21:53 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 14:22:24 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:21:30 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:21:30 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HMLRfp027427; Thu, 17 Feb 2011 14:21:27 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HMLQNo027426; Thu, 17 Feb 2011 14:21:26 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Thomas Gleixner Subject: [PATCH] MIPS: Octeon: Rewrite interrupt handling code. Date: Thu, 17 Feb 2011 14:21:25 -0800 Message-Id: <1297981285-27394-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 17 Feb 2011 22:21:30.0498 (UTC) FILETIME=[06B24E20:01CBCEF1] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29222 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This includes conversion to new style irq_chip functions, and correctly enabling/disabling per-CPU interrupts. The hardware interrupt bit to irq number mapping is now done with a flexible map, instead of by bit twiddling the irq number. Signed-off-by: David Daney Cc: Thomas Gleixner --- This patch depends on these two: http://patchwork.linux-mips.org/patch/2087 http://git.kernel.org/?p=linux/kernel/git/tip/linux-2.6-tip.git;a=commitdiff;h=986c011ddbb3ed44b35e1bfd67f6aa60b293b495 arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/octeon-irq.c | 1392 ++++++++++++++---------- arch/mips/cavium-octeon/setup.c | 12 - arch/mips/cavium-octeon/smp.c | 39 +- arch/mips/include/asm/mach-cavium-octeon/irq.h | 243 ++--- arch/mips/include/asm/octeon/octeon.h | 2 + arch/mips/pci/msi-octeon.c | 20 +- 7 files changed, 927 insertions(+), 782 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 89eff23..e89724e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1358,6 +1358,7 @@ config CPU_CAVIUM_OCTEON select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select GENERIC_HARDIRQS_NO_DEPRECATED help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index ce7500c..b365710 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -3,10 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks + * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks */ -#include + #include +#include +#include +#include #include #include @@ -14,6 +17,53 @@ static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); +static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror); +static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror); + +static __read_mostly u8 octeon_irq_ciu_to_irq[8][64]; + +union octeon_ciu_chip_data { + void *p; + unsigned long l; + struct { + unsigned int line:6; + unsigned int bit:6; + } s; +}; + +struct octeon_core_chip_data { + struct mutex core_irq_mutex; + bool current_en; + bool desired_en; + u8 bit; +}; + +struct octeon_irq_chip { + struct irq_chip chip; + void (*percpu_enable)(struct irq_data *); + void (*percpu_disable)(struct irq_data *); +}; + +#define MIPS_CORE_IRQ_LINES 8 + +static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; + +static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, + struct octeon_irq_chip *octeon_chip, + irq_flow_handler_t handler) +{ + union octeon_ciu_chip_data cd; + + set_irq_chip_and_handler(irq, &octeon_chip->chip, handler); + + cd.l = 0; + cd.s.line = line; + cd.s.bit = bit; + + set_irq_chip_data(irq, cd.p); + octeon_irq_ciu_to_irq[line][bit] = irq; +} + static int octeon_coreid_for_cpu(int cpu) { #ifdef CONFIG_SMP @@ -23,9 +73,20 @@ static int octeon_coreid_for_cpu(int cpu) #endif } -static void octeon_irq_core_ack(unsigned int irq) +static int octeon_cpu_for_coreid(int coreid) +{ +#ifdef CONFIG_SMP + return cpu_number_map(coreid); +#else + return smp_processor_id(); +#endif +} + +static void octeon_irq_core_ack(struct irq_data *data) { - unsigned int bit = irq - OCTEON_IRQ_SW0; + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + unsigned int bit = cd->bit; + /* * We don't need to disable IRQs to make these atomic since * they are already disabled earlier in the low level @@ -37,131 +98,121 @@ static void octeon_irq_core_ack(unsigned int irq) clear_c0_cause(0x100 << bit); } -static void octeon_irq_core_eoi(unsigned int irq) +static void octeon_irq_core_eoi(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - unsigned int bit = irq - OCTEON_IRQ_SW0; - /* - * If an IRQ is being processed while we are disabling it the - * handler will attempt to unmask the interrupt after it has - * been disabled. - */ - if ((unlikely(desc->status & IRQ_DISABLED))) - return; + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + /* * We don't need to disable IRQs to make these atomic since * they are already disabled earlier in the low level * interrupt code. */ - set_c0_status(0x100 << bit); + set_c0_status(0x100 << cd->bit); } -static void octeon_irq_core_enable(unsigned int irq) +static void octeon_irq_core_set_enable_local(void *arg) { - unsigned long flags; - unsigned int bit = irq - OCTEON_IRQ_SW0; + struct irq_data *data = arg; + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + unsigned int mask = 0x100 << cd->bit; /* - * We need to disable interrupts to make sure our updates are - * atomic. + * Interrupts are already disabled, so these are atomic. */ - local_irq_save(flags); - set_c0_status(0x100 << bit); - local_irq_restore(flags); + if (cd->desired_en) + set_c0_status(mask); + else + clear_c0_status(mask); + } -static void octeon_irq_core_disable_local(unsigned int irq) +static void octeon_irq_core_disable(struct irq_data *data) { - unsigned long flags; - unsigned int bit = irq - OCTEON_IRQ_SW0; - /* - * We need to disable interrupts to make sure our updates are - * atomic. - */ - local_irq_save(flags); - clear_c0_status(0x100 << bit); - local_irq_restore(flags); + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + cd->desired_en = false; } -static void octeon_irq_core_disable(unsigned int irq) +static void octeon_irq_core_enable(struct irq_data *data) { -#ifdef CONFIG_SMP - on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local, - (void *) (long) irq, 1); -#else - octeon_irq_core_disable_local(irq); -#endif + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + cd->desired_en = true; } -static struct irq_chip octeon_irq_chip_core = { - .name = "Core", - .enable = octeon_irq_core_enable, - .disable = octeon_irq_core_disable, - .ack = octeon_irq_core_ack, - .eoi = octeon_irq_core_eoi, -}; +static void octeon_irq_core_bus_lock(struct irq_data *data) +{ + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + mutex_lock(&cd->core_irq_mutex); +} -static void octeon_irq_ciu0_ack(unsigned int irq) +static void octeon_irq_core_bus_sync_unlock(struct irq_data *data) { - switch (irq) { - case OCTEON_IRQ_GMX_DRP0: - case OCTEON_IRQ_GMX_DRP1: - case OCTEON_IRQ_IPD_DRP: - case OCTEON_IRQ_KEY_ZERO: - case OCTEON_IRQ_TIMER0: - case OCTEON_IRQ_TIMER1: - case OCTEON_IRQ_TIMER2: - case OCTEON_IRQ_TIMER3: - { - int index = cvmx_get_core_num() * 2; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - /* - * CIU timer type interrupts must be acknoleged by - * writing a '1' bit to their sum0 bit. - */ - cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); - break; - } - default: - break; + struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); + + if (cd->desired_en != cd->current_en) { + on_each_cpu(octeon_irq_core_set_enable_local, data, 1); + + cd->current_en = cd->desired_en; } - /* - * In order to avoid any locking accessing the CIU, we - * acknowledge CIU interrupts by disabling all of them. This - * way we can use a per core register and avoid any out of - * core locking requirements. This has the side affect that - * CIU interrupts can't be processed recursively. - * - * We don't need to disable IRQs to make these atomic since - * they are already disabled earlier in the low level - * interrupt code. - */ - clear_c0_status(0x100 << 2); + mutex_unlock(&cd->core_irq_mutex); } -static void octeon_irq_ciu0_eoi(unsigned int irq) +static struct octeon_irq_chip octeon_irq_chip_core = { + .chip = { + .name = "Core", + .irq_enable = octeon_irq_core_enable, + .irq_disable = octeon_irq_core_disable, + .irq_ack = octeon_irq_core_ack, + .irq_eoi = octeon_irq_core_eoi, + .irq_bus_lock = octeon_irq_core_bus_lock, + .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock, + }, + .percpu_enable = octeon_irq_core_eoi, + .percpu_disable = octeon_irq_core_ack, +}; + +static void __init octeon_irq_init_core(void) { - /* - * Enable all CIU interrupts again. We don't need to disable - * IRQs to make these atomic since they are already disabled - * earlier in the low level interrupt code. - */ - set_c0_status(0x100 << 2); + int i; + int irq; + struct octeon_core_chip_data *cd; + + for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) { + cd = &octeon_irq_core_chip_data[i]; + cd->current_en = false; + cd->desired_en = false; + cd->bit = i; + mutex_init(&cd->core_irq_mutex); + + irq = OCTEON_IRQ_SW0 + i; + switch (irq) { + case OCTEON_IRQ_TIMER: + case OCTEON_IRQ_SW0: + case OCTEON_IRQ_SW1: + case OCTEON_IRQ_5: + case OCTEON_IRQ_PERF: + set_irq_chip_data(irq, cd); + set_irq_chip_and_handler(irq, &octeon_irq_chip_core.chip, + handle_percpu_irq); + break; + default: + break; + } + } } -static int next_coreid_for_irq(struct irq_desc *desc) +static int next_cpu_for_irq(struct irq_data *data) { #ifdef CONFIG_SMP - int coreid; - int weight = cpumask_weight(desc->affinity); + int cpu; + int weight = cpumask_weight(data->affinity); if (weight > 1) { - int cpu = smp_processor_id(); + cpu = smp_processor_id(); for (;;) { - cpu = cpumask_next(cpu, desc->affinity); + cpu = cpumask_next(cpu, data->affinity); if (cpu >= nr_cpu_ids) { cpu = -1; continue; @@ -169,83 +220,175 @@ static int next_coreid_for_irq(struct irq_desc *desc) break; } } - coreid = octeon_coreid_for_cpu(cpu); } else if (weight == 1) { - coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity)); + cpu = cpumask_first(data->affinity); } else { - coreid = cvmx_get_core_num(); + cpu = smp_processor_id(); } - return coreid; + return cpu; #else - return cvmx_get_core_num(); + return smp_processor_id(); #endif } -static void octeon_irq_ciu0_enable(unsigned int irq) +static void octeon_irq_ciu_enable(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - int coreid = next_coreid_for_irq(desc); + int cpu = next_cpu_for_irq(data); + int coreid = octeon_coreid_for_cpu(cpu); + unsigned long *pen; unsigned long flags; - uint64_t en0; - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + union octeon_ciu_chip_data cd; - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + cd.p = irq_data_get_irq_chip_data(data); + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + } } -static void octeon_irq_ciu0_enable_mbox(unsigned int irq) +static void octeon_irq_ciu_enable_local(struct irq_data *data) { - int coreid = cvmx_get_core_num(); + unsigned long *pen; unsigned long flags; - uint64_t en0; - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + } } -static void octeon_irq_ciu0_disable(unsigned int irq) +static void octeon_irq_ciu_disable_local(struct irq_data *data) { - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + unsigned long *pen; unsigned long flags; - uint64_t en0; + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + } +} + +static void octeon_irq_ciu_disable_all(struct irq_data *data) +{ + unsigned long flags; + unsigned long *pen; int cpu; - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); + union octeon_ciu_chip_data cd; + + wmb(); /* Make sure flag changes arrive before register updates. */ + + cd.p = irq_data_get_irq_chip_data(data); + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + } +} + +static void octeon_irq_ciu_enable_all(struct irq_data *data) +{ + unsigned long flags; + unsigned long *pen; + int cpu; + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } /* * Enable the irq on the next core in the affinity set for chips that * have the EN*_W1{S,C} registers. */ -static void octeon_irq_ciu0_enable_v2(unsigned int irq) +static void octeon_irq_ciu_enable_v2(struct irq_data *data) { - int index; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - struct irq_desc *desc = irq_to_desc(irq); + u64 mask; + int cpu = next_cpu_for_irq(data); + union octeon_ciu_chip_data cd; - if ((desc->status & IRQ_DISABLED) == 0) { - index = next_coreid_for_irq(desc) * 2; + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + /* + * Called under the desc lock, so these should never get out + * of sync. + */ + if (cd.s.line == 0) { + int index = octeon_coreid_for_cpu(cpu) * 2; + set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + } else { + int index = octeon_coreid_for_cpu(cpu) * 2 + 1; + set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); } } @@ -253,83 +396,132 @@ static void octeon_irq_ciu0_enable_v2(unsigned int irq) * Enable the irq on the current CPU for chips that * have the EN*_W1{S,C} registers. */ -static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq) +static void octeon_irq_ciu_enable_local_v2(struct irq_data *data) { - int index; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + u64 mask; + union octeon_ciu_chip_data cd; - index = cvmx_get_core_num() * 2; - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + int index = cvmx_get_core_num() * 2; + set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror)); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + } else { + int index = cvmx_get_core_num() * 2 + 1; + set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + } +} + +static void octeon_irq_ciu_disable_local_v2(struct irq_data *data) +{ + u64 mask; + union octeon_ciu_chip_data cd; + + cd.p = irq_data_get_irq_chip_data(data); + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + int index = cvmx_get_core_num() * 2; + clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror)); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + } else { + int index = cvmx_get_core_num() * 2 + 1; + clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + } } /* - * Disable the irq on the current core for chips that have the EN*_W1{S,C} - * registers. + * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq. */ -static void octeon_irq_ciu0_ack_v2(unsigned int irq) -{ - int index = cvmx_get_core_num() * 2; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - - switch (irq) { - case OCTEON_IRQ_GMX_DRP0: - case OCTEON_IRQ_GMX_DRP1: - case OCTEON_IRQ_IPD_DRP: - case OCTEON_IRQ_KEY_ZERO: - case OCTEON_IRQ_TIMER0: - case OCTEON_IRQ_TIMER1: - case OCTEON_IRQ_TIMER2: - case OCTEON_IRQ_TIMER3: - /* - * CIU timer type interrupts must be acknoleged by - * writing a '1' bit to their sum0 bit. - */ +static void octeon_irq_ciu_ack(struct irq_data *data) +{ + u64 mask; + union octeon_ciu_chip_data cd; + + cd.p = data->chip_data; + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + int index = cvmx_get_core_num() * 2; cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); - break; - default: - break; + } else { + cvmx_write_csr(CVMX_CIU_INT_SUM1, mask); } - - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); } /* - * Enable the irq on the current core for chips that have the EN*_W1{S,C} + * Disable the irq on the all cores for chips that have the EN*_W1{S,C} * registers. */ -static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq) +static void octeon_irq_ciu_disable_all_v2(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - int index = cvmx_get_core_num() * 2; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + int cpu; + u64 mask; + union octeon_ciu_chip_data cd; - if (likely((desc->status & IRQ_DISABLED) == 0)) - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + wmb(); /* Make sure flag changes arrive before register updates. */ + + cd.p = data->chip_data; + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + for_each_online_cpu(cpu) { + int index = octeon_coreid_for_cpu(cpu) * 2; + clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + } + } else { + for_each_online_cpu(cpu) { + int index = octeon_coreid_for_cpu(cpu) * 2 + 1; + clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + } + } } /* - * Disable the irq on the all cores for chips that have the EN*_W1{S,C} + * Enable the irq on the all cores for chips that have the EN*_W1{S,C} * registers. */ -static void octeon_irq_ciu0_disable_all_v2(unsigned int irq) +static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) { - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - int index; int cpu; - for_each_online_cpu(cpu) { - index = octeon_coreid_for_cpu(cpu) * 2; - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + u64 mask; + union octeon_ciu_chip_data cd; + + cd.p = data->chip_data; + mask = 1ull << (cd.s.bit); + + if (cd.s.line == 0) { + for_each_online_cpu(cpu) { + int index = octeon_coreid_for_cpu(cpu) * 2; + set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + } + } else { + for_each_online_cpu(cpu) { + int index = octeon_coreid_for_cpu(cpu) * 2 + 1; + set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + } } } #ifdef CONFIG_SMP -static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) +static int octeon_irq_ciu_set_affinity(struct irq_data *data, + const struct cpumask *dest, bool force) { int cpu; - struct irq_desc *desc = irq_to_desc(irq); + struct irq_desc *desc = irq_to_desc(data->irq); int enable_one = (desc->status & IRQ_DISABLED) == 0; unsigned long flags; - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + union octeon_ciu_chip_data cd; + + cd.p = data->chip_data; /* * For non-v2 CIU, we will allow only single CPU affinity. @@ -339,26 +531,40 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * if (cpumask_weight(dest) != 1) return -EINVAL; - raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - uint64_t en0 = - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - en0 |= 1ull << bit; - } else { - en0 &= ~(1ull << bit); + if (desc->status & IRQ_DISABLED) + return 0; + + if (cd.s.line == 0) { + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = 0; + set_bit(cd.s.bit, pen); + } else { + clear_bit(cd.s.bit, pen); + } + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); + } + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); + } else { + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); + for_each_online_cpu(cpu) { + int coreid = octeon_coreid_for_cpu(cpu); + unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = 0; + set_bit(cd.s.bit, pen); + } else { + clear_bit(cd.s.bit, pen); + } + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); } - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); - return 0; } @@ -366,22 +572,47 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * * Set affinity for the irq for chips that have the EN*_W1{S,C} * registers. */ -static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, - const struct cpumask *dest) +static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data, + const struct cpumask *dest, + bool force) { int cpu; - int index; - struct irq_desc *desc = irq_to_desc(irq); + struct irq_desc *desc = irq_to_desc(data->irq); int enable_one = (desc->status & IRQ_DISABLED) == 0; - u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); - - for_each_online_cpu(cpu) { - index = octeon_coreid_for_cpu(cpu) * 2; - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); - } else { - cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + u64 mask; + union octeon_ciu_chip_data cd; + + if (desc->status & IRQ_DISABLED) + return 0; + + cd.p = data->chip_data; + mask = 1ull << cd.s.bit; + + if (cd.s.line == 0) { + for_each_online_cpu(cpu) { + unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); + int index = octeon_coreid_for_cpu(cpu) * 2; + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = 0; + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + } else { + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + } + } + } else { + for_each_online_cpu(cpu) { + unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + int index = octeon_coreid_for_cpu(cpu) * 2 + 1; + if (cpumask_test_cpu(cpu, dest) && enable_one) { + enable_one = 0; + set_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + } else { + clear_bit(cd.s.bit, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + } } } return 0; @@ -389,80 +620,107 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, #endif /* + * The v1 CIU code already masks things, so supply a dummy version to + * the core chip code. + */ +static void octeon_irq_dummy_mask(struct irq_data *data) +{ + return; +} + +/* * Newer octeon chips have support for lockless CIU operation. */ -static struct irq_chip octeon_irq_chip_ciu0_v2 = { - .name = "CIU0", - .enable = octeon_irq_ciu0_enable_v2, - .disable = octeon_irq_ciu0_disable_all_v2, - .eoi = octeon_irq_ciu0_enable_v2, +static struct octeon_irq_chip octeon_irq_chip_ciu_v2 = { + .chip = { + .name = "CIU", + .irq_enable = octeon_irq_ciu_enable_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, #ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu0_set_affinity_v2, + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, #endif + }, }; -static struct irq_chip octeon_irq_chip_ciu0 = { - .name = "CIU0", - .enable = octeon_irq_ciu0_enable, - .disable = octeon_irq_ciu0_disable, - .eoi = octeon_irq_ciu0_eoi, +static struct octeon_irq_chip octeon_irq_chip_ciu_edge_v2 = { + .chip = { + .name = "CIU-E", + .irq_enable = octeon_irq_ciu_enable_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_ack = octeon_irq_ciu_ack, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, #ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu0_set_affinity, + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, #endif + }, }; -/* The mbox versions don't do any affinity or round-robin. */ -static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = { - .name = "CIU0-M", - .enable = octeon_irq_ciu0_enable_mbox_v2, - .disable = octeon_irq_ciu0_disable, - .eoi = octeon_irq_ciu0_eoi_mbox_v2, +static struct octeon_irq_chip octeon_irq_chip_ciu = { + .chip = { + .name = "CIU", + .irq_enable = octeon_irq_ciu_enable, + .irq_disable = octeon_irq_ciu_disable_all, + .irq_mask = octeon_irq_dummy_mask, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, +#endif + }, }; -static struct irq_chip octeon_irq_chip_ciu0_mbox = { - .name = "CIU0-M", - .enable = octeon_irq_ciu0_enable_mbox, - .disable = octeon_irq_ciu0_disable, - .eoi = octeon_irq_ciu0_eoi, +static struct octeon_irq_chip octeon_irq_chip_ciu_edge = { + .chip = { + .name = "CIU-E", + .irq_enable = octeon_irq_ciu_enable, + .irq_disable = octeon_irq_ciu_disable_all, + .irq_mask = octeon_irq_dummy_mask, + .irq_ack = octeon_irq_ciu_ack, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, +#endif + }, }; -static void octeon_irq_ciu1_ack(unsigned int irq) -{ - /* - * In order to avoid any locking accessing the CIU, we - * acknowledge CIU interrupts by disabling all of them. This - * way we can use a per core register and avoid any out of - * core locking requirements. This has the side affect that - * CIU interrupts can't be processed recursively. We don't - * need to disable IRQs to make these atomic since they are - * already disabled earlier in the low level interrupt code. - */ - clear_c0_status(0x100 << 3); -} +/* The mbox versions don't do any affinity or round-robin. */ +static struct octeon_irq_chip octeon_irq_chip_ciu_mbox_v2 = { + .chip = { + .name = "CIU-M", + .irq_enable = octeon_irq_ciu_enable_all_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_ack = octeon_irq_ciu_disable_local_v2, + .irq_eoi = octeon_irq_ciu_enable_local_v2, + }, + .percpu_enable = octeon_irq_ciu_enable_local_v2, + .percpu_disable = octeon_irq_ciu_disable_local_v2, +}; -static void octeon_irq_ciu1_eoi(unsigned int irq) -{ - /* - * Enable all CIU interrupts again. We don't need to disable - * IRQs to make these atomic since they are already disabled - * earlier in the low level interrupt code. - */ - set_c0_status(0x100 << 3); -} +static struct octeon_irq_chip octeon_irq_chip_ciu_mbox = { + .chip = { + .name = "CIU-M", + .irq_enable = octeon_irq_ciu_enable_all, + .irq_disable = octeon_irq_ciu_disable_all, + }, + .percpu_enable = octeon_irq_ciu_enable_local, + .percpu_disable = octeon_irq_ciu_disable_local, +}; -static void octeon_irq_ciu1_enable(unsigned int irq) +/* + * Watchdog interrupts are special. They are associated with a single + * core, so we hardwire the affinity to that core. + */ +static void octeon_irq_ciu_wd_enable(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - int coreid = next_coreid_for_irq(desc); unsigned long flags; - uint64_t en1; - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ + unsigned long *pen; + int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ + int cpu = octeon_cpu_for_coreid(coreid); raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); + pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); + set_bit(coreid, pen); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } @@ -470,286 +728,308 @@ static void octeon_irq_ciu1_enable(unsigned int irq) * Watchdog interrupts are special. They are associated with a single * core, so we hardwire the affinity to that core. */ -static void octeon_irq_ciu1_wd_enable(unsigned int irq) +static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data) { - unsigned long flags; - uint64_t en1; - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - int coreid = bit; + int coreid = data->irq - OCTEON_IRQ_WDOG0; + int cpu = octeon_cpu_for_coreid(coreid); - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid); } -static void octeon_irq_ciu1_disable(unsigned int irq) + +static struct octeon_irq_chip octeon_irq_chip_ciu_wd_v2 = { + .chip = { + .name = "CIU-W", + .irq_enable = octeon_irq_ciu1_wd_enable_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_local_v2, + }, +}; + +static struct octeon_irq_chip octeon_irq_chip_ciu_wd = { + .chip = { + .name = "CIU-W", + .irq_enable = octeon_irq_ciu_wd_enable, + .irq_disable = octeon_irq_ciu_disable_all, + .irq_mask = octeon_irq_dummy_mask, + }, +}; + +static void octeon_irq_ip2_v1(void) { - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - unsigned long flags; - uint64_t en1; - int cpu; - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); + const unsigned long core_id = cvmx_get_core_num(); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); + clear_c0_status(STATUSF_IP2); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[0][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); + set_c0_status(STATUSF_IP2); } -/* - * Enable the irq on the current core for chips that have the EN*_W1{S,C} - * registers. - */ -static void octeon_irq_ciu1_enable_v2(unsigned int irq) +static void octeon_irq_ip2_v2(void) { - int index; - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - struct irq_desc *desc = irq_to_desc(irq); - - if ((desc->status & IRQ_DISABLED) == 0) { - index = next_coreid_for_irq(desc) * 2 + 1; - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + const unsigned long core_id = cvmx_get_core_num(); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[0][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); } } - -/* - * Watchdog interrupts are special. They are associated with a single - * core, so we hardwire the affinity to that core. - */ -static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq) +static void octeon_irq_ip3_v1(void) { - int index; - int coreid = irq - OCTEON_IRQ_WDOG0; - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - struct irq_desc *desc = irq_to_desc(irq); - - if ((desc->status & IRQ_DISABLED) == 0) { - index = coreid * 2 + 1; - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); + clear_c0_status(STATUSF_IP3); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[1][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); } + set_c0_status(STATUSF_IP3); } -/* - * Disable the irq on the current core for chips that have the EN*_W1{S,C} - * registers. - */ -static void octeon_irq_ciu1_ack_v2(unsigned int irq) +static void octeon_irq_ip3_v2(void) { - int index = cvmx_get_core_num() * 2 + 1; - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); + + ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); + if (likely(ciu_sum)) { + int bit = fls64(ciu_sum) - 1; + int irq = octeon_irq_ciu_to_irq[1][bit]; + if (likely(irq)) + do_IRQ(irq); + else + spurious_interrupt(); + } else { + spurious_interrupt(); + } } -/* - * Disable the irq on the all cores for chips that have the EN*_W1{S,C} - * registers. - */ -static void octeon_irq_ciu1_disable_all_v2(unsigned int irq) +static void octeon_irq_ip4_mask(void) { - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - int index; - int cpu; - for_each_online_cpu(cpu) { - index = octeon_coreid_for_cpu(cpu) * 2 + 1; - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); - } + clear_c0_status(STATUSF_IP4); + spurious_interrupt(); } -#ifdef CONFIG_SMP -static int octeon_irq_ciu1_set_affinity(unsigned int irq, - const struct cpumask *dest) +static void (*octeon_irq_ip2)(void); +static void (*octeon_irq_ip3)(void); +static void (*octeon_irq_ip4)(void); + +void __cpuinitdata (*octeon_irq_setup_secondary)(void); + +static void __cpuinit octeon_irq_percpu_enable(void) { - int cpu; - struct irq_desc *desc = irq_to_desc(irq); - int enable_one = (desc->status & IRQ_DISABLED) == 0; + struct irq_desc *desc; + struct irq_data *data; + struct irq_chip *chip; + struct octeon_irq_chip *octeon_chip; unsigned long flags; - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ + int i; - /* - * For non-v2 CIU, we will allow only single CPU affinity. - * This removes the need to do locking in the .ack/.eoi - * functions. - */ - if (cpumask_weight(dest) != 1) - return -EINVAL; + /* Enable the percpu interrupts on this core */ + for (i = OCTEON_IRQ_SW0; i < OCTEON_IRQ_LAST; i++) { + chip = get_irq_chip(i); + if (!chip) + continue; - raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); - for_each_online_cpu(cpu) { - int coreid = octeon_coreid_for_cpu(cpu); - uint64_t en1 = - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - en1 |= 1ull << bit; - } else { - en1 &= ~(1ull << bit); + octeon_chip = container_of(chip, struct octeon_irq_chip, chip); + if (octeon_chip->percpu_enable) { + desc = irq_to_desc(i); + raw_spin_lock_irqsave(&desc->lock, flags); + if ((desc->status & IRQ_DISABLED) == 0) { + data = irq_get_irq_data(i); + octeon_chip->percpu_enable(data); + } + raw_spin_unlock_irqrestore(&desc->lock, flags); } - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); } +} + +static void __cpuinit octeon_irq_init_ciu_percpu(void) +{ + int coreid = cvmx_get_core_num(); /* - * We need to do a read after the last update to make sure all - * of them are done. + * Disable All CIU Interrupts. The ones we need will be + * enabled later. Read the SUM register so we know the write + * completed. */ - cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); - - return 0; + cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); + cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); } -/* - * Set affinity for the irq for chips that have the EN*_W1{S,C} - * registers. - */ -static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq, - const struct cpumask *dest) +static void __cpuinit octeon_irq_setup_secondary_ciu(void) { - int cpu; - int index; - struct irq_desc *desc = irq_to_desc(irq); - int enable_one = (desc->status & IRQ_DISABLED) == 0; - u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); - for_each_online_cpu(cpu) { - index = octeon_coreid_for_cpu(cpu) * 2 + 1; - if (cpumask_test_cpu(cpu, dest) && enable_one) { - enable_one = 0; - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); - } else { - cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); - } - } - return 0; -} -#endif -/* - * Newer octeon chips have support for lockless CIU operation. - */ -static struct irq_chip octeon_irq_chip_ciu1_v2 = { - .name = "CIU1", - .enable = octeon_irq_ciu1_enable_v2, - .disable = octeon_irq_ciu1_disable_all_v2, - .eoi = octeon_irq_ciu1_enable_v2, -#ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu1_set_affinity_v2, -#endif -}; + __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0; + __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0; -static struct irq_chip octeon_irq_chip_ciu1 = { - .name = "CIU1", - .enable = octeon_irq_ciu1_enable, - .disable = octeon_irq_ciu1_disable, - .eoi = octeon_irq_ciu1_eoi, -#ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu1_set_affinity, -#endif -}; + octeon_irq_init_ciu_percpu(); + octeon_irq_percpu_enable(); -static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = { - .name = "CIU1-W", - .enable = octeon_irq_ciu1_wd_enable_v2, - .disable = octeon_irq_ciu1_disable_all_v2, - .eoi = octeon_irq_ciu1_wd_enable_v2, -}; + /* Enable the CIU lines */ + set_c0_status(STATUSF_IP3 | STATUSF_IP2); + clear_c0_status(STATUSF_IP4); +} -static struct irq_chip octeon_irq_chip_ciu1_wd = { - .name = "CIU1-W", - .enable = octeon_irq_ciu1_wd_enable, - .disable = octeon_irq_ciu1_disable, - .eoi = octeon_irq_ciu1_eoi, -}; +static void __init octeon_irq_init_ciu(void) +{ + unsigned int i; + struct octeon_irq_chip *chip; + struct octeon_irq_chip *chip_edge; + struct octeon_irq_chip *chip_mbox; + struct octeon_irq_chip *chip_wd; -static void (*octeon_ciu0_ack)(unsigned int); -static void (*octeon_ciu1_ack)(unsigned int); + octeon_irq_init_ciu_percpu(); + octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; + + if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || + OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || + OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || + OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + octeon_irq_ip2 = octeon_irq_ip2_v2; + octeon_irq_ip3 = octeon_irq_ip3_v2; + chip = &octeon_irq_chip_ciu_v2; + chip_edge = &octeon_irq_chip_ciu_edge_v2; + chip_mbox = &octeon_irq_chip_ciu_mbox_v2; + chip_wd = &octeon_irq_chip_ciu_wd_v2; + } else { + octeon_irq_ip2 = octeon_irq_ip2_v1; + octeon_irq_ip3 = octeon_irq_ip3_v1; + chip = &octeon_irq_chip_ciu; + chip_edge = &octeon_irq_chip_ciu_edge; + chip_mbox = &octeon_irq_chip_ciu_mbox; + chip_wd = &octeon_irq_chip_ciu_wd; + } + octeon_irq_ip4 = octeon_irq_ip4_mask; + + /* Mips internal */ + octeon_irq_init_core(); + + /* CIU_0 */ + for (i = 0; i < 16; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); + for (i = 0; i < 16; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq); + + for (i = 0; i < 4; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); + for (i = 0; i < 4; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq); + + for (i = 0; i < 2; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq); + + for (i = 0; i < 4; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); + + /* CIU_1 */ + for (i = 0; i < 16; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq); + + /* Enable the CIU lines */ + set_c0_status(STATUSF_IP3 | STATUSF_IP2); + clear_c0_status(STATUSF_IP4); +} void __init arch_init_irq(void) { - unsigned int irq; - struct irq_chip *chip0; - struct irq_chip *chip0_mbox; - struct irq_chip *chip1; - struct irq_chip *chip1_wd; - #ifdef CONFIG_SMP /* Set the default affinity to the boot cpu. */ cpumask_clear(irq_default_affinity); cpumask_set_cpu(smp_processor_id(), irq_default_affinity); #endif - - if (NR_IRQS < OCTEON_IRQ_LAST) - pr_err("octeon_irq_init: NR_IRQS is set too low\n"); - - if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || - OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || - OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) { - octeon_ciu0_ack = octeon_irq_ciu0_ack_v2; - octeon_ciu1_ack = octeon_irq_ciu1_ack_v2; - chip0 = &octeon_irq_chip_ciu0_v2; - chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2; - chip1 = &octeon_irq_chip_ciu1_v2; - chip1_wd = &octeon_irq_chip_ciu1_wd_v2; - } else { - octeon_ciu0_ack = octeon_irq_ciu0_ack; - octeon_ciu1_ack = octeon_irq_ciu1_ack; - chip0 = &octeon_irq_chip_ciu0; - chip0_mbox = &octeon_irq_chip_ciu0_mbox; - chip1 = &octeon_irq_chip_ciu1; - chip1_wd = &octeon_irq_chip_ciu1_wd; - } - - /* 0 - 15 reserved for i8259 master and slave controller. */ - - /* 17 - 23 Mips internal */ - for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_core, - handle_percpu_irq); - } - - /* 24 - 87 CIU_INT_SUM0 */ - for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { - switch (irq) { - case OCTEON_IRQ_MBOX0: - case OCTEON_IRQ_MBOX1: - set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq); - break; - default: - set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq); - break; - } - } - - /* 88 - 151 CIU_INT_SUM1 */ - for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++) - set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq); - - for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++) - set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq); - - set_c0_status(0x300 << 2); + octeon_irq_init_ciu(); } asmlinkage void plat_irq_dispatch(void) { - const unsigned long core_id = cvmx_get_core_num(); - const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2); - const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2); - const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1; - const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1); unsigned long cop0_cause; unsigned long cop0_status; - uint64_t ciu_en; - uint64_t ciu_sum; - unsigned int irq; while (1) { cop0_cause = read_c0_cause(); @@ -757,33 +1037,16 @@ asmlinkage void plat_irq_dispatch(void) cop0_cause &= cop0_status; cop0_cause &= ST0_IM; - if (unlikely(cop0_cause & STATUSF_IP2)) { - ciu_sum = cvmx_read_csr(ciu_sum0_address); - ciu_en = cvmx_read_csr(ciu_en0_address); - ciu_sum &= ciu_en; - if (likely(ciu_sum)) { - irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1; - octeon_ciu0_ack(irq); - do_IRQ(irq); - } else { - spurious_interrupt(); - } - } else if (unlikely(cop0_cause & STATUSF_IP3)) { - ciu_sum = cvmx_read_csr(ciu_sum1_address); - ciu_en = cvmx_read_csr(ciu_en1_address); - ciu_sum &= ciu_en; - if (likely(ciu_sum)) { - irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1; - octeon_ciu1_ack(irq); - do_IRQ(irq); - } else { - spurious_interrupt(); - } - } else if (likely(cop0_cause)) { + if (unlikely(cop0_cause & STATUSF_IP2)) + octeon_irq_ip2(); + else if (unlikely(cop0_cause & STATUSF_IP3)) + octeon_irq_ip3(); + else if (unlikely(cop0_cause & STATUSF_IP4)) + octeon_irq_ip4(); + else if (likely(cop0_cause)) do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); - } else { + else break; - } } } @@ -793,60 +1056,46 @@ void fixup_irqs(void) { int irq; struct irq_desc *desc; + struct irq_data *data; + struct irq_chip *chip; + struct octeon_irq_chip *octeon_chip; cpumask_t new_affinity; unsigned long flags; - int do_set_affinity; int cpu; cpu = smp_processor_id(); - for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) - octeon_irq_core_disable_local(irq); - - for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) { + for (irq = OCTEON_IRQ_SW0; irq < OCTEON_IRQ_LAST; irq++) { desc = irq_to_desc(irq); - switch (irq) { - case OCTEON_IRQ_MBOX0: - case OCTEON_IRQ_MBOX1: - /* The eoi function will disable them on this CPU. */ - desc->chip->eoi(irq); - break; - case OCTEON_IRQ_WDOG0: - case OCTEON_IRQ_WDOG1: - case OCTEON_IRQ_WDOG2: - case OCTEON_IRQ_WDOG3: - case OCTEON_IRQ_WDOG4: - case OCTEON_IRQ_WDOG5: - case OCTEON_IRQ_WDOG6: - case OCTEON_IRQ_WDOG7: - case OCTEON_IRQ_WDOG8: - case OCTEON_IRQ_WDOG9: - case OCTEON_IRQ_WDOG10: - case OCTEON_IRQ_WDOG11: - case OCTEON_IRQ_WDOG12: - case OCTEON_IRQ_WDOG13: - case OCTEON_IRQ_WDOG14: - case OCTEON_IRQ_WDOG15: - /* - * These have special per CPU semantics and - * are handled in the watchdog driver. - */ - break; - default: - raw_spin_lock_irqsave(&desc->lock, flags); + if (desc == NULL) + continue; + + raw_spin_lock_irqsave(&desc->lock, flags); + if (desc->status & IRQ_DISABLED) + goto loop_unlock; + + data = irq_get_irq_data(irq); + chip = get_irq_chip(irq); + if (!data || !chip) + goto loop_unlock; + + octeon_chip = container_of(chip, struct octeon_irq_chip, chip); + + if (octeon_chip->percpu_disable) { + octeon_chip->percpu_disable(data); + } else if (chip->irq_set_affinity) { /* - * If this irq has an action, it is in use and - * must be migrated if it has affinity to this - * cpu. + * If this irq is not IRQ_DISABLED, it must be + * migrated if it has affinity to this cpu. */ - if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) { - if (cpumask_weight(desc->affinity) > 1) { + if (desc->action && cpumask_test_cpu(cpu, data->affinity)) { + if (cpumask_weight(data->affinity) > 1) { /* * It has multi CPU affinity, * just remove this CPU from * the affinity set. */ - cpumask_copy(&new_affinity, desc->affinity); + cpumask_copy(&new_affinity, data->affinity); cpumask_clear_cpu(cpu, &new_affinity); } else { /* @@ -856,17 +1105,16 @@ void fixup_irqs(void) cpumask_clear(&new_affinity); cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); } - do_set_affinity = 1; } else { - do_set_affinity = 0; + goto loop_unlock; } raw_spin_unlock_irqrestore(&desc->lock, flags); - if (do_set_affinity) - irq_set_affinity(irq, &new_affinity); - - break; + irq_set_affinity(irq, &new_affinity); + continue; /* Already unlocked */ } +loop_unlock: + raw_spin_unlock_irqrestore(&desc->lock, flags); } } diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 26e9bb3..7f8a522 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -413,7 +413,6 @@ void octeon_user_io_init(void) void __init prom_init(void) { struct cvmx_sysinfo *sysinfo; - const int coreid = cvmx_get_core_num(); int i; int argc; #ifdef CONFIG_CAVIUM_RESERVE32 @@ -530,17 +529,6 @@ void __init prom_init(void) octeon_uart = octeon_get_boot_uart(); - /* - * Disable All CIU Interrupts. The ones we need will be - * enabled later. Read the SUM register so we know the write - * completed. - */ - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); - cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); - #ifdef CONFIG_SMP octeon_write_lcd("LinuxSMP"); #else diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 391cefe..ba78b21 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -171,41 +171,19 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle) * After we've done initial boot, this function is called to allow the * board code to clean up state, if needed */ -static void octeon_init_secondary(void) +static void __cpuinit octeon_init_secondary(void) { - const int coreid = cvmx_get_core_num(); - union cvmx_ciu_intx_sum0 interrupt_enable; unsigned int sr; -#ifdef CONFIG_HOTPLUG_CPU - struct linux_app_boot_info *labi; - - labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); - - if (labi->labi_signature != LABI_SIGNATURE) - panic("The bootloader version on this board is incorrect."); -#endif - sr = set_c0_status(ST0_BEV); write_c0_ebase((u32)ebase); write_c0_status(sr); octeon_check_cpu_bist(); octeon_init_cvmcount(); - /* - pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid); - */ - /* Enable Mailbox interrupts to this core. These are the only - interrupts allowed on line 3 */ - cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff); - interrupt_enable.u64 = 0; - interrupt_enable.s.mbox = 0x3; - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64); - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); - /* Enable core interrupt processing for 2,3 and 7 */ - set_c0_status(0x8c01); + + octeon_irq_setup_secondary(); + raw_local_irq_enable(); } /** @@ -214,6 +192,15 @@ static void octeon_init_secondary(void) */ void octeon_prepare_cpus(unsigned int max_cpus) { +#ifdef CONFIG_HOTPLUG_CPU + struct linux_app_boot_info *labi; + + labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); + + if (labi->labi_signature != LABI_SIGNATURE) + panic("The bootloader version on this board is incorrect."); +#endif + cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, "mailbox0", mailbox_interrupt)) { diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 6ddab8a..5b05f18 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -11,172 +11,91 @@ #define NR_IRQS OCTEON_IRQ_LAST #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 -/* 0 - 7 represent the i8259 master */ -#define OCTEON_IRQ_I8259M0 0 -#define OCTEON_IRQ_I8259M1 1 -#define OCTEON_IRQ_I8259M2 2 -#define OCTEON_IRQ_I8259M3 3 -#define OCTEON_IRQ_I8259M4 4 -#define OCTEON_IRQ_I8259M5 5 -#define OCTEON_IRQ_I8259M6 6 -#define OCTEON_IRQ_I8259M7 7 -/* 8 - 15 represent the i8259 slave */ -#define OCTEON_IRQ_I8259S0 8 -#define OCTEON_IRQ_I8259S1 9 -#define OCTEON_IRQ_I8259S2 10 -#define OCTEON_IRQ_I8259S3 11 -#define OCTEON_IRQ_I8259S4 12 -#define OCTEON_IRQ_I8259S5 13 -#define OCTEON_IRQ_I8259S6 14 -#define OCTEON_IRQ_I8259S7 15 -/* 16 - 23 represent the 8 MIPS standard interrupt sources */ -#define OCTEON_IRQ_SW0 16 -#define OCTEON_IRQ_SW1 17 -#define OCTEON_IRQ_CIU0 18 -#define OCTEON_IRQ_CIU1 19 -#define OCTEON_IRQ_CIU4 20 -#define OCTEON_IRQ_5 21 -#define OCTEON_IRQ_PERF 22 -#define OCTEON_IRQ_TIMER 23 -/* 24 - 87 represent the sources in CIU_INTX_EN0 */ -#define OCTEON_IRQ_WORKQ0 24 -#define OCTEON_IRQ_WORKQ1 25 -#define OCTEON_IRQ_WORKQ2 26 -#define OCTEON_IRQ_WORKQ3 27 -#define OCTEON_IRQ_WORKQ4 28 -#define OCTEON_IRQ_WORKQ5 29 -#define OCTEON_IRQ_WORKQ6 30 -#define OCTEON_IRQ_WORKQ7 31 -#define OCTEON_IRQ_WORKQ8 32 -#define OCTEON_IRQ_WORKQ9 33 -#define OCTEON_IRQ_WORKQ10 34 -#define OCTEON_IRQ_WORKQ11 35 -#define OCTEON_IRQ_WORKQ12 36 -#define OCTEON_IRQ_WORKQ13 37 -#define OCTEON_IRQ_WORKQ14 38 -#define OCTEON_IRQ_WORKQ15 39 -#define OCTEON_IRQ_GPIO0 40 -#define OCTEON_IRQ_GPIO1 41 -#define OCTEON_IRQ_GPIO2 42 -#define OCTEON_IRQ_GPIO3 43 -#define OCTEON_IRQ_GPIO4 44 -#define OCTEON_IRQ_GPIO5 45 -#define OCTEON_IRQ_GPIO6 46 -#define OCTEON_IRQ_GPIO7 47 -#define OCTEON_IRQ_GPIO8 48 -#define OCTEON_IRQ_GPIO9 49 -#define OCTEON_IRQ_GPIO10 50 -#define OCTEON_IRQ_GPIO11 51 -#define OCTEON_IRQ_GPIO12 52 -#define OCTEON_IRQ_GPIO13 53 -#define OCTEON_IRQ_GPIO14 54 -#define OCTEON_IRQ_GPIO15 55 -#define OCTEON_IRQ_MBOX0 56 -#define OCTEON_IRQ_MBOX1 57 -#define OCTEON_IRQ_UART0 58 -#define OCTEON_IRQ_UART1 59 -#define OCTEON_IRQ_PCI_INT0 60 -#define OCTEON_IRQ_PCI_INT1 61 -#define OCTEON_IRQ_PCI_INT2 62 -#define OCTEON_IRQ_PCI_INT3 63 -#define OCTEON_IRQ_PCI_MSI0 64 -#define OCTEON_IRQ_PCI_MSI1 65 -#define OCTEON_IRQ_PCI_MSI2 66 -#define OCTEON_IRQ_PCI_MSI3 67 -#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ -#define OCTEON_IRQ_TWSI 69 -#define OCTEON_IRQ_RML 70 -#define OCTEON_IRQ_TRACE 71 -#define OCTEON_IRQ_GMX_DRP0 72 -#define OCTEON_IRQ_GMX_DRP1 73 -#define OCTEON_IRQ_IPD_DRP 74 -#define OCTEON_IRQ_KEY_ZERO 75 -#define OCTEON_IRQ_TIMER0 76 -#define OCTEON_IRQ_TIMER1 77 -#define OCTEON_IRQ_TIMER2 78 -#define OCTEON_IRQ_TIMER3 79 -#define OCTEON_IRQ_USB0 80 -#define OCTEON_IRQ_PCM 81 -#define OCTEON_IRQ_MPI 82 -#define OCTEON_IRQ_TWSI2 83 -#define OCTEON_IRQ_POWIQ 84 -#define OCTEON_IRQ_IPDPPTHR 85 -#define OCTEON_IRQ_MII0 86 -#define OCTEON_IRQ_BOOTDMA 87 -/* 88 - 151 represent the sources in CIU_INTX_EN1 */ -#define OCTEON_IRQ_WDOG0 88 -#define OCTEON_IRQ_WDOG1 89 -#define OCTEON_IRQ_WDOG2 90 -#define OCTEON_IRQ_WDOG3 91 -#define OCTEON_IRQ_WDOG4 92 -#define OCTEON_IRQ_WDOG5 93 -#define OCTEON_IRQ_WDOG6 94 -#define OCTEON_IRQ_WDOG7 95 -#define OCTEON_IRQ_WDOG8 96 -#define OCTEON_IRQ_WDOG9 97 -#define OCTEON_IRQ_WDOG10 98 -#define OCTEON_IRQ_WDOG11 99 -#define OCTEON_IRQ_WDOG12 100 -#define OCTEON_IRQ_WDOG13 101 -#define OCTEON_IRQ_WDOG14 102 -#define OCTEON_IRQ_WDOG15 103 -#define OCTEON_IRQ_UART2 104 -#define OCTEON_IRQ_USB1 105 -#define OCTEON_IRQ_MII1 106 -#define OCTEON_IRQ_RESERVED107 107 -#define OCTEON_IRQ_RESERVED108 108 -#define OCTEON_IRQ_RESERVED109 109 -#define OCTEON_IRQ_RESERVED110 110 -#define OCTEON_IRQ_RESERVED111 111 -#define OCTEON_IRQ_RESERVED112 112 -#define OCTEON_IRQ_RESERVED113 113 -#define OCTEON_IRQ_RESERVED114 114 -#define OCTEON_IRQ_RESERVED115 115 -#define OCTEON_IRQ_RESERVED116 116 -#define OCTEON_IRQ_RESERVED117 117 -#define OCTEON_IRQ_RESERVED118 118 -#define OCTEON_IRQ_RESERVED119 119 -#define OCTEON_IRQ_RESERVED120 120 -#define OCTEON_IRQ_RESERVED121 121 -#define OCTEON_IRQ_RESERVED122 122 -#define OCTEON_IRQ_RESERVED123 123 -#define OCTEON_IRQ_RESERVED124 124 -#define OCTEON_IRQ_RESERVED125 125 -#define OCTEON_IRQ_RESERVED126 126 -#define OCTEON_IRQ_RESERVED127 127 -#define OCTEON_IRQ_RESERVED128 128 -#define OCTEON_IRQ_RESERVED129 129 -#define OCTEON_IRQ_RESERVED130 130 -#define OCTEON_IRQ_RESERVED131 131 -#define OCTEON_IRQ_RESERVED132 132 -#define OCTEON_IRQ_RESERVED133 133 -#define OCTEON_IRQ_RESERVED134 134 -#define OCTEON_IRQ_RESERVED135 135 -#define OCTEON_IRQ_RESERVED136 136 -#define OCTEON_IRQ_RESERVED137 137 -#define OCTEON_IRQ_RESERVED138 138 -#define OCTEON_IRQ_RESERVED139 139 -#define OCTEON_IRQ_RESERVED140 140 -#define OCTEON_IRQ_RESERVED141 141 -#define OCTEON_IRQ_RESERVED142 142 -#define OCTEON_IRQ_RESERVED143 143 -#define OCTEON_IRQ_RESERVED144 144 -#define OCTEON_IRQ_RESERVED145 145 -#define OCTEON_IRQ_RESERVED146 146 -#define OCTEON_IRQ_RESERVED147 147 -#define OCTEON_IRQ_RESERVED148 148 -#define OCTEON_IRQ_RESERVED149 149 -#define OCTEON_IRQ_RESERVED150 150 -#define OCTEON_IRQ_RESERVED151 151 +enum octeon_irq { +/* 1 - 8 represent the 8 MIPS standard interrupt sources */ + OCTEON_IRQ_SW0 = 1, + OCTEON_IRQ_SW1, +/* CIU0, CUI2, CIU4 are 3, 4, 5 */ + OCTEON_IRQ_5 = 6, + OCTEON_IRQ_PERF, + OCTEON_IRQ_TIMER, +/* sources in CIU_INTX_EN0 */ + OCTEON_IRQ_WORKQ0, + OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16, + OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16, + OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, + OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, + OCTEON_IRQ_MBOX1, + OCTEON_IRQ_UART0, + OCTEON_IRQ_UART1, + OCTEON_IRQ_UART2, + OCTEON_IRQ_PCI_INT0, + OCTEON_IRQ_PCI_INT1, + OCTEON_IRQ_PCI_INT2, + OCTEON_IRQ_PCI_INT3, + OCTEON_IRQ_PCI_MSI0, + OCTEON_IRQ_PCI_MSI1, + OCTEON_IRQ_PCI_MSI2, + OCTEON_IRQ_PCI_MSI3, + + OCTEON_IRQ_TWSI, + OCTEON_IRQ_TWSI2, + OCTEON_IRQ_RML, + OCTEON_IRQ_TRACE0, + OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4, + OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5, + OCTEON_IRQ_KEY_ZERO, + OCTEON_IRQ_TIMER0, + OCTEON_IRQ_TIMER1, + OCTEON_IRQ_TIMER2, + OCTEON_IRQ_TIMER3, + OCTEON_IRQ_USB0, + OCTEON_IRQ_USB1, + OCTEON_IRQ_PCM, + OCTEON_IRQ_MPI, + OCTEON_IRQ_POWIQ, + OCTEON_IRQ_IPDPPTHR, + OCTEON_IRQ_MII0, + OCTEON_IRQ_MII1, + OCTEON_IRQ_BOOTDMA, + + OCTEON_IRQ_NAND, + OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */ + OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */ + OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */ + OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */ + OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */ + OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */ + OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */ + OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */ + OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */ + OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */ + OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */ + OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */ + OCTEON_IRQ_DFA, /* Summary of DFA */ + OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */ + OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */ + OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */ + OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */ + OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5, + OCTEON_IRQ_PTP, + OCTEON_IRQ_PEM0, + OCTEON_IRQ_PEM1, + OCTEON_IRQ_SRIO0, + OCTEON_IRQ_SRIO1, + OCTEON_IRQ_LMC0, + OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */ + OCTEON_IRQ_RST, +}; #ifdef CONFIG_PCI_MSI -/* 152 - 215 represent the MSI interrupts 0-63 */ -#define OCTEON_IRQ_MSI_BIT0 152 -#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) +/* 152 - 407 represent the MSI interrupts 0-255 */ +#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1) -#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) +#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) +#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) #else -#define OCTEON_IRQ_LAST 152 +#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1) #endif #endif diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index 6b34afd0..f72f768 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -257,4 +257,6 @@ extern struct cvmx_bootinfo *octeon_bootinfo; extern uint64_t octeon_bootloader_entry_addr; +extern void (*octeon_irq_setup_secondary)(void); + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index d808049..eebaf56 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -259,11 +259,11 @@ static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); static u64 msi_rcv_reg[4]; static u64 mis_ena_reg[4]; -static void octeon_irq_msi_enable_pcie(unsigned int irq) +static void octeon_irq_msi_enable_pcie(struct irq_data *data) { u64 en; unsigned long flags; - int msi_number = irq - OCTEON_IRQ_MSI_BIT0; + int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; int irq_index = msi_number >> 6; int irq_bit = msi_number & 0x3f; @@ -275,11 +275,11 @@ static void octeon_irq_msi_enable_pcie(unsigned int irq) raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); } -static void octeon_irq_msi_disable_pcie(unsigned int irq) +static void octeon_irq_msi_disable_pcie(struct irq_data *data) { u64 en; unsigned long flags; - int msi_number = irq - OCTEON_IRQ_MSI_BIT0; + int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; int irq_index = msi_number >> 6; int irq_bit = msi_number & 0x3f; @@ -293,11 +293,11 @@ static void octeon_irq_msi_disable_pcie(unsigned int irq) static struct irq_chip octeon_irq_chip_msi_pcie = { .name = "MSI", - .enable = octeon_irq_msi_enable_pcie, - .disable = octeon_irq_msi_disable_pcie, + .irq_enable = octeon_irq_msi_enable_pcie, + .irq_disable = octeon_irq_msi_disable_pcie, }; -static void octeon_irq_msi_enable_pci(unsigned int irq) +static void octeon_irq_msi_enable_pci(struct irq_data *data) { /* * Octeon PCI doesn't have the ability to mask/unmask MSI @@ -308,15 +308,15 @@ static void octeon_irq_msi_enable_pci(unsigned int irq) */ } -static void octeon_irq_msi_disable_pci(unsigned int irq) +static void octeon_irq_msi_disable_pci(struct irq_data *data) { /* See comment in enable */ } static struct irq_chip octeon_irq_chip_msi_pci = { .name = "MSI", - .enable = octeon_irq_msi_enable_pci, - .disable = octeon_irq_msi_disable_pci, + .irq_enable = octeon_irq_msi_enable_pci, + .irq_disable = octeon_irq_msi_disable_pci, }; /* -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 23:42:17 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 23:42:21 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10439 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491121Ab1BQWmR (ORCPT ); Thu, 17 Feb 2011 23:42:17 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 14:42:53 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:42:01 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:42:01 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HMfuOC004999; Thu, 17 Feb 2011 14:41:57 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HMfrQ2004998; Thu, 17 Feb 2011 14:41:53 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo , Deng-Cheng Zhu Subject: [PATCH] MIPS: perf: Add Octeon support for hardware perf. Date: Thu, 17 Feb 2011 14:41:51 -0800 Message-Id: <1297982511-4957-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 17 Feb 2011 22:42:01.0217 (UTC) FILETIME=[E4431F10:01CBCEF3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29223 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Enable hardware counters for Octeon, and add the corresponding event mappings. Signed-off-by: David Daney Cc: Peter Zijlstra Cc: Paul Mackerras Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Deng-Cheng Zhu --- arch/mips/Kconfig | 2 +- arch/mips/kernel/perf_event_mipsxx.c | 147 ++++++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e89724e..13ed8ba 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2032,7 +2032,7 @@ config NODES_SHIFT config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1) + depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON) default y help Enable hardware performance counter support for perf events. If diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 4957973..2d89198 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -843,6 +843,16 @@ static const struct mips_perf_event mipsxx74Kcore_event_map [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, }; +static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, + [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL }, + [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL }, + [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL }, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL }, + [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL }, + [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, +}; + /* 24K/34K/1004K cores can share the same cache event map. */ static const struct mips_perf_event mipsxxcore_cache_map [PERF_COUNT_HW_CACHE_MAX] @@ -1048,6 +1058,102 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map }, }; + +static const struct mips_perf_event octeon_cache_map + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { +[C(L1D)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL }, + [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(DTLB)] = { + /* + * Only general DTLB misses are counted use the same event for + * read and write. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(BPU)] = { + /* Using the same code for *HW_BRANCH* */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +}; + #ifdef CONFIG_MIPS_MT_SMP static void check_and_calc_range(struct perf_event *event, const struct mips_perf_event *pev) @@ -1385,6 +1491,39 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) return &raw_event; } +static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) +{ + unsigned int raw_id = config & 0xff; + unsigned int base_id = raw_id & 0x7f; + + + raw_event.cntr_mask = CNTR_ALL; + raw_event.event_id = base_id; + + if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { + if (base_id > 0x42) + return ERR_PTR(-EOPNOTSUPP); + } else { + if (base_id > 0x3a) + return ERR_PTR(-EOPNOTSUPP); + } + + switch (base_id) { + case 0x00: + case 0x0f: + case 0x1e: + case 0x1f: + case 0x2f: + case 0x34: + case 0x3b ... 0x3f: + return ERR_PTR(-EOPNOTSUPP); + default: + break; + } + + return &raw_event; +} + static int __init init_hw_perf_events(void) { @@ -1444,6 +1583,14 @@ init_hw_perf_events(void) mipspmu.general_event_map = &mipsxxcore_event_map; mipspmu.cache_event_map = &mipsxxcore_cache_map; break; + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + mipspmu.name = "octeon"; + mipspmu.general_event_map = &octeon_event_map; + mipspmu.cache_event_map = &octeon_cache_map; + mipspmu.map_raw_event = octeon_pmu_map_raw_event; + break; default: pr_cont("Either hardware does not support performance " "counters, or not yet implemented.\n"); -- 1.7.2.3 From David.Daney@caviumnetworks.com Thu Feb 17 23:48:05 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 17 Feb 2011 23:48:08 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10596 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491126Ab1BQWsF (ORCPT ); Thu, 17 Feb 2011 23:48:05 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 14:48:50 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:47:58 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 14:47:58 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1HMlt6H005166; Thu, 17 Feb 2011 14:47:55 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1HMls5A005165; Thu, 17 Feb 2011 14:47:54 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Octeon: Don't request interrupts for unused IPI mailbox bits. Date: Thu, 17 Feb 2011 14:47:52 -0800 Message-Id: <1297982872-5124-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 17 Feb 2011 22:47:58.0367 (UTC) FILETIME=[B923E2F0:01CBCEF4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29224 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips We only use the three low-order mailbox bits. Leave the upper bits alone for possible use by drivers and other software. Signed-off-by: David Daney --- arch/mips/cavium-octeon/smp.c | 15 +++++++-------- 1 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index ba78b21..716fae6 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -37,7 +37,7 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id) uint64_t action; /* Load the mailbox register to figure out what we're supposed to do */ - action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)); + action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff; /* Clear the mailbox to clear the interrupt */ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action); @@ -200,16 +200,15 @@ void octeon_prepare_cpus(unsigned int max_cpus) if (labi->labi_signature != LABI_SIGNATURE) panic("The bootloader version on this board is incorrect."); #endif - - cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); + /* + * Only the low order mailbox bits are used for IPIs, leave + * the other bits alone. + */ + cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, - "mailbox0", mailbox_interrupt)) { + "SMP-IPI", mailbox_interrupt)) { panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); } - if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED, - "mailbox1", mailbox_interrupt)) { - panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); - } } /** -- 1.7.2.3 From David.Daney@caviumnetworks.com Fri Feb 18 02:02:52 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Feb 2011 02:02:55 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13882 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491116Ab1BRBCw (ORCPT ); Fri, 18 Feb 2011 02:02:52 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 17:03:41 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 17:02:48 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 17:02:48 -0800 Message-ID: <4D5DC538.1090606@caviumnetworks.com> Date: Thu, 17 Feb 2011 17:02:48 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: linux-mips CC: GCC , binutils , Prasun Kapoor Subject: Re: RFC: A new MIPS64 ABI References: <4D5990A4.2050308@caviumnetworks.com> In-Reply-To: <4D5990A4.2050308@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 18 Feb 2011 01:02:48.0891 (UTC) FILETIME=[8F77E0B0:01CBCF07] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29225 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/14/2011 12:29 PM, David Daney wrote: > Background: > > Current MIPS 32-bit ABIs (both o32 and n32) are restricted to 2GB of > user virtual memory space. This is due the way MIPS32 memory space is > segmented. Only the range from 0..2^31-1 is available. Pointer > values are always sign extended. > > Because there are not already enough MIPS ABIs, I present the ... > > Proposal: A new ABI to support 4GB of address space with 32-bit > pointers. > > The proposed new ABI would only be available on MIPS64 platforms. It > would be identical to the current MIPS n32 ABI *except* that pointers > would be zero-extended rather than sign-extended when resident in > registers. In the remainder of this document I will call it > 'n32-big'. As a result, applications would have access to a full 4GB > of virtual address space. The operating environment would be > configured such that the entire lower 4GB of the virtual address space > was available to the program. > > > At a low level here is how it would work: > > 1) Load a pointer to a register from memory: > > n32: > LW $reg, offset($reg) > > n32-big: > LWU $reg, offset($reg) > > 2) Load an address constant into a register: > > n32: > LUI $reg, high_part > ORI $reg, low_part That is not reality. Really it is: LUI $reg, R_MIPS_HI16 ADDIU $reg, R_MIPS_LO16 > > n32-big: > ORI $reg, high_part > DSLL $reg, $reg, 16 > ORI $reg, low_part > This one would really be: ORI $reg, R_MIPS_HI16 DSLL $reg, $reg, 16 ADDIU $reg, R_MIPS_LO16 > > Q: What would have to change to make this work? > > o A new ELF header flag to denote the ABI. > > o Linker support to use proper library search paths, and linker scrips > to set the INTERP program header, etc. > > o GCC has to emit code for the new ABI. > > o Could all existing n32 relocation types be used? I think so. > > o Runtime libraries would have to be placed in a new location > (/lib32big, /usr/lib32big ...) > > o The C library's ld.so would have to use a distinct LD_LIBRARY_PATH > for n32-big code. > > o What would the Linux system call interface be? I would propose > using the existing Linux n32 system call interface. Most system > calls would just work. Some, that pass pointers in in-memory > structures, might require kernel modifications (sigaction() for > example). > From David.Daney@caviumnetworks.com Fri Feb 18 02:52:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Feb 2011 02:52:31 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14818 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491120Ab1BRBw2 (ORCPT ); Fri, 18 Feb 2011 02:52:28 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 17:53:17 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 17:52:24 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 17:52:24 -0800 Message-ID: <4D5DD0D8.4030104@caviumnetworks.com> Date: Thu, 17 Feb 2011 17:52:24 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: ralf@linux-mips.org CC: linux-mips@linux-mips.org, Antony Pavlov Subject: Re: [PATCH] MIPS: Only include arch/mips/cavium-octeon/Kconfig if CPU_CAVIUM_OCTEON References: <1297965723-26059-1-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1297965723-26059-1-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 18 Feb 2011 01:52:24.0535 (UTC) FILETIME=[7D171E70:01CBCF0E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29226 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/17/2011 10:02 AM, David Daney wrote: > Instead of making each Octeon specific option depend on > CPU_CAVIUM_OCTEON, just quit including cavium-octeon/Kconfig if it is > not applicable. > > Signed-off-by: David Daney > Cc: Antony Pavlov > --- > arch/mips/Kconfig | 4 ++++ > arch/mips/cavium-octeon/Kconfig | 3 --- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index bd7b64d..b0a1cb3 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -748,7 +748,11 @@ source "arch/mips/sgi-ip27/Kconfig" > source "arch/mips/sibyte/Kconfig" > source "arch/mips/txx9/Kconfig" > source "arch/mips/vr41xx/Kconfig" > + > +if CPU_CAVIUM_OCTEON > source "arch/mips/cavium-octeon/Kconfig" > +endif > + Ralf pointed out that nobody else has the IFs here. I will create a new patch that moves them into arch/mips/cavium-octeon/Kconfig David Daney > source "arch/mips/loongson/Kconfig" > > endmenu > diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig > index caae228..3dab0ec 100644 > --- a/arch/mips/cavium-octeon/Kconfig > +++ b/arch/mips/cavium-octeon/Kconfig > @@ -1,6 +1,5 @@ > config CAVIUM_OCTEON_SPECIFIC_OPTIONS > bool "Enable Octeon specific options" > - depends on CPU_CAVIUM_OCTEON > default "y" > > config CAVIUM_CN63XXP1 > @@ -93,7 +92,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY > config ARCH_SPARSEMEM_ENABLE > def_bool y > select SPARSEMEM_STATIC > - depends on CPU_CAVIUM_OCTEON > > config CAVIUM_OCTEON_HELPER > def_bool y > @@ -107,6 +105,5 @@ config NEED_SG_DMA_LENGTH > > config SWIOTLB > def_bool y > - depends on CPU_CAVIUM_OCTEON > select IOMMU_HELPER > select NEED_SG_DMA_LENGTH From David.Daney@caviumnetworks.com Fri Feb 18 03:23:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Feb 2011 03:23:48 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15390 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491120Ab1BRCXn (ORCPT ); Fri, 18 Feb 2011 03:23:43 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 17 Feb 2011 18:24:31 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 18:23:39 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 17 Feb 2011 18:23:39 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1I2NZgP004039; Thu, 17 Feb 2011 18:23:35 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1I2NYIK004038; Thu, 17 Feb 2011 18:23:34 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Octeon: Guard the body of arch/mips/cavium-octeon/Kconfig with CPU_CAVIUM_OCTEON Date: Thu, 17 Feb 2011 18:23:32 -0800 Message-Id: <1297995812-4006-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 18 Feb 2011 02:23:39.0114 (UTC) FILETIME=[DA6D2CA0:01CBCF12] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29227 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Instead of making each Octeon specific option depend on CPU_CAVIUM_OCTEON, gate the body of the entire file with CPU_CAVIUM_OCTEON. With this change, CAVIUM_OCTEON_SPECIFIC_OPTIONS becomes useless, so get rid of it as well. Signed-off-by: David Daney --- This patch replaces: http://patchwork.linux-mips.org/patch/2080 And should be applied before http://patchwork.linux-mips.org/patch/2081 . . . http://patchwork.linux-mips.org/patch/2090 arch/mips/cavium-octeon/Kconfig | 15 ++++----------- 1 files changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index caae228..cad555e 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -1,11 +1,7 @@ -config CAVIUM_OCTEON_SPECIFIC_OPTIONS - bool "Enable Octeon specific options" - depends on CPU_CAVIUM_OCTEON - default "y" +if CPU_CAVIUM_OCTEON config CAVIUM_CN63XXP1 bool "Enable CN63XXP1 errata worarounds" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS default "n" help The CN63XXP1 chip requires build time workarounds to @@ -16,7 +12,6 @@ config CAVIUM_CN63XXP1 config CAVIUM_OCTEON_2ND_KERNEL bool "Build the kernel to be used as a 2nd kernel on the same chip" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS default "n" help This option configures this kernel to be linked at a different @@ -26,7 +21,6 @@ config CAVIUM_OCTEON_2ND_KERNEL config CAVIUM_OCTEON_HW_FIX_UNALIGNED bool "Enable hardware fixups of unaligned loads and stores" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS default "y" help Configure the Octeon hardware to automatically fix unaligned loads @@ -38,7 +32,6 @@ config CAVIUM_OCTEON_HW_FIX_UNALIGNED config CAVIUM_OCTEON_CVMSEG_SIZE int "Number of L1 cache lines reserved for CVMSEG memory" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS range 0 54 default 1 help @@ -50,7 +43,6 @@ config CAVIUM_OCTEON_CVMSEG_SIZE config CAVIUM_OCTEON_LOCK_L2 bool "Lock often used kernel code in the L2" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS default "y" help Enable locking parts of the kernel into the L2 cache. @@ -93,7 +85,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC - depends on CPU_CAVIUM_OCTEON config CAVIUM_OCTEON_HELPER def_bool y @@ -107,6 +98,8 @@ config NEED_SG_DMA_LENGTH config SWIOTLB def_bool y - depends on CPU_CAVIUM_OCTEON select IOMMU_HELPER select NEED_SG_DMA_LENGTH + + +endif # CPU_CAVIUM_OCTEON -- 1.7.2.3 From miloody@gmail.com Fri Feb 18 08:12:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Feb 2011 08:12:12 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:33449 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491147Ab1BRHMJ (ORCPT ); Fri, 18 Feb 2011 08:12:09 +0100 Received: by iyh42 with SMTP id 42so3149204iyh.36 for ; Thu, 17 Feb 2011 23:12:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:cc:content-type; bh=e/hZLGDg9/OYyiAFJTQ93GrMjyob2cfKzlIS1H1YnJA=; b=dKIGMYsMyBnXVTOw6HZ6Fi+6doHRlHho03nVEln3eyzf63WK5mZeoa7OK5pMVaY54/ ld58Uw6hDtMmpUYFnOxguhfoywt1QMZgiSD8vrkX2LhhJQP0QIJ38XqPswNEqlipfmbL QUoPSglpepQc+ctt8cV9e8liM7gkDTZ1FuZ5s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:cc :content-type; b=Qyjqmn8hjzGpuI70C1+D9DixKxusv8yn6L3oPlUdO7qRdAv4vK8yla4fJ4tNdJY9JE GPOmEzN4uSTfl54qyXgx+LSi59vCICtmccB1QGGPYUxwJ8FHSzeDAIU0wlMMgc/ZmwHX bAxsoch3zENEsfm0AqaXtf1z+nDj1v0HZfXrw= MIME-Version: 1.0 Received: by 10.42.178.135 with SMTP id bm7mr495879icb.101.1298013120857; Thu, 17 Feb 2011 23:12:00 -0800 (PST) Received: by 10.42.108.74 with HTTP; Thu, 17 Feb 2011 23:12:00 -0800 (PST) In-Reply-To: References: <220544EE49E5824C9DE242B5ACE58C3041639ACA@EMBX01-BNG.jnpr.net> Date: Fri, 18 Feb 2011 15:12:00 +0800 Message-ID: Subject: Re: some questions about kernel source From: loody Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 To: unlisted-recipients:; (no To-header on input) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29228 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Hi all: 2011/2/18 John Mahoney : > On Thu, Feb 17, 2011 at 9:17 AM, loody wrote: >> hi :-) >> >> 2011/2/16 Mulyadi Santosa : >>> Hi :) >>> >>> On Wed, Feb 16, 2011 at 12:59, Rajat Jain wrote: >>>> Hello loody, >>>> >>>>> 1. in kernel/trace, I always see "__read_mostly" at the end of >>>>> parameter is that a compiler optimization parameter? >>>> >>>> Yes, it is a hint to the compiler that the parameter is mostly read, thus if the compiler has to make a decision between optimizing one of the read / write paths, it will optimize the read path even at the expense of write path. >>> >>> >>> To be precise, they will be grouped into same cache line as much as >>> possible. By doing so, those cache line won't be invalidated so often >>> (keeping them "hot" :) hehehhe ) >> >> I cannot find it on the gcc manual. >> is it a option in kernel for kernel usage? >> if so, where I can found them. >> If not, can I use it on normal user level program? >> > > It is a macro defined for x86 as: > > #define __read_mostly __attribute__((__section__(".data..read_mostly"))) I try to find "__read_mostly" of mips arch and below are the results I grep on arch/ ...... ia64/xen/hypervisor.c:29:struct shared_info *HYPERVISOR_shared_info __read_mostly = mips/kernel/irq_txx9.c:58:static struct txx9_irc_reg __iomem *txx9_ircptr __read_mostly; mips/kernel/irq_txx9.c:63:} txx9irq[TXx9_MAX_IR] __read_mostly; mips/kernel/setup.c:35:struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; mips/kernel/setup.c:55:unsigned long mips_machtype __read_mostly = MACH_UNKNOWN; mips/kernel/setup.c:72:const unsigned long mips_io_port_base __read_mostly = -1; mips/kernel/smp.c:58:cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; mips/kernel/process.c:329:static struct mips_frame_info schedule_mfi __read_mostly; mips/txx9/generic/irq_tx4939.c:50:} tx4939irq[TX4939_NUM_IR] __read_mostly; mips/mm/c-r4k.c:67:static unsigned long icache_size __read_mostly; mips/mm/c-r4k.c:68:static unsigned long dcache_size __read_mostly; mips/mm/c-r4k.c:69:static unsigned long scache_size __read_mostly; parisc/mm/init.c:543:unsigned long *empty_zero_page __read_mostly; parisc/include/asm/cache.h:31:#define __read_mostly __attribute__((__section__(".data.read_mostly"))) ..... x86/vdso/vdso32-setup.c:57:unsigned int __read_mostly vdso_enabled = VDSO_DEFAULT; x86/include/asm/cache.h:10:#define __read_mostly __attribute__((__section__(".data.read_mostly"))) Does Mips arch not use this option? -- Regards, miloody From kumba@gentoo.org Fri Feb 18 12:02:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Feb 2011 12:02:31 +0100 (CET) Received: from qmta13.westchester.pa.mail.comcast.net ([76.96.59.243]:39324 "EHLO qmta13.westchester.pa.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491055Ab1BRLC1 (ORCPT ); Fri, 18 Feb 2011 12:02:27 +0100 Received: from omta22.westchester.pa.mail.comcast.net ([76.96.62.73]) by qmta13.westchester.pa.mail.comcast.net with comcast id 9Nzd1g0011ap0As5DP2N3J; Fri, 18 Feb 2011 11:02:22 +0000 Received: from [192.168.1.13] ([69.251.104.163]) by omta22.westchester.pa.mail.comcast.net with comcast id 9P2L1g0063XYSBH3iP2Mb2; Fri, 18 Feb 2011 11:02:22 +0000 Message-ID: <4D5E51A8.8070408@gentoo.org> Date: Fri, 18 Feb 2011 06:02:00 -0500 From: Kumba User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: Lars-Peter Clausen CC: Linux MIPS List , rtc-linux@googlegroups.com Subject: Re: [PATCH 1/2]: Add support for Dallas/Maxim DS1685/1687 RTC References: <4D5A65E3.1050707@gentoo.org> <4D5C5C66.6060205@metafoo.de> <4D5CF0EE.7000308@gentoo.org> <4D5D09FF.6010005@metafoo.de> In-Reply-To: <4D5D09FF.6010005@metafoo.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29229 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips On 02/17/2011 06:43, Lars-Peter Clausen wrote: > > That is what I meant. Pass the return value of rtc_valid_tm on, instead of > setting the time to 0 and pretend everything went fine. > You can still keep the dev_err though, no problem with that. Okay, I got confused by this and thought you were referring to the quoted test box below in your first response. My bad. You're referring to the tail end of ds1685_rtc_read_time. To clarify, this construct exists in four existing RTC drivers. If this is wrong, I suggest fixing these four drivers, lest someone else come along and try to copy the idea, thinking it's the RightThing(); drivers/rtc/rtc-ds1553.c:131 drivers/rtc/rtc-ds1742.c:119 drivers/rtc/rtc-rs5c348.c:136 drivers/rtc/rtc-stk17ta8.c:133 I am going to assume the proper approach is: return rtc_Valid_tm(tm); Cheers!, -- Joshua Kinard Gentoo/MIPS kumba@gentoo.org "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." --Emperor Turhan, Centauri Republic From anoop.pa@gmail.com Fri Feb 18 14:20:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Feb 2011 14:20:09 +0100 (CET) Received: from mail-qw0-f49.google.com ([209.85.216.49]:43452 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491047Ab1BRNUG (ORCPT ); Fri, 18 Feb 2011 14:20:06 +0100 Received: by qwj9 with SMTP id 9so3193391qwj.36 for ; Fri, 18 Feb 2011 05:19:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:to:cc:in-reply-to:references :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=DT/reja8bgdkEnNAI76RNRcho/X4/K2zAvnnbs4YD6c=; b=epEpxscqFJwu9KKkVBXYZTIMzQ/ZRWXyajWTKZOo8kGSnzwL6AKI7i/RVb2zEdxy87 4gZJskfuv24R6Twd7CF7g+AwcvKerKm7NEEK6uiF1XjcgFYnOCNVbLJxyvgpm9+3X2hg bHaX7sDYTQ0opsbAe1qDq09UsC+x+bbNSZuRw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=BcplEk/n6ZwHLZzvSY6yozEZJ7t0D397X6bvqp/0A83dIOKRv1W3Vc/49xv/xRqGOv XnXCllEiikoBJogo0GehqWPH3wLN3i/VM8o2WJqZRZaS1hlfYfXsezGOwyWgVvOIg0Ex IcBUjmoPS6Q4uQEz6L85Ltbqgs12r72Y8xK8Y= Received: by 10.229.91.145 with SMTP id n17mr501884qcm.258.1298035198542; Fri, 18 Feb 2011 05:19:58 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id nb15sm1529657qcb.38.2011.02.18.05.19.54 (version=SSLv3 cipher=OTHER); Fri, 18 Feb 2011 05:19:56 -0800 (PST) Subject: Re: some questions about kernel source From: Anoop P A To: loody Cc: Linux MIPS Mailing List In-Reply-To: References: <220544EE49E5824C9DE242B5ACE58C3041639ACA@EMBX01-BNG.jnpr.net> Content-Type: text/plain; charset="UTF-8" Date: Fri, 18 Feb 2011 19:12:08 +0530 Message-ID: <1298036528.9950.11.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29230 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2011-02-18 at 15:12 +0800, loody wrote: > Hi all: > > 2011/2/18 John Mahoney : > > On Thu, Feb 17, 2011 at 9:17 AM, loody wrote: > >> hi :-) > >> > >> 2011/2/16 Mulyadi Santosa : > >>> Hi :) > >>> > >>> On Wed, Feb 16, 2011 at 12:59, Rajat Jain wrote: > >>>> Hello loody, > >>>> > >>>>> 1. in kernel/trace, I always see "__read_mostly" at the end of > >>>>> parameter is that a compiler optimization parameter? > >>>> > >>>> Yes, it is a hint to the compiler that the parameter is mostly read, thus if the compiler has to make a decision between optimizing one of the read / write paths, it will optimize the read path even at the expense of write path. > >>> > >>> > >>> To be precise, they will be grouped into same cache line as much as > >>> possible. By doing so, those cache line won't be invalidated so often > >>> (keeping them "hot" :) hehehhe ) > >> > >> I cannot find it on the gcc manual. > >> is it a option in kernel for kernel usage? > >> if so, where I can found them. > >> If not, can I use it on normal user level program? > >> > > > > It is a macro defined for x86 as: > > > > #define __read_mostly __attribute__((__section__(".data..read_mostly"))) > I try to find "__read_mostly" of mips arch and below are the results I > grep on arch/ > > ...... > ia64/xen/hypervisor.c:29:struct shared_info *HYPERVISOR_shared_info > __read_mostly = > mips/kernel/irq_txx9.c:58:static struct txx9_irc_reg __iomem > *txx9_ircptr __read_mostly; > mips/kernel/irq_txx9.c:63:} txx9irq[TXx9_MAX_IR] __read_mostly; > mips/kernel/setup.c:35:struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; > mips/kernel/setup.c:55:unsigned long mips_machtype __read_mostly = MACH_UNKNOWN; > mips/kernel/setup.c:72:const unsigned long mips_io_port_base __read_mostly = -1; > mips/kernel/smp.c:58:cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; > mips/kernel/process.c:329:static struct mips_frame_info schedule_mfi > __read_mostly; > mips/txx9/generic/irq_tx4939.c:50:} tx4939irq[TX4939_NUM_IR] __read_mostly; > mips/mm/c-r4k.c:67:static unsigned long icache_size __read_mostly; > mips/mm/c-r4k.c:68:static unsigned long dcache_size __read_mostly; > mips/mm/c-r4k.c:69:static unsigned long scache_size __read_mostly; > parisc/mm/init.c:543:unsigned long *empty_zero_page __read_mostly; > parisc/include/asm/cache.h:31:#define __read_mostly > __attribute__((__section__(".data.read_mostly"))) > ..... > x86/vdso/vdso32-setup.c:57:unsigned int __read_mostly vdso_enabled = > VDSO_DEFAULT; > x86/include/asm/cache.h:10:#define __read_mostly > __attribute__((__section__(".data.read_mostly"))) > > > Does Mips arch not use this option? arch/mips/include/asm/cache.h:#define __read_mostly __attribute__((__section__(".data.read_mostly"))) From anoop.pa@gmail.com Fri Feb 18 14:33:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Feb 2011 14:33:35 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:36372 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491047Ab1BRNdc (ORCPT ); Fri, 18 Feb 2011 14:33:32 +0100 Received: by vws5 with SMTP id 5so1827987vws.36 for ; Fri, 18 Feb 2011 05:33:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=FbZbxWubMihkgGCsHxZrTmYQBi9hozDPCpsT2lMjHOs=; b=aSsIwmgtOO2twHY24vH1+3aBRAQm8P+RdQMieNH5M0EtpSl1JGLUBrUcS9bMJefBOv bpUa48ZCy6bBQrEh6Auq0fnX+miN0Pkz1KQqBxRjht0GlCKnZhFD0Ws/gKgAY2jNE+AJ HHBz4+ji5kI1taJJS+AlBggKCavO8iDxqsItE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=KAW5jHVRLWSrNQck0XxCbg5utFD8kWHQNgOrf/sUjUQafNjRez9fZtLufyCsjPreNP vhxqXCoumDj5kMe+H06lCcxrK06fs6olFC78rfcOUuaYa4ltk/1/n9YhcymhSH72RbAQ 051k5D6NFpshohqgjRUbTSY+eBjU+g66vByqg= Received: by 10.52.163.73 with SMTP id yg9mr1221163vdb.256.1298036006244; Fri, 18 Feb 2011 05:33:26 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id y15sm991890vch.29.2011.02.18.05.33.21 (version=SSLv3 cipher=OTHER); Fri, 18 Feb 2011 05:33:24 -0800 (PST) From: "Anoop P.A" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Anoop P A Subject: [PATCH] Make msp7120_reset generic Date: Fri, 18 Feb 2011 19:25:29 +0530 Message-Id: <1298037329-13683-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29231 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop P A Remove platform dependency code from msp7120 reset code and make it generic. Now the code can be reused for other boards running msp71xx family SoC. Signed-off-by: Anoop P A --- arch/mips/pmc-sierra/msp71xx/msp_setup.c | 85 ++++++++++++++++++------------ 1 files changed, 52 insertions(+), 33 deletions(-) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index fb37a10..4a6cc0d 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -18,30 +18,33 @@ #include #include +#include #if defined(CONFIG_PMC_MSP7120_GW) -#include + /* GPIO 9 is the 4th GPIO of register 3 + */ #define MSP_BOARD_RESET_GPIO 9 +#else +#undef MSP_BOARD_RESET_GPIO #endif extern void msp_serial_setup(void); extern void pmctwiled_setup(void); -#if defined(CONFIG_PMC_MSP7120_EVAL) || \ - defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) /* - * Performs the reset for MSP7120-based boards + * Performs the reset for MSP71xx-based boards */ -void msp7120_reset(void) +void msp71xx_reset(void) { void *start, *end, *iptr; register int i; + register u32 temp __maybe_unused; /* Diasble all interrupts */ local_irq_disable(); #ifdef CONFIG_SYS_SUPPORTS_MULTITHREADING dvpe(); + dmt(); #endif /* Cache the reset code of this function */ @@ -78,49 +81,56 @@ void msp7120_reset(void) /* Wait a bit for the DDRC to settle */ for (i = 0; i < 100000000; i++); -#if defined(CONFIG_PMC_MSP7120_GW) +#if defined MSP_BOARD_RESET_GPIO /* - * Set GPIO 9 HI, (tied to board reset logic) - * GPIO 9 is the 4th GPIO of register 3 + * Set reset GPIO HI, (tied to board reset logic) * * NOTE: We cannot use the higher-level msp_gpio_mode()/out() * as GPIO char driver may not be enabled and it would look up * data inRAM! */ - set_value_reg32(GPIO_CFG3_REG, 0xf000, 0x8000); - set_reg32(GPIO_DATA3_REG, 8); + temp = __raw_readl(MSP_GPIO_MODE_REGISTER[MSP_BOARD_RESET_GPIO]) & + ~BASIC_MODE_MASK(MSP_BOARD_RESET_GPIO); + __raw_writel(temp | BASIC_MODE(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO), + MSP_GPIO_MODE_REGISTER[MSP_BOARD_RESET_GPIO]); + /* Now set the reset gpio pin hi */ + temp = __raw_readl(MSP_GPIO_DATA_REGISTER[MSP_BOARD_RESET_GPIO]); + __raw_writel(temp | BASIC_DATA_MASK(MSP_BOARD_RESET_GPIO), + MSP_GPIO_DATA_REGISTER[MSP_BOARD_RESET_GPIO]); /* - * In case GPIO9 doesn't reset the board (jumper configurable!) + * In case GPIO doesn't reset the board (jumper configurable!) * fallback to device reset below. */ #endif - /* Set bit 1 of the MSP7120 reset register */ - *RST_SET_REG = 0x00000001; + /* Set bit 1 of the MSP71xx reset register */ + __raw_writel(0x00000001, RST_SET_REG); __asm__ __volatile__ ( - "endpoint: \n" + "endpoint:\n" ); } -#endif void msp_restart(char *command) { - printk(KERN_WARNING "Now rebooting .......\n"); - -#if defined(CONFIG_PMC_MSP7120_EVAL) || \ - defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) - msp7120_reset(); -#else - /* No chip-specific reset code, just jump to the ROM reset vector */ - set_c0_status(ST0_BEV | ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -#endif + unsigned long family = identify_family(); + switch (family) { + case FAMILY_MSP7100: + msp71xx_reset(); + break; + default: + /* No chip-specific reset code, just jump + * to the ROM reset vector + */ + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + + __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); + break; + } } void msp_halt(void) @@ -141,9 +151,7 @@ void msp_power_off(void) void __init plat_mem_setup(void) { - _machine_restart = msp_restart; - _machine_halt = msp_halt; - pm_power_off = msp_power_off; +/*TODO: Move mem setup here */ } extern struct plat_smp_ops msp_smtc_smp_ops; @@ -244,3 +252,14 @@ void __init prom_init(void) pmctwiled_setup(); #endif } + +static int __init mips_reboot_setup(void) +{ + _machine_restart = msp_restart; + _machine_halt = msp_halt; + pm_power_off = msp_power_off; + + return 0; +} + +arch_initcall(mips_reboot_setup); -- 1.7.0.4 From miloody@gmail.com Fri Feb 18 15:23:31 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 18 Feb 2011 15:23:34 +0100 (CET) Received: from mail-iw0-f177.google.com ([209.85.214.177]:62375 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491131Ab1BROXa (ORCPT ); Fri, 18 Feb 2011 15:23:30 +0100 Received: by iwn38 with SMTP id 38so3576978iwn.36 for ; Fri, 18 Feb 2011 06:23:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=40fBPuhe/gp/paS1EQIENXZtpVXev1Hshlt2RmSGkbk=; b=N84TVscWKmF/LEoSXgb2u2LoOJfeZYuNHL6lMwUsPNeQJn+8EMEEidevz4upPBos3Y FoTc5M8T52eFFl0xReB/zS9Ht5LFyCqlFNuQrH8Q2dvkQUnW/QqbyGhMxg+TLiUuhya4 tqLnVamtq42EUu+soAzI5eHjyIDTwQVPz/q7o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=c71wqAa+OlcLo44F6wbNqrBWw/MhNEfed8rRrB2W0892bEzNsPZ4QLDUwDGQAq86in t/+1TQth9gleQDu3niFVxTsmEEFrBD8yFBT8ud+aXIa8srnaE2kUAN//X14BUfikvk8L ozQ+cb7FzMm1rtC0B8mE6Zv6Nzf9kPc6noQwo= MIME-Version: 1.0 Received: by 10.42.169.195 with SMTP id c3mr869434icz.503.1298039004673; Fri, 18 Feb 2011 06:23:24 -0800 (PST) Received: by 10.42.108.74 with HTTP; Fri, 18 Feb 2011 06:23:24 -0800 (PST) In-Reply-To: <1298036528.9950.11.camel@paanoop1-desktop> References: <220544EE49E5824C9DE242B5ACE58C3041639ACA@EMBX01-BNG.jnpr.net> <1298036528.9950.11.camel@paanoop1-desktop> Date: Fri, 18 Feb 2011 22:23:24 +0800 Message-ID: Subject: Re: some questions about kernel source From: loody To: Anoop P A Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29232 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips hi: 2011/2/18 Anoop P A : > On Fri, 2011-02-18 at 15:12 +0800, loody wrote: >> Hi all: >> >> 2011/2/18 John Mahoney : >> > On Thu, Feb 17, 2011 at 9:17 AM, loody wrote: >> >> hi :-) >> >> >> >> 2011/2/16 Mulyadi Santosa : >> >>> Hi :) >> >>> >> >>> On Wed, Feb 16, 2011 at 12:59, Rajat Jain wrote: >> >>>> Hello loody, >> >>>> >> >>>>> 1. in kernel/trace, I always see "__read_mostly" at the end of >> >>>>> parameter is that a compiler optimization parameter? >> >>>> >> >>>> Yes, it is a hint to the compiler that the parameter is mostly read, thus if the compiler has to make a decision between optimizing one of the read / write paths, it will optimize the read path even at the expense of write path. >> >>> >> >>> >> >>> To be precise, they will be grouped into same cache line as much as >> >>> possible. By doing so, those cache line won't be invalidated so often >> >>> (keeping them "hot" :) hehehhe ) >> >> >> >> I cannot find it on the gcc manual. >> >> is it a option in kernel for kernel usage? >> >> if so, where I can found them. >> >> If not, can I use it on normal user level program? >> >> >> > >> > It is a macro defined for x86 as: >> > >> > #define __read_mostly __attribute__((__section__(".data..read_mostly"))) >> I try to find "__read_mostly" of mips arch and below are the results I >> grep on arch/ >> >> ...... >> ia64/xen/hypervisor.c:29:struct shared_info *HYPERVISOR_shared_info >> __read_mostly = >> mips/kernel/irq_txx9.c:58:static struct txx9_irc_reg __iomem >> *txx9_ircptr __read_mostly; >> mips/kernel/irq_txx9.c:63:} txx9irq[TXx9_MAX_IR] __read_mostly; >> mips/kernel/setup.c:35:struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; >> mips/kernel/setup.c:55:unsigned long mips_machtype __read_mostly = MACH_UNKNOWN; >> mips/kernel/setup.c:72:const unsigned long mips_io_port_base __read_mostly = -1; >> mips/kernel/smp.c:58:cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; >> mips/kernel/process.c:329:static struct mips_frame_info schedule_mfi >> __read_mostly; >> mips/txx9/generic/irq_tx4939.c:50:} tx4939irq[TX4939_NUM_IR] __read_mostly; >> mips/mm/c-r4k.c:67:static unsigned long icache_size __read_mostly; >> mips/mm/c-r4k.c:68:static unsigned long dcache_size __read_mostly; >> mips/mm/c-r4k.c:69:static unsigned long scache_size __read_mostly; >> parisc/mm/init.c:543:unsigned long *empty_zero_page __read_mostly; >> parisc/include/asm/cache.h:31:#define __read_mostly >> __attribute__((__section__(".data.read_mostly"))) >> ..... >> x86/vdso/vdso32-setup.c:57:unsigned int __read_mostly vdso_enabled = >> VDSO_DEFAULT; >> x86/include/asm/cache.h:10:#define __read_mostly >> __attribute__((__section__(".data.read_mostly"))) >> >> >> Does Mips arch not use this option? > > arch/mips/include/asm/cache.h:#define __read_mostly > __attribute__((__section__(".data.read_mostly"))) > > > That is wired. I cat the content of my cache.h as below: linux-2.6.33.4.mips# cat arch/mips/include/asm/cache.h /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_CACHE_H #define _ASM_CACHE_H #include #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define SMP_CACHE_SHIFT L1_CACHE_SHIFT #define SMP_CACHE_BYTES L1_CACHE_BYTES #endif /* _ASM_CACHE_H */ linux-2.6.33.4.mips# Can I get the conclusion that before 2.6.33.4, there is no "__read_mostly"? Thanks a lot, miloody From sshtylyov@mvista.com Sun Feb 20 13:39:44 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 20 Feb 2011 13:39:48 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:52837 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491045Ab1BTMjo (ORCPT ); Sun, 20 Feb 2011 13:39:44 +0100 Received: by ewy23 with SMTP id 23so205407ewy.36 for ; Sun, 20 Feb 2011 04:39:37 -0800 (PST) Received: by 10.213.14.20 with SMTP id e20mr154551eba.28.1298205577285; Sun, 20 Feb 2011 04:39:37 -0800 (PST) Received: from [192.168.2.2] ([91.79.106.47]) by mx.google.com with ESMTPS id t50sm3857121eeh.6.2011.02.20.04.39.34 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 20 Feb 2011 04:39:35 -0800 (PST) Message-ID: <4D610B3A.5070705@mvista.com> Date: Sun, 20 Feb 2011 15:38:18 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: "Anoop P.A" CC: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] Make msp7120_reset generic References: <1298037329-13683-1-git-send-email-anoop.pa@gmail.com> In-Reply-To: <1298037329-13683-1-git-send-email-anoop.pa@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29233 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 18-02-2011 16:55, Anoop P.A wrote: > From: Anoop P A > Remove platform dependency code from msp7120 reset code and make it generic. > Now the code can be reused for other boards running msp71xx family SoC. > Signed-off-by: Anoop P A [...] > diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c > index fb37a10..4a6cc0d 100644 > --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c > +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c > @@ -18,30 +18,33 @@ > > #include > #include > +#include > > #if defined(CONFIG_PMC_MSP7120_GW) > -#include > + /* GPIO 9 is the 4th GPIO of register 3 > + */ Not clear why you're using a multi-line comment where a single-one line one (and not indented) would be enough? > @@ -78,49 +81,56 @@ void msp7120_reset(void) > /* Wait a bit for the DDRC to settle */ > for (i = 0; i < 100000000; i++); > > -#if defined(CONFIG_PMC_MSP7120_GW) > +#if defined MSP_BOARD_RESET_GPIO Hm, didn't know that the 'defined' syntax without parens is valid too... > @@ -141,9 +151,7 @@ void msp_power_off(void) > > void __init plat_mem_setup(void) > { > - _machine_restart = msp_restart; > - _machine_halt = msp_halt; > - pm_power_off = msp_power_off; > +/*TODO: Move mem setup here */ This line should be indented. WBR, Sergei From yad.naveen@gmail.com Mon Feb 21 14:07:33 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 21 Feb 2011 14:07:38 +0100 (CET) Received: from mail-vx0-f177.google.com ([209.85.220.177]:39583 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491178Ab1BUNHd (ORCPT ); Mon, 21 Feb 2011 14:07:33 +0100 Received: by vxg33 with SMTP id 33so1856991vxg.36 for ; Mon, 21 Feb 2011 05:07:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:date:message-id:subject:from:to :content-type; bh=TFVNJFzNwQSFH6U/jiOA8qyRj2ppi670p7I8SgzYMM4=; b=PJwLzOxgf1kcYX60ea9ZY7K+Zph/q6ThNpd1ymvSCnsHYubkKHk+y0KfhMoie1tdzx pTklDi61i9vr995tp2LxYuzWqze9aJ2OND8JbDoinvLTHOEx2D+Pv+EO15rMyQf0NqRl hm0jPtfLi52ZSL+jC7RBz4mjS2F0E4yQSLmzw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=n2eXccWPnMOrF9bfmpQzOEjkmHEnhJb8reItBJEIZi6B5DYXwQe31Gz47sPLHJBk2g R15j6GxJEekt2E5k1zRb76bWwI+ZafU1SWPb/7cHWg4kmdHiq6Shvqj+lmQTBQPZvjQm rdXq/4ee10yC9WsCMkxfoS06UMZG2ZIczMlnI= MIME-Version: 1.0 Received: by 10.52.158.196 with SMTP id ww4mr1762122vdb.220.1298293646492; Mon, 21 Feb 2011 05:07:26 -0800 (PST) Received: by 10.52.161.104 with HTTP; Mon, 21 Feb 2011 05:07:26 -0800 (PST) Date: Mon, 21 Feb 2011 18:37:26 +0530 Message-ID: Subject: Issue on 2.6.35.9 kernel with module insertion when Rootfs is NFS mounted From: naveen yadav To: kernelnewbies@nl.linux.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29234 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Hi All, When I am trying to insert some modules on 2.6.35.9, I am getting some random crash's. There are 2 scenarios:- 1) When my rootfs is NFS mounted. In this case, when I insmod modules some get inserted and some gives crash. I have tried with following modules :- a) ext2.ko ; size 93K ; status - successfully inserted b) ext3.ko ; size 188K ; status - insertion failed c) xfs.ko ; size 823K ; status - insertion failed d) usbcore.ko ; size 243K ; status - insertion failed 2) When I created kernel Image using Initramfs, hence making all modules part of ramfs image all insertions are successfull In case of rootfs as NFS mounted here are some of the crash logs :- Crash 1 Linux#> insmod usbcore.ko Module len 238547 truncated insmod: can't insert 'usbcore.ko': invalid module format Crash 2 Linux#> insmod usbcore.ko CPU 0 Unable to handle kernel paging request at virtual address 00100100, epc == 8008fb00, ra == 8008cf9c Oops[#1]: Cpu 0 $ 0 : 00000000 00000001 84166e00 00100100 $ 4 : 84166e00 8415e870 84166e00 8415e870 $ 8 : 84086720 83c12178 00000000 000081a4 $12 : 00000000 00000000 01a0c43d 00000000 $16 : 84166e00 83c12120 8410de58 00000000 $20 : 84166100 83c0b380 00000024 00002001 $24 : 00000000 800f058c $28 : 8410c000 8410ddb8 00000000 8008cf9c Hi : 000bf0c5 Lo : 6ab94a84 epc : 8008fb00 file_move+0x20/0x68 Not tainted ra : 8008cf9c __dentry_open+0x110/0x278 Status: 11008c03 KERNEL EXL IE Cause : 0080000c BadVA : 00100100 PrId : 00019555 (MIPS 34Kc) Modules linked in: Process insmod (pid: 260, threadinfo=8410c000, task=84136b20, tls=005c9470) Stack : 8410de58 8410de68 83c0b380 00000001 8410de58 84166e00 00000000 8410de58 8410de68 00000000 00002000 8008d1ec 83c06080 8410de58 00000000 83c06080 84086720 00000000 00000000 80099f4c ebb5351b 80380000 84086720 803177a0 8410de68 800900c0 ffffffe9 00000003 00002000 8410de68 ffffff9c 00000024 00000002 8009c23c 000003fc 00000000 84150420 84136b20 00000000 8400a000 ... Call Trace: [<8008fb00>] file_move+0x20/0x68 [<8008cf9c>] __dentry_open+0x110/0x278 [<8008d1ec>] nameidata_to_filp+0x38/0x5c [<80099f4c>] do_last+0x58c/0x6fc [<8009c23c>] do_filp_open+0x1c0/0x62c [<8008ce04>] do_sys_open+0x6c/0xc8 [<80002164>] stack_done+0x20/0x3c Code: af820014 8c830004 8c820000 8ce40000 ac430004 acc40000 ac860004 ace60000 Disabling lock debugging due to kernel taint note: insmod[260] exited with preempt_count 1 BUG: scheduling while atomic: insmod/260/0x10000002 Modules linked in: Call Trace: [<800051b4>] dump_stack+0x8/0x34 [<800054e0>] schedule+0x9c/0x4b4 [<80005a20>] _cond_resched+0x3c/0x60 [<80077788>] unmap_vmas+0x594/0x690 [<8007bf2c>] exit_mmap+0xc0/0x1a4 [<80024474>] mmput+0x3c/0x118 [<80028a88>] exit_mm+0x130/0x164 [<8002a89c>] do_exit+0x1b4/0x624 [<8000e3e8>] default_cu2_call+0x0/0x4c Segmentation fault I tried to debug myself and put some print in kernel/module.c function load_module, printing the length and offset of each section header. I found that on some sections the values are wrongly shown Linux#> insmod usbcore.ko load_module: umod=2aaa8008, len=238950, uargs=005c2f70 hdr->e_shnum 601 <= number of sections shown correctly header type sechdrs[i].sh_type =7 sechdrs[i].sh_offset=52 sechdrs[i].sh_size=36 <= correct header type sechdrs[i].sh_type =1 sechdrs[i].sh_offset=96 sechdrs[i].sh_size=0 <= correct header type sechdrs[i].sh_type =1 sechdrs[i].sh_offset=96 sechdrs[i].sh_size=72 <= correct header type sechdrs[i].sh_type =9 sechdrs[i].sh_offset=154448 sechdrs[i].sh_size=8 <= correct header type sechdrs[i].sh_type =1 sechdrs[i].sh_offset=168 sechdrs[i].sh_size=64 <= correct header type sechdrs[i].sh_type =9 sechdrs[i].sh_offset=154456 sechdrs[i].sh_size=8 <= correct header type sechdrs[i].sh_type =1 sechdrs[i].sh_offset=232 sechdrs[i].sh_size=64 <= correct header type sechdrs[i].sh_type =2136364925 sechdrs[i].sh_offset=4286298862 sechdrs[i].sh_size=1602090478 <= Incorrect header type sechdrs[i].sh_type =-1386227977 sechdrs[i].sh_offset=4293914174 sechdrs[i].sh_size=1429526523 <= Incorrect header type sechdrs[i].sh_type =-780708260 sechdrs[i].sh_offset=1579921686 sechdrs[i].sh_size=1562763221 <= Incorrect header type sechdrs[i].sh_type =-571181733 sechdrs[i].sh_offset=1875703162 sechdrs[i].sh_size=3600104807 <= Incorrect header type sechdrs[i].sh_type =9 sechdrs[i].sh_offset=182792 sechdrs[i].sh_size=32 <= correct header type sechdrs[i].sh_type =1 sechdrs[i].sh_offset=69044 sechdrs[i].sh_size=32 <= correct header type sechdrs[i].sh_type =9 sechdrs[i].sh_offset=182824 sechdrs[i].sh_size=32 <= correct header type sechdrs[i].sh_type =1 sechdrs[i].sh_offset=69076 sechdrs[i].sh_size=48 <= correct The prints goes on this way and lastly the insertion failed with this message :- CPU 0 Unable to handle kernel paging request at virtual address ed79cc5b, epc == 80054254, ra == 800541d8 Oops[#1]: Please suggest me some ideas to debug as to why when rootfs is NFS mounted I am not able to load modules. From f.fainelli@gmail.com Mon Feb 21 14:21:09 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 21 Feb 2011 14:21:13 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:65148 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491179Ab1BUNVJ (ORCPT ); Mon, 21 Feb 2011 14:21:09 +0100 Received: by wwi17 with SMTP id 17so5585235wwi.24 for ; Mon, 21 Feb 2011 05:21:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:user-agent :organization:cc:mime-version:content-type:content-transfer-encoding :message-id; bh=w4/OiM69rO3yA0nulzRZT4vEPgB1wULZei8QmoJ2HXc=; b=Ii8oyCYS7owEz/CFPwg70auIk9uC6jUVUlUr1ajawufAuS71pj7nu2TnjkFukJvvIj ls/yQTayehPVnsmTtqQcTYMEzz2vCvj+VFPv0IAuMS0fUlwfAP06ZnKqBGb7oemOx8Hx /a0JnebJ5VQO185WGEJGC8b+6xHoBfhB4kDiI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:organization:cc:mime-version :content-type:content-transfer-encoding:message-id; b=sPCnqhnQ/WGgLwI0vhuDLNSY60ozlFuknCtRLHyk1HQAEXIF2xVV3KczIxgSq7qYlL 386deI0LysuUBD8z4kMfTnn0rNUBtzDBBCMGo4UBVaj9N9F8XlIy4lO/uNwFStTIquvo Fp5ds/CMdrdGOR4YAv9GckD/3/GjHQVuhnKRQ= Received: by 10.227.134.135 with SMTP id j7mr1162717wbt.12.1298294463744; Mon, 21 Feb 2011 05:21:03 -0800 (PST) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id j49sm2056488wer.38.2011.02.21.05.21.00 (version=SSLv3 cipher=OTHER); Mon, 21 Feb 2011 05:21:01 -0800 (PST) From: Florian Fainelli To: linux-mips@linux-mips.org Subject: [PATCH] Alchemy: fix reset for MTX-1 and XXS1500 Date: Mon, 21 Feb 2011 14:28:02 +0100 User-Agent: KMail/1.13.5 (Linux/2.6.35-25-server; KDE/4.5.1; x86_64; ; ) Organization: OpenWrt Cc: ralf@linux-mips.org, br1@einfach.org MIME-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <201102211428.02125.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29235 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Since commit 32fd6901 (MIPS: Alchemy: get rid of common/reset.c) Alchemy-based boards use their own reset function. For MTX-1 and XXS1500, the reset function pokes at the BCSR.SYSTEM_RESET register, but this does not work. According to Bruno Randolf, this was not tested when written. Previously, the generic au1000_restart() routine called the board specific reset function, which for MTX-1 and XXS1500 did not work, but finally made a jump to the reset vector, which really triggers a system restart. Fix reboot for both targets by jumping to the reset vector. CC: Bruno Randolf CC: stable@kernel.org Signed-off-by: Florian Fainelli --- Stable: 2.6.34+ diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 6398fa9..40b84b9 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -54,8 +54,8 @@ int mtx1_pci_idsel(unsigned int devsel, int assert); static void mtx1_reset(char *c) { - /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ - au_writel(0x00000000, 0xAE00001C); + /* Jump to the reset vector */ + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); } static void mtx1_power_off(void) diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index b43c918..80c521e 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c @@ -36,8 +36,8 @@ static void xxs1500_reset(char *c) { - /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ - au_writel(0x00000000, 0xAE00001C); + /* Jump to the reset vector */ + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); } static void xxs1500_power_off(void) -- 1.7.1 From rdsandiford@googlemail.com Mon Feb 21 20:45:53 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 21 Feb 2011 20:45:56 +0100 (CET) Received: from mail-ew0-f53.google.com ([209.85.215.53]:54967 "EHLO mail-ew0-f53.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491079Ab1BUTpx (ORCPT ); Mon, 21 Feb 2011 20:45:53 +0100 Received: by ewy7 with SMTP id 7so704896ewy.26 for ; Mon, 21 Feb 2011 11:45:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:from:to:mail-followup-to:cc:subject:references :date:in-reply-to:message-id:user-agent:mime-version:content-type; bh=wylP01Qfd/4b9W2GtKTd3CXo6gPJ/zAGdUD3QXzwDOs=; b=tr1Meluh5YuwqpADNef6gCcS6HXUZlNqGXc+zENx/I0QBOOgA9DgAO4dEVgTe/wnd6 0wCJzRemQ8GhrgKYfwo1zPeznw38sgL8JYz1O9d1lUtOE+k6KYC4Gj1YfkpjfByorq19 1pIcHVAQnmcY9epAfPmKcZfSbf9U1eGD2MWvM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-type; b=rgve48zksyopJdQDGYjlXdeGEd2NNoY9kaDPdWwjPCdhkSfB15laRLIeKDcxAg/VWy jBw3/dTBojwWb6grpcSfZfTyXpCQ8biu1wjWn03sP3ajyFyb/MzERNNxYHgYZLKPZIep 5idEPEHdcFULyANVH9NbBJB2hzktLxgn8/TQw= Received: by 10.213.17.133 with SMTP id s5mr315888eba.76.1298317547858; Mon, 21 Feb 2011 11:45:47 -0800 (PST) Received: from localhost (rsandifo.gotadsl.co.uk [82.133.89.107]) by mx.google.com with ESMTPS id t5sm5209579eeh.2.2011.02.21.11.45.45 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 21 Feb 2011 11:45:46 -0800 (PST) From: Richard Sandiford To: David Daney Mail-Followup-To: David Daney ,linux-mips , GCC , binutils , Prasun Kapoor , rdsandiford@googlemail.com Cc: linux-mips , GCC , binutils , Prasun Kapoor Subject: Re: RFC: A new MIPS64 ABI References: <4D5990A4.2050308__41923.1521235362$1297715435$gmane$org@caviumnetworks.com> Date: Mon, 21 Feb 2011 19:45:41 +0000 In-Reply-To: <4D5990A4.2050308__41923.1521235362$1297715435$gmane$org@caviumnetworks.com> (David Daney's message of "Mon, 14 Feb 2011 12:29:24 -0800") Message-ID: <87hbbxqihm.fsf@firetop.home> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29236 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips David Daney writes: > Background: > > Current MIPS 32-bit ABIs (both o32 and n32) are restricted to 2GB of > user virtual memory space. This is due the way MIPS32 memory space is > segmented. Only the range from 0..2^31-1 is available. Pointer > values are always sign extended. > > Because there are not already enough MIPS ABIs, I present the ... > > Proposal: A new ABI to support 4GB of address space with 32-bit > pointers. FWIW, I'd be happy to see this go into GCC. Richard From br1@einfach.org Mon Feb 21 21:38:34 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 21 Feb 2011 21:38:37 +0100 (CET) Received: from postler.einfach.org ([86.59.21.14]:47200 "EHLO home.einfach.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491083Ab1BUUie (ORCPT ); Mon, 21 Feb 2011 21:38:34 +0100 Received: from home.einfach.org (localhost [127.0.0.1]) by home.einfach.org (Postfix) with ESMTP id 78EF3A2513; Mon, 21 Feb 2011 21:38:27 +0100 (CET) Received: from webmail.einfach.org (localhost [127.0.0.1]) by home.einfach.org (Postfix) with ESMTP id 5F8B17A577; Mon, 21 Feb 2011 21:38:27 +0100 (CET) Received: from 186.42.233.164 (SquirrelMail authenticated user br1@einfach.org) by webmail.einfach.org with HTTP; Mon, 21 Feb 2011 21:38:27 +0100 Message-ID: <02e6152682aed8348b84dac4508bef70.squirrel@webmail.einfach.org> In-Reply-To: <201102211428.02125.florian@openwrt.org> References: <201102211428.02125.florian@openwrt.org> Date: Mon, 21 Feb 2011 21:38:27 +0100 Subject: Re: [PATCH] Alchemy: fix reset for MTX-1 and XXS1500 From: br1@einfach.org To: "Florian Fainelli" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, br1@einfach.org User-Agent: SquirrelMail/1.4.21 MIME-Version: 1.0 Content-Type: text/plain;charset=iso-8859-15 Content-Transfer-Encoding: 8bit X-Priority: 3 (Normal) Importance: Normal Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29237 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: br1@einfach.org Precedence: bulk X-list: linux-mips > Since commit 32fd6901 (MIPS: Alchemy: get rid of common/reset.c) > Alchemy-based boards use their own reset function. For MTX-1 and XXS1500, > the reset function pokes at the BCSR.SYSTEM_RESET register, but this does > not work. According to Bruno Randolf, this was not tested when written. Well, I don´t know wether it was tested or not, but since it doesn´t work i think we can assume it wasn´t. > Previously, the generic au1000_restart() routine called the board specific > reset function, which for MTX-1 and XXS1500 did not work, but finally made > a jump to the reset vector, which really triggers a system restart. Fix > reboot for both targets by jumping to the reset vector. > > CC: Bruno Randolf > CC: stable@kernel.org > Signed-off-by: Florian Fainelli > --- > Stable: 2.6.34+ > > diff --git a/arch/mips/alchemy/mtx-1/board_setup.c > b/arch/mips/alchemy/mtx-1/board_setup.c > index 6398fa9..40b84b9 100644 > --- a/arch/mips/alchemy/mtx-1/board_setup.c > +++ b/arch/mips/alchemy/mtx-1/board_setup.c > @@ -54,8 +54,8 @@ int mtx1_pci_idsel(unsigned int devsel, int assert); > > static void mtx1_reset(char *c) > { > - /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ > - au_writel(0x00000000, 0xAE00001C); > + /* Jump to the reset vector */ > + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); > } > > static void mtx1_power_off(void) > diff --git a/arch/mips/alchemy/xxs1500/board_setup.c > b/arch/mips/alchemy/xxs1500/board_setup.c > index b43c918..80c521e 100644 > --- a/arch/mips/alchemy/xxs1500/board_setup.c > +++ b/arch/mips/alchemy/xxs1500/board_setup.c > @@ -36,8 +36,8 @@ > > static void xxs1500_reset(char *c) > { > - /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ > - au_writel(0x00000000, 0xAE00001C); > + /* Jump to the reset vector */ > + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); > } > > static void xxs1500_power_off(void) > -- > 1.7.1 > > Acked-by: Bruno Randolf From anoop.pa@gmail.com Tue Feb 22 07:19:07 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 07:19:12 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:33660 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491142Ab1BVGTH (ORCPT ); Tue, 22 Feb 2011 07:19:07 +0100 Received: by ywa8 with SMTP id 8so706156ywa.36 for ; Mon, 21 Feb 2011 22:19:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=YoJ4KQyYyjWGBSfsy7P2T3tquDjDzaKFHxYRSF9l8tw=; b=K2AGtkNWTO7pGAfBBPU6tFlKFXQPQX8qPmIXCUnNF5weP37EXfByINAPCkepWnzmtY Gz/e/BJ9FXE3NJrvXhTsmB7qFxloknkDzjhVj/8pcPMYoWrj24X8rJaNtE5uYrh9eBmA dxBPjcTBZJWOUShthbo00jPuZCf1IlzNXhIek= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Uq8vAIJ7KXAjf3bU6dqjZs4+J18CTP4uUWP1eTlyGwsk/tO2qAYFhD0aqRXUQ6RZWI 9Rl40acpSxRp2WshvZSuzVECesU4fXnKtXRUH1eNvQxf4E18FcZ9vgAFo9bnLaPXnrsi f0mAjHy3ljlmtsR58JfHepfFS0vBUx3rJLRS4= Received: by 10.150.52.3 with SMTP id z3mr2822451ybz.401.1298355540571; Mon, 21 Feb 2011 22:19:00 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id u27sm2866262yba.3.2011.02.21.22.18.56 (version=SSLv3 cipher=OTHER); Mon, 21 Feb 2011 22:18:59 -0800 (PST) From: "Anoop P.A" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Anoop P A Subject: [PATCH resend] Make msp7120_reset generic Date: Tue, 22 Feb 2011 12:11:45 +0530 Message-Id: <1298356905-17316-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <4D610B3A.5070705@mvista.com> References: <4D610B3A.5070705@mvista.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29238 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop P A Remove platform dependency code from msp7120 reset code and make it generic. Now the code can be reused for other boards running msp71xx family SoC. Signed-off-by: Anoop P A --- Fixing comments indentations as suggested by sergei arch/mips/pmc-sierra/msp71xx/msp_setup.c | 84 ++++++++++++++++++------------ 1 files changed, 51 insertions(+), 33 deletions(-) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index fb37a10..3bf92cd 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -18,30 +18,32 @@ #include #include +#include #if defined(CONFIG_PMC_MSP7120_GW) -#include + /* GPIO 9 is the 4th GPIO of register 3*/ #define MSP_BOARD_RESET_GPIO 9 +#else +#undef MSP_BOARD_RESET_GPIO #endif extern void msp_serial_setup(void); extern void pmctwiled_setup(void); -#if defined(CONFIG_PMC_MSP7120_EVAL) || \ - defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) /* - * Performs the reset for MSP7120-based boards + * Performs the reset for MSP71xx-based boards */ -void msp7120_reset(void) +void msp71xx_reset(void) { void *start, *end, *iptr; register int i; + register u32 temp __maybe_unused; /* Diasble all interrupts */ local_irq_disable(); #ifdef CONFIG_SYS_SUPPORTS_MULTITHREADING dvpe(); + dmt(); #endif /* Cache the reset code of this function */ @@ -78,49 +80,56 @@ void msp7120_reset(void) /* Wait a bit for the DDRC to settle */ for (i = 0; i < 100000000; i++); -#if defined(CONFIG_PMC_MSP7120_GW) +#if defined(MSP_BOARD_RESET_GPIO) /* - * Set GPIO 9 HI, (tied to board reset logic) - * GPIO 9 is the 4th GPIO of register 3 + * Set reset GPIO HI, (tied to board reset logic) * * NOTE: We cannot use the higher-level msp_gpio_mode()/out() * as GPIO char driver may not be enabled and it would look up * data inRAM! */ - set_value_reg32(GPIO_CFG3_REG, 0xf000, 0x8000); - set_reg32(GPIO_DATA3_REG, 8); + temp = __raw_readl(MSP_GPIO_MODE_REGISTER[MSP_BOARD_RESET_GPIO]) & + ~BASIC_MODE_MASK(MSP_BOARD_RESET_GPIO); + __raw_writel(temp | BASIC_MODE(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO), + MSP_GPIO_MODE_REGISTER[MSP_BOARD_RESET_GPIO]); + /* Now set the reset gpio pin hi */ + temp = __raw_readl(MSP_GPIO_DATA_REGISTER[MSP_BOARD_RESET_GPIO]); + __raw_writel(temp | BASIC_DATA_MASK(MSP_BOARD_RESET_GPIO), + MSP_GPIO_DATA_REGISTER[MSP_BOARD_RESET_GPIO]); /* - * In case GPIO9 doesn't reset the board (jumper configurable!) + * In case GPIO doesn't reset the board (jumper configurable!) * fallback to device reset below. */ #endif - /* Set bit 1 of the MSP7120 reset register */ - *RST_SET_REG = 0x00000001; + /* Set bit 1 of the MSP71xx reset register */ + __raw_writel(0x00000001, RST_SET_REG); __asm__ __volatile__ ( - "endpoint: \n" + "endpoint:\n" ); } -#endif void msp_restart(char *command) { - printk(KERN_WARNING "Now rebooting .......\n"); -#if defined(CONFIG_PMC_MSP7120_EVAL) || \ - defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) - msp7120_reset(); -#else - /* No chip-specific reset code, just jump to the ROM reset vector */ - set_c0_status(ST0_BEV | ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -#endif + unsigned long family = identify_family(); + switch (family) { + case FAMILY_MSP7100: + msp71xx_reset(); + break; + default: + /* No chip-specific reset code, just jump + * to the ROM reset vector + */ + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + + __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); + break; + } } void msp_halt(void) @@ -141,9 +150,7 @@ void msp_power_off(void) void __init plat_mem_setup(void) { - _machine_restart = msp_restart; - _machine_halt = msp_halt; - pm_power_off = msp_power_off; + /*TODO: Move mem setup here */ } extern struct plat_smp_ops msp_smtc_smp_ops; @@ -244,3 +251,14 @@ void __init prom_init(void) pmctwiled_setup(); #endif } + +static int __init mips_reboot_setup(void) +{ + _machine_restart = msp_restart; + _machine_halt = msp_halt; + pm_power_off = msp_power_off; + + return 0; +} + +arch_initcall(mips_reboot_setup); -- 1.7.0.4 From anoop.pa@gmail.com Tue Feb 22 15:58:28 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 15:58:32 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:64306 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491758Ab1BVO62 (ORCPT ); Tue, 22 Feb 2011 15:58:28 +0100 Received: by fxm16 with SMTP id 16so3820519fxm.36 for ; Tue, 22 Feb 2011 06:58:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=fuvGP94NaRfSwHiZtYBZMpJYZHLZxuKdiqZNeFBe1XY=; b=SMr+2u1n1N8kSYcaCseEPwMXKKdHSHCPGU3THcvlgjFd9B0TnNRu3xpfOoFCcYuCoN SBfFC/DRdKpGUGdCfQCiIcuSU0H6TYWXITRp6rS+GSjpLrHYQVc+QDvAOTiIfmGQkdxs 0+aOcVjTcSdOLx5nq8a316openwRx5LpVFC6s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=ff9rLV+cRMh5lqLOLWcNZSk6RtLXfHMW4zwvIF3ndy+WRpNg9M0ADJd8n6eHYSpH/V AhC/igoBIrLzHo0WHH69X2swWKUYzw/kMR4qbAqtDWEw/OhOWLDAbvIovnXkqC9wJUkw 8M1b1RrcBQkOC4rddOrpXgphNY9s7vN3eIDCY= Received: by 10.223.61.133 with SMTP id t5mr123499fah.103.1298386703297; Tue, 22 Feb 2011 06:58:23 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id n3sm3067021faa.29.2011.02.22.06.58.20 (version=SSLv3 cipher=OTHER); Tue, 22 Feb 2011 06:58:22 -0800 (PST) From: "Anoop P.A" To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Anoop P A Subject: [PATCH] MSP82XX pci support. Add pci fixup entries for MSP82XX Acadia board. Date: Tue, 22 Feb 2011 20:51:28 +0530 Message-Id: <1298388088-11338-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29239 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop P A Signed-off-by: Anoop P A --- arch/mips/pci/fixup-pmcmsp.c | 42 +++++++++++++++++++++++++++++++++++++++--- 1 files changed, 39 insertions(+), 3 deletions(-) diff --git a/arch/mips/pci/fixup-pmcmsp.c b/arch/mips/pci/fixup-pmcmsp.c index 65735b1..6569e70 100644 --- a/arch/mips/pci/fixup-pmcmsp.c +++ b/arch/mips/pci/fixup-pmcmsp.c @@ -122,6 +122,45 @@ static char irq_tab[][5] __initdata = { {0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */ }; +#elif defined(CONFIG_PMC_MSP82XX_ACADIA) + +/* Acadia Board IRQ wiring to PCI slots */ +static char irq_tab[][5] __initdata = { + /*INTA INTB INTC INTD */ + {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */ + {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */ + {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */ + {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */ + {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */ + {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */ + {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */ + {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */ + {0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */ + {0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */ + {0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */ + {0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */ + {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */ + {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */ + {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */ + {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */ + {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */ + {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */ + {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */ + {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */ + {0, IRQ5, IRQ5, 0, 0 }, /* 18 (AD[28]): slot 0 */ + {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */ + {0, IRQ4, IRQ4, 0, 0 }, /* 20 (AD[30]): slot 1*/ + {0, 0, 0, 0, 0 }, /* 21 (AD[31]): Unused */ +}; + #else /* Unknown board -- don't assign any IRQs */ @@ -204,9 +243,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) ****************************************************************************/ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { -#if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL) - printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n"); -#endif printk(KERN_WARNING "PCI: irq_tab returned %d for slot=%d pin=%d\n", irq_tab[slot][pin], slot, pin); -- 1.7.0.4 From anoop.pa@gmail.com Tue Feb 22 15:59:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 15:59:35 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:49396 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491758Ab1BVO7b (ORCPT ); Tue, 22 Feb 2011 15:59:31 +0100 Received: by fxm16 with SMTP id 16so3821533fxm.36 for ; Tue, 22 Feb 2011 06:59:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=nVnAKaU/qwB/fxqhtcP4XhyOPzG2HdRkTY5cuQCYQ5g=; b=NJibr+tLqWVVJvAaLxlHk9By2QJ/fosNsVSBiLPxj4sAg/TPk0rrviS973pwV6/8Wv BWibYuG6R992w6YGKkRcNzwPm39lnU8MFlKPMcnNtjUgOKz2Tf+hi9zQgWs8RXN/U+rV l7kcBQcA+mYluSPTzZeyt+kxSFNYw8MHgmw3o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=vJfu2DbgMZadOKaQ6zjCH7dgNwDpitxkdrhJbGJ71qGdEbWnuA+7YYAMkeKcsymrT5 PYILA6UKtiIssZg8Ni6pi428lrxNKXAjlZADusZnQFOzRP6UcYGq2iR6duFNphjhjGc0 2ERgFo1fop0QOBf4X3ChJ0hYzuCMo6hWXB2YA= Received: by 10.223.63.75 with SMTP id a11mr592876fai.88.1298386651416; Tue, 22 Feb 2011 06:57:31 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id a2sm1806725faw.22.2011.02.22.06.57.26 (version=SSLv3 cipher=OTHER); Tue, 22 Feb 2011 06:57:30 -0800 (PST) From: "Anoop P.A" To: ralf@linux-mips.org, ars@metafoo.de, ddaney@caviumnetworks.com, tj@kernel.org, yuasa@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: Anoop P A Subject: [PATCH] MSP82XX Acadia board support. Date: Tue, 22 Feb 2011 20:50:26 +0530 Message-Id: <1298388026-11221-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29240 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop P A MSP82XX series of processors comes under MSP7100 family. Currently couple of SoC's (MSP8210 and MSP8220) available in this series. Signed-off-by: Anoop P A --- This patch depends on following two patches http://patchwork.linux-mips.org/patch/2094/ http://patchwork.linux-mips.org/patch/2073/ arch/mips/include/asm/bootinfo.h | 1 + arch/mips/pmc-sierra/Kconfig | 38 ++++++++++++++++++++++++++++++ arch/mips/pmc-sierra/msp71xx/msp_irq.c | 9 ++++++- arch/mips/pmc-sierra/msp71xx/msp_prom.c | 6 ++++ arch/mips/pmc-sierra/msp71xx/msp_setup.c | 4 ++- arch/mips/pmc-sierra/msp71xx/msp_time.c | 2 + 6 files changed, 58 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index 35cd1ba..3604102 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -50,6 +50,7 @@ #define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */ #define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ +#define MACH_MSP82XX_ACADIA 9 /* PMC-Sierra MSP82XX Acadia */ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ /* diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig index d4984c3..0147b01 100644 --- a/arch/mips/pmc-sierra/Kconfig +++ b/arch/mips/pmc-sierra/Kconfig @@ -32,12 +32,50 @@ config PMC_MSP7120_FPGA select IRQ_MSP_CIC select MSP_HAS_PCI +config PMC_MSP8210 + bool "PMC-Sierra MSP8210 SoC" + select PMC_MSP82XX_ACADIA + help + Support for the PMC-Sierra MSP8210 System-on-a-Chip with + custom mips 34Kc core (7 TC) cpu. + For info http://www.pmc-sierra.com/products/details/msp8210/ + +config PMC_MSP8220 + bool "PMC-Sierra MSP8220 Security SoC" + select PMC_MSP82XX_ACADIA + select MSP_HAS_SEC + help + Support for the PMC-Sierra MSP8220 System-on-a-Chip with + custom mips 34Kc core (7 TC) cpu and IPSEC accelartion engine. + For info http://www.pmc-sierra.com/products/details/msp8220/ + endchoice config HYPERTRANSPORT bool "Hypertransport Support for PMC-Sierra Yosemite" depends on PMC_YOSEMITE +config PMC_MSP82XX_ACADIA + select SYS_SUPPORTS_MULTITHREADING + select IRQ_MSP_CIC + select HW_HAS_CARB + select DMA_TO_SPRAM + select MSP_HAS_DUAL_USB + select MSP_HAS_TSMAC + select MSP_HAS_PCI + bool + +config MSP_HAS_DUAL_USB + select MSP_HAS_USB + bool + +config MSP_HAS_TSMAC + select MSP_HAS_MAC + bool + +config MSP_HAS_SEC + bool + config MSP_HAS_USB boolean depends on PMC_MSP diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c b/arch/mips/pmc-sierra/msp71xx/msp_irq.c index 4531c4a..5b74d3a 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c @@ -37,7 +37,9 @@ static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); } static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); } static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); } static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); } +#ifndef CONFIG_PMC_MSP8210 static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); } +#endif /* * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded @@ -79,8 +81,10 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs) else if (pending & C_IRQ3) do_IRQ(MSP_INT_SAR); +#ifndef CONFIG_PMC_MSP8210 else if (pending & C_IRQ5) do_IRQ(MSP_INT_SEC); +#endif #else if (pending & C_IRQ5) @@ -133,7 +137,9 @@ void __init arch_init_irq(void) set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch); set_vi_handler(MSP_INT_SAR, mac2_int_dispatch); set_vi_handler(MSP_INT_USB, usb_int_dispatch); +#ifndef CONFIG_PMC_MSP8210 set_vi_handler(MSP_INT_SEC, sec_int_dispatch); +#endif #ifdef CONFIG_MIPS_MT_SMP msp_vsmp_int_init(); #elif defined CONFIG_MIPS_MT_SMTC @@ -142,8 +148,9 @@ void __init arch_init_irq(void) irq_hwmask[MSP_INT_MAC1] = C_IRQ1; irq_hwmask[MSP_INT_USB] = C_IRQ2; irq_hwmask[MSP_INT_SAR] = C_IRQ3; +#ifndef CONFIG_PMC_MSP8210 irq_hwmask[MSP_INT_SEC] = C_IRQ5; - +#endif #endif /* CONFIG_MIPS_MT_SMP */ #endif /* CONFIG_MIPS_MT */ /* setup the cascaded interrupts */ diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c index db00deb..adf8f3b 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_prom.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c @@ -71,6 +71,8 @@ static char msp_default_features[] = "EMEMSP"; #elif defined(CONFIG_PMC_MSP7120_FPGA) "EMEM"; +#elif defined(CONFIG_PMC_MSP82XX_ACADIA) + "EGEGEGSP"; #endif /* conversion functions */ @@ -132,6 +134,10 @@ const char *get_system_type(void) return "PMC-Sierra MSP7120 Residential Gateway"; #elif defined(CONFIG_PMC_MSP7120_FPGA) return "PMC-Sierra MSP7120 FPGA"; +#elif defined(CONFIG_PMC_MSP8210) + return "PMC-Sierra MSP8210 SoC"; +#elif defined(CONFIG_PMC_MSP8220) + return "PMC-Sierra MSP8220 SoC"; #else #error "What is the type of *your* MSP?" #endif diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index 3bf92cd..406353d 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -20,7 +20,7 @@ #include #include -#if defined(CONFIG_PMC_MSP7120_GW) +#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP82XX_ACADIA) /* GPIO 9 is the 4th GPIO of register 3*/ #define MSP_BOARD_RESET_GPIO 9 #else @@ -203,6 +203,8 @@ void __init prom_init(void) mips_machtype = MACH_MSP7120_EVAL; #elif defined(CONFIG_PMC_MSP7120_GW) mips_machtype = MACH_MSP7120_GW; +#elif defined(CONFIG_PMC_MSP82XX_ACADIA) + mips_machtype = MACH_MSP82XX_ACADIA; #else mips_machtype = MACH_MSP_OTHER; #endif diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index 8b42f30..929c18a 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -74,6 +74,8 @@ void __init plat_time_init(void) cpu_rate = 400000000; #elif defined(CONFIG_PMC_MSP7120_FPGA) cpu_rate = 25000000; +#elif defined(CONFIG_PMC_MSP82XX_ACADIA) + cpu_rate = 60000000; #else cpu_rate = 150000000; #endif -- 1.7.0.4 From anoop.pa@gmail.com Tue Feb 22 16:13:27 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 16:13:31 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:45260 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491124Ab1BVPN1 (ORCPT ); Tue, 22 Feb 2011 16:13:27 +0100 Received: by fxm16 with SMTP id 16so3835907fxm.36 for ; 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Tue, 22 Feb 2011 07:12:32 -0800 (PST) From: "Anoop P.A" To: "gregkh @ suse . de" , "dbrownell @ users . sourceforge . net" , "stern @ rowland . harvard . edu" , "pkondeti @ codeaurora . org" , "jacob . jun . pan @ intel . com" , "linux-usb @ vger . kernel . org" , "alek . du @ intel . com" , "linux-kernel @ vger . kernel . org" , "gadiyar @ ti . com" , "ralf @ linux-mips . org" , "linux-mips @ linux-mips . org" , Greg KH Cc: anoop.pa@gmail.com Subject: [PATCH v5] EHCI bus glue for on-chip PMC MSP USB controller Date: Tue, 22 Feb 2011 21:05:33 +0530 Message-Id: <1298388933-13707-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <4D5ABB65.3090101@parrot.com> References: <4D5ABB65.3090101@parrot.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29241 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips From: Anoop This patch add bus glue for USB controller commonly found in PMC-Sierra MSP71xx family of SoC's. Signed-off-by: Anoop P A --- Changes. ehci-pmcmsp.c is based on latest ehci-pci.c.Addressed some stylistic issue pointed by Greg. Addressed comments from Matthieu CASTET. drivers/usb/host/Kconfig | 15 +- drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-pmcmsp.c | 524 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 542 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/host/ehci-pmcmsp.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0e6afa2..1b01c99 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -91,17 +91,28 @@ config USB_EHCI_TT_NEWSCHED If unsure, say Y. +config USB_EHCI_HCD_PMC_MSP + tristate "EHCI support for on-chip PMC MSP USB controller" + depends on USB_EHCI_HCD && MSP_HAS_USB + default y + select USB_EHCI_BIG_ENDIAN_DESC + select USB_EHCI_BIG_ENDIAN_MMIO + ---help--- + Enables support for the onchip USB controller on the PMC_MSP7100 Family SoC's. + If unsure, say N. + config USB_EHCI_BIG_ENDIAN_MMIO bool depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ - PPC_MPC512x || CPU_CAVIUM_OCTEON) + PPC_MPC512x || CPU_CAVIUM_OCTEON || \ + PMC_MSP) default y config USB_EHCI_BIG_ENDIAN_DESC bool depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ - PPC_MPC512x) + PPC_MPC512x || PMC_MSP) default y config XPS_USB_HCD_XILINX diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index cbf451a..196050a 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1250,6 +1250,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_msm_driver #endif +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP +#include "ehci-pmcmsp.c" +#define PLATFORM_DRIVER ehci_hcd_msp_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c new file mode 100644 index 0000000..b157f19 --- /dev/null +++ b/drivers/usb/host/ehci-pmcmsp.c @@ -0,0 +1,524 @@ +/* + * PMC MSP EHCI (Host Controller Driver) for USB. + * + * (C) Copyright 2006-2010 PMC-Sierra Inc + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +/* includes */ +#include +#include +#include +#include + +/* stream disable*/ +#define USB_CTRL_MODE_STREAM_DISABLE 0x10 + +/* threshold */ +#define USB_CTRL_FIFO_THRESH 0x00300000 + +/* register offset for usb_mode */ +#define USB_EHCI_REG_USB_MODE 0x68 + +/* register offset for usb fifo */ +#define USB_EHCI_REG_USB_FIFO 0x24 + +/* register offset for usb status */ +#define USB_EHCI_REG_USB_STATUS 0x44 + +/* serial/parallel transceiver */ +#define USB_EHCI_REG_BIT_STAT_STS (1<<29) + +/* TWI USB0 host device pin */ +#define MSP_PIN_USB0_HOST_DEV 49 + +/* TWI USB1 host device pin */ +#define MSP_PIN_USB1_HOST_DEV 50 + + +static void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) +{ + u8 *base; + u8 *statreg; + u8 *fiforeg; + u32 val; + struct ehci_regs *reg_base = ehci->regs; + + /* get register base */ + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; + + /* Disable controller mode stream */ + val = ehci_readl(ehci, (u32 *)base); + ehci_writel(ehci, (val | USB_CTRL_MODE_STREAM_DISABLE), + (u32 *)base); + + /* clear STS to select parallel transceiver interface */ + val = ehci_readl(ehci, (u32 *)statreg); + val = val & ~USB_EHCI_REG_BIT_STAT_STS; + ehci_writel(ehci, val, (u32 *)statreg); + + /* write to set the proper fifo threshold */ + ehci_writel(ehci, USB_CTRL_FIFO_THRESH, (u32 *)fiforeg); + + /* set TWI GPIO USB_HOST_DEV pin high */ + gpio_direction_output(MSP_PIN_USB0_HOST_DEV, 1); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1); +#endif +} + +/* called after powerup, by probe or system-pm "wakeup" */ +static int ehci_msp_reinit(struct ehci_hcd *ehci) +{ + ehci_port_power(ehci, 0); + + return 0; +} + +/* called during probe() after chip reset completes */ +static int ehci_msp_setup(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 temp; + int retval; + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + hcd->has_tt = 1; + + retval = ehci_halt(ehci); + if (retval) + return retval; + + ehci_reset(ehci); + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); + temp &= 0x0f; + if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { + ehci_dbg(ehci, "bogus port configuration: " + "cc=%d x pcc=%d < ports=%d\n", + HCS_N_CC(ehci->hcs_params), + HCS_N_PCC(ehci->hcs_params), + HCS_N_PORTS(ehci->hcs_params)); + } + + usb_hcd_tdi_set_mode(ehci); + retval = ehci_msp_reinit(ehci); + + return retval; +} + +/*-------------------------------------------------------------------------*/ + +static void msp_start_hc(struct platform_device *dev) +{ +} + +static void msp_stop_hc(struct platform_device *dev) +{ +} + + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_PM + +/* suspend/resume, section 4.3 */ + +/* These routines rely on the bus glue + * to handle powerdown and wakeup, and currently also on + * transceivers that don't need any software attention to set up + * the right sort of wakeup. + * Also they depend on separate root hub suspend/resume. + */ +static int ehci_msp_suspend(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + unsigned long flags; + int rc; + + return 0; + rc = 0; + + if (time_before(jiffies, ehci->next_statechange)) + usleep(10000); + + /* Root hub was already suspended. Disable irq emission and + * mark HW unaccessible. The PM and USB cores make sure that + * the root hub is either suspended or stopped. + */ + spin_lock_irqsave(&ehci->lock, flags); + ehci_prepare_ports_for_controller_suspend(ehci, device_may_wakeup(dev)); + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + (void)ehci_readl(ehci, &ehci->regs->intr_enable); + + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + spin_unlock_irqrestore(&ehci->lock, flags); + + return rc; +} + +static int ehci_msp_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + + if (time_before(jiffies, ehci->next_statechange)) + msleep(100); + + /* Mark hardware accessible again as we are out of D3 state by now */ + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + /* If CF is still set, we maintained PCI Vaux power. + * Just undo the effect of ehci_pci_suspend(). + */ + if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) { + int mask = INTR_MASK; + + ehci_prepare_ports_for_controller_resume(ehci); + if (!hcd->self.root_hub->do_remote_wakeup) + mask &= ~STS_PCD; + ehci_writel(ehci, mask, &ehci->regs->intr_enable); + ehci_readl(ehci, &ehci->regs->intr_enable); + return 0; + } + + ehci_dbg(ehci, "lost power, restarting\n"); + usb_root_hub_lost_power(hcd->self.root_hub); + + /* Else reset, to cope with power loss or flush-to-storage + * style "resume" having let BIOS kick in during reboot. + */ + (void) ehci_halt(ehci); + (void) ehci_reset(ehci); + (void) ehci_msp_reinit(ehci); + + /* emptying the schedule aborts any urbs */ + spin_lock_irq(&ehci->lock); + if (ehci->reclaim) + end_unlink_async(ehci); + ehci_work(ehci); + spin_unlock_irq(&ehci->lock); + + ehci_writel(ehci, ehci->command, &ehci->regs->command); + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ + + /* here we "know" root ports should always stay powered */ + ehci_port_power(ehci, 1); + + hcd->state = HC_STATE_SUSPENDED; + + return 0; +} + +static const struct dev_pm_ops ehci_msp_pmops = { + .suspend = ehci_msp_suspend, + .resume = ehci_msp_resume, +}; +#endif + + +/* configure so an HC device and id are always provided + * always called with process context; sleeping is OK + */ + +static int usb_hcd_msp_map_regs(struct mspusb_device *dev) +{ + struct resource *res; + struct platform_device *pdev = &dev->dev; + u32 res_len; + int retval; + + /* MAB register space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res == NULL) + return -ENOMEM; + res_len = res->end - res->start + 1; + if (!request_mem_region(res->start, res_len, "mab regs")) + return -EBUSY; + + dev->mab_regs = ioremap_nocache(res->start, res_len); + if (dev->mab_regs == NULL) { + retval = -ENOMEM; + goto err1; + } + + /* MSP USB register space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (res == NULL) { + retval = -ENOMEM; + goto err2; + } + res_len = res->end - res->start + 1; + if (!request_mem_region(res->start, res_len, "usbid regs")) { + retval = -EBUSY; + goto err2; + } + dev->usbid_regs = ioremap_nocache(res->start, res_len); + if (dev->usbid_regs == NULL) { + retval = -ENOMEM; + goto err3; + } + + return 0; +err3: + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + res_len = res->end - res->start + 1; + release_mem_region(res->start, res_len); +err2: + iounmap(dev->mab_regs); +err1: + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + res_len = res->end - res->start + 1; + release_mem_region(res->start, res_len); + dev_err(&pdev->dev, "Failed to map non-EHCI regs.\n"); + return retval; +} + +/** + * usb_hcd_msp_probe - initialize PMC MSP-based HCDs + * Context: !in_interrupt() + * + * Allocates basic resources for this USB host controller, and + * then invokes the start() method for the HCD associated with it + * through the hotplug entry's driver_data. + * + */ +int usb_hcd_msp_probe(const struct hc_driver *driver, + struct platform_device *dev) +{ + int retval; + struct usb_hcd *hcd; + struct resource *res; + struct ehci_hcd *ehci ; + + hcd = usb_create_hcd(driver, &dev->dev, "pmcmsp"); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (res == NULL) { + pr_debug("No IOMEM resource info for %s.\n", dev->name); + retval = -ENOMEM; + goto err1; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, dev->name)) { + retval = -EBUSY; + goto err1; + } + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed"); + retval = -ENOMEM; + goto err2; + } + msp_start_hc(dev); + + res = platform_get_resource(dev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&dev->dev, "No IRQ resource info for %s.\n", dev->name); + retval = -ENOMEM; + goto err3; + } + + /* Map non-EHCI register spaces */ + retval = usb_hcd_msp_map_regs(to_mspusb_device(dev)); + if (retval != 0) + goto err3; + + ehci = hcd_to_ehci(hcd); + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; + + + retval = usb_add_hcd(hcd, res->start, IRQF_SHARED); + if (retval == 0) + return 0; + + usb_remove_hcd(hcd); +err3: + msp_stop_hc(dev); + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + + return retval; +} + + + +/** + * usb_hcd_msp_remove - shutdown processing for PMC MSP-based HCDs + * @dev: USB Host Controller being removed + * Context: !in_interrupt() + * + * Reverses the effect of usb_hcd_msp_probe(), first invoking + * the HCD's stop() method. It is always called from a thread + * context, normally "rmmod", "apmd", or something similar. + * + * may be called without controller electrically present + * may be called with controller, bus, and devices active + */ +void usb_hcd_msp_remove(struct usb_hcd *hcd, struct platform_device *dev) +{ + usb_remove_hcd(hcd); + msp_stop_hc(dev); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); +} + +#ifdef CONFIG_MSP_HAS_DUAL_USB +/*-------------------------------------------------------------------------*/ +/* + * Wrapper around the main ehci_irq. Since both USB host controllers are + * sharing the same IRQ, need to first determine whether we're the intended + * recipient of this interrupt. + */ +static irqreturn_t ehci_msp_irq(struct usb_hcd *hcd) +{ + u32 int_src; + struct device *dev = hcd->self.controller; + struct platform_device *pdev; + struct mspusb_device *mdev; + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + /* need to reverse-map a couple of containers to get our device */ + pdev = to_platform_device(dev); + mdev = to_mspusb_device(pdev); + + /* Check to see if this interrupt is for this host controller */ + int_src = ehci_readl(ehci, &mdev->mab_regs->int_stat); + if (int_src & (1 << pdev->id)) + return ehci_irq(hcd); + + /* Not for this device */ + return IRQ_NONE; +} +/*-------------------------------------------------------------------------*/ +#endif /* DUAL_USB */ + +static const struct hc_driver ehci_msp_hc_driver = { + .description = hcd_name, + .product_desc = "PMC MSP EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ +#ifdef CONFIG_MSP_HAS_DUAL_USB + .irq = ehci_msp_irq, +#else + .irq = ehci_irq, +#endif + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + */ + .reset = ehci_msp_setup, + .start = ehci_run, + .shutdown = ehci_shutdown, + .start = ehci_run, + .stop = ehci_stop, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_hcd_msp_drv_probe(struct platform_device *pdev) +{ + int ret; + + pr_debug("In ehci_hcd_msp_drv_probe"); + + if (usb_disabled()) + return -ENODEV; + + gpio_request(MSP_PIN_USB0_HOST_DEV, "USB0_HOST_DEV_GPIO"); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_request(MSP_PIN_USB1_HOST_DEV, "USB1_HOST_DEV_GPIO"); +#endif + + ret = usb_hcd_msp_probe(&ehci_msp_hc_driver, pdev); + + return ret; +} + +static int ehci_hcd_msp_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_hcd_msp_remove(hcd, pdev); + + /* free TWI GPIO USB_HOST_DEV pin */ + gpio_free(MSP_PIN_USB0_HOST_DEV); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_free(MSP_PIN_USB1_HOST_DEV); +#endif + + return 0; +} + +MODULE_ALIAS("pmcmsp-ehci"); + +static struct platform_driver ehci_hcd_msp_driver = { + .probe = ehci_hcd_msp_drv_probe, + .remove = ehci_hcd_msp_drv_remove, + .driver = { + .name = "pmcmsp-ehci", + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &ehci_msp_pmops, +#endif + }, +}; -- 1.7.0.4 From error27@gmail.com Tue Feb 22 21:04:58 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 21:05:01 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:33872 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491119Ab1BVUE6 (ORCPT ); Tue, 22 Feb 2011 21:04:58 +0100 Received: by ewy23 with SMTP id 23so1264808ewy.36 for ; Tue, 22 Feb 2011 12:04:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-type :content-disposition:in-reply-to:user-agent; bh=h5HlDlPTyK7dTHcd+n8CQaREA/YpXtWW9ZWwC0r1xhY=; b=CgaAcMgUId/UKR+2PjlJMwtqe80j0MGWkFZ15tGppZRW+w2+hm9VQKmlU3HpMoE8YI glD1rYFI4qBPHldVdinfeZLq3a908MTlkohasEQz7P/Z2xk6MY4vnJbflyPBhKA2eteJ 1SlghETiDdAaedCqyQvb8oGxBdSk4o9LxO6h0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:mail-followup-to:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; b=seewF4FLdSwS84LCnu/EuBxcoIIGGzs+D5vKor1D07C9KC0GFS5/bDPj8VzbsPXVVE Bi2yybcQ1lJFGYH9YXHFdX/vaCdvchjOJS+PUyrlkmWdKf8k3hMUDTtiRUkOup5+8gVW J6VN7EzaB8CdnY00egCHCmnicN82IlECB9gcs= Received: by 10.14.37.137 with SMTP id y9mr3466653eea.40.1298405091900; Tue, 22 Feb 2011 12:04:51 -0800 (PST) Received: from bicker ([212.49.88.34]) by mx.google.com with ESMTPS id t5sm6287975eeh.8.2011.02.22.12.04.39 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Feb 2011 12:04:50 -0800 (PST) Date: Tue, 22 Feb 2011 23:04:27 +0300 From: Dan Carpenter To: "Anoop P.A" Cc: "gregkh @ suse . de" , "dbrownell @ users . sourceforge . net" , "stern @ rowland . harvard . edu" , "pkondeti @ codeaurora . org" , "jacob . jun . pan @ intel . com" , "linux-usb @ vger . kernel . org" , "alek . du @ intel . com" , "linux-kernel @ vger . kernel . org" , "gadiyar @ ti . com" , "ralf @ linux-mips . org" , "linux-mips @ linux-mips . org" , Greg KH Subject: Re: [PATCH v5] EHCI bus glue for on-chip PMC MSP USB controller Message-ID: <20110222200427.GB1966@bicker> Mail-Followup-To: Dan Carpenter , "Anoop P.A" , "gregkh @ suse . de" , "dbrownell @ users . sourceforge . net" , "stern @ rowland . harvard . edu" , "pkondeti @ codeaurora . org" , "jacob . jun . pan @ intel . com" , "linux-usb @ vger . kernel . org" , "alek . du @ intel . com" , "linux-kernel @ vger . kernel . org" , "gadiyar @ ti . com" , "ralf @ linux-mips . org" , "linux-mips @ linux-mips . org" , Greg KH References: <4D5ABB65.3090101@parrot.com> <1298388933-13707-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1298388933-13707-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29242 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: error27@gmail.com Precedence: bulk X-list: linux-mips On Tue, Feb 22, 2011 at 09:05:33PM +0530, Anoop P.A wrote: > From: Anoop > > This patch add bus glue for USB controller commonly found in PMC-Sierra MSP71xx family of SoC's. > > > Signed-off-by: Anoop P A > --- > Changes. > ehci-pmcmsp.c is based on latest ehci-pci.c.Addressed some stylistic issue pointed by Greg. > Addressed comments from Matthieu CASTET. Could you spell that out more completely next time? > +config USB_EHCI_HCD_PMC_MSP > + tristate "EHCI support for on-chip PMC MSP USB controller" Better to say "EHCI support for on-chip PMC-Sierra MSP71xx USB controllers" > + depends on USB_EHCI_HCD && MSP_HAS_USB > + default y New features always default to No. > +#include Cannot find the msp_usb.h in linux-next. Doesn't compile. > +static void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) > +{ > + u8 *base; > + u8 *statreg; > + u8 *fiforeg; > + u32 val; > + struct ehci_regs *reg_base = ehci->regs; > + > + /* get register base */ > + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; > + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; > + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; > + > + /* Disable controller mode stream */ > + val = ehci_readl(ehci, (u32 *)base); It doesn't compile so I can't test this, but I think that this will cause a sparse warning. "base" should have an __iomem tag. Please run sparse on this driver. > +/* called after powerup, by probe or system-pm "wakeup" */ > +static int ehci_msp_reinit(struct ehci_hcd *ehci) > +{ > + ehci_port_power(ehci, 0); > + > + return 0; Better to make this function void. > +} > + > +/* called during probe() after chip reset completes */ > +static int ehci_msp_setup(struct usb_hcd *hcd) > +{ > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + u32 temp; > + int retval; Needs a blank line here to separate declarations from code. > + ehci->big_endian_mmio = 1; > + ehci->big_endian_desc = 1; > + > + ehci->caps = hcd->regs; > + ehci->regs = hcd->regs + > + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); [snip] > + /* data structure init */ > + retval = ehci_init(hcd); > + if (retval) > + return retval; > + > + temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); > + temp &= 0x0f; companion HCs * ports per CC & 0xf? What's the &= 0x0f for? It's left out of the printk. > + if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { > + ehci_dbg(ehci, "bogus port configuration: " > + "cc=%d x pcc=%d < ports=%d\n", > + HCS_N_CC(ehci->hcs_params), > + HCS_N_PCC(ehci->hcs_params), > + HCS_N_PORTS(ehci->hcs_params)); > + } [snip] > +/*-------------------------------------------------------------------------*/ No need for these blank comments. > + > +static void msp_start_hc(struct platform_device *dev) > +{ > +} > + > +static void msp_stop_hc(struct platform_device *dev) > +{ > +} > + I don't understand the point of these empty functions. > +static int ehci_msp_suspend(struct device *dev) > +{ > + struct usb_hcd *hcd = dev_get_drvdata(dev); > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > + unsigned long flags; > + int rc; > + > + return 0; > + rc = 0; > + > + if (time_before(jiffies, ehci->next_statechange)) > + usleep(10000); Is there still a usleep() function? Either way, can you send us something that compiles on linux-next? regards, dan carpenter From David.Daney@caviumnetworks.com Tue Feb 22 21:58:08 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 21:58:12 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13970 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491766Ab1BVU6I (ORCPT ); Tue, 22 Feb 2011 21:58:08 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:58:56 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:03 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:03 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKvw94020899; Tue, 22 Feb 2011 12:57:59 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKvuS2020898; Tue, 22 Feb 2011 12:57:56 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH 00/10] MIPS: Octeon: Use Device Tree. Date: Tue, 22 Feb 2011 12:57:44 -0800 Message-Id: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 22 Feb 2011 20:58:03.0738 (UTC) FILETIME=[32801BA0:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29243 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Background: The Octeon family of SOCs has a variety of on-chip controllers for Ethernet, MDIO, I2C, and several other I/O devices. These chips are used on boards with a great variety of different configurations. To date, the configuration and bus topology information has been hard coded in the drivers and support code. To facilitate supporting new chips and boards, we would like to make use use the Device Tree to encode the configuration information. I would like to get some feedback on the current code I am working with. The migration approach is as follows: o Several device tree templates are statically linked into the kernel image. Based on SOC type and board type one of these is selected in early boot. Legacy configuration probing code is used to prune and patch the device tree template. o New SOCs and boards will directly use a device tree passed by the bootloader (This patch set doesn't actually implement this, but it is trivial to add). 01/10 - Move configuration code to common place for use by Device Tree pruning and patching code. 02/10 - Add the statically linked Device Tree templates. 03/10 - Remove unused arch/mips/prom.c code that conflicts with following patches. 04/10 - irq_create_of_mapping() function. 05/10 - Rearrange legacy configuration code for following patch. 06/10 - Fix up Device Tree template for current environment. 07/10 - Convert I2C driver to use Device Tree. 08/10 - Convert MDIO driver to use Device Tree. 09/10 - Convert Ethernet mgmt driver to use Device Tree. 10/10 - Convert Octeon Ethernet driver to use Device Tree. David Daney (10): MIPS: Octeon: Move some Ethernet support files out of staging. MIPS: Octeon: Add device tree source files. MIPS: Prune some target specific code out of prom.c MIPS: Octeon: Add a irq_create_of_mapping() implementation. MIPS: Octeon: Rearrance CVMX files in preperation for device tree MIPS: Octeon: Initialize and fixup device tree. i2c: Convert i2c-octeon.c to use device tree. netdev: mdio-octeon.c: Convert to use device tree. netdev: octeon_mgmt: Convert to use device tree. staging: octeon_ethernet: Convert to use device tree. arch/mips/Kconfig | 2 + arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 13 + arch/mips/cavium-octeon/executive/Makefile | 5 + .../mips/cavium-octeon/executive}/cvmx-cmd-queue.c | 8 +- .../mips/cavium-octeon/executive}/cvmx-fpa.c | 0 .../cavium-octeon/executive}/cvmx-helper-board.c | 18 +- .../cavium-octeon/executive}/cvmx-helper-fpa.c | 0 .../cavium-octeon/executive}/cvmx-helper-loop.c | 6 +- .../cavium-octeon/executive}/cvmx-helper-npi.c | 6 +- .../cavium-octeon/executive}/cvmx-helper-rgmii.c | 17 +- .../cavium-octeon/executive}/cvmx-helper-sgmii.c | 18 +- .../cavium-octeon/executive}/cvmx-helper-spi.c | 20 +- .../cavium-octeon/executive}/cvmx-helper-util.c | 16 +- .../cavium-octeon/executive}/cvmx-helper-xaui.c | 32 +- .../mips/cavium-octeon/executive}/cvmx-helper.c | 120 ++++-- .../executive}/cvmx-interrupt-decodes.c | 10 +- .../cavium-octeon/executive}/cvmx-interrupt-rsl.c | 4 +- .../mips/cavium-octeon/executive}/cvmx-pko.c | 6 +- .../mips/cavium-octeon/executive}/cvmx-spi.c | 12 +- arch/mips/cavium-octeon/octeon-irq.c | 25 ++ arch/mips/cavium-octeon/octeon-platform.c | 456 ++++++++++++-------- arch/mips/cavium-octeon/octeon_3xxx.dts | 314 ++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 99 +++++ arch/mips/cavium-octeon/setup.c | 17 + .../mips/include/asm}/octeon/cvmx-address.h | 0 .../mips/include/asm}/octeon/cvmx-asxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-cmd-queue.h | 0 .../mips/include/asm}/octeon/cvmx-config.h | 0 .../mips/include/asm}/octeon/cvmx-dbg-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fau.h | 0 .../mips/include/asm}/octeon/cvmx-fpa-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-gmxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-helper-board.h | 0 .../mips/include/asm}/octeon/cvmx-helper-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-helper-loop.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-npi.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-rgmii.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-sgmii.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-spi.h | 1 + .../mips/include/asm}/octeon/cvmx-helper-util.h | 0 .../mips/include/asm}/octeon/cvmx-helper-xaui.h | 1 + .../mips/include/asm}/octeon/cvmx-helper.h | 1 + .../mips/include/asm}/octeon/cvmx-ipd.h | 0 .../mips/include/asm}/octeon/cvmx-mdio.h | 0 .../mips/include/asm}/octeon/cvmx-pcsx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pcsxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip.h | 0 .../mips/include/asm}/octeon/cvmx-pko-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pko.h | 0 .../mips/include/asm}/octeon/cvmx-pow.h | 0 .../mips/include/asm}/octeon/cvmx-scratch.h | 0 .../mips/include/asm}/octeon/cvmx-spi.h | 0 .../mips/include/asm}/octeon/cvmx-spxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-srxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-stxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-wqe.h | 0 arch/mips/include/asm/octeon/octeon.h | 5 - arch/mips/kernel/prom.c | 49 --- drivers/i2c/busses/i2c-octeon.c | 88 ++-- drivers/net/octeon/octeon_mgmt.c | 265 +++++++----- drivers/net/phy/mdio-octeon.c | 73 ++-- drivers/staging/octeon/Makefile | 5 - drivers/staging/octeon/cvmx-packet.h | 65 --- drivers/staging/octeon/cvmx-smix-defs.h | 178 -------- drivers/staging/octeon/ethernet-defines.h | 2 +- drivers/staging/octeon/ethernet-mdio.c | 31 +- drivers/staging/octeon/ethernet-mem.c | 2 +- drivers/staging/octeon/ethernet-rgmii.c | 4 +- drivers/staging/octeon/ethernet-rx.c | 14 +- drivers/staging/octeon/ethernet-rx.h | 2 +- drivers/staging/octeon/ethernet-sgmii.c | 4 +- drivers/staging/octeon/ethernet-spi.c | 6 +- drivers/staging/octeon/ethernet-tx.c | 12 +- drivers/staging/octeon/ethernet-xaui.c | 4 +- drivers/staging/octeon/ethernet.c | 115 +++-- drivers/staging/octeon/octeon-ethernet.h | 3 + 79 files changed, 1308 insertions(+), 852 deletions(-) create mode 100644 arch/mips/cavium-octeon/.gitignore rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-cmd-queue.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-board.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-loop.c (95%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-npi.c (96%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-rgmii.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-sgmii.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-spi.c (94%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-util.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-xaui.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper.c (93%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-decodes.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-rsl.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-pko.c (99%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-spi.c (99%) create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-address.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-asxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-cmd-queue.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-config.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-dbg-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fau.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-gmxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-board.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-loop.h (96%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-npi.h (96%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-rgmii.h (98%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-sgmii.h (98%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-spi.h (98%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-util.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-xaui.h (98%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper.h (99%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-ipd.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-mdio.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pow.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-scratch.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-srxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-stxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-wqe.h (100%) delete mode 100644 drivers/staging/octeon/cvmx-packet.h delete mode 100644 drivers/staging/octeon/cvmx-smix-defs.h -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 21:58:30 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 21:58:38 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13976 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491769Ab1BVU6T (ORCPT ); Tue, 22 Feb 2011 21:58:19 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:07 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:14 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:14 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKw2wh020903; Tue, 22 Feb 2011 12:58:02 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKw1o2020902; Tue, 22 Feb 2011 12:58:01 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH 01/10] MIPS: Octeon: Move some Ethernet support files out of staging. Date: Tue, 22 Feb 2011 12:57:45 -0800 Message-Id: <1298408274-20856-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:14.0800 (UTC) FILETIME=[39180900:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29244 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/cavium-octeon/executive/Makefile | 5 + .../mips/cavium-octeon/executive}/cvmx-cmd-queue.c | 8 +- .../mips/cavium-octeon/executive}/cvmx-fpa.c | 0 .../cavium-octeon/executive}/cvmx-helper-board.c | 18 +-- .../cavium-octeon/executive}/cvmx-helper-fpa.c | 0 .../cavium-octeon/executive}/cvmx-helper-loop.c | 6 +- .../cavium-octeon/executive}/cvmx-helper-npi.c | 6 +- .../cavium-octeon/executive}/cvmx-helper-rgmii.c | 17 +- .../cavium-octeon/executive}/cvmx-helper-sgmii.c | 12 +- .../cavium-octeon/executive}/cvmx-helper-spi.c | 10 +- .../cavium-octeon/executive}/cvmx-helper-util.c | 16 +- .../cavium-octeon/executive}/cvmx-helper-xaui.c | 10 +- .../mips/cavium-octeon/executive}/cvmx-helper.c | 27 ++-- .../executive}/cvmx-interrupt-decodes.c | 10 +- .../cavium-octeon/executive}/cvmx-interrupt-rsl.c | 4 +- .../mips/cavium-octeon/executive}/cvmx-pko.c | 6 +- .../mips/cavium-octeon/executive}/cvmx-spi.c | 12 +- .../mips/include/asm}/octeon/cvmx-address.h | 0 .../mips/include/asm}/octeon/cvmx-asxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-cmd-queue.h | 0 .../mips/include/asm}/octeon/cvmx-config.h | 0 .../mips/include/asm}/octeon/cvmx-dbg-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fau.h | 0 .../mips/include/asm}/octeon/cvmx-fpa-defs.h | 0 .../mips/include/asm}/octeon/cvmx-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-gmxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-helper-board.h | 0 .../mips/include/asm}/octeon/cvmx-helper-fpa.h | 0 .../mips/include/asm}/octeon/cvmx-helper-loop.h | 0 .../mips/include/asm}/octeon/cvmx-helper-npi.h | 0 .../mips/include/asm}/octeon/cvmx-helper-rgmii.h | 0 .../mips/include/asm}/octeon/cvmx-helper-sgmii.h | 0 .../mips/include/asm}/octeon/cvmx-helper-spi.h | 0 .../mips/include/asm}/octeon/cvmx-helper-util.h | 0 .../mips/include/asm}/octeon/cvmx-helper-xaui.h | 0 .../mips/include/asm}/octeon/cvmx-helper.h | 0 .../mips/include/asm}/octeon/cvmx-ipd.h | 0 .../mips/include/asm}/octeon/cvmx-mdio.h | 0 .../mips/include/asm}/octeon/cvmx-pcsx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pcsxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pip.h | 0 .../mips/include/asm}/octeon/cvmx-pko-defs.h | 0 .../mips/include/asm}/octeon/cvmx-pko.h | 0 .../mips/include/asm}/octeon/cvmx-pow.h | 0 .../mips/include/asm}/octeon/cvmx-scratch.h | 0 .../mips/include/asm}/octeon/cvmx-spi.h | 0 .../mips/include/asm}/octeon/cvmx-spxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-srxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-stxx-defs.h | 0 .../mips/include/asm}/octeon/cvmx-wqe.h | 0 drivers/staging/octeon/Makefile | 5 - drivers/staging/octeon/cvmx-packet.h | 65 ------- drivers/staging/octeon/cvmx-smix-defs.h | 178 -------------------- drivers/staging/octeon/ethernet-defines.h | 2 +- drivers/staging/octeon/ethernet-mdio.c | 4 +- drivers/staging/octeon/ethernet-mem.c | 2 +- drivers/staging/octeon/ethernet-rgmii.c | 4 +- drivers/staging/octeon/ethernet-rx.c | 14 +- drivers/staging/octeon/ethernet-rx.h | 2 +- drivers/staging/octeon/ethernet-sgmii.c | 4 +- drivers/staging/octeon/ethernet-spi.c | 6 +- drivers/staging/octeon/ethernet-tx.c | 12 +- drivers/staging/octeon/ethernet-xaui.c | 4 +- drivers/staging/octeon/ethernet.c | 14 +- 65 files changed, 116 insertions(+), 367 deletions(-) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-cmd-queue.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-board.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-fpa.c (100%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-loop.c (95%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-npi.c (96%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-rgmii.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-sgmii.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-spi.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-util.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper-xaui.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-helper.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-decodes.c (98%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-interrupt-rsl.c (97%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-pko.c (99%) rename {drivers/staging/octeon => arch/mips/cavium-octeon/executive}/cvmx-spi.c (99%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-address.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-asxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-cmd-queue.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-config.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-dbg-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fau.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-gmxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-board.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-fpa.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-loop.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-npi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-rgmii.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-sgmii.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-spi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-util.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper-xaui.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-helper.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-ipd.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-mdio.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pcsxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pip.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pko.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-pow.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-scratch.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spi.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-spxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-srxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-stxx-defs.h (100%) rename {drivers/staging => arch/mips/include/asm}/octeon/cvmx-wqe.h (100%) delete mode 100644 drivers/staging/octeon/cvmx-packet.h delete mode 100644 drivers/staging/octeon/cvmx-smix-defs.h diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile index 7f41c5b..eec0b88 100644 --- a/arch/mips/cavium-octeon/executive/Makefile +++ b/arch/mips/cavium-octeon/executive/Makefile @@ -10,5 +10,10 @@ # obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o +obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ + cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ + cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ + cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ + cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c similarity index 98% rename from drivers/staging/octeon/cvmx-cmd-queue.c rename to arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c index e9809d3..132bccc 100644 --- a/drivers/staging/octeon/cvmx-cmd-queue.c +++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c @@ -34,13 +34,13 @@ #include -#include "cvmx-config.h" -#include "cvmx-fpa.h" -#include "cvmx-cmd-queue.h" +#include +#include +#include #include #include -#include "cvmx-pko-defs.h" +#include /** * This application uses this pointer to access the global queue diff --git a/drivers/staging/octeon/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c similarity index 100% rename from drivers/staging/octeon/cvmx-fpa.c rename to arch/mips/cavium-octeon/executive/cvmx-fpa.c diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-board.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-board.c index 57d35dc..71590a3 100644 --- a/drivers/staging/octeon/cvmx-helper-board.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -34,16 +34,16 @@ #include #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" +#include -#include "cvmx-helper.h" -#include "cvmx-helper-util.h" -#include "cvmx-helper-board.h" +#include +#include +#include -#include "cvmx-gmxx-defs.h" -#include "cvmx-asxx-defs.h" +#include +#include /** * cvmx_override_board_link_get(int ipd_port) is a function @@ -493,7 +493,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_mdio_phy_reg_control_t reg_control; cvmx_mdio_phy_reg_status_t reg_status; cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; - cvmx_mdio_phy_reg_extended_status_t reg_extended_status; cvmx_mdio_phy_reg_control_1000_t reg_control_1000; reg_status.u16 = @@ -508,9 +507,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, reg_autoneg_adver.s.advert_100base_tx_full = 0; reg_autoneg_adver.s.advert_100base_tx_half = 0; if (reg_status.s.capable_extended_status) { - reg_extended_status.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_EXTENDED_STATUS); reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000); diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c similarity index 100% rename from drivers/staging/octeon/cvmx-helper-fpa.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c similarity index 95% rename from drivers/staging/octeon/cvmx-helper-loop.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-loop.c index 55a571a..bfbd461 100644 --- a/drivers/staging/octeon/cvmx-helper-loop.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c @@ -31,10 +31,10 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" -#include "cvmx-pip-defs.h" +#include +#include /** * Probe a LOOP interface and determine the number of ports diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c similarity index 96% rename from drivers/staging/octeon/cvmx-helper-npi.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-npi.c index 7388a1e..cc94cfa 100644 --- a/drivers/staging/octeon/cvmx-helper-npi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c @@ -31,11 +31,11 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" +#include -#include "cvmx-pip-defs.h" +#include /** * Probe a NPI interface and determine the number of ports diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-rgmii.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c index aa2d5d7..82b2184 100644 --- a/drivers/staging/octeon/cvmx-helper-rgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c @@ -31,18 +31,18 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include +#include #include -#include "cvmx-gmxx-defs.h" -#include "cvmx-asxx-defs.h" -#include "cvmx-dbg-defs.h" +#include +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_asxx_enable(int block); @@ -326,6 +326,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & ~(1 << index)); + memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save)); /* Disable all queues so that TX should become idle */ for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { int queue = cvmx_pko_get_base_queue(ipd_port) + i; diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-sgmii.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c index 6214e3b..464347f 100644 --- a/drivers/staging/octeon/cvmx-helper-sgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -32,14 +32,14 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-mdio.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsx-defs.h" +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-spi.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-spi.c index 8ba6c83..02a4442 100644 --- a/drivers/staging/octeon/cvmx-helper-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -35,12 +35,12 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index); */ #include -#include "cvmx-config.h" -#include "cvmx-spi.h" -#include "cvmx-helper.h" +#include +#include +#include -#include "cvmx-pip-defs.h" -#include "cvmx-pko-defs.h" +#include +#include /* * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c similarity index 97% rename from drivers/staging/octeon/cvmx-helper-util.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-util.c index 41ef8a4..8c98a22 100644 --- a/drivers/staging/octeon/cvmx-helper-util.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c @@ -32,16 +32,16 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-fpa.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-ipd.h" -#include "cvmx-spi.h" +#include +#include +#include +#include +#include -#include "cvmx-helper.h" -#include "cvmx-helper-util.h" +#include +#include #include diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper-xaui.c rename to arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index a11e676..667a8e3 100644 --- a/drivers/staging/octeon/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -33,13 +33,13 @@ #include -#include "cvmx-config.h" +#include -#include "cvmx-helper.h" +#include -#include "cvmx-pko-defs.h" -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsxx-defs.h" +#include +#include +#include void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); diff --git a/drivers/staging/octeon/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c similarity index 98% rename from drivers/staging/octeon/cvmx-helper.c rename to arch/mips/cavium-octeon/executive/cvmx-helper.c index 5915066..6238a22 100644 --- a/drivers/staging/octeon/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -32,19 +32,19 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-fpa.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-ipd.h" -#include "cvmx-spi.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" +#include +#include +#include +#include +#include +#include +#include -#include "cvmx-pip-defs.h" -#include "cvmx-smix-defs.h" -#include "cvmx-asxx-defs.h" +#include +#include +#include /** * cvmx_override_pko_queue_priority(int ipd_port, uint64_t @@ -548,7 +548,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) union cvmx_gmxx_prtx_cfg gmx_cfg; int retry_cnt; int retry_loop_cnt; - int mtu; int i; cvmx_helper_link_info_t link_info; @@ -662,10 +661,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); - mtu = - cvmx_read_csr(CVMX_GMXX_RXX_JABBER - (INDEX(FIX_IPD_OUTPORT), - INTERFACE(FIX_IPD_OUTPORT))); cvmx_write_csr(CVMX_GMXX_RXX_JABBER (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c similarity index 98% rename from drivers/staging/octeon/cvmx-interrupt-decodes.c rename to arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c index a3337e3..e59d1b7 100644 --- a/drivers/staging/octeon/cvmx-interrupt-decodes.c +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c @@ -34,11 +34,11 @@ #include -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsx-defs.h" -#include "cvmx-pcsxx-defs.h" -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" +#include +#include +#include +#include +#include #ifndef PRINT_ERROR #define PRINT_ERROR(format, ...) diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c similarity index 97% rename from drivers/staging/octeon/cvmx-interrupt-rsl.c rename to arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c index df50048..bea7538 100644 --- a/drivers/staging/octeon/cvmx-interrupt-rsl.c +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c @@ -32,8 +32,8 @@ #include -#include "cvmx-asxx-defs.h" -#include "cvmx-gmxx-defs.h" +#include +#include #ifndef PRINT_ERROR #define PRINT_ERROR(format, ...) diff --git a/drivers/staging/octeon/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c similarity index 99% rename from drivers/staging/octeon/cvmx-pko.c rename to arch/mips/cavium-octeon/executive/cvmx-pko.c index 00db915..f557084 100644 --- a/drivers/staging/octeon/cvmx-pko.c +++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c @@ -31,9 +31,9 @@ #include -#include "cvmx-config.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" +#include +#include +#include /** * Internal state of packet output diff --git a/drivers/staging/octeon/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c similarity index 99% rename from drivers/staging/octeon/cvmx-spi.c rename to arch/mips/cavium-octeon/executive/cvmx-spi.c index 82794d9..74afb17 100644 --- a/drivers/staging/octeon/cvmx-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c @@ -31,14 +31,14 @@ */ #include -#include "cvmx-config.h" +#include -#include "cvmx-pko.h" -#include "cvmx-spi.h" +#include +#include -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" -#include "cvmx-srxx-defs.h" +#include +#include +#include #define INVOKE_CB(function_p, args...) \ do { \ diff --git a/drivers/staging/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h similarity index 100% rename from drivers/staging/octeon/cvmx-address.h rename to arch/mips/include/asm/octeon/cvmx-address.h diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-asxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-asxx-defs.h diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h similarity index 100% rename from drivers/staging/octeon/cvmx-cmd-queue.h rename to arch/mips/include/asm/octeon/cvmx-cmd-queue.h diff --git a/drivers/staging/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h similarity index 100% rename from drivers/staging/octeon/cvmx-config.h rename to arch/mips/include/asm/octeon/cvmx-config.h diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-dbg-defs.h rename to arch/mips/include/asm/octeon/cvmx-dbg-defs.h diff --git a/drivers/staging/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h similarity index 100% rename from drivers/staging/octeon/cvmx-fau.h rename to arch/mips/include/asm/octeon/cvmx-fau.h diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-fpa-defs.h rename to arch/mips/include/asm/octeon/cvmx-fpa-defs.h diff --git a/drivers/staging/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h similarity index 100% rename from drivers/staging/octeon/cvmx-fpa.h rename to arch/mips/include/asm/octeon/cvmx-fpa.h diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-gmxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-gmxx-defs.h diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-board.h rename to arch/mips/include/asm/octeon/cvmx-helper-board.h diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-fpa.h rename to arch/mips/include/asm/octeon/cvmx-helper-fpa.h diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-loop.h rename to arch/mips/include/asm/octeon/cvmx-helper-loop.h diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-npi.h rename to arch/mips/include/asm/octeon/cvmx-helper-npi.h diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-rgmii.h rename to arch/mips/include/asm/octeon/cvmx-helper-rgmii.h diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-sgmii.h rename to arch/mips/include/asm/octeon/cvmx-helper-sgmii.h diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-spi.h rename to arch/mips/include/asm/octeon/cvmx-helper-spi.h diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-util.h rename to arch/mips/include/asm/octeon/cvmx-helper-util.h diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper-xaui.h rename to arch/mips/include/asm/octeon/cvmx-helper-xaui.h diff --git a/drivers/staging/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h similarity index 100% rename from drivers/staging/octeon/cvmx-helper.h rename to arch/mips/include/asm/octeon/cvmx-helper.h diff --git a/drivers/staging/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h similarity index 100% rename from drivers/staging/octeon/cvmx-ipd.h rename to arch/mips/include/asm/octeon/cvmx-ipd.h diff --git a/drivers/staging/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h similarity index 100% rename from drivers/staging/octeon/cvmx-mdio.h rename to arch/mips/include/asm/octeon/cvmx-mdio.h diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pcsx-defs.h rename to arch/mips/include/asm/octeon/cvmx-pcsx-defs.h diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pcsxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pip-defs.h rename to arch/mips/include/asm/octeon/cvmx-pip-defs.h diff --git a/drivers/staging/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h similarity index 100% rename from drivers/staging/octeon/cvmx-pip.h rename to arch/mips/include/asm/octeon/cvmx-pip.h diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-pko-defs.h rename to arch/mips/include/asm/octeon/cvmx-pko-defs.h diff --git a/drivers/staging/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h similarity index 100% rename from drivers/staging/octeon/cvmx-pko.h rename to arch/mips/include/asm/octeon/cvmx-pko.h diff --git a/drivers/staging/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h similarity index 100% rename from drivers/staging/octeon/cvmx-pow.h rename to arch/mips/include/asm/octeon/cvmx-pow.h diff --git a/drivers/staging/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h similarity index 100% rename from drivers/staging/octeon/cvmx-scratch.h rename to arch/mips/include/asm/octeon/cvmx-scratch.h diff --git a/drivers/staging/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h similarity index 100% rename from drivers/staging/octeon/cvmx-spi.h rename to arch/mips/include/asm/octeon/cvmx-spi.h diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-spxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-spxx-defs.h diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-srxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-srxx-defs.h diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h similarity index 100% rename from drivers/staging/octeon/cvmx-stxx-defs.h rename to arch/mips/include/asm/octeon/cvmx-stxx-defs.h diff --git a/drivers/staging/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h similarity index 100% rename from drivers/staging/octeon/cvmx-wqe.h rename to arch/mips/include/asm/octeon/cvmx-wqe.h diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile index fc850ba..9012dee 100644 --- a/drivers/staging/octeon/Makefile +++ b/drivers/staging/octeon/Makefile @@ -20,9 +20,4 @@ octeon-ethernet-y += ethernet-sgmii.o octeon-ethernet-y += ethernet-spi.o octeon-ethernet-y += ethernet-tx.o octeon-ethernet-y += ethernet-xaui.o -octeon-ethernet-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ - cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ - cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ - cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ - cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h deleted file mode 100644 index 62ffe78..0000000 --- a/drivers/staging/octeon/cvmx-packet.h +++ /dev/null @@ -1,65 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Packet buffer defines. - */ - -#ifndef __CVMX_PACKET_H__ -#define __CVMX_PACKET_H__ - -/** - * This structure defines a buffer pointer on Octeon - */ -union cvmx_buf_ptr { - void *ptr; - uint64_t u64; - struct { - /* - * if set, invert the "free" pick of the overall - * packet. HW always sets this bit to 0 on inbound - * packet - */ - uint64_t i:1; - /* - * Indicates the amount to back up to get to the - * buffer start in cache lines. In most cases this is - * less than one complete cache line, so the value is - * zero. - */ - uint64_t back:4; - /* The pool that the buffer came from / goes to */ - uint64_t pool:3; - /* The size of the segment pointed to by addr (in bytes) */ - uint64_t size:16; - /* Pointer to the first byte of the data, NOT buffer */ - uint64_t addr:40; - } s; -}; - -#endif /* __CVMX_PACKET_H__ */ diff --git a/drivers/staging/octeon/cvmx-smix-defs.h b/drivers/staging/octeon/cvmx-smix-defs.h deleted file mode 100644 index 9ae45fc..0000000 --- a/drivers/staging/octeon/cvmx-smix-defs.h +++ /dev/null @@ -1,178 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_SMIX_DEFS_H__ -#define __CVMX_SMIX_DEFS_H__ - -#define CVMX_SMIX_CLK(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_CMD(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_EN(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_RD_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_WR_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256)) - -union cvmx_smix_clk { - uint64_t u64; - struct cvmx_smix_clk_s { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t sample_mode:1; - uint64_t reserved_14_14:1; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } s; - struct cvmx_smix_clk_cn30xx { - uint64_t reserved_21_63:43; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn30xx; - struct cvmx_smix_clk_cn30xx cn31xx; - struct cvmx_smix_clk_cn30xx cn38xx; - struct cvmx_smix_clk_cn30xx cn38xxp2; - struct cvmx_smix_clk_cn50xx { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn50xx; - struct cvmx_smix_clk_s cn52xx; - struct cvmx_smix_clk_cn50xx cn52xxp1; - struct cvmx_smix_clk_s cn56xx; - struct cvmx_smix_clk_cn50xx cn56xxp1; - struct cvmx_smix_clk_cn30xx cn58xx; - struct cvmx_smix_clk_cn30xx cn58xxp1; -}; - -union cvmx_smix_cmd { - uint64_t u64; - struct cvmx_smix_cmd_s { - uint64_t reserved_18_63:46; - uint64_t phy_op:2; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } s; - struct cvmx_smix_cmd_cn30xx { - uint64_t reserved_17_63:47; - uint64_t phy_op:1; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } cn30xx; - struct cvmx_smix_cmd_cn30xx cn31xx; - struct cvmx_smix_cmd_cn30xx cn38xx; - struct cvmx_smix_cmd_cn30xx cn38xxp2; - struct cvmx_smix_cmd_s cn50xx; - struct cvmx_smix_cmd_s cn52xx; - struct cvmx_smix_cmd_s cn52xxp1; - struct cvmx_smix_cmd_s cn56xx; - struct cvmx_smix_cmd_s cn56xxp1; - struct cvmx_smix_cmd_cn30xx cn58xx; - struct cvmx_smix_cmd_cn30xx cn58xxp1; -}; - -union cvmx_smix_en { - uint64_t u64; - struct cvmx_smix_en_s { - uint64_t reserved_1_63:63; - uint64_t en:1; - } s; - struct cvmx_smix_en_s cn30xx; - struct cvmx_smix_en_s cn31xx; - struct cvmx_smix_en_s cn38xx; - struct cvmx_smix_en_s cn38xxp2; - struct cvmx_smix_en_s cn50xx; - struct cvmx_smix_en_s cn52xx; - struct cvmx_smix_en_s cn52xxp1; - struct cvmx_smix_en_s cn56xx; - struct cvmx_smix_en_s cn56xxp1; - struct cvmx_smix_en_s cn58xx; - struct cvmx_smix_en_s cn58xxp1; -}; - -union cvmx_smix_rd_dat { - uint64_t u64; - struct cvmx_smix_rd_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_rd_dat_s cn30xx; - struct cvmx_smix_rd_dat_s cn31xx; - struct cvmx_smix_rd_dat_s cn38xx; - struct cvmx_smix_rd_dat_s cn38xxp2; - struct cvmx_smix_rd_dat_s cn50xx; - struct cvmx_smix_rd_dat_s cn52xx; - struct cvmx_smix_rd_dat_s cn52xxp1; - struct cvmx_smix_rd_dat_s cn56xx; - struct cvmx_smix_rd_dat_s cn56xxp1; - struct cvmx_smix_rd_dat_s cn58xx; - struct cvmx_smix_rd_dat_s cn58xxp1; -}; - -union cvmx_smix_wr_dat { - uint64_t u64; - struct cvmx_smix_wr_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_wr_dat_s cn30xx; - struct cvmx_smix_wr_dat_s cn31xx; - struct cvmx_smix_wr_dat_s cn38xx; - struct cvmx_smix_wr_dat_s cn38xxp2; - struct cvmx_smix_wr_dat_s cn50xx; - struct cvmx_smix_wr_dat_s cn52xx; - struct cvmx_smix_wr_dat_s cn52xxp1; - struct cvmx_smix_wr_dat_s cn56xx; - struct cvmx_smix_wr_dat_s cn56xxp1; - struct cvmx_smix_wr_dat_s cn58xx; - struct cvmx_smix_wr_dat_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h index 6a2cd50..bdaec8d 100644 --- a/drivers/staging/octeon/ethernet-defines.h +++ b/drivers/staging/octeon/ethernet-defines.h @@ -59,7 +59,7 @@ #ifndef __ETHERNET_DEFINES_H__ #define __ETHERNET_DEFINES_H__ -#include "cvmx-config.h" +#include #define OCTEON_ETHERNET_VERSION "1.9" diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 10a82ef..0e5dab7 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -37,9 +37,9 @@ #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "cvmx-helper-board.h" +#include -#include "cvmx-smix-defs.h" +#include static void cvm_oct_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c index 635bb86..78b6cb7 100644 --- a/drivers/staging/octeon/ethernet-mem.c +++ b/drivers/staging/octeon/ethernet-mem.c @@ -32,7 +32,7 @@ #include "ethernet-defines.h" -#include "cvmx-fpa.h" +#include /** * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c index a0d4d4b..849af10 100644 --- a/drivers/staging/octeon/ethernet-rgmii.c +++ b/drivers/staging/octeon/ethernet-rgmii.c @@ -35,11 +35,11 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include #include #include -#include "cvmx-gmxx-defs.h" +#include DEFINE_SPINLOCK(global_register_lock); diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c index cb38f9e..d830393 100644 --- a/drivers/staging/octeon/ethernet-rx.c +++ b/drivers/staging/octeon/ethernet-rx.c @@ -51,14 +51,14 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" -#include "cvmx-wqe.h" -#include "cvmx-fau.h" -#include "cvmx-pow.h" -#include "cvmx-pip.h" -#include "cvmx-scratch.h" - -#include "cvmx-gmxx-defs.h" +#include +#include +#include +#include +#include +#include + +#include struct cvm_napi_wrapper { struct napi_struct napi; diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h index a0743b8..9240c85 100644 --- a/drivers/staging/octeon/ethernet-rx.h +++ b/drivers/staging/octeon/ethernet-rx.h @@ -24,7 +24,7 @@ * This file may also be available under a different license from Cavium. * Contact Cavium Networks for more information *********************************************************************/ -#include "cvmx-fau.h" +#include void cvm_oct_poll_controller(struct net_device *dev); void cvm_oct_rx_initialize(void); diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c index 2d8589e..d102277 100644 --- a/drivers/staging/octeon/ethernet-sgmii.c +++ b/drivers/staging/octeon/ethernet-sgmii.c @@ -34,9 +34,9 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include -#include "cvmx-gmxx-defs.h" +#include int cvm_oct_sgmii_open(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c index 9708254..2ce9135 100644 --- a/drivers/staging/octeon/ethernet-spi.c +++ b/drivers/staging/octeon/ethernet-spi.c @@ -34,11 +34,11 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-spi.h" +#include #include -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" +#include +#include static int number_spi_ports; static int need_retrain[2] = { 0, 0 }; diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c index afc2b73..1f03eb6 100644 --- a/drivers/staging/octeon/ethernet-tx.c +++ b/drivers/staging/octeon/ethernet-tx.c @@ -46,13 +46,13 @@ #include "ethernet-tx.h" #include "ethernet-util.h" -#include "cvmx-wqe.h" -#include "cvmx-fau.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" +#include +#include +#include +#include +#include -#include "cvmx-gmxx-defs.h" +#include #define CVM_OCT_SKB_CB(skb) ((u64 *)((skb)->cb)) diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c index 3fca1cc..321fafc 100644 --- a/drivers/staging/octeon/ethernet-xaui.c +++ b/drivers/staging/octeon/ethernet-xaui.c @@ -34,9 +34,9 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include -#include "cvmx-gmxx-defs.h" +#include int cvm_oct_xaui_open(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index a8f780e..042adf7 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -44,14 +44,14 @@ #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-fau.h" -#include "cvmx-ipd.h" -#include "cvmx-helper.h" - -#include "cvmx-gmxx-defs.h" -#include "cvmx-smix-defs.h" +#include +#include +#include +#include +#include + +#include +#include #if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \ && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 21:58:57 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 21:59:03 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13984 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491770Ab1BVU6T (ORCPT ); Tue, 22 Feb 2011 21:58:19 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:10 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:17 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:17 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwBwW020907; Tue, 22 Feb 2011 12:58:11 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwAx2020906; Tue, 22 Feb 2011 12:58:10 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH 02/10] MIPS: Octeon: Add device tree source files. Date: Tue, 22 Feb 2011 12:57:46 -0800 Message-Id: <1298408274-20856-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:17.0285 (UTC) FILETIME=[3A933750:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29245 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 13 ++ arch/mips/cavium-octeon/octeon_3xxx.dts | 314 +++++++++++++++++++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 99 ++++++++++ 4 files changed, 428 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore new file mode 100644 index 0000000..39c9686 --- /dev/null +++ b/arch/mips/cavium-octeon/.gitignore @@ -0,0 +1,2 @@ +*.dtb.S +*.dtb diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 19eb043..5e25dce 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -15,3 +15,16 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o + +DTS_FILES = octeon_3xxx.dts octeon_68xx.dts +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) + +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) + +$(obj)/%.dtb: $(src)/%.dts + $(call cmd,dtc) + +# Let's keep the .dtb files around in case we want to look at them. +.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) + +clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts new file mode 100644 index 0000000..ad0feaa --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_3xxx.dts @@ -0,0 +1,314 @@ +/dts-v1/; +/* OCTEON 3XXX, 5XXX, 63XX device tree skeleton. */ +/ { + model = "OCTEON"; + compatible = "octeon,octeon"; + #address-cells = <2>; + #size-cells = <2>; + + soc@0 { + device_type = "soc"; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: ciu-3xxx@1070000000000 { + compatible = "octeon,ciu-3xxx"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; + + /* SMI0 */ + mdio0: mdio@1180000001800 { + compatible = "octeon,mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + device_type = "mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + /* SMI1 */ + mdio1: mdio@1180000001900 { + compatible = "octeon,mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + device_type = "mdio"; + }; + + mgmt0: ethernet@1070000100000 { + compatible = "octeon,mgmt"; + device_type = "network"; + model = "mgmt"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + unit-number = <0>; + interrupt-parent = <&ciu>; + interrupts = <0 62>, <1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + mgmt1: ethernet@1070000100800 { + compatible = "octeon,mgmt"; + device_type = "network"; + model = "mgmt"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + unit-number = <1>; + interrupt-parent = <&ciu>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + + pip: pip@11800a0000000 { + compatible = "octeon,pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + device_type = "network"; + model = "pip"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + }; + ethernet@1 { + device_type = "network"; + model = "pip"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + }; + ethernet@2 { + device_type = "network"; + model = "pip"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + }; + ethernet@3 { + device_type = "network"; + model = "pip"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy5>; + }; + }; + + interface@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + device_type = "network"; + model = "pip"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy6>; + }; + ethernet@1 { + device_type = "network"; + model = "pip"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy7>; + }; + ethernet@2 { + device_type = "network"; + model = "pip"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy8>; + }; + ethernet@3 { + device_type = "network"; + model = "pip"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy9>; + }; + }; + + interface@2 { /* DPI interface. */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; /* interface */ + + ethernet@0 { + device_type = "network"; + model = "pip"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + device_type = "network"; + model = "pip"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + device_type = "network"; + model = "pip"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@3 { + device_type = "network"; + model = "pip"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@3 { /* Loop interface. */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; /* interface */ + + ethernet@0 { + device_type = "network"; + model = "pip"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + device_type = "network"; + model = "pip"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + device_type = "network"; + model = "pip"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@3 { + device_type = "network"; + model = "pip"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + }; + + /* TWSI 0 */ + i2c0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "octeon,twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupt-parent = <&ciu>; + interrupts = <0 45>; + clock-rate = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + }; + + /* TWSI 1 */ + i2c1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "octeon,twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupt-parent = <&ciu>; + interrupts = <0 59>; + clock-rate = <100000>; + }; + }; + + aliases { + ethernet-mgmt0 = &mgmt0; + ethernet-mgmt1 = &mgmt1; + pip = &pip; + mdio0 = &mdio0; + mdio1 = &mdio1; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; +}; diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts new file mode 100644 index 0000000..31dbd39 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_68xx.dts @@ -0,0 +1,99 @@ +/dts-v1/; +/* OCTEON 68XX device tree skeleton. */ +/ { + model = "OCTEON"; + compatible = "octeon,octeon"; + #address-cells = <2>; + #size-cells = <2>; + + soc@0 { + device_type = "soc"; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: ciu-68xx@1070100000000 { + compatible = "octeon,ciu-68xx"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; + + /* SMI0 */ + mdio0: mdio@1180000003800 { + compatible = "octeon,mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003800 0x0 0x40>; + device_type = "mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + device_type = "ethernet-phy"; + }; + }; + + /* SMI1 */ + mdio1: mdio@1180000003880 { + compatible = "octeon,mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003880 0x0 0x40>; + device_type = "mdio"; + }; + + /* SMI2 */ + mdio2: mdio@1180000003900 { + compatible = "octeon,mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003900 0x0 0x40>; + device_type = "mdio"; + }; + + /* SMI3 */ + mdio3: mdio@1180000003980 { + compatible = "octeon,mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003980 0x0 0x40>; + device_type = "mdio"; + }; + + mgmt0: ethernet@1070000100000 { + compatible = "octeon,mgmt"; + device_type = "network"; + model = "mgmt"; + /* Register banks: MIX AGL AGL_SHARED AGL_PRT_CTL*/ + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + unit-number = <0>; + interrupt-parent = <&ciu>; + interrupts = <6 40>, <6 32>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + }; + aliases { + ethernet-mgmt0 = &mgmt0; + mdio0 = &mdio0; + mdio1 = &mdio1; + mdio2 = &mdio2; + mdio3 = &mdio3; + }; +}; -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 21:59:22 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 21:59:27 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13988 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491771Ab1BVU6U (ORCPT ); Tue, 22 Feb 2011 21:58:20 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:11 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:18 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:18 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwDfE020911; Tue, 22 Feb 2011 12:58:13 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwCaH020910; Tue, 22 Feb 2011 12:58:12 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH 03/10] MIPS: Prune some target specific code out of prom.c Date: Tue, 22 Feb 2011 12:57:47 -0800 Message-Id: <1298408274-20856-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:18.0691 (UTC) FILETIME=[3B69C130:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29246 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This code is not common enough to be in a shared file. It is also not used by any existing boards, so just remove it. Signed-off-by: David Daney --- arch/mips/kernel/prom.c | 49 ----------------------------------------------- 1 files changed, 0 insertions(+), 49 deletions(-) diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index a19811e9..a07b6f1 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -59,52 +59,3 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start, initrd_below_start_ok = 1; } #endif - -/* - * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# - * - * Currently the mapping mechanism is trivial; simple flat hwirq numbers are - * mapped 1:1 onto Linux irq numbers. Cascaded irq controllers are not - * supported. - */ -unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) -{ - return intspec[0]; -} -EXPORT_SYMBOL_GPL(irq_create_of_mapping); - -void __init early_init_devtree(void *params) -{ - /* Setup flat device-tree pointer */ - initial_boot_params = params; - - /* Retrieve various informations from the /chosen node of the - * device-tree, including the platform type, initrd location and - * size, and more ... - */ - of_scan_flat_dt(early_init_dt_scan_chosen, NULL); - - /* Scan memory nodes */ - of_scan_flat_dt(early_init_dt_scan_root, NULL); - of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL); -} - -void __init device_tree_init(void) -{ - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_mem_mach(base, size); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_mem_mach(base, size); -} -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 21:59:46 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 21:59:56 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13995 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491772Ab1BVU6W (ORCPT ); Tue, 22 Feb 2011 21:58:22 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:13 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:20 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:20 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwE8i020915; Tue, 22 Feb 2011 12:58:14 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwEK7020914; Tue, 22 Feb 2011 12:58:14 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH 04/10] MIPS: Octeon: Add a irq_create_of_mapping() implementation. Date: Tue, 22 Feb 2011 12:57:48 -0800 Message-Id: <1298408274-20856-5-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:20.0191 (UTC) FILETIME=[3C4EA2F0:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29247 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is needed for Octeon to use the Device Tree. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index b365710..b0a9261 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -8,7 +8,9 @@ #include #include +#include #include +#include #include #include @@ -64,6 +66,29 @@ static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, octeon_irq_ciu_to_irq[line][bit] = irq; } +/* + * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# + * + * Octeon irq maps are a pair of indexes. The first selects either + * ciu0 or ciu1, the second is the bit within the ciu register. + */ +unsigned int irq_create_of_mapping(struct device_node *controller, + const u32 *intspec, unsigned int intsize) +{ + int ciu, bit; + unsigned int irq = 0; + + ciu = be32_to_cpup(intspec); + bit = be32_to_cpup(intspec + 1); + + if (ciu < 8 && bit < 64) + irq = octeon_irq_ciu_to_irq[ciu][bit]; + + return irq; +} +EXPORT_SYMBOL_GPL(irq_create_of_mapping); + + static int octeon_coreid_for_cpu(int cpu) { #ifdef CONFIG_SMP -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 22:00:15 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 22:00:22 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13999 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491773Ab1BVU6X (ORCPT ); Tue, 22 Feb 2011 21:58:23 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:14 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:21 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:21 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwG4H020919; Tue, 22 Feb 2011 12:58:16 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwFlc020918; Tue, 22 Feb 2011 12:58:15 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH 05/10] MIPS: Octeon: Rearrance CVMX files in preperation for device tree Date: Tue, 22 Feb 2011 12:57:49 -0800 Message-Id: <1298408274-20856-6-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:21.0754 (UTC) FILETIME=[3D3D21A0:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29248 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- .../cavium-octeon/executive/cvmx-helper-sgmii.c | 6 +- .../mips/cavium-octeon/executive/cvmx-helper-spi.c | 10 ++ .../cavium-octeon/executive/cvmx-helper-xaui.c | 22 +++-- arch/mips/cavium-octeon/executive/cvmx-helper.c | 93 ++++++++++++++++--- arch/mips/include/asm/octeon/cvmx-helper-loop.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-npi.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-rgmii.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-sgmii.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-spi.h | 1 + arch/mips/include/asm/octeon/cvmx-helper-xaui.h | 1 + arch/mips/include/asm/octeon/cvmx-helper.h | 1 + 11 files changed, 114 insertions(+), 24 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c index 464347f..0c0bf5d 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -326,6 +326,10 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) return 0; } +int __cvmx_helper_sgmii_enumerate(int interface) +{ + return 4; +} /** * Probe a SGMII interface and determine the number of ports * connected to it. The SGMII interface should still be down after @@ -347,7 +351,7 @@ int __cvmx_helper_sgmii_probe(int interface) mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); mode.s.en = 1; cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); - return 4; + return __cvmx_helper_sgmii_enumerate(interface); } /** diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c index 02a4442..2830e4b 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -51,6 +51,16 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index); #define CVMX_HELPER_SPI_TIMEOUT 10 #endif +int __cvmx_helper_spi_enumerate(int interface) +{ + if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && + cvmx_spi4000_is_present(interface)) { + return 10; + } else { + return 16; + } +} + /** * Probe a SPI interface and determine the number of ports * connected to it. The SPI interface should still be down after diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index 667a8e3..1723248e 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -44,6 +44,19 @@ void __cvmx_interrupt_gmxx_enable(int interface); void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); + +int __cvmx_helper_xaui_enumerate(int interface) +{ + union cvmx_gmxx_hg2_control gmx_hg2_control; + + /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ + gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); + if (gmx_hg2_control.s.hg2tx_en) + return 16; + else + return 1; +} + /** * Probe a XAUI interface and determine the number of ports * connected to it. The XAUI interface should still be down @@ -56,7 +69,6 @@ void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); int __cvmx_helper_xaui_probe(int interface) { int i; - union cvmx_gmxx_hg2_control gmx_hg2_control; union cvmx_gmxx_inf_mode mode; /* @@ -90,13 +102,7 @@ int __cvmx_helper_xaui_probe(int interface) pko_mem_port_ptrs.s.pid = interface * 16 + i; cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); } - - /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ - gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); - if (gmx_hg2_control.s.hg2tx_en) - return 16; - else - return 1; + return __cvmx_helper_xaui_enumerate(interface); } /** diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index 6238a22..bea6ab6 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -234,21 +234,16 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port) } /** - * This function probes an interface to determine the actual - * number of hardware ports connected to it. It doesn't setup the - * ports or enable them. The main goal here is to set the global - * interface_port_count[interface] correctly. Hardware setup of the - * ports will be performed later. + * This function sets the interface_port_count[interface] correctly, + * without modifying any hardware configuration. Hardware setup of + * the ports will be performed later. * * @interface: Interface to probe * * Returns Zero on success, negative on failure */ -int cvmx_helper_interface_probe(int interface) +int cvmx_helper_interface_enumerate(int interface) { - /* At this stage in the game we don't want packets to be moving yet. - The following probe calls should perform hardware setup - needed to determine port counts. Receive must still be disabled */ switch (cvmx_helper_interface_get_mode(interface)) { /* These types don't support ports to IPD/PKO */ case CVMX_HELPER_INTERFACE_MODE_DISABLED: @@ -258,7 +253,7 @@ int cvmx_helper_interface_probe(int interface) /* XAUI is a single high speed port */ case CVMX_HELPER_INTERFACE_MODE_XAUI: interface_port_count[interface] = - __cvmx_helper_xaui_probe(interface); + __cvmx_helper_xaui_enumerate(interface); break; /* * RGMII/GMII/MII are all treated about the same. Most @@ -267,7 +262,7 @@ int cvmx_helper_interface_probe(int interface) case CVMX_HELPER_INTERFACE_MODE_RGMII: case CVMX_HELPER_INTERFACE_MODE_GMII: interface_port_count[interface] = - __cvmx_helper_rgmii_probe(interface); + __cvmx_helper_rgmii_enumerate(interface); break; /* * SPI4 can have 1-16 ports depending on the device at @@ -275,7 +270,7 @@ int cvmx_helper_interface_probe(int interface) */ case CVMX_HELPER_INTERFACE_MODE_SPI: interface_port_count[interface] = - __cvmx_helper_spi_probe(interface); + __cvmx_helper_spi_enumerate(interface); break; /* * SGMII can have 1-4 ports depending on how many are @@ -284,12 +279,12 @@ int cvmx_helper_interface_probe(int interface) case CVMX_HELPER_INTERFACE_MODE_SGMII: case CVMX_HELPER_INTERFACE_MODE_PICMG: interface_port_count[interface] = - __cvmx_helper_sgmii_probe(interface); + __cvmx_helper_sgmii_enumerate(interface); break; /* PCI target Network Packet Interface */ case CVMX_HELPER_INTERFACE_MODE_NPI: interface_port_count[interface] = - __cvmx_helper_npi_probe(interface); + __cvmx_helper_npi_enumerate(interface); break; /* * Special loopback only ports. These are not the same @@ -297,7 +292,7 @@ int cvmx_helper_interface_probe(int interface) */ case CVMX_HELPER_INTERFACE_MODE_LOOP: interface_port_count[interface] = - __cvmx_helper_loop_probe(interface); + __cvmx_helper_loop_enumerate(interface); break; } @@ -313,6 +308,74 @@ int cvmx_helper_interface_probe(int interface) } /** + * This function probes an interface to determine the actual + * number of hardware ports connected to it. It doesn't setup the + * ports or enable them. The main goal here is to set the global + * interface_port_count[interface] correctly. Hardware setup of the + * ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_interface_probe(int interface) +{ + cvmx_helper_interface_enumerate(interface); + /* At this stage in the game we don't want packets to be moving yet. + The following probe calls should perform hardware setup + needed to determine port counts. Receive must still be disabled */ + switch (cvmx_helper_interface_get_mode(interface)) { + /* These types don't support ports to IPD/PKO */ + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + break; + /* XAUI is a single high speed port */ + case CVMX_HELPER_INTERFACE_MODE_XAUI: + __cvmx_helper_xaui_probe(interface); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII. + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + __cvmx_helper_rgmii_probe(interface); + break; + /* + * SPI4 can have 1-16 ports depending on the device at + * the other end. + */ + case CVMX_HELPER_INTERFACE_MODE_SPI: + __cvmx_helper_spi_probe(interface); + break; + /* + * SGMII can have 1-4 ports depending on how many are + * hooked up. + */ + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + __cvmx_helper_sgmii_probe(interface); + break; + /* PCI target Network Packet Interface */ + case CVMX_HELPER_INTERFACE_MODE_NPI: + __cvmx_helper_npi_probe(interface); + break; + /* + * Special loopback only ports. These are not the same + * as other ports in loopback mode. + */ + case CVMX_HELPER_INTERFACE_MODE_LOOP: + __cvmx_helper_loop_probe(interface); + break; + } + + /* Make sure all global variables propagate to other cores */ + CVMX_SYNCWS; + + return 0; +} + +/** * Setup the IPD/PIP for the ports on an interface. Packet * classification and tagging are set for every port on the * interface. The number of ports on the interface must already diff --git a/arch/mips/include/asm/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h index e646a6c..0a2488e 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-loop.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h @@ -44,6 +44,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_loop_probe(int interface); +static inline int __cvmx_helper_loop_enumerate(int interface) {return 4;} /** * Bringup and enable a LOOP interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h index 908e7b0..8df4c7f 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-npi.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_npi_probe(int interface); +#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe /** * Bringup and enable a NPI interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h index ea26526..78295ba 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h @@ -43,6 +43,7 @@ * Returns Number of RGMII/GMII/MII ports (0-4). */ extern int __cvmx_helper_rgmii_probe(int interface); +#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe /** * Put an RGMII interface in loopback mode. Internal packets sent diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h index 19b48d6..9a9b6c1 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_sgmii_probe(int interface); +extern int __cvmx_helper_sgmii_enumerate(int interface); /** * Bringup and enable a SGMII interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h index 69bac03..9f1c6b9 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-spi.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h @@ -42,6 +42,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_spi_probe(int interface); +extern int __cvmx_helper_spi_enumerate(int interface); /** * Bringup and enable a SPI interface. After this call packet I/O diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h index 4b4db2f..f6fbc4f 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h @@ -45,6 +45,7 @@ * Returns Number of ports on the interface. Zero to disable. */ extern int __cvmx_helper_xaui_probe(int interface); +extern int __cvmx_helper_xaui_enumerate(int interface); /** * Bringup and enable a XAUI interface. After this call packet diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h index 51916f3..3169cd7 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper.h +++ b/arch/mips/include/asm/octeon/cvmx-helper.h @@ -207,6 +207,7 @@ extern int cvmx_helper_link_set(int ipd_port, * Returns Zero on success, negative on failure */ extern int cvmx_helper_interface_probe(int interface); +extern int cvmx_helper_interface_enumerate(int interface); /** * Configure a port for internal and/or external loopback. Internal loopback -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 22:00:41 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 22:00:47 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14003 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491774Ab1BVU6Y (ORCPT ); Tue, 22 Feb 2011 21:58:24 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:15 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:23 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:22 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwHME020923; Tue, 22 Feb 2011 12:58:17 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwHC4020922; Tue, 22 Feb 2011 12:58:17 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [RFC PATCH 06/10] MIPS: Octeon: Initialize and fixup device tree. Date: Tue, 22 Feb 2011 12:57:50 -0800 Message-Id: <1298408274-20856-7-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:22.0941 (UTC) FILETIME=[3DF240D0:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29249 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/Kconfig | 2 + arch/mips/cavium-octeon/octeon-platform.c | 280 +++++++++++++++++++++++++++++ arch/mips/cavium-octeon/setup.c | 17 ++ 3 files changed, 299 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4baf7f2..a8fc970 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -699,6 +699,7 @@ config CAVIUM_OCTEON_SIMULATOR select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_HOTPLUG_CPU select SYS_HAS_CPU_CAVIUM_OCTEON + select OF_DYNAMIC help The Octeon simulator is software performance model of the Cavium Octeon Processor. It supports simulating Octeon processors on x86 @@ -715,6 +716,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD select SYS_SUPPORTS_HOTPLUG_CPU select SYS_HAS_EARLY_PRINTK select SYS_HAS_CPU_CAVIUM_OCTEON + select OF_DYNAMIC select SWAP_IO_SPACE select HW_HAS_PCI select ARCH_SUPPORTS_MSI diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index cecaf62..428de0d 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -13,10 +13,14 @@ #include #include #include +#include #include +#include #include #include +#include +#include static struct octeon_cf_data octeon_cf_data; @@ -440,6 +444,282 @@ device_initcall(octeon_ohci_device_init); #endif /* CONFIG_USB */ +static struct of_device_id __initdata octeon_ids[] = { + { .type = "soc", }, + { .compatible = "simple-bus", }, + {}, +}; + +static int __init set_phy_addr_prop(struct device_node *n, int phy) +{ + u32 *vp; + struct property *old_p; + struct property *p = kzalloc(sizeof(struct device_node) + sizeof(u32), GFP_KERNEL); + if (!p) + return -ENOMEM; + /* The value will immediatly follow the node in memory. */ + vp = (u32 *)(&p[1]); + p->name = "reg"; + p->length = sizeof(u32); + p->value = vp; + + *vp = cpu_to_be32((u32)phy); + + old_p = of_find_property(n, "reg", NULL); + if (old_p) + prom_remove_property(n, old_p); + return prom_add_property(n, p); +} + +static int __init set_mac_addr_prop(struct device_node *n, u64 mac) +{ + u8 *vp; + struct property *old_p; + struct property *p = kzalloc(sizeof(struct device_node) + 6, GFP_KERNEL); + if (!p) + return -ENOMEM; + /* The value will immediatly follow the node in memory. */ + vp = (u8 *)(&p[1]); + p->name = "local-mac-address"; + p->length = 6; + p->value = vp; + + vp[0] = (mac >> 40) & 0xff; + vp[1] = (mac >> 32) & 0xff; + vp[2] = (mac >> 24) & 0xff; + vp[3] = (mac >> 16) & 0xff; + vp[4] = (mac >> 8) & 0xff; + vp[5] = mac & 0xff; + + old_p = of_find_property(n, "local-mac-address", NULL); + if (old_p) + prom_remove_property(n, old_p); + return prom_add_property(n, p); +} + +static struct device_node * __init octeon_of_get_child(const struct device_node *parent, + int reg_val) +{ + struct device_node *node = NULL; + int size; + const __be32 *addr; + + for (;;) { + node = of_get_next_child(parent, node); + if (!node) + break; + addr = of_get_property(node, "reg", &size); + if (addr && (be32_to_cpu(*addr) == reg_val)) + break; + } + return node; +} + +int __init octeon_prune_device_tree(void) +{ + int i, p, max_port; + const char *node_path; + char name_buffer[20]; + struct device_node *aliases; + struct device_node *pip; + struct device_node *iface; + struct device_node *eth; + struct device_node *node; + + aliases = of_find_node_by_path("/aliases"); + if (!aliases) { + pr_err("Error: No /aliases node in device tree."); + return -EINVAL; + } + + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) + max_port = 2; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 1; + else + max_port = 0; + + for (i = 0; i < 2; i++) { + struct device_node *mgmt; + snprintf(name_buffer, sizeof(name_buffer), + "ethernet-mgmt%d", i); + node_path = of_get_property(aliases, name_buffer, NULL); + if (node_path) { + mgmt = of_find_node_by_path(node_path); + if (!mgmt) + continue; + if (i >= max_port) { + pr_notice("Deleting mgmt%d\n", i); + node = of_parse_phandle(mgmt, "phy-handle", 0); + if (node) { + of_detach_node(node); + of_node_put(node); + } + of_node_put(node); + + of_detach_node(mgmt); + of_node_put(mgmt); + } + of_node_put(mgmt); + } + } + + node_path = of_get_property(aliases, "pip", NULL); + if (node_path && (pip = of_find_node_by_path(node_path))) { + for (i = 0; i < 4; i++) { + cvmx_helper_interface_enumerate(i); + iface = octeon_of_get_child(pip, i); + if (!iface) + continue; + for (p = 0; p < 4; p++) { + eth = octeon_of_get_child(iface, p); + if (!eth) + continue; + node = of_parse_phandle(eth, "phy-handle", 0); + if (p < cvmx_helper_ports_on_interface(i)) { + int phy = cvmx_helper_board_get_mii_address(16 * i + p); + if (node && phy < 0) { + struct property *p = of_find_property(eth, "phy-handle", NULL); + of_detach_node(node); + of_node_put(node); + prom_remove_property(eth, p); + } + } else { + pr_notice("Deleting Ethernet %x:%x\n", i, p); + if (node) { + of_detach_node(node); + of_node_put(node); + } + of_detach_node(eth); + of_node_put(eth); + } + of_node_put(node); + of_node_put(eth); + } + of_node_put(iface); + } + of_node_put(pip); + } + + /* I2C */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + struct device_node *i2c; + snprintf(name_buffer, sizeof(name_buffer), + "i2c%d", i); + node_path = of_get_property(aliases, name_buffer, NULL); + if (node_path) { + i2c = of_find_node_by_path(node_path); + if (!i2c) + continue; + if (i >= max_port) { + pr_notice("Deleting i2c%d\n", i); + + of_detach_node(i2c); + of_node_put(i2c); + } + of_node_put(i2c); + } + } + + of_node_put(aliases); + return 0; +} + +int __init octeon_fix_device_tree(void) +{ + int i, p; + int rv; + const char *node_path; + char name_buffer[20]; + u64 mac_addr_base; + struct device_node *aliases; + struct device_node *pip; + struct device_node *iface; + struct device_node *eth; + struct device_node *node; + + /* + * Edit the device tree to reflect known board + * configurations. + */ + mac_addr_base = + ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | + ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | + ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | + ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | + ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | + (octeon_bootinfo->mac_addr_base[5] & 0xffull); + + aliases = of_find_node_by_path("/aliases"); + if (!aliases) { + pr_err("Error: No /aliases node in device tree."); + return -EINVAL; + } + + for (i = 0; i < 2; i++) { + struct device_node *mgmt; + snprintf(name_buffer, sizeof(name_buffer), + "ethernet-mgmt%d", i); + node_path = of_get_property(aliases, name_buffer, NULL); + if (node_path) { + mgmt = of_find_node_by_path(node_path); + if (!mgmt) + continue; + /* Set the ethernet address */ + rv = set_mac_addr_prop(mgmt, mac_addr_base); + if (rv) + goto err; + mac_addr_base++; + + of_node_put(mgmt); + } + } + + node_path = of_get_property(aliases, "pip", NULL); + if (node_path && (pip = of_find_node_by_path(node_path))) { + for (i = 0; i < 4; i++) { + iface = octeon_of_get_child(pip, i); + if (!iface) + continue; + for (p = 0; p < 4; p++) { + int phy = cvmx_helper_board_get_mii_address(16 * i + p); + eth = octeon_of_get_child(iface, p); + if (!eth) + continue; + node = of_parse_phandle(eth, "phy-handle", 0); + rv = set_mac_addr_prop(eth, mac_addr_base); + mac_addr_base++; + if (node && phy >= 0) + set_phy_addr_prop(node, cvmx_helper_board_get_mii_address(16 * i + p)); + of_node_put(node); + of_node_put(eth); + } + of_node_put(iface); + } + of_node_put(pip); + } + + of_node_put(aliases); + return 0; +err: + return rv; +} +arch_initcall(octeon_fix_device_tree); + +static int __init octeon_publish_devices(void) +{ + return of_platform_bus_probe(NULL, octeon_ids, NULL); +} +device_initcall(octeon_publish_devices); + + MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index ab1a106..818f66d5 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #ifdef CONFIG_BLK_DEV_INITRD #include #endif @@ -797,3 +798,19 @@ void prom_free_prom_memory(void) } #endif } + +int octeon_prune_device_tree(void); + +extern const char __dtb_octeon_3xxx_begin; +extern const char __dtb_octeon_3xxx_end; +void __init device_tree_init(void) +{ + int dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; + /* Copy the default tree from init memory. */ + initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); + if (initial_boot_params == NULL) + panic("Could not allocate initial_boot_params\n"); + memcpy(initial_boot_params, &__dtb_octeon_3xxx_begin, dt_size); + unflatten_device_tree(); + octeon_prune_device_tree(); +} -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 22:01:06 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 22:01:13 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14013 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491768Ab1BVU61 (ORCPT ); Tue, 22 Feb 2011 21:58:27 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:18 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:25 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:25 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwJaT020927; Tue, 22 Feb 2011 12:58:19 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwI5r020926; Tue, 22 Feb 2011 12:58:18 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney , "Jean Delvare (PC drivers, core)" , "Ben Dooks (embedded platforms)" , linux-i2c@vger.kernel.org Subject: [RFC PATCH 07/10] i2c: Convert i2c-octeon.c to use device tree. Date: Tue, 22 Feb 2011 12:57:51 -0800 Message-Id: <1298408274-20856-8-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:25.0910 (UTC) FILETIME=[3FB74960:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29250 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney Cc: "Jean Delvare (PC drivers, core)" Cc: "Ben Dooks (embedded platforms)" Cc: linux-i2c@vger.kernel.org --- arch/mips/cavium-octeon/octeon-platform.c | 84 --------------------------- arch/mips/include/asm/octeon/octeon.h | 5 -- drivers/i2c/busses/i2c-octeon.c | 88 +++++++++++++--------------- 3 files changed, 41 insertions(+), 136 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 428de0d..f148324 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -166,90 +166,6 @@ out: } device_initcall(octeon_rng_device_init); -static struct i2c_board_info __initdata octeon_i2c_devices[] = { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static int __init octeon_i2c_devices_init(void) -{ - return i2c_register_board_info(0, octeon_i2c_devices, - ARRAY_SIZE(octeon_i2c_devices)); -} -arch_initcall(octeon_i2c_devices_init); - -#define OCTEON_I2C_IO_BASE 0x1180000001000ull -#define OCTEON_I2C_IO_UNIT_OFFSET 0x200 - -static struct octeon_i2c_data octeon_i2c_data[2]; - -static int __init octeon_i2c_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource i2c_resources[] = { - { - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, - } - }; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) - num_ports = 2; - else - num_ports = 1; - - for (port = 0; port < num_ports; port++) { - octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate(); - /*FIXME: should be examined. At the moment is set for 100Khz */ - octeon_i2c_data[port].i2c_freq = 100000; - - pd = platform_device_alloc("i2c-octeon", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - pd->dev.platform_data = octeon_i2c_data + port; - - i2c_resources[0].start = - OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET); - i2c_resources[0].end = i2c_resources[0].start + 0x1f; - switch (port) { - case 0: - i2c_resources[1].start = OCTEON_IRQ_TWSI; - i2c_resources[1].end = OCTEON_IRQ_TWSI; - break; - case 1: - i2c_resources[1].start = OCTEON_IRQ_TWSI2; - i2c_resources[1].end = OCTEON_IRQ_TWSI2; - break; - default: - BUG(); - } - - ret = platform_device_add_resources(pd, - i2c_resources, - ARRAY_SIZE(i2c_resources)); - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); -out: - return ret; -} -device_initcall(octeon_i2c_device_init); - /* Octeon SMI/MDIO interface. */ static int __init octeon_mdiobus_device_init(void) { diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index f72f768..1e2486e 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -215,11 +215,6 @@ struct octeon_cf_data { int dma_engine; /* -1 for no DMA */ }; -struct octeon_i2c_data { - unsigned int sys_freq; - unsigned int i2c_freq; -}; - extern void octeon_write_lcd(const char *s); extern void octeon_check_cpu_bist(void); extern int octeon_get_boot_debug_flag(void); diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c index 56dbe54..99a20c6 100644 --- a/drivers/i2c/busses/i2c-octeon.c +++ b/drivers/i2c/busses/i2c-octeon.c @@ -11,17 +11,21 @@ * warranty of any kind, whether express or implied. */ +#include +#include +#include +#include #include #include +#include +#include +#include #include #include #include - -#include #include -#include -#include -#include +#include +#include #include @@ -67,9 +71,7 @@ struct octeon_i2c { int irq; int twsi_freq; int sys_freq; - resource_size_t twsi_phys; void __iomem *twsi_base; - resource_size_t regsize; struct device *dev; }; @@ -511,17 +513,18 @@ static int __devinit octeon_i2c_initlowlevel(struct octeon_i2c *i2c) return -EIO; } -static int __devinit octeon_i2c_probe(struct platform_device *pdev) +static int __devinit octeon_i2c_probe(struct platform_device *pdev, + const struct of_device_id *match) { int irq, result = 0; struct octeon_i2c *i2c; - struct octeon_i2c_data *i2c_data; - struct resource *res_mem; + const __be32 *data; + int len; /* All adaptors have an irq. */ - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + if (!irq) + return -ENXIO; i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); if (!i2c) { @@ -530,32 +533,16 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) goto out; } i2c->dev = &pdev->dev; - i2c_data = pdev->dev.platform_data; - - res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - if (res_mem == NULL) { - dev_err(i2c->dev, "found no memory resource\n"); - result = -ENXIO; - goto fail_region; - } - if (i2c_data == NULL) { - dev_err(i2c->dev, "no I2C frequency data\n"); - result = -ENXIO; - goto fail_region; - } + data = of_get_property(pdev->dev.of_node, "clock-rate", &len); + if (data && len == sizeof(*data)) + i2c->twsi_freq = be32_to_cpup(data); + else + i2c->twsi_freq = 100000; - i2c->twsi_phys = res_mem->start; - i2c->regsize = resource_size(res_mem); - i2c->twsi_freq = i2c_data->i2c_freq; - i2c->sys_freq = i2c_data->sys_freq; + i2c->sys_freq = octeon_get_io_clock_rate(); - if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) { - dev_err(i2c->dev, "request_mem_region failed\n"); - goto fail_region; - } - i2c->twsi_base = ioremap(i2c->twsi_phys, i2c->regsize); + i2c->twsi_base = of_iomap(pdev->dev.of_node, 0); init_waitqueue_head(&i2c->queue); @@ -581,27 +568,27 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) i2c->adap = octeon_i2c_ops; i2c->adap.dev.parent = &pdev->dev; - i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0; + i2c->adap.dev.of_node = pdev->dev.of_node; i2c_set_adapdata(&i2c->adap, i2c); platform_set_drvdata(pdev, i2c); - result = i2c_add_numbered_adapter(&i2c->adap); + result = i2c_add_adapter(&i2c->adap); if (result < 0) { dev_err(i2c->dev, "failed to add adapter\n"); goto fail_add; } - dev_info(i2c->dev, "version %s\n", DRV_VERSION); - return result; + of_i2c_register_devices(&i2c->adap); + + return 0; fail_add: platform_set_drvdata(pdev, NULL); free_irq(i2c->irq, i2c); fail_irq: iounmap(i2c->twsi_base); - release_mem_region(i2c->twsi_phys, i2c->regsize); -fail_region: + kfree(i2c); out: return result; @@ -615,17 +602,25 @@ static int __devexit octeon_i2c_remove(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); free_irq(i2c->irq, i2c); iounmap(i2c->twsi_base); - release_mem_region(i2c->twsi_phys, i2c->regsize); kfree(i2c); return 0; }; -static struct platform_driver octeon_i2c_driver = { +static struct of_device_id octeon_i2c_match[] = { + { + .compatible = "octeon,twsi", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_i2c_match); + +static struct of_platform_driver octeon_i2c_driver = { .probe = octeon_i2c_probe, .remove = __devexit_p(octeon_i2c_remove), .driver = { .owner = THIS_MODULE, .name = DRV_NAME, + .of_match_table = octeon_i2c_match, }, }; @@ -633,20 +628,19 @@ static int __init octeon_i2c_init(void) { int rv; - rv = platform_driver_register(&octeon_i2c_driver); + rv = of_register_platform_driver(&octeon_i2c_driver); return rv; } static void __exit octeon_i2c_exit(void) { - platform_driver_unregister(&octeon_i2c_driver); + of_unregister_platform_driver(&octeon_i2c_driver); } MODULE_AUTHOR("Michael Lawnick "); MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_VERSION); -MODULE_ALIAS("platform:" DRV_NAME); module_init(octeon_i2c_init); module_exit(octeon_i2c_exit); -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 22:01:32 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 22:01:37 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14026 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491778Ab1BVU63 (ORCPT ); Tue, 22 Feb 2011 21:58:29 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:20 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:27 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:27 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwMwG020933; Tue, 22 Feb 2011 12:58:22 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwLWv020932; Tue, 22 Feb 2011 12:58:21 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney , "David S. Miller" , netdev@vger.kernel.org Subject: [RFC PATCH 08/10] netdev: mdio-octeon.c: Convert to use device tree. Date: Tue, 22 Feb 2011 12:57:52 -0800 Message-Id: <1298408274-20856-9-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:27.0457 (UTC) FILETIME=[40A35710:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29251 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Get the MDIO bus controller addresses from the device tree. Signed-off-by: David Daney Cc: "David S. Miller" Cc: netdev@vger.kernel.org --- arch/mips/cavium-octeon/octeon-platform.c | 30 ------------ drivers/net/phy/mdio-octeon.c | 73 +++++++++++++++++------------ 2 files changed, 43 insertions(+), 60 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index f148324..a33dcf9 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -166,36 +166,6 @@ out: } device_initcall(octeon_rng_device_init); -/* Octeon SMI/MDIO interface. */ -static int __init octeon_mdiobus_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - - if (octeon_is_simulation()) - return 0; /* No mdio in the simulator. */ - - /* The bus number is the platform_device id. */ - pd = platform_device_alloc("mdio-octeon", 0); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - ret = platform_device_add(pd); - if (ret) - goto fail; - - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mdiobus_device_init); - /* Octeon mgmt port Ethernet interface. */ static int __init octeon_mgmt_device_init(void) { diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c index bd12ba9..b04c18c 100644 --- a/drivers/net/phy/mdio-octeon.c +++ b/drivers/net/phy/mdio-octeon.c @@ -6,10 +6,14 @@ * Copyright (C) 2009 Cavium Networks */ -#include -#include -#include #include +#include +#include +#include +#include +#include +#include +#include #include #include @@ -18,9 +22,15 @@ #define DRV_VERSION "1.0" #define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver" +#define SMI_CMD 0x0 +#define SMI_WR_DAT 0x8 +#define SMI_RD_DAT 0x10 +#define SMI_CLK 0x18 +#define SMI_EN 0x20 + struct octeon_mdiobus { struct mii_bus *mii_bus; - int unit; + u64 register_base; int phy_irq[PHY_MAX_ADDR]; }; @@ -35,15 +45,15 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum) smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); + cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - cvmx_wait(1000); - smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit)); + __delay(1000); + smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT); } while (smi_rd.s.pending && --timeout); if (smi_rd.s.val) @@ -62,21 +72,21 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, smi_wr.u64 = 0; smi_wr.s.dat = val; - cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64); + cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64); smi_cmd.u64 = 0; smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); + cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - cvmx_wait(1000); - smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit)); + __delay(1000); + smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT); } while (smi_wr.s.pending && --timeout); if (timeout <= 0) @@ -85,11 +95,11 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, return 0; } -static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) +static int __devinit octeon_mdiobus_probe(struct platform_device *pdev, + const struct of_device_id *match) { struct octeon_mdiobus *bus; union cvmx_smix_en smi_en; - int i; int err = -ENOENT; bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); @@ -97,8 +107,7 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) return -ENOMEM; /* The platform_device id is our unit number. */ - bus->unit = pdev->id; - + bus->register_base = (u64)of_iomap(pdev->dev.of_node, 0); bus->mii_bus = mdiobus_alloc(); if (!bus->mii_bus) @@ -106,19 +115,13 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) smi_en.u64 = 0; smi_en.s.en = 1; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); - /* - * Standard Octeon evaluation boards don't support phy - * interrupts, we need to poll. - */ - for (i = 0; i < PHY_MAX_ADDR; i++) - bus->phy_irq[i] = PHY_POLL; bus->mii_bus->priv = bus; bus->mii_bus->irq = bus->phy_irq; bus->mii_bus->name = "mdio-octeon"; - snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%x", bus->unit); + snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base); bus->mii_bus->parent = &pdev->dev; bus->mii_bus->read = octeon_mdiobus_read; @@ -126,7 +129,7 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, bus); - err = mdiobus_register(bus->mii_bus); + err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node); if (err) goto err_register; @@ -137,9 +140,9 @@ err_register: mdiobus_free(bus->mii_bus); err: - devm_kfree(&pdev->dev, bus); smi_en.u64 = 0; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + devm_kfree(&pdev->dev, bus); return err; } @@ -153,14 +156,24 @@ static int __devexit octeon_mdiobus_remove(struct platform_device *pdev) mdiobus_unregister(bus->mii_bus); mdiobus_free(bus->mii_bus); smi_en.u64 = 0; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + devm_kfree(&pdev->dev, bus); return 0; } -static struct platform_driver octeon_mdiobus_driver = { +static struct of_device_id octeon_mdiobus_match[] = { + { + .compatible = "octeon,mdio", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mdiobus_match); + +static struct of_platform_driver octeon_mdiobus_driver = { .driver = { .name = "mdio-octeon", .owner = THIS_MODULE, + .of_match_table = octeon_mdiobus_match, }, .probe = octeon_mdiobus_probe, .remove = __devexit_p(octeon_mdiobus_remove), @@ -174,12 +187,12 @@ EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency); static int __init octeon_mdiobus_mod_init(void) { - return platform_driver_register(&octeon_mdiobus_driver); + return of_register_platform_driver(&octeon_mdiobus_driver); } static void __exit octeon_mdiobus_mod_exit(void) { - platform_driver_unregister(&octeon_mdiobus_driver); + of_unregister_platform_driver(&octeon_mdiobus_driver); } module_init(octeon_mdiobus_mod_init); -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 22:01:56 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 22:02:04 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14032 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491779Ab1BVU6b (ORCPT ); Tue, 22 Feb 2011 21:58:31 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:21 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:28 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:28 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwNHg020937; Tue, 22 Feb 2011 12:58:23 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwNpT020936; Tue, 22 Feb 2011 12:58:23 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney , "David S. Miller" , netdev@vger.kernel.org Subject: [RFC PATCH 09/10] netdev: octeon_mgmt: Convert to use device tree. Date: Tue, 22 Feb 2011 12:57:53 -0800 Message-Id: <1298408274-20856-10-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:28.0816 (UTC) FILETIME=[4172B500:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29252 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The device tree will supply the register bank base addresses, make register addressing relative to those. PHY connection is now described by the device tree. Signed-off-by: David Daney Cc: "David S. Miller" Cc: netdev@vger.kernel.org --- arch/mips/cavium-octeon/octeon-platform.c | 62 ------- drivers/net/octeon/octeon_mgmt.c | 265 +++++++++++++++++------------ 2 files changed, 160 insertions(+), 167 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index a33dcf9..3a3867b 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -166,68 +166,6 @@ out: } device_initcall(octeon_rng_device_init); -/* Octeon mgmt port Ethernet interface. */ -static int __init octeon_mgmt_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource mgmt_port_resource = { - .flags = IORESOURCE_IRQ, - .start = -1, - .end = -1 - }; - - if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX)) - return 0; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - num_ports = 1; - else - num_ports = 2; - - for (port = 0; port < num_ports; port++) { - pd = platform_device_alloc("octeon_mgmt", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - /* No DMA restrictions */ - pd->dev.coherent_dma_mask = DMA_BIT_MASK(64); - pd->dev.dma_mask = &pd->dev.coherent_dma_mask; - - switch (port) { - case 0: - mgmt_port_resource.start = OCTEON_IRQ_MII0; - break; - case 1: - mgmt_port_resource.start = OCTEON_IRQ_MII1; - break; - default: - BUG(); - } - mgmt_port_resource.end = mgmt_port_resource.start; - - ret = platform_device_add_resources(pd, &mgmt_port_resource, 1); - - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mgmt_device_init); - #ifdef CONFIG_USB static int __init octeon_ehci_device_init(void) diff --git a/drivers/net/octeon/octeon_mgmt.c b/drivers/net/octeon/octeon_mgmt.c index b264f0f..6c301c7 100644 --- a/drivers/net/octeon/octeon_mgmt.c +++ b/drivers/net/octeon/octeon_mgmt.c @@ -6,16 +6,21 @@ * Copyright (C) 2009 Cavium Networks */ -#include -#include -#include #include -#include +#include #include +#include +#include +#include +#include +#include #include +#include +#include +#include +#include #include #include -#include #include #include @@ -55,8 +60,56 @@ union mgmt_port_ring_entry { } s; }; +#define MIX_ORING1 0x0 +#define MIX_ORING2 0x8 +#define MIX_IRING1 0x10 +#define MIX_IRING2 0x18 +#define MIX_CTL 0x20 +#define MIX_IRHWM 0x28 +#define MIX_IRCNT 0x30 +#define MIX_ORHWM 0x38 +#define MIX_ORCNT 0x40 +#define MIX_ISR 0x48 +#define MIX_INTENA 0x50 +#define MIX_REMCNT 0x58 +#define MIX_BIST 0x78 + +#define AGL_GMX_PRT_CFG 0x10 +#define AGL_GMX_RX_FRM_CTL 0x18 +#define AGL_GMX_RX_FRM_MAX 0x30 +#define AGL_GMX_RX_JABBER 0x38 +#define AGL_GMX_RX_STATS_CTL 0x50 + +#define AGL_GMX_RX_STATS_PKTS_DRP 0xb0 +#define AGL_GMX_RX_STATS_OCTS_DRP 0xb8 +#define AGL_GMX_RX_STATS_PKTS_BAD 0xc0 + +#define AGL_GMX_RX_ADR_CTL 0x100 +#define AGL_GMX_RX_ADR_CAM_EN 0x108 +#define AGL_GMX_RX_ADR_CAM0 0x180 +#define AGL_GMX_RX_ADR_CAM1 0x188 +#define AGL_GMX_RX_ADR_CAM2 0x190 +#define AGL_GMX_RX_ADR_CAM3 0x198 +#define AGL_GMX_RX_ADR_CAM4 0x1a0 +#define AGL_GMX_RX_ADR_CAM5 0x1a8 + +#define AGL_GMX_TX_STATS_CTL 0x268 +#define AGL_GMX_TX_CTL 0x270 +#define AGL_GMX_TX_STAT0 0x280 +#define AGL_GMX_TX_STAT1 0x288 +#define AGL_GMX_TX_STAT2 0x290 +#define AGL_GMX_TX_STAT3 0x298 +#define AGL_GMX_TX_STAT4 0x2a0 +#define AGL_GMX_TX_STAT5 0x2a8 +#define AGL_GMX_TX_STAT6 0x2b0 +#define AGL_GMX_TX_STAT7 0x2b8 +#define AGL_GMX_TX_STAT8 0x2c0 +#define AGL_GMX_TX_STAT9 0x2c8 + struct octeon_mgmt { struct net_device *netdev; + u64 mix; + u64 agl; int port; int irq; u64 *tx_ring; @@ -82,31 +135,30 @@ struct octeon_mgmt { struct napi_struct napi; struct tasklet_struct tx_clean_tasklet; struct phy_device *phydev; + struct device_node *phy_np; }; static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) { - int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); + mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); mix_intena.s.ithena = enable ? 1 : 0; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) { - int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); + mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); mix_intena.s.othena = enable ? 1 : 0; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -143,7 +195,6 @@ static unsigned int ring_size_to_bytes(unsigned int ring_size) static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) { unsigned int size; @@ -174,24 +225,23 @@ static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE; p->rx_current_fill++; /* Ring the bell. */ - cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); + cvmx_write_csr(p->mix + MIX_IRING2, 1); } } static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) { - int port = p->port; union cvmx_mixx_orcnt mix_orcnt; union mgmt_port_ring_entry re; struct sk_buff *skb; int cleaned = 0; unsigned long flags; - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); while (mix_orcnt.s.orcnt) { spin_lock_irqsave(&p->tx_list.lock, flags); - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); if (mix_orcnt.s.orcnt == 0) { spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -211,7 +261,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) mix_orcnt.s.orcnt = 1; /* Acknowledge to hardware that we have the buffer. */ - cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64); + cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); p->tx_current_fill--; spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -221,7 +271,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) dev_kfree_skb_any(skb); cleaned++; - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); } if (cleaned && netif_queue_stopped(p->netdev)) @@ -238,13 +288,12 @@ static void octeon_mgmt_clean_tx_tasklet(unsigned long arg) static void octeon_mgmt_update_rx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; unsigned long flags; u64 drop, bad; /* These reads also clear the count registers. */ - drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port)); - bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port)); + drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP); + bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD); if (drop || bad) { /* Do an atomic update. */ @@ -258,15 +307,14 @@ static void octeon_mgmt_update_rx_stats(struct net_device *netdev) static void octeon_mgmt_update_tx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; unsigned long flags; union cvmx_agl_gmx_txx_stat0 s0; union cvmx_agl_gmx_txx_stat1 s1; /* These reads also clear the count registers. */ - s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port)); - s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port)); + s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); + s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1); if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { /* Do an atomic update. */ @@ -305,7 +353,6 @@ static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p, static int octeon_mgmt_receive_one(struct octeon_mgmt *p) { - int port = p->port; struct net_device *netdev = p->netdev; union cvmx_mixx_ircnt mix_ircnt; union mgmt_port_ring_entry re; @@ -378,18 +425,17 @@ done: /* Tell the hardware we processed a packet. */ mix_ircnt.u64 = 0; mix_ircnt.s.ircnt = 1; - cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64); + cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); return rc; } static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) { - int port = p->port; unsigned int work_done = 0; union cvmx_mixx_ircnt mix_ircnt; int rc; - mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); + mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); while (work_done < budget && mix_ircnt.s.ircnt) { rc = octeon_mgmt_receive_one(p); @@ -397,7 +443,7 @@ static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) work_done++; /* Check for more packets. */ - mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); + mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); } octeon_mgmt_rx_fill_ring(p->netdev); @@ -431,16 +477,16 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) union cvmx_agl_gmx_bist agl_gmx_bist; mix_ctl.u64 = 0; - cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); } while (mix_ctl.s.busy); mix_ctl.s.reset = 1; - cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); - cvmx_read_csr(CVMX_MIXX_CTL(p->port)); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); + cvmx_read_csr(p->mix + MIX_CTL); cvmx_wait(64); - mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port)); + mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); if (mix_bist.u64) dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n", (unsigned long long)mix_bist.u64); @@ -471,7 +517,6 @@ static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs, static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_agl_gmx_rxx_adr_ctl adr_ctl; union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx; unsigned long flags; @@ -517,29 +562,29 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) spin_lock_irqsave(&p->lock, flags); /* Disable packet I/O. */ - agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prev_packet_enable = agl_gmx_prtx.s.en; agl_gmx_prtx.s.en = 0; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); adr_ctl.u64 = 0; adr_ctl.s.cam_mode = cam_mode; adr_ctl.s.mcst = multicast_mode; adr_ctl.s.bcst = 1; /* Allow broadcast */ - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask); /* Restore packet I/O. */ agl_gmx_prtx.s.en = prev_packet_enable; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -561,7 +606,6 @@ static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; /* @@ -577,8 +621,8 @@ static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) netdev->mtu = new_mtu; - cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs); - cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, size_without_fcs); + cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER, (size_without_fcs + 7) & 0xfff8); return 0; @@ -588,14 +632,13 @@ static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) { struct net_device *netdev = dev_id; struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_mixx_isr mixx_isr; - mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port)); + mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR); /* Clear any pending interrupts */ - cvmx_write_csr(CVMX_MIXX_ISR(port), mixx_isr.u64); - cvmx_read_csr(CVMX_MIXX_ISR(port)); + cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64); + cvmx_read_csr(p->mix + MIX_ISR); if (mixx_isr.s.irthresh) { octeon_mgmt_disable_rx_irq(p); @@ -626,7 +669,6 @@ static int octeon_mgmt_ioctl(struct net_device *netdev, static void octeon_mgmt_adjust_link(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_agl_gmx_prtx_cfg prtx_cfg; unsigned long flags; int link_changed = 0; @@ -637,11 +679,9 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) link_changed = 1; if (p->last_duplex != p->phydev->duplex) { p->last_duplex = p->phydev->duplex; - prtx_cfg.u64 = - cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.duplex = p->phydev->duplex; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), - prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); } } else { if (p->last_link) @@ -667,18 +707,16 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) static int octeon_mgmt_init_phy(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - char phy_id[20]; - if (octeon_is_simulation()) { + if (octeon_is_simulation() || p->phy_np == NULL) { /* No PHYs in the simulator. */ netif_carrier_on(netdev); return 0; } - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", p->port); - - p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0, - PHY_INTERFACE_MODE_MII); + p->phydev = of_phy_connect(netdev, p->phy_np, + octeon_mgmt_adjust_link, 0, + PHY_INTERFACE_MODE_MII); if (IS_ERR(p->phydev)) { p->phydev = NULL; @@ -734,14 +772,14 @@ static int octeon_mgmt_open(struct net_device *netdev) octeon_mgmt_reset_hw(p); - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); /* Bring it out of reset if needed. */ if (mix_ctl.s.reset) { mix_ctl.s.reset = 0; - cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); } while (mix_ctl.s.reset); } @@ -752,17 +790,17 @@ static int octeon_mgmt_open(struct net_device *netdev) oring1.u64 = 0; oring1.s.obase = p->tx_ring_handle >> 3; oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE; - cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64); + cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64); iring1.u64 = 0; iring1.s.ibase = p->rx_ring_handle >> 3; iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; - cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64); + cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); /* Disable packet I/O. */ - prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.en = 0; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); octeon_mgmt_set_mac_address(netdev, &sa); @@ -779,7 +817,7 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_ctl.s.nbtarb = 0; /* Arbitration mode */ /* MII CB-request FIFO programmable high watermark */ mix_ctl.s.mrq_hwm = 1; - cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { @@ -806,16 +844,16 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Clear statistics. */ /* Clear on read. */ - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1); - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0); - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0); + cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1); + cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0); + cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0); /* Clear any pending interrupts */ - cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port))); + cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name, netdev)) { @@ -826,18 +864,18 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Interrupt every single RX packet */ mix_irhwm.u64 = 0; mix_irhwm.s.irhwm = 0; - cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64); + cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64); /* Interrupt when we have 1 or more packets to clean. */ mix_orhwm.u64 = 0; mix_orhwm.s.orhwm = 1; - cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64); + cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); /* Enable receive and transmit interrupts */ mix_intena.u64 = 0; mix_intena.s.ithena = 1; mix_intena.s.othena = 1; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); /* Enable packet I/O. */ @@ -868,7 +906,7 @@ static int octeon_mgmt_open(struct net_device *netdev) * frame. GMX checks that the PREAMBLE is sent correctly. */ rxx_frm_ctl.s.pre_chk = 1; - cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); /* Enable the AGL block */ agl_gmx_inf_mode.u64 = 0; @@ -876,13 +914,13 @@ static int octeon_mgmt_open(struct net_device *netdev) cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); /* Configure the port duplex and enables */ - prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.tx_en = 1; prtx_cfg.s.rx_en = 1; prtx_cfg.s.en = 1; p->last_duplex = 1; prtx_cfg.s.duplex = p->last_duplex; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); p->last_link = 0; netif_carrier_off(netdev); @@ -946,7 +984,6 @@ static int octeon_mgmt_stop(struct net_device *netdev) static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union mgmt_port_ring_entry re; unsigned long flags; int rv = NETDEV_TX_BUSY; @@ -990,7 +1027,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) netdev->stats.tx_bytes += skb->len; /* Ring the bell. */ - cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); + cvmx_write_csr(p->mix + MIX_ORING2, 1); rv = NETDEV_TX_OK; out: @@ -1067,12 +1104,14 @@ static const struct net_device_ops octeon_mgmt_ops = { #endif }; -static int __devinit octeon_mgmt_probe(struct platform_device *pdev) +static int __devinit octeon_mgmt_probe(struct platform_device *pdev, + const struct of_device_id *match) { - struct resource *res_irq; struct net_device *netdev; struct octeon_mgmt *p; - int i; + const __be32 *data; + const u8 *mac; + int len; netdev = alloc_etherdev(sizeof(struct octeon_mgmt)); if (netdev == NULL) @@ -1086,14 +1125,21 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) p->netdev = netdev; p->dev = &pdev->dev; - p->port = pdev->id; + data = of_get_property(pdev->dev.of_node, "unit-number", &len); + if (data && len == sizeof(*data)) + p->port = be32_to_cpup(data); + else + p->port = 0; + snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port); - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_irq) + p->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + if (!p->irq) goto err; - p->irq = res_irq->start; + p->mix = (u64)of_iomap(pdev->dev.of_node, 0); + p->agl = (u64)of_iomap(pdev->dev.of_node, 1); + spin_lock_init(&p->lock); skb_queue_head_init(&p->tx_list); @@ -1104,15 +1150,15 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) netdev->netdev_ops = &octeon_mgmt_ops; netdev->ethtool_ops = &octeon_mgmt_ethtool_ops; - /* The mgmt ports get the first N MACs. */ - for (i = 0; i < 6; i++) - netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i]; - netdev->dev_addr[5] += p->port; + mac = of_get_mac_address(pdev->dev.of_node); + + if (mac) + memcpy(netdev->dev_addr, mac, 6); - if (p->port >= octeon_bootinfo->mac_addr_count) - dev_err(&pdev->dev, - "Error %s: Using MAC outside of the assigned range: %pM\n", - netdev->name, netdev->dev_addr); + p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); + + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; if (register_netdev(netdev)) goto err; @@ -1133,10 +1179,19 @@ static int __devexit octeon_mgmt_remove(struct platform_device *pdev) return 0; } -static struct platform_driver octeon_mgmt_driver = { +static struct of_device_id octeon_mgmt_match[] = { + { + .compatible = "octeon,mgmt", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mgmt_match); + +static struct of_platform_driver octeon_mgmt_driver = { .driver = { .name = "octeon_mgmt", .owner = THIS_MODULE, + .of_match_table = octeon_mgmt_match, }, .probe = octeon_mgmt_probe, .remove = __devexit_p(octeon_mgmt_remove), @@ -1148,12 +1203,12 @@ static int __init octeon_mgmt_mod_init(void) { /* Force our mdiobus driver module to be loaded first. */ octeon_mdiobus_force_mod_depencency(); - return platform_driver_register(&octeon_mgmt_driver); + return of_register_platform_driver(&octeon_mgmt_driver); } static void __exit octeon_mgmt_mod_exit(void) { - platform_driver_unregister(&octeon_mgmt_driver); + of_unregister_platform_driver(&octeon_mgmt_driver); } module_init(octeon_mgmt_mod_init); -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Feb 22 22:02:23 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 22 Feb 2011 22:02:30 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14040 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491766Ab1BVU6b (ORCPT ); Tue, 22 Feb 2011 21:58:31 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 22 Feb 2011 12:59:23 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:30 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 22 Feb 2011 12:58:30 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id p1MKwOYh020942; Tue, 22 Feb 2011 12:58:25 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id p1MKwOHl020941; Tue, 22 Feb 2011 12:58:24 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney , "David S. Miller" , netdev@vger.kernel.org Subject: [RFC PATCH 10/10] staging: octeon_ethernet: Convert to use device tree. Date: Tue, 22 Feb 2011 12:57:54 -0800 Message-Id: <1298408274-20856-11-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 22 Feb 2011 20:58:30.0082 (UTC) FILETIME=[4233E220:01CBD2D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29253 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Get MAC address and PHY connection from the device tree. Signed-off-by: David Daney Cc: "David S. Miller" Cc: netdev@vger.kernel.org --- drivers/staging/octeon/ethernet-mdio.c | 27 +++++---- drivers/staging/octeon/ethernet.c | 101 +++++++++++++++++++----------- drivers/staging/octeon/octeon-ethernet.h | 3 + 3 files changed, 82 insertions(+), 49 deletions(-) diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 0e5dab7..38a0153 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -27,6 +27,7 @@ #include #include #include +#include #include @@ -162,22 +163,24 @@ static void cvm_oct_adjust_link(struct net_device *dev) int cvm_oct_phy_setup_device(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); + struct device_node *phy_node; - int phy_addr = cvmx_helper_board_get_mii_address(priv->port); - if (phy_addr != -1) { - char phy_id[20]; + if (!priv->of_node) + return 0; - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", phy_addr); + phy_node = of_parse_phandle(priv->of_node, "phy-handle", 0); + if (!phy_node) + return 0; - priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, - PHY_INTERFACE_MODE_GMII); + priv->phydev = of_phy_connect(dev, phy_node, cvm_oct_adjust_link, 0, + PHY_INTERFACE_MODE_GMII); - if (IS_ERR(priv->phydev)) { - priv->phydev = NULL; - return -1; - } - priv->last_link = 0; - phy_start_aneg(priv->phydev); + if (IS_ERR(priv->phydev)) { + priv->phydev = NULL; + return -1; } + priv->last_link = 0; + phy_start_aneg(priv->phydev); + return 0; } diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 042adf7..87f8956 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -31,6 +31,7 @@ #include #include #include +#include #include @@ -112,15 +113,6 @@ int rx_napi_weight = 32; module_param(rx_napi_weight, int, 0444); MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter."); -/* - * The offset from mac_addr_base that should be used for the next port - * that is configured. By convention, if any mgmt ports exist on the - * chip, they get the first mac addresses, The ports controlled by - * this driver are numbered sequencially following any mgmt addresses - * that may exist. - */ -static unsigned int cvm_oct_mac_addr_offset; - /** * cvm_oct_poll_queue - Workqueue for polling operations. */ @@ -447,26 +439,13 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) int cvm_oct_common_init(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); - struct sockaddr sa; - u64 mac = ((u64)(octeon_bootinfo->mac_addr_base[0] & 0xff) << 40) | - ((u64)(octeon_bootinfo->mac_addr_base[1] & 0xff) << 32) | - ((u64)(octeon_bootinfo->mac_addr_base[2] & 0xff) << 24) | - ((u64)(octeon_bootinfo->mac_addr_base[3] & 0xff) << 16) | - ((u64)(octeon_bootinfo->mac_addr_base[4] & 0xff) << 8) | - (u64)(octeon_bootinfo->mac_addr_base[5] & 0xff); - - mac += cvm_oct_mac_addr_offset; - sa.sa_data[0] = (mac >> 40) & 0xff; - sa.sa_data[1] = (mac >> 32) & 0xff; - sa.sa_data[2] = (mac >> 24) & 0xff; - sa.sa_data[3] = (mac >> 16) & 0xff; - sa.sa_data[4] = (mac >> 8) & 0xff; - sa.sa_data[5] = mac & 0xff; - - if (cvm_oct_mac_addr_offset >= octeon_bootinfo->mac_addr_count) - printk(KERN_DEBUG "%s: Using MAC outside of the assigned range:" - " %pM\n", dev->name, sa.sa_data); - cvm_oct_mac_addr_offset++; + struct sockaddr sa = {0}; + + if (priv->of_node) { + const u8 *mac = of_get_mac_address(priv->of_node); + if (mac) + memcpy(sa.sa_data, mac, 6); + } /* * Force the interface to use the POW send if always_use_pow @@ -594,22 +573,68 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = { extern void octeon_mdiobus_force_mod_depencency(void); +static struct device_node * __init cvm_oct_of_get_child(const struct device_node *parent, + int reg_val) +{ + struct device_node *node = NULL; + int size; + const __be32 *addr; + + for (;;) { + node = of_get_next_child(parent, node); + if (!node) + break; + addr = of_get_property(node, "reg", &size); + if (addr && (be32_to_cpu(*addr) == reg_val)) + break; + } + return node; +} + +static struct device_node * __init cvm_oct_node_for_port(struct device_node *pip, + int interface, int port) +{ + struct device_node *ni, *np; + + ni = cvm_oct_of_get_child(pip, interface); + if (!ni) + return NULL; + + np = cvm_oct_of_get_child(ni, port); + of_node_put(ni); + + return np; +} + static int __init cvm_oct_init_module(void) { int num_interfaces; int interface; int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; int qos; + struct device_node *aliases; + const char *node_path; + struct device_node *pip; octeon_mdiobus_force_mod_depencency(); pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) - cvm_oct_mac_addr_offset = 2; /* First two are the mgmt ports. */ - else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - cvm_oct_mac_addr_offset = 1; /* First one is the mgmt port. */ - else - cvm_oct_mac_addr_offset = 0; + + aliases = of_find_node_by_path("/aliases"); + if (!aliases) { + pr_err("Error: No /aliases node in device tree."); + return -EINVAL; + } + node_path = of_get_property(aliases, "pip", NULL); + if (!node_path) { + pr_err("Error: No /aliases/pip node in device tree."); + return -EINVAL; + } + pip = of_find_node_by_path(node_path); + if (!pip) { + pr_err("Error: No %s in device tree.", node_path); + return -EINVAL; + } cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet"); if (cvm_oct_poll_queue == NULL) { @@ -688,10 +713,11 @@ static int __init cvm_oct_init_module(void) cvmx_helper_interface_get_mode(interface); int num_ports = cvmx_helper_ports_on_interface(interface); int port; + int port_index; - for (port = cvmx_helper_get_ipd_port(interface, 0); + for (port_index = 0, port = cvmx_helper_get_ipd_port(interface, 0); port < cvmx_helper_get_ipd_port(interface, num_ports); - port++) { + port_index++, port++) { struct octeon_ethernet *priv; struct net_device *dev = alloc_etherdev(sizeof(struct octeon_ethernet)); @@ -702,6 +728,7 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ priv = netdev_priv(dev); + priv->of_node = cvm_oct_node_for_port(pip, interface, port_index); INIT_DELAYED_WORK(&priv->port_periodic_work, cvm_oct_periodic_worker); diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index d581925..9360e22 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -31,6 +31,8 @@ #ifndef OCTEON_ETHERNET_H #define OCTEON_ETHERNET_H +#include + /** * This is the definition of the Ethernet driver's private * driver state stored in netdev_priv(dev). @@ -59,6 +61,7 @@ struct octeon_ethernet { void (*poll) (struct net_device *dev); struct delayed_work port_periodic_work; struct work_struct port_work; /* may be unused. */ + struct device_node *of_node; }; int cvm_oct_free_work(void *work_queue_entry); -- 1.7.2.3 From dgibson@ozlabs.org Wed Feb 23 01:36:43 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Feb 2011 01:37:06 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:38324 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491115Ab1BWAgn (ORCPT ); Wed, 23 Feb 2011 01:36:43 +0100 Received: by ozlabs.org (Postfix, from userid 1007) id AEA75B70E2; Wed, 23 Feb 2011 11:36:37 +1100 (EST) Date: Wed, 23 Feb 2011 11:07:59 +1100 From: David Gibson To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 02/10] MIPS: Octeon: Add device tree source files. Message-ID: <20110223000759.GA26300@yookeroo> Mail-Followup-To: David Gibson , David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> <1298408274-20856-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1298408274-20856-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29254 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david@gibson.dropbear.id.au Precedence: bulk X-list: linux-mips On Tue, Feb 22, 2011 at 12:57:46PM -0800, David Daney wrote: > Signed-off-by: David Daney > --- > arch/mips/cavium-octeon/.gitignore | 2 + > arch/mips/cavium-octeon/Makefile | 13 ++ > arch/mips/cavium-octeon/octeon_3xxx.dts | 314 +++++++++++++++++++++++++++++++ > arch/mips/cavium-octeon/octeon_68xx.dts | 99 ++++++++++ > 4 files changed, 428 insertions(+), 0 deletions(-) > create mode 100644 arch/mips/cavium-octeon/.gitignore > create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts > create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts > > diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore > new file mode 100644 > index 0000000..39c9686 > --- /dev/null > +++ b/arch/mips/cavium-octeon/.gitignore > @@ -0,0 +1,2 @@ > +*.dtb.S .dtb.S? [snip] > +/dts-v1/; > +/* OCTEON 3XXX, 5XXX, 63XX device tree skeleton. */ > +/ { > + model = "OCTEON"; 1 tab indents are the usual convention for device trees. > + compatible = "octeon,octeon"; There's no model number at all for this board? > + #address-cells = <2>; > + #size-cells = <2>; > + > + soc@0 { > + device_type = "soc"; Drop this device_type. > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; /* Direct mapping */ > + > + ciu: ciu-3xxx@1070000000000 { > + compatible = "octeon,ciu-3xxx"; So, names or compatible values with "wildcards" like 3xxx should be avoided. Instead, use the specific model number of this device, then future devices can claim compatibility with the earlier one. But, in addition the generic names convention means that the node name should be "interrupt-controller" rather than something model specific. > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + reg = <0x10700 0x00000000 0x0 0x7000>; > + }; > + > + /* SMI0 */ > + mdio0: mdio@1180000001800 { If SMI0 is the name generally used in the documentation, using that in the label instead of mdio0 might be more useful. > + compatible = "octeon,mdio"; No model or revision number? > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0x00001800 0x0 0x40>; > + device_type = "mdio"; Drop this device_type. > + > + phy0: ethernet-phy@0 { > + reg = <0>; > + }; > + > + phy1: ethernet-phy@1 { > + reg = <1>; > + }; > + > + phy2: ethernet-phy@2 { > + reg = <2>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy3: ethernet-phy@3 { > + reg = <3>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy4: ethernet-phy@4 { > + reg = <4>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy5: ethernet-phy@5 { > + reg = <5>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + > + phy6: ethernet-phy@6 { > + reg = <6>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy7: ethernet-phy@7 { > + reg = <7>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy8: ethernet-phy@8 { > + reg = <8>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + phy9: ethernet-phy@9 { > + reg = <9>; > + marvell,reg-init = <3 0x10 0 0x5777>, > + <3 0x11 0 0x00aa>, > + <3 0x12 0 0x4105>, > + <3 0x13 0 0x0a60>; > + }; > + }; > + > + /* SMI1 */ > + mdio1: mdio@1180000001900 { > + compatible = "octeon,mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0x00001900 0x0 0x40>; > + device_type = "mdio"; > + }; > + > + mgmt0: ethernet@1070000100000 { > + compatible = "octeon,mgmt"; > + device_type = "network"; > + model = "mgmt"; > + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ > + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ > + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ > + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ > + unit-number = <0>; What is this 'unit-number' property for? > + interrupt-parent = <&ciu>; > + interrupts = <0 62>, <1 46>; > + local-mac-address = [ 00 00 00 00 00 00 ]; That's not a valid MAC address of course. If this has to be patched in by the bootloader / later processing, you should add a comment to that effect. > + phy-handle = <&phy0>; > + }; > + > + mgmt1: ethernet@1070000100800 { > + compatible = "octeon,mgmt"; > + device_type = "network"; > + model = "mgmt"; > + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ > + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ > + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ > + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ > + unit-number = <1>; > + interrupt-parent = <&ciu>; > + interrupts = <1 18>, < 1 46>; > + local-mac-address = [ 00 00 00 00 00 00 ]; > + phy-handle = <&phy1>; > + }; > + > + pip: pip@11800a0000000 { > + compatible = "octeon,pip"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x11800 0xa0000000 0x0 0x2000>; > + > + interface@0 { These subnodes and subsubnodes should have compatible values too, even if it's just "octeon,pip-interface" and "octeon,pip-ethernet". > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; /* interface */ > + > + ethernet@0 { > + device_type = "network"; > + model = "pip"; This model property doesn't look very useful. [snip] > + /* TWSI 0 */ > + i2c0: i2c@1180000001000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "octeon,twsi"; > + reg = <0x11800 0x00001000 0x0 0x200>; > + interrupt-parent = <&ciu>; > + interrupts = <0 45>; > + clock-rate = <100000>; > + > + rtc@68 { > + compatible = "dallas,ds1337"; > + reg = <0x68>; > + }; > + }; > + > + /* TWSI 1 */ > + i2c1: i2c@1180000001200 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "octeon,twsi"; > + reg = <0x11800 0x00001200 0x0 0x200>; > + interrupt-parent = <&ciu>; > + interrupts = <0 59>; > + clock-rate = <100000>; > + }; > + }; Uh.. where are the CPUs? -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson From dgibson@ozlabs.org Wed Feb 23 01:37:25 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Feb 2011 01:37:48 +0100 (CET) Received: from ozlabs.org ([203.10.76.45]:38327 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491770Ab1BWAgo (ORCPT ); Wed, 23 Feb 2011 01:36:44 +0100 Received: by ozlabs.org (Postfix, from userid 1007) id 8398BB6F10; Wed, 23 Feb 2011 11:36:40 +1100 (EST) Date: Wed, 23 Feb 2011 11:16:39 +1100 From: David Gibson To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 06/10] MIPS: Octeon: Initialize and fixup device tree. Message-ID: <20110223001639.GB26300@yookeroo> Mail-Followup-To: David Gibson , David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org References: <1298408274-20856-1-git-send-email-ddaney@caviumnetworks.com> <1298408274-20856-7-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1298408274-20856-7-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29255 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david@gibson.dropbear.id.au Precedence: bulk X-list: linux-mips [snip] > +} > + > +static int __init set_mac_addr_prop(struct device_node *n, u64 mac) > +{ > + u8 *vp; > + struct property *old_p; > + struct property *p = kzalloc(sizeof(struct device_node) + 6, GFP_KERNEL); > + if (!p) > + return -ENOMEM; > + /* The value will immediatly follow the node in memory. */ > + vp = (u8 *)(&p[1]); > + p->name = "local-mac-address"; > + p->length = 6; > + p->value = vp; > + > + vp[0] = (mac >> 40) & 0xff; > + vp[1] = (mac >> 32) & 0xff; > + vp[2] = (mac >> 24) & 0xff; > + vp[3] = (mac >> 16) & 0xff; > + vp[4] = (mac >> 8) & 0xff; > + vp[5] = mac & 0xff; > + > + old_p = of_find_property(n, "local-mac-address", NULL); > + if (old_p) > + prom_remove_property(n, old_p); > + return prom_add_property(n, p); Hrm, since you entirely remove and replace the local-mac-address property here, I don't see much point to having the property with a bogus value in the .dts. [snip] > +int __init octeon_prune_device_tree(void) > +{ > + int i, p, max_port; > + const char *node_path; > + char name_buffer[20]; > + struct device_node *aliases; > + struct device_node *pip; > + struct device_node *iface; > + struct device_node *eth; > + struct device_node *node; > + > + aliases = of_find_node_by_path("/aliases"); > + if (!aliases) { > + pr_err("Error: No /aliases node in device tree."); > + return -EINVAL; > + } Ok, I think the .dts could do with some more comments indicating that it will be subject to extensive pruning before use. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson From yad.naveen@gmail.com Wed Feb 23 04:47:16 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Feb 2011 04:47:19 +0100 (CET) Received: from mail-vx0-f177.google.com ([209.85.220.177]:47918 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490956Ab1BWDrQ convert rfc822-to-8bit (ORCPT ); Wed, 23 Feb 2011 04:47:16 +0100 Received: by vxd2 with SMTP id 2so1474749vxd.36 for ; Tue, 22 Feb 2011 19:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=BkCGEJv7UhFogvi9Mj0zlSjiP584SX80047XVEWOhtk=; b=sQLLH68GHOrKy4KYqDejMWhvSxEjtUCWS63RZz37m1naaQEZGiOfjHjUN1ERPjMZrY u8SVYCXFydQvSmxOGGD0KnjtxuqMBr4Tx2pkghMnmWqf31fS3W/6QIU7jLsxHaVprEPf WVVARmdZVVFJKYbw9rrKK1aCx0l1hOqrGSz/8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=rRKSLnmpGxhTCAwSyt3u4DG6Tsxewb/hxIyQ8E18cwXuAcLKfOd8oMwIRCaBWkKuaB Fgm2Jcif3zd3xyMwb7TTEO1jClXAa4cCjDHTzBl0Mz3Iy8aXqh9DnSg+6WKXhVeXAInQ ivpKl9DjVl7cl18iMVFM76nOEn98de8dmrI/4= MIME-Version: 1.0 Received: by 10.52.158.196 with SMTP id ww4mr5267903vdb.220.1298432828825; Tue, 22 Feb 2011 19:47:08 -0800 (PST) Received: by 10.52.161.104 with HTTP; Tue, 22 Feb 2011 19:47:08 -0800 (PST) In-Reply-To: References: Date: Wed, 23 Feb 2011 09:17:08 +0530 Message-ID: Subject: Re: Issue on 2.6.35.9 kernel with module insertion when Rootfs is NFS mounted From: naveen yadav To: Mulyadi Santosa , linux-mips@linux-mips.org Cc: kernelnewbies@nl.linux.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29256 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Hi all, We investigated the problem and found out that there is some config issue. The config option was the problem:- Symbol: NFSD_V4 [=n] Prompt: NFS server support for NFS version 4 (EXPERIMENTAL) Defined at fs/nfsd/Kconfig:67 Depends on: NETWORK_FILESYSTEMS [=y] && NFSD [=n] && PROC_FS [=y] && EXPERIMENTAL [=y] Location: -> File systems -> Network File Systems (NETWORK_FILESYSTEMS [=y]) -> NFS server support (NFSD [=n]) Selects: NFSD_V3 [=n] && FS_POSIX_ACL [=y] && RPCSEC_GSS_KRB5 [=y] Thanks On Tue, Feb 22, 2011 at 9:22 AM, naveen yadav wrote: > Hi , > > Thanks for your answer, > > Yes I am sure it is from same kernel and sams GCC version, > The same module if put in Initiramfs, works fine. only issue occur > when I build kernel with rootfs mounted from NFS. > > > On Mon, Feb 21, 2011 at 11:03 PM, Mulyadi Santosa > wrote: >> Hi :) >> >> On Mon, Feb 21, 2011 at 20:07, naveen yadav wrote: >>> Hi All, >>> >>> When I am trying to insert some modules on 2.6.35.9, I am getting some >>> random crash's. >>> There are 2 scenarios:- >>> >>> 1) When my rootfs is NFS mounted. >>> >>> In this case, when I insmod modules some get inserted and some gives crash. >>> I have tried with following modules :- >>> a)      ext2.ko ; size 93K ; status - successfully inserted >>> b)      ext3.ko ; size 188K ; status - insertion failed >>> c)      xfs.ko ; size 823K ; status - insertion failed >>> d)      usbcore.ko ; size 243K ; status - insertion failed >>> >>> 2) When I created kernel Image using Initramfs, hence making all >>> modules part of ramfs image >>> all insertions are successfull >> >> Hm, easiest thing first to check: are you sure you are inserting >> modules that belongs to the currently running kernel's version? and >> they were compiled with the same gcc options? >> >> And furthermore, if they use symbol versioning, are they belong to the >> same symbol version? >> >> -- >> regards, >> >> Mulyadi Santosa >> Freelance Linux trainer and consultant >> >> blog: the-hydra.blogspot.com >> training: mulyaditraining.blogspot.com >> > From anoop.pa@gmail.com Wed Feb 23 13:59:10 2011 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 23 Feb 2011 13:59:13 +0100 (CET) Received: from mail-vx0-f177.google.com ([209.85.220.177]:56551 "EHLO mail-vx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491120Ab1BWM7K (ORCPT ); Wed, 23 Feb 2011 13:59:10 +0100 Received: by vxd2 with SMTP id 2so1726397vxd.36 for ; Wed, 23 Feb 2011 04:59:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:subject:from:to:cc:in-reply-to:references :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=PHRZA81oso+Gz90/KaMLqrLXwLP3ogqK0hAEC0YH93A=; b=dmHhKBkgGerk5h7czyvSnsuyZmIb2OFjFMWsBBfx2Jqnb5tWOF0vXcbisLcHIjzjHi N6y62QmQf4mgkkEh9ebMvm0WG+vAZihR6ET2JpRE4JSlvW2Dy7EcHORgHv3Buwfd5jOM 5N6dj1gEYL0yc+L17+b8SY87em0kdSkY7MV20= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=p2iMQDMXfhhx/6AzV/pXViV1envzkYmRTOjaLwYFB5bGRrBt69oP9W9rFCCBD9a2xE sqqCf91KVBCtTFUakej9uThF+8wp2gT0O2qvKruve2Zc6Z46kHZ8HepxQipvWGzofQ0K Ah4366PWff9oDOkFWGuOdDYSKY9QEwN/mjz78= Received: by 10.220.202.196 with SMTP id ff4mr854032vcb.256.1298465943341; Wed, 23 Feb 2011 04:59:03 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id e10sm3520990vch.19.2011.02.23.04.58.56 (version=SSLv3 cipher=OTHER); Wed, 23 Feb 2011 04:59:01 -0800 (PST) Subject: Re: [PATCH v5] EHCI bus glue for on-chip PMC MSP USB controller From: Anoop P A To: Dan Carpenter Cc: "gregkh @ suse . de" , "dbrownell @ users . sourceforge . net" , "stern @ rowland . harvard . edu" , "pkondeti @ codeaurora . org" , "jacob . jun . pan @ intel . com" , "linux-usb @ vger . kernel . org" , "alek . du @ intel . com" , "linux-kernel @ vger . kernel . org" , "gadiyar @ ti . com" , "ralf @ linux-mips . org" , "linux-mips @ linux-mips . org" , Greg KH In-Reply-To: <20110222200427.GB1966@bicker> References: <4D5ABB65.3090101@parrot.com> <1298388933-13707-1-git-send-email-anoop.pa@gmail.com> <20110222200427.GB1966@bicker> Content-Type: text/plain; charset="UTF-8" Date: Wed, 23 Feb 2011 18:52:23 +0530 Message-ID: <1298467343.9950.119.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 29257 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2011-02-22 at 23:04 +0300, Dan Carpenter wrote: > On Tue, Feb 22, 2011 at 09:05:33PM +0530, Anoop P.A wrote: > > From: Anoop > > > > This patch add bus glue for USB controller commonly found in PMC-Sierra MSP71xx family of SoC's. > > > > > > Signed-off-by: Anoop P A > > --- > > Changes. > > ehci-pmcmsp.c is based on latest ehci-pci.c.Addressed some stylistic issue pointed by Greg. > > Addressed comments from Matthieu CASTET. > > Could you spell that out more completely next time? OK > > > +config USB_EHCI_HCD_PMC_MSP > > + tristate "EHCI support for on-chip PMC MSP USB controller" > > Better to say "EHCI support for on-chip PMC-Sierra MSP71xx USB controllers" Ok will change that > > > + depends on USB_EHCI_HCD && MSP_HAS_USB > > + default y > > New features always default to No. O.k > > > +#include > > Cannot find the msp_usb.h in linux-next. Doesn't compile. msp_usb.h has made it's way to linux-mips queue tree along with the platform code > > > +static void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) > > +{ > > + u8 *base; > > + u8 *statreg; > > + u8 *fiforeg; > > + u32 val; > > + struct ehci_regs *reg_base = ehci->regs; > > + > > + /* get register base */ > > + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; > > + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; > > + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; > > + > > + /* Disable controller mode stream */ > > + val = ehci_readl(ehci, (u32 *)base); > > It doesn't compile so I can't test this, but I think that this will > cause a sparse warning. "base" should have an __iomem tag. Please > run sparse on this driver. Looks like mips platform build has been broken on linux-next ( unable to configure) . However I have tested code with linux-queue tree ( mips) and didn't see any such warnings > > > +/* called after powerup, by probe or system-pm "wakeup" */ > > +static int ehci_msp_reinit(struct ehci_hcd *ehci) > > +{ > > + ehci_port_power(ehci, 0); > > + > > + return 0; > > Better to make this function void. O.K > > > +} > > + > > +/* called during probe() after chip reset completes */ > > +static int ehci_msp_setup(struct usb_hcd *hcd) > > +{ > > + struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > + u32 temp; > > + int retval; > > Needs a blank line here to separate declarations from code. O.K > > > + ehci->big_endian_mmio = 1; > > + ehci->big_endian_desc = 1; > > + > > + ehci->caps = hcd->regs; > > + ehci->regs = hcd->regs + > > + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); > > [snip] > > > + /* data structure init */ > > + retval = ehci_init(hcd); > > + if (retval) > > + return retval; > > + > > + temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); > > + temp &= 0x0f; > > companion HCs * ports per CC & 0xf? > > What's the &= 0x0f for? It's left out of the printk. Code got carried forward from ehci-pci.c . Is that says ehci-pci.c is uptodate? . > > > + if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { > > + ehci_dbg(ehci, "bogus port configuration: " > > + "cc=%d x pcc=%d < ports=%d\