From yad.naveen@gmail.com Wed Dec 1 09:17:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 09:17:48 +0100 (CET) Received: from mail-qw0-f49.google.com ([209.85.216.49]:49444 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491988Ab0LAIRp (ORCPT ); Wed, 1 Dec 2010 09:17:45 +0100 Received: by qwh6 with SMTP id 6so2310154qwh.36 for ; Wed, 01 Dec 2010 00:17:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=v7/r4UGF58bvsvFq3wORRSkPzm7Sidw3kMEdIeDnXJY=; b=dGw78CHI4cxaXV9mBiIuHx/mDc+Fw8/uK4V29jPW0owlODKCkvD07f2LnTZaMdd1MA 1pl2KWRsrX5C4pojpsHPPlz+vSdJgHzpq1G50oEFLXhsBYnjsDEkpS5tPcTYDuhYW6Rh J0deqMllfr6xzcZcJuE4oplkELNs0/ajiUVw0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=xRwMGvfuP2qAgQu2TeEkpIc7TcVPjjlNwoNb0Du/oPONVFYae8+evwVgaXLFGFuzWr wCFfkrBfHJ352ISZhygWqZiaNu8SUgKNtv3uUoM0sM3xejz3eI7a2yCW/PiRdjocmtke SFhdJuPeagcbRuLoB0oAQqWtxEePV9B9Lx1eo= MIME-Version: 1.0 Received: by 10.229.238.16 with SMTP id kq16mr6959720qcb.134.1291191458928; Wed, 01 Dec 2010 00:17:38 -0800 (PST) Received: by 10.229.96.148 with HTTP; Wed, 1 Dec 2010 00:17:38 -0800 (PST) Date: Wed, 1 Dec 2010 13:47:38 +0530 Message-ID: Subject: double kfree From: naveen yadav To: kernelnewbies@nl.linux.org, linux-mips@linux-mips.org, linux-arm-kernel-request@lists.arm.linux.org.uk Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28576 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Hi all, I Have following question with regard for 2.6.30 kernel If we do double kfree() a) Then what will happen? b) Can kernel detect double kfree() ? I gone through google to find some way to find it, there it mention CONFIG_DEBUG_SLAB can help, but i am not sure how usefull is it. I have two targets will it support on both ? Thanks From yad.naveen@gmail.com Wed Dec 1 09:20:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 09:20:24 +0100 (CET) Received: from mail-qw0-f49.google.com ([209.85.216.49]:41290 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491988Ab0LAIUV (ORCPT ); Wed, 1 Dec 2010 09:20:21 +0100 Received: by qwh6 with SMTP id 6so2312282qwh.36 for ; Wed, 01 Dec 2010 00:20:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=fuqbgted2eneNrvsr/w1ALfbQgIhg3aEIDEUFGf8Dg4=; b=EWkoev9kad8cIyVqFbL8dy0yqRsNm6CDhP9zXwF94iJ8lSnFnsEZMotZcz4KMgaQVg MXBCWKE2p2R+2u4Y67CTu4EGhq/cYIlkewxRDMClUHrMfKWxuNHYEbs5FYY2TifycK+F SGAAAwjUW3WvsxAVRCPIXmsZWk4YYBWRBWKlM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=oSR+oRl3IxQ5O04SWbZpt/MJBjQjdWobCfH4X0lixxv7WrFBjVldt938hhxysaEZLe q+TTtQjg4AhRpweoYeMeFgsI0MGSWa9LZmpzJL7Qjwf1a2Fqj7xJ45k7Ys4k0YhUkDTZ DFhExCCQ8n5fpEjyZxRrlqXD5Jl6Q8o0pJ25E= MIME-Version: 1.0 Received: by 10.229.216.201 with SMTP id hj9mr7094921qcb.58.1291191613912; Wed, 01 Dec 2010 00:20:13 -0800 (PST) Received: by 10.229.96.148 with HTTP; Wed, 1 Dec 2010 00:20:13 -0800 (PST) Date: Wed, 1 Dec 2010 13:50:13 +0530 Message-ID: Subject: Change of Default kernel page size i.e 4KB From: naveen yadav To: kernelnewbies@nl.linux.org, linux-arm-kernel-request@lists.arm.linux.org.uk, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28577 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Hi All, I have few drivers and very big application running on ARM and MIPS target. I want to check the performance by changing the page size ie. 8K, 16K, 32K etc. Is it possile, If yes then what all care i need to take . Thanks. From ralf@linux-mips.org Wed Dec 1 12:24:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 12:24:27 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:37600 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492952Ab0LALYZ (ORCPT ); Wed, 1 Dec 2010 12:24:25 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB1BOCgN031109; Wed, 1 Dec 2010 11:24:13 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB1BOBsg031101; Wed, 1 Dec 2010 11:24:11 GMT Date: Wed, 1 Dec 2010 11:24:10 +0000 From: Ralf Baechle To: Anoop P Cc: linux-mips@linux-mips.org, dvomlehn@cisco.com, David Howells , Thomas Gleixner , David Daney , linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] Allow setup_irq call for VPE1 timer. Message-ID: <20101201112410.GL2916@linux-mips.org> References: <1290697632-6139-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1290697632-6139-1-git-send-email-anoop.pa@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28578 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Nov 25, 2010 at 08:37:12PM +0530, Anoop P wrote: > From: Anoop P A > > VSMP configuration can have seperate timer interrupts for each VPE.Need to setup IRQ for VPE1 timer. > +#ifndef CONFIG_MIPS_MT_SMP > if (cp0_timer_irq_installed) > return 0; > - > +#endif > cp0_timer_irq_installed = 1; > > setup_irq(irq, &c0_compare_irqaction); On the stylistic side adding an #ifdef gives me wrinkles. With CONFIG_MIPS_MT_SMP this patch results in sharing c0_compare_irqaction between multiple interrupts which is broken. Struct irqaction contains the interrupt number, all registered irqaction structs are part of a chained list via its ->next member and also there is a per interrupt proc directory. To fix this properly you'll have to introduce do a bit of bookkeeping - you want to register each interrupt only once - and allocate a struct irqaction per registered timer interrupt. The allocation is made a little trickier by kmalloc not being available yet by the time this code is getting invoked via time_init() so you'll have to move it to run via the late_time_init hook like x86: static __init void x86_late_time_init(void) { ... do the real work ... } /* ... */ void __init time_init(void) { late_time_init = x86_late_time_init; } Which makes me wonder if there is a reason why we need to have both time_init() and late_time_init() - can't we just move the time_init()? Ralf From sshtylyov@mvista.com Wed Dec 1 12:52:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 12:53:00 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:57743 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492959Ab0LALw4 (ORCPT ); Wed, 1 Dec 2010 12:52:56 +0100 Received: by ewy20 with SMTP id 20so3367231ewy.36 for ; Wed, 01 Dec 2010 03:52:56 -0800 (PST) Received: by 10.213.9.83 with SMTP id k19mr3526855ebk.47.1291204376092; Wed, 01 Dec 2010 03:52:56 -0800 (PST) Received: from [192.168.2.2] ([91.79.91.95]) by mx.google.com with ESMTPS id q58sm7438848eeh.9.2010.12.01.03.52.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Dec 2010 03:52:54 -0800 (PST) Message-ID: <4CF636A7.1030809@mvista.com> Date: Wed, 01 Dec 2010 14:51:03 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Maksim Rayskiy CC: "Kevin D. Kissell" , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: ASID conflict after CPU hotplug References: <20101122034141.GA13138@linux-mips.org> <4CEAE1EE.9020406@paralogos.com> <4CEE877C.7020309@paralogos.com> <4CF46741.9060902@paralogos.com> <4CF4CC6B.9090603@paralogos.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28579 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 30-11-2010 22:49, Maksim Rayskiy wrote: > From 9a03661a40407e14ee75295f5541f371f0a7cdda Mon Sep 17 00:00:00 2001 > From: Maksim Rayskiy > Date: Tue, 30 Nov 2010 11:34:31 -0800 > Subject: [PATCH] MIPS: Added local_flush_tlb_all_mm to clear all mm > contexts on calling cpu > When hotplug removing a cpu, all mm context TLB entries must be cleared > to avoid ASID conflict when cpu is restarted. > New functions local_flush_tlb_all_mm() and all-cpu version > flush_tlb_all_mm() are added. > To function properly, local_flush_tlb_all_mm() must be called when > mm_cpumask for all > mm context on given cpu is cleared. > Signed-off-by: Maksim Rayskiy [...] > diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c > index c618eed..5c03218 100644 > --- a/arch/mips/mm/tlb-r4k.c > +++ b/arch/mips/mm/tlb-r4k.c > @@ -66,6 +66,18 @@ extern void build_tlb_refill_handler(void); > > #endif > > +/* This function will clear all mm contexts on calling cpu > + * To produce desired effect it must be called > + * when mm_cpumask for all mm contexts is cleared > + */ > +void local_flush_tlb_all_mm(void) > +{ > + struct task_struct *p; An empty line wouldn't hurt here... > + for_each_process(p) > + if (p->mm) > + local_flush_tlb_mm(p->mm); > +} > + WBR, Sergei From ralf@linux-mips.org Wed Dec 1 14:24:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 14:24:43 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60323 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492979Ab0LANYk (ORCPT ); Wed, 1 Dec 2010 14:24:40 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB1DOciE002341; Wed, 1 Dec 2010 13:24:38 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB1DObIB002339; Wed, 1 Dec 2010 13:24:37 GMT Date: Wed, 1 Dec 2010 13:24:37 +0000 From: Ralf Baechle To: naveen yadav Cc: kernelnewbies@nl.linux.org, linux-arm-kernel@lists.arm.linux.org.uk, linux-mips@linux-mips.org Subject: Re: Change of Default kernel page size i.e 4KB Message-ID: <20101201132437.GA32555@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28580 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Dec 01, 2010 at 01:50:13PM +0530, naveen yadav wrote: > Cc: kernelnewbies@nl.linux.org, > linux-arm-kernel-request@lists.arm.linux.org.uk, ^^^^^^^^ WTF? > linux-mips@linux-mips.org > I have few drivers and very big application running on ARM and MIPS target. > I want to check the performance by changing the page size ie. > > 8K, 16K, 32K etc. > > Is it possile, If yes then what all care i need to take . For MIPS: Rebuild kernel with support for the new kernel size. Few MIPS cores. Note that the `odd´ page sizes, that those that aren't a power of 4 are only supported by Cavium while all MIPS III and newer processors support even `even´ sizes 4KB, 16KB and 64KB. Aside of rebuilding the kernel you also need a suitable userland; older versions of binutils will produce binaries that only run for 4kB page sizes. For ARM the page size is fixed at 4kB which will simplify your benchmarking efforts ;) Performance gains very much depends on the workload but in general larger sizes are beneficial except maybe for systems with very little memory. Ralf From ralf@linux-mips.org Wed Dec 1 14:47:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 14:48:02 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:38099 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492175Ab0LANr7 (ORCPT ); Wed, 1 Dec 2010 14:47:59 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB1Dlpfc002872; Wed, 1 Dec 2010 13:47:51 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB1DloZj002870; Wed, 1 Dec 2010 13:47:50 GMT Date: Wed, 1 Dec 2010 13:47:50 +0000 From: Ralf Baechle To: Arnaud Lacombe Cc: Steven Rostedt , John Reiser , linux-mips@linux-mips.org, wu zhangjin Subject: Re: Build failure triggered by recordmcount Message-ID: <20101201134750.GB32555@linux-mips.org> References: <4CEB37F8.1050504@bitwagon.com> <1290532165.30543.374.camel@gandalf.stny.rr.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28581 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 23, 2010 at 03:09:43PM -0500, Arnaud Lacombe wrote: > [0] Ralf, is there any specific reason mips keeps defining its own > _IOC_SIZEBITS ? History. The ABI once upon a time was meant to be compatible the existing commercial MIPS UNIX flavours. Today that's just historical baggage. Ralf From namhyung@gmail.com Wed Dec 1 16:54:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 16:54:35 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:62734 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493013Ab0LAPyb (ORCPT ); Wed, 1 Dec 2010 16:54:31 +0100 Received: by yxm34 with SMTP id 34so3760750yxm.36 for ; Wed, 01 Dec 2010 07:54:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=rb32R6kPzmkl7XoC233HzMmkJvuDgUwfVOJ9g3ASc+c=; b=cfpoJwbpXfwoLkgDf174Keqf7s6cSzPwB7aOXVyHXhAhdj+AFn1BkkKrbcro2TqEZt 9FXoMQR8OyqhAfBADy2MzPKvy8tYbu8S6EZwPgAgStnRK+t2nzSWYksZFnhAR004nQaP SNnwTazI+4Zn/h5Do88s2ygw3XrD57T4Xnwbo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=dH+LlP3GKlSSVZwuNV1+gjH7HclQM2YRVBwZZz9Q8CxaANG8hPcRGJm4XZ9Dso6nbG Dm9bzHi9nizY4hsddl0yPfEYjsdj+pklc8sfIBGdKkUMjey9n+bq9Z8GjaIJoGgcdGYi 7yEMy5dpMX4CAsqPlYNqcQjgFthStN5Dc/jWQ= Received: by 10.91.67.10 with SMTP id u10mr183945agk.187.1291218863612; Wed, 01 Dec 2010 07:54:23 -0800 (PST) Received: from [192.168.10.102] ([211.201.183.198]) by mx.google.com with ESMTPS id 31sm67747yhl.30.2010.12.01.07.54.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Dec 2010 07:54:22 -0800 (PST) Subject: Re: [PATCH RESEND] MIPS: Define dummy MAX_DMA_CHANNELS to fix build failure From: Namhyung Kim To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org In-Reply-To: <1289918840-13434-1-git-send-email-namhyung@gmail.com> References: <1289918840-13434-1-git-send-email-namhyung@gmail.com> Content-Type: text/plain; charset="UTF-8" Date: Thu, 02 Dec 2010 00:54:13 +0900 Message-ID: <1291218853.1684.35.camel@leonhard> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28582 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: namhyung@gmail.com Precedence: bulk X-list: linux-mips 2010-11-16 (í™”), 23:47 +0900, Namhyung Kim: > allmodconfig build failes like following: > > CC [M] sound/oss/soundcard.o > sound/oss/soundcard.c:68: error: 'MAX_DMA_CHANNELS' undeclared here (not in a function) > make[3]: *** [sound/oss/soundcard.o] Error 1 > make[2]: *** [sound/oss] Error 2 > make[1]: *** [sub-make] Error 2 > make: *** [all] Error 2 > > Signed-off-by: Namhyung Kim > --- > arch/mips/include/asm/dma.h | 4 +++- > 1 files changed, 3 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h > index 2d47da6..c601cff 100644 > --- a/arch/mips/include/asm/dma.h > +++ b/arch/mips/include/asm/dma.h > @@ -74,7 +74,9 @@ > * > */ > > -#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN > +#ifdef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN > +#define MAX_DMA_CHANNELS 0 > +#else > #define MAX_DMA_CHANNELS 8 > #endif > Ping. Any comments? -- Regards, Namhyung Kim From Viral.Mehta@lntinfotech.com Wed Dec 1 17:06:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:06:45 +0100 (CET) Received: from mail96.messagelabs.com ([216.82.254.19]:47330 "EHLO mail96.messagelabs.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493015Ab0LAQGm convert rfc822-to-8bit (ORCPT ); Wed, 1 Dec 2010 17:06:42 +0100 X-VirusChecked: Checked X-Env-Sender: Viral.Mehta@lntinfotech.com X-Msg-Ref: server-12.tower-96.messagelabs.com!1291219592!71160213!1 X-StarScan-Version: 6.2.9; banners=lntinfotech.com,-,- X-Originating-IP: [203.199.118.205] Received: (qmail 30912 invoked from network); 1 Dec 2010 16:06:35 -0000 Received: from unknown (HELO VSHINMSHTCAS01.vshodc.lntinfotech.com) (203.199.118.205) by server-12.tower-96.messagelabs.com with AES128-SHA encrypted SMTP; 1 Dec 2010 16:06:35 -0000 Received: from vshinmsmbx01.vshodc.lntinfotech.com ([172.17.24.117]) by VSHINMSHTCAS01.vshodc.lntinfotech.com ([172.17.24.112]) with mapi; Wed, 1 Dec 2010 21:36:31 +0530 From: Viral Mehta To: naveen yadav , "kernelnewbies@nl.linux.org" , "linux-arm-kernel-request@lists.arm.linux.org.uk" , "linux-mips@linux-mips.org" Date: Wed, 1 Dec 2010 21:36:31 +0530 Subject: RE: Change of Default kernel page size i.e 4KB Thread-Topic: Change of Default kernel page size i.e 4KB Thread-Index: AcuRMnA5Kidnzr40Rg2OCnrUNQ3tNAAPF7wM Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28583 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Viral.Mehta@lntinfotech.com Precedence: bulk X-list: linux-mips ________________________________________ From: kernelnewbies-bounce@nl.linux.org [kernelnewbies-bounce@nl.linux.org] On Behalf Of naveen yadav Hi, >Hi All, > >I have few drivers and very big application running on ARM and MIPS target. >I want to check the performance by changing the page size ie. I remember it is possible on powerpc. There is config option like CONFIG_PPC_64K_PAGES. Not sure about ARM/MIPS archs, but you can certianly grep for something like 4K_PAGE all around defconfigs >8K, 16K, 32K etc. > >Is it possile, If yes then what all care i need to take . > >Thanks. -- Viral This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. ______________________________________________________________________ From anoop.pa@gmail.com Wed Dec 1 17:10:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:10:30 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:41896 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493015Ab0LAQK1 (ORCPT ); Wed, 1 Dec 2010 17:10:27 +0100 Received: by fxm19 with SMTP id 19so2309195fxm.36 for ; Wed, 01 Dec 2010 08:10:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=b2wl2OXN96Nnesn+x2RTBvfHL8ZGUeHbQrMRo7SWEos=; b=TZ+wkS10Dh46UnNDPey2xGqXoKB4s4gwLiXG0ZlW8tW4NZuG9pMt8dEA8JbZr7ulT0 l4RJFF2EIByLVrflft4jF0QHS6jNp0yaEQcK4gTaa7E55yl8k7adQp5+HP59yaeAZZTq ZxOlgJMgF9mvudWSjiwtiZ53FqVIC+sgzxTLA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=Jsm9cyofeR2MQFTVDXA/+YksOQ0Ig6IlbwXquOeH+891i1juA6HmqK5oXFkFrvoHqG gf2Tgb6Q9/Hp5NHiSlyPzGpYyFacIcZps/C9rkl6DdYbrr6JD08x7xGU+qh5RR43YcII F3wm+yirwAj1cnVitOU4nDx8PR3nNE8ifz6GU= Received: by 10.223.108.147 with SMTP id f19mr8473446fap.68.1291219821392; Wed, 01 Dec 2010 08:10:21 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id a24sm938953fak.3.2010.12.01.08.10.17 (version=SSLv3 cipher=RC4-MD5); Wed, 01 Dec 2010 08:10:20 -0800 (PST) Subject: Subject: [RFC 0/3] VSMP support for msp71xx platforms From: Anoop P A To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, mcdonald.shane@gmail.com, "Kevin D. Kissell" Content-Type: text/plain; charset="UTF-8" Date: Wed, 01 Dec 2010 21:43:11 +0530 Message-ID: <1291219991.31413.8.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28584 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips >From 5bfd3ba210e521df2b493862446b4535bcdb0cdf Mon Sep 17 00:00:00 2001 Message-Id: From: Anoop P A Date: Wed, 1 Dec 2010 21:28:38 +0530 Subject: [RFC 0/3] VSMP support for msp71xx platforms Cc: anoop.pa@gmail.com Following series patches add VSMP support for MSP71xx series of SoC's. Anoop P A (3): VSMP support for msp71xx family of platforms. SMP support MSP CIC and PER cascaded interrupt subsystem. VSMP support for MSP71xx family. arch/mips/pmc-sierra/msp71xx/Makefile | 3 +- arch/mips/pmc-sierra/msp71xx/msp_irq.c | 49 +++++- arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c | 245 +++++++++++++++++++--------- arch/mips/pmc-sierra/msp71xx/msp_irq_per.c | 175 ++++++++++++++++++++ arch/mips/pmc-sierra/msp71xx/msp_setup.c | 3 + arch/mips/pmc-sierra/msp71xx/msp_smp.c | 75 +++++++++ arch/mips/pmc-sierra/msp71xx/msp_time.c | 2 +- 7 files changed, 463 insertions(+), 89 deletions(-) create mode 100644 arch/mips/pmc-sierra/msp71xx/msp_irq_per.c create mode 100644 arch/mips/pmc-sierra/msp71xx/msp_smp.c From anoop.pa@gmail.com Wed Dec 1 17:15:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:15:45 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:51576 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493021Ab0LAQPm (ORCPT ); Wed, 1 Dec 2010 17:15:42 +0100 Received: by gyg4 with SMTP id 4so3783832gyg.36 for ; Wed, 01 Dec 2010 08:15:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=nmsN8bV4OIvGebIUXaCKQc0y2Vo3PV/5GXBvjQvT9sQ=; b=InTSHDhbBa0XxLZlBNBt0DNP3bo8seY8vxB5ybHTcJ7u074IWHjMukH0goaEthzTwg Vf7h7PrbjWq4f97kPU7+31y3h/fEKWStQ0NaXbvoXR8X0bi15/Va5sxUElvBiFc9JwqO ot7kbFL+Q1b9PNPwK9KHhTBSoqZRmXC6eVO/U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=Ns8H9luAIJ+47peboyL+JoSjXjA6TKtWpFCnTbK8eMdgIb41mjUZ+LNPQU+dO5s3Ib 3JZRG7kgN+gTetLDstXO2hi7jQS52ixlj6MP/dUO19giyxYlaxKE14Gy0AVa6xDYgzm7 zYEWMojHPmUgC2PwC7geW+yxEUKNUWHLtBWl8= Received: by 10.223.70.194 with SMTP id e2mr982280faj.128.1291220134672; Wed, 01 Dec 2010 08:15:34 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id r24sm67329fax.27.2010.12.01.08.15.32 (version=SSLv3 cipher=RC4-MD5); Wed, 01 Dec 2010 08:15:34 -0800 (PST) Subject: [RFC 1/3] VSMP support for msp71xx family of platforms. From: Anoop P A To: Ralf Baechle , linux-mips@linux-mips.org, mcdonald.shane@gmail.com Content-Type: text/plain; charset="UTF-8" Date: Wed, 01 Dec 2010 21:48:27 +0530 Message-ID: <1291220307.31413.14.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28585 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips >From e5148874243f0b2b610cd6b077084bd782961d94 Mon Sep 17 00:00:00 2001 Message-Id: In-Reply-To: References: From: Anoop P A Date: Wed, 1 Dec 2010 20:58:28 +0530 Subject: [RFC 1/3] VSMP support for msp71xx family of platforms. Cc: anoop.pa@gmail.com msp_smp.c initiliase IPI call and resched irq. Signed-off-by: Anoop P A --- arch/mips/pmc-sierra/msp71xx/Makefile | 3 +- arch/mips/pmc-sierra/msp71xx/msp_smp.c | 75 ++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 1 deletions(-) create mode 100644 arch/mips/pmc-sierra/msp71xx/msp_smp.c diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile index e107f79..09627ae 100644 --- a/arch/mips/pmc-sierra/msp71xx/Makefile +++ b/arch/mips/pmc-sierra/msp71xx/Makefile @@ -6,7 +6,8 @@ obj-y += msp_prom.o msp_setup.o msp_irq.o \ obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o -obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o +obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o obj-$(CONFIG_PCI) += msp_pci.o obj-$(CONFIG_MSPETH) += msp_eth.o obj-$(CONFIG_USB_MSP71XX) += msp_usb.o +obj-$(CONFIG_MIPS_MT_SMP) += msp_smp.o diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c new file mode 100644 index 0000000..31a6c72 --- /dev/null +++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * Copyright (C) 2010 PMC-Sierra, Inc. + * + * VSMP support for MSP platforms . Derived from malta vsmp support. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include +#include + +#ifdef CONFIG_MIPS_MT_SMP +#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ +#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */ + + +static void ipi_resched_dispatch(void) +{ + do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ); +} + +static void ipi_call_dispatch(void) +{ + do_IRQ(MIPS_CPU_IPI_CALL_IRQ); +} + +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) +{ + smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +static struct irqaction irq_resched = { + .handler = ipi_resched_interrupt, + .flags = IRQF_DISABLED|IRQF_PERCPU, + .name = "IPI_resched" +}; + +static struct irqaction irq_call = { + .handler = ipi_call_interrupt, + .flags = IRQF_DISABLED|IRQF_PERCPU, + .name = "IPI_call" +}; +void __init arch_init_ipiirq(int irq, struct irqaction *action) +{ + setup_irq(irq, action); + set_irq_handler(irq, handle_percpu_irq); +} +void __init msp_vsmp_int_init(void) +{ + set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); + set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); + arch_init_ipiirq(MIPS_CPU_IPI_RESCHED_IRQ, &irq_resched); + arch_init_ipiirq(MIPS_CPU_IPI_CALL_IRQ, &irq_call); +} +#endif /* CONFIG_MIPS_MT_SMP */ -- 1.7.0.4 From anoop.pa@gmail.com Wed Dec 1 17:19:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:19:58 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:48956 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493021Ab0LAQTw (ORCPT ); Wed, 1 Dec 2010 17:19:52 +0100 Received: by fxm19 with SMTP id 19so2318713fxm.36 for ; Wed, 01 Dec 2010 08:19:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=5DRw8B6nqxf8m5smCIzw9gExgDUc7uytuTyURlhD01A=; b=nVaBy7ifuZYNCjOmkZjNszTM+wDxtVlOU+MJzudoowC5qZeUnxzfb5qRNRsAG3fVGU 9S3VIrc0sBhf6V+8To4qqt2ZrQ6aqOgAK0AkP2kHrUpoZ9Z30e7ZtDSpsX1TnpYACY4R vEPj0HUB+VdFqCg0Leair/v4ZV2pc+cqI3ais= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=lO1ZFBc1KYDaZoQIGJejHfT2kfJPh3Eg/XJEV45Th9HQbfuaGQu1bpbsyWcofcAZ6R kCoywA420kepBjEHaCtYZjbGuRc521rgLaAruWUm+Hbn6JJD47Gkm8WSvdKpPSCk5FJ4 V83nkSPQ2ZL9we20uwAQiatGTZaiPLn4hai/A= Received: by 10.223.89.142 with SMTP id e14mr3975489fam.143.1291220386518; Wed, 01 Dec 2010 08:19:46 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id 5sm69637fak.23.2010.12.01.08.19.42 (version=SSLv3 cipher=RC4-MD5); Wed, 01 Dec 2010 08:19:46 -0800 (PST) Subject: [RFC 2/3] SMP support MSP CIC and PER cascaded interrupt From: Anoop P A To: kevink@paralogos.com, linux-mips@linux-mips.org, Ralf Baechle , David Howells , Ralf Baechle , David Howells Content-Type: text/plain; charset="UTF-8" Date: Wed, 01 Dec 2010 21:52:37 +0530 Message-ID: <1291220557.31413.19.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28586 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips >From 1288493c35839fca6c05486445a9eecdecd9a60a Mon Sep 17 00:00:00 2001 Message-Id: <1288493c35839fca6c05486445a9eecdecd9a60a.1291219118.git.anoop.pa@gmail.com> In-Reply-To: References: From: Anoop P A Date: Wed, 1 Dec 2010 21:03:43 +0530 Subject: [RFC 2/3] SMP support MSP CIC and PER cascaded interrupt subsystem. Cc: anoop.pa@gmail.com Following patches will move PER interrupt handles to seperate file , Along with changes for SMP support. Signed-off-by: Anoop P A --- arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c | 245 +++++++++++++++++++--------- arch/mips/pmc-sierra/msp71xx/msp_irq_per.c | 175 ++++++++++++++++++++ 2 files changed, 341 insertions(+), 79 deletions(-) create mode 100644 arch/mips/pmc-sierra/msp71xx/msp_irq_per.c diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c index 07e71ff..f800d0c 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c @@ -1,8 +1,7 @@ /* - * This file define the irq handler for MSP SLM subsystem interrupts. + * Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c * - * Copyright 2005-2007 PMC-Sierra, Inc, derived from irq_cpu.c - * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com + * This file define the irq handler for MSP CIC subsystem interrupts. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -14,121 +13,209 @@ #include #include #include -#include +#include #include #include #include /* - * NOTE: We are only enabling support for VPE0 right now. + * External API */ +extern void msp_per_irq_init(void); +extern void msp_per_irq_dispatch(void); -static inline void unmask_msp_cic_irq(unsigned int irq) + +/* + * Convenience Macro. Should be somewhere generic. + */ +#define get_current_vpe() \ + ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) + +#ifdef CONFIG_SMP + +#define LOCK_VPE(flags, mtflags) \ +do { \ + local_irq_save(flags); \ + mtflags = dmt(); \ +} while (0) + +#define UNLOCK_VPE(flags, mtflags) \ +do { \ + emt(mtflags); \ + local_irq_restore(flags);\ +} while (0) + +#define LOCK_CORE(flags, mtflags) \ +do { \ + local_irq_save(flags); \ + mtflags = dvpe(); \ +} while (0) + +#define UNLOCK_CORE(flags, mtflags) \ +do { \ + evpe(mtflags); \ + local_irq_restore(flags);\ +} while (0) + +#else + +#define LOCK_VPE(flags, mtflags) +#define UNLOCK_VPE(flags, mtflags) + +#endif + +/* ensure writes to cic are completed */ +static inline void cic_wmb(void) { + const volatile void __iomem *cic_mem = CIC_VPE0_MSK_REG; + volatile u32 dummy_read; - /* check for PER interrupt range */ - if (irq < MSP_PER_INTBASE) - *CIC_VPE0_MSK_REG |= (1 << (irq - MSP_CIC_INTBASE)); - else - *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE)); + wmb(); + dummy_read = __raw_readl(cic_mem); + dummy_read++; } -static inline void mask_msp_cic_irq(unsigned int irq) + +static inline void unmask_cic_irq(unsigned int irq) { - /* check for PER interrupt range */ - if (irq < MSP_PER_INTBASE) - *CIC_VPE0_MSK_REG &= ~(1 << (irq - MSP_CIC_INTBASE)); - else - *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE)); + volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG; + int vpe; +#ifdef CONFIG_SMP + unsigned int mtflags; + unsigned long flags; + + /* + * Make sure we have IRQ affinity. It may have changed while + * we were processing the IRQ. + */ + if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) + return; +#endif + + vpe = get_current_vpe(); + LOCK_VPE(flags, mtflags); + cic_msk_reg[vpe] |= (1 << (irq - MSP_CIC_INTBASE)); + UNLOCK_VPE(flags, mtflags); + cic_wmb(); } -/* - * While we ack the interrupt interrupts are disabled and thus we don't need - * to deal with concurrency issues. Same for msp_cic_irq_end. - */ -static inline void ack_msp_cic_irq(unsigned int irq) +static inline void mask_cic_irq(unsigned int irq) { - mask_msp_cic_irq(irq); - + volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG; + int vpe = get_current_vpe(); +#ifdef CONFIG_SMP + unsigned long flags, mtflags; +#endif + LOCK_VPE(flags, mtflags); + cic_msk_reg[vpe] &= ~(1 << (irq - MSP_CIC_INTBASE)); + UNLOCK_VPE(flags, mtflags); + cic_wmb(); +} +static inline void msp_cic_irq_ack(unsigned int irq) +{ + mask_cic_irq(irq); /* - * only really necessary for 18, 16-14 and sometimes 3:0 (since - * these can be edge sensitive) but it doesn't hurt for the others. - */ - - /* check for PER interrupt range */ - if (irq < MSP_PER_INTBASE) - *CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE)); - else - *PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE)); + * Only really necessary for 18, 16-14 and sometimes 3:0 + * (since these can be edge sensitive) but it doesn't + * hurt for the others + */ + *CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE)); } +static void msp_cic_irq_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + unmask_cic_irq(irq); +} + +#ifdef CONFIG_SMP +static inline int msp_cic_irq_set_affinity(unsigned int irq, + const struct cpumask *cpumask) +{ + int cpu; + unsigned long flags; + unsigned int mtflags; + unsigned long imask = (1 << (irq - MSP_CIC_INTBASE)); + volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG; + + /* timer balancing should be disabled in kernel code */ + BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER); + + LOCK_CORE(flags, mtflags); + /* enable if any of each VPE's TCs require this IRQ */ + for_each_online_cpu(cpu) { + if (cpumask_test_cpu(cpu, cpumask)) + cic_mask[cpu] |= imask; + else + cic_mask[cpu] &= ~imask; + + } + + UNLOCK_CORE(flags, mtflags); + return 0; + +} +#endif + static struct irq_chip msp_cic_irq_controller = { .name = "MSP_CIC", - .ack = ack_msp_cic_irq, - .mask = ack_msp_cic_irq, - .mask_ack = ack_msp_cic_irq, - .unmask = unmask_msp_cic_irq, + .mask = msp_cic_irq_ack, + .mask_ack = msp_cic_irq_ack, + .unmask = unmask_cic_irq, + .ack = msp_cic_irq_ack, + .end = msp_cic_irq_end, +#ifdef CONFIG_SMP + .set_affinity = msp_cic_irq_set_affinity, +#endif }; - void __init msp_cic_irq_init(void) { int i; - /* Mask/clear interrupts. */ *CIC_VPE0_MSK_REG = 0x00000000; - *PER_INT_MSK_REG = 0x00000000; + *CIC_VPE1_MSK_REG = 0x00000000; *CIC_STS_REG = 0xFFFFFFFF; - *PER_INT_STS_REG = 0xFFFFFFFF; - -#if defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_EVAL) /* - * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI. - * These inputs map to EXT_INT_POL[6:4] inside the CIC. - * They are to be active low, level sensitive. - */ + * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI. + * These inputs map to EXT_INT_POL[6:4] inside the CIC. + * They are to be active low, level sensitive. + */ *CIC_EXT_CFG_REG &= 0xFFFF8F8F; -#endif /* initialize all the IRQ descriptors */ - for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++) + for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) { set_irq_chip_and_handler(i, &msp_cic_irq_controller, handle_level_irq); + } + + /* Initialize the PER interrupt sub-system */ + msp_per_irq_init(); } +/* CIC masked by CIC vector processing before dispatch called */ void msp_cic_irq_dispatch(void) { - u32 pending; - int intbase; - - intbase = MSP_CIC_INTBASE; - pending = *CIC_STS_REG & *CIC_VPE0_MSK_REG; - - /* check for PER interrupt */ - if (pending == (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) { - intbase = MSP_PER_INTBASE; - pending = *PER_INT_STS_REG & *PER_INT_MSK_REG; - } - - /* check for spurious interrupt */ - if (pending == 0x00000000) { - printk(KERN_ERR - "Spurious %s interrupt? status %08x, mask %08x\n", - (intbase == MSP_CIC_INTBASE) ? "CIC" : "PER", - (intbase == MSP_CIC_INTBASE) ? - *CIC_STS_REG : *PER_INT_STS_REG, - (intbase == MSP_CIC_INTBASE) ? - *CIC_VPE0_MSK_REG : *PER_INT_MSK_REG); - return; - } - - /* check for the timer and dispatch it first */ - if ((intbase == MSP_CIC_INTBASE) && - (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE)))) + volatile u32 *cic_msk_reg = (volatile u32 *)CIC_VPE0_MSK_REG; + u32 cic_mask; + u32 pending; + int cic_status = *CIC_STS_REG; + cic_mask = cic_msk_reg[get_current_vpe()]; + pending = cic_status & cic_mask; + + if (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))) { do_IRQ(MSP_INT_VPE0_TIMER); - else - do_IRQ(ffs(pending) + intbase - 1); + } else if (pending & (1 << (MSP_INT_VPE1_TIMER - MSP_CIC_INTBASE))) { + do_IRQ(MSP_INT_VPE1_TIMER); + } else if (pending & (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) { + msp_per_irq_dispatch(); + } else if (pending) { + do_IRQ(ffs(pending) + MSP_CIC_INTBASE - 1); + } else{ + spurious_interrupt(); + /* Re-enable the CIC cascaded interrupt. */ + irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC); + } } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c new file mode 100644 index 0000000..c7f4d95 --- /dev/null +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c @@ -0,0 +1,175 @@ +/* + * Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c + * + * This file define the irq handler for MSP PER subsystem interrupts. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + + +/* + * Convenience Macro. Should be somewhere generic. + */ +#define get_current_vpe() \ + ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) + +#ifdef CONFIG_SMP +/* + * The PER registers must be protected from concurrent access. + */ + +static DEFINE_SPINLOCK(per_lock); +#endif + +/* ensure writes to per are completed */ + +static inline void per_wmb(void) +{ + const volatile void __iomem *per_mem = PER_INT_MSK_REG; + volatile u32 dummy_read; + + wmb(); + dummy_read = __raw_readl(per_mem); + dummy_read++; +} + +static inline void unmask_per_irq(unsigned int irq) +{ +#ifdef CONFIG_SMP + unsigned long flags; + spin_lock_irqsave(&per_lock, flags); + *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE)); + spin_unlock_irqrestore(&per_lock, flags); +#else + *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE)); +#endif + per_wmb(); +} + +static inline void mask_per_irq(unsigned int irq) +{ +#ifdef CONFIG_SMP + unsigned long flags; + spin_lock_irqsave(&per_lock, flags); + *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE)); + spin_unlock_irqrestore(&per_lock, flags); +#else + *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE)); +#endif + per_wmb(); +} + +static inline void msp_per_irq_enable(unsigned int irq) +{ + unmask_per_irq(irq); +} + +static inline void msp_per_irq_disable(unsigned int irq) +{ + mask_per_irq(irq); +} + +static unsigned int msp_per_irq_startup(unsigned int irq) +{ + msp_per_irq_enable(irq); + return 0; +} + +#define msp_per_irq_shutdown msp_per_irq_disable + +static inline void msp_per_irq_ack(unsigned int irq) +{ + mask_per_irq(irq); + /* + * In the PER interrupt controller, only bits 11 and 10 + * are write-to-clear, (SPI TX complete, SPI RX complete). + * It does nothing for any others. + */ + + *PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE)); + + /* Re-enable the CIC cascaded interrupt and return */ + irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC); +} + +static void msp_per_irq_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + unmask_per_irq(irq); +} + +#ifdef CONFIG_SMP +static inline int msp_per_irq_set_affinity(unsigned int irq, const struct cpumask *affinity) +{ + unsigned long flags; + /* + * Calls to ack, end, startup, enable are spinlocked in setup_irq and + * __do_IRQ.Callers of this function do not spinlock,so we need to do so + * ourselves. + */ + raw_spin_lock_irqsave(&irq_desc[irq].lock, flags); + msp_per_irq_enable(irq); + raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags); + return 0; + +} +#endif + +static struct irq_chip msp_per_irq_controller = { + .name = "MSP_PER", + .startup = msp_per_irq_startup, + .shutdown = msp_per_irq_shutdown, + .enable = msp_per_irq_enable, + .disable = msp_per_irq_disable, +#ifdef CONFIG_SMP + .set_affinity = msp_per_irq_set_affinity, +#endif + .ack = msp_per_irq_ack, + .end = msp_per_irq_end, +}; + +void __init msp_per_irq_init(void) +{ + int i; + /* Mask/clear interrupts. */ + *PER_INT_MSK_REG = 0x00000000; + *PER_INT_STS_REG = 0xFFFFFFFF; + /* initialize all the IRQ descriptors */ + for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].chip = &msp_per_irq_controller; + } +} + +void msp_per_irq_dispatch(void) +{ + u32 per_mask = *PER_INT_MSK_REG; + u32 per_status = *PER_INT_STS_REG; + u32 pending; + + pending = per_status & per_mask; + if (pending) { + do_IRQ(ffs(pending) + MSP_PER_INTBASE - 1); + } else { + spurious_interrupt(); + /* Re-enable the CIC cascaded interrupt and return */ + irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC); + } +} -- 1.7.0.4 From anoop.pa@gmail.com Wed Dec 1 17:21:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:21:14 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:40416 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493023Ab0LAQVL (ORCPT ); Wed, 1 Dec 2010 17:21:11 +0100 Received: by fxm19 with SMTP id 19so2320233fxm.36 for ; Wed, 01 Dec 2010 08:21:05 -0800 (PST) DKIM-Signature: v=1; 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Wed, 01 Dec 2010 08:21:05 -0800 (PST) Subject: [RFC 3/3] VSMP support for MSP71xx family From: Anoop P A To: kevink@paralogos.com, linux-mips@linux-mips.org, David Howells , Ralf Baechle , Ralf Baechle Content-Type: text/plain; charset="UTF-8" Date: Wed, 01 Dec 2010 21:53:57 +0530 Message-ID: <1291220637.31413.20.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28587 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips >From 5bfd3ba210e521df2b493862446b4535bcdb0cdf Mon Sep 17 00:00:00 2001 Message-Id: <5bfd3ba210e521df2b493862446b4535bcdb0cdf.1291219118.git.anoop.pa@gmail.com> In-Reply-To: References: From: Anoop P A Date: Wed, 1 Dec 2010 21:08:37 +0530 Subject: [RFC 3/3] VSMP support for MSP71xx family. Cc: anoop.pa@gmail.com followig patches setup vectored interrupt in msp_irq.c and register vsmp_ops from msp_setup.c. It also changes get_c0_compare_int to return corresponding vpe timer interrupt. Signed-off-by: Anoop P A --- arch/mips/pmc-sierra/msp71xx/msp_irq.c | 49 +++++++++++++++++++++++++----- arch/mips/pmc-sierra/msp71xx/msp_setup.c | 3 ++ arch/mips/pmc-sierra/msp71xx/msp_time.c | 2 +- 3 files changed, 45 insertions(+), 9 deletions(-) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c b/arch/mips/pmc-sierra/msp71xx/msp_irq.c index 734d598..e9144c8 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c @@ -19,8 +19,6 @@ #include -extern void msp_int_handle(void); - /* SLP bases systems */ extern void msp_slp_irq_init(void); extern void msp_slp_irq_dispatch(void); @@ -29,6 +27,19 @@ extern void msp_slp_irq_dispatch(void); extern void msp_cic_irq_init(void); extern void msp_cic_irq_dispatch(void); +/* VSMP support init */ +extern void msp_vsmp_int_init(void); + +/* vectored interrupt implementation */ + +/* SW0/1 interrupts are used for SMP/SMTC */ +static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); } +static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); } +static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); } +static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); } +static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); } + + /* * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded * hierarchical system. The first level are the direct MIPS interrupts @@ -96,29 +107,51 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs) do_IRQ(MSP_INT_SW1); } -static struct irqaction cascade_msp = { +static struct irqaction cic_cascade_msp = { .handler = no_action, - .name = "MSP cascade" + .name = "MSP CIC cascade" }; +static struct irqaction per_cascade_msp = { + .handler = no_action, + .name = "MSP PER cascade" +}; void __init arch_init_irq(void) { + /* assume we'll be using vectored interrupt mode except in UP mode*/ +#ifdef CONFIG_MIPS_MT + BUG_ON(!cpu_has_vint); +#endif + /* initialize the 1st-level CPU based interrupt controller */ mips_cpu_irq_init(); #ifdef CONFIG_IRQ_MSP_CIC msp_cic_irq_init(); +#ifdef CONFIG_MIPS_MT + set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch); + set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch); + set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch); + set_vi_handler(MSP_INT_SAR, mac2_int_dispatch); + set_vi_handler(MSP_INT_USB, usb_int_dispatch); + set_vi_handler(MSP_INT_SEC, sec_int_dispatch); +#endif +#ifdef CONFIG_MIPS_MT_SMP + msp_vsmp_int_init(); +#endif /* setup the cascaded interrupts */ - setup_irq(MSP_INT_CIC, &cascade_msp); - setup_irq(MSP_INT_PER, &cascade_msp); + setup_irq(MSP_INT_CIC, &cic_cascade_msp); + setup_irq(MSP_INT_PER, &per_cascade_msp); + #else /* setup the 2nd-level SLP register based interrupt controller */ + /* VSMP /SMTC support support is not enabled for SLP */ msp_slp_irq_init(); /* setup the cascaded SLP/PER interrupts */ - setup_irq(MSP_INT_SLP, &cascade_msp); - setup_irq(MSP_INT_PER, &cascade_msp); + setup_irq(MSP_INT_SLP, &cic_cascade_msp); + setup_irq(MSP_INT_PER, &per_cascade_msp); #endif } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index a54e85b..d7e06b8 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -225,6 +225,9 @@ void __init prom_init(void) * in separate specific files. */ msp_serial_setup(); +#ifdef CONFIG_MIPS_MT_SMP + register_smp_ops(&vsmp_smp_ops); +#endif #ifdef CONFIG_PMCTWILED /* diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index 01df84c..67c0222 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -83,5 +83,5 @@ void __init plat_time_init(void) unsigned int __cpuinit get_c0_compare_int(void) { - return MSP_INT_VPE0_TIMER; + return smp_processor_id() ? MSP_INT_VPE1_TIMER : MSP_INT_VPE0_TIMER; } -- 1.7.0.4 From anoop.pa@gmail.com Wed Dec 1 17:28:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:28:32 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:59099 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493021Ab0LAQ23 (ORCPT ); Wed, 1 Dec 2010 17:28:29 +0100 Received: by gyg4 with SMTP id 4so3796439gyg.36 for ; Wed, 01 Dec 2010 08:28:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=yJr4s0+/AzPVHLmHb0byZkHv+o2Gf9+2kB8Q5kKviYA=; b=n3z+y7A6q2IaiPEWUuPXtYnr7H6wu8B0uUFx13czNG84atP3nB59JxBu5nVRKF65Ro p6zUqfGqJfCqbmtN5CnSIoo7b40k3ACkBrXjIBFKMrR8Xw5GZNFA/LKxJ8JpCYjtQDEk DXzyhUO5LGHAAgV1C41OAqS/a20/W2POHasLc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=wXFJOg0dS24S3ZAZCgGNKY7lWDd+UlJbuKh4rTvMFyHH1krQto6OuaWFKqPVuDolal ZDs//j5Q1RjMFJr9wuc0lBh/jPfqkpMccUb+q60VXPZIuCEubVBMnsSPNW+K7Yr/qXdp WX+4RoiOe/A2OuIKPrUNQiz5rhYUo09EejaQI= Received: by 10.223.109.200 with SMTP id k8mr8523487fap.136.1291220903161; Wed, 01 Dec 2010 08:28:23 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id n7sm75010fam.11.2010.12.01.08.28.20 (version=SSLv3 cipher=RC4-MD5); Wed, 01 Dec 2010 08:28:22 -0800 (PST) Subject: [PATCH] ifdef gic_present variable that is used only by malta From: Anoop P A To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Date: Wed, 01 Dec 2010 22:01:15 +0530 Message-ID: <1291221075.31413.24.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28588 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips gic_present variable will be used only in malta platforms.Other platforms with VSMP support will throw link error. Signed-off-by: Anoop P A --- arch/mips/kernel/smp-mt.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 43e7cdc..5b91c1a 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -151,6 +151,7 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { +#ifdef CONFIG_MIPS_MALTA extern int gic_present; /* This is Malta specific: IPI,performance and timer inetrrupts */ @@ -158,6 +159,7 @@ static void __cpuinit vsmp_init_secondary(void) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | STATUSF_IP7); else +#endif /* CONFIG_MIPS_MALTA */ change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7); } -- 1.7.0.4 From Viral.Mehta@lntinfotech.com Wed Dec 1 17:31:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:32:03 +0100 (CET) Received: from mail96.messagelabs.com ([216.82.254.19]:3245 "EHLO mail96.messagelabs.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493026Ab0LAQb7 convert rfc822-to-8bit (ORCPT ); Wed, 1 Dec 2010 17:31:59 +0100 X-VirusChecked: Checked X-Env-Sender: Viral.Mehta@lntinfotech.com X-Msg-Ref: server-10.tower-96.messagelabs.com!1291219797!53747085!1 X-StarScan-Version: 6.2.9; banners=lntinfotech.com,-,- X-Originating-IP: [203.199.118.205] Received: (qmail 27086 invoked from network); 1 Dec 2010 16:09:59 -0000 Received: from unknown (HELO VSHINMSHTCAS01.vshodc.lntinfotech.com) (203.199.118.205) by server-10.tower-96.messagelabs.com with AES128-SHA encrypted SMTP; 1 Dec 2010 16:09:59 -0000 Received: from vshinmsmbx01.vshodc.lntinfotech.com ([172.17.24.117]) by VSHINMSHTCAS01.vshodc.lntinfotech.com ([172.17.24.112]) with mapi; Wed, 1 Dec 2010 21:39:56 +0530 From: Viral Mehta To: naveen yadav , "kernelnewbies@nl.linux.org" , "linux-mips@linux-mips.org" , "linux-arm-kernel-request@lists.arm.linux.org.uk" Date: Wed, 1 Dec 2010 21:38:48 +0530 Subject: RE: double kfree Thread-Topic: double kfree Thread-Index: AcuRMm+2wNeXDG91SCe+reDrJIqR6gAP5mnw Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28589 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Viral.Mehta@lntinfotech.com Precedence: bulk X-list: linux-mips ________________________________________ From: kernelnewbies-bounce@nl.linux.org [kernelnewbies-bounce@nl.linux.org] On Behalf Of naveen yadav Hi, >Hi all, > >I Have following question with regard for 2.6.30 kernel > > If we do double kfree() >a) Then what will happen? >b) Can kernel detect double kfree() ? What do you want to do ? >I gone through google to find some way to find it, there it mention >CONFIG_DEBUG_SLAB can help, but i am not sure how usefull is it. Can we look at your code ? This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. ______________________________________________________________________ From namhyung@gmail.com Wed Dec 1 17:34:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:34:58 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:47541 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493026Ab0LAQez (ORCPT ); Wed, 1 Dec 2010 17:34:55 +0100 Received: by pwj8 with SMTP id 8so1387749pwj.36 for ; Wed, 01 Dec 2010 08:34:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=MroLykGlReq/tIZgiDgM9slRnup+A+Uqn1Cm2l9Yzx8=; b=uJoU+uKxgd0f6r9I7a/CL461xRwVOOldHCQY1cfXHvlVILCINbw4ORokDRdCUR65gL b2/TkvbeAUUu9uUb0B9aGPML4lMxQnCbMez6Z8G7KzZVV+0/e5hrGk3bZF/irZEexNd9 vyNqhpucvJNtWIFHRx2NwGPS2ijRm3iuJr8lc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=SBtUKUia2YBPC4CIwIbhFobNk0zJdx+znFY0N4Kr4rKMa73OkfAwFlX+uKzNk0ItLX +GYYzath/CacsPl7b2NRz/F+WaFxnb+ayFZFiFHEHkFPD1SXl9ODsaDRtZgO5Apvz9zu 3mmwjNdg7Oeok11QJqzu7eY6QxkfAyZpYoTss= Received: by 10.142.192.20 with SMTP id p20mr9104526wff.42.1291221288617; Wed, 01 Dec 2010 08:34:48 -0800 (PST) Received: from localhost.localdomain ([211.201.183.198]) by mx.google.com with ESMTPS id w42sm183330wfh.15.2010.12.01.08.34.45 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Dec 2010 08:34:47 -0800 (PST) From: Namhyung Kim To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH] MIPS: Fix build failure on mips_sc_is_activated() Date: Thu, 2 Dec 2010 01:34:42 +0900 Message-Id: <1291221282-9056-1-git-send-email-namhyung@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28590 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: namhyung@gmail.com Precedence: bulk X-list: linux-mips The commit ea31a6b20371 ("MIPS: Honor L2 bypass bit") breaks malta build as follows. Looks like not compile-tested :( CC arch/mips/mm/sc-mips.o arch/mips/mm/sc-mips.c: In function 'mips_sc_is_activated': arch/mips/mm/sc-mips.c:77:7 error: 'config2' undeclared (first use in this function) arch/mips/mm/sc-mips.c:77:7 note: each undeclared identifier is reported only once arch/mips/mm/sc-mips.c:77:7 for each function it appears in arch/mips/mm/sc-mips.c:81:2 error: 'tmp' undeclared (first use in this function) arch/mips/mm/sc-mips.c:86:1 warning: control reaches end of non-void function make[3]: *** [arch/mips/mm/sc-mips.o] Error 1 make[2]: *** [arch/mips/mm/sc-mips.o] Error 2 make[1]: *** [sub-make] Error 2 make: *** [all] Error 2 Signed-off-by: Namhyung Kim --- arch/mips/mm/sc-mips.c | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 505feca..a168f52 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -66,8 +66,11 @@ static struct bcache_ops mips_sc_ops = { * 12..15 as implementation defined so below function will eventually have * to be replaced by a platform specific probe. */ -static inline int mips_sc_is_activated(struct cpuinfo_mips *c) +static inline int mips_sc_is_activated(struct cpuinfo_mips *c, + unsigned int config2) { + unsigned int tmp; + /* Check the bypass bit (L2B) */ switch (c->cputype) { case CPU_34K: @@ -83,6 +86,8 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) c->scache.linesz = 2 << tmp; else return 0; + + return 1; } static inline int __init mips_sc_probe(void) @@ -108,7 +113,7 @@ static inline int __init mips_sc_probe(void) config2 = read_c0_config2(); - if (!mips_sc_is_activated(c)) + if (!mips_sc_is_activated(c, config2)) return 0; tmp = (config2 >> 8) & 0x0f; -- 1.7.0.4 From ralf@linux-mips.org Wed Dec 1 17:55:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 17:55:22 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47484 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493029Ab0LAQzT (ORCPT ); Wed, 1 Dec 2010 17:55:19 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB1GtHt0007366; Wed, 1 Dec 2010 16:55:17 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB1GtHUf007363; Wed, 1 Dec 2010 16:55:17 GMT Date: Wed, 1 Dec 2010 16:55:17 +0000 From: Ralf Baechle To: Namhyung Kim Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: Fix build failure on mips_sc_is_activated() Message-ID: <20101201165517.GA5560@linux-mips.org> References: <1291221282-9056-1-git-send-email-namhyung@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1291221282-9056-1-git-send-email-namhyung@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28591 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Dec 02, 2010 at 01:34:42AM +0900, Namhyung Kim wrote: > The commit ea31a6b20371 ("MIPS: Honor L2 bypass bit") breaks > malta build as follows. Looks like not compile-tested :( Already fixed in the linux-mips git tree by an identical patch in commit 9a3475880131752d3d78ac25516fd3eab3fca871. Thanks anyway! Ralf From namhyung@gmail.com Wed Dec 1 18:03:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Dec 2010 18:03:28 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:39304 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493038Ab0LARDZ (ORCPT ); Wed, 1 Dec 2010 18:03:25 +0100 Received: by gyg4 with SMTP id 4so3829856gyg.36 for ; Wed, 01 Dec 2010 09:03:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=UXbO+N571YzFORa4xu8GF3KRgcaDHGMbPpvnsTiW9iA=; b=gEPLlLEuW1TmQxtGwsbcQLkZEJ2M4XRYNCcwpN1hfYATeFxJXmNv6+sLChyvQSMAU9 epyD07rP4uK3L5OoCUvwaWJFWh8ppIv1192nRpc1M5ozjOM3P0yNKmNXZMtI/xtxzavY 0YWHIOhraCPbiurA7yCO/abBjLfY6mYSdRa6I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=GQNZZpwrittj1V46XIBegPVWjjWpFtCVn++cTTmGFsYva45a4OQY3vPdJjsfIHLVH2 pEsx5ky2zyAUlgTB0pDwKBRmmv5LfHovZsymivhuocm332rxHpc8+txuMifNzUGgyDgm I2tPuIFqQt/yQk+OrtO79hL16eVMmncAgN/5s= Received: by 10.151.47.9 with SMTP id z9mr15033831ybj.278.1291222998794; Wed, 01 Dec 2010 09:03:18 -0800 (PST) Received: from [192.168.10.102] ([211.201.183.198]) by mx.google.com with ESMTPS id k2sm1801450ybj.20.2010.12.01.09.03.16 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Dec 2010 09:03:18 -0800 (PST) Subject: Re: [PATCH] MIPS: Fix build failure on mips_sc_is_activated() From: Namhyung Kim To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org In-Reply-To: <20101201165517.GA5560@linux-mips.org> References: <1291221282-9056-1-git-send-email-namhyung@gmail.com> <20101201165517.GA5560@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Thu, 02 Dec 2010 02:03:11 +0900 Message-ID: <1291222991.1684.49.camel@leonhard> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28592 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: namhyung@gmail.com Precedence: bulk X-list: linux-mips 2010-12-01 (수), 16:55 +0000, Ralf Baechle: > On Thu, Dec 02, 2010 at 01:34:42AM +0900, Namhyung Kim wrote: > > > The commit ea31a6b20371 ("MIPS: Honor L2 bypass bit") breaks > > malta build as follows. Looks like not compile-tested :( > > Already fixed in the linux-mips git tree by an identical patch in > commit 9a3475880131752d3d78ac25516fd3eab3fca871. > > Thanks anyway! > > Ralf Oh, didn't know that. Thanks. -- Regards, Namhyung Kim From lacombar@gmail.com Thu Dec 2 05:55:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 05:55:08 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:47014 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491161Ab0LBEzE convert rfc822-to-8bit (ORCPT ); Thu, 2 Dec 2010 05:55:04 +0100 Received: by gyg4 with SMTP id 4so4193140gyg.36 for ; Wed, 01 Dec 2010 20:54:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=jXbYlbYdsjXFf07Jw9rsPjbCldq3duzKx+Bb4p0gXAc=; b=SOPILWpo4GDnoD6Yk/Ak5MXsFdkvIPfOl1mTlVcDbjBoBc9b4GjT3rVT6ITNgpyQqR hB4mdSZ4EWTk4SzrT3CVkTmUhDOTpZIf9UoQSkUZL+q4FVDzwgjNV9ktFgokhUYtC1AA +0dCxVyC7hF9jfJpxrw6Co9qPVMVzNdg9Wd4Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=iIE8jv276gjg4rqdrXDOjjNGXYgK72FcGdneiX8LUQLmHuCytwsi0KGz2iFhp85IR8 Ppr38k1Lwthd/qy5ZfrnAtBNP9VYPksAd3iY9AYcsJVmgbyk6AHjM9ROJfdI+9smPJpt W6pqrsRXEj6wyMJWz+W4y3wxLYqi00X9E5JXw= MIME-Version: 1.0 Received: by 10.42.169.2 with SMTP id z2mr2810725icy.296.1291265698270; Wed, 01 Dec 2010 20:54:58 -0800 (PST) Received: by 10.42.176.10 with HTTP; Wed, 1 Dec 2010 20:54:58 -0800 (PST) In-Reply-To: <4CEB37F8.1050504@bitwagon.com> References: <4CEB37F8.1050504@bitwagon.com> Date: Wed, 1 Dec 2010 23:54:58 -0500 Message-ID: Subject: Re: Build failure triggered by recordmcount From: Arnaud Lacombe To: John Reiser Cc: Steven Rostedt , linux-mips@linux-mips.org, wu zhangjin Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28593 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lacombar@gmail.com Precedence: bulk X-list: linux-mips Hi Folks, On Mon, Nov 22, 2010 at 10:41 PM, John Reiser wrote: > It looks to me like the change which introduced "virtual functions" > forgot about cross-platform endianness.  Can anyone please test this patch? > Thank you to Arnaud for supplying before+after data files do_mounts*.o. > > > recordmcount: Honor endianness in fn_ELF_R_INFO > > --- >  scripts/recordmcount.h |    2 +- >  1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/scripts/recordmcount.h b/scripts/recordmcount.h > index 58e933a..3966717 100644 > --- a/scripts/recordmcount.h > +++ b/scripts/recordmcount.h > @@ -119,7 +119,7 @@ static uint_t (*Elf_r_sym)(Elf_Rel const *rp) = fn_ELF_R_SYM; >  static void fn_ELF_R_INFO(Elf_Rel *const rp, unsigned sym, unsigned type) >  { > -       rp->r_info = ELF_R_INFO(sym, type); > +       rp->r_info = _w(ELF_R_INFO(sym, type)); >  } >  static void (*Elf_r_info)(Elf_Rel *const rp, unsigned sym, unsigned type) = fn_ELF_R_INFO; >  -- 1.7.3.2 > This patch does not seems to have made its way up to Linus tree, has it been picked by anyone ? Thanks, - Arnaud From sshtylyov@mvista.com Thu Dec 2 12:49:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 12:49:30 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:65294 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493198Ab0LBLt0 (ORCPT ); Thu, 2 Dec 2010 12:49:26 +0100 Received: by eyd9 with SMTP id 9so4151429eyd.36 for ; Thu, 02 Dec 2010 03:49:25 -0800 (PST) Received: by 10.14.37.10 with SMTP id x10mr45261eea.30.1291290565273; Thu, 02 Dec 2010 03:49:25 -0800 (PST) Received: from [192.168.2.2] ([91.79.87.12]) by mx.google.com with ESMTPS id b52sm398969eei.13.2010.12.02.03.49.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Dec 2010 03:49:23 -0800 (PST) Message-ID: <4CF78755.2070109@mvista.com> Date: Thu, 02 Dec 2010 14:47:33 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Anoop P A CC: Ralf Baechle , linux-mips@linux-mips.org, mcdonald.shane@gmail.com Subject: Re: [RFC 1/3] VSMP support for msp71xx family of platforms. References: <1291220307.31413.14.camel@paanoop1-desktop> In-Reply-To: <1291220307.31413.14.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28594 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips On 01.12.2010 19:18, Anoop P A wrote: >> From e5148874243f0b2b610cd6b077084bd782961d94 Mon Sep 17 00:00:00 2001 > Message-Id: > > In-Reply-To: > References: > From: Anoop P A > Date: Wed, 1 Dec 2010 20:58:28 +0530 > Subject: [RFC 1/3] VSMP support for msp71xx family of platforms. Don't include this into the patch, or Ralf will have to hand edit it out. > Cc: anoop.pa@gmail.com This should be in the signoff section. > msp_smp.c initiliase IPI call and resched irq. Only "initializes". > Signed-off-by: Anoop P A [...] > diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile > b/arch/mips/pmc-sierra/msp71xx/Makefile > index e107f79..09627ae 100644 > --- a/arch/mips/pmc-sierra/msp71xx/Makefile > +++ b/arch/mips/pmc-sierra/msp71xx/Makefile > @@ -6,7 +6,8 @@ obj-y += msp_prom.o msp_setup.o msp_irq.o \ > obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o > obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o > obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o > -obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o > +obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o What does this change have to do with the rest of the patch? > diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c > b/arch/mips/pmc-sierra/msp71xx/msp_smp.c > new file mode 100644 > index 0000000..31a6c72 > --- /dev/null > +++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c > @@ -0,0 +1,75 @@ > +/* > + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. > + * Copyright (C) 2001 Ralf Baechle > + * Copyright (C) 2010 PMC-Sierra, Inc. > + * > + * VSMP support for MSP platforms . Derived from malta vsmp support. > + * > + * This program is free software; you can distribute it and/or modify > it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but > WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY > or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License > along > + * with this program; if not, write to the Free Software Foundation, > Inc., Your patch is line-wrapped. > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + * > + */ > +#include > +#include > + > +#ifdef CONFIG_MIPS_MT_SMP > +#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ > +#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */ Align the comments please, and align the macro values with a tab. > +static struct irqaction irq_resched = { > + .handler = ipi_resched_interrupt, > + .flags = IRQF_DISABLED|IRQF_PERCPU, Need spaces around |. > + .name = "IPI_resched" > +}; > + > +static struct irqaction irq_call = { > + .handler = ipi_call_interrupt, > + .flags = IRQF_DISABLED|IRQF_PERCPU, Need spaces around |. > + .name = "IPI_call" > +}; Need an empty line here. > +void __init arch_init_ipiirq(int irq, struct irqaction *action) > +{ > + setup_irq(irq, action); > + set_irq_handler(irq, handle_percpu_irq); > +} Need an empty line here. > +void __init msp_vsmp_int_init(void) > +{ > + set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); > + set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); Spaces between the function name and ( are not allowed -- run your patch thru scripts/checkpatch.pl. WBR, Sergei From sshtylyov@mvista.com Thu Dec 2 13:00:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 13:00:48 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:55454 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493201Ab0LBMAl (ORCPT ); Thu, 2 Dec 2010 13:00:41 +0100 Received: by eyd9 with SMTP id 9so4155593eyd.36 for ; Thu, 02 Dec 2010 04:00:41 -0800 (PST) Received: by 10.213.26.15 with SMTP id b15mr652720ebc.13.1291291241409; Thu, 02 Dec 2010 04:00:41 -0800 (PST) Received: from [192.168.2.2] ([91.79.87.12]) by mx.google.com with ESMTPS id v56sm412806eeh.2.2010.12.02.04.00.39 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Dec 2010 04:00:40 -0800 (PST) Message-ID: <4CF789F9.2030608@mvista.com> Date: Thu, 02 Dec 2010 14:58:49 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Anoop P A CC: kevink@paralogos.com, linux-mips@linux-mips.org, David Howells , Ralf Baechle Subject: Re: [RFC 3/3] VSMP support for MSP71xx family References: <1291220637.31413.20.camel@paanoop1-desktop> In-Reply-To: <1291220637.31413.20.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28595 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 01-12-2010 19:23, Anoop P A wrote: >> From 5bfd3ba210e521df2b493862446b4535bcdb0cdf Mon Sep 17 00:00:00 2001 > Message-Id: > <5bfd3ba210e521df2b493862446b4535bcdb0cdf.1291219118.git.anoop.pa@gmail.com> > In-Reply-To: > References: > From: Anoop P A > Date: Wed, 1 Dec 2010 21:08:37 +0530 > Subject: [RFC 3/3] VSMP support for MSP71xx family. > Cc: anoop.pa@gmail.com Don't include this header please -- it will have to be edited out anyway when applying the patch. > followig Following. > patches Patches? I see only one. > setup vectored interrupt in msp_irq.c and > register vsmp_ops from msp_setup.c. > It also changes get_c0_compare_int to return corresponding vpe timer > interrupt. > Signed-off-by: Anoop P A [...] > diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c > b/arch/mips/pmc-sierra/msp71xx/msp_irq.c > index 734d598..e9144c8 100644 > --- a/arch/mips/pmc-sierra/msp71xx/msp_irq.c > +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c [...] > @@ -29,6 +27,19 @@ extern void msp_slp_irq_dispatch(void); > extern void msp_cic_irq_init(void); > extern void msp_cic_irq_dispatch(void); > > +/* VSMP support init */ > +extern void msp_vsmp_int_init(void); > + > +/* vectored interrupt implementation */ > + > +/* SW0/1 interrupts are used for SMP/SMTC */ > +static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); } > +static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); } > +static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); } You probably forgot a space here... > +static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); } > +static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); } > + > + > /* > * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded > * hierarchical system. The first level are the direct MIPS interrupts > @@ -96,29 +107,51 @@ asmlinkage void plat_irq_dispatch(struct pt_regs > *regs) Your patch is line wrapped. > void __init arch_init_irq(void) > { > + /* assume we'll be using vectored interrupt mode except in UP mode*/ You forgot a spce before */. > /* setup the 2nd-level SLP register based interrupt controller */ > + /* VSMP /SMTC support support is not enabled for SLP */ The preferred style for the multiline comments is this: /* * bla * bla */ WBR, Sergei From sshtylyov@mvista.com Thu Dec 2 13:03:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 13:03:21 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:54632 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493203Ab0LBMDT (ORCPT ); Thu, 2 Dec 2010 13:03:19 +0100 Received: by eyd9 with SMTP id 9so4156988eyd.36 for ; Thu, 02 Dec 2010 04:03:18 -0800 (PST) Received: by 10.213.32.9 with SMTP id a9mr2508593ebd.60.1291291398526; Thu, 02 Dec 2010 04:03:18 -0800 (PST) Received: from [192.168.2.2] ([91.79.87.12]) by mx.google.com with ESMTPS id v56sm414729eeh.2.2010.12.02.04.03.16 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Dec 2010 04:03:17 -0800 (PST) Message-ID: <4CF78A96.8000109@mvista.com> Date: Thu, 02 Dec 2010 15:01:26 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Arnaud Lacombe CC: John Reiser , Steven Rostedt , linux-mips@linux-mips.org, wu zhangjin Subject: Re: Build failure triggered by recordmcount References: <4CEB37F8.1050504@bitwagon.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28596 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips On 02.12.2010 7:54, Arnaud Lacombe wrote: >> It looks to me like the change which introduced "virtual functions" >> forgot about cross-platform endianness. Can anyone please test this patch? >> Thank you to Arnaud for supplying before+after data files do_mounts*.o. >> recordmcount: Honor endianness in fn_ELF_R_INFO >> --- >> scripts/recordmcount.h | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> diff --git a/scripts/recordmcount.h b/scripts/recordmcount.h >> index 58e933a..3966717 100644 >> --- a/scripts/recordmcount.h >> +++ b/scripts/recordmcount.h >> @@ -119,7 +119,7 @@ static uint_t (*Elf_r_sym)(Elf_Rel const *rp) = fn_ELF_R_SYM; >> static void fn_ELF_R_INFO(Elf_Rel *const rp, unsigned sym, unsigned type) >> { >> - rp->r_info = ELF_R_INFO(sym, type); >> + rp->r_info = _w(ELF_R_INFO(sym, type)); >> } >> static void (*Elf_r_info)(Elf_Rel *const rp, unsigned sym, unsigned type) = fn_ELF_R_INFO; >> -- 1.7.3.2 > This patch does not seems to have made its way up to Linus tree, has > it been picked by anyone ? It was not signed off, so couldn't be applied. > Thanks, > - Arnaud WBR, Sergei From rostedt@goodmis.org Thu Dec 2 13:41:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 13:41:47 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.124]:40782 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493213Ab0LBMlo (ORCPT ); Thu, 2 Dec 2010 13:41:44 +0100 X-Authority-Analysis: v=1.1 cv=NFUeGz0loTdi/T6hXKngYYtckjed7x3pKvNOqmBBK18= c=1 sm=0 a=ClBoAdZ3F6cA:10 a=Q9fys5e9bTEA:10 a=OPBmh+XkhLl+Enan7BmTLg==:17 a=x7__WfI_cIIZ8pTkQnEA:9 a=hkIQd6hWhJ326Va0KoKsjSwHE1QA:4 a=PUjeQqilurYA:10 a=OPBmh+XkhLl+Enan7BmTLg==:117 X-Cloudmark-Score: 0 X-Originating-IP: 67.242.120.143 Received: from [67.242.120.143] ([67.242.120.143:39874] helo=[192.168.23.10]) by hrndva-oedge04.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 20/0D-12606-FF397FC4; Thu, 02 Dec 2010 12:41:37 +0000 Subject: Re: Build failure triggered by recordmcount From: Steven Rostedt To: Sergei Shtylyov Cc: Arnaud Lacombe , John Reiser , linux-mips@linux-mips.org, wu zhangjin In-Reply-To: <4CF78A96.8000109@mvista.com> References: <4CEB37F8.1050504@bitwagon.com> <4CF78A96.8000109@mvista.com> Content-Type: text/plain; charset="ISO-8859-15" Date: Thu, 02 Dec 2010 07:41:34 -0500 Message-ID: <1291293694.12005.2.camel@gandalf.stny.rr.com> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28597 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk X-list: linux-mips On Thu, 2010-12-02 at 15:01 +0300, Sergei Shtylyov wrote: > > This patch does not seems to have made its way up to Linus tree, has > > it been picked by anyone ? I have it queued, but have been working on other things (things that pay me ;-) > > It was not signed off, so couldn't be applied. You're right! I only had it in the mbox to be queued. I would have notice this when I pulled it into git. John, Can you reply with your signed-off-by? Thanks, -- Steve From jreiser@bitwagon.com Thu Dec 2 15:38:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 15:38:49 +0100 (CET) Received: from bitwagon.com ([74.82.39.175]:45462 "HELO bitwagon.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1493234Ab0LBOim (ORCPT ); Thu, 2 Dec 2010 15:38:42 +0100 Received: from f11-64.local ([67.171.188.169]) by bitwagon.com for ; Thu, 2 Dec 2010 06:38:31 -0800 Message-ID: <4CF7AF4D.1060207@bitwagon.com> Date: Thu, 02 Dec 2010 06:38:05 -0800 From: John Reiser Organization: - User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc11 Thunderbird/3.0.4 MIME-Version: 1.0 To: Steven Rostedt CC: Sergei Shtylyov , Arnaud Lacombe , linux-mips@linux-mips.org, wu zhangjin Subject: Re: Build failure triggered by recordmcount References: <4CEB37F8.1050504@bitwagon.com> <4CF78A96.8000109@mvista.com> In-Reply-To: <4CF78A96.8000109@mvista.com> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28598 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jreiser@bitwagon.com Precedence: bulk X-list: linux-mips On 12/02/2010 04:01 AM, Sergei Shtylyov wrote: > On 02.12.2010 7:54, Arnaud Lacombe wrote: > >>> It looks to me like the change which introduced "virtual functions" >>> forgot about cross-platform endianness. Can anyone please test this >>> patch? >>> Thank you to Arnaud for supplying before+after data files do_mounts*.o. > > >>> recordmcount: Honor endianness in fn_ELF_R_INFO > >>> --- >>> scripts/recordmcount.h | 2 +- >>> 1 files changed, 1 insertions(+), 1 deletions(-) > >>> diff --git a/scripts/recordmcount.h b/scripts/recordmcount.h >>> index 58e933a..3966717 100644 >>> --- a/scripts/recordmcount.h >>> +++ b/scripts/recordmcount.h >>> @@ -119,7 +119,7 @@ static uint_t (*Elf_r_sym)(Elf_Rel const *rp) = >>> fn_ELF_R_SYM; >>> static void fn_ELF_R_INFO(Elf_Rel *const rp, unsigned sym, unsigned >>> type) >>> { >>> - rp->r_info = ELF_R_INFO(sym, type); >>> + rp->r_info = _w(ELF_R_INFO(sym, type)); >>> } >>> static void (*Elf_r_info)(Elf_Rel *const rp, unsigned sym, unsigned >>> type) = fn_ELF_R_INFO; >>> -- 1.7.3.2 > >> This patch does not seems to have made its way up to Linus tree, has >> it been picked by anyone ? > > It was not signed off, so couldn't be applied. > Signed-off-by: John Reiser -- From ralf@linux-mips.org Thu Dec 2 15:54:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 15:54:28 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35037 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493237Ab0LBOyV (ORCPT ); Thu, 2 Dec 2010 15:54:21 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB2EsDII008409; Thu, 2 Dec 2010 14:54:13 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB2EsCYb008407; Thu, 2 Dec 2010 14:54:12 GMT Date: Thu, 2 Dec 2010 14:54:12 +0000 From: Ralf Baechle To: Arnaud Lacombe Cc: wu zhangjin , John Reiser , Steven Rostedt , linux-mips@linux-mips.org Subject: Re: Build failure triggered by recordmcount Message-ID: <20101202145412.GA7503@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28599 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Nov 22, 2010 at 01:46:54PM -0500, Arnaud Lacombe wrote: > On Mon, Nov 22, 2010 at 9:57 AM, wu zhangjin wrote: > > Hi, > > > > The cause should be the endian problem, I guess you were cross-compiling it? > > > yes. > > > If we compile the kernel for (32bit + big endian) target on an x86 > > machine(little endian) or reversely, then, it will fail. > > > > Since the scripts/recordmcount is compiled with the local toolchain, > > the data structs will be explained according to the local > > configuration(endian...). > > > will it ? recordmcount.c does not switch endianness based on the host, > but based on format of the object file, see the switch > (ehdr->e_ident[EI_DATA]) { ... } in do_file(), the result does also > depend a runtime endianness check. > > > So, we may need to custom our own elf.h for recordmcount according to > > the target type(endian here) of the kernel image: > > > > At first, pass the target information to recordmcount(only a demo > > here, we may need to clear it carefully): Looks all right to me. Steven, can you merge it? Acked-by: Ralf Baechle Ralf From ralf@linux-mips.org Thu Dec 2 16:15:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 16:16:03 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47773 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493245Ab0LBPP4 (ORCPT ); Thu, 2 Dec 2010 16:15:56 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB2FFl1P008952; Thu, 2 Dec 2010 15:15:47 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB2FFk1j008950; Thu, 2 Dec 2010 15:15:46 GMT Date: Thu, 2 Dec 2010 15:15:46 +0000 From: Ralf Baechle To: wu zhangjin Cc: Arnaud Lacombe , John Reiser , Steven Rostedt , linux-mips@linux-mips.org Subject: Re: Build failure triggered by recordmcount Message-ID: <20101202151546.GB7503@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28600 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Nov 22, 2010 at 10:57:40PM +0800, wu zhangjin wrote: > The cause should be the endian problem, I guess you were cross-compiling it? > > If we compile the kernel for (32bit + big endian) target on an x86 > machine(little endian) or reversely, then, it will fail. > > Since the scripts/recordmcount is compiled with the local toolchain, > the data structs will be explained according to the local > configuration(endian...). > > So, we may need to custom our own elf.h for recordmcount according to > the target type(endian here) of the kernel image: > > At first, pass the target information to recordmcount(only a demo > here, we may need to clear it carefully): > > diff --git a/scripts/Makefile b/scripts/Makefile > index 2e08810..151fe3e 100644 > --- a/scripts/Makefile > +++ b/scripts/Makefile > @@ -11,6 +11,9 @@ hostprogs-$(CONFIG_KALLSYMS) += kallsyms > hostprogs-$(CONFIG_LOGO) += pnmtologo > hostprogs-$(CONFIG_VT) += conmakehash > hostprogs-$(CONFIG_IKCONFIG) += bin2c > +HOSTCFLAGS_recordmcount.o += -DARCH=__$(ARCH)__ \ > + -DBIT=__$(if $(CONFIG_64BIT),64,32)__ \ > + -DENDIAN=__$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)__ > hostprogs-$(BUILD_C_RECORDMCOUNT) += recordmcount > > always := $(hostprogs-y) $(hostprogs-m) FYI, dropping this one from the patchworks queue then as John's patch seems to be the right thing. Ralf From rostedt@goodmis.org Thu Dec 2 16:19:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 16:19:11 +0100 (CET) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.122]:40560 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493245Ab0LBPTE (ORCPT ); Thu, 2 Dec 2010 16:19:04 +0100 X-Authority-Analysis: v=1.1 cv=6ptpMFIBtxRk0xdOb6IhJTbTLVRlKjWFes7R4SsWCrA= c=1 sm=0 a=ClBoAdZ3F6cA:10 a=Q9fys5e9bTEA:10 a=OPBmh+XkhLl+Enan7BmTLg==:17 a=WPyIoOwQAAAA:8 a=w5Mvk01vzc27DdUpXGAA:9 a=8DTp0P9Tbi2iqBqt1eMA:7 a=lEtgAm3pwO0Pt8yHSJ7MvwtLFpUA:4 a=PUjeQqilurYA:10 a=1DbiqZag68YA:10 a=OPBmh+XkhLl+Enan7BmTLg==:117 X-Cloudmark-Score: 0 X-Originating-IP: 67.242.120.143 Received: from [67.242.120.143] ([67.242.120.143:39383] helo=[192.168.23.10]) by hrndva-oedge01.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id 6B/E1-26142-1E8B7FC4; Thu, 02 Dec 2010 15:18:58 +0000 Subject: Re: Build failure triggered by recordmcount From: Steven Rostedt To: Ralf Baechle Cc: Arnaud Lacombe , wu zhangjin , John Reiser , linux-mips@linux-mips.org In-Reply-To: <20101202145412.GA7503@linux-mips.org> References: <20101202145412.GA7503@linux-mips.org> Content-Type: text/plain; charset="ISO-8859-15" Date: Thu, 02 Dec 2010 10:18:56 -0500 Message-ID: <1291303136.12005.6.camel@gandalf.stny.rr.com> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28601 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk X-list: linux-mips On Thu, 2010-12-02 at 14:54 +0000, Ralf Baechle wrote: > > > So, we may need to custom our own elf.h for recordmcount according > to > > > the target type(endian here) of the kernel image: > > > > > > At first, pass the target information to recordmcount(only a demo > > > here, we may need to clear it carefully): > > Looks all right to me. Steven, can you merge it? > > Acked-by: Ralf Baechle > Will do, thanks! -- Steve From andy.kennedy@adtran.com Thu Dec 2 17:15:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 17:15:22 +0100 (CET) Received: from p02c12o147.mxlogic.net ([208.65.145.80]:49218 "EHLO p02c12o147.mxlogic.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493242Ab0LBQPP convert rfc822-to-8bit (ORCPT ); Thu, 2 Dec 2010 17:15:15 +0100 Received: from unknown [76.164.174.81] by p02c12o147.mxlogic.net(mxl_mta-6.8.0-0) with SMTP id 016c7fc4.0.19668.00-326.45958.p02c12o147.mxlogic.net (envelope-from ); Thu, 02 Dec 2010 09:15:14 -0700 (MST) X-MXL-Hash: 4cf7c6126834398f-c61c2af4c688db07a175be72adc7d11ef9bf9fa4 Received: from corp-exfr2.corp.adtran.com (172.23.101.22) by ex-hc1.corp.adtran.com (172.22.50.71) with Microsoft SMTP Server id 14.1.255.0; Thu, 2 Dec 2010 10:15:01 -0600 Received: from EXV1.corp.adtran.com ([172.22.48.215]) by corp-exfr2.corp.adtran.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 2 Dec 2010 10:15:00 -0600 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-Class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Issues attempting to boot vmlinuz Date: Thu, 2 Dec 2010 10:15:39 -0600 Message-ID: <9AC3F0E75060224C8BBC5BA2DDC8853A1E4E035F@EXV1.corp.adtran.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Issues attempting to boot vmlinuz Thread-Index: AcuSPCk1yeKNcWT/Q4Srhj6LbAm64w== From: ANDY KENNEDY To: X-OriginalArrivalTime: 02 Dec 2010 16:15:00.0725 (UTC) FILETIME=[11F67A50:01CB923C] X-Spam: [F=0.2000000000; CM=0.500; S=0.200(2010120101)] X-MAIL-FROM: X-SOURCE-IP: [(unknown)] X-AnalysisOut: [v=1.0 c=1 a=PjMH8U03xLAA:10 a=BLceEmwcHowA:10 a=kj9zAlcOel] X-AnalysisOut: [0A:10 a=0XgpNN2/4a34ymu16SVwsQ==:17 a=zTZC_Sm-60neGbu33w8A] X-AnalysisOut: [:9 a=N288De-YdjTRnJcXb0sA:7 a=7aqQGRpnWVA6h7vrVcxRLJbpmdUA] X-AnalysisOut: [:4 a=CjuIK1q_8ugA:10] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ANDY.KENNEDY@adtran.com Precedence: bulk X-list: linux-mips I create a vmlinux kernel and boot it just fine. The boot loader loads the kernel to 0x80404210 and I can execute from there. I next attempted to adjust the Kconfig files to allow me to build a vmlinuz. The boot loader puts the kernel image at 0x8075e8b0 which is the computed location of where the zipped kernel should go (I think). What happens next is an exception is returned to the boot loader and I end up back at the boot loader prompt: * Exception 0x0a (user) : Reserved instruction * * in address: 8075e8b0 __initcall_pm_qos_power_init7+0x48054: [8075e8b0] 9cda39f9 lwu r26,0x39f9(r6) So, I'm attempting now to hack around this issue, though I don't really know where to begin (I've been working with mips for about 4 wks now). I did find that the boot loader is configuring itself as the exception handler and it catches 0x0a (Reserved instruction exception - according to the mips documentation). But what does this mean? Any help you provide would be greatly appreciated. Thanks, Andy From anoop.pa@gmail.com Thu Dec 2 18:34:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Dec 2010 18:34:08 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:51530 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492335Ab0LBReA convert rfc822-to-8bit (ORCPT ); Thu, 2 Dec 2010 18:34:00 +0100 Received: by fxm19 with SMTP id 19so3474129fxm.36 for ; Thu, 02 Dec 2010 09:33:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=yydP2uiy442hR+TIm/kShJP+obcsROR/MsBao3CxDZc=; b=HWfiutyxl3oDpVvgsQH8aJ9A7GwYGQOHJi7Egez+ZZwI3HgR8jVoNucSXeEPP/HnbS kXdDhm5eKN8dXEMcWbR5lTefkzX7VqTlsRvKFudKb/8bRCleLvuTAVhzCso/IeTE8Sio PUPX5DGR0mtspSoFDF2G35yFCTNVrdzVNXMco= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=wTIsszDExjYw8lHlPnIDUzYQva2I6AhdUOpP9bXgz2hSGP2ZcRHIgGHGptIPZK8vvn 4YIk9ntlpQRvpc8+QRyJAP+Go2FxMt8vWN8n9gTgq+FGOnePMm+x+O98yY9hQQK52EFX bfhB9vg4HDt0Jx5VkKP1V0Wgcw9fy2sSL97WU= MIME-Version: 1.0 Received: by 10.223.79.72 with SMTP id o8mr878180fak.83.1291310849161; Thu, 02 Dec 2010 09:27:29 -0800 (PST) Received: by 10.223.101.198 with HTTP; Thu, 2 Dec 2010 09:27:29 -0800 (PST) In-Reply-To: <4CF78755.2070109@mvista.com> References: <1291220307.31413.14.camel@paanoop1-desktop> <4CF78755.2070109@mvista.com> Date: Thu, 2 Dec 2010 22:57:29 +0530 Message-ID: Subject: Re: [RFC 1/3] VSMP support for msp71xx family of platforms. From: anoop pa To: Sergei Shtylyov Cc: Ralf Baechle , linux-mips@linux-mips.org, mcdonald.shane@gmail.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28603 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips On Thu, Dec 2, 2010 at 5:17 PM, Sergei Shtylyov wrote: > On 01.12.2010 19:18, Anoop P A wrote: > >   Don't include this into the patch, or Ralf will have to hand edit it out. > Sure. Will take care in next patch series onwards. >> Cc: anoop.pa@gmail.com > >   This should be in the signoff section. > OK >> msp_smp.c initiliase IPI call and resched irq. > >   Only "initializes". > Sorry my bad. >> -obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o >> +obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o > >   What does this change have to do with the rest of the patch? > This change is required for next patch in this. series.Is this potentially wrong . Do I want to move this to next patch? >   Your patch is line-wrapped. > Will take care while creating next set of patches. >> +#define MIPS_CPU_IPI_CALL_IRQ 1                /* SW int 1 for call */ > >   Align the comments please, and align the macro values with a tab. > Ok >> +static struct irqaction irq_resched = { >> +       .handler        = ipi_resched_interrupt, >> +       .flags          = IRQF_DISABLED|IRQF_PERCPU, > >   Need spaces around |. > O.k >   Need an empty line here. > Ok >> +       set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); > >   Spaces between the function name and ( are not allowed -- run your patch > thru scripts/checkpatch.pl. Not sure what went wrong. I had checked it before sending . linux.git$ ./scripts/checkpatch.pl 0001-VSMP-support-for-msp71xx-family-of-platforms.patch total: 0 errors, 0 warnings, 84 lines checked 0001-VSMP-support-for-msp71xx-family-of-platforms.patch has no obvious style problems and is ready for submission. > > WBR, Sergei > Sergei Thank you very much reviewing the code. Regards, Anoop From sshtylyov@mvista.com Sun Dec 5 15:01:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Dec 2010 15:01:58 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:33076 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491128Ab0LEOBy (ORCPT ); Sun, 5 Dec 2010 15:01:54 +0100 Received: by eyd9 with SMTP id 9so5791747eyd.36 for ; Sun, 05 Dec 2010 06:01:51 -0800 (PST) Received: by 10.213.8.70 with SMTP id g6mr545338ebg.44.1291557711373; Sun, 05 Dec 2010 06:01:51 -0800 (PST) Received: from [192.168.2.2] ([91.79.97.62]) by mx.google.com with ESMTPS id w20sm3621468eeh.6.2010.12.05.06.01.48 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 05 Dec 2010 06:01:49 -0800 (PST) Message-ID: <4CFB9B15.9050308@mvista.com> Date: Sun, 05 Dec 2010 17:00:53 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: anoop pa CC: Ralf Baechle , linux-mips@linux-mips.org, mcdonald.shane@gmail.com Subject: Re: [RFC 1/3] VSMP support for msp71xx family of platforms. References: <1291220307.31413.14.camel@paanoop1-desktop> <4CF78755.2070109@mvista.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28605 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1202 Lines: 40 Hello. On 02-12-2010 20:27, anoop pa wrote: >>> -obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o >>> +obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o >> What does this change have to do with the rest of the patch? > This change is required for next patch in this. series.Is this > potentially wrong . It's not wrong -- it's just that one patch needs to address one issue. Or at least you should describe all your changed in the changelog. > Do I want to move this to next patch? I don't know what you want. :-) >>> + set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); >> Spaces between the function name and ( are not allowed -- run your patch >> thru scripts/checkpatch.pl. > Not sure what went wrong. I had checked it before sending . > linux.git$ ./scripts/checkpatch.pl > 0001-VSMP-support-for-msp71xx-family-of-platforms.patch > total: 0 errors, 0 warnings, 84 lines checked > 0001-VSMP-support-for-msp71xx-family-of-platforms.patch has no obvious > style problems and is ready for submission. I'm not sure -- perhaps checkpatch.pl has stopped complaing about those spaces... but it ceratainly did in the past. > Regards, > Anoop WBR, Sergei From mattst88@gmail.com Mon Dec 6 05:15:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 05:15:19 +0100 (CET) Received: from mail-gx0-f176.google.com ([209.85.161.176]:65148 "EHLO mail-gx0-f176.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490955Ab0LFEPP (ORCPT ); Mon, 6 Dec 2010 05:15:15 +0100 Received: by gxk4 with SMTP id 4so6619147gxk.35 for ; Sun, 05 Dec 2010 20:15:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=fRc2cB7JXFHnSMcu8LJdiBzm+qIDr2zU2Aicw2pK/wI=; b=BrDz6iAwrHheq2q2nMCxSTPGlsyePdHMXVKSRXFPMQmiGAT25NbHk+JCreD7VUHRd6 1Bk24IrZPdb/wq6Wy2wlNfKtuGbfFPJWq9/2PVsE0CgFSRdBjv1gkqTJ6yk6l1QEsoZX cVxGjWZwlAz3sYPdJYihuNmYgcSjv5M3AYIzI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=BugjNUVilg8g7fJVIuztTUs/2FnBWshWW/8hm1aKTBV/sbgppJ9QVXcc77vr/dtsqv sT3WY/MtPtaWIT+crQsQob4I6ivMnYgiLPmTyMofxVjoa9DFbos7zlxcaK/vsjw7giEr 7Bh+Ch1GHVcY6ywUPZiXpr78R7O8DdhekxaKs= Received: by 10.150.136.18 with SMTP id j18mr8151313ybd.169.1291608908054; Sun, 05 Dec 2010 20:15:08 -0800 (PST) Received: from localhost (cpe-065-190-173-137.nc.res.rr.com [65.190.173.137]) by mx.google.com with ESMTPS id u10sm1352778yba.1.2010.12.05.20.15.05 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 05 Dec 2010 20:15:06 -0800 (PST) From: Matt Turner To: Jean Delvare Cc: linux-mips@linux-mips.org, linux-i2c@vger.kernel.org, "Maciej W. Rozycki" , Matt Turner Subject: [PATCH 1/3] RTC: SMBus support for the M41T80, etc. driver Date: Sun, 5 Dec 2010 23:15:03 -0500 Message-Id: <1291608903-16993-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.2.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28606 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 12070 Lines: 410 From: Maciej W. Rozycki The BCM1250A SOC which is used on the SWARM board utilising an M41T81 chip only supports pure I2C in the raw bit-banged mode. Nobody sane really wants to use it unless absolutely necessary and the M41T80, etc. chips work just fine with an SMBus adapter which is what the standard mode of operation of the BCM1250A. The only drawback of byte accesses with the M41T80 is the chip only latches clock data registers for the duration of an I2C transaction which works fine with a block transfers, but not byte-wise accesses. The driver currently requires an I2C adapter providing both SMBus and raw I2C access. This is a set of changes to make it work with any SMBus adapter providing at least read byte and write byte protocols. Additionally, if a given SMBus adapter supports I2C block read and/or write protocols (a common extension beyond the SMBus spec), they are used as well. The problem of unlatched clock data if SMBus byte transactions are used is resolved in the standard way. For raw I2C controllers this functionality is provided by the I2C core as SMBus emulation in a transparent way. Tested-by: Matt Turner Signed-off-by: Matt Turner --- This patch was originally sent to the i2c list in May 2008, but looks like it got lost waiting on some changes in arch/mips to land upstream [2]. These landed long ago, so this patch should be good to go in as well. Jean, please apply. [1] http://lists.lm-sensors.org/pipermail/i2c/2008-May/003739.html [2] http://lists.lm-sensors.org/pipermail/i2c/2008-May/003658.html drivers/rtc/rtc-m41t80.c | 251 ++++++++++++++++++++-------------------------- 1 files changed, 107 insertions(+), 144 deletions(-) diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c index 5a8daa3..2233ed5 100644 --- a/drivers/rtc/rtc-m41t80.c +++ b/drivers/rtc/rtc-m41t80.c @@ -6,6 +6,7 @@ * Based on m41t00.c by Mark A. Greer * * 2006 (c) mycable GmbH + * Copyright (c) 2008 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -38,6 +39,8 @@ #define M41T80_REG_DAY 5 #define M41T80_REG_MON 6 #define M41T80_REG_YEAR 7 +#define M41T80_REG_CONTROL 8 +#define M41T80_REG_WATCHDOG 9 #define M41T80_REG_ALARM_MON 0xa #define M41T80_REG_ALARM_DAY 0xb #define M41T80_REG_ALARM_HOUR 0xc @@ -66,7 +69,7 @@ #define M41T80_FEATURE_WD (1 << 3) /* Extra watchdog resolution */ #define M41T80_FEATURE_SQ_ALT (1 << 4) /* RSx bits are in reg 4 */ -#define DRV_VERSION "0.05" +#define DRV_VERSION "0.06" static DEFINE_MUTEX(m41t80_rtc_mutex); static const struct i2c_device_id m41t80_id[] = { @@ -89,31 +92,89 @@ struct m41t80_data { struct rtc_device *rtc; }; -static int m41t80_get_datetime(struct i2c_client *client, - struct rtc_time *tm) + +static int m41t80_write_block_data(struct i2c_client *client, + u8 reg, u8 num, u8 *buf) { - u8 buf[M41T80_DATETIME_REG_SIZE], dt_addr[1] = { M41T80_REG_SEC }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, - .buf = buf + M41T80_REG_SEC, - }, - }; + int i, rc; + + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) { + i = i2c_smbus_write_i2c_block_data(client, reg, num, buf); + } else { + for (i = 0; i < num; i++) { + rc = i2c_smbus_write_byte_data(client, reg + i, + buf[i]); + if (rc < 0) { + i = rc; + goto out; + } + } + } +out: + return i; +} - if (i2c_transfer(client->adapter, msgs, 2) < 0) { - dev_err(&client->dev, "read error\n"); - return -EIO; +static int m41t80_read_block_data(struct i2c_client *client, + u8 reg, u8 num, u8 *buf) +{ + int i, rc; + + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + i = i2c_smbus_read_i2c_block_data(client, reg, num, buf); + } else { + for (i = 0; i < num; i++) { + rc = i2c_smbus_read_byte_data(client, reg + i); + if (rc < 0) { + i = rc; + goto out; + } + buf[i] = rc; + } } +out: + return i; +} + +static int m41t80_get_datetime(struct i2c_client *client, struct rtc_time *tm) +{ + u8 buf[M41T80_DATETIME_REG_SIZE]; + int loops = 2; + int sec0, sec1; + + /* + * Time registers are latched by this chip if an I2C block + * transfer is used, but with SMBus-style byte accesses + * this is not the case, so check seconds for a wraparound. + */ + do { + if (m41t80_read_block_data(client, M41T80_REG_SEC, + M41T80_DATETIME_REG_SIZE - + M41T80_REG_SEC, + buf + M41T80_REG_SEC) < 0) { + dev_err(&client->dev, "read error\n"); + return -EIO; + } + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + sec1 = buf[M41T80_REG_SEC]; + break; + } + + sec0 = buf[M41T80_REG_SEC]; + sec1 = i2c_smbus_read_byte_data(client, M41T80_REG_SEC); + if (sec1 < 0) { + dev_err(&client->dev, "read error\n"); + return -EIO; + } + + sec0 = bcd2bin(sec0 & 0x7f); + sec1 = bcd2bin(sec1 & 0x7f); + } while (sec1 < sec0 && --loops); - tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f); + tm->tm_sec = sec1; + tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f); tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f); @@ -128,39 +189,16 @@ static int m41t80_get_datetime(struct i2c_client *client, /* Sets the given date and time to the real time clock. */ static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm) { - u8 wbuf[1 + M41T80_DATETIME_REG_SIZE]; - u8 *buf = &wbuf[1]; - u8 dt_addr[1] = { M41T80_REG_SEC }; - struct i2c_msg msgs_in[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, - .buf = buf + M41T80_REG_SEC, - }, - }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1 + M41T80_DATETIME_REG_SIZE, - .buf = wbuf, - }, - }; + u8 buf[M41T80_DATETIME_REG_SIZE]; /* Read current reg values into buf[1..7] */ - if (i2c_transfer(client->adapter, msgs_in, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_SEC, + M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, + buf + M41T80_REG_SEC) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } - wbuf[0] = 0; /* offset into rtc's regs */ /* Merge time-data and register flags into buf[0..7] */ buf[M41T80_REG_SSEC] = 0; buf[M41T80_REG_SEC] = @@ -177,8 +215,8 @@ static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm) bin2bcd(tm->tm_mon + 1) | (buf[M41T80_REG_MON] & ~0x1f); /* assume 20YY not 19YY */ buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year % 100); - - if (i2c_transfer(client->adapter, msgs, 1) != 1) { + if (m41t80_write_block_data(client, M41T80_REG_SSEC, + M41T80_DATETIME_REG_SIZE, buf) < 0) { dev_err(&client->dev, "write error\n"); return -EIO; } @@ -252,34 +290,11 @@ err: static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) { struct i2c_client *client = to_i2c_client(dev); - u8 wbuf[1 + M41T80_ALARM_REG_SIZE]; - u8 *buf = &wbuf[1]; + u8 buf[M41T80_ALARM_REG_SIZE]; u8 *reg = buf - M41T80_REG_ALARM_MON; - u8 dt_addr[1] = { M41T80_REG_ALARM_MON }; - struct i2c_msg msgs_in[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_ALARM_REG_SIZE, - .buf = buf, - }, - }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1 + M41T80_ALARM_REG_SIZE, - .buf = wbuf, - }, - }; - if (i2c_transfer(client->adapter, msgs_in, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE, buf) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } @@ -289,7 +304,6 @@ static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) reg[M41T80_REG_ALARM_MIN] = 0; reg[M41T80_REG_ALARM_SEC] = 0; - wbuf[0] = M41T80_REG_ALARM_MON; /* offset into rtc's regs */ reg[M41T80_REG_ALARM_SEC] |= t->time.tm_sec >= 0 ? bin2bcd(t->time.tm_sec) : 0x80; reg[M41T80_REG_ALARM_MIN] |= t->time.tm_min >= 0 ? @@ -303,7 +317,8 @@ static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) else reg[M41T80_REG_ALARM_DAY] |= 0x40; - if (i2c_transfer(client->adapter, msgs, 1) != 1) { + if (m41t80_write_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE, buf) < 0) { dev_err(&client->dev, "write error\n"); return -EIO; } @@ -323,24 +338,10 @@ static int m41t80_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *t) { struct i2c_client *client = to_i2c_client(dev); u8 buf[M41T80_ALARM_REG_SIZE + 1]; /* all alarm regs and flags */ - u8 dt_addr[1] = { M41T80_REG_ALARM_MON }; u8 *reg = buf - M41T80_REG_ALARM_MON; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_ALARM_REG_SIZE + 1, - .buf = buf, - }, - }; - if (i2c_transfer(client->adapter, msgs, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE + 1, buf) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } @@ -513,26 +514,16 @@ static int boot_flag; */ static void wdt_ping(void) { - unsigned char i2c_data[2]; - struct i2c_msg msgs1[1] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 2, - .buf = i2c_data, - }, - }; - struct m41t80_data *clientdata = i2c_get_clientdata(save_client); + u8 wdt = 0x80; /* WDS = 1 (0x80) */ - i2c_data[0] = 0x09; /* watchdog register */ + struct m41t80_data *clientdata = i2c_get_clientdata(save_client); if (wdt_margin > 31) - i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */ + /* mulitplier = WD_TIMO / 4, resolution = 4s (0x3) */ + wdt |= (wdt_margin & 0xfc) | 0x3; else - /* - * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02) - */ - i2c_data[1] = wdt_margin<<2 | 0x82; + /* mulitplier = WD_TIMO, resolution = 1s (0x2) */ + wdt |= wdt_margin << 2 | 0x2; /* * M41T65 has three bits for watchdog resolution. Don't set bit 7, as @@ -541,7 +532,7 @@ static void wdt_ping(void) if (clientdata->features & M41T80_FEATURE_WD) i2c_data[1] &= ~M41T80_WATCHDOG_RB2; - i2c_transfer(save_client->adapter, msgs1, 1); + i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, wdt); } /** @@ -551,36 +542,8 @@ static void wdt_ping(void) */ static void wdt_disable(void) { - unsigned char i2c_data[2], i2c_buf[0x10]; - struct i2c_msg msgs0[2] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 1, - .buf = i2c_data, - }, - { - .addr = save_client->addr, - .flags = I2C_M_RD, - .len = 1, - .buf = i2c_buf, - }, - }; - struct i2c_msg msgs1[1] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 2, - .buf = i2c_data, - }, - }; - - i2c_data[0] = 0x09; - i2c_transfer(save_client->adapter, msgs0, 2); - - i2c_data[0] = 0x09; - i2c_data[1] = 0x00; - i2c_transfer(save_client->adapter, msgs1, 1); + i2c_smbus_read_byte_data(save_client, M41T80_REG_WATCHDOG); + i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, 0); } /** @@ -782,8 +745,8 @@ static int m41t80_probe(struct i2c_client *client, struct rtc_time tm; struct m41t80_data *clientdata = NULL; - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C - | I2C_FUNC_SMBUS_BYTE_DATA)) { + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) { rc = -ENODEV; goto exit; } -- 1.7.3.2 From mattst88@gmail.com Mon Dec 6 05:16:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 05:16:45 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:43067 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490955Ab0LFEQj (ORCPT ); Mon, 6 Dec 2010 05:16:39 +0100 Received: by gyg4 with SMTP id 4so6224490gyg.36 for ; Sun, 05 Dec 2010 20:16:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=M0fXeTXpLLQwT1mJbj4gQt21/JDP8r3qeMA9kGhevb8=; b=YQsev6DYTDNdtBqddBQcElQQdZ03viPQjTP+PwR27TxMHJtIQrk1S+CGK2cUUSYexF IZ69fFLvLVeTcjpCM3434MJ7rI32r8T5zWcauMr08lBY9Ie/PHu9BAZLT2U3nbCAmoVS p/BxP90//68TmcECLXo8o0zagXW5WvWo66/lI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=JQ/LNcu0nwUW8UhuF52n/e+65fKm2ih3S3pooEJVJtj9wDhRSXKsHlxLsaCUI421pM dj1kNILda2zorMd/nZWjJ1w3j0sOFcquzmvstW6uZeJUiVtJtKDqkx5lo63j18XY5a88 gb2C38r8LMOhrj4KwvzXgAODk9eveXAxVXATU= Received: by 10.151.150.4 with SMTP id c4mr8751987ybo.6.1291608992274; Sun, 05 Dec 2010 20:16:32 -0800 (PST) Received: from localhost (cpe-065-190-173-137.nc.res.rr.com [65.190.173.137]) by mx.google.com with ESMTPS id p30sm3014822ybk.20.2010.12.05.20.16.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 05 Dec 2010 20:16:31 -0800 (PST) From: Matt Turner To: Ralf Baechle Cc: Jean Delvare , linux-mips@linux-mips.org, "Maciej W. Rozycki" , Matt Turner Subject: [PATCH 2/3] MIPS: clean up SWARM RTC setup Date: Sun, 5 Dec 2010 23:16:40 -0500 Message-Id: <1291609000-17028-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.2.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28607 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 16037 Lines: 564 From: Maciej W. Rozycki Tested-by: Matt Turner Signed-off-by: Matt Turner --- arch/mips/sibyte/swarm/Makefile | 3 +- arch/mips/sibyte/swarm/rtc_m41t81.c | 233 -------------------------------- arch/mips/sibyte/swarm/rtc_xicor1241.c | 210 ---------------------------- arch/mips/sibyte/swarm/setup.c | 49 +------- 4 files changed, 3 insertions(+), 492 deletions(-) delete mode 100644 arch/mips/sibyte/swarm/rtc_m41t81.c delete mode 100644 arch/mips/sibyte/swarm/rtc_xicor1241.c diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile index 7b45f19..4676af3 100644 --- a/arch/mips/sibyte/swarm/Makefile +++ b/arch/mips/sibyte/swarm/Makefile @@ -1,4 +1,3 @@ -obj-y := platform.o setup.o rtc_xicor1241.o \ - rtc_m41t81.o +obj-y := platform.o setup.o obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c deleted file mode 100644 index b732600..0000000 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (C) 2000, 2001 Broadcom Corporation - * - * Copyright (C) 2002 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - - -/* M41T81 definitions */ - -/* - * Register bits - */ - -#define M41T81REG_SC_ST 0x80 /* stop bit */ -#define M41T81REG_HR_CB 0x40 /* century bit */ -#define M41T81REG_HR_CEB 0x80 /* century enable bit */ -#define M41T81REG_CTL_S 0x20 /* sign bit */ -#define M41T81REG_CTL_FT 0x40 /* frequency test bit */ -#define M41T81REG_CTL_OUT 0x80 /* output level */ -#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */ -#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */ -#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */ -#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */ -#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */ -#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */ -#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */ -#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */ -#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */ -#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */ -#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */ -#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */ -#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */ -#define M41T81REG_AHR_HT 0x40 /* halt update bit */ -#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */ -#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */ -#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */ -#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */ -#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */ -#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */ -#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */ -#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */ - - -/* - * Register numbers - */ - -#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */ -#define M41T81REG_SC 0x01 /* seconds */ -#define M41T81REG_MN 0x02 /* minute */ -#define M41T81REG_HR 0x03 /* hour/century */ -#define M41T81REG_DY 0x04 /* day of week */ -#define M41T81REG_DT 0x05 /* date of month */ -#define M41T81REG_MO 0x06 /* month */ -#define M41T81REG_YR 0x07 /* year */ -#define M41T81REG_CTL 0x08 /* control */ -#define M41T81REG_WD 0x09 /* watchdog */ -#define M41T81REG_AMO 0x0A /* alarm: month */ -#define M41T81REG_ADT 0x0B /* alarm: date */ -#define M41T81REG_AHR 0x0C /* alarm: hour */ -#define M41T81REG_AMN 0x0D /* alarm: minute */ -#define M41T81REG_ASC 0x0E /* alarm: second */ -#define M41T81REG_FLG 0x0F /* flags */ -#define M41T81REG_SQW 0x13 /* square wave register */ - -#define M41T81_CCR_ADDRESS 0x68 - -#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) - -static int m41t81_read(uint8_t addr) -{ - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { - /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); - return -1; - } - - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); -} - -static int m41t81_write(uint8_t addr, int b) -{ - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); - __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { - /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); - return -1; - } - - /* read the same byte again to make sure it is written */ - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - return 0; -} - -int m41t81_set_time(unsigned long t) -{ - struct rtc_time tm; - unsigned long flags; - - /* Note we don't care about the century */ - rtc_time_to_tm(t, &tm); - - /* - * Note the write order matters as it ensures the correctness. - * When we write sec, 10th sec is clear. It is reasonable to - * believe we should finish writing min within a second. - */ - - spin_lock_irqsave(&rtc_lock, flags); - tm.tm_sec = bin2bcd(tm.tm_sec); - m41t81_write(M41T81REG_SC, tm.tm_sec); - - tm.tm_min = bin2bcd(tm.tm_min); - m41t81_write(M41T81REG_MN, tm.tm_min); - - tm.tm_hour = bin2bcd(tm.tm_hour); - tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0); - m41t81_write(M41T81REG_HR, tm.tm_hour); - - /* tm_wday starts from 0 to 6 */ - if (tm.tm_wday == 0) tm.tm_wday = 7; - tm.tm_wday = bin2bcd(tm.tm_wday); - m41t81_write(M41T81REG_DY, tm.tm_wday); - - tm.tm_mday = bin2bcd(tm.tm_mday); - m41t81_write(M41T81REG_DT, tm.tm_mday); - - /* tm_mon starts from 0, *ick* */ - tm.tm_mon ++; - tm.tm_mon = bin2bcd(tm.tm_mon); - m41t81_write(M41T81REG_MO, tm.tm_mon); - - /* we don't do century, everything is beyond 2000 */ - tm.tm_year %= 100; - tm.tm_year = bin2bcd(tm.tm_year); - m41t81_write(M41T81REG_YR, tm.tm_year); - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -unsigned long m41t81_get_time(void) -{ - unsigned int year, mon, day, hour, min, sec; - unsigned long flags; - - /* - * min is valid if two reads of sec are the same. - */ - for (;;) { - spin_lock_irqsave(&rtc_lock, flags); - sec = m41t81_read(M41T81REG_SC); - min = m41t81_read(M41T81REG_MN); - if (sec == m41t81_read(M41T81REG_SC)) break; - spin_unlock_irqrestore(&rtc_lock, flags); - } - hour = m41t81_read(M41T81REG_HR) & 0x3f; - day = m41t81_read(M41T81REG_DT); - mon = m41t81_read(M41T81REG_MO); - year = m41t81_read(M41T81REG_YR); - spin_unlock_irqrestore(&rtc_lock, flags); - - sec = bcd2bin(sec); - min = bcd2bin(min); - hour = bcd2bin(hour); - day = bcd2bin(day); - mon = bcd2bin(mon); - year = bcd2bin(year); - - year += 2000; - - return mktime(year, mon, day, hour, min, sec); -} - -int m41t81_probe(void) -{ - unsigned int tmp; - - /* enable chip if it is not enabled yet */ - tmp = m41t81_read(M41T81REG_SC); - m41t81_write(M41T81REG_SC, tmp & 0x7f); - - return (m41t81_read(M41T81REG_SC) != -1); -} diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c deleted file mode 100644 index 4438b21..0000000 --- a/arch/mips/sibyte/swarm/rtc_xicor1241.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (C) 2000, 2001 Broadcom Corporation - * - * Copyright (C) 2002 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - - -/* Xicor 1241 definitions */ - -/* - * Register bits - */ - -#define X1241REG_SR_BAT 0x80 /* currently on battery power */ -#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */ -#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */ -#define X1241REG_SR_RTCF 0x01 /* clock failed */ -#define X1241REG_BL_BP2 0x80 /* block protect 2 */ -#define X1241REG_BL_BP1 0x40 /* block protect 1 */ -#define X1241REG_BL_BP0 0x20 /* block protect 0 */ -#define X1241REG_BL_WD1 0x10 -#define X1241REG_BL_WD0 0x08 -#define X1241REG_HR_MIL 0x80 /* military time format */ - -/* - * Register numbers - */ - -#define X1241REG_BL 0x10 /* block protect bits */ -#define X1241REG_INT 0x11 /* */ -#define X1241REG_SC 0x30 /* Seconds */ -#define X1241REG_MN 0x31 /* Minutes */ -#define X1241REG_HR 0x32 /* Hours */ -#define X1241REG_DT 0x33 /* Day of month */ -#define X1241REG_MO 0x34 /* Month */ -#define X1241REG_YR 0x35 /* Year */ -#define X1241REG_DW 0x36 /* Day of Week */ -#define X1241REG_Y2K 0x37 /* Year 2K */ -#define X1241REG_SR 0x3F /* Status register */ - -#define X1241_CCR_ADDRESS 0x6F - -#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) - -static int xicor_read(uint8_t addr) -{ - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); - __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { - /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); - return -1; - } - - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); -} - -static int xicor_write(uint8_t addr, int b) -{ - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); - __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); - __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, - SMB_CSR(R_SMB_START)); - - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) - ; - - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { - /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); - return -1; - } else { - return 0; - } -} - -int xicor_set_time(unsigned long t) -{ - struct rtc_time tm; - int tmp; - unsigned long flags; - - rtc_time_to_tm(t, &tm); - tm.tm_year += 1900; - - spin_lock_irqsave(&rtc_lock, flags); - /* unlock writes to the CCR */ - xicor_write(X1241REG_SR, X1241REG_SR_WEL); - xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL); - - /* trivial ones */ - tm.tm_sec = bin2bcd(tm.tm_sec); - xicor_write(X1241REG_SC, tm.tm_sec); - - tm.tm_min = bin2bcd(tm.tm_min); - xicor_write(X1241REG_MN, tm.tm_min); - - tm.tm_mday = bin2bcd(tm.tm_mday); - xicor_write(X1241REG_DT, tm.tm_mday); - - /* tm_mon starts from 0, *ick* */ - tm.tm_mon ++; - tm.tm_mon = bin2bcd(tm.tm_mon); - xicor_write(X1241REG_MO, tm.tm_mon); - - /* year is split */ - tmp = tm.tm_year / 100; - tm.tm_year %= 100; - xicor_write(X1241REG_YR, tm.tm_year); - xicor_write(X1241REG_Y2K, tmp); - - /* hour is the most tricky one */ - tmp = xicor_read(X1241REG_HR); - if (tmp & X1241REG_HR_MIL) { - /* 24 hour format */ - tm.tm_hour = bin2bcd(tm.tm_hour); - tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f); - } else { - /* 12 hour format, with 0x2 for pm */ - tmp = tmp & ~0x3f; - if (tm.tm_hour >= 12) { - tmp |= 0x20; - tm.tm_hour -= 12; - } - tm.tm_hour = bin2bcd(tm.tm_hour); - tmp |= tm.tm_hour; - } - xicor_write(X1241REG_HR, tmp); - - xicor_write(X1241REG_SR, 0); - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -unsigned long xicor_get_time(void) -{ - unsigned int year, mon, day, hour, min, sec, y2k; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - sec = xicor_read(X1241REG_SC); - min = xicor_read(X1241REG_MN); - hour = xicor_read(X1241REG_HR); - - if (hour & X1241REG_HR_MIL) { - hour &= 0x3f; - } else { - if (hour & 0x20) - hour = (hour & 0xf) + 0x12; - } - - day = xicor_read(X1241REG_DT); - mon = xicor_read(X1241REG_MO); - year = xicor_read(X1241REG_YR); - y2k = xicor_read(X1241REG_Y2K); - spin_unlock_irqrestore(&rtc_lock, flags); - - sec = bcd2bin(sec); - min = bcd2bin(min); - hour = bcd2bin(hour); - day = bcd2bin(day); - mon = bcd2bin(mon); - year = bcd2bin(year); - y2k = bcd2bin(y2k); - - year += (y2k * 100); - - return mktime(year, mon, day, hour, min, sec); -} - -int xicor_probe(void) -{ - return (xicor_read(X1241REG_SC) != -1); -} diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 41707a2..5143f68 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -56,14 +56,6 @@ extern void sb1250_setup(void); #error invalid SiByte board configuration #endif -extern int xicor_probe(void); -extern int xicor_set_time(unsigned long); -extern unsigned long xicor_get_time(void); - -extern int m41t81_probe(void); -extern int m41t81_set_time(unsigned long); -extern unsigned long m41t81_get_time(void); - const char *get_system_type(void) { return "SiByte " SIBYTE_BOARD_NAME; @@ -79,49 +71,17 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup) return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); } -enum swarm_rtc_type { - RTC_NONE, - RTC_XICOR, - RTC_M41T81, -}; - -enum swarm_rtc_type swarm_rtc_type; - void read_persistent_clock(struct timespec *ts) { unsigned long sec; - - switch (swarm_rtc_type) { - case RTC_XICOR: - sec = xicor_get_time(); - break; - - case RTC_M41T81: - sec = m41t81_get_time(); - break; - - case RTC_NONE: - default: - sec = mktime(2000, 1, 1, 0, 0, 0); - break; - } + sec = mktime(2000, 1, 1, 0, 0, 0); ts->tv_sec = sec; ts->tv_nsec = 0; } int rtc_mips_set_time(unsigned long sec) { - switch (swarm_rtc_type) { - case RTC_XICOR: - return xicor_set_time(sec); - - case RTC_M41T81: - return m41t81_set_time(sec); - - case RTC_NONE: - default: - return -1; - } + return -1; } void __init plat_mem_setup(void) @@ -138,11 +98,6 @@ void __init plat_mem_setup(void) board_be_handler = swarm_be_handler; - if (xicor_probe()) - swarm_rtc_type = RTC_XICOR; - if (m41t81_probe()) - swarm_rtc_type = RTC_M41T81; - #ifdef CONFIG_VT screen_info = (struct screen_info) { .orig_video_page = 52, -- 1.7.3.2 From mattst88@gmail.com Mon Dec 6 05:17:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 05:17:10 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:37844 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491004Ab0LFEQ7 (ORCPT ); Mon, 6 Dec 2010 05:16:59 +0100 Received: by ywf7 with SMTP id 7so6213531ywf.36 for ; Sun, 05 Dec 2010 20:16:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=jW00FTB7KQRtoofGQ33837FzMXck2ZXCEtwLio5yQ+k=; b=pmQ5RlfsLaBW1NC6JO2KGCj0IDfRpz+20ly3qicKxswzFCoC1HuJHwlEHQZvbS5pS8 GEl3ufCSEKuZt+DNuLy/0v65hYVPgzvBT4mD2m2SCgLpkPwr2EA5eBxyhDYEMaJywDqV ccjCdB0W61avyu3FWZ+O7PWhnMcHlIsRtNVPw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=csKx51o4+IDLkNTd4RWz9KvCNanPnFrzMwsDTcz5t7qD6zrYOu2VFnkqFKrvRlM8Ii IzS32Znlv9veyCOjd/4070zi0+agmErqF1seGljrWcOW/O3y6d0sHSVrJjOzLI3dkoa6 +pkcXAEXN0fYWlI2PRbKR6Yx8gvRMJrrleEu4= Received: by 10.151.10.12 with SMTP id n12mr8433085ybi.220.1291609012839; Sun, 05 Dec 2010 20:16:52 -0800 (PST) Received: from localhost (cpe-065-190-173-137.nc.res.rr.com [65.190.173.137]) by mx.google.com with ESMTPS id v8sm3013239yba.2.2010.12.05.20.16.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 05 Dec 2010 20:16:52 -0800 (PST) From: Matt Turner To: Ralf Baechle Cc: Jean Delvare , linux-mips@linux-mips.org, "Maciej W. Rozycki" , Matt Turner Subject: [PATCH 3/3] MIPS: register hwmon on SWARM Date: Sun, 5 Dec 2010 23:16:54 -0500 Message-Id: <1291609014-17060-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.2.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28608 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 981 Lines: 36 From: Maciej W. Rozycki Tested-by: Matt Turner Signed-off-by: Matt Turner --- arch/mips/sibyte/swarm/swarm-i2c.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/mips/sibyte/swarm/swarm-i2c.c b/arch/mips/sibyte/swarm/swarm-i2c.c index 0625050..a6e417f 100644 --- a/arch/mips/sibyte/swarm/swarm-i2c.c +++ b/arch/mips/sibyte/swarm/swarm-i2c.c @@ -13,6 +13,11 @@ #include #include +static struct i2c_board_info swarm_i2c_info0[] __initdata = { + { + I2C_BOARD_INFO("lm90", 0x2a), + }, +}; static struct i2c_board_info swarm_i2c_info1[] __initdata = { { @@ -24,6 +29,8 @@ static int __init swarm_i2c_init(void) { int err; + err = i2c_register_board_info(0, swarm_i2c_info0, + ARRAY_SIZE(swarm_i2c_info0)); err = i2c_register_board_info(1, swarm_i2c_info1, ARRAY_SIZE(swarm_i2c_info1)); if (err < 0) -- 1.7.3.2 From mattst88@gmail.com Mon Dec 6 07:38:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 07:38:51 +0100 (CET) Received: from mail-gw0-f41.google.com ([74.125.83.41]:51686 "EHLO mail-gw0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491080Ab0LFGiq (ORCPT ); Mon, 6 Dec 2010 07:38:46 +0100 Received: by gwj22 with SMTP id 22so4071562gwj.28 for ; Sun, 05 Dec 2010 22:38:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=oqfhufoZ44rYAE7c4I8EjKtqJ282+eUpilaiFc/z6uw=; b=r49B/mUc1cc74Fj994nhIiMgGQkmHjv0ON0bv2KMLZMdyZ7zRGl/kF3zyFYZEzR/sS Yhz0VHRpkoQ3j+sZ+WaktfEn8csx4FJ7M94lxBf1U/ZBKcVnX/A9jicYevJ+js1o+qU1 x07pSCNinkV3BvvRrd1yEkv12+qK1GtQUMikM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=v3z/XSuRMiS4IKPie0gtAR0rPau6fVOhP3EuWrtFi2Nj74gCsckU3NDXogFzS16yO1 7naG6vukSahlJ/J5KvUKi9icii4oXmMXB5Y3Y2bOjv+ZxvMj3/bomRs0d8Cb0bzct6EE WP8P4fpRhT70nX0ja+SRuxKSXwDRWglYf039o= Received: by 10.151.41.17 with SMTP id t17mr8657175ybj.373.1291617518134; Sun, 05 Dec 2010 22:38:38 -0800 (PST) Received: from localhost (cpe-065-190-173-137.nc.res.rr.com [65.190.173.137]) by mx.google.com with ESMTPS id f2sm1425754ybh.5.2010.12.05.22.38.36 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 05 Dec 2010 22:38:37 -0800 (PST) From: Matt Turner To: Jean Delvare Cc: linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , "Maciej W. Rozycki" , Matt Turner Subject: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Date: Mon, 6 Dec 2010 01:38:14 -0500 Message-Id: <1291617494-18430-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.2.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28609 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 12650 Lines: 423 From: Maciej W. Rozycki This is a rewrite of large parts of the driver mainly so that it uses SMBus interrupts to offload the CPU from busy-waiting on status inputs. As a part of the overhaul of the init and exit calls, all accesses to the hardware got converted to use accessory functions via an ioremap() cookie. Minimally rebased by Matt Turner. Tested-by: Matt Turner Signed-off-by: Matt Turner --- This patch was originally sent in May 2008 [1], but appears to have been lost. I believe this patch depends on [PATCH 1/3] RTC: SMBus support for the M41T80, etc. driver Please review the change in return values (search for ENXIO). I wasn't entirely sure how this code should look. (The code the original patch was against just returned -1 on error. See 102b59c6d6d30fb6560177fd1ae8a34c4c163897). Please apply if acceptable. [1] http://lists.lm-sensors.org/pipermail/i2c/2008-May/003638.html drivers/i2c/busses/i2c-sibyte.c | 278 +++++++++++++++++++++++++++++---------- 1 files changed, 208 insertions(+), 70 deletions(-) diff --git a/drivers/i2c/busses/i2c-sibyte.c b/drivers/i2c/busses/i2c-sibyte.c index 0fe505d..283747c 100644 --- a/drivers/i2c/busses/i2c-sibyte.c +++ b/drivers/i2c/busses/i2c-sibyte.c @@ -2,6 +2,7 @@ * Copyright (C) 2004 Steven J. Hill * Copyright (C) 2001,2002,2003 Broadcom Corporation * Copyright (C) 1995-2000 Simon G. Vogl + * Copyright (C) 2008 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -18,104 +19,159 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include +#include #include #include #include #include +#include +#include +#include +#include #include +#include #include #include struct i2c_algo_sibyte_data { - void *data; /* private data */ - int bus; /* which bus */ - void *reg_base; /* CSR base */ + wait_queue_head_t wait; /* IRQ queue */ + void __iomem *csr; /* mapped CSR handle */ + phys_t base; /* physical CSR base */ + char *name; /* IRQ handler name */ + spinlock_t lock; /* atomiser */ + int irq; /* IRQ line */ + int status; /* IRQ status */ }; -/* ----- global defines ----------------------------------------------- */ -#define SMB_CSR(a,r) ((long)(a->reg_base + r)) +static irqreturn_t i2c_sibyte_interrupt(int irq, void *dev_id) +{ + struct i2c_adapter *i2c_adap = dev_id; + struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; + void __iomem *csr = adap->csr; + u8 status; + + /* + * Ugh, no way to detect the finish interrupt, + * but if busy it is obviously not one. + */ + status = __raw_readq(csr + R_SMB_STATUS); + if ((status & (M_SMB_ERROR | M_SMB_BUSY)) == M_SMB_BUSY) + return IRQ_NONE; -static int smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, - unsigned short flags, char read_write, - u8 command, int size, union i2c_smbus_data * data) + /* + * Clear the error interrupt (write 1 to clear); + * the finish interrupt was cleared by the read above. + */ + __raw_writeq(status, csr + R_SMB_STATUS); + + /* Post the status. */ + spin_lock_irq(&adap->lock); + adap->status = status & (M_SMB_ERROR_TYPE | M_SMB_ERROR | M_SMB_BUSY); + wake_up(&adap->wait); + spin_unlock_irq(&adap->lock); + + return IRQ_HANDLED; +} + +static s32 i2c_sibyte_smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, + unsigned short cflags, + char read_write, u8 command, int size, + union i2c_smbus_data *data) { struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; + void __iomem *csr = adap->csr; + unsigned long flags; int data_bytes = 0; int error; - while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) - ; + spin_lock_irqsave(&adap->lock, flags); + + if (adap->status < 0) { + error = -EIO; + goto out_unlock; + } switch (size) { case I2C_SMBUS_QUICK: - csr_out32((V_SMB_ADDR(addr) | - (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | - V_SMB_TT_QUICKCMD), SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_ADDR(addr) | + (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | + V_SMB_TT_QUICKCMD, + csr + R_SMB_START); break; case I2C_SMBUS_BYTE: if (read_write == I2C_SMBUS_READ) { - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE, + csr + R_SMB_START); data_bytes = 1; } else { - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE, + csr + R_SMB_START); } break; case I2C_SMBUS_BYTE_DATA: - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); if (read_write == I2C_SMBUS_READ) { - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE, + csr + R_SMB_START); data_bytes = 1; } else { - csr_out32(V_SMB_LB(data->byte), - SMB_CSR(adap, R_SMB_DATA)); - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_LB(data->byte), csr + R_SMB_DATA); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE, + csr + R_SMB_START); } break; case I2C_SMBUS_WORD_DATA: - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); if (read_write == I2C_SMBUS_READ) { - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE, + csr + R_SMB_START); data_bytes = 2; } else { - csr_out32(V_SMB_LB(data->word & 0xff), - SMB_CSR(adap, R_SMB_DATA)); - csr_out32(V_SMB_MB(data->word >> 8), - SMB_CSR(adap, R_SMB_DATA)); - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), - SMB_CSR(adap, R_SMB_START)); + __raw_writeq(V_SMB_LB(data->word & 0xff), + csr + R_SMB_DATA); + __raw_writeq(V_SMB_MB(data->word >> 8), + csr + R_SMB_DATA); + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE, + csr + R_SMB_START); } break; default: - return -EOPNOTSUPP; + error = -EOPNOTSUPP; + goto out_unlock; } + mmiowb(); + __raw_readq(csr + R_SMB_START); + adap->status = -1; + + spin_unlock_irqrestore(&adap->lock, flags); + + wait_event_timeout(adap->wait, (adap->status >= 0), HZ); - while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) - ; + spin_lock_irqsave(&adap->lock, flags); - error = csr_in32(SMB_CSR(adap, R_SMB_STATUS)); - if (error & M_SMB_ERROR) { - /* Clear error bit by writing a 1 */ - csr_out32(M_SMB_ERROR, SMB_CSR(adap, R_SMB_STATUS)); - return (error & M_SMB_ERROR_TYPE) ? -EIO : -ENXIO; + if (adap->status < 0 || (adap->status & (M_SMB_ERROR | M_SMB_BUSY))) { + error = -EIO; + goto out_unlock; } if (data_bytes == 1) - data->byte = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xff; + data->byte = __raw_readq(csr + R_SMB_DATA) & 0xff; if (data_bytes == 2) - data->word = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xffff; + data->word = __raw_readq(csr + R_SMB_DATA) & 0xffff; - return 0; + error = 0; + +out_unlock: + spin_unlock_irqrestore(&adap->lock, flags); + + return error; } -static u32 bit_func(struct i2c_adapter *adap) +static u32 i2c_sibyte_bit_func(struct i2c_adapter *adap) { return (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA); @@ -125,8 +181,8 @@ static u32 bit_func(struct i2c_adapter *adap) /* -----exported algorithm data: ------------------------------------- */ static const struct i2c_algorithm i2c_sibyte_algo = { - .smbus_xfer = smbus_xfer, - .functionality = bit_func, + .smbus_xfer = i2c_sibyte_smbus_xfer, + .functionality = i2c_sibyte_bit_func, }; /* @@ -135,37 +191,108 @@ static const struct i2c_algorithm i2c_sibyte_algo = { static int __init i2c_sibyte_add_bus(struct i2c_adapter *i2c_adap, int speed) { struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; + void __iomem *csr; + int err; - /* Register new adapter to i2c module... */ - i2c_adap->algo = &i2c_sibyte_algo; + adap->status = 0; + init_waitqueue_head(&adap->wait); + spin_lock_init(&adap->lock); + + csr = ioremap(adap->base, R_SMB_PEC + SMB_REGISTER_SPACING); + if (!csr) { + err = -ENOMEM; + goto out; + } + adap->csr = csr; /* Set the requested frequency. */ - csr_out32(speed, SMB_CSR(adap,R_SMB_FREQ)); - csr_out32(0, SMB_CSR(adap,R_SMB_CONTROL)); + __raw_writeq(speed, csr + R_SMB_FREQ); + + /* Clear any pending error interrupt. */ + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); + /* Disable interrupts. */ + __raw_writeq(0, csr + R_SMB_CONTROL); + mmiowb(); + __raw_readq(csr + R_SMB_CONTROL); + + err = request_irq(adap->irq, i2c_sibyte_interrupt, IRQF_SHARED, + adap->name, i2c_adap); + if (err < 0) + goto out_unmap; + + /* Enable finish and error interrupts. */ + __raw_writeq(M_SMB_FINISH_INTR | M_SMB_ERR_INTR, csr + R_SMB_CONTROL); + + /* Register new adapter to i2c module... */ + err = i2c_add_numbered_adapter(i2c_adap); + if (err < 0) + goto out_unirq; - return i2c_add_numbered_adapter(i2c_adap); + return 0; + +out_unirq: + /* Disable interrupts. */ + __raw_writeq(0, csr + R_SMB_CONTROL); + mmiowb(); + __raw_readq(csr + R_SMB_CONTROL); + + free_irq(adap->irq, i2c_adap); + + /* Clear any pending error interrupt. */ + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); +out_unmap: + iounmap(csr); +out: + return err; } +static void i2c_sibyte_remove_bus(struct i2c_adapter *i2c_adap) +{ + struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; + void __iomem *csr = adap->csr; + + i2c_del_adapter(i2c_adap); + + /* Disable interrupts. */ + __raw_writeq(0, csr + R_SMB_CONTROL); + mmiowb(); + __raw_readq(csr + R_SMB_CONTROL); + + free_irq(adap->irq, i2c_adap); + + /* Clear any pending error interrupt. */ + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); + + iounmap(csr); +} -static struct i2c_algo_sibyte_data sibyte_board_data[2] = { - { NULL, 0, (void *) (CKSEG1+A_SMB_BASE(0)) }, - { NULL, 1, (void *) (CKSEG1+A_SMB_BASE(1)) } +static struct i2c_algo_sibyte_data i2c_sibyte_board_data[2] = { + { + .name = "sb1250-smbus-0", + .base = A_SMB_0, + .irq = K_INT_SMB_0, + }, + { + .name = "sb1250-smbus-1", + .base = A_SMB_1, + .irq = K_INT_SMB_1, + } }; -static struct i2c_adapter sibyte_board_adapter[2] = { +static struct i2c_adapter i2c_sibyte_board_adapter[2] = { { .owner = THIS_MODULE, .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, - .algo = NULL, - .algo_data = &sibyte_board_data[0], + .algo = &i2c_sibyte_algo, + .algo_data = &i2c_sibyte_board_data[0], .nr = 0, .name = "SiByte SMBus 0", }, { .owner = THIS_MODULE, .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, - .algo = NULL, - .algo_data = &sibyte_board_data[1], + .algo = &i2c_sibyte_algo, + .algo_data = &i2c_sibyte_board_data[1], .nr = 1, .name = "SiByte SMBus 1", }, @@ -173,21 +300,32 @@ static struct i2c_adapter sibyte_board_adapter[2] = { static int __init i2c_sibyte_init(void) { + int err; + pr_info("i2c-sibyte: i2c SMBus adapter module for SiByte board\n"); - if (i2c_sibyte_add_bus(&sibyte_board_adapter[0], K_SMB_FREQ_100KHZ) < 0) - return -ENODEV; - if (i2c_sibyte_add_bus(&sibyte_board_adapter[1], - K_SMB_FREQ_400KHZ) < 0) { - i2c_del_adapter(&sibyte_board_adapter[0]); - return -ENODEV; - } + + err = i2c_sibyte_add_bus(&i2c_sibyte_board_adapter[0], + K_SMB_FREQ_100KHZ); + if (err < 0) + goto out; + + err = i2c_sibyte_add_bus(&i2c_sibyte_board_adapter[1], + K_SMB_FREQ_400KHZ); + if (err < 0) + goto out_remove; + return 0; + +out_remove: + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[0]); +out: + return err; } static void __exit i2c_sibyte_exit(void) { - i2c_del_adapter(&sibyte_board_adapter[0]); - i2c_del_adapter(&sibyte_board_adapter[1]); + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[1]); + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[0]); } module_init(i2c_sibyte_init); -- 1.7.2.2 From anoop.pa@gmail.com Mon Dec 6 09:19:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 09:19:41 +0100 (CET) Received: from mail-gw0-f41.google.com ([74.125.83.41]:56271 "EHLO mail-gw0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491054Ab0LFITi (ORCPT ); Mon, 6 Dec 2010 09:19:38 +0100 Received: by gwj22 with SMTP id 22so4107178gwj.28 for ; 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Mon, 06 Dec 2010 00:19:30 -0800 (PST) Subject: [PATCH] Introduce mips_late_time_init From: Anoop P A To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Date: Mon, 06 Dec 2010 13:53:32 +0530 Message-ID: <1291623812.31822.6.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28610 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 641 Lines: 29 This patch moves plat_time_init and clocksoure init funtion calls to late_time_init. Signed-off-by: Anoop P A --- diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index fb74974..dbd1ac5 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -117,10 +117,16 @@ static __init int cpu_has_mfc0_count_bug(void) return 0; } -void __init time_init(void) +void __init mips_late_time_init(void) { plat_time_init(); if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) init_mips_clocksource(); } + + +void __init time_init(void) +{ + late_time_init = mips_late_time_init; +} From groeck@ericsson.com Mon Dec 6 15:59:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 15:59:56 +0100 (CET) Received: from imr4.ericy.com ([198.24.6.8]:53433 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491986Ab0LFO7w (ORCPT ); Mon, 6 Dec 2010 15:59:52 +0100 Received: from eusaamw0707.eamcs.ericsson.se ([147.117.20.32]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id oB6FSfXs007406; Mon, 6 Dec 2010 09:28:47 -0600 Received: from localhost (147.117.20.213) by eusaamw0707.eamcs.ericsson.se (147.117.20.92) with Microsoft SMTP Server id 8.2.234.1; Mon, 6 Dec 2010 09:59:23 -0500 Date: Mon, 6 Dec 2010 06:59:22 -0800 From: Guenter Roeck To: Matt Turner CC: Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle , "Maciej W. Rozycki" Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20101206145922.GA17758@ericsson.com> References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1291617494-18430-1-git-send-email-mattst88@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28612 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Content-Length: 17276 Lines: 434 On Mon, Dec 06, 2010 at 01:38:14AM -0500, Matt Turner wrote: > From: Maciej W. Rozycki > > This is a rewrite of large parts of the driver mainly so that it uses > SMBus interrupts to offload the CPU from busy-waiting on status inputs. > As a part of the overhaul of the init and exit calls, all accesses to the > hardware got converted to use accessory functions via an ioremap() cookie. > > Minimally rebased by Matt Turner. > > Tested-by: Matt Turner > Signed-off-by: Matt Turner > --- > This patch was originally sent in May 2008 [1], but appears to have been lost. > > I believe this patch depends on > [PATCH 1/3] RTC: SMBus support for the M41T80, etc. driver > > Please review the change in return values (search for ENXIO). I wasn't entirely > sure how this code should look. (The code the original patch was against just > returned -1 on error. See 102b59c6d6d30fb6560177fd1ae8a34c4c163897). Please > apply if acceptable. > > [1] http://lists.lm-sensors.org/pipermail/i2c/2008-May/003638.html > > drivers/i2c/busses/i2c-sibyte.c | 278 +++++++++++++++++++++++++++++---------- > 1 files changed, 208 insertions(+), 70 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-sibyte.c b/drivers/i2c/busses/i2c-sibyte.c > index 0fe505d..283747c 100644 > --- a/drivers/i2c/busses/i2c-sibyte.c > +++ b/drivers/i2c/busses/i2c-sibyte.c > @@ -2,6 +2,7 @@ > * Copyright (C) 2004 Steven J. Hill > * Copyright (C) 2001,2002,2003 Broadcom Corporation > * Copyright (C) 1995-2000 Simon G. Vogl > + * Copyright (C) 2008 Maciej W. Rozycki > * > * This program is free software; you can redistribute it and/or > * modify it under the terms of the GNU General Public License > @@ -18,104 +19,159 @@ > * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. > */ > > +#include > +#include > #include > #include > #include > #include > +#include > +#include > +#include > +#include > #include > +#include > #include > #include > > > struct i2c_algo_sibyte_data { > - void *data; /* private data */ > - int bus; /* which bus */ > - void *reg_base; /* CSR base */ > + wait_queue_head_t wait; /* IRQ queue */ > + void __iomem *csr; /* mapped CSR handle */ > + phys_t base; /* physical CSR base */ > + char *name; /* IRQ handler name */ > + spinlock_t lock; /* atomiser */ > + int irq; /* IRQ line */ > + int status; /* IRQ status */ > }; > > -/* ----- global defines ----------------------------------------------- */ > -#define SMB_CSR(a,r) ((long)(a->reg_base + r)) > > +static irqreturn_t i2c_sibyte_interrupt(int irq, void *dev_id) > +{ > + struct i2c_adapter *i2c_adap = dev_id; > + struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; > + void __iomem *csr = adap->csr; > + u8 status; > + > + /* > + * Ugh, no way to detect the finish interrupt, > + * but if busy it is obviously not one. > + */ > + status = __raw_readq(csr + R_SMB_STATUS); > + if ((status & (M_SMB_ERROR | M_SMB_BUSY)) == M_SMB_BUSY) > + return IRQ_NONE; > > -static int smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, > - unsigned short flags, char read_write, > - u8 command, int size, union i2c_smbus_data * data) > + /* > + * Clear the error interrupt (write 1 to clear); > + * the finish interrupt was cleared by the read above. > + */ > + __raw_writeq(status, csr + R_SMB_STATUS); > + > + /* Post the status. */ > + spin_lock_irq(&adap->lock); > + adap->status = status & (M_SMB_ERROR_TYPE | M_SMB_ERROR | M_SMB_BUSY); > + wake_up(&adap->wait); > + spin_unlock_irq(&adap->lock); > + > + return IRQ_HANDLED; > +} > + > +static s32 i2c_sibyte_smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr, > + unsigned short cflags, > + char read_write, u8 command, int size, > + union i2c_smbus_data *data) > { > struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; > + void __iomem *csr = adap->csr; > + unsigned long flags; > int data_bytes = 0; > int error; > > - while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) > - ; > + spin_lock_irqsave(&adap->lock, flags); > + > + if (adap->status < 0) { > + error = -EIO; > + goto out_unlock; > + } If a previous operation timed out, subsequent operations will fail forever. Is this a good idea ? Maybe it is - just asking. > > switch (size) { > case I2C_SMBUS_QUICK: > - csr_out32((V_SMB_ADDR(addr) | > - (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | > - V_SMB_TT_QUICKCMD), SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_ADDR(addr) | > + (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) | > + V_SMB_TT_QUICKCMD, > + csr + R_SMB_START); > break; > case I2C_SMBUS_BYTE: > if (read_write == I2C_SMBUS_READ) { > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE, > + csr + R_SMB_START); > data_bytes = 1; > } else { > - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE, > + csr + R_SMB_START); > } > break; > case I2C_SMBUS_BYTE_DATA: > - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); > + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); > if (read_write == I2C_SMBUS_READ) { > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE, > + csr + R_SMB_START); > data_bytes = 1; > } else { > - csr_out32(V_SMB_LB(data->byte), > - SMB_CSR(adap, R_SMB_DATA)); > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_LB(data->byte), csr + R_SMB_DATA); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE, > + csr + R_SMB_START); > } > break; > case I2C_SMBUS_WORD_DATA: > - csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD)); > + __raw_writeq(V_SMB_CMD(command), csr + R_SMB_CMD); > if (read_write == I2C_SMBUS_READ) { > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE, > + csr + R_SMB_START); > data_bytes = 2; > } else { > - csr_out32(V_SMB_LB(data->word & 0xff), > - SMB_CSR(adap, R_SMB_DATA)); > - csr_out32(V_SMB_MB(data->word >> 8), > - SMB_CSR(adap, R_SMB_DATA)); > - csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE), > - SMB_CSR(adap, R_SMB_START)); > + __raw_writeq(V_SMB_LB(data->word & 0xff), > + csr + R_SMB_DATA); > + __raw_writeq(V_SMB_MB(data->word >> 8), > + csr + R_SMB_DATA); > + __raw_writeq(V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE, > + csr + R_SMB_START); > } > break; > default: > - return -EOPNOTSUPP; > + error = -EOPNOTSUPP; > + goto out_unlock; > } > + mmiowb(); > + __raw_readq(csr + R_SMB_START); > + adap->status = -1; > + > + spin_unlock_irqrestore(&adap->lock, flags); > + > + wait_event_timeout(adap->wait, (adap->status >= 0), HZ); > > - while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY) > - ; > + spin_lock_irqsave(&adap->lock, flags); > > - error = csr_in32(SMB_CSR(adap, R_SMB_STATUS)); > - if (error & M_SMB_ERROR) { > - /* Clear error bit by writing a 1 */ > - csr_out32(M_SMB_ERROR, SMB_CSR(adap, R_SMB_STATUS)); > - return (error & M_SMB_ERROR_TYPE) ? -EIO : -ENXIO; > + if (adap->status < 0 || (adap->status & (M_SMB_ERROR | M_SMB_BUSY))) { > + error = -EIO; > + goto out_unlock; > } The idea was to return -ENXIO if there was no ACK from a device (per Documentation/i2c/fault-codes). With your change, this distinction gets lost. I think you should retain the original semantics, ie return -ENXIO if status > 0 && ((status & (M_SMB_ERROR | M_SMB_ERROR_TYPE) == M_SMB_ERROR). > > if (data_bytes == 1) > - data->byte = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xff; > + data->byte = __raw_readq(csr + R_SMB_DATA) & 0xff; > if (data_bytes == 2) > - data->word = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xffff; > + data->word = __raw_readq(csr + R_SMB_DATA) & 0xffff; > > - return 0; > + error = 0; > + > +out_unlock: > + spin_unlock_irqrestore(&adap->lock, flags); > + > + return error; > } > > -static u32 bit_func(struct i2c_adapter *adap) > +static u32 i2c_sibyte_bit_func(struct i2c_adapter *adap) > { > return (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | > I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA); > @@ -125,8 +181,8 @@ static u32 bit_func(struct i2c_adapter *adap) > /* -----exported algorithm data: ------------------------------------- */ > > static const struct i2c_algorithm i2c_sibyte_algo = { > - .smbus_xfer = smbus_xfer, > - .functionality = bit_func, > + .smbus_xfer = i2c_sibyte_smbus_xfer, > + .functionality = i2c_sibyte_bit_func, > }; > > /* > @@ -135,37 +191,108 @@ static const struct i2c_algorithm i2c_sibyte_algo = { > static int __init i2c_sibyte_add_bus(struct i2c_adapter *i2c_adap, int speed) > { > struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; > + void __iomem *csr; > + int err; > > - /* Register new adapter to i2c module... */ > - i2c_adap->algo = &i2c_sibyte_algo; > + adap->status = 0; > + init_waitqueue_head(&adap->wait); > + spin_lock_init(&adap->lock); > + > + csr = ioremap(adap->base, R_SMB_PEC + SMB_REGISTER_SPACING); > + if (!csr) { > + err = -ENOMEM; > + goto out; > + } > + adap->csr = csr; > > /* Set the requested frequency. */ > - csr_out32(speed, SMB_CSR(adap,R_SMB_FREQ)); > - csr_out32(0, SMB_CSR(adap,R_SMB_CONTROL)); > + __raw_writeq(speed, csr + R_SMB_FREQ); > + > + /* Clear any pending error interrupt. */ > + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); > + /* Disable interrupts. */ > + __raw_writeq(0, csr + R_SMB_CONTROL); > + mmiowb(); > + __raw_readq(csr + R_SMB_CONTROL); > + > + err = request_irq(adap->irq, i2c_sibyte_interrupt, IRQF_SHARED, > + adap->name, i2c_adap); > + if (err < 0) > + goto out_unmap; > + > + /* Enable finish and error interrupts. */ > + __raw_writeq(M_SMB_FINISH_INTR | M_SMB_ERR_INTR, csr + R_SMB_CONTROL); > + > + /* Register new adapter to i2c module... */ > + err = i2c_add_numbered_adapter(i2c_adap); > + if (err < 0) > + goto out_unirq; > > - return i2c_add_numbered_adapter(i2c_adap); > + return 0; > + > +out_unirq: > + /* Disable interrupts. */ > + __raw_writeq(0, csr + R_SMB_CONTROL); > + mmiowb(); > + __raw_readq(csr + R_SMB_CONTROL); > + > + free_irq(adap->irq, i2c_adap); > + > + /* Clear any pending error interrupt. */ > + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); > +out_unmap: > + iounmap(csr); > +out: > + return err; > } > > +static void i2c_sibyte_remove_bus(struct i2c_adapter *i2c_adap) > +{ > + struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data; > + void __iomem *csr = adap->csr; > + > + i2c_del_adapter(i2c_adap); > + > + /* Disable interrupts. */ > + __raw_writeq(0, csr + R_SMB_CONTROL); > + mmiowb(); > + __raw_readq(csr + R_SMB_CONTROL); > + > + free_irq(adap->irq, i2c_adap); > + > + /* Clear any pending error interrupt. */ > + __raw_writeq(__raw_readq(csr + R_SMB_STATUS), csr + R_SMB_STATUS); > + > + iounmap(csr); > +} > > -static struct i2c_algo_sibyte_data sibyte_board_data[2] = { > - { NULL, 0, (void *) (CKSEG1+A_SMB_BASE(0)) }, > - { NULL, 1, (void *) (CKSEG1+A_SMB_BASE(1)) } > +static struct i2c_algo_sibyte_data i2c_sibyte_board_data[2] = { > + { > + .name = "sb1250-smbus-0", > + .base = A_SMB_0, > + .irq = K_INT_SMB_0, > + }, > + { > + .name = "sb1250-smbus-1", > + .base = A_SMB_1, > + .irq = K_INT_SMB_1, > + } > }; > > -static struct i2c_adapter sibyte_board_adapter[2] = { > +static struct i2c_adapter i2c_sibyte_board_adapter[2] = { > { > .owner = THIS_MODULE, > .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, > - .algo = NULL, > - .algo_data = &sibyte_board_data[0], > + .algo = &i2c_sibyte_algo, > + .algo_data = &i2c_sibyte_board_data[0], > .nr = 0, > .name = "SiByte SMBus 0", > }, > { > .owner = THIS_MODULE, > .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, > - .algo = NULL, > - .algo_data = &sibyte_board_data[1], > + .algo = &i2c_sibyte_algo, > + .algo_data = &i2c_sibyte_board_data[1], > .nr = 1, > .name = "SiByte SMBus 1", > }, > @@ -173,21 +300,32 @@ static struct i2c_adapter sibyte_board_adapter[2] = { > > static int __init i2c_sibyte_init(void) > { > + int err; > + > pr_info("i2c-sibyte: i2c SMBus adapter module for SiByte board\n"); > - if (i2c_sibyte_add_bus(&sibyte_board_adapter[0], K_SMB_FREQ_100KHZ) < 0) > - return -ENODEV; > - if (i2c_sibyte_add_bus(&sibyte_board_adapter[1], > - K_SMB_FREQ_400KHZ) < 0) { > - i2c_del_adapter(&sibyte_board_adapter[0]); > - return -ENODEV; > - } > + > + err = i2c_sibyte_add_bus(&i2c_sibyte_board_adapter[0], > + K_SMB_FREQ_100KHZ); > + if (err < 0) > + goto out; > + > + err = i2c_sibyte_add_bus(&i2c_sibyte_board_adapter[1], > + K_SMB_FREQ_400KHZ); > + if (err < 0) > + goto out_remove; > + > return 0; > + > +out_remove: > + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[0]); > +out: > + return err; > } > > static void __exit i2c_sibyte_exit(void) > { > - i2c_del_adapter(&sibyte_board_adapter[0]); > - i2c_del_adapter(&sibyte_board_adapter[1]); > + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[1]); > + i2c_sibyte_remove_bus(&i2c_sibyte_board_adapter[0]); > } > > module_init(i2c_sibyte_init); > -- > 1.7.2.2 > > From groeck@ericsson.com Mon Dec 6 18:31:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 18:31:16 +0100 (CET) Received: from imr4.ericy.com ([198.24.6.8]:36566 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492036Ab0LFRbH (ORCPT ); Mon, 6 Dec 2010 18:31:07 +0100 Received: from eusaamw0706.eamcs.ericsson.se ([147.117.20.31]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id oB6I02vJ007644; Mon, 6 Dec 2010 12:00:06 -0600 Received: from localhost (147.117.20.213) by eusaamw0706.eamcs.ericsson.se (147.117.20.91) with Microsoft SMTP Server id 8.2.234.1; Mon, 6 Dec 2010 12:30:40 -0500 Date: Mon, 6 Dec 2010 09:30:40 -0800 From: Guenter Roeck To: Matt Turner CC: Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle , "Maciej W. Rozycki" Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20101206173040.GA18372@ericsson.com> References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1291617494-18430-1-git-send-email-mattst88@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28613 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Content-Length: 804 Lines: 21 On Mon, Dec 06, 2010 at 01:38:14AM -0500, Matt Turner wrote: > From: Maciej W. Rozycki > > This is a rewrite of large parts of the driver mainly so that it uses > SMBus interrupts to offload the CPU from busy-waiting on status inputs. > As a part of the overhaul of the init and exit calls, all accesses to the > hardware got converted to use accessory functions via an ioremap() cookie. > > Minimally rebased by Matt Turner. > > Tested-by: Matt Turner > Signed-off-by: Matt Turner I applied the patch to my 1480 tree. Unfortunately, it doesn't work with my system. As far as I can see, the driver does not get any interrupts. My tree is 2.6.32, though. Do you know if I might be missing some other relevant patch ? Thanks, Guenter From mattst88@gmail.com Mon Dec 6 18:40:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 18:40:46 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:51060 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492036Ab0LFRkm (ORCPT ); Mon, 6 Dec 2010 18:40:42 +0100 Received: by gyg4 with SMTP id 4so6627110gyg.36 for ; Mon, 06 Dec 2010 09:40:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:in-reply-to :references:from:date:message-id:subject:to:cc:content-type; bh=ARi+Mjrz5SkGRaXaYykSUHjna0yv0dvq51uk+OOXUYw=; b=o0m0sTXfV+XXxEZzORIP2gnTf1jZ1xX1MIaZ0vJWJGgQnaiL8ywur+LkJy+EG1ys60 nDCefFBfniIJOw+QCpb3fw5cvaS8Qd+Sd8FJ0bgPnXTUUXiiQZTv3mtI91whsDlMA3mb N/A1b+aY3I2GgFo5Q2BqbMnwHHuadC2UQ3uCk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; b=foJ7ccsbHZOj0X/f8kkZB5eHbMH3WaW7WeHvYXVuqZ5vAf58qxwDc0sTZ2UQc4pAYx 5+xln85sX+ULZv7rAhXiVkctkGJdUBWH8zY3hi8O4h0D0fySqeMBRjU3Z7Zj46WWIJcg 3ILlE4EZqTswWQ1GzZXoWW5SP5DWZCXGfqNqU= Received: by 10.223.102.79 with SMTP id f15mr184964fao.134.1291657235296; Mon, 06 Dec 2010 09:40:35 -0800 (PST) MIME-Version: 1.0 Received: by 10.204.46.199 with HTTP; Mon, 6 Dec 2010 09:40:15 -0800 (PST) In-Reply-To: <20101206173040.GA18372@ericsson.com> References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> From: Matt Turner Date: Mon, 6 Dec 2010 17:40:15 +0000 Message-ID: Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts To: Guenter Roeck Cc: Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle , "Maciej W. Rozycki" Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28614 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1059 Lines: 30 On Mon, Dec 6, 2010 at 5:30 PM, Guenter Roeck wrote: > On Mon, Dec 06, 2010 at 01:38:14AM -0500, Matt Turner wrote: >> From: Maciej W. Rozycki >> >> This is a rewrite of large parts of the driver mainly so that it uses >> SMBus interrupts to offload the CPU from busy-waiting on status inputs. >> As a part of the overhaul of the init and exit calls, all accesses to the >> hardware got converted to use accessory functions via an ioremap() cookie. >> >> Minimally rebased by Matt Turner. >> >> Tested-by: Matt Turner >> Signed-off-by: Matt Turner > > > I applied the patch to my 1480 tree. Unfortunately, it doesn't work with my system. > As far as I can see, the driver does not get any interrupts. > > My tree is 2.6.32, though. Do you know if I might be missing some other relevant patch ? > > Thanks, > Guenter I think this patch depends on http://www.linux-mips.org/archives/linux-mips/2010-12/msg00030.html Thanks for testing and the suggestions! :) Matt From David.Daney@caviumnetworks.com Mon Dec 6 18:42:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 18:42:52 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8764 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492046Ab0LFRms (ORCPT ); Mon, 6 Dec 2010 18:42:48 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 06 Dec 2010 09:43:28 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 6 Dec 2010 09:43:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 6 Dec 2010 09:43:52 -0800 Message-ID: <4CFD2095.9040404@caviumnetworks.com> Date: Mon, 06 Dec 2010 09:42:45 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Anoop P A CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] Introduce mips_late_time_init References: <1291623812.31822.6.camel@paanoop1-desktop> In-Reply-To: <1291623812.31822.6.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 Dec 2010 17:43:52.0866 (UTC) FILETIME=[25D1A020:01CB956D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28615 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1111 Lines: 45 On 12/06/2010 12:23 AM, Anoop P A wrote: > This patch moves plat_time_init and clocksoure init funtion calls to > late_time_init. > Why would you want to do this? The current code works perfectly, so I see no reason to change it. David Daney > Signed-off-by: Anoop P A > --- > diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c > index fb74974..dbd1ac5 100644 > --- a/arch/mips/kernel/time.c > +++ b/arch/mips/kernel/time.c > @@ -117,10 +117,16 @@ static __init int cpu_has_mfc0_count_bug(void) > return 0; > } > > -void __init time_init(void) > +void __init mips_late_time_init(void) > { > plat_time_init(); > > if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) > init_mips_clocksource(); > } > + > + > +void __init time_init(void) > +{ > + late_time_init = mips_late_time_init; > +} > > > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ > From macro@linux-mips.org Mon Dec 6 18:56:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 18:56:53 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40989 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492046Ab0LFR4u (ORCPT ); Mon, 6 Dec 2010 18:56:50 +0100 Date: Mon, 6 Dec 2010 17:56:50 +0000 (GMT) From: "Maciej W. Rozycki" To: Guenter Roeck cc: Matt Turner , Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts In-Reply-To: <20101206173040.GA18372@ericsson.com> Message-ID: References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28616 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 2317 Lines: 47 On Mon, 6 Dec 2010, Guenter Roeck wrote: > > From: Maciej W. Rozycki > > > > This is a rewrite of large parts of the driver mainly so that it uses > > SMBus interrupts to offload the CPU from busy-waiting on status inputs. > > As a part of the overhaul of the init and exit calls, all accesses to the > > hardware got converted to use accessory functions via an ioremap() cookie. > > > > Minimally rebased by Matt Turner. > > > > Tested-by: Matt Turner > > Signed-off-by: Matt Turner > > I applied the patch to my 1480 tree. Unfortunately, it doesn't work with > my system. As far as I can see, the driver does not get any interrupts. > > My tree is 2.6.32, though. Do you know if I might be missing some other > relevant patch ? As the original author I apologise for the lack of response about these changes -- I've had a really, really hectic time recently and will continue to suffer from that for several weeks yet at the very least. As to the patches -- these I submitted originally back in 2008 as a series. There may have been more than one series actually, but I can't recall the details offhand. There were some discussions and concerns about some of the patches which in the end I did not fully address owing to various disruptions and the lack of time, which is why they did not go in. I do remember some bits about interrupt handling as the original implementation of the I2C host interface used polling only and I saw it as a gross inefficiency. Obviously with all the bits in place they used to work at least for me. Matt, thanks for keeping your eye on these bits and reviving them; I've meant to do so for a long time now, but never came to it. Please note however, as I'm the original author, my original Signed-off-by markups continue to apply and you should be quoting them with the submissions. You should only add your own Signed-off-by annotation if you made any changes and it would make sense to state what these changes were. I'll do my best to provide some aid with these bits, but won't be able to do anything but plain code review up till January at the very least, and then maybe not even that. My SWARM board has been stuck with 2.6.27-ish for a long while now. Sorry. Maciej From groeck@ericsson.com Mon Dec 6 19:02:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 19:02:41 +0100 (CET) Received: from imr4.ericy.com ([198.24.6.8]:49412 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492054Ab0LFSCg (ORCPT ); Mon, 6 Dec 2010 19:02:36 +0100 Received: from eusaamw0706.eamcs.ericsson.se ([147.117.20.31]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id oB6IVFvG014290; Mon, 6 Dec 2010 12:31:38 -0600 Received: from localhost (147.117.20.213) by eusaamw0706.eamcs.ericsson.se (147.117.20.91) with Microsoft SMTP Server id 8.2.234.1; Mon, 6 Dec 2010 13:02:03 -0500 Date: Mon, 6 Dec 2010 10:02:03 -0800 From: Guenter Roeck To: Matt Turner CC: Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle , "Maciej W. Rozycki" Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20101206180203.GA18478@ericsson.com> References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28617 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Content-Length: 1458 Lines: 36 On Mon, Dec 06, 2010 at 12:40:15PM -0500, Matt Turner wrote: > On Mon, Dec 6, 2010 at 5:30 PM, Guenter Roeck > wrote: > > On Mon, Dec 06, 2010 at 01:38:14AM -0500, Matt Turner wrote: > >> From: Maciej W. Rozycki > >> > >> This is a rewrite of large parts of the driver mainly so that it uses > >> SMBus interrupts to offload the CPU from busy-waiting on status inputs. > >> As a part of the overhaul of the init and exit calls, all accesses to the > >> hardware got converted to use accessory functions via an ioremap() cookie. > >> > >> Minimally rebased by Matt Turner. > >> > >> Tested-by: Matt Turner > >> Signed-off-by: Matt Turner > > > > > > I applied the patch to my 1480 tree. Unfortunately, it doesn't work with my system. > > As far as I can see, the driver does not get any interrupts. > > > > My tree is 2.6.32, though. Do you know if I might be missing some other relevant patch ? > > > > Thanks, > > Guenter > > I think this patch depends on > http://www.linux-mips.org/archives/linux-mips/2010-12/msg00030.html > I did apply the second patch as well, since you had mentioned it in your patch. That did not help, though. Frankly, I don't see the dependency in the first place - the other patch only affects drivers/rtc/rtc-m41t80.c, and I would hope that SMBus support does not depend on an rtc driver. Am I missing something ? Thanks, Guenter From mattst88@gmail.com Mon Dec 6 19:02:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 19:03:04 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:36863 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492067Ab0LFSCq convert rfc822-to-8bit (ORCPT ); Mon, 6 Dec 2010 19:02:46 +0100 Received: by eyd9 with SMTP id 9so6345914eyd.36 for ; Mon, 06 Dec 2010 10:02:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:in-reply-to :references:from:date:message-id:subject:to:cc:content-type :content-transfer-encoding; bh=MuzeGz/Z/sEPplzDUDAq/Cl9br7ToDSEt8rGFouJ++E=; b=J38QA814CF1lP1XRYKd9P+tj0T8CJWgy8p7y88QdhUcfgT/MV/2vzqfYGI/hgUPS/G +MYksTGj5MSpIPctCerfbp9ND8YBsDLZmuMulB0kNBtqH3rEqk+F3zQSkLKDFCHo1Ryh HHpSCorTqtPgCrfeGVGP+Uz77yM95Tjgk5JcU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=vv9qMyXplom8SFjAO3xL4vSwmMJIJqi2v3GkKhnq9z1QeP4vT/K2gQ2X+ReuiNdioa Vi5n8fC7Za2p2kKVfjeV+kiTdf/DLEbLEPRBN0MCd2BmImNdyuEORryA2qWC6WXMe1Yw dHxu9brskRQLPgnQtDW14pJNGIXAmNgp2DCvE= Received: by 10.213.23.10 with SMTP id p10mr852913ebb.0.1291658565465; Mon, 06 Dec 2010 10:02:45 -0800 (PST) MIME-Version: 1.0 Received: by 10.204.46.199 with HTTP; Mon, 6 Dec 2010 10:02:25 -0800 (PST) In-Reply-To: References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> From: Matt Turner Date: Mon, 6 Dec 2010 18:02:25 +0000 Message-ID: Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts To: "Maciej W. Rozycki" Cc: Guenter Roeck , Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28618 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 790 Lines: 14 On Mon, Dec 6, 2010 at 5:56 PM, Maciej W. Rozycki wrote: >  Matt, thanks for keeping your eye on these bits and reviving them; I've > meant to do so for a long time now, but never came to it.  Please note > however, as I'm the original author, my original Signed-off-by markups > continue to apply and you should be quoting them with the submissions. > You should only add your own Signed-off-by annotation if you made any > changes and it would make sense to state what these changes were. Sure thing. Will fix. For patches 2 and 3 of the other series, I don't think I was ever 100% sure that you were the author, since they were living on OpenWRT.org and I couldn't find them in any mailing list archives. Can you confirm that these 4 patches are all yours? Matt From mattst88@gmail.com Mon Dec 6 19:04:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Dec 2010 19:04:52 +0100 (CET) Received: from mail-ew0-f54.google.com ([209.85.215.54]:45558 "EHLO mail-ew0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492046Ab0LFSEs (ORCPT ); Mon, 6 Dec 2010 19:04:48 +0100 Received: by ewy24 with SMTP id 24so34141551ewy.27 for ; Mon, 06 Dec 2010 10:04:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:in-reply-to :references:from:date:message-id:subject:to:cc:content-type; bh=+B8/H8wueQ5fv+MfuBPypWCySaF9lKGpOCMlm27GRXQ=; b=K/5idjwPMd+a7HiR6w92YLZbAlq67eS5OwXU0OUmg5suB8LPtl3Hixwcd+g5TGECJh gI3sg6FsUY6iF7fVJE4Jql4o5Z6AOVbmE6e12Cf/qdyH9aERwW+muB/zHCbHtK0PdubP r7Fz+lt5F4xHn5TA2j9PU8IPiqFYw5cRJguao= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; b=U+oDFhpGW5g8ZBIIi0SDEIO+7DqHsYORINchKCRvFVooTYoEJ9nbC/EdfEoy89FP9m UYJP0T+MI/Madudkm+EBiy+Pn/49Vph+YSFrocr1d37hG1Yv8fB3QdTrlrQgJvuyoTa2 M4Z5wIRYJvi/Li/E3lThSU22Z4yOn/+PTolio= Received: by 10.213.33.133 with SMTP id h5mr2617770ebd.87.1291658687211; Mon, 06 Dec 2010 10:04:47 -0800 (PST) MIME-Version: 1.0 Received: by 10.204.46.199 with HTTP; Mon, 6 Dec 2010 10:04:26 -0800 (PST) In-Reply-To: <20101206180203.GA18478@ericsson.com> References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> <20101206180203.GA18478@ericsson.com> From: Matt Turner Date: Mon, 6 Dec 2010 18:04:26 +0000 Message-ID: Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts To: Guenter Roeck Cc: Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle , "Maciej W. Rozycki" Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28619 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1785 Lines: 43 On Mon, Dec 6, 2010 at 6:02 PM, Guenter Roeck wrote: > On Mon, Dec 06, 2010 at 12:40:15PM -0500, Matt Turner wrote: >> On Mon, Dec 6, 2010 at 5:30 PM, Guenter Roeck >> wrote: >> > On Mon, Dec 06, 2010 at 01:38:14AM -0500, Matt Turner wrote: >> >> From: Maciej W. Rozycki >> >> >> >> This is a rewrite of large parts of the driver mainly so that it uses >> >> SMBus interrupts to offload the CPU from busy-waiting on status inputs. >> >> As a part of the overhaul of the init and exit calls, all accesses to the >> >> hardware got converted to use accessory functions via an ioremap() cookie. >> >> >> >> Minimally rebased by Matt Turner. >> >> >> >> Tested-by: Matt Turner >> >> Signed-off-by: Matt Turner >> > >> > >> > I applied the patch to my 1480 tree. Unfortunately, it doesn't work with my system. >> > As far as I can see, the driver does not get any interrupts. >> > >> > My tree is 2.6.32, though. Do you know if I might be missing some other relevant patch ? >> > >> > Thanks, >> > Guenter >> >> I think this patch depends on >> http://www.linux-mips.org/archives/linux-mips/2010-12/msg00030.html >> > I did apply the second patch as well, since you had mentioned it in your patch. > That did not help, though. Frankly, I don't see the dependency in the first place - the other > patch only affects drivers/rtc/rtc-m41t80.c, and I would hope that SMBus support does not depend > on an rtc driver. Am I missing something ? > > Thanks, > Guenter Indeed that does not make much sense. I really don't know. Perhaps Maciej can shed some light on this? It certainly might be the case that these patches haven't ever been tested on a BCM91480 before. Matt From macro@linux-mips.org Tue Dec 7 03:26:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Dec 2010 03:26:58 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:55937 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492182Ab0LGC0y (ORCPT ); Tue, 7 Dec 2010 03:26:54 +0100 Date: Tue, 7 Dec 2010 02:26:54 +0000 (GMT) From: "Maciej W. Rozycki" To: Matt Turner cc: Guenter Roeck , Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts In-Reply-To: Message-ID: References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=ISO-8859-15 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28620 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1937 Lines: 44 On Mon, 6 Dec 2010, Matt Turner wrote: > >  Matt, thanks for keeping your eye on these bits and reviving them; I've > > meant to do so for a long time now, but never came to it.  Please note > > however, as I'm the original author, my original Signed-off-by markups > > continue to apply and you should be quoting them with the submissions. > > You should only add your own Signed-off-by annotation if you made any > > changes and it would make sense to state what these changes were. > > Sure thing. Will fix. For patches 2 and 3 of the other series, I don't > think I was ever 100% sure that you were the author, since they were > living on OpenWRT.org and I couldn't find them in any mailing list > archives. Can you confirm that these 4 patches are all yours? All the relevant submissions should be present here: http://www.linux-mips.org/archives/linux-mips/2008-05/threads.html Specifically: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=Pine.LNX.4.55.0805180447210.10067%40cliff.in.clinika.pl (5th of a series of 6), and: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=Pine.LNX.4.55.0805070054440.16173%40cliff.in.clinika.pl (3rd of a series of 4), and: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=Pine.LNX.4.55.0805130353250.535%40cliff.in.clinika.pl (individual submission). The "clean up SWARM RTC setup" change seems to be modified (lacking e.g. a proper read_persistent_clock() implementation) compared to my proposal (second above) and most likely came from someone else and the lm90 change definitely comes from someone else. Note that for IRQ support you may have to investigate dependencies in the other two series as the patch (third above) was intended to apply on top of the two series (select the date sort for easier identification of the series). I'd have to dig into that code for further details and I cannot afford the time right now, sorry. Maciej From groeck@ericsson.com Tue Dec 7 06:15:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Dec 2010 06:15:12 +0100 (CET) Received: from imr4.ericy.com ([198.24.6.8]:43513 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491029Ab0LGFPH (ORCPT ); Tue, 7 Dec 2010 06:15:07 +0100 Received: from eusaamw0712.eamcs.ericsson.se ([147.117.20.181]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id oB75i73F025589; Mon, 6 Dec 2010 23:44:08 -0600 Received: from localhost (147.117.20.213) by eusaamw0712.eamcs.ericsson.se (147.117.20.182) with Microsoft SMTP Server id 8.2.234.1; Tue, 7 Dec 2010 00:14:39 -0500 Date: Mon, 6 Dec 2010 21:14:38 -0800 From: Guenter Roeck To: "Maciej W. Rozycki" CC: Matt Turner , Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20101207051438.GA20144@ericsson.com> References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28621 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Content-Length: 665 Lines: 15 On Mon, Dec 06, 2010 at 09:26:54PM -0500, Maciej W. Rozycki wrote: [ ... ] > > Note that for IRQ support you may have to investigate dependencies in the > other two series as the patch (third above) was intended to apply on top > of the two series (select the date sort for easier identification of the > series). I'd have to dig into that code for further details and I cannot > afford the time right now, sorry. > A quick look through sb1250 vs. sb1480 code shows that the 1480 uses different interrupt numbers. The patch assigns the sb1250 interrupt numbers, so unless I am missing something the code as written can not work for sb1480. Thanks, Guenter From groeck@ericsson.com Tue Dec 7 07:24:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Dec 2010 07:24:15 +0100 (CET) Received: from imr4.ericy.com ([198.24.6.8]:39062 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491057Ab0LGGYK (ORCPT ); Tue, 7 Dec 2010 07:24:10 +0100 Received: from eusaamw0711.eamcs.ericsson.se ([147.117.20.178]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id oB76rDnk027372; Tue, 7 Dec 2010 00:53:15 -0600 Received: from localhost (147.117.20.213) by eusaamw0711.eamcs.ericsson.se (147.117.20.179) with Microsoft SMTP Server id 8.2.234.1; Tue, 7 Dec 2010 01:23:44 -0500 Date: Mon, 6 Dec 2010 22:23:44 -0800 From: Guenter Roeck To: Matt Turner CC: Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle , "Maciej W. Rozycki" Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20101207062344.GA20673@ericsson.com> References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1291617494-18430-1-git-send-email-mattst88@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28622 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Content-Length: 1359 Lines: 36 On Mon, Dec 06, 2010 at 01:38:14AM -0500, Matt Turner wrote: > From: Maciej W. Rozycki > > This is a rewrite of large parts of the driver mainly so that it uses > SMBus interrupts to offload the CPU from busy-waiting on status inputs. > As a part of the overhaul of the init and exit calls, all accesses to the > hardware got converted to use accessory functions via an ioremap() cookie. > > Minimally rebased by Matt Turner. > > Tested-by: Matt Turner > Signed-off-by: Matt Turner [ .. ] > > -static struct i2c_algo_sibyte_data sibyte_board_data[2] = { > - { NULL, 0, (void *) (CKSEG1+A_SMB_BASE(0)) }, > - { NULL, 1, (void *) (CKSEG1+A_SMB_BASE(1)) } > +static struct i2c_algo_sibyte_data i2c_sibyte_board_data[2] = { > + { > + .name = "sb1250-smbus-0", > + .base = A_SMB_0, > + .irq = K_INT_SMB_0, > + }, > + { > + .name = "sb1250-smbus-1", > + .base = A_SMB_1, > + .irq = K_INT_SMB_1, Found my problem. The .irq settings don't work for BCM1480. It needs K_BCM1480_INT_SMB_0 and K_BCM1480_INT_SMB_1 from asm/sibyte/bcm1480_int.h. For a clean fix, i2c_sibyte_board_data[] should probably be defined in a platform file, not in the i2c bus driver. Guenter From macro@linux-mips.org Tue Dec 7 15:30:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Dec 2010 15:30:31 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:38479 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491888Ab0LGOa1 (ORCPT ); Tue, 7 Dec 2010 15:30:27 +0100 Date: Tue, 7 Dec 2010 14:30:27 +0000 (GMT) From: "Maciej W. Rozycki" To: Guenter Roeck cc: Matt Turner , Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts In-Reply-To: <20101207051438.GA20144@ericsson.com> Message-ID: References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> <20101207051438.GA20144@ericsson.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28623 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 668 Lines: 14 On Mon, 6 Dec 2010, Guenter Roeck wrote: > A quick look through sb1250 vs. sb1480 code shows that the 1480 uses different > interrupt numbers. The patch assigns the sb1250 interrupt numbers, so unless > I am missing something the code as written can not work for sb1480. That well could be -- I never had access to a BigSur board. The board-specific interrupt numbers should either be available from the board manual (I haven't checked if one has been released; I certainly have one for my SWARM) or quoted somewhere in our tree. Otherwise figuring them out by trial and error should be a trivial exercise for someone with actual hardware at hand. Maciej From groeck@ericsson.com Tue Dec 7 15:42:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Dec 2010 15:42:22 +0100 (CET) Received: from imr4.ericy.com ([198.24.6.8]:45667 "EHLO imr4.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491888Ab0LGOmR (ORCPT ); Tue, 7 Dec 2010 15:42:17 +0100 Received: from eusaamw0707.eamcs.ericsson.se ([147.117.20.32]) by imr4.ericy.com (8.14.3/8.14.3/Debian-9.1ubuntu1) with ESMTP id oB7FBLAR023712; Tue, 7 Dec 2010 09:11:24 -0600 Received: from localhost (147.117.20.213) by eusaamw0707.eamcs.ericsson.se (147.117.20.92) with Microsoft SMTP Server id 8.2.234.1; Tue, 7 Dec 2010 09:41:51 -0500 Date: Tue, 7 Dec 2010 06:41:50 -0800 From: Guenter Roeck To: "Maciej W. Rozycki" CC: Matt Turner , Jean Delvare , "linux-i2c@vger.kernel.org" , "linux-mips@linux-mips.org" , Ralf Baechle Subject: Re: [PATCH] I2C: SiByte: Convert the driver to make use of interrupts Message-ID: <20101207144150.GA21872@ericsson.com> References: <1291617494-18430-1-git-send-email-mattst88@gmail.com> <20101206173040.GA18372@ericsson.com> <20101207051438.GA20144@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28624 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Content-Length: 1013 Lines: 19 On Tue, Dec 07, 2010 at 09:30:27AM -0500, Maciej W. Rozycki wrote: > On Mon, 6 Dec 2010, Guenter Roeck wrote: > > > A quick look through sb1250 vs. sb1480 code shows that the 1480 uses different > > interrupt numbers. The patch assigns the sb1250 interrupt numbers, so unless > > I am missing something the code as written can not work for sb1480. > > That well could be -- I never had access to a BigSur board. The > board-specific interrupt numbers should either be available from the board > manual (I haven't checked if one has been released; I certainly have one > for my SWARM) or quoted somewhere in our tree. Otherwise figuring them > out by trial and error should be a trivial exercise for someone with > actual hardware at hand. > I already sent a reply to the original patch - I confirmed that the interrupts are different. Those are SOC interrupts, so they are CPU specific, not board specific. Code started working after I replaced the sb1250 interrupts with bcm1480 interrupts. Guenter From Anoop_P.A@pmc-sierra.com Wed Dec 8 14:49:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Dec 2010 14:49:26 +0100 (CET) Received: from bby1mta02.pmc-sierra.com ([216.241.235.117]:37498 "EHLO bby1mta02.pmc-sierra.bc.ca" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491164Ab0LHNtX convert rfc822-to-8bit (ORCPT ); Wed, 8 Dec 2010 14:49:23 +0100 Received: from bby1mta02.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id D3D578E00BC for ; Wed, 8 Dec 2010 05:49:06 -0800 (PST) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (bby1exg02 [216.241.231.167]) by bby1mta02.pmc-sierra.bc.ca (Postfix) with SMTP id C76298E00B9 for ; Wed, 8 Dec 2010 05:49:06 -0800 (PST) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.159]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.4675); Wed, 8 Dec 2010 05:49:07 -0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: SMTC support status in latest git head. Date: Wed, 8 Dec 2010 05:48:48 -0800 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: SMTC support status in latest git head. Thread-Index: AcuW3qPRrYkCuXj/TUWpvOZEokZpAQ== From: "Anoop P.A." To: X-OriginalArrivalTime: 08 Dec 2010 13:49:07.0010 (UTC) FILETIME=[AED21220:01CB96DE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28624 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips Content-Length: 2675 Lines: 49 Hi list, Any body is aware of SMTC support status in latest git sources?. I have tried testing SMTC kernel for malta in qemu / OVP without any success ( emulators not working for 34k). I am trying to bring up SMTC Linux support for an mips34K based soc ( MSP71xx family). While booting , kernel getting hung on calibrate loop delay. I am getting only one interrupt from timer. With similar smtc platform support file ( changed to map smp_ops structure) 2.6.24-stable branch kernel ( where latest timer structure introduced) boots fine. [ 0.000000] Linux version 2.6.37-rc1-pmc-00197-g5bfd3ba-dirty (paanoop1@paanoop1-desktop) (gcc version 4.5.1 (GCC) ) #168 SMP PREEMPT Wed Dec 8 19:19:490 [ 0.000000] DSPRAM0: PA=1c100000,Size=00008000,enabled [ 0.000000] UART clock set to 50000000 [ 0.000000] CPU revision is: 00019548 (MIPS 34Kc) [ 0.000000] Determined physical RAM map: [ 0.000000] memory: 00001000 @ 00000000 (reserved) [ 0.000000] memory: 000ff000 @ 00001000 (usable) [ 0.000000] memory: 003f2000 @ 00100000 (reserved) [ 0.000000] memory: 0fad9200 @ 004f2000 (usable) [ 0.000000] Wasting 32 bytes for tracking 1 unused pages [ 0.000000] Zone PFN ranges: [ 0.000000] Normal 0x00000000 -> 0x0000ffcb [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[1] active PFN ranges [ 0.000000] 0: 0x00000000 -> 0x0000ffcb [ 0.000000] 6 available secondary CPU TC(s) [ 0.000000] PERCPU: Embedded 7 pages/cpu @81203000 s6464 r8192 d14016 u32768 [ 0.000000] pcpu-alloc: s6464 r8192 d14016 u32768 alloc=8*4096 [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64971 [ 0.000000] Kernel command line: console=ttyS0,57600 [ 0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes) [ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes. [ 0.000000] Primary data cache 64kB, 4-way, PIPT, no aliases, linesize 32 bytes [ 0.000000] Writing ErrCtl register=00000000 [ 0.000000] Readback ErrCtl register=00000000 [ 0.000000] Memory: 254360k/257888k available (3081k kernel code, 3528k reserved, 653k data, 200k init, 0k highmem) [ 0.000000] Preemptable hierarchical RCU implementation. [ 0.000000] NR_IRQS:128 [ 0.000000] console [ttyS0] enabled [ 0.000000] Clock rate set to 600000000 [ 0.000000] Calibrating delay loop... Any idea to debug the issue ?. Thanks, Anoop From ralf@linux-mips.org Wed Dec 8 21:37:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Dec 2010 21:37:24 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42819 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491909Ab0LHUhU (ORCPT ); Wed, 8 Dec 2010 21:37:20 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB8Kb6OF008718; Wed, 8 Dec 2010 20:37:06 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB8Kb5lR008707; Wed, 8 Dec 2010 20:37:05 GMT Date: Wed, 8 Dec 2010 20:37:04 +0000 From: Ralf Baechle To: David Daney Cc: Anoop P A , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Thomas Gleixner Subject: Re: [PATCH] Introduce mips_late_time_init Message-ID: <20101208203704.GB30923@linux-mips.org> References: <1291623812.31822.6.camel@paanoop1-desktop> <4CFD2095.9040404@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4CFD2095.9040404@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28625 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Dec 06, 2010 at 09:42:45AM -0800, David Daney wrote: > On 12/06/2010 12:23 AM, Anoop P A wrote: > >This patch moves plat_time_init and clocksoure init funtion calls to > >late_time_init. > > > > Why would you want to do this? > > The current code works perfectly, so I see no reason to change it. Well, not really. By the time time_init is called kmalloc isn't ready yet. That's why mips_clockevent_device pretty much had to be statically allocated and is also why interrupts have to use setup_irq instead of request_irq. Keeping mips_clockevent_device statically allocated as per-CPU makes sense. Less for the struct irqaction and he'll have to allocate one for each VPE (think CPU) he installs a clockevent device on. Running everything from late_time_init() instead allows the use of kmalloc. X86 has the same issue with requiring kmalloc in time_init which is why they had moved everything to late_time_init. So the real question is, why can't we just move the call of time_init() in setup_kernel() to where late_time_init() is getting called from for all architectures, does anything rely on it getting called early? Ralf From tglx@linutronix.de Wed Dec 8 22:21:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Dec 2010 22:21:54 +0100 (CET) Received: from www.tglx.de ([62.245.132.106]:51463 "EHLO www.tglx.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492058Ab0LHVVp (ORCPT ); Wed, 8 Dec 2010 22:21:45 +0100 Received: from localhost (www.tglx.de [127.0.0.1]) by www.tglx.de (8.13.8/8.13.8/TGLX-2007100201) with ESMTP id oB8LL4vV026820 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 8 Dec 2010 22:21:05 +0100 Date: Wed, 8 Dec 2010 22:21:04 +0100 (CET) From: Thomas Gleixner To: Ralf Baechle cc: David Daney , Anoop P A , linux-mips@linux-mips.org, LKML , linux-arch@vger.kernel.org, Linus Torvalds , Andrew Morton Subject: Re: [PATCH] Introduce mips_late_time_init In-Reply-To: <20101208203704.GB30923@linux-mips.org> Message-ID: References: <1291623812.31822.6.camel@paanoop1-desktop> <4CFD2095.9040404@caviumnetworks.com> <20101208203704.GB30923@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: clamav-milter 0.95.3 at www.tglx.de X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28626 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tglx@linutronix.de Precedence: bulk X-list: linux-mips On Wed, 8 Dec 2010, Ralf Baechle wrote: > Running everything from late_time_init() instead allows the use of kmalloc. > X86 has the same issue with requiring kmalloc in time_init which is why > they had moved everything to late_time_init. It's more ioremap, but yeah. > So the real question is, why can't we just move the call of time_init() > in setup_kernel() to where late_time_init() is getting called from for > all architectures, does anything rely on it getting called early? That's a good question and I asked it myself already. I can't see a real reason why something would need it early. Definitely worth to try. Thanks, tglx From benh@kernel.crashing.org Wed Dec 8 23:46:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Dec 2010 23:46:48 +0100 (CET) Received: from gate.crashing.org ([63.228.1.57]:59735 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492096Ab0LHWqo (ORCPT ); Wed, 8 Dec 2010 23:46:44 +0100 Received: from [IPv6:::1] (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id oB8MjkZ3006547; Wed, 8 Dec 2010 16:45:47 -0600 Subject: Re: [PATCH] Introduce mips_late_time_init From: Benjamin Herrenschmidt To: Thomas Gleixner Cc: Ralf Baechle , David Daney , Anoop P A , linux-mips@linux-mips.org, LKML , linux-arch@vger.kernel.org, Linus Torvalds , Andrew Morton In-Reply-To: References: <1291623812.31822.6.camel@paanoop1-desktop> <4CFD2095.9040404@caviumnetworks.com> <20101208203704.GB30923@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Thu, 09 Dec 2010 09:45:46 +1100 Message-ID: <1291848346.16694.205.camel@pasglop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28627 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: benh@kernel.crashing.org Precedence: bulk X-list: linux-mips On Wed, 2010-12-08 at 22:21 +0100, Thomas Gleixner wrote: > On Wed, 8 Dec 2010, Ralf Baechle wrote: > > Running everything from late_time_init() instead allows the use of kmalloc. > > X86 has the same issue with requiring kmalloc in time_init which is why > > they had moved everything to late_time_init. > > It's more ioremap, but yeah. > > > So the real question is, why can't we just move the call of time_init() > > in setup_kernel() to where late_time_init() is getting called from for > > all architectures, does anything rely on it getting called early? > > That's a good question and I asked it myself already. I can't see a > real reason why something would need it early. Definitely worth to > try. Well, I can see some reasons at least... On ppc at least, we calibrate the timebase/decrementer in time_init, so things like udelay etc... are going to be unreliable until we've done that, which could be a problem if done too late due to sensitive HW accessors that might rely on these. So we'd probably need to move that to a different (early) arch callback if time_init is moved. Also, still on server PPC, you can't really disable the decrementer (only delay it). So if interrupts are enabled, we will eventually get timer ones. So we'd have to be careful about keeping some state, knowing that the stuff isn't initialized yet and just set the decrementer to fire again as late as possible, until it's properly configured. Besides, we can use kmalloc that early nowadays, can't we ? That's what the gfp_allowed_mask is all about ... Cheers, Ben. From ralf@linux-mips.org Thu Dec 9 18:07:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Dec 2010 18:07:54 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40910 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491814Ab0LIRHv (ORCPT ); Thu, 9 Dec 2010 18:07:51 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB9H7oV2017266; Thu, 9 Dec 2010 17:07:50 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB9H7nkY017264; Thu, 9 Dec 2010 17:07:49 GMT Date: Thu, 9 Dec 2010 17:07:48 +0000 From: Ralf Baechle To: "Anoop P.A." Cc: linux-mips@linux-mips.org, "Kevin D. Kissell" Subject: Re: SMTC support status in latest git head. Message-ID: <20101209170748.GC30923@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28628 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Dec 08, 2010 at 05:48:48AM -0800, Anoop P.A. wrote: > Any body is aware of SMTC support status in latest git sources?. I have tried testing SMTC kernel for malta in qemu / OVP without any success ( emulators not working for 34k). Correct. MTI's MIPSsim is the only simulator that supports multithreading afaik. SMTC is not terribly popular so doesn't receive the regular testing it should because it's also a complex beast. > I am trying to bring up SMTC Linux support for an mips34K based soc ( MSP71xx family). > > While booting , kernel getting hung on calibrate loop delay. I am getting only one interrupt from timer. With similar smtc platform support file ( changed to map smp_ops structure) 2.6.24-stable branch kernel ( where latest timer structure introduced) boots fine. Timer interrupts work differently in SMTC. Each CPU needs a clock event device, that is an interrupt timer but the CPU core is restricted to just one per VPE so in typical SMTC setup multiple CPUs aka TCs will have to share an interrupt timer. The way this works is that one of the TCs associated with a VPE will take the timer interrupt and forward it to the other TCs associated with the same VPE (if any) through a software IPI mechanism. The race conditions that need to handled to make this work are ... interesting. Your problem seems to be simpler as you only get a single timer interrupt. Ralf From ralf@linux-mips.org Thu Dec 9 19:46:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Dec 2010 19:46:45 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56951 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491194Ab0LISqm (ORCPT ); Thu, 9 Dec 2010 19:46:42 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oB9IkdaU019512; Thu, 9 Dec 2010 18:46:40 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oB9Ikcj6019510; Thu, 9 Dec 2010 18:46:39 GMT Date: Thu, 9 Dec 2010 18:46:38 +0000 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Fix build failure for IP22 Message-ID: <20101209184638.GD30923@linux-mips.org> References: <1290511948-10347-1-git-send-email-dmitri.vorobiev@movial.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1290511948-10347-1-git-send-email-dmitri.vorobiev@movial.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28629 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 23, 2010 at 01:32:28PM +0200, Dmitri Vorobiev wrote: > Commit 48e1fd5a81416a037f5a48120bf281102f2584e2 changed the name > of the MIPS-specific dma_cache_sync() routine by prefixing it with > `mips_', and removed the export for its symbol. Two drivers, which > did use dma_cache_sync(), namely, sgiseeq and sgiwd93, were not > converted to use the new function, which led to build failure for > the IP22 platform. > > This patch fixes the build failure by fixing the call sites of > mips_dma_cache_sync() and exporting the symbol for this routine as > a GPL symbol. While at it, some minor changes to improve Kconfig > help entries were done. dma_cache_sync isn't MIPS specific - mips_dma_cache_sync is but the function wasn't renamed everywhere. Looking into what went wrong now but your patch surely is not correct. Ralf From kevink@paralogos.com Thu Dec 9 19:52:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Dec 2010 19:52:25 +0100 (CET) Received: from gateway02.websitewelcome.com ([69.56.170.20]:53936 "HELO gateway02.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491847Ab0LISwV (ORCPT ); Thu, 9 Dec 2010 19:52:21 +0100 Received: (qmail 4883 invoked from network); 9 Dec 2010 18:51:59 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway02.websitewelcome.com with SMTP; 9 Dec 2010 18:51:59 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=OnLxfoov2IdmAskBIOhmEf7+LHvDaIwQlzeCPkRiidjqwaSnUdoMzh4BvMu8BmklftPob7Lug+n/o2n+vs95UVKZRL91H+eyYEWV+JstsSFU40aTSBXErwi+QkOBE+Ui; Received: from [216.239.45.4] (port=27791 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1PQlbB-000712-CR; Thu, 09 Dec 2010 12:52:13 -0600 Message-ID: <4D012560.6020003@paralogos.com> Date: Thu, 09 Dec 2010 10:52:16 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 MIME-Version: 1.0 To: "Anoop P.A." CC: linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28630 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips I used to do occasional tests and damage control patches for SMTC, but haven't had the time and resources for the past year or so. The "Calibrating delay loop" hang is an absolutely classic hang in SMTC systems that stems from the interrupt management system not being properly set up. Ralf alluded to the intra-TC timer propagation protocol, but your problem could just as easily (more easily, actually) have to do with enable mask management. In order to keep multiple threads from "convoying" into interrupt handlers chasing a single event, SMTC manipulates the interrupt enable mask at entry into an interrupt exception to ensure that only the initial TC goes after it. The interrupt is unmasked once the interrupt handler has quenched the source and invoked the IRQ ack function. Unfortunately, generic timer functions don't always do the canonical source quench performed by most device driver interrupt handlers. I tried to make all this self-contained in generic architecture-specific code, but at some point it ended up being cleaner and more efficient to have *some* hooks in platform specific timer code. It was there for Malta in the kernel.org mainline once upon a time, and I *thought* we'd propagated working code for the initial PMC-Sierra 34K-based SoC's at least as far as linux-mips.org, but the source tree has been considerably reorganized - there was a time when some of the hooks were under arch/mips/mips-boards/generic, which no longer exists - and I'm not sure where to point you. Git and grep are your friends. The first order of business is to break into that hung timer calibration loop and dump the CP0 registers for the VPE and the TCs, in particular checking the interrupt enable mask in Status against the pending interrupts in the Cause register. If you're seeing the timer interrupt's bit set in Cause, but clear in Status, you need to fix the SMTC interrupt mask hook for your platform timer. If that's *not* it, check to see if you're building for "tickless" operation. Tickless ends up being really important for SMTC, and I did get it working properly back in 2008, but I the SMTC-specific cevt-smtc.c code uses common functions in cevt-r4k.c, and I've seen some patches to cevt-r4k.c going by that I rather doubt were ever tested against an SMTC build/platform. There might have been breakage there, and configuring to use a fixed interval timer (say, 100Hz) would be a way to test that hypothesis. Regards, Kevin K. On 12/08/10 05:48, Anoop P.A. wrote: > Hi list, > > Any body is aware of SMTC support status in latest git sources?. I have tried testing SMTC kernel for malta in qemu / OVP without any success ( emulators not working for 34k). > > I am trying to bring up SMTC Linux support for an mips34K based soc ( MSP71xx family). > > While booting , kernel getting hung on calibrate loop delay. I am getting only one interrupt from timer. With similar smtc platform support file ( changed to map smp_ops structure) 2.6.24-stable branch kernel ( where latest timer structure introduced) boots fine. > > [ 0.000000] Linux version 2.6.37-rc1-pmc-00197-g5bfd3ba-dirty (paanoop1@paanoop1-desktop) (gcc version 4.5.1 (GCC) ) #168 SMP PREEMPT Wed Dec 8 19:19:490 > [ 0.000000] DSPRAM0: PA=1c100000,Size=00008000,enabled > [ 0.000000] UART clock set to 50000000 > [ 0.000000] CPU revision is: 00019548 (MIPS 34Kc) > [ 0.000000] Determined physical RAM map: > [ 0.000000] memory: 00001000 @ 00000000 (reserved) > [ 0.000000] memory: 000ff000 @ 00001000 (usable) > [ 0.000000] memory: 003f2000 @ 00100000 (reserved) > [ 0.000000] memory: 0fad9200 @ 004f2000 (usable) > [ 0.000000] Wasting 32 bytes for tracking 1 unused pages > [ 0.000000] Zone PFN ranges: > [ 0.000000] Normal 0x00000000 -> 0x0000ffcb > [ 0.000000] Movable zone start PFN for each node > [ 0.000000] early_node_map[1] active PFN ranges > [ 0.000000] 0: 0x00000000 -> 0x0000ffcb > [ 0.000000] 6 available secondary CPU TC(s) > [ 0.000000] PERCPU: Embedded 7 pages/cpu @81203000 s6464 r8192 d14016 u32768 > [ 0.000000] pcpu-alloc: s6464 r8192 d14016 u32768 alloc=8*4096 > [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 > [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64971 > [ 0.000000] Kernel command line: console=ttyS0,57600 > [ 0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes) > [ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) > [ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) > [ 0.000000] Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes. > [ 0.000000] Primary data cache 64kB, 4-way, PIPT, no aliases, linesize 32 bytes > [ 0.000000] Writing ErrCtl register=00000000 > [ 0.000000] Readback ErrCtl register=00000000 > [ 0.000000] Memory: 254360k/257888k available (3081k kernel code, 3528k reserved, 653k data, 200k init, 0k highmem) > [ 0.000000] Preemptable hierarchical RCU implementation. > [ 0.000000] NR_IRQS:128 > [ 0.000000] console [ttyS0] enabled > [ 0.000000] Clock rate set to 600000000 > [ 0.000000] Calibrating delay loop... > > Any idea to debug the issue ?. > > Thanks, > Anoop > > > > From dmitri.vorobiev@gmail.com Thu Dec 9 21:34:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Dec 2010 21:34:44 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:59442 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491948Ab0LIUek convert rfc822-to-8bit (ORCPT ); Thu, 9 Dec 2010 21:34:40 +0100 Received: by iyj21 with SMTP id 21so69353iyj.36 for ; Thu, 09 Dec 2010 12:34:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=nGrAPdr9zO5+lpeXfFXukK8zXPM99ZRbVxk3flXSxss=; b=rD1szn7ksItnZKIrYcZOJGCoL+UMpHxXtKxFsshPZ87aoCIJDqn8+p28E6yloSaobo JDw7fSJ4h5TUlCplHGbmqIKyCYMMeeQR4m4J4nP7uGkJgrQi9KEixHVG5CzsUQmxZUp4 pXhZJa8EbuvR6h3b2MjFh/WN6VX1nZBIVSnHo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=NzurbfGhJlCWBwmvjbcowXw8tSJ4V2Dm/uSR76pDA02/vpGNZeX79y0SeSoA1uswrj ltqMl8ima0HGA97Tv8WgDmm3cNZkWX3yvo3APYDSAP+luJJTT8GqRx17IqZL8iIO4R4+ j+K7NT6oadcWcwXTyUwGTfFhNaJU+9v9tFDQA= MIME-Version: 1.0 Received: by 10.231.35.8 with SMTP id n8mr720793ibd.123.1291926872614; Thu, 09 Dec 2010 12:34:32 -0800 (PST) Received: by 10.231.184.220 with HTTP; Thu, 9 Dec 2010 12:34:32 -0800 (PST) In-Reply-To: <20101209184638.GD30923@linux-mips.org> References: <1290511948-10347-1-git-send-email-dmitri.vorobiev@movial.com> <20101209184638.GD30923@linux-mips.org> Date: Thu, 9 Dec 2010 22:34:32 +0200 Message-ID: Subject: Re: [PATCH] MIPS: Fix build failure for IP22 From: Dmitri Vorobiev To: Ralf Baechle Cc: Dmitri Vorobiev , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28631 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Thu, Dec 9, 2010 at 8:46 PM, Ralf Baechle wrote: > On Tue, Nov 23, 2010 at 01:32:28PM +0200, Dmitri Vorobiev wrote: > >> Commit 48e1fd5a81416a037f5a48120bf281102f2584e2 changed the name >> of the MIPS-specific dma_cache_sync() routine by prefixing it with >> `mips_', and removed the export for its symbol. Two drivers, which >> did use dma_cache_sync(), namely, sgiseeq and sgiwd93, were not >> converted to use the new function, which led to build failure for >> the IP22 platform. >> >> This patch fixes the build failure by fixing the call sites of >> mips_dma_cache_sync() and exporting the symbol for this routine as >> a GPL symbol. While at it, some minor changes to improve Kconfig >> help entries were done. > > dma_cache_sync isn't MIPS specific - mips_dma_cache_sync is but the > function wasn't renamed everywhere.  Looking into what went wrong now > but your patch surely is not correct. OK, the main thing would be that the build failure be fixed. Thanks for looking into that. Dmitri > >  Ralf > > From lethal@linux-sh.org Fri Dec 10 18:22:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Dec 2010 18:22:45 +0100 (CET) Received: from 124x34x33x190.ap124.ftth.ucom.ne.jp ([124.34.33.190]:59561 "EHLO master.linux-sh.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491878Ab0LJRWm (ORCPT ); Fri, 10 Dec 2010 18:22:42 +0100 Received: from localhost (unknown [127.0.0.1]) by master.linux-sh.org (Postfix) with ESMTP id E3A2B6376C; Fri, 10 Dec 2010 17:21:25 +0000 (UTC) X-Virus-Scanned: amavisd-new at linux-sh.org Received: from master.linux-sh.org ([127.0.0.1]) by localhost (master.linux-sh.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RZ0miE+oGbP7; Sat, 11 Dec 2010 02:21:25 +0900 (JST) Received: by master.linux-sh.org (Postfix, from userid 500) id 82E9063778; Sat, 11 Dec 2010 02:21:25 +0900 (JST) Date: Sat, 11 Dec 2010 02:21:25 +0900 From: Paul Mundt To: Benjamin Herrenschmidt Cc: Thomas Gleixner , Ralf Baechle , David Daney , Anoop P A , linux-mips@linux-mips.org, LKML , linux-arch@vger.kernel.org, Linus Torvalds , Andrew Morton Subject: Re: [PATCH] Introduce mips_late_time_init Message-ID: <20101210172125.GA3750@linux-sh.org> References: <1291623812.31822.6.camel@paanoop1-desktop> <4CFD2095.9040404@caviumnetworks.com> <20101208203704.GB30923@linux-mips.org> <1291848346.16694.205.camel@pasglop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1291848346.16694.205.camel@pasglop> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28632 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lethal@linux-sh.org Precedence: bulk X-list: linux-mips On Thu, Dec 09, 2010 at 09:45:46AM +1100, Benjamin Herrenschmidt wrote: > On Wed, 2010-12-08 at 22:21 +0100, Thomas Gleixner wrote: > > On Wed, 8 Dec 2010, Ralf Baechle wrote: > > > Running everything from late_time_init() instead allows the use of kmalloc. > > > X86 has the same issue with requiring kmalloc in time_init which is why > > > they had moved everything to late_time_init. > > > > It's more ioremap, but yeah. > > > > > So the real question is, why can't we just move the call of time_init() > > > in setup_kernel() to where late_time_init() is getting called from for > > > all architectures, does anything rely on it getting called early? > > > > That's a good question and I asked it myself already. I can't see a > > real reason why something would need it early. Definitely worth to > > try. > > Well, I can see some reasons at least... > > On ppc at least, we calibrate the timebase/decrementer in time_init, so > things like udelay etc... are going to be unreliable until we've done > that, which could be a problem if done too late due to sensitive HW > accessors that might rely on these. > The SH case is similar. We bring up the clock framework during time_init() which we need for per-CPU loops_per_jiffy calculation in addition to initializing the clocksource/clockevent timers that come up during late_time_init. Presently we have a slab_is_available() check in the SH clkdev implementation mostly for board PLLs and so on, and our ioremap() implementation also transparently bolts on to fixed ioremaps through fixmap if we're really early anyways. It's possible that kmalloc is usable outright now after the reordering happened, I haven't gone back and checked it again since then. > So we'd probably need to move that to a different (early) arch callback > if time_init is moved. > late_time_init has always struck me as a bit of a misnomer, since it's still quite early as far as the rest of the system state is concerned, particularly the driver core (all SH and ARM SH-Mobile platforms use platform devices for clocksources/clockevents). In any event, SH would also need this. On ARM SH-Mobile we use the same approach although each platform explicitly calls in to clock framework initialization prior to assigning a late_time_init, which in turn gets all wrapped up in the ARM sys_timer abstraction. From ralf@linux-mips.org Fri Dec 10 21:40:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Dec 2010 21:40:57 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58731 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492014Ab0LJUky (ORCPT ); Fri, 10 Dec 2010 21:40:54 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oBAKersN001498; Fri, 10 Dec 2010 20:40:53 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oBAKerxD001497; Fri, 10 Dec 2010 20:40:53 GMT Date: Fri, 10 Dec 2010 20:40:52 +0000 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH V2] MIPS: Alchemy: fix build with SERIAL_8250=n Message-ID: <20101210204052.GA1274@linux-mips.org> References: <1288025051-17145-1-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288025051-17145-1-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28633 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Oct 25, 2010 at 06:44:11PM +0200, Manuel Lauss wrote: > In commit 7d172bfe ("Alchemy: Add UART PM methods") I introduced > platform PM methods which call a function of the 8250 driver; > this patch works around link failures when the kernel is built > without 8250 support. > > Signed-off-by: Manuel Lauss > --- > V2: added commit name to patch description as per Sergei's suggestion. Applied, thanks. Though anything like a CONFIG_SERIAL_8250 in board code always strikes me as wrong. What if the driver is built as a module? What if the kernel is built without the driver, then later on the module is built separately and then inserted? Ralf From manuel.lauss@googlemail.com Fri Dec 10 21:56:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Dec 2010 21:56:19 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:37626 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492017Ab0LJU4Q convert rfc822-to-8bit (ORCPT ); Fri, 10 Dec 2010 21:56:16 +0100 Received: by wwi17 with SMTP id 17so3901627wwi.24 for ; Fri, 10 Dec 2010 12:56:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=ZjZzNRviWvRpOlgS2gDZj7meviUxj/GGYfYeeIoflBc=; b=HAzIvD4Q6ejMsDKXJCe2DWR5NaALWPd2MPZWmRiAhvkqD6LHvSZ/d47ijDc71ehdue Pk7eg3v0YVUBniKJeuKD9ZX1FuavYWbe3HvwIngEZzDvWD0G1IbbDHu4RwdoPf1w/6yu JJ4OegfjlHuBhnoDFViFXbSKTWHaCm5QAXScg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=ZH/vxbINf5VcVtn++UXav2zhre1ylFknjGtHV/kvED6pgQnpNQ4Ok6ep6CbcAy1Jan 1aHmbCKy9XIJsLEqPkn5ScVStbkrtJyAANKUAW/CvguE1mVZYJBUTJz7gE9sN3g978f2 +X6yJi4MDIJaMFM+pKKAPSQPJB8AwKQE+L3A0= MIME-Version: 1.0 Received: by 10.216.172.65 with SMTP id s43mr1504173wel.14.1292014571239; Fri, 10 Dec 2010 12:56:11 -0800 (PST) Received: by 10.216.176.12 with HTTP; Fri, 10 Dec 2010 12:56:11 -0800 (PST) In-Reply-To: <20101210204052.GA1274@linux-mips.org> References: <1288025051-17145-1-git-send-email-manuel.lauss@googlemail.com> <20101210204052.GA1274@linux-mips.org> Date: Fri, 10 Dec 2010 21:56:11 +0100 Message-ID: Subject: Re: [PATCH V2] MIPS: Alchemy: fix build with SERIAL_8250=n From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28634 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Fri, Dec 10, 2010 at 9:40 PM, Ralf Baechle wrote: > > On Mon, Oct 25, 2010 at 06:44:11PM +0200, Manuel Lauss wrote: > > > In commit 7d172bfe ("Alchemy: Add UART PM methods") I introduced > > platform PM methods which call a function of the 8250 driver; > > this patch works around link failures when the kernel is built > > without 8250 support. > > > > Signed-off-by: Manuel Lauss > > --- > > V2: added commit name to patch description as per Sergei's suggestion. > > Applied, thanks. > > Though anything like a CONFIG_SERIAL_8250 in board code always strikes me > as wrong.  What if the driver is built as a module?  What if the kernel is > built without the driver, then later on the module is built separately and > then inserted? Hm, I think I understand.  How's this approach (untested)? -- From 8ee2aff5c0503be37e934fe5a2a49c50bb292f81 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 25 Oct 2010 12:28:27 +0200 Subject: [PATCH v3] MIPS: Alchemy: fix build with SERIAL_8250=n In commit 7d172bfe ("Alchemy: Add UART PM methods") I introduced platform PM methods which call a function of the 8250 driver; this patch works around link failures when the kernel is built without 8250 support. Signed-off-by: Manuel Lauss --- v3: account for modular 8250 code. v2: added commit name to patch description as per Sergei's suggestion. arch/mips/alchemy/common/platform.c | 15 ++++++++++++--- 1 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 3691630..1f98032 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -27,6 +27,9 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, unsigned int old_state) { + void(*pm_func)(struct uart_port *, unsigned int, unsigned int); + pm_func = symbol_get(serial8250_do_pm); + switch (state) { case 0: if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) { @@ -38,17 +41,23 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, } __raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */ wmb(); - serial8250_do_pm(port, state, old_state); + if (pm_func) + pm_func(port, state, old_state); break; case 3: /* power off */ - serial8250_do_pm(port, state, old_state); + if (pm_func) + pm_func(port, state, old_state); __raw_writel(0, port->membase + UART_MOD_CNTRL); wmb(); break; default: - serial8250_do_pm(port, state, old_state); + if (pm_func) + pm_func(port, state, old_state); break; } + + if (pm_func) + symbol_put(pm_func); } #define PORT(_base, _irq) \ -- 1.7.3.2 Thanks, Manuel Lauss From manuel.lauss@googlemail.com Sat Dec 11 14:13:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 11 Dec 2010 14:13:16 +0100 (CET) Received: from mail-ew0-f54.google.com ([209.85.215.54]:47273 "EHLO mail-ew0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491138Ab0LKNNN (ORCPT ); Sat, 11 Dec 2010 14:13:13 +0100 Received: by ewy24 with SMTP id 24so3180780ewy.27 for ; Sat, 11 Dec 2010 05:13:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=v0cTdGci7cw4E8rob7CoM0vvgFVfikIE3L+mg7WJ8xE=; b=wjD0RQhugVDTwYeqzblk1KNvWo4JLN2xIdttMRipTH08cfrm94wM2BUQqa3qis7mn/ 8x5xscYCCjM8eFp0t0cK60pfGq7ZCVXI04B6LKrmkl0ejy8Xn/9jkjrBpFDzYGHcmrSN o2JpLQ7MpVmOQXuji+DVhht3/zjHq30ALjqEU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=jNOspWbK1vb4U0bxlcEP7kBmFZLSEz3bvgWTiW20p9GWHSFaBKJ/KXtO8cbR5hnxLY QJwftADsYsqHrvM/1nWV353Kwh0GNkcfL8DDBRLMI2EZgdN5fSJWNnok2mgmOg/fYxl2 mJOAlzDdk7KYzOVgSBHvceyD4Veu8t+q7egWI= Received: by 10.213.108.72 with SMTP id e8mr515613ebp.70.1292073192742; Sat, 11 Dec 2010 05:13:12 -0800 (PST) Received: from localhost.localdomain (178-191-12-185.adsl.highway.telekom.at [178.191.12.185]) by mx.google.com with ESMTPS id u1sm918517eeh.22.2010.12.11.05.13.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 11 Dec 2010 05:13:12 -0800 (PST) From: Manuel Lauss To: Ralf Baechle , Linux-MIPS Cc: Manuel Lauss Subject: [PATCH v3] MIPS: Alchemy: fix build with SERIAL_8250=n Date: Sat, 11 Dec 2010 14:13:04 +0100 Message-Id: <1292073184-24117-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.3.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28635 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips In commit 7d172bfe ("Alchemy: Add UART PM methods") I introduced platform PM methods which call a function of the 8250 driver; this patch works around link failures when the kernel is built without 8250 support. Signed-off-by: Manuel Lauss --- Run-tested on DB1200. v3: account for modular 8250 code. v2: added commit name to patch description as per Sergei's suggestion. arch/mips/alchemy/common/platform.c | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 3691630..66ca7c5 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -27,6 +27,12 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, unsigned int old_state) { + /* account for 8250.c built as module. This code can only be called + * by 8250.c so symbol_get should never fail. + */ + void(*pm_func)(struct uart_port *, unsigned int, unsigned int); + pm_func = symbol_get(serial8250_do_pm); + switch (state) { case 0: if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) { @@ -38,17 +44,19 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, } __raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */ wmb(); - serial8250_do_pm(port, state, old_state); + pm_func(port, state, old_state); break; case 3: /* power off */ - serial8250_do_pm(port, state, old_state); + pm_func(port, state, old_state); __raw_writel(0, port->membase + UART_MOD_CNTRL); wmb(); break; default: - serial8250_do_pm(port, state, old_state); + pm_func(port, state, old_state); break; } + + symbol_put(pm_func); } #define PORT(_base, _irq) \ -- 1.7.3.3 From ben@decadent.org.uk Sat Dec 11 21:35:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 11 Dec 2010 21:35:05 +0100 (CET) Received: from shadbolt.e.decadent.org.uk ([88.96.1.126]:50558 "EHLO shadbolt.e.decadent.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491910Ab0LKUfC (ORCPT ); Sat, 11 Dec 2010 21:35:02 +0100 Received: from [192.168.4.185] (helo=localhost) by shadbolt.decadent.org.uk with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1PRW9h-0004nR-3f; Sat, 11 Dec 2010 20:34:57 +0000 Received: from ben by localhost with local (Exim 4.72) (envelope-from ) id 1PRW9g-0002nH-KI; Sat, 11 Dec 2010 20:34:56 +0000 From: Ben Hutchings To: Ralf Baechle Cc: Namhyung Kim , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org In-Reply-To: <20101201165517.GA5560@linux-mips.org> References: <1291221282-9056-1-git-send-email-namhyung@gmail.com> <20101201165517.GA5560@linux-mips.org> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-2vJGUNZKTMiI2T/S4QNl" Date: Sat, 11 Dec 2010 20:34:56 +0000 Message-ID: <1292099696.3136.46.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 X-SA-Exim-Connect-IP: 192.168.4.185 X-SA-Exim-Mail-From: ben@decadent.org.uk Subject: Re: [PATCH] MIPS: Fix build failure on mips_sc_is_activated() X-SA-Exim-Version: 4.2.1 (built Wed, 25 Jun 2008 17:14:11 +0000) X-SA-Exim-Scanned: Yes (on shadbolt.decadent.org.uk) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28636 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ben@decadent.org.uk Precedence: bulk X-list: linux-mips --=-2vJGUNZKTMiI2T/S4QNl Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2010-12-01 at 16:55 +0000, Ralf Baechle wrote: > On Thu, Dec 02, 2010 at 01:34:42AM +0900, Namhyung Kim wrote: >=20 > > The commit ea31a6b20371 ("MIPS: Honor L2 bypass bit") breaks > > malta build as follows. Looks like not compile-tested :( >=20 > Already fixed in the linux-mips git tree by an identical patch in > commit 9a3475880131752d3d78ac25516fd3eab3fca871. >=20 > Thanks anyway! This isn't in Linus's tree yet; please ask him to pull it in time for 2.6.37. Ben. --=20 Ben Hutchings Once a job is fouled up, anything done to improve it makes it worse. --=-2vJGUNZKTMiI2T/S4QNl Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIVAwUATQPga+e/yOyVhhEJAQJstg/+PaQfDbvpEoEPGWBdQaVuoPUPdmbrzKrN E0TYmeKD9S+B/YcvTgMB/moprKyjkuHuG+1Az4IUDlMvuyEg5nzDocd5LWoBqB1Y pkMLb8BurcMwD2rS192MlkSjgEfJolwyiusGzw4mu2YUKnrMfqbAZNymLQoSFVWz ytN2wBQlQ5D0MfFIgncY9f9J70TiAZkMeBVFOgfBJWKj3c8lRWXQVbFjBbI7Spmd E/d/2j76XQrb2sJRWCNRIr+ZRsDqiPJIDI8pRbveAZCtXKPXg8/mi1iVNq1XOsG+ CaDdos+U9vfgl+/2djF65nWcX8xQW4ls2+5Fkbv5eN8Po/Bqil8wRYfdrnYD5398 49ufElAs6YypenoaqLP17pvVij62y1DftuvHui5I2SlFCrwSUYrz6ckQvmPFjx0i VfRCgonwPtSn5Sse5udmwmUScr+ZHcZL4jr/irg3xD5k87my6TOh4nttsdHR0upo 4pRiIuQbEqSp64GX94DpmnT7wiEwWMtL+MdrUspIst0wP4HERRGlxJbjViRML7A3 CSUg4iA8Xn9W944Xo24Q3PxniSWMs/zD4/KM16r+K/LdLLcRLh5uUeyqR9M7IRmc 2tbRxyKBBZeRx+8SEzxUhWoEPzhmhUDoRRGI377R923s3B0LYDWAR23JN42e9x0V NBePjmAZLJc= =o547 -----END PGP SIGNATURE----- --=-2vJGUNZKTMiI2T/S4QNl-- From das.asutosh@gmail.com Sun Dec 12 14:04:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 12 Dec 2010 14:04:35 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:35225 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491173Ab0LLNEc (ORCPT ); Sun, 12 Dec 2010 14:04:32 +0100 Received: by wyf22 with SMTP id 22so5021707wyf.36 for ; Sun, 12 Dec 2010 05:04:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=CGOkekYRzU8rSMcVyzD4qicQ4V+UW6oJBOYgDlx1Vfs=; b=oMM9tkUGaYLZtKluPa5VGWAhXPx+e7oYfdJDYweCpsiIISrVn28bWd1/sy+VksRAtf qIew5Q2U0pyBEbNrpkLgyHXK2CGicyqOQfd4FZo0J3qApeJT2SnLoSxBcw+SnaNBouYv GNNgI7nwj85UI6cPcGBtew5O+QGLefqpGilxw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=G7IjUIw6pN+7VfFgpw/PWu0H3r2Fbxnt1d/pFjqPDgnU8jwZWHVqFTbRxDov/xP/7/ VsNc2wTU+2K38GH26gGaEjf+tUsApVGW4ljecBBqmMjTXB+Cn1f17EAJ8Zm9oHyqpGUs A+7eBS8ouF1kKjzW3eu2YmycEM58vCduRp6xY= MIME-Version: 1.0 Received: by 10.216.3.144 with SMTP id 16mr1980023weh.45.1292159066773; Sun, 12 Dec 2010 05:04:26 -0800 (PST) Received: by 10.216.157.146 with HTTP; Sun, 12 Dec 2010 05:04:26 -0800 (PST) Date: Sun, 12 Dec 2010 18:34:26 +0530 Message-ID: Subject: Re MIPS-DSP-ASE Instructions From: Asutosh Das To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28638 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: das.asutosh@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1212 Lines: 35 Hi , We are trying to use the MIPS-DSP-ASE instructions to extract bits from a bit-stream. The version is MIPS-32 rev 1. (Little Endian) (Linux 2.6.30.9) The problem is that, the extp and its variants extract the bits from left-most i.e. MSB. So each time we have to load to the accumulator, we have to reverse the stream and then load, and extract and then reverse. This in-turn is reducing the perfomance rather than increasing it. For instance, Stream -> 111011011 extract 3-bits in C code => 011 (x = (unsigned) stream& ((1<<3 )-1) ) Load this stream to accumulator and extract 3 bits => 111 ==== Now reverse the stream and load to accumulator => 110110111 extract 3 bits from accumulator => 110 Now reverse the extracted bits =>011 So we have to reverse the stream before loading to the accumulator and reverse it again after extracting from accumulator which reduces the performance drastically. we guess the MIPS engineers would definitely have thought about it but we are unable to figure out a way to use these instructions without reversing the bit-streams. Please can you let us know a way to use these instructions without reversing. -- Thank you, Warm Regards, Asutosh Das # (91) 9818 4494 69 From wg@grandegger.com Mon Dec 13 21:46:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Dec 2010 21:46:54 +0100 (CET) Received: from mail-out.m-online.net ([212.18.0.9]:59852 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491773Ab0LMUqv (ORCPT ); Mon, 13 Dec 2010 21:46:51 +0100 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 262511C08DE6; Mon, 13 Dec 2010 21:46:44 +0100 (CET) X-Auth-Info: kKA9cPkVHUvQcgLi2wAfJtIYiJFFVqTOnXofG0kYWN0= Received: from lancy.mylan.de (p4FE67482.dip.t-dialin.net [79.230.116.130]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 8B8161C000B7; Mon, 13 Dec 2010 21:46:44 +0100 (CET) Message-ID: <4D06868A.4000904@grandegger.com> Date: Mon, 13 Dec 2010 21:48:10 +0100 From: Wolfgang Grandegger User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100907 Fedora/3.0.7-1.fc12 Thunderbird/3.0.7 MIME-Version: 1.0 To: "tiejun.chen" CC: Linux-MIPS Subject: Re: Can't read from mmaped PCI memory space References: <4CF2C7B1.5030007@grandegger.com> <4CF37F5D.9070709@windriver.com> <4CF3A94B.6010407@grandegger.com> <4CF3AD82.3030100@grandegger.com> In-Reply-To: <4CF3AD82.3030100@grandegger.com> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28639 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips Content-Length: 1863 Lines: 43 On 11/29/2010 02:41 PM, Wolfgang Grandegger wrote: > Hello, > > I hit the send button too early, sorry... > > On 11/29/2010 02:23 PM, Wolfgang Grandegger wrote: >> On 11/29/2010 11:24 AM, tiejun.chen wrote: >>> Wolfgang Grandegger wrote: >>>> Hello, >>>> >>>> I'm trying to read from mmapped PCI memory space on an alchemy board, >>>> but I can't get it to work. Here's the lspci output of the PCI card: >>>> >>>> bash-3.00# lspci -v >>>> 00:00.0 Class 0200: 168c:001b (rev 01) >>>> Subsystem: 168c:2063 >>>> Flags: bus master, medium devsel, latency 168, IRQ 9 >>>> Memory at 0000000040000000 (32-bit, non-prefetchable) [size=64K] >>>> Capabilities: [44] Power Management version 2 >>>> >>>> I used mmap on "/dev/mem" and "/sys/bus/pci/.../resource0", but I do not >>>> read the expected values using "*(volatile u32 *)mmap_addr" from that >>>> region. The value also changes from read to read. Reading from kernel >>>> space just work fine. Am I doing something illegal? Any idea why it does >>>> not work? >>> >>> Form here I'm not sure how you did exactly. >>> >>> Theoretically, you can mmap() directly that at least from the sys resource. But >>> I think you have to notice the aligning requirement for a page. I means you >>> should firstly map one given base_address & ~(PAGE_SIZE - 1). Then access the >>> last destination address with adding the corresponding offset as you want. > > I'm aware of the alignment issue. Anyway, I'm mapping the above address, > which is already aligned. It must be something else. I'm using the > ath_info and devmem2 Program for testing. It's an issue with 64-bit address mapping. Currently mmap tries to map 0x4000'0000 but the physical address of the PCI memory space on my CPU is 0x4'4000'0000. I wonder why this problem has not yet been discovered. The attached patch below works for my board. Wolfgang. From 97fa0ab2beb1817785d017621ba2b6910006ed25 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Mon, 13 Dec 2010 21:29:09 +0100 Subject: [PATCH] mips/pci: use pci_resource_to_user to map pci memory space properly Content-Length: 962 Lines: 33 Signed-off-by: Wolfgang Grandegger --- arch/mips/include/asm/pci.h | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 576397c..f38943b 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -82,6 +82,18 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); +#define HAVE_ARCH_PCI_RESOURCE_TO_USER + +static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, + const struct resource *rsrc, resource_size_t *start, + resource_size_t *end) +{ + phys_t size = resource_size(rsrc); + + *start = fixup_bigphys_addr(rsrc->start, size); + *end = rsrc->start + size; +} + /* * Dynamic DMA mapping stuff. * MIPS has everything mapped statically. -- 1.7.2.3 From Anoop_P.A@pmc-sierra.com Tue Dec 14 16:26:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Dec 2010 16:26:11 +0100 (CET) Received: from bby1mta03.pmc-sierra.com ([216.241.235.118]:57196 "EHLO bby1mta03.pmc-sierra.bc.ca" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491056Ab0LNP0G convert rfc822-to-8bit (ORCPT ); Tue, 14 Dec 2010 16:26:06 +0100 Received: from bby1mta03.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id 7FBFF10700B7; Tue, 14 Dec 2010 07:25:58 -0800 (PST) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (bby1exg02 [216.241.231.167]) by bby1mta03.pmc-sierra.bc.ca (Postfix) with SMTP id 6265410700B6; Tue, 14 Dec 2010 07:25:58 -0800 (PST) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.159]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.4675); Tue, 14 Dec 2010 07:25:58 -0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: SMTC support status in latest git head. Date: Tue, 14 Dec 2010 07:25:53 -0800 Message-ID: In-Reply-To: <4D012560.6020003@paralogos.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: SMTC support status in latest git head. Thread-Index: AcuX0j1PIAaj8jwdRr+Z/ybT5uUfCQDzTakg References: <4D012560.6020003@paralogos.com> From: "Anoop P.A." To: "Kevin D. Kissell" Cc: X-OriginalArrivalTime: 14 Dec 2010 15:25:58.0555 (UTC) FILETIME=[353FF6B0:01CB9BA3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28640 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips Content-Length: 16375 Lines: 433 > it ended up being cleaner and more efficient to have *some* hooks in > platform specific timer code. It was there for Malta in the kernel.org > mainline once upon a time, and I *thought* we'd propagated working code > for the initial PMC-Sierra 34K-based SoC's at least as far as [Anoop P.A.] I was able to boot 2.6.24-7 git sources with a change in cevt-r4k.c ( c0_compare_int_pending changed as following "return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP)" > linux-mips.org, but the source tree has been considerably reorganized - > there was a time when some of the hooks were under > arch/mips/mips-boards/generic, which no longer exists - and I'm not sure > where to point you. Git and grep are your friends. [Anoop P.A.]malta code has been moved to arch/mips/mti-malta/ Can you recollect the version of l-m-o kernel with a known working SMTC support ?. > > The first order of business is to break into that hung timer calibration > loop and dump the CP0 registers for the VPE and the TCs, in particular > checking the interrupt enable mask in Status against the pending > interrupts in the Cause register. If you're seeing the timer > interrupt's bit set in Cause, but clear in Status, you need to fix the > SMTC interrupt mask hook for your platform timer. [Anoop P.A.] I tried dumping registers from calibration while loop. It looks like the timer interrupt bit stay high on both cause and status register ( in my case timer interrupt is connected to Cascaded CIC interrupt which is connected to irq -6 ( C_IRQ4)). Detailed log pasted below > check to see if you're building for "tickless" operation. Tickless ends > up being really important for SMTC, and I did get it working properly > back in 2008, but I the SMTC-specific cevt-smtc.c code uses common > functions in cevt-r4k.c, and I've seen some patches to cevt-r4k.c going > by that I rather doubt were ever tested against an SMTC build/platform. > There might have been breakage there, and configuring to use a fixed > interval timer (say, 100Hz) would be a way to test that hypothesis. [Anoop P.A.] I have tried both tickles and fixed interval timer. > > Regards, > > Kevin K. [Anoop P.A.] Thanks much for your and Ralf's detailed response. > [Anoop P.A.] [ 0.000000] Writing ErrCtl register=00000000 [ 0.000000] Readback ErrCtl register=00000000 [ 0.000000] Memory: 254384k/257912k available (3062k kernel code, 3528k reserved, 648k data, 200k init, 0k highmem) [ 0.000000] Preemptable hierarchical RCU implementation. [ 0.000000] NR_IRQS:128 [ 0.000000] console [ttyS0] enabled [ 0.000000] Clock rate set to 600000000 [ 0.000000] Calibrating delay loop... === MIPS MT State Dump === [ 0.000000] -- Global State -- [ 0.000000] MVPControl Passed: 00000000 [ 0.000000] MVPControl Read: 00000000 [ 0.000000] MVPConf0 : a8008406 [ 0.000000] -- per-VPE State -- [ 0.000000] VPE 0 [ 0.000000] VPEControl : 00000000 [ 0.000000] VPEConf0 : 800f0003 [ 0.000000] VPE0.Status : 11004001 [ 0.000000] VPE0.EPC : 80100000 _stext+0x0/0x10 [ 0.000000] VPE0.Cause : 40804000 [ 0.000000] VPE0.Config7 : 00010000 [ 0.000000] VPE 1 [ 0.000000] VPEControl : 00060000 [ 0.000000] VPEConf0 : 800f0000 [ 0.000000] VPE1.Status : 00408305 [ 0.000000] VPE1.EPC : 801024e0 except_vec_vi+0x0/0x84 [ 0.000000] VPE1.Cause : 40000200 [ 0.000000] VPE1.Config7 : 00010000 [ 0.000000] -- per-TC State -- [ 0.000000] TC 0 (current TC with VPE EPC above) [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00000000 [ 0.000000] TCRestart : 8010d860 mips_mt_regdump+0x2f0/0x3c4 [ 0.000000] TCHalt : 00000000 [ 0.000000] TCContext : 00000000 [ 0.000000] TC 1 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00200001 [ 0.000000] TCRestart : 80104b64 copy_thread+0x2ac/0x2b4 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00180000 [ 0.000000] TC 2 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00400001 [ 0.000000] TCRestart : 7ffffffc 0x7ffffffc [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00300000 [ 0.000000] TC 3 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00600001 [ 0.000000] TCRestart : fff7ffae 0xfff7ffae [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00480000 [ 0.000000] TC 4 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00800001 [ 0.000000] TCRestart : f3fff7fe 0xf3fff7fe [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00600000 [ 0.000000] TC 5 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00a00001 [ 0.000000] TCRestart : 7ffffbfe 0x7ffffbfe [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00780000 [ 0.000000] TC 6 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00c00001 [ 0.000000] TCRestart : ffff7ffe 0xffff7ffe [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00900000 [ 0.000000] Counter Interrupts taken per CPU (TC) [ 0.000000] 0: 0 [ 0.000000] 1: 0 [ 0.000000] 2: 0 [ 0.000000] 3: 0 [ 0.000000] 4: 0 [ 0.000000] 5: 0 [ 0.000000] 6: 0 [ 0.000000] 7: 0 [ 0.000000] Self-IPI invocations: [ 0.000000] 0: 0 [ 0.000000] 1: 0 [ 0.000000] 2: 0 [ 0.000000] 3: 0 [ 0.000000] 4: 0 [ 0.000000] 5: 0 [ 0.000000] 6: 0 [ 0.000000] 7: 0 [ 0.000000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] 0 Recoveries of "stolen" FPU [ 0.000000] =========================== [ 0.000000] In platform cic dispatch cic_mask=0x22000 stat=0x2402000f pend=0x20000 [ 0.010000] === MIPS MT State Dump === [ 0.010000] -- Global State -- [ 0.010000] MVPControl Passed: 00000000 [ 0.010000] MVPControl Read: 00000000 [ 0.010000] MVPConf0 : a8008406 [ 0.010000] -- per-VPE State -- [ 0.010000] VPE 0 [ 0.010000] VPEControl : 00000000 [ 0.010000] VPEConf0 : 800f0003 [ 0.010000] VPE0.Status : 18004000 [ 0.010000] VPE0.EPC : 8010d900 mips_mt_regdump+0x390/0x3c4 [ 0.010000] VPE0.Cause : 40804000 [ 0.010000] VPE0.Config7 : 00010000 [ 0.010000] VPE 1 [ 0.010000] VPEControl : 00060000 [ 0.010000] VPEConf0 : 800f0000 [ 0.010000] VPE1.Status : 00408305 [ 0.010000] VPE1.EPC : 801024e0 except_vec_vi+0x0/0x84 [ 0.010000] VPE1.Cause : 40000200 [ 0.010000] VPE1.Config7 : 00010000 [ 0.010000] -- per-TC State -- [ 0.010000] TC 0 (current TC with VPE EPC above) [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00000000 [ 0.010000] TCRestart : 803f791c printk+0xc/0x30 [ 0.010000] TCHalt : 00000000 [ 0.010000] TCContext : 00000000 [ 0.010000] TC 1 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00200001 [ 0.010000] TCRestart : 80104b64 copy_thread+0x2ac/0x2b4 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00180000 [ 0.010000] TC 2 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00400001 [ 0.010000] TCRestart : 7ffffffc 0x7ffffffc [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00300000 [ 0.010000] TC 3 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00600001 [ 0.010000] TCRestart : fff7ffae 0xfff7ffae [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00480000 [ 0.010000] TC 4 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00800001 [ 0.010000] TCRestart : f3fff7fe 0xf3fff7fe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00600000 [ 0.010000] TC 5 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00a00001 [ 0.010000] TCRestart : 7ffffbfe 0x7ffffbfe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00780000 [ 0.010000] TC 6 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00c00001 [ 0.010000] TCRestart : ffff7ffe 0xffff7ffe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00900000 [ 0.010000] Counter Interrupts taken per CPU (TC) [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] 2: 0 [ 0.010000] 3: 0 [ 0.010000] 4: 0 [ 0.010000] 5: 0 [ 0.010000] 6: 0 [ 0.010000] 7: 0 [ 0.010000] Self-IPI invocations: [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] 2: 0 [ 0.010000] 3: 0 [ 0.010000] 4: 0 [ 0.010000] 5: 0 [ 0.010000] 6: 0 [ 0.010000] 7: 0 [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] 0 Recoveries of "stolen" FPU [ 0.010000] =========================== [ 0.010000] === MIPS MT State Dump === [ 0.010000] -- Global State -- [ 0.010000] MVPControl Passed: 00000000 [ 0.010000] MVPControl Read: 00000000 [ 0.010000] MVPConf0 : a8008406 [ 0.010000] -- per-VPE State -- [ 0.010000] VPE 0 [ 0.010000] VPEControl : 00000000 [ 0.010000] VPEConf0 : 800f0003 [ 0.010000] VPE0.Status : 18004000 [ 0.010000] VPE0.EPC : 8010d900 mips_mt_regdump+0x390/0x3c4 [ 0.010000] VPE0.Cause : 40804000 [ 0.010000] VPE0.Config7 : 00010000 [ 0.010000] VPE 1 [ 0.010000] VPEControl : 00060000 [ 0.010000] VPEConf0 : 800f0000 [ 0.010000] VPE1.Status : 00408305 [ 0.010000] VPE1.EPC : 801024e0 except_vec_vi+0x0/0x84 [ 0.010000] VPE1.Cause : 40000200 [ 0.010000] VPE1.Config7 : 00010000 [ 0.010000] -- per-TC State -- [ 0.010000] TC 0 (current TC with VPE EPC above) [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00000000 [ 0.010000] TCRestart : 803f791c printk+0xc/0x30 [ 0.010000] TCHalt : 00000000 [ 0.010000] TCContext : 00000000 [ 0.010000] TC 1 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00200001 [ 0.010000] TCRestart : 80104b64 copy_thread+0x2ac/0x2b4 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00180000 [ 0.010000] TC 2 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00400001 [ 0.010000] TCRestart : 7ffffffc 0x7ffffffc [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00300000 [ 0.010000] TC 3 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00600001 [ 0.010000] TCRestart : fff7ffae 0xfff7ffae [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00480000 [ 0.010000] TC 4 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00800001 [ 0.010000] TCRestart : f3fff7fe 0xf3fff7fe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00600000 [ 0.010000] TC 5 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00a00001 [ 0.010000] TCRestart : 7ffffbfe 0x7ffffbfe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00780000 [ 0.010000] TC 6 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00c00001 [ 0.010000] TCRestart : ffff7ffe 0xffff7ffe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00900000 [ 0.010000] Counter Interrupts taken per CPU (TC) [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] 2: 0 [ 0.010000] 3: 0 [ 0.010000] 4: 0 [ 0.010000] 5: 0 [ 0.010000] 6: 0 [ 0.010000] 7: 0 [ 0.010000] Self-IPI invocations: [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] 2: 0 [ 0.010000] 3: 0 [ 0.010000] 4: 0 [ 0.010000] 5: 0 [ 0.010000] 6: 0 [ 0.010000] 7: 0 [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] 0 Recoveries of "stolen" FPU [ 0.010000] =========================== [ 0.010000] === MIPS MT State Dump === [ 0.010000] -- Global State -- [ 0.010000] MVPControl Passed: 00000000 [ 0.010000] MVPControl Read: 00000000 [ 0.010000] MVPConf0 : a8008406 [ 0.010000] -- per-VPE State -- [ 0.010000] VPE 0 [ 0.010000] VPEControl : 00000000 [ 0.010000] VPEConf0 : 800f0003 [ 0.010000] VPE0.Status : 18004000 [ 0.010000] VPE0.EPC : 8010d900 mips_mt_regdump+0x390/0x3c4 [ 0.010000] VPE0.Cause : 40804000 [ 0.010000] VPE0.Config7 : 00010000 [ 0.010000] VPE 1 [ 0.010000] VPEControl : 00060000 [ 0.010000] VPEConf0 : 800f0000 [ 0.010000] VPE1.Status : 00408305 [ 0.010000] VPE1.EPC : 801024e0 except_vec_vi+0x0/0x84 [ 0.010000] VPE1.Cause : 40000200 [ 0.010000] VPE1.Config7 : 00010000 [ 0.010000] -- per-TC State -- [ 0.010000] TC 0 (current TC with VPE EPC above) [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00000000 [ 0.010000] TCRestart : 803f791c printk+0xc/0x30 [ 0.010000] TCHalt : 00000000 [ 0.010000] TCContext : 00000000 [ 0.010000] TC 1 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00200001 [ 0.010000] TCRestart : 80104b64 copy_thread+0x2ac/0x2b4 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00180000 [ 0.010000] TC 2 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00400001 [ 0.010000] TCRestart : 7ffffffc 0x7ffffffc [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00300000 [ 0.010000] TC 3 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00600001 [ 0.010000] TCRestart : fff7ffae 0xfff7ffae [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00480000 [ 0.010000] TC 4 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00800001 [ 0.010000] TCRestart : f3fff7fe 0xf3fff7fe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00600000 [ 0.010000] TC 5 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00a00001 [ 0.010000] TCRestart : 7ffffbfe 0x7ffffbfe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00780000 [ 0.010000] TC 6 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00c00001 [ 0.010000] TCRestart : ffff7ffe 0xffff7ffe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00900000 [ 0.010000] Counter Interrupts taken per CPU (TC) [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] 2: 0 [ 0.010000] 3: 0 [ 0.010000] 4: 0 [ 0.010000] 5: 0 [ 0.010000] 6: 0 [ 0.010000] 7: 0 [ 0.010000] Self-IPI invocations: [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] 2: 0 [ 0.010000] 3: 0 [ 0.010000] 4: 0 [ 0.010000] 5: 0 [ 0.010000] 6: 0 [ 0.010000] 7: 0 [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] 0 Recoveries of "stolen" FPU From kevink@paralogos.com Tue Dec 14 19:33:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Dec 2010 19:33:30 +0100 (CET) Received: from gateway08.websitewelcome.com ([67.18.34.19]:52914 "HELO gateway08.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491814Ab0LNSdE (ORCPT ); Tue, 14 Dec 2010 19:33:04 +0100 Received: (qmail 32079 invoked from network); 14 Dec 2010 18:32:39 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway08.websitewelcome.com with SMTP; 14 Dec 2010 18:32:39 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=vtZI1tCCt1neVqXSmcX5zvbVpeOvjaTGFsCE0C7MWkMrD6H4Tl1+Yu9a8jzVQE9DMdjPGLGM29lJj6cJa/7y3Niiab6HfH356MD3Q18CTf5G6Thl7o1fIlTy429dTcay; Received: from [216.239.45.4] (port=33776 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1PSZgH-00054z-AU; Tue, 14 Dec 2010 12:32:57 -0600 Message-ID: <4D07B859.2020805@paralogos.com> Date: Tue, 14 Dec 2010 10:32:57 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: "Anoop P.A." CC: linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <4D012560.6020003@paralogos.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28641 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 20129 Lines: 490 Between your mailer and mine (Thunderbird 3.1 on Ubuntu), the quoting has become something of a dogs breakfast, so let me just lay things out here as best I can. I can't comment on your tweak to 2.6.24.7 without seeing it as a patch diff. I am no longer associated with MIPS Technologies and no longer have access to my email archives from that period. If I did, I could tell you which LMO kernel version(s) had SMTC working "out of the box". There definitely was at least one, and I commented on it in an email. You might be able to find it in the LMO email archives, but it's possible that I only sent it to a MIPS internal mailing list. There was also a message I wrote that I had *thought* had gone to the LMO mailing list, but may have only been sent to a group of internal MIPS and customer engineers, in which I described the recommended procedure for debugging exactly this canonical problem with porting SMTC. The recommended procedure was, and remains, to isolate clock propagation problems by using command line options "maxtcs=" and "maxvpes=". First, boot your SMTC kernel with maxtcs=1 and maxvpes=1, a virtual uniprocessor. If that doesn't run, you've got some fundamental problem with support for your platform, or someone has really fundamentally broken the SMTC build somewhere. Next, try booting with maxtcs=2 and maxvpes=1, then with no constraint on maxtcs and maxvpes=1. If those fail, your problem is probably in the interrupt mask management algorithms I described. On the other hand, if you boot with maxtcs=2 and maxvpes=2, there will be only one TC per VPE and far less vulnerability to interrupt mask lockup, but you need to have cross-VPE IPI interrupts working. The preferred method of doing cross-VPE IPIs would be to use a physical interrupt input that's instantiated per-VPE and manipulable by software. Malta didn't have one, so there's the historical hack of using MIPS MT instructions to freeze the other VPE and set up a software interrupt using MTTR to the remote Cause register. The PMC-Sierra platforms did, if I recall correctly, have some kind of register that one could write to cause a real cross-VPE hardware interrupt, but I don't recall whether it got used in the SMTC port. Your dump below looks as if it comes from 2 TCs running on 2 VPEs, and that the interrupt mask issues I alluded to earlier are neither relevant nor manifest. It looks instead as if the initialization of "CPU 1" (VPE1/TC1) may not have been done properly. Under normal operation, it would be pretty rare to catch TC 1 in the exception vector dispatch code, so the first hypothesis that comes to mind is that something isn't right in the vector/handler setup, and TC 1 is stuck in an infinite exception loop, unable to handshake with TC 0 and thus locking up the system. But that's just my best guess based on limited data. Regards, Kevin K. On 12/14/10 07:25, Anoop P.A. wrote: >> it ended up being cleaner and more efficient to have *some* hooks in >> platform specific timer code. It was there for Malta in the > kernel.org >> mainline once upon a time, and I *thought* we'd propagated working > code >> for the initial PMC-Sierra 34K-based SoC's at least as far as > [Anoop P.A.] > I was able to boot 2.6.24-7 git sources with a change in cevt-r4k.c ( > c0_compare_int_pending changed as following "return (read_c0_cause()>> > cp0_compare_irq_shift)& (1ul<< CAUSEB_IP)" > >> linux-mips.org, but the source tree has been considerably reorganized > - >> there was a time when some of the hooks were under >> arch/mips/mips-boards/generic, which no longer exists - and I'm not > sure >> where to point you. Git and grep are your friends. > [Anoop P.A.]malta code has been moved to arch/mips/mti-malta/ > Can you recollect the version of l-m-o kernel with a known working SMTC > support ?. > >> The first order of business is to break into that hung timer > calibration >> loop and dump the CP0 registers for the VPE and the TCs, in particular >> checking the interrupt enable mask in Status against the pending >> interrupts in the Cause register. If you're seeing the timer >> interrupt's bit set in Cause, but clear in Status, you need to fix the >> SMTC interrupt mask hook for your platform timer. > [Anoop P.A.] > I tried dumping registers from calibration while loop. > It looks like the timer interrupt bit stay high on both cause and status > register ( in my case timer interrupt is connected to Cascaded CIC > interrupt which is connected to irq -6 ( C_IRQ4)). Detailed log pasted > below > >> check to see if you're building for "tickless" operation. Tickless > ends >> up being really important for SMTC, and I did get it working properly >> back in 2008, but I the SMTC-specific cevt-smtc.c code uses common >> functions in cevt-r4k.c, and I've seen some patches to cevt-r4k.c > going >> by that I rather doubt were ever tested against an SMTC > build/platform. >> There might have been breakage there, and configuring to use a fixed >> interval timer (say, 100Hz) would be a way to test that hypothesis. > [Anoop P.A.] I have tried both tickles and fixed interval timer. > >> Regards, >> >> Kevin K. > > [Anoop P.A.] Thanks much for your and Ralf's detailed response. > [Anoop P.A.] > [ 0.000000] Writing ErrCtl register=00000000 > [ 0.000000] Readback ErrCtl register=00000000 > [ 0.000000] Memory: 254384k/257912k available (3062k kernel code, > 3528k reserved, 648k data, 200k init, 0k highmem) > [ 0.000000] Preemptable hierarchical RCU implementation. > [ 0.000000] NR_IRQS:128 > [ 0.000000] console [ttyS0] enabled > [ 0.000000] Clock rate set to 600000000 > [ 0.000000] Calibrating delay loop... === MIPS MT State Dump === > [ 0.000000] -- Global State -- > [ 0.000000] MVPControl Passed: 00000000 > [ 0.000000] MVPControl Read: 00000000 > [ 0.000000] MVPConf0 : a8008406 > [ 0.000000] -- per-VPE State -- > [ 0.000000] VPE 0 > [ 0.000000] VPEControl : 00000000 > [ 0.000000] VPEConf0 : 800f0003 > [ 0.000000] VPE0.Status : 11004001 > [ 0.000000] VPE0.EPC : 80100000 _stext+0x0/0x10 > [ 0.000000] VPE0.Cause : 40804000 > [ 0.000000] VPE0.Config7 : 00010000 > [ 0.000000] VPE 1 > [ 0.000000] VPEControl : 00060000 > [ 0.000000] VPEConf0 : 800f0000 > [ 0.000000] VPE1.Status : 00408305 > [ 0.000000] VPE1.EPC : 801024e0 except_vec_vi+0x0/0x84 > [ 0.000000] VPE1.Cause : 40000200 > [ 0.000000] VPE1.Config7 : 00010000 > [ 0.000000] -- per-TC State -- > [ 0.000000] TC 0 (current TC with VPE EPC above) > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00000000 > [ 0.000000] TCRestart : 8010d860 mips_mt_regdump+0x2f0/0x3c4 > [ 0.000000] TCHalt : 00000000 > [ 0.000000] TCContext : 00000000 > [ 0.000000] TC 1 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00200001 > [ 0.000000] TCRestart : 80104b64 copy_thread+0x2ac/0x2b4 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00180000 > [ 0.000000] TC 2 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00400001 > [ 0.000000] TCRestart : 7ffffffc 0x7ffffffc > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00300000 > [ 0.000000] TC 3 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00600001 > [ 0.000000] TCRestart : fff7ffae 0xfff7ffae > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00480000 > [ 0.000000] TC 4 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00800001 > [ 0.000000] TCRestart : f3fff7fe 0xf3fff7fe > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00600000 > [ 0.000000] TC 5 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00a00001 > [ 0.000000] TCRestart : 7ffffbfe 0x7ffffbfe > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00780000 > [ 0.000000] TC 6 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00c00001 > [ 0.000000] TCRestart : ffff7ffe 0xffff7ffe > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00900000 > [ 0.000000] Counter Interrupts taken per CPU (TC) > [ 0.000000] 0: 0 > [ 0.000000] 1: 0 > [ 0.000000] 2: 0 > [ 0.000000] 3: 0 > [ 0.000000] 4: 0 > [ 0.000000] 5: 0 > [ 0.000000] 6: 0 > [ 0.000000] 7: 0 > [ 0.000000] Self-IPI invocations: > [ 0.000000] 0: 0 > [ 0.000000] 1: 0 > [ 0.000000] 2: 0 > [ 0.000000] 3: 0 > [ 0.000000] 4: 0 > [ 0.000000] 5: 0 > [ 0.000000] 6: 0 > [ 0.000000] 7: 0 > [ 0.000000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] 0 Recoveries of "stolen" FPU > [ 0.000000] =========================== > [ 0.000000] In platform cic dispatch cic_mask=0x22000 stat=0x2402000f > pend=0x20000 > [ 0.010000] === MIPS MT State Dump === > [ 0.010000] -- Global State -- > [ 0.010000] MVPControl Passed: 00000000 > [ 0.010000] MVPControl Read: 00000000 > [ 0.010000] MVPConf0 : a8008406 > [ 0.010000] -- per-VPE State -- > [ 0.010000] VPE 0 > [ 0.010000] VPEControl : 00000000 > [ 0.010000] VPEConf0 : 800f0003 > [ 0.010000] VPE0.Status : 18004000 > [ 0.010000] VPE0.EPC : 8010d900 mips_mt_regdump+0x390/0x3c4 > [ 0.010000] VPE0.Cause : 40804000 > [ 0.010000] VPE0.Config7 : 00010000 > [ 0.010000] VPE 1 > [ 0.010000] VPEControl : 00060000 > [ 0.010000] VPEConf0 : 800f0000 > [ 0.010000] VPE1.Status : 00408305 > [ 0.010000] VPE1.EPC : 801024e0 except_vec_vi+0x0/0x84 > [ 0.010000] VPE1.Cause : 40000200 > [ 0.010000] VPE1.Config7 : 00010000 > [ 0.010000] -- per-TC State -- > [ 0.010000] TC 0 (current TC with VPE EPC above) > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00000000 > [ 0.010000] TCRestart : 803f791c printk+0xc/0x30 > [ 0.010000] TCHalt : 00000000 > [ 0.010000] TCContext : 00000000 > [ 0.010000] TC 1 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00200001 > [ 0.010000] TCRestart : 80104b64 copy_thread+0x2ac/0x2b4 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00180000 > [ 0.010000] TC 2 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00400001 > [ 0.010000] TCRestart : 7ffffffc 0x7ffffffc > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00300000 > [ 0.010000] TC 3 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00600001 > [ 0.010000] TCRestart : fff7ffae 0xfff7ffae > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00480000 > [ 0.010000] TC 4 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00800001 > [ 0.010000] TCRestart : f3fff7fe 0xf3fff7fe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00600000 > [ 0.010000] TC 5 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00a00001 > [ 0.010000] TCRestart : 7ffffbfe 0x7ffffbfe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00780000 > [ 0.010000] TC 6 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00c00001 > [ 0.010000] TCRestart : ffff7ffe 0xffff7ffe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00900000 > [ 0.010000] Counter Interrupts taken per CPU (TC) > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] 2: 0 > [ 0.010000] 3: 0 > [ 0.010000] 4: 0 > [ 0.010000] 5: 0 > [ 0.010000] 6: 0 > [ 0.010000] 7: 0 > [ 0.010000] Self-IPI invocations: > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] 2: 0 > [ 0.010000] 3: 0 > [ 0.010000] 4: 0 > [ 0.010000] 5: 0 > [ 0.010000] 6: 0 > [ 0.010000] 7: 0 > [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] 0 Recoveries of "stolen" FPU > [ 0.010000] =========================== > [ 0.010000] === MIPS MT State Dump === > [ 0.010000] -- Global State -- > [ 0.010000] MVPControl Passed: 00000000 > [ 0.010000] MVPControl Read: 00000000 > [ 0.010000] MVPConf0 : a8008406 > [ 0.010000] -- per-VPE State -- > [ 0.010000] VPE 0 > [ 0.010000] VPEControl : 00000000 > [ 0.010000] VPEConf0 : 800f0003 > [ 0.010000] VPE0.Status : 18004000 > [ 0.010000] VPE0.EPC : 8010d900 mips_mt_regdump+0x390/0x3c4 > [ 0.010000] VPE0.Cause : 40804000 > [ 0.010000] VPE0.Config7 : 00010000 > [ 0.010000] VPE 1 > [ 0.010000] VPEControl : 00060000 > [ 0.010000] VPEConf0 : 800f0000 > [ 0.010000] VPE1.Status : 00408305 > [ 0.010000] VPE1.EPC : 801024e0 except_vec_vi+0x0/0x84 > [ 0.010000] VPE1.Cause : 40000200 > [ 0.010000] VPE1.Config7 : 00010000 > [ 0.010000] -- per-TC State -- > [ 0.010000] TC 0 (current TC with VPE EPC above) > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00000000 > [ 0.010000] TCRestart : 803f791c printk+0xc/0x30 > [ 0.010000] TCHalt : 00000000 > [ 0.010000] TCContext : 00000000 > [ 0.010000] TC 1 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00200001 > [ 0.010000] TCRestart : 80104b64 copy_thread+0x2ac/0x2b4 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00180000 > [ 0.010000] TC 2 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00400001 > [ 0.010000] TCRestart : 7ffffffc 0x7ffffffc > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00300000 > [ 0.010000] TC 3 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00600001 > [ 0.010000] TCRestart : fff7ffae 0xfff7ffae > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00480000 > [ 0.010000] TC 4 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00800001 > [ 0.010000] TCRestart : f3fff7fe 0xf3fff7fe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00600000 > [ 0.010000] TC 5 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00a00001 > [ 0.010000] TCRestart : 7ffffbfe 0x7ffffbfe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00780000 > [ 0.010000] TC 6 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00c00001 > [ 0.010000] TCRestart : ffff7ffe 0xffff7ffe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00900000 > [ 0.010000] Counter Interrupts taken per CPU (TC) > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] 2: 0 > [ 0.010000] 3: 0 > [ 0.010000] 4: 0 > [ 0.010000] 5: 0 > [ 0.010000] 6: 0 > [ 0.010000] 7: 0 > [ 0.010000] Self-IPI invocations: > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] 2: 0 > [ 0.010000] 3: 0 > [ 0.010000] 4: 0 > [ 0.010000] 5: 0 > [ 0.010000] 6: 0 > [ 0.010000] 7: 0 > [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] 0 Recoveries of "stolen" FPU > [ 0.010000] =========================== > [ 0.010000] === MIPS MT State Dump === > [ 0.010000] -- Global State -- > [ 0.010000] MVPControl Passed: 00000000 > [ 0.010000] MVPControl Read: 00000000 > [ 0.010000] MVPConf0 : a8008406 > [ 0.010000] -- per-VPE State -- > [ 0.010000] VPE 0 > [ 0.010000] VPEControl : 00000000 > [ 0.010000] VPEConf0 : 800f0003 > [ 0.010000] VPE0.Status : 18004000 > [ 0.010000] VPE0.EPC : 8010d900 mips_mt_regdump+0x390/0x3c4 > [ 0.010000] VPE0.Cause : 40804000 > [ 0.010000] VPE0.Config7 : 00010000 > [ 0.010000] VPE 1 > [ 0.010000] VPEControl : 00060000 > [ 0.010000] VPEConf0 : 800f0000 > [ 0.010000] VPE1.Status : 00408305 > [ 0.010000] VPE1.EPC : 801024e0 except_vec_vi+0x0/0x84 > [ 0.010000] VPE1.Cause : 40000200 > [ 0.010000] VPE1.Config7 : 00010000 > [ 0.010000] -- per-TC State -- > [ 0.010000] TC 0 (current TC with VPE EPC above) > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00000000 > [ 0.010000] TCRestart : 803f791c printk+0xc/0x30 > [ 0.010000] TCHalt : 00000000 > [ 0.010000] TCContext : 00000000 > [ 0.010000] TC 1 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00200001 > [ 0.010000] TCRestart : 80104b64 copy_thread+0x2ac/0x2b4 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00180000 > [ 0.010000] TC 2 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00400001 > [ 0.010000] TCRestart : 7ffffffc 0x7ffffffc > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00300000 > [ 0.010000] TC 3 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00600001 > [ 0.010000] TCRestart : fff7ffae 0xfff7ffae > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00480000 > [ 0.010000] TC 4 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00800001 > [ 0.010000] TCRestart : f3fff7fe 0xf3fff7fe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00600000 > [ 0.010000] TC 5 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00a00001 > [ 0.010000] TCRestart : 7ffffbfe 0x7ffffbfe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00780000 > [ 0.010000] TC 6 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00c00001 > [ 0.010000] TCRestart : ffff7ffe 0xffff7ffe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00900000 > [ 0.010000] Counter Interrupts taken per CPU (TC) > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] 2: 0 > [ 0.010000] 3: 0 > [ 0.010000] 4: 0 > [ 0.010000] 5: 0 > [ 0.010000] 6: 0 > [ 0.010000] 7: 0 > [ 0.010000] Self-IPI invocations: > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] 2: 0 > [ 0.010000] 3: 0 > [ 0.010000] 4: 0 > [ 0.010000] 5: 0 > [ 0.010000] 6: 0 > [ 0.010000] 7: 0 > [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] 0 Recoveries of "stolen" FPU > > > From ralf@linux-mips.org Tue Dec 14 19:50:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Dec 2010 19:50:44 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53160 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491036Ab0LNSud (ORCPT ); Tue, 14 Dec 2010 19:50:33 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oBEIoWnl011389; Tue, 14 Dec 2010 18:50:32 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oBEIoV85011376; Tue, 14 Dec 2010 18:50:31 GMT Date: Tue, 14 Dec 2010 18:50:30 +0000 From: Ralf Baechle To: "Kevin D. Kissell" Cc: "Anoop P.A." , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. Message-ID: <20101214185030.GA9930@linux-mips.org> References: <4D012560.6020003@paralogos.com> <4D07B859.2020805@paralogos.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4D07B859.2020805@paralogos.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28642 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 964 Lines: 20 On Tue, Dec 14, 2010 at 10:32:57AM -0800, Kevin D. Kissell wrote: > I am no longer associated with MIPS Technologies and no longer have > access to my email archives from that period. If I did, I could tell you > which LMO kernel version(s) had SMTC working "out of the box". There > definitely was at least one, and I commented on it in an email. You > might be able to find it in the LMO email archives, but it's possible that > I only sent it to a MIPS internal mailing list. > > There was also a message I wrote that I had *thought* had gone to > the LMO mailing list, but may have only been sent to a group of internal > MIPS and customer engineers, in which I described the recommended > procedure for debugging exactly this canonical problem with porting > SMTC. git bisect to the rescue :) It's time consuming with a slow machine but perfectly doable. Go back, find some antique kernel version with functioning SMTC and take it from there. Ralf From stuart.venters@adtran.com Tue Dec 14 22:28:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Dec 2010 22:28:32 +0100 (CET) Received: from p02c12o141.mxlogic.net ([208.65.145.74]:34833 "EHLO p02c12o141.mxlogic.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491814Ab0LNV2Z convert rfc822-to-8bit (ORCPT ); Tue, 14 Dec 2010 22:28:25 +0100 Received: from unknown [76.164.174.83] (EHLO p02c12o141.mxlogic.net) by p02c12o141.mxlogic.net(mxl_mta-6.8.0-0) with ESMTP id 971e70d4.68894940.10995.00-594.23818.p02c12o141.mxlogic.net (envelope-from ); Tue, 14 Dec 2010 14:28:25 -0700 (MST) X-MXL-Hash: 4d07e179432a1c87-d379005a6eca0f917707264dd94984ddb625cfb6 Received: from unknown [76.164.174.83] by p02c12o141.mxlogic.net(mxl_mta-6.8.0-0) with SMTP id 071e70d4.0.10764.00-354.23643.p02c12o141.mxlogic.net (envelope-from ); Tue, 14 Dec 2010 14:28:16 -0700 (MST) X-MXL-Hash: 4d07e17017af04f7-6c8f06e56d39c4c8512ea8157ccf9d82a7f7841c Received: from corp-exfr2.corp.adtran.com (172.23.101.22) by ex-hc2.corp.adtran.com (172.22.50.75) with Microsoft SMTP Server id 14.1.255.0; Tue, 14 Dec 2010 15:28:10 -0600 Received: from EXV1.corp.adtran.com ([172.22.48.215]) by corp-exfr2.corp.adtran.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 14 Dec 2010 15:27:52 -0600 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-Class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: Re: SMTC support status in latest git head Date: Tue, 14 Dec 2010 15:27:51 -0600 Message-ID: <8F242B230AD6474C8E7815DE0B4982D7179FB87A@EXV1.corp.adtran.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Re: SMTC support status in latest git head Thread-Index: Acub1cNULrwAYfm5Q1CJzKro0b9CZg== From: STUART VENTERS To: CC: X-OriginalArrivalTime: 14 Dec 2010 21:27:52.0487 (UTC) FILETIME=[C3C30B70:01CB9BD5] X-Spam: [F=0.2000000000; CM=0.500; S=0.200(2010120101)] X-MAIL-FROM: X-SOURCE-IP: [76.164.174.83] X-AnalysisOut: [v=1.0 c=1 a=QDCeHUUGzXIA:10 a=BLceEmwcHowA:10 a=8nJEP1OIZ-] X-AnalysisOut: [IA:10 a=5zDNsY1we+1mvVcp/5+1jQ==:17 a=mBgF-BM1mv-uRL1zwEIA] X-AnalysisOut: [:9 a=wmUZ863uC3dQK3KFugFvsFSmS9UA:4 a=wPNLvfGTeEIA:10] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28643 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stuart.venters@adtran.com Precedence: bulk X-list: linux-mips Content-Length: 334 Lines: 17 Kevin, It turns out we are also looking at Linux SMTC support for 34kc. (For a different pmc part.) You said you remembered seeing it work on at least one version of the kernel. Could you help us find that version by bracketing the search a bit? Maybe a date and/or version range to look in. Regards, Stuart Venters Adtran From kevink@paralogos.com Wed Dec 15 00:01:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Dec 2010 00:01:14 +0100 (CET) Received: from gateway16.websitewelcome.com ([69.56.206.4]:35399 "HELO gateway16.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491036Ab0LNXBL (ORCPT ); Wed, 15 Dec 2010 00:01:11 +0100 Received: (qmail 20429 invoked from network); 14 Dec 2010 23:00:44 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway16.websitewelcome.com with SMTP; 14 Dec 2010 23:00:44 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=CKz2TKWJsn1Lhk8TTqS5SVOuhhGHojcRPKMdNLYh5AsT4HZJgAIGoAodUJcbsv+Alv71FQydP6cptxTRo0U3sVuWBxI9B6nASn68p/rcxqa1HRX857Tes4dacWOOZ1Us; Received: from [216.239.45.4] (port=4545 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1PSdrf-0000cJ-Ae; Tue, 14 Dec 2010 17:00:59 -0600 Message-ID: <4D07F72E.30608@paralogos.com> Date: Tue, 14 Dec 2010 15:01:02 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: STUART VENTERS CC: linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head References: <8F242B230AD6474C8E7815DE0B4982D7179FB87A@EXV1.corp.adtran.com> In-Reply-To: <8F242B230AD6474C8E7815DE0B4982D7179FB87A@EXV1.corp.adtran.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28644 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 1899 Lines: 44 On 12/14/10 13:27, STUART VENTERS wrote: > Kevin, > > It turns out we are also looking at Linux SMTC support for 34kc. > (For a different pmc part.) > > You said you remembered seeing it work on at least one version of the kernel. > > Could you help us find that version by bracketing the search a bit? > > Maybe a date and/or version range to look in. > There were early working versions without dyntick or interrupt affinity in the 2.6.23/24 timeframe, but as per the commit lots in linux-mips.org, I finally got the dyntick stuff working in September 2008, with the commits propagating to various git branches over the following two months. I can see that the new code was in 2.6.28.1 but not in 2.6.26.8 At some point subsequent to that, I'm pretty sure I checked out the then-latest stable version of the Malta branch and got a functional build. The last time I regression checked it was in March of 2009 at which point some infrastructure changes had broken things, which I fixed in patches posted on March 31, 2009, one which addressed a change in the semantics of CP0 access macros, and one of which fixed a name conflict. Those were committed on 3/31 and 5/14/2009, depending on the branch you look at. With those patches and only those patches on what was then the latest stable (Malta?) branch at LMO, it seemed to run OK to the limited degree I was able to have it tested. Someone else found a hole in smtc_distribute_timer() in November of 2009, and I worked with the discoverer on a very small patch committed November 13, 2009, but I never actually ran the code to test (then again, I'd never been able to drive a system into the failure it could cause). Sorry to be a little vague, but I no longer have my MIPS Linux development build or test systems, so I'm reduced to googling and searching LMO, just like anyone else. Regards, Kevin K. From anoop.pa@gmail.com Wed Dec 15 20:12:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Dec 2010 20:12:51 +0100 (CET) Received: from mail-fx0-f42.google.com ([209.85.161.42]:49808 "EHLO mail-fx0-f42.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491110Ab0LOTMr (ORCPT ); Wed, 15 Dec 2010 20:12:47 +0100 Received: by fxm11 with SMTP id 11so2254214fxm.29 for ; Wed, 15 Dec 2010 11:12:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=sh8qxYDDBIVlflyHatAxFsNIKo5Ia6iEq/WqOYJ5yXw=; b=C0GjguFnvNFXrFjPbAcO60iTgQGZbt8iXSNzoZF5msVIeLHkZ8VCI7oKYs/U/G8KTe +nf6doVQxuZ1i1Dql/didX7nQRQS8rVAHqjqnbqNN0QZHyQCku3G75mcda8ZovO4fiuZ icTXCe3d1TeeeS5rQ9D3LJObooNEwSuAwSct0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=Y5e+/1qDB80uIAbzXrv8oIVKfUeDjgg9ybRoCPsMWNRskqWSsphPU1LLtgDzIrGUBR +nKPKeu0h8KfumCo7Vx38menj7U0cuYSBIaOzjIhXW5zpIOKJzK/rWNARiEUWK5Fdc/J RLxzdTl26XtFvL74GqZwFMhimjLjDykgl05Kg= Received: by 10.223.109.203 with SMTP id k11mr7939403fap.136.1292440360365; Wed, 15 Dec 2010 11:12:40 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id n7sm589956fam.11.2010.12.15.11.12.36 (version=SSLv3 cipher=RC4-MD5); Wed, 15 Dec 2010 11:12:39 -0800 (PST) Subject: Re: SMTC support status in latest git head. From: Anoop P A To: "Kevin D. Kissell" Cc: "Anoop P.A." , linux-mips@linux-mips.org In-Reply-To: <4D07B859.2020805@paralogos.com> References: <4D012560.6020003@paralogos.com> <4D07B859.2020805@paralogos.com> Content-Type: text/plain; charset="UTF-8" Date: Thu, 16 Dec 2010 00:48:58 +0530 Message-ID: <1292440738.27399.33.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28645 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 9622 Lines: 254 On Tue, 2010-12-14 at 10:32 -0800, Kevin D. Kissell wrote: > Between your mailer and mine (Thunderbird 3.1 on Ubuntu), the quoting > has become something of a dogs breakfast, so let me just lay things out > here as best I can. I am sorry for that. With evolution it will be better I hope. > > I can't comment on your tweak to 2.6.24.7 without seeing it as a patch > diff. http://patchwork.linux-mips.org/patch/804/ I was speaking about this patch. Since my timer is connected through a cascaded CIC , It is required to check TI bit of cause register in order to ensure a timer interrupt. With above mentioned patch I was able to boot a 2.6.24-stable SMTC kernel. ( Not tested fully though ) > The recommended procedure was, and remains, to isolate clock > propagation problems by using command line options "maxtcs=" > and "maxvpes=". > > First, boot your SMTC kernel with maxtcs=1 and maxvpes=1, > a virtual uniprocessor. If that doesn't run, you've got some fundamental > problem with support for your platform, or someone has really fundamentally > broken the SMTC build somewhere. Next, try booting with maxtcs=2 > and maxvpes=1, then with no constraint on maxtcs and maxvpes=1. > If those fail, your problem is probably in the interrupt mask > management algorithms I described Even with command line maxtcs=1 and maxvpes=1 I am seeing same hung. The register dump is copied below. > Your dump below looks as if it comes from 2 TCs running on > 2 VPEs, and that the interrupt mask issues I alluded to earlier > are neither relevant nor manifest. It looks instead as if the > initialization of "CPU 1" (VPE1/TC1) may not have been done > properly. Under normal operation, it would be pretty rare to > catch TC 1 in the exception vector dispatch code, so the first > hypothesis that comes to mind is that something isn't right in > the vector/handler setup, and TC 1 is stuck in an infinite exception > loop, unable to handshake with TC 0 and thus locking up the > system. But that's just my best guess based on limited data. > > Regards, > > Kevin K. > I have tested few stable tags in git and isolated the code brake. 2.6.24-stable + patch[1] = SMTC boot success 2.6.29-stable + patch[1] = SMTC boot success 2.6.31-stable + patch[1] = SMTC boot success 2.6.32-stable + patch[1] = SMTC boot success 2.6.33-stable = SMTC boot failed 2.6.35-stable = SMTC boot failed So it looks like SMTC support got broke between 2.6.32 and 2.6.33 . Thanks and Regards, Anoop patch[1] : http://patchwork.linux-mips.org/patch/804/ #############################Log########################### 0.000000] Calibrating delay loop... === MIPS MT State Dump === [ 0.000000] -- Global State -- [ 0.000000] MVPControl Passed: 00000000 [ 0.000000] MVPControl Read: 00000000 [ 0.000000] MVPConf0 : a8008406 [ 0.000000] -- per-VPE State -- [ 0.000000] VPE 0 [ 0.000000] VPEControl : 00000000 [ 0.000000] VPEConf0 : 800f0003 [ 0.000000] VPE0.Status : 11004001 [ 0.000000] VPE0.EPC : 80100000 _stext+0x0/0x10 [ 0.000000] VPE0.Cause : 50804000 [ 0.000000] VPE0.Config7 : 00010000 [ 0.000000] VPE 1 [ 0.000000] VPEControl : 00060000 [ 0.000000] VPEConf0 : 800f0000 [ 0.000000] VPE1.Status : 00408305 [ 0.000000] VPE1.EPC : 80100380 name_to_dev_t+0x50/0x430 [ 0.000000] VPE1.Cause : 50000200 [ 0.000000] VPE1.Config7 : 00010000 [ 0.000000] -- per-TC State -- [ 0.000000] TC 0 (current TC with VPE EPC above) [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00000000 [ 0.000000] TCRestart : 8010d860 mips_mt_regdump+0x2f0/0x3c4 [ 0.000000] TCHalt : 00000000 [ 0.000000] TCContext : 00000000 [ 0.000000] TC 1 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00200001 [ 0.000000] TCRestart : 8f800020 0x8f800020 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00140000 [ 0.000000] TC 2 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00400001 [ 0.000000] TCRestart : 8f800020 0x8f800020 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00280000 [ 0.000000] TC 3 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00600001 [ 0.000000] TCRestart : 8f800020 0x8f800020 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 003c0000 [ 0.000000] TC 4 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00800001 [ 0.000000] TCRestart : 80100380 name_to_dev_t+0x50/0x430 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00500000 [ 0.000000] TC 5 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00a00001 [ 0.000000] TCRestart : 80100380 name_to_dev_t+0x50/0x430 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00640000 [ 0.000000] TC 6 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00c00001 [ 0.000000] TCRestart : 80268e00 aes_encrypt+0x10e4/0x164c [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 00780000 [ 0.000000] Counter Interrupts taken per CPU (TC) [ 0.000000] 0: 0 [ 0.000000] 1: 0 [ 0.000000] 2: 0 [ 0.000000] 3: 0 [ 0.000000] 4: 0 [ 0.000000] 5: 0 [ 0.000000] 6: 0 [ 0.000000] 7: 0 [ 0.000000] Self-IPI invocations: [ 0.000000] 0: 0 [ 0.000000] 1: 0 [ 0.000000] 2: 0 [ 0.000000] 3: 0 [ 0.000000] 4: 0 [ 0.000000] 5: 0 [ 0.000000] 6: 0 [ 0.000000] 7: 0 [ 0.000000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] 0 Recoveries of "stolen" FPU [ 0.000000] =========================== [ 0.000000] In platform cic dispatch cic_mask=0x22000 stat=0x2402000f pend=0x20000 [ 0.010000] === MIPS MT State Dump === [ 0.010000] -- Global State -- [ 0.010000] MVPControl Passed: 00000000 [ 0.010000] MVPControl Read: 00000000 [ 0.010000] MVPConf0 : a8008406 [ 0.010000] -- per-VPE State -- [ 0.010000] VPE 0 [ 0.010000] VPEControl : 00000000 [ 0.010000] VPEConf0 : 800f0003 [ 0.010000] VPE0.Status : 18004000 [ 0.010000] VPE0.EPC : 8010d900 mips_mt_regdump+0x390/0x3c4 [ 0.010000] VPE0.Cause : 40804000 [ 0.010000] VPE0.Config7 : 00010000 [ 0.010000] VPE 1 [ 0.010000] VPEControl : 00060000 [ 0.010000] VPEConf0 : 800f0000 [ 0.010000] VPE1.Status : 00408305 [ 0.010000] VPE1.EPC : 80100380 name_to_dev_t+0x50/0x430 [ 0.010000] VPE1.Cause : 50000200 [ 0.010000] VPE1.Config7 : 00010000 [ 0.010000] -- per-TC State -- [ 0.010000] TC 0 (current TC with VPE EPC above) [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00000000 [ 0.010000] TCRestart : 803f791c printk+0xc/0x30 [ 0.010000] TCHalt : 00000000 [ 0.010000] TCContext : 00000000 [ 0.010000] TC 1 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00200001 [ 0.010000] TCRestart : 8f800020 0x8f800020 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00140000 [ 0.010000] TC 2 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00400001 [ 0.010000] TCRestart : 8f800020 0x8f800020 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00280000 [ 0.010000] TC 3 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00600001 [ 0.010000] TCRestart : 8f800020 0x8f800020 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 003c0000 [ 0.010000] TC 4 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00800001 [ 0.010000] TCRestart : 80100380 name_to_dev_t+0x50/0x430 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00500000 [ 0.010000] TC 5 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00a00001 [ 0.010000] TCRestart : 80100380 name_to_dev_t+0x50/0x430 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00640000 [ 0.010000] TC 6 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00c00001 [ 0.010000] TCRestart : 80268e00 aes_encrypt+0x10e4/0x164c [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 00780000 [ 0.010000] Counter Interrupts taken per CPU (TC) [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] 2: 0 [ 0.010000] 3: 0 [ 0.010000] 4: 0 [ 0.010000] 5: 0 [ 0.010000] 6: 0 [ 0.010000] 7: 0 [ 0.010000] Self-IPI invocations: [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] 2: 0 [ 0.010000] 3: 0 [ 0.010000] 4: 0 [ 0.010000] 5: 0 [ 0.010000] 6: 0 [ 0.010000] 7: 0 [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] 0 Recoveries of "stolen" FPU [ 0.010000] =========================== From kevink@paralogos.com Wed Dec 15 20:58:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Dec 2010 20:58:46 +0100 (CET) Received: from gateway02.websitewelcome.com ([67.18.81.20]:54281 "HELO gateway02.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491826Ab0LOT6m (ORCPT ); Wed, 15 Dec 2010 20:58:42 +0100 Received: (qmail 28821 invoked from network); 15 Dec 2010 19:58:15 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway02.websitewelcome.com with SMTP; 15 Dec 2010 19:58:15 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=obGo1s4nTvDvALpKPIYPNuyheQj+ie1lvhEbp8TzSegNele3WGW740L4CAriRQcPZW9EFeXyJzT5u0yv1307gH3oYIxNyXBC37ojgIEQd6uPvuffMqxNdzvep+vga58Q; Received: from [216.239.45.4] (port=21599 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1PSxUh-0004Cq-Qi; Wed, 15 Dec 2010 13:58:36 -0600 Message-ID: <4D091DEE.60009@paralogos.com> Date: Wed, 15 Dec 2010 11:58:38 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: Anoop P A CC: "Anoop P.A." , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <4D012560.6020003@paralogos.com> <4D07B859.2020805@paralogos.com> <1292440738.27399.33.camel@paanoop1-desktop> In-Reply-To: <1292440738.27399.33.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28646 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 10167 Lines: 247 On 12/15/10 11:18, Anoop P A wrote: > On Tue, 2010-12-14 at 10:32 -0800, Kevin D. Kissell wrote: > >> I can't comment on your tweak to 2.6.24.7 without seeing it as a patch >> diff. > http://patchwork.linux-mips.org/patch/804/ I was speaking about this > patch. Since my timer is connected through a cascaded CIC , It is > required to check TI bit of cause register in order to ensure a timer > interrupt. With above mentioned patch I was able to boot a 2.6.24-stable > SMTC kernel. ( Not tested fully though ) OK, yes, of course, you'd need that patch. >> The recommended procedure was, and remains, to isolate clock >> propagation problems by using command line options "maxtcs=" >> and "maxvpes=". >> >> First, boot your SMTC kernel with maxtcs=1 and maxvpes=1, >> a virtual uniprocessor. If that doesn't run, you've got some fundamental >> problem with support for your platform, or someone has really fundamentally >> broken the SMTC build somewhere. Next, try booting with maxtcs=2 >> and maxvpes=1, then with no constraint on maxtcs and maxvpes=1. >> If those fail, your problem is probably in the interrupt mask >> management algorithms I described > Even with command line maxtcs=1 and maxvpes=1 I am seeing same hung. The > register dump is copied below. I guess what jumps out at me is that VPE0.EPC doesn't look to have changed since the very initial boot vector, as if we'd never successfully taken an exception or interrupt of any kind, prior to the NMI (I'm assuming you're getting that MT state dump by breaking in with an NMI). I'm puzzled that TC0.TCStatus is being reported as 0, when it should have a bunch of bits in common with VPE0.Status. And I'm particularly intrigued by the fact that you seem to have an interrupt bit set in Cause which is enabled in Status, with IE set and EXL/ERL clear, yet you don't seem to be getting interrupts. Do you have access to some kind of EJTAG probe for your system? > I have tested few stable tags in git and isolated the code brake. > > 2.6.24-stable + patch[1] = SMTC boot success > 2.6.29-stable + patch[1] = SMTC boot success > 2.6.31-stable + patch[1] = SMTC boot success > 2.6.32-stable + patch[1] = SMTC boot success > 2.6.33-stable = SMTC boot failed > 2.6.35-stable = SMTC boot failed > > So it looks like SMTC support got broke between 2.6.32 and 2.6.33 . That's a pretty good job of isolating the problem, and the fact that it happens even with no TC or VPE concurrency means it's not a failure of the SMTC logic per se, but that someone changed some code that's common to SMTC and "normal"/SMP operation in a way that breaks the more constrained assumptions of SMTC. > Thanks and Regards, > Anoop > > patch[1] : http://patchwork.linux-mips.org/patch/804/ > > > #############################Log########################### > 0.000000] Calibrating delay loop... === MIPS MT State Dump === > [ 0.000000] -- Global State -- > [ 0.000000] MVPControl Passed: 00000000 > [ 0.000000] MVPControl Read: 00000000 > [ 0.000000] MVPConf0 : a8008406 > [ 0.000000] -- per-VPE State -- > [ 0.000000] VPE 0 > [ 0.000000] VPEControl : 00000000 > [ 0.000000] VPEConf0 : 800f0003 > [ 0.000000] VPE0.Status : 11004001 > [ 0.000000] VPE0.EPC : 80100000 _stext+0x0/0x10 > [ 0.000000] VPE0.Cause : 50804000 > [ 0.000000] VPE0.Config7 : 00010000 > [ 0.000000] VPE 1 > [ 0.000000] VPEControl : 00060000 > [ 0.000000] VPEConf0 : 800f0000 > [ 0.000000] VPE1.Status : 00408305 > [ 0.000000] VPE1.EPC : 80100380 name_to_dev_t+0x50/0x430 > [ 0.000000] VPE1.Cause : 50000200 > [ 0.000000] VPE1.Config7 : 00010000 > [ 0.000000] -- per-TC State -- > [ 0.000000] TC 0 (current TC with VPE EPC above) > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00000000 > [ 0.000000] TCRestart : 8010d860 mips_mt_regdump+0x2f0/0x3c4 > [ 0.000000] TCHalt : 00000000 > [ 0.000000] TCContext : 00000000 > [ 0.000000] TC 1 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00200001 > [ 0.000000] TCRestart : 8f800020 0x8f800020 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00140000 > [ 0.000000] TC 2 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00400001 > [ 0.000000] TCRestart : 8f800020 0x8f800020 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00280000 > [ 0.000000] TC 3 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00600001 > [ 0.000000] TCRestart : 8f800020 0x8f800020 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 003c0000 > [ 0.000000] TC 4 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00800001 > [ 0.000000] TCRestart : 80100380 name_to_dev_t+0x50/0x430 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00500000 > [ 0.000000] TC 5 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00a00001 > [ 0.000000] TCRestart : 80100380 name_to_dev_t+0x50/0x430 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00640000 > [ 0.000000] TC 6 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00c00001 > [ 0.000000] TCRestart : 80268e00 aes_encrypt+0x10e4/0x164c > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 00780000 > [ 0.000000] Counter Interrupts taken per CPU (TC) > [ 0.000000] 0: 0 > [ 0.000000] 1: 0 > [ 0.000000] 2: 0 > [ 0.000000] 3: 0 > [ 0.000000] 4: 0 > [ 0.000000] 5: 0 > [ 0.000000] 6: 0 > [ 0.000000] 7: 0 > [ 0.000000] Self-IPI invocations: > [ 0.000000] 0: 0 > [ 0.000000] 1: 0 > [ 0.000000] 2: 0 > [ 0.000000] 3: 0 > [ 0.000000] 4: 0 > [ 0.000000] 5: 0 > [ 0.000000] 6: 0 > [ 0.000000] 7: 0 > [ 0.000000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] 0 Recoveries of "stolen" FPU > [ 0.000000] =========================== > [ 0.000000] In platform cic dispatch cic_mask=0x22000 stat=0x2402000f > pend=0x20000 > [ 0.010000] === MIPS MT State Dump === > [ 0.010000] -- Global State -- > [ 0.010000] MVPControl Passed: 00000000 > [ 0.010000] MVPControl Read: 00000000 > [ 0.010000] MVPConf0 : a8008406 > [ 0.010000] -- per-VPE State -- > [ 0.010000] VPE 0 > [ 0.010000] VPEControl : 00000000 > [ 0.010000] VPEConf0 : 800f0003 > [ 0.010000] VPE0.Status : 18004000 > [ 0.010000] VPE0.EPC : 8010d900 mips_mt_regdump+0x390/0x3c4 > [ 0.010000] VPE0.Cause : 40804000 > [ 0.010000] VPE0.Config7 : 00010000 > [ 0.010000] VPE 1 > [ 0.010000] VPEControl : 00060000 > [ 0.010000] VPEConf0 : 800f0000 > [ 0.010000] VPE1.Status : 00408305 > [ 0.010000] VPE1.EPC : 80100380 name_to_dev_t+0x50/0x430 > [ 0.010000] VPE1.Cause : 50000200 > [ 0.010000] VPE1.Config7 : 00010000 > [ 0.010000] -- per-TC State -- > [ 0.010000] TC 0 (current TC with VPE EPC above) > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00000000 > [ 0.010000] TCRestart : 803f791c printk+0xc/0x30 > [ 0.010000] TCHalt : 00000000 > [ 0.010000] TCContext : 00000000 > [ 0.010000] TC 1 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00200001 > [ 0.010000] TCRestart : 8f800020 0x8f800020 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00140000 > [ 0.010000] TC 2 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00400001 > [ 0.010000] TCRestart : 8f800020 0x8f800020 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00280000 > [ 0.010000] TC 3 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00600001 > [ 0.010000] TCRestart : 8f800020 0x8f800020 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 003c0000 > [ 0.010000] TC 4 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00800001 > [ 0.010000] TCRestart : 80100380 name_to_dev_t+0x50/0x430 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00500000 > [ 0.010000] TC 5 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00a00001 > [ 0.010000] TCRestart : 80100380 name_to_dev_t+0x50/0x430 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00640000 > [ 0.010000] TC 6 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00c00001 > [ 0.010000] TCRestart : 80268e00 aes_encrypt+0x10e4/0x164c > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 00780000 > [ 0.010000] Counter Interrupts taken per CPU (TC) > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] 2: 0 > [ 0.010000] 3: 0 > [ 0.010000] 4: 0 > [ 0.010000] 5: 0 > [ 0.010000] 6: 0 > [ 0.010000] 7: 0 > [ 0.010000] Self-IPI invocations: > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] 2: 0 > [ 0.010000] 3: 0 > [ 0.010000] 4: 0 > [ 0.010000] 5: 0 > [ 0.010000] 6: 0 > [ 0.010000] 7: 0 > [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[2]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[3]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[4]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[5]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[6]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[7]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] 0 Recoveries of "stolen" FPU > [ 0.010000] =========================== > > > From anoop.pa@gmail.com Thu Dec 16 13:57:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Dec 2010 13:57:28 +0100 (CET) Received: from mail-gw0-f41.google.com ([74.125.83.41]:59884 "EHLO mail-gw0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491922Ab0LPM5Z (ORCPT ); Thu, 16 Dec 2010 13:57:25 +0100 Received: by gwj22 with SMTP id 22so1963334gwj.28 for ; Thu, 16 Dec 2010 04:57:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=6KaOfjjuKMH0eDQ3mNIJTT+bdq7u1Vvn1yuhfA2qBsI=; b=nQ1cyGUzPkV1AikdXKnEVWxe9WdGP36pV1kCz1w2ClLDB3V73q4t4swJXwSuGULMfx uFx9Ll6Xfuui53KywcRtBg6xWpgU8osWhoPf7DTTPwoOhC9dbYUYcVrOTZzwbhUqDLOE uLpat6GIhB5/0iLhoLhDz6Ai+i7EQqwy8nSp4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=gt/ZNuqfK2MVZYeGTCG0tAQXr4k8vmZN0RRdo2z2fX5FFkQ3F1QhLi9ehpUugUkjLQ I5QfoRlg338nA3w5HZry/sVE86OxfVJ2F9oBSMijhiVRgc1Zsd78CKLfTvWjFFm/eXiQ 3XnTN5ZLtNpIngcDTkbi2u58KYaNzIbqbBj8E= Received: by 10.150.143.20 with SMTP id q20mr841592ybd.73.1292504239007; Thu, 16 Dec 2010 04:57:19 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id l4sm4687153ybj.9.2010.12.16.04.57.14 (version=SSLv3 cipher=RC4-MD5); Thu, 16 Dec 2010 04:57:16 -0800 (PST) Subject: Re: SMTC support status in latest git head. From: Anoop P A To: "Kevin D. Kissell" Cc: "Anoop P.A." , linux-mips@linux-mips.org In-Reply-To: <4D091DEE.60009@paralogos.com> References: <4D012560.6020003@paralogos.com> <4D07B859.2020805@paralogos.com> <1292440738.27399.33.camel@paanoop1-desktop> <4D091DEE.60009@paralogos.com> Content-Type: text/plain; charset="UTF-8" Date: Thu, 16 Dec 2010 18:33:47 +0530 Message-ID: <1292504627.27661.16.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28647 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 4406 Lines: 112 On Wed, 2010-12-15 at 11:58 -0800, Kevin D. Kissell wrote: > On 12/15/10 11:18, Anoop P A wrote: > >> management algorithms I described > > Even with command line maxtcs=1 and maxvpes=1 I am seeing same hung. The > > register dump is copied below. > I guess what jumps out at me is that VPE0.EPC doesn't look to have > changed since the very initial boot vector, as if we'd never successfully > taken an exception or interrupt of any kind, prior to the NMI (I'm assuming > you're getting that MT state dump by breaking in with an NMI). > I'm puzzled that TC0.TCStatus is being reported as 0, when it should > have a bunch of bits in common with VPE0.Status. And I'm particularly > intrigued by the fact that you seem to have an interrupt bit set in Cause > which is enabled in Status, with IE set and EXL/ERL clear, yet you don't > seem to be getting interrupts. > > Do you have access to some kind of EJTAG probe for your system? Unfortunately I don't have access to a working EJTAG at the moment. > > > I have tested few stable tags in git and isolated the code brake. > > > > 2.6.24-stable + patch[1] = SMTC boot success > > 2.6.29-stable + patch[1] = SMTC boot success > > 2.6.31-stable + patch[1] = SMTC boot success > > 2.6.32-stable + patch[1] = SMTC boot success > > 2.6.33-stable = SMTC boot failed > > 2.6.35-stable = SMTC boot failed > > > > So it looks like SMTC support got broke between 2.6.32 and 2.6.33 . > That's a pretty good job of isolating the problem, and the fact > that it happens even with no TC or VPE concurrency means it's > not a failure of the SMTC logic per se, but that someone changed > some code that's common to SMTC and "normal"/SMP operation > in a way that breaks the more constrained assumptions of SMTC. > I have tried digging diff between 2.6.32 and 2.6.33 but I couldn't spot any likely causes. I forgot to mention that I can boot newer kernels both in VSMP and UP mode. The other thing I have tried is booting kernel with pre-set lpj ( Just to test how far I can go), which lead me to a dsp exception (spurious ?) Let me know if you have any thoughts . Thanks, Anoop ################# log ############# Linux version 2.6.33.7-pmc (paanoop1@paanoop1-desktop) (gcc version 4.5.1 (GCC) ) #27 SMP PREEMPT Thu Dec 16 17:49:46 IST 2010 DSPRAM0: PA=1c100000,Size=00008000,enabled UART clock set to 50000000 CPU revision is: 00019548 (MIPS 34Kc) Determined physical RAM map: memory: 00001000 @ 00000000 (reserved) memory: 000ff000 @ 00001000 (usable) memory: 00271000 @ 00100000 (reserved) memory: 0fc5a200 @ 00371000 (usable) Wasting 32 bytes for tracking 1 unused pages Zone PFN ranges: Normal 0x00000000 -> 0x0000ffcb Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0x00000000 -> 0x0000ffcb 6 available secondary CPU TC(s) PERCPU: Embedded 7 pages/cpu @81203000 s4896 r8192 d15584 u65536 pcpu-alloc: s4896 r8192 d15584 u65536 alloc=16*4096 pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64971 Kernel command line: console=ttyS0,57600 lpj=796672 PID hash table entries: 1024 (order: 0, 4096 bytes) Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes. Primary data cache 64kB, 4-way, PIPT, no aliases, linesize 32 bytes Writing ErrCtl register=00000000 Readback ErrCtl register=00000000 Memory: 255548k/259428k available (1861k kernel code, 3504k reserved, 400k data, 156k init, 0k highmem) Hierarchical RCU implementation. NR_IRQS:128 Clock rate set to 600000000 console [ttyS0] enabled Calibrating delay loop (skipped) preset value.. 398.33 BogoMIPS (lpj=796672) Mount-cache hash table entries: 512 Cpu 0 $ 0 : 00000000 10102000 00000010 00000003 $ 4 : 00000003 00000000 00000000 8f82f758 $ 8 : 00000000 00000000 00000000 00000000 $12 : 00000000 00000007 8f82301c 00000000 $16 : 8f82f758 00800b00 8035d3c0 8f830000 $20 : 80329df8 00000000 8035d3c0 80360000 $24 : 00000000 00000001 $28 : 80328000 80329ce0 8f82f868 8010d018 Hi : 0000004c Lo : 3831f4b4 epc : 8010d054 copy_thread+0x88/0x348 Not tainted ra : 8010d018 copy_thread+0x4c/0x348 Status: 10102000 KERNEL Cause : 50804068 PrId : 00019548 (MIPS 34Kc) Kernel panic - not syncing: Unexpected DSP exception From stuart.venters@adtran.com Thu Dec 16 16:39:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Dec 2010 16:39:40 +0100 (CET) Received: from p02c12o148.mxlogic.net ([208.65.145.81]:47584 "EHLO p02c12o148.mxlogic.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491984Ab0LPPjg (ORCPT ); Thu, 16 Dec 2010 16:39:36 +0100 Received: from unknown [76.164.174.83] (EHLO p02c12o148.mxlogic.net) by p02c12o148.mxlogic.net(mxl_mta-6.8.0-0) with ESMTP id 8b23a0d4.4fd11940.16581.00-596.39485.p02c12o148.mxlogic.net (envelope-from ); Thu, 16 Dec 2010 08:39:36 -0700 (MST) X-MXL-Hash: 4d0a32b8520ce80c-dfa8330b89686899b5d3fcb14d218904f17fb405 Received: from unknown [76.164.174.83] (EHLO ex-hc2.corp.adtran.com) by p02c12o148.mxlogic.net(mxl_mta-6.8.0-0) over TLS secured channel with ESMTP id 3a23a0d4.0.16449.00-346.39120.p02c12o148.mxlogic.net (envelope-from ); Thu, 16 Dec 2010 08:39:22 -0700 (MST) X-MXL-Hash: 4d0a32aa2c213941-df095f40de2c3ae2673865912ad3b5ba8ae75495 Received: from corp-exfr2.corp.adtran.com (172.23.101.22) by ex-hc2.corp.adtran.com (172.22.50.75) with Microsoft SMTP Server id 14.1.255.0; Thu, 16 Dec 2010 09:39:14 -0600 Received: from EXV1.corp.adtran.com ([172.22.48.215]) by corp-exfr2.corp.adtran.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 16 Dec 2010 09:37:51 -0600 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-Class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01CB9D37.329CD4D4" Subject: Re: SMTC support status in latest git head. Date: Thu, 16 Dec 2010 09:37:50 -0600 Message-ID: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Re: SMTC support status in latest git head. Thread-Index: AcudNzLhpdxoeFw9TESvZ+VCX95xGQ== From: STUART VENTERS To: , CC: , X-OriginalArrivalTime: 16 Dec 2010 15:37:51.0732 (UTC) FILETIME=[3329A340:01CB9D37] X-Spam: [F=0.2000000000; CM=0.500; S=0.200(2010121501)] X-MAIL-FROM: X-SOURCE-IP: [76.164.174.83] X-AnalysisOut: [v=1.0 c=1 a=fMTePymILGAA:10 a=BLceEmwcHowA:10 a=5zDNsY1we+] X-AnalysisOut: [1mvVcp/5+1jQ==:17 a=2gDGsJ0qIHAYSYq85ygA:9 a=Rm815P_HxUJB1] X-AnalysisOut: [vUu0nx3oy7OdUIA:4 a=wPNLvfGTeEIA:10 a=bz_LyBC371D_bxk66sgA] X-AnalysisOut: [:9 a=kQzYtOy80GB8jIcn57UA:7 a=Wd32qH50gXumUTYiKwDOTyR-fzEA] X-AnalysisOut: [:4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28648 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stuart.venters@adtran.com Precedence: bulk X-list: linux-mips Content-Length: 1636 Lines: 56 ------_=_NextPart_001_01CB9D37.329CD4D4 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Two other possible clues: The EVP is clear in the MVPControl register. Does this say that only VPE0, T0 gets to run? Also the EXCPT bits in VPEControl for VPE1 indicate a Gating Storage = Exception dispatch. But that seems to conflict the EVP bit above. Perhaps these are an artifact of getting to a good state to dump things = out. ------_=_NextPart_001_01CB9D37.329CD4D4 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Re: SMTC support status in latest git head.

Two other possible clues:

The EVP is clear in the MVPControl = register.
   Does this say that only = VPE0, T0 gets to run?

Also the EXCPT bits in VPEControl for = VPE1 indicate a Gating Storage Exception dispatch.
   But that seems to = conflict the EVP bit above.

Perhaps these are an artifact of = getting to a good state to dump things out.

------_=_NextPart_001_01CB9D37.329CD4D4-- From ralf@linux-mips.org Thu Dec 16 19:03:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Dec 2010 19:04:03 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42509 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492064Ab0LPSD7 (ORCPT ); Thu, 16 Dec 2010 19:03:59 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oBGI3w8x002386; Thu, 16 Dec 2010 18:03:58 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oBGI3wbl002383; Thu, 16 Dec 2010 18:03:58 GMT Date: Thu, 16 Dec 2010 18:03:57 +0000 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] LD/SD o32 macro GAS fix update Message-ID: <20101216180357.GA2293@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28649 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 92 Lines: 5 On Sun, Oct 10, 2010 at 10:42:12AM +0100, Maciej W. Rozycki wrote: Thanks applied. Ralf From ralf@linux-mips.org Thu Dec 16 19:09:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Dec 2010 19:09:17 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36274 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492064Ab0LPSJO (ORCPT ); Thu, 16 Dec 2010 19:09:14 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oBGI9AKj002549; Thu, 16 Dec 2010 18:09:11 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oBGI99Ru002547; Thu, 16 Dec 2010 18:09:09 GMT Date: Thu, 16 Dec 2010 18:09:09 +0000 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Add a CONFIG_FORCE_MAX_ZONEORDER Kconfig option. Message-ID: <20101216180909.GB2293@linux-mips.org> References: <1286833965-27484-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1286833965-27484-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28650 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 346 Lines: 11 On Mon, Oct 11, 2010 at 02:52:45PM -0700, David Daney wrote: > For huge page support with base page size of 16K or 32K, we have to > increase the MAX_ORDER so that huge pages can be allocated. I don't think a user should have to configure obscure constants like this but for the time being this will have to suffice. Applied. Thanks, Ralf From kevink@paralogos.com Thu Dec 16 19:43:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Dec 2010 19:44:01 +0100 (CET) Received: from gateway09.websitewelcome.com ([64.5.38.13]:60624 "HELO gateway09.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S2097167Ab0LPSn6 (ORCPT ); Thu, 16 Dec 2010 19:43:58 +0100 Received: (qmail 26951 invoked from network); 16 Dec 2010 18:43:16 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway09.websitewelcome.com with SMTP; 16 Dec 2010 18:43:16 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=XSLy32PfR350CXBKwP2DFAGetSFA752FFdfm8taiGKP6QjhUBtbeM7YuP1zGk2pa4oZL6mqzJGRQtOYr4Z1g1C6ra6M1K1nTtPkCiLllTBwtfNloRqmROTH6Tg69gAau; Received: from [216.239.45.4] (port=56377 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1PTInu-000100-LL; Thu, 16 Dec 2010 12:43:50 -0600 Message-ID: <4D0A5DE9.9030604@paralogos.com> Date: Thu, 16 Dec 2010 10:43:53 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: Anoop P A CC: "Anoop P.A." , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <4D012560.6020003@paralogos.com> <4D07B859.2020805@paralogos.com> <1292440738.27399.33.camel@paanoop1-desktop> <4D091DEE.60009@paralogos.com> <1292504627.27661.16.camel@paanoop1-desktop> In-Reply-To: <1292504627.27661.16.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28651 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 6173 Lines: 144 Getting back to my previous comment, the value reported for TC0's TCStatus register in the MT register dump can't be right. There are bits that are literally the same flip-flops between TCStatus and the containing VPE's Status register, and those bits are turning up different. If the reporting is wrong, then one of the underlying assumptions of the dump code must have been broken. Taking a quick look at it - which is all the time I have for it today - I note with alarm that the TCStatus value reported for the TC currently executing comes from the "flags" variable used in the local_irq_save(flags) statement at the beginning of the dump code. That historically worked, because local_irq_save(x) propagated not only the interrupt enable bit (bit 0) in x, but the entire value of Status - or TCStatus in the case of SMTC. It certainly looks as if that's no longer true. I'm pretty sure that the dump function isn't the only place where the knowledge of local_irq_save()'s implementation was exploited by SMTC code. So you look for changes to the local_irq_save() macro definitions between 2.6.32 and 2.6.33. The fact that you're blowing up on a DSP after you force an exit from the timer calibration loop might also be attributable to TCStatus is getting trashed, accidentally clearing access rights to the DSP ASE state. Honestly, just how many lines changed under arch/mips (and include/asm-mips, if it was still outside arch/mips) between 2.6.32 and 2.6.33? There simply can't be that many to review. Regards, Kevin K. On 12/16/10 05:03, Anoop P A wrote: > On Wed, 2010-12-15 at 11:58 -0800, Kevin D. Kissell wrote: >> On 12/15/10 11:18, Anoop P A wrote: >>>> management algorithms I described >>> Even with command line maxtcs=1 and maxvpes=1 I am seeing same hung. The >>> register dump is copied below. >> I guess what jumps out at me is that VPE0.EPC doesn't look to have >> changed since the very initial boot vector, as if we'd never successfully >> taken an exception or interrupt of any kind, prior to the NMI (I'm assuming >> you're getting that MT state dump by breaking in with an NMI). >> I'm puzzled that TC0.TCStatus is being reported as 0, when it should >> have a bunch of bits in common with VPE0.Status. And I'm particularly >> intrigued by the fact that you seem to have an interrupt bit set in Cause >> which is enabled in Status, with IE set and EXL/ERL clear, yet you don't >> seem to be getting interrupts. >> >> Do you have access to some kind of EJTAG probe for your system? > Unfortunately I don't have access to a working EJTAG at the moment. > >>> I have tested few stable tags in git and isolated the code brake. >>> >>> 2.6.24-stable + patch[1] = SMTC boot success >>> 2.6.29-stable + patch[1] = SMTC boot success >>> 2.6.31-stable + patch[1] = SMTC boot success >>> 2.6.32-stable + patch[1] = SMTC boot success >>> 2.6.33-stable = SMTC boot failed >>> 2.6.35-stable = SMTC boot failed >>> >>> So it looks like SMTC support got broke between 2.6.32 and 2.6.33 . >> That's a pretty good job of isolating the problem, and the fact >> that it happens even with no TC or VPE concurrency means it's >> not a failure of the SMTC logic per se, but that someone changed >> some code that's common to SMTC and "normal"/SMP operation >> in a way that breaks the more constrained assumptions of SMTC. >> > I have tried digging diff between 2.6.32 and 2.6.33 but I couldn't spot > any likely causes. > > I forgot to mention that I can boot newer kernels both in VSMP and UP > mode. > > The other thing I have tried is booting kernel with pre-set lpj ( Just > to test how far I can go), which lead me to a dsp exception (spurious ?) > > Let me know if you have any thoughts . > > Thanks, > Anoop > > ################# log ############# > > Linux version 2.6.33.7-pmc (paanoop1@paanoop1-desktop) (gcc version > 4.5.1 (GCC) ) #27 SMP PREEMPT Thu Dec 16 17:49:46 IST 2010 > DSPRAM0: PA=1c100000,Size=00008000,enabled > UART clock set to 50000000 > CPU revision is: 00019548 (MIPS 34Kc) > Determined physical RAM map: > memory: 00001000 @ 00000000 (reserved) > memory: 000ff000 @ 00001000 (usable) > memory: 00271000 @ 00100000 (reserved) > memory: 0fc5a200 @ 00371000 (usable) > Wasting 32 bytes for tracking 1 unused pages > Zone PFN ranges: > Normal 0x00000000 -> 0x0000ffcb > Movable zone start PFN for each node > early_node_map[1] active PFN ranges > 0: 0x00000000 -> 0x0000ffcb > 6 available secondary CPU TC(s) > PERCPU: Embedded 7 pages/cpu @81203000 s4896 r8192 d15584 u65536 > pcpu-alloc: s4896 r8192 d15584 u65536 alloc=16*4096 > pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 > Built 1 zonelists in Zone order, mobility grouping on. Total pages: > 64971 > Kernel command line: console=ttyS0,57600 lpj=796672 > PID hash table entries: 1024 (order: 0, 4096 bytes) > Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) > Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) > Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes. > Primary data cache 64kB, 4-way, PIPT, no aliases, linesize 32 bytes > Writing ErrCtl register=00000000 > Readback ErrCtl register=00000000 > Memory: 255548k/259428k available (1861k kernel code, 3504k reserved, > 400k data, 156k init, 0k highmem) > Hierarchical RCU implementation. > NR_IRQS:128 > Clock rate set to 600000000 > console [ttyS0] enabled > Calibrating delay loop (skipped) preset value.. 398.33 BogoMIPS > (lpj=796672) > Mount-cache hash table entries: 512 > Cpu 0 > $ 0 : 00000000 10102000 00000010 00000003 > $ 4 : 00000003 00000000 00000000 8f82f758 > $ 8 : 00000000 00000000 00000000 00000000 > $12 : 00000000 00000007 8f82301c 00000000 > $16 : 8f82f758 00800b00 8035d3c0 8f830000 > $20 : 80329df8 00000000 8035d3c0 80360000 > $24 : 00000000 00000001 > $28 : 80328000 80329ce0 8f82f868 8010d018 > Hi : 0000004c > Lo : 3831f4b4 > epc : 8010d054 copy_thread+0x88/0x348 > Not tainted > ra : 8010d018 copy_thread+0x4c/0x348 > Status: 10102000 KERNEL > Cause : 50804068 > PrId : 00019548 (MIPS 34Kc) > Kernel panic - not syncing: Unexpected DSP exception > > From kevink@paralogos.com Thu Dec 16 20:58:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Dec 2010 20:58:42 +0100 (CET) Received: from gateway06.websitewelcome.com ([69.56.195.6]:33037 "HELO gateway06.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492080Ab0LPT6j (ORCPT ); Thu, 16 Dec 2010 20:58:39 +0100 Received: (qmail 20147 invoked from network); 16 Dec 2010 19:58:51 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway06.websitewelcome.com with SMTP; 16 Dec 2010 19:58:51 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=rRw0lC6wjvqXrXzsrWH/Gmhm0PqgEJJVpCDtfvCff0IP2U1Bp+AJFm7RMHa6Tl3auz7TVNz+v3CgyMSVSjXEzg9qwxb7Y7aGPFxoA981PWrvgOG8I3RAeINYR5WICAn4; Received: from [216.239.45.4] (port=10410 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1PTJy4-0006Bf-CG; Thu, 16 Dec 2010 13:58:24 -0600 Message-ID: <4D0A6F63.8080206@paralogos.com> Date: Thu, 16 Dec 2010 11:58:27 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: STUART VENTERS CC: anoop.pa@gmail.com, linux-mips@linux-mips.org, Anoop_P.A@pmc-sierra.com Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> In-Reply-To: <4D0A677C.6040104@paralogos.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28652 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 1976 Lines: 51 Ralf tells me that this message got blocked by the LMO server due to HTML content. So here it is again, textier. On 12/16/10 11:24, Kevin D. Kissell wrote: > On 12/16/10 07:37, STUART VENTERS wrote: > > Two other possible clues: > > The EVP is clear in the MVPControl register. > Does this say that only VPE0, T0 gets to run? That's correct. In the maxtcs=1/maxvpes=1 boot state, it wouldn't matter. It's just possible that setting EVP is conditional on more than one VPE being used, but that's not the way I remember it. > Also the EXCPT bits in VPEControl for VPE1 indicate a Gating Storage Exception dispatch. > But that seems to conflict the EVP bit above. I don't have a copy of the ASE spec handy to see whether those bits have a defined power-on value, but particularly if maxvpes=1 was set at boot time, I would expect VPE1's registers to be in a partly random power-up state. > Perhaps these are an artifact of getting to a good state to dump things out. As per my previous mail, I looked at the MT register dump source, and it really does pull values directly out of registers and doesn't depend on having a sane kernel stack frame. The exceptions to that rule are the reported values for TCStatus of the executing TC, which is based on the perhaps-now-broken assumption that local_irq_save(flags) stores the *entire* pre-invocation value of the TCStatus register in the flags variable, and MVPcontrol, which is based on the assumption that dvpe() returns the pre-invocation value of MVPcontrol. Break those assumptions, and you'll get inconsistent state dumps like this, and very possibly incorrect execution. Particularly if what was done was that effectively replaces the SMTC-specific implementation of local_irq_save()/local_irq_restore() with something that uses the generic MIPS32R2 atomic interrupt enable/disable instructions. That would have been a *very* bad idea... Regards, Kevin K. From jeff.chua.linux@gmail.com Fri Dec 17 08:19:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Dec 2010 08:19:55 +0100 (CET) Received: from mail-iy0-f177.google.com ([209.85.210.177]:57379 "EHLO mail-iy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491065Ab0LQHTv (ORCPT ); Fri, 17 Dec 2010 08:19:51 +0100 Received: by iyj21 with SMTP id 21so264478iyj.36 for ; Thu, 16 Dec 2010 23:19:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=0xs1W9upc+Gtd0MIvtyRg8H1x1Ws9ACVAp4yRSVVePQ=; b=o9ec33BnuRB99OD5lLCecZqIN05gIMzlVtgXINko1/fG7buFNVwfa9TsDHZ3XOD2iw svK7Jmn+ygFlC5xNpx6upwKmZ8+Dk6csbCGGNXqO7K2VAlPTLX9UI0q53897621hGKSM 2TXVh/dlphm1zzoQYdax1GiLTvYosySWpIKIY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=V4mQlv9jyU3oUjZAXkDKGW7CmA1AEm1pRm1C4dDW7aVeF85KzpdvyEcvjdYbK9dl5s iOpV5sXjVtB2QkoSGfb3jaxpkZGH5VfrfvyEj0huRd8Ig3KT0GOpca/go6UO1cX/utLj VzsJVH5sIH1cIyo2LB63X0kn7F4VkFb6dNT3I= MIME-Version: 1.0 Received: by 10.42.180.199 with SMTP id bv7mr553134icb.119.1292570385253; Thu, 16 Dec 2010 23:19:45 -0800 (PST) Received: by 10.42.23.136 with HTTP; Thu, 16 Dec 2010 23:19:45 -0800 (PST) In-Reply-To: <20101217045016.GA19218@lucon.org> References: <20101217045016.GA19218@lucon.org> Date: Fri, 17 Dec 2010 15:19:45 +0800 Message-ID: Subject: Re: The Linux binutils 2.21.51.0.4 is released From: Jeff Chua To: "H.J. Lu" Cc: linux-gcc@vger.kernel.org, gcc@gcc.gnu.org, GNU C Library , Mat Hostetter , Warner Losh , linux-mips@linux-mips.org, Ralf Baechle , linux-vax@pergamentum.com Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28653 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jeff.chua.linux@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 382 Lines: 11 On Fri, Dec 17, 2010 at 12:50 PM, H.J. Lu wrote: > This release fixes the Linux relocatable kernel build: > http://sourceware.org/bugzilla/show_bug.cgi?id=12327 > 1. binutils-2.21.51.0.4.tar.bz2. Source code. > The primary sites for the beta Linux binutils are: > 1. http://www.kernel.org/pub/linux/devel/binutils/ Did you forget to upload it? Thanks, Jeff From kevink@paralogos.com Fri Dec 17 22:35:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Dec 2010 22:35:35 +0100 (CET) Received: from gateway04.websitewelcome.com ([69.93.164.2]:49353 "HELO gateway04.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S2097379Ab0LQVfc (ORCPT ); Fri, 17 Dec 2010 22:35:32 +0100 Received: (qmail 9674 invoked from network); 17 Dec 2010 21:35:22 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway04.websitewelcome.com with SMTP; 17 Dec 2010 21:35:22 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=q+cB42DO3C1t+cQV3gHCJJGi1AYC05Uk39XAgrDCgGbazYQmZFMcbnMrYTIhZPcAg1xxE099zOZTP2e4109wCaGIKXvCRoLkfXnK5wfexc+SYnB/kcXBaB50cew3nFnn; Received: from [216.239.45.4] (port=8020 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1PThxV-0008FO-8Y; Fri, 17 Dec 2010 15:35:25 -0600 Message-ID: <4D0BD7A0.1030504@paralogos.com> Date: Fri, 17 Dec 2010 13:35:28 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: anoop.pa@gmail.com CC: STUART VENTERS , linux-mips@linux-mips.org, Anoop_P.A@pmc-sierra.com Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> In-Reply-To: <4D0A6F63.8080206@paralogos.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28654 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 2608 Lines: 65 So, Anoop, if you get a minute for this any time in the next day or so (after which I'll have very limited net access until next year), could you please do an -mips-objdump --disassemble of your kernel image (or even just the mips-mt.o module) from a failing kernel build and post the disassembly of mips_mt_regdump()? The confirmation or refutation of the theory about local_irq_save() no longer being built correctly for SMTC would be within the first few instructions... /K. On 12/16/10 11:58, Kevin D. Kissell wrote: > Ralf tells me that this message got blocked by the LMO server due to > HTML content. > So here it is again, textier. > > On 12/16/10 11:24, Kevin D. Kissell wrote: > > On 12/16/10 07:37, STUART VENTERS wrote: > > > > Two other possible clues: > > > > The EVP is clear in the MVPControl register. > > Does this say that only VPE0, T0 gets to run? > > That's correct. In the maxtcs=1/maxvpes=1 boot state, it wouldn't > matter. It's just possible that setting EVP is conditional on more > than one VPE being used, but that's not the way I remember it. > > > Also the EXCPT bits in VPEControl for VPE1 indicate a Gating Storage > Exception dispatch. > > But that seems to conflict the EVP bit above. > > I don't have a copy of the ASE spec handy to see whether those bits > have a defined power-on value, but particularly if maxvpes=1 was set > at boot time, I would expect VPE1's registers to be in a partly random > power-up state. > > > Perhaps these are an artifact of getting to a good state to dump > things out. > > As per my previous mail, I looked at the MT register dump source, and > it really does pull values directly > out of registers and doesn't depend on having a sane kernel stack > frame. The exceptions to that rule > are the reported values for TCStatus of the executing TC, which is > based on the perhaps-now-broken > assumption that local_irq_save(flags) stores the *entire* > pre-invocation value of the TCStatus register > in the flags variable, and MVPcontrol, which is based on the > assumption that dvpe() returns the pre-invocation > value of MVPcontrol. Break those assumptions, and you'll get > inconsistent state dumps like this, > and very possibly incorrect execution. Particularly if what was done > was that effectively replaces > the SMTC-specific implementation of > local_irq_save()/local_irq_restore() with something that uses > the generic MIPS32R2 atomic interrupt enable/disable instructions. > That would have been a *very* bad idea... > > Regards, > > Kevin K. > > From anoop.pa@gmail.com Mon Dec 20 11:44:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Dec 2010 11:44:54 +0100 (CET) Received: from mail-fx0-f42.google.com ([209.85.161.42]:60938 "EHLO mail-fx0-f42.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492456Ab0LTKou convert rfc822-to-8bit (ORCPT ); Mon, 20 Dec 2010 11:44:50 +0100 Received: by fxm11 with SMTP id 11so2516573fxm.29 for ; Mon, 20 Dec 2010 02:44:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=qiyjwEQxt5n/FqAnA7IGOe8dgPX5wyP9MsJdj9PUV+4=; b=Ba4IUMkT7KrqHKtQPdX3e70Grev5hyatAqLS9ev/YZtsrgxRUAJjgalm5OW+ST3VQa JobDfkUb4IfXvyeOiJcF69yu+9lWX/PeCX/XWfKUKSJ/noJ/G+cMFVwMavmoeVBEtZzJ 6ZhPqadVQI7h2L2wfsCVxceFMifgGM6dhas+Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=GJyNy2YntT8RupdBhm1JKhu5MsZekNrFU1XzhKkmXykK3aqroCuyONPJwcFh3qj9pw J4iSHN48uVRfAb0vis3m1Ch3tT6K8oSdM2407OLaYkotEdmT+FQ7OYkEsMnF/pnhgcfB hOxBsLs7IF9XENVID0hD6B62nNhXiE/V3XXKA= MIME-Version: 1.0 Received: by 10.223.71.200 with SMTP id i8mr4458869faj.142.1292841884400; Mon, 20 Dec 2010 02:44:44 -0800 (PST) Received: by 10.223.74.136 with HTTP; Mon, 20 Dec 2010 02:44:44 -0800 (PST) In-Reply-To: <4D0BD7A0.1030504@paralogos.com> References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> <4D0BD7A0.1030504@paralogos.com> Date: Mon, 20 Dec 2010 16:14:44 +0530 Message-ID: Subject: Re: SMTC support status in latest git head. From: Anoop P A To: "Kevin D. Kissell" Cc: STUART VENTERS , linux-mips@linux-mips.org, Anoop_P.A@pmc-sierra.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28655 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 12988 Lines: 320 Hi Kevin, Please find disassembly for mips_mt_reg_dump Thanks Anoop Disassembly of section .text: 00000000 : 0: 27bdffb8 addiu sp,sp,-72 4: 00802821 move a1,a0 8: afbf0044 sw ra,68(sp) c: afbe0040 sw s8,64(sp) 10: afb7003c sw s7,60(sp) 14: afb60038 sw s6,56(sp) 18: afb50034 sw s5,52(sp) 1c: afb40030 sw s4,48(sp) 20: afb3002c sw s3,44(sp) 24: afb20028 sw s2,40(sp) 28: afb10024 sw s1,36(sp) 2c: afb00020 sw s0,32(sp) 30: 40141001 mfc0 s4,c0_tcstatus 34: 36810400 ori at,s4,0x400 38: 40811001 mtc0 at,c0_tcstatus 3c: 32940400 andi s4,s4,0x400 40: 000000c0 ehb 44: 41610001 dvpe at 48: 0020a821 move s5,at 4c: 000000c0 ehb 50: 3c020000 lui v0,0x0 54: 24420060 addiu v0,v0,96 58: 00400408 jr.hb v0 5c: 00000000 nop 60: 3c040000 lui a0,0x0 64: 24840000 addiu a0,a0,0 68: 0c000000 jal 0 6c: afa50010 sw a1,16(sp) 70: 3c040000 lui a0,0x0 74: 0c000000 jal 0 78: 24840000 addiu a0,a0,0 7c: 8fa50010 lw a1,16(sp) 80: 3c040000 lui a0,0x0 84: 0c000000 jal 0 88: 24840000 addiu a0,a0,0 8c: 3c040000 lui a0,0x0 90: 24840000 addiu a0,a0,0 94: 0c000000 jal 0 98: 02a02821 move a1,s5 9c: 40110002 mfc0 s1,c0_mvpconf0 a0: 3c040000 lui a0,0x0 a4: 02202821 move a1,s1 a8: 0c000000 jal 0 ac: 24840000 addiu a0,a0,0 b0: 3c040000 lui a0,0x0 b4: 0c000000 jal 0 b8: 24840000 addiu a0,a0,0 bc: 7e331a80 ext s3,s1,0xa,0x4 c0: 3c090000 lui t1,0x0 c4: 323100ff andi s1,s1,0xff c8: 3c080000 lui t0,0x0 cc: 3c030000 lui v1,0x0 d0: 3c1e0000 lui s8,0x0 d4: 3c170000 lui s7,0x0 d8: 3c160000 lui s6,0x0 dc: 3c0a0000 lui t2,0x0 e0: 26730001 addiu s3,s3,1 e4: 26310001 addiu s1,s1,1 e8: 00008021 move s0,zero ec: 2412ff00 li s2,-256 f0: 25290000 addiu t1,t1,0 f4: 25080000 addiu t0,t0,0 f8: 24630000 addiu v1,v1,0 fc: 27de0000 addiu s8,s8,0 100: 26f70000 addiu s7,s7,0 104: 26d60000 addiu s6,s6,0 108: 254a0000 addiu t2,t2,0 10c: 00001021 move v0,zero 110: 40040801 mfc0 a0,c0_vpecontrol 114: 00922024 and a0,a0,s2 118: 00442025 or a0,v0,a0 11c: 40840801 mtc0 a0,c0_vpecontrol 120: 000000c0 ehb 124: 41020802 mftc0 at,c0_tcbind 128: 00202021 move a0,at 12c: 24420001 addiu v0,v0,1 130: 3084000f andi a0,a0,0xf 134: 12040031 beq s0,a0,1fc 138: 0051282a slt a1,v0,s1 13c: 14a0fff4 bnez a1,110 140: 00000000 nop 144: 26100001 addiu s0,s0,1 148: 0213102a slt v0,s0,s3 14c: 1440fff0 bnez v0,110 150: 00001021 move v0,zero 154: 3c040000 lui a0,0x0 158: 24840000 addiu a0,a0,0 15c: 3c1e0000 lui s8,0x0 160: 3c170000 lui s7,0x0 164: 3c160000 lui s6,0x0 168: 3c130000 lui s3,0x0 16c: 0c000000 jal 0 170: 3c120000 lui s2,0x0 174: 00008021 move s0,zero 178: 27de0000 addiu s8,s8,0 17c: 26f70000 addiu s7,s7,0 180: 26d60000 addiu s6,s6,0 184: 26730000 addiu s3,s3,0 188: 26520000 addiu s2,s2,0 18c: 40020801 mfc0 v0,c0_vpecontrol 190: 2403ff00 li v1,-256 194: 00431024 and v0,v0,v1 198: 02021025 or v0,s0,v0 19c: 40820801 mtc0 v0,c0_vpecontrol 1a0: 000000c0 ehb 1a4: 41020802 mftc0 at,c0_tcbind 1a8: 00201821 move v1,at 1ac: 40021002 mfc0 v0,c0_tcbind 1b0: 1062003f beq v1,v0,2b0 1b4: 00000000 nop 1b8: 41020804 mftc0 at,c0_tchalt 1bc: 00201821 move v1,at 1c0: 24020001 li v0,1 1c4: 00400821 move at,v0 1c8: 41811004 mttc0 at,c0_tchalt 1cc: 41020801 mftc0 at,c0_tcstatus 1d0: 00203021 move a2,at 1d4: 3c040000 lui a0,0x0 1d8: 02002821 move a1,s0 1dc: 24840000 addiu a0,a0,0 1e0: afa3001c sw v1,28(sp) 1e4: 0c000000 jal 0 1e8: afa60010 sw a2,16(sp) 1ec: 8fa60010 lw a2,16(sp) 1f0: 8fa3001c lw v1,28(sp) 1f4: 080000b2 j 2c8 1f8: 00c02821 move a1,a2 1fc: 01202021 move a0,t1 200: 02002821 move a1,s0 204: afa3001c sw v1,28(sp) 208: afa80014 sw t0,20(sp) 20c: afa90010 sw t1,16(sp) 210: 0c000000 jal 0 214: afaa0018 sw t2,24(sp) 218: 41010801 mftc0 at,c0_vpecontrol 21c: 00202821 move a1,at 220: 8fa80014 lw t0,20(sp) 224: 0c000000 jal 0 228: 01002021 move a0,t0 22c: 41010802 mftc0 at,c0_vpeconf0 230: 00202821 move a1,at 234: 8fa3001c lw v1,28(sp) 238: 0c000000 jal 0 23c: 00602021 move a0,v1 240: 410c0800 mftc0 at,c0_status 244: 00203021 move a2,at 248: 03c02021 move a0,s8 24c: 0c000000 jal 0 250: 02002821 move a1,s0 254: 410e0800 mftc0 at,c0_epc 258: 00203021 move a2,at 25c: 410e0800 mftc0 at,c0_epc 260: 00203821 move a3,at 264: 02e02021 move a0,s7 268: 0c000000 jal 0 26c: 02002821 move a1,s0 270: 410d0800 mftc0 at,c0_cause 274: 00203021 move a2,at 278: 02c02021 move a0,s6 27c: 0c000000 jal 0 280: 02002821 move a1,s0 284: 41100807 mftc0 at,$16,7 288: 00203021 move a2,at 28c: 8faa0018 lw t2,24(sp) 290: 02002821 move a1,s0 294: 0c000000 jal 0 298: 01402021 move a0,t2 29c: 8fa3001c lw v1,28(sp) 2a0: 8fa80014 lw t0,20(sp) 2a4: 8fa90010 lw t1,16(sp) 2a8: 08000051 j 144 2ac: 8faa0018 lw t2,24(sp) 2b0: 3c040000 lui a0,0x0 2b4: 02002821 move a1,s0 2b8: 0c000000 jal 0 2bc: 24840000 addiu a0,a0,0 2c0: 00001821 move v1,zero 2c4: 02802821 move a1,s4 2c8: 03c02021 move a0,s8 2cc: 0c000000 jal 0 2d0: afa3001c sw v1,28(sp) 2d4: 41020802 mftc0 at,c0_tcbind 2d8: 00202821 move a1,at 2dc: 0c000000 jal 0 2e0: 02e02021 move a0,s7 2e4: 41020803 mftc0 at,c0_tcrestart 2e8: 00202821 move a1,at 2ec: 41020803 mftc0 at,c0_tcrestart 2f0: 00203021 move a2,at 2f4: 0c000000 jal 0 2f8: 02c02021 move a0,s6 2fc: 8fa3001c lw v1,28(sp) 300: 02602021 move a0,s3 304: 0c000000 jal 0 308: 00602821 move a1,v1 30c: 41020805 mftc0 at,c0_tccontext 310: 00202821 move a1,at 314: 0c000000 jal 0 318: 02402021 move a0,s2 31c: 8fa3001c lw v1,28(sp) 320: 14600003 bnez v1,330 324: 00001021 move v0,zero 328: 00400821 move at,v0 32c: 41811004 mttc0 at,c0_tchalt 330: 26100001 addiu s0,s0,1 334: 0211102a slt v0,s0,s1 338: 1440ff94 bnez v0,18c 33c: 00000000 nop 340: 0c000000 jal 0 344: 32b50001 andi s5,s5,0x1 348: 3c040000 lui a0,0x0 34c: 0c000000 jal 0 350: 24840000 addiu a0,a0,0 354: 12a00004 beqz s5,368 358: 32820400 andi v0,s4,0x400 35c: 41600021 evpe 360: 000000c0 ehb 364: 32820400 andi v0,s4,0x400 368: 14400003 bnez v0,378 36c: 00000000 nop 370: 0c000000 jal 0 374: 00000000 nop 378: 40011001 mfc0 at,c0_tcstatus 37c: 32940400 andi s4,s4,0x400 380: 34210400 ori at,at,0x400 384: 38210400 xori at,at,0x400 388: 0281a025 or s4,s4,at 38c: 40941001 mtc0 s4,c0_tcstatus 390: 000000c0 ehb 394: 8fbf0044 lw ra,68(sp) 398: 8fbe0040 lw s8,64(sp) 39c: 8fb7003c lw s7,60(sp) 3a0: 8fb60038 lw s6,56(sp) 3a4: 8fb50034 lw s5,52(sp) 3a8: 8fb40030 lw s4,48(sp) 3ac: 8fb3002c lw s3,44(sp) 3b0: 8fb20028 lw s2,40(sp) 3b4: 8fb10024 lw s1,36(sp) 3b8: 8fb00020 lw s0,32(sp) 3bc: 03e00008 jr ra 3c0: 27bd0048 addiu sp,sp,72 On Sat, Dec 18, 2010 at 3:05 AM, Kevin D. Kissell wrote: > So, Anoop, if you get a minute for this any time in the next day or so > (after which I'll have very limited net access until next year), could you > please do an -mips-objdump --disassemble of your kernel > image (or even just the mips-mt.o module) from a failing kernel build and > post the disassembly of mips_mt_regdump()?  The confirmation or refutation > of the theory about local_irq_save() no longer being built correctly for > SMTC would be within the first few instructions... > > /K. > > > On 12/16/10 11:58, Kevin D. Kissell wrote: >> >> Ralf tells me that this message got blocked by the LMO server due to HTML >> content. >> So here it is again, textier. >> >> On 12/16/10 11:24, Kevin D. Kissell wrote: >> > On 12/16/10 07:37, STUART VENTERS wrote: >> > >> > Two other possible clues: >> > >> > The EVP is clear in the MVPControl register. >> > Does this say that only VPE0, T0 gets to run? >> >> That's correct.  In the maxtcs=1/maxvpes=1 boot state, it wouldn't matter. >>  It's just possible that setting EVP is conditional on more than one VPE >> being used, but that's not the way I remember it. >> >> > Also the EXCPT bits in VPEControl for VPE1 indicate a Gating Storage >> > Exception dispatch. >> > But that seems to conflict the EVP bit above. >> >> I don't have a copy of the ASE spec handy to see whether those bits have a >> defined power-on value, but particularly if maxvpes=1 was set at boot time, >> I would expect VPE1's registers to be in a partly random power-up state. >> >> > Perhaps these are an artifact of getting to a good state to dump things >> > out. >> >> As per my previous mail, I looked at the MT register dump source, and it >> really does pull values directly >> out of registers and doesn't depend on having a sane kernel stack frame. >>  The exceptions to that rule >> are the reported values for TCStatus of the executing TC, which is based >> on the perhaps-now-broken >> assumption that local_irq_save(flags) stores the *entire* pre-invocation >> value of the TCStatus register >> in the flags variable, and MVPcontrol, which is based on the assumption >> that dvpe() returns the pre-invocation >> value of MVPcontrol.  Break those assumptions, and you'll get inconsistent >> state dumps like this, >> and very possibly incorrect execution.   Particularly if what was done was >> that effectively replaces >> the SMTC-specific implementation of local_irq_save()/local_irq_restore() >> with something that uses >> the generic MIPS32R2 atomic interrupt enable/disable instructions.  That >> would have been a *very* bad idea... >> >>             Regards, >> >>             Kevin K. >> >> > > From David.Daney@caviumnetworks.com Mon Dec 20 22:17:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Dec 2010 22:17:27 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19509 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492584Ab0LTVRW (ORCPT ); Mon, 20 Dec 2010 22:17:22 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 20 Dec 2010 13:18:01 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 13:18:38 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 13:18:37 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBKLHD2A020533; Mon, 20 Dec 2010 13:17:14 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBKLHD36020532; Mon, 20 Dec 2010 13:17:13 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/3] MIPS: Probe for presence of KScratch registers. Date: Mon, 20 Dec 2010 13:17:06 -0800 Message-Id: <1292879828-20493-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292879828-20493-1-git-send-email-ddaney@caviumnetworks.com> References: <1292879828-20493-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 20 Dec 2010 21:18:38.0007 (UTC) FILETIME=[77BE9C70:01CBA08B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28656 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1758 Lines: 51 Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by: David Daney --- arch/mips/include/asm/cpu-info.h | 1 + arch/mips/kernel/cpu-probe.c | 2 ++ arch/mips/kernel/proc.c | 2 ++ 3 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index b39def3..c454550 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -78,6 +78,7 @@ struct cpuinfo_mips { unsigned int watch_reg_use_cnt; /* Usable by ptrace */ #define NUM_WATCH_REGS 4 u16 watch_reg_masks[NUM_WATCH_REGS]; + unsigned int kscratch_mask; /* Usable KScratch mask. */ } __attribute__((aligned(SMP_CACHE_BYTES))); extern struct cpuinfo_mips cpu_data[]; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 68dae7b..f65d4c8 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -739,6 +739,8 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c) && cpu_has_tlb) c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; + c->kscratch_mask = (config4 >> 16) & 0xff; + return config4 & MIPS_CONF_M; } diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 26109c4..f40bd6b 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -69,6 +69,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) ); seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); + seq_printf(m, "kscratch registers\t: %d\n", + hweight8(cpu_data[n].kscratch_mask)); seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", -- 1.7.2.3 From David.Daney@caviumnetworks.com Mon Dec 20 22:17:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Dec 2010 22:17:50 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19510 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492585Ab0LTVRX (ORCPT ); Mon, 20 Dec 2010 22:17:23 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 20 Dec 2010 13:18:01 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 13:18:38 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 13:18:37 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBKLHCiX020529; Mon, 20 Dec 2010 13:17:12 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBKLHA3U020528; Mon, 20 Dec 2010 13:17:10 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 0/3] Allow processors with scratch registers to use them for TLB refill. Date: Mon, 20 Dec 2010 13:17:05 -0800 Message-Id: <1292879828-20493-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 20 Dec 2010 21:18:38.0007 (UTC) FILETIME=[77BE9C70:01CBA08B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28657 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1155 Lines: 35 The MIPS32r2 and MIPS64r2 specifications allow processors to have scratch registers in coprocessor 0. If these are present, we can use one of them to carry the current PGD and save three instructions in the TLB handlers. There are three patches: 1 - Probe for presence of scratch registers an print number found in /proc/cpuinfo. 2 - Add DINSM to uasm for use by patch 3. 3 - Convert the TLB handlers. This also involves dynamically generating tlbmiss_handler_setup_pgd, which used to be statically defined. David Daney (3): MIPS: Probe for presence of KScratch registers. MIPS: Add DINSM to uasm. MIPS: Use C0_KScratch (if present) to hold PGD pointer. arch/mips/include/asm/cpu-info.h | 1 + arch/mips/include/asm/mmu_context.h | 8 +-- arch/mips/include/asm/uasm.h | 1 + arch/mips/kernel/cpu-probe.c | 2 + arch/mips/kernel/proc.c | 2 + arch/mips/kernel/traps.c | 2 +- arch/mips/mm/tlbex.c | 110 +++++++++++++++++++++++++++++++--- arch/mips/mm/uasm.c | 11 +++- 8 files changed, 118 insertions(+), 19 deletions(-) -- 1.7.2.3 From David.Daney@caviumnetworks.com Mon Dec 20 22:18:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Dec 2010 22:18:18 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19511 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492586Ab0LTVRZ (ORCPT ); Mon, 20 Dec 2010 22:17:25 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 20 Dec 2010 13:18:07 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 13:18:44 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 13:18:44 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBKLHHq1020541; Mon, 20 Dec 2010 13:17:17 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBKLHH7Q020540; Mon, 20 Dec 2010 13:17:17 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 3/3] MIPS: Use C0_KScratch (if present) to hold PGD pointer. Date: Mon, 20 Dec 2010 13:17:08 -0800 Message-Id: <1292879828-20493-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292879828-20493-1-git-send-email-ddaney@caviumnetworks.com> References: <1292879828-20493-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 20 Dec 2010 21:18:44.0351 (UTC) FILETIME=[7B86A0F0:01CBA08B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28658 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 6301 Lines: 213 Decide at runtime to use either Context or KScratch to hold the PGD pointer. Signed-off-by: David Daney --- arch/mips/include/asm/mmu_context.h | 8 +-- arch/mips/kernel/traps.c | 2 +- arch/mips/mm/tlbex.c | 110 +++++++++++++++++++++++++++++++--- 3 files changed, 102 insertions(+), 18 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d959273..73c0d45 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -29,13 +29,7 @@ #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)) -static inline void tlbmiss_handler_setup_pgd(unsigned long pgd) -{ - /* Check for swapper_pg_dir and convert to physical address. */ - if ((pgd & CKSEG3) == CKSEG0) - pgd = CPHYSADDR(pgd); - write_c0_context(pgd << 11); -} +extern void tlbmiss_handler_setup_pgd(unsigned long pgd); #define TLBMISS_HANDLER_SETUP() \ do { \ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d42e267..0e64aec 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1631,7 +1631,6 @@ void __cpuinit per_cpu_trap_init(void) #endif /* CONFIG_MIPS_MT_SMTC */ cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; - TLBMISS_HANDLER_SETUP(); atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; @@ -1653,6 +1652,7 @@ void __cpuinit per_cpu_trap_init(void) write_c0_wired(0); } #endif /* CONFIG_MIPS_MT_SMTC */ + TLBMISS_HANDLER_SETUP(); } /* Install CPU exception handler */ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 6184f0a..2e15aa6 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -26,8 +26,10 @@ #include #include #include +#include -#include +#include +#include #include #include @@ -173,7 +175,30 @@ static struct uasm_reloc relocs[128] __cpuinitdata; static int check_for_high_segbits __cpuinitdata; #endif -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + +static unsigned int kscratch_used_mask __cpuinitdata; + +static int __cpuinit allocate_kscratch(void) +{ + int r; + unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; + + r = ffs(a); + + if (r == 0) + return -1; + + r--; /* make it zero based */ + + kscratch_used_mask |= (1 << r); + + return r; +} + +static int pgd_reg __cpuinitdata; + +#else /* !CONFIG_MIPS_PGD_C0_CONTEXT*/ /* * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, * we cannot do r3000 under these circumstances. @@ -573,13 +598,22 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ #ifdef CONFIG_MIPS_PGD_C0_CONTEXT - /* - * &pgd << 11 stored in CONTEXT [23..63]. - */ - UASM_i_MFC0(p, ptr, C0_CONTEXT); - uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */ - uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_drotr(p, ptr, ptr, 11); + if (pgd_reg != -1) { + /* pgd is in pgd_reg */ + UASM_i_MFC0(p, ptr, 31, pgd_reg); + } else { + /* + * &pgd << 11 stored in CONTEXT [23..63]. + */ + UASM_i_MFC0(p, ptr, C0_CONTEXT); + + /* Clear lower 23 bits of context. */ + uasm_i_dins(p, ptr, 0, 0, 23); + + /* 1 0 1 0 1 << 6 xkphys cached */ + uasm_i_ori(p, ptr, ptr, 0x540); + uasm_i_drotr(p, ptr, ptr, 11); + } #elif defined(CONFIG_SMP) # ifdef CONFIG_MIPS_MT_SMTC /* @@ -1017,6 +1051,55 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT +u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned; + +static void __cpuinit build_r4000_setup_pgd(void) +{ + const int a0 = 4; + const int a1 = 5; + u32 *p = tlbmiss_handler_setup_pgd; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + + memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd)); + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + pgd_reg = allocate_kscratch(); + + if (pgd_reg == -1) { + /* PGD << 11 in c0_Context */ + /* + * If it is a ckseg0 address, convert to a physical + * address. Shifting right by 29 and adding 4 will + * result in zero for these addresses. + * + */ + UASM_i_SRA(&p, a1, a0, 29); + UASM_i_ADDIU(&p, a1, a1, 4); + uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); + uasm_i_nop(&p); + uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); + uasm_l_tlbl_goaround1(&l, p); + UASM_i_SLL(&p, a0, a0, 11); + uasm_i_jr(&p, 31); + UASM_i_MTC0(&p, a0, C0_CONTEXT); + } else { + /* PGD in c0_KScratch */ + uasm_i_jr(&p, 31); + UASM_i_MTC0(&p, a0, 31, pgd_reg); + } + if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd)) + panic("tlbmiss_handler_setup_pgd space exceeded"); + uasm_resolve_relocs(relocs, labels); + pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", + (unsigned int)(p - tlbmiss_handler_setup_pgd)); + + dump_handler(tlbmiss_handler_setup_pgd, + ARRAY_SIZE(tlbmiss_handler_setup_pgd)); +} +#endif static void __cpuinit iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) @@ -1629,13 +1712,16 @@ void __cpuinit build_tlb_refill_handler(void) break; default: - build_r4000_tlb_refill_handler(); if (!run_once) { +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + build_r4000_setup_pgd(); +#endif build_r4000_tlb_load_handler(); build_r4000_tlb_store_handler(); build_r4000_tlb_modify_handler(); run_once++; } + build_r4000_tlb_refill_handler(); } } @@ -1647,4 +1733,8 @@ void __cpuinit flush_tlb_handlers(void) (unsigned long)handle_tlbs + sizeof(handle_tlbs)); local_flush_icache_range((unsigned long)handle_tlbm, (unsigned long)handle_tlbm + sizeof(handle_tlbm)); +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, + (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm)); +#endif } -- 1.7.2.3 From David.Daney@caviumnetworks.com Mon Dec 20 22:18:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Dec 2010 22:18:42 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19512 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492587Ab0LTVR0 (ORCPT ); Mon, 20 Dec 2010 22:17:26 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 20 Dec 2010 13:18:09 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 13:18:45 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 13:18:45 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBKLHGql020537; Mon, 20 Dec 2010 13:17:16 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBKLHE72020536; Mon, 20 Dec 2010 13:17:14 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/3] MIPS: Add DINSM to uasm. Date: Mon, 20 Dec 2010 13:17:07 -0800 Message-Id: <1292879828-20493-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292879828-20493-1-git-send-email-ddaney@caviumnetworks.com> References: <1292879828-20493-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 20 Dec 2010 21:18:45.0539 (UTC) FILETIME=[7C3BE730:01CBA08B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28659 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 2024 Lines: 64 Signed-off-by: David Daney --- arch/mips/include/asm/uasm.h | 1 + arch/mips/mm/uasm.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 892062d..99dae68 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -115,6 +115,7 @@ Ip_0(_tlbwr); Ip_u3u1u2(_xor); Ip_u2u1u3(_xori); Ip_u2u1msbu3(_dins); +Ip_u2u1msbu3(_dinsm); Ip_u1(_syscall); /* Handle labels. */ diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 23afdeb..99f0347 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -68,7 +68,7 @@ enum opcode { insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, - insn_dins, insn_syscall, insn_bbit0, insn_bbit1 + insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1 }; struct insn { @@ -142,6 +142,7 @@ static struct insn insn_table[] __uasminitdata = { { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, + { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, @@ -340,6 +341,13 @@ Ip_u2u1msbu3(op) \ } \ UASM_EXPORT_SYMBOL(uasm_i##op); +#define I_u2u1msb32u3(op) \ +Ip_u2u1msbu3(op) \ +{ \ + build_insn(buf, insn##op, b, a, c+d-33, c); \ +} \ +UASM_EXPORT_SYMBOL(uasm_i##op); + #define I_u1u2(op) \ Ip_u1u2(op) \ { \ @@ -422,6 +430,7 @@ I_0(_tlbwr) I_u3u1u2(_xor) I_u2u1u3(_xori) I_u2u1msbu3(_dins); +I_u2u1msb32u3(_dinsm); I_u1(_syscall); I_u1u2s3(_bbit0); I_u1u2s3(_bbit1); -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Dec 21 00:55:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 00:55:07 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4098 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492617Ab0LTXzE (ORCPT ); Tue, 21 Dec 2010 00:55:04 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 20 Dec 2010 15:55:44 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 15:56:21 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 15:56:21 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBKNsrpX012884; Mon, 20 Dec 2010 15:54:53 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBKNsqSG012883; Mon, 20 Dec 2010 15:54:52 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 0/2] MIPS: Use Octeon BBIT instructions in TLB handlers. Date: Mon, 20 Dec 2010 15:54:48 -0800 Message-Id: <1292889290-12849-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 20 Dec 2010 23:56:21.0142 (UTC) FILETIME=[80366B60:01CBA0A1] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28660 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 542 Lines: 17 Octeon has instructions that conditionally branch based on the value of any single bit in any register. We use these to reduce the number of instructions in the generated TLB handlers. This set applies on top of the recent KScratch patch set. David Daney (2): MIPS: Declare uasm bbit0 and bbit1 functions. MIPS: Use BBIT instructions in TLB handlers arch/mips/include/asm/uasm.h | 2 + arch/mips/mm/tlbex.c | 119 +++++++++++++++++++++++++++++++---------- 2 files changed, 92 insertions(+), 29 deletions(-) -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Dec 21 00:55:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 00:55:31 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4099 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492618Ab0LTXzE (ORCPT ); Tue, 21 Dec 2010 00:55:04 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 20 Dec 2010 15:55:46 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 15:56:23 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 15:56:23 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBKNsvb3012888; Mon, 20 Dec 2010 15:54:57 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBKNstqr012887; Mon, 20 Dec 2010 15:54:55 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/2] MIPS: Declare uasm bbit0 and bbit1 functions. Date: Mon, 20 Dec 2010 15:54:49 -0800 Message-Id: <1292889290-12849-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292889290-12849-1-git-send-email-ddaney@caviumnetworks.com> References: <1292889290-12849-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 20 Dec 2010 23:56:23.0236 (UTC) FILETIME=[8175F040:01CBA0A1] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28661 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 610 Lines: 24 these are already defined, but declaring them allow them to be used outside of uasm.c. Signed-off-by: David Daney --- arch/mips/include/asm/uasm.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 99dae68..d361df3 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -117,6 +117,8 @@ Ip_u2u1u3(_xori); Ip_u2u1msbu3(_dins); Ip_u2u1msbu3(_dinsm); Ip_u1(_syscall); +Ip_u1u2s3(_bbit0); +Ip_u1u2s3(_bbit1); /* Handle labels. */ struct uasm_label { -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Dec 21 00:55:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 00:55:55 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4100 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492619Ab0LTXzG (ORCPT ); Tue, 21 Dec 2010 00:55:06 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 20 Dec 2010 15:55:49 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 15:56:25 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 20 Dec 2010 15:56:25 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBKNsx6l012892; Mon, 20 Dec 2010 15:54:59 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBKNswK8012891; Mon, 20 Dec 2010 15:54:58 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/2] MIPS: Use BBIT instructions in TLB handlers Date: Mon, 20 Dec 2010 15:54:50 -0800 Message-Id: <1292889290-12849-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292889290-12849-1-git-send-email-ddaney@caviumnetworks.com> References: <1292889290-12849-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 20 Dec 2010 23:56:25.0736 (UTC) FILETIME=[82F36880:01CBA0A1] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28662 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 6605 Lines: 210 If the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they are more efficient than an AND followed by an branch and then restoring the clobbered register. Signed-off-by: David Daney --- arch/mips/mm/tlbex.c | 119 +++++++++++++++++++++++++++++++++++++------------ 1 files changed, 90 insertions(+), 29 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index cec0e1b..601f4c2 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -65,6 +65,18 @@ static inline int __maybe_unused r10000_llsc_war(void) return R10000_LLSC_WAR; } +static int use_bbit_insns(void) +{ + switch (current_cpu_type()) { + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + return 1; + default: + return 0; + } +} + /* * Found by experiment: At least some revisions of the 4kc throw under * some circumstances a machine check exception, triggered by invalid @@ -507,8 +519,12 @@ build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, unsigned int pmd, int lid) { UASM_i_LW(p, tmp, 0, pmd); - uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); - uasm_il_bnez(p, r, tmp, lid); + if (use_bbit_insns()) { + uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); + } else { + uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); + uasm_il_bnez(p, r, tmp, lid); + } } static __cpuinit void build_huge_update_entries(u32 **p, @@ -1183,14 +1199,20 @@ build_pte_present(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { if (kernel_uses_smartmips_rixi) { - uasm_i_andi(p, pte, pte, _PAGE_PRESENT); - uasm_il_beqz(p, r, pte, lid); + if (use_bbit_insns()) { + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); + uasm_i_nop(p); + } else { + uasm_i_andi(p, pte, pte, _PAGE_PRESENT); + uasm_il_beqz(p, r, pte, lid); + iPTE_LW(p, pte, ptr); + } } else { uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); uasm_il_bnez(p, r, pte, lid); + iPTE_LW(p, pte, ptr); } - iPTE_LW(p, pte, ptr); } /* Make PTE valid, store result in PTR. */ @@ -1211,10 +1233,17 @@ static void __cpuinit build_pte_writable(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { - uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); - uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); - uasm_il_bnez(p, r, pte, lid); - iPTE_LW(p, pte, ptr); + if (use_bbit_insns()) { + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); + uasm_i_nop(p); + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); + uasm_i_nop(p); + } else { + uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); + uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); + uasm_il_bnez(p, r, pte, lid); + iPTE_LW(p, pte, ptr); + } } /* Make PTE writable, update software status bits as well, then store @@ -1238,9 +1267,14 @@ static void __cpuinit build_pte_modifiable(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { - uasm_i_andi(p, pte, pte, _PAGE_WRITE); - uasm_il_beqz(p, r, pte, lid); - iPTE_LW(p, pte, ptr); + if (use_bbit_insns()) { + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); + uasm_i_nop(p); + } else { + uasm_i_andi(p, pte, pte, _PAGE_WRITE); + uasm_il_beqz(p, r, pte, lid); + iPTE_LW(p, pte, ptr); + } } #ifndef CONFIG_MIPS_PGD_C0_CONTEXT @@ -1485,14 +1519,23 @@ static void __cpuinit build_r4000_tlb_load_handler(void) * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. */ - uasm_i_andi(&p, K0, K0, _PAGE_VALID); - uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); + if (use_bbit_insns()) { + uasm_il_bbit0(&p, &r, K0, ilog2(_PAGE_VALID), + label_tlbl_goaround1); + } else { + uasm_i_andi(&p, K0, K0, _PAGE_VALID); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); + } uasm_i_nop(&p); uasm_i_tlbr(&p); /* Examine entrylo 0 or 1 based on ptr. */ - uasm_i_andi(&p, K0, K1, sizeof(pte_t)); - uasm_i_beqz(&p, K0, 8); + if (use_bbit_insns()) { + uasm_i_bbit0(&p, K1, ilog2(sizeof(pte_t)), 8); + } else { + uasm_i_andi(&p, K0, K1, sizeof(pte_t)); + uasm_i_beqz(&p, K0, 8); + } UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ @@ -1500,12 +1543,18 @@ static void __cpuinit build_r4000_tlb_load_handler(void) * If the entryLo (now in K0) is valid (bit 1), RI or * XI must have triggered it. */ - uasm_i_andi(&p, K0, K0, 2); - uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); - - uasm_l_tlbl_goaround1(&l, p); - /* Reload the PTE value */ - iPTE_LW(&p, K0, K1); + if (use_bbit_insns()) { + uasm_il_bbit1(&p, &r, K0, 1, label_nopage_tlbl); + /* Reload the PTE value */ + iPTE_LW(&p, K0, K1); + uasm_l_tlbl_goaround1(&l, p); + } else { + uasm_i_andi(&p, K0, K0, 2); + uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); + uasm_l_tlbl_goaround1(&l, p); + /* Reload the PTE value */ + iPTE_LW(&p, K0, K1); + } } build_make_valid(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); @@ -1525,23 +1574,35 @@ static void __cpuinit build_r4000_tlb_load_handler(void) * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. */ - uasm_i_andi(&p, K0, K0, _PAGE_VALID); - uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + if (use_bbit_insns()) { + uasm_il_bbit0(&p, &r, K0, ilog2(_PAGE_VALID), + label_tlbl_goaround2); + } else { + uasm_i_andi(&p, K0, K0, _PAGE_VALID); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + } uasm_i_nop(&p); uasm_i_tlbr(&p); /* Examine entrylo 0 or 1 based on ptr. */ - uasm_i_andi(&p, K0, K1, sizeof(pte_t)); - uasm_i_beqz(&p, K0, 8); - + if (use_bbit_insns()) { + uasm_i_bbit0(&p, K1, ilog2(sizeof(pte_t)), 8); + } else { + uasm_i_andi(&p, K0, K1, sizeof(pte_t)); + uasm_i_beqz(&p, K0, 8); + } UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ /* * If the entryLo (now in K0) is valid (bit 1), RI or * XI must have triggered it. */ - uasm_i_andi(&p, K0, K0, 2); - uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + if (use_bbit_insns()) { + uasm_il_bbit0(&p, &r, K0, 1, label_tlbl_goaround2); + } else { + uasm_i_andi(&p, K0, K0, 2); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + } /* Reload the PTE value */ iPTE_LW(&p, K0, K1); -- 1.7.2.3 From anoop.pa@gmail.com Tue Dec 21 11:59:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 11:59:29 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:39111 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492700Ab0LUK7U (ORCPT ); Tue, 21 Dec 2010 11:59:20 +0100 Received: by ywf7 with SMTP id 7so1939898ywf.36 for ; Tue, 21 Dec 2010 02:59:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=vtY+GgjHX9GSQPyTN5d5SSo6e3M7Bs1SOY7kUSWN+Rc=; b=K5AHZku0VllkufVTZ+LT9tonw4IN5KSJ5x0U7Ilj7tgfCq+gSAdZw9LOq4LKbWookQ mjMZdAh+Ksdyq1GD8RCDD71cwy0i4JpHdhR92el+fmA3t/Xxp1j2DyYXxmmf0iHnUYcL X21ce9GONpBIQCiilzTTxaTu8cYbBbnZthJAA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=nJIjTN2eLyaOz5YGiQU/7ENJpyIHfakQIuGVDmSLg/e70Ja7FPd0+p7mUIpjFN4o9W 3z1exqhnhHFE1tXwu3IGlYe7wvJ7My7ZXoiOlosF+dzqZE6d/WqEy4LKh1EdWO2NJmfx F+TJMEZwuTQpQv0xI1YOVQpYByqDrDgCmyFBM= Received: by 10.100.108.19 with SMTP id g19mr1582146anc.123.1292929153795; Tue, 21 Dec 2010 02:59:13 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id x36sm9592611anx.34.2010.12.21.02.59.06 (version=SSLv3 cipher=RC4-MD5); Tue, 21 Dec 2010 02:59:12 -0800 (PST) From: Anoop P To: Ralf Baechle , gregkh@suse.de, dbrownell@users.sourceforge.net, stern@rowland.harvard.edu, sarah.a.sharp@linux.intel.com, andiry.xu@amd.com, agust@denx.de, ddaney@caviumnetworks.com, gadiyar@ti.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Cc: Anoop P A Subject: [PATCH] EHCI support for on-chip PMC MSP USB controller. Date: Tue, 21 Dec 2010 16:36:20 +0530 Message-Id: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28663 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 37419 Lines: 1240 From: Anoop P A This patch includes. 1. USB host driver for MSP71xx family SoC on-chip USB controller. 2. Platform support for USB controller. Signed-off-by: Anoop P A --- .../mips/include/asm/pmc-sierra/msp71xx/msp_regs.h | 17 +- arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h | 144 +++++ arch/mips/pmc-sierra/Kconfig | 8 + arch/mips/pmc-sierra/msp71xx/Makefile | 2 +- arch/mips/pmc-sierra/msp71xx/msp_usb.c | 239 +++++++--- drivers/usb/core/hub.c | 31 ++ drivers/usb/host/Kconfig | 15 +- drivers/usb/host/ehci-hcd.c | 12 + drivers/usb/host/ehci-pmcmsp.c | 555 ++++++++++++++++++++ 9 files changed, 949 insertions(+), 74 deletions(-) create mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h create mode 100644 drivers/usb/host/ehci-pmcmsp.c diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h index 603eb73..692c1b6 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h @@ -91,12 +91,10 @@ /* MAC C device registers */ #define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) /* ADSL2 device registers */ -#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) - /* USB device registers */ -#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) - /* USB device registers */ -#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF) - /* USB device registers */ +#define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000) + /* USB0 device registers */ +#define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000) + /* USB1 device registers */ #define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) /* CPU interface registers */ @@ -319,8 +317,11 @@ #define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) /* CPU/SLP Error status 1 */ -#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) - /* Extended GPIO register */ +/* Extended GPIO registers */ +#define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188) +#define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c) +#define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG + /* Backward-compatibility */ /* System Error registers */ #define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h new file mode 100644 index 0000000..4c9348d --- /dev/null +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h @@ -0,0 +1,144 @@ +/****************************************************************** + * Copyright (c) 2000-2007 PMC-Sierra INC. + * + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + * + * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS + * SOFTWARE. + */ +#ifndef MSP_USB_H_ +#define MSP_USB_H_ + +#ifdef CONFIG_MSP_HAS_DUAL_USB +#define NUM_USB_DEVS 2 +#else +#define NUM_USB_DEVS 1 +#endif + +/* Register spaces for USB host 0 */ +#define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0) +#define MSP_USB0_MAB_END (MSP_USB0_BASE + 0x17) +#define MSP_USB0_ID_START (MSP_USB0_BASE + 0x40000) +#define MSP_USB0_ID_END (MSP_USB0_BASE + 0x4008f) +#define MSP_USB0_HS_START (MSP_USB0_BASE + 0x40100) +#define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF) + +/* Register spaces for USB host 1 */ +#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0) +#define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17) +#define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000) +#define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f) +#define MSP_USB1_HS_START (MSP_USB1_BASE + 0x40100) +#define MSP_USB1_HS_END (MSP_USB1_BASE + 0x401ff) + +/* USB Identification registers */ +struct msp_usbid_regs { + u32 id; /* 0x0: Identification register */ + u32 hwgen; /* 0x4: General HW params */ + u32 hwhost; /* 0x8: Host HW params */ + u32 hwdev; /* 0xc: Device HW params */ + u32 hwtxbuf; /* 0x10: Tx buffer HW params */ + u32 hwrxbuf; /* 0x14: Rx buffer HW params */ + u32 reserved[26]; + u32 timer0_load; /* 0x80: General-purpose timer 0 load*/ + u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */ + u32 timer1_load; /* 0x88: General-purpose timer 1 load*/ + u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */ +}; + +/* MSBus to AMBA registers */ +struct msp_mab_regs { + u32 isr; /* 0x0: Interrupt status */ + u32 imr; /* 0x4: Interrupt mask */ + u32 thcr0; /* 0x8: Transaction header capture 0 */ + u32 thcr1; /* 0xc: Transaction header capture 1 */ + u32 int_stat; /* 0x10: Interrupt status summary */ + u32 phy_cfg; /* 0x14: USB phy config */ +}; + +/* EHCI registers */ +struct msp_usbhs_regs { + u32 hciver; /* 0x0: Version and offset to operational regs */ + u32 hcsparams; /* 0x4: Host control structural parameters */ + u32 hccparams; /* 0x8: Host control capability parameters */ + u32 reserved0[5]; + u32 dciver; /* 0x20: Device interface version */ + u32 dccparams; /* 0x24: Device control capability parameters */ + u32 reserved1[6]; + u32 cmd; /* 0x40: USB command */ + u32 sts; /* 0x44: USB status */ + u32 int_ena; /* 0x48: USB interrupt enable */ + u32 frindex; /* 0x4c: Frame index */ + u32 reserved3; + union { + struct { + u32 flb_addr; /* 0x54: Frame list base address */ + u32 next_async_addr; /* 0x58: next asynchronous addr */ + u32 ttctrl; /* 0x5c: embedded transaction translator + async buffer status */ + u32 burst_size; /* 0x60: Controller burst size */ + u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */ + u32 reserved0[4]; + u32 endpt_nak; /* 0x78: Endpoint NAK */ + u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */ + u32 cfg_flag; /* 0x80: Config flag */ + u32 port_sc1; /* 0x84: Port status & control 1 */ + u32 reserved1[7]; + u32 otgsc; /* 0xa4: OTG status & control */ + u32 mode; /* 0xa8: USB controller mode */ + } host; + + struct { + u32 dev_addr; /* 0x54: Device address */ + u32 endpt_list_addr; /* 0x58: Endpoint list address */ + u32 reserved0[7]; + u32 endpt_nak; /* 0x74 */ + u32 endpt_nak_ctrl; /* 0x78 */ + u32 cfg_flag; /* 0x80 */ + u32 port_sc1; /* 0x84: Port status & control 1 */ + u32 reserved[7]; + u32 otgsc; /* 0xa4: OTG status & control */ + u32 mode; /* 0xa8: USB controller mode */ + u32 endpt_setup_stat; /* 0xac */ + u32 endpt_prime; /* 0xb0 */ + u32 endpt_flush; /* 0xb4 */ + u32 endpt_stat; /* 0xb8 */ + u32 endpt_complete; /* 0xbc */ + u32 endpt_ctrl0; /* 0xc0 */ + u32 endpt_ctrl1; /* 0xc4 */ + u32 endpt_ctrl2; /* 0xc8 */ + u32 endpt_ctrl3; /* 0xcc */ + } device; + } u; +}; +/* + * Container for the more-generic platform_device. + * This exists mainly as a way to map the non-standard register + * spaces and make them accessible to the USB ISR. + */ +struct mspusb_device { + struct msp_mab_regs __iomem *mab_regs; + struct msp_usbid_regs __iomem *usbid_regs; + struct msp_usbhs_regs __iomem *usbhs_regs; + struct platform_device dev; +}; + +#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev) +#define TO_HOST_ID(x) ((x) & 0x3) +#endif /*MSP_USB_H_*/ diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig index 8d79849..a80ad25 100644 --- a/arch/mips/pmc-sierra/Kconfig +++ b/arch/mips/pmc-sierra/Kconfig @@ -23,6 +23,7 @@ config PMC_MSP7120_GW select SYS_SUPPORTS_MULTITHREADING select IRQ_MSP_CIC select HW_HAS_PCI + select MSP_HAS_USB config PMC_MSP7120_FPGA bool "PMC-Sierra MSP7120 FPGA" @@ -35,3 +36,10 @@ endchoice config HYPERTRANSPORT bool "Hypertransport Support for PMC-Sierra Yosemite" depends on PMC_YOSEMITE + + +config MSP_HAS_USB + boolean + depends on PMC_MSP + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_HCD diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile index 09627ae..380d39d 100644 --- a/arch/mips/pmc-sierra/msp71xx/Makefile +++ b/arch/mips/pmc-sierra/msp71xx/Makefile @@ -9,5 +9,5 @@ obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o obj-$(CONFIG_PCI) += msp_pci.o obj-$(CONFIG_MSPETH) += msp_eth.o -obj-$(CONFIG_USB_MSP71XX) += msp_usb.o +obj-$(CONFIG_MSP_HAS_USB) += msp_usb.o obj-$(CONFIG_MIPS_MT_SMP) += msp_smp.o diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c index 0ee01e3..9a1aef8 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c @@ -1,7 +1,7 @@ /* * The setup file for USB related hardware on PMC-Sierra MSP processors. * - * Copyright 2006-2007 PMC-Sierra, Inc. + * Copyright 2006 PMC-Sierra, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -23,8 +23,8 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) -#include #include #include #include @@ -34,40 +34,56 @@ #include #include #include +#include + #if defined(CONFIG_USB_EHCI_HCD) -static struct resource msp_usbhost_resources [] = { - [0] = { - .start = MSP_USB_BASE_START, - .end = MSP_USB_BASE_END, - .flags = IORESOURCE_MEM, +static struct resource msp_usbhost0_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB0_HS_START, + .end = MSP_USB0_HS_END, + .flags = IORESOURCE_MEM, }, [1] = { - .start = MSP_INT_USB, - .end = MSP_INT_USB, - .flags = IORESOURCE_IRQ, + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB0_MAB_START, + .end = MSP_USB0_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB0_ID_START, + .end = MSP_USB0_ID_END, + .flags = IORESOURCE_MEM, }, }; -static u64 msp_usbhost_dma_mask = DMA_BIT_MASK(32); +static u64 msp_usbhost0_dma_mask = 0xffffffffUL; -static struct platform_device msp_usbhost_device = { - .name = "pmcmsp-ehci", - .id = 0, +static struct mspusb_device msp_usbhost0_device = { .dev = { - .dma_mask = &msp_usbhost_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), + .name = "pmcmsp-ehci", + .id = 0, + .dev = { + .dma_mask = &msp_usbhost0_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbhost0_resources), + .resource = msp_usbhost0_resources, }, - .num_resources = ARRAY_SIZE(msp_usbhost_resources), - .resource = msp_usbhost_resources, }; -#endif /* CONFIG_USB_EHCI_HCD */ -#if defined(CONFIG_USB_GADGET) -static struct resource msp_usbdev_resources [] = { - [0] = { - .start = MSP_USB_BASE, - .end = MSP_USB_BASE_END, +/* MSP7140/MSP82XX has two USB2 hosts. */ +#ifdef CONFIG_MSP_HAS_DUAL_USB +static u64 msp_usbhost1_dma_mask = 0xffffffffUL; + +static struct resource msp_usbhost1_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB1_HS_START, + .end = MSP_USB1_HS_END, .flags = IORESOURCE_MEM, }, [1] = { @@ -75,76 +91,173 @@ static struct resource msp_usbdev_resources [] = { .end = MSP_INT_USB, .flags = IORESOURCE_IRQ, }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB1_MAB_START, + .end = MSP_USB1_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB1_ID_START, + .end = MSP_USB1_ID_END, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mspusb_device msp_usbhost1_device = { + .dev = { + .name = "pmcmsp-ehci", + .id = 1, + .dev = { + .dma_mask = &msp_usbhost1_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbhost1_resources), + .resource = msp_usbhost1_resources, + }, }; +#endif /* CONFIG_MSP_HAS_DUAL_USB */ +#endif /* CONFIG_USB_EHCI_HCD */ -static u64 msp_usbdev_dma_mask = DMA_BIT_MASK(32); +#if defined(CONFIG_USB_GADGET) +static struct resource msp_usbdev0_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB0_HS_START, + .end = MSP_USB0_HS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB0_MAB_START, + .end = MSP_USB0_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB0_ID_START, + .end = MSP_USB0_ID_END, + .flags = IORESOURCE_MEM, + }, +}; -static struct platform_device msp_usbdev_device = { - .name = "msp71xx_udc", - .id = 0, +static u64 msp_usbdev_dma_mask = 0xffffffffUL; + +/* This may need to be converted to a mspusb_device, too. */ +static struct mspusb_device msp_usbdev0_device = { .dev = { - .dma_mask = &msp_usbdev_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), + .name = "msp71xx_udc", + .id = 0, + .dev = { + .dma_mask = &msp_usbdev_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbdev0_resources), + .resource = msp_usbdev0_resources, }, - .num_resources = ARRAY_SIZE(msp_usbdev_resources), - .resource = msp_usbdev_resources, }; -#endif /* CONFIG_USB_GADGET */ -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) -static struct platform_device *msp_devs[1]; -#endif +#ifdef CONFIG_MSP_HAS_DUAL_USB +static struct resource msp_usbdev1_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB1_HS_START, + .end = MSP_USB1_HS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB1_MAB_START, + .end = MSP_USB1_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB1_ID_START, + .end = MSP_USB1_ID_END, + .flags = IORESOURCE_MEM, + }, +}; +/* This may need to be converted to a mspusb_device, too. */ +static struct mspusb_device msp_usbdev1_device = { + .dev = { + .name = "msp71xx_udc", + .id = 0, + .dev = { + .dma_mask = &msp_usbdev_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbdev1_resources), + .resource = msp_usbdev1_resources, + }, +}; + +#endif /* CONFIG_MSP_HAS_DUAL_USB */ +#endif /* CONFIG_USB_GADGET */ static int __init msp_usb_setup(void) { -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) - char *strp; - char envstr[32]; - unsigned int val = 0; - int result = 0; + char *strp; + char envstr[32]; + struct platform_device *msp_devs[NUM_USB_DEVS]; + unsigned int val; + /* construct environment name usbmode */ + /* set usbmode as pmon environment var */ /* - * construct environment name usbmode - * set usbmode as pmon environment var + * Could this perhaps be integrated into the "features" env var? + * Use the features key "U", and follow with "H" for host-mode, + * "D" for device-mode. If it works for Ethernet, why not USB... + * -- hammtrev, 2007/03/22 */ snprintf((char *)&envstr[0], sizeof(envstr), "usbmode"); -#if defined(CONFIG_USB_EHCI_HCD) - /* default to host mode */ + /* set default host mode */ val = 1; -#endif /* get environment string */ strp = prom_getenv((char *)&envstr[0]); if (strp) { + /* compare string */ if (!strcmp(strp, "device")) val = 0; } if (val) { #if defined(CONFIG_USB_EHCI_HCD) - /* get host mode device */ - msp_devs[0] = &msp_usbhost_device; - ppfinit("platform add USB HOST done %s.\n", - msp_devs[0]->name); - - result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); -#endif /* CONFIG_USB_EHCI_HCD */ - } + msp_devs[0] = &msp_usbhost0_device.dev; + ppfinit("platform add USB HOST done %s.\n", msp_devs[0]->name); +#ifdef CONFIG_MSP_HAS_DUAL_USB + msp_devs[1] = &msp_usbhost1_device.dev; + ppfinit("platform add USB HOST done %s.\n", msp_devs[1]->name); +#endif +#else + ppfinit("%s: echi_hcd not supported\n", __FILE__); +#endif /* CONFIG_USB_EHCI_HCD */ + } else { #if defined(CONFIG_USB_GADGET) - else { /* get device mode structure */ - msp_devs[0] = &msp_usbdev_device; - ppfinit("platform add USB DEVICE done %s.\n", - msp_devs[0]->name); - - result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); + msp_devs[0] = &msp_usbdev0_device.dev; + ppfinit("platform add USB DEVICE done %s.\n" + , msp_devs[0]->name); +#ifdef CONFIG_MSP_HAS_DUAL_USB + msp_devs[1] = &msp_usbdev1_device.dev; + ppfinit("platform add USB DEVICE done %s.\n" + , msp_devs[1]->name); +#endif +#else + ppfinit("%s: usb_gadget not supported\n", __FILE__); +#endif /* CONFIG_USB_GADGET */ } -#endif /* CONFIG_USB_GADGET */ -#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ + /* add device */ + platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); - return result; + return 0; } subsys_initcall(msp_usb_setup); +#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 27115b4..f2a45ba 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -3377,12 +3377,43 @@ static void hub_events(void) } if (portchange & USB_PORT_STAT_C_OVERCURRENT) { +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP +#define OVER_CURR_DELAY 100 + /* clear OCC bit */ + clear_port_feature(hdev, i, + USB_PORT_FEAT_C_OVER_CURRENT); + + /* This step is required to toggle the PP bit + * to 0 and 1 (by hub_power_on) in order the + * CSC bit to be transitioned + * properly for device hotplug + */ + /* clear PP bit */ + clear_port_feature(hdev, i, + USB_PORT_FEAT_POWER); + + /* resume power */ + hub_power_on(hub, true); + + /* delay 100 usec */ + udelay(OVER_CURR_DELAY); + + /* read OCA bit */ + if (portstatus & + (1< +#include +#include + +/* includes */ +#define USB_CTRL_MODE_HOST 0x3 + /* host mode */ +#define USB_CTRL_MODE_BIG_ENDIAN 0x4 + /* big endian */ +#define USB_CTRL_MODE_STREAM_DISABLE 0x10 + /* stream disable*/ +#define USB_CTRL_FIFO_THRESH 0x00300000 + /* thresh hold */ +#define USB_EHCI_REG_USB_MODE 0x68 + /* register offset for usb_mode */ +#define USB_EHCI_REG_USB_FIFO 0x24 + /* register offset for usb fifo */ +#define USB_EHCI_REG_USB_STATUS 0x44 + /* register offset for usb status */ +#define USB_EHCI_REG_BIT_STAT_STS (1<<29) + /* serial/parallel transceiver */ +#define MSP_PIN_USB0_HOST_DEV 49 + /* TWI USB0 host device pin */ +#define MSP_PIN_USB1_HOST_DEV 50 + /* TWI USB1 host device pin */ + +extern int usb_disabled(void); + +void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) +{ + u8 *base; + u8 *statreg; + u8 *fiforeg; + u32 val; + struct ehci_regs *reg_base = ehci->regs; + + /* get register base */ + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; + + /* set the controller to host mode and BIG ENDIAN */ + ehci_writel(ehci, (USB_CTRL_MODE_HOST | USB_CTRL_MODE_BIG_ENDIAN + | USB_CTRL_MODE_STREAM_DISABLE), (u32 *)base); + + /* clear STS to select parallel transceiver interface */ + val = ehci_readl(ehci, (u32 *)statreg); + val = val & ~USB_EHCI_REG_BIT_STAT_STS; + ehci_writel(ehci, val, (u32 *)statreg); + + /* write to set the proper fifo threshold */ + ehci_writel(ehci, USB_CTRL_FIFO_THRESH, (u32 *)fiforeg); + + /* set TWI GPIO USB_HOST_DEV pin high */ + gpio_direction_output(MSP_PIN_USB0_HOST_DEV, 1); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1); +#endif +} + +/* called after powerup, by probe or system-pm "wakeup" */ +static int ehci_msp_reinit(struct ehci_hcd *ehci) +{ + ehci_port_power(ehci, 0); + + return 0; +} + +/* called during probe() after chip reset completes */ +static int ehci_msp_setup(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 temp; + int retval; +#if 1 + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); +#endif + hcd->has_tt = 1; + tdi_reset(ehci); + + retval = ehci_halt(ehci); + if (retval) + return retval; + + ehci_reset(ehci); + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); + temp &= 0x0f; + if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { + ehci_dbg(ehci, "bogus port configuration: " + "cc=%d x pcc=%d < ports=%d\n", + HCS_N_CC(ehci->hcs_params), + HCS_N_PCC(ehci->hcs_params), + HCS_N_PORTS(ehci->hcs_params)); + } + + retval = ehci_msp_reinit(ehci); + + return retval; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_PM + +/* suspend/resume, section 4.3 */ + +/* These routines rely on the bus glue + * to handle powerdown and wakeup, and currently also on + * transceivers that don't need any software attention to set up + * the right sort of wakeup. + * Also they depend on separate root hub suspend/resume. + */ + +static int ehci_msp_suspend(struct usb_hcd *hcd, pm_message_t message) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + unsigned long flags; + int rc = 0; + + if (time_before(jiffies, ehci->next_statechange)) + msleep(10); + + /* Root hub was already suspended. Disable irq emission and + * mark HW unaccessible, bail out if RH has been resumed. Use + * the spinlock to properly synchronize with possible pending + * RH suspend or resume activity. + * + * This is still racy as hcd->state is manipulated outside of + * any locks =P But that will be a different fix. + */ + spin_lock_irqsave(&ehci->lock, flags); + if (hcd->state != HC_STATE_SUSPENDED) { + rc = -EINVAL; + goto bail; + } + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + (void)ehci_readl(ehci, &ehci->regs->intr_enable); + + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + bail: + spin_unlock_irqrestore(&ehci->lock, flags); + + /* could save FLADJ in case of Vaux power loss + ... we'd only use it to handle clock skew */ + + return rc; +} + +static int ehci_msp_resume(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + unsigned port; + struct usb_device *root = hcd->self.root_hub; + int retval = -EINVAL; + + /* maybe restore FLADJ */ + + if (time_before(jiffies, ehci->next_statechange)) + msleep(100); + + /* Mark hardware accessible again as we are out of D3 state by now */ + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + /* If CF is clear, we lost PCI Vaux power and need to restart. */ + if (ehci_readl(ehci, &ehci->regs->configured_flag) != FLAG_CF) + goto restart; + + /* If any port is suspended (or owned by the companion), + * we know we can/must resume the HC (and mustn't reset it). + * We just defer that to the root hub code. + */ + for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { + u32 status; + port--; + status = ehci_readl(ehci, &ehci->regs->port_status[port]); + if (!(status & PORT_POWER)) + continue; + if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) { + usb_hcd_resume_root_hub(hcd); + return 0; + } + } + +restart: + ehci_dbg(ehci, "lost power, restarting\n"); + for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { + port--; + if (!root->children[port]) + continue; + usb_set_device_state(root->children[port], + USB_STATE_NOTATTACHED); + } + + /* Else reset, to cope with power loss or flush-to-storage + * style "resume" having let BIOS kick in during reboot. + */ + (void) ehci_halt(ehci); + (void) ehci_reset(ehci); + (void) ehci_msp_reinit(ehci, pdev); + + /* emptying the schedule aborts any urbs */ + spin_lock_irq(&ehci->lock); + if (ehci->reclaim) + ehci->reclaim_ready = 1; + ehci_work(ehci, NULL); + spin_unlock_irq(&ehci->lock); + + /* restart; khubd will disconnect devices */ + retval = ehci_run(hcd); + + /* here we "know" root ports should always stay powered */ + ehci_port_power(ehci, 1); + + return retval; +} +#endif + +/*-------------------------------------------------------------------------*/ + +static void msp_start_hc(struct platform_device *dev) +{ + printk(KERN_DEBUG __FILE__ + ": starting PMC MSP EHCI USB Controller\n"); + + /* + * Now, carefully enable the USB clock, and take + * the USB host controller out of reset. + */ + printk(KERN_DEBUG __FILE__ + ": Clock to USB host has been enabled\n"); +} + +static void msp_stop_hc(struct platform_device *dev) +{ + printk(KERN_DEBUG __FILE__ + ": stopping PMC MSP EHCI USB Controller\n"); +} + + +/*-------------------------------------------------------------------------*/ + +/* configure so an HC device and id are always provided */ +/* always called with process context; sleeping is OK */ + +static int usb_hcd_msp_map_regs(struct mspusb_device *dev) +{ + struct resource *res; + struct platform_device *pdev = &dev->dev; + u32 res_len; + int retval; + + /* MAB register space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res == NULL) + return -ENOMEM; + res_len = res->end - res->start + 1; + if (!request_mem_region(res->start, res_len, "mab regs")) + return -EBUSY; + + dev->mab_regs = ioremap_nocache(res->start, res_len); + if (dev->mab_regs == NULL) { + retval = -ENOMEM; + goto err1; + } + + /* MSP USB register space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (res == NULL) { + retval = -ENOMEM; + goto err2; + } + res_len = res->end - res->start + 1; + if (!request_mem_region(res->start, res_len, "usbid regs")) { + retval = -EBUSY; + goto err2; + } + dev->usbid_regs = ioremap_nocache(res->start, res_len); + if (dev->usbid_regs == NULL) { + retval = -ENOMEM; + goto err3; + } + + return 0; +err3: + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + res_len = res->end - res->start + 1; + release_mem_region(res->start, res_len); +err2: + iounmap(dev->mab_regs); +err1: + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + res_len = res->end - res->start + 1; + release_mem_region(res->start, res_len); + dev_err(&pdev->dev, "Failed to map non-EHCI regs.\n"); + return retval; +} + +/** + * usb_hcd_msp_probe - initialize PMC MSP-based HCDs + * Context: !in_interrupt() + * + * Allocates basic resources for this USB host controller, and + * then invokes the start() method for the HCD associated with it + * through the hotplug entry's driver_data. + * + */ +int usb_hcd_msp_probe(const struct hc_driver *driver, + struct platform_device *dev) +{ + int retval; + struct usb_hcd *hcd; + struct resource *res; + struct ehci_hcd *ehci ; + + hcd = usb_create_hcd(driver, &dev->dev, "pmcmsp"); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (res == NULL) { + pr_debug("No IOMEM resource info for %s.\n", dev->name); + retval = -ENOMEM; + goto err1; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, dev->name)) { + retval = -EBUSY; + goto err1; + } + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed"); + retval = -ENOMEM; + goto err2; + } + msp_start_hc(dev); + + res = platform_get_resource(dev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&dev->dev, "No IRQ resource info for %s.\n", dev->name); + retval = -ENOMEM; + goto err3; + } + + /* Map non-EHCI register spaces */ + retval = usb_hcd_msp_map_regs(to_mspusb_device(dev)); + if (retval != 0) + goto err3; + + ehci = hcd_to_ehci(hcd); + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; + + + retval = usb_add_hcd(hcd, res->start, IRQF_SHARED); + if (retval == 0) + return 0; + + usb_remove_hcd(hcd); +err3: + msp_stop_hc(dev); + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + + return retval; +} + + +/* may be called without controller electrically present */ +/* may be called with controller, bus, and devices active */ + +/** + * usb_hcd_msp_remove - shutdown processing for PMC MSP-based HCDs + * @dev: USB Host Controller being removed + * Context: !in_interrupt() + * + * Reverses the effect of usb_hcd_msp_probe(), first invoking + * the HCD's stop() method. It is always called from a thread + * context, normally "rmmod", "apmd", or something similar. + * + */ +void usb_hcd_msp_remove(struct usb_hcd *hcd, struct platform_device *dev) +{ + usb_remove_hcd(hcd); + msp_stop_hc(dev); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); +} + +#ifdef CONFIG_MSP_HAS_DUAL_USB +/*-------------------------------------------------------------------------*/ +/* + * Wrapper around the main ehci_irq. Since both USB host controllers are + * sharing the same IRQ, need to first determine whether we're the intended + * recipient of this interrupt. + */ +static irqreturn_t ehci_msp_irq(struct usb_hcd *hcd) +{ + u32 int_src; + struct device *dev = hcd->self.controller; + struct platform_device *pdev; + struct mspusb_device *mdev; + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + /* need to reverse-map a couple of containers to get our device */ + pdev = to_platform_device(dev); + mdev = to_mspusb_device(pdev); + + /* Check to see if this interrupt is for this host controller */ + int_src = ehci_readl(ehci, &mdev->mab_regs->int_stat); + if (int_src & (1 << pdev->id)) + return ehci_irq(hcd); + + /* Not for this device */ + return IRQ_NONE; +} +/*-------------------------------------------------------------------------*/ +#endif /* DUAL_USB */ + +static const struct hc_driver ehci_msp_hc_driver = { + .description = hcd_name, + .product_desc = "PMC MSP EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ +#ifdef CONFIG_MSP_HAS_DUAL_USB + .irq = ehci_msp_irq, +#else + .irq = ehci_irq, +#endif + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + */ + .reset = ehci_msp_setup, + .start = ehci_run, +#ifdef CONFIG_PM + .suspend = ehci_msp_suspend, + .resume = ehci_msp_resume, +#endif /*CONFIG_PM*/ + .stop = ehci_stop, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +}; + +/*-------------------------------------------------------------------------*/ + +static int ehci_hcd_msp_drv_probe(struct platform_device *pdev) +{ + int ret; + + pr_debug("In ehci_hcd_msp_drv_probe"); + + if (usb_disabled()) + return -ENODEV; + + gpio_request(MSP_PIN_USB0_HOST_DEV, "USB0_HOST_DEV_GPIO"); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_request(MSP_PIN_USB1_HOST_DEV, "USB1_HOST_DEV_GPIO"); +#endif + + ret = usb_hcd_msp_probe(&ehci_msp_hc_driver, pdev); + + return ret; +} + +static int ehci_hcd_msp_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_hcd_msp_remove(hcd, pdev); + + /* free TWI GPIO USB_HOST_DEV pin */ + gpio_free(MSP_PIN_USB0_HOST_DEV); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_free(MSP_PIN_USB1_HOST_DEV); +#endif + + return 0; +} + +MODULE_ALIAS("pmcmsp-ehci"); +static struct platform_driver ehci_hcd_msp_driver = { + .probe = ehci_hcd_msp_drv_probe, + .remove = ehci_hcd_msp_drv_remove, + .driver = { + .name = "pmcmsp-ehci", + }, +}; -- 1.7.0.4 From stern+4d08bae8@rowland.harvard.edu Tue Dec 21 17:00:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 17:00:10 +0100 (CET) Received: from netrider.rowland.org ([192.131.102.5]:50186 "HELO netrider.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492663Ab0LUQAF (ORCPT ); Tue, 21 Dec 2010 17:00:05 +0100 Received: (qmail 32521 invoked by uid 500); 21 Dec 2010 11:00:02 -0500 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 21 Dec 2010 11:00:02 -0500 Date: Tue, 21 Dec 2010 11:00:02 -0500 (EST) From: Alan Stern X-X-Sender: stern@netrider.rowland.org To: Anoop P cc: Ralf Baechle , , , , , , , , , , Subject: Re: [PATCH] EHCI support for on-chip PMC MSP USB controller. In-Reply-To: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28664 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Content-Length: 3245 Lines: 127 On Tue, 21 Dec 2010, Anoop P wrote: > From: Anoop P A > > This patch includes. > > 1. USB host driver for MSP71xx family SoC on-chip USB controller. > 2. Platform support for USB controller. It also contains changes to the core USB hub driver code. You should mention things like that in the patch description. ... > diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c > index 27115b4..f2a45ba 100644 > --- a/drivers/usb/core/hub.c > +++ b/drivers/usb/core/hub.c > @@ -3377,12 +3377,43 @@ static void hub_events(void) > } > > if (portchange & USB_PORT_STAT_C_OVERCURRENT) { > +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP > +#define OVER_CURR_DELAY 100 What happens if CONFIG_USB_EHCI_HCD_PMC_MSP is defined, but an overcurrent status is detected on an external hub instead of the root hub? > + /* clear OCC bit */ > + clear_port_feature(hdev, i, > + USB_PORT_FEAT_C_OVER_CURRENT); > + > + /* This step is required to toggle the PP bit > + * to 0 and 1 (by hub_power_on) in order the > + * CSC bit to be transitioned > + * properly for device hotplug > + */ > + /* clear PP bit */ > + clear_port_feature(hdev, i, > + USB_PORT_FEAT_POWER); > + > + /* resume power */ > + hub_power_on(hub, true); > + > + /* delay 100 usec */ > + udelay(OVER_CURR_DELAY); > + > + /* read OCA bit */ > + if (portstatus & > + (1< + /* declare overcurrent */ > + dev_err(hub_dev, > + "over-current change on port %d\n", > + i); > + } > +#else > dev_err (hub_dev, > "over-current change on port %d\n", > i); > clear_port_feature(hdev, i, > USB_PORT_FEAT_C_OVER_CURRENT); > hub_power_on(hub, true); > +#endif > } "#ifdef" inside code like this is strongly discouraged. This should be written using a separate subroutine. ... > diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c > new file mode 100644 > index 0000000..b1b4f21 > --- /dev/null > +++ b/drivers/usb/host/ehci-pmcmsp.c > +static const struct hc_driver ehci_msp_hc_driver = { > + .description = hcd_name, > + .product_desc = "PMC MSP EHCI", > + .hcd_priv_size = sizeof(struct ehci_hcd), > + > + /* > + * generic hardware linkage > + */ > +#ifdef CONFIG_MSP_HAS_DUAL_USB > + .irq = ehci_msp_irq, > +#else > + .irq = ehci_irq, > +#endif > + .flags = HCD_MEMORY | HCD_USB2, > + > + /* > + * basic lifecycle operations > + */ > + .reset = ehci_msp_setup, > + .start = ehci_run, > +#ifdef CONFIG_PM > + .suspend = ehci_msp_suspend, > + .resume = ehci_msp_resume, > +#endif /*CONFIG_PM*/ > + .stop = ehci_stop, > + > + /* > + * managing i/o requests and associated device resources > + */ > + .urb_enqueue = ehci_urb_enqueue, > + .urb_dequeue = ehci_urb_dequeue, > + .endpoint_disable = ehci_endpoint_disable, > + > + /* > + * scheduling support > + */ > + .get_frame_number = ehci_get_frame, > + > + /* > + * root hub support > + */ > + .hub_status_data = ehci_hub_status_data, > + .hub_control = ehci_hub_control, > +}; This appears to have been copied from a really old version of ehci-pci.c. You should start with the most up-to-date code. Alan Stern From gregkh@suse.de Tue Dec 21 18:59:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 19:00:00 +0100 (CET) Received: from cantor2.suse.de ([195.135.220.15]:44082 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492780Ab0LUR75 (ORCPT ); Tue, 21 Dec 2010 18:59:57 +0100 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) by mx2.suse.de (Postfix) with ESMTP id E2C4F8B45E; Tue, 21 Dec 2010 18:59:53 +0100 (CET) Date: Tue, 21 Dec 2010 09:59:42 -0800 From: Greg KH To: Alan Stern , Anoop P , Ralf Baechle , dbrownell@users.sourceforge.net, sarah.a.sharp@linux.intel.com, andiry.xu@amd.com, agust@denx.de, ddaney@caviumnetworks.com, gadiyar@ti.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Subject: Re: [PATCH] EHCI support for on-chip PMC MSP USB controller. Message-ID: <20101221175942.GB8709@suse.de> References: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28665 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Content-Length: 537 Lines: 19 On Tue, Dec 21, 2010 at 11:00:02AM -0500, Alan Stern wrote: > On Tue, 21 Dec 2010, Anoop P wrote: > > > From: Anoop P A > > > > This patch includes. > > > > 1. USB host driver for MSP71xx family SoC on-chip USB controller. > > 2. Platform support for USB controller. > > It also contains changes to the core USB hub driver code. You should > mention things like that in the patch description. And that portion of the code should be split into a different patch to make it easier to review. thanks, greg k-h From David.Daney@caviumnetworks.com Tue Dec 21 19:46:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 19:46:35 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:7189 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492794Ab0LUSqa (ORCPT ); Tue, 21 Dec 2010 19:46:30 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 21 Dec 2010 10:31:49 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 10:32:27 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 10:32:26 -0800 Message-ID: <4D10F268.8080706@caviumnetworks.com> Date: Tue, 21 Dec 2010 10:31:04 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 3/3] MIPS: Use C0_KScratch (if present) to hold PGD pointer. References: <1292879828-20493-1-git-send-email-ddaney@caviumnetworks.com> <1292879828-20493-4-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1292879828-20493-4-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 21 Dec 2010 18:32:26.0975 (UTC) FILETIME=[6AF59EF0:01CBA13D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28666 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 989 Lines: 34 On 12/20/2010 01:17 PM, David Daney wrote: > Decide at runtime to use either Context or KScratch to hold the PGD > pointer. > > Signed-off-by: David Daney > --- > arch/mips/include/asm/mmu_context.h | 8 +-- > arch/mips/kernel/traps.c | 2 +- > arch/mips/mm/tlbex.c | 110 +++++++++++++++++++++++++++++++--- > 3 files changed, 102 insertions(+), 18 deletions(-) > [...] > /* Install CPU exception handler */ > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > index 6184f0a..2e15aa6 100644 > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -26,8 +26,10 @@ > #include > #include > #include > +#include > > -#include Whoops, that include should stay, it is needed for ip32. > +#include > +#include > #include > #include >[...] I will send a revised patch. From Anoop_P.A@pmc-sierra.com Tue Dec 21 21:07:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 21:07:15 +0100 (CET) Received: from bby1mta02.pmc-sierra.com ([216.241.235.117]:47200 "EHLO bby1mta02.pmc-sierra.bc.ca" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492818Ab0LUUHL convert rfc822-to-8bit (ORCPT ); Tue, 21 Dec 2010 21:07:11 +0100 Received: from bby1mta02.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id 8B8878E00DE; Tue, 21 Dec 2010 12:07:01 -0800 (PST) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (bby1exg02 [216.241.231.167]) by bby1mta02.pmc-sierra.bc.ca (Postfix) with SMTP id 627498E00F7; Tue, 21 Dec 2010 12:07:01 -0800 (PST) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.159]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 12:07:01 -0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: RE: SMTC support status in latest git head. Date: Tue, 21 Dec 2010 12:06:57 -0800 Message-ID: In-Reply-To: <4D10F7A9.1020306@paralogos.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: SMTC support status in latest git head. Thread-Index: AcuhQGKZ5K7N538AQs2q7v545EZbTwACfOSA References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> <4D0BD7A0.1030504@paralogos.com> <4D10F7A9.1020306@paralogos.com> From: "Anoop P.A." To: "Kevin D. Kissell" , "Anoop P A" Cc: "STUART VENTERS" , X-OriginalArrivalTime: 21 Dec 2010 20:07:01.0391 (UTC) FILETIME=[A12CC9F0:01CBA14A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28667 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips Content-Length: 14840 Lines: 358 OK. I will check it. BTW following patch is responsible for irq change. http://git.linux-mips.org/?p=linux.git;a=commitdiff;h=df9ee29270c11dba7d0fe0b83ce47a4d8e8d2101 Thanks Anoop ________________________________________ From: Kevin D. Kissell [mailto:kevink@paralogos.com] Sent: Wednesday, December 22, 2010 12:23 AM To: Anoop P A Cc: STUART VENTERS; linux-mips@linux-mips.org; Anoop P.A. Subject: Re: SMTC support status in latest git head. OK, I see why the MT register dump isn't giving us useful information.  It's not clear that it's at the root of your functional problems, though.  Apparently, somebody decided that it was unwholesome to propagate anything other than the previous interrupt enable state in the flags variable passed between irq_save() and irq_restore().  I agree philosophically, but it does break the MT register dump function.  And I'm quite sure that there were other bits of SMTC code that knew that it was a TCStatus value, at least in the earliest versions of the code.  I'm not a gitweb power user,  but I haven't been able to figure out how to determine when the "andi \\result 0x400" on or about line 138 of irqflags.h (at least that's where it is in the head of tree) was checked-in.  If it's at the boundary between working and non-working versions for SMTC, it might be the cause of the problems, but it may well not be responsible for anything other than the problem with reporting the value in the MT register dump - which really ought to be fixed. I'm in a small village in France for the holidays with no git/build system at my disposal, but I think that if you were to tweak mips-mt.c at line 103 to change the         tcstatval = flags; /* And pre-dump TCStatus is flags */ to something more like /* Pre-dump TCStatus Interrupt Inhibit bit is in flags variable */ tcstatval = (read_c0_tcstatus() & ~0x400) | flags; should fix the dump.             Regards,             Kevin K. On 12/20/10 2:44 AM, Anoop P A wrote: Hi Kevin, Please find disassembly for mips_mt_reg_dump Thanks Anoop Disassembly of section .text: 00000000 : 0: 27bdffb8 addiu sp,sp,-72 4: 00802821 move a1,a0 8: afbf0044 sw ra,68(sp) c: afbe0040 sw s8,64(sp) 10: afb7003c sw s7,60(sp) 14: afb60038 sw s6,56(sp) 18: afb50034 sw s5,52(sp) 1c: afb40030 sw s4,48(sp) 20: afb3002c sw s3,44(sp) 24: afb20028 sw s2,40(sp) 28: afb10024 sw s1,36(sp) 2c: afb00020 sw s0,32(sp) 30: 40141001 mfc0 s4,c0_tcstatus 34: 36810400 ori at,s4,0x400 38: 40811001 mtc0 at,c0_tcstatus 3c: 32940400 andi s4,s4,0x400 40: 000000c0 ehb 44: 41610001 dvpe at 48: 0020a821 move s5,at 4c: 000000c0 ehb 50: 3c020000 lui v0,0x0 54: 24420060 addiu v0,v0,96 58: 00400408 jr.hb v0 5c: 00000000 nop 60: 3c040000 lui a0,0x0 64: 24840000 addiu a0,a0,0 68: 0c000000 jal 0 6c: afa50010 sw a1,16(sp) 70: 3c040000 lui a0,0x0 74: 0c000000 jal 0 78: 24840000 addiu a0,a0,0 7c: 8fa50010 lw a1,16(sp) 80: 3c040000 lui a0,0x0 84: 0c000000 jal 0 88: 24840000 addiu a0,a0,0 8c: 3c040000 lui a0,0x0 90: 24840000 addiu a0,a0,0 94: 0c000000 jal 0 98: 02a02821 move a1,s5 9c: 40110002 mfc0 s1,c0_mvpconf0 a0: 3c040000 lui a0,0x0 a4: 02202821 move a1,s1 a8: 0c000000 jal 0 ac: 24840000 addiu a0,a0,0 b0: 3c040000 lui a0,0x0 b4: 0c000000 jal 0 b8: 24840000 addiu a0,a0,0 bc: 7e331a80 ext s3,s1,0xa,0x4 c0: 3c090000 lui t1,0x0 c4: 323100ff andi s1,s1,0xff c8: 3c080000 lui t0,0x0 cc: 3c030000 lui v1,0x0 d0: 3c1e0000 lui s8,0x0 d4: 3c170000 lui s7,0x0 d8: 3c160000 lui s6,0x0 dc: 3c0a0000 lui t2,0x0 e0: 26730001 addiu s3,s3,1 e4: 26310001 addiu s1,s1,1 e8: 00008021 move s0,zero ec: 2412ff00 li s2,-256 f0: 25290000 addiu t1,t1,0 f4: 25080000 addiu t0,t0,0 f8: 24630000 addiu v1,v1,0 fc: 27de0000 addiu s8,s8,0 100: 26f70000 addiu s7,s7,0 104: 26d60000 addiu s6,s6,0 108: 254a0000 addiu t2,t2,0 10c: 00001021 move v0,zero 110: 40040801 mfc0 a0,c0_vpecontrol 114: 00922024 and a0,a0,s2 118: 00442025 or a0,v0,a0 11c: 40840801 mtc0 a0,c0_vpecontrol 120: 000000c0 ehb 124: 41020802 mftc0 at,c0_tcbind 128: 00202021 move a0,at 12c: 24420001 addiu v0,v0,1 130: 3084000f andi a0,a0,0xf 134: 12040031 beq s0,a0,1fc 138: 0051282a slt a1,v0,s1 13c: 14a0fff4 bnez a1,110 140: 00000000 nop 144: 26100001 addiu s0,s0,1 148: 0213102a slt v0,s0,s3 14c: 1440fff0 bnez v0,110 150: 00001021 move v0,zero 154: 3c040000 lui a0,0x0 158: 24840000 addiu a0,a0,0 15c: 3c1e0000 lui s8,0x0 160: 3c170000 lui s7,0x0 164: 3c160000 lui s6,0x0 168: 3c130000 lui s3,0x0 16c: 0c000000 jal 0 170: 3c120000 lui s2,0x0 174: 00008021 move s0,zero 178: 27de0000 addiu s8,s8,0 17c: 26f70000 addiu s7,s7,0 180: 26d60000 addiu s6,s6,0 184: 26730000 addiu s3,s3,0 188: 26520000 addiu s2,s2,0 18c: 40020801 mfc0 v0,c0_vpecontrol 190: 2403ff00 li v1,-256 194: 00431024 and v0,v0,v1 198: 02021025 or v0,s0,v0 19c: 40820801 mtc0 v0,c0_vpecontrol 1a0: 000000c0 ehb 1a4: 41020802 mftc0 at,c0_tcbind 1a8: 00201821 move v1,at 1ac: 40021002 mfc0 v0,c0_tcbind 1b0: 1062003f beq v1,v0,2b0 1b4: 00000000 nop 1b8: 41020804 mftc0 at,c0_tchalt 1bc: 00201821 move v1,at 1c0: 24020001 li v0,1 1c4: 00400821 move at,v0 1c8: 41811004 mttc0 at,c0_tchalt 1cc: 41020801 mftc0 at,c0_tcstatus 1d0: 00203021 move a2,at 1d4: 3c040000 lui a0,0x0 1d8: 02002821 move a1,s0 1dc: 24840000 addiu a0,a0,0 1e0: afa3001c sw v1,28(sp) 1e4: 0c000000 jal 0 1e8: afa60010 sw a2,16(sp) 1ec: 8fa60010 lw a2,16(sp) 1f0: 8fa3001c lw v1,28(sp) 1f4: 080000b2 j 2c8 1f8: 00c02821 move a1,a2 1fc: 01202021 move a0,t1 200: 02002821 move a1,s0 204: afa3001c sw v1,28(sp) 208: afa80014 sw t0,20(sp) 20c: afa90010 sw t1,16(sp) 210: 0c000000 jal 0 214: afaa0018 sw t2,24(sp) 218: 41010801 mftc0 at,c0_vpecontrol 21c: 00202821 move a1,at 220: 8fa80014 lw t0,20(sp) 224: 0c000000 jal 0 228: 01002021 move a0,t0 22c: 41010802 mftc0 at,c0_vpeconf0 230: 00202821 move a1,at 234: 8fa3001c lw v1,28(sp) 238: 0c000000 jal 0 23c: 00602021 move a0,v1 240: 410c0800 mftc0 at,c0_status 244: 00203021 move a2,at 248: 03c02021 move a0,s8 24c: 0c000000 jal 0 250: 02002821 move a1,s0 254: 410e0800 mftc0 at,c0_epc 258: 00203021 move a2,at 25c: 410e0800 mftc0 at,c0_epc 260: 00203821 move a3,at 264: 02e02021 move a0,s7 268: 0c000000 jal 0 26c: 02002821 move a1,s0 270: 410d0800 mftc0 at,c0_cause 274: 00203021 move a2,at 278: 02c02021 move a0,s6 27c: 0c000000 jal 0 280: 02002821 move a1,s0 284: 41100807 mftc0 at,$16,7 288: 00203021 move a2,at 28c: 8faa0018 lw t2,24(sp) 290: 02002821 move a1,s0 294: 0c000000 jal 0 298: 01402021 move a0,t2 29c: 8fa3001c lw v1,28(sp) 2a0: 8fa80014 lw t0,20(sp) 2a4: 8fa90010 lw t1,16(sp) 2a8: 08000051 j 144 2ac: 8faa0018 lw t2,24(sp) 2b0: 3c040000 lui a0,0x0 2b4: 02002821 move a1,s0 2b8: 0c000000 jal 0 2bc: 24840000 addiu a0,a0,0 2c0: 00001821 move v1,zero 2c4: 02802821 move a1,s4 2c8: 03c02021 move a0,s8 2cc: 0c000000 jal 0 2d0: afa3001c sw v1,28(sp) 2d4: 41020802 mftc0 at,c0_tcbind 2d8: 00202821 move a1,at 2dc: 0c000000 jal 0 2e0: 02e02021 move a0,s7 2e4: 41020803 mftc0 at,c0_tcrestart 2e8: 00202821 move a1,at 2ec: 41020803 mftc0 at,c0_tcrestart 2f0: 00203021 move a2,at 2f4: 0c000000 jal 0 2f8: 02c02021 move a0,s6 2fc: 8fa3001c lw v1,28(sp) 300: 02602021 move a0,s3 304: 0c000000 jal 0 308: 00602821 move a1,v1 30c: 41020805 mftc0 at,c0_tccontext 310: 00202821 move a1,at 314: 0c000000 jal 0 318: 02402021 move a0,s2 31c: 8fa3001c lw v1,28(sp) 320: 14600003 bnez v1,330 324: 00001021 move v0,zero 328: 00400821 move at,v0 32c: 41811004 mttc0 at,c0_tchalt 330: 26100001 addiu s0,s0,1 334: 0211102a slt v0,s0,s1 338: 1440ff94 bnez v0,18c 33c: 00000000 nop 340: 0c000000 jal 0 344: 32b50001 andi s5,s5,0x1 348: 3c040000 lui a0,0x0 34c: 0c000000 jal 0 350: 24840000 addiu a0,a0,0 354: 12a00004 beqz s5,368 358: 32820400 andi v0,s4,0x400 35c: 41600021 evpe 360: 000000c0 ehb 364: 32820400 andi v0,s4,0x400 368: 14400003 bnez v0,378 36c: 00000000 nop 370: 0c000000 jal 0 374: 00000000 nop 378: 40011001 mfc0 at,c0_tcstatus 37c: 32940400 andi s4,s4,0x400 380: 34210400 ori at,at,0x400 384: 38210400 xori at,at,0x400 388: 0281a025 or s4,s4,at 38c: 40941001 mtc0 s4,c0_tcstatus 390: 000000c0 ehb 394: 8fbf0044 lw ra,68(sp) 398: 8fbe0040 lw s8,64(sp) 39c: 8fb7003c lw s7,60(sp) 3a0: 8fb60038 lw s6,56(sp) 3a4: 8fb50034 lw s5,52(sp) 3a8: 8fb40030 lw s4,48(sp) 3ac: 8fb3002c lw s3,44(sp) 3b0: 8fb20028 lw s2,40(sp) 3b4: 8fb10024 lw s1,36(sp) 3b8: 8fb00020 lw s0,32(sp) 3bc: 03e00008 jr ra 3c0: 27bd0048 addiu sp,sp,72 On Sat, Dec 18, 2010 at 3:05 AM, Kevin D. Kissell wrote: So, Anoop, if you get a minute for this any time in the next day or so (after which I'll have very limited net access until next year), could you please do an -mips-objdump --disassemble of your kernel image (or even just the mips-mt.o module) from a failing kernel build and post the disassembly of mips_mt_regdump()?  The confirmation or refutation of the theory about local_irq_save() no longer being built correctly for SMTC would be within the first few instructions... /K. On 12/16/10 11:58, Kevin D. Kissell wrote: Ralf tells me that this message got blocked by the LMO server due to HTML content. So here it is again, textier. On 12/16/10 11:24, Kevin D. Kissell wrote: On 12/16/10 07:37, STUART VENTERS wrote: Two other possible clues: The EVP is clear in the MVPControl register. Does this say that only VPE0, T0 gets to run? That's correct.  In the maxtcs=1/maxvpes=1 boot state, it wouldn't matter.  It's just possible that setting EVP is conditional on more than one VPE being used, but that's not the way I remember it. Also the EXCPT bits in VPEControl for VPE1 indicate a Gating Storage Exception dispatch. But that seems to conflict the EVP bit above. I don't have a copy of the ASE spec handy to see whether those bits have a defined power-on value, but particularly if maxvpes=1 was set at boot time, I would expect VPE1's registers to be in a partly random power-up state. Perhaps these are an artifact of getting to a good state to dump things out. As per my previous mail, I looked at the MT register dump source, and it really does pull values directly out of registers and doesn't depend on having a sane kernel stack frame.  The exceptions to that rule are the reported values for TCStatus of the executing TC, which is based on the perhaps-now-broken assumption that local_irq_save(flags) stores the *entire* pre-invocation value of the TCStatus register in the flags variable, and MVPcontrol, which is based on the assumption that dvpe() returns the pre-invocation value of MVPcontrol.  Break those assumptions, and you'll get inconsistent state dumps like this, and very possibly incorrect execution.   Particularly if what was done was that effectively replaces the SMTC-specific implementation of local_irq_save()/local_irq_restore() with something that uses the generic MIPS32R2 atomic interrupt enable/disable instructions.  That would have been a *very* bad idea...             Regards,             Kevin K. From Anoop_P.A@pmc-sierra.com Tue Dec 21 21:29:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 21:29:18 +0100 (CET) Received: from bby1mta03.pmc-sierra.com ([216.241.235.118]:33227 "EHLO bby1mta03.pmc-sierra.bc.ca" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492822Ab0LUU3O convert rfc822-to-8bit (ORCPT ); Tue, 21 Dec 2010 21:29:14 +0100 Received: from bby1mta03.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id D18FC10711BC; Tue, 21 Dec 2010 12:29:06 -0800 (PST) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (bby1exg02 [216.241.231.167]) by bby1mta03.pmc-sierra.bc.ca (Postfix) with SMTP id B5D4D1070F30; Tue, 21 Dec 2010 12:29:06 -0800 (PST) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.159]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 12:29:06 -0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: RE: SMTC support status in latest git head. Date: Tue, 21 Dec 2010 12:29:03 -0800 Message-ID: In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: SMTC support status in latest git head. Thread-Index: AcuhQGKZ5K7N538AQs2q7v545EZbTwACfOSAAACxQeA= References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> <4D0BD7A0.1030504@paralogos.com> <4D10F7A9.1020306@paralogos.com> From: "Anoop P.A." To: "Anoop P.A." , "Kevin D. Kissell" , "Anoop P A" Cc: "STUART VENTERS" , X-OriginalArrivalTime: 21 Dec 2010 20:29:06.0688 (UTC) FILETIME=[B71D1000:01CBA14D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28668 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips Content-Length: 18962 Lines: 415 Sorry I misunderstood file. git blame shows that "andi" is around for quite sometime . 49a89efb include/asm-mips/irqflags.h (Ralf Baechle 2007-10-11 23:46:15 +0100 128) __asm__( df9ee292 arch/mips/include/asm/irqflags.h (David Howells 2010-10-07 14:08:55 +0100 129) " .macro arch_local_irq_save result ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 130) " .set push ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 131) " .set reorder ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 132) " .set noat 41c594ab include/asm-mips/interrupt.h (Ralf Baechle 2006-04-05 09:45:45 +0100 133) #ifdef CONFIG_MIPS_MT_SMTC 41c594ab include/asm-mips/interrupt.h (Ralf Baechle 2006-04-05 09:45:45 +0100 134) " mfc0 \\result, $2, 1 41c594ab include/asm-mips/interrupt.h (Ralf Baechle 2006-04-05 09:45:45 +0100 135) " ori $1, \\result, 0x400 41c594ab include/asm-mips/interrupt.h (Ralf Baechle 2006-04-05 09:45:45 +0100 136) " .set noreorder 41c594ab include/asm-mips/interrupt.h (Ralf Baechle 2006-04-05 09:45:45 +0100 137) " mtc0 $1, $2, 1 41c594ab include/asm-mips/interrupt.h (Ralf Baechle 2006-04-05 09:45:45 +0100 138) " andi \\result, \\result, 0x400 41c594ab include/asm-mips/interrupt.h (Ralf Baechle 2006-04-05 09:45:45 +0100 139) #elif defined(CONFIG_CPU_MIPSR2) ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 140) " di \\result 15265251 include/asm-mips/interrupt.h (Maxime Bizon 2005-12-20 06:32:19 +0100 141) " andi \\result, 1 ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 142) #else ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 143) " mfc0 \\result, $12 c226f260 include/asm-mips/interrupt.h (Atsushi Nemoto 2006-02-03 01:34:01 +0900 144) " ori $1, \\result, 0x1f c226f260 include/asm-mips/interrupt.h (Atsushi Nemoto 2006-02-03 01:34:01 +0900 145) " xori $1, 0x1f ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 146) " .set noreorder ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 147) " mtc0 $1, $12 ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 148) #endif ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 149) " irq_disable_hazard ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 150) " .set pop ff88f8a3 include/asm-mips/interrupt.h (Ralf Baechle 2005-07-12 14:54:31 +0000 151) " .endm ^1da177e include/asm-mips/interrupt.h (Linus Torvalds 2005-04-16 15:20:36 -0700 152) > -----Original Message----- > From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux- > mips.org] On Behalf Of Anoop P.A. > Sent: Wednesday, December 22, 2010 1:37 AM > To: Kevin D. Kissell; Anoop P A > Cc: STUART VENTERS; linux-mips@linux-mips.org > Subject: RE: SMTC support status in latest git head. > > > OK. I will check it. > > BTW following patch is responsible for irq change. > > http://git.linux- > mips.org/?p=linux.git;a=commitdiff;h=df9ee29270c11dba7d0fe0b83ce47a4d8e8d2 > 101 > > Thanks > Anoop > ________________________________________ > From: Kevin D. Kissell [mailto:kevink@paralogos.com] > Sent: Wednesday, December 22, 2010 12:23 AM > To: Anoop P A > Cc: STUART VENTERS; linux-mips@linux-mips.org; Anoop P.A. > Subject: Re: SMTC support status in latest git head. > > OK, I see why the MT register dump isn't giving us useful information. > It's not clear that it's at the root of your functional problems, though. > Apparently, somebody decided that it was unwholesome to propagate anything > other than the previous interrupt enable state in the flags variable > passed between irq_save() and irq_restore().  I agree philosophically, but > it does break the MT register dump function.  And I'm quite sure that > there were other bits of SMTC code that knew that it was a TCStatus value, > at least in the earliest versions of the code.  I'm not a gitweb power > user,  but I haven't been able to figure out how to determine when the > "andi \\result 0x400" on or about line 138 of irqflags.h (at least that's > where it is in the head of tree) was checked-in.  If it's at the boundary > between working and non-working versions for SMTC, it might be the cause > of the problems, but it may well not be responsible for anything other > than the problem with reporting the value in > the MT register dump - which really ought to be fixed. > > I'm in a small village in France for the holidays with no git/build system > at my disposal, but I think that if you were to tweak mips-mt.c at line > 103 to change > the > >         tcstatval = flags; /* And pre-dump TCStatus is flags */ > > > > to something more like > > > > /* Pre-dump TCStatus Interrupt Inhibit bit is in flags variable > */ > > tcstatval = (read_c0_tcstatus() & ~0x400) | flags; > > > > should fix the dump. > >             Regards, > >             Kevin K. > > On 12/20/10 2:44 AM, Anoop P A wrote: > Hi Kevin, > > Please find disassembly for mips_mt_reg_dump > > Thanks > Anoop > > Disassembly of section .text: > > 00000000 : > 0: 27bdffb8 addiu sp,sp,-72 > 4: 00802821 move a1,a0 > 8: afbf0044 sw ra,68(sp) > c: afbe0040 sw s8,64(sp) > 10: afb7003c sw s7,60(sp) > 14: afb60038 sw s6,56(sp) > 18: afb50034 sw s5,52(sp) > 1c: afb40030 sw s4,48(sp) > 20: afb3002c sw s3,44(sp) > 24: afb20028 sw s2,40(sp) > 28: afb10024 sw s1,36(sp) > 2c: afb00020 sw s0,32(sp) > 30: 40141001 mfc0 s4,c0_tcstatus > 34: 36810400 ori at,s4,0x400 > 38: 40811001 mtc0 at,c0_tcstatus > 3c: 32940400 andi s4,s4,0x400 > 40: 000000c0 ehb > 44: 41610001 dvpe at > 48: 0020a821 move s5,at > 4c: 000000c0 ehb > 50: 3c020000 lui v0,0x0 > 54: 24420060 addiu v0,v0,96 > 58: 00400408 jr.hb v0 > 5c: 00000000 nop > 60: 3c040000 lui a0,0x0 > 64: 24840000 addiu a0,a0,0 > 68: 0c000000 jal 0 > 6c: afa50010 sw a1,16(sp) > 70: 3c040000 lui a0,0x0 > 74: 0c000000 jal 0 > 78: 24840000 addiu a0,a0,0 > 7c: 8fa50010 lw a1,16(sp) > 80: 3c040000 lui a0,0x0 > 84: 0c000000 jal 0 > 88: 24840000 addiu a0,a0,0 > 8c: 3c040000 lui a0,0x0 > 90: 24840000 addiu a0,a0,0 > 94: 0c000000 jal 0 > 98: 02a02821 move a1,s5 > 9c: 40110002 mfc0 s1,c0_mvpconf0 > a0: 3c040000 lui a0,0x0 > a4: 02202821 move a1,s1 > a8: 0c000000 jal 0 > ac: 24840000 addiu a0,a0,0 > b0: 3c040000 lui a0,0x0 > b4: 0c000000 jal 0 > b8: 24840000 addiu a0,a0,0 > bc: 7e331a80 ext s3,s1,0xa,0x4 > c0: 3c090000 lui t1,0x0 > c4: 323100ff andi s1,s1,0xff > c8: 3c080000 lui t0,0x0 > cc: 3c030000 lui v1,0x0 > d0: 3c1e0000 lui s8,0x0 > d4: 3c170000 lui s7,0x0 > d8: 3c160000 lui s6,0x0 > dc: 3c0a0000 lui t2,0x0 > e0: 26730001 addiu s3,s3,1 > e4: 26310001 addiu s1,s1,1 > e8: 00008021 move s0,zero > ec: 2412ff00 li s2,-256 > f0: 25290000 addiu t1,t1,0 > f4: 25080000 addiu t0,t0,0 > f8: 24630000 addiu v1,v1,0 > fc: 27de0000 addiu s8,s8,0 > 100: 26f70000 addiu s7,s7,0 > 104: 26d60000 addiu s6,s6,0 > 108: 254a0000 addiu t2,t2,0 > 10c: 00001021 move v0,zero > 110: 40040801 mfc0 a0,c0_vpecontrol > 114: 00922024 and a0,a0,s2 > 118: 00442025 or a0,v0,a0 > 11c: 40840801 mtc0 a0,c0_vpecontrol > 120: 000000c0 ehb > 124: 41020802 mftc0 at,c0_tcbind > 128: 00202021 move a0,at > 12c: 24420001 addiu v0,v0,1 > 130: 3084000f andi a0,a0,0xf > 134: 12040031 beq s0,a0,1fc > 138: 0051282a slt a1,v0,s1 > 13c: 14a0fff4 bnez a1,110 > 140: 00000000 nop > 144: 26100001 addiu s0,s0,1 > 148: 0213102a slt v0,s0,s3 > 14c: 1440fff0 bnez v0,110 > 150: 00001021 move v0,zero > 154: 3c040000 lui a0,0x0 > 158: 24840000 addiu a0,a0,0 > 15c: 3c1e0000 lui s8,0x0 > 160: 3c170000 lui s7,0x0 > 164: 3c160000 lui s6,0x0 > 168: 3c130000 lui s3,0x0 > 16c: 0c000000 jal 0 > 170: 3c120000 lui s2,0x0 > 174: 00008021 move s0,zero > 178: 27de0000 addiu s8,s8,0 > 17c: 26f70000 addiu s7,s7,0 > 180: 26d60000 addiu s6,s6,0 > 184: 26730000 addiu s3,s3,0 > 188: 26520000 addiu s2,s2,0 > 18c: 40020801 mfc0 v0,c0_vpecontrol > 190: 2403ff00 li v1,-256 > 194: 00431024 and v0,v0,v1 > 198: 02021025 or v0,s0,v0 > 19c: 40820801 mtc0 v0,c0_vpecontrol > 1a0: 000000c0 ehb > 1a4: 41020802 mftc0 at,c0_tcbind > 1a8: 00201821 move v1,at > 1ac: 40021002 mfc0 v0,c0_tcbind > 1b0: 1062003f beq v1,v0,2b0 > 1b4: 00000000 nop > 1b8: 41020804 mftc0 at,c0_tchalt > 1bc: 00201821 move v1,at > 1c0: 24020001 li v0,1 > 1c4: 00400821 move at,v0 > 1c8: 41811004 mttc0 at,c0_tchalt > 1cc: 41020801 mftc0 at,c0_tcstatus > 1d0: 00203021 move a2,at > 1d4: 3c040000 lui a0,0x0 > 1d8: 02002821 move a1,s0 > 1dc: 24840000 addiu a0,a0,0 > 1e0: afa3001c sw v1,28(sp) > 1e4: 0c000000 jal 0 > 1e8: afa60010 sw a2,16(sp) > 1ec: 8fa60010 lw a2,16(sp) > 1f0: 8fa3001c lw v1,28(sp) > 1f4: 080000b2 j 2c8 > 1f8: 00c02821 move a1,a2 > 1fc: 01202021 move a0,t1 > 200: 02002821 move a1,s0 > 204: afa3001c sw v1,28(sp) > 208: afa80014 sw t0,20(sp) > 20c: afa90010 sw t1,16(sp) > 210: 0c000000 jal 0 > 214: afaa0018 sw t2,24(sp) > 218: 41010801 mftc0 at,c0_vpecontrol > 21c: 00202821 move a1,at > 220: 8fa80014 lw t0,20(sp) > 224: 0c000000 jal 0 > 228: 01002021 move a0,t0 > 22c: 41010802 mftc0 at,c0_vpeconf0 > 230: 00202821 move a1,at > 234: 8fa3001c lw v1,28(sp) > 238: 0c000000 jal 0 > 23c: 00602021 move a0,v1 > 240: 410c0800 mftc0 at,c0_status > 244: 00203021 move a2,at > 248: 03c02021 move a0,s8 > 24c: 0c000000 jal 0 > 250: 02002821 move a1,s0 > 254: 410e0800 mftc0 at,c0_epc > 258: 00203021 move a2,at > 25c: 410e0800 mftc0 at,c0_epc > 260: 00203821 move a3,at > 264: 02e02021 move a0,s7 > 268: 0c000000 jal 0 > 26c: 02002821 move a1,s0 > 270: 410d0800 mftc0 at,c0_cause > 274: 00203021 move a2,at > 278: 02c02021 move a0,s6 > 27c: 0c000000 jal 0 > 280: 02002821 move a1,s0 > 284: 41100807 mftc0 at,$16,7 > 288: 00203021 move a2,at > 28c: 8faa0018 lw t2,24(sp) > 290: 02002821 move a1,s0 > 294: 0c000000 jal 0 > 298: 01402021 move a0,t2 > 29c: 8fa3001c lw v1,28(sp) > 2a0: 8fa80014 lw t0,20(sp) > 2a4: 8fa90010 lw t1,16(sp) > 2a8: 08000051 j 144 > 2ac: 8faa0018 lw t2,24(sp) > 2b0: 3c040000 lui a0,0x0 > 2b4: 02002821 move a1,s0 > 2b8: 0c000000 jal 0 > 2bc: 24840000 addiu a0,a0,0 > 2c0: 00001821 move v1,zero > 2c4: 02802821 move a1,s4 > 2c8: 03c02021 move a0,s8 > 2cc: 0c000000 jal 0 > 2d0: afa3001c sw v1,28(sp) > 2d4: 41020802 mftc0 at,c0_tcbind > 2d8: 00202821 move a1,at > 2dc: 0c000000 jal 0 > 2e0: 02e02021 move a0,s7 > 2e4: 41020803 mftc0 at,c0_tcrestart > 2e8: 00202821 move a1,at > 2ec: 41020803 mftc0 at,c0_tcrestart > 2f0: 00203021 move a2,at > 2f4: 0c000000 jal 0 > 2f8: 02c02021 move a0,s6 > 2fc: 8fa3001c lw v1,28(sp) > 300: 02602021 move a0,s3 > 304: 0c000000 jal 0 > 308: 00602821 move a1,v1 > 30c: 41020805 mftc0 at,c0_tccontext > 310: 00202821 move a1,at > 314: 0c000000 jal 0 > 318: 02402021 move a0,s2 > 31c: 8fa3001c lw v1,28(sp) > 320: 14600003 bnez v1,330 > 324: 00001021 move v0,zero > 328: 00400821 move at,v0 > 32c: 41811004 mttc0 at,c0_tchalt > 330: 26100001 addiu s0,s0,1 > 334: 0211102a slt v0,s0,s1 > 338: 1440ff94 bnez v0,18c > 33c: 00000000 nop > 340: 0c000000 jal 0 > 344: 32b50001 andi s5,s5,0x1 > 348: 3c040000 lui a0,0x0 > 34c: 0c000000 jal 0 > 350: 24840000 addiu a0,a0,0 > 354: 12a00004 beqz s5,368 > 358: 32820400 andi v0,s4,0x400 > 35c: 41600021 evpe > 360: 000000c0 ehb > 364: 32820400 andi v0,s4,0x400 > 368: 14400003 bnez v0,378 > 36c: 00000000 nop > 370: 0c000000 jal 0 > 374: 00000000 nop > 378: 40011001 mfc0 at,c0_tcstatus > 37c: 32940400 andi s4,s4,0x400 > 380: 34210400 ori at,at,0x400 > 384: 38210400 xori at,at,0x400 > 388: 0281a025 or s4,s4,at > 38c: 40941001 mtc0 s4,c0_tcstatus > 390: 000000c0 ehb > 394: 8fbf0044 lw ra,68(sp) > 398: 8fbe0040 lw s8,64(sp) > 39c: 8fb7003c lw s7,60(sp) > 3a0: 8fb60038 lw s6,56(sp) > 3a4: 8fb50034 lw s5,52(sp) > 3a8: 8fb40030 lw s4,48(sp) > 3ac: 8fb3002c lw s3,44(sp) > 3b0: 8fb20028 lw s2,40(sp) > 3b4: 8fb10024 lw s1,36(sp) > 3b8: 8fb00020 lw s0,32(sp) > 3bc: 03e00008 jr ra > 3c0: 27bd0048 addiu sp,sp,72 > > > On Sat, Dec 18, 2010 at 3:05 AM, Kevin D. Kissell > wrote: > So, Anoop, if you get a minute for this any time in the next day or so > (after which I'll have very limited net access until next year), could you > please do an -mips-objdump --disassemble of your kernel > image (or even just the mips-mt.o module) from a failing kernel build and > post the disassembly of mips_mt_regdump()?  The confirmation or refutation > of the theory about local_irq_save() no longer being built correctly for > SMTC would be within the first few instructions... > > /K. > > > On 12/16/10 11:58, Kevin D. Kissell wrote: > Ralf tells me that this message got blocked by the LMO server due to HTML > content. > So here it is again, textier. > > On 12/16/10 11:24, Kevin D. Kissell wrote: > On 12/16/10 07:37, STUART VENTERS wrote: > > Two other possible clues: > > The EVP is clear in the MVPControl register. > Does this say that only VPE0, T0 gets to run? > That's correct.  In the maxtcs=1/maxvpes=1 boot state, it wouldn't matter. >  It's just possible that setting EVP is conditional on more than one VPE > being used, but that's not the way I remember it. > > Also the EXCPT bits in VPEControl for VPE1 indicate a Gating Storage > Exception dispatch. > But that seems to conflict the EVP bit above. > I don't have a copy of the ASE spec handy to see whether those bits have a > defined power-on value, but particularly if maxvpes=1 was set at boot > time, > I would expect VPE1's registers to be in a partly random power-up state. > > Perhaps these are an artifact of getting to a good state to dump things > out. > As per my previous mail, I looked at the MT register dump source, and it > really does pull values directly > out of registers and doesn't depend on having a sane kernel stack frame. >  The exceptions to that rule > are the reported values for TCStatus of the executing TC, which is based > on the perhaps-now-broken > assumption that local_irq_save(flags) stores the *entire* pre-invocation > value of the TCStatus register > in the flags variable, and MVPcontrol, which is based on the assumption > that dvpe() returns the pre-invocation > value of MVPcontrol.  Break those assumptions, and you'll get inconsistent > state dumps like this, > and very possibly incorrect execution.   Particularly if what was done was > that effectively replaces > the SMTC-specific implementation of local_irq_save()/local_irq_restore() > with something that uses > the generic MIPS32R2 atomic interrupt enable/disable instructions.  That > would have been a *very* bad idea... > >             Regards, > >             Kevin K. > > > From David.Daney@caviumnetworks.com Tue Dec 21 23:19:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 23:19:27 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12580 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491758Ab0LUWTX (ORCPT ); Tue, 21 Dec 2010 23:19:23 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 21 Dec 2010 14:20:04 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 14:20:41 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 14:20:41 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBLMJFxj011454; Tue, 21 Dec 2010 14:19:15 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBLMJDMD011453; Tue, 21 Dec 2010 14:19:13 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2 0/3] Allow processors with scratch registers to use them for TLB refill. Date: Tue, 21 Dec 2010 14:19:08 -0800 Message-Id: <1292969951-11418-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 21 Dec 2010 22:20:41.0956 (UTC) FILETIME=[4DCDE240:01CBA15D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28669 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1408 Lines: 45 v2: Declare pgd_current for mipsr1 and mips32 builds. This other patch set: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1292889290-12849-1-git-send-email-ddaney%40caviumnetworks.com Should still be applied *after* this one. From v1: The MIPS32r2 and MIPS64r2 specifications allow processors to have scratch registers in coprocessor 0. If these are present, we can use one of them to carry the current PGD and save three instructions in the TLB handlers. There are three patches: 1 - Probe for presence of scratch registers an print number found in /proc/cpuinfo. 2 - Add DINSM to uasm for use by patch 3. 3 - Convert the TLB handlers. This also involves dynamically generating tlbmiss_handler_setup_pgd, which used to be statically defined. David Daney (3): MIPS: Probe for presence of KScratch registers. MIPS: Add DINSM to uasm. MIPS: Use C0_KScratch (if present) to hold PGD pointer. arch/mips/include/asm/cpu-info.h | 1 + arch/mips/include/asm/mmu_context.h | 8 +-- arch/mips/include/asm/uasm.h | 1 + arch/mips/kernel/cpu-probe.c | 2 + arch/mips/kernel/proc.c | 2 + arch/mips/kernel/traps.c | 2 +- arch/mips/mm/tlbex.c | 116 ++++++++++++++++++++++++++++++++--- arch/mips/mm/uasm.c | 11 +++- 8 files changed, 124 insertions(+), 19 deletions(-) -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Dec 21 23:19:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 23:19:54 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12582 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491840Ab0LUWT0 (ORCPT ); Tue, 21 Dec 2010 23:19:26 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 21 Dec 2010 14:20:09 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 14:20:46 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 14:20:46 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBLMJKVk011463; Tue, 21 Dec 2010 14:19:20 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBLMJKQg011462; Tue, 21 Dec 2010 14:19:20 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2 2/3] MIPS: Add DINSM to uasm. Date: Tue, 21 Dec 2010 14:19:10 -0800 Message-Id: <1292969951-11418-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292969951-11418-1-git-send-email-ddaney@caviumnetworks.com> References: <1292969951-11418-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 21 Dec 2010 22:20:46.0816 (UTC) FILETIME=[50B37600:01CBA15D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28670 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 2024 Lines: 64 Signed-off-by: David Daney --- arch/mips/include/asm/uasm.h | 1 + arch/mips/mm/uasm.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 892062d..99dae68 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -115,6 +115,7 @@ Ip_0(_tlbwr); Ip_u3u1u2(_xor); Ip_u2u1u3(_xori); Ip_u2u1msbu3(_dins); +Ip_u2u1msbu3(_dinsm); Ip_u1(_syscall); /* Handle labels. */ diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 23afdeb..99f0347 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -68,7 +68,7 @@ enum opcode { insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, - insn_dins, insn_syscall, insn_bbit0, insn_bbit1 + insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1 }; struct insn { @@ -142,6 +142,7 @@ static struct insn insn_table[] __uasminitdata = { { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, + { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, @@ -340,6 +341,13 @@ Ip_u2u1msbu3(op) \ } \ UASM_EXPORT_SYMBOL(uasm_i##op); +#define I_u2u1msb32u3(op) \ +Ip_u2u1msbu3(op) \ +{ \ + build_insn(buf, insn##op, b, a, c+d-33, c); \ +} \ +UASM_EXPORT_SYMBOL(uasm_i##op); + #define I_u1u2(op) \ Ip_u1u2(op) \ { \ @@ -422,6 +430,7 @@ I_0(_tlbwr) I_u3u1u2(_xor) I_u2u1u3(_xori) I_u2u1msbu3(_dins); +I_u2u1msb32u3(_dinsm); I_u1(_syscall); I_u1u2s3(_bbit0); I_u1u2s3(_bbit1); -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Dec 21 23:20:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 23:20:20 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12581 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491118Ab0LUWT0 (ORCPT ); Tue, 21 Dec 2010 23:19:26 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 21 Dec 2010 14:20:09 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 14:20:46 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 14:20:46 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBLMJLP9011467; Tue, 21 Dec 2010 14:19:21 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBLMJLen011466; Tue, 21 Dec 2010 14:19:21 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2 3/3] MIPS: Use C0_KScratch (if present) to hold PGD pointer. Date: Tue, 21 Dec 2010 14:19:11 -0800 Message-Id: <1292969951-11418-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292969951-11418-1-git-send-email-ddaney@caviumnetworks.com> References: <1292969951-11418-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 21 Dec 2010 22:20:46.0816 (UTC) FILETIME=[50B37600:01CBA15D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28671 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 6691 Lines: 230 Decide at runtime to use either Context or KScratch to hold the PGD pointer. Signed-off-by: David Daney --- arch/mips/include/asm/mmu_context.h | 8 +-- arch/mips/kernel/traps.c | 2 +- arch/mips/mm/tlbex.c | 116 ++++++++++++++++++++++++++++++++--- 3 files changed, 108 insertions(+), 18 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d959273..73c0d45 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -29,13 +29,7 @@ #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)) -static inline void tlbmiss_handler_setup_pgd(unsigned long pgd) -{ - /* Check for swapper_pg_dir and convert to physical address. */ - if ((pgd & CKSEG3) == CKSEG0) - pgd = CPHYSADDR(pgd); - write_c0_context(pgd << 11); -} +extern void tlbmiss_handler_setup_pgd(unsigned long pgd); #define TLBMISS_HANDLER_SETUP() \ do { \ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e971043..71350f7 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1592,7 +1592,6 @@ void __cpuinit per_cpu_trap_init(void) #endif /* CONFIG_MIPS_MT_SMTC */ cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; - TLBMISS_HANDLER_SETUP(); atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; @@ -1614,6 +1613,7 @@ void __cpuinit per_cpu_trap_init(void) write_c0_wired(0); } #endif /* CONFIG_MIPS_MT_SMTC */ + TLBMISS_HANDLER_SETUP(); } /* Install CPU exception handler */ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 93816f3..0bb4c3b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -26,8 +26,10 @@ #include #include #include +#include -#include +#include +#include #include #include @@ -173,11 +175,38 @@ static struct uasm_reloc relocs[128] __cpuinitdata; static int check_for_high_segbits __cpuinitdata; #endif -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + +static unsigned int kscratch_used_mask __cpuinitdata; + +static int __cpuinit allocate_kscratch(void) +{ + int r; + unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; + + r = ffs(a); + + if (r == 0) + return -1; + + r--; /* make it zero based */ + + kscratch_used_mask |= (1 << r); + + return r; +} + +static int pgd_reg __cpuinitdata; + +#else /* !CONFIG_MIPS_PGD_C0_CONTEXT*/ /* * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, * we cannot do r3000 under these circumstances. + * + * Declare pgd_current here instead of including mmu_context.h to avoid type + * conflicts for tlbmiss_handler_setup_pgd */ +extern unsigned long pgd_current[]; /* * The R3000 TLB handler is simple. @@ -573,13 +602,22 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ #ifdef CONFIG_MIPS_PGD_C0_CONTEXT - /* - * &pgd << 11 stored in CONTEXT [23..63]. - */ - UASM_i_MFC0(p, ptr, C0_CONTEXT); - uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */ - uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_drotr(p, ptr, ptr, 11); + if (pgd_reg != -1) { + /* pgd is in pgd_reg */ + UASM_i_MFC0(p, ptr, 31, pgd_reg); + } else { + /* + * &pgd << 11 stored in CONTEXT [23..63]. + */ + UASM_i_MFC0(p, ptr, C0_CONTEXT); + + /* Clear lower 23 bits of context. */ + uasm_i_dins(p, ptr, 0, 0, 23); + + /* 1 0 1 0 1 << 6 xkphys cached */ + uasm_i_ori(p, ptr, ptr, 0x540); + uasm_i_drotr(p, ptr, ptr, 11); + } #elif defined(CONFIG_SMP) # ifdef CONFIG_MIPS_MT_SMTC /* @@ -1014,6 +1052,55 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT +u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned; + +static void __cpuinit build_r4000_setup_pgd(void) +{ + const int a0 = 4; + const int a1 = 5; + u32 *p = tlbmiss_handler_setup_pgd; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + + memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd)); + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + pgd_reg = allocate_kscratch(); + + if (pgd_reg == -1) { + /* PGD << 11 in c0_Context */ + /* + * If it is a ckseg0 address, convert to a physical + * address. Shifting right by 29 and adding 4 will + * result in zero for these addresses. + * + */ + UASM_i_SRA(&p, a1, a0, 29); + UASM_i_ADDIU(&p, a1, a1, 4); + uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); + uasm_i_nop(&p); + uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); + uasm_l_tlbl_goaround1(&l, p); + UASM_i_SLL(&p, a0, a0, 11); + uasm_i_jr(&p, 31); + UASM_i_MTC0(&p, a0, C0_CONTEXT); + } else { + /* PGD in c0_KScratch */ + uasm_i_jr(&p, 31); + UASM_i_MTC0(&p, a0, 31, pgd_reg); + } + if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd)) + panic("tlbmiss_handler_setup_pgd space exceeded"); + uasm_resolve_relocs(relocs, labels); + pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", + (unsigned int)(p - tlbmiss_handler_setup_pgd)); + + dump_handler(tlbmiss_handler_setup_pgd, + ARRAY_SIZE(tlbmiss_handler_setup_pgd)); +} +#endif static void __cpuinit iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) @@ -1161,6 +1248,8 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r, } #ifndef CONFIG_MIPS_PGD_C0_CONTEXT + + /* * R3000 style TLB load/store/modify handlers. */ @@ -1623,13 +1712,16 @@ void __cpuinit build_tlb_refill_handler(void) break; default: - build_r4000_tlb_refill_handler(); if (!run_once) { +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + build_r4000_setup_pgd(); +#endif build_r4000_tlb_load_handler(); build_r4000_tlb_store_handler(); build_r4000_tlb_modify_handler(); run_once++; } + build_r4000_tlb_refill_handler(); } } @@ -1641,4 +1733,8 @@ void __cpuinit flush_tlb_handlers(void) (unsigned long)handle_tlbs + sizeof(handle_tlbs)); local_flush_icache_range((unsigned long)handle_tlbm, (unsigned long)handle_tlbm + sizeof(handle_tlbm)); +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, + (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm)); +#endif } -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Dec 21 23:20:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Dec 2010 23:20:42 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12583 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490956Ab0LUWTa (ORCPT ); Tue, 21 Dec 2010 23:19:30 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 21 Dec 2010 14:20:14 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 14:20:51 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 21 Dec 2010 14:20:51 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oBLMJIn7011459; Tue, 21 Dec 2010 14:19:18 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oBLMJHBG011458; Tue, 21 Dec 2010 14:19:17 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH v2 1/3] MIPS: Probe for presence of KScratch registers. Date: Tue, 21 Dec 2010 14:19:09 -0800 Message-Id: <1292969951-11418-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292969951-11418-1-git-send-email-ddaney@caviumnetworks.com> References: <1292969951-11418-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 21 Dec 2010 22:20:51.0550 (UTC) FILETIME=[5385CFE0:01CBA15D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28672 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1758 Lines: 51 Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by: David Daney --- arch/mips/include/asm/cpu-info.h | 1 + arch/mips/kernel/cpu-probe.c | 2 ++ arch/mips/kernel/proc.c | 2 ++ 3 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index b39def3..c454550 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -78,6 +78,7 @@ struct cpuinfo_mips { unsigned int watch_reg_use_cnt; /* Usable by ptrace */ #define NUM_WATCH_REGS 4 u16 watch_reg_masks[NUM_WATCH_REGS]; + unsigned int kscratch_mask; /* Usable KScratch mask. */ } __attribute__((aligned(SMP_CACHE_BYTES))); extern struct cpuinfo_mips cpu_data[]; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 68dae7b..f65d4c8 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -739,6 +739,8 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c) && cpu_has_tlb) c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; + c->kscratch_mask = (config4 >> 16) & 0xff; + return config4 & MIPS_CONF_M; } diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 26109c4..f40bd6b 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -69,6 +69,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) ); seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); + seq_printf(m, "kscratch registers\t: %d\n", + hweight8(cpu_data[n].kscratch_mask)); seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", -- 1.7.2.3 From kevink@paralogos.com Wed Dec 22 11:27:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 11:27:48 +0100 (CET) Received: from gateway15.websitewelcome.com ([69.56.150.8]:55588 "HELO gateway15.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1490979Ab0LVK1o (ORCPT ); Wed, 22 Dec 2010 11:27:44 +0100 Received: (qmail 22218 invoked from network); 22 Dec 2010 10:27:48 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway15.websitewelcome.com with SMTP; 22 Dec 2010 10:27:48 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=WEcPoa+vVA5YNH/3DHbv7SY5xmIjyfVIZAQydnXTJcdCew8EsglOlNjYZnNermcqzN8LL/ZvjG7soP6l47MygaqvYDeNTOWKFI/zsC89+U/xzHKZjBj3c1t+Q+f+/BO7; Received: from [88.123.214.42] (port=49815 helo=kkissell-macbookpro.local) by gator750.hostgator.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1PVLv0-0001V7-HJ; Wed, 22 Dec 2010 04:27:39 -0600 Message-ID: <4D11D28D.80501@paralogos.com> Date: Wed, 22 Dec 2010 02:27:25 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: "Anoop P.A." CC: Anoop P A , STUART VENTERS , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> <4D0BD7A0.1030504@paralogos.com> <4D10F7A9.1020306@paralogos.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28673 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 1272 Lines: 35 > Sorry I misunderstood file. git blame shows that "andi" is around for quite > some time. I've never used git blame, so I don't know how far it can be trusted, but if that change was made in 2006, that would predate the major breakage by several years. So my suggestion from yesterday is a reasonable one: > I think that if you were to tweak mips-mt.c at line 103 to change > the > > tcstatval = flags; /* And pre-dump TCStatus is flags */ > > to something more like > > /* Pre-dump TCStatus Interrupt Inhibit bit is in flags variable */ > tcstatval = (read_c0_tcstatus() & ~0x400) | flags; > > should fix the dump. With that patch, if you re-run the experiment of hang-breakout-dump, we might be able to deduce something. Ralf wrote to me independently to say that my message from yesterday with that suggestion and some other commentary got eaten once again by the LMO mail forwarder because of the HTML content. With all due respect, I'm using a very standard open-source mail client (Thunderbird) with a very normal option (reply to text with text, HTML with HTML). Perhaps it it's the LMO mail system that needs to change, and not the mail configurations of the whole LMO community. Regards, Kevin K. From anoop.pa@gmail.com Wed Dec 22 12:27:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 12:27:18 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:61878 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490992Ab0LVL1P (ORCPT ); Wed, 22 Dec 2010 12:27:15 +0100 Received: by gyg4 with SMTP id 4so2327988gyg.36 for ; Wed, 22 Dec 2010 03:27:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=raD3TO90jUl//qiJPJFjzrg50H4GsXY/GxEg50Z9atY=; b=ov2VpoI6B7HRs5xnwujnHYfKOuEjasP+plY8frsfO6AYp7dYzmkL+jWJtYJoHk8oIV wIvYtmA6VlfsNeUPhPi/HKPxRC6J5bGPVfmYbJvua75iM5gb6Tw3HMOzcZTGeDJ9Dqug p5Cxzyqn0uLqzVgL6mOwwU0n6ZChfC1IhxahY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=xrjmHVchz/tbArudqQQdsp2sZv9S6OZUhtQW3dcG3j4T6WCDnjEzbQGnni6Z6tk7NZ i9uRXmymqwqtjD7HNMQCrecx00ifGrpE4m+EOaeCBURIYGGSOVbqrcOQxv3k22G7lIIG 13s/19hWZv936BqFffwkPPs64qEhbv4pdG77I= Received: by 10.150.145.4 with SMTP id s4mr10223601ybd.10.1293017227258; Wed, 22 Dec 2010 03:27:07 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id u31sm5737590yba.21.2010.12.22.03.27.02 (version=SSLv3 cipher=RC4-MD5); Wed, 22 Dec 2010 03:27:04 -0800 (PST) Subject: Re: SMTC support status in latest git head. From: Anoop P A To: "Kevin D. Kissell" Cc: "Anoop P.A." , STUART VENTERS , linux-mips@linux-mips.org In-Reply-To: <4D11D28D.80501@paralogos.com> References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> <4D0BD7A0.1030504@paralogos.com> <4D10F7A9.1020306@paralogos.com> <4D11D28D.80501@paralogos.com> Content-Type: text/plain; charset="UTF-8" Date: Wed, 22 Dec 2010 17:05:02 +0530 Message-ID: <1293017702.27661.36.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28674 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 6693 Lines: 179 On Wed, 2010-12-22 at 02:27 -0800, Kevin D. Kissell wrote: > > Sorry I misunderstood file. git blame shows that "andi" is around for > quite > > some time. > > I've never used git blame, so I don't know how far it can be trusted, > but if that change was made in 2006, that would predate the major > breakage by several > years. So my suggestion from yesterday is a reasonable one: That change is present in booting 2.6.32 kernel.Corresponding patch can be found in gitweb . http://git.linux-mips.org/?p=linux.git;a=commitdiff;h=41c594ab65fc89573af296d192aa5235d09717ab#patch39 > > > I think that if you were to tweak mips-mt.c at line 103 to change > > the > > > > tcstatval = flags; /* And pre-dump TCStatus is flags */ > > > > to something more like > > > > /* Pre-dump TCStatus Interrupt Inhibit bit is in flags variable */ > > tcstatval = (read_c0_tcstatus() & ~0x400) | flags; > > > > should fix the dump. > > With that patch, if you re-run the experiment of hang-breakout-dump, we > might be able to deduce something. Here is the dump with the patch. [ 0.000000] Calibrating delay loop... === MIPS MT State Dump === [ 0.000000] -- Global State -- [ 0.000000] MVPControl Passed: 00000000 [ 0.000000] MVPControl Read: 00000000 [ 0.000000] MVPConf0 : a8008406 [ 0.000000] -- per-VPE State -- [ 0.000000] VPE 0 [ 0.000000] VPEControl : 00000000 [ 0.000000] VPEConf0 : 800f0003 [ 0.000000] VPE0.Status : 11004001 [ 0.000000] VPE0.EPC : 80100000 _stext+0x0/0x10 [ 0.000000] VPE0.Cause : e080407c [ 0.000000] VPE0.Config7 : 00010000 [ 0.000000] VPE 1 [ 0.000000] VPEControl : 00030000 [ 0.000000] VPEConf0 : 800f0000 [ 0.000000] VPE1.Status : 00407904 [ 0.000000] VPE1.EPC : fffdffff 0xfffdffff [ 0.000000] VPE1.Cause : 4000027c [ 0.000000] VPE1.Config7 : 00010000 [ 0.000000] -- per-TC State -- [ 0.000000] TC 0 (current TC with VPE EPC above) [ 0.000000] TCStatus : 11004001 [ 0.000000] TCBind : 00000000 [ 0.000000] TCRestart : 803fc408 printk+0x10/0x30 [ 0.000000] TCHalt : 00000000 [ 0.000000] TCContext : 00000000 [ 0.000000] TC 1 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00200001 [ 0.000000] TCRestart : 3ffffffe 0x3ffffffe [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : efffffff [ 0.000000] TC 2 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00400001 [ 0.000000] TCRestart : ffffffee 0xffffffee [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : efffffbf [ 0.000000] TC 3 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00600001 [ 0.000000] TCRestart : ffe00200 0xffe00200 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 7fffb77f [ 0.000000] TC 4 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00800001 [ 0.000000] TCRestart : ffe00200 0xffe00200 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : 7ffdf736 [ 0.000000] TC 5 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00a00001 [ 0.000000] TCRestart : ffe00200 0xffe00200 [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : ee5ffff7 [ 0.000000] TC 6 [ 0.000000] TCStatus : 00000000 [ 0.000000] TCBind : 00c00001 [ 0.000000] TCRestart : f7ff7ffe 0xf7ff7ffe [ 0.000000] TCHalt : 00000001 [ 0.000000] TCContext : e6fffffb [ 0.000000] Counter Interrupts taken per CPU (TC) [ 0.000000] 0: 0 [ 0.000000] 1: 0 [ 0.000000] Self-IPI invocations: [ 0.000000] 0: 0 [ 0.000000] 1: 0 [ 0.000000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 [ 0.000000] 0 Recoveries of "stolen" FPU [ 0.000000] =========================== [ 0.010000] === MIPS MT State Dump === [ 0.010000] -- Global State -- [ 0.010000] MVPControl Passed: 00000000 [ 0.010000] MVPControl Read: 00000000 [ 0.010000] MVPConf0 : a8008406 [ 0.010000] -- per-VPE State -- [ 0.010000] VPE 0 [ 0.010000] VPEControl : 00000000 [ 0.010000] VPEConf0 : 800f0003 [ 0.010000] VPE0.Status : 18004000 [ 0.010000] VPE0.EPC : 8010c9b4 mips_mt_regdump+0x3a4/0x3d4 [ 0.010000] VPE0.Cause : 50804000 [ 0.010000] VPE0.Config7 : 00010000 [ 0.010000] VPE 1 [ 0.010000] VPEControl : 00030000 [ 0.010000] VPEConf0 : 800f0000 [ 0.010000] VPE1.Status : 00407904 [ 0.010000] VPE1.EPC : fffdffff 0xfffdffff [ 0.010000] VPE1.Cause : 4000027c [ 0.010000] VPE1.Config7 : 00010000 [ 0.010000] -- per-TC State -- [ 0.010000] TC 0 (current TC with VPE EPC above) [ 0.010000] TCStatus : 18004000 [ 0.010000] TCBind : 00000000 [ 0.010000] TCRestart : 803fc408 printk+0x10/0x30 [ 0.010000] TCHalt : 00000000 [ 0.010000] TCContext : 00000000 [ 0.010000] TC 1 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00200001 [ 0.010000] TCRestart : 3ffffffe 0x3ffffffe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : efffffff [ 0.010000] TC 2 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00400001 [ 0.010000] TCRestart : ffffffee 0xffffffee [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : efffffbf [ 0.010000] TC 3 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00600001 [ 0.010000] TCRestart : ffe00200 0xffe00200 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 7fffb77f [ 0.010000] TC 4 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00800001 [ 0.010000] TCRestart : ffe00200 0xffe00200 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : 7ffdf736 [ 0.010000] TC 5 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00a00001 [ 0.010000] TCRestart : ffe00200 0xffe00200 [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : ee5ffff7 [ 0.010000] TC 6 [ 0.010000] TCStatus : 00000000 [ 0.010000] TCBind : 00c00001 [ 0.010000] TCRestart : f7ff7ffe 0xf7ff7ffe [ 0.010000] TCHalt : 00000001 [ 0.010000] TCContext : e6fffffb [ 0.010000] Counter Interrupts taken per CPU (TC) [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] Self-IPI invocations: [ 0.010000] 0: 0 [ 0.010000] 1: 0 [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 [ 0.010000] 0 Recoveries of "stolen" FPU [ 0.010000] =========================== From kevink@paralogos.com Wed Dec 22 12:37:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 12:37:15 +0100 (CET) Received: from gateway12.websitewelcome.com ([69.56.195.22]:36289 "HELO gateway12.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1490992Ab0LVLhM (ORCPT ); Wed, 22 Dec 2010 12:37:12 +0100 Received: (qmail 8577 invoked from network); 22 Dec 2010 11:36:27 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway12.websitewelcome.com with SMTP; 22 Dec 2010 11:36:27 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=Xciwu+OQBgxu4l0AUb9vsaK4K9ymDwWrA2yD+c2scXFQVurHC2m3gLxP3KnKtnQWBfappm20hZzxpqEJki/p/937CHvqv68ru/CRwnSDFSTean1FkhK25ohL+OzWr0lY; Received: from [88.123.214.42] (port=49197 helo=kkissell-macbookpro.local) by gator750.hostgator.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1PVN0E-0001qX-Su; Wed, 22 Dec 2010 05:37:07 -0600 Message-ID: <4D11E2E2.80809@paralogos.com> Date: Wed, 22 Dec 2010 03:37:06 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Anoop P A CC: "Anoop P.A." , STUART VENTERS , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> <4D0BD7A0.1030504@paralogos.com> <4D10F7A9.1020306@paralogos.com> <4D11D28D.80501@paralogos.com> <1293017702.27661.36.camel@paanoop1-desktop> In-Reply-To: <1293017702.27661.36.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28675 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 7936 Lines: 200 Thanks. This is indeed strange. The VPE0 Status and TC0 TCStatus/Cause all indicate that interrupts are enabled and not inhibited at the per-TC level, and the presumed timer interrupt, in the 0x4000 bit, is present and not masked-off. Logically, the system must be entering (and exiting) the interrupt handler, yet the timer calibration isn't completing. That leaves more complex possible explanations for failure, most of which would fall into two categories: 1) The platform interrupt handler is failing to decode the event properly as a timer event. 2) Despite there being only one TC active, the calibration code is waiting for some handshake from another "CPU" To test the first, you might consider adding a kprintf() to the case of a "spurious" timer-like interrupt being detected and ignored... Regards, Kevin K. On 12/22/10 3:35 AM, Anoop P A wrote: > On Wed, 2010-12-22 at 02:27 -0800, Kevin D. Kissell wrote: >>> Sorry I misunderstood file. git blame shows that "andi" is around for >> quite >> > some time. >> >> I've never used git blame, so I don't know how far it can be trusted, >> but if that change was made in 2006, that would predate the major >> breakage by several >> years. So my suggestion from yesterday is a reasonable one: > That change is present in booting 2.6.32 kernel.Corresponding patch can > be found in gitweb . > http://git.linux-mips.org/?p=linux.git;a=commitdiff;h=41c594ab65fc89573af296d192aa5235d09717ab#patch39 > >> > I think that if you were to tweak mips-mt.c at line 103 to change >> > the >> > >> > tcstatval = flags; /* And pre-dump TCStatus is flags */ >> > >> > to something more like >> > >> > /* Pre-dump TCStatus Interrupt Inhibit bit is in flags variable */ >> > tcstatval = (read_c0_tcstatus()& ~0x400) | flags; >> > >> > should fix the dump. >> >> With that patch, if you re-run the experiment of hang-breakout-dump, we >> might be able to deduce something. > Here is the dump with the patch. > > [ 0.000000] Calibrating delay loop... === MIPS MT State Dump === > [ 0.000000] -- Global State -- > [ 0.000000] MVPControl Passed: 00000000 > [ 0.000000] MVPControl Read: 00000000 > [ 0.000000] MVPConf0 : a8008406 > [ 0.000000] -- per-VPE State -- > [ 0.000000] VPE 0 > [ 0.000000] VPEControl : 00000000 > [ 0.000000] VPEConf0 : 800f0003 > [ 0.000000] VPE0.Status : 11004001 > [ 0.000000] VPE0.EPC : 80100000 _stext+0x0/0x10 > [ 0.000000] VPE0.Cause : e080407c > [ 0.000000] VPE0.Config7 : 00010000 > [ 0.000000] VPE 1 > [ 0.000000] VPEControl : 00030000 > [ 0.000000] VPEConf0 : 800f0000 > [ 0.000000] VPE1.Status : 00407904 > [ 0.000000] VPE1.EPC : fffdffff 0xfffdffff > [ 0.000000] VPE1.Cause : 4000027c > [ 0.000000] VPE1.Config7 : 00010000 > [ 0.000000] -- per-TC State -- > [ 0.000000] TC 0 (current TC with VPE EPC above) > [ 0.000000] TCStatus : 11004001 > [ 0.000000] TCBind : 00000000 > [ 0.000000] TCRestart : 803fc408 printk+0x10/0x30 > [ 0.000000] TCHalt : 00000000 > [ 0.000000] TCContext : 00000000 > [ 0.000000] TC 1 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00200001 > [ 0.000000] TCRestart : 3ffffffe 0x3ffffffe > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : efffffff > [ 0.000000] TC 2 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00400001 > [ 0.000000] TCRestart : ffffffee 0xffffffee > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : efffffbf > [ 0.000000] TC 3 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00600001 > [ 0.000000] TCRestart : ffe00200 0xffe00200 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 7fffb77f > [ 0.000000] TC 4 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00800001 > [ 0.000000] TCRestart : ffe00200 0xffe00200 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : 7ffdf736 > [ 0.000000] TC 5 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00a00001 > [ 0.000000] TCRestart : ffe00200 0xffe00200 > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : ee5ffff7 > [ 0.000000] TC 6 > [ 0.000000] TCStatus : 00000000 > [ 0.000000] TCBind : 00c00001 > [ 0.000000] TCRestart : f7ff7ffe 0xf7ff7ffe > [ 0.000000] TCHalt : 00000001 > [ 0.000000] TCContext : e6fffffb > [ 0.000000] Counter Interrupts taken per CPU (TC) > [ 0.000000] 0: 0 > [ 0.000000] 1: 0 > [ 0.000000] Self-IPI invocations: > [ 0.000000] 0: 0 > [ 0.000000] 1: 0 > [ 0.000000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > [ 0.000000] 0 Recoveries of "stolen" FPU > [ 0.000000] =========================== > [ 0.010000] === MIPS MT State Dump === > [ 0.010000] -- Global State -- > [ 0.010000] MVPControl Passed: 00000000 > [ 0.010000] MVPControl Read: 00000000 > [ 0.010000] MVPConf0 : a8008406 > [ 0.010000] -- per-VPE State -- > [ 0.010000] VPE 0 > [ 0.010000] VPEControl : 00000000 > [ 0.010000] VPEConf0 : 800f0003 > [ 0.010000] VPE0.Status : 18004000 > [ 0.010000] VPE0.EPC : 8010c9b4 mips_mt_regdump+0x3a4/0x3d4 > [ 0.010000] VPE0.Cause : 50804000 > [ 0.010000] VPE0.Config7 : 00010000 > [ 0.010000] VPE 1 > [ 0.010000] VPEControl : 00030000 > [ 0.010000] VPEConf0 : 800f0000 > [ 0.010000] VPE1.Status : 00407904 > [ 0.010000] VPE1.EPC : fffdffff 0xfffdffff > [ 0.010000] VPE1.Cause : 4000027c > [ 0.010000] VPE1.Config7 : 00010000 > [ 0.010000] -- per-TC State -- > [ 0.010000] TC 0 (current TC with VPE EPC above) > [ 0.010000] TCStatus : 18004000 > [ 0.010000] TCBind : 00000000 > [ 0.010000] TCRestart : 803fc408 printk+0x10/0x30 > [ 0.010000] TCHalt : 00000000 > [ 0.010000] TCContext : 00000000 > [ 0.010000] TC 1 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00200001 > [ 0.010000] TCRestart : 3ffffffe 0x3ffffffe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : efffffff > [ 0.010000] TC 2 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00400001 > [ 0.010000] TCRestart : ffffffee 0xffffffee > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : efffffbf > [ 0.010000] TC 3 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00600001 > [ 0.010000] TCRestart : ffe00200 0xffe00200 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 7fffb77f > [ 0.010000] TC 4 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00800001 > [ 0.010000] TCRestart : ffe00200 0xffe00200 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : 7ffdf736 > [ 0.010000] TC 5 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00a00001 > [ 0.010000] TCRestart : ffe00200 0xffe00200 > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : ee5ffff7 > [ 0.010000] TC 6 > [ 0.010000] TCStatus : 00000000 > [ 0.010000] TCBind : 00c00001 > [ 0.010000] TCRestart : f7ff7ffe 0xf7ff7ffe > [ 0.010000] TCHalt : 00000001 > [ 0.010000] TCContext : e6fffffb > [ 0.010000] Counter Interrupts taken per CPU (TC) > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] Self-IPI invocations: > [ 0.010000] 0: 0 > [ 0.010000] 1: 0 > [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > [ 0.010000] 0 Recoveries of "stolen" FPU > [ 0.010000] =========================== > > > From anoop.pa@gmail.com Wed Dec 22 12:43:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 12:43:30 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:41938 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490989Ab0LVLn1 (ORCPT ); Wed, 22 Dec 2010 12:43:27 +0100 Received: by gyg4 with SMTP id 4so2333494gyg.36 for ; Wed, 22 Dec 2010 03:43:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=dG03KCQQCR7bf/e3kvyJK4z1YmhbMqQ/fr7xZQu3VmY=; b=adgAASDY9jFO+hQcN55rj14x7OH8WUUZ1NftCTnEMdH/Dt+aSYj1HSV6XvnUHM3vA4 2qEzDKzlZ46BJV9GUmQ+T5ZuSzfJuyb07brC6K4IqTTtEuU99rkNlU7w0rwduuWgDcsV 9O4ULR7EzgWrnc8zOMsDqDmxGFmL4nWuusQQs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=sM8xJZ/2qk1P8wkfFeVCI5ho6eQlCMXSTBk5DNHQMJr7OzmL6wMPMloKYkj8efcbLV 9D9DNg0them+QHxWIY1W6IseqoW8v0aOPKbgk9V5vFfd+dMKcwuZOZ1UVyvi1Vnjtpiv Ps1YvmRTOI5F8PHUEKLUodgFbW2MICRxpOyKA= Received: by 10.151.41.9 with SMTP id t9mr10112972ybj.255.1293018199850; Wed, 22 Dec 2010 03:43:19 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id u10sm8877219yba.1.2010.12.22.03.43.15 (version=SSLv3 cipher=RC4-MD5); Wed, 22 Dec 2010 03:43:18 -0800 (PST) Subject: Re: SMTC support status in latest git head. From: Anoop P A To: "Kevin D. Kissell" Cc: "Anoop P.A." , STUART VENTERS , linux-mips@linux-mips.org In-Reply-To: <4D11E2E2.80809@paralogos.com> References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> <4D0BD7A0.1030504@paralogos.com> <4D10F7A9.1020306@paralogos.com> <4D11D28D.80501@paralogos.com> <1293017702.27661.36.camel@paanoop1-desktop> <4D11E2E2.80809@paralogos.com> Content-Type: text/plain; charset="UTF-8" Date: Wed, 22 Dec 2010 17:21:15 +0530 Message-ID: <1293018675.27661.40.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28676 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 8569 Lines: 208 On Wed, 2010-12-22 at 03:37 -0800, Kevin D. Kissell wrote: > Thanks. This is indeed strange. The VPE0 Status and TC0 TCStatus/Cause > all indicate that interrupts are enabled and not inhibited at the per-TC > level, and the presumed timer interrupt, in the 0x4000 bit, is present > and not masked-off. Logically, the system must be entering (and > exiting) the interrupt handler, yet the timer calibration isn't > completing. That leaves more complex possible explanations for failure, > most of which would fall into two categories: > > 1) The platform interrupt handler is failing to decode the event > properly as a timer event. > 2) Despite there being only one TC active, the calibration code is > waiting for some handshake from another "CPU" > > To test the first, you might consider adding a kprintf() to the case of > a "spurious" timer-like interrupt being detected and ignored... I have tried it . only one interrupt is coming and platform handler detect it as timer interrupt and acknowledges properly . you can see a time stamp change in the logs. > > Regards, > > Kevin K. > > On 12/22/10 3:35 AM, Anoop P A wrote: > > On Wed, 2010-12-22 at 02:27 -0800, Kevin D. Kissell wrote: > >>> Sorry I misunderstood file. git blame shows that "andi" is around for > >> quite > >> > some time. > >> > >> I've never used git blame, so I don't know how far it can be trusted, > >> but if that change was made in 2006, that would predate the major > >> breakage by several > >> years. So my suggestion from yesterday is a reasonable one: > > That change is present in booting 2.6.32 kernel.Corresponding patch can > > be found in gitweb . > > http://git.linux-mips.org/?p=linux.git;a=commitdiff;h=41c594ab65fc89573af296d192aa5235d09717ab#patch39 > > > >> > I think that if you were to tweak mips-mt.c at line 103 to change > >> > the > >> > > >> > tcstatval = flags; /* And pre-dump TCStatus is flags */ > >> > > >> > to something more like > >> > > >> > /* Pre-dump TCStatus Interrupt Inhibit bit is in flags variable */ > >> > tcstatval = (read_c0_tcstatus()& ~0x400) | flags; > >> > > >> > should fix the dump. > >> > >> With that patch, if you re-run the experiment of hang-breakout-dump, we > >> might be able to deduce something. > > Here is the dump with the patch. > > > > [ 0.000000] Calibrating delay loop... === MIPS MT State Dump === > > [ 0.000000] -- Global State -- > > [ 0.000000] MVPControl Passed: 00000000 > > [ 0.000000] MVPControl Read: 00000000 > > [ 0.000000] MVPConf0 : a8008406 > > [ 0.000000] -- per-VPE State -- > > [ 0.000000] VPE 0 > > [ 0.000000] VPEControl : 00000000 > > [ 0.000000] VPEConf0 : 800f0003 > > [ 0.000000] VPE0.Status : 11004001 > > [ 0.000000] VPE0.EPC : 80100000 _stext+0x0/0x10 > > [ 0.000000] VPE0.Cause : e080407c > > [ 0.000000] VPE0.Config7 : 00010000 > > [ 0.000000] VPE 1 > > [ 0.000000] VPEControl : 00030000 > > [ 0.000000] VPEConf0 : 800f0000 > > [ 0.000000] VPE1.Status : 00407904 > > [ 0.000000] VPE1.EPC : fffdffff 0xfffdffff > > [ 0.000000] VPE1.Cause : 4000027c > > [ 0.000000] VPE1.Config7 : 00010000 > > [ 0.000000] -- per-TC State -- > > [ 0.000000] TC 0 (current TC with VPE EPC above) > > [ 0.000000] TCStatus : 11004001 > > [ 0.000000] TCBind : 00000000 > > [ 0.000000] TCRestart : 803fc408 printk+0x10/0x30 > > [ 0.000000] TCHalt : 00000000 > > [ 0.000000] TCContext : 00000000 > > [ 0.000000] TC 1 > > [ 0.000000] TCStatus : 00000000 > > [ 0.000000] TCBind : 00200001 > > [ 0.000000] TCRestart : 3ffffffe 0x3ffffffe > > [ 0.000000] TCHalt : 00000001 > > [ 0.000000] TCContext : efffffff > > [ 0.000000] TC 2 > > [ 0.000000] TCStatus : 00000000 > > [ 0.000000] TCBind : 00400001 > > [ 0.000000] TCRestart : ffffffee 0xffffffee > > [ 0.000000] TCHalt : 00000001 > > [ 0.000000] TCContext : efffffbf > > [ 0.000000] TC 3 > > [ 0.000000] TCStatus : 00000000 > > [ 0.000000] TCBind : 00600001 > > [ 0.000000] TCRestart : ffe00200 0xffe00200 > > [ 0.000000] TCHalt : 00000001 > > [ 0.000000] TCContext : 7fffb77f > > [ 0.000000] TC 4 > > [ 0.000000] TCStatus : 00000000 > > [ 0.000000] TCBind : 00800001 > > [ 0.000000] TCRestart : ffe00200 0xffe00200 > > [ 0.000000] TCHalt : 00000001 > > [ 0.000000] TCContext : 7ffdf736 > > [ 0.000000] TC 5 > > [ 0.000000] TCStatus : 00000000 > > [ 0.000000] TCBind : 00a00001 > > [ 0.000000] TCRestart : ffe00200 0xffe00200 > > [ 0.000000] TCHalt : 00000001 > > [ 0.000000] TCContext : ee5ffff7 > > [ 0.000000] TC 6 > > [ 0.000000] TCStatus : 00000000 > > [ 0.000000] TCBind : 00c00001 > > [ 0.000000] TCRestart : f7ff7ffe 0xf7ff7ffe > > [ 0.000000] TCHalt : 00000001 > > [ 0.000000] TCContext : e6fffffb > > [ 0.000000] Counter Interrupts taken per CPU (TC) > > [ 0.000000] 0: 0 > > [ 0.000000] 1: 0 > > [ 0.000000] Self-IPI invocations: > > [ 0.000000] 0: 0 > > [ 0.000000] 1: 0 > > [ 0.000000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > > [ 0.000000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > > [ 0.000000] 0 Recoveries of "stolen" FPU > > [ 0.000000] =========================== > > [ 0.010000] === MIPS MT State Dump === > > [ 0.010000] -- Global State -- > > [ 0.010000] MVPControl Passed: 00000000 > > [ 0.010000] MVPControl Read: 00000000 > > [ 0.010000] MVPConf0 : a8008406 > > [ 0.010000] -- per-VPE State -- > > [ 0.010000] VPE 0 > > [ 0.010000] VPEControl : 00000000 > > [ 0.010000] VPEConf0 : 800f0003 > > [ 0.010000] VPE0.Status : 18004000 > > [ 0.010000] VPE0.EPC : 8010c9b4 mips_mt_regdump+0x3a4/0x3d4 > > [ 0.010000] VPE0.Cause : 50804000 > > [ 0.010000] VPE0.Config7 : 00010000 > > [ 0.010000] VPE 1 > > [ 0.010000] VPEControl : 00030000 > > [ 0.010000] VPEConf0 : 800f0000 > > [ 0.010000] VPE1.Status : 00407904 > > [ 0.010000] VPE1.EPC : fffdffff 0xfffdffff > > [ 0.010000] VPE1.Cause : 4000027c > > [ 0.010000] VPE1.Config7 : 00010000 > > [ 0.010000] -- per-TC State -- > > [ 0.010000] TC 0 (current TC with VPE EPC above) > > [ 0.010000] TCStatus : 18004000 > > [ 0.010000] TCBind : 00000000 > > [ 0.010000] TCRestart : 803fc408 printk+0x10/0x30 > > [ 0.010000] TCHalt : 00000000 > > [ 0.010000] TCContext : 00000000 > > [ 0.010000] TC 1 > > [ 0.010000] TCStatus : 00000000 > > [ 0.010000] TCBind : 00200001 > > [ 0.010000] TCRestart : 3ffffffe 0x3ffffffe > > [ 0.010000] TCHalt : 00000001 > > [ 0.010000] TCContext : efffffff > > [ 0.010000] TC 2 > > [ 0.010000] TCStatus : 00000000 > > [ 0.010000] TCBind : 00400001 > > [ 0.010000] TCRestart : ffffffee 0xffffffee > > [ 0.010000] TCHalt : 00000001 > > [ 0.010000] TCContext : efffffbf > > [ 0.010000] TC 3 > > [ 0.010000] TCStatus : 00000000 > > [ 0.010000] TCBind : 00600001 > > [ 0.010000] TCRestart : ffe00200 0xffe00200 > > [ 0.010000] TCHalt : 00000001 > > [ 0.010000] TCContext : 7fffb77f > > [ 0.010000] TC 4 > > [ 0.010000] TCStatus : 00000000 > > [ 0.010000] TCBind : 00800001 > > [ 0.010000] TCRestart : ffe00200 0xffe00200 > > [ 0.010000] TCHalt : 00000001 > > [ 0.010000] TCContext : 7ffdf736 > > [ 0.010000] TC 5 > > [ 0.010000] TCStatus : 00000000 > > [ 0.010000] TCBind : 00a00001 > > [ 0.010000] TCRestart : ffe00200 0xffe00200 > > [ 0.010000] TCHalt : 00000001 > > [ 0.010000] TCContext : ee5ffff7 > > [ 0.010000] TC 6 > > [ 0.010000] TCStatus : 00000000 > > [ 0.010000] TCBind : 00c00001 > > [ 0.010000] TCRestart : f7ff7ffe 0xf7ff7ffe > > [ 0.010000] TCHalt : 00000001 > > [ 0.010000] TCContext : e6fffffb > > [ 0.010000] Counter Interrupts taken per CPU (TC) > > [ 0.010000] 0: 0 > > [ 0.010000] 1: 0 > > [ 0.010000] Self-IPI invocations: > > [ 0.010000] 0: 0 > > [ 0.010000] 1: 0 > > [ 0.010000] IPIQ[0]: head = 0x0, tail = 0x0, depth = 0 > > [ 0.010000] IPIQ[1]: head = 0x0, tail = 0x0, depth = 0 > > [ 0.010000] 0 Recoveries of "stolen" FPU > > [ 0.010000] =========================== > > > > > > > From kevink@paralogos.com Wed Dec 22 14:03:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 14:03:16 +0100 (CET) Received: from gateway11.websitewelcome.com ([69.41.245.3]:41025 "HELO gateway11.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491018Ab0LVNDN (ORCPT ); Wed, 22 Dec 2010 14:03:13 +0100 Received: (qmail 21349 invoked from network); 22 Dec 2010 13:11:52 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway11.websitewelcome.com with SMTP; 22 Dec 2010 13:11:52 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=JSGqu+v3HoFFzOnFa3Xs3F6Wv/9BVyVmBjAZ86ChBGSFtOru84MBWj4oV/vSwlKRhQONYtknFAtzCX5uJcs8HAv6yN0Z651yLUCL6qnBKKmMCymYkB8iOkoNkjjpSICT; Received: from [88.123.214.42] (port=49250 helo=kkissell-macbookpro.local) by gator750.hostgator.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1PVOLQ-0008Av-EY; Wed, 22 Dec 2010 07:03:06 -0600 Message-ID: <4D11F707.8040205@paralogos.com> Date: Wed, 22 Dec 2010 05:03:03 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Anoop P A CC: "Anoop P.A." , STUART VENTERS , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB880@EXV1.corp.adtran.com> <4D0A677C.6040104@paralogos.com> <4D0A6F63.8080206@paralogos.com> <4D0BD7A0.1030504@paralogos.com> <4D10F7A9.1020306@paralogos.com> <4D11D28D.80501@paralogos.com> <1293017702.27661.36.camel@paanoop1-desktop> <4D11E2E2.80809@paralogos.com> <1293018675.27661.40.camel@paanoop1-desktop> In-Reply-To: <1293018675.27661.40.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28677 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 2677 Lines: 51 On 12/22/10 3:51 AM, Anoop P A wrote: > On Wed, 2010-12-22 at 03:37 -0800, Kevin D. Kissell wrote: >> Thanks. This is indeed strange. The VPE0 Status and TC0 TCStatus/Cause >> all indicate that interrupts are enabled and not inhibited at the per-TC >> level, and the presumed timer interrupt, in the 0x4000 bit, is present >> and not masked-off. Logically, the system must be entering (and >> exiting) the interrupt handler, yet the timer calibration isn't >> completing. That leaves more complex possible explanations for failure, >> most of which would fall into two categories: >> >> 1) The platform interrupt handler is failing to decode the event >> properly as a timer event. >> 2) Despite there being only one TC active, the calibration code is >> waiting for some handshake from another "CPU" >> >> To test the first, you might consider adding a kprintf() to the case of >> a "spurious" timer-like interrupt being detected and ignored... > I have tried it . only one interrupt is coming and platform handler > detect it as timer interrupt and acknowledges properly . you can see a > time stamp change in the logs. That's really strange. And your timer interrupt is definitely on the interrupt that corresponds to the 0x4000 mask? I may have written the MT spec and the original SMTC code, but I don't have a copy of the spec, and it's been a few years, and I can't interpret the MVP and VPE control/config values. But I just don't see how the processor could not be taking more interrupts. Stuart did decode the global/VPE state enough to observe that global multithreaded execution wasn't enabled, which is indeed strange - it shouldn't matter for single-TC execution, but I don't recall there being any special-case in the SMTC initialization that bypassed that enable. That makes me suspect that maybe someone changed the initialization sequence in a way that bypasses one of the canonical initialization steps in a way that would break SMTC, but I don't know why that would result in the interrupt behavior you observe. It might be yet another blind alley, but could you add/arm diagnostic output for each of the initialization functions in smtc.c? Ah, yes, and one other thing. You should add a dump of ErrorEPC to the MT register dump. I did it for myself once upon a time when I was confronted with a similar mystery, but never filed a patch. If you're breaking in with NMI, that could help identify more precisely where it's locking up. You really ought to try to borrow an EJTAG probe. It would save us both a lot of time. And my time to trouble-shoot this with you is limited. Regards, Kevin K. From anoop.pa@gmail.com Wed Dec 22 15:26:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 15:26:38 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:65138 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491022Ab0LVO0f (ORCPT ); Wed, 22 Dec 2010 15:26:35 +0100 Received: by vws5 with SMTP id 5so1965316vws.36 for ; Wed, 22 Dec 2010 06:26:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=3qQ2BY/EB6dHKwekKjyPhCmb+j36oO3wfvRAKy/P4Cc=; b=pqmf6lNg6vqCCzoY7X8/Q1JZnsZYqLlxpOLmwPYyTEzuvsILXQu7C9HUPEk54kWWHU Gg8pDeZoKjY9wFeset82krSG5sUJah2z39XHjdjz0i1shZSrxQ2rCjwPTPJ/ZHih2/YZ URwi49ndl4zoYk/8V19P9oQ/f8ANRA8bHBkgI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=JSF1oj52VTHVk+IIA7XzkaN1uA9c2OmCpy0Gd5klHTW60FAvGo91B6sG8UW7ZvtcQT d4n2w9dj8wNOO92Cdju8nnOVJEcbNDKBjqPp+c275JSR6nNj4M6jbJoBnY++wjbv4y8Q vkR2N45esd1mC6KWl+/8yYSC9hQQ369zy9hAs= Received: by 10.220.186.205 with SMTP id ct13mr1763769vcb.232.1293027988625; Wed, 22 Dec 2010 06:26:28 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id k39sm1330538vcr.2.2010.12.22.06.26.21 (version=SSLv3 cipher=RC4-MD5); Wed, 22 Dec 2010 06:26:27 -0800 (PST) From: "Anoop P.A" To: Ralf Baechle , Greg Kroah-Hartman , Anatolij Gustschin , Anand Gadiyar , Alan Stern , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Sarah Sharp , Oliver Neukum , Hans de Goede , Paul Mortier , Andiry Xu Cc: Anoop P A Subject: [PATCH V2 0/2] EHCI support for on-chip PMC MSP USB controller Date: Wed, 22 Dec 2010 20:04:07 +0530 Message-Id: <1293028447-21703-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> References: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28678 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1216 Lines: 26 From: Anoop P A Changes Since V1: 1.Updated driver code with changes from ehci-pci.c 2.Moved over current fixup to different patch. 3.Removed #ifdef and added quirk list entry for overcurrent fixup. Anoop P A (2): EHCI support for on-chip PMC MSP USB controller. MSP onchip root hub over current quirk. .../mips/include/asm/pmc-sierra/msp71xx/msp_regs.h | 17 +- arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h | 144 +++++ arch/mips/pmc-sierra/Kconfig | 8 + arch/mips/pmc-sierra/msp71xx/Makefile | 2 +- arch/mips/pmc-sierra/msp71xx/msp_usb.c | 239 +++++++--- drivers/usb/core/hub.c | 45 ++- drivers/usb/core/quirks.c | 3 + drivers/usb/host/Kconfig | 15 +- drivers/usb/host/ehci-hcd.c | 12 + drivers/usb/host/ehci-pmcmsp.c | 551 ++++++++++++++++++++ include/linux/usb/quirks.h | 3 + 11 files changed, 959 insertions(+), 80 deletions(-) create mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h create mode 100644 drivers/usb/host/ehci-pmcmsp.c From anoop.pa@gmail.com Wed Dec 22 15:28:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 15:28:25 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:35456 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491022Ab0LVO2U (ORCPT ); Wed, 22 Dec 2010 15:28:20 +0100 Received: by vws5 with SMTP id 5so1966015vws.36 for ; Wed, 22 Dec 2010 06:28:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=PkpR+9efewW7XatrUZVv1fljpSrvxCAuG9a5d4ytogg=; b=v2IOpd5gX+4GyN2u5EhQ38gP4KOxePUBOzrK7TDZ2yjd33QyBJjYi+JDDP1FQVQhlc DwEdtgy80T1aJMy1ERIHARiFAws4F7GN+7G06Ht4HolCx0xY4EmCGP8La6Jo8vSCpyx9 x9IwGDCEm298shR5CJcpAjJFN55X8TwgMSI7U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=haGDwgCa5rVXNVWrwR8gYfKHCV+53G8NSYtHFImCVcM8AVwRet8E3E5cGq+WJ2jq30 4NfiYG95w/fAiMSkV2zjxw32TleORmi7pY932kwfB/CbY6qUGE33HauKI1euYqNn4l1O /b5Pjxr7hE5Z342LDk7LGIvIhQFmOqXtiapkw= Received: by 10.220.94.83 with SMTP id y19mr1767963vcm.263.1293028092929; Wed, 22 Dec 2010 06:28:12 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id r7sm2370586vbx.19.2010.12.22.06.28.06 (version=SSLv3 cipher=RC4-MD5); Wed, 22 Dec 2010 06:28:11 -0800 (PST) From: "Anoop P.A" To: Ralf Baechle , Greg Kroah-Hartman , Anatolij Gustschin , Anand Gadiyar , Alan Stern , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Cc: Anoop P A Subject: [PATCH V2 1/2] EHCI support for on-chip PMC MSP USB controller. Date: Wed, 22 Dec 2010 20:06:01 +0530 Message-Id: <1293028561-22125-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> References: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28679 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 36015 Lines: 1187 From: Anoop P A This patch includes. 1. USB host driver for MSP71xx family SoC on-chip USB controller. 2. Platform support for USB controller. Signed-off-by: Anoop P A --- .../mips/include/asm/pmc-sierra/msp71xx/msp_regs.h | 17 +- arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h | 144 +++++ arch/mips/pmc-sierra/Kconfig | 8 + arch/mips/pmc-sierra/msp71xx/Makefile | 2 +- arch/mips/pmc-sierra/msp71xx/msp_usb.c | 239 +++++++--- drivers/usb/host/Kconfig | 15 +- drivers/usb/host/ehci-hcd.c | 12 + drivers/usb/host/ehci-pmcmsp.c | 551 ++++++++++++++++++++ 8 files changed, 914 insertions(+), 74 deletions(-) create mode 100644 arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h create mode 100644 drivers/usb/host/ehci-pmcmsp.c diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h index 603eb73..692c1b6 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h @@ -91,12 +91,10 @@ /* MAC C device registers */ #define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) /* ADSL2 device registers */ -#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) - /* USB device registers */ -#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) - /* USB device registers */ -#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF) - /* USB device registers */ +#define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000) + /* USB0 device registers */ +#define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000) + /* USB1 device registers */ #define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) /* CPU interface registers */ @@ -319,8 +317,11 @@ #define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) /* CPU/SLP Error status 1 */ -#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) - /* Extended GPIO register */ +/* Extended GPIO registers */ +#define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188) +#define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c) +#define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG + /* Backward-compatibility */ /* System Error registers */ #define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h new file mode 100644 index 0000000..4c9348d --- /dev/null +++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h @@ -0,0 +1,144 @@ +/****************************************************************** + * Copyright (c) 2000-2007 PMC-Sierra INC. + * + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + * + * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS + * SOFTWARE. + */ +#ifndef MSP_USB_H_ +#define MSP_USB_H_ + +#ifdef CONFIG_MSP_HAS_DUAL_USB +#define NUM_USB_DEVS 2 +#else +#define NUM_USB_DEVS 1 +#endif + +/* Register spaces for USB host 0 */ +#define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0) +#define MSP_USB0_MAB_END (MSP_USB0_BASE + 0x17) +#define MSP_USB0_ID_START (MSP_USB0_BASE + 0x40000) +#define MSP_USB0_ID_END (MSP_USB0_BASE + 0x4008f) +#define MSP_USB0_HS_START (MSP_USB0_BASE + 0x40100) +#define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF) + +/* Register spaces for USB host 1 */ +#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0) +#define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17) +#define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000) +#define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f) +#define MSP_USB1_HS_START (MSP_USB1_BASE + 0x40100) +#define MSP_USB1_HS_END (MSP_USB1_BASE + 0x401ff) + +/* USB Identification registers */ +struct msp_usbid_regs { + u32 id; /* 0x0: Identification register */ + u32 hwgen; /* 0x4: General HW params */ + u32 hwhost; /* 0x8: Host HW params */ + u32 hwdev; /* 0xc: Device HW params */ + u32 hwtxbuf; /* 0x10: Tx buffer HW params */ + u32 hwrxbuf; /* 0x14: Rx buffer HW params */ + u32 reserved[26]; + u32 timer0_load; /* 0x80: General-purpose timer 0 load*/ + u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */ + u32 timer1_load; /* 0x88: General-purpose timer 1 load*/ + u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */ +}; + +/* MSBus to AMBA registers */ +struct msp_mab_regs { + u32 isr; /* 0x0: Interrupt status */ + u32 imr; /* 0x4: Interrupt mask */ + u32 thcr0; /* 0x8: Transaction header capture 0 */ + u32 thcr1; /* 0xc: Transaction header capture 1 */ + u32 int_stat; /* 0x10: Interrupt status summary */ + u32 phy_cfg; /* 0x14: USB phy config */ +}; + +/* EHCI registers */ +struct msp_usbhs_regs { + u32 hciver; /* 0x0: Version and offset to operational regs */ + u32 hcsparams; /* 0x4: Host control structural parameters */ + u32 hccparams; /* 0x8: Host control capability parameters */ + u32 reserved0[5]; + u32 dciver; /* 0x20: Device interface version */ + u32 dccparams; /* 0x24: Device control capability parameters */ + u32 reserved1[6]; + u32 cmd; /* 0x40: USB command */ + u32 sts; /* 0x44: USB status */ + u32 int_ena; /* 0x48: USB interrupt enable */ + u32 frindex; /* 0x4c: Frame index */ + u32 reserved3; + union { + struct { + u32 flb_addr; /* 0x54: Frame list base address */ + u32 next_async_addr; /* 0x58: next asynchronous addr */ + u32 ttctrl; /* 0x5c: embedded transaction translator + async buffer status */ + u32 burst_size; /* 0x60: Controller burst size */ + u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */ + u32 reserved0[4]; + u32 endpt_nak; /* 0x78: Endpoint NAK */ + u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */ + u32 cfg_flag; /* 0x80: Config flag */ + u32 port_sc1; /* 0x84: Port status & control 1 */ + u32 reserved1[7]; + u32 otgsc; /* 0xa4: OTG status & control */ + u32 mode; /* 0xa8: USB controller mode */ + } host; + + struct { + u32 dev_addr; /* 0x54: Device address */ + u32 endpt_list_addr; /* 0x58: Endpoint list address */ + u32 reserved0[7]; + u32 endpt_nak; /* 0x74 */ + u32 endpt_nak_ctrl; /* 0x78 */ + u32 cfg_flag; /* 0x80 */ + u32 port_sc1; /* 0x84: Port status & control 1 */ + u32 reserved[7]; + u32 otgsc; /* 0xa4: OTG status & control */ + u32 mode; /* 0xa8: USB controller mode */ + u32 endpt_setup_stat; /* 0xac */ + u32 endpt_prime; /* 0xb0 */ + u32 endpt_flush; /* 0xb4 */ + u32 endpt_stat; /* 0xb8 */ + u32 endpt_complete; /* 0xbc */ + u32 endpt_ctrl0; /* 0xc0 */ + u32 endpt_ctrl1; /* 0xc4 */ + u32 endpt_ctrl2; /* 0xc8 */ + u32 endpt_ctrl3; /* 0xcc */ + } device; + } u; +}; +/* + * Container for the more-generic platform_device. + * This exists mainly as a way to map the non-standard register + * spaces and make them accessible to the USB ISR. + */ +struct mspusb_device { + struct msp_mab_regs __iomem *mab_regs; + struct msp_usbid_regs __iomem *usbid_regs; + struct msp_usbhs_regs __iomem *usbhs_regs; + struct platform_device dev; +}; + +#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev) +#define TO_HOST_ID(x) ((x) & 0x3) +#endif /*MSP_USB_H_*/ diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig index 8d79849..a80ad25 100644 --- a/arch/mips/pmc-sierra/Kconfig +++ b/arch/mips/pmc-sierra/Kconfig @@ -23,6 +23,7 @@ config PMC_MSP7120_GW select SYS_SUPPORTS_MULTITHREADING select IRQ_MSP_CIC select HW_HAS_PCI + select MSP_HAS_USB config PMC_MSP7120_FPGA bool "PMC-Sierra MSP7120 FPGA" @@ -35,3 +36,10 @@ endchoice config HYPERTRANSPORT bool "Hypertransport Support for PMC-Sierra Yosemite" depends on PMC_YOSEMITE + + +config MSP_HAS_USB + boolean + depends on PMC_MSP + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_HCD diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile index 09627ae..380d39d 100644 --- a/arch/mips/pmc-sierra/msp71xx/Makefile +++ b/arch/mips/pmc-sierra/msp71xx/Makefile @@ -9,5 +9,5 @@ obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o obj-$(CONFIG_PCI) += msp_pci.o obj-$(CONFIG_MSPETH) += msp_eth.o -obj-$(CONFIG_USB_MSP71XX) += msp_usb.o +obj-$(CONFIG_MSP_HAS_USB) += msp_usb.o obj-$(CONFIG_MIPS_MT_SMP) += msp_smp.o diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c index 0ee01e3..9a1aef8 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c @@ -1,7 +1,7 @@ /* * The setup file for USB related hardware on PMC-Sierra MSP processors. * - * Copyright 2006-2007 PMC-Sierra, Inc. + * Copyright 2006 PMC-Sierra, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -23,8 +23,8 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) -#include #include #include #include @@ -34,40 +34,56 @@ #include #include #include +#include + #if defined(CONFIG_USB_EHCI_HCD) -static struct resource msp_usbhost_resources [] = { - [0] = { - .start = MSP_USB_BASE_START, - .end = MSP_USB_BASE_END, - .flags = IORESOURCE_MEM, +static struct resource msp_usbhost0_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB0_HS_START, + .end = MSP_USB0_HS_END, + .flags = IORESOURCE_MEM, }, [1] = { - .start = MSP_INT_USB, - .end = MSP_INT_USB, - .flags = IORESOURCE_IRQ, + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB0_MAB_START, + .end = MSP_USB0_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB0_ID_START, + .end = MSP_USB0_ID_END, + .flags = IORESOURCE_MEM, }, }; -static u64 msp_usbhost_dma_mask = DMA_BIT_MASK(32); +static u64 msp_usbhost0_dma_mask = 0xffffffffUL; -static struct platform_device msp_usbhost_device = { - .name = "pmcmsp-ehci", - .id = 0, +static struct mspusb_device msp_usbhost0_device = { .dev = { - .dma_mask = &msp_usbhost_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), + .name = "pmcmsp-ehci", + .id = 0, + .dev = { + .dma_mask = &msp_usbhost0_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbhost0_resources), + .resource = msp_usbhost0_resources, }, - .num_resources = ARRAY_SIZE(msp_usbhost_resources), - .resource = msp_usbhost_resources, }; -#endif /* CONFIG_USB_EHCI_HCD */ -#if defined(CONFIG_USB_GADGET) -static struct resource msp_usbdev_resources [] = { - [0] = { - .start = MSP_USB_BASE, - .end = MSP_USB_BASE_END, +/* MSP7140/MSP82XX has two USB2 hosts. */ +#ifdef CONFIG_MSP_HAS_DUAL_USB +static u64 msp_usbhost1_dma_mask = 0xffffffffUL; + +static struct resource msp_usbhost1_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB1_HS_START, + .end = MSP_USB1_HS_END, .flags = IORESOURCE_MEM, }, [1] = { @@ -75,76 +91,173 @@ static struct resource msp_usbdev_resources [] = { .end = MSP_INT_USB, .flags = IORESOURCE_IRQ, }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB1_MAB_START, + .end = MSP_USB1_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB1_ID_START, + .end = MSP_USB1_ID_END, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mspusb_device msp_usbhost1_device = { + .dev = { + .name = "pmcmsp-ehci", + .id = 1, + .dev = { + .dma_mask = &msp_usbhost1_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbhost1_resources), + .resource = msp_usbhost1_resources, + }, }; +#endif /* CONFIG_MSP_HAS_DUAL_USB */ +#endif /* CONFIG_USB_EHCI_HCD */ -static u64 msp_usbdev_dma_mask = DMA_BIT_MASK(32); +#if defined(CONFIG_USB_GADGET) +static struct resource msp_usbdev0_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB0_HS_START, + .end = MSP_USB0_HS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB0_MAB_START, + .end = MSP_USB0_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB0_ID_START, + .end = MSP_USB0_ID_END, + .flags = IORESOURCE_MEM, + }, +}; -static struct platform_device msp_usbdev_device = { - .name = "msp71xx_udc", - .id = 0, +static u64 msp_usbdev_dma_mask = 0xffffffffUL; + +/* This may need to be converted to a mspusb_device, too. */ +static struct mspusb_device msp_usbdev0_device = { .dev = { - .dma_mask = &msp_usbdev_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), + .name = "msp71xx_udc", + .id = 0, + .dev = { + .dma_mask = &msp_usbdev_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbdev0_resources), + .resource = msp_usbdev0_resources, }, - .num_resources = ARRAY_SIZE(msp_usbdev_resources), - .resource = msp_usbdev_resources, }; -#endif /* CONFIG_USB_GADGET */ -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) -static struct platform_device *msp_devs[1]; -#endif +#ifdef CONFIG_MSP_HAS_DUAL_USB +static struct resource msp_usbdev1_resources[] = { + [0] = { /* EHCI-HS operational and capabilities registers */ + .start = MSP_USB1_HS_START, + .end = MSP_USB1_HS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_USB, + .end = MSP_INT_USB, + .flags = IORESOURCE_IRQ, + }, + [2] = { /* MSBus-to-AMBA bridge register space */ + .start = MSP_USB1_MAB_START, + .end = MSP_USB1_MAB_END, + .flags = IORESOURCE_MEM, + }, + [3] = { /* Identification and general hardware parameters */ + .start = MSP_USB1_ID_START, + .end = MSP_USB1_ID_END, + .flags = IORESOURCE_MEM, + }, +}; +/* This may need to be converted to a mspusb_device, too. */ +static struct mspusb_device msp_usbdev1_device = { + .dev = { + .name = "msp71xx_udc", + .id = 0, + .dev = { + .dma_mask = &msp_usbdev_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE(msp_usbdev1_resources), + .resource = msp_usbdev1_resources, + }, +}; + +#endif /* CONFIG_MSP_HAS_DUAL_USB */ +#endif /* CONFIG_USB_GADGET */ static int __init msp_usb_setup(void) { -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) - char *strp; - char envstr[32]; - unsigned int val = 0; - int result = 0; + char *strp; + char envstr[32]; + struct platform_device *msp_devs[NUM_USB_DEVS]; + unsigned int val; + /* construct environment name usbmode */ + /* set usbmode as pmon environment var */ /* - * construct environment name usbmode - * set usbmode as pmon environment var + * Could this perhaps be integrated into the "features" env var? + * Use the features key "U", and follow with "H" for host-mode, + * "D" for device-mode. If it works for Ethernet, why not USB... + * -- hammtrev, 2007/03/22 */ snprintf((char *)&envstr[0], sizeof(envstr), "usbmode"); -#if defined(CONFIG_USB_EHCI_HCD) - /* default to host mode */ + /* set default host mode */ val = 1; -#endif /* get environment string */ strp = prom_getenv((char *)&envstr[0]); if (strp) { + /* compare string */ if (!strcmp(strp, "device")) val = 0; } if (val) { #if defined(CONFIG_USB_EHCI_HCD) - /* get host mode device */ - msp_devs[0] = &msp_usbhost_device; - ppfinit("platform add USB HOST done %s.\n", - msp_devs[0]->name); - - result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); -#endif /* CONFIG_USB_EHCI_HCD */ - } + msp_devs[0] = &msp_usbhost0_device.dev; + ppfinit("platform add USB HOST done %s.\n", msp_devs[0]->name); +#ifdef CONFIG_MSP_HAS_DUAL_USB + msp_devs[1] = &msp_usbhost1_device.dev; + ppfinit("platform add USB HOST done %s.\n", msp_devs[1]->name); +#endif +#else + ppfinit("%s: echi_hcd not supported\n", __FILE__); +#endif /* CONFIG_USB_EHCI_HCD */ + } else { #if defined(CONFIG_USB_GADGET) - else { /* get device mode structure */ - msp_devs[0] = &msp_usbdev_device; - ppfinit("platform add USB DEVICE done %s.\n", - msp_devs[0]->name); - - result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); + msp_devs[0] = &msp_usbdev0_device.dev; + ppfinit("platform add USB DEVICE done %s.\n" + , msp_devs[0]->name); +#ifdef CONFIG_MSP_HAS_DUAL_USB + msp_devs[1] = &msp_usbdev1_device.dev; + ppfinit("platform add USB DEVICE done %s.\n" + , msp_devs[1]->name); +#endif +#else + ppfinit("%s: usb_gadget not supported\n", __FILE__); +#endif /* CONFIG_USB_GADGET */ } -#endif /* CONFIG_USB_GADGET */ -#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ + /* add device */ + platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); - return result; + return 0; } subsys_initcall(msp_usb_setup); +#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 2391c39..bc955d0 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -91,17 +91,28 @@ config USB_EHCI_TT_NEWSCHED If unsure, say Y. +config USB_EHCI_HCD_PMC_MSP + tristate "EHCI support for on-chip PMC MSP USB controller" + depends on USB_EHCI_HCD && MSP_HAS_USB + default y + select USB_EHCI_BIG_ENDIAN_DESC + select USB_EHCI_BIG_ENDIAN_MMIO + ---help--- + Enables support for the onchip USB controller on the PMC_MSP7100 Family SoC's. + If unsure, say N. + config USB_EHCI_BIG_ENDIAN_MMIO bool depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ - PPC_MPC512x || CPU_CAVIUM_OCTEON) + PPC_MPC512x || CPU_CAVIUM_OCTEON || \ + MSP_HAS_USB) default y config USB_EHCI_BIG_ENDIAN_DESC bool depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ - PPC_MPC512x) + PPC_MPC512x || MSP_HAS_USB) default y config XPS_USB_HCD_XILINX diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 502a7e6..833d96a 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -120,6 +120,9 @@ MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n"); #include "ehci-dbg.c" /*-------------------------------------------------------------------------*/ +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP +extern void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci); +#endif static void timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) @@ -259,6 +262,10 @@ static void tdi_reset (struct ehci_hcd *ehci) if (ehci_big_endian_mmio(ehci)) tmp |= USBMODE_BE; ehci_writel(ehci, tmp, reg_ptr); +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP + /* set controller in host mode */ + usb_hcd_tdi_set_mode(ehci); +#endif } /* reset a non-running (STS_HALT == 1) controller */ @@ -1216,6 +1223,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_octeon_driver #endif +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP +#include "ehci-pmcmsp.c" +#define PLATFORM_DRIVER ehci_hcd_msp_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c new file mode 100644 index 0000000..547f63c --- /dev/null +++ b/drivers/usb/host/ehci-pmcmsp.c @@ -0,0 +1,551 @@ +/* + * PMC MSP EHCI (Host Controller Driver) for USB. + * + * (C) Copyright 2006-2010 PMC-Sierra Inc + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +/* includes */ +#define USB_CTRL_MODE_HOST 0x3 + /* host mode */ +#define USB_CTRL_MODE_BIG_ENDIAN 0x4 + /* big endian */ +#define USB_CTRL_MODE_STREAM_DISABLE 0x10 + /* stream disable*/ +#define USB_CTRL_FIFO_THRESH 0x00300000 + /* thresh hold */ +#define USB_EHCI_REG_USB_MODE 0x68 + /* register offset for usb_mode */ +#define USB_EHCI_REG_USB_FIFO 0x24 + /* register offset for usb fifo */ +#define USB_EHCI_REG_USB_STATUS 0x44 + /* register offset for usb status */ +#define USB_EHCI_REG_BIT_STAT_STS (1<<29) + /* serial/parallel transceiver */ +#define MSP_PIN_USB0_HOST_DEV 49 + /* TWI USB0 host device pin */ +#define MSP_PIN_USB1_HOST_DEV 50 + /* TWI USB1 host device pin */ + +extern int usb_disabled(void); + +void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci) +{ + u8 *base; + u8 *statreg; + u8 *fiforeg; + u32 val; + struct ehci_regs *reg_base = ehci->regs; + + /* get register base */ + base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; + statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; + fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; + + /* set the controller to host mode and BIG ENDIAN */ + ehci_writel(ehci, (USB_CTRL_MODE_HOST | USB_CTRL_MODE_BIG_ENDIAN + | USB_CTRL_MODE_STREAM_DISABLE), (u32 *)base); + + /* clear STS to select parallel transceiver interface */ + val = ehci_readl(ehci, (u32 *)statreg); + val = val & ~USB_EHCI_REG_BIT_STAT_STS; + ehci_writel(ehci, val, (u32 *)statreg); + + /* write to set the proper fifo threshold */ + ehci_writel(ehci, USB_CTRL_FIFO_THRESH, (u32 *)fiforeg); + + /* set TWI GPIO USB_HOST_DEV pin high */ + gpio_direction_output(MSP_PIN_USB0_HOST_DEV, 1); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1); +#endif +} + +/* called after powerup, by probe or system-pm "wakeup" */ +static int ehci_msp_reinit(struct ehci_hcd *ehci) +{ + ehci_port_power(ehci, 0); + + return 0; +} + +/* called during probe() after chip reset completes */ +static int ehci_msp_setup(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 temp; + int retval; + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + hcd->has_tt = 1; + tdi_reset(ehci); + + retval = ehci_halt(ehci); + if (retval) + return retval; + + ehci_reset(ehci); + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); + temp &= 0x0f; + if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { + ehci_dbg(ehci, "bogus port configuration: " + "cc=%d x pcc=%d < ports=%d\n", + HCS_N_CC(ehci->hcs_params), + HCS_N_PCC(ehci->hcs_params), + HCS_N_PORTS(ehci->hcs_params)); + } + + retval = ehci_msp_reinit(ehci); + + return retval; +} + +/*-------------------------------------------------------------------------*/ + +static void msp_start_hc(struct platform_device *dev) +{ + printk(KERN_DEBUG __FILE__ + ": starting PMC MSP EHCI USB Controller\n"); + + /* + * Now, carefully enable the USB clock, and take + * the USB host controller out of reset. + */ + printk(KERN_DEBUG __FILE__ + ": Clock to USB host has been enabled\n"); +} + +static void msp_stop_hc(struct platform_device *dev) +{ + printk(KERN_DEBUG __FILE__ + ": stopping PMC MSP EHCI USB Controller\n"); +} + + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_PM + +/* suspend/resume, section 4.3 */ + +/* These routines rely on the bus glue + * to handle powerdown and wakeup, and currently also on + * transceivers that don't need any software attention to set up + * the right sort of wakeup. + * Also they depend on separate root hub suspend/resume. + */ +static int ehci_msp_suspend(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + unsigned long flags; + int rc; + + return 0; + rc = 0; + + if (time_before(jiffies, ehci->next_statechange)) + msleep(10); + + /* Root hub was already suspended. Disable irq emission and + * mark HW unaccessible. The PM and USB cores make sure that + * the root hub is either suspended or stopped. + */ + spin_lock_irqsave(&ehci->lock, flags); + ehci_prepare_ports_for_controller_suspend(ehci, device_may_wakeup(dev)); + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + (void)ehci_readl(ehci, &ehci->regs->intr_enable); + + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + spin_unlock_irqrestore(&ehci->lock, flags); + + /* could save FLADJ in case of Vaux power loss + ... we'd only use it to handle clock skew */ + + return rc; +} + +static int ehci_msp_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + + /* maybe restore FLADJ */ + + if (time_before(jiffies, ehci->next_statechange)) + msleep(100); + + /* Mark hardware accessible again as we are out of D3 state by now */ + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + /* If CF is still set, we maintained PCI Vaux power. + * Just undo the effect of ehci_pci_suspend(). + */ + if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) { + int mask = INTR_MASK; + + ehci_prepare_ports_for_controller_resume(ehci); + if (!hcd->self.root_hub->do_remote_wakeup) + mask &= ~STS_PCD; + ehci_writel(ehci, mask, &ehci->regs->intr_enable); + ehci_readl(ehci, &ehci->regs->intr_enable); + return 0; + } + + ehci_dbg(ehci, "lost power, restarting\n"); + usb_root_hub_lost_power(hcd->self.root_hub); + + /* Else reset, to cope with power loss or flush-to-storage + * style "resume" having let BIOS kick in during reboot. + */ + (void) ehci_halt(ehci); + (void) ehci_reset(ehci); + (void) ehci_msp_reinit(ehci); + + /* emptying the schedule aborts any urbs */ + spin_lock_irq(&ehci->lock); + if (ehci->reclaim) + end_unlink_async(ehci); + ehci_work(ehci); + spin_unlock_irq(&ehci->lock); + + ehci_writel(ehci, ehci->command, &ehci->regs->command); + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ + + /* here we "know" root ports should always stay powered */ + ehci_port_power(ehci, 1); + + hcd->state = HC_STATE_SUSPENDED; + + return 0; +} + +static const struct dev_pm_ops ehci_msp_pmops = { + .suspend = ehci_msp_suspend, + .resume = ehci_msp_resume, +}; +#endif + + +/* configure so an HC device and id are always provided */ +/* always called with process context; sleeping is OK */ + +static int usb_hcd_msp_map_regs(struct mspusb_device *dev) +{ + struct resource *res; + struct platform_device *pdev = &dev->dev; + u32 res_len; + int retval; + + /* MAB register space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res == NULL) + return -ENOMEM; + res_len = res->end - res->start + 1; + if (!request_mem_region(res->start, res_len, "mab regs")) + return -EBUSY; + + dev->mab_regs = ioremap_nocache(res->start, res_len); + if (dev->mab_regs == NULL) { + retval = -ENOMEM; + goto err1; + } + + /* MSP USB register space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (res == NULL) { + retval = -ENOMEM; + goto err2; + } + res_len = res->end - res->start + 1; + if (!request_mem_region(res->start, res_len, "usbid regs")) { + retval = -EBUSY; + goto err2; + } + dev->usbid_regs = ioremap_nocache(res->start, res_len); + if (dev->usbid_regs == NULL) { + retval = -ENOMEM; + goto err3; + } + + return 0; +err3: + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + res_len = res->end - res->start + 1; + release_mem_region(res->start, res_len); +err2: + iounmap(dev->mab_regs); +err1: + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + res_len = res->end - res->start + 1; + release_mem_region(res->start, res_len); + dev_err(&pdev->dev, "Failed to map non-EHCI regs.\n"); + return retval; +} + +/** + * usb_hcd_msp_probe - initialize PMC MSP-based HCDs + * Context: !in_interrupt() + * + * Allocates basic resources for this USB host controller, and + * then invokes the start() method for the HCD associated with it + * through the hotplug entry's driver_data. + * + */ +int usb_hcd_msp_probe(const struct hc_driver *driver, + struct platform_device *dev) +{ + int retval; + struct usb_hcd *hcd; + struct resource *res; + struct ehci_hcd *ehci ; + + hcd = usb_create_hcd(driver, &dev->dev, "pmcmsp"); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (res == NULL) { + pr_debug("No IOMEM resource info for %s.\n", dev->name); + retval = -ENOMEM; + goto err1; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, dev->name)) { + retval = -EBUSY; + goto err1; + } + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed"); + retval = -ENOMEM; + goto err2; + } + msp_start_hc(dev); + + res = platform_get_resource(dev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&dev->dev, "No IRQ resource info for %s.\n", dev->name); + retval = -ENOMEM; + goto err3; + } + + /* Map non-EHCI register spaces */ + retval = usb_hcd_msp_map_regs(to_mspusb_device(dev)); + if (retval != 0) + goto err3; + + ehci = hcd_to_ehci(hcd); + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 1; + + + retval = usb_add_hcd(hcd, res->start, IRQF_SHARED); + if (retval == 0) + return 0; + + usb_remove_hcd(hcd); +err3: + msp_stop_hc(dev); + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + + return retval; +} + + +/* may be called without controller electrically present */ +/* may be called with controller, bus, and devices active */ + +/** + * usb_hcd_msp_remove - shutdown processing for PMC MSP-based HCDs + * @dev: USB Host Controller being removed + * Context: !in_interrupt() + * + * Reverses the effect of usb_hcd_msp_probe(), first invoking + * the HCD's stop() method. It is always called from a thread + * context, normally "rmmod", "apmd", or something similar. + * + */ +void usb_hcd_msp_remove(struct usb_hcd *hcd, struct platform_device *dev) +{ + usb_remove_hcd(hcd); + msp_stop_hc(dev); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); +} + +#ifdef CONFIG_MSP_HAS_DUAL_USB +/*-------------------------------------------------------------------------*/ +/* + * Wrapper around the main ehci_irq. Since both USB host controllers are + * sharing the same IRQ, need to first determine whether we're the intended + * recipient of this interrupt. + */ +static irqreturn_t ehci_msp_irq(struct usb_hcd *hcd) +{ + u32 int_src; + struct device *dev = hcd->self.controller; + struct platform_device *pdev; + struct mspusb_device *mdev; + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + /* need to reverse-map a couple of containers to get our device */ + pdev = to_platform_device(dev); + mdev = to_mspusb_device(pdev); + + /* Check to see if this interrupt is for this host controller */ + int_src = ehci_readl(ehci, &mdev->mab_regs->int_stat); + if (int_src & (1 << pdev->id)) + return ehci_irq(hcd); + + /* Not for this device */ + return IRQ_NONE; +} +/*-------------------------------------------------------------------------*/ +#endif /* DUAL_USB */ + +static const struct hc_driver ehci_msp_hc_driver = { + .description = hcd_name, + .product_desc = "PMC MSP EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ +#ifdef CONFIG_MSP_HAS_DUAL_USB + .irq = ehci_msp_irq, +#else + .irq = ehci_irq, +#endif + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + */ + .reset = ehci_msp_setup, + .start = ehci_run, + .shutdown = ehci_shutdown, + .start = ehci_run, + .stop = ehci_stop, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_hcd_msp_drv_probe(struct platform_device *pdev) +{ + int ret; + + pr_debug("In ehci_hcd_msp_drv_probe"); + + if (usb_disabled()) + return -ENODEV; + + gpio_request(MSP_PIN_USB0_HOST_DEV, "USB0_HOST_DEV_GPIO"); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_request(MSP_PIN_USB1_HOST_DEV, "USB1_HOST_DEV_GPIO"); +#endif + + ret = usb_hcd_msp_probe(&ehci_msp_hc_driver, pdev); + + return ret; +} + +static int ehci_hcd_msp_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_hcd_msp_remove(hcd, pdev); + + /* free TWI GPIO USB_HOST_DEV pin */ + gpio_free(MSP_PIN_USB0_HOST_DEV); +#ifdef CONFIG_MSP_HAS_DUAL_USB + gpio_free(MSP_PIN_USB1_HOST_DEV); +#endif + + return 0; +} + +MODULE_ALIAS("pmcmsp-ehci"); + +static struct platform_driver ehci_hcd_msp_driver = { + .probe = ehci_hcd_msp_drv_probe, + .remove = ehci_hcd_msp_drv_remove, + .driver = { + .name = "pmcmsp-ehci", + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &ehci_msp_pmops, +#endif + }, +}; -- 1.7.0.4 From anoop.pa@gmail.com Wed Dec 22 15:29:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 15:29:15 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:36741 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491022Ab0LVO3M (ORCPT ); Wed, 22 Dec 2010 15:29:12 +0100 Received: by vws5 with SMTP id 5so1966273vws.36 for ; Wed, 22 Dec 2010 06:29:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=ziC+gyI7yK3WCyafHo2RJ1yj4XbyAfv7VfB4xVWs2CE=; b=aI4CYGgM+yaMKPxNbFml5HQsmEAtNQr9sVoKqPv2pG5jFMFDSAfxAKEbiJtj7FNaeT F0/BRAdRajLoN+3b36r2XRGTNPNyxgVe9DARL2fx9meLxXvDT2j3wa1GNVDoDtQ7rVCi BnOIKBKeqSoc9lmJZr0jKIcWGDqK9e90OMiqo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=DFBRRDdB8xY4+AEFPg1e7a6onemgbYYNhChMR8vYJLRE53ThN4eNNr4JZIVfWYiTxU 4D8ZgrRd7Z+7q3iFTpiovbwdS/PmDL3H8YVJ5uzyyp84XzURWdVPs/lfsgIZZrrPO3dW iPBkbd/H2MWpVlsRUF48XG9kUepvomrBkHPD8= Received: by 10.220.194.197 with SMTP id dz5mr1924193vcb.113.1293028139785; Wed, 22 Dec 2010 06:28:59 -0800 (PST) Received: from localhost.localdomain ([59.160.135.215]) by mx.google.com with ESMTPS id g27sm2364430vby.4.2010.12.22.06.28.53 (version=SSLv3 cipher=RC4-MD5); Wed, 22 Dec 2010 06:28:59 -0800 (PST) From: "Anoop P.A" To: Ralf Baechle , Greg Kroah-Hartman , Anatolij Gustschin , Anand Gadiyar , Alan Stern , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Sarah Sharp , Oliver Neukum , Hans de Goede , Paul Mortier , Andiry Xu Cc: Anoop P A Subject: [PATCH V2 2/2] MSP onchip root hub over current quirk. Date: Wed, 22 Dec 2010 20:06:50 +0530 Message-Id: <1293028610-22233-1-git-send-email-anoop.pa@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> References: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28680 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 2696 Lines: 96 From: Anoop P A Adding chip specific code under quirk. Signed-off-by: Anoop P A --- drivers/usb/core/hub.c | 45 ++++++++++++++++++++++++++++++++++++++----- drivers/usb/core/quirks.c | 3 ++ include/linux/usb/quirks.h | 3 ++ 3 files changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 27115b4..4bff994 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -3377,12 +3377,45 @@ static void hub_events(void) } if (portchange & USB_PORT_STAT_C_OVERCURRENT) { - dev_err (hub_dev, - "over-current change on port %d\n", - i); - clear_port_feature(hdev, i, - USB_PORT_FEAT_C_OVER_CURRENT); - hub_power_on(hub, true); + usb_detect_quirks(hdev); + if (hdev->quirks & USB_QUIRK_MSP_OVERCURRENT) { + /* clear OCC bit */ + clear_port_feature(hdev, i, + USB_PORT_FEAT_C_OVER_CURRENT); + + /* This step is required to toggle the + * PP bit to 0 and 1 (by hub_power_on) + * in order the CSC bit to be + * transitioned properly for device + * hotplug + */ + /* clear PP bit */ + clear_port_feature(hdev, i, + USB_PORT_FEAT_POWER); + + /* resume power */ + hub_power_on(hub, true); + + /* delay 100 usec */ + udelay(100); + + /* read OCA bit */ + if (portstatus & + (1<); Wed, 22 Dec 2010 15:50:23 +0100 Received: by vws5 with SMTP id 5so1975611vws.36 for ; Wed, 22 Dec 2010 06:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=kFuBNt8cU37MG+QfJ8JVaxnecPIh930NClxrReMYnYM=; b=F7+YWBlrT79TILqNg7rJhxEMwGcod+q0XiK59ViGdD3EtjyM+rDL8xvEHG8GIn9zg4 RU2ulQev8u+w12aHhb2hV3/X/oZ2PLvkjJW09HV8VUToh8DuN+XWxBlyYFlmJMaD8SVZ UmCkfNI21H8kQE6Sei5I0L6knPr/EqXjl3uIA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=HSsJG9OgoKwt1Cp7QZ+N98TlD9sIm4vrFcjZT4jckr43ELseXqpV3mAxiX1n5zmXsL tY98sRpIlMbnWv7XyMiwyWMik5pXUciU55OqxXLheRYQJMJXkjA77xY/vLiLhjrDKpY+ +KuRLApPo1iLdJZSsoWM28Ci9H2V5bH8e83EU= Received: by 10.220.175.139 with SMTP id ba11mr2248390vcb.58.1293029416496; Wed, 22 Dec 2010 06:50:16 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id y4sm1340855vch.11.2010.12.22.06.50.11 (version=SSLv3 cipher=RC4-MD5); Wed, 22 Dec 2010 06:50:14 -0800 (PST) Subject: Re: [PATCH V2 1/2] EHCI support for on-chip PMC MSP USB controller. From: Anoop P A To: Ralf Baechle Cc: Greg Kroah-Hartman , Anatolij Gustschin , Anand Gadiyar , Alan Stern , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org In-Reply-To: <1293028561-22125-1-git-send-email-anoop.pa@gmail.com> References: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> <1293028561-22125-1-git-send-email-anoop.pa@gmail.com> Content-Type: text/plain; charset="UTF-8" Date: Wed, 22 Dec 2010 20:28:12 +0530 Message-ID: <1293029892.27661.42.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28681 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 387 Lines: 17 On Wed, 2010-12-22 at 20:06 +0530, Anoop P.A wrote: > From: Anoop P A > > This patch includes. > > 1. USB host driver for MSP71xx family SoC on-chip USB controller. > ehci_writel(ehci, tmp, reg_ptr); > +#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP > + /* set controller in host mode */ > + usb_hcd_tdi_set_mode(ehci); > +#endif Missed this one while cleaning :( > } From stuart.venters@adtran.com Wed Dec 22 17:35:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 17:35:31 +0100 (CET) Received: from p02c12o145.mxlogic.net ([208.65.145.78]:38206 "EHLO p02c12o145.mxlogic.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491042Ab0LVQf1 (ORCPT ); Wed, 22 Dec 2010 17:35:27 +0100 Received: from unknown [76.164.174.81] by p02c12o145.mxlogic.net(mxl_mta-6.8.0-0) with SMTP id ac8221d4.0.11843.00-257.30000.p02c12o145.mxlogic.net (envelope-from ); Wed, 22 Dec 2010 09:35:27 -0700 (MST) X-MXL-Hash: 4d1228cf14712109-8edf2454727f4f048cf37951eb1249d161abde92 Received: from corp-exfr1.corp.adtran.com (172.23.101.21) by ex-hc1.corp.adtran.com (172.22.50.71) with Microsoft SMTP Server id 14.1.255.0; Wed, 22 Dec 2010 10:35:19 -0600 Received: from EXV1.corp.adtran.com ([172.22.48.215]) by corp-exfr1.corp.adtran.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 22 Dec 2010 10:34:41 -0600 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-Class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Subject: RE: SMTC support status in latest git head. Date: Wed, 22 Dec 2010 10:34:39 -0600 Message-ID: <8F242B230AD6474C8E7815DE0B4982D7179FB887@EXV1.corp.adtran.com> In-Reply-To: <4D11F707.8040205@paralogos.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: SMTC support status in latest git head. Thread-Index: Acuh2JVP6SJCcb4LQuy7QpT3p4hZEgAHK/jw From: STUART VENTERS To: Anoop P A CC: Anoop P.A. , , "Kevin D. Kissell" X-OriginalArrivalTime: 22 Dec 2010 16:34:41.0011 (UTC) FILETIME=[21BAD430:01CBA1F6] X-Spam: [F=0.2000000000; CM=0.500; S=0.200(2010121501)] X-MAIL-FROM: X-SOURCE-IP: [(unknown)] X-AnalysisOut: [v=1.0 c=1 a=fMTePymILGAA:10 a=BLceEmwcHowA:10 a=IkcTkHD0fZ] X-AnalysisOut: [MA:10 a=0XgpNN2/4a34ymu16SVwsQ==:17 a=GD5LJJB7AAAA:8 a=WPy] X-AnalysisOut: [IoOwQAAAA:8 a=l1wv9796wFpycM6FTcYA:9 a=00FmtkIcvJrjAydLHE0] X-AnalysisOut: [A:7 a=jaZI9WZ0oLx7qkTLzJc8KuY4qjcA:4 a=QEXdDO2ut3YA:10 a=b] X-AnalysisOut: [vPO4xL1mq4A:10 a=1DbiqZag68YA:10] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28682 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stuart.venters@adtran.com Precedence: bulk X-list: linux-mips Content-Length: 4398 Lines: 58 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ZSANCmJyZWFraW5nIGluIHdpdGggTk1JLCB0aGF0IGNvdWxkIGhlbHAgaWRlbnRpZnkgbW9yZSBw cmVjaXNlbHkgd2hlcmUgaXQncyANCmxvY2tpbmcgdXAuDQoNCllvdSByZWFsbHkgb3VnaHQgdG8g dHJ5IHRvIGJvcnJvdyBhbiBFSlRBRyBwcm9iZS4gIEl0IHdvdWxkIHNhdmUgdXMgYm90aCANCmEg bG90IG9mIHRpbWUuICBBbmQgbXkgdGltZSB0byB0cm91YmxlLXNob290IHRoaXMgd2l0aCB5b3Ug aXMgbGltaXRlZC4NCg0KICAgICAgICAgICAgIFJlZ2FyZHMsDQoNCiAgICAgICAgICAgICBLZXZp biBLLg0K From juhosg@openwrt.org Wed Dec 22 21:31:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:31:27 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37484 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491061Ab0LVUbW (ORCPT ); Wed, 22 Dec 2010 21:31:22 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id A86ED80F0; Wed, 22 Dec 2010 21:31:17 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id F22DE1F0001; Wed, 22 Dec 2010 21:31:16 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos , David Brownell Subject: [PATCH v2 02/16] MIPS: ath79: add GPIOLIB support Date: Wed, 22 Dec 2010 21:30:47 +0100 Message-Id: <1293049861-28913-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F2572671 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28683 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 10021 Lines: 358 This patch implements generic GPIO routines for the built-in GPIO controllers of the Atheros AR71XX/AR724X/AR913X SoCs. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: David Brownell --- Changes since RFC: --- Changes since v1: - rebased against 2.6.37-rc7 arch/mips/Kconfig | 1 + arch/mips/ath79/Makefile | 2 +- arch/mips/ath79/common.h | 5 + arch/mips/ath79/gpio.c | 197 ++++++++++++++++++++++++ arch/mips/ath79/setup.c | 2 +- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 21 +++ arch/mips/include/asm/mach-ath79/gpio.h | 26 +++ 7 files changed, 252 insertions(+), 2 deletions(-) create mode 100644 arch/mips/ath79/gpio.c create mode 100644 arch/mips/include/asm/mach-ath79/gpio.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c0511d6..c3270a4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -67,6 +67,7 @@ config AR7 config ATH79 bool "Atheros AR71XX/AR724X/AR913X based boards" + select ARCH_REQUIRE_GPIOLIB select BOOT_RAW select CEVT_R4K select CSRC_R4K diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index b4ec9c2..facbb70 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -8,7 +8,7 @@ # under the terms of the GNU General Public License version 2 as published # by the Free Software Foundation. -obj-y := prom.o setup.o irq.o common.o +obj-y := prom.o setup.o irq.o common.o gpio.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h index a1bcdbb..cb2f3e8 100644 --- a/arch/mips/ath79/common.h +++ b/arch/mips/ath79/common.h @@ -22,4 +22,9 @@ void ath79_ddr_wb_flush(unsigned int reg); +void ath79_gpio_function_enable(u32 mask); +void ath79_gpio_function_disable(u32 mask); +void ath79_gpio_function_setup(u32 set, u32 clear); +void ath79_gpio_init(void) __init; + #endif /* __ATH79_COMMON_H */ diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c new file mode 100644 index 0000000..a0c426b --- /dev/null +++ b/arch/mips/ath79/gpio.c @@ -0,0 +1,197 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "common.h" + +static void __iomem *ath79_gpio_base; +static unsigned long ath79_gpio_count; +static DEFINE_SPINLOCK(ath79_gpio_lock); + +static void __ath79_gpio_set_value(unsigned gpio, int value) +{ + void __iomem *base = ath79_gpio_base; + + if (value) + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); +} + +static int __ath79_gpio_get_value(unsigned gpio) +{ + return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1; +} + +static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + return __ath79_gpio_get_value(offset); +} + +static void ath79_gpio_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + __ath79_gpio_set_value(offset, value); +} + +static int ath79_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static int ath79_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + if (value) + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, + .set = ath79_gpio_set_value, + .direction_input = ath79_gpio_direction_input, + .direction_output = ath79_gpio_direction_output, + .base = 0, +}; + +void ath79_gpio_function_enable(u32 mask) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void ath79_gpio_function_disable(u32 mask) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void ath79_gpio_function_setup(u32 set, u32 clear) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void __init ath79_gpio_init(void) +{ + int err; + + if (soc_is_ar71xx()) + ath79_gpio_count = AR71XX_GPIO_COUNT; + else if (soc_is_ar724x()) + ath79_gpio_count = AR724X_GPIO_COUNT; + else if (soc_is_ar913x()) + ath79_gpio_count = AR913X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; + + err = gpiochip_add(&ath79_gpio_chip); + if (err) + panic("cannot add AR71xx GPIO chip, error=%d", err); +} + +int gpio_get_value(unsigned gpio) +{ + if (gpio < ath79_gpio_count) + return __ath79_gpio_get_value(gpio); + + return __gpio_get_value(gpio); +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int value) +{ + if (gpio < ath79_gpio_count) + __ath79_gpio_set_value(gpio, value); + else + __gpio_set_value(gpio, value); +} +EXPORT_SYMBOL(gpio_set_value); + +int gpio_to_irq(unsigned gpio) +{ + /* FIXME */ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int irq_to_gpio(unsigned irq) +{ + /* FIXME */ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 4157ddc..83dd855 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -230,7 +230,6 @@ void __init plat_mem_setup(void) AR71XX_RESET_SIZE); ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); - ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE); @@ -256,6 +255,7 @@ void __init plat_time_init(void) static int __init ath79_setup(void) { + ath79_gpio_init(); ath79_register_uart(); return 0; } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 5a9e5e1..7f2933d 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -25,6 +25,8 @@ #define AR71XX_DDR_CTRL_SIZE 0x100 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR71XX_UART_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) #define AR71XX_PLL_SIZE 0x100 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) @@ -204,4 +206,23 @@ #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ AR71XX_SPI_IOC_CS2) +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +#define AR71XX_GPIO_COUNT 16 +#define AR724X_GPIO_COUNT 18 +#define AR913X_GPIO_COUNT 22 + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/arch/mips/include/asm/mach-ath79/gpio.h b/arch/mips/include/asm/mach-ath79/gpio.h new file mode 100644 index 0000000..60dcb62 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/gpio.h @@ -0,0 +1,26 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MACH_ATH79_GPIO_H +#define __ASM_MACH_ATH79_GPIO_H + +#define ARCH_NR_GPIOS 64 +#include + +int gpio_to_irq(unsigned gpio); +int irq_to_gpio(unsigned irq); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); + +#define gpio_cansleep __gpio_cansleep + +#endif /* __ASM_MACH_ATH79_GPIO_H */ -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:31:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:31:53 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37482 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491050Ab0LVUbW (ORCPT ); Wed, 22 Dec 2010 21:31:22 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 9EAC380EC; Wed, 22 Dec 2010 21:31:15 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 049241F0001; Wed, 22 Dec 2010 21:31:14 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 00/16] MIPS: initial support for the Atheros AR71XX/AR724X/AR913X SoCs Date: Wed, 22 Dec 2010 21:30:45 +0100 Message-Id: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 X-VBMS: A10F1D64E69 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28684 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 6695 Lines: 122 This patch set contains initial support for the Atheros AR71XX/AR724X/AR913X SoCs. Generic changes since v1: - rebased against 2.6.37-rc7 - the 'MIPS: Add generic support for multiple machines within a single kernel' patch has been removed, because that is in the mips-queue tree already - the 'input: add input driver for polled GPIO buttons' patch has been removed, because a slightly different version of that driver is present in 2.6.37-rc7 already as 'gpio_keys_polled' Gabor Juhos (16): MIPS: add initial support for the Atheros AR71XX/AR724X/AR931X SoCs MIPS: ath79: add GPIOLIB support MIPS: ath79: utilize the MIPS multi-machine support MIPS: ath79: add initial support for the Atheros PB44 reference board MIPS: ath79: add common GPIO LEDs device watchdog: add driver for the Atheros AR71XX/AR724X/AR913X SoCs MIPS: ath79: add common watchdog device MIPS: ath79: add common GPIO buttons device spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs MIPS: ath79: add common SPI controller device USB: ehci: add workaround for Synopsys HC bug USB: ehci: add bus glue for the Atheros AR71XX/AR724X/AR913X SoCs USB: ohci: add bus glue for the Atheros AR71XX/AR7240 SoCs MIPS: ath79: add common USB Host Controller device MIPS: ath79: add initial support for the Atheros AP81 reference board MIPS: ath79: add common WMAC device for AR913X based boards arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 17 ++ arch/mips/ath79/Kconfig | 60 ++++ arch/mips/ath79/Makefile | 29 ++ arch/mips/ath79/Platform | 7 + arch/mips/ath79/common.c | 97 +++++++ arch/mips/ath79/common.h | 30 ++ arch/mips/ath79/dev-ar913x-wmac.c | 60 ++++ arch/mips/ath79/dev-ar913x-wmac.h | 17 ++ arch/mips/ath79/dev-common.c | 69 +++++ arch/mips/ath79/dev-common.h | 18 ++ arch/mips/ath79/dev-gpio-buttons.c | 58 ++++ arch/mips/ath79/dev-gpio-buttons.h | 23 ++ arch/mips/ath79/dev-leds-gpio.c | 56 ++++ arch/mips/ath79/dev-leds-gpio.h | 21 ++ arch/mips/ath79/dev-spi.c | 38 +++ arch/mips/ath79/dev-spi.h | 22 ++ arch/mips/ath79/dev-usb.c | 194 +++++++++++++ arch/mips/ath79/dev-usb.h | 17 ++ arch/mips/ath79/early_printk.c | 36 +++ arch/mips/ath79/gpio.c | 197 +++++++++++++ arch/mips/ath79/irq.c | 187 +++++++++++++ arch/mips/ath79/mach-ap81.c | 100 +++++++ arch/mips/ath79/mach-pb44.c | 120 ++++++++ arch/mips/ath79/machtypes.h | 23 ++ arch/mips/ath79/prom.c | 57 ++++ arch/mips/ath79/setup.c | 279 +++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 253 +++++++++++++++++ arch/mips/include/asm/mach-ath79/ath79.h | 100 +++++++ .../include/asm/mach-ath79/ath79_ehci_platform.h | 18 ++ .../include/asm/mach-ath79/ath79_spi_platform.h | 19 ++ .../include/asm/mach-ath79/cpu-feature-overrides.h | 56 ++++ arch/mips/include/asm/mach-ath79/gpio.h | 26 ++ arch/mips/include/asm/mach-ath79/irq.h | 36 +++ .../include/asm/mach-ath79/kernel-entry-init.h | 32 +++ arch/mips/include/asm/mach-ath79/war.h | 25 ++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 290 +++++++++++++++++++ drivers/usb/host/Kconfig | 16 + drivers/usb/host/ehci-ath79.c | 176 ++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-q.c | 3 + drivers/usb/host/ehci.h | 1 + drivers/usb/host/ohci-ath79.c | 162 +++++++++++ drivers/usb/host/ohci-hcd.c | 5 + drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ath79_wdt.c | 293 ++++++++++++++++++++ 49 files changed, 3367 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/Kconfig create mode 100644 arch/mips/ath79/Makefile create mode 100644 arch/mips/ath79/Platform create mode 100644 arch/mips/ath79/common.c create mode 100644 arch/mips/ath79/common.h create mode 100644 arch/mips/ath79/dev-ar913x-wmac.c create mode 100644 arch/mips/ath79/dev-ar913x-wmac.h create mode 100644 arch/mips/ath79/dev-common.c create mode 100644 arch/mips/ath79/dev-common.h create mode 100644 arch/mips/ath79/dev-gpio-buttons.c create mode 100644 arch/mips/ath79/dev-gpio-buttons.h create mode 100644 arch/mips/ath79/dev-leds-gpio.c create mode 100644 arch/mips/ath79/dev-leds-gpio.h create mode 100644 arch/mips/ath79/dev-spi.c create mode 100644 arch/mips/ath79/dev-spi.h create mode 100644 arch/mips/ath79/dev-usb.c create mode 100644 arch/mips/ath79/dev-usb.h create mode 100644 arch/mips/ath79/early_printk.c create mode 100644 arch/mips/ath79/gpio.c create mode 100644 arch/mips/ath79/irq.c create mode 100644 arch/mips/ath79/mach-ap81.c create mode 100644 arch/mips/ath79/mach-pb44.c create mode 100644 arch/mips/ath79/machtypes.h create mode 100644 arch/mips/ath79/prom.c create mode 100644 arch/mips/ath79/setup.c create mode 100644 arch/mips/include/asm/mach-ath79/ar71xx_regs.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h create mode 100644 arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-ath79/gpio.h create mode 100644 arch/mips/include/asm/mach-ath79/irq.h create mode 100644 arch/mips/include/asm/mach-ath79/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-ath79/war.h create mode 100644 drivers/spi/ath79_spi.c create mode 100644 drivers/usb/host/ehci-ath79.c create mode 100644 drivers/usb/host/ohci-ath79.c create mode 100644 drivers/watchdog/ath79_wdt.c -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:32:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:32:18 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37483 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491063Ab0LVUbX (ORCPT ); Wed, 22 Dec 2010 21:31:23 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 5EB3D80EF; Wed, 22 Dec 2010 21:31:17 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 7E51A1F0001; Wed, 22 Dec 2010 21:31:15 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 01/16] MIPS: add initial support for the Atheros AR71XX/AR724X/AR931X SoCs Date: Wed, 22 Dec 2010 21:30:46 +0100 Message-Id: <1293049861-28913-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F21E45A2 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28685 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 40831 Lines: 1455 This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- Changes since RFC: - the ATH79_DEV_UART Kconfig option is removed, and the URT platform code has been moved into dev-common[ch] Changes since v1: - ath79_device_{start,stop} has been renamed to ath79_device_reset_{set,clear} to to reflect the purpose of these functions better - some definitions has been moved from 'arch/mips/ath79/common.h' to 'arch/mips/include/asm/mach-ath79/ath79.h' to make them available for future drivers - rebased against 2.6.37-rc7 arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 15 ++ arch/mips/ath79/Kconfig | 12 + arch/mips/ath79/Makefile | 18 ++ arch/mips/ath79/Platform | 7 + arch/mips/ath79/common.c | 97 +++++++ arch/mips/ath79/common.h | 25 ++ arch/mips/ath79/dev-common.c | 59 +++++ arch/mips/ath79/dev-common.h | 17 ++ arch/mips/ath79/early_printk.c | 36 +++ arch/mips/ath79/irq.c | 187 ++++++++++++++ arch/mips/ath79/prom.c | 57 +++++ arch/mips/ath79/setup.c | 263 ++++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 207 +++++++++++++++ arch/mips/include/asm/mach-ath79/ath79.h | 100 ++++++++ .../include/asm/mach-ath79/cpu-feature-overrides.h | 56 ++++ arch/mips/include/asm/mach-ath79/irq.h | 36 +++ .../include/asm/mach-ath79/kernel-entry-init.h | 32 +++ arch/mips/include/asm/mach-ath79/war.h | 25 ++ 19 files changed, 1250 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/Kconfig create mode 100644 arch/mips/ath79/Makefile create mode 100644 arch/mips/ath79/Platform create mode 100644 arch/mips/ath79/common.c create mode 100644 arch/mips/ath79/common.h create mode 100644 arch/mips/ath79/dev-common.c create mode 100644 arch/mips/ath79/dev-common.h create mode 100644 arch/mips/ath79/early_printk.c create mode 100644 arch/mips/ath79/irq.c create mode 100644 arch/mips/ath79/prom.c create mode 100644 arch/mips/ath79/setup.c create mode 100644 arch/mips/include/asm/mach-ath79/ar71xx_regs.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79.h create mode 100644 arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-ath79/irq.h create mode 100644 arch/mips/include/asm/mach-ath79/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-ath79/war.h diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 78439b8..7ff9b54 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -2,6 +2,7 @@ platforms += alchemy platforms += ar7 +platforms += ath79 platforms += bcm47xx platforms += bcm63xx platforms += cavium-octeon diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 913d50d..c0511d6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -65,6 +65,20 @@ config AR7 Support for the Texas Instruments AR7 System-on-a-Chip family: TNETD7100, 7200 and 7300. +config ATH79 + bool "Atheros AR71XX/AR724X/AR913X based boards" + select BOOT_RAW + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + Support for the Atheros AR71XX/AR724X/AR913X SoCs. + config BCM47XX bool "Broadcom BCM47XX based boards" select CEVT_R4K @@ -717,6 +731,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD endchoice source "arch/mips/alchemy/Kconfig" +source "arch/mips/ath79/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig new file mode 100644 index 0000000..50b9334 --- /dev/null +++ b/arch/mips/ath79/Kconfig @@ -0,0 +1,12 @@ +if ATH79 + +config SOC_AR71XX + def_bool n + +config SOC_AR724X + def_bool n + +config SOC_AR913X + def_bool n + +endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile new file mode 100644 index 0000000..b4ec9c2 --- /dev/null +++ b/arch/mips/ath79/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the Atheros AR71XX/AR724X/AR913X specific parts of the kernel +# +# Copyright (C) 2008-2010 Gabor Juhos +# Copyright (C) 2008 Imre Kaloz +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := prom.o setup.o irq.o common.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +# +# Devices +# +obj-y += dev-common.o diff --git a/arch/mips/ath79/Platform b/arch/mips/ath79/Platform new file mode 100644 index 0000000..2bd6636 --- /dev/null +++ b/arch/mips/ath79/Platform @@ -0,0 +1,7 @@ +# +# Atheros AR71xx/AR724x/AR913x +# + +platform-$(CONFIG_ATH79) += ath79/ +cflags-$(CONFIG_ATH79) += -I$(srctree)/arch/mips/include/asm/mach-ath79 +load-$(CONFIG_ATH79) = 0xffffffff80060000 diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c new file mode 100644 index 0000000..58f60e7 --- /dev/null +++ b/arch/mips/ath79/common.c @@ -0,0 +1,97 @@ +/* + * Atheros AR71XX/AR724X/AR913X common routines + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include "common.h" + +static DEFINE_SPINLOCK(ath79_device_reset_lock); + +u32 ath79_cpu_freq; +EXPORT_SYMBOL_GPL(ath79_cpu_freq); + +u32 ath79_ahb_freq; +EXPORT_SYMBOL_GPL(ath79_ahb_freq); + +u32 ath79_ddr_freq; +EXPORT_SYMBOL_GPL(ath79_ddr_freq); + +enum ath79_soc_type ath79_soc; + +void __iomem *ath79_pll_base; +void __iomem *ath79_reset_base; +EXPORT_SYMBOL_GPL(ath79_reset_base); +void __iomem *ath79_ddr_base; + +void ath79_ddr_wb_flush(u32 reg) +{ + void __iomem *flush_reg = ath79_ddr_base + reg; + + /* Flush the DDR write buffer. */ + __raw_writel(0x1, flush_reg); + while (__raw_readl(flush_reg) & 0x1) + ; + + /* It must be run twice. */ + __raw_writel(0x1, flush_reg); + while (__raw_readl(flush_reg) & 0x1) + ; +} +EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush); + +void ath79_device_reset_set(u32 mask) +{ + unsigned long flags; + u32 reg; + u32 t; + + if (soc_is_ar71xx()) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x()) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x()) + reg = AR913X_RESET_REG_RESET_MODULE; + else + BUG(); + + spin_lock_irqsave(&ath79_device_reset_lock, flags); + t = ath79_reset_rr(reg); + ath79_reset_wr(reg, t | mask); + spin_unlock_irqrestore(&ath79_device_reset_lock, flags); +} +EXPORT_SYMBOL_GPL(ath79_device_reset_set); + +void ath79_device_reset_clear(u32 mask) +{ + unsigned long flags; + u32 reg; + u32 t; + + if (soc_is_ar71xx()) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x()) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x()) + reg = AR913X_RESET_REG_RESET_MODULE; + else + BUG(); + + spin_lock_irqsave(&ath79_device_reset_lock, flags); + t = ath79_reset_rr(reg); + ath79_reset_wr(reg, t & ~mask); + spin_unlock_irqrestore(&ath79_device_reset_lock, flags); +} +EXPORT_SYMBOL_GPL(ath79_device_reset_clear); diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h new file mode 100644 index 0000000..a1bcdbb --- /dev/null +++ b/arch/mips/ath79/common.h @@ -0,0 +1,25 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ATH79_COMMON_H +#define __ATH79_COMMON_H + +#include +#include + +#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) +#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) + +void ath79_ddr_wb_flush(unsigned int reg); + +#endif /* __ATH79_COMMON_H */ diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c new file mode 100644 index 0000000..897522c --- /dev/null +++ b/arch/mips/ath79/dev-common.c @@ -0,0 +1,59 @@ +/* + * Atheros AR71XX/AR724X/AR913X common devices + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include "common.h" +#include "dev-common.h" + +static struct resource ath79_uart_resources[] = { + { + .start = AR71XX_UART_BASE, + .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) +static struct plat_serial8250_port ath79_uart_data[] = { + { + .mapbase = AR71XX_UART_BASE, + .irq = ATH79_MISC_IRQ_UART, + .flags = AR71XX_UART_FLAGS, + .iotype = UPIO_MEM32, + .regshift = 2, + }, { + /* terminating entry */ + } +}; + +static struct platform_device ath79_uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .resource = ath79_uart_resources, + .num_resources = ARRAY_SIZE(ath79_uart_resources), + .dev = { + .platform_data = ath79_uart_data + }, +}; + +void __init ath79_register_uart(void) +{ + ath79_uart_data[0].uartclk = ath79_ahb_freq; + platform_device_register(&ath79_uart_device); +} diff --git a/arch/mips/ath79/dev-common.h b/arch/mips/ath79/dev-common.h new file mode 100644 index 0000000..1cec894 --- /dev/null +++ b/arch/mips/ath79/dev-common.h @@ -0,0 +1,17 @@ +/* + * Atheros AR71XX/AR724X/AR913X common devices + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_COMMON_H +#define _ATH79_DEV_COMMON_H + +void ath79_register_uart(void) __init; + +#endif /* _ATH79_DEV_COMMON_H */ diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c new file mode 100644 index 0000000..7499b0e --- /dev/null +++ b/arch/mips/ath79/early_printk.c @@ -0,0 +1,36 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC early printk support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +static inline void prom_wait_thre(void __iomem *base) +{ + u32 lsr; + + do { + lsr = __raw_readl(base + UART_LSR * 4); + if (lsr & UART_LSR_THRE) + break; + } while (1); +} + +void prom_putchar(unsigned char ch) +{ + void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); + + prom_wait_thre(base); + __raw_writel(ch, base + UART_TX * 4); + prom_wait_thre(base); +} diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c new file mode 100644 index 0000000..1bf7f71 --- /dev/null +++ b/arch/mips/ath79/irq.c @@ -0,0 +1,187 @@ +/* + * Atheros AR71xx/AR724x/AR913x specific interrupt handling + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "common.h" + +static unsigned int ath79_ip2_flush_reg; +static unsigned int ath79_ip3_flush_reg; + +static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *base = ath79_reset_base; + u32 pending; + + pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + if (pending & MISC_INT_UART) + generic_handle_irq(ATH79_MISC_IRQ_UART); + + else if (pending & MISC_INT_DMA) + generic_handle_irq(ATH79_MISC_IRQ_DMA); + + else if (pending & MISC_INT_PERFC) + generic_handle_irq(ATH79_MISC_IRQ_PERFC); + + else if (pending & MISC_INT_TIMER) + generic_handle_irq(ATH79_MISC_IRQ_TIMER); + + else if (pending & MISC_INT_OHCI) + generic_handle_irq(ATH79_MISC_IRQ_OHCI); + + else if (pending & MISC_INT_ERROR) + generic_handle_irq(ATH79_MISC_IRQ_ERROR); + + else if (pending & MISC_INT_GPIO) + generic_handle_irq(ATH79_MISC_IRQ_GPIO); + + else if (pending & MISC_INT_WDOG) + generic_handle_irq(ATH79_MISC_IRQ_WDOG); + + else + spurious_interrupt(); +} + +static void ar71xx_misc_irq_unmask(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + +static void ar71xx_misc_irq_mask(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + +static void ar724x_misc_irq_ack(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); +} + +static struct irq_chip ath79_misc_irq_chip = { + .name = "MISC", + .unmask = ar71xx_misc_irq_unmask, + .mask = ar71xx_misc_irq_mask, +}; + +static void __init ath79_misc_irq_init(void) +{ + void __iomem *base = ath79_reset_base; + int i; + + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); + + if (soc_is_ar71xx() || soc_is_ar913x()) + ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; + else if (soc_is_ar724x()) + ath79_misc_irq_chip.ack = ar724x_misc_irq_ack; + else + BUG(); + + for (i = ATH79_MISC_IRQ_BASE; + i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { + irq_desc[i].status = IRQ_DISABLED; + set_irq_chip_and_handler(i, &ath79_misc_irq_chip, + handle_level_irq); + } + + set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(ATH79_CPU_IRQ_TIMER); + + else if (pending & STATUSF_IP2) { + ath79_ddr_wb_flush(ath79_ip2_flush_reg); + do_IRQ(ATH79_CPU_IRQ_IP2); + } + + else if (pending & STATUSF_IP4) + do_IRQ(ATH79_CPU_IRQ_GE0); + + else if (pending & STATUSF_IP5) + do_IRQ(ATH79_CPU_IRQ_GE1); + + else if (pending & STATUSF_IP3) { + ath79_ddr_wb_flush(ath79_ip3_flush_reg); + do_IRQ(ATH79_CPU_IRQ_USB); + } + + else if (pending & STATUSF_IP6) + do_IRQ(ATH79_CPU_IRQ_MISC); + + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + if (soc_is_ar71xx()) { + ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; + ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; + } else if (soc_is_ar724x()) { + ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; + ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; + } else if (soc_is_ar913x()) { + ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; + ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; + } else + BUG(); + + cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + mips_cpu_irq_init(); + ath79_misc_irq_init(); +} diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c new file mode 100644 index 0000000..e9cbd7c --- /dev/null +++ b/arch/mips/ath79/prom.c @@ -0,0 +1,57 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific prom routines + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "common.h" + +static inline int is_valid_ram_addr(void *addr) +{ + if (((u32) addr > KSEG0) && + ((u32) addr < (KSEG0 + ATH79_MEM_SIZE_MAX))) + return 1; + + if (((u32) addr > KSEG1) && + ((u32) addr < (KSEG1 + ATH79_MEM_SIZE_MAX))) + return 1; + + return 0; +} + +static __init void ath79_prom_init_cmdline(int argc, char **argv) +{ + int i; + + if (!is_valid_ram_addr(argv)) + return; + + for (i = 0; i < argc; i++) + if (is_valid_ram_addr(argv[i])) { + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); + } +} + +void __init prom_init(void) +{ + ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); +} + +void __init prom_free_prom_memory(void) +{ + /* We do not have to prom memory to free */ +} diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c new file mode 100644 index 0000000..4157ddc --- /dev/null +++ b/arch/mips/ath79/setup.c @@ -0,0 +1,263 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific setup + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include /* for mips_hpt_frequency */ +#include /* for _machine_{restart,halt} */ + +#include +#include +#include "common.h" +#include "dev-common.h" + +#define ATH79_SYS_TYPE_LEN 64 + +#define AR71XX_BASE_FREQ 40000000 +#define AR724X_BASE_FREQ 5000000 +#define AR913X_BASE_FREQ 5000000 + +static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; + +static void ath79_restart(char *command) +{ + ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); + for (;;) + if (cpu_wait) + cpu_wait(); +} + +static void ath79_halt(void) +{ + while (1) + cpu_wait(); +} + +static void __init ath79_detect_mem_size(void) +{ + unsigned long size; + + for (size = ATH79_MEM_SIZE_MIN; size < ATH79_MEM_SIZE_MAX; + size <<= 1) { + if (!memcmp(ath79_detect_mem_size, + ath79_detect_mem_size + size, 1024)) + break; + } + + add_memory_region(0, size, BOOT_MEM_RAM); +} + +static void __init ath79_detect_sys_type(void) +{ + char *chip = "????"; + u32 id; + u32 major; + u32 minor; + u32 rev = 0; + + id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + ath79_soc = ATH79_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + ath79_soc = ATH79_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + ath79_soc = ATH79_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + ath79_soc = ATH79_SOC_AR7240; + chip = "7240"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7241: + ath79_soc = ATH79_SOC_AR7241; + chip = "7241"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7242: + ath79_soc = ATH79_SOC_AR7242; + chip = "7242"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; + rev &= AR913X_REV_ID_REVISION_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + ath79_soc = ATH79_SOC_AR9130; + chip = "9130"; + break; + + case AR913X_REV_ID_MINOR_AR9132: + ath79_soc = ATH79_SOC_AR9132; + chip = "9132"; + break; + } + break; + + default: + panic("ath79: unknown SoC, id:0x%08x\n", id); + } + + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); +} + +static void __init ar71xx_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; + freq = div * AR71XX_BASE_FREQ; + + div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; + ath79_cpu_freq = freq / div; + + div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ar724x_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * AR724X_BASE_FREQ; + + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); + freq *= div; + + ath79_cpu_freq = freq; + + div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ar913x_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); + freq = div * AR913X_BASE_FREQ; + + ath79_cpu_freq = freq; + + div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ath79_detect_sys_frequency(void) +{ + if (soc_is_ar71xx()) + ar71xx_detect_sys_frequency(); + else if (soc_is_ar724x()) + ar724x_detect_sys_frequency(); + else if (soc_is_ar913x()) + ar913x_detect_sys_frequency(); + else + BUG(); +} + +const char *get_system_type(void) +{ + return ath79_sys_type; +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(KSEG1); + + ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE); + ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, + AR71XX_PLL_SIZE); + + ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, + AR71XX_DDR_CTRL_SIZE); + + ath79_detect_sys_type(); + ath79_detect_mem_size(); + ath79_detect_sys_frequency(); + + pr_info("SoC: %s, CPU:%u.%03u MHz, DDR:%u.%03u MHz, AHB:%u.%03u MHz\n", + ath79_sys_type, + ath79_cpu_freq / 1000000, (ath79_cpu_freq / 1000) % 1000, + ath79_ddr_freq / 1000000, (ath79_ddr_freq / 1000) % 1000, + ath79_ahb_freq / 1000000, (ath79_ahb_freq / 1000) % 1000); + + _machine_restart = ath79_restart; + _machine_halt = ath79_halt; + pm_power_off = ath79_halt; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = ath79_cpu_freq / 2; +} + +static int __init ath79_setup(void) +{ + ath79_register_uart(); + return 0; +} + +arch_initcall(ath79_setup); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h new file mode 100644 index 0000000..5a9e5e1 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -0,0 +1,207 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#include +#include +#include +#include + +#define AR71XX_APB_BASE 0x18000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_OHCI_DLL BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +#endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h new file mode 100644 index 0000000..34fa294 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -0,0 +1,100 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include +#include + +extern u32 ath79_ahb_freq; +extern u32 ath79_cpu_freq; +extern u32 ath79_ddr_freq; + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132 +}; + +extern enum ath79_soc_type ath79_soc; + +static inline int soc_is_ar71xx(void) +{ + return (ath79_soc == ATH79_SOC_AR7130 || + ath79_soc == ATH79_SOC_AR7141 || + ath79_soc == ATH79_SOC_AR7161); +} + +static inline int soc_is_ar724x(void) +{ + return (ath79_soc == ATH79_SOC_AR7240 || + ath79_soc == ATH79_SOC_AR7241 || + ath79_soc == ATH79_SOC_AR7242); +} + +static inline int soc_is_ar7240(void) +{ + return (ath79_soc == ATH79_SOC_AR7240); +} + +static inline int soc_is_ar7241(void) +{ + return (ath79_soc == ATH79_SOC_AR7241); +} + +static inline int soc_is_ar7242(void) +{ + return (ath79_soc == ATH79_SOC_AR7242); +} + +static inline int soc_is_ar913x(void) +{ + return (ath79_soc == ATH79_SOC_AR9130 || + ath79_soc == ATH79_SOC_AR9132); +} + +extern void __iomem *ath79_ddr_base; +extern void __iomem *ath79_pll_base; +extern void __iomem *ath79_reset_base; + +static inline void ath79_pll_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ath79_pll_base + reg); +} + +static inline u32 ath79_pll_rr(unsigned reg) +{ + return __raw_readl(ath79_pll_base + reg); +} + +static inline void ath79_reset_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ath79_reset_base + reg); +} + +static inline u32 ath79_reset_rr(unsigned reg) +{ + return __raw_readl(ath79_reset_base + reg); +} + +void ath79_device_reset_set(u32 mask); +void ath79_device_reset_clear(u32 mask); + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h new file mode 100644 index 0000000..4476fa0 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific CPU feature overrides + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h new file mode 100644 index 0000000..189bc6e --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_ATH79_IRQ_H +#define __ASM_MACH_ATH79_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 16 + +#define ATH79_MISC_IRQ_BASE 8 +#define ATH79_MISC_IRQ_COUNT 8 + +#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) +#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) +#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) +#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) +#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) +#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7) + +#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) +#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) +#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) +#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3) +#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4) +#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) +#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) +#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) + +#include_next + +#endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h new file mode 100644 index 0000000..d8d046b --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h @@ -0,0 +1,32 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific kernel entry setup + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ATH79_KERNEL_ENTRY_H +#define __ASM_MACH_ATH79_KERNEL_ENTRY_H + + /* + * Some bootloaders set the 'Kseg0 coherency algorithm' to + * 'Cacheable, noncoherent, write-through, no write allocate' + * and this cause performance issues. Let's go and change it to + * 'Cacheable, noncoherent, write-back, write allocate' + */ + .macro kernel_entry_setup + mfc0 t0, CP0_CONFIG + li t1, ~CONF_CM_CMASK + and t0, t1 + ori t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + nop + .endm + + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_ATH79_KERNEL_ENTRY_H */ diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h new file mode 100644 index 0000000..323d9f1 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_ATH79_WAR_H +#define __ASM_MACH_ATH79_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_ATH79_WAR_H */ -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:32:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:32:43 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37489 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491065Ab0LVUbX (ORCPT ); Wed, 22 Dec 2010 21:31:23 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 3C34D80F3; Wed, 22 Dec 2010 21:31:18 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id B68611F0001; Wed, 22 Dec 2010 21:31:17 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 03/16] MIPS: ath79: utilize the MIPS multi-machine support Date: Wed, 22 Dec 2010 21:30:48 +0100 Message-Id: <1293049861-28913-4-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F2C13FE7 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28686 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 2388 Lines: 95 Signed-off-by: Gabor Juhos --- Changes since RFC: --- Changes since v1: - rebased against 2.6.37-rc7 arch/mips/Kconfig | 1 + arch/mips/ath79/machtypes.h | 21 +++++++++++++++++++++ arch/mips/ath79/setup.c | 15 +++++++++++++++ 3 files changed, 37 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/machtypes.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c3270a4..feb8de4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -73,6 +73,7 @@ config ATH79 select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU + select MIPS_MACHINE select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h new file mode 100644 index 0000000..fac0e26 --- /dev/null +++ b/arch/mips/ath79/machtypes.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71XX/AR724X/AR913X machine type definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_MACHTYPE_H +#define _ATH79_MACHTYPE_H + +#include + +enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, +}; + +#endif /* _ATH79_MACHTYPE_H */ diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 83dd855..5f2b6de 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -18,11 +18,13 @@ #include #include /* for mips_hpt_frequency */ #include /* for _machine_{restart,halt} */ +#include #include #include #include "common.h" #include "dev-common.h" +#include "machtypes.h" #define ATH79_SYS_TYPE_LEN 64 @@ -257,7 +259,20 @@ static int __init ath79_setup(void) { ath79_gpio_init(); ath79_register_uart(); + + mips_machine_setup(); + return 0; } arch_initcall(ath79_setup); + +static void __init ath79_generic_init(void) +{ + /* Nothing to do */ +} + +MIPS_MACHINE(ATH79_MACH_GENERIC, + "Generic", + "Generic AR71XX/AR724X/AR913X based board", + ath79_generic_init); -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:33:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:33:06 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37494 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491067Ab0LVUbX (ORCPT ); Wed, 22 Dec 2010 21:31:23 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id B9F4D80F4; Wed, 22 Dec 2010 21:31:18 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 248BC1F0001; Wed, 22 Dec 2010 21:31:18 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 04/16] MIPS: ath79: add initial support for the Atheros PB44 reference board Date: Wed, 22 Dec 2010 21:30:49 +0100 Message-Id: <1293049861-28913-5-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F328F7B6 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28687 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 3233 Lines: 127 Signed-off-by: Gabor Juhos --- Changes since RFC: - don't use 'default n' for the ATH79_MACH_PB44 Kconfig option Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 11 ++++++++ arch/mips/ath79/Makefile | 5 ++++ arch/mips/ath79/mach-pb44.c | 56 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 73 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/mach-pb44.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 50b9334..fabb2b0 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -1,5 +1,16 @@ if ATH79 +menu "Atheros AR71XX/AR724X/AR913X machine selection" + +config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX + help + Say 'Y' here if you want your kernel to support the + Atheros PB44 reference board. + +endmenu + config SOC_AR71XX def_bool n diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index facbb70..a9ba120 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -16,3 +16,8 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o # Devices # obj-y += dev-common.o + +# +# Machines +# +obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c new file mode 100644 index 0000000..ffc24d7 --- /dev/null +++ b/arch/mips/ath79/mach-pb44.c @@ -0,0 +1,56 @@ +/* + * Atheros PB44 reference board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "machtypes.h" + +#define PB44_GPIO_I2C_SCL 0 +#define PB44_GPIO_I2C_SDA 1 + +#define PB44_GPIO_EXP_BASE 16 + +static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { + .sda_pin = PB44_GPIO_I2C_SDA, + .scl_pin = PB44_GPIO_I2C_SCL, +}; + +static struct platform_device pb44_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &pb44_i2c_gpio_data, + } +}; + +static struct pcf857x_platform_data pb44_pcf857x_data = { + .gpio_base = PB44_GPIO_EXP_BASE, +}; + +static struct i2c_board_info pb44_i2c_board_info[] __initdata = { + { + I2C_BOARD_INFO("pcf8575", 0x20), + .platform_data = &pb44_pcf857x_data, + }, +}; + +static void __init pb44_init(void) +{ + i2c_register_board_info(0, pb44_i2c_board_info, + ARRAY_SIZE(pb44_i2c_board_info)); + platform_device_register(&pb44_i2c_gpio_device); +} + +MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", + pb44_init); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index fac0e26..a796fa3 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -16,6 +16,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, + ATH79_MACH_PB44, /* Atheros PB44 reference board */ }; #endif /* _ATH79_MACHTYPE_H */ -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:33:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:33:29 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37531 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491086Ab0LVUb2 (ORCPT ); Wed, 22 Dec 2010 21:31:28 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id DB87080FD; Wed, 22 Dec 2010 21:31:19 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 287FC1F0001; Wed, 22 Dec 2010 21:31:19 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos , Wim Van Sebroeck , linux-watchdog@vger.kernel.org Subject: [PATCH v2 06/16] watchdog: add driver for the Atheros AR71XX/AR724X/AR913X SoCs Date: Wed, 22 Dec 2010 21:30:51 +0100 Message-Id: <1293049861-28913-7-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F3DA41BE | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28688 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 8731 Lines: 353 This patch adds a driver for the built-in hardware watchdog device of the Atheros AR71XX/AR724X/AR913X SoCs. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: Wim Van Sebroeck Cc: linux-watchdog@vger.kernel.org --- Changes since RFC: --- Changes since v1: - rebased against 2.6.37-rc7 drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ath79_wdt.c | 293 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 302 insertions(+), 0 deletions(-) create mode 100644 drivers/watchdog/ath79_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index a5ad77e..7833e44 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -930,6 +930,14 @@ config BCM63XX_WDT To compile this driver as a loadable module, choose M here. The module will be called bcm63xx_wdt. +config ATH79_WDT + tristate "Atheros AR71XX/AR724X/AR913X hardware watchdog" + depends on ATH79 + help + Hardware driver for the built-in watchdog timer on the Atheros + AR71XX/AR724X/AR913X SoCs. + + # PARISC Architecture # POWERPC Architecture diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 4b0ef38..6d7af07 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -117,6 +117,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o obj-$(CONFIG_AR7_WDT) += ar7_wdt.o obj-$(CONFIG_TXX9_WDT) += txx9wdt.o +obj-$(CONFIG_ATH79_WDT) += ath79_wdt.o obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o diff --git a/drivers/watchdog/ath79_wdt.c b/drivers/watchdog/ath79_wdt.c new file mode 100644 index 0000000..f8e027b --- /dev/null +++ b/drivers/watchdog/ath79_wdt.c @@ -0,0 +1,293 @@ +/* + * Atheros AR71XX/AR724X/AR913X built-in hardware watchdog timer. + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This driver was based on: drivers/watchdog/ixp4xx_wdt.c + * Author: Deepak Saxena + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * which again was based on sa1100 driver, + * Copyright (C) 2000 Oleg Drokin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "ath79-wdt" +#define DRIVER_DESC "Atheros AR71XX/AR724X/AR913X hardware watchdog driver" + +#define WDT_TIMEOUT 15 /* seconds */ + +#define WDOG_CTRL_LAST_RESET BIT(31) +#define WDOG_CTRL_ACTION_MASK 3 +#define WDOG_CTRL_ACTION_NONE 0 /* no action */ +#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ +#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ +#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ + +static int nowayout = WATCHDOG_NOWAYOUT; + +#ifdef CONFIG_WATCHDOG_NOWAYOUT +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " + "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +#endif + +static unsigned long wdt_flags; + +#define WDT_FLAGS_BUSY 0 +#define WDT_FLAGS_EXPECT_CLOSE 1 + +static int wdt_timeout = WDT_TIMEOUT; +static int boot_status; +static int max_timeout; + +static inline void ath79_wdt_keepalive(void) +{ + ath79_reset_wr(AR71XX_RESET_REG_WDOG, ath79_ahb_freq * wdt_timeout); +} + +static inline void ath79_wdt_enable(void) +{ + ath79_wdt_keepalive(); + ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); +} + +static inline void ath79_wdt_disable(void) +{ + ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); +} + +static int ath79_wdt_set_timeout(int val) +{ + if (val < 1 || val > max_timeout) + return -EINVAL; + + wdt_timeout = val; + ath79_wdt_keepalive(); + + return 0; +} + +static int ath79_wdt_open(struct inode *inode, struct file *file) +{ + if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags)) + return -EBUSY; + + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + ath79_wdt_enable(); + + return nonseekable_open(inode, file); +} + +static int ath79_wdt_release(struct inode *inode, struct file *file) +{ + if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags)) + ath79_wdt_disable(); + else + pr_crit(DRIVER_NAME ": device closed unexpectedly, " + "watchdog timer will not stop!\n"); + + clear_bit(WDT_FLAGS_BUSY, &wdt_flags); + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + + return 0; +} + +static ssize_t ath79_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) +{ + if (len) { + if (!nowayout) { + size_t i; + + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + + for (i = 0; i != len; i++) { + char c; + + if (get_user(c, data + i)) + return -EFAULT; + + if (c == 'V') + set_bit(WDT_FLAGS_EXPECT_CLOSE, + &wdt_flags); + } + } + + ath79_wdt_keepalive(); + } + + return len; +} + +static const struct watchdog_info ath79_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE | WDIOF_CARDRESET, + .firmware_version = 0, + .identity = "ATH79 watchdog", +}; + +static long ath79_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + void __user *argp = (void __user *)arg; + int __user *p = argp; + int err; + int t; + + switch (cmd) { + case WDIOC_GETSUPPORT: + err = copy_to_user(argp, &ath79_wdt_info, + sizeof(ath79_wdt_info)) ? -EFAULT : 0; + break; + + case WDIOC_GETSTATUS: + err = put_user(0, p); + break; + + case WDIOC_GETBOOTSTATUS: + err = put_user(boot_status, p); + break; + + case WDIOC_KEEPALIVE: + ath79_wdt_keepalive(); + err = 0; + break; + + case WDIOC_SETTIMEOUT: + err = get_user(t, p); + if (err) + break; + + err = ath79_wdt_set_timeout(t); + if (err) + break; + + /* fallthrough */ + case WDIOC_GETTIMEOUT: + err = put_user(wdt_timeout, p); + break; + + default: + err = -ENOTTY; + break; + } + + return err; +} + +static const struct file_operations ath79_wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = ath79_wdt_write, + .unlocked_ioctl = ath79_wdt_ioctl, + .open = ath79_wdt_open, + .release = ath79_wdt_release, +}; + +static int ath79_wdt_notify_sys(struct notifier_block *this, + unsigned long code, void *unused) +{ + if (code == SYS_DOWN || code == SYS_HALT) + ath79_wdt_disable(); + + return NOTIFY_DONE; +} + +static struct notifier_block ath79_wdt_notifier = { + .notifier_call = ath79_wdt_notify_sys, +}; + +static struct miscdevice ath79_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &ath79_wdt_fops, +}; + +static int __init ath79_wdt_probe(struct platform_device *pdev) +{ + u32 ctrl; + int err; + + max_timeout = (0xfffffffful / ath79_ahb_freq); + wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; + + ctrl = ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL); + boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0; + + err = register_reboot_notifier(&ath79_wdt_notifier); + if (err) { + dev_err(&pdev->dev, + "unable to register reboot notifier, err=%d\n", err); + goto err; + } + + err = misc_register(&ath79_wdt_miscdev); + if (err) { + dev_err(&pdev->dev, + "unable to register misc device, err=%d\n", err); + goto err_unregister; + } + + return 0; + +err_unregister: + unregister_reboot_notifier(&ath79_wdt_notifier); + +err: + return err; +} + +static int __exit ath79_wdt_remove(struct platform_device *pdev) +{ + misc_deregister(&ath79_wdt_miscdev); + return 0; +} + +static struct platform_driver ath79_wdt_driver = { + .remove = __exit_p(ath79_wdt_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ath79_wdt_init(void) +{ + return platform_driver_probe(&ath79_wdt_driver, ath79_wdt_probe); +} +module_init(ath79_wdt_init); + +static void __exit ath79_wdt_exit(void) +{ + platform_driver_unregister(&ath79_wdt_driver); +} +module_exit(ath79_wdt_exit); + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_AUTHOR("Gabor Juhos ); Wed, 22 Dec 2010 21:31:28 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 4BF6980F5; Wed, 22 Dec 2010 21:31:19 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id A1A081F0001; Wed, 22 Dec 2010 21:31:18 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 05/16] MIPS: ath79: add common GPIO LEDs device Date: Wed, 22 Dec 2010 21:30:50 +0100 Message-Id: <1293049861-28913-6-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F381D1FB | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28689 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 5243 Lines: 193 Almost all boards have one or more LEDs connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the LEDs on the PB44 board. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- Changes since RFC: --- Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 4 +++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-leds-gpio.c | 56 +++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/dev-leds-gpio.h | 21 ++++++++++++++ arch/mips/ath79/mach-pb44.c | 18 ++++++++++++ 5 files changed, 100 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-leds-gpio.c create mode 100644 arch/mips/ath79/dev-leds-gpio.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index fabb2b0..5bc480e 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -5,6 +5,7 @@ menu "Atheros AR71XX/AR724X/AR913X machine selection" config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX + select ATH79_DEV_LEDS_GPIO help Say 'Y' here if you want your kernel to support the Atheros PB44 reference board. @@ -20,4 +21,7 @@ config SOC_AR724X config SOC_AR913X def_bool n +config ATH79_DEV_LEDS_GPIO + def_bool n + endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index a9ba120..d14b597 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o # Devices # obj-y += dev-common.o +obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o # # Machines diff --git a/arch/mips/ath79/dev-leds-gpio.c b/arch/mips/ath79/dev-leds-gpio.c new file mode 100644 index 0000000..cdade68 --- /dev/null +++ b/arch/mips/ath79/dev-leds-gpio.c @@ -0,0 +1,56 @@ +/* + * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include "dev-leds-gpio.h" + +void __init ath79_register_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds) +{ + struct platform_device *pdev; + struct gpio_led_platform_data pdata; + struct gpio_led *p; + int err; + + p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, leds, num_leds * sizeof(*p)); + + pdev = platform_device_alloc("leds-gpio", id); + if (!pdev) + goto err_free_leds; + + memset(&pdata, 0, sizeof(pdata)); + pdata.num_leds = num_leds; + pdata.leds = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_leds: + kfree(p); +} diff --git a/arch/mips/ath79/dev-leds-gpio.h b/arch/mips/ath79/dev-leds-gpio.h new file mode 100644 index 0000000..0fb0ed1 --- /dev/null +++ b/arch/mips/ath79/dev-leds-gpio.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_LEDS_GPIO_H +#define _ATH79_DEV_LEDS_GPIO_H + +#include + +void ath79_register_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds) __init; + +#endif /* _ATH79_DEV_LEDS_GPIO_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index ffc24d7..e176779 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -15,11 +15,14 @@ #include #include "machtypes.h" +#include "dev-leds-gpio.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 #define PB44_GPIO_EXP_BASE 16 +#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) +#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { .sda_pin = PB44_GPIO_I2C_SDA, @@ -45,11 +48,26 @@ static struct i2c_board_info pb44_i2c_board_info[] __initdata = { }, }; +static struct gpio_led pb44_leds_gpio[] __initdata = { + { + .name = "pb44:amber:jump1", + .gpio = PB44_GPIO_LED_JUMP1, + .active_low = 1, + }, { + .name = "pb44:green:jump2", + .gpio = PB44_GPIO_LED_JUMP2, + .active_low = 1, + }, +}; + static void __init pb44_init(void) { i2c_register_board_info(0, pb44_i2c_board_info, ARRAY_SIZE(pb44_i2c_board_info)); platform_device_register(&pb44_i2c_gpio_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), + pb44_leds_gpio); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:34:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:34:17 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37531 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491088Ab0LVUb2 (ORCPT ); Wed, 22 Dec 2010 21:31:28 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id D27AD8103; Wed, 22 Dec 2010 21:31:26 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 3BC951F0001; Wed, 22 Dec 2010 21:31:26 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 16/16] MIPS: ath79: add common WMAC device for AR913X based boards Date: Wed, 22 Dec 2010 21:31:01 +0100 Message-Id: <1293049861-28913-17-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F79A3AC2 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28690 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 6148 Lines: 201 Add common platform_device and helper code to make the registration of the built-in wireless MAC easier on the Atheros AR9130/AR9132 based boards. Also register the WMAC device on the AR81 board. Signed-off-by: Gabor Juhos --- Changes since RFC: --- Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 5 ++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-ar913x-wmac.c | 60 ++++++++++++++++++++++++ arch/mips/ath79/dev-ar913x-wmac.h | 17 +++++++ arch/mips/ath79/mach-ap81.c | 6 ++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 + 6 files changed, 92 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-ar913x-wmac.c create mode 100644 arch/mips/ath79/dev-ar913x-wmac.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 1912d54..af01669 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -5,6 +5,7 @@ menu "Atheros AR71XX/AR724X/AR913X machine selection" config ATH79_MACH_AP81 bool "Atheros AP81 reference board" select SOC_AR913X + select ATH79_DEV_AR913X_WMAC select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO select ATH79_DEV_SPI @@ -40,6 +41,10 @@ config SOC_AR913X select USB_ARCH_HAS_EHCI def_bool n +config ATH79_DEV_AR913X_WMAC + depends on SOC_AR913X + def_bool n + config ATH79_DEV_GPIO_BUTTONS def_bool n diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 1b111d8..48398561 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o # Devices # obj-y += dev-common.o +obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c new file mode 100644 index 0000000..48f425a --- /dev/null +++ b/arch/mips/ath79/dev-ar913x-wmac.c @@ -0,0 +1,60 @@ +/* + * Atheros AR913X SoC built-in WMAC device support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include "dev-ar913x-wmac.h" + +static struct ath9k_platform_data ar913x_wmac_data; + +static struct resource ar913x_wmac_resources[] = { + { + .start = AR913X_WMAC_BASE, + .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = ATH79_CPU_IRQ_IP2, + .end = ATH79_CPU_IRQ_IP2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ar913x_wmac_device = { + .name = "ath9k", + .id = -1, + .resource = ar913x_wmac_resources, + .num_resources = ARRAY_SIZE(ar913x_wmac_resources), + .dev = { + .platform_data = &ar913x_wmac_data, + }, +}; + +void __init ath79_register_ar913x_wmac(u8 *cal_data) +{ + if (cal_data) + memcpy(ar913x_wmac_data.eeprom_data, cal_data, + sizeof(ar913x_wmac_data.eeprom_data)); + + /* reset the WMAC */ + ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); + mdelay(10); + + ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); + mdelay(10); + + platform_device_register(&ar913x_wmac_device); +} diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-ar913x-wmac.h new file mode 100644 index 0000000..5df653f --- /dev/null +++ b/arch/mips/ath79/dev-ar913x-wmac.h @@ -0,0 +1,17 @@ +/* + * Atheros AR913X SoC built-in WMAC device support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_AR913X_WMAC_H +#define _ATH79_DEV_AR913X_WMAC_H + +void ath79_register_ar913x_wmac(u8 *cal_data) __init; + +#endif /* _ATH79_DEV_AR913X_WMAC_H */ diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c index 909ca5d..03719b8 100644 --- a/arch/mips/ath79/mach-ap81.c +++ b/arch/mips/ath79/mach-ap81.c @@ -10,6 +10,7 @@ */ #include "machtypes.h" +#include "dev-ar913x-wmac.h" #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" @@ -26,6 +27,8 @@ #define AP81_KEYS_POLL_INTERVAL 20 /* msecs */ #define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL) +#define AP81_CAL_DATA_ADDR 0x1fff1000 + static struct gpio_led ap81_leds_gpio[] __initdata = { { .name = "ap81:green:status", @@ -80,6 +83,8 @@ static struct ath79_spi_platform_data ap81_spi_data = { static void __init ap81_setup(void) { + u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), ap81_leds_gpio); ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, @@ -88,6 +93,7 @@ static void __init ap81_setup(void) ath79_register_spi(&ap81_spi_data, ap81_spi_info, ARRAY_SIZE(ap81_spi_info)); ath79_register_usb(); + ath79_register_ar913x_wmac(cal_data); } MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index f125f1e..9beb073 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -43,6 +43,9 @@ #define AR7240_OHCI_BASE 0x1b000000 #define AR7240_OHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + /* * DDR_CTRL block */ -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:34:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:34:41 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37534 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491094Ab0LVUb2 (ORCPT ); Wed, 22 Dec 2010 21:31:28 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 76F9A8100; Wed, 22 Dec 2010 21:31:22 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 9066B1F0001; Wed, 22 Dec 2010 21:31:21 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos , David Brownell , spi-devel-general@lists.sourceforge.net Subject: [PATCH v2 09/16] spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs Date: Wed, 22 Dec 2010 21:30:54 +0100 Message-Id: <1293049861-28913-10-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F4B39E59 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28691 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 10190 Lines: 384 The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This patch implements a driver for that. Signed-off-by: Gabor Juhos Cc: David Brownell Cc: spi-devel-general@lists.sourceforge.net --- Changes since RFC: - remove DRV_DESC definition and use its previous value directly in the MODULE_DESCRIPTION() macro, - use io{read,write}32 accesors instead of __raw_{read,write}l, - use __dev{init,exit,exit_p} annotations where in the appropriate places, - initialize 'master->bus_num' field to -1 if no platform data specified, so that a bus number can be dynamically assigned, - rename ath79_spi_drv to ath79_spi_driver to avoid section mismatch warnings Changes since v1: - rebased against 2.6.37-rc7 .../include/asm/mach-ath79/ath79_spi_platform.h | 19 ++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 290 ++++++++++++++++++++ 4 files changed, 318 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h create mode 100644 drivers/spi/ath79_spi.c diff --git a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h new file mode 100644 index 0000000..aa71216 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h @@ -0,0 +1,19 @@ +/* + * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller + * + * Copyright (C) 2008-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_SPI_PLATFORM_H +#define _ATH79_SPI_PLATFORM_H + +struct ath79_spi_platform_data { + unsigned bus_num; + unsigned num_chipselect; +}; + +#endif /* _ATH79_SPI_PLATFORM_H */ diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 78f9fd0..f2093e1 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -53,6 +53,14 @@ if SPI_MASTER comment "SPI Master Controller Drivers" +config SPI_ATH79 + tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver" + depends on ATH79 && GENERIC_GPIO + select SPI_BITBANG + help + This enables support for the SPI controller present on the + Atheros AR71XX/AR724X/AR913X SoCs. + config SPI_ATMEL tristate "Atmel SPI Controller" depends on (ARCH_AT91 || AVR32) diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8bc1a5a..875bc3d 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SPI_MASTER) += spi.o # SPI master controller drivers (bus) obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o +obj-$(CONFIG_SPI_ATH79) += ath79_spi.o obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o obj-$(CONFIG_SPI_AU1550) += au1550_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..96f169a --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,290 @@ +/* + * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This driver has been based on the spi-gpio.c: + * Copyright (C) 2006,2008 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_NAME "ath79-spi" + +struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; + u32 reg_ctrl; + + void __iomem *base; + + struct platform_device *pdev; +}; + +static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) +{ + return ioread32(sp->base + reg); +} + +static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) +{ + iowrite32(val, sp->base + reg); +} + +static inline struct ath79_spi *spidev_to_sp(struct spi_device *spi) +{ + return spi_master_get_devdata(spi->master); +} + +static void ath79_spi_chipselect(struct spi_device *spi, int is_active) +{ + struct ath79_spi *sp = spidev_to_sp(spi); + int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; + + if (is_active) { + /* set initial clock polarity */ + if (spi->mode & SPI_CPOL) + sp->ioc_base |= AR71XX_SPI_IOC_CLK; + else + sp->ioc_base &= ~AR71XX_SPI_IOC_CLK; + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + + if (spi->chip_select) { + unsigned long gpio = (unsigned long) spi->controller_data; + + /* SPI is normally active-low */ + gpio_set_value(gpio, cs_high); + } else { + if (cs_high) + sp->ioc_base |= AR71XX_SPI_IOC_CS0; + else + sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + +} + +static int ath79_spi_setup_cs(struct spi_device *spi) +{ + struct ath79_spi *sp = spidev_to_sp(spi); + + /* enable GPIO mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); + + /* save CTRL register */ + sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); + sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); + + /* TODO: setup speed? */ + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + + if (spi->chip_select) { + unsigned long gpio = (unsigned long) spi->controller_data; + int status = 0; + + status = gpio_request(gpio, dev_name(&spi->dev)); + if (status) + return status; + + status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); + if (status) { + gpio_free(gpio); + return status; + } + } else { + if (spi->mode & SPI_CS_HIGH) + sp->ioc_base |= AR71XX_SPI_IOC_CS0; + else + sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + + return 0; +} + +static void ath79_spi_cleanup_cs(struct spi_device *spi) +{ + struct ath79_spi *sp = spidev_to_sp(spi); + + if (spi->chip_select) { + unsigned long gpio = (unsigned long) spi->controller_data; + gpio_free(gpio); + } + + /* restore CTRL register */ + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); + /* disable GPIO mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); +} + +static int ath79_spi_setup(struct spi_device *spi) +{ + int status = 0; + + if (spi->bits_per_word > 32) + return -EINVAL; + + if (!spi->controller_state) { + status = ath79_spi_setup_cs(spi); + if (status) + return status; + } + + status = spi_bitbang_setup(spi); + if (status && !spi->controller_state) + ath79_spi_cleanup_cs(spi); + + return status; +} + +static void ath79_spi_cleanup(struct spi_device *spi) +{ + ath79_spi_cleanup_cs(spi); + spi_bitbang_cleanup(spi); +} + +static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, + u32 word, u8 bits) +{ + struct ath79_spi *sp = spidev_to_sp(spi); + u32 ioc = sp->ioc_base; + + /* clock starts at inactive polarity */ + for (word <<= (32 - bits); likely(bits); bits--) { + u32 out; + + if (word & (1 << 31)) + out = ioc | AR71XX_SPI_IOC_DO; + else + out = ioc & ~AR71XX_SPI_IOC_DO; + + /* setup MSB (to slave) on trailing edge */ + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); + + word <<= 1; + } + + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); +} + +static __devinit int ath79_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct ath79_spi *sp; + struct ath79_spi_platform_data *pdata; + struct resource *r; + int ret; + + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); + return -ENOMEM; + } + + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + + pdata = pdev->dev.platform_data; + + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; + if (pdata) { + master->bus_num = pdata->bus_num; + master->num_chipselect = pdata->num_chipselect; + } else { + master->bus_num = -1; + master->num_chipselect = 1; + } + + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = ath79_spi_chipselect; + sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; + sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; + sp->bitbang.flags = SPI_CS_HIGH; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + ret = -ENOENT; + goto err_put_master; + } + + sp->base = ioremap(r->start, r->end - r->start + 1); + if (!sp->base) { + ret = -ENXIO; + goto err_put_master; + } + + ret = spi_bitbang_start(&sp->bitbang); + if (ret) + goto err_unmap; + + return 0; + +err_unmap: + iounmap(sp->base); +err_put_master: + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + + return ret; +} + +static __devexit int ath79_spi_remove(struct platform_device *pdev) +{ + struct ath79_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + + return 0; +} + +static struct platform_driver ath79_spi_driver = { + .probe = ath79_spi_probe, + .remove = __devexit_p(ath79_spi_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static __init int ath79_spi_init(void) +{ + return platform_driver_register(&ath79_spi_driver); +} +module_init(ath79_spi_init); + +static __exit void ath79_spi_exit(void) +{ + platform_driver_unregister(&ath79_spi_driver); +} +module_exit(ath79_spi_exit); + +MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR91X"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:34:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:35:05 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37535 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491096Ab0LVUb2 (ORCPT ); Wed, 22 Dec 2010 21:31:28 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id E07AE8101; Wed, 22 Dec 2010 21:31:22 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 412801F0001; Wed, 22 Dec 2010 21:31:22 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 10/16] MIPS: ath79: add common SPI controller device Date: Wed, 22 Dec 2010 21:30:55 +0100 Message-Id: <1293049861-28913-11-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F4FB0711 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28692 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 5634 Lines: 185 Several boards are using the built-in SPI controller of the AR71XX/AR724X/AR913X SoCs. This patch adds common platform_device and helper code to register it. Additionally, the patch registers the SPI bus on the PB44 board. Signed-off-by: Gabor Juhos --- Changes since RFC: --- Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 4 ++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-spi.c | 38 ++++++++++++++++++++++++ arch/mips/ath79/dev-spi.h | 22 ++++++++++++++ arch/mips/ath79/mach-pb44.c | 17 ++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 + 6 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-spi.c create mode 100644 arch/mips/ath79/dev-spi.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 185a8d6..cd6c738 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -7,6 +7,7 @@ config ATH79_MACH_PB44 select SOC_AR71XX select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI help Say 'Y' here if you want your kernel to support the Atheros PB44 reference board. @@ -28,4 +29,7 @@ config ATH79_DEV_GPIO_BUTTONS config ATH79_DEV_LEDS_GPIO def_bool n +config ATH79_DEV_SPI + def_bool n + endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 0ceb45e..a8de078 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += dev-common.o obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o +obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o # # Machines diff --git a/arch/mips/ath79/dev-spi.c b/arch/mips/ath79/dev-spi.c new file mode 100644 index 0000000..aa30163 --- /dev/null +++ b/arch/mips/ath79/dev-spi.c @@ -0,0 +1,38 @@ +/* + * Atheros AR71XX/AR724X/AR913X SPI controller device + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "dev-spi.h" + +static struct resource ath79_spi_resources[] = { + { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ath79_spi_device = { + .name = "ath79-spi", + .id = -1, + .resource = ath79_spi_resources, + .num_resources = ARRAY_SIZE(ath79_spi_resources), +}; + +void __init ath79_register_spi(struct ath79_spi_platform_data *pdata, + struct spi_board_info const *info, + unsigned n) +{ + spi_register_board_info(info, n); + ath79_spi_device.dev.platform_data = pdata; + platform_device_register(&ath79_spi_device); +} diff --git a/arch/mips/ath79/dev-spi.h b/arch/mips/ath79/dev-spi.h new file mode 100644 index 0000000..9a98333 --- /dev/null +++ b/arch/mips/ath79/dev-spi.h @@ -0,0 +1,22 @@ +/* + * Atheros AR71XX/AR724X/AR913X SPI controller device + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_SPI_H +#define _ATH79_DEV_SPI_H + +#include +#include + +void __init ath79_register_spi(struct ath79_spi_platform_data *pdata, + struct spi_board_info const *info, + unsigned n); + +#endif /* _ATH79_DEV_SPI_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index 3dc5080..ec7b7a1 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -17,6 +17,7 @@ #include "machtypes.h" #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" +#include "dev-spi.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 @@ -84,6 +85,20 @@ static struct gpio_keys_button pb44_gpio_keys[] __initdata = { } }; +static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", + }, +}; + +static struct ath79_spi_platform_data pb44_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + static void __init pb44_init(void) { i2c_register_board_info(0, pb44_i2c_board_info, @@ -95,6 +110,8 @@ static void __init pb44_init(void) ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL, ARRAY_SIZE(pb44_gpio_keys), pb44_gpio_keys); + ath79_register_spi(&pb44_spi_data, pb44_spi_info, + ARRAY_SIZE(pb44_spi_info)); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 7f2933d..4f2b621 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -20,6 +20,8 @@ #include #define AR71XX_APB_BASE 0x18000000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) #define AR71XX_DDR_CTRL_SIZE 0x100 -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:35:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:35:30 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37533 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491087Ab0LVUb2 (ORCPT ); Wed, 22 Dec 2010 21:31:28 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id B08F580FF; Wed, 22 Dec 2010 21:31:21 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 3694B1F0001; Wed, 22 Dec 2010 21:31:20 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 08/16] MIPS: ath79: add common GPIO buttons device Date: Wed, 22 Dec 2010 21:30:53 +0100 Message-Id: <1293049861-28913-9-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F477F8D0 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28693 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 6189 Lines: 216 Almost all boards have one or more push buttons connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the buttons on the PB44 board. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- Changes since RFC: --- Changes since v1: - converted to use the gpio_keys_polled driver - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 4 ++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-gpio-buttons.c | 58 ++++++++++++++++++++++++++++++++++++ arch/mips/ath79/dev-gpio-buttons.h | 23 ++++++++++++++ arch/mips/ath79/mach-pb44.c | 27 ++++++++++++++++ 5 files changed, 113 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-gpio-buttons.c create mode 100644 arch/mips/ath79/dev-gpio-buttons.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 5bc480e..185a8d6 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -5,6 +5,7 @@ menu "Atheros AR71XX/AR724X/AR913X machine selection" config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX + select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO help Say 'Y' here if you want your kernel to support the @@ -21,6 +22,9 @@ config SOC_AR724X config SOC_AR913X def_bool n +config ATH79_DEV_GPIO_BUTTONS + def_bool n + config ATH79_DEV_LEDS_GPIO def_bool n diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index d14b597..0ceb45e 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o # Devices # obj-y += dev-common.o +obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o # diff --git a/arch/mips/ath79/dev-gpio-buttons.c b/arch/mips/ath79/dev-gpio-buttons.c new file mode 100644 index 0000000..4b0168a --- /dev/null +++ b/arch/mips/ath79/dev-gpio-buttons.c @@ -0,0 +1,58 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO button support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "linux/init.h" +#include "linux/slab.h" +#include + +#include "dev-gpio-buttons.h" + +void __init ath79_register_gpio_keys_polled(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons) +{ + struct platform_device *pdev; + struct gpio_keys_platform_data pdata; + struct gpio_keys_button *p; + int err; + + p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, buttons, nbuttons * sizeof(*p)); + + pdev = platform_device_alloc("gpio-keys-polled", id); + if (!pdev) + goto err_free_buttons; + + memset(&pdata, 0, sizeof(pdata)); + pdata.poll_interval = poll_interval; + pdata.nbuttons = nbuttons; + pdata.buttons = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_buttons: + kfree(p); +} diff --git a/arch/mips/ath79/dev-gpio-buttons.h b/arch/mips/ath79/dev-gpio-buttons.h new file mode 100644 index 0000000..51783af --- /dev/null +++ b/arch/mips/ath79/dev-gpio-buttons.h @@ -0,0 +1,23 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO button support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_GPIO_BUTTONS_H +#define _ATH79_DEV_GPIO_BUTTONS_H + +#include +#include + +void ath79_register_gpio_keys_polled(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons) __init; + +#endif /* _ATH79_DEV_GPIO_BUTTONS_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index e176779..3dc5080 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -15,15 +15,21 @@ #include #include "machtypes.h" +#include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 #define PB44_GPIO_EXP_BASE 16 +#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) +#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) #define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) +#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */ +#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL) + static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { .sda_pin = PB44_GPIO_I2C_SDA, .scl_pin = PB44_GPIO_I2C_SCL, @@ -60,6 +66,24 @@ static struct gpio_led pb44_leds_gpio[] __initdata = { }, }; +static struct gpio_keys_button pb44_gpio_keys[] __initdata = { + { + .desc = "soft_reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB44_GPIO_SW_RESET, + .active_low = 1, + } , { + .desc = "jumpstart", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB44_GPIO_SW_JUMP, + .active_low = 1, + } +}; + static void __init pb44_init(void) { i2c_register_board_info(0, pb44_i2c_board_info, @@ -68,6 +92,9 @@ static void __init pb44_init(void) ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), pb44_leds_gpio); + ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pb44_gpio_keys), + pb44_gpio_keys); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:35:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:35:53 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37532 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491089Ab0LVUb2 (ORCPT ); Wed, 22 Dec 2010 21:31:28 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 4CF6080FE; Wed, 22 Dec 2010 21:31:20 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id B801D1F0001; Wed, 22 Dec 2010 21:31:19 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 07/16] MIPS: ath79: add common watchdog device Date: Wed, 22 Dec 2010 21:30:52 +0100 Message-Id: <1293049861-28913-8-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F432403D | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28694 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 1764 Lines: 63 All supported SoCs have a built-in hardware watchdog driver. This patch registers a platform_device for that to make it usable. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- Changes since RFC: - remove the ATH79_DEV_WDT Kconfig option, and move the watchdog platform code into dev-common.[ch] Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/dev-common.c | 10 ++++++++++ arch/mips/ath79/dev-common.h | 1 + arch/mips/ath79/setup.c | 1 + 3 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c index 897522c..74b1e3b 100644 --- a/arch/mips/ath79/dev-common.c +++ b/arch/mips/ath79/dev-common.c @@ -57,3 +57,13 @@ void __init ath79_register_uart(void) ath79_uart_data[0].uartclk = ath79_ahb_freq; platform_device_register(&ath79_uart_device); } + +static struct platform_device ath79_wdt_device = { + .name = "ath79-wdt", + .id = -1, +}; + +void __init ath79_register_wdt(void) +{ + platform_device_register(&ath79_wdt_device); +} diff --git a/arch/mips/ath79/dev-common.h b/arch/mips/ath79/dev-common.h index 1cec894..65bf400 100644 --- a/arch/mips/ath79/dev-common.h +++ b/arch/mips/ath79/dev-common.h @@ -13,5 +13,6 @@ #define _ATH79_DEV_COMMON_H void ath79_register_uart(void) __init; +void ath79_register_wdt(void) __init; #endif /* _ATH79_DEV_COMMON_H */ diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 5f2b6de..ef4207f 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -259,6 +259,7 @@ static int __init ath79_setup(void) { ath79_gpio_init(); ath79_register_uart(); + ath79_register_wdt(); mips_machine_setup(); -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:36:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:36:17 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37540 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491098Ab0LVUb2 (ORCPT ); Wed, 22 Dec 2010 21:31:28 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id B674C80EC; Wed, 22 Dec 2010 21:31:23 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id BF40A1F0001; Wed, 22 Dec 2010 21:31:22 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos , David Brownell , Greg Kroah-Hartman , linux-usb@vger.kernel.org Subject: [PATCH v2 11/16] USB: ehci: add workaround for Synopsys HC bug Date: Wed, 22 Dec 2010 21:30:56 +0100 Message-Id: <1293049861-28913-12-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F5977879 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28695 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 3229 Lines: 83 A Synopsys USB core used in various SoCs has a bug which might cause that the host controller not issuing ping. When software uses the Doorbell mechanism to remove queue heads, the host controller still has references to the removed queue head even after indicating an Interrupt on Async Advance. This happens if the last executed queue head's Next Link queue head is removed. Consequences of the defect: The Host controller fetches the removed queue head, using memory that would otherwise be deallocated.This results in incorrect transactions on both the USB and system memory. This may result in undefined behavior. Workarounds: 1) If no queue head is active (no Status field's Active bit is set) after removing the queue heads, the software can write one of the valid queue head addresses to the ASYNCLISTADDR register and deallocate the removed queue head's memory after 2 microframes. If one or more of the queue heads is active (the Active bit is set in the Status field) after removing the queue heads, the software can delay memory deallocation after time X, where X is the time required for the Host Controller to go through all the queue heads once. X varies with the number of queue heads and the time required to process periodic transactions: if more periodic transactions must be performed, the Host Controller has less time to process asynchronous transaction processing. 2) Do not use the Doorbell mechanism to remove the queue heads. Disable the Asynchronous Schedule Enable bit instead. The bug has been discussed on the linux-usb-devel mailing-list four years ago, the original thread can be found here: http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg45345.html This patch implements the first workaround as suggested by David Brownell. The built-in USB host controller of the Atheros AR7130/AR7141/AR7161 SoCs requires this to work properly. Signed-off-by: Gabor Juhos Cc: David Brownell Cc: Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org --- Changes since RFC: --- Changes since v1: - rebased against 2.6.37-rc7 drivers/usb/host/ehci-q.c | 3 +++ drivers/usb/host/ehci.h | 1 + 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c index 233c288..343b8de 100644 --- a/drivers/usb/host/ehci-q.c +++ b/drivers/usb/host/ehci-q.c @@ -1193,6 +1193,9 @@ static void end_unlink_async (struct ehci_hcd *ehci) ehci->reclaim = NULL; start_unlink_async (ehci, next); } + + if (ehci->has_synopsys_hc_bug) + writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); } /* makes sure the async qh will become idle */ diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index ba8eab3..6da85b2 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -133,6 +133,7 @@ struct ehci_hcd { /* one per controller */ unsigned broken_periodic:1; unsigned fs_i_thresh:1; /* Intel iso scheduling */ unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ + unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ /* required for usb32 quirk */ #define OHCI_CTRL_HCFS (3 << 6) -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:36:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:36:40 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37551 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491099Ab0LVUb3 (ORCPT ); Wed, 22 Dec 2010 21:31:29 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 8691F80EF; Wed, 22 Dec 2010 21:31:24 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id BF59E1F0001; Wed, 22 Dec 2010 21:31:23 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos , David Brownell , Greg Kroah-Hartman , linux-usb@vger.kernel.org Subject: [PATCH v2 12/16] USB: ehci: add bus glue for the Atheros AR71XX/AR724X/AR913X SoCs Date: Wed, 22 Dec 2010 21:30:57 +0100 Message-Id: <1293049861-28913-13-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F63563BE | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28696 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 7970 Lines: 292 The Atheros AR71XX/AR724X/AR913X SoCs have a built-in EHCI controller. This patch adds the necessary glue code to make the generic EHCI driver usable for them. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: David Brownell Cc: Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org --- Changes since RFC: - don't use 'default y if SOC_*', select USB_ARCH_HAS_EHCI option in the platform specific Kconfig file instead - add missing 'ath79_ehci_platform.h' file Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 3 + .../include/asm/mach-ath79/ath79_ehci_platform.h | 18 ++ drivers/usb/host/Kconfig | 8 + drivers/usb/host/ehci-ath79.c | 176 ++++++++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + 5 files changed, 210 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h create mode 100644 drivers/usb/host/ehci-ath79.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index cd6c738..647f535 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -15,12 +15,15 @@ config ATH79_MACH_PB44 endmenu config SOC_AR71XX + select USB_ARCH_HAS_EHCI def_bool n config SOC_AR724X + select USB_ARCH_HAS_EHCI def_bool n config SOC_AR913X + select USB_ARCH_HAS_EHCI def_bool n config ATH79_DEV_GPIO_BUTTONS diff --git a/arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h b/arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h new file mode 100644 index 0000000..6ee075f --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h @@ -0,0 +1,18 @@ +/* + * Platform data definition for Atheros AR71XX/AR913X EHCI controller + * + * Copyright (C) 2008-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_EHCI_PLATFORM_H +#define _ATH79_EHCI_PLATFORM_H + +struct ath79_ehci_platform_data { + u8 is_ar913x; +}; + +#endif /* _ATH79_EHCI_PLATFORM_H */ diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 6f4f8e6..3a2667a 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -147,6 +147,14 @@ config USB_W90X900_EHCI ---help--- Enables support for the W90X900 USB controller +config USB_EHCI_ATH79 + bool "EHCI support for AR71XX/AR724X/AR913X SoCs" + depends on USB_EHCI_HCD && ATH79 + select USB_EHCI_ROOT_HUB_TT + ---help--- + Enables support for the built-in EHCI controller present + on the Atheros AR71XX/AR724X/AR913X SoCs. + config USB_OXU210HP_HCD tristate "OXU210HP HCD support" depends on USB diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c new file mode 100644 index 0000000..43a728f --- /dev/null +++ b/drivers/usb/host/ehci-ath79.c @@ -0,0 +1,176 @@ +/* + * Bus Glue for Atheros AR71XX/AR913X built-in EHCI controller. + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * Copyright (C) 2007 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +static int ehci_ath79_init(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct ath79_ehci_platform_data *pdata; + int ret; + + pdata = hcd->self.controller->platform_data; + + if (pdata->is_ar913x) { + hcd->has_tt = 1; + + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + } else { + ehci->has_synopsys_hc_bug = 1; + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + } + + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + ehci->sbrn = 0x20; + + ehci_reset(ehci); + + ret = ehci_init(hcd); + if (ret) + return ret; + + ehci_port_power(ehci, 0); + + return 0; +} + +static const struct hc_driver ehci_ath79_hc_driver = { + .description = hcd_name, + .product_desc = "Atheros built-in EHCI controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + .reset = ehci_ath79_init, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#ifdef CONFIG_PM + .hub_suspend = ehci_hub_suspend, + .hub_resume = ehci_hub_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_ath79_probe(struct platform_device *pdev) +{ + struct ath79_ehci_platform_data *pdata; + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + if (usb_disabled()) + return -ENODEV; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_dbg(&pdev->dev, "no platform data specified for %s\n", + dev_name(&pdev->dev)); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_dbg(&pdev->dev, "no IRQ specified for %s\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "no base address specified for %s\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + + hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (ret) + goto err_iounmap; + + return 0; + +err_iounmap: + iounmap(hcd->regs); + +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_ath79_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static struct platform_driver ehci_ath79_driver = { + .probe = ehci_ath79_probe, + .remove = ehci_ath79_remove, + .driver = { + .owner = THIS_MODULE, + .name = "ath79-ehci", + } +}; + +MODULE_ALIAS("platform:ath79-ehci"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index e906280..b1313af 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1216,6 +1216,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_octeon_driver #endif +#ifdef CONFIG_USB_EHCI_ATH79 +#include "ehci-ath79.c" +#define PLATFORM_DRIVER ehci_ath79_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:36:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:37:05 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37559 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491057Ab0LVUba (ORCPT ); Wed, 22 Dec 2010 21:31:30 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 26E7580F3; Wed, 22 Dec 2010 21:31:25 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 693B81F0001; Wed, 22 Dec 2010 21:31:24 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos , David Brownell , Greg Kroah-Hartman , linux-usb@vger.kernel.org Subject: [PATCH v2 13/16] USB: ohci: add bus glue for the Atheros AR71XX/AR7240 SoCs Date: Wed, 22 Dec 2010 21:30:58 +0100 Message-Id: <1293049861-28913-14-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F68EAC17 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28697 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 6514 Lines: 249 The Atheros AR71XX/AR7240 SoCs have a built-in OHCI controller. This patch adds the necessary glue code to make the generic OHCI driver usable for them. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: David Brownell Cc: Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org --- Changes since RFC: - don't use 'defauly y if SOC_*', select the USB_ARCH_HAS_OHCI option in the platform specific Kconfig file instead - remove ath79_ehci_platform.h, it belongs to the EHCI patch Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 2 + drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/ohci-ath79.c | 162 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 5 + 4 files changed, 177 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ohci-ath79.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 647f535..d4456ce 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -16,10 +16,12 @@ endmenu config SOC_AR71XX select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI def_bool n config SOC_AR724X select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI def_bool n config SOC_AR913X diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 3a2667a..39ed353 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -240,6 +240,14 @@ config USB_OHCI_HCD_OMAP3 Enables support for the on-chip OHCI controller on OMAP3 and later chips. +config USB_OHCI_ATH79 + bool "USB OHCI support for the Atheros AR71XX/AR724X SoCs" + depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) + default y + help + Enables support for the uilt-in OHCI controller present on the + Atheros AR71XX/AR724X SoCs. + config USB_OHCI_HCD_PPC_SOC bool "OHCI support for on-chip PPC USB controller" depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) diff --git a/drivers/usb/host/ohci-ath79.c b/drivers/usb/host/ohci-ath79.c new file mode 100644 index 0000000..6e864bf --- /dev/null +++ b/drivers/usb/host/ohci-ath79.c @@ -0,0 +1,162 @@ +/* + * OHCI HCD (Host Controller Driver) for USB. + * + * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * Copyright (C) 2007 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +static int usb_hcd_ath79_probe(const struct hc_driver *driver, + struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_dbg(&pdev->dev, "no IRQ specified for %s\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "no base address specified for %s\n", + dev_name(&pdev->dev)); + ret = -ENODEV; + goto err_put_hcd; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ohci_hcd_init(hcd_to_ohci(hcd)); + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); + if (ret) + goto err_stop_hcd; + + return 0; + +err_stop_hcd: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +void usb_hcd_ath79_remove(struct usb_hcd *hcd, struct platform_device *pdev) +{ + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); +} + +static int __devinit ohci_ath79_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int ret; + + ret = ohci_init(ohci); + if (ret < 0) + return ret; + + ret = ohci_run(ohci); + if (ret < 0) + goto err; + + return 0; + +err: + ohci_stop(hcd); + return ret; +} + +static const struct hc_driver ohci_ath79_hc_driver = { + .description = hcd_name, + .product_desc = "Atheros built-in OHCI controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + + .irq = ohci_irq, + .flags = HCD_USB11 | HCD_MEMORY, + + .start = ohci_ath79_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ohci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, + .start_port_reset = ohci_start_port_reset, +}; + +static int ohci_hcd_ath79_drv_probe(struct platform_device *pdev) +{ + if (usb_disabled()) + return -ENODEV; + + return usb_hcd_ath79_probe(&ohci_ath79_hc_driver, pdev); +} + +static int ohci_hcd_ath79_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_hcd_ath79_remove(hcd, pdev); + return 0; +} + +static struct platform_driver ohci_hcd_ath79_driver = { + .probe = ohci_hcd_ath79_drv_probe, + .remove = ohci_hcd_ath79_drv_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ath79-ohci", + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS("platform:ath79-ohci"); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 5179acb..6daeb68 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1111,6 +1111,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_octeon_driver #endif +#ifdef CONFIG_USB_OHCI_ATH79 +#include "ohci-ath79.c" +#define PLATFORM_DRIVER ohci_hcd_ath79_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:37:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:37:28 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37566 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491101Ab0LVUba (ORCPT ); Wed, 22 Dec 2010 21:31:30 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 9FB7F80F4; Wed, 22 Dec 2010 21:31:25 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 072751F0001; Wed, 22 Dec 2010 21:31:24 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 14/16] MIPS: ath79: add common USB Host Controller device Date: Wed, 22 Dec 2010 21:30:59 +0100 Message-Id: <1293049861-28913-15-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F7069C5A | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28698 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 10336 Lines: 367 Add common platform_device and helper code to make the registration of the built-in USB controllers easier on the board which are using them. Also register the USB controller on the PB44 board. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- Changes since RFC: --- Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 4 + arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-usb.c | 194 ++++++++++++++++++++++++ arch/mips/ath79/dev-usb.h | 17 ++ arch/mips/ath79/mach-pb44.c | 2 + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 22 +++- 6 files changed, 239 insertions(+), 1 deletions(-) create mode 100644 arch/mips/ath79/dev-usb.c create mode 100644 arch/mips/ath79/dev-usb.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index d4456ce..5d67942 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -8,6 +8,7 @@ config ATH79_MACH_PB44 select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO select ATH79_DEV_SPI + select ATH79_DEV_USB help Say 'Y' here if you want your kernel to support the Atheros PB44 reference board. @@ -37,4 +38,7 @@ config ATH79_DEV_LEDS_GPIO config ATH79_DEV_SPI def_bool n +config ATH79_DEV_USB + def_bool n + endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index a8de078..494d106 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -19,6 +19,7 @@ obj-y += dev-common.o obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o +obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o # # Machines diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c new file mode 100644 index 0000000..fb7033f --- /dev/null +++ b/arch/mips/ath79/dev-usb.c @@ -0,0 +1,194 @@ +/* + * Atheros AR71XX/AR724X/AR913X USB Host Controller support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "common.h" +#include "dev-usb.h" + +static void __iomem *ath79_usb_ctrl_base; + +static struct resource ar71xx_ohci_resources[] = { + [0] = { + .start = AR71XX_OHCI_BASE, + .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_MISC_IRQ_OHCI, + .end = ATH79_MISC_IRQ_OHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource ar724x_usb_resources[] = { + [0] = { + .start = AR7240_OHCI_BASE, + .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_CPU_IRQ_USB, + .end = ATH79_CPU_IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); +static struct platform_device ath79_ohci_device = { + .name = "ath79-ohci", + .id = -1, + .resource = ar71xx_ohci_resources, + .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), + .dev = { + .dma_mask = &ath79_ohci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource ar71xx_ehci_resources[] = { + [0] = { + .start = AR71XX_EHCI_BASE, + .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_CPU_IRQ_USB, + .end = ATH79_CPU_IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); +static struct ath79_ehci_platform_data ath79_ehci_data; + +static struct platform_device ath79_ehci_device = { + .name = "ath79-ehci", + .id = -1, + .resource = ar71xx_ehci_resources, + .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), + .dev = { + .dma_mask = &ath79_ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &ath79_ehci_data, + }, +}; + +#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ + AR71XX_RESET_USB_PHY | \ + AR71XX_RESET_USB_OHCI_DLL) + +static void __init ar71xx_usb_setup(void) +{ + ath79_device_reset_set(AR71XX_USB_RESET_MASK); + mdelay(1000); + ath79_device_reset_clear(AR71XX_USB_RESET_MASK); + + /* Turning on the Buff and Desc swap bits */ + __raw_writel(0xf0000, ath79_usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG); + + /* WAR for HW bug. Here it adjusts the duration between two SOFS */ + __raw_writel(0x20c00, ath79_usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); + + mdelay(900); + + platform_device_register(&ath79_ohci_device); + platform_device_register(&ath79_ehci_device); +} + +static void __init ar7240_usb_setup(void) +{ + ath79_device_reset_clear(AR7240_RESET_OHCI_DLL); + ath79_device_reset_set(AR7240_RESET_USB_HOST); + mdelay(1000); + ath79_device_reset_set(AR7240_RESET_OHCI_DLL); + ath79_device_reset_clear(AR7240_RESET_USB_HOST); + + /* WAR for HW bug. Here it adjusts the duration between two SOFS */ + __raw_writel(0x3, ath79_usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); + + ath79_ohci_device.resource = ar724x_usb_resources; + ath79_ohci_device.num_resources = ARRAY_SIZE(ar724x_usb_resources); + platform_device_register(&ath79_ohci_device); +} + +static void __init ar724x_usb_setup(void) +{ + ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE); + mdelay(10); + + ath79_device_reset_clear(AR724X_RESET_USB_HOST); + mdelay(10); + + ath79_device_reset_clear(AR724X_RESET_USB_PHY); + mdelay(10); + + ath79_ehci_data.is_ar913x = 1; + ath79_ehci_device.resource = ar724x_usb_resources; + ath79_ehci_device.num_resources = ARRAY_SIZE(ar724x_usb_resources); + platform_device_register(&ath79_ehci_device); +} + +static void __init ar913x_usb_setup(void) +{ + ath79_device_reset_set(AR71XX_RESET_USBSUS_OVERRIDE); + mdelay(10); + + ath79_device_reset_clear(AR71XX_RESET_USB_HOST); + mdelay(10); + + ath79_device_reset_clear(AR71XX_RESET_USB_PHY); + mdelay(10); + + ath79_ehci_data.is_ar913x = 1; + platform_device_register(&ath79_ehci_device); +} + +void __init ath79_register_usb(void) +{ + ath79_usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, + AR71XX_USB_CTRL_SIZE); + + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + ar71xx_usb_setup(); + break; + + case ATH79_SOC_AR7240: + ar7240_usb_setup(); + break; + + case ATH79_SOC_AR7241: + case ATH79_SOC_AR7242: + ar724x_usb_setup(); + break; + + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + ar913x_usb_setup(); + break; + + default: + BUG(); + } +} diff --git a/arch/mips/ath79/dev-usb.h b/arch/mips/ath79/dev-usb.h new file mode 100644 index 0000000..dbe6d3d --- /dev/null +++ b/arch/mips/ath79/dev-usb.h @@ -0,0 +1,17 @@ +/* + * Atheros AR71XX/AR724X/AR913X USB Host Controller support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_USB_H +#define _ATH79_DEV_USB_H + +void ath79_register_usb(void) __init; + +#endif /* _ATH79_DEV_USB_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index ec7b7a1..fe9701a 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -18,6 +18,7 @@ #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" +#include "dev-usb.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 @@ -112,6 +113,7 @@ static void __init pb44_init(void) pb44_gpio_keys); ath79_register_spi(&pb44_spi_data, pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); + ath79_register_usb(); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 4f2b621..f125f1e 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -20,6 +20,10 @@ #include #define AR71XX_APB_BASE 0x18000000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 #define AR71XX_SPI_BASE 0x1f000000 #define AR71XX_SPI_SIZE 0x01000000 @@ -27,6 +31,8 @@ #define AR71XX_DDR_CTRL_SIZE 0x100 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) #define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) @@ -34,6 +40,9 @@ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) #define AR71XX_RESET_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + /* * DDR_CTRL block */ @@ -102,6 +111,12 @@ #define AR913X_AHB_DIV_MASK 0x1 /* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* * RESET block */ #define AR71XX_RESET_REG_TIMER 0x00 @@ -155,12 +170,17 @@ #define AR71XX_RESET_PCI_BUS BIT(1) #define AR71XX_RESET_PCI_CORE BIT(0) +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + #define AR724X_RESET_GE1_MDIO BIT(23) #define AR724X_RESET_GE0_MDIO BIT(22) #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) #define AR724X_RESET_PCIE_PHY BIT(7) #define AR724X_RESET_PCIE BIT(6) -#define AR724X_RESET_OHCI_DLL BIT(3) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) #define AR913X_RESET_AMBA2WMAC BIT(22) -- 1.7.2.1 From juhosg@openwrt.org Wed Dec 22 21:37:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Dec 2010 21:37:51 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:37576 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491102Ab0LVUbd (ORCPT ); Wed, 22 Dec 2010 21:31:33 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 5E7E98102; Wed, 22 Dec 2010 21:31:26 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 79CE31F0001; Wed, 22 Dec 2010 21:31:25 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , Gabor Juhos Subject: [PATCH v2 15/16] MIPS: ath79: add initial support for the Atheros AP81 reference board Date: Wed, 22 Dec 2010 21:31:00 +0100 Message-Id: <1293049861-28913-16-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> X-VBMS: A10F7533D2E | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28699 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 4364 Lines: 164 Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- Changes since RFC: - don't use 'default n' for the ATH79_MACH_AP81 Kconfig option Changes since v1: - rebased against 2.6.37-rc7 arch/mips/ath79/Kconfig | 11 +++++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/mach-ap81.c | 94 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 107 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/mach-ap81.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 5d67942..1912d54 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -2,6 +2,17 @@ if ATH79 menu "Atheros AR71XX/AR724X/AR913X machine selection" +config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + select ATH79_DEV_USB + help + Say 'Y' here if you want your kernel to support the + Atheros AP81 reference board. + config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 494d106..1b111d8 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -24,4 +24,5 @@ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o # # Machines # +obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c new file mode 100644 index 0000000..909ca5d --- /dev/null +++ b/arch/mips/ath79/mach-ap81.c @@ -0,0 +1,94 @@ +/* + * Atheros AP81 board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * Copyright (C) 2009 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "machtypes.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" +#include "dev-usb.h" + +#define AP81_GPIO_LED_STATUS 1 +#define AP81_GPIO_LED_AOSS 3 +#define AP81_GPIO_LED_WLAN 6 +#define AP81_GPIO_LED_POWER 14 + +#define AP81_GPIO_BTN_SW4 12 +#define AP81_GPIO_BTN_SW1 21 + +#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL) + +static struct gpio_led ap81_leds_gpio[] __initdata = { + { + .name = "ap81:green:status", + .gpio = AP81_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "ap81:amber:aoss", + .gpio = AP81_GPIO_LED_AOSS, + .active_low = 1, + }, { + .name = "ap81:green:wlan", + .gpio = AP81_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "ap81:green:power", + .gpio = AP81_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap81_gpio_keys[] __initdata = { + { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP81_GPIO_BTN_SW1, + .active_low = 1, + } , { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP81_GPIO_BTN_SW4, + .active_low = 1, + } +}; + +static struct spi_board_info ap81_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", + } +}; + +static struct ath79_spi_platform_data ap81_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +static void __init ap81_setup(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), + ap81_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap81_gpio_keys), + ap81_gpio_keys); + ath79_register_spi(&ap81_spi_data, ap81_spi_info, + ARRAY_SIZE(ap81_spi_info)); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", + ap81_setup); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index a796fa3..3940fe4 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -16,6 +16,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP81, /* Atheros AP81 reference board */ ATH79_MACH_PB44, /* Atheros PB44 reference board */ }; -- 1.7.2.1 From gregkh@suse.de Thu Dec 23 01:30:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Dec 2010 01:31:01 +0100 (CET) Received: from cantor2.suse.de ([195.135.220.15]:58369 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491102Ab0LWAa5 (ORCPT ); Thu, 23 Dec 2010 01:30:57 +0100 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) by mx2.suse.de (Postfix) with ESMTP id 133E888B6C; Thu, 23 Dec 2010 01:30:56 +0100 (CET) Date: Wed, 22 Dec 2010 16:30:48 -0800 From: Greg KH To: Gabor Juhos Cc: Ralf Baechle , linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , David Brownell , linux-usb@vger.kernel.org Subject: Re: [PATCH v2 11/16] USB: ehci: add workaround for Synopsys HC bug Message-ID: <20101223003048.GB9811@suse.de> References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> <1293049861-28913-12-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1293049861-28913-12-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28700 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Content-Length: 3482 Lines: 85 On Wed, Dec 22, 2010 at 09:30:56PM +0100, Gabor Juhos wrote: > A Synopsys USB core used in various SoCs has a bug which might cause > that the host controller not issuing ping. > > When software uses the Doorbell mechanism to remove queue heads, the > host controller still has references to the removed queue head even > after indicating an Interrupt on Async Advance. This happens if the last > executed queue head's Next Link queue head is removed. > > Consequences of the defect: > The Host controller fetches the removed queue head, using memory that > would otherwise be deallocated.This results in incorrect transactions on > both the USB and system memory. This may result in undefined behavior. > > Workarounds: > > 1) If no queue head is active (no Status field's Active bit is set) > after removing the queue heads, the software can write one of the valid > queue head addresses to the ASYNCLISTADDR register and deallocate the > removed queue head's memory after 2 microframes. > > If one or more of the queue heads is active (the Active bit is set in > the Status field) after removing the queue heads, the software can delay > memory deallocation after time X, where X is the time required for the > Host Controller to go through all the queue heads once. X varies with > the number of queue heads and the time required to process periodic > transactions: if more periodic transactions must be performed, the Host > Controller has less time to process asynchronous transaction processing. > > 2) Do not use the Doorbell mechanism to remove the queue heads. Disable > the Asynchronous Schedule Enable bit instead. > > The bug has been discussed on the linux-usb-devel mailing-list > four years ago, the original thread can be found here: > http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg45345.html > > This patch implements the first workaround as suggested by David Brownell. > The built-in USB host controller of the Atheros AR7130/AR7141/AR7161 SoCs > requires this to work properly. > > Signed-off-by: Gabor Juhos > Cc: David Brownell > Cc: Greg Kroah-Hartman > Cc: linux-usb@vger.kernel.org > --- > > Changes since RFC: --- > > Changes since v1: > - rebased against 2.6.37-rc7 > > drivers/usb/host/ehci-q.c | 3 +++ > drivers/usb/host/ehci.h | 1 + > 2 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c > index 233c288..343b8de 100644 > --- a/drivers/usb/host/ehci-q.c > +++ b/drivers/usb/host/ehci-q.c > @@ -1193,6 +1193,9 @@ static void end_unlink_async (struct ehci_hcd *ehci) > ehci->reclaim = NULL; > start_unlink_async (ehci, next); > } > + > + if (ehci->has_synopsys_hc_bug) > + writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); > } > > /* makes sure the async qh will become idle */ > diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h > index ba8eab3..6da85b2 100644 > --- a/drivers/usb/host/ehci.h > +++ b/drivers/usb/host/ehci.h > @@ -133,6 +133,7 @@ struct ehci_hcd { /* one per controller */ > unsigned broken_periodic:1; > unsigned fs_i_thresh:1; /* Intel iso scheduling */ > unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ > + unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ That's fine, but who sets this value to 1? I don't see any code that does that, so why add this at all? :) thanks, greg k-h From stern+4d08bae8@rowland.harvard.edu Thu Dec 23 03:18:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Dec 2010 03:18:28 +0100 (CET) Received: from netrider.rowland.org ([192.131.102.5]:51833 "HELO netrider.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1490992Ab0LWCSY (ORCPT ); Thu, 23 Dec 2010 03:18:24 +0100 Received: (qmail 27175 invoked by uid 500); 22 Dec 2010 21:18:20 -0500 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 22 Dec 2010 21:18:20 -0500 Date: Wed, 22 Dec 2010 21:18:20 -0500 (EST) From: Alan Stern X-X-Sender: stern@netrider.rowland.org To: "Anoop P.A" cc: Ralf Baechle , Greg Kroah-Hartman , Anatolij Gustschin , Anand Gadiyar , , , , Sarah Sharp , Oliver Neukum , Hans de Goede , Paul Mortier , Andiry Xu Subject: Re: [PATCH V2 2/2] MSP onchip root hub over current quirk. In-Reply-To: <1293028610-22233-1-git-send-email-anoop.pa@gmail.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28701 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Content-Length: 3353 Lines: 112 On Wed, 22 Dec 2010, Anoop P.A wrote: > From: Anoop P A > > Adding chip specific code under quirk. NAK. See below. > Signed-off-by: Anoop P A > --- > drivers/usb/core/hub.c | 45 ++++++++++++++++++++++++++++++++++++++----- > drivers/usb/core/quirks.c | 3 ++ > include/linux/usb/quirks.h | 3 ++ > 3 files changed, 45 insertions(+), 6 deletions(-) > > diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c > index 27115b4..4bff994 100644 > --- a/drivers/usb/core/hub.c > +++ b/drivers/usb/core/hub.c > @@ -3377,12 +3377,45 @@ static void hub_events(void) > } > > if (portchange & USB_PORT_STAT_C_OVERCURRENT) { > - dev_err (hub_dev, > - "over-current change on port %d\n", > - i); > - clear_port_feature(hdev, i, > - USB_PORT_FEAT_C_OVER_CURRENT); > - hub_power_on(hub, true); > + usb_detect_quirks(hdev); This line is wrong. usb_detect_quirks() gets called only once per device, when the device is initialized. Besides, you probably want to use a hub-specific flag for this rather than a device-specific flag. > + if (hdev->quirks & USB_QUIRK_MSP_OVERCURRENT) { Also, it would be better to put this code in a separate subroutine instead of indenting it so far. > + /* clear OCC bit */ > + clear_port_feature(hdev, i, > + USB_PORT_FEAT_C_OVER_CURRENT); > + > + /* This step is required to toggle the > + * PP bit to 0 and 1 (by hub_power_on) > + * in order the CSC bit to be > + * transitioned properly for device > + * hotplug > + */ > + /* clear PP bit */ > + clear_port_feature(hdev, i, > + USB_PORT_FEAT_POWER); > + > + /* resume power */ > + hub_power_on(hub, true); > + > + /* delay 100 usec */ > + udelay(100); > + > + /* read OCA bit */ > + if (portstatus & > + (1< + /* declare overcurrent */ > + dev_err(hub_dev, > + "over-current change \ > + on port %d\n", i); > + } > + } else { > + dev_err(hub_dev, > + "over-current change \ > + on port %d\n", i); > + clear_port_feature(hdev, i, > + USB_PORT_FEAT_C_OVER_CURRENT); > + hub_power_on(hub, true); > + } > + > } > > if (portchange & USB_PORT_STAT_C_RESET) { > diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c > index 25719da..59843b9 100644 > --- a/drivers/usb/core/quirks.c > +++ b/drivers/usb/core/quirks.c > @@ -88,6 +88,9 @@ static const struct usb_device_id usb_quirk_list[] = { > /* INTEL VALUE SSD */ > { USB_DEVICE(0x8086, 0xf1a5), .driver_info = USB_QUIRK_RESET_RESUME }, > > + /* PMC MSP over current quirk */ > + { USB_DEVICE(0x1d6b, 0x0002), .driver_info = USB_QUIRK_MSP_OVERCURRENT }, > + This implementation is completely wrong. It applies to all USB-2.0 root hubs in Linux, not just the PMC MSP. > { } /* terminating entry must be last */ > }; > > diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h > index 3e93de7..97ab168 100644 > --- a/include/linux/usb/quirks.h > +++ b/include/linux/usb/quirks.h > @@ -30,4 +30,7 @@ > descriptor */ > #define USB_QUIRK_DELAY_INIT 0x00000040 > > +/*MSP SoC onchip EHCI overcurrent issue */ > +#define USB_QUIRK_MSP_OVERCURRENT 0x00000080 > + > #endif /* __LINUX_USB_QUIRKS_H */ > From juhosg@openwrt.org Thu Dec 23 09:29:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Dec 2010 09:29:39 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:48146 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491012Ab0LWI3g (ORCPT ); Thu, 23 Dec 2010 09:29:36 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 06FEF80E0; Thu, 23 Dec 2010 09:29:29 +0100 (CET) Received: from [192.168.254.10] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id A7C3C1F0002; Thu, 23 Dec 2010 09:29:28 +0100 (CET) Message-ID: <4D13085E.5060001@openwrt.org> Date: Thu, 23 Dec 2010 09:29:18 +0100 From: Gabor Juhos User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; hu-HU; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Greg KH CC: Ralf Baechle , linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori , David Brownell , linux-usb@vger.kernel.org Subject: Re: [PATCH v2 11/16] USB: ehci: add workaround for Synopsys HC bug References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> <1293049861-28913-12-git-send-email-juhosg@openwrt.org> <20101223003048.GB9811@suse.de> In-Reply-To: <20101223003048.GB9811@suse.de> X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-VBMS: A1474DD8D18 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28702 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 1219 Lines: 36 Hi Greg, <...> >> diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c >> index 233c288..343b8de 100644 >> --- a/drivers/usb/host/ehci-q.c >> +++ b/drivers/usb/host/ehci-q.c >> @@ -1193,6 +1193,9 @@ static void end_unlink_async (struct ehci_hcd *ehci) >> ehci->reclaim = NULL; >> start_unlink_async (ehci, next); >> } >> + >> + if (ehci->has_synopsys_hc_bug) >> + writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); >> } >> >> /* makes sure the async qh will become idle */ >> diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h >> index ba8eab3..6da85b2 100644 >> --- a/drivers/usb/host/ehci.h >> +++ b/drivers/usb/host/ehci.h >> @@ -133,6 +133,7 @@ struct ehci_hcd { /* one per controller */ >> unsigned broken_periodic:1; >> unsigned fs_i_thresh:1; /* Intel iso scheduling */ >> unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ >> + unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ > > That's fine, but who sets this value to 1? I don't see any code that > does that, so why add this at all? :) It will be set to 1 by ehci_ath79_init which is in the next patch [1] of this series. -Gabor 1. http://marc.info/?l=linux-usb&m=129304988827418&w=2 From anoop.pa@gmail.com Thu Dec 23 10:21:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Dec 2010 10:21:05 +0100 (CET) Received: from mail-yi0-f49.google.com ([209.85.218.49]:39962 "EHLO mail-yi0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491016Ab0LWJVC (ORCPT ); Thu, 23 Dec 2010 10:21:02 +0100 Received: by yib2 with SMTP id 2so867689yib.36 for ; Thu, 23 Dec 2010 01:20:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=vWTCy3Nn+wkiGSZRYYyOLutQltazPLhTcAjo1t6+EAU=; b=b2t4EtU31wKLoJT0I89eK5VuJ92T0pJGJOZUdw7PJ2ftcWG2dL3dSLoG3g2oK1dVgD njCGBbYDUAO7QPY3aOnJriGGuk+tpYJ//MJOW9wXDxokC1i9OtLxHWIoCwkG4yca7TwF MEhRzUYZoLD9K0v+4IW9FeajlAdksu2U1bDhg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=cR3S1rnYr0qwFLZh+nRGId1TU+aENBLWQJLzR597fXK2ZZ15l3xlgVKc0Mu+OMTL/q PDuCcKgvPR4AhUKViix78WzfRcFkvWhDRea1fT65NmwGG3ATELM4ZfGBhb4gxOtoMPJI 1L8FxdtIi511yiz/8iv5wsC1WhGUtJ7xVeUF4= Received: by 10.91.121.3 with SMTP id y3mr9815936agm.156.1293096056185; Thu, 23 Dec 2010 01:20:56 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id 35sm12269091ano.11.2010.12.23.01.20.49 (version=SSLv3 cipher=RC4-MD5); Thu, 23 Dec 2010 01:20:54 -0800 (PST) Subject: Re: [PATCH V2 2/2] MSP onchip root hub over current quirk. From: Anoop P A To: Alan Stern Cc: Ralf Baechle , Greg Kroah-Hartman , Anatolij Gustschin , Anand Gadiyar , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Sarah Sharp , Oliver Neukum , Hans de Goede , Paul Mortier , Andiry Xu In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Date: Thu, 23 Dec 2010 14:59:01 +0530 Message-ID: <1293096541.27661.46.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28703 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 3765 Lines: 120 On Wed, 2010-12-22 at 21:18 -0500, Alan Stern wrote: > On Wed, 22 Dec 2010, Anoop P.A wrote: > > > From: Anoop P A > > > > Adding chip specific code under quirk. > > NAK. See below. > > > Signed-off-by: Anoop P A > > --- > > drivers/usb/core/hub.c | 45 ++++++++++++++++++++++++++++++++++++++----- > > drivers/usb/core/quirks.c | 3 ++ > > include/linux/usb/quirks.h | 3 ++ > > 3 files changed, 45 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c > > index 27115b4..4bff994 100644 > > --- a/drivers/usb/core/hub.c > > +++ b/drivers/usb/core/hub.c > > @@ -3377,12 +3377,45 @@ static void hub_events(void) > > } > > > > if (portchange & USB_PORT_STAT_C_OVERCURRENT) { > > - dev_err (hub_dev, > > - "over-current change on port %d\n", > > - i); > > - clear_port_feature(hdev, i, > > - USB_PORT_FEAT_C_OVER_CURRENT); > > - hub_power_on(hub, true); > > + usb_detect_quirks(hdev); > > This line is wrong. usb_detect_quirks() gets called only once per > device, when the device is initialized. Besides, you probably want to > use a hub-specific flag for this rather than a device-specific flag. Can you point me to an example for the recommended way of doing the hack. I don't have much exposure to USB subsystem. > > > + if (hdev->quirks & USB_QUIRK_MSP_OVERCURRENT) { > > Also, it would be better to put this code in a separate subroutine > instead of indenting it so far. > > > + /* clear OCC bit */ > > + clear_port_feature(hdev, i, > > + USB_PORT_FEAT_C_OVER_CURRENT); > > + > > + /* This step is required to toggle the > > + * PP bit to 0 and 1 (by hub_power_on) > > + * in order the CSC bit to be > > + * transitioned properly for device > > + * hotplug > > + */ > > + /* clear PP bit */ > > + clear_port_feature(hdev, i, > > + USB_PORT_FEAT_POWER); > > + > > + /* resume power */ > > + hub_power_on(hub, true); > > + > > + /* delay 100 usec */ > > + udelay(100); > > + > > + /* read OCA bit */ > > + if (portstatus & > > + (1< > + /* declare overcurrent */ > > + dev_err(hub_dev, > > + "over-current change \ > > + on port %d\n", i); > > + } > > + } else { > > + dev_err(hub_dev, > > + "over-current change \ > > + on port %d\n", i); > > + clear_port_feature(hdev, i, > > + USB_PORT_FEAT_C_OVER_CURRENT); > > + hub_power_on(hub, true); > > + } > > + > > } > > > > if (portchange & USB_PORT_STAT_C_RESET) { > > diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c > > index 25719da..59843b9 100644 > > --- a/drivers/usb/core/quirks.c > > +++ b/drivers/usb/core/quirks.c > > @@ -88,6 +88,9 @@ static const struct usb_device_id usb_quirk_list[] = { > > /* INTEL VALUE SSD */ > > { USB_DEVICE(0x8086, 0xf1a5), .driver_info = USB_QUIRK_RESET_RESUME }, > > > > + /* PMC MSP over current quirk */ > > + { USB_DEVICE(0x1d6b, 0x0002), .driver_info = USB_QUIRK_MSP_OVERCURRENT }, > > + > > This implementation is completely wrong. It applies to all USB-2.0 > root hubs in Linux, not just the PMC MSP. > > > { } /* terminating entry must be last */ > > }; > > > > diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h > > index 3e93de7..97ab168 100644 > > --- a/include/linux/usb/quirks.h > > +++ b/include/linux/usb/quirks.h > > @@ -30,4 +30,7 @@ > > descriptor */ > > #define USB_QUIRK_DELAY_INIT 0x00000040 > > > > +/*MSP SoC onchip EHCI overcurrent issue */ > > +#define USB_QUIRK_MSP_OVERCURRENT 0x00000080 > > + > > #endif /* __LINUX_USB_QUIRKS_H */ > > > Thanks Anoop From sshtylyov@mvista.com Thu Dec 23 11:42:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Dec 2010 11:42:43 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:38701 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491019Ab0LWKmk (ORCPT ); Thu, 23 Dec 2010 11:42:40 +0100 Received: by eyd9 with SMTP id 9so4106932eyd.36 for ; Thu, 23 Dec 2010 02:42:37 -0800 (PST) Received: by 10.213.13.14 with SMTP id z14mr6508543ebz.52.1293100957466; Thu, 23 Dec 2010 02:42:37 -0800 (PST) Received: from [192.168.2.2] ([91.79.89.129]) by mx.google.com with ESMTPS id u1sm5482943eeh.10.2010.12.23.02.42.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 23 Dec 2010 02:42:35 -0800 (PST) Message-ID: <4D13275D.8010204@mvista.com> Date: Thu, 23 Dec 2010 13:41:33 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips@linux-mips.org, Imre Kaloz , "Luis R. Rodriguez" , Cliff Holden , Kathy Giori Subject: Re: [PATCH v2 07/16] MIPS: ath79: add common watchdog device References: <1293049861-28913-1-git-send-email-juhosg@openwrt.org> <1293049861-28913-8-git-send-email-juhosg@openwrt.org> In-Reply-To: <1293049861-28913-8-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 660 Lines: 24 Hello. On 22-12-2010 23:30, Gabor Juhos wrote: > All supported SoCs have a built-in hardware watchdog driver. This patch > registers a platform_device for that to make it usable. > Signed-off-by: Gabor Juhos > Signed-off-by: Imre Kaloz [...] > diff --git a/arch/mips/ath79/dev-common.h b/arch/mips/ath79/dev-common.h > index 1cec894..65bf400 100644 > --- a/arch/mips/ath79/dev-common.h > +++ b/arch/mips/ath79/dev-common.h > @@ -13,5 +13,6 @@ > #define _ATH79_DEV_COMMON_H > > void ath79_register_uart(void) __init; > +void ath79_register_wdt(void) __init; '__init' not needed with declarations. WBR, Sergei From stern+4d08bae8@rowland.harvard.edu Thu Dec 23 17:08:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Dec 2010 17:08:43 +0100 (CET) Received: from netrider.rowland.org ([192.131.102.5]:33567 "HELO netrider.rowland.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491031Ab0LWQIk (ORCPT ); Thu, 23 Dec 2010 17:08:40 +0100 Received: (qmail 6003 invoked by uid 500); 23 Dec 2010 11:08:36 -0500 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 23 Dec 2010 11:08:36 -0500 Date: Thu, 23 Dec 2010 11:08:36 -0500 (EST) From: Alan Stern X-X-Sender: stern@netrider.rowland.org To: Anoop P A cc: Ralf Baechle , Greg Kroah-Hartman , Anatolij Gustschin , Anand Gadiyar , , , , Sarah Sharp , Oliver Neukum , Hans de Goede , Paul Mortier , Andiry Xu Subject: Re: [PATCH V2 2/2] MSP onchip root hub over current quirk. In-Reply-To: <1293096541.27661.46.camel@paanoop1-desktop> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28705 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stern@rowland.harvard.edu Precedence: bulk X-list: linux-mips Content-Length: 767 Lines: 21 On Thu, 23 Dec 2010, Anoop P A wrote: > > > + usb_detect_quirks(hdev); > > > > This line is wrong. usb_detect_quirks() gets called only once per > > device, when the device is initialized. Besides, you probably want to > > use a hub-specific flag for this rather than a device-specific flag. > > Can you point me to an example for the recommended way of doing the > hack. I don't have much exposure to USB subsystem. One example, suitable for PCI devices, can be found in drivers/usb/host/ehci-pci.c:ehci_pci_setup(). However the best approach would be for you to avoid adding any special-purpose code at all. Is it possible to handle overcurrent-change events in a way that will work just as well for normal hubs as for your MSP root hub? Alan Stern From stuart.venters@adtran.com Thu Dec 23 22:10:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Dec 2010 22:10:47 +0100 (CET) Received: from p02c11o143.mxlogic.net ([208.65.144.76]:59761 "EHLO p02c11o143.mxlogic.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491064Ab0LWVKo (ORCPT ); Thu, 23 Dec 2010 22:10:44 +0100 Received: from unknown [76.164.174.82] (EHLO p02c11o143.mxlogic.net) by p02c11o143.mxlogic.net(mxl_mta-6.8.0-0) with ESMTP id 3dab31d4.4b8f6940.35674.00-570.76355.p02c11o143.mxlogic.net (envelope-from ); Thu, 23 Dec 2010 14:10:43 -0700 (MST) X-MXL-Hash: 4d13bad34fe8d479-20942920a9a8fc763413eb1c33b40be73a7804fe Received: from unknown [76.164.174.82] (EHLO ex-hc3.corp.adtran.com) by p02c11o143.mxlogic.net(mxl_mta-6.8.0-0) over TLS secured channel with ESMTP id 0cab31d4.0.35556.00-364.76062.p02c11o143.mxlogic.net (envelope-from ); Thu, 23 Dec 2010 14:10:25 -0700 (MST) X-MXL-Hash: 4d13bac17948bb5e-81ec37ae14579c9278f13e0f471f98a0d7755a78 Received: from corp-exfr1.corp.adtran.com (172.23.101.21) by ex-hc3.corp.adtran.com (172.22.50.73) with Microsoft SMTP Server id 14.1.255.0; Thu, 23 Dec 2010 15:09:37 -0600 Received: from EXV1.corp.adtran.com ([172.22.48.215]) by corp-exfr1.corp.adtran.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 23 Dec 2010 15:09:30 -0600 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-Class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----_=_NextPart_001_01CBA2E5.AFC9CCF4" Subject: RE: SMTC support status in latest git head. Date: Thu, 23 Dec 2010 15:09:29 -0600 Message-ID: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> In-Reply-To: <4D11F707.8040205@paralogos.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: SMTC support status in latest git head. Thread-Index: Acuh2JVP6SJCcb4LQuy7QpT3p4hZEgBC5lbA From: STUART VENTERS To: "Kevin D. Kissell" CC: Anoop P.A. , , Anoop P A X-OriginalArrivalTime: 23 Dec 2010 21:09:30.0303 (UTC) FILETIME=[B086DCF0:01CBA2E5] X-Spam: [F=0.2000000000; CM=0.500; S=0.200(2010121501)] X-MAIL-FROM: X-SOURCE-IP: [76.164.174.82] X-AnalysisOut: [v=1.0 c=1 a=fMTePymILGAA:10 a=BLceEmwcHowA:10 a=J+LXdEUA8t] X-AnalysisOut: [8MtBPt16/Qbg==:17 a=-3IdzM-eE8yl22iDLqIA:9 a=ti0iJLGcbkqTQ] X-AnalysisOut: [UonrUCE9zTu75UA:4 a=QEXdDO2ut3YA:10 a=5A_KNP5RJ4JJmUoO5KwA] X-AnalysisOut: [:9 a=dVZk0e5d2ZhcXv0xrMaFsLW7S1QA:4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stuart.venters@adtran.com Precedence: bulk X-list: linux-mips Content-Length: 64530 Lines: 848 ------_=_NextPart_001_01CBA2E5.AFC9CCF4 Content-Type: text/plain; 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h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=xWw6LGds5mUpP45zOWbymOGYzRgNCxjj5w0uIKha4uo=; b=wXmkBF6vkh0onu/4VueiQoObHDPYZRptfUNfEYMntrV8ljFVKwoZjhQ/gEGz9AUk+P wYvkmV66nEvy19G52hG++FmBXpL7VH+K4zvHNuGxqfUkBHpIXLJbDGsI63D3bMEzwPdU R2XIjVsocNCvk4NwITLeu5pZPoF4iPCX+QcfE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=rXzkFC5dku7Iv9+9LFxSsH4PPsSVlbOer4a+tACIB5vUY5Q1SeBErxDSO2XuIkBAVf UCwwkjFeLTMpmyYOlq8jub0wPa4Ib1YWFRpaY/mqje7m2+NhbJwTS86Y+6iCibUKEg7o RxXtJwx+4g93R6C9cceJS1jr+HJ+wSX6Gn/uE= MIME-Version: 1.0 Received: by 10.229.74.147 with SMTP id u19mr8175494qcj.72.1293183292822; Fri, 24 Dec 2010 01:34:52 -0800 (PST) Received: by 10.229.107.10 with HTTP; Fri, 24 Dec 2010 01:34:52 -0800 (PST) In-Reply-To: <1290067948.9091.14.camel@paanoop1-desktop> References: <1290067948.9091.14.camel@paanoop1-desktop> Date: Fri, 24 Dec 2010 03:34:52 -0600 Message-ID: Subject: Re: [PATCH] Select R4K timer lib for all MSP platforms From: Shane McDonald To: Anoop P A Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 572 Lines: 14 Hi Anoop: On Thu, Nov 18, 2010 at 2:12 AM, Anoop P A wrote: > >From c872cbbe5f475d3bb3cb7f821270cb466eead1f7 Mon Sep 17 00:00:00 2001 > From: Anoop P A > Signed-off-by: Anoop P A > Date: Thu, 18 Nov 2010 01:33:36 +0530 > Subject: [PATCH] Select R4K timer lib for all MSP platforms I have successfully booted a 2.6.37-rc6 kernel with this patch applied on an MSP7120 Garibaldi evaluation board. It's good to see PMC-Sierra pushing things back upstream! Tested-by: Shane McDonald From mcdonald.shane@gmail.com Fri Dec 24 10:36:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Dec 2010 10:36:19 +0100 (CET) Received: from mail-qw0-f49.google.com ([209.85.216.49]:46376 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491041Ab0LXJgP convert rfc822-to-8bit (ORCPT ); Fri, 24 Dec 2010 10:36:15 +0100 Received: by qwj9 with SMTP id 9so7081202qwj.36 for ; Fri, 24 Dec 2010 01:36:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=RcMBnZ1wOW4V7bVnq1yR7cvS7OBRjXz0VKwe0ON63AU=; b=LbEea74JevWN9GZnucdD5cw045e3YnTY20VXYyf4kzo7Lw9xo+yQ8dbtelC17b3uYU 4N31VD3vy00k+fj2AY0nK4PqHQWKSytCLhV1ZBCPFCM5HYhiBUWoJITWAAICKBabd7Yj wgvnPFJBabS11/LCyEJIoz9+cA+6MhMXP6sV0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=kROBJMAqsa1F4gdmiqJIAQnuVRL08nze/Vjh2J12kAenapwPuT7scLiM24gDXGDat3 Rho/0EtXXqCs3gkvs2OUhJRmP8pl0h7rd8GHn5JTTBW35Gn2NRQd0HjxqGEvXjkK4xIN fV/SVE4MVBsQH4/Jhd00i1smuqNmE1Ya2sV7A= MIME-Version: 1.0 Received: by 10.229.88.207 with SMTP id b15mr8206585qcm.34.1293183369359; Fri, 24 Dec 2010 01:36:09 -0800 (PST) Received: by 10.229.107.10 with HTTP; Fri, 24 Dec 2010 01:36:09 -0800 (PST) In-Reply-To: <1290076370.31469.1.camel@paanoop1-desktop> References: <1290076370.31469.1.camel@paanoop1-desktop> Date: Fri, 24 Dec 2010 03:36:09 -0600 Message-ID: Subject: Re: [PATCH] Fix MSP71xx bpci interrupt handler return value From: Shane McDonald To: Anoop P A Cc: Ralf Baechle , Ben Hutchings , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 400 Lines: 13 Hi Anoop: On Thu, Nov 18, 2010 at 4:32 AM, Anoop P A wrote: > > Signed-off-by: Anoop P A > --- >  arch/mips/pci/ops-pmcmsp.c |    4 ++-- >  1 files changed, 2 insertions(+), 2 deletions(-) I have successfully booted a 2.6.37-rc6 kernel with this patch applied on an MSP7120 Garibaldi evaluation board. Tested-by: Shane McDonald From mcdonald.shane@gmail.com Fri Dec 24 10:44:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Dec 2010 10:44:41 +0100 (CET) Received: from mail-qy0-f170.google.com ([209.85.216.170]:63924 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491041Ab0LXJoi (ORCPT ); Fri, 24 Dec 2010 10:44:38 +0100 Received: by qyk10 with SMTP id 10so8923743qyk.15 for ; Fri, 24 Dec 2010 01:44:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=Hxf2F6gbQLfn0Nq8udECe0JE4vwQrVvzvFOOt5+5cGI=; b=YZdt+3TdHc75J68JlozhCw7/OWWylohim49SY6GdItaEqVvGmAB/8YkERuprYvMXTP 4nSEBPTlIWe+G1vPk/VlqQf0JW07ttbwRsjY87i5WqTrtmu2LjAmkuoSxLEVTWC4Cxgl J5QTqYRr1jPmBYRlpg3FLyytmhtDDIv44d19k= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=dAO7ct11FZ2vPCERKcFsxKGXN6Ccou/PgE88P5ABQv07N3h2xxosUNq/Vsnp7kz0SK YkKbKrVHRWBGH8UtYDXQ8V8j5PY6O1XkJFk/DKrxKrGJE4msq7A1HmikwqNTwGGgegqc 7DMOmOADY5VkYYmiH1s8WbGIZxy7wEhY+fWZ8= MIME-Version: 1.0 Received: by 10.229.84.135 with SMTP id j7mr8114640qcl.186.1293183871722; Fri, 24 Dec 2010 01:44:31 -0800 (PST) Received: by 10.229.107.10 with HTTP; Fri, 24 Dec 2010 01:44:31 -0800 (PST) In-Reply-To: <1293028561-22125-1-git-send-email-anoop.pa@gmail.com> References: <1292929580-5829-1-git-send-email-anoop.pa@gmail.com> <1293028561-22125-1-git-send-email-anoop.pa@gmail.com> Date: Fri, 24 Dec 2010 03:44:31 -0600 Message-ID: Subject: Re: [PATCH V2 1/2] EHCI support for on-chip PMC MSP USB controller. From: Shane McDonald To: "Anoop P.A" Cc: Ralf Baechle , Greg Kroah-Hartman , Anatolij Gustschin , Anand Gadiyar , Alan Stern , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28709 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 907 Lines: 24 Hi Anoop: On Wed, Dec 22, 2010 at 8:36 AM, Anoop P.A wrote: > From: Anoop P A > > This patch includes. > > 1. USB host driver for MSP71xx family SoC on-chip USB controller. > 2. Platform support for USB controller. > > Signed-off-by: Anoop P A I tried to apply this patch to a pristine linux-mips.org 2.6.37-rc6 kernel, but the patch failed on arch/mips/pmc-sierra/msp71xx/Makefile. I think you must have applied an SMP patch to your tree before generating this patch. That was easy to fix, and once I did that, I tried testing this on a PMC-Sierra MSP7120 Garibaldi evaluation board. Using your original changes to drivers/usb/core/hub.c in addition to this patch, I was able to boot a system, plug a USB hard drive in, and that drive was recognized by the Garibaldi. You can add my: Tested-by: Shane McDonald From sshtylyov@mvista.com Fri Dec 24 12:32:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Dec 2010 12:32:40 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:60106 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491066Ab0LXLch (ORCPT ); Fri, 24 Dec 2010 12:32:37 +0100 Received: by eyd9 with SMTP id 9so4465204eyd.36 for ; Fri, 24 Dec 2010 03:32:37 -0800 (PST) Received: by 10.213.4.11 with SMTP id 11mr8734297ebp.3.1293190356595; Fri, 24 Dec 2010 03:32:36 -0800 (PST) Received: from [192.168.2.2] ([91.79.84.9]) by mx.google.com with ESMTPS id x54sm6377083eeh.23.2010.12.24.03.32.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 24 Dec 2010 03:32:35 -0800 (PST) Message-ID: <4D148495.4030703@mvista.com> Date: Fri, 24 Dec 2010 14:31:33 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Anoop P A CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] Select R4K timer lib for all MSP platforms References: <1290067948.9091.14.camel@paanoop1-desktop> In-Reply-To: <1290067948.9091.14.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 429 Lines: 14 Hello. On 18-11-2010 11:12, Anoop P A wrote: >> From c872cbbe5f475d3bb3cb7f821270cb466eead1f7 Mon Sep 17 00:00:00 2001 > From: Anoop P A > Signed-off-by: Anoop P A > Date: Thu, 18 Nov 2010 01:33:36 +0530 > Subject: [PATCH] Select R4K timer lib for all MSP platforms Please don't include this header (except the signoff line) -- Ralf will have to manually edit it out. WBR, Sergei From kevink@paralogos.com Fri Dec 24 13:32:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Dec 2010 13:32:42 +0100 (CET) Received: from gateway13.websitewelcome.com ([69.41.255.6]:56427 "HELO gateway13.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491041Ab0LXMcj (ORCPT ); Fri, 24 Dec 2010 13:32:39 +0100 Received: (qmail 14377 invoked from network); 24 Dec 2010 12:31:44 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway13.websitewelcome.com with SMTP; 24 Dec 2010 12:31:44 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=bMCOdYk+LNHyzC9RtW5zbZbr0GPD9jzkvQ3bFM03X3NiuySiszFgtkEykgYD846rPzka34FR4+jWx18YlZFf7Qw6XziE2NeVZf28aqV4Q5L+boBHtPwzeieaVgSoa19P; Received: from [74.125.122.49] (port=10059 helo=kkissell-macbookpro.local) by gator750.hostgator.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1PW6oz-00068p-TP; Fri, 24 Dec 2010 06:32:34 -0600 Message-ID: <4D1492E0.5090407@paralogos.com> Date: Fri, 24 Dec 2010 04:32:32 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: STUART VENTERS CC: "Anoop P.A." , linux-mips@linux-mips.org, Anoop P A Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> In-Reply-To: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 2088 Lines: 68 Thank you, Stuart! I've spotted some definite breakage to SMTC between those versions. In arch/mips/include/asm/stackframe.h, someone moved the store of the Status register value in SAVE_SOME (line 169 or 204, depending on the version) from two instructions after the mfc0 to a point after the #ifdef for SMTC, presumably to get better pipelining of the register access. Unfortunately, the v1 register is also used in the SMTC-specific fragment to save TCStatus, so the Status value gets clobbered before it gets stored. This will eventually result in the Status register getting a TCStatus value, which has some bits on common, but isn't identical and sooner or later Bad Things will happen. I'm a little surprised this wasn't caught by visual inspection of the patch. Possible solutions would include reverting the store of the CP0_STATUS value to the block above the #ifdef, or, to retain whatever performance advantage was obtained by moving the store downward, to use v0/$2 instead of v1/$3, as the staging register for the TCStatus value. I'd lean toward the second option, but I'm not in a position to test and submit a patch just now. Regards, Kevin K. On 12/23/10 1:09 PM, STUART VENTERS wrote: > Kevin, > > I'm not sure if it's useful, > but finally I got the time to look at the two kernel versions Anoop pointed out. > works 2.6.32-stable with patch 804 > works_not 2.6.33-stable > > greping for files with CONFIG_MIPS_MT_SMTC > and looking for timer interrupt related stuff found the following differences: > > > arch/mips/include/asm/irq.h > arch/mips/kernel/irq.c > do_IRQ > > arch/mips/include/asm/stackframe.h > SAVE_SOME SAVE_TEMP get/set_saved_sp > > arch/mips/include/asm/time.h > clocksource_set_clock > > arch/mips/kernel/process.c > cpu_idle > > arch/mips/kernel/smtc.c > __irq_entry > ipi_decode > SMTC_CLOCK_TICK > > > Enclosed are the two subsets of files for a more expert look. > > I'll try to look in more detail after Christmas. > > > Cheers, > > Stuart > > > > From anoop.pa@gmail.com Fri Dec 24 15:30:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Dec 2010 15:30:53 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:50272 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491081Ab0LXOau (ORCPT ); Fri, 24 Dec 2010 15:30:50 +0100 Received: by gxk27 with SMTP id 27so3838311gxk.36 for ; Fri, 24 Dec 2010 06:30:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=A4nk52Jz8pr4arWTtEIM09MPPNDissjfKWbAXJuRmQU=; b=Y5DlpO1vbH/pJz8rcGGRi2NVx8nSe5JNmdzjj6tf/LBiOGBo1hvQQffx/GdWIlpEAU mXaYFSF7nuDRR1sIX2M/C7LWUnPY9OSBOvClKEy9cyK0Kz3BKaGIJbwxs24aqN3U5n2V ur9C7gnLm9ciV3HNPwKoISXekT67qn4cZGvHo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=eE4aFkMVHoHK9XxmfoDjjglXSgohHHzNev8NWvUIi5AJqUYm5VetZfrsiwAR4zMwOu 3g6DMQpT9OrLQxIsTBtYCVZKdAl+PNP492saxvMZxLIRKSWACKUl3SkH2/tkpGiQP8ea 2Ym41YpmWiNY3m7Yfp2kYMH8137fatddhR6kI= Received: by 10.90.219.8 with SMTP id r8mr853953agg.49.1293201039251; Fri, 24 Dec 2010 06:30:39 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id c7sm13881416ana.17.2010.12.24.06.30.35 (version=SSLv3 cipher=RC4-MD5); Fri, 24 Dec 2010 06:30:37 -0800 (PST) Subject: Re: SMTC support status in latest git head. From: Anoop P A To: "Kevin D. Kissell" Cc: STUART VENTERS , "Anoop P.A." , linux-mips@linux-mips.org In-Reply-To: <4D1492E0.5090407@paralogos.com> References: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> <4D1492E0.5090407@paralogos.com> Content-Type: text/plain; charset="UTF-8" Date: Fri, 24 Dec 2010 20:09:05 +0530 Message-ID: <1293201545.27661.55.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 2517 Lines: 84 Hi Kevin, Stuart , Woohooo You guys spotted !. http://git.linux-mips.org/?p=linux.git;a=commit;h=d5ec6e3c seems to be the culprit Once I restored previous version of stackframe.h 2.6.33-stable started booting !. Thanks, Anoop On Fri, 2010-12-24 at 04:32 -0800, Kevin D. Kissell wrote: > Thank you, Stuart! I've spotted some definite breakage to SMTC between > those versions. In arch/mips/include/asm/stackframe.h, someone moved > the store of the Status register value in SAVE_SOME (line 169 or 204, > depending on the version) from two instructions after the mfc0 to a > point after the #ifdef for SMTC, presumably to get better pipelining of > the register access. Unfortunately, the v1 register is also used in the > SMTC-specific fragment to save TCStatus, so the Status value gets > clobbered before it gets stored. This will eventually result in the > Status register getting a TCStatus value, which has some bits on common, > but isn't identical and sooner or later Bad Things will happen. > > I'm a little surprised this wasn't caught by visual inspection of the patch. > > Possible solutions would include reverting the store of the CP0_STATUS > value to the block above the #ifdef, or, to retain whatever performance > advantage was obtained by moving the store downward, to use v0/$2 > instead of v1/$3, as the staging register for the TCStatus value. I'd > lean toward the second option, but I'm not in a position to test and > submit a patch just now. > > Regards, > > Kevin K. > > On 12/23/10 1:09 PM, STUART VENTERS wrote: > > Kevin, > > > > I'm not sure if it's useful, > > but finally I got the time to look at the two kernel versions Anoop pointed out. > > works 2.6.32-stable with patch 804 > > works_not 2.6.33-stable > > > > greping for files with CONFIG_MIPS_MT_SMTC > > and looking for timer interrupt related stuff found the following differences: > > > > > > arch/mips/include/asm/irq.h > > arch/mips/kernel/irq.c > > do_IRQ > > > > arch/mips/include/asm/stackframe.h > > SAVE_SOME SAVE_TEMP get/set_saved_sp > > > > arch/mips/include/asm/time.h > > clocksource_set_clock > > > > arch/mips/kernel/process.c > > cpu_idle > > > > arch/mips/kernel/smtc.c > > __irq_entry > > ipi_decode > > SMTC_CLOCK_TICK > > > > > > Enclosed are the two subsets of files for a more expert look. > > > > I'll try to look in more detail after Christmas. > > > > > > Cheers, > > > > Stuart > > > > > > > > > From kevink@paralogos.com Fri Dec 24 15:54:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Dec 2010 15:54:30 +0100 (CET) Received: from gateway01.websitewelcome.com ([69.56.184.19]:55216 "HELO gateway01.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491081Ab0LXOy1 (ORCPT ); Fri, 24 Dec 2010 15:54:27 +0100 Received: (qmail 28759 invoked from network); 24 Dec 2010 14:53:35 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway01.websitewelcome.com with SMTP; 24 Dec 2010 14:53:35 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:X-Source:X-Source-Args:X-Source-Dir; b=PcPMLr8jqJhaYsVWgBIpjrvP8ufmMWLYnc04sq2rNTFRqg9jot3ZTZqlNfOGl2vrjjYXCRbWYgNV9h/31TpIbLn1LTIinYBWwLW7QKipou1sj3fDnxNl6YQZN+Wr4WnZ; Received: from [74.125.122.49] (port=35229 helo=kkissell-macbookpro.local) by gator750.hostgator.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1PW91f-0006XY-Ro; Fri, 24 Dec 2010 08:53:48 -0600 Message-ID: <4D14B3FA.5080304@paralogos.com> Date: Fri, 24 Dec 2010 06:53:46 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Anoop P A CC: STUART VENTERS , "Anoop P.A." , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> <4D1492E0.5090407@paralogos.com> <1293201545.27661.55.camel@paanoop1-desktop> In-Reply-To: <1293201545.27661.55.camel@paanoop1-desktop> Content-Type: multipart/mixed; boundary="------------060200050507040401000609" X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 3734 Lines: 111 This is a multi-part message in MIME format. --------------060200050507040401000609 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Excellent! Now, does the attached patch (relative to 2.6.37.11) also fix things, while preserving the other fixes and performance enhancements? /K. On 12/24/10 6:39 AM, Anoop P A wrote: > Hi Kevin, Stuart , > > Woohooo You guys spotted !. > > http://git.linux-mips.org/?p=linux.git;a=commit;h=d5ec6e3c seems to be > the culprit > > Once I restored previous version of stackframe.h 2.6.33-stable started > booting !. > > Thanks, > Anoop > > On Fri, 2010-12-24 at 04:32 -0800, Kevin D. Kissell wrote: >> Thank you, Stuart! I've spotted some definite breakage to SMTC between >> those versions. In arch/mips/include/asm/stackframe.h, someone moved >> the store of the Status register value in SAVE_SOME (line 169 or 204, >> depending on the version) from two instructions after the mfc0 to a >> point after the #ifdef for SMTC, presumably to get better pipelining of >> the register access. Unfortunately, the v1 register is also used in the >> SMTC-specific fragment to save TCStatus, so the Status value gets >> clobbered before it gets stored. This will eventually result in the >> Status register getting a TCStatus value, which has some bits on common, >> but isn't identical and sooner or later Bad Things will happen. >> >> I'm a little surprised this wasn't caught by visual inspection of the patch. >> >> Possible solutions would include reverting the store of the CP0_STATUS >> value to the block above the #ifdef, or, to retain whatever performance >> advantage was obtained by moving the store downward, to use v0/$2 >> instead of v1/$3, as the staging register for the TCStatus value. I'd >> lean toward the second option, but I'm not in a position to test and >> submit a patch just now. >> >> Regards, >> >> Kevin K. >> >> On 12/23/10 1:09 PM, STUART VENTERS wrote: >>> Kevin, >>> >>> I'm not sure if it's useful, >>> but finally I got the time to look at the two kernel versions Anoop pointed out. >>> works 2.6.32-stable with patch 804 >>> works_not 2.6.33-stable >>> >>> greping for files with CONFIG_MIPS_MT_SMTC >>> and looking for timer interrupt related stuff found the following differences: >>> >>> >>> arch/mips/include/asm/irq.h >>> arch/mips/kernel/irq.c >>> do_IRQ >>> >>> arch/mips/include/asm/stackframe.h >>> SAVE_SOME SAVE_TEMP get/set_saved_sp >>> >>> arch/mips/include/asm/time.h >>> clocksource_set_clock >>> >>> arch/mips/kernel/process.c >>> cpu_idle >>> >>> arch/mips/kernel/smtc.c >>> __irq_entry >>> ipi_decode >>> SMTC_CLOCK_TICK >>> >>> >>> Enclosed are the two subsets of files for a more expert look. >>> >>> I'll try to look in more detail after Christmas. >>> >>> >>> Cheers, >>> >>> Stuart >>> >>> >>> >>> > --------------060200050507040401000609 Content-Type: text/plain; x-mac-type="0"; x-mac-creator="0"; name="smtc_stackframe.h.patch" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smtc_stackframe.h.patch" LS0tIHN0YWNrZnJhbWUuaAkyMDEwLTEyLTI0IDA2OjQ3OjA2LjAwMDAwMDAwMCAtMDgwMAor Kysgc3RhY2tmcmFtZS5oLnRlc3QJMjAxMC0xMi0yNCAwNjo0ODo1Ni4wMDAwMDAwMDAgLTA4 MDAKQEAgLTE5NSw5ICsxOTUsOSBAQAogCQkgKiB0byBjb3ZlciB0aGUgcGlwZWxpbmUgZGVs YXkuCiAJCSAqLwogCQkuc2V0CW1pcHMzMgotCQltZmMwCXYxLCBDUDBfVENTVEFUVVMKKwkJ bWZjMAl2MCwgQ1AwX1RDU1RBVFVTCiAJCS5zZXQJbWlwczAKLQkJTE9OR19TCXYxLCBQVF9U Q1NUQVRVUyhzcCkKKwkJTE9OR19TCXYwLCBQVF9UQ1NUQVRVUyhzcCkKICNlbmRpZiAvKiBD T05GSUdfTUlQU19NVF9TTVRDICovCiAJCUxPTkdfUwkkNCwgUFRfUjQoc3ApCiAJCUxPTkdf UwkkNSwgUFRfUjUoc3ApCg== --------------060200050507040401000609-- From anoop.pa@gmail.com Fri Dec 24 16:53:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Dec 2010 16:53:58 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:64764 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491081Ab0LXPxy (ORCPT ); Fri, 24 Dec 2010 16:53:54 +0100 Received: by gyg4 with SMTP id 4so3313249gyg.36 for ; Fri, 24 Dec 2010 07:53:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=MeEKLCJKYi80D0bEPEuzNf2WNzhuYYtxczNCw1zcKc0=; b=AjxNo20ucZPThK5GqrnUu6acZpBghcIWyZR/ZIQPYagB7EfppfFX0y/q8H0kiebgl5 m9apou7JPd5lwDmG3S43MOlcwZs5jx1T9nWUtw3J/I9sSLl65BtDCGuLbNoIChhQqMy1 gU+CxyG4HOZbX8KVAernNUf6FOik0rU50IWhA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=SY6a3ClUHr/xrkhiRu4MgEVcu7HqSlsq3cIDKAWBkRpel8Y75fj2/yj19sUAMVmmA8 3phxngohVStcrh7TleVMkvHZlWzz4yhHRc8oQ8Kby1ikOD2CT4ANKuQWDq0eXpAyzjyb qBRj4/jwQWsL+/IJNpvERFhh8JKoV86KP5whc= Received: by 10.150.205.21 with SMTP id c21mr13662054ybg.368.1293206027118; Fri, 24 Dec 2010 07:53:47 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id v39sm10461219yba.19.2010.12.24.07.53.43 (version=SSLv3 cipher=RC4-MD5); Fri, 24 Dec 2010 07:53:46 -0800 (PST) Subject: Re: SMTC support status in latest git head. From: Anoop P A To: "Kevin D. Kissell" Cc: STUART VENTERS , "Anoop P.A." , linux-mips@linux-mips.org In-Reply-To: <4D14B3FA.5080304@paralogos.com> References: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> <4D1492E0.5090407@paralogos.com> <1293201545.27661.55.camel@paanoop1-desktop> <4D14B3FA.5080304@paralogos.com> Content-Type: text/plain; charset="UTF-8" Date: Fri, 24 Dec 2010 21:32:16 +0530 Message-ID: <1293206536.27661.63.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 3827 Lines: 123 On Fri, 2010-12-24 at 06:53 -0800, Kevin D. Kissell wrote: > Excellent! Now, does the attached patch (relative to 2.6.37.11) also > fix things, while preserving the other fixes and performance enhancements? > I have tested that patch with 2.6.37 branch it well passes calibration loop but hangs after switching to mips closource TC 6 going on-line as CPU 6 Brought up 7 CPUs bio: create slab at 0 SCSI subsystem initialized Switching to clocksource MIPS I Presume this is a different issue as restoring older file didn't help much to get rid of this hang. diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 58730c5..7fc9f10 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -195,9 +195,9 @@ * to cover the pipeline delay. */ .set mips32 - mfc0 v1, CP0_TCSTATUS + mfc0 v0, CP0_TCSTATUS .set mips0 - LONG_S v1, PT_TCSTATUS(sp) + LONG_S v0, PT_TCSTATUS(sp) #endif /* CONFIG_MIPS_MT_SMTC */ LONG_S $4, PT_R4(sp) LONG_S $5, PT_R5(sp) > /K. > > On 12/24/10 6:39 AM, Anoop P A wrote: > > Hi Kevin, Stuart , > > > > Woohooo You guys spotted !. > > > > http://git.linux-mips.org/?p=linux.git;a=commit;h=d5ec6e3c seems to be > > the culprit > > > > Once I restored previous version of stackframe.h 2.6.33-stable started > > booting !. > > > > Thanks, > > Anoop > > > > On Fri, 2010-12-24 at 04:32 -0800, Kevin D. Kissell wrote: > >> Thank you, Stuart! I've spotted some definite breakage to SMTC between > >> those versions. In arch/mips/include/asm/stackframe.h, someone moved > >> the store of the Status register value in SAVE_SOME (line 169 or 204, > >> depending on the version) from two instructions after the mfc0 to a > >> point after the #ifdef for SMTC, presumably to get better pipelining of > >> the register access. Unfortunately, the v1 register is also used in the > >> SMTC-specific fragment to save TCStatus, so the Status value gets > >> clobbered before it gets stored. This will eventually result in the > >> Status register getting a TCStatus value, which has some bits on common, > >> but isn't identical and sooner or later Bad Things will happen. > >> > >> I'm a little surprised this wasn't caught by visual inspection of the patch. > >> > >> Possible solutions would include reverting the store of the CP0_STATUS > >> value to the block above the #ifdef, or, to retain whatever performance > >> advantage was obtained by moving the store downward, to use v0/$2 > >> instead of v1/$3, as the staging register for the TCStatus value. I'd > >> lean toward the second option, but I'm not in a position to test and > >> submit a patch just now. > >> > >> Regards, > >> > >> Kevin K. > >> > >> On 12/23/10 1:09 PM, STUART VENTERS wrote: > >>> Kevin, > >>> > >>> I'm not sure if it's useful, > >>> but finally I got the time to look at the two kernel versions Anoop pointed out. > >>> works 2.6.32-stable with patch 804 > >>> works_not 2.6.33-stable > >>> > >>> greping for files with CONFIG_MIPS_MT_SMTC > >>> and looking for timer interrupt related stuff found the following differences: > >>> > >>> > >>> arch/mips/include/asm/irq.h > >>> arch/mips/kernel/irq.c > >>> do_IRQ > >>> > >>> arch/mips/include/asm/stackframe.h > >>> SAVE_SOME SAVE_TEMP get/set_saved_sp > >>> > >>> arch/mips/include/asm/time.h > >>> clocksource_set_clock > >>> > >>> arch/mips/kernel/process.c > >>> cpu_idle > >>> > >>> arch/mips/kernel/smtc.c > >>> __irq_entry > >>> ipi_decode > >>> SMTC_CLOCK_TICK > >>> > >>> > >>> Enclosed are the two subsets of files for a more expert look. > >>> > >>> I'll try to look in more detail after Christmas. > >>> > >>> > >>> Cheers, > >>> > >>> Stuart > >>> > >>> > >>> > >>> > > > From kevink@paralogos.com Sat Dec 25 00:34:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Dec 2010 00:34:31 +0100 (CET) Received: from gateway15.websitewelcome.com ([67.18.137.87]:43214 "HELO gateway15.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491098Ab0LXXe1 (ORCPT ); Sat, 25 Dec 2010 00:34:27 +0100 Received: (qmail 10294 invoked from network); 24 Dec 2010 23:34:30 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway15.websitewelcome.com with SMTP; 24 Dec 2010 23:34:30 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=h4675lkYmZ/Scntbz1255AsLG43RXH3tt9vjS8jME3aFnyx9kJnm/aGP3jhjz1RqFtMgSemlHc16QENZbg3ZvKv/A5NkwsUchxwvb5GsF+H7mK33BqpO+Uy7XG1R6nEH; Received: from [88.123.214.42] (port=49378 helo=kkissell-macbookpro.local) by gator750.hostgator.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1PWH9N-0005rY-ER; Fri, 24 Dec 2010 17:34:18 -0600 Message-ID: <4D152DFA.5090504@paralogos.com> Date: Fri, 24 Dec 2010 15:34:18 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Anoop P A CC: STUART VENTERS , "Anoop P.A." , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> <4D1492E0.5090407@paralogos.com> <1293201545.27661.55.camel@paanoop1-desktop> <4D14B3FA.5080304@paralogos.com> <1293206536.27661.63.camel@paanoop1-desktop> In-Reply-To: <1293206536.27661.63.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 4457 Lines: 135 Ah, well, at least we have a stackframe.h fix that preserves David's performance tweak for the deeper pipelined processors. In looking for this, I did notice that someone did some modification to the SMTC clock tick logic that I was skeptical had ever been tested. If you've still got that kernel binary handy, you might check to see if it boots with maxtcs=1 maxvpes=1, maxtcs=2 maxvpes=1, and/or maxtcs=2 maxvpes=2. Oh, yes, and Merry Christmas one and all! Regards, Kevin K. On 12/24/10 8:02 AM, Anoop P A wrote: > On Fri, 2010-12-24 at 06:53 -0800, Kevin D. Kissell wrote: >> Excellent! Now, does the attached patch (relative to 2.6.37.11) also >> fix things, while preserving the other fixes and performance enhancements? >> > I have tested that patch with 2.6.37 branch it well passes calibration > loop but hangs after switching to mips closource > > TC 6 going on-line as CPU 6 > Brought up 7 CPUs > bio: create slab at 0 > SCSI subsystem initialized > Switching to clocksource MIPS > > I Presume this is a different issue as restoring older file didn't help > much to get rid of this hang. > > diff --git a/arch/mips/include/asm/stackframe.h > b/arch/mips/include/asm/stackframe.h > index 58730c5..7fc9f10 100644 > --- a/arch/mips/include/asm/stackframe.h > +++ b/arch/mips/include/asm/stackframe.h > @@ -195,9 +195,9 @@ > * to cover the pipeline delay. > */ > .set mips32 > - mfc0 v1, CP0_TCSTATUS > + mfc0 v0, CP0_TCSTATUS > .set mips0 > - LONG_S v1, PT_TCSTATUS(sp) > + LONG_S v0, PT_TCSTATUS(sp) > #endif /* CONFIG_MIPS_MT_SMTC */ > LONG_S $4, PT_R4(sp) > LONG_S $5, PT_R5(sp) > > >> /K. >> >> On 12/24/10 6:39 AM, Anoop P A wrote: >>> Hi Kevin, Stuart , >>> >>> Woohooo You guys spotted !. >>> >>> http://git.linux-mips.org/?p=linux.git;a=commit;h=d5ec6e3c seems to be >>> the culprit >>> >>> Once I restored previous version of stackframe.h 2.6.33-stable started >>> booting !. >>> >>> Thanks, >>> Anoop >>> >>> On Fri, 2010-12-24 at 04:32 -0800, Kevin D. Kissell wrote: >>>> Thank you, Stuart! I've spotted some definite breakage to SMTC between >>>> those versions. In arch/mips/include/asm/stackframe.h, someone moved >>>> the store of the Status register value in SAVE_SOME (line 169 or 204, >>>> depending on the version) from two instructions after the mfc0 to a >>>> point after the #ifdef for SMTC, presumably to get better pipelining of >>>> the register access. Unfortunately, the v1 register is also used in the >>>> SMTC-specific fragment to save TCStatus, so the Status value gets >>>> clobbered before it gets stored. This will eventually result in the >>>> Status register getting a TCStatus value, which has some bits on common, >>>> but isn't identical and sooner or later Bad Things will happen. >>>> >>>> I'm a little surprised this wasn't caught by visual inspection of the patch. >>>> >>>> Possible solutions would include reverting the store of the CP0_STATUS >>>> value to the block above the #ifdef, or, to retain whatever performance >>>> advantage was obtained by moving the store downward, to use v0/$2 >>>> instead of v1/$3, as the staging register for the TCStatus value. I'd >>>> lean toward the second option, but I'm not in a position to test and >>>> submit a patch just now. >>>> >>>> Regards, >>>> >>>> Kevin K. >>>> >>>> On 12/23/10 1:09 PM, STUART VENTERS wrote: >>>>> Kevin, >>>>> >>>>> I'm not sure if it's useful, >>>>> but finally I got the time to look at the two kernel versions Anoop pointed out. >>>>> works 2.6.32-stable with patch 804 >>>>> works_not 2.6.33-stable >>>>> >>>>> greping for files with CONFIG_MIPS_MT_SMTC >>>>> and looking for timer interrupt related stuff found the following differences: >>>>> >>>>> >>>>> arch/mips/include/asm/irq.h >>>>> arch/mips/kernel/irq.c >>>>> do_IRQ >>>>> >>>>> arch/mips/include/asm/stackframe.h >>>>> SAVE_SOME SAVE_TEMP get/set_saved_sp >>>>> >>>>> arch/mips/include/asm/time.h >>>>> clocksource_set_clock >>>>> >>>>> arch/mips/kernel/process.c >>>>> cpu_idle >>>>> >>>>> arch/mips/kernel/smtc.c >>>>> __irq_entry >>>>> ipi_decode >>>>> SMTC_CLOCK_TICK >>>>> >>>>> >>>>> Enclosed are the two subsets of files for a more expert look. >>>>> >>>>> I'll try to look in more detail after Christmas. >>>>> >>>>> >>>>> Cheers, >>>>> >>>>> Stuart >>>>> >>>>> >>>>> >>>>> > From anoop.pa@gmail.com Sat Dec 25 08:23:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Dec 2010 08:23:54 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:42001 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491122Ab0LYHXu (ORCPT ); Sat, 25 Dec 2010 08:23:50 +0100 Received: by ywf7 with SMTP id 7so3593043ywf.36 for ; Fri, 24 Dec 2010 23:23:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=6P7v4hOeqJepBh74tFI9txKeiR5UkC3DhhTV/AXmm6w=; b=Jv+KL1C8YxA28ONuqGlezavaPdc8xBcfRKw2XQ10H+sZqu+gSJcstia//naidPf8Tq qcOcJ81ESlfHR17LRZCZZ641aOkNboYBgr9dC0biy2Pn7V02wym3zXDhcfBjaJU/oHkO UZyk6fyOXaskMCSzYLKIrvPjzgiw8cimttIHI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=gSC73ihWGYqAPsd4XZvuRjfMiJA1al0n5RJ1gFWC5dF1fO03F9nXb1vnwR7XTzklkC U/ZVGxp25tORd1HmHDQ2qVoqTkmmfPCeDi/8VUjXmXNlsmquBVreNOhav+GSDXqJ/eDl pZxHwIQairiC3OqiAFkL36IiwDS83tzxoWywE= Received: by 10.150.52.20 with SMTP id z20mr14857239ybz.193.1293261822957; Fri, 24 Dec 2010 23:23:42 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id q33sm7686006yba.7.2010.12.24.23.23.39 (version=SSLv3 cipher=RC4-MD5); Fri, 24 Dec 2010 23:23:41 -0800 (PST) Subject: Re: SMTC support status in latest git head. From: Anoop P A To: "Kevin D. Kissell" Cc: STUART VENTERS , "Anoop P.A." , linux-mips@linux-mips.org In-Reply-To: <4D152DFA.5090504@paralogos.com> References: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> <4D1492E0.5090407@paralogos.com> <1293201545.27661.55.camel@paanoop1-desktop> <4D14B3FA.5080304@paralogos.com> <1293206536.27661.63.camel@paanoop1-desktop> <4D152DFA.5090504@paralogos.com> Content-Type: text/plain; charset="UTF-8" Date: Sat, 25 Dec 2010 13:02:21 +0530 Message-ID: <1293262341.27661.188.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 5661 Lines: 172 On Fri, 2010-12-24 at 15:34 -0800, Kevin D. Kissell wrote: > Ah, well, at least we have a stackframe.h fix that preserves David's > performance tweak for the deeper pipelined processors. In looking for > this, I did notice that someone did some modification to the SMTC clock > tick logic that I was skeptical had ever been tested. If you've still > got that kernel binary handy, you might check to see if it boots with > maxtcs=1 maxvpes=1, maxtcs=2 maxvpes=1, and/or maxtcs=2 maxvpes=2. Yes I have tried with various combinations of tcs and vpes. with maxvpes=1 I can boot with a max of 4 TCS ( VPE0 has 4 TCs) . However setting maxpes=2 and maxtcs=2 hangs pretty early. Clock rate set to 600000000 console [ttyS0] enabled Calibrating delay loop... 398.33 BogoMIPS (lpj=796672) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 Limit of 2 VPEs set Limit of 2 TCs set TLB of 64 entry pairs shared by 2 VPEs VPE 0: TC 0, VPE 1: TC 1 IPI buffer pool of 32 buffers CPU revision is: 00019548 ((null)) TC 1 going on-line as CPU 1 Brought up 2 CPUs One strange observation is with maxtcs=3 and maxvpes=2 kernel boots all the way. Again with maxtcs=5 and maxvpes=2 it hangs after switching to MIPS clocksource. I strongly suspect some issue with locking. I will dig the code early next week. > > Oh, yes, and Merry Christmas one and all! Thank you ! .. Everybody Happy Christmas. > > Regards, > > Kevin K. > > On 12/24/10 8:02 AM, Anoop P A wrote: > > On Fri, 2010-12-24 at 06:53 -0800, Kevin D. Kissell wrote: > >> Excellent! Now, does the attached patch (relative to 2.6.37.11) also > >> fix things, while preserving the other fixes and performance enhancements? > >> > > I have tested that patch with 2.6.37 branch it well passes calibration > > loop but hangs after switching to mips closource > > > > TC 6 going on-line as CPU 6 > > Brought up 7 CPUs > > bio: create slab at 0 > > SCSI subsystem initialized > > Switching to clocksource MIPS > > > > I Presume this is a different issue as restoring older file didn't help > > much to get rid of this hang. > > > > diff --git a/arch/mips/include/asm/stackframe.h > > b/arch/mips/include/asm/stackframe.h > > index 58730c5..7fc9f10 100644 > > --- a/arch/mips/include/asm/stackframe.h > > +++ b/arch/mips/include/asm/stackframe.h > > @@ -195,9 +195,9 @@ > > * to cover the pipeline delay. > > */ > > .set mips32 > > - mfc0 v1, CP0_TCSTATUS > > + mfc0 v0, CP0_TCSTATUS > > .set mips0 > > - LONG_S v1, PT_TCSTATUS(sp) > > + LONG_S v0, PT_TCSTATUS(sp) > > #endif /* CONFIG_MIPS_MT_SMTC */ > > LONG_S $4, PT_R4(sp) > > LONG_S $5, PT_R5(sp) > > > > > >> /K. > >> > >> On 12/24/10 6:39 AM, Anoop P A wrote: > >>> Hi Kevin, Stuart , > >>> > >>> Woohooo You guys spotted !. > >>> > >>> http://git.linux-mips.org/?p=linux.git;a=commit;h=d5ec6e3c seems to be > >>> the culprit > >>> > >>> Once I restored previous version of stackframe.h 2.6.33-stable started > >>> booting !. > >>> > >>> Thanks, > >>> Anoop > >>> > >>> On Fri, 2010-12-24 at 04:32 -0800, Kevin D. Kissell wrote: > >>>> Thank you, Stuart! I've spotted some definite breakage to SMTC between > >>>> those versions. In arch/mips/include/asm/stackframe.h, someone moved > >>>> the store of the Status register value in SAVE_SOME (line 169 or 204, > >>>> depending on the version) from two instructions after the mfc0 to a > >>>> point after the #ifdef for SMTC, presumably to get better pipelining of > >>>> the register access. Unfortunately, the v1 register is also used in the > >>>> SMTC-specific fragment to save TCStatus, so the Status value gets > >>>> clobbered before it gets stored. This will eventually result in the > >>>> Status register getting a TCStatus value, which has some bits on common, > >>>> but isn't identical and sooner or later Bad Things will happen. > >>>> > >>>> I'm a little surprised this wasn't caught by visual inspection of the patch. > >>>> > >>>> Possible solutions would include reverting the store of the CP0_STATUS > >>>> value to the block above the #ifdef, or, to retain whatever performance > >>>> advantage was obtained by moving the store downward, to use v0/$2 > >>>> instead of v1/$3, as the staging register for the TCStatus value. I'd > >>>> lean toward the second option, but I'm not in a position to test and > >>>> submit a patch just now. > >>>> > >>>> Regards, > >>>> > >>>> Kevin K. > >>>> > >>>> On 12/23/10 1:09 PM, STUART VENTERS wrote: > >>>>> Kevin, > >>>>> > >>>>> I'm not sure if it's useful, > >>>>> but finally I got the time to look at the two kernel versions Anoop pointed out. > >>>>> works 2.6.32-stable with patch 804 > >>>>> works_not 2.6.33-stable > >>>>> > >>>>> greping for files with CONFIG_MIPS_MT_SMTC > >>>>> and looking for timer interrupt related stuff found the following differences: > >>>>> > >>>>> > >>>>> arch/mips/include/asm/irq.h > >>>>> arch/mips/kernel/irq.c > >>>>> do_IRQ > >>>>> > >>>>> arch/mips/include/asm/stackframe.h > >>>>> SAVE_SOME SAVE_TEMP get/set_saved_sp > >>>>> > >>>>> arch/mips/include/asm/time.h > >>>>> clocksource_set_clock > >>>>> > >>>>> arch/mips/kernel/process.c > >>>>> cpu_idle > >>>>> > >>>>> arch/mips/kernel/smtc.c > >>>>> __irq_entry > >>>>> ipi_decode > >>>>> SMTC_CLOCK_TICK > >>>>> > >>>>> > >>>>> Enclosed are the two subsets of files for a more expert look. > >>>>> > >>>>> I'll try to look in more detail after Christmas. > >>>>> > >>>>> > >>>>> Cheers, > >>>>> > >>>>> Stuart > >>>>> > >>>>> > >>>>> > >>>>> > > > From wuzhangjin@gmail.com Sat Dec 25 16:12:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Dec 2010 16:12:20 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:47179 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491136Ab0LYPMR (ORCPT ); Sat, 25 Dec 2010 16:12:17 +0100 Received: by pzk30 with SMTP id 30so1926006pzk.36 for ; Sat, 25 Dec 2010 07:12:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=mlzF2yGiJe7Ex74hpMfzqWU7t8RFy8FOL+eraui2WCs=; b=AuUqXlrrIcrO1DenJhp1iX+IP0izrwWdsnxBcebn460aMy4VPHYp2jLfgq4e20OxPW 0kBy4cvFhvJrJbxs412RJrzw31QWi8Cv46i4JV27Pb5kBlK9gLm0WDOl2kAOpoOoOhm8 YP6s3G5vj1LmV9xpPwO5+NNhOn1Y/vPEjMUU4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=HkGMB33rWjA0OZziyygQtvM0lQqQEt6HcmR3qm47QIDLoGyVnO02tXiAaYatG8+LP5 Xnf/hoEw9IlFLZuxCfRIW+2DZBjmAYyA0DOZ7cX16vrmY8DzBr9rQvrYhX9f1bHZhT+s lpu6zd12MwD1qtMWAW3l+//nuROo9YhEcpqw4= Received: by 10.142.128.18 with SMTP id a18mr8339323wfd.267.1293289929947; Sat, 25 Dec 2010 07:12:09 -0800 (PST) Received: from localhost.localdomain ([61.48.57.245]) by mx.google.com with ESMTPS id x35sm14223266wfd.1.2010.12.25.07.12.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 25 Dec 2010 07:12:08 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH] MIPS: Reduce kernel image size for !CONFIG_DEBUG_ZBOOT Date: Sat, 25 Dec 2010 23:11:49 +0800 Message-Id: <1293289909-7635-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1656 Lines: 47 !CONFIG_DEBUG_ZBOOT doesn't need puts() and puthex(), remove them and the according strings for !CONFIG_DEBUG_ZBOOT, as a result, it saves about 1280 bytes. Signed-off-by: Wu Zhangjin --- arch/mips/boot/compressed/Makefile | 3 ++- arch/mips/boot/compressed/decompress.c | 5 +++++ 2 files changed, 7 insertions(+), 1 deletions(-) diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index 5042d51..aab6d7f 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -28,9 +28,10 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o # decompressor objects (linked with vmlinuz) -vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o +vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o ifdef CONFIG_DEBUG_ZBOOT +vmlinuzobjs-y += $(obj)/dbg.o vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o endif diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c index 5cad0fa..c9cbff5 100644 --- a/arch/mips/boot/compressed/decompress.c +++ b/arch/mips/boot/compressed/decompress.c @@ -27,8 +27,13 @@ unsigned long free_mem_end_ptr; extern unsigned char __image_begin, __image_end; /* debug interfaces */ +#ifdef CONFIG_DEBUG_ZBOOT extern void puts(const char *s); extern void puthex(unsigned long long val); +#else +#define puts(s) do {} while (0) +#define puthex(val) do {} while (0) +#endif void error(char *x) { -- 1.7.1 From kevink@paralogos.com Sat Dec 25 16:17:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Dec 2010 16:17:13 +0100 (CET) Received: from gateway03.websitewelcome.com ([69.93.223.19]:35759 "HELO gateway03.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491136Ab0LYPRK (ORCPT ); Sat, 25 Dec 2010 16:17:10 +0100 Received: (qmail 4117 invoked from network); 25 Dec 2010 15:16:32 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway03.websitewelcome.com with SMTP; 25 Dec 2010 15:16:32 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=HMdMBmmMnDGtlJmyE4eiPzoHagsnMSwzAEGkeAdwVucEK/RwqfKv1ilMzpRBFhoTVk4K36jBwSueBDV2dpqm679d7aMEeaXCspMtDz0nHUJdEI6j1V9ETcNWFp/9JE2D; Received: from [88.123.214.42] (port=49651 helo=kkissell-macbookpro.local) by gator750.hostgator.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1PWVrk-0003HC-EM; Sat, 25 Dec 2010 09:17:05 -0600 Message-ID: <4D160AEF.7000203@paralogos.com> Date: Sat, 25 Dec 2010 07:17:03 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: Anoop P A CC: STUART VENTERS , "Anoop P.A." , linux-mips@linux-mips.org Subject: Re: SMTC support status in latest git head. References: <8F242B230AD6474C8E7815DE0B4982D7179FB88D@EXV1.corp.adtran.com> <4D1492E0.5090407@paralogos.com> <1293201545.27661.55.camel@paanoop1-desktop> <4D14B3FA.5080304@paralogos.com> <1293206536.27661.63.camel@paanoop1-desktop> <4D152DFA.5090504@paralogos.com> <1293262341.27661.188.camel@paanoop1-desktop> In-Reply-To: <1293262341.27661.188.camel@paanoop1-desktop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 2260 Lines: 51 On 12/24/10 11:32 PM, Anoop P A wrote: > On Fri, 2010-12-24 at 15:34 -0800, Kevin D. Kissell wrote: >> Ah, well, at least we have a stackframe.h fix that preserves David's >> performance tweak for the deeper pipelined processors. In looking for >> this, I did notice that someone did some modification to the SMTC clock >> tick logic that I was skeptical had ever been tested. If you've still >> got that kernel binary handy, you might check to see if it boots with >> maxtcs=1 maxvpes=1, maxtcs=2 maxvpes=1, and/or maxtcs=2 maxvpes=2. > Yes I have tried with various combinations of tcs and vpes. with > maxvpes=1 I can boot with a max of 4 TCS ( VPE0 has 4 TCs) . > However setting maxpes=2 and maxtcs=2 hangs pretty early. > > Clock rate set to 600000000 > console [ttyS0] enabled > Calibrating delay loop... 398.33 BogoMIPS (lpj=796672) > pid_max: default: 32768 minimum: 301 > Mount-cache hash table entries: 512 > Limit of 2 VPEs set > Limit of 2 TCs set > TLB of 64 entry pairs shared by 2 VPEs > VPE 0: TC 0, VPE 1: TC 1 > IPI buffer pool of 32 buffers > CPU revision is: 00019548 ((null)) > TC 1 going on-line as CPU 1 > Brought up 2 CPUs > > One strange observation is with maxtcs=3 and maxvpes=2 kernel boots all > the way. > > Again with maxtcs=5 and maxvpes=2 it hangs after switching to MIPS > clocksource. > > I strongly suspect some issue with locking. I will dig the code early > next week. If locking is screwed up, I'd expect more problems with 4 TC "CPUs" in the same VPE. It also suggests that the basic distribution via local low-latency IPI within a VPE is functioning, but that something is broken in the cross-VPE evengt propagation. I strongly suspect that your maxtcs=3, maxvpes=2 case would hang sooner or later, but by luck of the draw none of the init threads got scheduled on VPE 1 long enough to get stuck. I note that there were some changes made under the rubric "MIPS: SMTC: Avoid queueing multiple reschedule IPIs" in October and November of last year that make me nervous. I wouldn't have coded things that way myself, but they might be OK. Still, the first bisection I'd make if I was trouble-shooting this would be to roll back to just before they went in. Ho, ho, ho, Kevin K. From wuzhangjin@gmail.com Sat Dec 25 16:28:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Dec 2010 16:28:29 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:59064 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491139Ab0LYP2U (ORCPT ); Sat, 25 Dec 2010 16:28:20 +0100 Received: by pzk30 with SMTP id 30so1927532pzk.36 for ; Sat, 25 Dec 2010 07:28:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=ViCeubmsBbYQpPqahL4nCw5n6NxGkoeGK3FjmG3WztY=; b=syEKAMnZEnwaP3fjg3P2+mQ3ZnuHuE8GQVJnwDqzv80x3GsqZhn8n712zyhYyxZPFh elM+/+kEI1LUNiGMvQTP5rId9vY5PGLNPptFjqMHZwNw88cQ2llMhbepQHbeY/OoJ+cd +yzGp0QmkPBaHVrfK3A8dg7n+16gQPwJfiPps= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=quRB23f0b1/r93jgudsanSH8pG+taJfMTrSg/+nkzGFaPiOBo3GlFfHU6a1H2SpdZ9 RIWaJ6LacpUS3bA5kN5OK+W8DHHQ536vgPBPJ4y1mCIqocrQabLfuWpt5CPNpj+SdjZH aIz5CdFk7hc06T7SodwGK2rT9oPhYImLtcjhU= Received: by 10.142.221.17 with SMTP id t17mr8367187wfg.138.1293290893580; Sat, 25 Dec 2010 07:28:13 -0800 (PST) Received: from localhost.localdomain ([61.48.57.245]) by mx.google.com with ESMTPS id x18sm14239920wfa.23.2010.12.25.07.28.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 25 Dec 2010 07:28:12 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH] MIPS: Add current_cpu_prid() to optimize the code generation Date: Sat, 25 Dec 2010 23:27:56 +0800 Message-Id: <1293290876-11731-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 18170 Lines: 506 current_cpu_prid(), cpu_prid_comp(), cpu_prid_imp() and cpu_prid_rev() are added to simplify/beautify the c->processord_id related code, as a result, the code generation will be optimized. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/cpu-features.h | 6 ++- arch/mips/include/asm/cpu.h | 10 +++- .../asm/mach-loongson/cpu-feature-overrides.h | 12 ++++ arch/mips/kernel/cpu-probe.c | 60 +++++++++---------- arch/mips/kernel/time.c | 2 +- arch/mips/loongson/common/env.c | 4 +- arch/mips/loongson/common/platform.c | 4 +- arch/mips/mm/c-r4k.c | 7 +- arch/mips/mm/page.c | 2 +- arch/mips/mm/tlbex.c | 2 +- arch/mips/oprofile/op_model_mipsxx.c | 2 +- arch/mips/pci/pci-vr41xx.c | 2 +- arch/mips/vr41xx/common/init.c | 4 +- 13 files changed, 67 insertions(+), 50 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7..c4e1834 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -13,8 +13,12 @@ #include #include +#ifndef current_cpu_prid +#define current_cpu_prid() current_cpu_data.processor_id +#endif + #ifndef current_cpu_type -#define current_cpu_type() current_cpu_data.cputype +#define current_cpu_type() current_cpu_data.cputype #endif /* diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..df8b008 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -36,6 +36,8 @@ #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 +#define PRID_COMP_MASK 0xff0000 + /* * Assigned values for the product ID register. In order to detect a * certain CPU type exactly eventually additional registers may need to @@ -73,6 +75,7 @@ #define PRID_IMP_LOONGSON2 0x6300 #define PRID_IMP_UNKNOWN 0xff00 +#define PRID_IMP_MASK 0xff00 /* * These are the PRID's for when 23:16 == PRID_COMP_MIPS @@ -166,6 +169,12 @@ #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 +#define cpu_prid_comp() (current_cpu_prid() & PRID_COMP_MASK) +#define cpu_prid_imp() (current_cpu_prid() & PRID_IMP_MASK) +#define cpu_prid_rev() (current_cpu_prid() & PRID_REV_MASK) + +#define cpu_prid_encode(comp, imp, rev) ((comp) | (imp) | (rev)) + /* * Older processors used to encode processor version and revision in two * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores @@ -294,5 +303,4 @@ enum cpu_type_enum { #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ - #endif /* _ASM_CPU_H */ diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 675bd86..0fcf5ed 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -16,6 +16,18 @@ #ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H +#ifdef CONFIG_CPU_LOONGSON2 +#define cpu_prid_loongson2() \ + cpu_prid_encode(PRID_COMP_LEGACY, PRID_IMP_LOONGSON2, 0) + +#ifdef CONFIG_CPU_LOONGSON2F +#define current_cpu_prid() (cpu_prid_loongson2() | PRID_REV_LOONGSON2F) +#else /* CONFIG_CPU_LOONGSON2E */ +#define current_cpu_prid() (cpu_prid_loongson2() | PRID_REV_LOONGSON2E) +#endif + +#endif /* CONFIG_CPU_LOONGSON2 */ + #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 877155f..cb14f1e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -153,8 +153,6 @@ __setup("nodsp", dsp_disable); void __init check_wait(void) { - struct cpuinfo_mips *c = ¤t_cpu_data; - if (nowait) { printk("Wait instruction disabled.\n"); return; @@ -208,7 +206,7 @@ void __init check_wait(void) case CPU_74K: cpu_wait = r4k_wait; - if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) + if (cpu_prid_rev() >= PRID_REV_ENCODE_332(2, 1, 0)) cpu_wait = r4k_wait_irqoff; break; @@ -224,7 +222,7 @@ void __init check_wait(void) * WAIT on Rev2.0 and Rev3.0 has E16. * Rev3.1 WAIT is nop, why bother */ - if ((c->processor_id & 0xff) <= 0x64) + if (cpu_prid_rev() <= 0x64) break; /* @@ -237,7 +235,7 @@ void __init check_wait(void) */ break; case CPU_RM9000: - if ((c->processor_id & 0x00ff) >= 0x40) + if (cpu_prid_rev() >= 0x40) cpu_wait = r4k_wait; break; default: @@ -247,8 +245,6 @@ void __init check_wait(void) static inline void check_errata(void) { - struct cpuinfo_mips *c = ¤t_cpu_data; - switch (current_cpu_type()) { case CPU_34K: /* @@ -256,7 +252,7 @@ static inline void check_errata(void) * This code only handles VPE0, any SMP/SMTC/RTOS code * making use of VPE1 will be responsable for that VPE. */ - if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) + if (cpu_prid_rev() <= PRID_REV_34K_V1_0_2) write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); break; default: @@ -327,7 +323,7 @@ static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) { - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_R2000: c->cputype = CPU_R2000; __cpu_name[cpu] = "R2000"; @@ -339,7 +335,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->tlbsize = 64; break; case PRID_IMP_R3000: - if ((c->processor_id & 0xff) == PRID_REV_R3000A) { + if (cpu_prid_rev() == PRID_REV_R3000A) { if (cpu_has_confreg()) { c->cputype = CPU_R3081E; __cpu_name[cpu] = "R3081"; @@ -361,7 +357,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) break; case PRID_IMP_R4000: if (read_c0_config() & CONF_SC) { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) { + if (cpu_prid_rev() >= PRID_REV_R4400) { c->cputype = CPU_R4400PC; __cpu_name[cpu] = "R4400PC"; } else { @@ -369,7 +365,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R4000PC"; } } else { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) { + if (cpu_prid_rev() >= PRID_REV_R4400) { c->cputype = CPU_R4400SC; __cpu_name[cpu] = "R4400SC"; } else { @@ -385,7 +381,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->tlbsize = 48; break; case PRID_IMP_VR41XX: - switch (c->processor_id & 0xf0) { + switch (current_cpu_prid() & 0xf0) { case PRID_REV_VR4111: c->cputype = CPU_VR4111; __cpu_name[cpu] = "NEC VR4111"; @@ -395,7 +391,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "NEC VR4121"; break; case PRID_REV_VR4122: - if ((c->processor_id & 0xf) < 0x3) { + if ((current_cpu_prid() & 0xf) < 0x3) { c->cputype = CPU_VR4122; __cpu_name[cpu] = "NEC VR4122"; } else { @@ -404,7 +400,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) } break; case PRID_REV_VR4130: - if ((c->processor_id & 0xf) < 0x4) { + if ((current_cpu_prid() & 0xf) < 0x4) { c->cputype = CPU_VR4131; __cpu_name[cpu] = "NEC VR4131"; } else { @@ -457,12 +453,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; - if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { + if ((current_cpu_prid() & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; __cpu_name[cpu] = "TX3927"; c->tlbsize = 64; } else { - switch (c->processor_id & 0xff) { + switch (cpu_prid_rev()) { case PRID_REV_TX3912: c->cputype = CPU_TX3912; __cpu_name[cpu] = "TX3912"; @@ -489,7 +485,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R49XX"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_LLSC; - if (!(c->processor_id & 0x08)) + if (!(current_cpu_prid() & 0x08)) c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; c->tlbsize = 48; break; @@ -772,7 +768,7 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_4KC: c->cputype = CPU_4KC; __cpu_name[cpu] = "MIPS 4Kc"; @@ -824,11 +820,11 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: c->cputype = CPU_ALCHEMY; - switch ((c->processor_id >> 24) & 0xff) { + switch ((current_cpu_prid() >> 24) & 0xff) { case 0: __cpu_name[cpu] = "Au1000"; break; @@ -843,7 +839,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) break; case 4: __cpu_name[cpu] = "Au1200"; - if ((c->processor_id & 0xff) == 2) + if (cpu_prid_rev() == 2) __cpu_name[cpu] = "Au1250"; break; case 5: @@ -861,12 +857,12 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_SB1: c->cputype = CPU_SB1; __cpu_name[cpu] = "SiByte SB1"; /* FPU in pass1 is known to have issues. */ - if ((c->processor_id & 0xff) < 0x02) + if (cpu_prid_rev() < 0x02) c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); break; case PRID_IMP_SB1A: @@ -879,7 +875,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; __cpu_name[cpu] = "Sandcraft SR71000"; @@ -892,7 +888,7 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_PR4450: c->cputype = CPU_PR4450; __cpu_name[cpu] = "Philips PR4450"; @@ -904,7 +900,7 @@ static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_BMIPS32_REV4: case PRID_IMP_BMIPS32_REV8: c->cputype = CPU_BMIPS32; @@ -917,7 +913,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS3300"; break; case PRID_IMP_BMIPS43XX: { - int rev = c->processor_id & 0xff; + int rev = cpu_prid_rev(); if (rev >= PRID_REV_BMIPS4380_LO && rev <= PRID_REV_BMIPS4380_HI) { @@ -940,7 +936,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN31XX: case PRID_IMP_CAVIUM_CN30XX: @@ -975,7 +971,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) decode_configs(c); /* JZRISC does not implement the CP0 counter. */ c->options &= ~MIPS_CPU_COUNTER; - switch (c->processor_id & 0xff00) { + switch (cpu_prid_imp()) { case PRID_IMP_JZRISC: c->cputype = CPU_JZRISC; __cpu_name[cpu] = "Ingenic JZRISC"; @@ -1005,7 +1001,7 @@ __cpuinit void cpu_probe(void) c->cputype = CPU_UNKNOWN; c->processor_id = read_c0_prid(); - switch (c->processor_id & 0xff0000) { + switch (cpu_prid_comp()) { case PRID_COMP_LEGACY: cpu_probe_legacy(c, cpu); break; @@ -1081,7 +1077,7 @@ __cpuinit void cpu_report(void) struct cpuinfo_mips *c = ¤t_cpu_data; printk(KERN_INFO "CPU revision is: %08x (%s)\n", - c->processor_id, cpu_name_string()); + current_cpu_prid(), cpu_name_string()); if (c->options & MIPS_CPU_FPU) printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); } diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index fb74974..9d08a95 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -105,7 +105,7 @@ static __init int cpu_has_mfc0_count_bug(void) * The published errata for the R4400 upto 3.0 say the CPU * has the mfc0 from count bug. */ - if ((current_cpu_data.processor_id & 0xff) <= 0x30) + if (cpu_prid_rev() <= 0x30) return 1; /* diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c index 11b193f..7ad79b4 100644 --- a/arch/mips/loongson/common/env.c +++ b/arch/mips/loongson/common/env.c @@ -39,7 +39,6 @@ void __init prom_init_env(void) /* pmon passes arguments in 32bit pointers */ int *_prom_envp; unsigned long bus_clock; - unsigned int processor_id; long l; /* firmware arguments are initialized in head.S */ @@ -59,8 +58,7 @@ void __init prom_init_env(void) if (bus_clock == 0) bus_clock = 66000000; if (cpu_clock_freq == 0) { - processor_id = (¤t_cpu_data)->processor_id; - switch (processor_id & PRID_REV_MASK) { + switch (cpu_prid_rev()) { case PRID_REV_LOONGSON2E: cpu_clock_freq = 533080000; break; diff --git a/arch/mips/loongson/common/platform.c b/arch/mips/loongson/common/platform.c index ed007a2..8c79906 100644 --- a/arch/mips/loongson/common/platform.c +++ b/arch/mips/loongson/common/platform.c @@ -18,10 +18,8 @@ static struct platform_device loongson2_cpufreq_device = { static int __init loongson2_cpufreq_init(void) { - struct cpuinfo_mips *c = ¤t_cpu_data; - /* Only 2F revision and it's successors support CPUFreq */ - if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F) + if (cpu_prid_rev() >= PRID_REV_LOONGSON2F) return platform_device_register(&loongson2_cpufreq_device); return -ENODEV; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index e79fc25..d594c8a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -850,10 +850,11 @@ static void __cpuinit probe_pcache(void) write_c0_config(config & ~VR41_CONF_P4K); case CPU_VR4131: /* Workaround for cache instruction bug of VR4131 */ - if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || - c->processor_id == 0x0c82U) { + if (current_cpu_prid() == 0x0c80U || + current_cpu_prid() == 0x0c81U || + current_cpu_prid() == 0x0c82U) { config |= 0x00400000U; - if (c->processor_id == 0x0c80U) + if (current_cpu_prid() == 0x0c80U) config |= VR41_CONF_BP; write_c0_config(config); } else diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 36272f7..24cdc98 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -212,7 +212,7 @@ static void __cpuinit set_prefetch_parameters(void) * hints are broken. */ if (current_cpu_type() == CPU_SB1 && - (current_cpu_data.processor_id & 0xff) < 0x02) { + cpu_prid_rev() < 0x02) { pref_src_mode = Pref_Load; pref_dst_mode = Pref_Store; } else { diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 48191a4..cb9d53b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -74,7 +74,7 @@ static inline int __maybe_unused r10000_llsc_war(void) */ static int __cpuinit m4kc_tlbp_war(void) { - return (current_cpu_data.processor_id & 0xffff00) == + return (current_cpu_prid() & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_MIPS | PRID_IMP_4KC); } diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..8e74878 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -349,7 +349,7 @@ static int __init mipsxx_init(void) break; case CPU_R10000: - if ((current_cpu_data.processor_id & 0xff) == 0x20) + if (cpu_prid_rev() == 0x20) op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x"; else op_model_mipsxx_ops.cpu_type = "mips/r10000"; diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c index 5652571..94056bb 100644 --- a/arch/mips/pci/pci-vr41xx.c +++ b/arch/mips/pci/pci-vr41xx.c @@ -147,7 +147,7 @@ static int __init vr41xx_pciu_init(void) pciu_write(PCICLKSELREG, EQUAL_VTCLOCK); else if ((vtclock / 2) < pci_clock_max) pciu_write(PCICLKSELREG, HALF_VTCLOCK); - else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 && + else if (current_cpu_prid() >= PRID_VR4131_REV2_1 && (vtclock / 3) < pci_clock_max) pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK); else if ((vtclock / 4) < pci_clock_max) diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index 2391632..aca5c76 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -43,8 +43,8 @@ void __init plat_time_init(void) vr41xx_calculate_clock_frequency(); tclock = vr41xx_get_tclock_frequency(); - if (current_cpu_data.processor_id == PRID_VR4131_REV2_0 || - current_cpu_data.processor_id == PRID_VR4131_REV2_1) + if (current_cpu_prid() == PRID_VR4131_REV2_0 || + current_cpu_prid() == PRID_VR4131_REV2_1) mips_hpt_frequency = tclock / 2; else mips_hpt_frequency = tclock / 4; -- 1.7.1 From wuzhangjin@gmail.com Sat Dec 25 18:18:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Dec 2010 18:18:47 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:38954 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491141Ab0LYRSo (ORCPT ); Sat, 25 Dec 2010 18:18:44 +0100 Received: by wyf22 with SMTP id 22so7570327wyf.36 for ; Sat, 25 Dec 2010 09:18:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=gvFWB3qtNkfbl4ok3C1oNvCAiIlcDRf+WZ627HIo494=; b=vCQEyQRqZUyw7mfP/0KJPJQsFq8BMVsqVEg1I14YuLXIfPqlZbv4IgdJHS4lFunN2Y NkXxZxgSdxngzJ4pA/oBj8VY9MqpbbT8AVUQo17oNWFh9Eqku3fiKdz0JotKLekUG0tV 4vvnadCCRkpCZcXXJAA0WzdBxDlVT/qJ+FOpo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=KImrnIDfbybhOrwkaOtegknub48jvlpZUeszDvVaQeIwDOYqVP0gZ+ahRn5mIGfcBk 8p1L25Rsyew3f5OxLRW8LNNeT0EkwhFd3I3Js0M/C3PGbBgw7h2GzyAz6pv7w4+0Aja9 AuL+7lXD03y2N87maG6ak12ZRn7tY2a8ev/9A= MIME-Version: 1.0 Received: by 10.216.139.224 with SMTP id c74mr2526503wej.50.1293297518496; Sat, 25 Dec 2010 09:18:38 -0800 (PST) Received: by 10.216.131.88 with HTTP; Sat, 25 Dec 2010 09:18:38 -0800 (PST) In-Reply-To: <1293290876-11731-1-git-send-email-wuzhangjin@gmail.com> References: <1293290876-11731-1-git-send-email-wuzhangjin@gmail.com> Date: Sun, 26 Dec 2010 01:18:38 +0800 Message-ID: Subject: Re: [PATCH] MIPS: Add current_cpu_prid() to optimize the code generation From: wu zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 407 Lines: 12 Hi, Ralf The 2nd revision will be sent out with some enhancement and more comments, so, please ignore this one. Regards, Wu Zhangjin On Sat, Dec 25, 2010 at 11:27 PM, Wu Zhangjin wrote: > current_cpu_prid(), cpu_prid_comp(), cpu_prid_imp() and cpu_prid_rev() > are added to simplify/beautify the c->processord_id related code, as a > result, the code generation will be optimized. From wuzhangjin@gmail.com Sat Dec 25 18:40:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Dec 2010 18:40:34 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:57443 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491143Ab0LYRk1 (ORCPT ); Sat, 25 Dec 2010 18:40:27 +0100 Received: by pzk30 with SMTP id 30so1939180pzk.36 for ; Sat, 25 Dec 2010 09:40:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=7fhv/faPfgGKQnyUi3csjFWpHvAEStvE8QsFfJCL0AY=; b=BD37ZFrnwRf/5TXU4G30LoSH5To0iBwa4egwschU5Zy+vY4Wzw0v3xos1tkxgWyC+j vqJ3unwar4w8zv/XBMO+qysv4xzr8nwxN3sw2ZKvRWV1GnAyaGogoPTjq81ArrynJmMK Dj1HC323LBcnfPZXCLWX6uEM1YC8NBkJMCbI0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=nUmzsb7LTmRASs1BYuuwPdNDTynXiWA9ar40eWGQ3i/ewWZ/27InqxEjlmOGVDvd7z x1w9FOp1mKKRrCO8y8umaqPEDIe8WpXgZApahpKrmzzjeCX3GrMO46fPzJyQ3mz7mMrm MuCxguXn8NuREnfKRp3MuT5FJYFWaM/zCzdFU= Received: by 10.142.134.13 with SMTP id h13mr8365601wfd.315.1293298819550; Sat, 25 Dec 2010 09:40:19 -0800 (PST) Received: from localhost.localdomain ([61.48.57.245]) by mx.google.com with ESMTPS id v19sm14415197wfh.0.2010.12.25.09.40.13 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 25 Dec 2010 09:40:17 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [v2 PATCH] MIPS: Add current_cpu_prid() to optimize the code generation Date: Sun, 26 Dec 2010 01:40:02 +0800 Message-Id: <1293298802-12727-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 30155 Lines: 816 current_cpu_prid(), cpu_prid_comp(), cpu_prid_imp() and cpu_prid_rev() are added to simplify/beautify the processord_id related code. And if current_cpu_prid() is pre-encoded for the specific processor in cpu-feature-overrides.h, the code generation will be optimized. cpu_prid_encode() and cpu_prid_encode_copt() are added to encode the current_cpu_prid(), the former one can be used by most of the processors whose 'Company Options' part of the prid register is 0 or is not used by any of the existing codes. Or current_cpu_prid() can be simply assigned as the value of read_c0_prid(), which can be printed by the show_cpuinfo() defined in arch/mips/kernel/proc.c. The size of compressed kernel image(vmlinuz) can be reduced about 0.1M if current_cpu_prid() is pre-defined as a fixed value in cpu-feature-overrides.h. Signed-off-by: Wu Zhangjin --- arch/mips/alchemy/common/pci.c | 5 +- arch/mips/alchemy/common/setup.c | 2 +- arch/mips/alchemy/devboards/pb1000/board_setup.c | 5 +- arch/mips/bcm63xx/cpu.c | 2 +- arch/mips/cavium-octeon/setup.c | 2 +- arch/mips/include/asm/cpu-features.h | 6 ++- arch/mips/include/asm/cpu.h | 17 ++++++ arch/mips/include/asm/mach-au1x00/au1000.h | 6 +- .../asm/mach-loongson/cpu-feature-overrides.h | 14 +++++ arch/mips/kernel/cpu-probe.c | 56 ++++++++++---------- arch/mips/kernel/time.c | 2 +- arch/mips/kernel/traps.c | 2 +- arch/mips/loongson/common/env.c | 4 +- arch/mips/loongson/common/platform.c | 4 +- arch/mips/mipssim/sim_time.c | 2 +- arch/mips/mm/c-r4k.c | 19 +++---- arch/mips/mm/cerr-sb1.c | 2 +- arch/mips/mm/page.c | 5 +-- arch/mips/mm/tlbex.c | 2 +- arch/mips/mti-malta/malta-time.c | 2 +- arch/mips/oprofile/op_model_mipsxx.c | 2 +- arch/mips/pci/pci-vr41xx.c | 2 +- arch/mips/sgi-ip27/ip27-nmi.c | 2 +- arch/mips/sibyte/bcm1480/setup.c | 2 +- arch/mips/sibyte/sb1250/setup.c | 2 +- arch/mips/sni/setup.c | 2 +- arch/mips/vr41xx/common/init.c | 4 +- 27 files changed, 99 insertions(+), 76 deletions(-) diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c index 7866cf5..e086300 100644 --- a/arch/mips/alchemy/common/pci.c +++ b/arch/mips/alchemy/common/pci.c @@ -82,9 +82,8 @@ static int __init au1x_pci_setup(void) /* * Set the NC bit in controller for Au1500 pre-AC silicon */ - u32 prid = read_c0_prid(); - - if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) { + if (cpu_prid_copt() == 0x01000000 && + current_cpu_prid() < 0x01030202) { au_writel((1 << 16) | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG); printk(KERN_INFO "Non-coherent PCI accesses enabled\n"); diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 561e5da..451a9ea 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -46,7 +46,7 @@ void __init plat_mem_setup(void) est_freq = au1xxx_calc_clock(); est_freq += 5000; /* round */ est_freq -= est_freq % 10000; - printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(), + pr_info("(PRId %08x) @ %lu.%02lu MHz\n", current_cpu_prid(), est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); /* this is faster than wasting cycles trying to approximate it */ diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index f6540ec..8c7f375 100644 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c @@ -58,7 +58,6 @@ void __init board_setup(void) { u32 pin_func, static_cfg0; u32 sys_freqctrl, sys_clksrc; - u32 prid = read_c0_prid(); sys_freqctrl = 0; sys_clksrc = 0; @@ -87,7 +86,7 @@ void __init board_setup(void) sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); - switch (prid & 0x000000FF) { + switch (cpu_prid_rev()) { case 0x00: /* DA */ case 0x01: /* HA */ case 0x02: /* HB */ @@ -176,7 +175,7 @@ void __init board_setup(void) * Enable Au1000 BCLK switching - note: sed1356 must not use * its BCLK (Au1000 LCLK) for any timings */ - switch (prid & 0x000000FF) { + switch (cpu_prid_rev()) { case 0x00: /* DA */ case 0x01: /* HA */ case 0x02: /* HB */ diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 7c7e4d4..7bd5176 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -299,7 +299,7 @@ void __init bcm63xx_cpu_init(void) switch (c->cputype) { case CPU_BMIPS3300: - if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) { + if (cpu_prid_imp() == PRID_IMP_BMIPS3300_ALT) { expected_cpu_id = BCM6348_CPU_ID; bcm63xx_regs_base = bcm96348_regs_base; bcm63xx_irqs = bcm96348_irqs; diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index b0c3686..3c7de6d 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -276,7 +276,7 @@ const char *octeon_board_type_string(void) static char name[80]; sprintf(name, "%s (%s)", cvmx_board_type_to_string(octeon_bootinfo->board_type), - octeon_model_get_string(read_c0_prid())); + octeon_model_get_string(current_cpu_prid())); return name; } diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index ca400f7..c4e1834 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -13,8 +13,12 @@ #include #include +#ifndef current_cpu_prid +#define current_cpu_prid() current_cpu_data.processor_id +#endif + #ifndef current_cpu_type -#define current_cpu_type() current_cpu_data.cputype +#define current_cpu_type() current_cpu_data.cputype #endif /* diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 8687753..25d2eb4 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -22,6 +22,7 @@ that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 spec. */ +#define PRID_COPT_MASK 0xff000000 #define PRID_COMP_LEGACY 0x000000 #define PRID_COMP_MIPS 0x010000 @@ -36,6 +37,8 @@ #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 +#define PRID_COMP_MASK 0xff0000 + /* * Assigned values for the product ID register. In order to detect a * certain CPU type exactly eventually additional registers may need to @@ -73,6 +76,7 @@ #define PRID_IMP_LOONGSON2 0x6300 #define PRID_IMP_UNKNOWN 0xff00 +#define PRID_IMP_MASK 0xff00 /* * These are the PRID's for when 23:16 == PRID_COMP_MIPS @@ -166,6 +170,15 @@ #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 +#define cpu_prid_copt() (current_cpu_prid() & PRID_COPT_MASK) +#define cpu_prid_comp() (current_cpu_prid() & PRID_COMP_MASK) +#define cpu_prid_imp() (current_cpu_prid() & PRID_IMP_MASK) +#define cpu_prid_rev() (current_cpu_prid() & PRID_REV_MASK) + +#define cpu_prid_encode(comp, imp, rev) ((comp) | (imp) | (rev)) +#define cpu_prid_encode_copt(copt, comp, imp, rev) \ + ((copt) | cpu_prid_encode(comp, imp, rev)) + /* * Older processors used to encode processor version and revision in two * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores @@ -294,5 +307,9 @@ enum cpu_type_enum { #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ +#define cpu_is_r4600_v1_x() \ + ((current_cpu_prid() & 0xfffffff0) == 0x00002010) +#define cpu_is_r4600_v2_x() \ + ((current_cpu_prid() & 0xfffffff0) == 0x00002020) #endif /* _ASM_CPU_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index a697661..3de5493 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -94,7 +94,7 @@ static inline u32 au_readl(unsigned long reg) /* Early Au1000 have a write-only SYS_CPUPLL register. */ static inline int au1xxx_cpu_has_pll_wo(void) { - switch (read_c0_prid()) { + switch (current_cpu_prid()) { case 0x00030100: /* Au1000 DA */ case 0x00030201: /* Au1000 HA */ case 0x00030202: /* Au1000 HB */ @@ -111,7 +111,7 @@ static inline int au1xxx_cpu_needs_config_od(void) * early revisions of Alchemy SOCs. It disables the bus trans- * action overlapping and needs to be set to fix various errata. */ - switch (read_c0_prid()) { + switch (current_cpu_prid()) { case 0x00030100: /* Au1000 DA */ case 0x00030201: /* Au1000 HA */ case 0x00030202: /* Au1000 HB */ @@ -139,7 +139,7 @@ static inline int au1xxx_cpu_needs_config_od(void) static inline int alchemy_get_cputype(void) { - switch (read_c0_prid() & 0xffff0000) { + switch (cpu_prid_copt() | cpu_prid_comp()) { case 0x00030000: return ALCHEMY_CPU_AU1000; break; diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 675bd86..a941bcc 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -16,6 +16,20 @@ #ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H +#ifdef CONFIG_CPU_LOONGSON2 +#define cpu_prid_loongson2() \ + cpu_prid_encode(PRID_COMP_LEGACY, PRID_IMP_LOONGSON2, 0) + +#ifdef CONFIG_CPU_LOONGSON2F +#define current_cpu_prid() (cpu_prid_loongson2() | PRID_REV_LOONGSON2F) +#endif + +#ifdef CONFIG_CPU_LOONGSON2E +#define current_cpu_prid() (cpu_prid_loongson2() | PRID_REV_LOONGSON2E) +#endif + +#endif /* CONFIG_CPU_LOONGSON2 */ + #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 68dae7b..34cb533 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -208,7 +208,7 @@ void __init check_wait(void) case CPU_74K: cpu_wait = r4k_wait; - if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) + if (cpu_prid_rev() >= PRID_REV_ENCODE_332(2, 1, 0)) cpu_wait = r4k_wait_irqoff; break; @@ -224,7 +224,7 @@ void __init check_wait(void) * WAIT on Rev2.0 and Rev3.0 has E16. * Rev3.1 WAIT is nop, why bother */ - if ((c->pro