From glikely@secretlab.ca Mon Nov 1 06:17:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2010 06:17:50 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:46226 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491029Ab0KAFRm (ORCPT ); Mon, 1 Nov 2010 06:17:42 +0100 Received: by gxk25 with SMTP id 25so3222781gxk.36 for ; Sun, 31 Oct 2010 22:17:36 -0700 (PDT) Received: by 10.229.219.10 with SMTP id hs10mr14454945qcb.238.1288588656574; Sun, 31 Oct 2010 22:17:36 -0700 (PDT) Received: from angua ([12.157.84.6]) by mx.google.com with ESMTPS id x20sm1395919vcr.47.2010.10.31.22.17.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 31 Oct 2010 22:17:35 -0700 (PDT) Received: by angua (Postfix, from userid 1000) id 524FB3C00E5; Mon, 1 Nov 2010 05:17:34 +0000 (GMT) Date: Mon, 1 Nov 2010 01:17:34 -0400 From: Grant Likely To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Michal Simek , Benjamin Herrenschmidt , Wolfram Sang , Paul Mackerras , "David S. Miller" , Corey Minyard , Pantelis Antoniou , Vitaly Bordug , Anatolij Gustschin , John Rigby , Wolfgang Denk , Anton Vorontsov , Sandeep Gopalpet , Kumar Gala , Li Yang , Sergey Matyukevich , Jiri Pirko , Eric Dumazet , Sean MacLennan , Sadanand Mutyala , Andres Salomon , microblaze-uclinux@itee.uq.edu.au, linuxppc-dev@lists.ozlabs.org, netdev@vger.kernel.org Subject: Re: [PATCH] OF device tree: Move of_get_mac_address() to a common source file. Message-ID: <20101101051734.GB17587@angua.secretlab.ca> References: <1288130833-16421-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288130833-16421-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28281 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Tue, Oct 26, 2010 at 03:07:13PM -0700, David Daney wrote: > There are two identical implementations of of_get_mac_address(), one > each in arch/powerpc/kernel/prom_parse.c and > arch/microblaze/kernel/prom_parse.c. Move this function to a new > common file of_net.{c,h} and adjust all the callers to include the new > header. Applied, thanks; but made some changes to protect this code because it does not work on little endian (it can be fixed in a separate patch) Also... > > Signed-off-by: David Daney > Cc: Michal Simek > Cc: Grant Likely > Cc: Benjamin Herrenschmidt > Cc: Wolfram Sang > Cc: Paul Mackerras > Cc: "David S. Miller" > Cc: Corey Minyard > Cc: Pantelis Antoniou > Cc: Vitaly Bordug > Cc: Anatolij Gustschin > Cc: John Rigby > Cc: Wolfgang Denk > Cc: Anton Vorontsov > Cc: Sandeep Gopalpet > Cc: Kumar Gala > Cc: Li Yang > Cc: Sergey Matyukevich > Cc: Jiri Pirko > Cc: Eric Dumazet > Cc: Sean MacLennan > Cc: Sadanand Mutyala > Cc: Andres Salomon > Cc: microblaze-uclinux@itee.uq.edu.au > Cc: linux-kernel@vger.kernel.org > Cc: linuxppc-dev@lists.ozlabs.org > Cc: netdev@vger.kernel.org > Cc: devicetree-discuss@lists.ozlabs.org You don't need to believe everything that get_maintainers is telling you. When you get a large list like this, don't Cc everyone, but apply some educated guesses. You can guess that the PowerPC and Microblaze maintainers care because it touches their trees, and you can guess that I care because I'm the dt maintainer. David Miller isn't a bad guess because of networking. But 22 people is excessive. g. From sshtylyov@mvista.com Mon Nov 1 12:45:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2010 12:45:53 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:43816 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491176Ab0KALps (ORCPT ); Mon, 1 Nov 2010 12:45:48 +0100 Received: by ewy19 with SMTP id 19so2624885ewy.36 for ; Mon, 01 Nov 2010 04:45:47 -0700 (PDT) Received: by 10.213.31.73 with SMTP id x9mr2152489ebc.36.1288611947543; Mon, 01 Nov 2010 04:45:47 -0700 (PDT) Received: from [192.168.2.2] ([91.79.40.22]) by mx.google.com with ESMTPS id q58sm4124420eeh.21.2010.11.01.04.45.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Nov 2010 04:45:45 -0700 (PDT) Message-ID: <4CCEA800.9040500@mvista.com> Date: Mon, 01 Nov 2010 14:44:00 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 MIME-Version: 1.0 To: Grant Likely CC: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Jeremy Kerr , Benjamin Herrenschmidt , Dan Carpenter , Greg Kroah-Hartman Subject: Re: [PATCH] of: of_mdio: Fix some endianness problems. References: <1288227827-5447-1-git-send-email-ddaney@caviumnetworks.com> <20101030063237.GC2456@angua.secretlab.ca> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28282 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 31-10-2010 5:54, Grant Likely wrote: >>> In of_mdiobus_register(), the __be32 *addr variable is dereferenced. >>> This will not work on little-endian targets. Also since it is >>> unsigned, checking for less than zero is redundant. >>> Fix these two issues. >>> Signed-off-by: David Daney >>> Cc: Grant Likely >>> Cc: Jeremy Kerr >>> Cc: Benjamin Herrenschmidt >>> Cc: Dan Carpenter >>> Cc: Greg Kroah-Hartman >>> --- >>> drivers/of/of_mdio.c | 23 ++++++++++++++--------- >>> 1 files changed, 14 insertions(+), 9 deletions(-) >>> >>> diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c >>> index 1fce00e..b370306 100644 >>> --- a/drivers/of/of_mdio.c >>> +++ b/drivers/of/of_mdio.c >>> @@ -52,27 +52,32 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) >>> >>> /* Loop over the child nodes and register a phy_device for each one */ >>> for_each_child_of_node(np, child) { >>> - const __be32 *addr; >>> + const __be32 *paddr; >>> + u32 addr; >>> int len; >>> >>> /* A PHY must have a reg property in the range [0-31] */ >>> - addr = of_get_property(child, "reg",&len); >>> - if (!addr || len< sizeof(*addr) || *addr>= 32 || *addr< 0) { >>> + paddr = of_get_property(child, "reg",&len); >>> + if (!paddr || len< sizeof(*paddr)) { >>> +addr_err: >>> dev_err(&mdio->dev, "%s has invalid PHY address\n", >>> child->full_name); >>> continue; >>> } >>> + addr = be32_to_cpup(paddr); >>> + if (addr>= 32) >>> + goto addr_err; >> goto's are fine for jumping to the end of a function to unwind >> allocations, but please don't use it in this manner. The original >> structure will actually work just fine if you do it thusly: >> if (!paddr || len< sizeof(*paddr) || >> *(addr = be32_to_cpup(paddr))>= 32) { >> dev_err(&mdio->dev, "%s has invalid PHY address\n", >> child->full_name); >> continue; >> } >> Otherwise this patch looks good. After you've reworked and retested >> I'll pick it up for 2.6.37 (or dave will). > Actually, I mistyped this. I think it should be: > > if (!paddr || len< sizeof(*paddr) || > (addr = be32_to_cpup(paddr))>= 32) { This assignment would probably cause checkpatch.pl to complain... WBR, Sergei From timur.tabi@gmail.com Mon Nov 1 13:04:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2010 13:04:59 +0100 (CET) Received: from mail-gw0-f49.google.com ([74.125.83.49]:33047 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491176Ab0KAMEz convert rfc822-to-8bit (ORCPT ); Mon, 1 Nov 2010 13:04:55 +0100 Received: by gwj17 with SMTP id 17so3381863gwj.36 for ; Mon, 01 Nov 2010 05:04:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:sender:received :in-reply-to:references:from:date:x-google-sender-auth:message-id :subject:to:cc:content-type:content-transfer-encoding; bh=PgP/Hy6kcWCM86ih+3w/dsLcIKkxtCUdKKbZgi/C0fI=; b=iM/jZSpwjQPSTgrXdEKcDIDKzaVJumtDXdJUtvLPyPNExYW3CYVpyC3vk5gBoQX/kB CRoTYEv+qKo6OBCZ8oxyhdWb8qwfodr8knNnssga36ltzLvrhvM1eZU/uY2fp+EkwJad i/WSCs8hGyJ/eRMij3R2Jjdvhf+1UiC6v7Urg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type :content-transfer-encoding; b=hVFSDp4do5rTR1OTaLKFcHyjAVVBj+LBDoqd2TFToBuwqjpvRIpIOj83eFvtbejgGh lJcMrFKDqnt9ZR+ZmSspJJtUuzZmD8WZN638xrhCB/OD+Na/BJNTf0ssoj+r5qRNThEw wlqVzgmDjI3Qy5OpDxWquxrZNBc/GEMUfjdpM= Received: by 10.42.179.136 with SMTP id bq8mr272398icb.341.1288613087818; Mon, 01 Nov 2010 05:04:47 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.30.74 with HTTP; Mon, 1 Nov 2010 05:04:17 -0700 (PDT) In-Reply-To: <20101101051734.GB17587@angua.secretlab.ca> References: <1288130833-16421-1-git-send-email-ddaney@caviumnetworks.com> <20101101051734.GB17587@angua.secretlab.ca> From: Timur Tabi Date: Mon, 1 Nov 2010 07:04:17 -0500 X-Google-Sender-Auth: VI9oJ3aCdTzsbwYSyjoewVGYw3U Message-ID: Subject: Re: [PATCH] OF device tree: Move of_get_mac_address() to a common source file. To: Grant Likely Cc: David Daney , linux-mips@linux-mips.org, microblaze-uclinux@itee.uq.edu.au, devicetree-discuss@lists.ozlabs.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28283 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: timur@freescale.com Precedence: bulk X-list: linux-mips On Mon, Nov 1, 2010 at 12:17 AM, Grant Likely wrote: >> Signed-off-by: David Daney >> Cc: Michal Simek >> Cc: Grant Likely >> Cc: Benjamin Herrenschmidt >> Cc: Wolfram Sang >> Cc: Paul Mackerras >> Cc: "David S. Miller" >> Cc: Corey Minyard >> Cc: Pantelis Antoniou >> Cc: Vitaly Bordug >> Cc: Anatolij Gustschin >> Cc: John Rigby >> Cc: Wolfgang Denk >> Cc: Anton Vorontsov >> Cc: Sandeep Gopalpet >> Cc: Kumar Gala >> Cc: Li Yang >> Cc: Sergey Matyukevich >> Cc: Jiri Pirko >> Cc: Eric Dumazet >> Cc: Sean MacLennan >> Cc: Sadanand Mutyala >> Cc: Andres Salomon >> Cc: microblaze-uclinux@itee.uq.edu.au >> Cc: linux-kernel@vger.kernel.org >> Cc: linuxppc-dev@lists.ozlabs.org >> Cc: netdev@vger.kernel.org >> Cc: devicetree-discuss@lists.ozlabs.org > > You don't need to believe everything that get_maintainers is telling > you.  When you get a large list like this, don't Cc everyone, but > apply some educated guesses.  You can guess that the PowerPC and > Microblaze maintainers care because it touches their trees, and you > can guess that I care because I'm the dt maintainer. David Miller > isn't a bad guess because of networking.  But 22 people is excessive. And ironically, he left out the person who wrote the function -- me. -- Timur Tabi Linux kernel developer at Freescale From glikely@secretlab.ca Mon Nov 1 15:21:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2010 15:21:20 +0100 (CET) Received: from mail-gw0-f49.google.com ([74.125.83.49]:41506 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491193Ab0KAOVP convert rfc822-to-8bit (ORCPT ); Mon, 1 Nov 2010 15:21:15 +0100 Received: by gwj17 with SMTP id 17so3488429gwj.36 for ; Mon, 01 Nov 2010 07:21:09 -0700 (PDT) Received: by 10.151.46.14 with SMTP id y14mr25355761ybj.383.1288621269098; Mon, 01 Nov 2010 07:21:09 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.15.4 with HTTP; Mon, 1 Nov 2010 07:20:48 -0700 (PDT) In-Reply-To: <4CCEA800.9040500@mvista.com> References: <1288227827-5447-1-git-send-email-ddaney@caviumnetworks.com> <20101030063237.GC2456@angua.secretlab.ca> <4CCEA800.9040500@mvista.com> From: Grant Likely Date: Mon, 1 Nov 2010 10:20:48 -0400 X-Google-Sender-Auth: aJ_SFnkJBqV3HrgTGjomm8X0rdg Message-ID: Subject: Re: [PATCH] of: of_mdio: Fix some endianness problems. To: Sergei Shtylyov Cc: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Jeremy Kerr , Benjamin Herrenschmidt , Dan Carpenter , Greg Kroah-Hartman Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28284 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Mon, Nov 1, 2010 at 7:44 AM, Sergei Shtylyov wrote: > Hello. > > On 31-10-2010 5:54, Grant Likely wrote: > >>>> In of_mdiobus_register(), the __be32 *addr variable is dereferenced. >>>> This will not work on little-endian targets.  Also since it is >>>> unsigned, checking for less than zero is redundant. > >>>> Fix these two issues. > >>>> Signed-off-by: David Daney >>>> Cc: Grant Likely >>>> Cc: Jeremy Kerr >>>> Cc: Benjamin Herrenschmidt >>>> Cc: Dan Carpenter >>>> Cc: Greg Kroah-Hartman >>>> --- >>>>  drivers/of/of_mdio.c |   23 ++++++++++++++--------- >>>>  1 files changed, 14 insertions(+), 9 deletions(-) >>>> >>>> diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c >>>> index 1fce00e..b370306 100644 >>>> --- a/drivers/of/of_mdio.c >>>> +++ b/drivers/of/of_mdio.c >>>> @@ -52,27 +52,32 @@ int of_mdiobus_register(struct mii_bus *mdio, struct >>>> device_node *np) >>>> >>>>       /* Loop over the child nodes and register a phy_device for each >>>> one */ >>>>       for_each_child_of_node(np, child) { >>>> -             const __be32 *addr; >>>> +             const __be32 *paddr; >>>> +             u32 addr; >>>>               int len; >>>> >>>>               /* A PHY must have a reg property in the range [0-31] */ >>>> -             addr = of_get_property(child, "reg",&len); >>>> -             if (!addr || len<  sizeof(*addr) || *addr>= 32 || *addr< >>>>  0) { >>>> +             paddr = of_get_property(child, "reg",&len); >>>> +             if (!paddr || len<  sizeof(*paddr)) { >>>> +addr_err: >>>>                       dev_err(&mdio->dev, "%s has invalid PHY >>>> address\n", >>>>                               child->full_name); >>>>                       continue; >>>>               } >>>> +             addr = be32_to_cpup(paddr); >>>> +             if (addr>= 32) >>>> +                     goto addr_err; > >>> goto's are fine for jumping to the end of a function to unwind >>> allocations, but please don't use it in this manner.  The original >>> structure will actually work just fine if you do it thusly: > >>>                if (!paddr || len<  sizeof(*paddr) || >>>                    *(addr = be32_to_cpup(paddr))>= 32) { >>>                        dev_err(&mdio->dev, "%s has invalid PHY >>> address\n", >>>                                child->full_name); >>>                        continue; >>>                } > >>> Otherwise this patch looks good. After you've reworked and retested >>> I'll pick it up for 2.6.37 (or dave will). > >> Actually, I mistyped this.  I think it should be: >> >>                if (!paddr || len<  sizeof(*paddr) || >>                    (addr = be32_to_cpup(paddr))>= 32) { > >  This assignment would probably cause checkpatch.pl to complain... checkpatch isn't always right. Alternately, I'd also be okay with David's approach of splitting the tests into two if() blocks if without the goto... Actually, don't worry about it. I just merged David's patch and removed the goto myself in the process. g. From camm@maguirefamily.org Mon Nov 1 17:24:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2010 17:24:35 +0100 (CET) Received: from tvwna-ip-c-172.princeton.org ([66.180.187.89]:54320 "EHLO localhost.m.enhanced.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491200Ab0KAQYa (ORCPT ); Mon, 1 Nov 2010 17:24:30 +0100 Received: from camm by localhost.m.enhanced.com with local (Exim 4.69) (envelope-from ) id 1PCxB2-0000A9-S1; Mon, 01 Nov 2010 12:24:08 -0400 To: David Daney Cc: "Maciej W. Rozycki" , debian-mips@lists.debian.org, gcl-devel@gnu.org, Andreas Barth , linux-mips Subject: mips and ADDR_NO_RANDOMIZE References: <4C93993E.7030008@caviumnetworks.com> <8762y49k1k.fsf@maguirefamily.org> <4C93D86D.5090201@caviumnetworks.com> <87fwx4dwu5.fsf@maguirefamily.org> <4C97D9A1.7050102@caviumnetworks.com> <87lj6te9t1.fsf@maguirefamily.org> <4C9A8BC9.1020605@caviumnetworks.com> <4C9A9699.6080908@caviumnetworks.com> <87pqvbs7oa.fsf@maguirefamily.org> <4CB88D2C.8020900@caviumnetworks.com> <87r5fksxby.fsf_-_@maguirefamily.org> <4CBF1B1E.6050804@caviumnetworks.com> <8762wwlfen.fsf@maguirefamily.org> <4CC06826.2070508@caviumnetworks.com> <4CC0787C.2040902@caviumnetworks.com> <878w1m3qmn.fsf_-_@maguirefamily.org> <4CC5FA72.6080005@caviumnetworks.com> <4CC70DA9.6000906@caviumnetworks.com> From: Camm Maguire Date: Mon, 01 Nov 2010 12:24:08 -0400 In-Reply-To: <4CC70DA9.6000906@caviumnetworks.com> (David Daney's message of "Tue\, 26 Oct 2010 10\:19\:37 -0700") Message-ID: <87bp69811z.fsf_-_@maguirefamily.org> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28285 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: camm@maguirefamily.org Precedence: bulk X-list: linux-mips Greetings! Executing personality() with the ADDR_NO_RANDOMIZE bit set, and re-executing via execve, should yield a process with traditional contiguous brk() addresses appended to the .data segment, independent of the setting of sysctl kernel.randomize_va_space, right? At least this is the way the linux kernel has been working on x86 for many years. The latest Debian mips kernel is not honoring this setting. I'd like to know if this is a kernel bug. ============================================================================= h/unrandomize.h ============================================================================= #include #include #include #include #include { errno=0; { long pers = personality(0xffffffffUL); if (pers==-1) {printf("personality failure %d\n",errno);exit(-1);} if (!(pers & ADDR_NO_RANDOMIZE) && !getenv("GCL_UNRANDOMIZE")) { errno=0; if (personality(pers | ADDR_NO_RANDOMIZE) != -1 && personality(0xffffffffUL) & ADDR_NO_RANDOMIZE) { int i; char **n; for (i=0;envp[i];i++); n=alloca((i+2)*sizeof(*n)); n[i+1]=0; n[i--]="GCL_UNRANDOMIZE=t"; for (;i>=0;i--) n[i]=envp[i]; #ifdef GCL_GPROF gprof_cleanup(); #endif errno=0; execve(*argv,argv,n); printf("execve failure %d\n",errno); exit(-1); } else { printf("personality change failure %d\n",errno); exit(-1); } } } } ============================================================================= f.c ============================================================================= #include void gprof_cleanup() {}; int main(int argc,char * argv[],char * envp[]) { FILE *f; #include "h/unrandomize.h" if (!(f=fopen("conftest1","w"))) return -1; fprintf(f,"%u",sbrk(0)); return 0;} ============================================================================= ./f && cat conftest1 && echo && ./f && cat conftest1 10043392 10584064 ============================================================================= strace -f ./f ============================================================================= execve("./f", ["./f"], [/* 16 vars */]) = 0 brk(0) = 0x7a4000 old_mmap(NULL, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2b938000 uname({sys="Linux", node="phrixos", ...}) = 0 access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) open("/etc/ld.so.cache", O_RDONLY) = 3 fstat64(3, {st_mode=S_IFREG|0644, st_size=16547, ...}) = 0 old_mmap(NULL, 16547, PROT_READ, MAP_PRIVATE, 3, 0) = 0x2b93c000 close(3) = 0 access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) open("/lib/libc.so.6", O_RDONLY) = 3 read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\10\0\1\0\0\0\24s\1\0004\0\0\0"..., 512) = 512 lseek(3, 760, SEEK_SET) = 760 read(3, "\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\22\0\0\0", 32) = 32 fstat64(3, {st_mode=S_IFREG|0755, st_size=1594664, ...}) = 0 old_mmap(NULL, 1576560, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x2b948000 mprotect(0x2baac000, 49152, PROT_NONE) = 0 old_mmap(0x2bab8000, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x160000) = 0x2bab8000 old_mmap(0x2bac8000, 3696, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x2bac8000 close(3) = 0 set_thread_area(0x2b940ad0) = 0 mprotect(0x2bab8000, 49152, PROT_READ) = 0 munmap(0x2b93c000, 16547) = 0 personality(0xffffffff /* PER_??? */) = 0 personality(0x40000 /* PER_??? */) = 0 personality(0xffffffff /* PER_??? */) = 262144 execve("./f", ["./f"], [/* 17 vars */]) = 0 brk(0) = 0x670000 old_mmap(NULL, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2ba70000 uname({sys="Linux", node="phrixos", ...}) = 0 access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) open("/etc/ld.so.cache", O_RDONLY) = 3 fstat64(3, {st_mode=S_IFREG|0644, st_size=16547, ...}) = 0 old_mmap(NULL, 16547, PROT_READ, MAP_PRIVATE, 3, 0) = 0x2ba74000 close(3) = 0 access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) open("/lib/libc.so.6", O_RDONLY) = 3 read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\10\0\1\0\0\0\24s\1\0004\0\0\0"..., 512) = 512 lseek(3, 760, SEEK_SET) = 760 read(3, "\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\22\0\0\0", 32) = 32 fstat64(3, {st_mode=S_IFREG|0755, st_size=1594664, ...}) = 0 old_mmap(NULL, 1576560, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x2ba80000 mprotect(0x2bbe4000, 49152, PROT_NONE) = 0 old_mmap(0x2bbf0000, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x160000) = 0x2bbf0000 old_mmap(0x2bc00000, 3696, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x2bc00000 close(3) = 0 set_thread_area(0x2ba78ad0) = 0 mprotect(0x2bbf0000, 49152, PROT_READ) = 0 munmap(0x2ba74000, 16547) = 0 personality(0xffffffff /* PER_??? */) = 0 brk(0) = 0x670000 brk(0x694000) = 0x694000 open("conftest1", O_WRONLY|O_CREAT|O_TRUNC, 0666) = 3 fstat64(3, {st_mode=S_IFREG|0644, st_size=0, ...}) = 0 old_mmap(NULL, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2bc04000 write(3, "6897664", 7) = 7 exit_group(0) = ? ============================================================================= uname -a ============================================================================= Linux phrixos 2.6.36-rc6-loongson-2f #1 Mon Oct 4 20:36:22 UTC 2010 mips64 GNU/Linux ============================================================================= /proc/cpuinfo ============================================================================= system type : lemote-fuloong-2f-box processor : 0 cpu model : ICT Loongson-2 V0.3 FPU V0.1 BogoMIPS : 528.38 wait instruction : yes microsecond timers : yes tlb_entries : 64 extra interrupt vector : no hardware watchpoint : yes, count: 0, address/irw mask: [] ASEs implemented : shadow register sets : 1 core : 0 VCED exceptions : not available VCEI exceptions : not available ============================================================================= Take care, -- Camm Maguire camm@maguirefamily.org ========================================================================== "The earth is but one country, and mankind its citizens." -- Baha'u'llah From David.Daney@caviumnetworks.com Mon Nov 1 19:06:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2010 19:06:22 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4040 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491204Ab0KASGT (ORCPT ); Mon, 1 Nov 2010 19:06:19 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 01 Nov 2010 11:06:53 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 1 Nov 2010 11:06:48 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 1 Nov 2010 11:06:48 -0700 Message-ID: <4CCF0197.2030407@caviumnetworks.com> Date: Mon, 01 Nov 2010 11:06:15 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.12) Gecko/20100907 Fedora/3.0.7-1.fc12 Thunderbird/3.0.7 MIME-Version: 1.0 To: Camm Maguire CC: "Maciej W. Rozycki" , debian-mips@lists.debian.org, gcl-devel@gnu.org, Andreas Barth , linux-mips Subject: Re: mips and ADDR_NO_RANDOMIZE References: <4C93993E.7030008@caviumnetworks.com> <8762y49k1k.fsf@maguirefamily.org> <4C93D86D.5090201@caviumnetworks.com> <87fwx4dwu5.fsf@maguirefamily.org> <4C97D9A1.7050102@caviumnetworks.com> <87lj6te9t1.fsf@maguirefamily.org> <4C9A8BC9.1020605@caviumnetworks.com> <4C9A9699.6080908@caviumnetworks.com> <87pqvbs7oa.fsf@maguirefamily.org> <4CB88D2C.8020900@caviumnetworks.com> <87r5fksxby.fsf_-_@maguirefamily.org> <4CBF1B1E.6050804@caviumnetworks.com> <8762wwlfen.fsf@maguirefamily.org> <4CC06826.2070508@caviumnetworks.com> <4CC0787C.2040902@caviumnetworks.com> <878w1m3qmn.fsf_-_@maguirefamily.org> <4CC5FA72.6080005@caviumnetworks.com> <4CC70DA9.6000906@caviumnetworks.com> <87bp69811z.fsf_-_@maguirefamily.org> In-Reply-To: <87bp69811z.fsf_-_@maguirefamily.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Nov 2010 18:06:48.0309 (UTC) FILETIME=[8D305250:01CB79EF] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28286 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 11/01/2010 09:24 AM, Camm Maguire wrote: > Greetings! Executing personality() with the ADDR_NO_RANDOMIZE bit set, > and re-executing via execve, should yield a process with traditional > contiguous brk() addresses appended to the .data segment, independent > of the setting of sysctl kernel.randomize_va_space, right? At least > this is the way the linux kernel has been working on x86 for many > years. > > The latest Debian mips kernel is not honoring this setting. I'd like > to know if this is a kernel bug. > For things like this, we need to know what kind of kernel it is. Is it a 64-bit kernel running a 32-bit application? I am going to guess that it is. The 32-bit sys_personality wrapper in the kernel looks incorrect. But It should probably still work, to set ADDR_NO_RANDOMIZE, so I don't really know where it is going off track yet. Having implemented the randomization, I would like to see it work correctly, so I guess I will look at it. You seem to have a certain knack for uncovering obscure bugs. David Daney > ============================================================================= > h/unrandomize.h > ============================================================================= > #include > #include > #include > #include > #include > > > { > errno=0; > > { > > long pers = personality(0xffffffffUL); > if (pers==-1) {printf("personality failure %d\n",errno);exit(-1);} > if (!(pers& ADDR_NO_RANDOMIZE)&& !getenv("GCL_UNRANDOMIZE")) { > errno=0; > if (personality(pers | ADDR_NO_RANDOMIZE) != -1&& personality(0xffffffffUL)& ADDR_NO_RANDOMIZE) { > int i; > char **n; > for (i=0;envp[i];i++); > n=alloca((i+2)*sizeof(*n)); > n[i+1]=0; > n[i--]="GCL_UNRANDOMIZE=t"; > for (;i>=0;i--) > n[i]=envp[i]; > #ifdef GCL_GPROF > gprof_cleanup(); > #endif > errno=0; > execve(*argv,argv,n); > printf("execve failure %d\n",errno); > exit(-1); > } else { > printf("personality change failure %d\n",errno); > exit(-1); > } > } > } > } > ============================================================================= > f.c > ============================================================================= > #include > void gprof_cleanup() {}; > int main(int argc,char * argv[],char * envp[]) { > FILE *f; > > #include "h/unrandomize.h" > > if (!(f=fopen("conftest1","w"))) return -1; > fprintf(f,"%u",sbrk(0)); > return 0;} > ============================================================================= > ./f&& cat conftest1&& echo&& ./f&& cat conftest1 > 10043392 > 10584064 > ============================================================================= > strace -f ./f > ============================================================================= > execve("./f", ["./f"], [/* 16 vars */]) = 0 > brk(0) = 0x7a4000 > old_mmap(NULL, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2b938000 > uname({sys="Linux", node="phrixos", ...}) = 0 > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) > access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) > open("/etc/ld.so.cache", O_RDONLY) = 3 > fstat64(3, {st_mode=S_IFREG|0644, st_size=16547, ...}) = 0 > old_mmap(NULL, 16547, PROT_READ, MAP_PRIVATE, 3, 0) = 0x2b93c000 > close(3) = 0 > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) > open("/lib/libc.so.6", O_RDONLY) = 3 > read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\10\0\1\0\0\0\24s\1\0004\0\0\0"..., 512) = 512 > lseek(3, 760, SEEK_SET) = 760 > read(3, "\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\22\0\0\0", 32) = 32 > fstat64(3, {st_mode=S_IFREG|0755, st_size=1594664, ...}) = 0 > old_mmap(NULL, 1576560, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x2b948000 > mprotect(0x2baac000, 49152, PROT_NONE) = 0 > old_mmap(0x2bab8000, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x160000) = 0x2bab8000 > old_mmap(0x2bac8000, 3696, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x2bac8000 > close(3) = 0 > set_thread_area(0x2b940ad0) = 0 > mprotect(0x2bab8000, 49152, PROT_READ) = 0 > munmap(0x2b93c000, 16547) = 0 > personality(0xffffffff /* PER_??? */) = 0 > personality(0x40000 /* PER_??? */) = 0 > personality(0xffffffff /* PER_??? */) = 262144 > execve("./f", ["./f"], [/* 17 vars */]) = 0 > brk(0) = 0x670000 > old_mmap(NULL, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2ba70000 > uname({sys="Linux", node="phrixos", ...}) = 0 > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) > access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) > open("/etc/ld.so.cache", O_RDONLY) = 3 > fstat64(3, {st_mode=S_IFREG|0644, st_size=16547, ...}) = 0 > old_mmap(NULL, 16547, PROT_READ, MAP_PRIVATE, 3, 0) = 0x2ba74000 > close(3) = 0 > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) > open("/lib/libc.so.6", O_RDONLY) = 3 > read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\10\0\1\0\0\0\24s\1\0004\0\0\0"..., 512) = 512 > lseek(3, 760, SEEK_SET) = 760 > read(3, "\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\22\0\0\0", 32) = 32 > fstat64(3, {st_mode=S_IFREG|0755, st_size=1594664, ...}) = 0 > old_mmap(NULL, 1576560, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x2ba80000 > mprotect(0x2bbe4000, 49152, PROT_NONE) = 0 > old_mmap(0x2bbf0000, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x160000) = 0x2bbf0000 > old_mmap(0x2bc00000, 3696, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x2bc00000 > close(3) = 0 > set_thread_area(0x2ba78ad0) = 0 > mprotect(0x2bbf0000, 49152, PROT_READ) = 0 > munmap(0x2ba74000, 16547) = 0 > personality(0xffffffff /* PER_??? */) = 0 > brk(0) = 0x670000 > brk(0x694000) = 0x694000 > open("conftest1", O_WRONLY|O_CREAT|O_TRUNC, 0666) = 3 > fstat64(3, {st_mode=S_IFREG|0644, st_size=0, ...}) = 0 > old_mmap(NULL, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2bc04000 > write(3, "6897664", 7) = 7 > exit_group(0) = ? > ============================================================================= > uname -a > ============================================================================= > Linux phrixos 2.6.36-rc6-loongson-2f #1 Mon Oct 4 20:36:22 UTC 2010 > mips64 GNU/Linux > ============================================================================= > /proc/cpuinfo > ============================================================================= > system type : lemote-fuloong-2f-box > processor : 0 > cpu model : ICT Loongson-2 V0.3 FPU V0.1 > BogoMIPS : 528.38 > wait instruction : yes > microsecond timers : yes > tlb_entries : 64 > extra interrupt vector : no > hardware watchpoint : yes, count: 0, address/irw mask: [] > ASEs implemented : > shadow register sets : 1 > core : 0 > VCED exceptions : not available > VCEI exceptions : not available > ============================================================================= > > Take care, From camm@maguirefamily.org Mon Nov 1 19:25:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2010 19:25:16 +0100 (CET) Received: from tvwna-ip-c-172.princeton.org ([66.180.187.89]:37897 "EHLO localhost.m.enhanced.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491207Ab0KASZM (ORCPT ); Mon, 1 Nov 2010 19:25:12 +0100 Received: from camm by localhost.m.enhanced.com with local (Exim 4.69) (envelope-from ) id 1PCz3r-0003eM-Dz; Mon, 01 Nov 2010 14:24:51 -0400 To: David Daney Cc: "Maciej W. Rozycki" , debian-mips@lists.debian.org, gcl-devel@gnu.org, Andreas Barth , linux-mips Subject: Re: mips and ADDR_NO_RANDOMIZE References: <8762y49k1k.fsf@maguirefamily.org> <4C93D86D.5090201@caviumnetworks.com> <87fwx4dwu5.fsf@maguirefamily.org> <4C97D9A1.7050102@caviumnetworks.com> <87lj6te9t1.fsf@maguirefamily.org> <4C9A8BC9.1020605@caviumnetworks.com> <4C9A9699.6080908@caviumnetworks.com> <87pqvbs7oa.fsf@maguirefamily.org> <4CB88D2C.8020900@caviumnetworks.com> <87r5fksxby.fsf_-_@maguirefamily.org> <4CBF1B1E.6050804@caviumnetworks.com> <8762wwlfen.fsf@maguirefamily.org> <4CC06826.2070508@caviumnetworks.com> <4CC0787C.2040902@caviumnetworks.com> <878w1m3qmn.fsf_-_@maguirefamily.org> <4CC5FA72.6080005@caviumnetworks.com> <4CC70DA9.6000906@caviumnetworks.com> <87bp69811z.fsf_-_@maguirefamily.org> <4CCF0197.2030407@caviumnetworks.com> From: Camm Maguire Date: Mon, 01 Nov 2010 14:24:51 -0400 In-Reply-To: <4CCF0197.2030407@caviumnetworks.com> (David Daney's message of "Mon\, 01 Nov 2010 11\:06\:15 -0700") Message-ID: <87bp68x5os.fsf@maguirefamily.org> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28287 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: camm@maguirefamily.org Precedence: bulk X-list: linux-mips Greetings! David Daney writes: > On 11/01/2010 09:24 AM, Camm Maguire wrote: >> Greetings! Executing personality() with the ADDR_NO_RANDOMIZE bit set, >> and re-executing via execve, should yield a process with traditional >> contiguous brk() addresses appended to the .data segment, independent >> of the setting of sysctl kernel.randomize_va_space, right? At least >> this is the way the linux kernel has been working on x86 for many >> years. >> >> The latest Debian mips kernel is not honoring this setting. I'd like >> to know if this is a kernel bug. >> > > For things like this, we need to know what kind of kernel it is. Is > it a 64-bit kernel running a 32-bit application? > The kernel is Debian 2.6.36-rc6-loongson-2f. Does this suffice? > I am going to guess that it is. > > The 32-bit sys_personality wrapper in the kernel looks incorrect. But > It should probably still work, to set ADDR_NO_RANDOMIZE, so I don't > really know where it is going off track yet. > > Having implemented the randomization, I would like to see it work > correctly, so I guess I will look at it. > Thanks so much! > You seem to have a certain knack for uncovering obscure bugs. > :-) Take care, > David Daney > >> ============================================================================= >> h/unrandomize.h >> ============================================================================= >> #include >> #include >> #include >> #include >> #include >> >> >> { >> errno=0; >> >> { >> >> long pers = personality(0xffffffffUL); >> if (pers==-1) {printf("personality failure %d\n",errno);exit(-1);} >> if (!(pers& ADDR_NO_RANDOMIZE)&& !getenv("GCL_UNRANDOMIZE")) { >> errno=0; >> if (personality(pers | ADDR_NO_RANDOMIZE) != -1&& personality(0xffffffffUL)& ADDR_NO_RANDOMIZE) { >> int i; >> char **n; >> for (i=0;envp[i];i++); >> n=alloca((i+2)*sizeof(*n)); >> n[i+1]=0; >> n[i--]="GCL_UNRANDOMIZE=t"; >> for (;i>=0;i--) >> n[i]=envp[i]; >> #ifdef GCL_GPROF >> gprof_cleanup(); >> #endif >> errno=0; >> execve(*argv,argv,n); >> printf("execve failure %d\n",errno); >> exit(-1); >> } else { >> printf("personality change failure %d\n",errno); >> exit(-1); >> } >> } >> } >> } >> ============================================================================= >> f.c >> ============================================================================= >> #include >> void gprof_cleanup() {}; >> int main(int argc,char * argv[],char * envp[]) { >> FILE *f; >> >> #include "h/unrandomize.h" >> >> if (!(f=fopen("conftest1","w"))) return -1; >> fprintf(f,"%u",sbrk(0)); >> return 0;} >> ============================================================================= >> ./f&& cat conftest1&& echo&& ./f&& cat conftest1 >> 10043392 >> 10584064 >> ============================================================================= >> strace -f ./f >> ============================================================================= >> execve("./f", ["./f"], [/* 16 vars */]) = 0 >> brk(0) = 0x7a4000 >> old_mmap(NULL, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2b938000 >> uname({sys="Linux", node="phrixos", ...}) = 0 >> access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) >> access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) >> open("/etc/ld.so.cache", O_RDONLY) = 3 >> fstat64(3, {st_mode=S_IFREG|0644, st_size=16547, ...}) = 0 >> old_mmap(NULL, 16547, PROT_READ, MAP_PRIVATE, 3, 0) = 0x2b93c000 >> close(3) = 0 >> access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) >> open("/lib/libc.so.6", O_RDONLY) = 3 >> read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\10\0\1\0\0\0\24s\1\0004\0\0\0"..., 512) = 512 >> lseek(3, 760, SEEK_SET) = 760 >> read(3, "\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\22\0\0\0", 32) = 32 >> fstat64(3, {st_mode=S_IFREG|0755, st_size=1594664, ...}) = 0 >> old_mmap(NULL, 1576560, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x2b948000 >> mprotect(0x2baac000, 49152, PROT_NONE) = 0 >> old_mmap(0x2bab8000, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x160000) = 0x2bab8000 >> old_mmap(0x2bac8000, 3696, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x2bac8000 >> close(3) = 0 >> set_thread_area(0x2b940ad0) = 0 >> mprotect(0x2bab8000, 49152, PROT_READ) = 0 >> munmap(0x2b93c000, 16547) = 0 >> personality(0xffffffff /* PER_??? */) = 0 >> personality(0x40000 /* PER_??? */) = 0 >> personality(0xffffffff /* PER_??? */) = 262144 >> execve("./f", ["./f"], [/* 17 vars */]) = 0 >> brk(0) = 0x670000 >> old_mmap(NULL, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2ba70000 >> uname({sys="Linux", node="phrixos", ...}) = 0 >> access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) >> access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) >> open("/etc/ld.so.cache", O_RDONLY) = 3 >> fstat64(3, {st_mode=S_IFREG|0644, st_size=16547, ...}) = 0 >> old_mmap(NULL, 16547, PROT_READ, MAP_PRIVATE, 3, 0) = 0x2ba74000 >> close(3) = 0 >> access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or directory) >> open("/lib/libc.so.6", O_RDONLY) = 3 >> read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0\10\0\1\0\0\0\24s\1\0004\0\0\0"..., 512) = 512 >> lseek(3, 760, SEEK_SET) = 760 >> read(3, "\4\0\0\0\20\0\0\0\1\0\0\0GNU\0\0\0\0\0\2\0\0\0\6\0\0\0\22\0\0\0", 32) = 32 >> fstat64(3, {st_mode=S_IFREG|0755, st_size=1594664, ...}) = 0 >> old_mmap(NULL, 1576560, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x2ba80000 >> mprotect(0x2bbe4000, 49152, PROT_NONE) = 0 >> old_mmap(0x2bbf0000, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x160000) = 0x2bbf0000 >> old_mmap(0x2bc00000, 3696, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x2bc00000 >> close(3) = 0 >> set_thread_area(0x2ba78ad0) = 0 >> mprotect(0x2bbf0000, 49152, PROT_READ) = 0 >> munmap(0x2ba74000, 16547) = 0 >> personality(0xffffffff /* PER_??? */) = 0 >> brk(0) = 0x670000 >> brk(0x694000) = 0x694000 >> open("conftest1", O_WRONLY|O_CREAT|O_TRUNC, 0666) = 3 >> fstat64(3, {st_mode=S_IFREG|0644, st_size=0, ...}) = 0 >> old_mmap(NULL, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x2bc04000 >> write(3, "6897664", 7) = 7 >> exit_group(0) = ? >> ============================================================================= >> uname -a >> ============================================================================= >> Linux phrixos 2.6.36-rc6-loongson-2f #1 Mon Oct 4 20:36:22 UTC 2010 >> mips64 GNU/Linux >> ============================================================================= >> /proc/cpuinfo >> ============================================================================= >> system type : lemote-fuloong-2f-box >> processor : 0 >> cpu model : ICT Loongson-2 V0.3 FPU V0.1 >> BogoMIPS : 528.38 >> wait instruction : yes >> microsecond timers : yes >> tlb_entries : 64 >> extra interrupt vector : no >> hardware watchpoint : yes, count: 0, address/irw mask: [] >> ASEs implemented : >> shadow register sets : 1 >> core : 0 >> VCED exceptions : not available >> VCEI exceptions : not available >> ============================================================================= >> >> Take care, > > > > > -- Camm Maguire camm@maguirefamily.org ========================================================================== "The earth is but one country, and mankind its citizens." -- Baha'u'llah From David.Daney@caviumnetworks.com Tue Nov 2 01:43:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2010 01:43:29 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14691 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491028Ab0KBAnZ (ORCPT ); Tue, 2 Nov 2010 01:43:25 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 01 Nov 2010 17:44:00 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 1 Nov 2010 17:43:55 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 1 Nov 2010 17:43:55 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oA20hFOZ026844; Mon, 1 Nov 2010 17:43:16 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oA20hA2w026834; Mon, 1 Nov 2010 17:43:11 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Camm Maguire Subject: [PATCH 1/2] MIPS: Quit clobbering personality bits. Date: Mon, 1 Nov 2010 17:43:07 -0700 Message-Id: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 02 Nov 2010 00:43:55.0917 (UTC) FILETIME=[078CC3D0:01CB7A27] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28288 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The high bits of current->personality carry settings that we don't want to clobber on each exec. Only clobber them if the lower bits that indicate either PER_LINUX or PER_LINUX32 are invalid. The clobbering prevents us from using useful bits like ADDR_NO_RANDOMIZE. Reported-by: Camm Maguire Signed-off-by: David Daney Cc: Camm Maguire --- arch/mips/include/asm/elf.h | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index fd1d39e..2ef5e82 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -249,7 +249,8 @@ extern struct mips_abi mips_abi_n32; #define SET_PERSONALITY(ex) \ do { \ - set_personality(PER_LINUX); \ + if (personality(current->personality) != PER_LINUX) \ + set_personality(PER_LINUX); \ \ current->thread.abi = &mips_abi; \ } while (0) @@ -296,6 +297,7 @@ do { \ #define SET_PERSONALITY(ex) \ do { \ + unsigned int p; \ clear_thread_flag(TIF_32BIT_REGS); \ clear_thread_flag(TIF_32BIT_ADDR); \ \ @@ -304,7 +306,8 @@ do { \ else \ current->thread.abi = &mips_abi; \ \ - if (current->personality != PER_LINUX32) \ + p = personality(current->personality); \ + if (p != PER_LINUX32 && p != PER_LINUX) \ set_personality(PER_LINUX); \ } while (0) -- 1.7.2.3 From David.Daney@caviumnetworks.com Tue Nov 2 01:43:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2010 01:43:53 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14688 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491758Ab0KBAnZ (ORCPT ); Tue, 2 Nov 2010 01:43:25 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 01 Nov 2010 17:44:00 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 1 Nov 2010 17:43:55 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 1 Nov 2010 17:43:55 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oA20hJQq026849; Mon, 1 Nov 2010 17:43:19 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oA20hIPD026848; Mon, 1 Nov 2010 17:43:18 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Camm Maguire Subject: [PATCH 2/2] MIPS: Don't clobber personality bits in 32-bit sys_personality(). Date: Mon, 1 Nov 2010 17:43:08 -0700 Message-Id: <1288658588-26801-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> References: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 02 Nov 2010 00:43:55.0917 (UTC) FILETIME=[078CC3D0:01CB7A27] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28289 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips If PER_LINUX32 has been set on a 32-bit kernel, only twiddle with the low-order personality bits, let the upper bits pass through. Signed-off-by: David Daney Cc: Camm Maguire --- arch/mips/kernel/linux32.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 6343b4a..a63f4e2 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -252,13 +252,13 @@ SYSCALL_DEFINE5(n32_msgrcv, int, msqid, u32, msgp, size_t, msgsz, SYSCALL_DEFINE1(32_personality, unsigned long, personality) { int ret; - personality &= 0xffffffff; + unsigned int p = personality & 0xffffffff; if (personality(current->personality) == PER_LINUX32 && - personality == PER_LINUX) - personality = PER_LINUX32; - ret = sys_personality(personality); - if (ret == PER_LINUX32) - ret = PER_LINUX; + personality(p) == PER_LINUX) + p = (p & ~PER_MASK) | PER_LINUX32; + ret = sys_personality(p); + if (ret != -1 && personality(ret) == PER_LINUX32) + ret = (ret & ~PER_MASK) | PER_LINUX; return ret; } -- 1.7.2.3 From miloody@gmail.com Tue Nov 2 13:50:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2010 13:50:27 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:44737 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491791Ab0KBMuY (ORCPT ); Tue, 2 Nov 2010 13:50:24 +0100 Received: by wwi18 with SMTP id 18so1008334wwi.24 for ; Tue, 02 Nov 2010 05:50:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=7e/DeKvLFVT29DeRRta0FEF6DI7sGcEPfFITgXpXz/c=; b=SzUP+jBFQXtyOkrkZ7szJQOXWfNL1UY98Yhnxi+toPpVZwPLOGW3g+0MhlJxTXk4/y SFgx+H4BW+njutBtH1zmgOt237I8UxlsIlLCBLYe4cJexsNEPzHV0ykCDdyi0fN6zgLb 31NWlhZ+XReekpG5q5gQ5B6SyY55IOWxaCaew= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=UXqLxrRWsehsT0dnhcCT2WYlhMSld1v7fBOnoGWwMf0bXXfplnpR0f5OZI+oNQJeVw T3YQXKeeIfLd4qzK4Eb6r/cjFyERUsEaLxOKg1oX1lV4fblz/dh5EL8W5Xyu9bGls1az 7NAvG6j069scn13o7uJXXo7TQEEOCdV+E0YAA= MIME-Version: 1.0 Received: by 10.216.16.85 with SMTP id g63mr921652weg.114.1288702218364; Tue, 02 Nov 2010 05:50:18 -0700 (PDT) Received: by 10.216.19.213 with HTTP; Tue, 2 Nov 2010 05:50:18 -0700 (PDT) Date: Tue, 2 Nov 2010 20:50:18 +0800 Message-ID: Subject: where is blast_dcache32 ? From: loody To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28290 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Dear all: I try to grep blast_dcache32 but the results show as below. #pwd linux-2.6.30.9/arch/mips #grep -rnw 'blast_dcache32' * mm/c-r4k.c:140: r4k_blast_dcache = blast_dcache32; Binary file mm/built-in.o matches mm/.svn/text-base/c-r4k.c.svn-base:140: r4k_blast_dcache = blast_dcache32; Binary file mm/c-r4k.o matches # Would anyone tell me where I can find it? did I grep the wrong folder? Thanks for your help, miloody From ralf@linux-mips.org Tue Nov 2 13:59:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2010 13:59:56 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:37078 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491791Ab0KBM7w (ORCPT ); Tue, 2 Nov 2010 13:59:52 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA2CxpXf025299; Tue, 2 Nov 2010 12:59:51 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA2CxpZ6025297; Tue, 2 Nov 2010 12:59:51 GMT Date: Tue, 2 Nov 2010 12:59:51 +0000 From: Ralf Baechle To: loody Cc: Linux MIPS Mailing List Subject: Re: where is blast_dcache32 ? Message-ID: <20101102125951.GB6570@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28291 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 02, 2010 at 08:50:18PM +0800, loody wrote: > Dear all: > I try to grep blast_dcache32 but the results show as below. > #pwd > linux-2.6.30.9/arch/mips > #grep -rnw 'blast_dcache32' * > mm/c-r4k.c:140: r4k_blast_dcache = blast_dcache32; > Binary file mm/built-in.o matches > mm/.svn/text-base/c-r4k.c.svn-base:140: r4k_blast_dcache = blast_dcache32; > Binary file mm/c-r4k.o matches > # > > Would anyone tell me where I can find it? > did I grep the wrong folder? You made the mistake of using grep ;-) The function is generated by a number of pretty ugly macros arch/mips/include/asm/r4kcache.h. Ralf From miloody@gmail.com Tue Nov 2 14:21:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2010 14:21:15 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:55759 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491805Ab0KBNVL convert rfc822-to-8bit (ORCPT ); Tue, 2 Nov 2010 14:21:11 +0100 Received: by wwi18 with SMTP id 18so1036712wwi.24 for ; Tue, 02 Nov 2010 06:21:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=8rfG5qe4ljN6VnIxN6t04gKawpFfoVyEFwqJYBDYGfc=; b=U2jl2y/awAoi9assjmR7KykpPSauwmh9YARVu/0leyyXmrIQNoqRa0CKeZnb0f5hpQ ATsPfpAfvty9cn3gDfKhYTK+xlHrkuxo4MGbSZ30S3qPutHB1PgHDG2eUiGrQYucPeCV 3KSx2kYQ7D1c6bW1FMuNsb8UGDRv+6b/YFArE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=KFPH7E4V0mSsTbLanFF3SDLLopAsil5uPG+jl59ZwzXetX0QHBP/+OV4PHeVhoMWr8 dgpY31+K1z/8v45VB+uaRUHQx6ZOx45/eYLRgwPktnyGEqPu1cfMi69gNh/n21qZ7jUM DgQi6zejh1IjyssoBAurz3YO6vZs1SJW0nA8I= MIME-Version: 1.0 Received: by 10.227.147.84 with SMTP id k20mr506282wbv.222.1288704066134; Tue, 02 Nov 2010 06:21:06 -0700 (PDT) Received: by 10.216.19.213 with HTTP; Tue, 2 Nov 2010 06:21:06 -0700 (PDT) In-Reply-To: <20101102125951.GB6570@linux-mips.org> References: <20101102125951.GB6570@linux-mips.org> Date: Tue, 2 Nov 2010 21:21:06 +0800 Message-ID: Subject: Re: where is blast_dcache32 ? From: loody To: Ralf Baechle Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28292 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips hi ralf: 2010/11/2 Ralf Baechle : > On Tue, Nov 02, 2010 at 08:50:18PM +0800, loody wrote: > >> Dear all: >> I try to grep blast_dcache32 but the results show as below. >> #pwd >> linux-2.6.30.9/arch/mips >> #grep -rnw 'blast_dcache32' * >> mm/c-r4k.c:140:               r4k_blast_dcache = blast_dcache32; >> Binary file mm/built-in.o matches >> mm/.svn/text-base/c-r4k.c.svn-base:140:               r4k_blast_dcache = blast_dcache32; >> Binary file mm/c-r4k.o matches >> # >> >> Would anyone tell me where I can find it? >> did I grep the wrong folder? > > You made the mistake of using grep ;-)  The function is generated by a > number of pretty ugly macros arch/mips/include/asm/r4kcache.h. I found it ~~ thanks a lot :-) miloody From sshtylyov@mvista.com Tue Nov 2 17:12:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2010 17:12:27 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:46933 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491831Ab0KBQMY (ORCPT ); Tue, 2 Nov 2010 17:12:24 +0100 Received: by ewy19 with SMTP id 19so3438797ewy.36 for ; Tue, 02 Nov 2010 09:12:23 -0700 (PDT) Received: by 10.213.9.207 with SMTP id m15mr8336971ebm.85.1288714341673; Tue, 02 Nov 2010 09:12:21 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id x54sm5559016eeh.11.2010.11.02.09.12.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 02 Nov 2010 09:12:20 -0700 (PDT) Message-ID: <4CD03817.4050907@mvista.com> Date: Tue, 02 Nov 2010 19:11:03 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, ralf@linux-mips.org, Camm Maguire Subject: Re: [PATCH 2/2] MIPS: Don't clobber personality bits in 32-bit sys_personality(). References: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> <1288658588-26801-2-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1288658588-26801-2-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28293 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. David Daney wrote: > If PER_LINUX32 has been set on a 32-bit kernel, only twiddle with the > low-order personality bits, let the upper bits pass through. > Signed-off-by: David Daney > Cc: Camm Maguire > --- > arch/mips/kernel/linux32.c | 12 ++++++------ > 1 files changed, 6 insertions(+), 6 deletions(-) > diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c > index 6343b4a..a63f4e2 100644 > --- a/arch/mips/kernel/linux32.c > +++ b/arch/mips/kernel/linux32.c > @@ -252,13 +252,13 @@ SYSCALL_DEFINE5(n32_msgrcv, int, msqid, u32, msgp, size_t, msgsz, > SYSCALL_DEFINE1(32_personality, unsigned long, personality) > { > int ret; > - personality &= 0xffffffff; > + unsigned int p = personality & 0xffffffff; I'd have inserted an empty line here... > if (personality(current->personality) == PER_LINUX32 && > - personality == PER_LINUX) > - personality = PER_LINUX32; > - ret = sys_personality(personality); > - if (ret == PER_LINUX32) > - ret = PER_LINUX; > + personality(p) == PER_LINUX) > + p = (p & ~PER_MASK) | PER_LINUX32; > + ret = sys_personality(p); > + if (ret != -1 && personality(ret) == PER_LINUX32) > + ret = (ret & ~PER_MASK) | PER_LINUX; > return ret; > } WBR, Sergei From camm@maguirefamily.org Tue Nov 2 19:43:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2010 19:43:20 +0100 (CET) Received: from tvwna-ip-c-172.princeton.org ([66.180.187.89]:49232 "EHLO localhost.m.enhanced.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491187Ab0KBSnR (ORCPT ); Tue, 2 Nov 2010 19:43:17 +0100 Received: from camm by localhost.m.enhanced.com with local (Exim 4.69) (envelope-from ) id 1PDLp9-00014m-T6; Tue, 02 Nov 2010 14:43:11 -0400 To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: Quit clobbering personality bits. References: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> From: Camm Maguire Date: Tue, 02 Nov 2010 14:43:11 -0400 In-Reply-To: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> (David Daney's message of "Mon\, 1 Nov 2010 17\:43\:07 -0700") Message-ID: <87lj5ba7nk.fsf@maguirefamily.org> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28294 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: camm@maguirefamily.org Precedence: bulk X-list: linux-mips Thank you! -- Camm Maguire camm@maguirefamily.org ========================================================================== "The earth is but one country, and mankind its citizens." -- Baha'u'llah From cernekee@gmail.com Wed Nov 3 06:32:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Nov 2010 06:32:39 +0100 (CET) Received: from [69.28.251.93] ([69.28.251.93]:45853 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1490990Ab0KCFcf (ORCPT ); Wed, 3 Nov 2010 06:32:35 +0100 Received: (qmail 15360 invoked from network); 3 Nov 2010 05:32:31 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 3 Nov 2010 05:32:31 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Tue, 02 Nov 2010 22:32:30 -0700 From: Kevin Cernekee To: Ralf Baechle Cc: , Subject: [PATCH] MIPS: Fix build errors in sc-mips.c Date: Tue, 02 Nov 2010 22:28:01 -0700 Message-Id: <01184c101e5d39225a6380cce3c5bad5@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28295 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Seen with malta_defconfig on Linus' tree: CC arch/mips/mm/sc-mips.o arch/mips/mm/sc-mips.c: In function 'mips_sc_is_activated': arch/mips/mm/sc-mips.c:77: error: 'config2' undeclared (first use in this function) arch/mips/mm/sc-mips.c:77: error: (Each undeclared identifier is reported only once arch/mips/mm/sc-mips.c:77: error: for each function it appears in.) arch/mips/mm/sc-mips.c:81: error: 'tmp' undeclared (first use in this function) make[2]: *** [arch/mips/mm/sc-mips.o] Error 1 make[1]: *** [arch/mips/mm] Error 2 make: *** [arch/mips] Error 2 Signed-off-by: Kevin Cernekee --- arch/mips/mm/sc-mips.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 505feca..ef625eb 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -66,8 +66,11 @@ static struct bcache_ops mips_sc_ops = { * 12..15 as implementation defined so below function will eventually have * to be replaced by a platform specific probe. */ -static inline int mips_sc_is_activated(struct cpuinfo_mips *c) +static inline int mips_sc_is_activated(struct cpuinfo_mips *c, + unsigned int config2) { + unsigned int tmp; + /* Check the bypass bit (L2B) */ switch (c->cputype) { case CPU_34K: @@ -83,6 +86,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) c->scache.linesz = 2 << tmp; else return 0; + return 1; } static inline int __init mips_sc_probe(void) @@ -108,7 +112,7 @@ static inline int __init mips_sc_probe(void) config2 = read_c0_config2(); - if (!mips_sc_is_activated(c)) + if (!mips_sc_is_activated(c, config2)) return 0; tmp = (config2 >> 8) & 0x0f; -- 1.7.0.4 From rmh.aybabtu@gmail.com Thu Nov 4 13:18:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 13:18:52 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:54976 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491863Ab0KDMSt (ORCPT ); Thu, 4 Nov 2010 13:18:49 +0100 Received: by wyf22 with SMTP id 22so1776747wyf.36 for ; Thu, 04 Nov 2010 05:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:subject:to :x-mailer:message-id:mime-version:content-type; bh=9t9h+kn5cxVamWXw7fiQwbLRKIT2Xfi0vuC/7+4m6WQ=; b=dQRYoTOtffgwuDig2lsKl+6aym52BrwkdK4pCl7i19uo9vcIbFlcNSTmxglLXQ/Vm7 pJQKXQjQSXZkSV+KO/9J4zN1D3LeqNZFLpWCleql+wsbUyEhnuWnNJq+UHp/g/BnmijE jH99k1VrD2fJSds+1wov0dTIu3mAOLZ2kNhUQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:subject:to:x-mailer:message-id:mime-version :content-type; b=uXLGwVErYGDPz0AVfuHJJtRIV69Wwm1I7aQ1oOp3TlDhrHIhaeSbl/poVAllbFShy/ xrMNecVN17irUZ21ykOY9V2oXng6yFwkSuAVKJg7mzj0C+ikD45MGKWhbqPCvcZlvXmd 7Oz23aSAGx7H9hWVGQfx4RDOMWkQUcKLJnHTs= Received: by 10.227.32.147 with SMTP id c19mr656671wbd.43.1288873123222; Thu, 04 Nov 2010 05:18:43 -0700 (PDT) Received: from thorin ([81.38.198.117]) by mx.google.com with ESMTPS id i19sm8498206wbe.17.2010.11.04.05.18.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Nov 2010 05:18:42 -0700 (PDT) Date: Thu, 04 Nov 2010 13:18:39 +0100 From: Robert Millan Subject: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU To: Ralf Baechle , linux-mips@linux-mips.org X-Mailer: Balsa 2.4.1 Message-Id: <1288873119.12965.1@thorin> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-5GodYgjBcmMHasXlITod" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28296 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips --=-5GodYgjBcmMHasXlITod Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Please consider this patch, it enables AT_PLATFORM for Loongson 2F CPU. --=-5GodYgjBcmMHasXlITod Content-Type: text/x-patch; charset=us-ascii; name=loongson-2f.diff Content-Disposition: attachment; filename=loongson-2f.diff Content-Transfer-Encoding: quoted-printable Enable AT_PLATFORM for Loongson 2F CPU. Signed-off-by: Robert Millan diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 71620e1..504f3b1 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -614,6 +614,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips= *c, unsigned int cpu) case PRID_IMP_LOONGSON2: c->cputype =3D CPU_LOONGSON2; __cpu_name[cpu] =3D "ICT Loongson-2"; + if (cpu =3D=3D 0) + __elf_platform =3D "loongson-2f"; c->isa_level =3D MIPS_CPU_ISA_III; c->options =3D R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | --=-5GodYgjBcmMHasXlITod-- From wuzhangjin@gmail.com Thu Nov 4 16:20:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 16:20:28 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:50160 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491871Ab0KDPU0 (ORCPT ); Thu, 4 Nov 2010 16:20:26 +0100 Received: by gxk25 with SMTP id 25so1579543gxk.36 for ; Thu, 04 Nov 2010 08:20:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:cc:content-type; bh=mRkTiy6c6468jbBa7c6gDYHXozw/zp+y1mwe1qP7Ye4=; b=j3pPc7/82aKgGnlTcjONnXWpXXTC/z1kieWjJjokxHOh6QG/OKS9ugZLwzjP+v7XCx QPLX/TXhQeXmRK9L68uJP7s6+UdNJOROMB40aUOM9xadZ+uPqCuwCkIE2X5n4YGuZY/6 +SVSnkXcmsJ2u5wPX2tjbwIjz33S4vRQS73w4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; b=gLCqZRXY7GGb+3GXyWz5pcqO/1LtDbBVRz92vajvCFPmUKb9P3YNKut2dHcFHJfNtS GV1w1MLYCoJljoZVa8/Z6IX1Wq99yABn+cJUkJCXp7ObsCKzwsVmqONFX3c/AhHCAEXt ncptvSBnpyVbwRwuVHy5KhUgZLMha1wQevCuw= MIME-Version: 1.0 Received: by 10.216.175.18 with SMTP id y18mr896336wel.30.1288884019221; Thu, 04 Nov 2010 08:20:19 -0700 (PDT) Received: by 10.216.63.195 with HTTP; Thu, 4 Nov 2010 08:20:19 -0700 (PDT) Date: Thu, 4 Nov 2010 23:20:19 +0800 Message-ID: Subject: [BUG] The Perf support of MIPS is broken for the upstream changes From: wu zhangjin To: Deng-Cheng Zhu Cc: Ralf Baechle , linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28297 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, Deng Cheng Just took a try to add the Perf support for Loongson but failed for the skeleton of the Perf Support of MIPS was broken. After some investigation, I have found several important changes have been applied for the upstream Perf event, which has broken the Perf support of MIPS. Here lists several important changes: 1. e360adbe29241a0194e10e20595360dd7b98a2b3: irq_work: Add generic hardirq context callbacks This commit has added "generic hardirq context callbacks": irq_work, which are designed particularly for NMI code that needs to interact with the rest of the system. Like ARM, MIPS performance counters do not raise NMI upon overflow, instead, they emit regular interrupts, so, simply remove the empty set_perf_event_pending() in perf_event.h and call irq_work_run() instead of perf_event_do_pend() is needed. 2. a4eaf7f14675cb512d69f0c928055e73d0c6d252: perf: Rework the PMU methods This has replaced the pmu::{enable,disable,start,stop,unthrottle} with pmu::{add,del,start,stop}, which has made the current implementation of Perf for MIPS completely broken, so, we also need to make related changes. 3. b0a873ebbf87bf38bf70b5e39a7cadc96099fa13: perf: Register PMU implementations The weak hw_perf_event_init() function is replaced by a new member: event_init() of struct pmu(). You can track more upstream changes via the following command: $ git log {kernel/perf_event.c,include/linux/perf_event.h} Of course, at first, you may need to clone/pull a latest mainline kernel. Regards, Wu Zhangjin From ralf@linux-mips.org Thu Nov 4 16:31:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 16:31:07 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36897 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491875Ab0KDPbE (ORCPT ); Thu, 4 Nov 2010 16:31:04 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA4FV1HE022694; Thu, 4 Nov 2010 15:31:02 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA4FUwoK022693; Thu, 4 Nov 2010 15:30:58 GMT Date: Thu, 4 Nov 2010 15:30:57 +0000 From: Ralf Baechle To: wu zhangjin Cc: Deng-Cheng Zhu , linux-mips Subject: Re: [BUG] The Perf support of MIPS is broken for the upstream changes Message-ID: <20101104153055.GA22377@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28298 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Nov 04, 2010 at 11:20:19PM +0800, wu zhangjin wrote: > $ git log {kernel/perf_event.c,include/linux/perf_event.h} > > Of course, at first, you may need to clone/pull a latest mainline kernel. Note that the linux-mips.org kernel repository is a superset of the mainline kernel. To reduce the confusion I just don't push any of Linus' tags but the kernel objects are all there. Anybody who wants to get Linus' tags or a linus branch as well can fetch from Linus tree. The size increase is minimal. Ralf From David.Daney@caviumnetworks.com Thu Nov 4 17:44:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 17:44:53 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12561 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491870Ab0KDQou (ORCPT ); Thu, 4 Nov 2010 17:44:50 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 04 Nov 2010 09:45:23 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 4 Nov 2010 09:45:21 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 4 Nov 2010 09:45:21 -0700 Message-ID: <4CD2E2F7.4090701@caviumnetworks.com> Date: Thu, 04 Nov 2010 09:44:39 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.12) Gecko/20100907 Fedora/3.0.7-1.fc12 Thunderbird/3.0.7 MIME-Version: 1.0 To: Robert Millan , Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU References: <1288873119.12965.1@thorin> In-Reply-To: <1288873119.12965.1@thorin> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 04 Nov 2010 16:45:21.0121 (UTC) FILETIME=[AB6FDD10:01CB7C3F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28299 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 11/04/2010 05:18 AM, Robert Millan wrote: > > Please consider this patch, it enables AT_PLATFORM for Loongson 2F CPU. > > [...] > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 71620e1..504f3b1 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -614,6 +614,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) > case PRID_IMP_LOONGSON2: > c->cputype = CPU_LOONGSON2; > __cpu_name[cpu] = "ICT Loongson-2"; > + if (cpu == 0) > + __elf_platform = "loongson-2f"; > c->isa_level = MIPS_CPU_ISA_III; > c->options = R4K_OPTS | > MIPS_CPU_FPU | MIPS_CPU_LLSC | This doesn't look right to me. You are claiming that all loongson2 are loongson-2f. Is that really true? Or are there other types of loongson2 that are not loongson-2f? You need to be very careful here. This is part of the userspace ABI, so if you get it wrong, you are stuck with it forever. One question you didn't address is why userspace would care that it is running on exactly "loongson-2f" instead of just mips4. The __elf_platform gets converted to a directory name by ld.so, so you may want to choose a value without '-' in it. My suggestion would be to set "loongson2" for the generic CPU_LOONGSON2, and if there is a good reason for it, "loongson2f" for the 'f' variant. David Daney From aurelien@aurel32.net Thu Nov 4 18:33:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 18:33:35 +0100 (CET) Received: from hall.aurel32.net ([88.191.82.174]:41150 "EHLO hall.aurel32.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491869Ab0KDRdc (ORCPT ); Thu, 4 Nov 2010 18:33:32 +0100 Received: from [2001:660:5001:1a:200:5efe:86d6:4cf] by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1PE3gn-0000HR-Lz; Thu, 04 Nov 2010 18:33:29 +0100 Message-ID: <4CD2EE64.5060404@aurel32.net> Date: Thu, 04 Nov 2010 18:33:24 +0100 From: Aurelien Jarno User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: David Daney CC: Robert Millan , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU References: <1288873119.12965.1@thorin> <4CD2E2F7.4090701@caviumnetworks.com> In-Reply-To: <4CD2E2F7.4090701@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28300 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aurelien@aurel32.net Precedence: bulk X-list: linux-mips David Daney a écrit : > On 11/04/2010 05:18 AM, Robert Millan wrote: >> Please consider this patch, it enables AT_PLATFORM for Loongson 2F CPU. >> >> > [...] >> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c >> index 71620e1..504f3b1 100644 >> --- a/arch/mips/kernel/cpu-probe.c >> +++ b/arch/mips/kernel/cpu-probe.c >> @@ -614,6 +614,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) >> case PRID_IMP_LOONGSON2: >> c->cputype = CPU_LOONGSON2; >> __cpu_name[cpu] = "ICT Loongson-2"; >> + if (cpu == 0) >> + __elf_platform = "loongson-2f"; >> c->isa_level = MIPS_CPU_ISA_III; >> c->options = R4K_OPTS | >> MIPS_CPU_FPU | MIPS_CPU_LLSC | > > This doesn't look right to me. > > You are claiming that all loongson2 are loongson-2f. Is that really > true? Or are there other types of loongson2 that are not loongson-2f? > > You need to be very careful here. This is part of the userspace ABI, so > if you get it wrong, you are stuck with it forever. > > One question you didn't address is why userspace would care that it is > running on exactly "loongson-2f" instead of just mips4. > > The __elf_platform gets converted to a directory name by ld.so, so you > may want to choose a value without '-' in it. > > My suggestion would be to set "loongson2" for the generic CPU_LOONGSON2, > and if there is a good reason for it, "loongson2f" for the 'f' variant. > You should definitely define here loongson-2e and loongson-2f separately. They have the same instruction set, but different opcodes for the loongson specific instructions, hence they are not compatible. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net From rmh.aybabtu@gmail.com Thu Nov 4 19:43:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 19:43:13 +0100 (CET) Received: from mail-iw0-f177.google.com ([209.85.214.177]:63483 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491876Ab0KDSnK convert rfc822-to-8bit (ORCPT ); Thu, 4 Nov 2010 19:43:10 +0100 Received: by iwn8 with SMTP id 8so1636268iwn.36 for ; Thu, 04 Nov 2010 11:43:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type:content-transfer-encoding; bh=MqwrLWR/RP2KyKNgJBo8btO05YQs+f0OejXSwDZyay4=; b=hCUl/HOPRa9yxNCrjpAbY+loNYSw2mwi5rsVW/9qxFOQ8xMJl+f9M8JXIGE9uP6dkz 7NWkriVO4EQcWN92itE+rFKSxenPe+dY8AYKYFv+EyI2i5j0wb1wGsdSK3VrXh/e8H5x TzszpOo0p39Tx6Wg5m6qjLh/TqJGQaMIsAM4I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=HdKjJ9k5xevNUHqbDRqEM16kfaxzuPIPa0+z/TF+9RtC08mV9hBkPzfiHLRyzDavVv 7jcW2KdRHRy8GZTum41vHEsEHp4RC1LTZuq4hEiyMANSiChgENYDeCQ4jPoXhl09T2u4 NPKgxztg+018fWrEmPLeYegXZcfi/woOtW+Jc= MIME-Version: 1.0 Received: by 10.231.14.74 with SMTP id f10mr895344iba.185.1288896188394; Thu, 04 Nov 2010 11:43:08 -0700 (PDT) Received: by 10.231.170.70 with HTTP; Thu, 4 Nov 2010 11:43:08 -0700 (PDT) In-Reply-To: <4CD2EE64.5060404@aurel32.net> References: <1288873119.12965.1@thorin> <4CD2E2F7.4090701@caviumnetworks.com> <4CD2EE64.5060404@aurel32.net> Date: Thu, 4 Nov 2010 19:43:08 +0100 X-Google-Sender-Auth: rK2MWbYORQ1uzP74w3hbb-j-Re4 Message-ID: Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU From: Robert Millan To: David Daney Cc: Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28301 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips Hi! David Daney a écrit : > You are claiming that all loongson2 are loongson-2f.  Is that really > true?  Or are there other types of loongson2 that are not loongson-2f? > > You need to be very careful here.  This is part of the userspace ABI, so > if you get it wrong, you are stuck with it forever. I'll figure out how to distinguish them and send a new patch. > One question you didn't address is why userspace would care that it is > running on exactly "loongson-2f" instead of just mips4. I think Aurelien answered this. > The __elf_platform gets converted to a directory name by ld.so, so you > may want to choose a value without '-' in it. Well I appreciate consistency with GCC flag names, so I'd rather keep the dash, but then again it's not my decision to make. In any case, whoever commits this can adjust the name to his/her liking. -- Robert Millan From David.Daney@caviumnetworks.com Thu Nov 4 20:11:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 20:11:19 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17673 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491118Ab0KDTLQ (ORCPT ); Thu, 4 Nov 2010 20:11:16 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 04 Nov 2010 12:11:52 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 4 Nov 2010 12:11:50 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 4 Nov 2010 12:11:50 -0700 Message-ID: <4CD30551.1000006@caviumnetworks.com> Date: Thu, 04 Nov 2010 12:11:13 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.12) Gecko/20100907 Fedora/3.0.7-1.fc12 Thunderbird/3.0.7 MIME-Version: 1.0 To: Robert Millan CC: Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU References: <1288873119.12965.1@thorin> <4CD2E2F7.4090701@caviumnetworks.com> <4CD2EE64.5060404@aurel32.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 04 Nov 2010 19:11:50.0317 (UTC) FILETIME=[2234BDD0:01CB7C54] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28302 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 11/04/2010 11:43 AM, Robert Millan wrote: > Hi! > > David Daney a écrit : >> You are claiming that all loongson2 are loongson-2f. Is that really >> true? Or are there other types of loongson2 that are not loongson-2f? >> >> You need to be very careful here. This is part of the userspace ABI, so >> if you get it wrong, you are stuck with it forever. > > I'll figure out how to distinguish them and send a new patch. > >> One question you didn't address is why userspace would care that it is >> running on exactly "loongson-2f" instead of just mips4. > > I think Aurelien answered this. > >> The __elf_platform gets converted to a directory name by ld.so, so you >> may want to choose a value without '-' in it. > > Well I appreciate consistency with GCC flag names, so I'd rather keep > the dash, but then again it's not my decision to make. In any case, > whoever commits this can adjust the name to his/her liking. I don't like to put words into Ralf's mouth, but it is easier to work with patches that have been tested and are ready to go, rather than having to re-write everything. Some of the strings in use are "i686", "x86_64", "octeon", "octeon2", "PARISC", "PARISC32", tilegx-m32", "v4l", "v3l", "v4b", and "v3b", these last for for ARM and they don't match the GCC -mcpu= values. So I guess what ever you want. David Daney From ralf@linux-mips.org Thu Nov 4 20:30:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 20:30:06 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48005 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491876Ab0KDTaD (ORCPT ); Thu, 4 Nov 2010 20:30:03 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA4JTiml028529; Thu, 4 Nov 2010 19:29:45 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA4JThru028526; Thu, 4 Nov 2010 19:29:43 GMT Date: Thu, 4 Nov 2010 19:29:43 +0000 From: Ralf Baechle To: David Daney Cc: Robert Millan , Aurelien Jarno , linux-mips@linux-mips.org Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU Message-ID: <20101104192943.GA28245@linux-mips.org> References: <1288873119.12965.1@thorin> <4CD2E2F7.4090701@caviumnetworks.com> <4CD2EE64.5060404@aurel32.net> <4CD30551.1000006@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4CD30551.1000006@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28303 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Nov 04, 2010 at 12:11:13PM -0700, David Daney wrote: > >Well I appreciate consistency with GCC flag names, so I'd rather keep > >the dash, but then again it's not my decision to make. In any case, > >whoever commits this can adjust the name to his/her liking. > > I don't like to put words into Ralf's mouth, but it is easier to > work with patches that have been tested and are ready to go, rather > than having to re-write everything. Indeed. I modify lots of patches that I can't test on my hardware collection so any change I have to do also increases of me adding bugs. Heck, I do most of my builds on fairly modest dual core machines so I can't even afford test builds which is how occasionally the most stupid errors end up getting committed. Which is why I'm increasingly asking people to do trivial changes to patches, not because I'm lazy. > Some of the strings in use are "i686", "x86_64", "octeon", > "octeon2", "PARISC", "PARISC32", tilegx-m32", "v4l", "v3l", "v4b", > and "v3b", these last for for ARM and they don't match the GCC > -mcpu= values. > > So I guess what ever you want. It's probably reasonable if the names don't diverge too far from each other. Then again with the number of cpu type synonyms accepted by gcc that may just be wishful thinking. Ralf From lars@metafoo.de Thu Nov 4 23:26:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 23:26:38 +0100 (CET) Received: from smtp-out-083.synserver.de ([212.40.180.83]:1030 "HELO smtp-out-081.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491881Ab0KDW0f (ORCPT ); Thu, 4 Nov 2010 23:26:35 +0100 Received: (qmail 11315 invoked by uid 0); 4 Nov 2010 22:26:27 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 10773 Received: from c128026.adsl.hansenet.de (HELO localhost.localdomain) [213.39.128.26] by 217.119.54.81 with SMTP; 4 Nov 2010 22:26:26 -0000 From: Lars-Peter Clausen To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Lars-Peter Clausen , stable@kernel.org Subject: [PATCH] MIPS: jz4740: qi_lb60: Fix gpio for the 6th row of the keyboard matrix Date: Thu, 4 Nov 2010 23:25:56 +0100 Message-Id: <1288909557-20088-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28304 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch fixes the gpio number for the 6th row of the keyboard matrix. (And fixes a typo in my name...) Signed-off-by: Lars-Peter Clausen Cc: stable@kernel.org --- arch/mips/jz4740/board-qi_lb60.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)A --- This patch should go into 2.6.36.x stable diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 3221846..05297ef 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -5,7 +5,7 @@ * * Copyright (c) 2009 Qi Hardware inc., * Author: Xiangfu Liu - * Copyright 2010, Lars-Petrer Clausen + * Copyright 2010, Lars-Peter Clausen * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 or later @@ -236,7 +236,7 @@ static const unsigned int qi_lb60_keypad_rows[] = { QI_LB60_GPIO_KEYIN(3), QI_LB60_GPIO_KEYIN(4), QI_LB60_GPIO_KEYIN(5), - QI_LB60_GPIO_KEYIN(7), + QI_LB60_GPIO_KEYIN(6), QI_LB60_GPIO_KEYIN8, }; -- 1.5.6.5 From lars@metafoo.de Thu Nov 4 23:26:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2010 23:27:03 +0100 (CET) Received: from smtp-out-083.synserver.de ([212.40.180.83]:1062 "HELO smtp-out-081.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491884Ab0KDW0j (ORCPT ); Thu, 4 Nov 2010 23:26:39 +0100 Received: (qmail 11349 invoked by uid 0); 4 Nov 2010 22:26:28 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 10773 Received: from c128026.adsl.hansenet.de (HELO localhost.localdomain) [213.39.128.26] by 217.119.54.81 with SMTP; 4 Nov 2010 22:26:27 -0000 From: Lars-Peter Clausen To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Lars-Peter Clausen Subject: [PATCH] MIPS: JZ4740: prom: Fix section mismatch Date: Thu, 4 Nov 2010 23:25:57 +0100 Message-Id: <1288909557-20088-2-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1288909557-20088-1-git-send-email-lars@metafoo.de> References: <1288909557-20088-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28305 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch fixes the following section mismatch: WARNING: arch/mips/built-in.o(.text+0xc): Section mismatch in reference from the function jz4740_init_cmdline() to the variable .init.data:arcs_cmdline While were at it, make jz4740_init_cmdline static as well. Signed-off-by: Lars-Peter Clausen --- arch/mips/jz4740/prom.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c index cfeac15..4a70407 100644 --- a/arch/mips/jz4740/prom.c +++ b/arch/mips/jz4740/prom.c @@ -23,7 +23,7 @@ #include #include -void jz4740_init_cmdline(int argc, char *argv[]) +static __init void jz4740_init_cmdline(int argc, char *argv[]) { unsigned int count = COMMAND_LINE_SIZE - 1; int i; -- 1.5.6.5 From ralf@linux-mips.org Fri Nov 5 00:45:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 00:45:02 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51790 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491881Ab0KDXpA (ORCPT ); Fri, 5 Nov 2010 00:45:00 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA4NivRB017532; Thu, 4 Nov 2010 23:44:58 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA4NiuX1017530; Thu, 4 Nov 2010 23:44:56 GMT Date: Thu, 4 Nov 2010 23:44:56 +0000 From: Ralf Baechle To: Kevin Cernekee Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: Fix build errors in sc-mips.c Message-ID: <20101104234455.GB28245@linux-mips.org> References: <01184c101e5d39225a6380cce3c5bad5@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <01184c101e5d39225a6380cce3c5bad5@localhost> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28306 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 02, 2010 at 10:28:01PM -0700, Kevin Cernekee wrote: Thanks, applied. Ralf From ralf@linux-mips.org Fri Nov 5 01:10:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 01:11:00 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60424 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491884Ab0KEAK5 (ORCPT ); Fri, 5 Nov 2010 01:10:57 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA50Avej019491; Fri, 5 Nov 2010 00:10:57 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA50AvDs019490; Fri, 5 Nov 2010 00:10:57 GMT Date: Fri, 5 Nov 2010 00:10:57 +0000 From: Ralf Baechle To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: JZ4740: prom: Fix section mismatch Message-ID: <20101105001057.GB19092@linux-mips.org> References: <1288909557-20088-1-git-send-email-lars@metafoo.de> <1288909557-20088-2-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288909557-20088-2-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28307 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Fri Nov 5 01:11:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 01:11:43 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60435 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491889Ab0KEALl (ORCPT ); Fri, 5 Nov 2010 01:11:41 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA50AHdk019484; Fri, 5 Nov 2010 00:10:17 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA50AGuV019483; Fri, 5 Nov 2010 00:10:16 GMT Date: Fri, 5 Nov 2010 00:10:15 +0000 From: Ralf Baechle To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, stable@kernel.org Subject: Re: [PATCH] MIPS: jz4740: qi_lb60: Fix gpio for the 6th row of the keyboard matrix Message-ID: <20101105001015.GA19092@linux-mips.org> References: <1288909557-20088-1-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288909557-20088-1-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28308 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From joe@perches.com Fri Nov 5 04:08:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 04:08:46 +0100 (CET) Received: from mail.perches.com ([173.55.12.10]:4045 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490974Ab0KEDIn (ORCPT ); Fri, 5 Nov 2010 04:08:43 +0100 Received: from Joe-Laptop.home (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id E8EF024368; Thu, 4 Nov 2010 19:08:25 -0800 (PST) From: Joe Perches To: Jiri Kosina Cc: linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, cbe-oss-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, amd64-microcode@amd64.org, linux-crypto@vger.kernel.org, linux-atm-general@lists.sourceforge.net, netdev@vger.kernel.org, drbd-user@lists.linbit.com, dri-devel@lists.freedesktop.org, linux-input@vger.kernel.org, linux-rdma@vger.kernel.org, dm-devel@redhat.com, linux-raid@vger.kernel.org, linux-media@vger.kernel.org, linux-mtd@lists.infradead.org, e1000-devel@lists.sourceforge.net, linux-scsi@vger.kernel.org, osst-users@lists.sourceforge.net, devel@driverdev.osuosl.org, xen-devel@lists.xen.org, virtualization@lists.osdl.org, linux-ext4@vger.kernel.org, reiserfs-devel@vger.kernel.org, xfs@oss.sgi.com, codalist@coda.cs.cmu.edu, linux-mm@kvack.org, containers@lists.linux-foundation.org, netfilter-devel@vger.kernel.org, netfilter@vger.kernel.org, coreteam@netfilter.org, rds-devel@oss.oracle.com, alsa-devel@alsa-project.org Subject: [PATCH 00/49] Use vzalloc not vmalloc/kmemset Date: Thu, 4 Nov 2010 20:07:24 -0700 Message-Id: X-Mailer: git-send-email 1.7.3.1.g432b3.dirty In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28309 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Converted vmalloc/memset and vmalloc_node/memset to vzalloc or vzalloc_node using a cocci script and some editing Reduces text a little bit. Compiled x86 only. There are still vmalloc_32 with memset calls still around. Broken out to multiple patches to cc appropriate maintainers. Joe Perches (49): arch/ia64: Use vzalloc arch/mips: Use vzalloc arch/powerpc: Use vzalloc arch/s390: Use vzalloc arch/x86: Use vzalloc crypto: Use vzalloc drivers/atm: Use vzalloc drivers/block: Use vzalloc drivers/char: Use vzalloc drivers/gpu: Use vzalloc drivers/hid: Use vzalloc drivers/infiniband: Use vzalloc drivers/isdn: Use vzalloc drivers/md: Use vzalloc drivers/media: Use vzalloc drivers/mtd: Use vzalloc drivers/net/cxgb3: Use vzalloc drivers/net/cxgb4: Use vzalloc drivers/net/e1000: Use vzalloc drivers/net/e1000e: Use vzalloc drivers/net/ehea: Use vzalloc drivers/net/igb: Use vzalloc drivers/net/igbvf: Use vzalloc drivers/net/ixgb: Use vzalloc drivers/net/ixgbe: Use vzalloc drivers/net/ixgbevf: Use vzalloc drivers/net/netxen: Use vzalloc drivers/net/pch_gbe: Use vzalloc drivers/net/qlcnic: Use vzalloc drivers/net/sfc: Use vzalloc drivers/net/vxge: Use vzalloc drivers/net/bnx2.c: Use vzalloc drivers/s390: Use vzalloc drivers/scsi: Use vzalloc drivers/staging: Use vzalloc drivers/video: Use vzalloc fs/ext4: Use vzalloc fs/jffs2: Use vzalloc fs/reiserfs: Use vzalloc fs/udf: Use vzalloc fs/xfs: Use vzalloc include/linux/coda_linux.h: Use vzalloc kernel: Use vzalloc mm: Use vzalloc net/core/pktgen.c: Use vzalloc net/netfilter: Use vzalloc net/rds: Use vzalloc sound/oss/dev_table.c: Use vzalloc virt/kvm/kvm_main.c: Use vzalloc arch/ia64/kernel/perfmon.c | 3 +- arch/mips/sibyte/common/sb_tbprof.c | 3 +- arch/powerpc/kvm/book3s.c | 6 +-- arch/powerpc/platforms/cell/spufs/lscsa_alloc.c | 3 +- arch/s390/hypfs/hypfs_diag.c | 3 +- arch/x86/kernel/microcode_amd.c | 3 +- arch/x86/kvm/x86.c | 3 +- arch/x86/mm/pageattr-test.c | 3 +- crypto/deflate.c | 3 +- crypto/zlib.c | 3 +- drivers/atm/idt77252.c | 11 ++++--- drivers/atm/lanai.c | 3 +- drivers/block/drbd/drbd_bitmap.c | 5 +-- drivers/char/agp/backend.c | 3 +- drivers/char/mspec.c | 5 +-- drivers/gpu/drm/via/via_dmablit.c | 4 +- drivers/hid/hid-core.c | 3 +- drivers/infiniband/hw/amso1100/c2_rnic.c | 5 +-- drivers/infiniband/hw/ehca/ipz_pt_fn.c | 5 +-- drivers/infiniband/hw/ipath/ipath_driver.c | 3 +- drivers/infiniband/hw/ipath/ipath_file_ops.c | 11 ++----- drivers/infiniband/hw/ipath/ipath_init_chip.c | 5 +-- drivers/infiniband/hw/qib/qib_init.c | 7 +--- drivers/infiniband/ulp/ipoib/ipoib_cm.c | 10 ++---- drivers/infiniband/ulp/ipoib/ipoib_main.c | 3 +- drivers/isdn/i4l/isdn_common.c | 4 +- drivers/isdn/mISDN/dsp_core.c | 3 +- drivers/isdn/mISDN/l1oip_codec.c | 6 +-- drivers/md/dm-log.c | 3 +- drivers/md/dm-snap-persistent.c | 3 +- drivers/md/dm-table.c | 4 +-- drivers/media/dvb/ngene/ngene-core.c | 3 +- drivers/media/video/mx3_camera.c | 3 +- drivers/media/video/pwc/pwc-if.c | 3 +- drivers/media/video/videobuf-dma-sg.c | 3 +- drivers/mtd/nand/nandsim.c | 3 +- drivers/mtd/ubi/vtbl.c | 6 +-- drivers/net/bnx2.c | 10 +----- drivers/net/cxgb3/cxgb3_offload.c | 7 ++-- drivers/net/cxgb4/cxgb4_main.c | 7 ++-- drivers/net/e1000/e1000_main.c | 6 +-- drivers/net/e1000e/netdev.c | 6 +-- drivers/net/ehea/ehea_main.c | 4 +-- drivers/net/igb/igb_main.c | 6 +-- drivers/net/igbvf/netdev.c | 6 +-- drivers/net/ixgb/ixgb_main.c | 6 +-- drivers/net/ixgbe/ixgbe_main.c | 10 ++---- drivers/net/ixgbevf/ixgbevf_main.c | 6 +-- drivers/net/netxen/netxen_nic_init.c | 7 +--- drivers/net/pch_gbe/pch_gbe_main.c | 6 +-- drivers/net/qlcnic/qlcnic_init.c | 7 +--- drivers/net/sfc/filter.c | 3 +- drivers/net/vxge/vxge-config.c | 37 +++++----------------- drivers/s390/cio/blacklist.c | 3 +- drivers/scsi/bfa/bfad.c | 3 +- drivers/scsi/bfa/bfad_debugfs.c | 8 +---- drivers/scsi/cxgbi/libcxgbi.h | 9 ++---- drivers/scsi/osst.c | 3 +- drivers/scsi/qla2xxx/qla_attr.c | 3 +- drivers/scsi/qla2xxx/qla_bsg.c | 3 +- drivers/scsi/scsi_debug.c | 7 +--- drivers/staging/comedi/drivers.c | 4 +-- drivers/staging/rtl8192e/r8192E_core.c | 4 +-- drivers/staging/udlfb/udlfb.c | 5 +-- drivers/staging/xgifb/XGI_main_26.c | 3 +- drivers/staging/zram/zram_drv.c | 3 +- drivers/video/arcfb.c | 5 +-- drivers/video/broadsheetfb.c | 4 +-- drivers/video/hecubafb.c | 5 +-- drivers/video/metronomefb.c | 4 +-- drivers/video/xen-fbfront.c | 3 +- fs/ext4/super.c | 4 +-- fs/jffs2/build.c | 5 +-- fs/reiserfs/journal.c | 9 ++---- fs/reiserfs/resize.c | 4 +-- fs/udf/super.c | 5 +-- fs/xfs/linux-2.6/kmem.h | 7 +---- include/linux/coda_linux.h | 26 ++++++++++------ kernel/profile.c | 6 +-- kernel/relay.c | 4 +-- mm/memcontrol.c | 5 +-- mm/page_cgroup.c | 3 +- mm/percpu.c | 8 +---- mm/swapfile.c | 3 +- net/core/pktgen.c | 3 +- net/netfilter/x_tables.c | 5 +-- net/rds/ib_cm.c | 6 +-- sound/oss/dev_table.c | 6 +-- virt/kvm/kvm_main.c | 13 ++------ 89 files changed, 167 insertions(+), 328 deletions(-) -- 1.7.3.1.g432b3.dirty From joe@perches.com Fri Nov 5 04:09:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 04:09:12 +0100 (CET) Received: from mail.perches.com ([173.55.12.10]:4055 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490978Ab0KEDIn (ORCPT ); Fri, 5 Nov 2010 04:08:43 +0100 Received: from Joe-Laptop.home (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id 804092436C; Thu, 4 Nov 2010 19:08:27 -0800 (PST) From: Joe Perches To: Jiri Kosina Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/49] arch/mips: Use vzalloc Date: Thu, 4 Nov 2010 20:07:26 -0700 Message-Id: <5c276d41d5e8833fc912b3f60088b1d8b991b21b.1288925424.git.joe@perches.com> X-Mailer: git-send-email 1.7.3.1.g432b3.dirty In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28310 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Signed-off-by: Joe Perches --- arch/mips/sibyte/common/sb_tbprof.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index 87ccdb4..48853ab 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -410,14 +410,13 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp) return -EBUSY; memset(&sbp, 0, sizeof(struct sbprof_tb)); - sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES); + sbp.sbprof_tbbuf = vzalloc(MAX_TBSAMPLE_BYTES); if (!sbp.sbprof_tbbuf) { sbp.open = SB_CLOSED; wmb(); return -ENOMEM; } - memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES); init_waitqueue_head(&sbp.tb_sync); init_waitqueue_head(&sbp.tb_read); mutex_init(&sbp.lock); -- 1.7.3.1.g432b3.dirty From ralf@linux-mips.org Fri Nov 5 11:53:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 11:53:21 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41347 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491893Ab0KEKxO (ORCPT ); Fri, 5 Nov 2010 11:53:14 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA5Aptk7000595; Fri, 5 Nov 2010 10:51:56 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA5Apqdc000592; Fri, 5 Nov 2010 10:51:52 GMT Date: Fri, 5 Nov 2010 10:51:51 +0000 From: Ralf Baechle To: Joe Perches Cc: Jiri Kosina , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 02/49] arch/mips: Use vzalloc Message-ID: <20101105105150.GA32759@linux-mips.org> References: <5c276d41d5e8833fc912b3f60088b1d8b991b21b.1288925424.git.joe@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5c276d41d5e8833fc912b3f60088b1d8b991b21b.1288925424.git.joe@perches.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28311 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.38. Ralf From ralf@linux-mips.org Fri Nov 5 12:12:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 12:12:38 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:50861 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491893Ab0KELMf (ORCPT ); Fri, 5 Nov 2010 12:12:35 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA5BCVvP001272; Fri, 5 Nov 2010 11:12:32 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA5BCS1H001270; Fri, 5 Nov 2010 11:12:29 GMT Date: Fri, 5 Nov 2010 11:12:27 +0000 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, Camm Maguire Subject: Re: [PATCH 1/2] MIPS: Quit clobbering personality bits. Message-ID: <20101105111224.GB32759@linux-mips.org> References: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28312 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Fri Nov 5 16:17:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 16:17:33 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:43533 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491927Ab0KEPRa (ORCPT ); Fri, 5 Nov 2010 16:17:30 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA5FHRWE006936; Fri, 5 Nov 2010 15:17:27 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA5FHPAx006934; Fri, 5 Nov 2010 15:17:25 GMT Date: Fri, 5 Nov 2010 15:17:24 +0000 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, Camm Maguire , Sergei Shtylyov Subject: Re: [PATCH 2/2] MIPS: Don't clobber personality bits in 32-bit sys_personality(). Message-ID: <20101105151724.GA6838@linux-mips.org> References: <1288658588-26801-1-git-send-email-ddaney@caviumnetworks.com> <1288658588-26801-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288658588-26801-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28313 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied, including some whitespace whitewash according to my personal religion :) Thanks, Ralf From David.Daney@caviumnetworks.com Fri Nov 5 23:13:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2010 23:13:04 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16368 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491937Ab0KEWNA (ORCPT ); Fri, 5 Nov 2010 23:13:00 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 05 Nov 2010 15:13:36 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 5 Nov 2010 15:13:35 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 5 Nov 2010 15:13:35 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oA5MCqha017544; Fri, 5 Nov 2010 15:12:53 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oA5MCowN017543; Fri, 5 Nov 2010 15:12:50 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Thomas Gleixner Subject: [PATCH] MIPS: Rework GENERIC_HARDIRQS Kconfig. Date: Fri, 5 Nov 2010 15:12:48 -0700 Message-Id: <1288995168-17511-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 05 Nov 2010 22:13:35.0404 (UTC) FILETIME=[B08EB6C0:01CB7D36] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28314 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Recent changes to CONFIG_GENERIC_HARDIRQS have caused us to start getting: warning: (SMP && SYS_SUPPORTS_SMP) selects IRQ_PER_CPU which has unmet direct dependencies (HAVE_GENERIC_HARDIRQS) Rearranging our Kconfig quiets the message. Signed-off-by: David Daney Cc: Thomas Gleixner --- arch/mips/Kconfig | 16 ++-------------- 1 files changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 67a2fa2..7fc6bd1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -19,6 +19,8 @@ config MIPS select GENERIC_ATOMIC64 if !64BIT select HAVE_DMA_ATTRS select HAVE_DMA_API_DEBUG + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE menu "Machine selection" @@ -1922,20 +1924,6 @@ config CPU_R4400_WORKAROUNDS bool # -# Use the generic interrupt handling code in kernel/irq/: -# -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_IRQ_PROBE - bool - default y - -config IRQ_PER_CPU - bool - -# # - Highmem only makes sense for the 32-bit kernel. # - The current highmem code will only work properly on physically indexed # caches such as R3000, SB1, R7000 or those that look like they're virtually -- 1.7.2.3 From dmitri.vorobiev@gmail.com Sat Nov 6 21:05:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Nov 2010 21:05:11 +0100 (CET) Received: from mail-iw0-f177.google.com ([209.85.214.177]:41412 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491206Ab0KFUFI (ORCPT ); Sat, 6 Nov 2010 21:05:08 +0100 Received: by iwn8 with SMTP id 8so4254052iwn.36 for ; Sat, 06 Nov 2010 13:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=3e/9V/ltUqga1xOxn0cDOFryhGHv8Mfq0Rq+ISuwut4=; b=BKtAEF2GX19wceuP+iDpVEQsdGLZCO4WDe/CSnOD5xm51oL850DAJmammriBu/9w/J BQYmPVau5PVs/Yb0eMXUChSlTV5ZTV56ZmQu6QtD6ClRePWHZ3sWPqxeglrj/hUGi/KH PTELTWolcpcex+Q/D0e46hSh+kxoPHwa68BqQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=JaCpdc2UV2ig1dBvzMD3vSxaKW6kwi3fnIDw/s/UWN5IwdjdZouIh7dayGtRp45C83 naPO/GFGPzuLePtkHGzKZ8QWIExTvvJEWBUDG/vFjG5OkcpSSBgzGDRJoyhI+ZmrrQ4Q cVaCwdtGxaxx80N43RJuARZPQcRuhJzI7iPPI= MIME-Version: 1.0 Received: by 10.231.16.204 with SMTP id p12mr2719364iba.194.1289073904887; Sat, 06 Nov 2010 13:05:04 -0700 (PDT) Received: by 10.231.192.138 with HTTP; Sat, 6 Nov 2010 13:05:04 -0700 (PDT) Date: Sat, 6 Nov 2010 22:05:04 +0200 Message-ID: Subject: build error in current Linus' git tree From: Dmitri Vorobiev To: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28315 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips Hello, The latest Linus tree (151f52f0) yields the following build error for ip22_defconfig: LD .tmp_vmlinux1 drivers/built-in.o: In function `dma_setup': sgiwd93.c:(.text+0x38d9c): undefined reference to `dma_cache_sync' sgiwd93.c:(.text+0x38d9c): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' drivers/built-in.o: In function `sgiseeq_start_xmit': sgiseeq.c:(.text+0x4acfc): undefined reference to `dma_cache_sync' sgiseeq.c:(.text+0x4acfc): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' sgiseeq.c:(.text+0x4ad6c): undefined reference to `dma_cache_sync' sgiseeq.c:(.text+0x4ad6c): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' sgiseeq.c:(.text+0x4ada4): undefined reference to `dma_cache_sync' sgiseeq.c:(.text+0x4ada4): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' sgiseeq.c:(.text+0x4adcc): undefined reference to `dma_cache_sync' sgiseeq.c:(.text+0x4adcc): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' drivers/built-in.o:sgiseeq.c:(.text+0x4aeb4): more undefined references to `dma_cache_sync' follow drivers/built-in.o: In function `sgiseeq_start_xmit': sgiseeq.c:(.text+0x4aeb4): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' sgiseeq.c:(.text+0x4aef0): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' drivers/built-in.o: In function `sgiseeq_interrupt': sgiseeq.c:(.text+0x4afec): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' sgiseeq.c:(.text+0x4b1a0): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' sgiseeq.c:(.text+0x4b1c4): relocation truncated to fit: R_MIPS_26 against `dma_cache_sync' sgiseeq.c:(.text+0x4b1f8): additional relocation overflows omitted from the output make: *** [.tmp_vmlinux1] Error 1 Dmitri From rmh.aybabtu@gmail.com Sun Nov 7 13:31:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 07 Nov 2010 13:31:38 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:58686 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491099Ab0KGMbe (ORCPT ); Sun, 7 Nov 2010 13:31:34 +0100 Received: by wyf22 with SMTP id 22so4496065wyf.36 for ; Sun, 07 Nov 2010 04:31:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:subject:to :cc:in-reply-to:x-mailer:message-id:mime-version:content-type; bh=21TpNNB6G5+W2+jF3xq1AqeNquwbxp1WRfh0VqwunhQ=; b=mwtUn/+L0A5Vc94efoYLVpeIV8Up2toc6EtXlYsw2XdCxuANqzpgOap2b95NbEmTgd RoG8GPku5o/TnPEgth2phRJDlRnfFY1URe+rK3s8FQog8ppDzBmawSsJZc7L/yTr3e+s PhBWe8+iZbMzT9UIHnlz8MKq0Aa//Dm+hKjPQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:subject:to:cc:in-reply-to:x-mailer:message-id :mime-version:content-type; b=PRavX4DN7HygNEqHkzL5ntPla60HwYb6QxjY8+Ji4X72oDnSElSGhkbrES9i7ow3Le 5Jnv0myygJ7+BWq7YX1jaMnKL1qDh3PyNtBCGAY+N9BPd1xp1CcR4DQNxfDW69yYXxGd CfxYJpcMoMi7NiSsGIt8QgL4ACp+sueH8sMPs= Received: by 10.216.179.81 with SMTP id g59mr3177260wem.35.1289133088168; Sun, 07 Nov 2010 04:31:28 -0800 (PST) Received: from thorin ([81.38.198.117]) by mx.google.com with ESMTPS id w8sm2349706wei.21.2010.11.07.04.31.25 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 07 Nov 2010 04:31:27 -0800 (PST) Date: Sun, 07 Nov 2010 13:30:59 +0100 From: Robert Millan Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU To: Robert Millan Cc: David Daney , Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: (from rmh@gnu.org on Thu Nov 4 19:43:08 2010) X-Mailer: Balsa 2.4.1 Message-Id: <1289133059.1547.0@thorin> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-sNv32FuZMrZ1rJb7Jb1J" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28316 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips --=-sNv32FuZMrZ1rJb7Jb1J Content-Type: text/plain; charset=ISO-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable El 04/11/10 19:43:08, en/na Robert Millan va escriure: > David Daney a =E9crit : > > You are claiming that all loongson2 are loongson-2f. =A0Is that=20 > > really true? =A0Or are there other types of loongson2 that are not > > loongson-2f? >=20 > I'll figure out how to distinguish them and send a new patch. I looked at details about CPU identification, and this seems to be broken. See the the notes about PRId in pages 72 and 66, respectively: http://dev.lemote.com/files/resource/documents/Loongson/ls2f/Loongson2FUser= Guide.pdf In both 2E and 2F, the implementation field is the same (0x63). Revision field is the same too, according to docs, and it can't be used anyway (no garantee of consistency). I'm sending a new patch that uses machtype instead. Yes, I know it's a bit of a kludge, but it really seems to be the only way. > Well I appreciate consistency with GCC flag names, Actually, I missread GCC flag (it's dashless). I'm using "loongson2f" as David requested. --=-sNv32FuZMrZ1rJb7Jb1J Content-Type: text/x-patch; charset=us-ascii; name=loongson2f.diff Content-Disposition: attachment; filename=loongson2f.diff Content-Transfer-Encoding: quoted-printable Enable AT_PLATFORM for Loongson 2F CPU. Signed-off-by: Robert Millan diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 71620e1..69905d2 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -5,6 +5,7 @@ * Copyright (C) 1994 - 2006 Ralf Baechle * Copyright (C) 2003, 2004 Maciej W. Rozycki * Copyright (C) 2001, 2004 MIPS Inc. + * Copyright (C) 2010 Robert Millan * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -18,6 +19,7 @@ #include #include =20 +#include #include #include #include @@ -613,7 +615,30 @@ static inline void cpu_probe_legacy(struct cpuinfo_mip= s *c, unsigned int cpu) break; case PRID_IMP_LOONGSON2: c->cputype =3D CPU_LOONGSON2; - __cpu_name[cpu] =3D "ICT Loongson-2"; + /* + * On Loongson 2, PRID doesn't specify sub-class reliably. + * We use machtype info passed by bootloader, when available, + * or otherwise fallback to generic "ICT Loongson-2". + */ + switch (mips_machtype) { + case MACH_LEMOTE_FL2E: + __cpu_name[cpu] =3D "ICT Loongson-2E"; + if (cpu =3D=3D 0) + __elf_platform =3D "loongson2e"; + break; + case MACH_LEMOTE_FL2F: + case MACH_LEMOTE_ML2F7: + case MACH_LEMOTE_YL2F89: + case MACH_DEXXON_GDIUM2F10: + case MACH_LEMOTE_NAS: + case MACH_LEMOTE_LL2F: + __cpu_name[cpu] =3D "ICT Loongson-2F"; + if (cpu =3D=3D 0) + __elf_platform =3D "loongson2f"; + break; + default: + __cpu_name[cpu] =3D "ICT Loongson-2"; + } c->isa_level =3D MIPS_CPU_ISA_III; c->options =3D R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index acd3f2c..74b8c16 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -551,6 +551,14 @@ void __init setup_arch(char **cmdline_p) { cpu_probe(); prom_init(); +#ifdef CONFIG_MACH_LOONGSON + /* + * On Loongson 2, CPU detection is defective. machtype + * heuristics are used instead, but they only work after + * prom_init(). + */ + cpu_probe(); +#endif =20 #ifdef CONFIG_EARLY_PRINTK setup_early_printk(); --=-sNv32FuZMrZ1rJb7Jb1J-- From rmh.aybabtu@gmail.com Sun Nov 7 13:38:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 07 Nov 2010 13:38:44 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:34299 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491099Ab0KGMik (ORCPT ); Sun, 7 Nov 2010 13:38:40 +0100 Received: by wyf22 with SMTP id 22so4499427wyf.36 for ; Sun, 07 Nov 2010 04:38:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:subject:to :x-mailer:message-id:mime-version:content-type; bh=qP4lPjzpxuEsSmTHQzOdXrAIBGW8+jrx5WVorUFk6kA=; b=Gq6nckwqFAX/JpZrN57qoR/IiyD+rOWNiiVTxbUjEoGESK9U4WTPswRpbuwGlXtNmZ Czf2fReJKLGB7UMQdUUP+Zq7ixsG0fqsm9lPC+0YVJPSdiQJspkgyorGPcLUPzgs8n0F TjFtsN5BRm/R5lRvV68BvkJSu0vN8m59g9a5U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:subject:to:x-mailer:message-id:mime-version :content-type; b=djapiWYLkfILPS/5wR4oOMXKPTMkbp+QSupx+w0nr/usgyPeGbaCTMiYTQtsxNX1oz ghpDtLPAEbWl+BDRgJF8tRaZb7K/IgEsVIQwxFH5W1DpkxDntmbFULr7d30dohe0qXnK J0UGoLvtIjnhzwQrgWHhZNWrJakd8uBzO1bmQ= Received: by 10.216.71.66 with SMTP id q44mr4245246wed.44.1289133514424; Sun, 07 Nov 2010 04:38:34 -0800 (PST) Received: from thorin ([81.38.198.117]) by mx.google.com with ESMTPS id p4sm2353465wer.5.2010.11.07.04.38.32 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 07 Nov 2010 04:38:33 -0800 (PST) Date: Sun, 07 Nov 2010 13:38:29 +0100 From: Robert Millan Subject: [PATCH] removed ad-hoc cmdline default To: linux-mips@linux-mips.org X-Mailer: Balsa 2.4.1 Message-Id: <1289133509.1547.1@thorin> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-s9UoF+Gmfng2LtbuSY6p" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28317 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips --=-s9UoF+Gmfng2LtbuSY6p Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Loongson builds have an ad-hoc cmdline default of "console=3DttyS0,115200=20 root=3D/dev/hda1". These settings come from vendor (I remember builds=20 from Lemote branch requiring a "console=3Dtty" override in order to get a=20 working console). At least on my Yeeloong, they're particularly useless: there's no=20 (external) serial port, and the IDE drive is now recognised as /dev/ sda. I recommend removing them. They make sense from a distributor/vendor=20 POV but otherwise are just a nuissance. --=-s9UoF+Gmfng2LtbuSY6p Content-Type: text/x-patch; charset=us-ascii; name=loongson_cmdline.diff Content-Disposition: attachment; filename=loongson_cmdline.diff Content-Transfer-Encoding: quoted-printable Remove ad-hoc cmdline settings. Signed-off-by: Robert Millan diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/commo= n/cmdline.c index 1a06def..353e1d2 100644 --- a/arch/mips/loongson/common/cmdline.c +++ b/arch/mips/loongson/common/cmdline.c @@ -44,10 +44,5 @@ void __init prom_init_cmdline(void) strcat(arcs_cmdline, " "); } =20 - if ((strstr(arcs_cmdline, "console=3D")) =3D=3D NULL) - strcat(arcs_cmdline, " console=3DttyS0,115200"); - if ((strstr(arcs_cmdline, "root=3D")) =3D=3D NULL) - strcat(arcs_cmdline, " root=3D/dev/hda1"); - prom_init_machtype(); } --=-s9UoF+Gmfng2LtbuSY6p-- From ralf@linux-mips.org Sun Nov 7 15:29:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 07 Nov 2010 15:29:40 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46228 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491765Ab0KGO3h (ORCPT ); Sun, 7 Nov 2010 15:29:37 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA7ETY2h001591; Sun, 7 Nov 2010 14:29:34 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA7ETYiF001589; Sun, 7 Nov 2010 14:29:34 GMT Date: Sun, 7 Nov 2010 14:29:33 +0000 From: Ralf Baechle To: Jesper Juhl Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] Check vmalloc return value in vpe_open Message-ID: <20101107142933.GA7999@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28318 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Oct 30, 2010 at 06:37:16PM +0200, Jesper Juhl wrote: > I noticed that the return value of the > vmalloc() call in arch/mips/kernel/vpe.c::vpe_open() is not checked, so we > potentially store a null pointer in v->pbuffer. As far as I can tell this > will be a problem. However, I don't know the mips code at all, so there > may be something, somewhere where I did not look, that handles this in a > safe manner but I couldn't find it. > > To me it looks like we should do what the patch below implements and check > for a null return and then return -ENOMEM in that case. Comments? All users check if the buffer was successfully allocated so the code is safe wrt. to that. Doesn't mean that it's not a pukeogenic piece of code. Look at the use of v->pbuffer in vpe_release for example. First use it the vmalloc'ed memory then carefully check the pointer for being non-NULL before calling vfree. If the pointer could actually be non-NULL that's too late and vfree does that check itself anyway. And more such gems, general uglyness and freedom of concept. It used to be even worse. Ralf From cernekee@gmail.com Sun Nov 7 19:27:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 07 Nov 2010 19:27:15 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:34010 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491828Ab0KGS1L convert rfc822-to-8bit (ORCPT ); Sun, 7 Nov 2010 19:27:11 +0100 Received: by fxm11 with SMTP id 11so3473809fxm.36 for ; Sun, 07 Nov 2010 10:27:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=2NWAvIHGANjKHWGwjifJYmK+ZblCR8LW0bShuUlvTYw=; b=LnJb7/hTdIYprWwZkZQqr3fgKrzRJi95+itaqbAKImSv1c3oG02bDT0ujfB9kXvvRd g1e7BRegbjAeiMYHfJJEFfxEp3A97eS1jZ1E1Qu+KQ+5/zGOMfThCX+iDR3G7/WTAdcJ kKz5W22jfbbg/UQpsRk6iXROjNU57gznJoDBc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Z9s40Z5SlwCjnIH3/tu5FKG+hVsGee3AIIz8TC6/WMTvkZus9JF66/Nj7YUDx/bI8A F6cgkLSAk1xQvSV7+Bpj49kcBqlszAxBn1I150gLF0FLlhNol7+q3KZXLZlZkR3QylBn vBYJs3Knc0Nf3FWchk5cA5e1O003mnAaiFIt8= MIME-Version: 1.0 Received: by 10.223.97.13 with SMTP id j13mr2957154fan.146.1289154422724; Sun, 07 Nov 2010 10:27:02 -0800 (PST) Received: by 10.223.78.134 with HTTP; Sun, 7 Nov 2010 10:27:02 -0800 (PST) In-Reply-To: <20101013075346.GA24052@linux-mips.org> References: <20101013075346.GA24052@linux-mips.org> Date: Sun, 7 Nov 2010 10:27:02 -0800 Message-ID: Subject: Re: [PATCH v3 2/2] MIPS: HIGHMEM DMA on noncoherent MIPS32 processors From: Kevin Cernekee To: Ralf Baechle Cc: dediao@cisco.com, ddaney@caviumnetworks.com, dvomlehn@cisco.com, sshtylyov@mvista.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28319 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips On Wed, Oct 13, 2010 at 12:53 AM, Ralf Baechle wrote: > The good news is that Peter Zijlstra has rewritten kmap to make the need > for manually allocated kmap types go away and his patches are queued to > be merged for 2.6.37.  So I'd like to put this patch on hold until after > his patches are merged. v4 of this patch applies cleanly to 2.6.37-rc1 and tests OK on my hardware: http://patchwork.linux-mips.org/patch/1695/ What do you think about queuing it for 2.6.37? From jj@chaosbits.net Sun Nov 7 19:59:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 07 Nov 2010 19:59:47 +0100 (CET) Received: from swampdragon.chaosbits.net ([90.184.90.115]:20686 "EHLO swampdragon.chaosbits.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491832Ab0KGS7n (ORCPT ); Sun, 7 Nov 2010 19:59:43 +0100 Received: by swampdragon.chaosbits.net (Postfix, from userid 1000) id 31F0F94040; Sun, 7 Nov 2010 19:48:25 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by swampdragon.chaosbits.net (Postfix) with ESMTP id 2A1289403F; Sun, 7 Nov 2010 19:48:25 +0100 (CET) Date: Sun, 7 Nov 2010 19:48:25 +0100 (CET) From: Jesper Juhl To: Ralf Baechle cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH] MIPS VPE support module: don't deref potentially null pbuffer and don't do pointless null check before vfree In-Reply-To: <20101107142933.GA7999@linux-mips.org> Message-ID: References: <20101107142933.GA7999@linux-mips.org> User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28320 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jj@chaosbits.net Precedence: bulk X-list: linux-mips On Sun, 7 Nov 2010, Ralf Baechle wrote: > On Sat, Oct 30, 2010 at 06:37:16PM +0200, Jesper Juhl wrote: > > > I noticed that the return value of the > > vmalloc() call in arch/mips/kernel/vpe.c::vpe_open() is not checked, so we > > potentially store a null pointer in v->pbuffer. As far as I can tell this > > will be a problem. However, I don't know the mips code at all, so there > > may be something, somewhere where I did not look, that handles this in a > > safe manner but I couldn't find it. > > > > To me it looks like we should do what the patch below implements and check > > for a null return and then return -ENOMEM in that case. Comments? > > All users check if the buffer was successfully allocated so the code is > safe wrt. to that. > > Doesn't mean that it's not a pukeogenic piece of code. Look at the use of > v->pbuffer in vpe_release for example. First use it the vmalloc'ed memory > then carefully check the pointer for being non-NULL before calling vfree. > If the pointer could actually be non-NULL that's too late and vfree does > that check itself anyway. And more such gems, general uglyness and > freedom of concept. It used to be even worse. > Thanks for looking at the patch and commenting. I've taken a second look. I still have no way at all to test this, so please take a close look before potentially applying it, but how does this look to you? Don't dereference pbuffer before ttesting it for null. Don't do pointless check of pointer passed to vfree for null as vfree does this itself. Signed-off-by: Jesper Juhl --- vpe.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 3eb3cde..e22f258 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -854,6 +854,9 @@ static int vpe_elfload(struct vpe * v) strcpy(mod.name, "VPE loader"); hdr = (Elf_Ehdr *) v->pbuffer; + if (!hdr) + return -ENOMEM; + len = v->plen; /* Sanity checks against insmoding binaries or wrong arch, @@ -1129,6 +1132,10 @@ static int vpe_release(struct inode *inode, struct file *filp) return -ENODEV; hdr = (Elf_Ehdr *) v->pbuffer; + if (!hdr) { + ret = -ENOMEM; + goto out; + } if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { if (vpe_elfload(v) >= 0) { vpe_run(v); @@ -1141,6 +1148,7 @@ static int vpe_release(struct inode *inode, struct file *filp) ret = -ENOEXEC; } + out: /* It's good to be able to run the SP and if it chokes have a look at the /dev/rt?. But if we reset the pointer to the shared struct we lose what has happened. So perhaps if garbage is sent to the vpe @@ -1150,8 +1158,7 @@ static int vpe_release(struct inode *inode, struct file *filp) v->shared_ptr = NULL; // cleanup any temp buffers - if (v->pbuffer) - vfree(v->pbuffer); + vfree(v->pbuffer); v->plen = 0; return ret; } -- Jesper Juhl http://www.chaosbits.net/ Don't top-post http://www.catb.org/~esr/jargon/html/T/top-post.html Plain text mails only, please. From f.fainelli@gmail.com Mon Nov 8 08:24:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2010 08:24:38 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:48350 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491076Ab0KHHYe convert rfc822-to-8bit (ORCPT ); Mon, 8 Nov 2010 08:24:34 +0100 Received: by wwb13 with SMTP id 13so3341876wwb.24 for ; Sun, 07 Nov 2010 23:24:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:reply-to:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=zIfKtzG7CnvJINJcbJJv1yfPg8U4PDn6UWTbyqofsMU=; b=L6bbdSqeQ/FiVFUXVS9AgAkxSmUWKx8lpV9fo8h2pG2Tsgj1rjQZok8JC+NfC6WQbD gUpxYl6pK58l7hI68Z2ZUJGqO34hJ3PcPQf5sRuhzyC9DYtnlu3jlDds22wbBjSpKWpg BR53rXrxw3RGO7SNCqZBbKEbn+04Ajy/1msEs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:reply-to:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=W29WTeRnhN6o+QRhi3bbYaj7qFYyQC5ioWTmlyLqt0I95UBpNEwgUzeIdOOgFzRz2V CJQ9/Fo4JNeTRcz6JSFtCuCcl1ibZHvrhZN1aea5y8dv1KARFcFLA9HKTfnexdZX9+XY M54P8jfsBBeQU619FtWz5Gacze0cmS7RXw80c= Received: by 10.216.176.8 with SMTP id a8mr3603640wem.93.1289201067728; Sun, 07 Nov 2010 23:24:27 -0800 (PST) Received: from lenovo.localnet (fbx.mimichou.net [82.236.225.16]) by mx.google.com with ESMTPS id w29sm2865478weq.19.2010.11.07.23.24.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 07 Nov 2010 23:24:22 -0800 (PST) From: Florian Fainelli Reply-To: Florian Fainelli To: Andy Shevchenko Subject: Re: [PATCH] arch: mips: use newly introduced hex_to_bin() Date: Mon, 8 Nov 2010 08:26:23 +0100 User-Agent: KMail/1.13.5 (Linux/2.6.36-trunk-amd64; KDE/4.4.5; x86_64; ; ) Cc: linux-kernel@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org References: <1284212009-25708-1-git-send-email-andy.shevchenko@gmail.com> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Message-Id: <201011080826.25676.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28321 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 11 October 2010 18:34:16, Andy Shevchenko a écrit : > Any comments here? Acked-by: Florian Fainelli > > On Sat, Sep 11, 2010 at 4:33 PM, Andy Shevchenko > > wrote: > > Remove custom implementation of hex_to_bin(). > > > > Signed-off-by: Andy Shevchenko > > Cc: Ralf Baechle > > Cc: linux-mips@linux-mips.org > > --- > > arch/mips/rb532/devices.c | 24 +++++++++--------------- > > 1 files changed, 9 insertions(+), 15 deletions(-) > > > > diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c > > index 041fc1a..a969eb8 100644 > > --- a/arch/mips/rb532/devices.c > > +++ b/arch/mips/rb532/devices.c > > @@ -251,28 +251,22 @@ static struct platform_device *rb532_devs[] = { > > > > static void __init parse_mac_addr(char *macstr) > > { > > - int i, j; > > - unsigned char result, value; > > + int i, h, l; > > > > for (i = 0; i < 6; i++) { > > - result = 0; > > - > > if (i != 5 && *(macstr + 2) != ':') > > return; > > > > - for (j = 0; j < 2; j++) { > > - if (isxdigit(*macstr) > > - && (value = > > - isdigit(*macstr) ? *macstr - > > - '0' : toupper(*macstr) - 'A' + 10) < 16) > > { - result = result * 16 + value; > > - macstr++; > > - } else > > - return; > > - } > > + h = hex_to_bin(*macstr++); > > + if (h == -1) > > + return; > > + > > + l = hex_to_bin(*macstr++); > > + if (l == -1) > > + return; > > > > macstr++; > > - korina_dev0_data.mac[i] = result; > > + korina_dev0_data.mac[i] = (h << 4) + l; > > } > > } > > > > -- > > 1.7.2.2 From yyuasa@gmail.com Mon Nov 8 09:25:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2010 09:25:40 +0100 (CET) Received: from mail-iw0-f177.google.com ([209.85.214.177]:63758 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491116Ab0KHIZg (ORCPT ); Mon, 8 Nov 2010 09:25:36 +0100 Received: by iwn8 with SMTP id 8so5817293iwn.36 for ; Mon, 08 Nov 2010 00:25:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=fjR3ry0Pz6SfGtIR2+Ym1jkbtoCQl0WtKI0R95cWhCk=; b=a+L4an5C3DSIXKEgckvmCxZYOQ6DdTfV2OSpzUNCA+Nujf09XCcWx8oNwH9gRtR1ly 9wT9RED1mSKpijG74Iv+9Bm32tiNiVqbZedweK193VaMwDAxeYJ6gZNjPs3eKVCbeIaJ N4izTtYGYkzTtRk1w3ea4MDSuDnExm6ZWYZ1w= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=CMKzQxhvDpF89IqUKq1q96HBYmQcJApcO3hBM8KjeRtrzc1Y8K6i5Qe1dPECBNH3yH jyZQJSPHOyuTtbWRtDDr9KuYUvRTkUnWpkYzGrpEbwN9tNnW4vCsPXODJ9+lyGF9+ki1 YmjA+FRN4sfySBaU80R8+lI6BQzywGaji5jVw= Received: by 10.42.193.135 with SMTP id du7mr3240613icb.321.1289204734255; Mon, 08 Nov 2010 00:25:34 -0800 (PST) Received: from stratos (sannin29007.nirai.ne.jp [203.160.29.7]) by mx.google.com with ESMTPS id 34sm5712900ibi.8.2010.11.08.00.25.32 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 08 Nov 2010 00:25:33 -0800 (PST) Date: Mon, 8 Nov 2010 17:23:52 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: MIPS: alchemy: add return value check for strict_strtoul() Message-Id: <20101108172352.db48962c.yuasa@linux-mips.org> X-Mailer: Sylpheed 3.0.3 (GTK+ 2.16.6; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28322 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips arch/mips/alchemy/devboards/prom.c: In function 'prom_init': arch/mips/alchemy/devboards/prom.c:60: error: ignoring return value of 'strict_strtoul', declared with attribute warn_unused_result Signed-off-by: Yoichi Yuasa --- arch/mips/alchemy/devboards/prom.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index b30df5c..baeb213 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -54,10 +54,9 @@ void __init prom_init(void) prom_init_cmdline(); memsize_str = prom_getenv("memsize"); - if (!memsize_str) + if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; - else - strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); } -- 1.7.3.2 From wuzhangjin@gmail.com Mon Nov 8 14:25:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2010 14:25:48 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:49430 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491772Ab0KHNZp (ORCPT ); Mon, 8 Nov 2010 14:25:45 +0100 Received: by pzk27 with SMTP id 27so1002917pzk.36 for ; Mon, 08 Nov 2010 05:25:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=43siHbyWZfWjGPlOnVBwrNHsQplPu65XcR1Pc6+tl+k=; b=BodpivRfNIk6R/GGhjct7YCDhSq1SmyPtFhxz6kxorOfQP8Vu+T+5ApDtMOioy160g 8caStu841rCqy7hgU5qdJbXB8Jb9wPa3RvkZzJ8pZsMWdRTcuUnvdcnvaW+N/yPPuUyB wpnohX0e5KYhPL+axZE9aeqGu9W4RNekc+a9I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=Zj5a94Sa4i+1zyFoepqIaqrCCgtULP4tDKBysN3kvNYAwndIp8h9v/oBuCjrHL3/Xl 9hnkni24oCJC9p7DUbxnHttnQmZ47eb+2lT8uCogIoT1zr11czBiVRT0Uv1ulQ/k9z+a tmyrgl6IPxio5FjlVOne1R7jt8V0ZqksjAqLY= Received: by 10.142.229.19 with SMTP id b19mr4559332wfh.217.1289222738359; Mon, 08 Nov 2010 05:25:38 -0800 (PST) Received: from localhost.localdomain ([221.220.250.231]) by mx.google.com with ESMTPS id q13sm8104622wfc.5.2010.11.08.05.25.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 08 Nov 2010 05:25:37 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips , Wu Zhangjin Subject: [PATCH] MIPS: Loongson: add return value check for strict_strtoul() Date: Mon, 8 Nov 2010 21:25:24 +0800 Message-Id: <1289222724-8237-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28323 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips cc1: warnings being treated as errors arch/mips/loongson/common/env.c: In function 'prom_init_env': arch/mips/loongson/common/env.c:49: error: ignoring return value of 'strict_strtol', declared with attribute warn_unused_result arch/mips/loongson/common/env.c:50: error: ignoring return value of 'strict_strtol', declared with attribute warn_unused_result arch/mips/loongson/common/env.c:51: error: ignoring return value of 'strict_strtol', declared with attribute warn_unused_result arch/mips/loongson/common/env.c:52: error: ignoring return value of 'strict_strtol', declared with attribute warn_unused_result Signed-off-by: Wu Zhangjin --- arch/mips/loongson/common/env.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c index ae4cff9..11b193f 100644 --- a/arch/mips/loongson/common/env.c +++ b/arch/mips/loongson/common/env.c @@ -29,9 +29,9 @@ unsigned long memsize, highmemsize; #define parse_even_earlier(res, option, p) \ do { \ + int ret; \ if (strncmp(option, (char *)p, strlen(option)) == 0) \ - strict_strtol((char *)p + strlen(option"="), \ - 10, &res); \ + ret = strict_strtol((char *)p + strlen(option"="), 10, &res); \ } while (0) void __init prom_init_env(void) -- 1.7.1 From David.Daney@caviumnetworks.com Mon Nov 8 20:13:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2010 20:13:54 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11727 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491995Ab0KHTNv (ORCPT ); Mon, 8 Nov 2010 20:13:51 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 08 Nov 2010 11:14:26 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 8 Nov 2010 11:14:27 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 8 Nov 2010 11:14:27 -0800 Message-ID: <4CD84BEA.6010607@caviumnetworks.com> Date: Mon, 08 Nov 2010 11:13:46 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Robert Millan CC: Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU References: <1289133059.1547.0@thorin> In-Reply-To: <1289133059.1547.0@thorin> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 08 Nov 2010 19:14:27.0520 (UTC) FILETIME=[298F0400:01CB7F79] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28324 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 11/07/2010 04:30 AM, Robert Millan wrote: > El 04/11/10 19:43:08, en/na Robert Millan va escriure: >> David Daney a écrit : >>> You are claiming that all loongson2 are loongson-2f. Is that >>> really true? Or are there other types of loongson2 that are not >>> loongson-2f? >> >> I'll figure out how to distinguish them and send a new patch. > > I looked at details about CPU identification, and this > seems to be broken. > > See the the notes about PRId in pages 72 and 66, respectively: > http://dev.lemote.com/files/resource/documents/Loongson/ls2f/Loongson2FUserGuide.pdf > > In both 2E and 2F, the implementation field is the same (0x63). > > Revision field is the same too, according to docs, and it can't > be used anyway (no garantee of consistency). I seems weird to me that you cannot get this information from the PRId register. Perhaps the documentation is defective. The Chinese version of the Loongson2E user guide seems to say something about the two lower nibbles of the PRId, but being a non-chinese reader, I have no idea if it would be relevant. I would think that the low order bits of the register can reliably differentiate these two parts. David Daney > > I'm sending a new patch that uses machtype instead. Yes, I know > it's a bit of a kludge, but it really seems to be the only way. > >> Well I appreciate consistency with GCC flag names, > > Actually, I missread GCC flag (it's dashless). I'm using > "loongson2f" as David requested. > From rmh.aybabtu@gmail.com Mon Nov 8 23:27:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2010 23:27:47 +0100 (CET) Received: from mail-iw0-f177.google.com ([209.85.214.177]:51256 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492100Ab0KHW1n convert rfc822-to-8bit (ORCPT ); Mon, 8 Nov 2010 23:27:43 +0100 Received: by iwn8 with SMTP id 8so6711201iwn.36 for ; Mon, 08 Nov 2010 14:27:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type:content-transfer-encoding; bh=ZTb9WojDWbYsd/XAjh8i+u3HyvrzA9UuXFiKGnUjPmA=; b=cb/bUFncvczQ1Pd4iHqlp8uhcvJ//GNmM/uOrIe6mlI6B66a/mwQ+0XKImNj+zx541 UZvlNusmyVMblTBI4xfUYLwSr9l/xXzOJzKmVcs6WvqEhNhntw6808/F7uW+Koi6qXpE BK+B0wxDEzgmRYuY2mxTKwyVnz5w07fFfgC6Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=gmenFC7vTO9N8WvtoyZBW28+9AxXFkWyisGQ6RbHHE9EELyqihwwBxGTV8sEfD9w7b q5drXKe1GuVteomGy56qpf3xZAzSFZVFsYD+iDInQvuJeLbbZfP7ItUx1RBW/XBqbnGF sXuIGVBAl8kZ7903Xe2P4ryGwFFdk2sTLyRNU= MIME-Version: 1.0 Received: by 10.231.36.197 with SMTP id u5mr2080891ibd.110.1289255260185; Mon, 08 Nov 2010 14:27:40 -0800 (PST) Received: by 10.231.170.70 with HTTP; Mon, 8 Nov 2010 14:27:40 -0800 (PST) In-Reply-To: <4CD84BEA.6010607@caviumnetworks.com> References: <1289133059.1547.0@thorin> <4CD84BEA.6010607@caviumnetworks.com> Date: Mon, 8 Nov 2010 23:27:40 +0100 X-Google-Sender-Auth: -LIdXYo83hsrRBx9oCudeA6gw0k Message-ID: Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU From: Robert Millan To: David Daney Cc: Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28325 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips 2010/11/8 David Daney : > I seems weird to me that you cannot get this information from the PRId > register.  Perhaps the documentation is defective. Yes, I agree it's really shortsighted of them, but I don't see any way around it. > The Chinese version of the Loongson2E user guide seems to say something > about the two lower nibbles of the PRId, but being a non-chinese reader, I > have no idea if it would be relevant. > > I would think that the low order bits of the register can reliably > differentiate these two parts. There are English versions for both 2E and 2F. See page 66 of the Loongson 2F document: http://dev.lemote.com/files/resource/documents/Loongson/ls2f/Loongson2FUserGuide.pdf The revision number can distinguish some chip revisions, however there is no guarantee that changes to the chip will necessarily be reflected in the PRId register, or that changes to the revision number necessarily reflect real chip changes. For this reason, software should not rely on the revision number in the PRId register to characterize the chip. Page 72 of the Loongson 2E document (http://www.lemote.com/upfiles/godson2e-user-manual-V0.6.pdf) has the same text. In both documents, the lower byte is defined as "Revision number", and its value is 0x02 (for both 2E and 2F). If you'd rather not assume the docs are correct, I can test if my Yeeloong (Loongson 2F) has 0x02, but then in case it's something higher, would you be willing to assume: rev <= 0x02 --> 2E rev > 0x02 --> 2F or similar logic? This seems risky if we take into account that there's no guarantee from the vendor. -- Robert Millan From David.Daney@caviumnetworks.com Mon Nov 8 23:50:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2010 23:50:54 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17393 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492040Ab0KHWuv (ORCPT ); Mon, 8 Nov 2010 23:50:51 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 08 Nov 2010 14:51:28 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 8 Nov 2010 14:51:29 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 8 Nov 2010 14:51:29 -0800 Message-ID: <4CD87EC3.2060405@caviumnetworks.com> Date: Mon, 08 Nov 2010 14:50:43 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Robert Millan CC: Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU References: <1289133059.1547.0@thorin> <4CD84BEA.6010607@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 08 Nov 2010 22:51:29.0502 (UTC) FILETIME=[7B43C7E0:01CB7F97] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28326 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 11/08/2010 02:27 PM, Robert Millan wrote: > 2010/11/8 David Daney: >> I seems weird to me that you cannot get this information from the PRId >> register. Perhaps the documentation is defective. > > Yes, I agree it's really shortsighted of them, but I don't > see any way around it. > >> The Chinese version of the Loongson2E user guide seems to say something >> about the two lower nibbles of the PRId, but being a non-chinese reader, I >> have no idea if it would be relevant. >> >> I would think that the low order bits of the register can reliably >> differentiate these two parts. > > There are English versions for both 2E and 2F. See page 66 > of the Loongson 2F document: > > http://dev.lemote.com/files/resource/documents/Loongson/ls2f/Loongson2FUserGuide.pdf > > > The revision number can distinguish some chip revisions, however there > is no guarantee > that changes to the chip will necessarily be reflected in the PRId > register, or that changes to > the revision number necessarily reflect real chip changes. For this > reason, software should > not rely on the revision number in the PRId register to characterize the chip. > > > Page 72 of the Loongson 2E document > (http://www.lemote.com/upfiles/godson2e-user-manual-V0.6.pdf) has the > same text. > > In both documents, the lower byte is defined as "Revision number", > and its value is 0x02 (for both 2E and 2F). > > If you'd rather not assume the docs are correct, I can test if > my Yeeloong (Loongson 2F) has 0x02, but then in case it's > something higher, would you be willing to assume: > > rev<= 0x02 --> 2E > rev> 0x02 --> 2F > No, I refuse to assume that. Look at the description of the register in this document: http://dev.lemote.com/files/resource/documents/Loongson/ls2e/godson2e.user.manual.pdf On page 49, it says that bits 0-3 contain the minor version number and bits 4-7 are the major version number (according to a workmate that reads Chinese). I don't know for certain, but it seems plausible that the 2E and 2F will differ in bits 4-7, and bits 0-3 can be ignored. > or similar logic? This seems risky if we take into account > that there's no guarantee from the vendor. > From rmh.aybabtu@gmail.com Tue Nov 9 00:02:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 00:02:44 +0100 (CET) Received: from mail-iw0-f177.google.com ([209.85.214.177]:51166 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492045Ab0KHXCk (ORCPT ); Tue, 9 Nov 2010 00:02:40 +0100 Received: by iwn8 with SMTP id 8so6746756iwn.36 for ; Mon, 08 Nov 2010 15:02:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type; bh=AsXgKyn6YsVwqo2p8+ckF93ZRnVj/KqrGbaxj5OWIC4=; b=Id3AMXQie+9OXfFk7rKjS6sgIa3ked/qKRJE+EqisdHYC2CGusI+ens2M82L2ugLi6 OysZQij15eDstrXOw5adVR+nowia+MN8UGmc8IaesDiotQT2DoAFZnkGOpc+39aQoWsv Ha7+TxdI7PGsGNbY9AzcIc0DR6OZ5vLk+q6kk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; b=ZNNI7FzLa63aAHCpxpxaLNzkCL+21WNZZ+f+D8JaEt5BPxj61NblMyWtfRTDQIl63g KAljvrjixfsrFBTAHf6tSfr0ry4rUf3OJqH3l7fddoi9kNiKYvdDykZeWwoR5MF7OXBH 7Xayiyh0FcEh3xKBnopQMFVgiFFfeQSj64V6A= MIME-Version: 1.0 Received: by 10.231.14.2 with SMTP id e2mr4602841iba.160.1289257359354; Mon, 08 Nov 2010 15:02:39 -0800 (PST) Received: by 10.231.170.70 with HTTP; Mon, 8 Nov 2010 15:02:39 -0800 (PST) In-Reply-To: <4CD87EC3.2060405@caviumnetworks.com> References: <1289133059.1547.0@thorin> <4CD84BEA.6010607@caviumnetworks.com> <4CD87EC3.2060405@caviumnetworks.com> Date: Tue, 9 Nov 2010 00:02:39 +0100 X-Google-Sender-Auth: Xc26dYfUNdv0oKl4uOBUxmgrF0Q Message-ID: Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU From: Robert Millan To: David Daney Cc: Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28327 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips 2010/11/8 David Daney : > Look at the description of the register in this document: > > http://dev.lemote.com/files/resource/documents/Loongson/ls2e/godson2e.user.manual.pdf > > On page 49, it says that bits 0-3 contain the minor version number and bits > 4-7 are the major version number (according to a workmate that reads > Chinese). > > I don't know for certain, but it seems plausible that the 2E and 2F will > differ in bits 4-7, and bits 0-3 can be ignored. Thanks for investigating, but ignoring bits 0-3 doesn't really change anything. Our problem was that bits 0-7 are the same on 2E and 2F (0x02). If we ignore bits 0-3, then our problem is that bits 4-7 are the same on 2E and 2F (0x2). -- Robert Millan From ralf@linux-mips.org Tue Nov 9 05:23:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:23:34 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45719 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492116Ab0KIEXH (ORCPT ); Tue, 9 Nov 2010 05:23:07 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA9101NW010476; Tue, 9 Nov 2010 01:00:02 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA9100NI010472; Tue, 9 Nov 2010 01:00:00 GMT Date: Tue, 9 Nov 2010 00:59:59 +0000 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, Camm Maguire Subject: Re: [PATCH] MIPS: Send proper signal and siginfo on FP emulator faults. Message-ID: <20101109005959.GA9468@linux-mips.org> References: <1287703946-18623-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1287703946-18623-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28328 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Tue Nov 9 05:23:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:24:00 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45725 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492121Ab0KIEXR (ORCPT ); Tue, 9 Nov 2010 05:23:17 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA90mB2n010155; Tue, 9 Nov 2010 00:48:11 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA90m9Qu010153; Tue, 9 Nov 2010 00:48:09 GMT Date: Tue, 9 Nov 2010 00:48:09 +0000 From: Ralf Baechle To: Julia Lawall Cc: kernel-janitors@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/14] arch/mips/pmc-sierra/yosemite/setup.c: delete double assignment Message-ID: <20101109004808.GA10116@linux-mips.org> References: <1288088743-3725-1-git-send-email-julia@diku.dk> <1288088743-3725-7-git-send-email-julia@diku.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288088743-3725-7-git-send-email-julia@diku.dk> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28329 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Oct 26, 2010 at 12:25:35PM +0200, Julia Lawall wrote: > From: Julia Lawall > > Delete successive assignments to the same location. [...] > This change also makes the variable cpu_clock_freq be not used in the > current file. If this is the correct change to plat_time_init, then > perhaps the declaration of that variable should be moved elsewhere, or the > variable should be deleted completely. The 2nd assignment is a temporary override for debugging purpose that is it's there intionsionally. Thanks! Ralf From ralf@linux-mips.org Tue Nov 9 05:24:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:24:29 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45734 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492137Ab0KIEYF (ORCPT ); Tue, 9 Nov 2010 05:24:05 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA8NaQ7n008567; Mon, 8 Nov 2010 23:36:27 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA8NaOMN008565; Mon, 8 Nov 2010 23:36:24 GMT Date: Mon, 8 Nov 2010 23:36:23 +0000 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] AR7: fix loops per jiffies on TNETD7200 devices Message-ID: <20101108233622.GA8381@linux-mips.org> References: <1288565398-30300-1-git-send-email-florian@openwrt.org> <1288565398-30300-2-git-send-email-florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288565398-30300-2-git-send-email-florian@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28330 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Tue Nov 9 05:24:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:25:01 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45734 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492138Ab0KIEYH (ORCPT ); Tue, 9 Nov 2010 05:24:07 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA8NPYW4008207; Mon, 8 Nov 2010 23:25:34 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA8NPX8f008205; Mon, 8 Nov 2010 23:25:33 GMT Date: Mon, 8 Nov 2010 23:25:33 +0000 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] AR7: fix double ar7_gpio_init declaration Message-ID: <20101108232533.GB7806@linux-mips.org> References: <1288565398-30300-1-git-send-email-florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288565398-30300-1-git-send-email-florian@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28331 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Tue Nov 9 05:25:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:25:28 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45734 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492143Ab0KIEYP (ORCPT ); Tue, 9 Nov 2010 05:24:15 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA8MwbfE007436; Mon, 8 Nov 2010 22:58:37 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA8MwawG007434; Mon, 8 Nov 2010 22:58:36 GMT Date: Mon, 8 Nov 2010 22:58:35 +0000 From: Ralf Baechle To: Robert Millan Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] removed ad-hoc cmdline default Message-ID: <20101108225835.GA7167@linux-mips.org> References: <1289133509.1547.1@thorin> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1289133509.1547.1@thorin> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28332 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Nov 07, 2010 at 01:38:29PM +0100, Robert Millan wrote: > Loongson builds have an ad-hoc cmdline default of "console=ttyS0,115200 > root=/dev/hda1". These settings come from vendor (I remember builds > from Lemote branch requiring a "console=tty" override in order to get a > working console). > > At least on my Yeeloong, they're particularly useless: there's no > (external) serial port, and the IDE drive is now recognised as /dev/ > sda. > > I recommend removing them. They make sense from a distributor/vendor > POV but otherwise are just a nuissance. Makes sense to me but I'm not an authoritative expert for all Loongson platforms so I'm going to wait for comments for a few days before I'm going to apply this. Generally forcing options like this is just a bad idea. Ralf From ralf@linux-mips.org Tue Nov 9 05:25:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:25:53 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45734 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492029Ab0KIEYP (ORCPT ); Tue, 9 Nov 2010 05:24:15 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA8NLoG8008031; Mon, 8 Nov 2010 23:21:50 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA8NLnEC008029; Mon, 8 Nov 2010 23:21:49 GMT Date: Mon, 8 Nov 2010 23:21:48 +0000 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, Thomas Gleixner Subject: Re: [PATCH] MIPS: Rework GENERIC_HARDIRQS Kconfig. Message-ID: <20101108232148.GA7806@linux-mips.org> References: <1288995168-17511-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1288995168-17511-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28333 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Nov 05, 2010 at 03:12:48PM -0700, David Daney wrote: > Recent changes to CONFIG_GENERIC_HARDIRQS have caused us to start > getting: > > warning: (SMP && SYS_SUPPORTS_SMP) selects IRQ_PER_CPU which has unmet direct dependencies (HAVE_GENERIC_HARDIRQS) > > Rearranging our Kconfig quiets the message. Thanks, applied. I noticed that some of the same sort of cruft also still exists in other architectures. Ralf From ralf@linux-mips.org Tue Nov 9 05:26:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:26:15 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49024 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492144Ab0KIEYU (ORCPT ); Tue, 9 Nov 2010 05:24:20 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA8Mi56i007023; Mon, 8 Nov 2010 22:44:06 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA8Mi4hn007021; Mon, 8 Nov 2010 22:44:04 GMT Date: Mon, 8 Nov 2010 22:44:04 +0000 From: Ralf Baechle To: Jesper Juhl Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS VPE support module: don't deref potentially null pbuffer and don't do pointless null check before vfree Message-ID: <20101108224404.GA6689@linux-mips.org> References: <20101107142933.GA7999@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28334 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Nov 07, 2010 at 07:48:25PM +0100, Jesper Juhl wrote: > I've taken a second look. I still have no way at all to test this, so > please take a close look before potentially applying it, but how does this > look to you? Testing is a little tricky - it requires a MIPS 34K processor in a configuration with more than one VPE. > Don't dereference pbuffer before ttesting it for null. > Don't do pointless check of pointer passed to vfree for null as vfree does > this itself. I've already checked in something based on your first patch with the other changes I suggested added. Thanks! Ralf From ralf@linux-mips.org Tue Nov 9 05:26:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:26:38 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49028 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492121Ab0KIEYY (ORCPT ); Tue, 9 Nov 2010 05:24:24 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA8M1CR1005850; Mon, 8 Nov 2010 22:01:12 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA8M1CG5005849; Mon, 8 Nov 2010 22:01:12 GMT Date: Mon, 8 Nov 2010 22:01:11 +0000 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: MIPS: alchemy: add return value check for strict_strtoul() Message-ID: <20101108220111.GA5659@linux-mips.org> References: <20101108172352.db48962c.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20101108172352.db48962c.yuasa@linux-mips.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28335 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Tue Nov 9 05:26:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 05:27:00 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49028 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492148Ab0KIEYZ (ORCPT ); Tue, 9 Nov 2010 05:24:25 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA8LaKiK005124; Mon, 8 Nov 2010 21:36:20 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA8LaJ1r005122; Mon, 8 Nov 2010 21:36:19 GMT Date: Mon, 8 Nov 2010 21:36:18 +0000 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips Subject: Re: [PATCH] MIPS: Loongson: add return value check for strict_strtoul() Message-ID: <20101108213618.GA4886@linux-mips.org> References: <1289222724-8237-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1289222724-8237-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28336 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks Wu, applied! Ralf From julia@diku.dk Tue Nov 9 08:10:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 08:10:41 +0100 (CET) Received: from mgw2.diku.dk ([130.225.96.92]:54286 "EHLO mgw2.diku.dk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492018Ab0KIHKc (ORCPT ); Tue, 9 Nov 2010 08:10:32 +0100 Received: from localhost (localhost [127.0.0.1]) by mgw2.diku.dk (Postfix) with ESMTP id 1853A19BFE5; Tue, 9 Nov 2010 08:10:31 +0100 (CET) Received: from mgw2.diku.dk ([127.0.0.1]) by localhost (mgw2.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 04127-17; Tue, 9 Nov 2010 08:10:29 +0100 (CET) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw2.diku.dk (Postfix) with ESMTP id E167E4DC00F; Tue, 9 Nov 2010 08:10:29 +0100 (CET) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id 0842C6DF835; Tue, 9 Nov 2010 08:06:51 +0100 (CET) Received: by ask.diku.dk (Postfix, from userid 3767) id C3BF02085D; Tue, 9 Nov 2010 08:10:29 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id BA1202084B; Tue, 9 Nov 2010 08:10:29 +0100 (CET) Date: Tue, 9 Nov 2010 08:10:29 +0100 (CET) From: Julia Lawall To: Ralf Baechle Cc: kernel-janitors@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/14] arch/mips/pmc-sierra/yosemite/setup.c: delete double assignment In-Reply-To: <20101109004808.GA10116@linux-mips.org> Message-ID: References: <1288088743-3725-1-git-send-email-julia@diku.dk> <1288088743-3725-7-git-send-email-julia@diku.dk> <20101109004808.GA10116@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28337 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julia@diku.dk Precedence: bulk X-list: linux-mips On Tue, 9 Nov 2010, Ralf Baechle wrote: > On Tue, Oct 26, 2010 at 12:25:35PM +0200, Julia Lawall wrote: > > From: Julia Lawall > > > > Delete successive assignments to the same location. > > [...] > > > This change also makes the variable cpu_clock_freq be not used in the > > current file. If this is the correct change to plat_time_init, then > > perhaps the declaration of that variable should be moved elsewhere, or the > > variable should be deleted completely. > > The 2nd assignment is a temporary override for debugging purpose that is > it's there intionsionally. OK, thanks. I indeed suspected that, but I thought it might be worthwhile to mention it, in case it had outlived its usefulness. julia From tung7970@gmail.com Tue Nov 9 08:48:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 08:48:13 +0100 (CET) Received: from mail-fx0-f49.google.com ([209.85.161.49]:43176 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491146Ab0KIHsI (ORCPT ); Tue, 9 Nov 2010 08:48:08 +0100 Received: by fxm11 with SMTP id 11so4888759fxm.36 for ; Mon, 08 Nov 2010 23:48:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=bnt5TvfQOHxa0HWfo/uAGtTvLyFjh+MVqX6p0s1X3GM=; b=eKiRgXaySy2GlgIZDq9OjvendNBUakNrF83T3MmvqnMwO1EUgq+CnGi0JEeU4iHv5/ N7FuBa7ybBWnEB9ZvDS+yXn39p394KikccRp5BqZICD2vSZDdrQO2JGDMPlCRLDI5yQQ 2yzJZ44AFppxnIy+msJ0fNtsb1wnteAP53Qxg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=EMt1RERH0gU9AedAd1DQhlvLYbg3z6a0GcsqPosBO7fnGwg6LwKDOn9DTabBk4gmsZ 3UMYq9VYxbcFvbREsp8YjGZxbtp/WxK6kA01HDJ47SMk+9RAL1Hcc2QLrrcBTvG90kd/ FV9XczTi33SIHY9yZRub9wZd7E2PIhAuVv+Fo= MIME-Version: 1.0 Received: by 10.223.93.202 with SMTP id w10mr4047285fam.22.1289288883210; Mon, 08 Nov 2010 23:48:03 -0800 (PST) Received: by 10.223.86.200 with HTTP; Mon, 8 Nov 2010 23:48:03 -0800 (PST) Date: Tue, 9 Nov 2010 15:48:03 +0800 Message-ID: Subject: [PATCH] MIPS: Separate two consecutive loads in memset.S From: Tony Wu To: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28338 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tung7970@gmail.com Precedence: bulk X-list: linux-mips partial_fixup is used in noreorder block. Separating two consecutive loads can save one cycle on processors with GPR intrelock and can fix load-use on processors that need a load delay slot. Also do so for fwd_fixup. Signed-off-by: Tony Wu --- arch/mips/lib/memset.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index 77dc3b2..606c8a9 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S @@ -161,16 +161,16 @@ FEXPORT(__bzero) .Lfwd_fixup: PTR_L t0, TI_TASK($28) - LONG_L t0, THREAD_BUADDR(t0) andi a2, 0x3f + LONG_L t0, THREAD_BUADDR(t0) LONG_ADDU a2, t1 jr ra LONG_SUBU a2, t0 .Lpartial_fixup: PTR_L t0, TI_TASK($28) - LONG_L t0, THREAD_BUADDR(t0) andi a2, LONGMASK + LONG_L t0, THREAD_BUADDR(t0) LONG_ADDU a2, t1 jr ra LONG_SUBU a2, t0 -- 1.7.1 From wuzhangjin@gmail.com Tue Nov 9 10:48:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 10:48:47 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:47215 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492031Ab0KIJsk convert rfc822-to-8bit (ORCPT ); Tue, 9 Nov 2010 10:48:40 +0100 Received: by wwb31 with SMTP id 31so679017wwb.24 for ; Tue, 09 Nov 2010 01:48:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=s8vCMx5meCHvTAnPiEWEPxirybPRF0Lbt3zw408zF1U=; b=q+FNxMJ9G0TYIXZkQ6Dq76C1qfxPWi1kbByAW2N86xELIh+xHtTNqaUINx2MxOl0qo DhqWd33iKhRnegfqtmP3s0uXtFCgCKsXOCCenqnzJ+TKUYbzEiAiIDA9gsbXBfq7HEVo SOVLhowta9mFT8oXaX+0eQ/Oitx+BfWoWXWmI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Kf9+GSF8dGj7a0gp6mUYPvgdTRF6A+puFBSxBNSbMSgbDRD9uT38P/itM88b+MnkMP 2KdecqYFUt/IaUw/RF1m9iKlxTf6QxoZd5Kr1q5vhgeSTSu0Hx38G/1u8I5z6ztYUg2u yUxgX9mg6T27G4Tg8021E/bB2/DZjsVcFRtls= MIME-Version: 1.0 Received: by 10.216.51.21 with SMTP id a21mr6552244wec.50.1289296114315; Tue, 09 Nov 2010 01:48:34 -0800 (PST) Received: by 10.216.131.88 with HTTP; Tue, 9 Nov 2010 01:48:34 -0800 (PST) In-Reply-To: References: <1289133059.1547.0@thorin> <4CD84BEA.6010607@caviumnetworks.com> <4CD87EC3.2060405@caviumnetworks.com> Date: Tue, 9 Nov 2010 17:48:34 +0800 Message-ID: Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU From: wu zhangjin To: Robert Millan Cc: David Daney , Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28339 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, Robert On Tue, Nov 9, 2010 at 7:02 AM, Robert Millan wrote: > 2010/11/8 David Daney : >> Look at the description of the register in this document: >> >> http://dev.lemote.com/files/resource/documents/Loongson/ls2e/godson2e.user.manual.pdf >> >> On page 49, it says that bits 0-3 contain the minor version number and bits >> 4-7 are the major version number (according to a workmate that reads >> Chinese). >> >> I don't know for certain, but it seems plausible that the 2E and 2F will >> differ in bits 4-7, and bits 0-3 can be ignored. > > Thanks for investigating, but ignoring bits 0-3 doesn't > really change anything.  Our problem was that bits 0-7 > are the same on 2E and 2F (0x02).  If we ignore bits 0-3, > then our problem is that bits 4-7 are the same on 2E > and 2F (0x2). Just rechecked this with a friend from Lemote, in reality, the revision id of Loongson-2F is 0x3, so, my old code should be a reference for you: arch/mips/loongson/common/platform.c PRID_REV_LOONGSON2F and PRID_REV_LOONGSON2E has already been defined in arch/mips/include/asm/cpu.h So, the manual is buggy, perhaps the editors of the manuals did copy and paste for I have found the title of the 2F manual is the same as the 2E manual ;-) Best Regards, Wu Zhangjin From rmh.aybabtu@gmail.com Tue Nov 9 13:24:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 13:24:28 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:63404 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490989Ab0KIMYV (ORCPT ); Tue, 9 Nov 2010 13:24:21 +0100 Received: by ewy19 with SMTP id 19so3349762ewy.36 for ; Tue, 09 Nov 2010 04:24:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:subject:to :cc:references:in-reply-to:x-mailer:message-id:mime-version :content-type; bh=KhepWFfgNBsyvGhKfSBe4KtulHN0sFWpQBzWrZYlpMA=; b=wR/DcIMtcreZseqtuGyyB6cBVw+2dsZzpNqn+7tWbW/C8GFjS8+M4bt3u6TcYUNsIA KYnn5NIc7ZBzWz9tl1b7CKTpOCAUHbNEoHkDmYn7PTt3tChLYfJvdRLOl/xwJPk3h1bp QZlv4JAn1CtAielkF1RU/gWwRuC9iJVAaVNB4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:subject:to:cc:references:in-reply-to:x-mailer :message-id:mime-version:content-type; b=dLJjiBRZ4IqMZAXzbzvM6DHF92+Vc+cFIEvBbHa8TpfEewwcpQ1rIaN0W/ljYVRz7g LIxJvgwAZTdw1+wvrob5OVWNHl3xtRyLJDJpRVoWNPxGyj7T2a5gBhvyv6CruU/IjRhs 4SDfz17U6moCHZ4HrQZxUw7JFvU+hPcRWfNqM= Received: by 10.213.16.69 with SMTP id n5mr5400762eba.26.1289305460984; Tue, 09 Nov 2010 04:24:20 -0800 (PST) Received: from thorin ([83.45.77.222]) by mx.google.com with ESMTPS id b52sm1108629eei.7.2010.11.09.04.24.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 09 Nov 2010 04:24:20 -0800 (PST) Date: Tue, 09 Nov 2010 13:24:02 +0100 From: Robert Millan Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU To: wu zhangjin Cc: David Daney , Aurelien Jarno , Ralf Baechle , linux-mips@linux-mips.org References: In-Reply-To: (from wuzhangjin@gmail.com on Tue Nov 9 10:48:34 2010) X-Mailer: Balsa 2.4.1 Message-Id: <1289305442.31389.0@thorin> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-S8j8ieXtJRiiHPDhJPxR" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28340 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips --=-S8j8ieXtJRiiHPDhJPxR Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable El 09/11/10 10:48:34, en/na wu zhangjin va escriure: > Just rechecked this with a friend from Lemote, in reality, the > revision id of Loongson-2F is 0x3, so, my old code should be a > reference for you: >=20 > arch/mips/loongson/common/platform.c >=20 > PRID_REV_LOONGSON2F and PRID_REV_LOONGSON2E has already been defined > in arch/mips/include/asm/cpu.h >=20 > So, the manual is buggy, perhaps the editors of the manuals did copy > and paste for I have found the title of the 2F manual is the same as > the 2E manual ;-) Thank you! Then I suppose this will do it. --=-S8j8ieXtJRiiHPDhJPxR Content-Type: text/x-patch; charset=us-ascii; name=loongson2f.diff Content-Disposition: attachment; filename=loongson2f.diff Content-Transfer-Encoding: quoted-printable Signed-off-by: Robert Millan diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 71620e1..4341950 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -613,7 +613,20 @@ static inline void cpu_probe_legacy(struct cpuinfo_mip= s *c, unsigned int cpu) break; case PRID_IMP_LOONGSON2: c->cputype =3D CPU_LOONGSON2; - __cpu_name[cpu] =3D "ICT Loongson-2"; + switch (c->processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON2E: + __cpu_name[cpu] =3D "ICT Loongson-2E"; + if (cpu =3D=3D 0) + __elf_platform =3D "loongson2e"; + break; + case PRID_REV_LOONGSON2F: + __cpu_name[cpu] =3D "ICT Loongson-2F"; + if (cpu =3D=3D 0) + __elf_platform =3D "loongson2f"; + break; + default: + __cpu_name[cpu] =3D "ICT Loongson-2"; + } c->isa_level =3D MIPS_CPU_ISA_III; c->options =3D R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | --=-S8j8ieXtJRiiHPDhJPxR-- From ralf@linux-mips.org Tue Nov 9 14:26:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 14:26:33 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49931 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492018Ab0KIN01 (ORCPT ); Tue, 9 Nov 2010 14:26:27 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA9DQOH8027440; Tue, 9 Nov 2010 13:26:24 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA9DQOIP027438; Tue, 9 Nov 2010 13:26:24 GMT Date: Tue, 9 Nov 2010 13:26:23 +0000 From: Ralf Baechle To: Tony Wu Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Separate two consecutive loads in memset.S Message-ID: <20101109132623.GA27392@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28341 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 09, 2010 at 03:48:03PM +0800, Tony Wu wrote: > partial_fixup is used in noreorder block. > > Separating two consecutive loads can save one cycle on processors with > GPR intrelock and can fix load-use on processors that need a load delay slot. > > Also do so for fwd_fixup. Patch is whitespace mangled; please resend. Ralf From BATV+59881b75a86bc7c2a8cd+2634+infradead.org+hch@bombadil.srs.infradead.org Tue Nov 9 15:05:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 15:05:37 +0100 (CET) Received: from bombadil.infradead.org ([18.85.46.34]:55843 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492018Ab0KIOFd (ORCPT ); Tue, 9 Nov 2010 15:05:33 +0100 Received: from hch by bombadil.infradead.org with local (Exim 4.72 #1 (Red Hat Linux)) id 1PFopE-0004tc-1P; Tue, 09 Nov 2010 14:05:28 +0000 Date: Tue, 9 Nov 2010 09:05:28 -0500 From: Christoph Hellwig To: Ajeet Yadav Cc: Christoph Hellwig , "xfs@oss.sgi.com" , linux-mips@linux-mips.org Subject: Re: XFS mounting fails on MIPS Message-ID: <20101109140527.GA13041@infradead.org> References: <20101104125052.GA22429@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org See http://www.infradead.org/rpr.html Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28342 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@infradead.org Precedence: bulk X-list: linux-mips Hi Ajeet, On Tue, Nov 09, 2010 at 04:43:04PM +0530, Ajeet Yadav wrote: > True, its the same system and you were right it was cache VIPT cache problem > the cache hold the stale value even after xlog_bread() update the buffer. > I do not know whether its correct ways to resolve the problem, but the > problem no longer occur. It seems like you more less re-implemented the vmap coherency hooks inside XFS, hardcoded to the mips implementation. The actual helpers would looks something like: static inline void flush_kernel_vmap_range(void *addr, int size) { dma_cache_inv(addr, size); } static inline void invalidate_kernel_vmap_range(void *addr, int size) { dma_cache_inv(addr, size); } For some reason the kernel also expects flush_dcache_page to be implemented by an architecture if we want to implement these two (it's keyed off ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE). Can someone of the mips folks helps with this? The testcase is easy, mounting an xfs filesystem after an unclean shutdown on a machine with virtually indexed caches. From ralf@linux-mips.org Tue Nov 9 16:41:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 16:41:11 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52485 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490959Ab0KIPlI (ORCPT ); Tue, 9 Nov 2010 16:41:08 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oA9FeuH0030651; Tue, 9 Nov 2010 15:40:57 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oA9FetFc030650; Tue, 9 Nov 2010 15:40:55 GMT Date: Tue, 9 Nov 2010 15:40:55 +0000 From: Ralf Baechle To: Robert Millan Cc: wu zhangjin , David Daney , Aurelien Jarno , linux-mips@linux-mips.org Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU Message-ID: <20101109154055.GD10799@linux-mips.org> References: <1289305442.31389.0@thorin> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1289305442.31389.0@thorin> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28343 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 09, 2010 at 01:24:02PM +0100, Robert Millan wrote: > El 09/11/10 10:48:34, en/na wu zhangjin va escriure: > > Just rechecked this with a friend from Lemote, in reality, the > > revision id of Loongson-2F is 0x3, so, my old code should be a > > reference for you: > > > > arch/mips/loongson/common/platform.c > > > > PRID_REV_LOONGSON2F and PRID_REV_LOONGSON2E has already been defined > > in arch/mips/include/asm/cpu.h > > > > So, the manual is buggy, perhaps the editors of the manuals did copy > > and paste for I have found the title of the 2F manual is the same as > > the 2E manual ;-) > > Thank you! Then I suppose this will do it. Looks technically ok; I just have a more stylistic problem with the patch: > + if (cpu == 0) > + __elf_platform = "loongson2e"; Cavium introduced this idion first. Now your patch is repeating it and I'm sure other SMP platforms will soon use it. I don't want a thousand if (cpu == 0) in that file, so can you cook a patch that introduces a helper, something like static void set_elf_platform(const char *plat) { if (cpu == 0) __elf_platform = plat; } Then use that for all assignments to __elf_platform? Thanks. Ralf From wuzhangjin@gmail.com Tue Nov 9 17:26:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 17:26:38 +0100 (CET) Received: from mail-px0-f177.google.com ([209.85.212.177]:61349 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492024Ab0KIQ0P (ORCPT ); Tue, 9 Nov 2010 17:26:15 +0100 Received: by pxi7 with SMTP id 7so1575158pxi.36 for ; Tue, 09 Nov 2010 08:26:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=RISbGM1lH/WpSOoAomKG1Of2r0UtBzMEeihqWvMEWt0=; b=ho9iCWu5aDpbe0QmMo21UDIpAtsk5fPf7s0i9yXrfBvUeC0NzZHe8UjtDBfDtb57mB NoH4keEzoxLVnEVoPThXQ8cuGNhfiWMb9+tRXE7SHO57+up/ehDq9lzrCumDUgUQlVfE U/EmxidwkDpGHF5dFGNP7xHLLX7/hAR7WVtZ4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=vwIhyQvunt9Qr0KDmxI1qBwdflerqz8PbL0/6PkaOHv2bfub7cbLWGN2YveUwCVf/X 9AaIsioAEEOEr/RcNzyYZFdUx5rMm/g40AHvxjuWAENL/U5dadmbh9IhsJYRMJuzysap dID90DZaeAH/AJRDW737LgE61Mr/jAualcaxQ= Received: by 10.142.229.18 with SMTP id b18mr5665018wfh.414.1289319969011; Tue, 09 Nov 2010 08:26:09 -0800 (PST) Received: from localhost.localdomain ([221.220.250.231]) by mx.google.com with ESMTPS id x35sm1882369wfd.1.2010.11.09.08.26.05 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 09 Nov 2010 08:26:08 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, David Daney , Wu Zhangjin Subject: [PATCH 1/2] MIPS: Remove useless comment about kprobe from arch/mips/Makefile Date: Wed, 10 Nov 2010 00:25:53 +0800 Message-Id: <81fc5055a5980ee2877004944553387ed8bdb2b8.1289319749.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28344 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips The commit "MIPS: kprobe: Add support." introduced an useless comment, drops it here. Signed-off-by: Wu Zhangjin --- arch/mips/Makefile | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7c1102e..4a7bfa7 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -259,9 +259,6 @@ endif vmlinux.32: vmlinux $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ - -#obj-$(CONFIG_KPROBES) += kprobes.o - # # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit # ELF files from 32-bit files by conversion. -- 1.7.1 From wuzhangjin@gmail.com Tue Nov 9 17:26:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 17:27:03 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:64650 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492028Ab0KIQ0y (ORCPT ); Tue, 9 Nov 2010 17:26:54 +0100 Received: by pwj8 with SMTP id 8so476324pwj.36 for ; Tue, 09 Nov 2010 08:26:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=mcMfl7EPLUxEcSTUwYi0XXAG2azpdI74kuft3weCIrA=; b=YHHHGb5nfcEJYq0Z5O8mY379g1dfCcJOHHjysk/6g/r1cBWf/J0mYVAP9pFreJHgz3 yIV19AquQeOnC540jlLuwrxevfN6yZ4g2YQItSIqTBxnQ3tiifoYMCTVCXxco39/rPiZ m1ryReYOskJJ5p2Dmb71gUzJ0hoteQzB3bfsQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=CK3gIQ2xUS1a1JSr6vfm2y7qG34EQPt81QZjLe6OkqhKUqn/eH6k4s+5ZDAFTQWQ/H qTdz2+ni/vZ1/LPuLc2O4bPoSmOoytXr6Szcos6tWHF6IktvlgzBaq3FUVHWdsAGIDdb 05/OL6zXvC0fOQOsGXqHwWwIWwjUTH/lx1T9w= Received: by 10.142.163.6 with SMTP id l6mr1676522wfe.406.1289320007633; Tue, 09 Nov 2010 08:26:47 -0800 (PST) Received: from localhost.localdomain ([221.220.250.231]) by mx.google.com with ESMTPS id x4sm1872040wfd.21.2010.11.09.08.26.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 09 Nov 2010 08:26:46 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Sam Ravnborg , Wu Zhangjin Subject: [PATCH 2/2] MIPS: Quiet the building output of vmlinux.32 and vmlinux.64 Date: Wed, 10 Nov 2010 00:26:34 +0800 Message-Id: <6f2125c69f79f864518a20af44568f81ce309c77.1289319749.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <81fc5055a5980ee2877004944553387ed8bdb2b8.1289319749.git.wuzhangjin@gmail.com> References: <81fc5055a5980ee2877004944553387ed8bdb2b8.1289319749.git.wuzhangjin@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28345 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Based on quiet_cmd_X and cmd_X, this patch quiets the building output of vmlinux.32 and vmlinux.64. Signed-off-by: Wu Zhangjin --- arch/mips/Makefile | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 4a7bfa7..d1f132d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -256,15 +256,19 @@ endif # Other need ECOFF, so we build a 32-bit ELF binary for them which we then # convert to ECOFF using elf2ecoff. # +quiet_cmd_32 = OBJCOPY $@ + cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ vmlinux.32: vmlinux - $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ + $(call cmd,32) # # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit # ELF files from 32-bit files by conversion. # +quiet_cmd_64 = OBJCOPY $@ + cmd_64 = $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ vmlinux.64: vmlinux - $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ + $(call cmd,64) all: $(all-y) -- 1.7.1 From David.Daney@caviumnetworks.com Tue Nov 9 21:35:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2010 21:36:01 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11327 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492057Ab0KIUfz (ORCPT ); Tue, 9 Nov 2010 21:35:55 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 09 Nov 2010 12:36:31 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 9 Nov 2010 12:36:33 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 9 Nov 2010 12:36:32 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oA9KZkAO022141; Tue, 9 Nov 2010 12:35:46 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oA9KZhFx022140; Tue, 9 Nov 2010 12:35:43 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Steven Rostedt , Jason Baron Subject: [PATCH v3] jump label: Add MIPS support. Date: Tue, 9 Nov 2010 12:35:41 -0800 Message-Id: <1289334941-22107-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 09 Nov 2010 20:36:33.0015 (UTC) FILETIME=[CBCBA870:01CB804D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28346 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips When in Rome... In order not to be left behind, we add jump label support for MIPS. Tested on 64-bit big endian (Octeon), and 32-bit little endian (malta/qemu). Signed-off-by: David Daney Cc: Steven Rostedt Cc: Jason Baron --- Now that the core jump label support has been merged, this patch easily go via Ralf's tree. The only changes from v2 are Makefile and Kconfig improvements. arch/mips/Kconfig | 1 + arch/mips/include/asm/jump_label.h | 48 ++++++++++++++++++++++++++++++++++ arch/mips/kernel/Makefile | 2 + arch/mips/kernel/jump_label.c | 50 ++++++++++++++++++++++++++++++++++++ arch/mips/kernel/module.c | 5 +++ 5 files changed, 106 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/jump_label.h create mode 100644 arch/mips/kernel/jump_label.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7fc6bd1..4419e83 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -21,6 +21,7 @@ config MIPS select HAVE_DMA_API_DEBUG select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE + select HAVE_ARCH_JUMP_LABEL menu "Machine selection" diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h new file mode 100644 index 0000000..7622ccf --- /dev/null +++ b/arch/mips/include/asm/jump_label.h @@ -0,0 +1,48 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2010 Cavium Networks, Inc. + */ +#ifndef _ASM_MIPS_JUMP_LABEL_H +#define _ASM_MIPS_JUMP_LABEL_H + +#include + +#ifdef __KERNEL__ + +#define JUMP_LABEL_NOP_SIZE 4 + +#ifdef CONFIG_64BIT +#define WORD_INSN ".dword" +#else +#define WORD_INSN ".word" +#endif + +#define JUMP_LABEL(key, label) \ + do { \ + asm goto("1:\tnop\n\t" \ + "nop\n\t" \ + ".pushsection __jump_table, \"a\"\n\t" \ + WORD_INSN " 1b, %l[" #label "], %0\n\t" \ + ".popsection\n\t" \ + : : "i" (key) : : label); \ + } while (0) + + +#endif /* __KERNEL__ */ + +#ifdef CONFIG_64BIT +typedef u64 jump_label_t; +#else +typedef u32 jump_label_t; +#endif + +struct jump_entry { + jump_label_t code; + jump_label_t target; + jump_label_t key; +}; + +#endif /* _ASM_MIPS_JUMP_LABEL_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 22b2e0e..35ce5a5 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -106,4 +106,6 @@ obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_JUMP_LABEL) += jump_label.o + CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) diff --git a/arch/mips/kernel/jump_label.c b/arch/mips/kernel/jump_label.c new file mode 100644 index 0000000..52d3c70 --- /dev/null +++ b/arch/mips/kernel/jump_label.c @@ -0,0 +1,50 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2010 Cavium Networks, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define J_RANGE_MASK ((1ul << 28) - 1) + +void arch_jump_label_transform(struct jump_entry *e, + enum jump_label_type type) +{ + union mips_instruction insn; + union mips_instruction *insn_p = + (union mips_instruction *)(unsigned long)e->code; + + /* Jump only works within a 256MB aligned region. */ + BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK)); + + /* Target must have 4 byte alignment. */ + BUG_ON((e->target & 3) != 0); + + if (type == JUMP_LABEL_ENABLE) { + insn.j_format.opcode = j_op; + insn.j_format.target = (e->target & J_RANGE_MASK) >> 2; + } else { + insn.word = 0; /* nop */ + } + + get_online_cpus(); + mutex_lock(&text_mutex); + *insn_p = insn; + + flush_icache_range((unsigned long)insn_p, + (unsigned long)insn_p + sizeof(*insn_p)); + + mutex_unlock(&text_mutex); + put_online_cpus(); +} diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index 6f51dda..bb9cde4 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -30,6 +30,8 @@ #include #include #include +#include + #include /* MODULE_START */ struct mips_hi16 { @@ -390,6 +392,9 @@ int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *s; char *secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; + /* Make jump label nops. */ + jump_label_apply_nops(me); + INIT_LIST_HEAD(&me->arch.dbe_list); for (s = sechdrs; s < sechdrs + hdr->e_shnum; s++) { if (strcmp("__dbe_table", secstrings + s->sh_name) != 0) -- 1.7.2.3 From tung7970@gmail.com Wed Nov 10 14:48:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2010 14:48:48 +0100 (CET) Received: from mail-pv0-f177.google.com ([74.125.83.177]:37991 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491176Ab0KJNsp (ORCPT ); Wed, 10 Nov 2010 14:48:45 +0100 Received: by pvg7 with SMTP id 7so109394pvg.36 for ; Wed, 10 Nov 2010 05:48:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:date:from:to:subject :message-id:mime-version:content-type:content-disposition:user-agent; bh=bnt5TvfQOHxa0HWfo/uAGtTvLyFjh+MVqX6p0s1X3GM=; b=kIMK3o9Zmuk73KN8F0U68n54Blp9gdZ5/rUcL3ktlqLxApivxj8bbLD8EWY0LecLLX kE9bmlHtM5K7Kw5ijiIPy8SFHeYGTSQUtGGUiDPfOgLOB04qcFTZurForD4oChxTfgjq 8YLzxLCtHGh/EFmQAdE4Z2OkRUltSrZtS6r2I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:subject:message-id:mime-version:content-type :content-disposition:user-agent; b=R+SMkiZvdQEoRP5kuN+dpgvFaQy/QLJANkP89N07IVHgMmPaPwYeeSeVLTybL3dO0S unweTcNiR2JP88Rl6cjYxxAE8A9/4uan4ND0DOa+0iAK/xlWZGMTXoP/8gsknkIFdnEn Nol9gtSO7X/LQa7HQEU7eJsG0eIm46K3Efkzw= Received: by 10.143.44.1 with SMTP id w1mr6658769wfj.447.1289396918101; Wed, 10 Nov 2010 05:48:38 -0800 (PST) Received: from metis (220-138-164-213.dynamic.hinet.net [220.138.164.213]) by mx.google.com with ESMTPS id v19sm878017wfh.0.2010.11.10.05.48.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 10 Nov 2010 05:48:35 -0800 (PST) Date: Wed, 10 Nov 2010 21:48:15 +0800 From: Tony Wu To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH v2] MIPS: Separate two consecutive loads in memset.S Message-ID: <20101110134815.GA28312@metis> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28347 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tung7970@gmail.com Precedence: bulk X-list: linux-mips partial_fixup is used in noreorder block. Separating two consecutive loads can save one cycle on processors with GPR intrelock and can fix load-use on processors that need a load delay slot. Also do so for fwd_fixup. Signed-off-by: Tony Wu --- arch/mips/lib/memset.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index 77dc3b2..606c8a9 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S @@ -161,16 +161,16 @@ FEXPORT(__bzero) .Lfwd_fixup: PTR_L t0, TI_TASK($28) - LONG_L t0, THREAD_BUADDR(t0) andi a2, 0x3f + LONG_L t0, THREAD_BUADDR(t0) LONG_ADDU a2, t1 jr ra LONG_SUBU a2, t0 .Lpartial_fixup: PTR_L t0, TI_TASK($28) - LONG_L t0, THREAD_BUADDR(t0) andi a2, LONGMASK + LONG_L t0, THREAD_BUADDR(t0) LONG_ADDU a2, t1 jr ra LONG_SUBU a2, t0 -- 1.7.1 From ralf@linux-mips.org Wed Nov 10 15:09:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2010 15:09:58 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36665 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491183Ab0KJOJ4 (ORCPT ); Wed, 10 Nov 2010 15:09:56 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oAAE9pDj030297; Wed, 10 Nov 2010 14:09:53 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oAAE9n7J030286; Wed, 10 Nov 2010 14:09:49 GMT Date: Wed, 10 Nov 2010 14:09:45 +0000 From: Ralf Baechle To: Tony Wu Cc: linux-mips@linux-mips.org Subject: Re: [PATCH v2] MIPS: Separate two consecutive loads in memset.S Message-ID: <20101110140945.GA29377@linux-mips.org> References: <20101110134815.GA28312@metis> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20101110134815.GA28312@metis> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28348 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 10, 2010 at 09:48:15PM +0800, Tony Wu wrote: This new version applies cleanly, so applied. Only R2000/R3000 class processors are lacking the the load-user interlock and even some of those got it retrofitted. With R2000/R3000 being fairly uncommon these days the impact of this bug should be minor but the last R3000 DECstation user on this list may be interested ;-) Thanks a lot! Ralf From Andrei.Ardelean@idt.com Wed Nov 10 16:49:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2010 16:49:43 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:42575 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491189Ab0KJPtk convert rfc822-to-8bit (ORCPT ); Wed, 10 Nov 2010 16:49:40 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oAAFnWPB031635 for ; Wed, 10 Nov 2010 07:49:32 -0800 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oAAFnUBo008726 for ; Wed, 10 Nov 2010 07:49:31 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oAAFnUU19135 for ; Wed, 10 Nov 2010 07:49:30 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Kernel is stuck in Calibrating delay loop Date: Wed, 10 Nov 2010 07:49:27 -0800 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Kernel is stuck in Calibrating delay loop Thread-Index: AcuA7trpS8wH/gWjRwSJWvIpood+/g== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28349 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, I am porting MIPS Malta on a new platform and during the boot process the Kernel remains in a infinite loop in "Calibrating delay loop ..." in calibrate.c. I checked and the timer interrupt which is supposed to be wired on h/w 5 interrupt (MIPS 7 irq) is not activated in MIPS Status.IM7 register. Where in the Kernel the MIPS irq wired to the timer interrupt needs to be enabled? Can I use enable_irq()? On my platform I don't have any 8259 and I am trying to use MIPS Count/Compare internal timer for Kernel tick. Thanks, Andrei From macro@linux-mips.org Thu Nov 11 00:30:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 00:30:59 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:35424 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491918Ab0KJXa4 (ORCPT ); Thu, 11 Nov 2010 00:30:56 +0100 Date: Wed, 10 Nov 2010 23:30:56 +0000 (GMT) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Tony Wu , linux-mips@linux-mips.org Subject: Re: [PATCH v2] MIPS: Separate two consecutive loads in memset.S In-Reply-To: <20101110140945.GA29377@linux-mips.org> Message-ID: References: <20101110134815.GA28312@metis> <20101110140945.GA29377@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28350 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, 10 Nov 2010, Ralf Baechle wrote: > Only R2000/R3000 class processors are lacking the the load-user interlock > and even some of those got it retrofitted. With R2000/R3000 being fairly > uncommon these days the impact of this bug should be minor but the last > R3000 DECstation user on this list may be interested ;-) Good catch Tony, thanks! Maciej From wuzhangjin@gmail.com Thu Nov 11 02:23:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 02:23:53 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:37316 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491938Ab0KKBXu convert rfc822-to-8bit (ORCPT ); Thu, 11 Nov 2010 02:23:50 +0100 Received: by wyf22 with SMTP id 22so1417915wyf.36 for ; Wed, 10 Nov 2010 17:23:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=jJFUFXiYE6ovFXQTstHwjBHgbTnge0QNKnSvz1fPlXk=; b=ceK4aSW2dKi+8Tr+V0CbP3ZWMJJxsSyn8o4+2eMpvWwavEwlrXu/AAxLDw71vC8fo5 58PF3G6tkrGtoBzUjXV7EZ7Z9JriT6X5zD7Fjwf14SYxpMh8AK9wBS0xeJ9mOIwoZF6c ZtUTO6pwiqc5aIBvRZbQCLU6VZXtA5qZOi15E= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=FDz80fN+bErDFfsnz+Wo3sB69u8wZ0GuEl7z9Sb8TanjberiKbonL3PLi48roxAqdv Kj2cU2KDNVzr400Qm7SUUrvx9ve9//8LsO4Bskso86Wf5ZHaUuZibmG+TLEFVfXyZTRg WYkc2ri9bIkdIFMDMKsXpsHW2jwjo9aiXa+tk= MIME-Version: 1.0 Received: by 10.216.51.21 with SMTP id a21mr86798wec.50.1289438624715; Wed, 10 Nov 2010 17:23:44 -0800 (PST) Received: by 10.216.131.88 with HTTP; Wed, 10 Nov 2010 17:23:44 -0800 (PST) In-Reply-To: References: Date: Thu, 11 Nov 2010 09:23:44 +0800 Message-ID: Subject: Re: Kernel is stuck in Calibrating delay loop From: wu zhangjin To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28351 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, Nov 10, 2010 at 11:49 PM, Ardelean, Andrei wrote: > Hi, > > I am porting MIPS Malta on a new platform and during the boot process > the Kernel remains in a infinite loop in "Calibrating delay loop ..." in > calibrate.c. > I checked and the timer interrupt which is supposed to be wired on h/w 5 > interrupt (MIPS 7 irq) is not activated in MIPS Status.IM7 register. > Where in the Kernel the MIPS irq wired to the timer interrupt needs to > be enabled?  Can I use enable_irq()? > On my platform I don't have any 8259 and I am trying to use MIPS > Count/Compare internal timer for Kernel tick. Did you select the r4k timer for your platform? arch/mips/Kconfig: config MIPS_MALTA [snip] select CEVT_R4K select CSRC_R4K [snip] And please check if arch/mips/kernel/*r4k.c are compiled into your kernel image. Regards, Wu Zhangjin From ajeet.yadav.77@gmail.com Thu Nov 11 05:57:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 05:57:16 +0100 (CET) Received: from mail-qy0-f177.google.com ([209.85.216.177]:43731 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491102Ab0KKE5L (ORCPT ); Thu, 11 Nov 2010 05:57:11 +0100 Received: by qyk2 with SMTP id 2so1499220qyk.15 for ; Wed, 10 Nov 2010 20:57:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=oiQ2Dtu4EYBW0WDzehrquzkiiNj++SZR0wsq885KmgY=; b=I5sr8MR5SK2Ts8MYif+ZPJRblRABXdwf+uOSKGeufmDbX1uaqpBzJr3Pqf6R2nyGnW WMQ9KxNQxwOVWmmWWWh9QOHG+1J6GFwZpYCC0SVnGv2NZnllpxzC3tCPQh+pL791k2Qt 00Edb6lIRoYZTEVMTpEnMHzwv5xHuHcxFo9F4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=mkjUhVbd4Zp+eWZo/BCVbXETdmM3ePQVooxsGDRVoTXroCJRPLuZc5nEhlibgXrAUX 1yzAHaTovnqOh29NVu881MGnrsSLcEr2OYCQoKacupNjIQFCgyO1FYv+n8+T7CUl2Ssg ulDPaEySZFpEhfLkHFHQVbSdqDcXOMRL4x4is= MIME-Version: 1.0 Received: by 10.229.232.15 with SMTP id js15mr370275qcb.161.1289451425254; Wed, 10 Nov 2010 20:57:05 -0800 (PST) Received: by 10.220.162.69 with HTTP; Wed, 10 Nov 2010 20:57:05 -0800 (PST) In-Reply-To: <20101109140527.GA13041@infradead.org> References: <20101104125052.GA22429@infradead.org> <20101109140527.GA13041@infradead.org> Date: Thu, 11 Nov 2010 10:27:05 +0530 Message-ID: Subject: Re: XFS mounting fails on MIPS From: Ajeet Yadav To: Christoph Hellwig Cc: "xfs@oss.sgi.com" , linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=0016363b90c42850810494bfce0f Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28352 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ajeet.yadav.77@gmail.com Precedence: bulk X-list: linux-mips --0016363b90c42850810494bfce0f Content-Type: text/plain; charset=ISO-8859-1 Coming back to problem, I wish to know about this problem Linux XFS version : 2.6.34 Architecure: MIPS I am getting the following error during mount. XFS mounting filesystem sda2 Starting XFS recovery on filesystem: sda2 (logdev: internal) XFS internal error XFS_WANT_CORRUPTED_GOTO at line 1518 of file fs/xfs/xfs_alloc.c. Caller 0x801174a0 Call Trace: [<800050bc>] dump_stack+0x8/0x34 [<80115254>] xfs_free_ag_extent+0x128/0x7a8 [<801174a0>] xfs_free_extent+0xa0/0xcc [<80155278>] xlog_recover_process_efi+0x15c/0x210 [<801553cc>] xlog_recover_process_efis+0xa0/0x12c [<8015590c>] xlog_recover_finish+0x28/0xcc [<8015d4fc>] xfs_mountfs+0x4f0/0x5d0 [<801758d8>] xfs_fs_fill_super+0x158/0x360 [<8008b67c>] get_sb_bdev+0x11c/0x1c4 [<801734e0>] xfs_fs_get_sb+0x20/0x2c [<80089cd0>] vfs_kern_mount+0x68/0xd0 [<80089d9c>] do_kern_mount+0x54/0x118 [<800a4e98>] do_mount+0x7f0/0x86c [<800a4fb0>] sys_mount+0x9c/0xf8 [<80002124>] stack_done+0x20/0x3c Filesystem "sda2": XFS internal error xfs_trans_cancel at line 1161 of file fs/xfs/xfs_trans.c. Caller 0x801552f8 Call Trace: [<800050bc>] dump_stack+0x8/0x34 [<801601f0>] xfs_trans_cancel+0x88/0x118 [<801552f8>] xlog_recover_process_efi+0x1dc/0x210 [<801553cc>] xlog_recover_process_efis+0xa0/0x12c [<8015590c>] xlog_recover_finish+0x28/0xcc [<8015d4fc>] xfs_mountfs+0x4f0/0x5d0 [<801758d8>] xfs_fs_fill_super+0x158/0x360 [<8008b67c>] get_sb_bdev+0x11c/0x1c4 [<801734e0>] xfs_fs_get_sb+0x20/0x2c [<80089cd0>] vfs_kern_mount+0x68/0xd0 [<80089d9c>] do_kern_mount+0x54/0x118 [<800a4e98>] do_mount+0x7f0/0x86c [<800a4fb0>] sys_mount+0x9c/0xf8 [<80002124>] stack_done+0x20/0x3c xfs_force_shutdown(sda2,0x8) called from line 1162 of file fs/xfs/xfs_trans.c. Return address = 0x80160204 Filesystem "sda2": Corruption of in-memory data detected. Shutting down filesystem: sda2 Please umount the filesystem, and rectify the problem(s) Failed to recover EFIs on filesystem: sda2 XFS: log mount finish failed With Regards Ajeet Yadav On Tue, Nov 9, 2010 at 7:35 PM, Christoph Hellwig wrote: > Hi Ajeet, > > On Tue, Nov 09, 2010 at 04:43:04PM +0530, Ajeet Yadav wrote: > > True, its the same system and you were right it was cache VIPT cache > problem > > the cache hold the stale value even after xlog_bread() update the buffer. > > I do not know whether its correct ways to resolve the problem, but the > > problem no longer occur. > > It seems like you more less re-implemented the vmap coherency hooks > inside XFS, hardcoded to the mips implementation. > > The actual helpers would looks something like: > > static inline void flush_kernel_vmap_range(void *addr, int size) > { > dma_cache_inv(addr, size); > } > > static inline void invalidate_kernel_vmap_range(void *addr, int size) > { > dma_cache_inv(addr, size); > } > > For some reason the kernel also expects flush_dcache_page to be > implemented by an architecture if we want to implement these two > (it's keyed off ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE). > > Can someone of the mips folks helps with this? > > The testcase is easy, mounting an xfs filesystem after an unclean > shutdown on a machine with virtually indexed caches. > > --0016363b90c42850810494bfce0f Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Coming back to problem, I wish to know about this problem
Linux XFS version : 2.6.34
Architecure: MIPS
I am getting the following error during mount.
=A0
XFS mounting filesystem sda2
Starting XFS recovery on filesystem: sda2 = (logdev: internal)
XFS internal error XFS_WANT_CORRUPTED_GOTO at line 15= 18 of file fs/xfs/xfs_alloc.c.=A0 Caller 0x801174a0
Call Trace:
[<800050bc>] dump_stack+0x8/0x34
[<80115254>]= xfs_free_ag_extent+0x128/0x7a8
[<801174a0>] xfs_free_extent+0xa0/= 0xcc
[<80155278>] xlog_recover_process_efi+0x15c/0x210
[<801= 553cc>] xlog_recover_process_efis+0xa0/0x12c
[<8015590c>] xlog_recover_finish+0x28/0xcc
[<8015d4fc>] xfs_= mountfs+0x4f0/0x5d0
[<801758d8>] xfs_fs_fill_super+0x158/0x360
= [<8008b67c>] get_sb_bdev+0x11c/0x1c4
[<801734e0>] xfs_fs_get= _sb+0x20/0x2c
[<80089cd0>] vfs_kern_mount+0x68/0xd0
[<80089d9c>] do_kern_m= ount+0x54/0x118
[<800a4e98>] do_mount+0x7f0/0x86c
[<800a4fb0= >] sys_mount+0x9c/0xf8
[<80002124>] stack_done+0x20/0x3c
=A0
Filesystem "sda2": XFS internal error xfs_trans_cancel at = line 1161 of file fs/xfs/xfs_trans.c.=A0 Caller 0x801552f8
=A0
Call T= race:
[<800050bc>] dump_stack+0x8/0x34
[<801601f0>] xfs_t= rans_cancel+0x88/0x118
[<801552f8>] xlog_recover_process_efi+0x1dc/0x210
[<801553cc>= ;] xlog_recover_process_efis+0xa0/0x12c
[<8015590c>] xlog_recover_= finish+0x28/0xcc
[<8015d4fc>] xfs_mountfs+0x4f0/0x5d0
[<8017= 58d8>] xfs_fs_fill_super+0x158/0x360
[<8008b67c>] get_sb_bdev+0x11c/0x1c4
[<801734e0>] xfs_fs_get= _sb+0x20/0x2c
[<80089cd0>] vfs_kern_mount+0x68/0xd0
[<80089d= 9c>] do_kern_mount+0x54/0x118
[<800a4e98>] do_mount+0x7f0/0x86c=
[<800a4fb0>] sys_mount+0x9c/0xf8
[<80002124>] stack_done+0x2= 0/0x3c
=A0
xfs_force_shutdown(sda2,0x8) called from line 1162 of file= fs/xfs/xfs_trans.c.=A0 Return address =3D 0x80160204
Filesystem "s= da2": Corruption of in-memory data detected.=A0 Shutting down filesyst= em: sda2
Please umount the filesystem, and rectify the problem(s)
Failed to recov= er EFIs on filesystem: sda2
XFS: log mount finish failed
=A0
With Regards
Ajeet Yadav

On Tue, Nov 9, 2010 at 7:35 PM, Christoph Hellwig <hch@infradead.org> wrote:
Hi Ajeet,

On Tue, Nov 09, 2010 at 04:43:04PM +0530, Ajeet Yadav wrote:
> True, its the same system and you were right it was cache VIPT cache p= roblem
> the cache hold the stale value even after xlog_bread() update the buff= er.
> I do not know whether its correct ways to resolve the problem, but the=
> problem no longer occur.

It seems like you more less re-implemented the vmap coherency hooks inside XFS, hardcoded to the mips implementation.

The actual helpers would looks something like:

static inline void flush_kernel_vmap_range(void *addr, int size)
{
=A0 =A0 =A0 =A0dma_cache_inv(addr, size);
}

static inline void invalidate_kernel_vmap_range(void *addr, int size)
{
=A0 =A0 =A0 =A0dma_cache_inv(addr, size);
}

For some reason the kernel also expects flush_dcache_page to be
implemented by an architecture if we want to implement these two
(it's keyed off ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE).

Can someone of the mips folks helps with this?

The testcase is easy, mounting an xfs filesystem after an unclean
shutdown on a machine with virtually indexed caches.


--0016363b90c42850810494bfce0f-- From ajeet.yadav.77@gmail.com Thu Nov 11 06:40:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 06:40:43 +0100 (CET) Received: from mail-qw0-f49.google.com ([209.85.216.49]:57176 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491102Ab0KKFkj (ORCPT ); Thu, 11 Nov 2010 06:40:39 +0100 Received: by qwh6 with SMTP id 6so1502278qwh.36 for ; Wed, 10 Nov 2010 21:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=1G1zuw18GvkLF3bXBPvxFbD1HW/W2IEjBT6WWX9QzLQ=; b=X5QZbM6NC7bPZfhAKbEaVOUReBqAdsxersjZgPyOZH/Qg4XgppJEEI5tmtC4gfcgyB SmfRLk2FC/6iqGUhwJ6UerQ1k9MgqNTgQ0KAJvapA5zMtxaax7iWxKLJuB1tVQDGesDz 9Vgq0ZH9gaAJV/gDNOzsD5s6nTjonAMujzpCM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=EcGeIWpWMzfnZLxh5tUBngjL0ROX2ezNwobhiVECpUMTWLmKOdDHMPgS0ODvibV+DO awEM2A8K7z43B1yxx8KtUwAEHIZmE/2L6s311/7E/pFRWLGE98Ru/8JfXG5Kuc12+K4O syP49deMDelifB1owFPEh3VaQiB5Ezd3R8z3U= MIME-Version: 1.0 Received: by 10.229.212.5 with SMTP id gq5mr379359qcb.275.1289454033387; Wed, 10 Nov 2010 21:40:33 -0800 (PST) Received: by 10.220.162.69 with HTTP; Wed, 10 Nov 2010 21:40:33 -0800 (PST) In-Reply-To: References: <20101104125052.GA22429@infradead.org> <20101109140527.GA13041@infradead.org> Date: Thu, 11 Nov 2010 11:10:33 +0530 Message-ID: Subject: Re: XFS mounting fails on MIPS From: Ajeet Yadav To: Christoph Hellwig Cc: "xfs@oss.sgi.com" , linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=0016363103059d42a60494c0695b Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28353 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ajeet.yadav.77@gmail.com Precedence: bulk X-list: linux-mips --0016363103059d42a60494c0695b Content-Type: text/plain; charset=ISO-8859-1 I think mips folks agree with the change. I really wish to have there comment. I also wish to know do we really need fix in XFS for virtual indexed architecture, I think its generic issue as many architecture now use VIVT or VIPT caches. Do we want to say XFS is relatively unstable with virtual indexed architecture ? On Thu, Nov 11, 2010 at 10:27 AM, Ajeet Yadav wrote: > Coming back to problem, I wish to know about this problem > Linux XFS version : 2.6.34 > Architecure: MIPS > I am getting the following error during mount. > > XFS mounting filesystem sda2 > Starting XFS recovery on filesystem: sda2 (logdev: internal) > XFS internal error XFS_WANT_CORRUPTED_GOTO at line 1518 of file > fs/xfs/xfs_alloc.c. Caller 0x801174a0 > Call Trace: > [<800050bc>] dump_stack+0x8/0x34 > [<80115254>] xfs_free_ag_extent+0x128/0x7a8 > [<801174a0>] xfs_free_extent+0xa0/0xcc > [<80155278>] xlog_recover_process_efi+0x15c/0x210 > [<801553cc>] xlog_recover_process_efis+0xa0/0x12c > [<8015590c>] xlog_recover_finish+0x28/0xcc > [<8015d4fc>] xfs_mountfs+0x4f0/0x5d0 > [<801758d8>] xfs_fs_fill_super+0x158/0x360 > [<8008b67c>] get_sb_bdev+0x11c/0x1c4 > [<801734e0>] xfs_fs_get_sb+0x20/0x2c > [<80089cd0>] vfs_kern_mount+0x68/0xd0 > [<80089d9c>] do_kern_mount+0x54/0x118 > [<800a4e98>] do_mount+0x7f0/0x86c > [<800a4fb0>] sys_mount+0x9c/0xf8 > [<80002124>] stack_done+0x20/0x3c > > Filesystem "sda2": XFS internal error xfs_trans_cancel at line 1161 of file > fs/xfs/xfs_trans.c. Caller 0x801552f8 > > Call Trace: > [<800050bc>] dump_stack+0x8/0x34 > [<801601f0>] xfs_trans_cancel+0x88/0x118 > [<801552f8>] xlog_recover_process_efi+0x1dc/0x210 > [<801553cc>] xlog_recover_process_efis+0xa0/0x12c > [<8015590c>] xlog_recover_finish+0x28/0xcc > [<8015d4fc>] xfs_mountfs+0x4f0/0x5d0 > [<801758d8>] xfs_fs_fill_super+0x158/0x360 > [<8008b67c>] get_sb_bdev+0x11c/0x1c4 > [<801734e0>] xfs_fs_get_sb+0x20/0x2c > [<80089cd0>] vfs_kern_mount+0x68/0xd0 > [<80089d9c>] do_kern_mount+0x54/0x118 > [<800a4e98>] do_mount+0x7f0/0x86c > [<800a4fb0>] sys_mount+0x9c/0xf8 > [<80002124>] stack_done+0x20/0x3c > > xfs_force_shutdown(sda2,0x8) called from line 1162 of file > fs/xfs/xfs_trans.c. Return address = 0x80160204 > Filesystem "sda2": Corruption of in-memory data detected. Shutting down > filesystem: sda2 > Please umount the filesystem, and rectify the problem(s) > Failed to recover EFIs on filesystem: sda2 > XFS: log mount finish failed > > With Regards > Ajeet Yadav > > On Tue, Nov 9, 2010 at 7:35 PM, Christoph Hellwig wrote: > >> Hi Ajeet, >> >> On Tue, Nov 09, 2010 at 04:43:04PM +0530, Ajeet Yadav wrote: >> > True, its the same system and you were right it was cache VIPT cache >> problem >> > the cache hold the stale value even after xlog_bread() update the >> buffer. >> > I do not know whether its correct ways to resolve the problem, but the >> > problem no longer occur. >> >> It seems like you more less re-implemented the vmap coherency hooks >> inside XFS, hardcoded to the mips implementation. >> >> The actual helpers would looks something like: >> >> static inline void flush_kernel_vmap_range(void *addr, int size) >> { >> dma_cache_inv(addr, size); >> } >> >> static inline void invalidate_kernel_vmap_range(void *addr, int size) >> { >> dma_cache_inv(addr, size); >> } >> >> For some reason the kernel also expects flush_dcache_page to be >> implemented by an architecture if we want to implement these two >> (it's keyed off ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE). >> >> Can someone of the mips folks helps with this? >> >> The testcase is easy, mounting an xfs filesystem after an unclean >> shutdown on a machine with virtually indexed caches. >> >> > --0016363103059d42a60494c0695b Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable I think mips folks agree with the change. I really wish to have there comme= nt.

I also wish to know do we really need fix in XFS for= virtual indexed architecture, I think its generic issue as many architectu= re now use VIVT or VIPT caches. Do we want to say XFS is relatively unstabl= e with virtual indexed architecture ?
=A0

On Thu, Nov 11, 2010 at 1= 0:27 AM, Ajeet Yadav <ajeet.yadav.77@gmail.com> wrote:
Coming back to problem, I wish to know about this problem
=
Linux XFS version : 2.6.34
Architecure: MI= PS
I am getting the following error during mount.
=A0
XFS mounting filesystem sda2
St= arting XFS recovery on filesystem: sda2 (logdev: internal)
XFS internal = error XFS_WANT_CORRUPTED_GOTO at line 1518 of file fs/xfs/xfs_alloc.c.=A0 C= aller 0x801174a0
Call Trace:
[<800050bc>] dump_stack+0x8/0x34
[<80115254>]= xfs_free_ag_extent+0x128/0x7a8
[<801174a0>] xfs_free_extent+0xa0/= 0xcc
[<80155278>] xlog_recover_process_efi+0x15c/0x210
[<801= 553cc>] xlog_recover_process_efis+0xa0/0x12c
[<8015590c>] xlog_recover_finish+0x28/0xcc
[<8015d4fc>] xfs_= mountfs+0x4f0/0x5d0
[<801758d8>] xfs_fs_fill_super+0x158/0x360
= [<8008b67c>] get_sb_bdev+0x11c/0x1c4
[<801734e0>] xfs_fs_get= _sb+0x20/0x2c
[<80089cd0>] vfs_kern_mount+0x68/0xd0
[<80089d9c>] do_kern_m= ount+0x54/0x118
[<800a4e98>] do_mount+0x7f0/0x86c
[<800a4fb0= >] sys_mount+0x9c/0xf8
[<80002124>] stack_done+0x20/0x3c
=A0
Filesystem "sda2": XFS internal error xfs_trans_cancel at = line 1161 of file fs/xfs/xfs_trans.c.=A0 Caller 0x801552f8
=A0
Call T= race:
[<800050bc>] dump_stack+0x8/0x34
[<801601f0>] xfs_t= rans_cancel+0x88/0x118
[<801552f8>] xlog_recover_process_efi+0x1dc/0x210
[<801553cc>= ;] xlog_recover_process_efis+0xa0/0x12c
[<8015590c>] xlog_recover_= finish+0x28/0xcc
[<8015d4fc>] xfs_mountfs+0x4f0/0x5d0
[<8017= 58d8>] xfs_fs_fill_super+0x158/0x360
[<8008b67c>] get_sb_bdev+0x11c/0x1c4
[<801734e0>] xfs_fs_get= _sb+0x20/0x2c
[<80089cd0>] vfs_kern_mount+0x68/0xd0
[<80089d= 9c>] do_kern_mount+0x54/0x118
[<800a4e98>] do_mount+0x7f0/0x86c=
[<800a4fb0>] sys_mount+0x9c/0xf8
[<80002124>] stack_done+0x2= 0/0x3c
=A0
xfs_force_shutdown(sda2,0x8) called from line 1162 of file= fs/xfs/xfs_trans.c.=A0 Return address =3D 0x80160204
Filesystem "s= da2": Corruption of in-memory data detected.=A0 Shutting down filesyst= em: sda2
Please umount the filesystem, and rectify the problem(s)
Failed to recov= er EFIs on filesystem: sda2
XFS: log mount finish failed
=A0
With Regards
Ajeet Yadav

On Tue, Nov 9, 2010 at 7:35 PM, Christoph Hellwig <hch@infradead.org&g= t; wrote:
Hi Ajeet,

On Tue, Nov 09, 2010 at 04:43:04PM +0530, Ajeet Yadav wrote:
> True, its the same system and you were right it was cache VIPT cache p= roblem
> the cache hold the stale value even after xlog_bread() update the buff= er.
> I do not know whether its correct ways to resolve the problem, but the=
> problem no longer occur.

It seems like you more less re-implemented the vmap coherency hooks inside XFS, hardcoded to the mips implementation.

The actual helpers would looks something like:

static inline void flush_kernel_vmap_range(void *addr, int size)
{
=A0 =A0 =A0 =A0dma_cache_inv(addr, size);
}

static inline void invalidate_kernel_vmap_range(void *addr, int size)
{
=A0 =A0 =A0 =A0dma_cache_inv(addr, size);
}

For some reason the kernel also expects flush_dcache_page to be
implemented by an architecture if we want to implement these two
(it's keyed off ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE).

Can someone of the mips folks helps with this?

The testcase is easy, mounting an xfs filesystem after an unclean
shutdown on a machine with virtually indexed caches.



--0016363103059d42a60494c0695b-- From shannon.owens-malett@ttu.edu Thu Nov 11 08:43:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 08:43:11 +0100 (CET) Received: from eurymedon.net.ttu.edu ([129.118.1.225]:18927 "EHLO eurymedon.net.ttu.edu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491187Ab0KKHnI convert rfc822-to-8bit (ORCPT ); Thu, 11 Nov 2010 08:43:08 +0100 Received: from hippolytus.net.ttu.edu (129.118.1.212) by tmrc.ttu.edu (129.118.1.179) with Microsoft SMTP Server id 8.2.254.0; Thu, 11 Nov 2010 01:42:59 -0600 Received: from CALYPSO.ttu.edu ([129.118.1.208]) by hippolytus.net.ttu.edu ([129.118.1.212]) with mapi; Thu, 11 Nov 2010 01:42:54 -0600 From: "Owens-Malett, Shannon" Date: Thu, 11 Nov 2010 01:42:52 -0600 Subject: I am Dr. Paul Wizman, reply to (dr.paul.wizman@9.cn) Thread-Topic: I am Dr. Paul Wizman, reply to (dr.paul.wizman@9.cn) Thread-Index: AQHLgXQLDttGuh6WyUS24iQGzXliTg== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 To: Undisclosed recipients:; Received-SPF: Pass (eurymedon.net.ttu.edu: domain of shannon.owens-malett@ttu.edu designates 129.118.1.212 as permitted sender) receiver=eurymedon.net.ttu.edu; client-ip=129.118.1.212; helo=hippolytus.net.ttu.edu; X-TechMail-Edge-Route: TTU Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28354 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shannon.owens-malett@ttu.edu Precedence: bulk X-list: linux-mips I am Dr. Paul Wizman , a diagnosed glandular cancer patient on bed is willing to donate her funds to help you as her last gift from God. reply to my private email (dr.paul.wizman@9.cn) From BATV+ecf49ddc94d187cb2a78+2636+infradead.org+hch@bombadil.srs.infradead.org Thu Nov 11 13:49:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 13:50:02 +0100 (CET) Received: from bombadil.infradead.org ([18.85.46.34]:54044 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491827Ab0KKMt6 (ORCPT ); Thu, 11 Nov 2010 13:49:58 +0100 Received: from hch by bombadil.infradead.org with local (Exim 4.72 #1 (Red Hat Linux)) id 1PGWbB-0002u0-09; Thu, 11 Nov 2010 12:49:53 +0000 Date: Thu, 11 Nov 2010 07:49:52 -0500 From: Christoph Hellwig To: Ajeet Yadav Cc: Christoph Hellwig , "xfs@oss.sgi.com" , linux-mips@linux-mips.org Subject: Re: XFS mounting fails on MIPS Message-ID: <20101111124952.GA11052@infradead.org> References: <20101104125052.GA22429@infradead.org> <20101109140527.GA13041@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org See http://www.infradead.org/rpr.html Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28355 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@infradead.org Precedence: bulk X-list: linux-mips On Thu, Nov 11, 2010 at 11:10:33AM +0530, Ajeet Yadav wrote: > I think mips folks agree with the change. I really wish to have there > comment. > > I also wish to know do we really need fix in XFS for virtual indexed > architecture, I think its generic issue as many architecture now use VIVT or > VIPT caches. Do we want to say XFS is relatively unstable with virtual > indexed architecture ? The vmap flushing APIs I repeatedly pointed you at are the generic solution. They've been implement for arm, parisc and sh already, it's just that no one has bothered to do it for mips yet. Without the proper flushing anything that uses vmap, which includes XFS is not "relatively unstable" but in fact not usable on systems with virtually indexed caches. From rmh.aybabtu@gmail.com Thu Nov 11 15:47:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 15:47:58 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:60826 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491032Ab0KKOrz (ORCPT ); Thu, 11 Nov 2010 15:47:55 +0100 Received: by ewy19 with SMTP id 19so1069118ewy.36 for ; Thu, 11 Nov 2010 06:47:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:subject:to :cc:references:in-reply-to:x-mailer:message-id:mime-version :content-type; bh=CF+CDz0EY6LLLYN6cvWUD9FP7j7zAXobvo9oOGwTjHc=; b=R9/2FjO8NUys0fPHYEqmxndHj0p012l6ERADux7nG0EI2O8wmY7K+DULWuA3QfJ5zq wshf4KVW1JByCNNqNbauAXmGzfBEjCbYWtESTYojZuLuVWkeMp3CSo11qziVn+FtNO/i 3/nOJgZaj5JiDGj/DSnElThn3xFJMm3vE2lyU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:subject:to:cc:references:in-reply-to:x-mailer :message-id:mime-version:content-type; b=XuazlcYThTdoK/wQ5mkdqLUfhZjr9dwhtdA44iDCBtQAxWlOzeu/6Ozah5vyVRdS6/ FwPAyP91tsZEydyFv//aGi33T81/rksy2XKvIAuGmOMBo5OORrMhdv7Qdj64NhUQDipQ vSG0uRuns7ADJ4ybWdlxYww3ZhC5k6J1qRhe4= Received: by 10.213.3.80 with SMTP id 16mr1883055ebm.11.1289486874302; Thu, 11 Nov 2010 06:47:54 -0800 (PST) Received: from thorin ([83.45.77.222]) by mx.google.com with ESMTPS id x54sm1994573eeh.23.2010.11.11.06.47.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 11 Nov 2010 06:47:52 -0800 (PST) Date: Thu, 11 Nov 2010 15:47:35 +0100 From: Robert Millan Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU To: Ralf Baechle Cc: wu zhangjin , David Daney , Aurelien Jarno , linux-mips@linux-mips.org References: <1289305442.31389.0@thorin> <20101109154055.GD10799@linux-mips.org> In-Reply-To: <20101109154055.GD10799@linux-mips.org> (from ralf@linux-mips.org on Tue Nov 9 16:40:55 2010) X-Mailer: Balsa 2.4.1 Message-Id: <1289486855.14828.0@thorin> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-JmLzlPP0kTVobA4+X7Q2" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28356 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips --=-JmLzlPP0kTVobA4+X7Q2 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable El 09/11/10 16:40:55, en/na Ralf Baechle va escriure: > Cavium introduced this idion first. Now your patch is repeating it > and I'm > sure other SMP platforms will soon use it. I don't want a thousand > if (cpu =3D=3D 0) in that file, so can you cook a patch that introduces a > helper, something like >=20 > static void set_elf_platform(const char *plat) > { > if (cpu =3D=3D 0) > __elf_platform =3D plat; > } >=20 > Then use that for all assignments to __elf_platform? Thanks. Here. --=-JmLzlPP0kTVobA4+X7Q2 Content-Type: text/x-patch; charset=us-ascii; name=loongson2f.diff Content-Disposition: attachment; filename=loongson2f.diff Content-Transfer-Encoding: quoted-printable Signed-off-by: Robert Millan diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index fd1d39e..58844f6 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -344,6 +344,12 @@ extern int dump_task_fpu(struct task_struct *, elf_fpr= egset_t *); #define ELF_PLATFORM __elf_platform extern const char *__elf_platform; =20 +static inline void set_elf_platform(int cpu, const char *plat) +{ + if (cpu =3D=3D 0) + __elf_platform =3D plat; +} + /* * See comments in asm-alpha/elf.h, this is the same thing * on the MIPS. diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 71620e1..7e547ca 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -613,7 +613,18 @@ static inline void cpu_probe_legacy(struct cpuinfo_mip= s *c, unsigned int cpu) break; case PRID_IMP_LOONGSON2: c->cputype =3D CPU_LOONGSON2; - __cpu_name[cpu] =3D "ICT Loongson-2"; + switch (c->processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON2E: + __cpu_name[cpu] =3D "ICT Loongson-2E"; + set_elf_platform(cpu, "loongson2e"); + break; + case PRID_REV_LOONGSON2F: + __cpu_name[cpu] =3D "ICT Loongson-2F"; + set_elf_platform(cpu, "loongson2f"); + break; + default: + __cpu_name[cpu] =3D "ICT Loongson-2"; + } c->isa_level =3D MIPS_CPU_ISA_III; c->options =3D R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | @@ -957,14 +968,12 @@ static inline void cpu_probe_cavium(struct cpuinfo_mi= ps *c, unsigned int cpu) c->cputype =3D CPU_CAVIUM_OCTEON_PLUS; __cpu_name[cpu] =3D "Cavium Octeon+"; platform: - if (cpu =3D=3D 0) - __elf_platform =3D "octeon"; + set_elf_platform(cpu, "octeon"); break; case PRID_IMP_CAVIUM_CN63XX: c->cputype =3D CPU_CAVIUM_OCTEON2; __cpu_name[cpu] =3D "Cavium Octeon II"; - if (cpu =3D=3D 0) - __elf_platform =3D "octeon2"; + set_elf_platform(cpu, "octeon2"); break; default: printk(KERN_INFO "Unknown Octeon chip!\n"); --=-JmLzlPP0kTVobA4+X7Q2-- From ajeet.yadav.77@gmail.com Thu Nov 11 15:56:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 15:56:38 +0100 (CET) Received: from mail-qy0-f170.google.com ([209.85.216.170]:58251 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491032Ab0KKO4e (ORCPT ); Thu, 11 Nov 2010 15:56:34 +0100 Received: by qyk4 with SMTP id 4so985448qyk.15 for ; Thu, 11 Nov 2010 06:56:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=XAEkQ2ZOSsU7ceROWZiogWiIzxB03DR5Gk9YKWUKjl4=; b=joiP3wnNyBiFbz98GNyXSJsCsLfL1hayh1Zg1afR0vW30iGW0ltm1/PorcA/rbS11M 4kMgslNzgU01LfAQPkojqNQuBeKg3cS4pB1CXQN9WkuqD8xCxkvjAqGF6q6CuO+tiYP8 NWvDuy8iyNGxuZ8VaxggXmQPfmI7mrqwlmEkY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=H0SJsoYzsGLrEEuZYl4TZaljRD6R/mrR+EMswtgBqgxh3RJYNKfihkJpxGKIsyG/Qp MgsrLeoHOWgjujx9dk4LOQhZWUZhyIJXDMz+Yo8gkAZF5T33EUd2R3ZRNAsa8344upaS E9D5HLHbI7SUru1SxkxHalZUQVCdytKcTrtHU= MIME-Version: 1.0 Received: by 10.224.19.129 with SMTP id a1mr958738qab.154.1289487387967; Thu, 11 Nov 2010 06:56:27 -0800 (PST) Received: by 10.220.162.69 with HTTP; Thu, 11 Nov 2010 06:56:27 -0800 (PST) In-Reply-To: <20101111124952.GA11052@infradead.org> References: <20101104125052.GA22429@infradead.org> <20101109140527.GA13041@infradead.org> <20101111124952.GA11052@infradead.org> Date: Thu, 11 Nov 2010 20:26:27 +0530 Message-ID: Subject: Re: XFS mounting fails on MIPS From: Ajeet Yadav To: Christoph Hellwig Cc: "xfs@oss.sgi.com" , linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=0015175cb2c2b3c1990494c82db3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28357 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ajeet.yadav.77@gmail.com Precedence: bulk X-list: linux-mips --0015175cb2c2b3c1990494c82db3 Content-Type: text/plain; charset=ISO-8859-1 Ah! I got your point thank you very much On Thu, Nov 11, 2010 at 6:19 PM, Christoph Hellwig wrote: > On Thu, Nov 11, 2010 at 11:10:33AM +0530, Ajeet Yadav wrote: > > I think mips folks agree with the change. I really wish to have there > > comment. > > > > I also wish to know do we really need fix in XFS for virtual indexed > > architecture, I think its generic issue as many architecture now use VIVT > or > > VIPT caches. Do we want to say XFS is relatively unstable with virtual > > indexed architecture ? > > The vmap flushing APIs I repeatedly pointed you at are the generic > solution. They've been implement for arm, parisc and sh already, it's > just that no one has bothered to do it for mips yet. > > Without the proper flushing anything that uses vmap, which includes > XFS is not "relatively unstable" but in fact not usable on systems > with virtually indexed caches. > --0015175cb2c2b3c1990494c82db3 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Ah! I got your point
thank you very much
On Thu, Nov 11, 2010 at 6:19 PM, Christoph Hellw= ig <hch@infradead= .org> wrote:
On Thu, Nov 11, 2010 at 11:10:33AM +0530, Ajeet Yadav wro= te:
> I think mips folks agree with the change. I really wish to have= there
> comment.
>
> I also wish to know do we really ne= ed fix in XFS for virtual indexed
> architecture, I think its generic issue as many architecture now use V= IVT or
> VIPT caches. Do we want to say XFS is relatively unstable wi= th virtual
> indexed architecture ?

The vmap flushing AP= Is I repeatedly pointed you at are the generic
solution. =A0They've been implement for arm, parisc and sh already, it&= #39;s
just that no one has bothered to do it for mips yet.

Withou= t the proper flushing anything that uses vmap, which includes
XFS is not= "relatively unstable" but in fact not usable on systems
with virtually indexed caches.

--0015175cb2c2b3c1990494c82db3-- From Andrei.Ardelean@idt.com Thu Nov 11 16:04:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 16:04:51 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:53626 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491853Ab0KKPEs convert rfc822-to-8bit (ORCPT ); Thu, 11 Nov 2010 16:04:48 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oABF4eVH026996; Thu, 11 Nov 2010 07:04:40 -0800 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oABF4dC2010418; Thu, 11 Nov 2010 07:04:39 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oABF4dI03317; Thu, 11 Nov 2010 07:04:39 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: RE: Kernel is stuck in Calibrating delay loop Date: Thu, 11 Nov 2010 07:04:38 -0800 Message-ID: In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Kernel is stuck in Calibrating delay loop Thread-Index: AcuBQ1Lndw2zVe1FSiia4jaaYqwMQAAbMViw References: From: "Ardelean, Andrei" To: "wu zhangjin" Cc: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28358 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi Wu, I have those options enabled for my platform, I found that because of some h/w logic which is muxing different sources of interrupts to the MIPS h/w 5 interrupt the c0_compare_int_usable() failed in r4k_clockevent_init(). After fixing that I have timer interrupts but instead of coming every 10ms I have two interrupts 10ms, 1.8ms, 10ms, 1.8ms ... etc. So there is an additional one I am struggling to understand what can be the issue. One other issue I see is that when an interrupt happens I see Cause.IV bit is zero. That is not good because in my target I configured cpu_has_vint=1 to use Vectored Interrupt and I was relying on Linux to set correctly this bit. Any idea or advice is appreciated. Thanks, Andrei -----Original Message----- From: wu zhangjin [mailto:wuzhangjin@gmail.com] Sent: Wednesday, November 10, 2010 8:24 PM To: Ardelean, Andrei Cc: linux-mips@linux-mips.org Subject: Re: Kernel is stuck in Calibrating delay loop On Wed, Nov 10, 2010 at 11:49 PM, Ardelean, Andrei wrote: > Hi, > > I am porting MIPS Malta on a new platform and during the boot process > the Kernel remains in a infinite loop in "Calibrating delay loop ..." in > calibrate.c. > I checked and the timer interrupt which is supposed to be wired on h/w 5 > interrupt (MIPS 7 irq) is not activated in MIPS Status.IM7 register. > Where in the Kernel the MIPS irq wired to the timer interrupt needs to > be enabled?  Can I use enable_irq()? > On my platform I don't have any 8259 and I am trying to use MIPS > Count/Compare internal timer for Kernel tick. Did you select the r4k timer for your platform? arch/mips/Kconfig: config MIPS_MALTA [snip] select CEVT_R4K select CSRC_R4K [snip] And please check if arch/mips/kernel/*r4k.c are compiled into your kernel image. Regards, Wu Zhangjin From lars@metafoo.de Thu Nov 11 19:09:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 19:09:23 +0100 (CET) Received: from smtp-out-138.synserver.de ([212.40.180.138]:1037 "HELO smtp-out-138.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492041Ab0KKSJV (ORCPT ); Thu, 11 Nov 2010 19:09:21 +0100 Received: (qmail 27567 invoked by uid 0); 11 Nov 2010 18:09:12 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 27496 Received: from d124041.adsl.hansenet.de (HELO localhost.localdomain) [80.171.124.41] by 217.119.54.81 with SMTP; 11 Nov 2010 18:09:12 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH] MIPS: JZ4740: Fix pcm device name Date: Thu, 11 Nov 2010 19:08:52 +0100 Message-Id: <1289498933-12836-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28359 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips As part the ASoC multi-component patch (commit f0fba2ad) the jz4740 pcm driver was renamed to 'jz4740-pcm-audio'. Adjust the device name accordingly. Signed-off-by: Lars-Peter Clausen --- arch/mips/jz4740/platform.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c index c860b01..a17a17b 100644 --- a/arch/mips/jz4740/platform.c +++ b/arch/mips/jz4740/platform.c @@ -208,7 +208,7 @@ struct platform_device jz4740_i2s_device = { /* PCM */ struct platform_device jz4740_pcm_device = { - .name = "jz4740-pcm", + .name = "jz4740-pcm-audio", .id = -1, }; -- 1.5.6.5 From lars@metafoo.de Thu Nov 11 19:09:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2010 19:09:48 +0100 (CET) Received: from smtp-out-138.synserver.de ([212.40.180.138]:1043 "HELO smtp-out-138.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492004Ab0KKSJX (ORCPT ); Thu, 11 Nov 2010 19:09:23 +0100 Received: (qmail 27606 invoked by uid 0); 11 Nov 2010 18:09:13 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 27496 Received: from d124041.adsl.hansenet.de (HELO localhost.localdomain) [80.171.124.41] by 217.119.54.81 with SMTP; 11 Nov 2010 18:09:13 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH] MIPS: JZ4740: Set nand ecc offsets for the qi_lb60 board Date: Thu, 11 Nov 2010 19:08:53 +0100 Message-Id: <1289498933-12836-2-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1289498933-12836-1-git-send-email-lars@metafoo.de> References: <1289498933-12836-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28360 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Now that the mtd core supports more then 64 ecc bytes we can use it instead of some a custom hack in the jz4740 nand driver. This patches sets the ecc pos fields of the ecc_layout of the qi_lb60 board. Signed-off-by: Lars-Peter Clausen --- arch/mips/jz4740/board-qi_lb60.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) --- diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 05297ef..3a41014 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -50,14 +50,14 @@ static bool is_avt2; /* NAND */ static struct nand_ecclayout qi_lb60_ecclayout_1gb = { -/* .eccbytes = 36, + .eccbytes = 36, .eccpos = { 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 - },*/ + }, .oobfree = { { .offset = 2, .length = 4 }, { .offset = 42, .length = 22 } @@ -86,7 +86,7 @@ static struct mtd_partition qi_lb60_partitions_1gb[] = { }; static struct nand_ecclayout qi_lb60_ecclayout_2gb = { -/* .eccbytes = 72, + .eccbytes = 72, .eccpos = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, @@ -97,7 +97,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_2gb = { 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83 - },*/ + }, .oobfree = { { .offset = 2, .length = 10 }, { .offset = 84, .length = 44 }, -- 1.5.6.5 From wilbur512@gmail.com Fri Nov 12 16:19:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 16:19:19 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:43587 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491849Ab0KLPTQ (ORCPT ); Fri, 12 Nov 2010 16:19:16 +0100 Received: by eyd9 with SMTP id 9so1826537eyd.36 for ; Fri, 12 Nov 2010 07:19:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=8Uyj+PHbWdMmv7DCoIHtFVfmMRKh19vT0PQfEYzuG+s=; b=babu+diyYWllG1LAnH5OmBSEJS0Leq96iX7GZnhWjuGNf5WQSiByMfk1vNjX2N5oD2 amZftiTUnO6770u4y1IqQt9pZHbSHIKanQtY4wz7uohVb0urjT0u9HMP43bmVeLQ0LbH b5Hp3c6hX2dvuQr6ZKXNMeFW5cmeB+5s2KdWA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=qM+wvYOspSYcAxnsgVu1mtsj+Asfm0KQKrXjUswGVVNX5aljI3MwZqYwbm0/n5p27P 54FEkZkQ/HvCpIKPguy+vlFKhh9TDbxQmOp1CUjXg0eRPEjgNEKRE2ZgnK6/UW9ICCSI NXanuoTLLhqluNuLhmzFnkp2Ih9yEW24gFh/s= MIME-Version: 1.0 Received: by 10.216.11.66 with SMTP id 44mr2078230wew.69.1289575154831; Fri, 12 Nov 2010 07:19:14 -0800 (PST) Received: by 10.216.154.147 with HTTP; Fri, 12 Nov 2010 07:19:14 -0800 (PST) Date: Fri, 12 Nov 2010 23:19:14 +0800 Message-ID: Subject: printk failed in cpu bus/cache error From: "wilbur.chan" To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28361 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips linux 2.6.21.7 mips xlr 732 configured with 32bits system I found that when an cpu/cache error was triggered by an unaligned access , printk does not work well in the cache error handler. printk hangs on spin_lock(&logbuf_lock), further more , the code was located exactly to : spin_lock -- > _raw_spin_trylock -->asm( " sc %2, %1" ) include/asm-mips/spinlock.h If ' sc ' instruction unavailable when cache error occured? From Andrei.Ardelean@idt.com Fri Nov 12 19:46:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 19:46:58 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:40499 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492152Ab0KLSqy convert rfc822-to-8bit (ORCPT ); Fri, 12 Nov 2010 19:46:54 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oACIklvK005657 for ; Fri, 12 Nov 2010 10:46:47 -0800 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oACIkjmj003169 for ; Fri, 12 Nov 2010 10:46:46 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oACIkjr22167 for ; Fri, 12 Nov 2010 10:46:45 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Kernel crash when loading initramfs Date: Fri, 12 Nov 2010 10:46:42 -0800 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Kernel crash when loading initramfs Thread-Index: AcuCmfLUb2iexdpqT2+/GkNIYZZQ3Q== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28362 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, I am trying to bring-up MIPS Linux on our FPGA board with initramfs inside the kernel (cpio) and I have the bellow messages. Any idea/advice how to proceed? Thanks, Andrei Linux version 2.6.29-ts-mipsisa32r2elup (aardelea@tor-aardelea-cos54) (gcc versi on 4.3.2 (GCC) ) #139 Fri Nov 12 10:25:30 EST 2010 LINUX started... console [early0] enabled CPU revision is: 00019750 (MIPS 74Kc) FPU revision is: 01739700 Determined physical RAM map: memory: 00001000 @ 00000000 (reserved) memory: 000ef000 @ 00001000 (ROM data) memory: 00914000 @ 000f0000 (reserved) memory: 0f5fc000 @ 00a04000 (usable) Wasting 82048 bytes for tracking 2564 unused pages Initrd not found or empty - disabling initrd Zone PFN ranges: Normal 0x00000000 -> 0x00010000 Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0x00000000 -> 0x00010000 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024 Kernel command line: console=ttyS0,38400 Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes Writing ErrCtl register=00000000 Readback ErrCtl register=00000000 PID hash table entries: 1024 (order: 10, 4096 bytes) CPU frequency 50.00 MHz Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Memory: 249284k/251888k available (1644k kernel code, 2280k reserved, 461k data, 7016k init, 0k highmem) Calibrating delay loop... 1.35 BogoMIPS (lpj=6784) Mount-cache hash table entries: 512 net_namespace: 296 bytes NET: Registered protocol family 16 bio: create slab at 0 CPU 0 Unable to handle kernel paging request at virtual address 01108f84, epc == 8031382c, ra == 80313834 Oops[#1]: Cpu 0 $ 0 : 00000000 00000000 00000001 0000000d $ 4 : 01108f80 00000001 8f8010c0 000016a6 $ 8 : 0000000f 006b7649 809f0000 8f85fc90 $12 : 809f0000 006b7649 809f0000 8029d338 $16 : 01108f86 8f839000 00000081 809f0000 $20 : 809f0000 0000011e 0000001c 809f0000 $24 : 00000000 8f8616dc $28 : 8f820000 8f821e38 809f0000 80313834 Hi : 00000000 Lo : 00000000 epc : 8031382c huft_free+0x14/0x38 Not tainted ra : 80313834 huft_free+0x1c/0x38 Status: 11008003 KERNEL EXL IE Cause : 80000008 BadVA : 01108f84 PrId : 00019750 (MIPS 74Kc) Modules linked in: Process swapper (pid: 1, threadinfo=8f820000, task=8f81fa18, tls=00000000) Stack : 809f0000 0000011e 0000001c 809f0000 00000000 803155e8 8f86e008 8f857408 00000009 00000006 8029d418 8f85fc04 8f821e7c 00000000 8f86e008 8f857408 00000009 00000006 809f0000 80186e58 00000000 006b7649 80331000 803163f8 80330000 00000000 00000000 80330000 00000000 80316268 00000000 8012fbcc 00000000 00000000 00000009 802f94c0 80300d40 8f802e80 00000000 80a02b70 ... Call Trace: [<8031382c>] huft_free+0x14/0x38 [<803155e8>] inflate_dynamic+0x628/0x644 [<80316268>] unpack_to_rootfs+0xaa0/0xc30 [<80316428>] populate_rootfs+0x30/0x134 [<80107e44>] __kprobes_text_end+0x3c/0x1dc [<8030f30c>] kernel_init+0xc0/0x130 [<80109868>] kernel_thread_helper+0x10/0x18 Code: 10800006 afb00010 2484fffa <0c0619a5> 8c900004 1600fffc 02002021 8fbf 0014 00001021 Kernel panic - not syncing: Attempted to kill init! From Andrei.Ardelean@idt.com Fri Nov 12 19:53:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 19:53:15 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:40826 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492149Ab0KLSxM convert rfc822-to-8bit (ORCPT ); Fri, 12 Nov 2010 19:53:12 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oACIr5XY006114 for ; Fri, 12 Nov 2010 10:53:05 -0800 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oACIr5DY003837 for ; Fri, 12 Nov 2010 10:53:05 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oACIr4d22724 for ; Fri, 12 Nov 2010 10:53:04 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Why do we have ebase located at some high memory address when we use Vectored Interrupts? Date: Fri, 12 Nov 2010 10:53:02 -0800 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Why do we have ebase located at some high memory address when we use Vectored Interrupts? Thread-Index: AcuCmtVspzOQ1PvOQLyjfo6oJCB30A== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28363 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, Why do we have ebase located at some high memory address when we use Vectored Interrupts and for Compatible Mode we have the normal location close to zero? Thanks, Andrei .............................. in void __init trap_init(void): if (cpu_has_veic || cpu_has_vint) { unsigned long size = 0x200 + VECTORSPACING*64; ebase = (unsigned long) __alloc_bootmem(size, 1 << fls(size), 0); } else { ebase = CAC_BASE; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); } ......................... From joe@perches.com Fri Nov 12 22:38:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:38:27 +0100 (CET) Received: from mail.perches.com ([173.55.12.10]:1037 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492155Ab0KLViV (ORCPT ); Fri, 12 Nov 2010 22:38:21 +0100 Received: from Joe-Laptop.home (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id F245E2436C; Fri, 12 Nov 2010 13:37:32 -0800 (PST) From: Joe Perches To: Jiri Kosina Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] arch/mips: Use printf extension %pR for struct resource Date: Fri, 12 Nov 2010 13:37:52 -0800 Message-Id: X-Mailer: git-send-email 1.7.3.1.g432b3.dirty In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28364 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Using %pR standardizes the struct resource output. Signed-off-by: Joe Perches --- arch/mips/txx9/generic/pci.c | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c index 9a0be81..c609e7b 100644 --- a/arch/mips/txx9/generic/pci.c +++ b/arch/mips/txx9/generic/pci.c @@ -213,11 +213,8 @@ txx9_alloc_pci_controller(struct pci_controller *pcic, pcic->mem_offset = 0; /* busaddr == physaddr */ - printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n", - (unsigned long long)pcic->mem_resource[1].start, - (unsigned long long)pcic->mem_resource[1].end, - (unsigned long long)pcic->mem_resource[0].start, - (unsigned long long)pcic->mem_resource[0].end); + printk(KERN_INFO "PCI: IO %pR MEM %pR\n", + &pcic->mem_resource[1], &pcic->mem_resource[0]); /* register_pci_controller() will request MEM resource */ release_resource(&pcic->mem_resource[0]); -- 1.7.3.1.g432b3.dirty From joe@perches.com Fri Nov 12 22:38:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:38:52 +0100 (CET) Received: from mail.perches.com ([173.55.12.10]:1036 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492067Ab0KLViV (ORCPT ); Fri, 12 Nov 2010 22:38:21 +0100 Received: from Joe-Laptop.home (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id C096F24368; Fri, 12 Nov 2010 13:37:31 -0800 (PST) From: Joe Perches To: Jiri Kosina Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-rdma@vger.kernel.org, linux-mtd@lists.infradead.org, socketcan-core@lists.berlios.de, netdev@vger.kernel.org, linux-parisc@vger.kernel.org, linux-usb@vger.kernel.org, alsa-devel@alsa-project.org Subject: [PATCH 00/14] Use printf extension %pR for struct resource Date: Fri, 12 Nov 2010 13:37:50 -0800 Message-Id: X-Mailer: git-send-email 1.7.3.1.g432b3.dirty Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28365 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Yet more trivia... Joe Perches (14): arch/frv: Use printf extension %pR for struct resource arch/mips: Use printf extension %pR for struct resource arch/powerpc: Use printf extension %pR for struct resource drivers/dma/ppc4xx: Use printf extension %pR for struct resource drivers/infiniband: Use printf extension %pR for struct resource drivers/mfd: Use printf extension %pR for struct resource drivers/mtd/maps: Use printf extension %pR for struct resource drivers/mtd/nand: Use printf extension %pR for struct resource drivers/net/can/sja1000: Use printf extension %pR for struct resource drivers/parisc: Use printf extension %pR for struct resource drivers/rapidio: Use printf extension %pR for struct resource drivers/uwb: Use printf extension %pR for struct resource drivers/video: Use printf extension %pR for struct resource sound/ppc: Use printf extension %pR for struct resource arch/frv/mb93090-mb00/pci-vdk.c | 8 ++------ arch/mips/txx9/generic/pci.c | 7 ++----- arch/powerpc/kernel/pci_64.c | 3 +-- arch/powerpc/sysdev/tsi108_dev.c | 8 ++++---- drivers/dma/ppc4xx/adma.c | 5 ++--- drivers/infiniband/hw/ipath/ipath_driver.c | 5 ++--- drivers/mfd/sm501.c | 7 ++----- drivers/mtd/maps/amd76xrom.c | 7 ++----- drivers/mtd/maps/ck804xrom.c | 7 ++----- drivers/mtd/maps/esb2rom.c | 9 +++------ drivers/mtd/maps/ichxrom.c | 9 +++------ drivers/mtd/maps/physmap_of.c | 4 +--- drivers/mtd/maps/scx200_docflash.c | 5 ++--- drivers/mtd/nand/pasemi_nand.c | 2 +- drivers/net/can/sja1000/sja1000_of_platform.c | 8 ++------ drivers/parisc/dino.c | 13 +++++-------- drivers/parisc/hppb.c | 6 ++---- drivers/rapidio/rio.c | 4 ++-- drivers/uwb/umc-dev.c | 7 ++----- drivers/video/platinumfb.c | 8 ++------ sound/ppc/pmac.c | 12 ++++-------- 21 files changed, 48 insertions(+), 96 deletions(-) -- 1.7.3.1.g432b3.dirty From juhosg@openwrt.org Fri Nov 12 22:51:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:51:57 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56891 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492067Ab0KLVvx (ORCPT ); Fri, 12 Nov 2010 22:51:53 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 4D58641C001; Fri, 12 Nov 2010 22:51:48 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 89891270001; Fri, 12 Nov 2010 22:51:47 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 00/18] MIPS: initial support for the Atheros AR71XX/AR724X/AR913X SoCs Date: Fri, 12 Nov 2010 22:51:06 +0100 Message-Id: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 X-VBMS: A12258C7DF1 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28366 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch set contains initial support for the Atheros AR71XX/AR724X/AR913X SoCs. Gabor Juhos (18): MIPS: add initial support for the Atheros AR71XX/AR724X/AR931X SoCs MIPS: ath79: add GPIOLIB support MIPS: add generic support for multiple machines within a single kernel MIPS: ath79: utilize the MIPS multi-machine support MIPS: ath79: add initial support for the Atheros PB44 reference board MIPS: ath79: add common GPIO LEDs device watchdog: add driver for the Atheros AR71XX/AR724X/AR913X SoCs MIPS: ath79: add common watchdog device input: add input driver for polled GPIO buttons MIPS: ath79: add common GPIO buttons device spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs MIPS: ath79: add common SPI controller device USB: ehci: add workaround for Synopsys HC bug USB: ehci: add bus glue for the Atheros AR71XX/AR724X/AR913X SoCs USB: ohci: add bus glue for the Atheros AR71XX/AR7240 SoCs MIPS: ath79: add common USB Host Controller device MIPS: ath79: add initial support for the Atheros AP81 reference board MIPS: ath79: add common WMAC device for AR913X based boards arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 20 ++ arch/mips/ath79/Kconfig | 63 +++++ arch/mips/ath79/Makefile | 27 ++ arch/mips/ath79/Platform | 7 + arch/mips/ath79/common.c | 113 ++++++++ arch/mips/ath79/common.h | 67 +++++ arch/mips/ath79/dev-ar913x-wmac.c | 60 ++++ arch/mips/ath79/dev-ar913x-wmac.h | 17 ++ arch/mips/ath79/dev-gpio-buttons.c | 58 ++++ arch/mips/ath79/dev-gpio-buttons.h | 23 ++ arch/mips/ath79/dev-leds-gpio.c | 56 ++++ arch/mips/ath79/dev-leds-gpio.h | 21 ++ arch/mips/ath79/dev-spi.c | 38 +++ arch/mips/ath79/dev-spi.h | 22 ++ arch/mips/ath79/dev-uart.c | 59 ++++ arch/mips/ath79/dev-uart.h | 17 ++ arch/mips/ath79/dev-usb.c | 192 +++++++++++++ arch/mips/ath79/dev-usb.h | 17 ++ arch/mips/ath79/dev-wdt.c | 30 ++ arch/mips/ath79/dev-wdt.h | 17 ++ arch/mips/ath79/early_printk.c | 36 +++ arch/mips/ath79/gpio.c | 196 +++++++++++++ arch/mips/ath79/irq.c | 187 +++++++++++++ arch/mips/ath79/mach-ap81.c | 98 +++++++ arch/mips/ath79/mach-pb44.c | 119 ++++++++ arch/mips/ath79/machtypes.h | 23 ++ arch/mips/ath79/prom.c | 57 ++++ arch/mips/ath79/setup.c | 280 +++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 248 +++++++++++++++++ arch/mips/include/asm/mach-ath79/ath79.h | 50 ++++ .../include/asm/mach-ath79/ath79_ehci_platform.h | 18 ++ .../include/asm/mach-ath79/ath79_spi_platform.h | 19 ++ .../include/asm/mach-ath79/cpu-feature-overrides.h | 56 ++++ arch/mips/include/asm/mach-ath79/gpio.h | 26 ++ arch/mips/include/asm/mach-ath79/irq.h | 36 +++ .../include/asm/mach-ath79/kernel-entry-init.h | 32 +++ arch/mips/include/asm/mach-ath79/war.h | 25 ++ arch/mips/include/asm/mips_machine.h | 54 ++++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/mips_machine.c | 86 ++++++ arch/mips/kernel/proc.c | 7 +- arch/mips/kernel/vmlinux.lds.S | 7 + drivers/input/misc/Kconfig | 16 + drivers/input/misc/Makefile | 1 + drivers/input/misc/gpio_buttons.c | 232 ++++++++++++++++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 291 +++++++++++++++++++ drivers/usb/Kconfig | 5 + drivers/usb/host/Kconfig | 16 + drivers/usb/host/ehci-ath79.c | 176 ++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-q.c | 3 + drivers/usb/host/ehci.h | 1 + drivers/usb/host/ohci-ath79.c | 162 +++++++++++ drivers/usb/host/ohci-hcd.c | 5 + drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ath79_wdt.c | 293 ++++++++++++++++++++ include/linux/gpio_buttons.h | 33 +++ 61 files changed, 3842 insertions(+), 1 deletions(-) create mode 100644 arch/mips/ath79/Kconfig create mode 100644 arch/mips/ath79/Makefile create mode 100644 arch/mips/ath79/Platform create mode 100644 arch/mips/ath79/common.c create mode 100644 arch/mips/ath79/common.h create mode 100644 arch/mips/ath79/dev-ar913x-wmac.c create mode 100644 arch/mips/ath79/dev-ar913x-wmac.h create mode 100644 arch/mips/ath79/dev-gpio-buttons.c create mode 100644 arch/mips/ath79/dev-gpio-buttons.h create mode 100644 arch/mips/ath79/dev-leds-gpio.c create mode 100644 arch/mips/ath79/dev-leds-gpio.h create mode 100644 arch/mips/ath79/dev-spi.c create mode 100644 arch/mips/ath79/dev-spi.h create mode 100644 arch/mips/ath79/dev-uart.c create mode 100644 arch/mips/ath79/dev-uart.h create mode 100644 arch/mips/ath79/dev-usb.c create mode 100644 arch/mips/ath79/dev-usb.h create mode 100644 arch/mips/ath79/dev-wdt.c create mode 100644 arch/mips/ath79/dev-wdt.h create mode 100644 arch/mips/ath79/early_printk.c create mode 100644 arch/mips/ath79/gpio.c create mode 100644 arch/mips/ath79/irq.c create mode 100644 arch/mips/ath79/mach-ap81.c create mode 100644 arch/mips/ath79/mach-pb44.c create mode 100644 arch/mips/ath79/machtypes.h create mode 100644 arch/mips/ath79/prom.c create mode 100644 arch/mips/ath79/setup.c create mode 100644 arch/mips/include/asm/mach-ath79/ar71xx_regs.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h create mode 100644 arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-ath79/gpio.h create mode 100644 arch/mips/include/asm/mach-ath79/irq.h create mode 100644 arch/mips/include/asm/mach-ath79/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-ath79/war.h create mode 100644 arch/mips/include/asm/mips_machine.h create mode 100644 arch/mips/kernel/mips_machine.c create mode 100644 drivers/input/misc/gpio_buttons.c create mode 100644 drivers/spi/ath79_spi.c create mode 100644 drivers/usb/host/ehci-ath79.c create mode 100644 drivers/usb/host/ohci-ath79.c create mode 100644 drivers/watchdog/ath79_wdt.c create mode 100644 include/linux/gpio_buttons.h -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:52:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:52:27 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56903 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492156Ab0KLVvy (ORCPT ); Fri, 12 Nov 2010 22:51:54 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 50B7F41C002; Fri, 12 Nov 2010 22:51:49 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id CED2E270002; Fri, 12 Nov 2010 22:51:47 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 01/18] MIPS: add initial support for the Atheros AR71XX/AR724X/AR931X SoCs Date: Fri, 12 Nov 2010 22:51:07 +0100 Message-Id: <1289598684-30624-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A1225FA2FF1 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28367 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 15 ++ arch/mips/ath79/Kconfig | 15 ++ arch/mips/ath79/Makefile | 15 ++ arch/mips/ath79/Platform | 7 + arch/mips/ath79/common.c | 113 +++++++++ arch/mips/ath79/common.h | 62 +++++ arch/mips/ath79/dev-uart.c | 59 +++++ arch/mips/ath79/dev-uart.h | 17 ++ arch/mips/ath79/early_printk.c | 36 +++ arch/mips/ath79/irq.c | 187 ++++++++++++++ arch/mips/ath79/prom.c | 57 +++++ arch/mips/ath79/setup.c | 263 ++++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 207 +++++++++++++++ arch/mips/include/asm/mach-ath79/ath79.h | 50 ++++ .../include/asm/mach-ath79/cpu-feature-overrides.h | 56 ++++ arch/mips/include/asm/mach-ath79/irq.h | 36 +++ .../include/asm/mach-ath79/kernel-entry-init.h | 32 +++ arch/mips/include/asm/mach-ath79/war.h | 25 ++ 19 files changed, 1253 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/Kconfig create mode 100644 arch/mips/ath79/Makefile create mode 100644 arch/mips/ath79/Platform create mode 100644 arch/mips/ath79/common.c create mode 100644 arch/mips/ath79/common.h create mode 100644 arch/mips/ath79/dev-uart.c create mode 100644 arch/mips/ath79/dev-uart.h create mode 100644 arch/mips/ath79/early_printk.c create mode 100644 arch/mips/ath79/irq.c create mode 100644 arch/mips/ath79/prom.c create mode 100644 arch/mips/ath79/setup.c create mode 100644 arch/mips/include/asm/mach-ath79/ar71xx_regs.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79.h create mode 100644 arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-ath79/irq.h create mode 100644 arch/mips/include/asm/mach-ath79/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-ath79/war.h diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 78439b8..7ff9b54 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -2,6 +2,7 @@ platforms += alchemy platforms += ar7 +platforms += ath79 platforms += bcm47xx platforms += bcm63xx platforms += cavium-octeon diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index cf8d094..5da5f81 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -58,6 +58,20 @@ config AR7 Support for the Texas Instruments AR7 System-on-a-Chip family: TNETD7100, 7200 and 7300. +config ATH79 + bool "Atheros AR71XX/AR724X/AR913X based boards" + select BOOT_RAW + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + Support for the Atheros AR71XX/AR724X/AR913X SoCs. + config BCM47XX bool "Broadcom BCM47XX based boards" select CEVT_R4K @@ -707,6 +721,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD endchoice source "arch/mips/alchemy/Kconfig" +source "arch/mips/ath79/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig new file mode 100644 index 0000000..32e2658 --- /dev/null +++ b/arch/mips/ath79/Kconfig @@ -0,0 +1,15 @@ +if ATH79 + +config SOC_AR71XX + def_bool n + +config SOC_AR724X + def_bool n + +config SOC_AR913X + def_bool n + +config ATH79_DEV_UART + def_bool y + +endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile new file mode 100644 index 0000000..438929f --- /dev/null +++ b/arch/mips/ath79/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the Atheros AR71XX/AR724X/AR913X specific parts of the kernel +# +# Copyright (C) 2008-2010 Gabor Juhos +# Copyright (C) 2008 Imre Kaloz +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := prom.o setup.o irq.o common.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_ATH79_DEV_UART) += dev-uart.o diff --git a/arch/mips/ath79/Platform b/arch/mips/ath79/Platform new file mode 100644 index 0000000..2bd6636 --- /dev/null +++ b/arch/mips/ath79/Platform @@ -0,0 +1,7 @@ +# +# Atheros AR71xx/AR724x/AR913x +# + +platform-$(CONFIG_ATH79) += ath79/ +cflags-$(CONFIG_ATH79) += -I$(srctree)/arch/mips/include/asm/mach-ath79 +load-$(CONFIG_ATH79) = 0xffffffff80060000 diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c new file mode 100644 index 0000000..b6eaaf5 --- /dev/null +++ b/arch/mips/ath79/common.c @@ -0,0 +1,113 @@ +/* + * Atheros AR71XX/AR724X/AR913X common routines + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include "common.h" + +static DEFINE_SPINLOCK(ath79_device_lock); + +u32 ath79_cpu_freq; +EXPORT_SYMBOL_GPL(ath79_cpu_freq); + +u32 ath79_ahb_freq; +EXPORT_SYMBOL_GPL(ath79_ahb_freq); + +u32 ath79_ddr_freq; +EXPORT_SYMBOL_GPL(ath79_ddr_freq); + +enum ath79_soc_type ath79_soc; + +void __iomem *ath79_pll_base; +void __iomem *ath79_reset_base; +EXPORT_SYMBOL_GPL(ath79_reset_base); +void __iomem *ath79_ddr_base; + +void ath79_ddr_wb_flush(u32 reg) +{ + void __iomem *flush_reg = ath79_ddr_base + reg; + + /* Flush the DDR write buffer. */ + __raw_writel(0x1, flush_reg); + while (__raw_readl(flush_reg) & 0x1) + ; + + /* It must be run twice. */ + __raw_writel(0x1, flush_reg); + while (__raw_readl(flush_reg) & 0x1) + ; +} +EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush); + +void ath79_device_stop(u32 mask) +{ + unsigned long flags; + u32 mask_inv; + u32 t; + + if (soc_is_ar71xx()) { + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR71XX_RESET_REG_RESET_MODULE); + ath79_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else if (soc_is_ar724x()) { + mask_inv = mask & AR724X_RESET_OHCI_DLL; + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE); + t |= mask; + t &= ~mask_inv; + ath79_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else if (soc_is_ar913x()) { + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR913X_RESET_REG_RESET_MODULE); + ath79_reset_wr(AR913X_RESET_REG_RESET_MODULE, t | mask); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else { + BUG(); + } +} +EXPORT_SYMBOL_GPL(ath79_device_stop); + +void ath79_device_start(u32 mask) +{ + unsigned long flags; + u32 mask_inv; + u32 t; + + if (soc_is_ar71xx()) { + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR71XX_RESET_REG_RESET_MODULE); + ath79_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else if (soc_is_ar724x()) { + mask_inv = mask & AR724X_RESET_OHCI_DLL; + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE); + t &= ~mask; + t |= mask_inv; + ath79_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else if (soc_is_ar913x()) { + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR913X_RESET_REG_RESET_MODULE); + ath79_reset_wr(AR913X_RESET_REG_RESET_MODULE, t & ~mask); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else { + BUG(); + } +} +EXPORT_SYMBOL_GPL(ath79_device_start); diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h new file mode 100644 index 0000000..62d7503 --- /dev/null +++ b/arch/mips/ath79/common.h @@ -0,0 +1,62 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ATH79_COMMON_H +#define __ATH79_COMMON_H + +#include +#include +#include +#include + +#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) +#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) + +extern void __iomem *ath79_ddr_base; +void ath79_ddr_wb_flush(unsigned int reg); + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132 +}; + +extern enum ath79_soc_type ath79_soc; + +static inline int soc_is_ar71xx(void) +{ + return (ath79_soc == ATH79_SOC_AR7130 || + ath79_soc == ATH79_SOC_AR7141 || + ath79_soc == ATH79_SOC_AR7161); +} + +static inline int soc_is_ar724x(void) +{ + return (ath79_soc == ATH79_SOC_AR7240 || + ath79_soc == ATH79_SOC_AR7241 || + ath79_soc == ATH79_SOC_AR7242); +} + +static inline int soc_is_ar913x(void) +{ + return (ath79_soc == ATH79_SOC_AR9130 || + ath79_soc == ATH79_SOC_AR9132); +} + +#endif /* __ATH79_COMMON_H */ diff --git a/arch/mips/ath79/dev-uart.c b/arch/mips/ath79/dev-uart.c new file mode 100644 index 0000000..d7ca5d6 --- /dev/null +++ b/arch/mips/ath79/dev-uart.c @@ -0,0 +1,59 @@ +/* + * Atheros AR71XX/AR724X/AR913X UART device + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include "common.h" +#include "dev-uart.h" + +static struct resource ath79_uart_resources[] = { + { + .start = AR71XX_UART_BASE, + .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) +static struct plat_serial8250_port ath79_uart_data[] = { + { + .mapbase = AR71XX_UART_BASE, + .irq = ATH79_MISC_IRQ_UART, + .flags = AR71XX_UART_FLAGS, + .iotype = UPIO_MEM32, + .regshift = 2, + }, { + /* terminating entry */ + } +}; + +static struct platform_device ath79_uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .resource = ath79_uart_resources, + .num_resources = ARRAY_SIZE(ath79_uart_resources), + .dev = { + .platform_data = ath79_uart_data + }, +}; + +void __init ath79_register_uart(void) +{ + ath79_uart_data[0].uartclk = ath79_ahb_freq; + platform_device_register(&ath79_uart_device); +} diff --git a/arch/mips/ath79/dev-uart.h b/arch/mips/ath79/dev-uart.h new file mode 100644 index 0000000..fc1680a --- /dev/null +++ b/arch/mips/ath79/dev-uart.h @@ -0,0 +1,17 @@ +/* + * Atheros AR71XX/AR724X/AR913X UART device + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_UART_H +#define _ATH79_DEV_UART_H + +void ath79_register_uart(void) __init; + +#endif /* _ATH79_DEV_UART_H */ diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c new file mode 100644 index 0000000..7499b0e --- /dev/null +++ b/arch/mips/ath79/early_printk.c @@ -0,0 +1,36 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC early printk support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +static inline void prom_wait_thre(void __iomem *base) +{ + u32 lsr; + + do { + lsr = __raw_readl(base + UART_LSR * 4); + if (lsr & UART_LSR_THRE) + break; + } while (1); +} + +void prom_putchar(unsigned char ch) +{ + void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); + + prom_wait_thre(base); + __raw_writel(ch, base + UART_TX * 4); + prom_wait_thre(base); +} diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c new file mode 100644 index 0000000..1bf7f71 --- /dev/null +++ b/arch/mips/ath79/irq.c @@ -0,0 +1,187 @@ +/* + * Atheros AR71xx/AR724x/AR913x specific interrupt handling + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "common.h" + +static unsigned int ath79_ip2_flush_reg; +static unsigned int ath79_ip3_flush_reg; + +static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *base = ath79_reset_base; + u32 pending; + + pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + if (pending & MISC_INT_UART) + generic_handle_irq(ATH79_MISC_IRQ_UART); + + else if (pending & MISC_INT_DMA) + generic_handle_irq(ATH79_MISC_IRQ_DMA); + + else if (pending & MISC_INT_PERFC) + generic_handle_irq(ATH79_MISC_IRQ_PERFC); + + else if (pending & MISC_INT_TIMER) + generic_handle_irq(ATH79_MISC_IRQ_TIMER); + + else if (pending & MISC_INT_OHCI) + generic_handle_irq(ATH79_MISC_IRQ_OHCI); + + else if (pending & MISC_INT_ERROR) + generic_handle_irq(ATH79_MISC_IRQ_ERROR); + + else if (pending & MISC_INT_GPIO) + generic_handle_irq(ATH79_MISC_IRQ_GPIO); + + else if (pending & MISC_INT_WDOG) + generic_handle_irq(ATH79_MISC_IRQ_WDOG); + + else + spurious_interrupt(); +} + +static void ar71xx_misc_irq_unmask(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + +static void ar71xx_misc_irq_mask(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + +static void ar724x_misc_irq_ack(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); +} + +static struct irq_chip ath79_misc_irq_chip = { + .name = "MISC", + .unmask = ar71xx_misc_irq_unmask, + .mask = ar71xx_misc_irq_mask, +}; + +static void __init ath79_misc_irq_init(void) +{ + void __iomem *base = ath79_reset_base; + int i; + + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); + + if (soc_is_ar71xx() || soc_is_ar913x()) + ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; + else if (soc_is_ar724x()) + ath79_misc_irq_chip.ack = ar724x_misc_irq_ack; + else + BUG(); + + for (i = ATH79_MISC_IRQ_BASE; + i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { + irq_desc[i].status = IRQ_DISABLED; + set_irq_chip_and_handler(i, &ath79_misc_irq_chip, + handle_level_irq); + } + + set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(ATH79_CPU_IRQ_TIMER); + + else if (pending & STATUSF_IP2) { + ath79_ddr_wb_flush(ath79_ip2_flush_reg); + do_IRQ(ATH79_CPU_IRQ_IP2); + } + + else if (pending & STATUSF_IP4) + do_IRQ(ATH79_CPU_IRQ_GE0); + + else if (pending & STATUSF_IP5) + do_IRQ(ATH79_CPU_IRQ_GE1); + + else if (pending & STATUSF_IP3) { + ath79_ddr_wb_flush(ath79_ip3_flush_reg); + do_IRQ(ATH79_CPU_IRQ_USB); + } + + else if (pending & STATUSF_IP6) + do_IRQ(ATH79_CPU_IRQ_MISC); + + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + if (soc_is_ar71xx()) { + ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; + ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; + } else if (soc_is_ar724x()) { + ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; + ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; + } else if (soc_is_ar913x()) { + ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; + ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; + } else + BUG(); + + cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + mips_cpu_irq_init(); + ath79_misc_irq_init(); +} diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c new file mode 100644 index 0000000..e9cbd7c --- /dev/null +++ b/arch/mips/ath79/prom.c @@ -0,0 +1,57 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific prom routines + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "common.h" + +static inline int is_valid_ram_addr(void *addr) +{ + if (((u32) addr > KSEG0) && + ((u32) addr < (KSEG0 + ATH79_MEM_SIZE_MAX))) + return 1; + + if (((u32) addr > KSEG1) && + ((u32) addr < (KSEG1 + ATH79_MEM_SIZE_MAX))) + return 1; + + return 0; +} + +static __init void ath79_prom_init_cmdline(int argc, char **argv) +{ + int i; + + if (!is_valid_ram_addr(argv)) + return; + + for (i = 0; i < argc; i++) + if (is_valid_ram_addr(argv[i])) { + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); + } +} + +void __init prom_init(void) +{ + ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); +} + +void __init prom_free_prom_memory(void) +{ + /* We do not have to prom memory to free */ +} diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c new file mode 100644 index 0000000..63896b9 --- /dev/null +++ b/arch/mips/ath79/setup.c @@ -0,0 +1,263 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific setup + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include /* for mips_hpt_frequency */ +#include /* for _machine_{restart,halt} */ + +#include +#include +#include "common.h" +#include "dev-uart.h" + +#define ATH79_SYS_TYPE_LEN 64 + +#define AR71XX_BASE_FREQ 40000000 +#define AR724X_BASE_FREQ 5000000 +#define AR913X_BASE_FREQ 5000000 + +static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; + +static void ath79_restart(char *command) +{ + ath79_device_stop(AR71XX_RESET_FULL_CHIP); + for (;;) + if (cpu_wait) + cpu_wait(); +} + +static void ath79_halt(void) +{ + while (1) + cpu_wait(); +} + +static void __init ath79_detect_mem_size(void) +{ + unsigned long size; + + for (size = ATH79_MEM_SIZE_MIN; size < ATH79_MEM_SIZE_MAX; + size <<= 1) { + if (!memcmp(ath79_detect_mem_size, + ath79_detect_mem_size + size, 1024)) + break; + } + + add_memory_region(0, size, BOOT_MEM_RAM); +} + +static void __init ath79_detect_sys_type(void) +{ + char *chip = "????"; + u32 id; + u32 major; + u32 minor; + u32 rev = 0; + + id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + ath79_soc = ATH79_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + ath79_soc = ATH79_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + ath79_soc = ATH79_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + ath79_soc = ATH79_SOC_AR7240; + chip = "7240"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7241: + ath79_soc = ATH79_SOC_AR7241; + chip = "7241"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7242: + ath79_soc = ATH79_SOC_AR7242; + chip = "7242"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; + rev &= AR913X_REV_ID_REVISION_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + ath79_soc = ATH79_SOC_AR9130; + chip = "9130"; + break; + + case AR913X_REV_ID_MINOR_AR9132: + ath79_soc = ATH79_SOC_AR9132; + chip = "9132"; + break; + } + break; + + default: + panic("ath79: unknown SoC, id:0x%08x\n", id); + } + + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); +} + +static void __init ar71xx_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; + freq = div * AR71XX_BASE_FREQ; + + div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; + ath79_cpu_freq = freq / div; + + div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ar724x_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * AR724X_BASE_FREQ; + + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); + freq *= div; + + ath79_cpu_freq = freq; + + div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ar913x_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); + freq = div * AR913X_BASE_FREQ; + + ath79_cpu_freq = freq; + + div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ath79_detect_sys_frequency(void) +{ + if (soc_is_ar71xx()) + ar71xx_detect_sys_frequency(); + else if (soc_is_ar724x()) + ar724x_detect_sys_frequency(); + else if (soc_is_ar913x()) + ar913x_detect_sys_frequency(); + else + BUG(); +} + +const char *get_system_type(void) +{ + return ath79_sys_type; +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(KSEG1); + + ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE); + ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, + AR71XX_PLL_SIZE); + + ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, + AR71XX_DDR_CTRL_SIZE); + + ath79_detect_sys_type(); + ath79_detect_mem_size(); + ath79_detect_sys_frequency(); + + pr_info("SoC: %s, CPU:%u.%03u MHz, DDR:%u.%03u MHz, AHB:%u.%03u MHz\n", + ath79_sys_type, + ath79_cpu_freq / 1000000, (ath79_cpu_freq / 1000) % 1000, + ath79_ddr_freq / 1000000, (ath79_ddr_freq / 1000) % 1000, + ath79_ahb_freq / 1000000, (ath79_ahb_freq / 1000) % 1000); + + _machine_restart = ath79_restart; + _machine_halt = ath79_halt; + pm_power_off = ath79_halt; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = ath79_cpu_freq / 2; +} + +static int __init ath79_setup(void) +{ + ath79_register_uart(); + return 0; +} + +arch_initcall(ath79_setup); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h new file mode 100644 index 0000000..5a9e5e1 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -0,0 +1,207 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#include +#include +#include +#include + +#define AR71XX_APB_BASE 0x18000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_OHCI_DLL BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +#endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h new file mode 100644 index 0000000..14248c9 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -0,0 +1,50 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include +#include + +extern u32 ath79_ahb_freq; +extern u32 ath79_cpu_freq; +extern u32 ath79_ddr_freq; + +extern void __iomem *ath79_pll_base; +extern void __iomem *ath79_reset_base; + +static inline void ath79_pll_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ath79_pll_base + reg); +} + +static inline u32 ath79_pll_rr(unsigned reg) +{ + return __raw_readl(ath79_pll_base + reg); +} + +static inline void ath79_reset_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ath79_reset_base + reg); +} + +static inline u32 ath79_reset_rr(unsigned reg) +{ + return __raw_readl(ath79_reset_base + reg); +} + +void ath79_device_stop(u32 mask); +void ath79_device_start(u32 mask); + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h new file mode 100644 index 0000000..4476fa0 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific CPU feature overrides + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h new file mode 100644 index 0000000..189bc6e --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_ATH79_IRQ_H +#define __ASM_MACH_ATH79_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 16 + +#define ATH79_MISC_IRQ_BASE 8 +#define ATH79_MISC_IRQ_COUNT 8 + +#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) +#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) +#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) +#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) +#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) +#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7) + +#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) +#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) +#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) +#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3) +#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4) +#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) +#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) +#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) + +#include_next + +#endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h new file mode 100644 index 0000000..d8d046b --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h @@ -0,0 +1,32 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific kernel entry setup + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ATH79_KERNEL_ENTRY_H +#define __ASM_MACH_ATH79_KERNEL_ENTRY_H + + /* + * Some bootloaders set the 'Kseg0 coherency algorithm' to + * 'Cacheable, noncoherent, write-through, no write allocate' + * and this cause performance issues. Let's go and change it to + * 'Cacheable, noncoherent, write-back, write allocate' + */ + .macro kernel_entry_setup + mfc0 t0, CP0_CONFIG + li t1, ~CONF_CM_CMASK + and t0, t1 + ori t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + nop + .endm + + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_ATH79_KERNEL_ENTRY_H */ diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h new file mode 100644 index 0000000..323d9f1 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_ATH79_WAR_H +#define __ASM_MACH_ATH79_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_ATH79_WAR_H */ -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:52:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:52:53 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56910 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492159Ab0KLVvy (ORCPT ); Fri, 12 Nov 2010 22:51:54 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 7A6E241C003; Fri, 12 Nov 2010 22:51:49 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id AAB62270001; Fri, 12 Nov 2010 22:51:48 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos , David Brownell Subject: [RFC 02/18] MIPS: ath79: add GPIOLIB support Date: Fri, 12 Nov 2010 22:51:08 +0100 Message-Id: <1289598684-30624-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A1226201715 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28368 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch implements generic GPIO routines for the built-in GPIO controllers of the Atheros AR71XX/AR724X/AR913X SoCs. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: David Brownell --- arch/mips/Kconfig | 1 + arch/mips/ath79/Makefile | 2 +- arch/mips/ath79/common.h | 5 + arch/mips/ath79/gpio.c | 196 ++++++++++++++++++++++++ arch/mips/ath79/setup.c | 2 +- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 21 +++ arch/mips/include/asm/mach-ath79/gpio.h | 26 +++ 7 files changed, 251 insertions(+), 2 deletions(-) create mode 100644 arch/mips/ath79/gpio.c create mode 100644 arch/mips/include/asm/mach-ath79/gpio.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5da5f81..a738966 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -60,6 +60,7 @@ config AR7 config ATH79 bool "Atheros AR71XX/AR724X/AR913X based boards" + select ARCH_REQUIRE_GPIOLIB select BOOT_RAW select CEVT_R4K select CSRC_R4K diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 438929f..6914685 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -8,7 +8,7 @@ # under the terms of the GNU General Public License version 2 as published # by the Free Software Foundation. -obj-y := prom.o setup.o irq.o common.o +obj-y := prom.o setup.o irq.o common.o gpio.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h index 62d7503..041ca7e 100644 --- a/arch/mips/ath79/common.h +++ b/arch/mips/ath79/common.h @@ -59,4 +59,9 @@ static inline int soc_is_ar913x(void) ath79_soc == ATH79_SOC_AR9132); } +void ath79_gpio_function_enable(u32 mask); +void ath79_gpio_function_disable(u32 mask); +void ath79_gpio_function_setup(u32 set, u32 clear); +void ath79_gpio_init(void) __init; + #endif /* __ATH79_COMMON_H */ diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c new file mode 100644 index 0000000..fd88c64 --- /dev/null +++ b/arch/mips/ath79/gpio.c @@ -0,0 +1,196 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "common.h" + +static void __iomem *ath79_gpio_base; +static unsigned long ath79_gpio_count; +static DEFINE_SPINLOCK(ath79_gpio_lock); + +static void __ath79_gpio_set_value(unsigned gpio, int value) +{ + void __iomem *base = ath79_gpio_base; + + if (value) + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); +} + +static int __ath79_gpio_get_value(unsigned gpio) +{ + return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1; +} + +static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + return __ath79_gpio_get_value(offset); +} + +static void ath79_gpio_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + __ath79_gpio_set_value(offset, value); +} + +static int ath79_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static int ath79_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + if (value) + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, + .set = ath79_gpio_set_value, + .direction_input = ath79_gpio_direction_input, + .direction_output = ath79_gpio_direction_output, + .base = 0, +}; + +void ath79_gpio_function_enable(u32 mask) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void ath79_gpio_function_disable(u32 mask) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void ath79_gpio_function_setup(u32 set, u32 clear) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void __init ath79_gpio_init(void) +{ + int err; + + if (soc_is_ar71xx()) + ath79_gpio_count = AR71XX_GPIO_COUNT; + else if (soc_is_ar724x()) + ath79_gpio_count = AR724X_GPIO_COUNT; + else if (soc_is_ar913x()) + ath79_gpio_count = AR913X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; + + err = gpiochip_add(&ath79_gpio_chip); + if (err) + panic("cannot add AR71xx GPIO chip, error=%d", err); +} + +int gpio_get_value(unsigned gpio) +{ + if (gpio < ath79_gpio_count) + return __ath79_gpio_get_value(gpio); + + return __gpio_get_value(gpio); +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int value) +{ + if (gpio < ath79_gpio_count) + __ath79_gpio_set_value(gpio, value); + else + __gpio_set_value(gpio, value); +} +EXPORT_SYMBOL(gpio_set_value); + +int gpio_to_irq(unsigned gpio) +{ + /* FIXME */ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int irq_to_gpio(unsigned irq) +{ + /* FIXME */ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 63896b9..c1a95e1 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -230,7 +230,6 @@ void __init plat_mem_setup(void) AR71XX_RESET_SIZE); ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); - ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE); @@ -256,6 +255,7 @@ void __init plat_time_init(void) static int __init ath79_setup(void) { + ath79_gpio_init(); ath79_register_uart(); return 0; } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 5a9e5e1..7f2933d 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -25,6 +25,8 @@ #define AR71XX_DDR_CTRL_SIZE 0x100 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR71XX_UART_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) #define AR71XX_PLL_SIZE 0x100 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) @@ -204,4 +206,23 @@ #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ AR71XX_SPI_IOC_CS2) +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +#define AR71XX_GPIO_COUNT 16 +#define AR724X_GPIO_COUNT 18 +#define AR913X_GPIO_COUNT 22 + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/arch/mips/include/asm/mach-ath79/gpio.h b/arch/mips/include/asm/mach-ath79/gpio.h new file mode 100644 index 0000000..60dcb62 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/gpio.h @@ -0,0 +1,26 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MACH_ATH79_GPIO_H +#define __ASM_MACH_ATH79_GPIO_H + +#define ARCH_NR_GPIOS 64 +#include + +int gpio_to_irq(unsigned gpio); +int irq_to_gpio(unsigned irq); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); + +#define gpio_cansleep __gpio_cansleep + +#endif /* __ASM_MACH_ATH79_GPIO_H */ -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:53:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:53:18 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56918 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492160Ab0KLVvy (ORCPT ); Fri, 12 Nov 2010 22:51:54 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id B40BF41C004; Fri, 12 Nov 2010 22:51:49 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 06351270002; Fri, 12 Nov 2010 22:51:49 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 03/18] MIPS: add generic support for multiple machines within a single kernel Date: Fri, 12 Nov 2010 22:51:09 +0100 Message-Id: <1289598684-30624-4-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122653DA52 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28369 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch adds a generic solution to support multiple machines based on a given SoC within a single kernel image. It is implemented already for several other architectures but MIPS has no generic support for that yet. Signed-off-by: Gabor Juhos --- arch/mips/Kconfig | 3 + arch/mips/include/asm/mips_machine.h | 54 +++++++++++++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/mips_machine.c | 86 ++++++++++++++++++++++++++++++++++ arch/mips/kernel/proc.c | 7 ++- arch/mips/kernel/vmlinux.lds.S | 7 +++ 6 files changed, 157 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/mips_machine.h create mode 100644 arch/mips/kernel/mips_machine.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a738966..436fc24 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -889,6 +889,9 @@ config MIPS_DISABLE_OBSOLETE_IDE config SYNC_R4K bool +config MIPS_MACHINE + def_bool n + config NO_IOPORT def_bool n diff --git a/arch/mips/include/asm/mips_machine.h b/arch/mips/include/asm/mips_machine.h new file mode 100644 index 0000000..363bb35 --- /dev/null +++ b/arch/mips/include/asm/mips_machine.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MIPS_MACHINE_H +#define __ASM_MIPS_MACHINE_H + +#include +#include + +#include + +struct mips_machine { + unsigned long mach_type; + const char *mach_id; + const char *mach_name; + void (*mach_setup)(void); +}; + +#define MIPS_MACHINE(_type, _id, _name, _setup) \ +static const char machine_name_##_type[] __initconst \ + __aligned(1) = _name; \ +static const char machine_id_##_type[] __initconst \ + __aligned(1) = _id; \ +static struct mips_machine machine_##_type \ + __used __section(.mips.machines.init) = \ +{ \ + .mach_type = _type, \ + .mach_id = machine_id_##_type, \ + .mach_name = machine_name_##_type, \ + .mach_setup = _setup, \ +}; + +extern long __mips_machines_start; +extern long __mips_machines_end; + +#ifdef CONFIG_MIPS_MACHINE +int mips_machtype_setup(char *id) __init; +void mips_machine_setup(void) __init; +void mips_set_machine_name(const char *name) __init; +char *mips_get_machine_name(void); +#else +static inline int mips_machtype_setup(char *id) { return 1; } +static inline void mips_machine_setup(void) { } +static inline void mips_set_machine_name(const char *name) { } +static inline char *mips_get_machine_name(void) { return NULL; } +#endif /* CONFIG_MIPS_MACHINE */ + +#endif /* __ASM_MIPS_MACHINE_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 8088498..3b26371 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o +obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o obj-$(CONFIG_OF) += prom.o diff --git a/arch/mips/kernel/mips_machine.c b/arch/mips/kernel/mips_machine.c new file mode 100644 index 0000000..411a058 --- /dev/null +++ b/arch/mips/kernel/mips_machine.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#include +#include +#include + +#include + +static struct mips_machine *mips_machine __initdata; +static char *mips_machine_name = "Unknown"; + +#define for_each_machine(mach) \ + for ((mach) = (struct mips_machine *)&__mips_machines_start; \ + (mach) && \ + (unsigned long)(mach) < (unsigned long)&__mips_machines_end; \ + (mach)++) + +__init void mips_set_machine_name(const char *name) +{ + char *p; + + if (name == NULL) + return; + + p = kstrdup(name, GFP_KERNEL); + if (!p) + pr_err("MIPS: no memory for machine_name\n"); + + mips_machine_name = p; +} + +char *mips_get_machine_name(void) +{ + return mips_machine_name; +} + +__init int mips_machtype_setup(char *id) +{ + struct mips_machine *mach; + + for_each_machine(mach) { + if (mach->mach_id == NULL) + continue; + + if (strcmp(mach->mach_id, id) == 0) { + mips_machtype = mach->mach_type; + return 0; + } + } + + pr_err("MIPS: no machine found for id '%s', supported machines:\n", id); + pr_err("%-24s %s\n", "id", "name"); + for_each_machine(mach) + pr_err("%-24s %s\n", mach->mach_id, mach->mach_name); + + return 1; +} + +__setup("machtype=", mips_machtype_setup); + +__init void mips_machine_setup(void) +{ + struct mips_machine *mach; + + for_each_machine(mach) { + if (mips_machtype == mach->mach_type) { + mips_machine = mach; + break; + } + } + + if (!mips_machine) + return; + + mips_set_machine_name(mips_machine->mach_name); + pr_info("MIPS: machine is %s\n", mips_machine_name); + + if (mips_machine->mach_setup) + mips_machine->mach_setup(); +} diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 26109c4..4195abb 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -12,6 +12,7 @@ #include #include #include +#include unsigned int vced_count, vcei_count; @@ -31,8 +32,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) /* * For the first processor also print the system type */ - if (n == 0) + if (n == 0) { seq_printf(m, "system type\t\t: %s\n", get_system_type()); + if (mips_get_machine_name()) + seq_printf(m, "machine\t\t\t: %s\n", + mips_get_machine_name()); + } seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index f25df73..570607b 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -98,6 +98,13 @@ SECTIONS INIT_TEXT_SECTION(PAGE_SIZE) INIT_DATA_SECTION(16) + . = ALIGN(4); + .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) { + __mips_machines_start = .; + *(.mips.machines.init) + __mips_machines_end = .; + } + /* .exit.text is discarded at runtime, not link time, to deal with * references from .rodata */ -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:53:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:53:45 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56923 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492161Ab0KLVvz (ORCPT ); Fri, 12 Nov 2010 22:51:55 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id D5DB541C005; Fri, 12 Nov 2010 22:51:49 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 44B49270001; Fri, 12 Nov 2010 22:51:49 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 04/18] MIPS: ath79: utilize the MIPS multi-machine support Date: Fri, 12 Nov 2010 22:51:10 +0100 Message-Id: <1289598684-30624-5-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A1226B73416 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28370 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Signed-off-by: Gabor Juhos --- arch/mips/Kconfig | 1 + arch/mips/ath79/machtypes.h | 21 +++++++++++++++++++++ arch/mips/ath79/setup.c | 15 +++++++++++++++ 3 files changed, 37 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/machtypes.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 436fc24..7307e62 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -66,6 +66,7 @@ config ATH79 select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU + select MIPS_MACHINE select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h new file mode 100644 index 0000000..fac0e26 --- /dev/null +++ b/arch/mips/ath79/machtypes.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71XX/AR724X/AR913X machine type definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_MACHTYPE_H +#define _ATH79_MACHTYPE_H + +#include + +enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, +}; + +#endif /* _ATH79_MACHTYPE_H */ diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index c1a95e1..b36f9f2 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -18,11 +18,13 @@ #include #include /* for mips_hpt_frequency */ #include /* for _machine_{restart,halt} */ +#include #include #include #include "common.h" #include "dev-uart.h" +#include "machtypes.h" #define ATH79_SYS_TYPE_LEN 64 @@ -257,7 +259,20 @@ static int __init ath79_setup(void) { ath79_gpio_init(); ath79_register_uart(); + + mips_machine_setup(); + return 0; } arch_initcall(ath79_setup); + +static void __init ath79_generic_init(void) +{ + /* Nothing to do */ +} + +MIPS_MACHINE(ATH79_MACH_GENERIC, + "Generic", + "Generic AR71XX/AR724X/AR913X based board", + ath79_generic_init); -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:54:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:54:10 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56998 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492163Ab0KLVv6 (ORCPT ); Fri, 12 Nov 2010 22:51:58 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 68A3A41C007; Fri, 12 Nov 2010 22:51:50 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id B09A6270002; Fri, 12 Nov 2010 22:51:49 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 06/18] MIPS: ath79: add common GPIO LEDs device Date: Fri, 12 Nov 2010 22:51:12 +0100 Message-Id: <1289598684-30624-7-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A12280F3C5F | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28371 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Almost all boards have one or more LEDs connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the LEDs on the PB44 board. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- arch/mips/ath79/Kconfig | 4 +++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-leds-gpio.c | 56 +++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/dev-leds-gpio.h | 21 ++++++++++++++ arch/mips/ath79/mach-pb44.c | 18 ++++++++++++ 5 files changed, 100 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-leds-gpio.c create mode 100644 arch/mips/ath79/dev-leds-gpio.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 47a8af4..2bd35ef 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -5,6 +5,7 @@ menu "Atheros AR71XX/AR724X/AR913X machine selection" config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX + select ATH79_DEV_LEDS_GPIO default n help Say 'Y' here if you want your kernel to support the @@ -21,6 +22,9 @@ config SOC_AR724X config SOC_AR913X def_bool n +config ATH79_DEV_LEDS_GPIO + def_bool n + config ATH79_DEV_UART def_bool y diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index aef7ce6..a231967 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -12,6 +12,7 @@ obj-y := prom.o setup.o irq.o common.o gpio.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_UART) += dev-uart.o # diff --git a/arch/mips/ath79/dev-leds-gpio.c b/arch/mips/ath79/dev-leds-gpio.c new file mode 100644 index 0000000..cdade68 --- /dev/null +++ b/arch/mips/ath79/dev-leds-gpio.c @@ -0,0 +1,56 @@ +/* + * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include "dev-leds-gpio.h" + +void __init ath79_register_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds) +{ + struct platform_device *pdev; + struct gpio_led_platform_data pdata; + struct gpio_led *p; + int err; + + p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, leds, num_leds * sizeof(*p)); + + pdev = platform_device_alloc("leds-gpio", id); + if (!pdev) + goto err_free_leds; + + memset(&pdata, 0, sizeof(pdata)); + pdata.num_leds = num_leds; + pdata.leds = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_leds: + kfree(p); +} diff --git a/arch/mips/ath79/dev-leds-gpio.h b/arch/mips/ath79/dev-leds-gpio.h new file mode 100644 index 0000000..0fb0ed1 --- /dev/null +++ b/arch/mips/ath79/dev-leds-gpio.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_LEDS_GPIO_H +#define _ATH79_DEV_LEDS_GPIO_H + +#include + +void ath79_register_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds) __init; + +#endif /* _ATH79_DEV_LEDS_GPIO_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index ffc24d7..e176779 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -15,11 +15,14 @@ #include #include "machtypes.h" +#include "dev-leds-gpio.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 #define PB44_GPIO_EXP_BASE 16 +#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) +#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { .sda_pin = PB44_GPIO_I2C_SDA, @@ -45,11 +48,26 @@ static struct i2c_board_info pb44_i2c_board_info[] __initdata = { }, }; +static struct gpio_led pb44_leds_gpio[] __initdata = { + { + .name = "pb44:amber:jump1", + .gpio = PB44_GPIO_LED_JUMP1, + .active_low = 1, + }, { + .name = "pb44:green:jump2", + .gpio = PB44_GPIO_LED_JUMP2, + .active_low = 1, + }, +}; + static void __init pb44_init(void) { i2c_register_board_info(0, pb44_i2c_board_info, ARRAY_SIZE(pb44_i2c_board_info)); platform_device_register(&pb44_i2c_gpio_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), + pb44_leds_gpio); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:54:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:54:34 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56999 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492164Ab0KLVv6 (ORCPT ); Fri, 12 Nov 2010 22:51:58 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 224D041C006; Fri, 12 Nov 2010 22:51:50 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 797ED270001; Fri, 12 Nov 2010 22:51:49 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 05/18] MIPS: ath79: add initial support for the Atheros PB44 reference board Date: Fri, 12 Nov 2010 22:51:11 +0100 Message-Id: <1289598684-30624-6-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A12274AB137 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28372 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Signed-off-by: Gabor Juhos --- arch/mips/ath79/Kconfig | 12 +++++++++ arch/mips/ath79/Makefile | 5 ++++ arch/mips/ath79/mach-pb44.c | 56 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 74 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/mach-pb44.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 32e2658..47a8af4 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -1,5 +1,17 @@ if ATH79 +menu "Atheros AR71XX/AR724X/AR913X machine selection" + +config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX + default n + help + Say 'Y' here if you want your kernel to support the + Atheros PB44 reference board. + +endmenu + config SOC_AR71XX def_bool n diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 6914685..aef7ce6 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -13,3 +13,8 @@ obj-y := prom.o setup.o irq.o common.o gpio.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_ATH79_DEV_UART) += dev-uart.o + +# +# Machines +# +obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c new file mode 100644 index 0000000..ffc24d7 --- /dev/null +++ b/arch/mips/ath79/mach-pb44.c @@ -0,0 +1,56 @@ +/* + * Atheros PB44 reference board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "machtypes.h" + +#define PB44_GPIO_I2C_SCL 0 +#define PB44_GPIO_I2C_SDA 1 + +#define PB44_GPIO_EXP_BASE 16 + +static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { + .sda_pin = PB44_GPIO_I2C_SDA, + .scl_pin = PB44_GPIO_I2C_SCL, +}; + +static struct platform_device pb44_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &pb44_i2c_gpio_data, + } +}; + +static struct pcf857x_platform_data pb44_pcf857x_data = { + .gpio_base = PB44_GPIO_EXP_BASE, +}; + +static struct i2c_board_info pb44_i2c_board_info[] __initdata = { + { + I2C_BOARD_INFO("pcf8575", 0x20), + .platform_data = &pb44_pcf857x_data, + }, +}; + +static void __init pb44_init(void) +{ + i2c_register_board_info(0, pb44_i2c_board_info, + ARRAY_SIZE(pb44_i2c_board_info)); + platform_device_register(&pb44_i2c_gpio_device); +} + +MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", + pb44_init); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index fac0e26..a796fa3 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -16,6 +16,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, + ATH79_MACH_PB44, /* Atheros PB44 reference board */ }; #endif /* _ATH79_MACHTYPE_H */ -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:54:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:54:58 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56998 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492165Ab0KLVv7 (ORCPT ); Fri, 12 Nov 2010 22:51:59 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 664BA41C010; Fri, 12 Nov 2010 22:51:53 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 9C874270001; Fri, 12 Nov 2010 22:51:52 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos , David Brownell , Greg Kroah-Hartman , linux-usb@vger.kernel.org Subject: [RFC 15/18] USB: ohci: add bus glue for the Atheros AR71XX/AR7240 SoCs Date: Fri, 12 Nov 2010 22:51:21 +0100 Message-Id: <1289598684-30624-16-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122AADFFD6 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28373 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The Atheros AR71XX/AR7240 SoCs have a built-in OHCI controller. This patch adds the necessary glue code to make the generic OHCI driver usable for them. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: David Brownell Cc: Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org --- Sorry for sending this twice, i forgot to add some CCs in the first round. .../include/asm/mach-ath79/ath79_ehci_platform.h | 18 +++ drivers/usb/Kconfig | 2 + drivers/usb/host/Kconfig | 8 + drivers/usb/host/ohci-ath79.c | 162 ++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 5 + 5 files changed, 195 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h create mode 100644 drivers/usb/host/ohci-ath79.c diff --git a/arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h b/arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h new file mode 100644 index 0000000..6ee075f --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h @@ -0,0 +1,18 @@ +/* + * Platform data definition for Atheros AR71XX/AR913X EHCI controller + * + * Copyright (C) 2008-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_EHCI_PLATFORM_H +#define _ATH79_EHCI_PLATFORM_H + +struct ath79_ehci_platform_data { + u8 is_ar913x; +}; + +#endif /* _ATH79_EHCI_PLATFORM_H */ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index a4d06bb..6e21ab8 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -47,6 +47,8 @@ config USB_ARCH_HAS_OHCI # MIPS: default y if MIPS_ALCHEMY default y if MACH_JZ4740 + default y if SOC_AR71XX + default y if SOC_AR724X # SH: default y if CPU_SUBTYPE_SH7720 default y if CPU_SUBTYPE_SH7721 diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d01e878..14e13a2 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -239,6 +239,14 @@ config USB_OHCI_HCD_OMAP3 Enables support for the on-chip OHCI controller on OMAP3 and later chips. +config USB_OHCI_ATH79 + bool "USB OHCI support for the Atheros AR71XX/AR724X SoCs" + depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) + default y + help + Enables support for the uilt-in OHCI controller present on the + Atheros AR71XX/AR724X SoCs. + config USB_OHCI_HCD_PPC_SOC bool "OHCI support for on-chip PPC USB controller" depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) diff --git a/drivers/usb/host/ohci-ath79.c b/drivers/usb/host/ohci-ath79.c new file mode 100644 index 0000000..6e864bf --- /dev/null +++ b/drivers/usb/host/ohci-ath79.c @@ -0,0 +1,162 @@ +/* + * OHCI HCD (Host Controller Driver) for USB. + * + * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * Copyright (C) 2007 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +static int usb_hcd_ath79_probe(const struct hc_driver *driver, + struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_dbg(&pdev->dev, "no IRQ specified for %s\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "no base address specified for %s\n", + dev_name(&pdev->dev)); + ret = -ENODEV; + goto err_put_hcd; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ohci_hcd_init(hcd_to_ohci(hcd)); + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); + if (ret) + goto err_stop_hcd; + + return 0; + +err_stop_hcd: + iounmap(hcd->regs); +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +void usb_hcd_ath79_remove(struct usb_hcd *hcd, struct platform_device *pdev) +{ + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); +} + +static int __devinit ohci_ath79_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int ret; + + ret = ohci_init(ohci); + if (ret < 0) + return ret; + + ret = ohci_run(ohci); + if (ret < 0) + goto err; + + return 0; + +err: + ohci_stop(hcd); + return ret; +} + +static const struct hc_driver ohci_ath79_hc_driver = { + .description = hcd_name, + .product_desc = "Atheros built-in OHCI controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + + .irq = ohci_irq, + .flags = HCD_USB11 | HCD_MEMORY, + + .start = ohci_ath79_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ohci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, + .start_port_reset = ohci_start_port_reset, +}; + +static int ohci_hcd_ath79_drv_probe(struct platform_device *pdev) +{ + if (usb_disabled()) + return -ENODEV; + + return usb_hcd_ath79_probe(&ohci_ath79_hc_driver, pdev); +} + +static int ohci_hcd_ath79_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_hcd_ath79_remove(hcd, pdev); + return 0; +} + +static struct platform_driver ohci_hcd_ath79_driver = { + .probe = ohci_hcd_ath79_drv_probe, + .remove = ohci_hcd_ath79_drv_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "ath79-ohci", + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS("platform:ath79-ohci"); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index f3713f4..470895b 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1106,6 +1106,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_jz4740_driver #endif +#ifdef CONFIG_USB_OHCI_ATH79 +#include "ohci-ath79.c" +#define PLATFORM_DRIVER ohci_hcd_ath79_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:55:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:55:22 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:56999 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492166Ab0KLVv7 (ORCPT ); Fri, 12 Nov 2010 22:51:59 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id E4F6041C011; Fri, 12 Nov 2010 22:51:53 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 3ECDC270001; Fri, 12 Nov 2010 22:51:53 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 17/18] MIPS: ath79: add initial support for the Atheros AP81 reference board Date: Fri, 12 Nov 2010 22:51:23 +0100 Message-Id: <1289598684-30624-18-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122BA70962 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28374 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- arch/mips/ath79/Kconfig | 13 ++++++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/mach-ap81.c | 93 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 108 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/mach-ap81.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 9843044..53d9b39 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -2,6 +2,19 @@ if ATH79 menu "Atheros AR71XX/AR724X/AR913X machine selection" +config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X + select ATH79_DEV_AR913X_WMAC + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + select ATH79_DEV_USB + default n + help + Say 'Y' here if you want your kernel to support the + Atheros AP81 reference board. + config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index e0c07a7..107f1e8 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -22,4 +22,5 @@ obj-$(CONFIG_ATH79_DEV_WDT) += dev-wdt.o # # Machines # +obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c new file mode 100644 index 0000000..9cfaff3 --- /dev/null +++ b/arch/mips/ath79/mach-ap81.c @@ -0,0 +1,93 @@ +/* + * Atheros AP81 board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * Copyright (C) 2009 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "machtypes.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" +#include "dev-usb.h" + +#define AP81_GPIO_LED_STATUS 1 +#define AP81_GPIO_LED_AOSS 3 +#define AP81_GPIO_LED_WLAN 6 +#define AP81_GPIO_LED_POWER 14 + +#define AP81_GPIO_BTN_SW4 12 +#define AP81_GPIO_BTN_SW1 21 + +#define AP81_BUTTONS_POLL_INTERVAL 20 + +static struct gpio_led ap81_leds_gpio[] __initdata = { + { + .name = "ap81:green:status", + .gpio = AP81_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "ap81:amber:aoss", + .gpio = AP81_GPIO_LED_AOSS, + .active_low = 1, + }, { + .name = "ap81:green:wlan", + .gpio = AP81_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "ap81:green:power", + .gpio = AP81_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static struct gpio_button ap81_gpio_buttons[] __initdata = { + { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .threshold = 3, + .gpio = AP81_GPIO_BTN_SW1, + .active_low = 1, + } , { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_1, + .threshold = 3, + .gpio = AP81_GPIO_BTN_SW4, + .active_low = 1, + } +}; + +static struct spi_board_info ap81_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", + } +}; + +static struct ath79_spi_platform_data ap81_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +static void __init ap81_setup(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), + ap81_leds_gpio); + ath79_register_gpio_buttons(-1, AP81_BUTTONS_POLL_INTERVAL, + ARRAY_SIZE(ap81_gpio_buttons), + ap81_gpio_buttons); + ath79_register_spi(&ap81_spi_data, ap81_spi_info, + ARRAY_SIZE(ap81_spi_info)); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", + ap81_setup); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index a796fa3..3940fe4 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -16,6 +16,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP81, /* Atheros AP81 reference board */ ATH79_MACH_PB44, /* Atheros PB44 reference board */ }; -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:55:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:55:48 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57010 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492167Ab0KLVv7 (ORCPT ); Fri, 12 Nov 2010 22:51:59 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id BF13A41C008; Fri, 12 Nov 2010 22:51:50 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 05AEB270001; Fri, 12 Nov 2010 22:51:50 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos , Wim Van Sebroeck , linux-watchdog@vger.kernel.org Subject: [RFC 07/18] watchdog: add driver for the Atheros AR71XX/AR724X/AR913X SoCs Date: Fri, 12 Nov 2010 22:51:13 +0100 Message-Id: <1289598684-30624-8-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122844ACD8 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28375 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch adds a driver for the built-in hardware watchdog device of the Atheros AR71XX/AR724X/AR913X SoCs. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: Wim Van Sebroeck Cc: linux-watchdog@vger.kernel.org --- Sorry for sending this twice, i forgot to add some CCs in the first round. drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ath79_wdt.c | 293 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 302 insertions(+), 0 deletions(-) create mode 100644 drivers/watchdog/ath79_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 4a29104..998eed3 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -927,6 +927,14 @@ config BCM63XX_WDT To compile this driver as a loadable module, choose M here. The module will be called bcm63xx_wdt. +config ATH79_WDT + tristate "Atheros AR71XX/AR724X/AR913X hardware watchdog" + depends on ATH79 + help + Hardware driver for the built-in watchdog timer on the Atheros + AR71XX/AR724X/AR913X SoCs. + + # PARISC Architecture # POWERPC Architecture diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 4b0ef38..6d7af07 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -117,6 +117,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o obj-$(CONFIG_AR7_WDT) += ar7_wdt.o obj-$(CONFIG_TXX9_WDT) += txx9wdt.o +obj-$(CONFIG_ATH79_WDT) += ath79_wdt.o obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o diff --git a/drivers/watchdog/ath79_wdt.c b/drivers/watchdog/ath79_wdt.c new file mode 100644 index 0000000..f8e027b --- /dev/null +++ b/drivers/watchdog/ath79_wdt.c @@ -0,0 +1,293 @@ +/* + * Atheros AR71XX/AR724X/AR913X built-in hardware watchdog timer. + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This driver was based on: drivers/watchdog/ixp4xx_wdt.c + * Author: Deepak Saxena + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * which again was based on sa1100 driver, + * Copyright (C) 2000 Oleg Drokin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "ath79-wdt" +#define DRIVER_DESC "Atheros AR71XX/AR724X/AR913X hardware watchdog driver" + +#define WDT_TIMEOUT 15 /* seconds */ + +#define WDOG_CTRL_LAST_RESET BIT(31) +#define WDOG_CTRL_ACTION_MASK 3 +#define WDOG_CTRL_ACTION_NONE 0 /* no action */ +#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ +#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ +#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ + +static int nowayout = WATCHDOG_NOWAYOUT; + +#ifdef CONFIG_WATCHDOG_NOWAYOUT +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " + "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +#endif + +static unsigned long wdt_flags; + +#define WDT_FLAGS_BUSY 0 +#define WDT_FLAGS_EXPECT_CLOSE 1 + +static int wdt_timeout = WDT_TIMEOUT; +static int boot_status; +static int max_timeout; + +static inline void ath79_wdt_keepalive(void) +{ + ath79_reset_wr(AR71XX_RESET_REG_WDOG, ath79_ahb_freq * wdt_timeout); +} + +static inline void ath79_wdt_enable(void) +{ + ath79_wdt_keepalive(); + ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); +} + +static inline void ath79_wdt_disable(void) +{ + ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); +} + +static int ath79_wdt_set_timeout(int val) +{ + if (val < 1 || val > max_timeout) + return -EINVAL; + + wdt_timeout = val; + ath79_wdt_keepalive(); + + return 0; +} + +static int ath79_wdt_open(struct inode *inode, struct file *file) +{ + if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags)) + return -EBUSY; + + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + ath79_wdt_enable(); + + return nonseekable_open(inode, file); +} + +static int ath79_wdt_release(struct inode *inode, struct file *file) +{ + if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags)) + ath79_wdt_disable(); + else + pr_crit(DRIVER_NAME ": device closed unexpectedly, " + "watchdog timer will not stop!\n"); + + clear_bit(WDT_FLAGS_BUSY, &wdt_flags); + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + + return 0; +} + +static ssize_t ath79_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) +{ + if (len) { + if (!nowayout) { + size_t i; + + clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + + for (i = 0; i != len; i++) { + char c; + + if (get_user(c, data + i)) + return -EFAULT; + + if (c == 'V') + set_bit(WDT_FLAGS_EXPECT_CLOSE, + &wdt_flags); + } + } + + ath79_wdt_keepalive(); + } + + return len; +} + +static const struct watchdog_info ath79_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE | WDIOF_CARDRESET, + .firmware_version = 0, + .identity = "ATH79 watchdog", +}; + +static long ath79_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + void __user *argp = (void __user *)arg; + int __user *p = argp; + int err; + int t; + + switch (cmd) { + case WDIOC_GETSUPPORT: + err = copy_to_user(argp, &ath79_wdt_info, + sizeof(ath79_wdt_info)) ? -EFAULT : 0; + break; + + case WDIOC_GETSTATUS: + err = put_user(0, p); + break; + + case WDIOC_GETBOOTSTATUS: + err = put_user(boot_status, p); + break; + + case WDIOC_KEEPALIVE: + ath79_wdt_keepalive(); + err = 0; + break; + + case WDIOC_SETTIMEOUT: + err = get_user(t, p); + if (err) + break; + + err = ath79_wdt_set_timeout(t); + if (err) + break; + + /* fallthrough */ + case WDIOC_GETTIMEOUT: + err = put_user(wdt_timeout, p); + break; + + default: + err = -ENOTTY; + break; + } + + return err; +} + +static const struct file_operations ath79_wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = ath79_wdt_write, + .unlocked_ioctl = ath79_wdt_ioctl, + .open = ath79_wdt_open, + .release = ath79_wdt_release, +}; + +static int ath79_wdt_notify_sys(struct notifier_block *this, + unsigned long code, void *unused) +{ + if (code == SYS_DOWN || code == SYS_HALT) + ath79_wdt_disable(); + + return NOTIFY_DONE; +} + +static struct notifier_block ath79_wdt_notifier = { + .notifier_call = ath79_wdt_notify_sys, +}; + +static struct miscdevice ath79_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &ath79_wdt_fops, +}; + +static int __init ath79_wdt_probe(struct platform_device *pdev) +{ + u32 ctrl; + int err; + + max_timeout = (0xfffffffful / ath79_ahb_freq); + wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; + + ctrl = ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL); + boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0; + + err = register_reboot_notifier(&ath79_wdt_notifier); + if (err) { + dev_err(&pdev->dev, + "unable to register reboot notifier, err=%d\n", err); + goto err; + } + + err = misc_register(&ath79_wdt_miscdev); + if (err) { + dev_err(&pdev->dev, + "unable to register misc device, err=%d\n", err); + goto err_unregister; + } + + return 0; + +err_unregister: + unregister_reboot_notifier(&ath79_wdt_notifier); + +err: + return err; +} + +static int __exit ath79_wdt_remove(struct platform_device *pdev) +{ + misc_deregister(&ath79_wdt_miscdev); + return 0; +} + +static struct platform_driver ath79_wdt_driver = { + .remove = __exit_p(ath79_wdt_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ath79_wdt_init(void) +{ + return platform_driver_probe(&ath79_wdt_driver, ath79_wdt_probe); +} +module_init(ath79_wdt_init); + +static void __exit ath79_wdt_exit(void) +{ + platform_driver_unregister(&ath79_wdt_driver); +} +module_exit(ath79_wdt_exit); + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_AUTHOR("Gabor Juhos ); Fri, 12 Nov 2010 22:51:59 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id A120941C00B; Fri, 12 Nov 2010 22:51:51 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id E0E07270002; Fri, 12 Nov 2010 22:51:50 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 10/18] MIPS: ath79: add common GPIO buttons device Date: Fri, 12 Nov 2010 22:51:16 +0100 Message-Id: <1289598684-30624-11-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122942C7B7 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28376 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Almost all boards have one or more push buttons connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the buttons on the PB44 board. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- arch/mips/ath79/Kconfig | 4 ++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-gpio-buttons.c | 58 ++++++++++++++++++++++++++++++++++++ arch/mips/ath79/dev-gpio-buttons.h | 23 ++++++++++++++ arch/mips/ath79/mach-pb44.c | 26 ++++++++++++++++ 5 files changed, 112 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-gpio-buttons.c create mode 100644 arch/mips/ath79/dev-gpio-buttons.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 79bb528..0c34db1 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -5,6 +5,7 @@ menu "Atheros AR71XX/AR724X/AR913X machine selection" config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX + select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO default n help @@ -22,6 +23,9 @@ config SOC_AR724X config SOC_AR913X def_bool n +config ATH79_DEV_GPIO_BUTTONS + def_bool n + config ATH79_DEV_LEDS_GPIO def_bool n diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 1b01868..c604f46 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -12,6 +12,7 @@ obj-y := prom.o setup.o irq.o common.o gpio.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_UART) += dev-uart.o obj-$(CONFIG_ATH79_DEV_WDT) += dev-wdt.o diff --git a/arch/mips/ath79/dev-gpio-buttons.c b/arch/mips/ath79/dev-gpio-buttons.c new file mode 100644 index 0000000..3bc4a18 --- /dev/null +++ b/arch/mips/ath79/dev-gpio-buttons.c @@ -0,0 +1,58 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO button support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "linux/init.h" +#include "linux/slab.h" +#include + +#include "dev-gpio-buttons.h" + +void __init ath79_register_gpio_buttons(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_button *buttons) +{ + struct platform_device *pdev; + struct gpio_buttons_platform_data pdata; + struct gpio_button *p; + int err; + + p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, buttons, nbuttons * sizeof(*p)); + + pdev = platform_device_alloc("gpio-buttons", id); + if (!pdev) + goto err_free_buttons; + + memset(&pdata, 0, sizeof(pdata)); + pdata.poll_interval = poll_interval; + pdata.nbuttons = nbuttons; + pdata.buttons = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_buttons: + kfree(p); +} diff --git a/arch/mips/ath79/dev-gpio-buttons.h b/arch/mips/ath79/dev-gpio-buttons.h new file mode 100644 index 0000000..57bf1d6f --- /dev/null +++ b/arch/mips/ath79/dev-gpio-buttons.h @@ -0,0 +1,23 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO button support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_GPIO_BUTTONS_H +#define _ATH79_DEV_GPIO_BUTTONS_H + +#include +#include + +void ath79_register_gpio_buttons(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_button *buttons) __init; + +#endif /* _ATH79_DEV_GPIO_BUTTONS_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index e176779..5e7b544 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -15,15 +15,20 @@ #include #include "machtypes.h" +#include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 #define PB44_GPIO_EXP_BASE 16 +#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) +#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) #define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) +#define PB44_BUTTONS_POLL_INTERVAL 20 + static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { .sda_pin = PB44_GPIO_I2C_SDA, .scl_pin = PB44_GPIO_I2C_SCL, @@ -60,6 +65,24 @@ static struct gpio_led pb44_leds_gpio[] __initdata = { }, }; +static struct gpio_button pb44_gpio_buttons[] __initdata = { + { + .desc = "soft_reset", + .type = EV_KEY, + .code = KEY_RESTART, + .threshold = 3, + .gpio = PB44_GPIO_SW_RESET, + .active_low = 1, + } , { + .desc = "jumpstart", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .threshold = 3, + .gpio = PB44_GPIO_SW_JUMP, + .active_low = 1, + } +}; + static void __init pb44_init(void) { i2c_register_board_info(0, pb44_i2c_board_info, @@ -68,6 +91,9 @@ static void __init pb44_init(void) ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), pb44_leds_gpio); + ath79_register_gpio_buttons(-1, PB44_BUTTONS_POLL_INTERVAL, + ARRAY_SIZE(pb44_gpio_buttons), + pb44_gpio_buttons); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:56:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:56:38 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57011 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492168Ab0KLVv7 (ORCPT ); Fri, 12 Nov 2010 22:51:59 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id F3C5A41C009; Fri, 12 Nov 2010 22:51:50 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 50EA1270002; Fri, 12 Nov 2010 22:51:50 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 08/18] MIPS: ath79: add common watchdog device Date: Fri, 12 Nov 2010 22:51:14 +0100 Message-Id: <1289598684-30624-9-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A1228985E73 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28377 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips All supported SoCs have a built-in hardware watchdog driver. This patch registers a platform_device for that to make it usable. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- arch/mips/ath79/Kconfig | 3 +++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-wdt.c | 30 ++++++++++++++++++++++++++++++ arch/mips/ath79/dev-wdt.h | 17 +++++++++++++++++ arch/mips/ath79/setup.c | 2 ++ 5 files changed, 53 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-wdt.c create mode 100644 arch/mips/ath79/dev-wdt.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 2bd35ef..79bb528 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -28,4 +28,7 @@ config ATH79_DEV_LEDS_GPIO config ATH79_DEV_UART def_bool y +config ATH79_DEV_WDT + def_bool y + endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index a231967..1b01868 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_UART) += dev-uart.o +obj-$(CONFIG_ATH79_DEV_WDT) += dev-wdt.o # # Machines diff --git a/arch/mips/ath79/dev-wdt.c b/arch/mips/ath79/dev-wdt.c new file mode 100644 index 0000000..ba6b8bd --- /dev/null +++ b/arch/mips/ath79/dev-wdt.c @@ -0,0 +1,30 @@ +/* + * Atheros AR71XX/AR724X/AR913X watchdog device + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include "common.h" +#include "dev-wdt.h" + +static struct platform_device ath79_wdt_device = { + .name = "ath79-wdt", + .id = -1, +}; + +void __init ath79_register_wdt(void) +{ + platform_device_register(&ath79_wdt_device); +} diff --git a/arch/mips/ath79/dev-wdt.h b/arch/mips/ath79/dev-wdt.h new file mode 100644 index 0000000..2546415 --- /dev/null +++ b/arch/mips/ath79/dev-wdt.h @@ -0,0 +1,17 @@ +/* + * Atheros AR71XX/AR724X/AR913X watchdog device + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH_DEV_WDT_H +#define _ATH_DEV_WDT_H + +void ath79_register_wdt(void) __init; + +#endif diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index b36f9f2..693a9e6 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -24,6 +24,7 @@ #include #include "common.h" #include "dev-uart.h" +#include "dev-wdt.h" #include "machtypes.h" #define ATH79_SYS_TYPE_LEN 64 @@ -259,6 +260,7 @@ static int __init ath79_setup(void) { ath79_gpio_init(); ath79_register_uart(); + ath79_register_wdt(); mips_machine_setup(); -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:56:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:57:03 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57016 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492171Ab0KLVwA (ORCPT ); Fri, 12 Nov 2010 22:52:00 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 0653D41C00C; Fri, 12 Nov 2010 22:51:52 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 32294270001; Fri, 12 Nov 2010 22:51:51 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos , David Brownell , spi-devel-general@lists.sourceforge.net Subject: [RFC 11/18] spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs Date: Fri, 12 Nov 2010 22:51:17 +0100 Message-Id: <1289598684-30624-12-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122987B96B | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28378 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This patch implements a driver for that. Signed-off-by: Gabor Juhos Cc: David Brownell Cc: spi-devel-general@lists.sourceforge.net --- Sorry for sending this twice, i forgot to add some CCs in the first round. .../include/asm/mach-ath79/ath79_spi_platform.h | 19 ++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 291 ++++++++++++++++++++ 4 files changed, 319 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h create mode 100644 drivers/spi/ath79_spi.c diff --git a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h new file mode 100644 index 0000000..aa71216 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h @@ -0,0 +1,19 @@ +/* + * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller + * + * Copyright (C) 2008-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_SPI_PLATFORM_H +#define _ATH79_SPI_PLATFORM_H + +struct ath79_spi_platform_data { + unsigned bus_num; + unsigned num_chipselect; +}; + +#endif /* _ATH79_SPI_PLATFORM_H */ diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 78f9fd0..f2093e1 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -53,6 +53,14 @@ if SPI_MASTER comment "SPI Master Controller Drivers" +config SPI_ATH79 + tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver" + depends on ATH79 && GENERIC_GPIO + select SPI_BITBANG + help + This enables support for the SPI controller present on the + Atheros AR71XX/AR724X/AR913X SoCs. + config SPI_ATMEL tristate "Atmel SPI Controller" depends on (ARCH_AT91 || AVR32) diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8bc1a5a..875bc3d 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SPI_MASTER) += spi.o # SPI master controller drivers (bus) obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o +obj-$(CONFIG_SPI_ATH79) += ath79_spi.o obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o obj-$(CONFIG_SPI_AU1550) += au1550_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..9b9f9cf --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,291 @@ +/* + * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This driver has been based on the spi-gpio.c: + * Copyright (C) 2006,2008 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_DESC "SPI controller driver for Atheros AR71XX/AR724X/AR91X" +#define DRV_NAME "ath79-spi" + +struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; + u32 reg_ctrl; + + void __iomem *base; + + struct platform_device *pdev; +}; + +static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) +{ + return __raw_readl(sp->base + reg); +} + +static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) +{ + __raw_writel(val, sp->base + reg); +} + +static inline struct ath79_spi *spidev_to_sp(struct spi_device *spi) +{ + return spi_master_get_devdata(spi->master); +} + +static void ath79_spi_chipselect(struct spi_device *spi, int is_active) +{ + struct ath79_spi *sp = spidev_to_sp(spi); + int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; + + if (is_active) { + /* set initial clock polarity */ + if (spi->mode & SPI_CPOL) + sp->ioc_base |= AR71XX_SPI_IOC_CLK; + else + sp->ioc_base &= ~AR71XX_SPI_IOC_CLK; + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + + if (spi->chip_select) { + unsigned long gpio = (unsigned long) spi->controller_data; + + /* SPI is normally active-low */ + gpio_set_value(gpio, cs_high); + } else { + if (cs_high) + sp->ioc_base |= AR71XX_SPI_IOC_CS0; + else + sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + +} + +static int ath79_spi_setup_cs(struct spi_device *spi) +{ + struct ath79_spi *sp = spidev_to_sp(spi); + + /* enable GPIO mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); + + /* save CTRL register */ + sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); + sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); + + /* TODO: setup speed? */ + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + + if (spi->chip_select) { + unsigned long gpio = (unsigned long) spi->controller_data; + int status = 0; + + status = gpio_request(gpio, dev_name(&spi->dev)); + if (status) + return status; + + status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); + if (status) { + gpio_free(gpio); + return status; + } + } else { + if (spi->mode & SPI_CS_HIGH) + sp->ioc_base |= AR71XX_SPI_IOC_CS0; + else + sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + + return 0; +} + +static void ath79_spi_cleanup_cs(struct spi_device *spi) +{ + struct ath79_spi *sp = spidev_to_sp(spi); + + if (spi->chip_select) { + unsigned long gpio = (unsigned long) spi->controller_data; + gpio_free(gpio); + } + + /* restore CTRL register */ + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); + /* disable GPIO mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); +} + +static int ath79_spi_setup(struct spi_device *spi) +{ + int status = 0; + + if (spi->bits_per_word > 32) + return -EINVAL; + + if (!spi->controller_state) { + status = ath79_spi_setup_cs(spi); + if (status) + return status; + } + + status = spi_bitbang_setup(spi); + if (status && !spi->controller_state) + ath79_spi_cleanup_cs(spi); + + return status; +} + +static void ath79_spi_cleanup(struct spi_device *spi) +{ + ath79_spi_cleanup_cs(spi); + spi_bitbang_cleanup(spi); +} + +static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, + u32 word, u8 bits) +{ + struct ath79_spi *sp = spidev_to_sp(spi); + u32 ioc = sp->ioc_base; + + /* clock starts at inactive polarity */ + for (word <<= (32 - bits); likely(bits); bits--) { + u32 out; + + if (word & (1 << 31)) + out = ioc | AR71XX_SPI_IOC_DO; + else + out = ioc & ~AR71XX_SPI_IOC_DO; + + /* setup MSB (to slave) on trailing edge */ + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); + + word <<= 1; + } + + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); +} + +static int ath79_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct ath79_spi *sp; + struct ath79_spi_platform_data *pdata; + struct resource *r; + int ret; + + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); + return -ENOMEM; + } + + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + + pdata = pdev->dev.platform_data; + + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; + if (pdata) { + master->bus_num = pdata->bus_num; + master->num_chipselect = pdata->num_chipselect; + } else { + master->bus_num = 0; + master->num_chipselect = 1; + } + + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = ath79_spi_chipselect; + sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; + sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; + sp->bitbang.flags = SPI_CS_HIGH; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + ret = -ENOENT; + goto err_put_master; + } + + sp->base = ioremap(r->start, r->end - r->start + 1); + if (!sp->base) { + ret = -ENXIO; + goto err_put_master; + } + + ret = spi_bitbang_start(&sp->bitbang); + if (ret) + goto err_unmap; + + return 0; + +err_unmap: + iounmap(sp->base); +err_put_master: + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + + return ret; +} + +static int ath79_spi_remove(struct platform_device *pdev) +{ + struct ath79_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + + return 0; +} + +static struct platform_driver ath79_spi_drv = { + .probe = ath79_spi_probe, + .remove = ath79_spi_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ath79_spi_init(void) +{ + return platform_driver_register(&ath79_spi_drv); +} +module_init(ath79_spi_init); + +static void __exit ath79_spi_exit(void) +{ + platform_driver_unregister(&ath79_spi_drv); +} +module_exit(ath79_spi_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:57:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:57:29 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57014 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492170Ab0KLVv7 (ORCPT ); Fri, 12 Nov 2010 22:51:59 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 6298041C00A; Fri, 12 Nov 2010 22:51:51 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 8D69B270001; Fri, 12 Nov 2010 22:51:50 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos , Dmitry Torokhov , Mike Frysinger , linux-input@vger.kernel.org Subject: [RFC 09/18] input: add input driver for polled GPIO buttons Date: Fri, 12 Nov 2010 22:51:15 +0100 Message-Id: <1289598684-30624-10-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A1228FDC681 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28379 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The existing gpio-keys driver can be usable only for GPIO lines with interrupt support. Several devices have buttons connected to a GPIO line which is not capable to generate interrupts. This patch adds a new input driver using the generic GPIO layer and the input-polldev to support such buttons. Signed-off-by: Gabor Juhos Cc: Dmitry Torokhov Cc: Mike Frysinger Cc: linux-input@vger.kernel.org --- Sorry for sending this twice, i forgot to add some CCs in the first round. drivers/input/misc/Kconfig | 16 +++ drivers/input/misc/Makefile | 1 + drivers/input/misc/gpio_buttons.c | 232 +++++++++++++++++++++++++++++++++++++ include/linux/gpio_buttons.h | 33 +++++ 4 files changed, 282 insertions(+), 0 deletions(-) create mode 100644 drivers/input/misc/gpio_buttons.c create mode 100644 include/linux/gpio_buttons.h diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index b99b8cb..3439b79 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -448,4 +448,20 @@ config INPUT_ADXL34X_SPI To compile this driver as a module, choose M here: the module will be called adxl34x-spi. +config INPUT_GPIO_BUTTONS + tristate "Polled GPIO buttons interface" + depends on GENERIC_GPIO + select INPUT_POLLDEV + help + This driver implements support for buttons connected + to GPIO pins of various CPUs (and some other chips). + + Say Y here if your device has buttons connected + directly to such GPIO pins. Your board-specific + setup logic must also provide a platform device, + with configuration data saying which GPIOs are used. + + To compile this driver as a module, choose M here: the + module will be called gpio-buttons. + endif diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 1fe1f6c..3791050 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -42,4 +42,5 @@ obj-$(CONFIG_INPUT_WINBOND_CIR) += winbond-cir.o obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o +obj-$(CONFIG_INPUT_GPIO_BUTTONS) += gpio_buttons.o diff --git a/drivers/input/misc/gpio_buttons.c b/drivers/input/misc/gpio_buttons.c new file mode 100644 index 0000000..51288a3 --- /dev/null +++ b/drivers/input/misc/gpio_buttons.c @@ -0,0 +1,232 @@ +/* + * Driver for buttons on GPIO lines not capable of generating interrupts + * + * Copyright (C) 2007-2010 Gabor Juhos + * Copyright (C) 2010 Nuno Goncalves + * + * This file was based on: /drivers/input/misc/cobalt_btns.c + * Copyright (C) 2007 Yoichi Yuasa + * + * also was based on: /drivers/input/keyboard/gpio_keys.c + * Copyright 2005 Phil Blundell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "gpio-buttons" + +struct gpio_button_data { + int last_state; + int count; + int can_sleep; +}; + +struct gpio_buttons_dev { + struct input_polled_dev *poll_dev; + struct gpio_buttons_platform_data *pdata; + struct gpio_button_data *data; +}; + +static void gpio_buttons_check_state(struct input_dev *input, + struct gpio_button *button, + struct gpio_button_data *bdata) +{ + int state; + + if (bdata->can_sleep) + state = !!gpio_get_value_cansleep(button->gpio); + else + state = !!gpio_get_value(button->gpio); + + if (state != bdata->last_state) { + unsigned int type = button->type ?: EV_KEY; + + input_event(input, type, button->code, + !!(state ^ button->active_low)); + input_sync(input); + bdata->count = 0; + bdata->last_state = state; + } +} + +static void gpio_buttons_poll(struct input_polled_dev *dev) +{ + struct gpio_buttons_dev *bdev = dev->private; + struct gpio_buttons_platform_data *pdata = bdev->pdata; + struct input_dev *input = dev->input; + int i; + + for (i = 0; i < bdev->pdata->nbuttons; i++) { + struct gpio_button *button = &pdata->buttons[i]; + struct gpio_button_data *bdata = &bdev->data[i]; + + if (bdata->count < button->threshold) + bdata->count++; + else + gpio_buttons_check_state(input, button, bdata); + + } +} + +static int __devinit gpio_buttons_probe(struct platform_device *pdev) +{ + struct gpio_buttons_platform_data *pdata = pdev->dev.platform_data; + struct device *dev = &pdev->dev; + struct gpio_buttons_dev *bdev; + struct input_polled_dev *poll_dev; + struct input_dev *input; + int error; + int i; + + if (!pdata) + return -ENXIO; + + bdev = kzalloc(sizeof(struct gpio_buttons_dev) + + pdata->nbuttons * sizeof(struct gpio_button_data), + GFP_KERNEL); + if (!bdev) { + dev_err(dev, "no memory for private data\n"); + return -ENOMEM; + } + + bdev->data = (struct gpio_button_data *) &bdev[1]; + + poll_dev = input_allocate_polled_device(); + if (!poll_dev) { + dev_err(dev, "no memory for polled device\n"); + error = -ENOMEM; + goto err_free_bdev; + } + + poll_dev->private = bdev; + poll_dev->poll = gpio_buttons_poll; + poll_dev->poll_interval = pdata->poll_interval; + + input = poll_dev->input; + + input->evbit[0] = BIT(EV_KEY); + input->name = pdev->name; + input->phys = "gpio-buttons/input0"; + input->dev.parent = &pdev->dev; + + input->id.bustype = BUS_HOST; + input->id.vendor = 0x0001; + input->id.product = 0x0001; + input->id.version = 0x0100; + + for (i = 0; i < pdata->nbuttons; i++) { + struct gpio_button *button = &pdata->buttons[i]; + unsigned int gpio = button->gpio; + unsigned int type = button->type ?: EV_KEY; + + error = gpio_request(gpio, + button->desc ? button->desc : DRV_NAME); + if (error) { + dev_err(dev, "unable to claim gpio %u, err=%d\n", + gpio, error); + goto err_free_gpio; + } + + error = gpio_direction_input(gpio); + if (error) { + dev_err(dev, + "unable to set direction on gpio %u, err=%d\n", + gpio, error); + goto err_free_gpio; + } + + bdev->data[i].can_sleep = gpio_cansleep(gpio); + bdev->data[i].last_state = -1; + + input_set_capability(input, type, button->code); + } + + bdev->poll_dev = poll_dev; + bdev->pdata = pdata; + platform_set_drvdata(pdev, bdev); + + error = input_register_polled_device(poll_dev); + if (error) { + dev_err(dev, "unable to register polled device, err=%d\n", + error); + goto err_free_gpio; + } + + /* report initial state of the buttons */ + for (i = 0; i < pdata->nbuttons; i++) + gpio_buttons_check_state(input, &pdata->buttons[i], + &bdev->data[i]); + + return 0; + +err_free_gpio: + for (i = i - 1; i >= 0; i--) + gpio_free(pdata->buttons[i].gpio); + + input_free_polled_device(poll_dev); + +err_free_bdev: + kfree(bdev); + + platform_set_drvdata(pdev, NULL); + return error; +} + +static int __devexit gpio_buttons_remove(struct platform_device *pdev) +{ + struct gpio_buttons_dev *bdev = platform_get_drvdata(pdev); + struct gpio_buttons_platform_data *pdata = bdev->pdata; + int i; + + input_unregister_polled_device(bdev->poll_dev); + + for (i = 0; i < pdata->nbuttons; i++) + gpio_free(pdata->buttons[i].gpio); + + input_free_polled_device(bdev->poll_dev); + + kfree(bdev); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver gpio_buttons_driver = { + .probe = gpio_buttons_probe, + .remove = __devexit_p(gpio_buttons_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init gpio_buttons_init(void) +{ + return platform_driver_register(&gpio_buttons_driver); +} + +static void __exit gpio_buttons_exit(void) +{ + platform_driver_unregister(&gpio_buttons_driver); +} + +module_init(gpio_buttons_init); +module_exit(gpio_buttons_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION("Polled GPIO Buttons driver"); diff --git a/include/linux/gpio_buttons.h b/include/linux/gpio_buttons.h new file mode 100644 index 0000000..f85b993 --- /dev/null +++ b/include/linux/gpio_buttons.h @@ -0,0 +1,33 @@ +/* + * Definitions for the GPIO buttons interface driver + * + * Copyright (C) 2007-2010 Gabor Juhos + * + * This file was based on: /include/linux/gpio_keys.h + * The original gpio_keys.h seems not to have a license. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _GPIO_BUTTONS_H_ +#define _GPIO_BUTTONS_H_ + +struct gpio_button { + int gpio; /* GPIO line number */ + int active_low; + char *desc; /* button description */ + int type; /* input event type (EV_KEY, EV_SW) */ + int code; /* input event code (KEY_*, SW_*) */ + int threshold; /* count threshold */ +}; + +struct gpio_buttons_platform_data { + struct gpio_button *buttons; + int nbuttons; /* number of buttons */ + int poll_interval; /* polling interval */ +}; + +#endif /* _GPIO_BUTTONS_H_ */ -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:57:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:57:55 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57018 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492173Ab0KLVwA (ORCPT ); Fri, 12 Nov 2010 22:52:00 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id D408E41C00E; Fri, 12 Nov 2010 22:51:52 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 163DE270001; Fri, 12 Nov 2010 22:51:52 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos , David Brownell , Greg Kroah-Hartman , linux-usb@vger.kernel.org Subject: [RFC 13/18] USB: ehci: add workaround for Synopsys HC bug Date: Fri, 12 Nov 2010 22:51:19 +0100 Message-Id: <1289598684-30624-14-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122A2500A7 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28380 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips A Synopsys USB core used in various SoCs has a bug which might cause that the host controller not issuing ping. When software uses the Doorbell mechanism to remove queue heads, the host controller still has references to the removed queue head even after indicating an Interrupt on Async Advance. This happens if the last executed queue head's Next Link queue head is removed. Consequences of the defect: The Host controller fetches the removed queue head, using memory that would otherwise be deallocated.This results in incorrect transactions on both the USB and system memory. This may result in undefined behavior. Workarounds: 1) If no queue head is active (no Status field's Active bit is set) after removing the queue heads, the software can write one of the valid queue head addresses to the ASYNCLISTADDR register and deallocate the removed queue head's memory after 2 microframes. If one or more of the queue heads is active (the Active bit is set in the Status field) after removing the queue heads, the software can delay memory deallocation after time X, where X is the time required for the Host Controller to go through all the queue heads once. X varies with the number of queue heads and the time required to process periodic transactions: if more periodic transactions must be performed, the Host Controller has less time to process asynchronous transaction processing. 2) Do not use the Doorbell mechanism to remove the queue heads. Disable the Asynchronous Schedule Enable bit instead. The bug has been discussed on the linux-usb-devel mailing-list four years ago, the original thread can be found here: http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg45345.html This patch implements the first workaround as suggested by David Brownell. The built-in USB host controller of the Atheros AR7130/AR7141/AR7161 SoCs requires this to work properly. Signed-off-by: Gabor Juhos Cc: David Brownell Cc: Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org --- Sorry for sending this twice, i forgot to add some CCs in the first round. drivers/usb/host/ehci-q.c | 3 +++ drivers/usb/host/ehci.h | 1 + 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c index 233c288..343b8de 100644 --- a/drivers/usb/host/ehci-q.c +++ b/drivers/usb/host/ehci-q.c @@ -1193,6 +1193,9 @@ static void end_unlink_async (struct ehci_hcd *ehci) ehci->reclaim = NULL; start_unlink_async (ehci, next); } + + if (ehci->has_synopsys_hc_bug) + writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); } /* makes sure the async qh will become idle */ diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index bde823f..7c0151a 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -131,6 +131,7 @@ struct ehci_hcd { /* one per controller */ unsigned need_io_watchdog:1; unsigned broken_periodic:1; unsigned fs_i_thresh:1; /* Intel iso scheduling */ + unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ /* required for usb32 quirk */ #define OHCI_CTRL_HCFS (3 << 6) -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:58:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:58:20 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57017 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492172Ab0KLVwA (ORCPT ); Fri, 12 Nov 2010 22:52:00 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 85EE841C00D; Fri, 12 Nov 2010 22:51:52 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 8034D270002; Fri, 12 Nov 2010 22:51:51 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 12/18] MIPS: ath79: add common SPI controller device Date: Fri, 12 Nov 2010 22:51:18 +0100 Message-Id: <1289598684-30624-13-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A1229D0BBBF | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28381 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Several boards are using the built-in SPI controller of the AR71XX/AR724X/AR913X SoCs. This patch adds common platform_device and helper code to register it. Additionally, the patch registers the SPI bus on the PB44 board. Signed-off-by: Gabor Juhos --- arch/mips/ath79/Kconfig | 4 ++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-spi.c | 38 ++++++++++++++++++++++++ arch/mips/ath79/dev-spi.h | 22 ++++++++++++++ arch/mips/ath79/mach-pb44.c | 17 ++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 + 6 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-spi.c create mode 100644 arch/mips/ath79/dev-spi.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 0c34db1..78f9999 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -7,6 +7,7 @@ config ATH79_MACH_PB44 select SOC_AR71XX select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI default n help Say 'Y' here if you want your kernel to support the @@ -29,6 +30,9 @@ config ATH79_DEV_GPIO_BUTTONS config ATH79_DEV_LEDS_GPIO def_bool n +config ATH79_DEV_SPI + def_bool n + config ATH79_DEV_UART def_bool y diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index c604f46..875df71 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o +obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o obj-$(CONFIG_ATH79_DEV_UART) += dev-uart.o obj-$(CONFIG_ATH79_DEV_WDT) += dev-wdt.o diff --git a/arch/mips/ath79/dev-spi.c b/arch/mips/ath79/dev-spi.c new file mode 100644 index 0000000..aa30163 --- /dev/null +++ b/arch/mips/ath79/dev-spi.c @@ -0,0 +1,38 @@ +/* + * Atheros AR71XX/AR724X/AR913X SPI controller device + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "dev-spi.h" + +static struct resource ath79_spi_resources[] = { + { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ath79_spi_device = { + .name = "ath79-spi", + .id = -1, + .resource = ath79_spi_resources, + .num_resources = ARRAY_SIZE(ath79_spi_resources), +}; + +void __init ath79_register_spi(struct ath79_spi_platform_data *pdata, + struct spi_board_info const *info, + unsigned n) +{ + spi_register_board_info(info, n); + ath79_spi_device.dev.platform_data = pdata; + platform_device_register(&ath79_spi_device); +} diff --git a/arch/mips/ath79/dev-spi.h b/arch/mips/ath79/dev-spi.h new file mode 100644 index 0000000..9a98333 --- /dev/null +++ b/arch/mips/ath79/dev-spi.h @@ -0,0 +1,22 @@ +/* + * Atheros AR71XX/AR724X/AR913X SPI controller device + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_SPI_H +#define _ATH79_DEV_SPI_H + +#include +#include + +void __init ath79_register_spi(struct ath79_spi_platform_data *pdata, + struct spi_board_info const *info, + unsigned n); + +#endif /* _ATH79_DEV_SPI_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index 5e7b544..257815e 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -17,6 +17,7 @@ #include "machtypes.h" #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" +#include "dev-spi.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 @@ -83,6 +84,20 @@ static struct gpio_button pb44_gpio_buttons[] __initdata = { } }; +static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", + }, +}; + +static struct ath79_spi_platform_data pb44_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + static void __init pb44_init(void) { i2c_register_board_info(0, pb44_i2c_board_info, @@ -94,6 +109,8 @@ static void __init pb44_init(void) ath79_register_gpio_buttons(-1, PB44_BUTTONS_POLL_INTERVAL, ARRAY_SIZE(pb44_gpio_buttons), pb44_gpio_buttons); + ath79_register_spi(&pb44_spi_data, pb44_spi_info, + ARRAY_SIZE(pb44_spi_info)); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 7f2933d..4f2b621 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -20,6 +20,8 @@ #include #define AR71XX_APB_BASE 0x18000000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) #define AR71XX_DDR_CTRL_SIZE 0x100 -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:58:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:58:46 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57019 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492174Ab0KLVwA (ORCPT ); Fri, 12 Nov 2010 22:52:00 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 1AA9A41C00F; Fri, 12 Nov 2010 22:51:53 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 54BE5270002; Fri, 12 Nov 2010 22:51:52 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos , David Brownell , Greg Kroah-Hartman , linux-usb@vger.kernel.org Subject: [RFC 14/18] USB: ehci: add bus glue for the Atheros AR71XX/AR724X/AR913X SoCs Date: Fri, 12 Nov 2010 22:51:20 +0100 Message-Id: <1289598684-30624-15-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122A696A1A | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28382 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips The Atheros AR71XX/AR724X/AR913X SoCs have a built-in EHCI controller. This patch adds the necessary glue code to make the generic EHCI driver usable for them. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: David Brownell Cc: Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org --- Sorry for sending this twice, i forgot to add some CCs in the first round. drivers/usb/Kconfig | 3 + drivers/usb/host/Kconfig | 8 ++ drivers/usb/host/ehci-ath79.c | 176 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + 4 files changed, 192 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-ath79.c diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 67eb377..a4d06bb 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -60,6 +60,9 @@ config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx default y if PPC_MPC512x + default y if SOC_AR71XX + default y if SOC_AR724X + default y if SOC_AR913X default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index bf2e7d2..d01e878 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -146,6 +146,14 @@ config USB_W90X900_EHCI ---help--- Enables support for the W90X900 USB controller +config USB_EHCI_ATH79 + bool "EHCI support for AR71XX/AR724X/AR913X SoCs" + depends on USB_EHCI_HCD && ATH79 + select USB_EHCI_ROOT_HUB_TT + ---help--- + Enables support for the built-in EHCI controller present + on the Atheros AR71XX/AR724X/AR913X SoCs. + config USB_OXU210HP_HCD tristate "OXU210HP HCD support" depends on USB diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c new file mode 100644 index 0000000..43a728f --- /dev/null +++ b/drivers/usb/host/ehci-ath79.c @@ -0,0 +1,176 @@ +/* + * Bus Glue for Atheros AR71XX/AR913X built-in EHCI controller. + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * Copyright (C) 2007 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +static int ehci_ath79_init(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct ath79_ehci_platform_data *pdata; + int ret; + + pdata = hcd->self.controller->platform_data; + + if (pdata->is_ar913x) { + hcd->has_tt = 1; + + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + } else { + ehci->has_synopsys_hc_bug = 1; + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + } + + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + ehci->sbrn = 0x20; + + ehci_reset(ehci); + + ret = ehci_init(hcd); + if (ret) + return ret; + + ehci_port_power(ehci, 0); + + return 0; +} + +static const struct hc_driver ehci_ath79_hc_driver = { + .description = hcd_name, + .product_desc = "Atheros built-in EHCI controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + .reset = ehci_ath79_init, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#ifdef CONFIG_PM + .hub_suspend = ehci_hub_suspend, + .hub_resume = ehci_hub_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_ath79_probe(struct platform_device *pdev) +{ + struct ath79_ehci_platform_data *pdata; + struct usb_hcd *hcd; + struct resource *res; + int irq; + int ret; + + if (usb_disabled()) + return -ENODEV; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_dbg(&pdev->dev, "no platform data specified for %s\n", + dev_name(&pdev->dev)); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_dbg(&pdev->dev, "no IRQ specified for %s\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "no base address specified for %s\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + + hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + ret = -EBUSY; + goto err_put_hcd; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + ret = -EFAULT; + goto err_release_region; + } + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (ret) + goto err_iounmap; + + return 0; + +err_iounmap: + iounmap(hcd->regs); + +err_release_region: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_put_hcd: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_ath79_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +static struct platform_driver ehci_ath79_driver = { + .probe = ehci_ath79_probe, + .remove = ehci_ath79_remove, + .driver = { + .owner = THIS_MODULE, + .name = "ath79-ehci", + } +}; + +MODULE_ALIAS("platform:ath79-ehci"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 2adae8e..05e759d 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1211,6 +1211,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_atmel_driver #endif +#ifdef CONFIG_USB_EHCI_ATH79 +#include "ehci-ath79.c" +#define PLATFORM_DRIVER ehci_ath79_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:59:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:59:11 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57020 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492175Ab0KLVwE (ORCPT ); Fri, 12 Nov 2010 22:52:04 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id B773841C001; Fri, 12 Nov 2010 22:51:53 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id E8C7E270002; Fri, 12 Nov 2010 22:51:52 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 16/18] MIPS: ath79: add common USB Host Controller device Date: Fri, 12 Nov 2010 22:51:22 +0100 Message-Id: <1289598684-30624-17-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122B63A736 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28383 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Add common platform_device and helper code to make the registration of the built-in USB controllers easier on the board which are using them. Also register the USB controller on the PB44 board. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- arch/mips/ath79/Kconfig | 4 + arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-usb.c | 192 ++++++++++++++++++++++++ arch/mips/ath79/dev-usb.h | 17 ++ arch/mips/ath79/mach-pb44.c | 2 + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 15 ++ 6 files changed, 231 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-usb.c create mode 100644 arch/mips/ath79/dev-usb.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 78f9999..9843044 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -8,6 +8,7 @@ config ATH79_MACH_PB44 select ATH79_DEV_GPIO_BUTTONS select ATH79_DEV_LEDS_GPIO select ATH79_DEV_SPI + select ATH79_DEV_USB default n help Say 'Y' here if you want your kernel to support the @@ -36,6 +37,9 @@ config ATH79_DEV_SPI config ATH79_DEV_UART def_bool y +config ATH79_DEV_USB + def_bool n + config ATH79_DEV_WDT def_bool y diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 875df71..e0c07a7 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o obj-$(CONFIG_ATH79_DEV_UART) += dev-uart.o +obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o obj-$(CONFIG_ATH79_DEV_WDT) += dev-wdt.o # diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c new file mode 100644 index 0000000..78b049a --- /dev/null +++ b/arch/mips/ath79/dev-usb.c @@ -0,0 +1,192 @@ +/* + * Atheros AR71XX/AR724X/AR913X USB Host Controller support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "common.h" +#include "dev-usb.h" + +static void __iomem *ath79_usb_ctrl_base; + +static struct resource ar71xx_ohci_resources[] = { + [0] = { + .start = AR71XX_OHCI_BASE, + .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_MISC_IRQ_OHCI, + .end = ATH79_MISC_IRQ_OHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource ar724x_usb_resources[] = { + [0] = { + .start = AR7240_OHCI_BASE, + .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_CPU_IRQ_USB, + .end = ATH79_CPU_IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); +static struct platform_device ath79_ohci_device = { + .name = "ath79-ohci", + .id = -1, + .resource = ar71xx_ohci_resources, + .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), + .dev = { + .dma_mask = &ath79_ohci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource ar71xx_ehci_resources[] = { + [0] = { + .start = AR71XX_EHCI_BASE, + .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ATH79_CPU_IRQ_USB, + .end = ATH79_CPU_IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); +static struct ath79_ehci_platform_data ath79_ehci_data; + +static struct platform_device ath79_ehci_device = { + .name = "ath79-ehci", + .id = -1, + .resource = ar71xx_ehci_resources, + .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), + .dev = { + .dma_mask = &ath79_ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &ath79_ehci_data, + }, +}; + +#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ + AR71XX_RESET_USB_PHY | \ + AR71XX_RESET_USB_OHCI_DLL) + +static void __init ar71xx_usb_setup(void) +{ + ath79_device_stop(AR71XX_USB_RESET_MASK); + mdelay(1000); + ath79_device_start(AR71XX_USB_RESET_MASK); + + /* Turning on the Buff and Desc swap bits */ + __raw_writel(0xf0000, ath79_usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG); + + /* WAR for HW bug. Here it adjusts the duration between two SOFS */ + __raw_writel(0x20c00, ath79_usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); + + mdelay(900); + + platform_device_register(&ath79_ohci_device); + platform_device_register(&ath79_ehci_device); +} + +#define AR724X_USB_RESET_MASK (AR71XX_RESET_USB_HOST | AR724X_RESET_OHCI_DLL) + +static void __init ar7240_usb_setup(void) +{ + ath79_device_stop(AR724X_USB_RESET_MASK); + mdelay(1000); + ath79_device_start(AR724X_USB_RESET_MASK); + + /* WAR for HW bug. Here it adjusts the duration between two SOFS */ + __raw_writel(0x3, ath79_usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); + + ath79_ohci_device.resource = ar724x_usb_resources; + ath79_ohci_device.num_resources = ARRAY_SIZE(ar724x_usb_resources); + platform_device_register(&ath79_ohci_device); +} + +static void __init ar724x_usb_setup(void) +{ + ath79_device_stop(AR724X_USB_RESET_MASK); + mdelay(1000); + ath79_device_start(AR724X_USB_RESET_MASK); + + /* WAR for HW bug. Here it adjusts the duration between two SOFS */ + __raw_writel(0x3, ath79_usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); + + ath79_ehci_data.is_ar913x = 1; + ath79_ehci_device.resource = ar724x_usb_resources; + ath79_ehci_device.num_resources = ARRAY_SIZE(ar724x_usb_resources); + platform_device_register(&ath79_ehci_device); +} + +static void __init ar913x_usb_setup(void) +{ + ath79_device_stop(AR71XX_RESET_USBSUS_OVERRIDE); + mdelay(10); + + ath79_device_start(AR71XX_RESET_USB_HOST); + mdelay(10); + + ath79_device_start(AR71XX_RESET_USB_PHY); + mdelay(10); + + ath79_ehci_data.is_ar913x = 1; + platform_device_register(&ath79_ehci_device); +} + +void __init ath79_register_usb(void) +{ + ath79_usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, + AR71XX_USB_CTRL_SIZE); + + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + ar71xx_usb_setup(); + break; + + case ATH79_SOC_AR7240: + ar7240_usb_setup(); + break; + + case ATH79_SOC_AR7241: + case ATH79_SOC_AR7242: + ar724x_usb_setup(); + break; + + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + ar913x_usb_setup(); + break; + + default: + BUG(); + } +} diff --git a/arch/mips/ath79/dev-usb.h b/arch/mips/ath79/dev-usb.h new file mode 100644 index 0000000..dbe6d3d --- /dev/null +++ b/arch/mips/ath79/dev-usb.h @@ -0,0 +1,17 @@ +/* + * Atheros AR71XX/AR724X/AR913X USB Host Controller support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_USB_H +#define _ATH79_DEV_USB_H + +void ath79_register_usb(void) __init; + +#endif /* _ATH79_DEV_USB_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index 257815e..3e0bb05 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -18,6 +18,7 @@ #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" +#include "dev-usb.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 @@ -111,6 +112,7 @@ static void __init pb44_init(void) pb44_gpio_buttons); ath79_register_spi(&pb44_spi_data, pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); + ath79_register_usb(); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 4f2b621..95be423 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -20,6 +20,10 @@ #include #define AR71XX_APB_BASE 0x18000000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 #define AR71XX_SPI_BASE 0x1f000000 #define AR71XX_SPI_SIZE 0x01000000 @@ -27,6 +31,8 @@ #define AR71XX_DDR_CTRL_SIZE 0x100 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) #define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) @@ -34,6 +40,9 @@ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) #define AR71XX_RESET_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + /* * DDR_CTRL block */ @@ -102,6 +111,12 @@ #define AR913X_AHB_DIV_MASK 0x1 /* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* * RESET block */ #define AR71XX_RESET_REG_TIMER 0x00 -- 1.7.2.1 From juhosg@openwrt.org Fri Nov 12 22:59:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 22:59:35 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:57021 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492176Ab0KLVwE (ORCPT ); Fri, 12 Nov 2010 22:52:04 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 33AF041C012; Fri, 12 Nov 2010 22:51:54 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTP id 747F8270002; Fri, 12 Nov 2010 22:51:53 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , Gabor Juhos Subject: [RFC 18/18] MIPS: ath79: add common WMAC device for AR913X based boards Date: Fri, 12 Nov 2010 22:51:24 +0100 Message-Id: <1289598684-30624-19-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> X-VBMS: A122C3B3269 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28384 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Add common platform_device and helper code to make the registration of the built-in wireless MAC easier on the Atheros AR9130/AR9132 based boards. Also register the WMA controller on the AR81 board. Signed-off-by: Gabor Juhos --- arch/mips/ath79/Kconfig | 4 ++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-ar913x-wmac.c | 60 ++++++++++++++++++++++++ arch/mips/ath79/dev-ar913x-wmac.h | 17 +++++++ arch/mips/ath79/mach-ap81.c | 5 ++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 + 6 files changed, 90 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-ar913x-wmac.c create mode 100644 arch/mips/ath79/dev-ar913x-wmac.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 53d9b39..bcaf948 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -38,6 +38,10 @@ config SOC_AR724X config SOC_AR913X def_bool n +config ATH79_DEV_AR913X_WMAC + depends on SOC_AR913X + def_bool n + config ATH79_DEV_GPIO_BUTTONS def_bool n diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 107f1e8..6f18c0a 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -12,6 +12,7 @@ obj-y := prom.o setup.o irq.o common.o gpio.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c new file mode 100644 index 0000000..ad2a39f --- /dev/null +++ b/arch/mips/ath79/dev-ar913x-wmac.c @@ -0,0 +1,60 @@ +/* + * Atheros AR913X SoC built-in WMAC device support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include "dev-ar913x-wmac.h" + +static struct ath9k_platform_data ar913x_wmac_data; + +static struct resource ar913x_wmac_resources[] = { + { + .start = AR913X_WMAC_BASE, + .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = ATH79_CPU_IRQ_IP2, + .end = ATH79_CPU_IRQ_IP2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ar913x_wmac_device = { + .name = "ath9k", + .id = -1, + .resource = ar913x_wmac_resources, + .num_resources = ARRAY_SIZE(ar913x_wmac_resources), + .dev = { + .platform_data = &ar913x_wmac_data, + }, +}; + +void __init ath79_register_ar913x_wmac(u8 *cal_data) +{ + if (cal_data) + memcpy(ar913x_wmac_data.eeprom_data, cal_data, + sizeof(ar913x_wmac_data.eeprom_data)); + + /* reset the WMAC */ + ath79_device_stop(AR913X_RESET_AMBA2WMAC); + mdelay(10); + + ath79_device_start(AR913X_RESET_AMBA2WMAC); + mdelay(10); + + platform_device_register(&ar913x_wmac_device); +} diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-ar913x-wmac.h new file mode 100644 index 0000000..5df653f --- /dev/null +++ b/arch/mips/ath79/dev-ar913x-wmac.h @@ -0,0 +1,17 @@ +/* + * Atheros AR913X SoC built-in WMAC device support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_AR913X_WMAC_H +#define _ATH79_DEV_AR913X_WMAC_H + +void ath79_register_ar913x_wmac(u8 *cal_data) __init; + +#endif /* _ATH79_DEV_AR913X_WMAC_H */ diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c index 9cfaff3..00ef1cd 100644 --- a/arch/mips/ath79/mach-ap81.c +++ b/arch/mips/ath79/mach-ap81.c @@ -10,6 +10,7 @@ */ #include "machtypes.h" +#include "dev-ar913x-wmac.h" #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-spi.h" @@ -24,6 +25,7 @@ #define AP81_GPIO_BTN_SW1 21 #define AP81_BUTTONS_POLL_INTERVAL 20 +#define AP81_CAL_DATA_ADDR 0x1fff1000 static struct gpio_led ap81_leds_gpio[] __initdata = { { @@ -79,6 +81,8 @@ static struct ath79_spi_platform_data ap81_spi_data = { static void __init ap81_setup(void) { + u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), ap81_leds_gpio); ath79_register_gpio_buttons(-1, AP81_BUTTONS_POLL_INTERVAL, @@ -87,6 +91,7 @@ static void __init ap81_setup(void) ath79_register_spi(&ap81_spi_data, ap81_spi_info, ARRAY_SIZE(ap81_spi_info)); ath79_register_usb(); + ath79_register_ar913x_wmac(cal_data); } MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 95be423..e8b0e2f 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -43,6 +43,9 @@ #define AR7240_OHCI_BASE 0x1b000000 #define AR7240_OHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + /* * DDR_CTRL block */ -- 1.7.2.1 From mcgrof@gmail.com Fri Nov 12 23:01:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2010 23:01:32 +0100 (CET) Received: from mail-gw0-f49.google.com ([74.125.83.49]:52880 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492173Ab0KLWB0 convert rfc822-to-8bit (ORCPT ); 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Fri, 12 Nov 2010 14:01:19 -0800 (PST) MIME-Version: 1.0 Received: by 10.231.174.209 with HTTP; Fri, 12 Nov 2010 14:00:56 -0800 (PST) In-Reply-To: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> From: "Luis R. Rodriguez" Date: Fri, 12 Nov 2010 14:00:56 -0800 Message-ID: Subject: Re: [RFC 00/18] MIPS: initial support for the Atheros AR71XX/AR724X/AR913X SoCs To: Gabor Juhos Cc: Ralf Baechle , linux-mips@linux-mips.org, Cliff Holden , Imre Kaloz Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28385 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcgrof@gmail.com Precedence: bulk X-list: linux-mips On Fri, Nov 12, 2010 at 1:51 PM, Gabor Juhos wrote: > This patch set contains initial support for the > Atheros AR71XX/AR724X/AR913X SoCs. > > Gabor Juhos (18): >  MIPS: add initial support for the Atheros AR71XX/AR724X/AR931X SoCs >  MIPS: ath79: add GPIOLIB support >  MIPS: add generic support for multiple machines within a single kernel >  MIPS: ath79: utilize the MIPS multi-machine support >  MIPS: ath79: add initial support for the Atheros PB44 reference board >  MIPS: ath79: add common GPIO LEDs device >  watchdog: add driver for the Atheros AR71XX/AR724X/AR913X SoCs >  MIPS: ath79: add common watchdog device >  input: add input driver for polled GPIO buttons >  MIPS: ath79: add common GPIO buttons device >  spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs >  MIPS: ath79: add common SPI controller device >  USB: ehci: add workaround for Synopsys HC bug >  USB: ehci: add bus glue for the Atheros AR71XX/AR724X/AR913X SoCs >  USB: ohci: add bus glue for the Atheros AR71XX/AR7240 SoCs >  MIPS: ath79: add common USB Host Controller device >  MIPS: ath79: add initial support for the Atheros AP81 reference board >  MIPS: ath79: add common WMAC device for AR913X based boards Awesome, thanks a lot! Luis From sshtylyov@mvista.com Sat Nov 13 12:48:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 13 Nov 2010 12:48:22 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:61244 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491054Ab0KMLsQ (ORCPT ); Sat, 13 Nov 2010 12:48:16 +0100 Received: by ewy19 with SMTP id 19so2269057ewy.36 for ; Sat, 13 Nov 2010 03:48:14 -0800 (PST) Received: by 10.213.7.65 with SMTP id c1mr3058931ebc.26.1289648894679; Sat, 13 Nov 2010 03:48:14 -0800 (PST) Received: from [192.168.2.2] ([91.79.89.47]) by mx.google.com with ESMTPS id v56sm4294731eeh.20.2010.11.13.03.48.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 13 Nov 2010 03:48:13 -0800 (PST) Message-ID: <4CDE7A92.8040602@mvista.com> Date: Sat, 13 Nov 2010 14:46:26 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz Subject: Re: [RFC 05/18] MIPS: ath79: add initial support for the Atheros PB44 reference board References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-6-git-send-email-juhosg@openwrt.org> In-Reply-To: <1289598684-30624-6-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28386 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 13-11-2010 0:51, Gabor Juhos wrote: > Signed-off-by: Gabor Juhos [...] > diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig > index 32e2658..47a8af4 100644 > --- a/arch/mips/ath79/Kconfig > +++ b/arch/mips/ath79/Kconfig > @@ -1,5 +1,17 @@ > if ATH79 > > +menu "Atheros AR71XX/AR724X/AR913X machine selection" > + > +config ATH79_MACH_PB44 > + bool "Atheros PB44 reference board" > + select SOC_AR71XX > + default n That "default n" is assumed, so there's no need to specify it. WBR, Sergei From sshtylyov@mvista.com Sat Nov 13 12:54:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 13 Nov 2010 12:55:04 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:60458 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491104Ab0KMLy6 (ORCPT ); Sat, 13 Nov 2010 12:54:58 +0100 Received: by ewy19 with SMTP id 19so2270093ewy.36 for ; Sat, 13 Nov 2010 03:54:58 -0800 (PST) Received: by 10.14.119.205 with SMTP id n53mr2281843eeh.37.1289649298203; Sat, 13 Nov 2010 03:54:58 -0800 (PST) Received: from [192.168.2.2] ([91.79.89.47]) by mx.google.com with ESMTPS id b52sm4302239eei.7.2010.11.13.03.54.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 13 Nov 2010 03:54:57 -0800 (PST) Message-ID: <4CDE7C25.4080204@mvista.com> Date: Sat, 13 Nov 2010 14:53:09 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Gabor Juhos CC: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz Subject: Re: [RFC 08/18] MIPS: ath79: add common watchdog device References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-9-git-send-email-juhosg@openwrt.org> In-Reply-To: <1289598684-30624-9-git-send-email-juhosg@openwrt.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28387 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 13-11-2010 0:51, Gabor Juhos wrote: > All supported SoCs have a built-in hardware watchdog driver. This patch > registers a platform_device for that to make it usable. > Signed-off-by: Gabor Juhos > Signed-off-by: Imre Kaloz [...] > diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig > index 2bd35ef..79bb528 100644 > --- a/arch/mips/ath79/Kconfig > +++ b/arch/mips/ath79/Kconfig > @@ -28,4 +28,7 @@ config ATH79_DEV_LEDS_GPIO > config ATH79_DEV_UART > def_bool y > > +config ATH79_DEV_WDT > + def_bool y What's the point of introducing this? > diff --git a/arch/mips/ath79/dev-wdt.c b/arch/mips/ath79/dev-wdt.c > new file mode 100644 > index 0000000..ba6b8bd > --- /dev/null > +++ b/arch/mips/ath79/dev-wdt.c > @@ -0,0 +1,30 @@ > +/* > + * Atheros AR71XX/AR724X/AR913X watchdog device > + * > + * Copyright (C) 2008-2010 Gabor Juhos > + * Copyright (C) 2008 Imre Kaloz > + * > + * Parts of this file are based on Atheros' 2.6.15 BSP > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > + > +#include > +#include "common.h" > +#include "dev-wdt.h" > + > +static struct platform_device ath79_wdt_device = { > + .name = "ath79-wdt", > + .id = -1, > +}; > + > +void __init ath79_register_wdt(void) > +{ > + platform_device_register(&ath79_wdt_device); > +} I'm not sure creating a separate file for the WDT platfrom device is really worth it... > diff --git a/arch/mips/ath79/dev-wdt.h b/arch/mips/ath79/dev-wdt.h > new file mode 100644 > index 0000000..2546415 > --- /dev/null > +++ b/arch/mips/ath79/dev-wdt.h > @@ -0,0 +1,17 @@ > +/* > + * Atheros AR71XX/AR724X/AR913X watchdog device > + * > + * Copyright (C) 2008-2010 Gabor Juhos > + * Copyright (C) 2008 Imre Kaloz > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > +#ifndef _ATH_DEV_WDT_H > +#define _ATH_DEV_WDT_H > + > +void ath79_register_wdt(void) __init; > + > +#endif I think this should better be put into some more common header... > diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c > index b36f9f2..693a9e6 100644 > --- a/arch/mips/ath79/setup.c > +++ b/arch/mips/ath79/setup.c > @@ -24,6 +24,7 @@ > #include > #include "common.h" > #include "dev-uart.h" > +#include "dev-wdt.h" > #include "machtypes.h" > > #define ATH79_SYS_TYPE_LEN 64 > @@ -259,6 +260,7 @@ static int __init ath79_setup(void) > { > ath79_gpio_init(); > ath79_register_uart(); > + ath79_register_wdt(); Now what if CONFIG_ATH79_DEV_WDT is not enabled? You'll siply get a linker error. I think you should define an empty inline ath79_register_wdt() in that case. WBR, Sergei From glikely@secretlab.ca Sun Nov 14 09:22:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2010 09:23:00 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:51238 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491064Ab0KNIWz (ORCPT ); Sun, 14 Nov 2010 09:22:55 +0100 Received: by pwj8 with SMTP id 8so986465pwj.36 for ; Sun, 14 Nov 2010 00:22:46 -0800 (PST) Received: by 10.142.162.21 with SMTP id k21mr3373695wfe.412.1289722965464; Sun, 14 Nov 2010 00:22:45 -0800 (PST) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id w42sm6831648wfh.15.2010.11.14.00.22.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 14 Nov 2010 00:22:44 -0800 (PST) Received: by angua (Postfix, from userid 1000) id D261D3C00E5; Sun, 14 Nov 2010 01:22:42 -0700 (MST) Date: Sun, 14 Nov 2010 01:22:42 -0700 From: Grant Likely To: Gabor Juhos Cc: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , David Brownell , spi-devel-general@lists.sourceforge.net, Imre Kaloz Subject: Re: [RFC 11/18] spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs Message-ID: <20101114082242.GA3137@angua.secretlab.ca> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-12-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1289598684-30624-12-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28388 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Fri, Nov 12, 2010 at 10:51:17PM +0100, Gabor Juhos wrote: > The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This > patch implements a driver for that. > > Signed-off-by: Gabor Juhos > Cc: David Brownell > Cc: spi-devel-general@lists.sourceforge.net Hi Gabor, Overall looks pretty good, but a few questions below. g. > --- > Sorry for sending this twice, i forgot to add some CCs in the first round. > > .../include/asm/mach-ath79/ath79_spi_platform.h | 19 ++ > drivers/spi/Kconfig | 8 + > drivers/spi/Makefile | 1 + > drivers/spi/ath79_spi.c | 291 ++++++++++++++++++++ > 4 files changed, 319 insertions(+), 0 deletions(-) > create mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h > create mode 100644 drivers/spi/ath79_spi.c > > diff --git a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h > new file mode 100644 > index 0000000..aa71216 > --- /dev/null > +++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h > @@ -0,0 +1,19 @@ > +/* > + * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller > + * > + * Copyright (C) 2008-2010 Gabor Juhos > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > +#ifndef _ATH79_SPI_PLATFORM_H > +#define _ATH79_SPI_PLATFORM_H > + > +struct ath79_spi_platform_data { > + unsigned bus_num; > + unsigned num_chipselect; > +}; > + > +#endif /* _ATH79_SPI_PLATFORM_H */ > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 78f9fd0..f2093e1 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -53,6 +53,14 @@ if SPI_MASTER > > comment "SPI Master Controller Drivers" > > +config SPI_ATH79 > + tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver" > + depends on ATH79 && GENERIC_GPIO > + select SPI_BITBANG > + help > + This enables support for the SPI controller present on the > + Atheros AR71XX/AR724X/AR913X SoCs. > + > config SPI_ATMEL > tristate "Atmel SPI Controller" > depends on (ARCH_AT91 || AVR32) > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 8bc1a5a..875bc3d 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_SPI_MASTER) += spi.o > > # SPI master controller drivers (bus) > obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o > +obj-$(CONFIG_SPI_ATH79) += ath79_spi.o > obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o > obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o > obj-$(CONFIG_SPI_AU1550) += au1550_spi.o > diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c > new file mode 100644 > index 0000000..9b9f9cf > --- /dev/null > +++ b/drivers/spi/ath79_spi.c > @@ -0,0 +1,291 @@ > +/* > + * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs > + * > + * Copyright (C) 2009-2010 Gabor Juhos > + * > + * This driver has been based on the spi-gpio.c: > + * Copyright (C) 2006,2008 David Brownell > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +#define DRV_DESC "SPI controller driver for Atheros AR71XX/AR724X/AR91X" Used exactly once. Don't bother with a #define > +#define DRV_NAME "ath79-spi" > + > +struct ath79_spi { > + struct spi_bitbang bitbang; > + u32 ioc_base; > + u32 reg_ctrl; > + > + void __iomem *base; > + > + struct platform_device *pdev; > +}; > + > +static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) > +{ > + return __raw_readl(sp->base + reg); > +} > + > +static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) > +{ > + __raw_writel(val, sp->base + reg); > +} This is suspect. Why is __raw_{readl,writel} being used instead of ioread32/iowrite32? The __raw versions don't provide any kind of ordering barriers. > + > +static inline struct ath79_spi *spidev_to_sp(struct spi_device *spi) > +{ > + return spi_master_get_devdata(spi->master); > +} > + > +static void ath79_spi_chipselect(struct spi_device *spi, int is_active) > +{ > + struct ath79_spi *sp = spidev_to_sp(spi); > + int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; > + > + if (is_active) { > + /* set initial clock polarity */ > + if (spi->mode & SPI_CPOL) > + sp->ioc_base |= AR71XX_SPI_IOC_CLK; > + else > + sp->ioc_base &= ~AR71XX_SPI_IOC_CLK; > + > + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); > + } > + > + if (spi->chip_select) { > + unsigned long gpio = (unsigned long) spi->controller_data; > + > + /* SPI is normally active-low */ > + gpio_set_value(gpio, cs_high); > + } else { > + if (cs_high) > + sp->ioc_base |= AR71XX_SPI_IOC_CS0; > + else > + sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; > + > + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); > + } > + > +} > + > +static int ath79_spi_setup_cs(struct spi_device *spi) > +{ > + struct ath79_spi *sp = spidev_to_sp(spi); > + > + /* enable GPIO mode */ > + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); > + > + /* save CTRL register */ > + sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); > + sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); > + > + /* TODO: setup speed? */ > + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); > + > + if (spi->chip_select) { > + unsigned long gpio = (unsigned long) spi->controller_data; > + int status = 0; > + > + status = gpio_request(gpio, dev_name(&spi->dev)); > + if (status) > + return status; > + > + status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); > + if (status) { > + gpio_free(gpio); > + return status; > + } > + } else { > + if (spi->mode & SPI_CS_HIGH) > + sp->ioc_base |= AR71XX_SPI_IOC_CS0; > + else > + sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; > + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); > + } > + > + return 0; > +} > + > +static void ath79_spi_cleanup_cs(struct spi_device *spi) > +{ > + struct ath79_spi *sp = spidev_to_sp(spi); > + > + if (spi->chip_select) { > + unsigned long gpio = (unsigned long) spi->controller_data; > + gpio_free(gpio); > + } > + > + /* restore CTRL register */ > + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); > + /* disable GPIO mode */ > + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); > +} > + > +static int ath79_spi_setup(struct spi_device *spi) > +{ > + int status = 0; > + > + if (spi->bits_per_word > 32) > + return -EINVAL; > + > + if (!spi->controller_state) { > + status = ath79_spi_setup_cs(spi); > + if (status) > + return status; > + } > + > + status = spi_bitbang_setup(spi); > + if (status && !spi->controller_state) > + ath79_spi_cleanup_cs(spi); > + > + return status; > +} > + > +static void ath79_spi_cleanup(struct spi_device *spi) > +{ > + ath79_spi_cleanup_cs(spi); > + spi_bitbang_cleanup(spi); > +} > + > +static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, > + u32 word, u8 bits) > +{ > + struct ath79_spi *sp = spidev_to_sp(spi); > + u32 ioc = sp->ioc_base; > + > + /* clock starts at inactive polarity */ > + for (word <<= (32 - bits); likely(bits); bits--) { > + u32 out; > + > + if (word & (1 << 31)) > + out = ioc | AR71XX_SPI_IOC_DO; > + else > + out = ioc & ~AR71XX_SPI_IOC_DO; > + > + /* setup MSB (to slave) on trailing edge */ > + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); > + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); > + > + word <<= 1; > + } > + > + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); > +} > + > +static int ath79_spi_probe(struct platform_device *pdev) __devinit > +{ > + struct spi_master *master; > + struct ath79_spi *sp; > + struct ath79_spi_platform_data *pdata; > + struct resource *r; > + int ret; > + > + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); > + if (master == NULL) { > + dev_err(&pdev->dev, "failed to allocate spi master\n"); > + return -ENOMEM; > + } > + > + sp = spi_master_get_devdata(master); > + platform_set_drvdata(pdev, sp); > + > + pdata = pdev->dev.platform_data; > + > + master->setup = ath79_spi_setup; > + master->cleanup = ath79_spi_cleanup; > + if (pdata) { > + master->bus_num = pdata->bus_num; > + master->num_chipselect = pdata->num_chipselect; > + } else { > + master->bus_num = 0; Use -1 so that a bus number can be dynamically assigned. > + master->num_chipselect = 1; > + } > + > + sp->bitbang.master = spi_master_get(master); > + sp->bitbang.chipselect = ath79_spi_chipselect; > + sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; > + sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; > + sp->bitbang.flags = SPI_CS_HIGH; > + > + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (r == NULL) { > + ret = -ENOENT; > + goto err_put_master; > + } > + > + sp->base = ioremap(r->start, r->end - r->start + 1); > + if (!sp->base) { > + ret = -ENXIO; > + goto err_put_master; > + } > + > + ret = spi_bitbang_start(&sp->bitbang); > + if (ret) > + goto err_unmap; > + > + return 0; > + > +err_unmap: > + iounmap(sp->base); > +err_put_master: > + platform_set_drvdata(pdev, NULL); > + spi_master_put(sp->bitbang.master); > + > + return ret; > +} > + > +static int ath79_spi_remove(struct platform_device *pdev) __devexit > +{ > + struct ath79_spi *sp = platform_get_drvdata(pdev); > + > + spi_bitbang_stop(&sp->bitbang); > + iounmap(sp->base); > + platform_set_drvdata(pdev, NULL); > + spi_master_put(sp->bitbang.master); > + > + return 0; > +} > + > +static struct platform_driver ath79_spi_drv = { > + .probe = ath79_spi_probe, > + .remove = ath79_spi_remove, __devexit_p(ath79_spi_remove), > + .driver = { > + .name = DRV_NAME, > + .owner = THIS_MODULE, > + }, > +}; > + > +static int __init ath79_spi_init(void) > +{ > + return platform_driver_register(&ath79_spi_drv); > +} > +module_init(ath79_spi_init); > + > +static void __exit ath79_spi_exit(void) > +{ > + platform_driver_unregister(&ath79_spi_drv); > +} > +module_exit(ath79_spi_exit); > + > +MODULE_DESCRIPTION(DRV_DESC); > +MODULE_AUTHOR("Gabor Juhos "); > +MODULE_LICENSE("GPL v2"); > +MODULE_ALIAS("platform:" DRV_NAME); > -- > 1.7.2.1 > > > ------------------------------------------------------------------------------ > Centralized Desktop Delivery: Dell and VMware Reference Architecture > Simplifying enterprise desktop deployment and management using > Dell EqualLogic storage and VMware View: A highly scalable, end-to-end > client virtualization framework. Read more! > http://p.sf.net/sfu/dell-eql-dev2dev > _______________________________________________ > spi-devel-general mailing list > spi-devel-general@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/spi-devel-general From juhosg@openwrt.org Sun Nov 14 18:41:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2010 18:41:46 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:41423 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491919Ab0KNRl1 (ORCPT ); Sun, 14 Nov 2010 18:41:27 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 833833FC040; Sun, 14 Nov 2010 18:41:18 +0100 (CET) Received: from [192.168.254.10] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id E08221F0001; Sun, 14 Nov 2010 18:41:17 +0100 (CET) Message-ID: <4CE01F3D.8070308@openwrt.org> Date: Sun, 14 Nov 2010 18:41:17 +0100 From: Gabor Juhos User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; hu-HU; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz Subject: Re: [RFC 08/18] MIPS: ath79: add common watchdog device References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-9-git-send-email-juhosg@openwrt.org> <4CDE7C25.4080204@mvista.com> In-Reply-To: <4CDE7C25.4080204@mvista.com> X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-VBMS: A17DE314353 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28389 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Hi Sergei, > On 13-11-2010 0:51, Gabor Juhos wrote: > >> All supported SoCs have a built-in hardware watchdog driver. This patch >> registers a platform_device for that to make it usable. > >> Signed-off-by: Gabor Juhos >> Signed-off-by: Imre Kaloz > [...] > >> diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig >> index 2bd35ef..79bb528 100644 >> --- a/arch/mips/ath79/Kconfig >> +++ b/arch/mips/ath79/Kconfig >> @@ -28,4 +28,7 @@ config ATH79_DEV_LEDS_GPIO >> config ATH79_DEV_UART >> def_bool y >> >> +config ATH79_DEV_WDT >> + def_bool y > > What's the point of introducing this? My first thought was that it will be selectable by the board specific config options. Because the watchdog timer is integrated into the SoC it will be available on all boards anyway. I will remove the ATH79_DEV_UART and ATH79_DEV_WDT config options and will change the Makefile accordingly. >> <...> >> +void __init ath79_register_wdt(void) >> +{ >> + platform_device_register(&ath79_wdt_device); >> +} > > I'm not sure creating a separate file for the WDT platfrom device is really > worth it... You are right probably. Because it is always used, it can be moved into a common file instead. I will do that. >> <..> >> +#ifndef _ATH_DEV_WDT_H >> +#define _ATH_DEV_WDT_H >> + >> +void ath79_register_wdt(void) __init; >> + >> +#endif > > I think this should better be put into some more common header... Yes, i will move this too. >> <...> >> @@ -259,6 +260,7 @@ static int __init ath79_setup(void) >> { >> ath79_gpio_init(); >> ath79_register_uart(); >> + ath79_register_wdt(); > > Now what if CONFIG_ATH79_DEV_WDT is not enabled? You'll siply get a linker > error. Correct. > I think you should define an empty inline ath79_register_wdt() in that case. This won't be needed after the changes proposed above. Thank you, Gabor From juhosg@openwrt.org Sun Nov 14 18:42:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2010 18:42:12 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:41432 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491921Ab0KNRlt (ORCPT ); Sun, 14 Nov 2010 18:41:49 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 21F8E3FC018; Sun, 14 Nov 2010 18:41:44 +0100 (CET) Received: from [192.168.254.10] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 878C91F0001; Sun, 14 Nov 2010 18:41:43 +0100 (CET) Message-ID: <4CE01F56.8090304@openwrt.org> Date: Sun, 14 Nov 2010 18:41:42 +0100 From: Gabor Juhos User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; hu-HU; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Sergei Shtylyov CC: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz Subject: Re: [RFC 05/18] MIPS: ath79: add initial support for the Atheros PB44 reference board References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-6-git-send-email-juhosg@openwrt.org> <4CDE7A92.8040602@mvista.com> In-Reply-To: <4CDE7A92.8040602@mvista.com> X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-VBMS: A17E12B3A37 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Hi Sergei, > Hello. > > On 13-11-2010 0:51, Gabor Juhos wrote: > >> Signed-off-by: Gabor Juhos > [...] > >> diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig >> index 32e2658..47a8af4 100644 >> --- a/arch/mips/ath79/Kconfig >> +++ b/arch/mips/ath79/Kconfig >> @@ -1,5 +1,17 @@ >> if ATH79 >> >> +menu "Atheros AR71XX/AR724X/AR913X machine selection" >> + >> +config ATH79_MACH_PB44 >> + bool "Atheros PB44 reference board" >> + select SOC_AR71XX >> + default n > > That "default n" is assumed, so there's no need to specify it. Ok. I will remove that. Thank you, Gabor From juhosg@openwrt.org Sun Nov 14 22:04:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2010 22:04:11 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:44657 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491923Ab0KNVEI (ORCPT ); Sun, 14 Nov 2010 22:04:08 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id AE1D745C002; Sun, 14 Nov 2010 22:04:01 +0100 (CET) Received: from [192.168.254.10] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 0E04A1F0003; Sun, 14 Nov 2010 22:03:58 +0100 (CET) Message-ID: <4CE04EBC.4080701@openwrt.org> Date: Sun, 14 Nov 2010 22:03:56 +0100 From: Gabor Juhos User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; hu-HU; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Grant Likely CC: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , David Brownell , spi-devel-general@lists.sourceforge.net, Imre Kaloz Subject: Re: [RFC 11/18] spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-12-git-send-email-juhosg@openwrt.org> <20101114082242.GA3137@angua.secretlab.ca> In-Reply-To: <20101114082242.GA3137@angua.secretlab.ca> X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-VBMS: A112754AD59 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Hi Grant, >> <...> >> +#include >> + >> +#define DRV_DESC "SPI controller driver for Atheros AR71XX/AR724X/AR91X" > > Used exactly once. Don't bother with a #define Ok. >> +#define DRV_NAME "ath79-spi" >> + >> +struct ath79_spi { >> + struct spi_bitbang bitbang; >> + u32 ioc_base; >> + u32 reg_ctrl; >> + >> + void __iomem *base; >> + >> + struct platform_device *pdev; >> +}; >> + >> +static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) >> +{ >> + return __raw_readl(sp->base + reg); >> +} >> + >> +static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) >> +{ >> + __raw_writel(val, sp->base + reg); >> +} > > This is suspect. Why is __raw_{readl,writel} being used instead of > ioread32/iowrite32? The __raw versions don't provide any kind of > ordering barriers. Mainly because the resulting code is smaller, and the performance is a bit better with the use of the __raw versions. The controller is embedded into the SoC and the registers are memory mapped, so i think it is safe to access them with __raw_{readl,writel}. However I can change it if that is the preferred method. >> <...> >> +static int ath79_spi_probe(struct platform_device *pdev) > > __devinit I will add this. > >> +{ >> + struct spi_master *master; >> + struct ath79_spi *sp; >> + struct ath79_spi_platform_data *pdata; >> + struct resource *r; >> + int ret; >> + >> + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); >> + if (master == NULL) { >> + dev_err(&pdev->dev, "failed to allocate spi master\n"); >> + return -ENOMEM; >> + } >> + >> + sp = spi_master_get_devdata(master); >> + platform_set_drvdata(pdev, sp); >> + >> + pdata = pdev->dev.platform_data; >> + >> + master->setup = ath79_spi_setup; >> + master->cleanup = ath79_spi_cleanup; >> + if (pdata) { >> + master->bus_num = pdata->bus_num; >> + master->num_chipselect = pdata->num_chipselect; >> + } else { >> + master->bus_num = 0; > > Use -1 so that a bus number can be dynamically assigned All right. >> <...> >> +static int ath79_spi_remove(struct platform_device *pdev) > > __devexit > >> +{ >> + struct ath79_spi *sp = platform_get_drvdata(pdev); >> + >> + spi_bitbang_stop(&sp->bitbang); >> + iounmap(sp->base); >> + platform_set_drvdata(pdev, NULL); >> + spi_master_put(sp->bitbang.master); >> + >> + return 0; >> +} >> + >> +static struct platform_driver ath79_spi_drv = { >> + .probe = ath79_spi_probe, >> + .remove = ath79_spi_remove, > > __devexit_p(ath79_spi_remove), > I will add these annotations as well. Thank you, Gabor From glikely@secretlab.ca Mon Nov 15 05:05:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 05:05:09 +0100 (CET) Received: from mail-gw0-f49.google.com ([74.125.83.49]:36907 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490969Ab0KOEFG (ORCPT ); Mon, 15 Nov 2010 05:05:06 +0100 Received: by gwb11 with SMTP id 11so923454gwb.36 for ; Sun, 14 Nov 2010 20:05:00 -0800 (PST) Received: by 10.151.39.4 with SMTP id r4mr2498996ybj.135.1289793899718; Sun, 14 Nov 2010 20:04:59 -0800 (PST) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id n48sm4304477yha.7.2010.11.14.20.04.57 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 14 Nov 2010 20:04:59 -0800 (PST) Received: by angua (Postfix, from userid 1000) id 2F43B3C00E5; Sun, 14 Nov 2010 21:04:56 -0700 (MST) Date: Sun, 14 Nov 2010 21:04:56 -0700 From: Grant Likely To: Gabor Juhos Cc: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , David Brownell , spi-devel-general@lists.sourceforge.net, Imre Kaloz Subject: Re: [RFC 11/18] spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs Message-ID: <20101115040456.GB19965@angua.secretlab.ca> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-12-git-send-email-juhosg@openwrt.org> <20101114082242.GA3137@angua.secretlab.ca> <4CE04EBC.4080701@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4CE04EBC.4080701@openwrt.org> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Sun, Nov 14, 2010 at 10:03:56PM +0100, Gabor Juhos wrote: > >> +static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) > >> +{ > >> + return __raw_readl(sp->base + reg); > >> +} > >> + > >> +static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) > >> +{ > >> + __raw_writel(val, sp->base + reg); > >> +} > > > > This is suspect. Why is __raw_{readl,writel} being used instead of > > ioread32/iowrite32? The __raw versions don't provide any kind of > > ordering barriers. > > Mainly because the resulting code is smaller, and the performance is a bit > better with the use of the __raw versions. The controller is embedded into the > SoC and the registers are memory mapped, so i think it is safe to access them > with __raw_{readl,writel}. However I can change it if that is the preferred method. > Smaller, yes, because it doesn't have any io barriers; but is it safe? Do you know whether or not the CPU will reorder the instructions on you? Being embedded into the SoC doesn't really mean anything in this regard. Unless you really understand all the behaviour of the CPU and bus, then the safe versions must be used. If you *do* really understand all the behaviour and decide it is safe to use the __raw versions, then the driver needs to be well documented as to the reasons why the __raw versions are safe to use. g. From mattst88@gmail.com Mon Nov 15 05:53:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 05:53:06 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:48030 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491042Ab0KOExA (ORCPT ); Mon, 15 Nov 2010 05:53:00 +0100 Received: by ywf7 with SMTP id 7so1814926ywf.36 for ; Sun, 14 Nov 2010 20:52:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:from:to:cc:subject :date:message-id:x-mailer; bh=7XuCggeZ/PbTrcbSRl9lE4StecQcW4x+jDJBvWpAbTA=; b=iZd8NSj27210vGEnk5biTtf/YaPssi4oGWOwQ0OwhnDwSLvh6aYiNSjjJHsS3ZL/H5 QclEjgKA0FFcsYI6M137Koc1YWEtUp2U2Cq7dq9KOKrefyR5hlo2LGHhrGBX0Bbkq4kr r/G7xlI1PFdqH3GvtEsx5RR3Cr/K5aYuzkbO8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=L0v5ycmREtZwxUfJVQvnWNetgL/ZIT6HnSAjP+tabYeI+WtP9GtelgphjMewXi5Yh8 FxWhZjjabDaSrO8X+eSYUmZJKr1fC/1xHkiYcpYoqkuEIRw9j70eA52opVnhZ9uSdZtd BLRiZkW3phwxaOsf8DcFVJbMbuKsIjKrBen0o= Received: by 10.100.137.7 with SMTP id k7mr3955147and.248.1289796773306; Sun, 14 Nov 2010 20:52:53 -0800 (PST) Received: from mattst88@gmail.com (cpe-065-190-173-137.nc.res.rr.com [65.190.173.137]) by mx.google.com with ESMTPS id w15sm3328488anw.33.2010.11.14.20.52.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 14 Nov 2010 20:52:52 -0800 (PST) Received: by mattst88@gmail.com (sSMTP sendmail emulation); Sun, 14 Nov 2010 23:54:17 -0500 From: Matt Turner To: linux-mips@linux-mips.org Cc: Ralf Baechle , "Maciej W. Rozycki" , kaloz@openwrt.org, Mark Zhan Subject: MIPS: RTC and hwmon for SWARM Date: Sun, 14 Nov 2010 23:53:46 -0500 Message-Id: <1289796829-29222-1-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.2.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Hi Ralf, Following are three patches that enable hwmon and rtc on SWARM. They were found [1] where there are two more as well. I've said that Maciej is the author, because [2], but I also see [3]. There's a pretty extensive commit message in [2] that I haven't included so maybe Maciej would like to comment on this patch. The first patch probably needs to go through the RTC tree anyway, but I wasn't sure if it was needed for the subsequent patches. I've tested these patches on my SWARM and they work fine. Thanks, Matt [1] https://dev.openwrt.org/browser/trunk/target/linux/sibyte/patches/ [2] http://lkml.org/lkml/2008/5/12/391 [3] http://lists.lm-sensors.org/pipermail/i2c/2007-September/001907.html From mattst88@gmail.com Mon Nov 15 05:53:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 05:53:32 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:48030 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0KOExC (ORCPT ); Mon, 15 Nov 2010 05:53:02 +0100 Received: by mail-yw0-f49.google.com with SMTP id 7so1814926ywf.36 for ; Sun, 14 Nov 2010 20:53:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:from:to:cc:subject :date:message-id:x-mailer:in-reply-to:references; bh=60LB/r9UeBf+SbYNRj9ky1sUG+z8kctbw9XCzlX185g=; b=nCYZECyfTmPIoKU5+GWYS7b2efhHS9Mxc7B736NQ/jwwuZ0n+DZF5RTpoAHf/QmCpo 4AYkrRtQTagUAnkQC22l4G4NkFX72cZQh3yarq90pJxO+0vV4ngsRZmdqMGgqvJXgnH7 m0lhrUqYz1fwwfaihghQqBESbxnl+M/EpS0i8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=QIku80ml04BxF9haoDw9TvHwMo0VOl72plowo9DjpyPUucW0Kn6OhlgjPvXcaz2evz 2W0slx8BdM8k80OyoMoOR03XRO9ud5MB02xlSdDUQLqocKwfPKvKm5xUMrRmstzL+LBc o8RR35cqBQiSaVwCu8NwKZqSiNjfgr0gbhJDA= Received: by 10.151.45.20 with SMTP id x20mr8674886ybj.231.1289796780755; Sun, 14 Nov 2010 20:53:00 -0800 (PST) Received: from mattst88@gmail.com (cpe-065-190-173-137.nc.res.rr.com [65.190.173.137]) by mx.google.com with ESMTPS id v9sm2685083ybe.21.2010.11.14.20.52.58 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 14 Nov 2010 20:53:00 -0800 (PST) Received: by mattst88@gmail.com (sSMTP sendmail emulation); Sun, 14 Nov 2010 23:54:25 -0500 From: Matt Turner To: linux-mips@linux-mips.org Cc: Ralf Baechle , "Maciej W. Rozycki" , kaloz@openwrt.org, Mark Zhan , Matt Turner Subject: [PATCH 1/3] RTC: SMBus support for the M41T80 Date: Sun, 14 Nov 2010 23:53:47 -0500 Message-Id: <1289796829-29222-2-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1289796829-29222-1-git-send-email-mattst88@gmail.com> References: <1289796829-29222-1-git-send-email-mattst88@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips From: Maciej W. Rozycki Tested-by: Matt Turner Signed-off-by: Matt Turner --- drivers/rtc/rtc-m41t80.c | 251 ++++++++++++++++++++-------------------------- 1 files changed, 107 insertions(+), 144 deletions(-) diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c index 5a8daa3..2233ed5 100644 --- a/drivers/rtc/rtc-m41t80.c +++ b/drivers/rtc/rtc-m41t80.c @@ -6,6 +6,7 @@ * Based on m41t00.c by Mark A. Greer * * 2006 (c) mycable GmbH + * Copyright (c) 2008 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -38,6 +39,8 @@ #define M41T80_REG_DAY 5 #define M41T80_REG_MON 6 #define M41T80_REG_YEAR 7 +#define M41T80_REG_CONTROL 8 +#define M41T80_REG_WATCHDOG 9 #define M41T80_REG_ALARM_MON 0xa #define M41T80_REG_ALARM_DAY 0xb #define M41T80_REG_ALARM_HOUR 0xc @@ -66,7 +69,7 @@ #define M41T80_FEATURE_WD (1 << 3) /* Extra watchdog resolution */ #define M41T80_FEATURE_SQ_ALT (1 << 4) /* RSx bits are in reg 4 */ -#define DRV_VERSION "0.05" +#define DRV_VERSION "0.06" static DEFINE_MUTEX(m41t80_rtc_mutex); static const struct i2c_device_id m41t80_id[] = { @@ -89,31 +92,89 @@ struct m41t80_data { struct rtc_device *rtc; }; -static int m41t80_get_datetime(struct i2c_client *client, - struct rtc_time *tm) + +static int m41t80_write_block_data(struct i2c_client *client, + u8 reg, u8 num, u8 *buf) { - u8 buf[M41T80_DATETIME_REG_SIZE], dt_addr[1] = { M41T80_REG_SEC }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, - .buf = buf + M41T80_REG_SEC, - }, - }; + int i, rc; + + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) { + i = i2c_smbus_write_i2c_block_data(client, reg, num, buf); + } else { + for (i = 0; i < num; i++) { + rc = i2c_smbus_write_byte_data(client, reg + i, + buf[i]); + if (rc < 0) { + i = rc; + goto out; + } + } + } +out: + return i; +} - if (i2c_transfer(client->adapter, msgs, 2) < 0) { - dev_err(&client->dev, "read error\n"); - return -EIO; +static int m41t80_read_block_data(struct i2c_client *client, + u8 reg, u8 num, u8 *buf) +{ + int i, rc; + + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + i = i2c_smbus_read_i2c_block_data(client, reg, num, buf); + } else { + for (i = 0; i < num; i++) { + rc = i2c_smbus_read_byte_data(client, reg + i); + if (rc < 0) { + i = rc; + goto out; + } + buf[i] = rc; + } } +out: + return i; +} + +static int m41t80_get_datetime(struct i2c_client *client, struct rtc_time *tm) +{ + u8 buf[M41T80_DATETIME_REG_SIZE]; + int loops = 2; + int sec0, sec1; + + /* + * Time registers are latched by this chip if an I2C block + * transfer is used, but with SMBus-style byte accesses + * this is not the case, so check seconds for a wraparound. + */ + do { + if (m41t80_read_block_data(client, M41T80_REG_SEC, + M41T80_DATETIME_REG_SIZE - + M41T80_REG_SEC, + buf + M41T80_REG_SEC) < 0) { + dev_err(&client->dev, "read error\n"); + return -EIO; + } + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + sec1 = buf[M41T80_REG_SEC]; + break; + } + + sec0 = buf[M41T80_REG_SEC]; + sec1 = i2c_smbus_read_byte_data(client, M41T80_REG_SEC); + if (sec1 < 0) { + dev_err(&client->dev, "read error\n"); + return -EIO; + } + + sec0 = bcd2bin(sec0 & 0x7f); + sec1 = bcd2bin(sec1 & 0x7f); + } while (sec1 < sec0 && --loops); - tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f); + tm->tm_sec = sec1; + tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f); tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f); @@ -128,39 +189,16 @@ static int m41t80_get_datetime(struct i2c_client *client, /* Sets the given date and time to the real time clock. */ static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm) { - u8 wbuf[1 + M41T80_DATETIME_REG_SIZE]; - u8 *buf = &wbuf[1]; - u8 dt_addr[1] = { M41T80_REG_SEC }; - struct i2c_msg msgs_in[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, - .buf = buf + M41T80_REG_SEC, - }, - }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1 + M41T80_DATETIME_REG_SIZE, - .buf = wbuf, - }, - }; + u8 buf[M41T80_DATETIME_REG_SIZE]; /* Read current reg values into buf[1..7] */ - if (i2c_transfer(client->adapter, msgs_in, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_SEC, + M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC, + buf + M41T80_REG_SEC) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } - wbuf[0] = 0; /* offset into rtc's regs */ /* Merge time-data and register flags into buf[0..7] */ buf[M41T80_REG_SSEC] = 0; buf[M41T80_REG_SEC] = @@ -177,8 +215,8 @@ static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm) bin2bcd(tm->tm_mon + 1) | (buf[M41T80_REG_MON] & ~0x1f); /* assume 20YY not 19YY */ buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year % 100); - - if (i2c_transfer(client->adapter, msgs, 1) != 1) { + if (m41t80_write_block_data(client, M41T80_REG_SSEC, + M41T80_DATETIME_REG_SIZE, buf) < 0) { dev_err(&client->dev, "write error\n"); return -EIO; } @@ -252,34 +290,11 @@ err: static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) { struct i2c_client *client = to_i2c_client(dev); - u8 wbuf[1 + M41T80_ALARM_REG_SIZE]; - u8 *buf = &wbuf[1]; + u8 buf[M41T80_ALARM_REG_SIZE]; u8 *reg = buf - M41T80_REG_ALARM_MON; - u8 dt_addr[1] = { M41T80_REG_ALARM_MON }; - struct i2c_msg msgs_in[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_ALARM_REG_SIZE, - .buf = buf, - }, - }; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1 + M41T80_ALARM_REG_SIZE, - .buf = wbuf, - }, - }; - if (i2c_transfer(client->adapter, msgs_in, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE, buf) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } @@ -289,7 +304,6 @@ static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) reg[M41T80_REG_ALARM_MIN] = 0; reg[M41T80_REG_ALARM_SEC] = 0; - wbuf[0] = M41T80_REG_ALARM_MON; /* offset into rtc's regs */ reg[M41T80_REG_ALARM_SEC] |= t->time.tm_sec >= 0 ? bin2bcd(t->time.tm_sec) : 0x80; reg[M41T80_REG_ALARM_MIN] |= t->time.tm_min >= 0 ? @@ -303,7 +317,8 @@ static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) else reg[M41T80_REG_ALARM_DAY] |= 0x40; - if (i2c_transfer(client->adapter, msgs, 1) != 1) { + if (m41t80_write_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE, buf) < 0) { dev_err(&client->dev, "write error\n"); return -EIO; } @@ -323,24 +338,10 @@ static int m41t80_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *t) { struct i2c_client *client = to_i2c_client(dev); u8 buf[M41T80_ALARM_REG_SIZE + 1]; /* all alarm regs and flags */ - u8 dt_addr[1] = { M41T80_REG_ALARM_MON }; u8 *reg = buf - M41T80_REG_ALARM_MON; - struct i2c_msg msgs[] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = dt_addr, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = M41T80_ALARM_REG_SIZE + 1, - .buf = buf, - }, - }; - if (i2c_transfer(client->adapter, msgs, 2) < 0) { + if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON, + M41T80_ALARM_REG_SIZE + 1, buf) < 0) { dev_err(&client->dev, "read error\n"); return -EIO; } @@ -513,26 +514,16 @@ static int boot_flag; */ static void wdt_ping(void) { - unsigned char i2c_data[2]; - struct i2c_msg msgs1[1] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 2, - .buf = i2c_data, - }, - }; - struct m41t80_data *clientdata = i2c_get_clientdata(save_client); + u8 wdt = 0x80; /* WDS = 1 (0x80) */ - i2c_data[0] = 0x09; /* watchdog register */ + struct m41t80_data *clientdata = i2c_get_clientdata(save_client); if (wdt_margin > 31) - i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */ + /* mulitplier = WD_TIMO / 4, resolution = 4s (0x3) */ + wdt |= (wdt_margin & 0xfc) | 0x3; else - /* - * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02) - */ - i2c_data[1] = wdt_margin<<2 | 0x82; + /* mulitplier = WD_TIMO, resolution = 1s (0x2) */ + wdt |= wdt_margin << 2 | 0x2; /* * M41T65 has three bits for watchdog resolution. Don't set bit 7, as @@ -541,7 +532,7 @@ static void wdt_ping(void) if (clientdata->features & M41T80_FEATURE_WD) i2c_data[1] &= ~M41T80_WATCHDOG_RB2; - i2c_transfer(save_client->adapter, msgs1, 1); + i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, wdt); } /** @@ -551,36 +542,8 @@ static void wdt_ping(void) */ static void wdt_disable(void) { - unsigned char i2c_data[2], i2c_buf[0x10]; - struct i2c_msg msgs0[2] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 1, - .buf = i2c_data, - }, - { - .addr = save_client->addr, - .flags = I2C_M_RD, - .len = 1, - .buf = i2c_buf, - }, - }; - struct i2c_msg msgs1[1] = { - { - .addr = save_client->addr, - .flags = 0, - .len = 2, - .buf = i2c_data, - }, - }; - - i2c_data[0] = 0x09; - i2c_transfer(save_client->adapter, msgs0, 2); - - i2c_data[0] = 0x09; - i2c_data[1] = 0x00; - i2c_transfer(save_client->adapter, msgs1, 1); + i2c_smbus_read_byte_data(save_client, M41T80_REG_WATCHDOG); + i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, 0); } /** @@ -782,8 +745,8 @@ static int m41t80_probe(struct i2c_client *client, struct rtc_time tm; struct m41t80_data *clientdata = NULL; - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C - | I2C_FUNC_SMBUS_BYTE_DATA)) { + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) { rc = -ENODEV; goto exit; } -- 1.7.3.2 From mattst88@gmail.com Mon Nov 15 05:53:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 05:53:58 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:48030 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491067Ab0KOExN (ORCPT ); Mon, 15 Nov 2010 05:53:13 +0100 Received: by mail-yw0-f49.google.com with SMTP id 7so1814926ywf.36 for ; Sun, 14 Nov 2010 20:53:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:from:to:cc:subject :date:message-id:x-mailer:in-reply-to:references; bh=xjY5Rx29mx1wztFVSGJMO92P9c0I09KEI5o0g40TyaQ=; b=tHCFUm7sM6dloGTPZZazSNgnFosBcokWTjKNRc/I3TBnYnMEl2msW2EQan+mF93HZy Gl4lFEaQnWuDfvE5LeFRdRY/XvPSno6doIg4SRTiC/WKyyAe6gdipruAJ16rpQRmFzwH sBI0zj31lFXmvaTNgK9ahtdb4LOGjilJTP+lA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Hhl33KwaiD7ixuDSo5PzyDdMYLqbxqpcXE4/5unWevc1veklV/spIj4XF5RSKVmCqj 26fDzUXv8T1Q2R4FKY+pl7tl8wsnGyZiJlbAAgJQmUy3WrPxwLKzJrjz4Un3irBzA/FP +WihqC3wnUh3+KAFtOWcTz5ilGji223wT3joQ= Received: by 10.90.57.3 with SMTP id f3mr7147560aga.120.1289796792640; Sun, 14 Nov 2010 20:53:12 -0800 (PST) Received: from mattst88@gmail.com (cpe-065-190-173-137.nc.res.rr.com [65.190.173.137]) by mx.google.com with ESMTPS id j64sm4328211yha.24.2010.11.14.20.53.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 14 Nov 2010 20:53:11 -0800 (PST) Received: by mattst88@gmail.com (sSMTP sendmail emulation); Sun, 14 Nov 2010 23:54:37 -0500 From: Matt Turner To: linux-mips@linux-mips.org Cc: Ralf Baechle , "Maciej W. Rozycki" , kaloz@openwrt.org, Mark Zhan , Matt Turner Subject: [PATCH 2/3] MIPS: clean up SWARM RTC setup Date: Sun, 14 Nov 2010 23:53:48 -0500 Message-Id: <1289796829-29222-3-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1289796829-29222-1-git-send-email-mattst88@gmail.com> References: <1289796829-29222-1-git-send-email-mattst88@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips From: Maciej W. Rozycki Tested-by: Matt Turner Signed-off-by: Matt Turner --- arch/mips/sibyte/swarm/setup.c | 49 +-------------------------------------- 1 files changed, 2 insertions(+), 47 deletions(-) diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 41707a2..5143f68 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -56,14 +56,6 @@ extern void sb1250_setup(void); #error invalid SiByte board configuration #endif -extern int xicor_probe(void); -extern int xicor_set_time(unsigned long); -extern unsigned long xicor_get_time(void); - -extern int m41t81_probe(void); -extern int m41t81_set_time(unsigned long); -extern unsigned long m41t81_get_time(void); - const char *get_system_type(void) { return "SiByte " SIBYTE_BOARD_NAME; @@ -79,49 +71,17 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup) return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); } -enum swarm_rtc_type { - RTC_NONE, - RTC_XICOR, - RTC_M41T81, -}; - -enum swarm_rtc_type swarm_rtc_type; - void read_persistent_clock(struct timespec *ts) { unsigned long sec; - - switch (swarm_rtc_type) { - case RTC_XICOR: - sec = xicor_get_time(); - break; - - case RTC_M41T81: - sec = m41t81_get_time(); - break; - - case RTC_NONE: - default: - sec = mktime(2000, 1, 1, 0, 0, 0); - break; - } + sec = mktime(2000, 1, 1, 0, 0, 0); ts->tv_sec = sec; ts->tv_nsec = 0; } int rtc_mips_set_time(unsigned long sec) { - switch (swarm_rtc_type) { - case RTC_XICOR: - return xicor_set_time(sec); - - case RTC_M41T81: - return m41t81_set_time(sec); - - case RTC_NONE: - default: - return -1; - } + return -1; } void __init plat_mem_setup(void) @@ -138,11 +98,6 @@ void __init plat_mem_setup(void) board_be_handler = swarm_be_handler; - if (xicor_probe()) - swarm_rtc_type = RTC_XICOR; - if (m41t81_probe()) - swarm_rtc_type = RTC_M41T81; - #ifdef CONFIG_VT screen_info = (struct screen_info) { .orig_video_page = 52, -- 1.7.3.2 From mattst88@gmail.com Mon Nov 15 05:54:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 05:54:21 +0100 (CET) Received: from mail-gw0-f49.google.com ([74.125.83.49]:49105 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491042Ab0KOExb (ORCPT ); Mon, 15 Nov 2010 05:53:31 +0100 Received: by gwb11 with SMTP id 11so935908gwb.36 for ; Sun, 14 Nov 2010 20:53:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:from:to:cc:subject :date:message-id:x-mailer:in-reply-to:references; bh=jW00FTB7KQRtoofGQ33837FzMXck2ZXCEtwLio5yQ+k=; b=jE1pjVEAmVMgfzQA0xl8K3MSwbgdVIBEnPevnpbEks4MIhI0wWWbCzyS22jtAD6vRw w6H31jkZ/XnB7EemKmRTekyWZu4kQwyAusvu1ksLKHLVFIOFcSghfSnJ3IYPnIT2T4+X 904IrtZ1zFKwgH980adDxF6M/CwHUXgpIFs90= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=vb+aKF/3nYS7Iklwl3X7jc0INqpx8Tc+HzCx+uGU1qpJ0bFZJdBdGPvrOqGl5KORZm ovPqQXMGTIa3katOW8ws68XzsSOXDxibARTQfeJod5y2Hvxl+Ael9evu5PyQvZFJRi08 z6S0TECEiLVt8hpd00qvex7vU7Hj28zImuPkY= Received: by 10.150.182.11 with SMTP id e11mr8699350ybf.210.1289796804292; Sun, 14 Nov 2010 20:53:24 -0800 (PST) Received: from mattst88@gmail.com (cpe-065-190-173-137.nc.res.rr.com [65.190.173.137]) by mx.google.com with ESMTPS id h68sm4331199yha.15.2010.11.14.20.53.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 14 Nov 2010 20:53:23 -0800 (PST) Received: by mattst88@gmail.com (sSMTP sendmail emulation); Sun, 14 Nov 2010 23:54:49 -0500 From: Matt Turner To: linux-mips@linux-mips.org Cc: Ralf Baechle , "Maciej W. Rozycki" , kaloz@openwrt.org, Mark Zhan , Matt Turner Subject: [PATCH 3/3] MIPS: register hwmon on SWARM Date: Sun, 14 Nov 2010 23:53:49 -0500 Message-Id: <1289796829-29222-4-git-send-email-mattst88@gmail.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1289796829-29222-1-git-send-email-mattst88@gmail.com> References: <1289796829-29222-1-git-send-email-mattst88@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips From: Maciej W. Rozycki Tested-by: Matt Turner Signed-off-by: Matt Turner --- arch/mips/sibyte/swarm/swarm-i2c.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/mips/sibyte/swarm/swarm-i2c.c b/arch/mips/sibyte/swarm/swarm-i2c.c index 0625050..a6e417f 100644 --- a/arch/mips/sibyte/swarm/swarm-i2c.c +++ b/arch/mips/sibyte/swarm/swarm-i2c.c @@ -13,6 +13,11 @@ #include #include +static struct i2c_board_info swarm_i2c_info0[] __initdata = { + { + I2C_BOARD_INFO("lm90", 0x2a), + }, +}; static struct i2c_board_info swarm_i2c_info1[] __initdata = { { @@ -24,6 +29,8 @@ static int __init swarm_i2c_init(void) { int err; + err = i2c_register_board_info(0, swarm_i2c_info0, + ARRAY_SIZE(swarm_i2c_info0)); err = i2c_register_board_info(1, swarm_i2c_info1, ARRAY_SIZE(swarm_i2c_info1)); if (err < 0) -- 1.7.3.2 From juhosg@openwrt.org Mon Nov 15 10:09:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 10:09:50 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:36351 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491955Ab0KOJJr convert rfc822-to-8bit (ORCPT ); Mon, 15 Nov 2010 10:09:47 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 2C0FC45C030; Mon, 15 Nov 2010 10:09:40 +0100 (CET) Received: from [192.168.254.10] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id BCF57370001; Mon, 15 Nov 2010 10:09:39 +0100 (CET) Message-ID: <4CE0F8D1.8000704@openwrt.org> Date: Mon, 15 Nov 2010 10:09:37 +0100 From: Gabor Juhos User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; hu-HU; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Grant Likely CC: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , David Brownell , spi-devel-general@lists.sourceforge.net, Imre Kaloz Subject: Re: [RFC 11/18] spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-12-git-send-email-juhosg@openwrt.org> <20101114082242.GA3137@angua.secretlab.ca> <4CE04EBC.4080701@openwrt.org> <20101115040456.GB19965@angua.secretlab.ca> In-Reply-To: <20101115040456.GB19965@angua.secretlab.ca> X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-VBMS: A1577CF2F7C | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips 2010.11.15. 5:04 keltezéssel, Grant Likely írta: > On Sun, Nov 14, 2010 at 10:03:56PM +0100, Gabor Juhos wrote: >>>> +static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) >>>> +{ >>>> + return __raw_readl(sp->base + reg); >>>> +} >>>> + >>>> +static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) >>>> +{ >>>> + __raw_writel(val, sp->base + reg); >>>> +} >>> >>> This is suspect. Why is __raw_{readl,writel} being used instead of >>> ioread32/iowrite32? The __raw versions don't provide any kind of >>> ordering barriers. >> >> Mainly because the resulting code is smaller, and the performance is a bit >> better with the use of the __raw versions. The controller is embedded into the >> SoC and the registers are memory mapped, so i think it is safe to access them >> with __raw_{readl,writel}. However I can change it if that is the preferred method. >> > > Smaller, yes, because it doesn't have any io barriers; but is it safe? > Do you know whether or not the CPU will reorder the instructions on > you? Being embedded into the SoC doesn't really mean anything in this > regard. Unless you really understand all the behaviour of the CPU and > bus, then the safe versions must be used. > > If you *do* really understand all the behaviour and decide it is safe > to use the __raw versions, then the driver needs to be well documented > as to the reasons why the __raw versions are safe to use. These SoCs are using the MIPS 24K core. This core is based on an in-order architecture, so it is safe to use the __raw versions from the CPU's side. To be honest, I have no informations about that the completion of the request is always in order that the request are received on the AHB bus between the CPU and the SPI controller. However the Atheros' reference code uses the __raw versions everywhere to access the registers of the built-in devices, so I assume that no out-of-order completion is allowed on that bus. Regards, Gabor From wim@iguana.be Mon Nov 15 11:13:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 11:13:21 +0100 (CET) Received: from mailrelay012.isp.belgacom.be ([195.238.6.179]:61005 "EHLO mailrelay012.isp.belgacom.be" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491962Ab0KOKNP (ORCPT ); Mon, 15 Nov 2010 11:13:15 +0100 X-Belgacom-Dynamic: yes X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEANeU4ExR8Ieb/2dsb2JhbACiVXK7TQ2FPQQ Received: from 155.135-240-81.adsl-dyn.isp.belgacom.be (HELO infomag) ([81.240.135.155]) by relay.skynet.be with ESMTP; 15 Nov 2010 11:13:07 +0100 Received: from wim by infomag with local (Exim 4.69) (envelope-from ) id 1PHw3e-0005vL-MP; Mon, 15 Nov 2010 11:13:06 +0100 Date: Mon, 15 Nov 2010 11:13:06 +0100 From: Wim Van Sebroeck To: Gabor Juhos Cc: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , linux-watchdog@vger.kernel.org Subject: Re: [RFC 07/18] watchdog: add driver for the Atheros AR71XX/AR724X/AR913X SoCs Message-ID: <20101115101306.GE4046@infomag.iguana.be> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-8-git-send-email-juhosg@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1289598684-30624-8-git-send-email-juhosg@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk X-list: linux-mips Hi Gabor, > This patch adds a driver for the built-in hardware watchdog device > of the Atheros AR71XX/AR724X/AR913X SoCs. > > Signed-off-by: Gabor Juhos > Signed-off-by: Imre Kaloz > Cc: Wim Van Sebroeck > Cc: linux-watchdog@vger.kernel.org Driver queud for review. Kind regards, Wim. From juhosg@openwrt.org Mon Nov 15 11:30:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 11:30:42 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:34878 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492197Ab0KOKag (ORCPT ); Mon, 15 Nov 2010 11:30:36 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 0E20F45C033; Mon, 15 Nov 2010 11:30:29 +0100 (CET) Received: from [192.168.254.10] (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 0BB9B1F0001; Mon, 15 Nov 2010 11:30:27 +0100 (CET) Message-ID: <4CE10BC0.6090002@openwrt.org> Date: Mon, 15 Nov 2010 11:30:24 +0100 From: Gabor Juhos User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; hu-HU; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Wim Van Sebroeck CC: Ralf Baechle , linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , Imre Kaloz , linux-watchdog@vger.kernel.org Subject: Re: [RFC 07/18] watchdog: add driver for the Atheros AR71XX/AR724X/AR913X SoCs References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-8-git-send-email-juhosg@openwrt.org> <20101115101306.GE4046@infomag.iguana.be> In-Reply-To: <20101115101306.GE4046@infomag.iguana.be> X-Enigmail-Version: 1.1.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-VBMS: A12B9CE606C | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Hi Wim, >> This patch adds a driver for the built-in hardware watchdog device >> of the Atheros AR71XX/AR724X/AR913X SoCs. >> >> Signed-off-by: Gabor Juhos >> Signed-off-by: Imre Kaloz >> Cc: Wim Van Sebroeck >> Cc: linux-watchdog@vger.kernel.org > > Driver queud for review. Thank you! Regards, Gabor From glikely@secretlab.ca Mon Nov 15 17:28:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2010 17:28:38 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:37819 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492227Ab0KOQ2c convert rfc822-to-8bit (ORCPT ); Mon, 15 Nov 2010 17:28:32 +0100 Received: by gxk25 with SMTP id 25so3389433gxk.36 for ; Mon, 15 Nov 2010 08:28:26 -0800 (PST) Received: by 10.42.167.9 with SMTP id q9mr2369955icy.76.1289838506140; Mon, 15 Nov 2010 08:28:26 -0800 (PST) MIME-Version: 1.0 Received: by 10.231.5.194 with HTTP; Mon, 15 Nov 2010 08:28:05 -0800 (PST) In-Reply-To: <4CE0F8D1.8000704@openwrt.org> References: <1289598684-30624-1-git-send-email-juhosg@openwrt.org> <1289598684-30624-12-git-send-email-juhosg@openwrt.org> <20101114082242.GA3137@angua.secretlab.ca> <4CE04EBC.4080701@openwrt.org> <20101115040456.GB19965@angua.secretlab.ca> <4CE0F8D1.8000704@openwrt.org> From: Grant Likely Date: Mon, 15 Nov 2010 09:28:05 -0700 X-Google-Sender-Auth: v7XhZ4mWHk7J19QmZ8hNKFf2JRc Message-ID: Subject: Re: [RFC 11/18] spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs To: Gabor Juhos , Ralf Baechle Cc: linux-mips@linux-mips.org, "Luis R. Rodriguez" , Cliff Holden , David Brownell , spi-devel-general@lists.sourceforge.net, Imre Kaloz Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Mon, Nov 15, 2010 at 2:09 AM, Gabor Juhos wrote: > 2010.11.15. 5:04 keltezéssel, Grant Likely írta: >> On Sun, Nov 14, 2010 at 10:03:56PM +0100, Gabor Juhos wrote: >>>>> +static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) >>>>> +{ >>>>> +  return __raw_readl(sp->base + reg); >>>>> +} >>>>> + >>>>> +static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) >>>>> +{ >>>>> +  __raw_writel(val, sp->base + reg); >>>>> +} >>>> >>>> This is suspect.  Why is __raw_{readl,writel} being used instead of >>>> ioread32/iowrite32?  The __raw versions don't provide any kind of >>>> ordering barriers. >>> >>> Mainly because the resulting code is smaller, and the performance is a bit >>> better with the use of the __raw versions. The controller is embedded into the >>> SoC and the registers are memory mapped, so i think it is safe to access them >>> with __raw_{readl,writel}. However I can change it if that is the preferred method. >>> >> >> Smaller, yes, because it doesn't have any io barriers; but is it safe? >> Do you know whether or not the CPU will reorder the instructions on >> you?  Being embedded into the SoC doesn't really mean anything in this >> regard.  Unless you really understand all the behaviour of the CPU and >> bus, then the safe versions must be used. >> >> If you *do* really understand all the behaviour and decide it is safe >> to use the __raw versions, then the driver needs to be well documented >> as to the reasons why the __raw versions are safe to use. > > These SoCs are using the MIPS 24K core. This core is based on an in-order > architecture, so it is safe to use the __raw versions from the CPU's side. > > To be honest, I have no informations about that the completion of the request is > always in order that the request are received on the AHB bus between the CPU and > the SPI controller. However the Atheros' reference code uses the __raw versions > everywhere to access the registers of the built-in devices, so I assume that no > out-of-order completion is allowed on that bus. Ralf, what say you? I personally don't like this, and it makes for a bad example of driver code, but I'll accept it if you say that it is the right thing to do for MIPS device drivers. (Although I retain my requirement that the use of __raw accessors needs to be well documented). g. From rmh.aybabtu@gmail.com Tue Nov 16 00:50:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2010 00:50:46 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:34712 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492263Ab0KOXul (ORCPT ); Tue, 16 Nov 2010 00:50:41 +0100 Received: by ewy19 with SMTP id 19so27107ewy.36 for ; Mon, 15 Nov 2010 15:50:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:subject:to :cc:references:in-reply-to:x-mailer:message-id:mime-version :content-type; bh=dEA7e5sH5ys0mV71RRyRLQ2cfgXuvWLrNN4jUOz9ZKc=; b=kD6YYWHGFDzEysTOxPqCxpHT04Sz/S7FP4Mi9yOhMGrV4iTYrBWAY6Q/GS/ir/ek1x sdi180ABz/2ObO5sVkJi08198k4VtSpLiFFQNlV104E22eRwzpZH8djE1l+8EyMHFNhq 5o4gDdl0988P8I/7TJSjrMCEv6+4ZN15B1xL0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:subject:to:cc:references:in-reply-to:x-mailer :message-id:mime-version:content-type; b=wpaUVIoRkY7tbiDp4d9lQGCNCsNgkPN+IBZ2ndvUGFGZ3RI9x5OYCirYLc11HYLj45 P8gw0mjfGrTLUE5YQpx4p8Gl1t2tk8fNvFpuGZQHIPFqTuk3OTJvL5ekd3BM5zlWxmlU Q3Aj0cRMSY7LVo2oHG76PzkJfO54XIUUQVCwY= Received: by 10.213.8.136 with SMTP id h8mr5314304ebh.36.1289865039884; Mon, 15 Nov 2010 15:50:39 -0800 (PST) Received: from thorin ([83.45.77.222]) by mx.google.com with ESMTPS id x54sm500933eeh.11.2010.11.15.15.50.36 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 15 Nov 2010 15:50:37 -0800 (PST) Date: Tue, 16 Nov 2010 00:50:28 +0100 From: Robert Millan Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU To: Robert Millan Cc: Ralf Baechle , wu zhangjin , David Daney , Aurelien Jarno , linux-mips@linux-mips.org References: <20101109154055.GD10799@linux-mips.org> <1289486855.14828.0@thorin> In-Reply-To: <1289486855.14828.0@thorin> (from rmh@gnu.org on Thu Nov 11 15:47:35 2010) X-Mailer: Balsa 2.4.1 Message-Id: <1289865028.9277.0@thorin> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-TrgpL6pPRRG/T6pcLOqM" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips --=-TrgpL6pPRRG/T6pcLOqM Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable El 11/11/10 15:47:35, en/na Robert Millan va escriure: > - __cpu_name[cpu] =3D "ICT Loongson-2"; > + switch (c->processor_id & PRID_REV_MASK) { > + case PRID_REV_LOONGSON2E: > + __cpu_name[cpu] =3D "ICT Loongson-2E"; Actually, the V0.2 / V0.3 that follows in cpuinfo output already indicates revision. And I noticed that appending the 'E' or 'F' breaks GCC's -march=3Dnative option (which works by parsing /proc/cpuinfo). Please use this patch instead. --=-TrgpL6pPRRG/T6pcLOqM Content-Type: text/x-patch; charset=us-ascii; name=loongson2f.diff Content-Disposition: attachment; filename=loongson2f.diff Content-Transfer-Encoding: quoted-printable Signed-off-by: Robert Millan diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index fd1d39e..58844f6 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -344,6 +344,12 @@ extern int dump_task_fpu(struct task_struct *, elf_fpr= egset_t *); #define ELF_PLATFORM __elf_platform extern const char *__elf_platform; =20 +static inline void set_elf_platform(int cpu, const char *plat) +{ + if (cpu =3D=3D 0) + __elf_platform =3D plat; +} + /* * See comments in asm-alpha/elf.h, this is the same thing * on the MIPS. diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 71620e1..accde65 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -614,6 +614,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mip= s *c, unsigned int cpu) case PRID_IMP_LOONGSON2: c->cputype =3D CPU_LOONGSON2; __cpu_name[cpu] =3D "ICT Loongson-2"; + switch (c->processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON2E: + set_elf_platform(cpu, "loongson2e"); + break; + case PRID_REV_LOONGSON2F: + set_elf_platform(cpu, "loongson2f"); + break; + } c->isa_level =3D MIPS_CPU_ISA_III; c->options =3D R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | @@ -957,14 +965,12 @@ static inline void cpu_probe_cavium(struct cpuinfo_mi= ps *c, unsigned int cpu) c->cputype =3D CPU_CAVIUM_OCTEON_PLUS; __cpu_name[cpu] =3D "Cavium Octeon+"; platform: - if (cpu =3D=3D 0) - __elf_platform =3D "octeon"; + set_elf_platform(cpu, "octeon"); break; case PRID_IMP_CAVIUM_CN63XX: c->cputype =3D CPU_CAVIUM_OCTEON2; __cpu_name[cpu] =3D "Cavium Octeon II"; - if (cpu =3D=3D 0) - __elf_platform =3D "octeon2"; + set_elf_platform(cpu, "octeon2"); break; default: printk(KERN_INFO "Unknown Octeon chip!\n"); --=-TrgpL6pPRRG/T6pcLOqM-- From David.Daney@caviumnetworks.com Tue Nov 16 00:59:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2010 00:59:50 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11492 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492263Ab0KOX7r (ORCPT ); Tue, 16 Nov 2010 00:59:47 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Nov 2010 16:00:23 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 15 Nov 2010 16:00:30 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 15 Nov 2010 16:00:30 -0800 Message-ID: <4CE1C96F.1030909@caviumnetworks.com> Date: Mon, 15 Nov 2010 15:59:43 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: Robert Millan , Ralf Baechle CC: wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU References: <20101109154055.GD10799@linux-mips.org> <1289486855.14828.0@thorin> <1289865028.9277.0@thorin> In-Reply-To: <1289865028.9277.0@thorin> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 16 Nov 2010 00:00:30.0560 (UTC) FILETIME=[486B5600:01CB8521] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 11/15/2010 03:50 PM, Robert Millan wrote: > El 11/11/10 15:47:35, en/na Robert Millan va escriure: >> > - __cpu_name[cpu] = "ICT Loongson-2"; >> > + switch (c->processor_id& PRID_REV_MASK) { >> > + case PRID_REV_LOONGSON2E: >> > + __cpu_name[cpu] = "ICT Loongson-2E"; > Actually, the V0.2 / V0.3 that follows in cpuinfo output > already indicates revision. And I noticed that appending > the 'E' or 'F' breaks GCC's -march=native option (which > works by parsing /proc/cpuinfo). > Good catch, this is true, __cpu_name for better or worse is part of the kernel/user ABI. GCC parses this in gcc/config/mips/driver-native.c > Please use this patch instead. > > > > loongson2f.diff > > > > Signed-off-by: Robert Millan > Acked-by: David Daney > diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h > index fd1d39e..58844f6 100644 > --- a/arch/mips/include/asm/elf.h > +++ b/arch/mips/include/asm/elf.h > @@ -344,6 +344,12 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); > #define ELF_PLATFORM __elf_platform > extern const char *__elf_platform; > > +static inline void set_elf_platform(int cpu, const char *plat) > +{ > + if (cpu == 0) > + __elf_platform = plat; > +} > + > /* > * See comments in asm-alpha/elf.h, this is the same thing > * on the MIPS. > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 71620e1..accde65 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -614,6 +614,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) > case PRID_IMP_LOONGSON2: > c->cputype = CPU_LOONGSON2; > __cpu_name[cpu] = "ICT Loongson-2"; > + switch (c->processor_id& PRID_REV_MASK) { > + case PRID_REV_LOONGSON2E: > + set_elf_platform(cpu, "loongson2e"); > + break; > + case PRID_REV_LOONGSON2F: > + set_elf_platform(cpu, "loongson2f"); > + break; > + } > c->isa_level = MIPS_CPU_ISA_III; > c->options = R4K_OPTS | > MIPS_CPU_FPU | MIPS_CPU_LLSC | > @@ -957,14 +965,12 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) > c->cputype = CPU_CAVIUM_OCTEON_PLUS; > __cpu_name[cpu] = "Cavium Octeon+"; > platform: > - if (cpu == 0) > - __elf_platform = "octeon"; > + set_elf_platform(cpu, "octeon"); > break; > case PRID_IMP_CAVIUM_CN63XX: > c->cputype = CPU_CAVIUM_OCTEON2; > __cpu_name[cpu] = "Cavium Octeon II"; > - if (cpu == 0) > - __elf_platform = "octeon2"; > + set_elf_platform(cpu, "octeon2"); > break; > default: > printk(KERN_INFO "Unknown Octeon chip!\n"); > From namhyung@gmail.com Tue Nov 16 15:47:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2010 15:47:33 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:53752 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492291Ab0KPOra (ORCPT ); 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Tue, 16 Nov 2010 06:47:21 -0800 (PST) From: Namhyung Kim To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND] MIPS: Define dummy MAX_DMA_CHANNELS to fix build failure Date: Tue, 16 Nov 2010 23:47:20 +0900 Message-Id: <1289918840-13434-1-git-send-email-namhyung@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: namhyung@gmail.com Precedence: bulk X-list: linux-mips allmodconfig build failes like following: CC [M] sound/oss/soundcard.o sound/oss/soundcard.c:68: error: 'MAX_DMA_CHANNELS' undeclared here (not in a function) make[3]: *** [sound/oss/soundcard.o] Error 1 make[2]: *** [sound/oss] Error 2 make[1]: *** [sub-make] Error 2 make: *** [all] Error 2 Signed-off-by: Namhyung Kim --- arch/mips/include/asm/dma.h | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h index 2d47da6..c601cff 100644 --- a/arch/mips/include/asm/dma.h +++ b/arch/mips/include/asm/dma.h @@ -74,7 +74,9 @@ * */ -#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN +#ifdef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN +#define MAX_DMA_CHANNELS 0 +#else #define MAX_DMA_CHANNELS 8 #endif -- 1.7.0.4 From David.Daney@caviumnetworks.com Tue Nov 16 23:42:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2010 23:42:37 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:7358 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492348Ab0KPWme (ORCPT ); Tue, 16 Nov 2010 23:42:34 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 16 Nov 2010 14:43:06 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 16 Nov 2010 14:43:14 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 16 Nov 2010 14:43:14 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id oAGMgKYW014417; Tue, 16 Nov 2010 14:42:20 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id oAGMgIa7014416; Tue, 16 Nov 2010 14:42:18 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, grant.likely@secretlab.ca, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH] of: Request module by alias in of_i2c.c Date: Tue, 16 Nov 2010 14:42:14 -0800 Message-Id: <1289947334-14375-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.3 X-OriginalArrivalTime: 16 Nov 2010 22:43:14.0642 (UTC) FILETIME=[A79C2320:01CB85DF] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips If we are registering an i2c device that has a device tree node like this real-world example: rtc@68 { compatible = "dallas,ds1337"; reg = <0x68>; }; of_i2c_register_devices() will try to load a module called ds1337.ko. There is no such module, so it will fail. If we look in modules.alias we will find entries like these: . . . alias i2c:ds1339 rtc_ds1307 alias i2c:ds1338 rtc_ds1307 alias i2c:ds1337 rtc_ds1307 alias i2c:ds1307 rtc_ds1307 alias i2c:ds1374 rtc_ds1374 . . . The module we want is really called rtc_ds1307.ko. If we request a module called "i2c:ds1337", the userspace module loader will do the right thing (unless it is busybox) and load rtc_ds1307.ko. So we add the I2C_MODULE_PREFIX to the request_module() string. Signed-off-by: David Daney --- drivers/of/of_i2c.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/of/of_i2c.c b/drivers/of/of_i2c.c index c85d3c7..f37fbeb 100644 --- a/drivers/of/of_i2c.c +++ b/drivers/of/of_i2c.c @@ -61,7 +61,7 @@ void of_i2c_register_devices(struct i2c_adapter *adap) info.of_node = of_node_get(node); info.archdata = &dev_ad; - request_module("%s", info.type); + request_module("%s%s", I2C_MODULE_PREFIX, info.type); result = i2c_new_device(adap, &info); if (result == NULL) { -- 1.7.2.3 From glikely@secretlab.ca Wed Nov 17 07:24:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2010 07:24:25 +0100 (CET) Received: from mail-yw0-f49.google.com ([209.85.213.49]:49150 "EHLO mail-yw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490991Ab0KQGYV (ORCPT ); Wed, 17 Nov 2010 07:24:21 +0100 Received: by ywf7 with SMTP id 7so997062ywf.36 for ; Tue, 16 Nov 2010 22:24:15 -0800 (PST) Received: by 10.100.119.13 with SMTP id r13mr5893615anc.153.1289975055523; Tue, 16 Nov 2010 22:24:15 -0800 (PST) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id w15sm6006681anw.33.2010.11.16.22.24.13 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 16 Nov 2010 22:24:14 -0800 (PST) Received: by angua (Postfix, from userid 1000) id 474AD3C00E5; Tue, 16 Nov 2010 23:24:12 -0700 (MST) Date: Tue, 16 Nov 2010 23:24:12 -0700 From: Grant Likely To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] of: Request module by alias in of_i2c.c Message-ID: <20101117062412.GK12813@angua.secretlab.ca> References: <1289947334-14375-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1289947334-14375-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Tue, Nov 16, 2010 at 02:42:14PM -0800, David Daney wrote: > If we are registering an i2c device that has a device tree node like > this real-world example: > > rtc@68 { > compatible = "dallas,ds1337"; > reg = <0x68>; > }; > > of_i2c_register_devices() will try to load a module called ds1337.ko. > There is no such module, so it will fail. If we look in modules.alias > we will find entries like these: > > . > . > . > alias i2c:ds1339 rtc_ds1307 > alias i2c:ds1338 rtc_ds1307 > alias i2c:ds1337 rtc_ds1307 > alias i2c:ds1307 rtc_ds1307 > alias i2c:ds1374 rtc_ds1374 > . > . > . > > The module we want is really called rtc_ds1307.ko. If we request a > module called "i2c:ds1337", the userspace module loader will do the > right thing (unless it is busybox) and load rtc_ds1307.ko. So we add > the I2C_MODULE_PREFIX to the request_module() string. > > Signed-off-by: David Daney Applied, thanks. g. > --- > drivers/of/of_i2c.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/of/of_i2c.c b/drivers/of/of_i2c.c > index c85d3c7..f37fbeb 100644 > --- a/drivers/of/of_i2c.c > +++ b/drivers/of/of_i2c.c > @@ -61,7 +61,7 @@ void of_i2c_register_devices(struct i2c_adapter *adap) > info.of_node = of_node_get(node); > info.archdata = &dev_ad; > > - request_module("%s", info.type); > + request_module("%s%s", I2C_MODULE_PREFIX, info.type); > > result = i2c_new_device(adap, &info); > if (result == NULL) { > -- > 1.7.2.3 > From maksim.rayskiy@gmail.com Wed Nov 17 19:49:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2010 19:49:18 +0100 (CET) Received: from mail-yx0-f177.google.com ([209.85.213.177]:37336 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491979Ab0KQStP (ORCPT ); Wed, 17 Nov 2010 19:49:15 +0100 Received: by yxj4 with SMTP id 4so1011814yxj.36 for ; Wed, 17 Nov 2010 10:49:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=oVBZz93BdDpTlmmXtAJGUAXJaXcUcKVPmRlxN9Pp/f4=; b=GXRC522MHjKfwfR2TpDs8cx8o08flgx6saHvHYHhvg5sI6lT6+nJFO+QMsYE+mcsUr C28SLcIbw6xYvTOi0sPOjmuTrMrrcNteSdXa2iK4/soZcCjtYWoCQlbrMSbv/9g5OR44 ph1Ovp8d8Gg+CgROsQtf+gQOIIaq2CaAVffok= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=YhQQMtJnhLhL7U3x1Afiiofb6kwmKts4ebMLhhTrXZcHekpOyGcVbneLFRIR+hZST+ IMn6DYvnbMRsqDWHrwSiDYWAE6mXBlWWwgl35Yz2syilUo44mb552l5gefoSeFSJ6SPy hRx85xcGkVyQ3VxA45Q8N4LuLRTkSUfy4tPi8= MIME-Version: 1.0 Received: by 10.100.17.4 with SMTP id 4mr6408000anq.119.1290019749723; Wed, 17 Nov 2010 10:49:09 -0800 (PST) Received: by 10.100.7.13 with HTTP; Wed, 17 Nov 2010 10:49:09 -0800 (PST) Date: Wed, 17 Nov 2010 10:49:09 -0800 Message-ID: Subject: [PATCH] MIPS: ASID conflict after CPU hotplug From: Maksim Rayskiy To: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28406 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maksim.rayskiy@gmail.com Precedence: bulk X-list: linux-mips This is a repost of my original message which somehow did not reach the mailing list (filtered out?). Hello, I am running SMP Linux 2.6.37-rc1 on BMIPS5000 (single core dual thread) and observe some abnormalities when doing system suspend/resume which I narrowed down to cpu hotplugging. The suspend brings the second thread processor down and then restarts it, after which I see memory corruption in userspace. I started digging and found out that problem occurs because while doing execve() the child process is getting the same ASID as the parent, which obviously corrupts parent's address space. Further digging showed that: activate_mm() calls get_new_mmu_context() to get a new ASID, but at this time ASID field in entryHi is 1, and asid_cache(cpu) is 0x100 (it was just reset to ASID_FIRST_VERSION when the secondary TP was booting). So, get_new_mmu_context() increments the asid_cache(cpu) value to 0x101, and thus puts 0x01 into entryHi. The result - ASID field does not get changed as it was supposed to. My solution was very simple - do not reset asid_cache(cpu) on TP warm restart. But I would welcome any comments because my understanding of the code is somewhat fuzzy. diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d83f325..ccf9272 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1577,7 +1577,8 @@ void __cpuinit per_cpu_trap_init(void) } #endif /* CONFIG_MIPS_MT_SMTC */ - cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; + if (!cpu_data[cpu].asid_cache) + cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; TLBMISS_HANDLER_SETUP(); atomic_inc(&init_mm.mm_count); Regards, Max Rayskiy. From dengcheng.zhu@gmail.com Thu Nov 18 08:01:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 08:01:37 +0100 (CET) Received: from mail-pz0-f49.google.com ([209.85.210.49]:52603 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492040Ab0KRHBe (ORCPT ); Thu, 18 Nov 2010 08:01:34 +0100 Received: by pzk3 with SMTP id 3so602449pzk.36 for ; Wed, 17 Nov 2010 23:01:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=2WeiCj9vXGc7SwD6nQIQ9dJ9Y/ijZceXjGv1cKAQz/E=; b=nTWDdSXWFWV3G8MlpQYxICIGgU5jWJHiCNBPgRT1d8Izb33yP24vjUqG/EAosAJm+8 DtKL3DlOBkI8smTE6jOOX0vG6xZb59oEhmCUUtt5RxQ/5W6fLP8oRlJJDtPadO4bx6AT jHjG25Owfz6zC/RSgCa+K1gIAZbl5qmeZP+p0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=sHf0X8h9onw/YrR7qmU6W02bKhoK7EmZoAsGSnbypFilEpC9F3dFeo6nJFHvoFpgAf iwBiU9w4Bnqp0Icrqc6AnxpXi4Nr6dYNguqz7xx9yQFIvaeE0UiT+8Qf085F5e37SAw2 1h5yCe9AYNb9dkyxA7MVNlrsEcv6EmIN+jYf4= Received: by 10.142.213.11 with SMTP id l11mr179587wfg.278.1290063687037; Wed, 17 Nov 2010 23:01:27 -0800 (PST) Received: from localhost.localdomain ([210.13.118.102]) by mx.google.com with ESMTPS id w27sm81044wfd.14.2010.11.17.23.01.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 17 Nov 2010 23:01:24 -0800 (PST) From: Deng-Cheng Zhu To: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, dengcheng.zhu@gmail.com Subject: [PATCH 0/5] MIPS/Perf-events: Sync with mainline upper layer Date: Thu, 18 Nov 2010 14:56:36 +0800 Message-Id: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28407 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Current MIPS Perf-events uses older interfaces to the generic layer. So it will not work. This patch set fixes this issue by adding MIPS counterparts for a list of previous commits that went to mainline earlier. Deng-Cheng Zhu (5): MIPS/Perf-events: Work with irq_work MIPS/Perf-events: Work with the new PMU interface MIPS/Perf-events: Check event state in validate_event() MIPS/Perf-events: Work with the new callchain interface MIPS/Perf-events: Use unsigned delta for right shift in event update arch/mips/Kconfig | 1 + arch/mips/include/asm/perf_event.h | 12 +- arch/mips/kernel/perf_event.c | 342 ++++++++++++++++------------------ arch/mips/kernel/perf_event_mipsxx.c | 4 +- 4 files changed, 169 insertions(+), 190 deletions(-) From dengcheng.zhu@gmail.com Thu Nov 18 08:01:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 08:02:01 +0100 (CET) Received: from mail-pv0-f177.google.com ([74.125.83.177]:37560 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492043Ab0KRHBl (ORCPT ); Thu, 18 Nov 2010 08:01:41 +0100 Received: by pvg7 with SMTP id 7so775496pvg.36 for ; Wed, 17 Nov 2010 23:01:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=1/W/zOLpovt+kA92/y6DKOs6Igp8/p9BDUaLRZ5qJKk=; b=ny0OvviZZC9jCgX40NqqDZaywDuBAx0BMknUqPkPMmcn6be1L3uAJhYzRA+bZHJdCD LpmxlYvmq5rQOwOUH867tE5uxwpnvAtQBcjmv/5ADnpPY4ZHNz57eapKGcj4WWLDVIpZ iBOfLDWakjH5/FzFPlInxFkUu5An8k3oU6BRk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=EqmQhW4pKawkY1rkXoO+2GROQbANS76eK9lNt2lJ4iHXf5RcC/f12IS5Mxhyy7s8kB H2kGiS2N5IVoKMgl3RiBku/+I/NdtIEsXC08ataSSK2Jjg/oh4sm052s0XO8XpV9JTlr tG0bd8AbJVGCzXJDT6pdiBdwFMm2XVpJFCFQM= Received: by 10.143.4.19 with SMTP id g19mr199244wfi.81.1290063692204; Wed, 17 Nov 2010 23:01:32 -0800 (PST) Received: from localhost.localdomain ([210.13.118.102]) by mx.google.com with ESMTPS id w27sm81044wfd.14.2010.11.17.23.01.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 17 Nov 2010 23:01:31 -0800 (PST) From: Deng-Cheng Zhu To: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, dengcheng.zhu@gmail.com Subject: [PATCH 1/5] MIPS/Perf-events: Work with irq_work Date: Thu, 18 Nov 2010 14:56:37 +0800 Message-Id: <1290063401-25440-2-git-send-email-dengcheng.zhu@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28408 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips This is the MIPS part of the following commit by Peter Zijlstra: e360adbe29241a0194e10e20595360dd7b98a2b3 irq_work: Add generic hardirq context callbacks Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 1 + arch/mips/include/asm/perf_event.h | 12 +----------- arch/mips/kernel/perf_event_mipsxx.c | 2 +- 3 files changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 67a2fa2..c44c38d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,7 @@ config MIPS select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE select HAVE_OPROFILE + select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_ARCH_KGDB diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h index e00007c..d0c7749 100644 --- a/arch/mips/include/asm/perf_event.h +++ b/arch/mips/include/asm/perf_event.h @@ -11,15 +11,5 @@ #ifndef __MIPS_PERF_EVENT_H__ #define __MIPS_PERF_EVENT_H__ - -/* - * MIPS performance counters do not raise NMI upon overflow, a regular - * interrupt will be signaled. Hence we can do the pending perf event - * work at the tail of the irq handler. - */ -static inline void -set_perf_event_pending(void) -{ -} - +/* Leave it empty here. The file is required by linux/perf_event.h */ #endif /* __MIPS_PERF_EVENT_H__ */ diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 5c7c6fc..fa00edc 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -696,7 +696,7 @@ static int mipsxx_pmu_handle_shared_irq(void) * interrupt, not NMI. */ if (handled == IRQ_HANDLED) - perf_event_do_pending(); + irq_work_run(); #ifdef CONFIG_MIPS_MT_SMP read_unlock(&pmuint_rwlock); -- 1.7.1 From dengcheng.zhu@gmail.com Thu Nov 18 08:02:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 08:02:28 +0100 (CET) Received: from mail-pv0-f177.google.com ([74.125.83.177]:46405 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492045Ab0KRHBo (ORCPT ); Thu, 18 Nov 2010 08:01:44 +0100 Received: by pvg7 with SMTP id 7so775511pvg.36 for ; Wed, 17 Nov 2010 23:01:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=3hl02e1xIwahP0UIHL9c0EOwa8MT4GDn0SyR4tf6Qe4=; b=Nx5eH7NszBdM9/7p0q/y6H6+VRILF9V+MqwObMpSZ/ngTs1eG64rkZP3vInP2ZgiLF knBfOyLS+In7WB8ATms1mYqcRrF2MueXWPS90Cnmf1yhJEDZSrkV6z41gF5akhpgV7H2 peIotVSZHOtWwCoLLm0MROuOeCvP737sSpgcQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=F5VCSxbGz1+BJJBLvsHas7QPgZD/YpbCI83MukpqyEVccYKW7CuWn0I8Ozmkf3p3lh hl7Ilnc1SAltoGUwmCFpUM0fjvkFNaTAh8yI99pXKKKeHSxps2y8kBsVpYrbeCJyOQmO 82iiK0nICWjMp36OExSdw+AvVac/0WS3KSHKs= Received: by 10.142.149.3 with SMTP id w3mr117927wfd.368.1290063697442; Wed, 17 Nov 2010 23:01:37 -0800 (PST) Received: from localhost.localdomain ([210.13.118.102]) by mx.google.com with ESMTPS id w27sm81044wfd.14.2010.11.17.23.01.32 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 17 Nov 2010 23:01:36 -0800 (PST) From: Deng-Cheng Zhu To: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, dengcheng.zhu@gmail.com Subject: [PATCH 2/5] MIPS/Perf-events: Work with the new PMU interface Date: Thu, 18 Nov 2010 14:56:38 +0800 Message-Id: <1290063401-25440-3-git-send-email-dengcheng.zhu@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28409 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips This is the MIPS part of the following commits by Peter Zijlstra: a4eaf7f14675cb512d69f0c928055e73d0c6d252 perf: Rework the PMU methods 33696fc0d141bbbcb12f75b69608ea83282e3117 perf: Per PMU disable 24cd7f54a0d47e1d5b3de29e2456bfbd2d8447b7 perf: Reduce perf_disable() usage b0a873ebbf87bf38bf70b5e39a7cadc96099fa13 perf: Register PMU implementations 51b0fe39549a04858001922919ab355dee9bdfcf perf: Deconstify struct pmu Signed-off-by: Deng-Cheng Zhu --- arch/mips/kernel/perf_event.c | 275 +++++++++++++++++++--------------- arch/mips/kernel/perf_event_mipsxx.c | 2 + 2 files changed, 158 insertions(+), 119 deletions(-) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index 2b7f3f7..1ee44a3 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -161,41 +161,6 @@ mipspmu_event_set_period(struct perf_event *event, return ret; } -static int mipspmu_enable(struct perf_event *event) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - struct hw_perf_event *hwc = &event->hw; - int idx; - int err = 0; - - /* To look for a free counter for this event. */ - idx = mipspmu->alloc_counter(cpuc, hwc); - if (idx < 0) { - err = idx; - goto out; - } - - /* - * If there is an event in the counter we are going to use then - * make sure it is disabled. - */ - event->hw.idx = idx; - mipspmu->disable_event(idx); - cpuc->events[idx] = event; - - /* Set the period for the event. */ - mipspmu_event_set_period(event, hwc, idx); - - /* Enable the event. */ - mipspmu->enable_event(hwc, idx); - - /* Propagate our changes to the userspace mapping. */ - perf_event_update_userpage(event); - -out: - return err; -} - static void mipspmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, int idx) @@ -231,32 +196,90 @@ again: return; } -static void mipspmu_disable(struct perf_event *event) +static void mipspmu_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc = &event->hw; + + if (!mipspmu) + return; + + if (flags & PERF_EF_RELOAD) + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); + + hwc->state = 0; + + /* Set the period for the event. */ + mipspmu_event_set_period(event, hwc, hwc->idx); + + /* Enable the event. */ + mipspmu->enable_event(hwc, hwc->idx); +} + +static void mipspmu_stop(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc = &event->hw; + + if (!mipspmu) + return; + + if (!(hwc->state & PERF_HES_STOPPED)) { + /* We are working on a local event. */ + mipspmu->disable_event(hwc->idx); + barrier(); + mipspmu_event_update(event, hwc, hwc->idx); + hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; + } +} + +static int mipspmu_add(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; + int idx; + int err = 0; + perf_pmu_disable(event->pmu); - WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + /* To look for a free counter for this event. */ + idx = mipspmu->alloc_counter(cpuc, hwc); + if (idx < 0) { + err = idx; + goto out; + } - /* We are working on a local event. */ + /* + * If there is an event in the counter we are going to use then + * make sure it is disabled. + */ + event->hw.idx = idx; mipspmu->disable_event(idx); + cpuc->events[idx] = event; - barrier(); - - mipspmu_event_update(event, hwc, idx); - cpuc->events[idx] = NULL; - clear_bit(idx, cpuc->used_mask); + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; + if (flags & PERF_EF_START) + mipspmu_start(event, PERF_EF_RELOAD); + /* Propagate our changes to the userspace mapping. */ perf_event_update_userpage(event); + +out: + perf_pmu_enable(event->pmu); + return err; } -static void mipspmu_unthrottle(struct perf_event *event) +static void mipspmu_del(struct perf_event *event, int flags) { + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; - mipspmu->enable_event(hwc, hwc->idx); + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + mipspmu_stop(event, PERF_EF_UPDATE); + cpuc->events[idx] = NULL; + clear_bit(idx, cpuc->used_mask); + + perf_event_update_userpage(event); } static void mipspmu_read(struct perf_event *event) @@ -270,12 +293,17 @@ static void mipspmu_read(struct perf_event *event) mipspmu_event_update(event, hwc, hwc->idx); } -static struct pmu pmu = { - .enable = mipspmu_enable, - .disable = mipspmu_disable, - .unthrottle = mipspmu_unthrottle, - .read = mipspmu_read, -}; +static void mipspmu_enable(struct pmu *pmu) +{ + if (mipspmu) + mipspmu->start(); +} + +static void mipspmu_disable(struct pmu *pmu) +{ + if (mipspmu) + mipspmu->stop(); +} static atomic_t active_events = ATOMIC_INIT(0); static DEFINE_MUTEX(pmu_reserve_mutex); @@ -318,6 +346,82 @@ static void mipspmu_free_irq(void) perf_irq = save_perf_irq; } +/* + * mipsxx/rm9000/loongson2 have different performance counters, they have + * specific low-level init routines. + */ +static void reset_counters(void *arg); +static int __hw_perf_event_init(struct perf_event *event); + +static void hw_perf_event_destroy(struct perf_event *event) +{ + if (atomic_dec_and_mutex_lock(&active_events, + &pmu_reserve_mutex)) { + /* + * We must not call the destroy function with interrupts + * disabled. + */ + on_each_cpu(reset_counters, + (void *)(long)mipspmu->num_counters, 1); + mipspmu_free_irq(); + mutex_unlock(&pmu_reserve_mutex); + } +} + +static int mipspmu_event_init(struct perf_event *event) +{ + int err = 0; + + switch (event->attr.type) { + case PERF_TYPE_RAW: + case PERF_TYPE_HARDWARE: + case PERF_TYPE_HW_CACHE: + break; + + default: + return -ENOENT; + } + + if (!mipspmu || event->cpu >= nr_cpumask_bits || + (event->cpu >= 0 && !cpu_online(event->cpu))) + return -ENODEV; + + if (!atomic_inc_not_zero(&active_events)) { + if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) { + atomic_dec(&active_events); + return -ENOSPC; + } + + mutex_lock(&pmu_reserve_mutex); + if (atomic_read(&active_events) == 0) + err = mipspmu_get_irq(); + + if (!err) + atomic_inc(&active_events); + mutex_unlock(&pmu_reserve_mutex); + } + + if (err) + return err; + + err = __hw_perf_event_init(event); + if (err) + hw_perf_event_destroy(event); + + return err; +} + +static struct pmu pmu = { + .pmu_enable = mipspmu_enable, + .pmu_disable = mipspmu_disable, + .event_init = mipspmu_event_init, + .add = mipspmu_add, + .del = mipspmu_del, + .start = mipspmu_start, + .stop = mipspmu_stop, + .read = mipspmu_read, +}; + static inline unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) { @@ -409,73 +513,6 @@ static int validate_group(struct perf_event *event) return 0; } -/* - * mipsxx/rm9000/loongson2 have different performance counters, they have - * specific low-level init routines. - */ -static void reset_counters(void *arg); -static int __hw_perf_event_init(struct perf_event *event); - -static void hw_perf_event_destroy(struct perf_event *event) -{ - if (atomic_dec_and_mutex_lock(&active_events, - &pmu_reserve_mutex)) { - /* - * We must not call the destroy function with interrupts - * disabled. - */ - on_each_cpu(reset_counters, - (void *)(long)mipspmu->num_counters, 1); - mipspmu_free_irq(); - mutex_unlock(&pmu_reserve_mutex); - } -} - -const struct pmu *hw_perf_event_init(struct perf_event *event) -{ - int err = 0; - - if (!mipspmu || event->cpu >= nr_cpumask_bits || - (event->cpu >= 0 && !cpu_online(event->cpu))) - return ERR_PTR(-ENODEV); - - if (!atomic_inc_not_zero(&active_events)) { - if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) { - atomic_dec(&active_events); - return ERR_PTR(-ENOSPC); - } - - mutex_lock(&pmu_reserve_mutex); - if (atomic_read(&active_events) == 0) - err = mipspmu_get_irq(); - - if (!err) - atomic_inc(&active_events); - mutex_unlock(&pmu_reserve_mutex); - } - - if (err) - return ERR_PTR(err); - - err = __hw_perf_event_init(event); - if (err) - hw_perf_event_destroy(event); - - return err ? ERR_PTR(err) : &pmu; -} - -void hw_perf_enable(void) -{ - if (mipspmu) - mipspmu->start(); -} - -void hw_perf_disable(void) -{ - if (mipspmu) - mipspmu->stop(); -} - /* This is needed by specific irq handlers in perf_event_*.c */ static void handle_associated_event(struct cpu_hw_events *cpuc, diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index fa00edc..c9406d6 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1045,6 +1045,8 @@ init_hw_perf_events(void) "CPU, irq %d%s\n", mipspmu->name, counters, irq, irq < 0 ? " (share with timer interrupt)" : ""); + perf_pmu_register(&pmu); + return 0; } arch_initcall(init_hw_perf_events); -- 1.7.1 From dengcheng.zhu@gmail.com Thu Nov 18 08:02:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 08:02:53 +0100 (CET) Received: from mail-pv0-f177.google.com ([74.125.83.177]:37560 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492046Ab0KRHBs (ORCPT ); Thu, 18 Nov 2010 08:01:48 +0100 Received: by mail-pv0-f177.google.com with SMTP id 7so775496pvg.36 for ; Wed, 17 Nov 2010 23:01:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=wEmISudtWgUNsGJO7Ud6NE/7oDQg5mk5R0OoZg7vT50=; b=HtC6WNaGQ/PNrhsTvOJBFz1ntSVIMTnuzt3LNoe+DO0BCd+FK7ZRQL51LbLgmPQkCz QU6TdkSX8F7O5433vBa8jFJvHiIlxqSqx26ZcGLV9nNGBBNo5MdFXp/uVkQ2uhci9gGa bOlC11dij3s4D/MieGxwyvVjNJdkdzfxac4gE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=KYtDo8E+v5CWKjaZcZZ0JATVjxOI0YklUF3HkMBccKj9SsqN4L79MlucIGxtQRmu07 SnA9ba3zR1jrvMAImrV3k0Jr/xL3KFuMn9NDHFrMWUHT31Byd0wT/0m9FjDxWYF/k/u+ UQDmyoQbKwACyBEXohscc7z3V77wZUFKHv7PU= Received: by 10.142.109.12 with SMTP id h12mr202873wfc.31.1290063707807; Wed, 17 Nov 2010 23:01:47 -0800 (PST) Received: from localhost.localdomain ([210.13.118.102]) by mx.google.com with ESMTPS id w27sm81044wfd.14.2010.11.17.23.01.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 17 Nov 2010 23:01:46 -0800 (PST) From: Deng-Cheng Zhu To: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, dengcheng.zhu@gmail.com Subject: [PATCH 4/5] MIPS/Perf-events: Work with the new callchain interface Date: Thu, 18 Nov 2010 14:56:40 +0800 Message-Id: <1290063401-25440-5-git-send-email-dengcheng.zhu@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28410 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips This is the MIPS part of the following commits by Frederic Weisbecker: f72c1a931e311bb7780fee19e41a89ac42cab50e perf: Factorize callchain context handling 56962b4449af34070bb1994621ef4f0265eed4d8 perf: Generalize some arch callchain code 70791ce9ba68a5921c9905ef05d23f62a90bc10c perf: Generalize callchain_store() c1a65932fd7216fdc9a0db8bbffe1d47842f862c perf: Drop unappropriate tests on arch callchains Signed-off-by: Deng-Cheng Zhu --- arch/mips/kernel/perf_event.c | 63 ++++------------------------------------- 1 files changed, 6 insertions(+), 57 deletions(-) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index 9c6442a..345232a 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -533,21 +533,13 @@ handle_associated_event(struct cpu_hw_events *cpuc, #include "perf_event_mipsxx.c" /* Callchain handling code. */ -static inline void -callchain_store(struct perf_callchain_entry *entry, - u64 ip) -{ - if (entry->nr < PERF_MAX_STACK_DEPTH) - entry->ip[entry->nr++] = ip; -} /* * Leave userspace callchain empty for now. When we find a way to trace * the user stack callchains, we add here. */ -static void -perf_callchain_user(struct pt_regs *regs, - struct perf_callchain_entry *entry) +void perf_callchain_user(struct perf_callchain_entry *entry, + struct pt_regs *regs) { } @@ -560,23 +552,21 @@ static void save_raw_perf_callchain(struct perf_callchain_entry *entry, while (!kstack_end(sp)) { addr = *sp++; if (__kernel_text_address(addr)) { - callchain_store(entry, addr); + perf_callchain_store(entry, addr); if (entry->nr >= PERF_MAX_STACK_DEPTH) break; } } } -static void -perf_callchain_kernel(struct pt_regs *regs, - struct perf_callchain_entry *entry) +void perf_callchain_kernel(struct perf_callchain_entry *entry, + struct pt_regs *regs) { unsigned long sp = regs->regs[29]; #ifdef CONFIG_KALLSYMS unsigned long ra = regs->regs[31]; unsigned long pc = regs->cp0_epc; - callchain_store(entry, PERF_CONTEXT_KERNEL); if (raw_show_trace || !__kernel_text_address(pc)) { unsigned long stack_page = (unsigned long)task_stack_page(current); @@ -586,53 +576,12 @@ perf_callchain_kernel(struct pt_regs *regs, return; } do { - callchain_store(entry, pc); + perf_callchain_store(entry, pc); if (entry->nr >= PERF_MAX_STACK_DEPTH) break; pc = unwind_stack(current, &sp, pc, &ra); } while (pc); #else - callchain_store(entry, PERF_CONTEXT_KERNEL); save_raw_perf_callchain(entry, sp); #endif } - -static void -perf_do_callchain(struct pt_regs *regs, - struct perf_callchain_entry *entry) -{ - int is_user; - - if (!regs) - return; - - is_user = user_mode(regs); - - if (!current || !current->pid) - return; - - if (is_user && current->state != TASK_RUNNING) - return; - - if (!is_user) { - perf_callchain_kernel(regs, entry); - if (current->mm) - regs = task_pt_regs(current); - else - regs = NULL; - } - if (regs) - perf_callchain_user(regs, entry); -} - -static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); - -struct perf_callchain_entry * -perf_callchain(struct pt_regs *regs) -{ - struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry); - - entry->nr = 0; - perf_do_callchain(regs, entry); - return entry; -} -- 1.7.1 From dengcheng.zhu@gmail.com Thu Nov 18 08:03:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 08:03:16 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:35419 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492049Ab0KRHBy (ORCPT ); Thu, 18 Nov 2010 08:01:54 +0100 Received: by pwj8 with SMTP id 8so783632pwj.36 for ; Wed, 17 Nov 2010 23:01:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=zeFJ/G7Zo4m6FcSjcQ1z2PiISXw/VUK5Czf4Fr/d1/M=; b=n/IO6gPcdACUY/XnXqTYa3D78AyalnReRPWxczb6cQLU7jE5kJCaKQmMzZAHUMCP1U bZsP7Z9vaQkD4HtqkuZ6ulyZ33NeNE8YxFBkU/0s0Jpi0ajCaocYtmMLD2mYHQ+OVEFC KtKTCIpcx7nHGOCIlyvDJGoR5i7MKvT03yds0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=AWj0KK4qaI847m0nXW8lWlwSxpJSHe3g1JwdNDtOI5/s2mykmyUh2+NCzhMs8Pvim7 1lLGXVr5O32fAxmeQXtXkkDNeqJD8y9dDitzN7jR0q8+s2GTvu30XtZREDRM14/CYSqL a/sYjeU4OBd8DS/vIVsCZCx40SHWMI1QsbjrQ= Received: by 10.142.223.3 with SMTP id v3mr205710wfg.12.1290063702640; Wed, 17 Nov 2010 23:01:42 -0800 (PST) Received: from localhost.localdomain ([210.13.118.102]) by mx.google.com with ESMTPS id w27sm81044wfd.14.2010.11.17.23.01.37 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 17 Nov 2010 23:01:41 -0800 (PST) From: Deng-Cheng Zhu To: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, dengcheng.zhu@gmail.com Subject: [PATCH 3/5] MIPS/Perf-events: Check event state in validate_event() Date: Thu, 18 Nov 2010 14:56:39 +0800 Message-Id: <1290063401-25440-4-git-send-email-dengcheng.zhu@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28411 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Ignore events that are not for this PMU or are in off/error state. Signed-off-by: Deng-Cheng Zhu --- arch/mips/kernel/perf_event.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index 1ee44a3..9c6442a 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -486,7 +486,7 @@ static int validate_event(struct cpu_hw_events *cpuc, { struct hw_perf_event fake_hwc = event->hw; - if (event->pmu && event->pmu != &pmu) + if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) return 0; return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; -- 1.7.1 From dengcheng.zhu@gmail.com Thu Nov 18 08:03:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 08:03:39 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:64229 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492040Ab0KRHB7 (ORCPT ); Thu, 18 Nov 2010 08:01:59 +0100 Received: by pwj8 with SMTP id 8so783650pwj.36 for ; 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Wed, 17 Nov 2010 23:01:52 -0800 (PST) From: Deng-Cheng Zhu To: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, will.deacon@arm.com Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com, dengcheng.zhu@gmail.com Subject: [PATCH 5/5] MIPS/Perf-events: Use unsigned delta for right shift in event update Date: Thu, 18 Nov 2010 14:56:41 +0800 Message-Id: <1290063401-25440-6-git-send-email-dengcheng.zhu@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28412 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Leverage the commit for ARM by Will Deacon: 446a5a8b1eb91a6990e5c8fe29f14e7a95b69132 ARM: 6205/1: perf: ensure counter delta is treated as unsigned Signed-off-by: Deng-Cheng Zhu --- arch/mips/kernel/perf_event.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index 345232a..0f1cdf5 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -169,7 +169,7 @@ static void mipspmu_event_update(struct perf_event *event, unsigned long flags; int shift = 64 - TOTAL_BITS; s64 prev_raw_count, new_raw_count; - s64 delta; + u64 delta; again: prev_raw_count = local64_read(&hwc->prev_count); -- 1.7.1 From anoop.pa@gmail.com Thu Nov 18 09:05:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 09:05:59 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:41039 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492370Ab0KRIFu (ORCPT ); Thu, 18 Nov 2010 09:05:50 +0100 Received: by gyf1 with SMTP id 1so1793033gyf.36 for ; Thu, 18 Nov 2010 00:05:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=ajiYjWnuGVkXQOyYQEjdy3lao1fTBTDkTyWkesw02wY=; b=VOzKsYzu3yCRIFevrNk9xRYYY1MKw/d+P4fsR2XmZ4ctEuAZAa3c/RvP8REPTyqrf5 fWrAcZKwoF6K/VXJSROAe5ABOpQmVYubtEWOISVAhGi0me+ebgeMAkobyloU1TOBJP1F 1uGaSDoaqN9+zczX4fMXtuZF7HrdFAMDdoUoc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=eOOXa9anJHTWSXZz/mILrhPMd6Tbf5X7Nt8fZWiuuwJYc0gktdQWNlXUchIAdoBpPr SCWgMuiRy3M3Y5i4HsyqJZM4fZX64Qi//zUtR9fnnu87VPCJPLb3k1SxxAKMqGcs41fp fS4T89nmB2MlGvVpaQ5/LLPkCTio1KKAcr6Tg= Received: by 10.90.15.31 with SMTP id 31mr596998ago.10.1290067542761; Thu, 18 Nov 2010 00:05:42 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id j21sm84478yha.12.2010.11.18.00.05.39 (version=SSLv3 cipher=RC4-MD5); Thu, 18 Nov 2010 00:05:42 -0800 (PST) Subject: [PATCH] Select R4K timer lib for all MSP platforms From: Anoop P A To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Date: Thu, 18 Nov 2010 13:42:28 +0530 Message-ID: <1290067948.9091.14.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28413 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips >From c872cbbe5f475d3bb3cb7f821270cb466eead1f7 Mon Sep 17 00:00:00 2001 From: Anoop P A Signed-off-by: Anoop P A Date: Thu, 18 Nov 2010 01:33:36 +0530 Subject: [PATCH] Select R4K timer lib for all MSP platforms --- arch/mips/Kconfig | 2 ++ arch/mips/pmc-sierra/Kconfig | 4 ---- arch/mips/pmc-sierra/msp71xx/msp_time.c | 2 +- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7fc6bd1..168cdbe 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -316,6 +316,8 @@ config PNX8550_STB810 config PMC_MSP bool "PMC-Sierra MSP chipsets" depends on EXPERIMENTAL + select CEVT_R4K + select CSRC_R4K select DMA_NONCOHERENT select SWAP_IO_SPACE select NO_EXCEPT_FILL diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig index c139988..8d79849 100644 --- a/arch/mips/pmc-sierra/Kconfig +++ b/arch/mips/pmc-sierra/Kconfig @@ -4,15 +4,11 @@ choice config PMC_MSP4200_EVAL bool "PMC-Sierra MSP4200 Eval Board" - select CEVT_R4K - select CSRC_R4K select IRQ_MSP_SLP select HW_HAS_PCI config PMC_MSP4200_GW bool "PMC-Sierra MSP4200 VoIP Gateway" - select CEVT_R4K - select CSRC_R4K select IRQ_MSP_SLP select HW_HAS_PCI diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index cca64e1..01df84c 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -81,7 +81,7 @@ void __init plat_time_init(void) mips_hpt_frequency = cpu_rate/2; } -unsigned int __init get_c0_compare_int(void) +unsigned int __cpuinit get_c0_compare_int(void) { return MSP_INT_VPE0_TIMER; } -- 1.7.0.4 From Will.Deacon@arm.com Thu Nov 18 10:28:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 10:28:15 +0100 (CET) Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:47512 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492402Ab0KRJ2G (ORCPT ); Thu, 18 Nov 2010 10:28:06 +0100 Received: from cam-owa1.Emea.Arm.com (cam-owa1.emea.arm.com [10.1.255.62]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id oAI9LwF9018119; Thu, 18 Nov 2010 09:21:58 GMT Received: from [10.1.68.185] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Thu, 18 Nov 2010 09:27:42 +0000 Subject: Re: [PATCH 5/5] MIPS/Perf-events: Use unsigned delta for right shift in event update From: Will Deacon To: Deng-Cheng Zhu Cc: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com In-Reply-To: <1290063401-25440-6-git-send-email-dengcheng.zhu@gmail.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-6-git-send-email-dengcheng.zhu@gmail.com> Content-Type: text/plain; charset="UTF-8" Date: Thu, 18 Nov 2010 09:27:38 +0000 Message-ID: <1290072458.18450.1.camel@e102144-lin.cambridge.arm.com> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 18 Nov 2010 09:27:42.0299 (UTC) FILETIME=[D9BE1AB0:01CB8702] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28414 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: will.deacon@arm.com Precedence: bulk X-list: linux-mips On Thu, 2010-11-18 at 06:56 +0000, Deng-Cheng Zhu wrote: > Leverage the commit for ARM by Will Deacon: > > 446a5a8b1eb91a6990e5c8fe29f14e7a95b69132 > ARM: 6205/1: perf: ensure counter delta is treated as unsigned > > Signed-off-by: Deng-Cheng Zhu > --- > arch/mips/kernel/perf_event.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c > index 345232a..0f1cdf5 100644 > --- a/arch/mips/kernel/perf_event.c > +++ b/arch/mips/kernel/perf_event.c > @@ -169,7 +169,7 @@ static void mipspmu_event_update(struct perf_event *event, > unsigned long flags; > int shift = 64 - TOTAL_BITS; > s64 prev_raw_count, new_raw_count; > - s64 delta; > + u64 delta; > > again: > prev_raw_count = local64_read(&hwc->prev_count); > -- > 1.7.1 Acked-by: Will Deacon You might also want to look at commit 65b4711f if you based the MIPS port on the old ARM code. Thanks, Will From anoop.pa@gmail.com Thu Nov 18 11:26:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 11:26:14 +0100 (CET) Received: from mail-gx0-f177.google.com ([209.85.161.177]:37737 "EHLO mail-gx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492426Ab0KRK0K (ORCPT ); Thu, 18 Nov 2010 11:26:10 +0100 Received: by gxk25 with SMTP id 25so1857880gxk.36 for ; Thu, 18 Nov 2010 02:26:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=RkF9Pb+EhzaCqM96K97fdZOnFUk+Uf97VaOx2J+PsXc=; b=rrppKAFxnPoLIg5dZbEa7OPe7ESTM3p/BCxrkR9RBXAr/QD5kX/cRihm5LWIvnO+8m a+d7Fo0Y6wg88yxOnKsMWvzqNGkHEb/55GsrUZ7GXahSzPjNi3mBH8GJD0qgkNs6xtJ1 dQNDcT8VXvjIJe3n+sPGboKRV5C6ZqbjUrH+o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=lQaYczvhXqDwqhmAHI0NwdZgi5rLifXyYrZJ3d+vtM2fmODQKmeZ8OM9nGlYYNrlC6 GL8qkk+sB6TQxoNGovB/h+Ctz5G4+HSCFjf+fzV50arBdsWOAEcYysoMvYxX+8A+dt1s cOLkjmSuVuezbqlLyr3Wweic2Do6VhnNv66+0= Received: by 10.150.228.12 with SMTP id a12mr891817ybh.313.1290075964258; Thu, 18 Nov 2010 02:26:04 -0800 (PST) Received: from [172.16.48.51] ([59.160.135.215]) by mx.google.com with ESMTPS id v12sm196823ybk.11.2010.11.18.02.26.00 (version=SSLv3 cipher=RC4-MD5); Thu, 18 Nov 2010 02:26:03 -0800 (PST) Subject: [PATCH] Fix MSP71xx bpci interrupt handler return value From: Anoop P A To: Ralf Baechle , Ben Hutchings , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Date: Thu, 18 Nov 2010 16:02:50 +0530 Message-ID: <1290076370.31469.1.camel@paanoop1-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28415 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anoop.pa@gmail.com Precedence: bulk X-list: linux-mips Signed-off-by: Anoop P A --- arch/mips/pci/ops-pmcmsp.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c index b7c03d8..68798f8 100644 --- a/arch/mips/pci/ops-pmcmsp.c +++ b/arch/mips/pci/ops-pmcmsp.c @@ -308,7 +308,7 @@ static struct resource pci_mem_resource = { * RETURNS: PCIBIOS_SUCCESSFUL - success * ****************************************************************************/ -static int bpci_interrupt(int irq, void *dev_id) +static irqreturn_t bpci_interrupt(int irq, void *dev_id) { struct msp_pci_regs *preg = (void *)PCI_BASE_REG; unsigned int stat = preg->if_status; @@ -326,7 +326,7 @@ static int bpci_interrupt(int irq, void *dev_id) /* write to clear all asserted interrupts */ preg->if_status = stat; - return PCIBIOS_SUCCESSFUL; + return IRQ_HANDLED; } /***************************************************************************** -- 1.7.0.4 From Andrei.Ardelean@idt.com Thu Nov 18 19:55:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 19:56:10 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:59541 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492603Ab0KRSzv convert rfc822-to-8bit (ORCPT ); Thu, 18 Nov 2010 19:55:51 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oAIItiB7020580 for ; Thu, 18 Nov 2010 10:55:44 -0800 Received: from corpml3.corp.idt.com (corpml3.corp.idt.com [157.165.140.25]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oAIIthBh024441 for ; Thu, 18 Nov 2010 10:55:43 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml3.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oAIItfr24175 for ; Thu, 18 Nov 2010 10:55:42 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: The new "real" console doesn't display printk() messages like "early" console! Date: Thu, 18 Nov 2010 10:55:39 -0800 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: The new "real" console doesn't display printk() messages like "early" console! Thread-Index: AcuHUjGIdgCnRPbVSCuuNdXyXpkKCw== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28416 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, I am porting MIPS Linux on a new platform and my kernel crashes after console is switched from early console to the new real console (8250.c) I see messages displayed using the new console like "Freeing prom memory: 956k freed" (this is the last message I have) so the new console is up and running. My problem is that the new console doesn't display printk() messages. The early console displays all printk() messages. What do I need to set at compiling time that the new console to display printk() messages like early console? Thanks, Andrei From sshtylyov@mvista.com Thu Nov 18 20:22:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 20:22:15 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:57144 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492617Ab0KRTWM (ORCPT ); Thu, 18 Nov 2010 20:22:12 +0100 Received: by eyd9 with SMTP id 9so2192443eyd.36 for ; Thu, 18 Nov 2010 11:22:10 -0800 (PST) Received: by 10.213.105.145 with SMTP id t17mr4046964ebo.65.1290108130501; Thu, 18 Nov 2010 11:22:10 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id b52sm686275eei.1.2010.11.18.11.22.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 18 Nov 2010 11:22:09 -0800 (PST) Message-ID: <4CE57C92.6030705@mvista.com> Date: Thu, 18 Nov 2010 22:20:50 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: "Ardelean, Andrei" CC: linux-mips@linux-mips.org Subject: Re: The new "real" console doesn't display printk() messages like "early" console! References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28417 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Ardelean, Andrei wrote: > I am porting MIPS Linux on a new platform and my kernel crashes after > console is switched from early console to the new real console (8250.c) > I see messages displayed using the new console like "Freeing prom > memory: 956k freed" (this is the last message I have) so the new console > is up and running. > My problem is that the new console doesn't display printk() messages. > The early console displays all printk() messages. > What do I need to set at compiling time that the new console to display > printk() messages like early console? Have you specified "console=ttyS, as the kernel parameter? > Thanks, > Andrei WBR, Sergei From wg@grandegger.com Thu Nov 18 20:58:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 20:58:05 +0100 (CET) Received: from mail-out.m-online.net ([212.18.0.10]:33660 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492002Ab0KRT6C (ORCPT ); Thu, 18 Nov 2010 20:58:02 +0100 Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id B4AF1188B584; Thu, 18 Nov 2010 20:58:01 +0100 (CET) X-Auth-Info: nrImGtJdgx8Uo6j1nWM7d3eYPwqfzyuI5gYk7V3HdlE= Received: from lancy.mylan.de (p4FE6480F.dip.t-dialin.net [79.230.72.15]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 0F0991C00173; Thu, 18 Nov 2010 20:58:00 +0100 (CET) Message-ID: <4CE58593.50509@grandegger.com> Date: Thu, 18 Nov 2010 20:59:15 +0100 From: Wolfgang Grandegger User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100907 Fedora/3.0.7-1.fc12 Thunderbird/3.0.7 MIME-Version: 1.0 To: Linux-MIPS CC: Netdev@vger.kernel.org, Florian Fainelli Subject: alchemy/gpr: au1000_eth regression with v2.6.37rc2 X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28418 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips Hello, I just realized that the v2.6.37-rc2 kernel does not boot any more on the Alchemy GPR board. It works fine with v2.6.36. It hangs in the probe function of the au1000_eth driver when probing the second ethernet port (eth1): au1000_eth_mii: probed au1000-eth au1000-eth.0: (unregistered net_device): attached PHY driver [Generic PHY] (mii_bus:phy_addr=0:00, irq=-1) au1000-eth au1000-eth.0: eth0: Au1xx0 Ethernet found at 0x10500000, irq 35 au1000_eth: au1000_eth version 1.7 Pete Popov ... hangs ... Similar messages should follow for eth1. I narrowed down (bisect'ed) the problem to commit: commit d0e7cb5d401695809ba8c980124ab1d8c66efc8b Author: Florian Fainelli Date: Wed Sep 8 11:15:13 2010 +0000 au1000-eth: remove volatiles, switch to I/O accessors Remove all the volatile keywords where they were used, switch to using the proper readl/writel accessors. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller The kernel actually hangs when accessing "&aup->mac->mii_control" in au1000_mdio_read(), but only for eth1. Any idea what does go wrong? In principle, I do not want to access the MII regs of the MAC because eth0 and eth1 are connected to switches. But that's not possible, even with "aup->phy_static_config=1" and "aup->phy_addr=0". TIA, Wolfgang. From Andrei.Ardelean@idt.com Thu Nov 18 21:04:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 21:05:00 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:35054 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491992Ab0KRUE5 convert rfc822-to-8bit (ORCPT ); Thu, 18 Nov 2010 21:04:57 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oAIK4oU3025526; Thu, 18 Nov 2010 12:04:50 -0800 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oAIK4oX7001979; Thu, 18 Nov 2010 12:04:50 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oAIK4n116645; Thu, 18 Nov 2010 12:04:49 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: The new "real" console doesn't display printk() messages like "early" console! Date: Thu, 18 Nov 2010 12:04:26 -0800 Message-ID: In-Reply-To: <4CE57C92.6030705@mvista.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: The new "real" console doesn't display printk() messages like "early" console! Thread-Index: AcuHWbAJ3WMOvi3FT0K1Uo59L9wjuwAANU5A References: <4CE57C92.6030705@mvista.com> From: "Ardelean, Andrei" To: "Sergei Shtylyov" Cc: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28419 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi Sergei, I specified that when the bootloader calls the kernel and I did see that the baudrate is correct and I have some messages but when the system is crashing I cannot see printk messages. For instance, I step with JTAG and I can see that printk(KERNEL_WARNING "unable to open initial console") is called but on the terminal I cannot see the message. The same, die() is called but there is no messages on UART terminal. Thanks, Andrei -----Original Message----- From: Sergei Shtylyov [mailto:sshtylyov@mvista.com] Sent: Thursday, November 18, 2010 2:21 PM To: Ardelean, Andrei Cc: linux-mips@linux-mips.org Subject: Re: The new "real" console doesn't display printk() messages like "early" console! Hello. Ardelean, Andrei wrote: > I am porting MIPS Linux on a new platform and my kernel crashes after > console is switched from early console to the new real console (8250.c) > I see messages displayed using the new console like "Freeing prom > memory: 956k freed" (this is the last message I have) so the new console > is up and running. > My problem is that the new console doesn't display printk() messages. > The early console displays all printk() messages. > What do I need to set at compiling time that the new console to display > printk() messages like early console? Have you specified "console=ttyS, as the kernel parameter? > Thanks, > Andrei WBR, Sergei From mendoza.ricardo@gmail.com Thu Nov 18 22:21:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 22:21:09 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:53870 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490955Ab0KRVVG (ORCPT ); Thu, 18 Nov 2010 22:21:06 +0100 Received: by ewy19 with SMTP id 19so2301365ewy.36 for ; Thu, 18 Nov 2010 13:21:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type; bh=AqQpor/PyVvtH2gllAhYZMfb+BscoMhO16i5Nh8SSIg=; b=I8/c3eqPuKq9+Nxz6a8fxRZvbBieiHQ6mNMPeJhG0I4dm3DO1dyyl0O/XoU6YjgEnm mOUH3RXmivbPSgZxUuKwtoJ9pHhlVqJAs0t3INYLiWEwzQFfQq35ix9kLI2DegSoUcHm sYuSU4nAo3bLaUU5CxcF1gmgHJG45ceMEAgsE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; b=ZeJYWCsvnH/znrtsxjcUsqonqg/GRJ5eeqV63Nxw8CsBziZcRvaSRJWJUc5o3wbCNT secaf6NoOxQW7zvyG8DIMREvGYeQeMa2AibgBlKaPDQWT2VxNWmgjoTCd4JkL1EmrUGD Wd175aQkqyZpDoTpeMHE8/PzY4hhBuXfaoZvI= MIME-Version: 1.0 Received: by 10.216.28.77 with SMTP id f55mr29133wea.91.1290115266223; Thu, 18 Nov 2010 13:21:06 -0800 (PST) Received: by 10.216.91.8 with HTTP; Thu, 18 Nov 2010 13:21:06 -0800 (PST) In-Reply-To: References: <4CE57C92.6030705@mvista.com> Date: Thu, 18 Nov 2010 21:21:06 +0000 X-Google-Sender-Auth: a3tyewqjAZn6z2_50a5ZE_2QhFk Message-ID: Subject: Re: The new "real" console doesn't display printk() messages like "early" console! From: Ricardo Mendoza To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28420 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ricmm@gentoo.org Precedence: bulk X-list: linux-mips On Thu, Nov 18, 2010 at 8:04 PM, Ardelean, Andrei wrote: > I specified that when the bootloader calls the kernel and I did see that > the baudrate is correct and I have some messages but when the system is > crashing I cannot see printk messages. For instance, I step with JTAG > and I can see that printk(KERNEL_WARNING "unable to open initial > console") is called but on the terminal I cannot see the message. The > same, die() is called but there is no messages on UART terminal. You say you are porting to a new system, perhaps you didn't set up your 8250 platform device. Most boards will have an example for you in the tree. Ricardo From Andrei.Ardelean@idt.com Thu Nov 18 23:01:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 23:01:38 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:40939 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490955Ab0KRWBf convert rfc822-to-8bit (ORCPT ); Thu, 18 Nov 2010 23:01:35 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oAIM1JjU001105; Thu, 18 Nov 2010 14:01:19 -0800 Received: from corpml3.corp.idt.com (corpml3.corp.idt.com [157.165.140.25]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oAIM1IDj013242; Thu, 18 Nov 2010 14:01:18 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml3.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oAIM1Hf18075; Thu, 18 Nov 2010 14:01:17 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: The new "real" console doesn't display printk() messages like "early" console! Date: Thu, 18 Nov 2010 14:01:06 -0800 Message-ID: In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: The new "real" console doesn't display printk() messages like "early" console! Thread-Index: AcuHag9+u82cHfU/Q72jKCa6Mm+O3AAAXMcQ References: <4CE57C92.6030705@mvista.com> From: "Ardelean, Andrei" To: "Ricardo Mendoza" Cc: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28421 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi Ricardo, I implemented serial platform driver taking as model serial.c from cavium-octeon. Here is my code: /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2004-2007 Cavium Networks */ #include #include #include #include #include #include #include #include #include #include #ifdef CONFIG_GDB_CONSOLE #define DEBUG_UART 0 #else #define DEBUG_UART 1 #endif unsigned int gd_serial_in(struct uart_port *up, int offset) { int rv = inl((unsigned int)(up->membase + (offset << 2))); if (offset == UART_IIR && (rv & 0xf) == 7) { /* Busy interrupt, read the USR (39) and try again. */ inl((unsigned int)(up->membase + (39 << 2))); rv = inl((unsigned int)(up->membase + (offset << 2))); } return rv; } void gd_serial_out(struct uart_port *up, int offset, int value) { outl( value & 0xff, (unsigned int)(up->membase + (offset << 2))); } /* * Allocated in .bss, so it is all zeroed. */ #define GD_MAX_UARTS 1 static struct plat_serial8250_port gd_uart8250_data[GD_MAX_UARTS + 1]; static struct platform_device gd_uart8250_device = { .name = "serial8250", .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = gd_uart8250_data, }, }; static void __init gd_uart_set_common(struct plat_serial8250_port *p) { p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; p->type = PORT_GD; p->iotype = UPIO_MEM; p->regshift = 2; /* I/O addresses are every 4 bytes */ p->uartclk = UART_CLK; p->serial_in = gd_serial_in; p->serial_out = gd_serial_out; } static int __init gd_serial_init(void) { int enable_uart0; struct plat_serial8250_port *p; enable_uart0 = 1; p = gd_uart8250_data; if (enable_uart0) { /* Add a ttyS device for hardware uart 0 */ gd_uart_set_common(p); p->membase = (void *) offMCU_UART_THR_OR_RBR_OR_DLL; p->mapbase = offMCU_UART_THR_OR_RBR_OR_DLL; p->irq = MIPSCPU_INT_UART; p++; } return platform_device_register(&gd_uart8250_device); } device_initcall(gd_serial_init); ------------------------------------------------------------------------ ----------------------- Thanks, Andrei -----Original Message----- From: mendoza.ricardo@gmail.com [mailto:mendoza.ricardo@gmail.com] On Behalf Of Ricardo Mendoza Sent: Thursday, November 18, 2010 4:21 PM To: Ardelean, Andrei Cc: linux-mips@linux-mips.org Subject: Re: The new "real" console doesn't display printk() messages like "early" console! On Thu, Nov 18, 2010 at 8:04 PM, Ardelean, Andrei wrote: > I specified that when the bootloader calls the kernel and I did see that > the baudrate is correct and I have some messages but when the system is > crashing I cannot see printk messages. For instance, I step with JTAG > and I can see that printk(KERNEL_WARNING "unable to open initial > console") is called but on the terminal I cannot see the message. The > same, die() is called but there is no messages on UART terminal. You say you are porting to a new system, perhaps you didn't set up your 8250 platform device. Most boards will have an example for you in the tree. Ricardo From f.fainelli@gmail.com Thu Nov 18 23:28:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2010 23:28:08 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:48685 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490979Ab0KRW2F convert rfc822-to-8bit (ORCPT ); Thu, 18 Nov 2010 23:28:05 +0100 Received: by wyf22 with SMTP id 22so3828452wyf.36 for ; Thu, 18 Nov 2010 14:28:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:reply-to:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=eaF+hH9d4AqKT9AZZdB4z0IVuVxwWNp1wfWdGIKkc3A=; b=fH/AY23GeWRVKUstdPkGuGRAHUOdvouJ3PdFNfJnf9w+7aVjW/x4vtNN9m9UCzgR4R PpGD5EalmM9UXIelCfHypynBXMRzCf3gxPdOuzM0tOrIOD7wG4x1iOxxIEL252SaDbrE 71+XiJKgxFnCrmOVbhAwGoL3Aefr7fKQuODk0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:reply-to:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=Ob5ptQqLciYNdiP0hTvEOzIh3DXESZvUeFdeHnMSqcs+kLrB/n5b6AtL2P3KdYUsbz O/E3ZP52G2i5jitPH4R/CZLhscHyItvJUafVgw5EgHkWfLn/VpSPd81y09yos9WDJDGZ CeIrOZKnbhV9IA4j/JKATvrj4q0Fcvmsn5D1g= Received: by 10.216.30.67 with SMTP id j45mr176320wea.99.1290119279796; Thu, 18 Nov 2010 14:27:59 -0800 (PST) Received: from lenovo.localnet (fbx.mimichou.net [82.236.225.16]) by mx.google.com with ESMTPS id x59sm480564weq.38.2010.11.18.14.27.57 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 18 Nov 2010 14:27:58 -0800 (PST) From: Florian Fainelli Reply-To: Florian Fainelli To: Wolfgang Grandegger Subject: Re: alchemy/gpr: au1000_eth regression with v2.6.37rc2 Date: Thu, 18 Nov 2010 23:30:07 +0100 User-Agent: KMail/1.13.5 (Linux/2.6.36-trunk-amd64; KDE/4.4.5; x86_64; ; ) Cc: "Linux-MIPS" , Netdev@vger.kernel.org References: <4CE58593.50509@grandegger.com> In-Reply-To: <4CE58593.50509@grandegger.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Message-Id: <201011182330.08488.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28422 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hello Wolfgang, Le Thursday 18 November 2010 20:59:15, Wolfgang Grandegger a écrit : > Hello, > > I just realized that the v2.6.37-rc2 kernel does not boot any more on > the Alchemy GPR board. It works fine with v2.6.36. It hangs in the > probe function of the au1000_eth driver when probing the second > ethernet port (eth1): > > au1000_eth_mii: probed > au1000-eth au1000-eth.0: (unregistered net_device): attached PHY driver > [Generic PHY] (mii_bus:phy_addr=0:00, irq=-1) au1000-eth au1000-eth.0: > eth0: Au1xx0 Ethernet found at 0x10500000, irq 35 au1000_eth: au1000_eth > version 1.7 Pete Popov ... hangs ... > > Similar messages should follow for eth1. I narrowed down (bisect'ed) the > problem to commit: > > commit d0e7cb5d401695809ba8c980124ab1d8c66efc8b > Author: Florian Fainelli > Date: Wed Sep 8 11:15:13 2010 +0000 > > au1000-eth: remove volatiles, switch to I/O accessors > > Remove all the volatile keywords where they were used, switch to using > the proper readl/writel accessors. > > Signed-off-by: Florian Fainelli > Signed-off-by: David S. Miller > > The kernel actually hangs when accessing "&aup->mac->mii_control" in > au1000_mdio_read(), but only for eth1. Any idea what does go wrong? I do not understand so far while it hangs only for eth1. My device only has one ethernet MAC, so I could not notice the problem. Looking at this close, there are a couple of u32 const* usages in au1000_mdio_{read,write} which are looking wrong to me now. Can you try to remove these? > > In principle, I do not want to access the MII regs of the MAC because > eth0 and eth1 are connected to switches. But that's not possible, even > with "aup->phy_static_config=1" and "aup->phy_addr=0". If you think this is another issue, I will fix it in another patch. -- Florian From mendoza.ricardo@gmail.com Fri Nov 19 00:58:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 00:58:32 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:45057 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491000Ab0KRX63 (ORCPT ); Fri, 19 Nov 2010 00:58:29 +0100 Received: by wwj40 with SMTP id 40so1282020wwj.24 for ; Thu, 18 Nov 2010 15:58:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type; bh=z1V6lp1d5dM0VVUS7Oeyj9wBx+/KnEReAZYoroV1WgU=; b=iAl4vfDXQXLWk1KV+lw5f05iLjZ2iIDt2mW7EOp16GqozQs8w/sEfOwhOMjXr8s/6s XnGoOaztF9cEDTSkUdumze5vg64IXN25J2f6tZZOF+y3O+M8v3gKvD89ud0hoyxVpovx 6DJkRDfRmRAnMFcgJ/iMqPfLC6SNYA+zsEnfc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; b=VrvRfPA/TVNgZgv/FMhnD6C9qzMNpEb2r9CBWSlIg+sYh2rgUHNnJnDZQLjYjd8RRP Ep2a/V/DPh0C1VhhO1KGjAYhS741VvzFu/y+Ui/79oV2HjlQvWda0yb89kzdGcFcPqC6 2BpZpYoQARhNgIb8Ji3ULRXd0wkgrIgEjquz4= MIME-Version: 1.0 Received: by 10.216.38.71 with SMTP id z49mr173314wea.76.1290124703482; Thu, 18 Nov 2010 15:58:23 -0800 (PST) Received: by 10.216.91.8 with HTTP; Thu, 18 Nov 2010 15:58:23 -0800 (PST) In-Reply-To: References: <4CE57C92.6030705@mvista.com> Date: Thu, 18 Nov 2010 23:58:23 +0000 X-Google-Sender-Auth: l3MTMKawxjN1te2EiGtNSwoKjCE Message-ID: Subject: Re: The new "real" console doesn't display printk() messages like "early" console! From: Ricardo Mendoza To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28423 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ricmm@gentoo.org Precedence: bulk X-list: linux-mips On Thu, Nov 18, 2010 at 10:01 PM, Ardelean, Andrei wrote: > Hi Ricardo, > > I implemented serial platform driver taking as model serial.c from > cavium-octeon. > > Here is my code: > > ... Why use the Octeon code which has platform specific bits that might have nothing to do with your platform? Build up from the simple ones. Ricardo From dengcheng.zhu@gmail.com Fri Nov 19 08:17:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 08:17:17 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:63077 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491039Ab0KSHRN convert rfc822-to-8bit (ORCPT ); Fri, 19 Nov 2010 08:17:13 +0100 Received: by wwb34 with SMTP id 34so214371wwb.24 for ; Thu, 18 Nov 2010 23:17:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=717P+WGYG6KnRcP3Nk2/7bHuoWs4hZFdykzCeaGHs2U=; b=KGLYEeGAsxH2sAyJQNHbUbIraIbP4ILn2MMaU+/fZ0/k/qs7NJp+ZsYeNihDjSbdp5 mTYW771Q6VJwBMr1APT5cyUGAS/yTK/frm8DOtgr04pMvN3QlCneNxzOGivZaaiZD6b3 KG1ZRunWFtYjBuPiHTcy3ZNpMr8wSNuDfMJks= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=JB/MF0u9e9OvkSkEqnrXLax+vhU+qI9zxISy0218Mmu1nF16frdeUTszuw5GP/AmX1 WUHlfpRQsmRDzeKrn5Lqbc8qMqVPRyKFkKxYreXcDBA+GHqzPdYpJSZM2agckprbWrHY YT/Rn2U/wSqsIemE2BTsq2L6rCJISrXYV5b5U= MIME-Version: 1.0 Received: by 10.216.45.199 with SMTP id p49mr514217web.29.1290151021245; Thu, 18 Nov 2010 23:17:01 -0800 (PST) Received: by 10.216.236.138 with HTTP; Thu, 18 Nov 2010 23:16:38 -0800 (PST) In-Reply-To: <1290072458.18450.1.camel@e102144-lin.cambridge.arm.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-6-git-send-email-dengcheng.zhu@gmail.com> <1290072458.18450.1.camel@e102144-lin.cambridge.arm.com> Date: Fri, 19 Nov 2010 15:16:38 +0800 Message-ID: Subject: Re: [PATCH 5/5] MIPS/Perf-events: Use unsigned delta for right shift in event update From: Deng-Cheng Zhu To: Will Deacon Cc: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28424 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Thanks. The commit you pointed out was also in this patch set (#3). But I think the return value should stick to 0, not 1. Something out of my consideration? Deng-Cheng 2010/11/18 Will Deacon : > On Thu, 2010-11-18 at 06:56 +0000, Deng-Cheng Zhu wrote: >> Leverage the commit for ARM by Will Deacon: >> >> 446a5a8b1eb91a6990e5c8fe29f14e7a95b69132 >>         ARM: 6205/1: perf: ensure counter delta is treated as unsigned >> >> Signed-off-by: Deng-Cheng Zhu >> --- >>  arch/mips/kernel/perf_event.c |    2 +- >>  1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c >> index 345232a..0f1cdf5 100644 >> --- a/arch/mips/kernel/perf_event.c >> +++ b/arch/mips/kernel/perf_event.c >> @@ -169,7 +169,7 @@ static void mipspmu_event_update(struct perf_event *event, >>         unsigned long flags; >>         int shift = 64 - TOTAL_BITS; >>         s64 prev_raw_count, new_raw_count; >> -       s64 delta; >> +       u64 delta; >> >>  again: >>         prev_raw_count = local64_read(&hwc->prev_count); >> -- >> 1.7.1 > > Acked-by: Will Deacon > > You might also want to look at commit 65b4711f if you based > the MIPS port on the old ARM code. > > Thanks, > > Will > > -- > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you. > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you. > > From Will.Deacon@arm.com Fri Nov 19 10:43:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 10:43:59 +0100 (CET) Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:56299 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491181Ab0KSJnz (ORCPT ); Fri, 19 Nov 2010 10:43:55 +0100 Received: from cam-owa1.Emea.Arm.com (cam-owa1.emea.arm.com [10.1.255.62]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id oAJ9biF9003366; Fri, 19 Nov 2010 09:37:44 GMT Received: from [10.1.68.185] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Fri, 19 Nov 2010 09:43:30 +0000 Subject: Re: [PATCH 3/5] MIPS/Perf-events: Check event state in validate_event() From: Will Deacon To: Deng-Cheng Zhu Cc: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com In-Reply-To: <1290063401-25440-4-git-send-email-dengcheng.zhu@gmail.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-4-git-send-email-dengcheng.zhu@gmail.com> Content-Type: text/plain; charset="UTF-8" Date: Fri, 19 Nov 2010 09:43:26 +0000 Message-ID: <1290159806.9342.7.camel@e102144-lin.cambridge.arm.com> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 19 Nov 2010 09:43:30.0259 (UTC) FILETIME=[392F1230:01CB87CE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28425 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: will.deacon@arm.com Precedence: bulk X-list: linux-mips Hi Deng-Cheng, On Thu, 2010-11-18 at 06:56 +0000, Deng-Cheng Zhu wrote: > Ignore events that are not for this PMU or are in off/error state. > Sorry I didn't see this before, thanks for pointing out that you had included it for MIPS. > Signed-off-by: Deng-Cheng Zhu > --- > arch/mips/kernel/perf_event.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c > index 1ee44a3..9c6442a 100644 > --- a/arch/mips/kernel/perf_event.c > +++ b/arch/mips/kernel/perf_event.c > @@ -486,7 +486,7 @@ static int validate_event(struct cpu_hw_events *cpuc, > { > struct hw_perf_event fake_hwc = event->hw; > > - if (event->pmu && event->pmu != &pmu) > + if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) > return 0; > > return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; So this is the opposite of what we're doing on ARM. Our approach is to ignore events that are OFF (or in the ERROR state) or that belong to a different PMU. We do this by allowing them to *pass* validation (i.e. by returning 1 above). This means that we won't unconditionally fail a mixed event group. x86 does something similar in the collect_events function. Will From wg@grandegger.com Fri Nov 19 11:28:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 11:28:39 +0100 (CET) Received: from mail-out.m-online.net ([212.18.0.9]:37854 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491178Ab0KSK2g (ORCPT ); Fri, 19 Nov 2010 11:28:36 +0100 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 1746C1C089C9; Fri, 19 Nov 2010 11:28:30 +0100 (CET) X-Auth-Info: JHjCkpAFC7/MXyyWJRH+e2qIAfE/frdUMdUZRTclbK8= Received: from lancy.mylan.de (p4FE63FAF.dip.t-dialin.net [79.230.63.175]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 8F0C61C00436; Fri, 19 Nov 2010 11:28:30 +0100 (CET) Message-ID: <4CE65199.7030007@grandegger.com> Date: Fri, 19 Nov 2010 11:29:45 +0100 From: Wolfgang Grandegger User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100907 Fedora/3.0.7-1.fc12 Thunderbird/3.0.7 MIME-Version: 1.0 To: Florian Fainelli CC: Linux-MIPS , Netdev@vger.kernel.org Subject: Re: alchemy/gpr: au1000_eth regression with v2.6.37rc2 References: <4CE58593.50509@grandegger.com> <201011182330.08488.florian@openwrt.org> In-Reply-To: <201011182330.08488.florian@openwrt.org> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28426 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips Hello Florian, On 11/18/2010 11:30 PM, Florian Fainelli wrote: > Hello Wolfgang, > > Le Thursday 18 November 2010 20:59:15, Wolfgang Grandegger a écrit : >> Hello, >> >> I just realized that the v2.6.37-rc2 kernel does not boot any more on >> the Alchemy GPR board. It works fine with v2.6.36. It hangs in the >> probe function of the au1000_eth driver when probing the second >> ethernet port (eth1): >> >> au1000_eth_mii: probed >> au1000-eth au1000-eth.0: (unregistered net_device): attached PHY driver >> [Generic PHY] (mii_bus:phy_addr=0:00, irq=-1) au1000-eth au1000-eth.0: >> eth0: Au1xx0 Ethernet found at 0x10500000, irq 35 au1000_eth: au1000_eth >> version 1.7 Pete Popov ... hangs ... >> >> Similar messages should follow for eth1. I narrowed down (bisect'ed) the >> problem to commit: >> >> commit d0e7cb5d401695809ba8c980124ab1d8c66efc8b >> Author: Florian Fainelli >> Date: Wed Sep 8 11:15:13 2010 +0000 >> >> au1000-eth: remove volatiles, switch to I/O accessors >> >> Remove all the volatile keywords where they were used, switch to using >> the proper readl/writel accessors. >> >> Signed-off-by: Florian Fainelli >> Signed-off-by: David S. Miller >> >> The kernel actually hangs when accessing "&aup->mac->mii_control" in >> au1000_mdio_read(), but only for eth1. Any idea what does go wrong? > > I do not understand so far while it hangs only for eth1. My device only has > one ethernet MAC, so I could not notice the problem. Looking at this close, > there are a couple of u32 const* usages in au1000_mdio_{read,write} which are > looking wrong to me now. Can you try to remove these? That did not help. >> In principle, I do not want to access the MII regs of the MAC because >> eth0 and eth1 are connected to switches. But that's not possible, even >> with "aup->phy_static_config=1" and "aup->phy_addr=0". > > If you think this is another issue, I will fix it in another patch. Accessing the MII registers of the MAC should not hang the system even if I do not need to. First I want to understand why. Looks like a wired optimizer issue. BTW: why do you use readl() and writel() instead of the usual au_readl() and au_writel() to access memory mapped cpu registers? It did not help, anyway. Wolfgang From f.fainelli@gmail.com Fri Nov 19 11:46:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 11:46:16 +0100 (CET) Received: from mail-ww0-f54.google.com ([74.125.82.54]:51232 "EHLO mail-ww0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491178Ab0KSKqJ convert rfc822-to-8bit (ORCPT ); Fri, 19 Nov 2010 11:46:09 +0100 Received: by wwi17 with SMTP id 17so2633125wwi.23 for ; Fri, 19 Nov 2010 02:46:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:organization:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=uU/hejWilqltcIzXSySkrUmHUf2URpsr1qAzd3Dl7dk=; b=arrkkZfmbqGC6O8YShacjCXffaz/RcVbm3/e8HkNJ5ia3ppcqpGrT65b2Ta1elMuzZ dtb8EKYctlZOMSq+i3fQ0EqPsxM92fsMBkXHBsIs8To8JEu2RVPtMHstdlXvjN0uTWoV 23jiL6NtV6H13UyG+KlixZjmdXX2f/B1u0bAs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=o8r47LKOcNVfLFqa28BJLgeUb+n1ZPVokbsjYAi3/iBBMgV36N/63I/EpQAhn+9IeS kTE6NZW0/t3DAByBNfweEGf1iR4oym5Oj05D8OomAhnIdVGUtBEetBeTj740V8RIMDNh ItLXyYebXQZeGFFVhegyUCdnf7QfU3sVvAB0M= Received: by 10.216.164.137 with SMTP id c9mr4258985wel.19.1290163564185; Fri, 19 Nov 2010 02:46:04 -0800 (PST) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id w41sm708312weq.32.2010.11.19.02.46.02 (version=SSLv3 cipher=RC4-MD5); Fri, 19 Nov 2010 02:46:02 -0800 (PST) From: Florian Fainelli Organization: OpenWrt To: Wolfgang Grandegger Subject: Re: alchemy/gpr: au1000_eth regression with v2.6.37rc2 Date: Fri, 19 Nov 2010 11:46:01 +0100 User-Agent: KMail/1.13.5 (Linux/2.6.35-22-server; KDE/4.5.1; x86_64; ; ) Cc: "Linux-MIPS" , Netdev@vger.kernel.org References: <4CE58593.50509@grandegger.com> <201011182330.08488.florian@openwrt.org> <4CE65199.7030007@grandegger.com> In-Reply-To: <4CE65199.7030007@grandegger.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Message-Id: <201011191146.01454.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28427 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hello Wolfgang, On Friday 19 November 2010 11:29:45 Wolfgang Grandegger wrote: > Hello Florian, > > On 11/18/2010 11:30 PM, Florian Fainelli wrote: > > Hello Wolfgang, > > > > Le Thursday 18 November 2010 20:59:15, Wolfgang Grandegger a écrit : > >> Hello, > >> > >> I just realized that the v2.6.37-rc2 kernel does not boot any more on > >> the Alchemy GPR board. It works fine with v2.6.36. It hangs in the > >> probe function of the au1000_eth driver when probing the second > >> > >> ethernet port (eth1): > >> au1000_eth_mii: probed > >> au1000-eth au1000-eth.0: (unregistered net_device): attached PHY > >> driver > >> > >> [Generic PHY] (mii_bus:phy_addr=0:00, irq=-1) au1000-eth au1000-eth.0: > >> eth0: Au1xx0 Ethernet found at 0x10500000, irq 35 au1000_eth: au1000_eth > >> version 1.7 Pete Popov ... hangs ... > >> > >> Similar messages should follow for eth1. I narrowed down (bisect'ed) the > >> > >> problem to commit: > >> commit d0e7cb5d401695809ba8c980124ab1d8c66efc8b > >> Author: Florian Fainelli > >> Date: Wed Sep 8 11:15:13 2010 +0000 > >> > >> au1000-eth: remove volatiles, switch to I/O accessors > >> > >> Remove all the volatile keywords where they were used, switch to > >> using > >> > >> the proper readl/writel accessors. > >> > >> Signed-off-by: Florian Fainelli > >> Signed-off-by: David S. Miller > >> > >> The kernel actually hangs when accessing "&aup->mac->mii_control" in > >> au1000_mdio_read(), but only for eth1. Any idea what does go wrong? > > > > I do not understand so far while it hangs only for eth1. My device only > > has one ethernet MAC, so I could not notice the problem. Looking at this > > close, there are a couple of u32 const* usages in > > au1000_mdio_{read,write} which are looking wrong to me now. Can you try > > to remove these? > > That did not help. I suspected it, but thanks for the confirmation. > > >> In principle, I do not want to access the MII regs of the MAC because > >> eth0 and eth1 are connected to switches. But that's not possible, even > >> with "aup->phy_static_config=1" and "aup->phy_addr=0". > > > > If you think this is another issue, I will fix it in another patch. > > Accessing the MII registers of the MAC should not hang the system even > if I do not need to. First I want to understand why. Looks like a wired > optimizer issue. I definitively agree, furthermore since there is a timeout for read and write operations. I will look at the assembly and see if I can see anything different. > > BTW: why do you use readl() and writel() instead of the usual au_readl() > and au_writel() to access memory mapped cpu registers? It did not help, > anyway. This is just because they are generic accessors, and the au_{readl,writel} variants were not different. -- Florian From a.p.zijlstra@chello.nl Fri Nov 19 12:27:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 12:27:47 +0100 (CET) Received: from casper.infradead.org ([85.118.1.10]:56088 "EHLO casper.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491188Ab0KSL1j convert rfc822-to-8bit (ORCPT ); Fri, 19 Nov 2010 12:27:39 +0100 Received: from f199130.upc-f.chello.nl ([80.56.199.130] helo=laptop) by casper.infradead.org with esmtpsa (Exim 4.72 #1 (Red Hat Linux)) id 1PJP7Z-0002Hv-MF; Fri, 19 Nov 2010 11:27:33 +0000 Received: by laptop (Postfix, from userid 1000) id 6358E1035D2D7; Fri, 19 Nov 2010 12:27:32 +0100 (CET) Subject: Re: [PATCH 3/5] MIPS/Perf-events: Check event state in validate_event() From: Peter Zijlstra To: Will Deacon Cc: Deng-Cheng Zhu , ralf@linux-mips.org, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com In-Reply-To: <1290159806.9342.7.camel@e102144-lin.cambridge.arm.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-4-git-send-email-dengcheng.zhu@gmail.com> <1290159806.9342.7.camel@e102144-lin.cambridge.arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Date: Fri, 19 Nov 2010 12:27:31 +0100 Message-ID: <1290166051.2109.1539.camel@laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28428 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: a.p.zijlstra@chello.nl Precedence: bulk X-list: linux-mips On Fri, 2010-11-19 at 09:43 +0000, Will Deacon wrote: > Hi Deng-Cheng, > > On Thu, 2010-11-18 at 06:56 +0000, Deng-Cheng Zhu wrote: > > Ignore events that are not for this PMU or are in off/error state. > > > Sorry I didn't see this before, thanks for pointing out that you > had included it for MIPS. > > > Signed-off-by: Deng-Cheng Zhu > > --- > > arch/mips/kernel/perf_event.c | 2 +- > > 1 files changed, 1 insertions(+), 1 deletions(-) > > > > diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c > > index 1ee44a3..9c6442a 100644 > > --- a/arch/mips/kernel/perf_event.c > > +++ b/arch/mips/kernel/perf_event.c > > @@ -486,7 +486,7 @@ static int validate_event(struct cpu_hw_events *cpuc, > > { > > struct hw_perf_event fake_hwc = event->hw; > > > > - if (event->pmu && event->pmu != &pmu) > > + if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) > > return 0; > > > > return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; > > So this is the opposite of what we're doing on ARM. Our > approach is to ignore events that are OFF (or in the ERROR > state) or that belong to a different PMU. We do this by > allowing them to *pass* validation (i.e. by returning 1 above). > This means that we won't unconditionally fail a mixed event group. > > x86 does something similar in the collect_events function. Right, note that the generic code only allows mixing with software events, so simply accepting them is ok as software events give the guarantee they're always schedulable. From dengcheng.zhu@gmail.com Fri Nov 19 12:30:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 12:30:23 +0100 (CET) Received: from mail-ww0-f54.google.com ([74.125.82.54]:62638 "EHLO mail-ww0-f54.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491198Ab0KSLaP convert rfc822-to-8bit (ORCPT ); Fri, 19 Nov 2010 12:30:15 +0100 Received: by wwi17 with SMTP id 17so2675601wwi.23 for ; Fri, 19 Nov 2010 03:30:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=9WWMP7VaLk1hrVMuEjnpl5wRHnvbBFrmMg4iMawwZZo=; b=OHVpP0CzhnugVnB7EcnFpmJcgXRS341G79lHqLik22e5MkAU1G56njMhxYq5QPM3Ka l+ooK/C1TaRi/s0wbu7oMg5/Vm0emeOYW9ifSKVUK6Crx72RGcxhux6PhQchQVR5iS0s h9QjyUfW3xIKwdLWpolcfKMOBUloOijb5ZxgE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=PdaxowgncmQWzKHwuY24euDca/WQPMG9YwDuEOfRX29GZneHcquv8keYkW43FFWlxu zeJarmTEoBytNKPenQ8IsozFHfmoUqZnai4UCLEEfb1rnY2PKZHFmv2EPoypc8t39HoG MDhC5G2qqSze2phUimbN0oa8nFDlypZGDIRm0= MIME-Version: 1.0 Received: by 10.216.176.20 with SMTP id a20mr1730781wem.14.1290166208798; Fri, 19 Nov 2010 03:30:08 -0800 (PST) Received: by 10.216.236.138 with HTTP; Fri, 19 Nov 2010 03:30:08 -0800 (PST) In-Reply-To: <1290159806.9342.7.camel@e102144-lin.cambridge.arm.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-4-git-send-email-dengcheng.zhu@gmail.com> <1290159806.9342.7.camel@e102144-lin.cambridge.arm.com> Date: Fri, 19 Nov 2010 19:30:08 +0800 Message-ID: Subject: Re: [PATCH 3/5] MIPS/Perf-events: Check event state in validate_event() From: Deng-Cheng Zhu To: Will Deacon Cc: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28429 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Ah, I see. Thanks for your explanation. But by doing this, I think we need to modify validate_group() as well. Consider a group which has all its events either not for this PMU or in OFF/Error state. Then the last validate_event() in validate_group() does not work. Right? So, how about the following: diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index 1ee44a3..4010bc0 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -486,8 +486,8 @@ static int validate_event(struct cpu_hw_events *cpuc, { struct hw_perf_event fake_hwc = event->hw; - if (event->pmu && event->pmu != &pmu) - return 0; + if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) + return 1; return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; } @@ -496,6 +496,7 @@ static int validate_group(struct perf_event *event) { struct perf_event *sibling, *leader = event->group_leader; struct cpu_hw_events fake_cpuc; + struct hw_perf_event fake_hwc = event->hw; memset(&fake_cpuc, 0, sizeof(fake_cpuc)); @@ -507,10 +508,12 @@ static int validate_group(struct perf_event *event) return -ENOSPC; } - if (!validate_event(&fake_cpuc, event)) + if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) + return -EINVAL; + else if (mipspmu->alloc_counter(&fake_cpuc, &fake_hwc) < 0) return -ENOSPC; - - return 0; + else + return 0; } /* This is needed by specific irq handlers in perf_event_*.c */ Thanks, Deng-Cheng 2010/11/19 Will Deacon : > Hi Deng-Cheng, > > On Thu, 2010-11-18 at 06:56 +0000, Deng-Cheng Zhu wrote: >> Ignore events that are not for this PMU or are in off/error state. >> > Sorry I didn't see this before, thanks for pointing out that you > had included it for MIPS. > >> Signed-off-by: Deng-Cheng Zhu >> --- >>  arch/mips/kernel/perf_event.c |    2 +- >>  1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c >> index 1ee44a3..9c6442a 100644 >> --- a/arch/mips/kernel/perf_event.c >> +++ b/arch/mips/kernel/perf_event.c >> @@ -486,7 +486,7 @@ static int validate_event(struct cpu_hw_events *cpuc, >>  { >>         struct hw_perf_event fake_hwc = event->hw; >> >> -       if (event->pmu && event->pmu != &pmu) >> +       if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) >>                 return 0; >> >>         return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; > > So this is the opposite of what we're doing on ARM. Our > approach is to ignore events that are OFF (or in the ERROR > state) or that belong to a different PMU. We do this by > allowing them to *pass* validation (i.e. by returning 1 above). > This means that we won't unconditionally fail a mixed event group. > > x86 does something similar in the collect_events function. > > Will > > -- > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you. > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you. > > From will.deacon@arm.com Fri Nov 19 13:03:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 13:03:52 +0100 (CET) Received: from service87.mimecast.com ([94.185.240.25]:53370 "HELO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491188Ab0KSMDp convert rfc822-to-8bit (ORCPT ); Fri, 19 Nov 2010 13:03:45 +0100 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 19 Nov 2010 12:03:32 +0000 Received: from [10.1.68.185] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Fri, 19 Nov 2010 12:03:30 +0000 Subject: Re: [PATCH 3/5] MIPS/Perf-events: Check event state in validate_event() From: Will Deacon To: Peter Zijlstra Cc: Deng-Cheng Zhu , ralf@linux-mips.org, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com In-Reply-To: <1290166051.2109.1539.camel@laptop> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-4-git-send-email-dengcheng.zhu@gmail.com> <1290159806.9342.7.camel@e102144-lin.cambridge.arm.com> <1290166051.2109.1539.camel@laptop> Date: Fri, 19 Nov 2010 12:03:27 +0000 Message-ID: <1290168207.8175.6.camel@e102144-lin.cambridge.arm.com> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 X-OriginalArrivalTime: 19 Nov 2010 12:03:30.0603 (UTC) FILETIME=[C82DD7B0:01CB87E1] X-MC-Unique: 110111912033201301 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28430 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: will.deacon@arm.com Precedence: bulk X-list: linux-mips On Fri, 2010-11-19 at 11:27 +0000, Peter Zijlstra wrote: > > So this is the opposite of what we're doing on ARM. Our > > approach is to ignore events that are OFF (or in the ERROR > > state) or that belong to a different PMU. We do this by > > allowing them to *pass* validation (i.e. by returning 1 above). > > This means that we won't unconditionally fail a mixed event group. > > > > x86 does something similar in the collect_events function. > > Right, note that the generic code only allows mixing with software > events, so simply accepting them is ok as software events give the > guarantee they're always schedulable. > > Ok. Initially it was software events that I had in mind, but does this constraint prevent you from grouping CPU events with events for other PMUs within the system? For external L2 cache controllers with their own PMUs, it would be desirable to group some L2 events with L1 events on a different PMU. If each PMU can validate its own events and ignore others then it sounds like it should be straightforward... Will From will.deacon@arm.com Fri Nov 19 13:05:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 13:05:18 +0100 (CET) Received: from service87.mimecast.com ([94.185.240.25]:34624 "HELO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491188Ab0KSMFO convert rfc822-to-8bit (ORCPT ); Fri, 19 Nov 2010 13:05:14 +0100 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 19 Nov 2010 12:05:10 +0000 Received: from [10.1.68.185] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Fri, 19 Nov 2010 12:05:06 +0000 Subject: Re: [PATCH 3/5] MIPS/Perf-events: Check event state in validate_event() From: Will Deacon To: Deng-Cheng Zhu Cc: ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com In-Reply-To: References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-4-git-send-email-dengcheng.zhu@gmail.com> <1290159806.9342.7.camel@e102144-lin.cambridge.arm.com> Date: Fri, 19 Nov 2010 12:05:05 +0000 Message-ID: <1290168306.8175.8.camel@e102144-lin.cambridge.arm.com> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 X-OriginalArrivalTime: 19 Nov 2010 12:05:07.0087 (UTC) FILETIME=[01B021F0:01CB87E2] X-MC-Unique: 110111912051005301 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28431 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: will.deacon@arm.com Precedence: bulk X-list: linux-mips On Fri, 2010-11-19 at 11:30 +0000, Deng-Cheng Zhu wrote: > Ah, I see. Thanks for your explanation. > > But by doing this, I think we need to modify validate_group() as well. > Consider a group which has all its events either not for this PMU or in > OFF/Error state. Then the last validate_event() in validate_group() does > not work. Right? So, how about the following: [...] If none of the events are for this PMU, then our validate_group() won't be called. If all the events are OFF/ERROR then I don't see what's wrong with passing the validation. Will From a.p.zijlstra@chello.nl Fri Nov 19 13:09:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 13:09:52 +0100 (CET) Received: from canuck.infradead.org ([134.117.69.58]:38005 "EHLO canuck.infradead.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491183Ab0KSMJs convert rfc822-to-8bit (ORCPT ); Fri, 19 Nov 2010 13:09:48 +0100 Received: from f199130.upc-f.chello.nl ([80.56.199.130] helo=laptop) by canuck.infradead.org with esmtpsa (Exim 4.72 #1 (Red Hat Linux)) id 1PJPmg-0008IJ-Sj; Fri, 19 Nov 2010 12:09:43 +0000 Received: by laptop (Postfix, from userid 1000) id 50C791035D2EE; Fri, 19 Nov 2010 13:10:00 +0100 (CET) Subject: Re: [PATCH 3/5] MIPS/Perf-events: Check event state in validate_event() From: Peter Zijlstra To: Will Deacon Cc: Deng-Cheng Zhu , ralf@linux-mips.org, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com In-Reply-To: <1290168207.8175.6.camel@e102144-lin.cambridge.arm.com> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-4-git-send-email-dengcheng.zhu@gmail.com> <1290159806.9342.7.camel@e102144-lin.cambridge.arm.com> <1290166051.2109.1539.camel@laptop> <1290168207.8175.6.camel@e102144-lin.cambridge.arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Date: Fri, 19 Nov 2010 13:09:59 +0100 Message-ID: <1290168599.2109.1567.camel@laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28432 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: a.p.zijlstra@chello.nl Precedence: bulk X-list: linux-mips On Fri, 2010-11-19 at 12:03 +0000, Will Deacon wrote: > On Fri, 2010-11-19 at 11:27 +0000, Peter Zijlstra wrote: > > > So this is the opposite of what we're doing on ARM. Our > > > approach is to ignore events that are OFF (or in the ERROR > > > state) or that belong to a different PMU. We do this by > > > allowing them to *pass* validation (i.e. by returning 1 above). > > > This means that we won't unconditionally fail a mixed event group. > > > > > > x86 does something similar in the collect_events function. > > > > Right, note that the generic code only allows mixing with software > > events, so simply accepting them is ok as software events give the > > guarantee they're always schedulable. > > > > > > Ok. Initially it was software events that I had in mind, but does > this constraint prevent you from grouping CPU events with events > for other PMUs within the system? For external L2 cache controllers > with their own PMUs, it would be desirable to group some L2 events > with L1 events on a different PMU. > > If each PMU can validate its own events and ignore others then it > sounds like it should be straightforward... Getting them all scheduled on the hardware at the same time will be 'interesting'.. therefore we currently don't allow for this. The current code would pretty much result in such a group being starved if there were other contenders. From Andrei.Ardelean@idt.com Fri Nov 19 15:04:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 15:04:31 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:56155 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491872Ab0KSOE2 convert rfc822-to-8bit (ORCPT ); Fri, 19 Nov 2010 15:04:28 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oAJE4Iem030438; Fri, 19 Nov 2010 06:04:18 -0800 Received: from corpml3.corp.idt.com (corpml3.corp.idt.com [157.165.140.25]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oAJE4HSr022869; Fri, 19 Nov 2010 06:04:17 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml3.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oAJE4Gm26236; Fri, 19 Nov 2010 06:04:16 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: The new "real" console doesn't display printk() messages like "early" console! Date: Fri, 19 Nov 2010 06:04:07 -0800 Message-ID: In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: The new "real" console doesn't display printk() messages like "early" console! Thread-Index: AcuHf5ATiEo4mLPfSaesmCyQSEQaSgAcbkZA References: <4CE57C92.6030705@mvista.com> From: "Ardelean, Andrei" To: "Ricardo Mendoza" Cc: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28433 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi Ricardo, I used Octeon just as a model, I added my own PORT_GD and my own serial_in/out driver functions which work well, I have some messages on the screen. My problem is that I can see messages like "Freeing unused kernel memory..." but I cannot see printk() error/warning/debug messages, like the messages printed by die(). Thanks, Andrei -----Original Message----- From: mendoza.ricardo@gmail.com [mailto:mendoza.ricardo@gmail.com] On Behalf Of Ricardo Mendoza Sent: Thursday, November 18, 2010 6:58 PM To: Ardelean, Andrei Cc: linux-mips@linux-mips.org Subject: Re: The new "real" console doesn't display printk() messages like "early" console! On Thu, Nov 18, 2010 at 10:01 PM, Ardelean, Andrei wrote: > Hi Ricardo, > > I implemented serial platform driver taking as model serial.c from > cavium-octeon. > > Here is my code: > > ... Why use the Octeon code which has platform specific bits that might have nothing to do with your platform? Build up from the simple ones. Ricardo From fweisbec@gmail.com Fri Nov 19 15:34:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 15:34:28 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:34312 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491875Ab0KSOeZ (ORCPT ); Fri, 19 Nov 2010 15:34:25 +0100 Received: by bwz5 with SMTP id 5so4048862bwz.36 for ; Fri, 19 Nov 2010 06:34:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:date:from:to:cc :subject:message-id:references:mime-version:content-type :content-disposition:in-reply-to:user-agent; bh=QfppuqDMucQuvSJAK5drXEMCdaWXZKatI+E5xOBrIY8=; b=mrAAZllHeLDOHWKLvLpMgR9CIX70xYmLEheWqYbPYi719EP97fd0fkhc7dZaliVAxh 7HPOOSYZI2ZvLfvYXbC0btjDtRX5bRyP0qqkOkq/uWLohDNq56aolpQtqcRdCEUb1/e9 +whsvOQdSQ6WbUh1t0/Gln4TzFRo2Qc4rpw8c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; b=AzOY2aM4+eGMCCQuAADWy6nZmxnNXguAxLc0yhVEX9oG+QBvFF2f9a3m+ZGVOgazr4 ICfyGi6oywQzsuSOqmxi3LwWpBVzVTu9eTT/RPuclaKAM5rsGJvx0g/ZQ/19SUMd0o7i JkjkiVvQJcTmaswWiJ3K0P349OqcFf2cY5oCI= Received: by 10.204.136.70 with SMTP id q6mr2120991bkt.208.1290177265312; Fri, 19 Nov 2010 06:34:25 -0800 (PST) Received: from nowhere (p549AACDD.dip.t-dialin.net [84.154.172.221]) by mx.google.com with ESMTPS id v20sm402564bku.22.2010.11.19.06.34.22 (version=SSLv3 cipher=RC4-MD5); Fri, 19 Nov 2010 06:34:23 -0800 (PST) Received: by nowhere (nbSMTP-1.00) for uid 1000 (using TLSv1/SSLv3 with cipher RC4-MD5 (128/128 bits)) fweisbec@gmail.com; Fri, 19 Nov 2010 15:34:23 +0100 (CET) Date: Fri, 19 Nov 2010 15:34:21 +0100 From: Frederic Weisbecker To: Deng-Cheng Zhu Cc: ralf@linux-mips.org, a.p.zijlstra@chello.nl, will.deacon@arm.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com Subject: Re: [PATCH 4/5] MIPS/Perf-events: Work with the new callchain interface Message-ID: <20101119143416.GA5558@nowhere> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-5-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1290063401-25440-5-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28434 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fweisbec@gmail.com Precedence: bulk X-list: linux-mips On Thu, Nov 18, 2010 at 02:56:40PM +0800, Deng-Cheng Zhu wrote: > This is the MIPS part of the following commits by Frederic Weisbecker: > > f72c1a931e311bb7780fee19e41a89ac42cab50e > perf: Factorize callchain context handling > 56962b4449af34070bb1994621ef4f0265eed4d8 > perf: Generalize some arch callchain code > 70791ce9ba68a5921c9905ef05d23f62a90bc10c > perf: Generalize callchain_store() > c1a65932fd7216fdc9a0db8bbffe1d47842f862c > perf: Drop unappropriate tests on arch callchains > > Signed-off-by: Deng-Cheng Zhu > --- Acked-by: Frederic Weisbecker Why did I miss this arch? I did a grep on HAVE_PERF_EVENT or something, may be it hadn't it at that time? Thanks! From sshtylyov@mvista.com Fri Nov 19 17:09:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2010 17:10:11 +0100 (CET) Received: from mail-ew0-f49.google.com ([209.85.215.49]:64287 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491917Ab0KSQJ5 (ORCPT ); Fri, 19 Nov 2010 17:09:57 +0100 Received: by ewy19 with SMTP id 19so2732846ewy.36 for ; Fri, 19 Nov 2010 08:09:56 -0800 (PST) Received: by 10.213.35.72 with SMTP id o8mr4892761ebd.62.1290182996408; Fri, 19 Nov 2010 08:09:56 -0800 (PST) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id x54sm1595087eeh.5.2010.11.19.08.09.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 19 Nov 2010 08:09:54 -0800 (PST) Message-ID: <4CE6A103.8030009@mvista.com> Date: Fri, 19 Nov 2010 19:08:35 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: "Ardelean, Andrei" CC: Ricardo Mendoza , linux-mips@linux-mips.org Subject: Re: The new "real" console doesn't display printk() messages like "early" console! References: <4CE57C92.6030705@mvista.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28435 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Ardelean, Andrei wrote: > Hi Ricardo, > I implemented serial platform driver taking as model serial.c from > cavium-octeon. I think you should really have used something simpler as an example. > Here is my code: > /* > * This file is subject to the terms and conditions of the GNU General > Public > * License. See the file "COPYING" in the main directory of this > archive > * for more details. > * > * Copyright (C) 2004-2007 Cavium Networks > */ > > #include > #include > #include > #include > #include > #include > #include > #include > #include > #include > > > #ifdef CONFIG_GDB_CONSOLE This is never defined for MIPS. And there shouldn't be such dependencies. > #define DEBUG_UART 0 > #else > #define DEBUG_UART 1 > #endif > > unsigned int gd_serial_in(struct uart_port *up, int offset) > { > int rv = inl((unsigned int)(up->membase + (offset << 2))); Should be an empty line here. > if (offset == UART_IIR && (rv & 0xf) == 7) { Are you sure this Octeon specific quirk also allpies to your UART? > /* Busy interrupt, read the USR (39) and try again. */ > inl((unsigned int)(up->membase + (39 << 2))); > rv = inl((unsigned int)(up->membase + (offset << 2))); > } > return rv; > } > > void gd_serial_out(struct uart_port *up, int offset, int value) > { > outl( value & 0xff, (unsigned int)(up->membase + (offset << No spaces allowed after (. > 2))); > } > > /* > * Allocated in .bss, so it is all zeroed. > */ > #define GD_MAX_UARTS 1 Then how DEBUG_UART can be 1? > static struct plat_serial8250_port gd_uart8250_data[GD_MAX_UARTS + 1]; > static struct platform_device gd_uart8250_device = { > .name = "serial8250", > .id = PLAT8250_DEV_PLATFORM, > .dev = { > .platform_data = gd_uart8250_data, Where is 'gd_uart8250_data'? > }, > }; > static void __init gd_uart_set_common(struct plat_serial8250_port *p) > { > p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; > p->type = PORT_GD; What is PORT_GD? > p->iotype = UPIO_MEM; Judging from your code, it should be UPIO_MEM32. > p->regshift = 2; /* I/O addresses are every 4 bytes */ > p->uartclk = UART_CLK; > p->serial_in = gd_serial_in; > p->serial_out = gd_serial_out; > } > > static int __init gd_serial_init(void) > { > int enable_uart0; > struct plat_serial8250_port *p; > > enable_uart0 = 1; What's the point in existence of this variable? > p = gd_uart8250_data; > if (enable_uart0) { > /* Add a ttyS device for hardware uart 0 */ > gd_uart_set_common(p); > p->membase = (void *) offMCU_UART_THR_OR_RBR_OR_DLL; > p->mapbase = offMCU_UART_THR_OR_RBR_OR_DLL; Are your UART registers identity mapped to virtual address space? You are not obliged to pass 'membase', unless you have pre-existing mapping but in this case you also need to pass UPF_IOREMAP in 'flags'. > p->irq = MIPSCPU_INT_UART; > p++; > } > return platform_device_register(&gd_uart8250_device); > } > > device_initcall(gd_serial_init); > ------------------------------------------------------------------------ > ----------------------- > > Thanks, > Andrei WBR, Sergei From shmprtd@googlemail.com Sun Nov 21 01:15:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2010 01:15:21 +0100 (CET) Received: from mail-bw0-f49.google.com ([209.85.214.49]:59285 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491819Ab0KUAPO (ORCPT ); Sun, 21 Nov 2010 01:15:14 +0100 Received: by bwz5 with SMTP id 5so5239724bwz.36 for ; Sat, 20 Nov 2010 16:15:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:date:from:subject:to:cc :message-id:mime-version:content-type:content-disposition; bh=CflpetpbLumIqMJVAkzva+YYXntKLsMdzsPHjsM0d2U=; b=ez5B/Q2YolkZip6TSp+N6Vn7A9mKjeKnAOgxl5tQMTPSEb5x9FdNed9tiVECAeZqOO xnT6CaztZFucXD31tPKZBI2X0MnCY1mOr/cQ32yWOIlUOitMySnZf7TQI2clQ8YMFWlB 0JgIjTpAy5ARIkXlBz5OaR7Z4wzF94dkv+MQc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=date:from:subject:to:cc:message-id:mime-version:content-type :content-disposition; b=tB8BHwFJ1afzM5s5mT+55qHuwba36Kn1cLifFzAT+stCV+ZbSsiOWTAS5Y8ExRAWno KmJNb72VyPKMkkgnUcEO/kJOPfh+6cHzod+25ACWMcLhlHwB0zflF+e8sTyA4mFhPt1U oRP8WE2QU1GsoDYpmkwy428Ab963hmc6pGEu4= Received: by 10.204.116.4 with SMTP id k4mr3634823bkq.187.1290298513254; Sat, 20 Nov 2010 16:15:13 -0800 (PST) Received: from psycho-wlan.lan (dslc-082-083-253-034.pools.arcor-ip.net [82.83.253.34]) by mx.google.com with ESMTPS id v25sm1606144bkt.6.2010.11.20.16.15.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 20 Nov 2010 16:15:12 -0800 (PST) Date: Sun, 21 Nov 2010 01:15:11 +0100 (CET) From: shmprtd@googlemail.com Subject: [PATCH] Add support for Realtek Media Player SoCs To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; CHARSET=us-ascii Content-Disposition: INLINE Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28436 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shmprtd@googlemail.com Precedence: bulk X-list: linux-mips Hi, I added support for at least one of the Realtek "Galaxy" SoCs to recent 2.6.36 kernel. Most of the patch is based on existing linux-mips code and a 2.6.12 kernel source released by some of Realtek customers. Currently, this allows to start the kernel and setup serial console. Further development/porting will have to be done for additional platform devices. This code is tested on a Realtek Mars SoC. Commercial product name is rtd1073dd but cpu/soc id is 0x1283. Other SoCs (Venus,Jupiter,Neptune) have not been tested, yet. Please comment on the patch and feel free to suggest changes that need to be done prior integration. Sebastian diff -uNr linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-board.h linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-board.h --- linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-board.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-board.h 2010-11-19 18:20:47.000000000 +0100 @@ -0,0 +1,51 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#ifndef _RTD128X_BOARD_H_ +#define _RTD128X_BOARD_H_ + +#include + +enum rtd128x_board_type { + RTD128X_BOARD_UNKNOWN = -1, + RTD128X_BOARD_EM7080 = 0, +}; + +struct rtd128x_board { + char name[16]; + u32 ext_freq; + unsigned int has_eth0:1; + unsigned int has_pci:1; + unsigned int has_pccard:1; + unsigned int has_ohci0:1; + unsigned int has_ehci0:1; + unsigned int has_sata0:1; + unsigned int has_sata1:1; + unsigned int has_uart0:1; + unsigned int has_uart1:1; + unsigned int has_vfd:1; + + void (*machine_restart) (char *); + void (*machine_halt) (void); + void (*machine_poweroff) (void); + + /* + * Autodetected / PROM values + */ + + phys_t memory_size; + char bootrev[16]; + u16 company_id; + u32 board_id; + u8 cpu_id; + u8 chip_rev; + u16 chip_id; +}; + +extern struct rtd128x_board rtd128x_board_info; + +#endif diff -uNr linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-io.h linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-io.h --- linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-io.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-io.h 2010-11-19 18:20:10.000000000 +0100 @@ -0,0 +1,276 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#ifndef _RTD128X_IO_H_ +#define _RTD128X_IO_H_ + +#define RTD128X_SYS_BASE_OFFSET 0x0000 +#define RTD128X_EHCI_BASE_OFFSET 0x3000 +#define RTD128X_UHCI_BASE_OFFSET 0x3400 +#define RTD128X_USBH_BASE_OFFSET 0x3800 +#define RTD128X_MCP_BASE_OFFSET 0x5100 +#define RTD128X_ETH_BASE_OFFSET 0x6000 +#define RTD128X_TVE_BASE_OFFSET 0x8000 +#define RTD128X_TVD_BASE_OFFSET 0x9000 +#define RTD128X_SB2_BASE_OFFSET 0xa000 +#define RTD128X_MISC_BASE_OFFSET 0xb000 +#define RTD128X_GPIO_BASE_OFFSET 0xb100 +#define RTD128X_UART_BASE_OFFSET 0xb200 +#define RTD128X_I2C0_BASE_OFFSET 0xb300 +#define RTD128X_IRDA_BASE_OFFSET 0xb400 +#define RTD128X_TIMR_BASE_OFFSET 0xb500 +#define RTD128X_RTC_BASE_OFFSET 0xb600 +#define RTD128X_VFDC_BASE_OFFSET 0xb700 +#define RTD128X_PCMCIA_BASE_OFFSET 0xb800 +#define RTD128X_CEC_BASE_OFFSET 0xb900 +#define RTD128X_SC0_BASE_OFFSET 0xba00 +#define RTD128X_I2C1_BASE_OFFSET 0xbb00 +#define RTD128X_SC1_BASE_OFFSET 0xbc00 + +/* + * Misc (PLL, IRQ ??) + */ + +#define RTD128X_MISC_PSELH_OFFSET 0x000 +#define RTD128X_MISC_PSELL_OFFSET 0x004 +#define RTD128X_MISC_UMSK_ISR_OFFSET 0x008 +#define RTD128X_MISC_ISR_OFFSET 0x00c +#define RTD128X_MISC_UMSK_ISR_GP0A_OFFSET 0x010 +#define RTD128X_MISC_UMSK_ISR_GP0DA_OFFSET 0x014 +#define RTD128X_MISC_UMSK_ISR_KPADAH_OFFSET 0x018 +#define RTD128X_MISC_UMSK_ISR_KPADAL_OFFSET 0x01c +#define RTD128X_MISC_UMSK_ISR_KPADDAH_OFFSET 0x020 +#define RTD128X_MISC_UMSK_ISR_KPADDAL_OFFSET 0x024 +#define RTD128X_MISC_UMSK_ISR_SW_OFFSET 0x028 +#define RTD128X_MISC_DBG_OFFSET 0x02c +#define RTD128X_MISC_DUMMY_OFFSET 0x030 +#define RTD128X_MISC_PSEL2_OFFSET 0x034 +#define RTD128X_MISC_UMSK_ISR_GP1A_OFFSET 0x038 +#define RTD128X_MISC_UMSK_ISR_GP1DA_OFFSET 0x03c + +#define RTD128X_MISC_BASE (RTD128X_MISC_BASE_OFFSET) +#define RTD128X_MISC_PSELH (RTD128X_MISC_BASE+RTD128X_MISC_PSELH_OFFSET) +#define RTD128X_MISC_PSELL (RTD128X_MISC_BASE+RTD128X_MISC_PSELL_OFFSET) +#define RTD128X_MISC_UMSK_ISR (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_OFFSET) +#define RTD128X_MISC_ISR (RTD128X_MISC_BASE+RTD128X_MISC_ISR_OFFSET) +#define RTD128X_MISC_UMSK_ISR_GP0A (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_GP0A_OFFSET) +#define RTD128X_MISC_UMSK_ISR_GP0DA (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_GP0DA_OFFSET) +#define RTD128X_MISC_UMSK_ISR_KPADAH (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_KPADAH_OFFSET) +#define RTD128X_MISC_UMSK_ISR_KPADAL (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_KPADAL_OFFSET) +#define RTD128X_MISC_UMSK_ISR_KPADDAH (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_KPADDAH_OFFSET) +#define RTD128X_MISC_UMSK_ISR_KPADDAL (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_KPADDAL_OFFSET) +#define RTD128X_MISC_UMSK_ISR_SW (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_SW_OFFSET) +#define RTD128X_MISC_DBG (RTD128X_MISC_BASE+RTD128X_MISC_DBG_OFFSET) +#define RTD128X_MISC_DUMMY (RTD128X_MISC_BASE+RTD128X_MISC_DUMMY_OFFSET) +#define RTD128X_MISC_PSEL2 (RTD128X_MISC_BASE+RTD128X_MISC_PSEL2_OFFSET) +#define RTD128X_MISC_UMSK_ISR_GP1A (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_GP1A_OFFSET) +#define RTD128X_MISC_UMSK_ISR_GP1DA (RTD128X_MISC_BASE+RTD128X_MISC_UMSK_ISR_GP1DA_OFFSET) + +/* + * UART0/UART1 (8250 compatible) + */ + +#define RTD128X_UART_U0RBR_THR_DLL_OFFSET 0x000 +#define RTD128X_UART_U0IER_DLH_OFFSET 0x004 +#define RTD128X_UART_U0IIR_FCR_OFFSET 0x008 +#define RTD128X_UART_U0LCR_OFFSET 0x00c +#define RTD128X_UART_U0MCR_OFFSET 0x010 +#define RTD128X_UART_U0LSR_OFFSET 0x014 +#define RTD128X_UART_U0MSR_OFFSET 0x018 +#define RTD128X_UART_U0SCR_OFFSET 0x01c +#define RTD128X_UART_U1RBR_THR_DLL_OFFSET 0x020 +#define RTD128X_UART_U1IER_DLH_OFFSET 0x024 +#define RTD128X_UART_U1IIR_FCR_OFFSET 0x028 +#define RTD128X_UART_U1LCR_OFFSET 0x02c +#define RTD128X_UART_U1MCR_OFFSET 0x030 +#define RTD128X_UART_U1LSR_OFFSET 0x034 +#define RTD128X_UART_U1MSR_OFFSET 0x038 +#define RTD128X_UART_U1SCR_OFFSET 0x03c + +#define RTD128X_UART_BASE (RTD128X_UART_BASE_OFFSET) +#define RTD128X_UART_U0RBR_THR_DLL (RTD128X_UART_BASE+RTD128X_UART_U0RBR_THR_DLL_OFFSET) +#define RTD128X_UART_U0IER_DLH (RTD128X_UART_BASE+RTD128X_UART_U0IER_DLH_OFFSET) +#define RTD128X_UART_U0IIR_FCR (RTD128X_UART_BASE+RTD128X_UART_U0IIR_FCR_OFFSET) +#define RTD128X_UART_U0LCR (RTD128X_UART_BASE+RTD128X_UART_U0LCR_OFFSET) +#define RTD128X_UART_U0MCR (RTD128X_UART_BASE+RTD128X_UART_U0MCR_OFFSET) +#define RTD128X_UART_U0LSR (RTD128X_UART_BASE+RTD128X_UART_U0LSR_OFFSET) +#define RTD128X_UART_U0MSR (RTD128X_UART_BASE+RTD128X_UART_U0MSR_OFFSET) +#define RTD128X_UART_U0SCR (RTD128X_UART_BASE+RTD128X_UART_U0SCR_OFFSET) +#define RTD128X_UART_U1RBR_THR_DLL (RTD128X_UART_BASE+RTD128X_UART_U1RBR_THR_DLL_OFFSET) +#define RTD128X_UART_U1IER_DLH (RTD128X_UART_BASE+RTD128X_UART_U1IER_DLH_OFFSET) +#define RTD128X_UART_U1IIR_FCR (RTD128X_UART_BASE+RTD128X_UART_U1IIR_FCR_OFFSET) +#define RTD128X_UART_U1LCR (RTD128X_UART_BASE+RTD128X_UART_U1LCR_OFFSET) +#define RTD128X_UART_U1MCR (RTD128X_UART_BASE+RTD128X_UART_U1MCR_OFFSET) +#define RTD128X_UART_U1LSR (RTD128X_UART_BASE+RTD128X_UART_U1LSR_OFFSET) +#define RTD128X_UART_U1MSR (RTD128X_UART_BASE+RTD128X_UART_U1MSR_OFFSET) +#define RTD128X_UART_U1SCR (RTD128X_UART_BASE+RTD128X_UART_U1SCR_OFFSET) + +#define RTD128X_UART0_BASE RTD128X_UART_U0RBR_THR_DLL +#define RTD128X_UART1_BASE RTD128X_UART_U1RBR_THR_DLL + +/* + * Timer + */ + +#define RTD128X_TIMR_TC0TVR_OFFSET 0x000 +#define RTD128X_TIMR_TC1TVR_OFFSET 0x004 +#define RTD128X_TIMR_TC2TVR_OFFSET 0x008 +#define RTD128X_TIMR_TC0CVR_OFFSET 0x00c +#define RTD128X_TIMR_TC1CVR_OFFSET 0x010 +#define RTD128X_TIMR_TC2CVR_OFFSET 0x014 +#define RTD128X_TIMR_TC0CR_OFFSET 0x018 +#define RTD128X_TIMR_TC1CR_OFFSET 0x01c +#define RTD128X_TIMR_TC2CR_OFFSET 0x020 +#define RTD128X_TIMR_TC0ICR_OFFSET 0x024 +#define RTD128X_TIMR_TC1ICR_OFFSET 0x028 +#define RTD128X_TIMR_TC2ICR_OFFSET 0x02c +#define RTD128X_TIMR_TCWCR_OFFSET 0x030 +#define RTD128X_TIMR_TCWTR_OFFSET 0x034 +#define RTD128X_TIMR_CLK27M_CLK90K_CNT_OFFSET 0x038 +#define RTD128X_TIMR_CLK90K_TM_LO_OFFSET 0x03c +#define RTD128X_TIMR_CLK90K_TM_HI_OFFSET 0x040 + +#define RTD128X_TIMR_BASE (RTD128X_TIMR_BASE_OFFSET) +#define RTD128X_TIMR_TC0TVR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC0TVR_OFFSET) +#define RTD128X_TIMR_TC1TVR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC1TVR_OFFSET) +#define RTD128X_TIMR_TC2TVR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC2TVR_OFFSET) +#define RTD128X_TIMR_TC0CVR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC0CVR_OFFSET) +#define RTD128X_TIMR_TC1CVR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC1CVR_OFFSET) +#define RTD128X_TIMR_TC2CVR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC2CVR_OFFSET) +#define RTD128X_TIMR_TC0CR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC0CR_OFFSET) +#define RTD128X_TIMR_TC1CR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC1CR_OFFSET) +#define RTD128X_TIMR_TC2CR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC2CR_OFFSET) +#define RTD128X_TIMR_TC0ICR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC0ICR_OFFSET) +#define RTD128X_TIMR_TC1ICR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC1ICR_OFFSET) +#define RTD128X_TIMR_TC2ICR (RTD128X_TIMR_BASE+RTD128X_TIMR_TC2ICR_OFFSET) +#define RTD128X_TIMR_TCWCR (RTD128X_TIMR_BASE+RTD128X_TIMR_TCWCR_OFFSET) +#define RTD128X_TIMR_TCWTR (RTD128X_TIMR_BASE+RTD128X_TIMR_TCWTR_OFFSET) +#define RTD128X_TIMR_CLK27M_CLK90K_CNT (RTD128X_TIMR_BASE+RTD128X_TIMR_CLK27M_CLK90K_CNT_OFFSET) +#define RTD128X_TIMR_CLK90K_TM_LO (RTD128X_TIMR_BASE+RTD128X_TIMR_CLK90K_TM_LO_OFFSET) +#define RTD128X_TIMR_CLK90K_TM_HI (RTD128X_TIMR_BASE+RTD128X_TIMR_CLK90K_TM_HI_OFFSET) + +/* + * RTC + */ + +#define RTD128X_RTC_SEC_OFFSET 0x000 +#define RTD128X_RTC_MIN_OFFSET 0x004 +#define RTD128X_RTC_HR_OFFSET 0x008 +#define RTD128X_RTC_DATE1_OFFSET 0x00c +#define RTD128X_RTC_DATE2_OFFSET 0x010 +#define RTD128X_RTC_ALMMIN_OFFSET 0x014 +#define RTD128X_RTC_ALMHR_OFFSET 0x018 +#define RTD128X_RTC_ALMDATE1_OFFSET 0x01c +#define RTD128X_RTC_ALMDATE2_OFFSET 0x020 +#define RTD128X_RTC_STOP_OFFSET 0x024 +#define RTD128X_RTC_ACR_OFFSET 0x028 +#define RTD128X_RTC_EN_OFFSET 0x02c +#define RTD128X_RTC_CR_OFFSET 0x030 + +#define RTD128X_RTC_BASE (RTD128X_RTC_BASE_OFFSET) +#define RTD128X_RTC_SEC (RTD128X_RTC_BASE+RTD128X_RTC_SEC_OFFSET) +#define RTD128X_RTC_MIN (RTD128X_RTC_BASE+RTD128X_RTC_MIN_OFFSET) +#define RTD128X_RTC_HR (RTD128X_RTC_BASE+RTD128X_RTC_HR_OFFSET) +#define RTD128X_RTC_DATE1 (RTD128X_RTC_BASE+RTD128X_RTC_DATE1_OFFSET) +#define RTD128X_RTC_DATE2 (RTD128X_RTC_BASE+RTD128X_RTC_DATE2_OFFSET) +#define RTD128X_RTC_ALMMIN (RTD128X_RTC_BASE+RTD128X_RTC_ALMMIN_OFFSET) +#define RTD128X_RTC_ALMHR (RTD128X_RTC_BASE+RTD128X_RTC_ALMHR_OFFSET) +#define RTD128X_RTC_ALMDATE1 (RTD128X_RTC_BASE+RTD128X_RTC_ALMDATE1_OFFSET) +#define RTD128X_RTC_ALMDATE2 (RTD128X_RTC_BASE+RTD128X_RTC_ALMDATE2_OFFSET) +#define RTD128X_RTC_STOP (RTD128X_RTC_BASE+RTD128X_RTC_STOP_OFFSET) +#define RTD128X_RTC_ACR (RTD128X_RTC_BASE+RTD128X_RTC_ACR_OFFSET) +#define RTD128X_RTC_EN (RTD128X_RTC_BASE+RTD128X_RTC_EN_OFFSET) +#define RTD128X_RTC_CR (RTD128X_RTC_BASE+RTD128X_RTC_CR_OFFSET) + +/* + * SB2 + */ + +#define RTD128X_SB2_HD_SEM_OFFSET 0x000 +#define RTD128X_SB2_INV_INTEN_OFFSET 0x004 +#define RTD128X_SB2_INV_INTSTAT_OFFSET 0x008 +#define RTD128X_SB2_INV_ADDR_OFFSET 0x00c + +#define RTD128X_SB2_CHIP_ID_OFFSET 0x200 +#define RTD128X_SB2_CHIP_INFO_OFFSET 0x204 + +#define RTD128X_SB2_DBG_START_REG0_OFFSET 0x458 +#define RTD128X_SB2_DBG_START_REG1_OFFSET 0x45c +#define RTD128X_SB2_DBG_START_REG2_OFFSET 0x460 +#define RTD128X_SB2_DBG_START_REG3_OFFSET 0x464 +#define RTD128X_SB2_DBG_START_REG4_OFFSET 0x468 +#define RTD128X_SB2_DBG_START_REG5_OFFSET 0x46c +#define RTD128X_SB2_DBG_START_REG6_OFFSET 0x470 +#define RTD128X_SB2_DBG_START_REG7_OFFSET 0x474 + +#define RTD128X_SB2_DBG_END_REG0_OFFSET 0x478 +#define RTD128X_SB2_DBG_END_REG1_OFFSET 0x47c +#define RTD128X_SB2_DBG_END_REG2_OFFSET 0x480 +#define RTD128X_SB2_DBG_END_REG3_OFFSET 0x484 +#define RTD128X_SB2_DBG_END_REG4_OFFSET 0x488 +#define RTD128X_SB2_DBG_END_REG5_OFFSET 0x48c +#define RTD128X_SB2_DBG_END_REG6_OFFSET 0x490 +#define RTD128X_SB2_DBG_END_REG7_OFFSET 0x494 + +#define RTD128X_SB2_DBG_CTRL_REG0_OFFSET 0x498 +#define RTD128X_SB2_DBG_CTRL_REG1_OFFSET 0x49c +#define RTD128X_SB2_DBG_CTRL_REG2_OFFSET 0x4a0 +#define RTD128X_SB2_DBG_CTRL_REG3_OFFSET 0x4a4 +#define RTD128X_SB2_DBG_CTRL_REG4_OFFSET 0x4a8 +#define RTD128X_SB2_DBG_CTRL_REG5_OFFSET 0x4ac +#define RTD128X_SB2_DBG_CTRL_REG6_OFFSET 0x4b0 +#define RTD128X_SB2_DBG_CTRL_REG7_OFFSET 0x4b4 + +#define RTD128X_SB2_DBG_ADDR_AUDIO_OFFSET 0x4b8 +#define RTD128X_SB2_DBG_ADDR_VIDEO_OFFSET 0x4bc +#define RTD128X_SB2_DBG_ADDR_SYSTEM_OFFSET 0x4c0 + +#define RTD128X_SB2_DBG_INT_OFFSET 0x4e0 + +#define RTD128X_SB2_BASE (RTD128X_SB2_BASE_OFFSET) +#define RTD128X_SB2_HD_SEM (RTD128X_SB2_BASE+RTD128X_SB2_HD_SEM_OFFSET) +#define RTD128X_SB2_INV_INTEN (RTD128X_SB2_BASE+RTD128X_SB2_INV_INTEN_OFFSET) +#define RTD128X_SB2_INV_INTSTAT (RTD128X_SB2_BASE+RTD128X_SB2_INV_INTSTAT_OFFSET) +#define RTD128X_SB2_INV_ADDR (RTD128X_SB2_BASE+RTD128X_SB2_INV_ADDR_OFFSET) + +#define RTD128X_SB2_CHIP_ID (RTD128X_SB2_BASE+RTD128X_SB2_CHIP_ID_OFFSET) +#define RTD128X_SB2_CHIP_INFO (RTD128X_SB2_BASE+RTD128X_SB2_CHIP_INFO_OFFSET) + +#define RTD128X_SB2_DBG_START_REG0 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_START_REG0_OFFSET) +#define RTD128X_SB2_DBG_START_REG1 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_START_REG1_OFFSET) +#define RTD128X_SB2_DBG_START_REG2 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_START_REG2_OFFSET) +#define RTD128X_SB2_DBG_START_REG3 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_START_REG3_OFFSET) +#define RTD128X_SB2_DBG_START_REG4 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_START_REG4_OFFSET) +#define RTD128X_SB2_DBG_START_REG5 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_START_REG5_OFFSET) +#define RTD128X_SB2_DBG_START_REG6 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_START_REG6_OFFSET) +#define RTD128X_SB2_DBG_START_REG7 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_START_REG7_OFFSET) + +#define RTD128X_SB2_DBG_END_REG0 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_END_REG0_OFFSET) +#define RTD128X_SB2_DBG_END_REG1 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_END_REG1_OFFSET) +#define RTD128X_SB2_DBG_END_REG2 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_END_REG2_OFFSET) +#define RTD128X_SB2_DBG_END_REG3 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_END_REG3_OFFSET) +#define RTD128X_SB2_DBG_END_REG4 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_END_REG4_OFFSET) +#define RTD128X_SB2_DBG_END_REG5 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_END_REG5_OFFSET) +#define RTD128X_SB2_DBG_END_REG6 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_END_REG6_OFFSET) +#define RTD128X_SB2_DBG_END_REG7 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_END_REG7_OFFSET) + +#define RTD128X_SB2_DBG_CTRL_REG0 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_CTRL_REG0_OFFSET) +#define RTD128X_SB2_DBG_CTRL_REG1 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_CTRL_REG1_OFFSET) +#define RTD128X_SB2_DBG_CTRL_REG2 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_CTRL_REG2_OFFSET) +#define RTD128X_SB2_DBG_CTRL_REG3 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_CTRL_REG3_OFFSET) +#define RTD128X_SB2_DBG_CTRL_REG4 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_CTRL_REG4_OFFSET) +#define RTD128X_SB2_DBG_CTRL_REG5 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_CTRL_REG5_OFFSET) +#define RTD128X_SB2_DBG_CTRL_REG6 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_CTRL_REG6_OFFSET) +#define RTD128X_SB2_DBG_CTRL_REG7 (RTD128X_SB2_BASE+RTD128X_SB2_DBG_CTRL_REG7_OFFSET) + +#define RTD128X_SB2_DBG_ADDR_AUDIO (RTD128X_SB2_BASE+RTD128X_SB2_DBG_ADDR_AUDIO_OFFSET) +#define RTD128X_SB2_DBG_ADDR_VIDEO (RTD128X_SB2_BASE+RTD128X_SB2_DBG_ADDR_VIDEO_OFFSET) +#define RTD128X_SB2_DBG_ADDR_SYSTEM (RTD128X_SB2_BASE+RTD128X_SB2_DBG_ADDR_SYSTEM_OFFSET) + +#define RTD128X_SB2_DBG_INT (RTD128X_SB2_BASE+RTD128X_SB2_DBG_INT_OFFSET) + +#endif diff -uNr linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-irq.h linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-irq.h --- linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-irq.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-irq.h 2010-11-19 18:20:21.000000000 +0100 @@ -0,0 +1,70 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#ifndef _RTD128X_IRQ_H +#define _RTD128X_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 + +#ifdef CONFIG_RTD128X_EXTERNAL_TIMER +#define MIPS_CPU_TIMER_IRQ RTD128X_IRQ_EXT_TIMER +#else +#define MIPS_CPU_TIMER_IRQ RTD128X_IRQ_TIMER +#endif + +#define RTD128X_IRQ_BASE 2 +#define RTD128X_INTERNAL_IRQ_BASE 8 + +#define RTD128X_MISC_IRQ_UART0 2 +#define RTD128X_MISC_IRQ_UART1 3 +#define RTD128X_MISC_IRQ_I2C0 4 +#define RTD128X_MISC_IRQ_IRDA 5 + +#define RTD128X_MISC_IRQ_TIMER2 8 + +#define RTD128X_MISC_IRQ_VFD_DONE 14 +#define RTD128X_MISC_IRQ_KP_DOWN 15 +#define RTD128X_MISC_IRQ_KP_UP 16 +#define RTD128X_MISC_IRQ_SW_DOWN 17 +#define RTD128X_MISC_IRQ_SW_UP 18 + +#define RTD128X_MISC_IRQ_GPIO 20 +#define RTD128X_MISC_IRQ_PCMCIA 21 +#define RTD128X_MISC_IRQ_CEC_TX 22 +#define RTD128X_MISC_IRQ_CEC_RX 23 +#define RTD128X_MISC_IRQ_SCARD0 24 +#define RTD128X_MISC_IRQ_SCARD1 25 +#define RTD128X_MISC_IRQ_I2C1 26 + +#define RTD128X_IRQ_USB (RTD128X_IRQ_BASE+0) +#define RTD128X_IRQ_ETH (RTD128X_IRQ_BASE+0) +#define RTD128X_IRQ_MISC (RTD128X_IRQ_BASE+1) +#define RTD128X_IRQ_CP (RTD128X_IRQ_BASE+1) +#define RTD128X_IRQ_1394 (RTD128X_IRQ_BASE+2) +#define RTD128X_IRQ_ATA (RTD128X_IRQ_BASE+2) +#define RTD128X_IRQ_AUD (RTD128X_IRQ_BASE+3) +#define RTD128X_IRQ_VID (RTD128X_IRQ_BASE+3) +#define RTD128X_IRQ_SE (RTD128X_IRQ_BASE+3) +#define RTD128X_IRQ_SB2 (RTD128X_IRQ_BASE+3) +#define RTD128X_IRQ_EXT_TIMER (RTD128X_IRQ_BASE+4) +#define RTD128X_IRQ_TIMER (RTD128X_IRQ_BASE+5) +#define RTD128X_IRQ_RTC (RTD128X_IRQ_BASE+5) + +#define RTD128X_IRQ_UART0 (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_UART0) +#define RTD128X_IRQ_UART1 (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_UART1) +#define RTD128X_IRQ_I2C0 (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_I2C0) + +#define RTD128X_IRQ_TIMER2 (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_TIMER2) + +#define RTD128X_IRQ_PCMCIA (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_PCMCIA) +#define RTD128X_IRQ_CEC_TX (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_CEC_TX) +#define RTD128X_IRQ_CEC_RX (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_CEC_RX) +#define RTD128X_IRQ_SCARD0 (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_SCARD0) +#define RTD128X_IRQ_SCARD1 (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_SCARD1) +#define RTD128X_IRQ_I2C1 (RTD128X_INTERNAL_IRQ_BASE+RTD128X_MISC_IRQ_I2C1) + +#endif diff -uNr linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-soc.h linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-soc.h --- linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-soc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-soc.h 2010-11-19 18:20:28.000000000 +0100 @@ -0,0 +1,41 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#ifndef _RTD128X_SOC_H_ +#define _RTD128X_SOC_H_ + +#define RTD128X_DEFAULT_LEXRA_MEMBASE 0x01b00000 +#define RTD128X_DEFAULT_HIGHMEM_START 0x02000000 + +#define RTD128X_IO_PORT_BASE 0x18010000 + +#define RTD128X_CHIPID_VENUS 0x1281 +#define RTD128X_CHIPID_NEPTUNE 0x1282 +#define RTD128X_CHIPID_MARS 0x1283 +#define RTD128X_CHIPID_JUPITER 0x1284 + +static inline int rtd128x_is_venus_soc(void) +{ + return (rtd128x_board_info.chip_id == RTD128X_CHIPID_VENUS); +} + +static inline int rtd128x_is_neptune_soc(void) +{ + return (rtd128x_board_info.chip_id == RTD128X_CHIPID_NEPTUNE); +} + +static inline int rtd128x_is_mars_soc(void) +{ + return (rtd128x_board_info.chip_id == RTD128X_CHIPID_MARS); +} + +static inline int rtd128x_is_jupiter_soc(void) +{ + return (rtd128x_board_info.chip_id == RTD128X_CHIPID_JUPITER); +} + +#endif diff -uNr linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/war.h linux-2.6.36/arch/mips/include/asm/mach-rtd128x/war.h --- linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/war.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/include/asm/mach-rtd128x/war.h 2010-11-16 19:05:54.000000000 +0100 @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ + +#ifndef __ASM_MIPS_MACH_RTD128x_WAR_H +#define __ASM_MIPS_MACH_RTD128x_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_RTD128x_WAR_H */ diff -uNr linux-2.6.36-vanilla/arch/mips/Kbuild.platforms linux-2.6.36/arch/mips/Kbuild.platforms --- linux-2.6.36-vanilla/arch/mips/Kbuild.platforms 2010-10-20 23:23:01.000000000 +0200 +++ linux-2.6.36/arch/mips/Kbuild.platforms 2010-11-16 01:16:43.000000000 +0100 @@ -18,6 +18,7 @@ platforms += pnx833x platforms += pnx8550 platforms += powertv +platforms += rtd128x platforms += rb532 platforms += sgi-ip22 platforms += sgi-ip27 diff -uNr linux-2.6.36-vanilla/arch/mips/Kconfig linux-2.6.36/arch/mips/Kconfig --- linux-2.6.36-vanilla/arch/mips/Kconfig 2010-10-20 23:23:01.000000000 +0200 +++ linux-2.6.36/arch/mips/Kconfig 2010-11-16 01:16:43.000000000 +0100 @@ -706,6 +706,22 @@ Hikari Say Y here for most Octeon reference boards. +config RTD128X + bool "Realtek Galaxy SoC based boards" + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select GENERIC_ISA_DMA + select DMA_NONCOHERENT + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_ZBOOT_UART16550 + help + This options supports Realtek SoC based boards. + Say Y here for Realtek SoC based boards. + endchoice source "arch/mips/alchemy/Kconfig" @@ -721,6 +737,7 @@ source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson/Kconfig" +source "arch/mips/rtd128x/Kconfig" endmenu diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/board.c linux-2.6.36/arch/mips/rtd128x/common/board.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/board.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/board.c 2010-11-19 18:09:57.000000000 +0100 @@ -0,0 +1,137 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include + +#include +#include +#include + +struct rtd128x_board rtd128x_board_info; + +static struct rtd128x_board rtd128x_em7080_info = { + .name = "em7080", + .ext_freq = 27000000, + .has_eth0 = 1, + .has_pci = 0, + .has_pccard = 0, + .has_ohci0 = 1, + .has_ehci0 = 1, + .has_sata0 = 1, + .has_sata1 = 1, + .has_uart0 = 1, + .has_uart1 = 1, + .has_vfd = 0, + .machine_restart = NULL, + .machine_halt = NULL, + .machine_poweroff = NULL, +}; + +/* + * rtd128x reset and halt handlers + */ + +static void rtd128x_common_machine_restart(char *cmd) +{ +#ifdef CONFIG_RTD128X_WATCHDOG + /* + * Use Watchdog to reset SoC + */ + kill_watchdog(); +#else + /* + * TODO: Find a way to reset the SoC + */ + outl(0x0, RTD128X_TIMR_TCWCR); +#endif + msleep(5000); +} + +static void rtd128x_common_machine_halt(void) +{ + msleep(5000); +} + +/* + * rtd128x soc + */ + +static const char *rtd128x_get_soc_name(void) +{ + switch (rtd128x_board_info.chip_id) { + case RTD128X_CHIPID_VENUS: + return "Venus"; + case RTD128X_CHIPID_NEPTUNE: + return "Neptune"; + case RTD128X_CHIPID_MARS: + return "Mars"; + case RTD128X_CHIPID_JUPITER: + return "Jupiter"; + } + return "unknown"; +} + +void rtd128x_detect_soc(void) +{ + u32 id, rev; + + id = inl(RTD128X_SB2_CHIP_ID); + rev = inl(RTD128X_SB2_CHIP_INFO); + + rtd128x_board_info.chip_id = id & 0xffff; + rtd128x_board_info.chip_rev = (id >> 16) & 0xffff; + + printk("Detected rtd%04x SoC, type %s rev %x\n", + rtd128x_board_info.chip_id, + rtd128x_get_soc_name(), rtd128x_board_info.chip_rev); +} + +/* + * rtd128x boards + */ + +static enum rtd128x_board_type rtd128x_detect_board(void) +{ + return RTD128X_BOARD_EM7080; + + /* + * TODO: Detect different board types + */ + + return RTD128X_BOARD_UNKNOWN; +} + +void rtd128x_board_setup(void) +{ + switch (rtd128x_detect_board()) { + case RTD128X_BOARD_EM7080: + memcpy(&rtd128x_board_info, &rtd128x_em7080_info, + sizeof(struct rtd128x_board)); + break; + default: + printk("Unknown rtd128x board."); + return; + } + + if (rtd128x_board_info.machine_restart == NULL) { + rtd128x_board_info.machine_restart = + rtd128x_common_machine_restart; + } + + if (rtd128x_board_info.machine_halt == NULL) { + rtd128x_board_info.machine_halt = rtd128x_common_machine_halt; + } + + if (rtd128x_board_info.machine_poweroff == NULL) { + rtd128x_board_info.machine_poweroff = + rtd128x_common_machine_halt; + } + + printk("Detected %s board\n", rtd128x_board_info.name); +} diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/irq.c linux-2.6.36/arch/mips/rtd128x/common/irq.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/irq.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/irq.c 2010-11-19 18:10:09.000000000 +0100 @@ -0,0 +1,137 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +extern void rtd128x_sb2_setup(void); + +static int rtd128x_internal_irq_dispatch(void) +{ + u32 pending; + static int i; + + pending = inl(RTD128X_MISC_ISR); + + if (!pending) + return 0; + + while (1) { + int to_call = i; + + i = (i + 1) & 0x1f; + if (pending & (1 << to_call)) { + do_IRQ(to_call + RTD128X_INTERNAL_IRQ_BASE); + break; + } + } + return 1; +} + +void plat_irq_dispatch(void) +{ + u32 cause; + + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP; + + clear_c0_status(cause); + + if (cause & CAUSEF_IP7) + do_IRQ(7); + if (cause & CAUSEF_IP2) + do_IRQ(2); + if ((cause & CAUSEF_IP3) && (!rtd128x_internal_irq_dispatch())) + do_IRQ(3); + if (cause & CAUSEF_IP4) + do_IRQ(4); + if (cause & CAUSEF_IP5) + do_IRQ(5); + if (cause & CAUSEF_IP6) + do_IRQ(6); +} + +static inline void rtd128x_internal_irq_mask(unsigned int irq) +{ +#if 0 + u32 mask; + + irq -= RTD128X_INTERNAL_IRQ_BASE; + mask = inl(RTD128X_MISC_UMSK_ISR); + mask &= ~(1 << irq); + outl(mask, RTD128X_MISC_UMSK_ISR); +#endif +} + +static void rtd128x_internal_irq_unmask(unsigned int irq) +{ +#if 0 + u32 mask; + + irq -= RTD128X_INTERNAL_IRQ_BASE; + mask = inl(RTD128X_MISC_UMSK_ISR); + mask |= (1 << irq); + outl(mask, RTD128X__MISC_UMSK_ISR); +#endif +} + +static void rtd128x_internal_irq_ack(unsigned int irq) +{ + irq -= RTD128X_INTERNAL_IRQ_BASE; + outl((1 << irq), RTD128X_MISC_ISR); +} + +static void rtd128x_internal_irq_mask_ack(unsigned int irq) +{ + rtd128x_internal_irq_mask(irq); + rtd128x_internal_irq_ack(irq); +} + +static unsigned int rtd128x_internal_irq_startup(unsigned int irq) +{ + rtd128x_internal_irq_unmask(irq); + return 0; +} + +static struct irq_chip rtd128x_internal_irq_chip = { + .name = "rtd128x-irq", + .startup = rtd128x_internal_irq_startup, + .shutdown = rtd128x_internal_irq_mask, + .ack = rtd128x_internal_irq_ack, + .mask = rtd128x_internal_irq_mask, + .mask_ack = rtd128x_internal_irq_mask_ack, + .unmask = rtd128x_internal_irq_unmask, +}; + +void __init arch_init_irq(void) +{ + int i; + + /* disable RTC interrupts */ + outl(0x0000, RTD128X_RTC_CR); + + /* clear device interrupts */ + outl(0x3ffc, RTD128X_MISC_ISR); + + mips_cpu_irq_init(); + + for (i = 0; i < 32; ++i) + set_irq_chip_and_handler(RTD128X_INTERNAL_IRQ_BASE + i, + &rtd128x_internal_irq_chip, + handle_level_irq); + + set_c0_status(1 << (RTD128X_IRQ_MISC + 8)); + + rtd128x_sb2_setup(); +} diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/Makefile linux-2.6.36/arch/mips/rtd128x/common/Makefile --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/Makefile 2010-11-16 01:16:43.000000000 +0100 @@ -0,0 +1,10 @@ +obj-$(CONFIG_RTD128X) += platform.o +obj-$(CONFIG_RTD128X) += irq.o +obj-$(CONFIG_RTD128X) += memory.o +obj-$(CONFIG_RTD128X) += prom.o +obj-$(CONFIG_RTD128X) += setup.o +obj-$(CONFIG_RTD128X) += time.o +obj-$(CONFIG_RTD128X) += board.o +obj-$(CONFIG_RTD128X) += printk.o +obj-$(CONFIG_RTD128X) += sb2.o + diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/memory.c linux-2.6.36/arch/mips/rtd128x/common/memory.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/memory.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/memory.c 2010-11-19 18:10:26.000000000 +0100 @@ -0,0 +1,202 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +//#define DEBUG + +enum yamon_memtypes { + yamon_dontuse, + yamon_prom, + yamon_free, +}; +static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +#ifdef DEBUG +static char *mtypes[3] = { + "Dont use memory", + "YAMON PROM memory", + "Free memmory", +}; +#endif + +/* determined physical memory size, not overridden by command line args */ +unsigned long physical_memsize = 0L; +unsigned long lexra_membase = 0L; + +static struct prom_pmemblock *__init prom_getmdesc(void) +{ + char *memsize_str; + unsigned int memsize; + char *ptr; + static char cmdline[COMMAND_LINE_SIZE] __initdata; + + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + printk(KERN_WARNING + "memsize not set in boot prom, set to default (32Mb)\n"); + physical_memsize = 0x02000000; + } else { +#ifdef DEBUG + pr_debug("prom_memsize = %s\n", memsize_str); +#endif + physical_memsize = simple_strtol(memsize_str, NULL, 0); + } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + word of physical memory */ + physical_memsize -= PAGE_SIZE; +#endif + + /* Check the command line for a memsize directive that overrides + the physical/default amount */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) + memsize = memparse(ptr + 8, &ptr); + else + memsize = physical_memsize; + + /* Check the command line for lexra_membase directive that overrides + the default base address */ + ptr = strstr(cmdline, "lexra_membase="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " lexra_membase="); + + if (ptr) + lexra_membase = memparse(ptr + 8, &ptr); + else + lexra_membase = RTD128X_DEFAULT_LEXRA_MEMBASE; + + lexra_membase = CPHYSADDR(PFN_ALIGN(lexra_membase)); + + memset(mdesc, 0, sizeof(mdesc)); + + /* + * free pre-kernel memory + */ + mdesc[0].type = yamon_free; + mdesc[0].base = 0x00000000; + mdesc[0].size = CPHYSADDR(PFN_ALIGN(&_text)); + + /* + * protect kernel memory + */ + mdesc[1].type = yamon_dontuse; + mdesc[1].base = CPHYSADDR(PFN_ALIGN(&_text)); + mdesc[1].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[1].base; + + /* + * free post-kernel memory + */ + mdesc[2].type = yamon_free; + mdesc[2].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[2].size = lexra_membase - mdesc[2].base; + + /* + * protect lexra memory + */ + mdesc[3].type = yamon_dontuse; + mdesc[3].base = lexra_membase; + mdesc[3].size = RTD128X_DEFAULT_HIGHMEM_START - mdesc[3].base; + + /* + * kernel high memory + */ + mdesc[4].type = yamon_free; + mdesc[4].base = RTD128X_DEFAULT_HIGHMEM_START; + mdesc[4].size = memsize - mdesc[4].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case yamon_free: + return BOOT_MEM_RAM; + case yamon_prom: + return BOOT_MEM_ROM_DATA; + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + + p = prom_getmdesc(); + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + unsigned long recl = 0; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + recl += + (1 + + (boot_mem_map.map[i].size >> PAGE_SHIFT)) << PAGE_SHIFT; + } + + printk("Freeing PROM memory: %luk\n", recl / 1024); + +#ifdef CONFIG_RTD128X_RECLAIM_BOOT_MEMORY + { + unsigned long addr = 0; + unsigned long dest = 0; + + if (rtd138x_is_mars_cpu()) { + addr = F_ADDR2; + dest = (debug_flag) ? T_ADDR1 : T_ADDR3; + } else { + addr = F_ADDR1; + dest = (debug_flag) ? T_ADDR1 : T_ADDR2; + } + + free_init_pages("bootloader memory", addr, dest); + recl = dest - addr; + recl = (1 + (recl >> PAGE_SHIFT)) << PAGE_SHIFT; + printk("Reclaimed bootloader memory: %luk\n", recl); + } +#endif +} diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/platform.c linux-2.6.36/arch/mips/rtd128x/common/platform.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/platform.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/platform.c 2010-11-19 18:10:34.000000000 +0100 @@ -0,0 +1,103 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include + +#include +#include +#include +#include + +/* + * rtd128x uart + */ + +static unsigned int rtd128x_serial_in(struct uart_port *p, int offset) +{ + offset <<= p->regshift; + return readl(p->membase + offset) & 0xff; +} + +static void rtd128x_serial_out(struct uart_port *p, int offset, int value) +{ + offset <<= p->regshift; + writel(value & 0xff, p->membase + offset); +} + +static struct plat_serial8250_port rtd128x_serial_data[] = { + [0] = {}, + [1] = {}, + {} +}; + +static struct platform_device rtd128x_serial8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = rtd128x_serial_data, + }, +}; + +static void __init rtd128x_register_uart(void) +{ + int n = 0; + + if (rtd128x_board_info.has_uart0) { + rtd128x_serial_data[n].iobase = RTD128X_UART0_BASE; + rtd128x_serial_data[n].membase = + (unsigned char __iomem *)KSEG1ADDR(RTD128X_IO_PORT_BASE + + RTD128X_UART0_BASE); + rtd128x_serial_data[n].mapbase = + RTD128X_IO_PORT_BASE + RTD128X_UART0_BASE; + rtd128x_serial_data[n].irq = RTD128X_IRQ_UART0; + rtd128x_serial_data[1].uartclk = rtd128x_board_info.ext_freq; + rtd128x_serial_data[n].iotype = UPIO_MEM; + rtd128x_serial_data[n].flags = UPF_BOOT_AUTOCONF; + rtd128x_serial_data[n].regshift = 2; + rtd128x_serial_data[n].serial_in = &rtd128x_serial_in; + rtd128x_serial_data[n].serial_out = &rtd128x_serial_out; + n++; + } + + if (rtd128x_board_info.has_uart1) { + rtd128x_serial_data[n].iobase = RTD128X_UART1_BASE; + rtd128x_serial_data[n].membase = + (unsigned char __iomem *)KSEG1ADDR(RTD128X_IO_PORT_BASE + + RTD128X_UART1_BASE); + rtd128x_serial_data[n].mapbase = + RTD128X_IO_PORT_BASE + RTD128X_UART1_BASE; + rtd128x_serial_data[n].irq = RTD128X_IRQ_UART1; + rtd128x_serial_data[0].uartclk = rtd128x_board_info.ext_freq; + rtd128x_serial_data[n].iotype = UPIO_MEM; + rtd128x_serial_data[n].flags = UPF_BOOT_AUTOCONF; + rtd128x_serial_data[n].regshift = 2; + rtd128x_serial_data[n].serial_in = &rtd128x_serial_in; + rtd128x_serial_data[n].serial_out = &rtd128x_serial_out; + n++; + } + + if (n) + platform_device_register(&rtd128x_serial8250_device); +} + +/* + * platform and device init + */ + +void __init platform_init(void) +{ +} + +static int __init rtd128x_devinit(void) +{ + rtd128x_register_uart(); + return 0; +} + +device_initcall(rtd128x_devinit); diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/printk.c linux-2.6.36/arch/mips/rtd128x/common/printk.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/printk.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/printk.c 2010-11-19 18:10:44.000000000 +0100 @@ -0,0 +1,33 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include + +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ + +static void __init wait_xfered(void) +{ + unsigned int val; + + /* wait for any previous char to be transmitted */ + do { + val = inl(RTD128X_UART_U0LSR); + if ((val & (UART_LSR_TEMT | UART_LSR_THRE)) == + (UART_LSR_TEMT | UART_LSR_THRE)) + break; + } while (1); +} + +void __init prom_putchar(char c) +{ + wait_xfered(); + outl(c, RTD128X_UART_U0RBR_THR_DLL); + wait_xfered(); +} diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/prom.c linux-2.6.36/arch/mips/rtd128x/common/prom.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/prom.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/prom.c 2010-11-19 18:11:05.000000000 +0100 @@ -0,0 +1,250 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +extern void platform_init(void); +extern void platform_setup(void); +extern void prom_putchar(char); +extern void rtd128x_detect_soc(void); + +//#define DEBUG + +void prom_puts(char *s) +{ + while (*s != '\0') { + if (*s == '\n') { + prom_putchar(*s++); + prom_putchar('\r'); + } else + prom_putchar(*s++); + } +} + +void prom_puthex(unsigned long l) +{ + char n; + int i; + prom_putchar('0'); + prom_putchar('x'); + for (i = 7; i >= 0; i--) { + n = (char)((l >> (4 * i)) & 0xf); + switch (n) { + case 10: + prom_putchar('a'); + break; + case 11: + prom_putchar('b'); + break; + case 12: + prom_putchar('c'); + break; + case 13: + prom_putchar('d'); + break; + case 14: + prom_putchar('e'); + break; + case 15: + prom_putchar('f'); + break; + default: + prom_putchar(0x30 + n); + } + } +} + +int prom_argc; +int *_prom_argv, *_prom_envp; +unsigned long _prom_memsize; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +char *prom_getenv(char *envname) +{ + char *result = NULL; + + if (_prom_envp != NULL) { + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index = 0; + + i = strlen(envname); + + while (prom_envp(index)) { + if (strncmp(envname, prom_envp(index), i) == 0) { + result = prom_envp(index + 1); + break; + } + index += 2; + } + } + + return result; +} + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char *__init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while (actr < prom_argc) { + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) { + /* get rid of trailing space */ + --cp; + *cp = '\0'; + } +} + +/* TODO: Verify on linux-mips mailing list that the following two */ +/* functions are correct */ +/* TODO: Copy NMI and EJTAG exception vectors to memory from the */ +/* BootROM exception vectors. Flush their cache entries. test it. */ + +static void __init mips_nmi_setup(void) +{ + void *base; +#if defined(CONFIG_CPU_MIPS32_R1) + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : (void *)(CAC_BASE + 0x380); +#elif defined(CONFIG_CPU_MIPS32_R2) + base = (void *)0xbfc00000; +#else +#error NMI exception handler address not defined +#endif +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + +#if defined(CONFIG_CPU_MIPS32_R1) + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : (void *)(CAC_BASE + 0x300); +#elif defined(CONFIG_CPU_MIPS32_R2) + base = (void *)0xbfc00480; +#else +#error EJTAG exception handler address not defined +#endif +} + +void __init rtd128x_env_get_bootrev(void) +{ + char *envp; + unsigned short v0, v1, v2; + + envp = prom_getenv("bootrev"); + if (envp) { + strcpy(rtd128x_board_info.bootrev, envp); + sscanf(envp, "%hx.%hx.%hx", &v0, &v1, &v2); + + rtd128x_board_info.company_id = v0; + rtd128x_board_info.board_id = (v0 << 16) | v1; + + /* old bootrev format : aa.bb.ccc */ + /* new bootrev format : aaaa.bbbb.cccc */ + if (envp[2] == '.') + rtd128x_board_info.cpu_id = (v1 & 0xf0) >> 4; + else + rtd128x_board_info.cpu_id = (v1 & 0xff00) >> 8; +#ifdef DEBUG + printk + ("bootrev = '%s' => company_id = %04x, cpu_id = %02x, board_id = %08x\n", + rtd128x_board_info.bootrev, rtd128x_board_info.company_id, + rtd128x_board_info.cpu_id, rtd128x_board_info.board_id); +#endif + } +} + +void __init prom_init(void) +{ + int i; + prom_argc = fw_arg0; + _prom_argv = (int *)fw_arg1; + _prom_envp = (int *)fw_arg2; + _prom_memsize = (unsigned long)fw_arg3; + + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + rtd128x_board_info.memory_size = _prom_memsize; + + rtd128x_env_get_bootrev(); + + set_io_port_base(KSEG1ADDR(RTD128X_IO_PORT_BASE)); + rtd128x_detect_soc(); + + platform_init(); + prom_init_cmdline(); + prom_meminit(); +} diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/sb2.c linux-2.6.36/arch/mips/rtd128x/common/sb2.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/sb2.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/sb2.c 2010-11-19 18:11:12.000000000 +0100 @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include + +#include +#include + +static irqreturn_t rtd128x_sb2_irq_handler(int irq, void *dev_id) +{ + unsigned int addr; + + if (!(inl(RTD128X_SB2_INV_INTSTAT) & 0x2)) + return IRQ_NONE; + + /* + * The seems to be a problem on Mars with prefetching + * specific memory regions. This patch should circumvent + * this bug. + */ + addr = inl(RTD128X_SB2_INV_ADDR); + if (addr > 0x8001000 && ((addr & 0xfffff000) != 0x1800c000)) { + printk("Access to invalid hw address 0x%x\n", addr); + } + outl(0xE, RTD128X_SB2_INV_INTSTAT); + + return IRQ_HANDLED; +} + +static struct irqaction rtd128x_sb2_irq_action = { + .handler = rtd128x_sb2_irq_handler, + .flags = IRQF_SHARED, + .name = "rtd128x-sb2", +}; + +void __init rtd128x_sb2_setup(void) +{ + outl(0x3, RTD128X_SB2_INV_INTEN); + outl(0xe, RTD128X_SB2_INV_INTSTAT); + setup_irq(RTD128X_IRQ_SB2, &rtd128x_sb2_irq_action); +} diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/setup.c linux-2.6.36/arch/mips/rtd128x/common/setup.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/setup.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/setup.c 2010-11-19 18:11:21.000000000 +0100 @@ -0,0 +1,179 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern void rtd128x_board_setup(void); + +#define VAL(n) STR(n) + +/* + * Macros for loading addresses and storing registers: + * LONG_L_ Stringified version of LONG_L for use in asm() statement + * LONG_S_ Stringified version of LONG_S for use in asm() statement + * PTR_LA_ Stringified version of PTR_LA for use in asm() statement + * REG_SIZE Number of 8-bit bytes in a full width register + */ +#define LONG_L_ VAL(LONG_L) " " +#define LONG_S_ VAL(LONG_S) " " +#define PTR_LA_ VAL(PTR_LA) " " + +#ifdef CONFIG_64BIT +#warning TODO: 64-bit code needs to be verified +#define REG_SIZE "8" /* In bytes */ +#endif + +#ifdef CONFIG_32BIT +#define REG_SIZE "4" /* In bytes */ +#endif + +static void register_panic_notifier(void); +static int panic_handler(struct notifier_block *notifier_block, + unsigned long event, void *cause_string); + +/* + * Install a panic notifier for platform-specific diagnostics + */ +static void register_panic_notifier() +{ + static struct notifier_block panic_notifier = { + .notifier_call = panic_handler, + .next = NULL, + .priority = INT_MAX + }; + atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier); +} + +static int panic_handler(struct notifier_block *notifier_block, + unsigned long event, void *cause_string) +{ + struct pt_regs my_regs; + + /* Save all of the registers */ + { + unsigned long at, v0, v1; /* Must be on the stack */ + + /* Start by saving $at and v0 on the stack. We use $at + * ourselves, but it looks like the compiler may use v0 or v1 + * to load the address of the pt_regs structure. We'll come + * back later to store the registers in the pt_regs + * structure. */ + __asm__ __volatile__(".set noat\n" + LONG_S_ "$at, %[at]\n" + LONG_S_ "$2, %[v0]\n" + LONG_S_ "$3, %[v1]\n": + [at] "=m"(at),[v0] "=m"(v0),[v1] "=m"(v1) + ::"at"); + + __asm__ __volatile__(".set noat\n" + "move $at, %[pt_regs]\n" + /* Argument registers */ + LONG_S_ "$4, " VAL(PT_R4) "($at)\n" + LONG_S_ "$5, " VAL(PT_R5) "($at)\n" + LONG_S_ "$6, " VAL(PT_R6) "($at)\n" + LONG_S_ "$7, " VAL(PT_R7) "($at)\n" + /* Temporary regs */ + LONG_S_ "$8, " VAL(PT_R8) "($at)\n" + LONG_S_ "$9, " VAL(PT_R9) "($at)\n" + LONG_S_ "$10, " VAL(PT_R10) "($at)\n" + LONG_S_ "$11, " VAL(PT_R11) "($at)\n" + LONG_S_ "$12, " VAL(PT_R12) "($at)\n" + LONG_S_ "$13, " VAL(PT_R13) "($at)\n" + LONG_S_ "$14, " VAL(PT_R14) "($at)\n" + LONG_S_ "$15, " VAL(PT_R15) "($at)\n" + /* "Saved" registers */ + LONG_S_ "$16, " VAL(PT_R16) "($at)\n" + LONG_S_ "$17, " VAL(PT_R17) "($at)\n" + LONG_S_ "$18, " VAL(PT_R18) "($at)\n" + LONG_S_ "$19, " VAL(PT_R19) "($at)\n" + LONG_S_ "$20, " VAL(PT_R20) "($at)\n" + LONG_S_ "$21, " VAL(PT_R21) "($at)\n" + LONG_S_ "$22, " VAL(PT_R22) "($at)\n" + LONG_S_ "$23, " VAL(PT_R23) "($at)\n" + /* Add'l temp regs */ + LONG_S_ "$24, " VAL(PT_R24) "($at)\n" + LONG_S_ "$25, " VAL(PT_R25) "($at)\n" + /* Kernel temp regs */ + LONG_S_ "$26, " VAL(PT_R26) "($at)\n" + LONG_S_ "$27, " VAL(PT_R27) "($at)\n" + /* Global pointer, stack pointer, frame pointer and + * return address */ + LONG_S_ "$gp, " VAL(PT_R28) "($at)\n" + LONG_S_ "$sp, " VAL(PT_R29) "($at)\n" + LONG_S_ "$fp, " VAL(PT_R30) "($at)\n" + LONG_S_ "$ra, " VAL(PT_R31) "($at)\n" + /* Now we can get the $at and v0 registers back and + * store them */ + LONG_L_ "$8, %[at]\n" + LONG_S_ "$8, " VAL(PT_R1) "($at)\n" + LONG_L_ "$8, %[v0]\n" + LONG_S_ "$8, " VAL(PT_R2) "($at)\n" + LONG_L_ "$8, %[v1]\n" + LONG_S_ "$8, " VAL(PT_R3) "($at)\n":: + [at] "m"(at), + [v0] "m"(v0), + [v1] "m"(v1),[pt_regs] "r"(&my_regs) + :"at", "t0"); + + /* Set the current EPC value to be the current location in this + * function */ + __asm__ __volatile__(".set noat\n" + "1:\n" + PTR_LA_ "$at, 1b\n" + LONG_S_ "$at, %[cp0_epc]\n": + [cp0_epc] "=m"(my_regs.cp0_epc) + ::"at"); + + my_regs.cp0_cause = read_c0_cause(); + my_regs.cp0_status = read_c0_status(); + } + + pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " + "zzzz... \n"); + + return NOTIFY_DONE; +} + +const char *get_system_type(void) +{ + return rtd128x_board_info.name; +} + +void __init plat_mem_setup(void) +{ + panic_on_oops = 1; + register_panic_notifier(); + + _machine_restart = rtd128x_board_info.machine_restart; + _machine_halt = rtd128x_board_info.machine_halt; + pm_power_off = rtd128x_board_info.machine_poweroff; + + rtd128x_board_setup(); +} diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/time.c linux-2.6.36/arch/mips/rtd128x/common/time.c --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/time.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/common/time.c 2010-11-19 18:11:27.000000000 +0100 @@ -0,0 +1,87 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +extern void platform_setup(void); + +unsigned long cpu_khz; + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned long flags; + unsigned int count; + unsigned int cause; + + local_irq_save(flags); + + cause = read_c0_cause(); + write_c0_cause(cause & ~0x08000000); + outl(0, RTD128X_TIMR_TC2CR); + outl(0x80000000, RTD128X_TIMR_TC2CR); + + write_c0_count(0); + + while (inl(RTD128X_TIMR_TC2CVR) < (rtd128x_board_info.ext_freq / HZ)) ; + + count = read_c0_count(); + + write_c0_cause(cause); + outl(0, RTD128X_TIMR_TC2CR); + + local_irq_restore(flags); + + count *= HZ; + count *= 2; + count += 5000; /* round */ + count -= count % 10000; + + return count; +} + +unsigned int __init get_c0_compare_int(void) +{ + return RTD128X_IRQ_TIMER; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq; + + est_freq = estimate_cpu_frequency(); + + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000, + (est_freq % 1000000) * 100 / 1000000); + + write_c0_count(0); + write_c0_compare(0xffff); + write_c0_cause(read_c0_cause() & ~0x08000000); + + mips_hpt_frequency = est_freq; +} diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/Kconfig linux-2.6.36/arch/mips/rtd128x/Kconfig --- linux-2.6.36-vanilla/arch/mips/rtd128x/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/Kconfig 2010-11-19 18:09:41.000000000 +0100 @@ -0,0 +1,14 @@ +config RTD128X_RECLAIM_BOOT_MEMORY + bool "reclaim memory from bootloader" + +# +# FIXME: do we really need this? +# +#config RTD128X_EXTERNAL_TIMER +# bool "use external timer interrupt" + +# +# TODO +# +#config RTD128X_WATCHDOG +# bool "use internal watchdog" diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/Makefile linux-2.6.36/arch/mips/rtd128x/Makefile --- linux-2.6.36-vanilla/arch/mips/rtd128x/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/Makefile 2010-11-16 01:16:43.000000000 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_RTD128X) += common/ diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/Platform linux-2.6.36/arch/mips/rtd128x/Platform --- linux-2.6.36-vanilla/arch/mips/rtd128x/Platform 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.36/arch/mips/rtd128x/Platform 2010-11-16 01:16:43.000000000 +0100 @@ -0,0 +1,8 @@ +# +# Realtek Galaxy SoC boards +# + +platform-${CONFIG_RTD128X} += rtd128x/ +cflags-${CONFIG_RTD128X} += -I$(srctree)/arch/mips/include/asm/mach-rtd128x/ +load-${CONFIG_RTD128X} := 0xffffffff80100000 +all-$(CONFIG_RTD128X) := $(COMPRESSION_FNAME).bin From arnaud.patard@rtp-net.org Sun Nov 21 10:59:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2010 10:59:10 +0100 (CET) Received: from lechat.rtp-net.org ([88.191.19.38]:53508 "EHLO lechat.rtp-net.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491040Ab0KUJ7H (ORCPT ); Sun, 21 Nov 2010 10:59:07 +0100 Received: by lechat.rtp-net.org (Postfix, from userid 5001) id 725DF1009C; Sun, 21 Nov 2010 11:01:26 +0100 (CET) Received: from lechat.rtp-net.org (ip6-localhost [IPv6:::1]) by lechat.rtp-net.org (Postfix) with ESMTP id 2D8DB10096; Sun, 21 Nov 2010 11:01:21 +0100 (CET) From: Arnaud Patard (Rtp) To: shmprtd@googlemail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] Add support for Realtek Media Player SoCs Organization: RtpNet References: Date: Sun, 21 Nov 2010 11:01:21 +0100 In-Reply-To: (shmprtd@googlemail.com's message of "Sun, 21 Nov 2010 01:15:11 +0100 (CET)") Message-ID: <87r5efyozy.fsf@lechat.rtp-net.org> User-Agent: Gnus/5.110009 (No Gnus v0.9) Emacs/22.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28437 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arnaud.patard@rtp-net.org Precedence: bulk X-list: linux-mips shmprtd@googlemail.com writes: > Hi, Hi, Please read Documentation/SubmittingPatches. One big patch is just impossible to review (at least for me), please split it in fewer chunks. > > I added support for at least one of the Realtek "Galaxy" SoCs to recent > 2.6.36 kernel. Most of the patch is based on existing linux-mips code and > a 2.6.12 kernel source released by some of Realtek customers. > > Currently, this allows to start the kernel and setup serial console. > Further development/porting will have to be done for additional platform > devices. Do you have an exact status of the different platform device support ? How do you deal with the audio/video support (for instance firmware loading & their rpc stuff) ? > > This code is tested on a Realtek Mars SoC. Commercial product name > is rtd1073dd but cpu/soc id is 0x1283. Other SoCs (Venus,Jupiter,Neptune) > have not been tested, yet. Do you know the differences between the different versions and/or have public specs of the SoCs ? Also, I'm seeing a lot of rtd128x in the file names... Commercial name for the Venus is rtd1261 for instance. I find this really confusing. I would be tempted to use mach-realtek but I don't know enough the realtek mips SoCs to say if it's a good idea. Arnaud From arnaud.patard@rtp-net.org Sun Nov 21 12:38:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2010 12:38:17 +0100 (CET) Received: from lechat.rtp-net.org ([88.191.19.38]:55621 "EHLO lechat.rtp-net.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491083Ab0KULiO (ORCPT ); Sun, 21 Nov 2010 12:38:14 +0100 Received: by lechat.rtp-net.org (Postfix, from userid 5001) id 9E5291009C; Sun, 21 Nov 2010 12:40:36 +0100 (CET) Received: from lechat.rtp-net.org (ip6-localhost [IPv6:::1]) by lechat.rtp-net.org (Postfix) with ESMTP id 4FBD910096; Sun, 21 Nov 2010 12:40:31 +0100 (CET) From: Arnaud Patard (Rtp) To: shmprtd@googlemail.com Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Add support for Realtek Media Player SoCs Organization: RtpNet References: <87r5efyozy.fsf@lechat.rtp-net.org> <4CE8FA88.2020107@googlemail.com> Date: Sun, 21 Nov 2010 12:40:31 +0100 In-Reply-To: <4CE8FA88.2020107@googlemail.com> (shmprtd@googlemail.com's message of "Sun, 21 Nov 2010 11:55:04 +0100") Message-ID: <87mxp2zyz4.fsf@lechat.rtp-net.org> User-Agent: Gnus/5.110009 (No Gnus v0.9) Emacs/22.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28438 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arnaud.patard@rtp-net.org Precedence: bulk X-list: linux-mips shmprtd@googlemail.com writes: > Arnaud Patard (Rtp) wrote: >> Please read Documentation/SubmittingPatches. One big patch is just >> impossible to review (at least for me), please split it in fewer >> chunks. > > I already spoke to Ralf about this. I wanted to submit smaller patches > but as adding initial support is "one logical change" I stuck to one large > patch for now. But I understand the need for a nicer way to review the > changes. Although most of them are new files for the mach anyway. Ok, will harder to look at it, then. At least, that should not prevent you to follow SubmittingPatches way (For instance, there's no signed-off-by in your patch submission). At least, I will try to find time to test it on my rtd1261 board. > >> Do you have an exact status of the different platform device support ? >> How do you deal with the audio/video support (for instance firmware >> loading & their rpc stuff) ? > > I have no exact status except the 2.6.12 source that is delivered with > most (all?) of the media players. As far as I checked the a/v code everything > interesting is done in userspace by ioctls. I don't like it that way but > for a first shot it would be easier to keep it that way and then start to > port it to common kernel interfaces. Can't tell now if this will be possible > at all without any documentation available. yeah, afaik it's ioctl but the code is horrible which makes it hard to understand (see RPCpoll.c, RPCintr.c, se* for instance) and is not necessary the best way to handle that. I've only given a brief look at the realtek 2.6.12.6 tree so I may be missing some stuff. > > The firmware for the Lexras gets copied to reserved mem areas by the bootloader. >>From the debug messages of the original bootloader and kernel I would guess > you can halt, reset and run the Lexras by writing into some registers. ok. > > Other devices include sata, usb, and eth. The eth is a rtl8139c+ where there > is a driver available already but relies on pci. Realtek itself took this > code and modified it for bus accesses. Usb and sata drivers are there from > the 2.6.12 but again I did no in-depth study of the code, yet. yeah but the realtek way of duplicating 8139 code is not really a good path to follow. finding a better way would be nice. I was thinking about a phy driver. I don't know if it's a good idea. Getting ethernet and sata would be first thing to do. This would help testing/developing imho. > >> Do you know the differences between the different versions and/or have >> public specs of the SoCs ? > > I cannot tell you the exact differences between the SoCs and I have no > documentation at all. > too bad. This means we're stuck at parsing the realtek code :/ >> Also, I'm seeing a lot of rtd128x in the file names... Commercial name >> for the Venus is rtd1261 for instance. I find this really >> confusing. I would be tempted to use mach-realtek but I don't know >> enough the realtek mips SoCs to say if it's a good idea. > > Yeah, this is confusing but may be caused by the confusing way realtek > calls their chips. I always thought the rtd1261 is Mars and rtd1071 is > Venus (so the other way round). But the chip id of the rtd1071 tells me > it is Mars and I have no other SoC available. The boot logs of my board are saying "cpu id: 0". In the 2.6.12.6 code I have, it maps to typedef enum { realtek_venus_cpu =0x0, realtek_venus2_cpu =0x10, realtek_neptune_cpu =0x1, realtek_neptuneB_cpu =0x11 } cpu_id_t; So I have a Venus and on it, it's written rtd1261. > > I chose rtd128x because the chip id register for all SoCs named by planets > is 0x1281, 0x1282, 0x1283, aso. Therefore, I thought using value-based > naming would be nicer than weird commercial names. Finding good naming is hard. At least, I wouldn't look for rtd1261 support in something called rtd128x. > > I guess mach-realtek would be to generic (think of rtl8181) but maybe > galaxy could be used because of the planet names of the SoCs. I see. So, maybe galaxy as you're suggesting is better. Ralf, any opinion ? Arnaud From ralf@linux-mips.org Mon Nov 22 01:41:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 01:41:20 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:38159 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491942Ab0KVAlR (ORCPT ); Mon, 22 Nov 2010 01:41:17 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oAM0fF3Z011216; Mon, 22 Nov 2010 00:41:15 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oAM0fEOw011214; Mon, 22 Nov 2010 00:41:14 GMT Date: Mon, 22 Nov 2010 00:41:14 +0000 From: Ralf Baechle To: Arnaud Patard Cc: shmprtd@googlemail.com, linux-mips@linux-mips.org Subject: Re: [PATCH] Add support for Realtek Media Player SoCs Message-ID: <20101122004114.GA10923@linux-mips.org> References: <87r5efyozy.fsf@lechat.rtp-net.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87r5efyozy.fsf@lechat.rtp-net.org> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28439 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Nov 21, 2010 at 11:01:21AM +0100, Arnaud Patard wrote: > Please read Documentation/SubmittingPatches. One big patch is just > impossible to review (at least for me), please split it in fewer > chunks. This is not outrageously huge and actually well smaller than the "atoms" some other patches were split into. Ideally patches should be split such that each patch fixes one bug or adds one feature and such that applying only a part of a patch series does not result in a regression. The absolute size or number of patches at least to me is a secondary consideration. Ralf From ralf@linux-mips.org Mon Nov 22 03:24:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 03:24:42 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42857 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491948Ab0KVCYi (ORCPT ); Mon, 22 Nov 2010 03:24:38 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oAM2Oakv012929; Mon, 22 Nov 2010 02:24:36 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oAM2OZSr012927; Mon, 22 Nov 2010 02:24:35 GMT Date: Mon, 22 Nov 2010 02:24:35 +0000 From: Ralf Baechle To: shmprtd@googlemail.com Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Add support for Realtek Media Player SoCs Message-ID: <20101122022435.GB10923@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28440 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Nov 21, 2010 at 01:15:11AM +0100, shmprtd@googlemail.com wrote: > I added support for at least one of the Realtek "Galaxy" SoCs to recent > 2.6.36 kernel. Most of the patch is based on existing linux-mips code and > a 2.6.12 kernel source released by some of Realtek customers. For submission please use the latest linux-queue git tree or at least the linux-mips tree. > Currently, this allows to start the kernel and setup serial console. > Further development/porting will have to be done for additional platform > devices. > > This code is tested on a Realtek Mars SoC. Commercial product name > is rtd1073dd but cpu/soc id is 0x1283. Other SoCs (Venus,Jupiter,Neptune) > have not been tested, yet. > > Please comment on the patch and feel free to suggest changes that need > to be done prior integration. Let the flaming begin :-) First, when submitting patches, please include a Signed-off-by: line. For details on that, see Documentation/SubmittingPatches in the kernel sources. Strictly seen this is not needed to get a patch reviewed but only for the actual submission of a patch but it's good style to always include it. Other people might grab a patch and base their work on it and even hell might freeze over and a patch might be applied right away. Also please include a diffstat of a patch so everybody can see right away what a particular patch touches. arch/mips/Kbuild.platforms | 1 arch/mips/Kconfig | 17 + arch/mips/include/asm/mach-rtd128x/rtd128x-board.h | 51 +++ arch/mips/include/asm/mach-rtd128x/rtd128x-io.h | 276 +++++++++++++++++++++ arch/mips/include/asm/mach-rtd128x/rtd128x-irq.h | 70 +++++ arch/mips/include/asm/mach-rtd128x/rtd128x-soc.h | 41 +++ arch/mips/include/asm/mach-rtd128x/war.h | 26 + arch/mips/rtd128x/Kconfig | 14 + arch/mips/rtd128x/Makefile | 1 arch/mips/rtd128x/Platform | 8 arch/mips/rtd128x/common/Makefile | 10 arch/mips/rtd128x/common/board.c | 137 ++++++++++ arch/mips/rtd128x/common/irq.c | 137 ++++++++++ arch/mips/rtd128x/common/memory.c | 202 +++++++++++++++ arch/mips/rtd128x/common/platform.c | 103 +++++++ arch/mips/rtd128x/common/printk.c | 33 ++ arch/mips/rtd128x/common/prom.c | 224 +++++++++++++++++ arch/mips/rtd128x/common/sb2.c | 46 +++ arch/mips/rtd128x/common/setup.c | 179 +++++++++++++ arch/mips/rtd128x/common/time.c | 87 ++++++ 20 files changed, 1663 insertions(+) And the diffstat raises the question why the common directory if the entire code ends up there? Also you want to add a arch/mips/include/asm/mach-rtd128x/cpu-feature- overrides.h file for better performance and significantly smaller kernel code. So let's see ... > diff -uNr linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-board.h linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-board.h > --- linux-2.6.36-vanilla/arch/mips/include/asm/mach-rtd128x/rtd128x-board.h 1970-01-01 01:00:00.000000000 +0100 > +++ linux-2.6.36/arch/mips/include/asm/mach-rtd128x/rtd128x-board.h 2010-11-19 18:20:47.000000000 +0100 > @@ -0,0 +1,51 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + */ > + > +#ifndef _RTD128X_BOARD_H_ > +#define _RTD128X_BOARD_H_ > + > +#include > + > +enum rtd128x_board_type { > + RTD128X_BOARD_UNKNOWN = -1, > + RTD128X_BOARD_EM7080 = 0, > +}; You probably want to have RTD128X_BOARD_UNKNOWN = 0 such that an un- initialized variable of type enum rtd128x_board_type will be treated as unknown platform type and not RTD128X_BOARD_EM7080. [...] > +#define RTD128X_SYS_BASE_OFFSET 0x0000 > +#define RTD128X_EHCI_BASE_OFFSET 0x3000 ^^^^ Format with tabs, please. > +/* > + * UART0/UART1 (8250 compatible) > + */ [37 lines of UART definitions deleted.] You may want to use the definitions instead. A simple wrapper macro to do writes into the UART should do the job. > --- linux-2.6.36-vanilla/arch/mips/Kbuild.platforms 2010-10-20 23:23:01.000000000 +0200 > +++ linux-2.6.36/arch/mips/Kbuild.platforms 2010-11-16 01:16:43.000000000 +0100 > @@ -18,6 +18,7 @@ > platforms += pnx833x > platforms += pnx8550 > platforms += powertv > +platforms += rtd128x Read the comment at line 1 of this file! > --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/board.c 1970-01-01 01:00:00.000000000 +0100 > +++ linux-2.6.36/arch/mips/rtd128x/common/board.c 2010-11-19 18:09:57.000000000 +0100 > @@ -0,0 +1,137 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + */ > + > +#include > +#include > +#include Use - or scripts/checkpatch.pl will moan loudly. > +static void rtd128x_common_machine_restart(char *cmd) > +{ > +#ifdef CONFIG_RTD128X_WATCHDOG CONFIG_RTD128X_WATCHDOG is meant to control building the driver in drivers/watchdog? The kernel should still work ok even if it was build without support for a particular driver, then the driver later compiled and be loaded into the previously built kernel. Iow, this #ifdef should go. > + */ > + kill_watchdog(); > +#else > + /* > + * TODO: Find a way to reset the SoC > + */ > + outl(0x0, RTD128X_TIMR_TCWCR); MIPS doesn't have an I/O port address space. That's pure x86 legacy and even there it's deprecated. in, out and their whole clan are meant to be exclusively used to access for I/O port accesses, that is (E)ISA or PCI port addresses. > +#endif > + msleep(5000); Just make this "while (1);" > + > +static enum rtd128x_board_type rtd128x_detect_board(void) > +{ > + return RTD128X_BOARD_EM7080; > + > + /* > + * TODO: Detect different board types > + */ > + > + return RTD128X_BOARD_UNKNOWN; > +} I see dead code :) > +void rtd128x_board_setup(void) > +{ > + switch (rtd128x_detect_board()) { > + case RTD128X_BOARD_EM7080: > + memcpy(&rtd128x_board_info, &rtd128x_em7080_info, > + sizeof(struct rtd128x_board)); You probably want to turn rtd128x_board_info into a pointer which would turn this into a simple pointer assignment: rtd128x_board_info = &rtd128x_em7080_info; And many other places would get a little more elegant also. > + break; > + default: > + printk("Unknown rtd128x board."); I guess as early as this not even early prinkt is working yet so maybe just BUG() would do? > +++ linux-2.6.36/arch/mips/rtd128x/common/memory.c 2010-11-19 18:10:26.000000000 +0100 > @@ -0,0 +1,202 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +//#define DEBUG > + > +enum yamon_memtypes { > + yamon_dontuse, > + yamon_prom, > + yamon_free, > +}; > +static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; Ah, the 3rd copy of YAMON support code. No fucking way. Please extract the code from the other copies to a shared place and use those definitions for the rtd128x. > +#ifdef CONFIG_CPU_BIG_ENDIAN > + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last > + word of physical memory */ > + physical_memsize -= PAGE_SIZE; > +#endif But you most likely don't have SOC-it (a system controller from MIPS). And your Kconfig is setup to hardwire endianess to little endian so this is doubly dead code. > +#ifdef CONFIG_RTD128X_RECLAIM_BOOT_MEMORY Is there a good reason why CONFIG_RTD128X_RECLAIM_BOOT_MEMORY is configurable? This probably should always be abled. > +device_initcall(rtd128x_devinit); > diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/printk.c linux-2.6.36/arch/mips/rtd128x/common/printk.c > --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/printk.c 1970-01-01 01:00:00.000000000 +0100 > +++ linux-2.6.36/arch/mips/rtd128x/common/printk.c 2010-11-19 18:10:44.000000000 +0100 > @@ -0,0 +1,33 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + */ > + > +#include > +#include Again, use . > +#include > + > +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ > +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ This duplicates definitions from . > +void __init prom_putchar(char c) > +{ > + wait_xfered(); > + outl(c, RTD128X_UART_U0RBR_THR_DLL); > + wait_xfered(); > +} Should be ok to only wait only before writing the character into the output register. UART accesses are terribly slow and that way you can at least overlap some of the I/O with other activity. > +void prom_puts(char *s) > +{ > + while (*s != '\0') { > + if (*s == '\n') { > + prom_putchar(*s++); What's wrong with prm_putchar('\n'); > + > +void prom_puthex(unsigned long l) > +{ > + char n; > + int i; Insert blank line here. > + prom_putchar('0'); > + prom_putchar('x'); > +int prom_argc; > +int *_prom_argv, *_prom_envp; Consider making these static and __init. I assume these variables are not being used after kernel initialization? > + > +/* TODO: Verify on linux-mips mailing list that the following two */ > +/* functions are correct */ Ah, comments copied from PowerTV :) > +/* TODO: Copy NMI and EJTAG exception vectors to memory from the */ > +/* BootROM exception vectors. Flush their cache entries. test it. */ > + > +static void __init mips_nmi_setup(void) > +{ > + void *base; > +#if defined(CONFIG_CPU_MIPS32_R1) > + base = cpu_has_veic ? > + (void *)(CAC_BASE + 0xa80) : (void *)(CAC_BASE + 0x380); Won't fly for NMI. NMIs set BEV = 1 which means all your nice vectors will be bypassed and the processor will jump straight to 0xbfc00000. The average firmware will reininitialize the system but some is slightly nicer and allows the OS to regain control. > +#elif defined(CONFIG_CPU_MIPS32_R2) > + base = (void *)0xbfc00000; > +#else > +#error NMI exception handler address not defined > +#endif > +} > --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/sb2.c 1970-01-01 01:00:00.000000000 +0100 > +++ linux-2.6.36/arch/mips/rtd128x/common/sb2.c 2010-11-19 18:11:12.000000000 +0100 > + if (!(inl(RTD128X_SB2_INV_INTSTAT) & 0x2)) > + return IRQ_NONE; > + > + /* ^^^^ remove the trailing space, please. > diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/common/setup.c linux-2.6.36/arch/mips/rtd128x/common/setup.c > --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/setup.c 1970-01-01 01:00:00.000000000 +0100 > +++ linux-2.6.36/arch/mips/rtd128x/common/setup.c 2010-11-19 18:11:21.000000000 +0100 > @@ -0,0 +1,179 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + */ > + > +#include > +#include Do you really need sched.h? > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +extern void rtd128x_board_setup(void); > + > +#define VAL(n) STR(n) > + > +/* > + * Macros for loading addresses and storing registers: > + * LONG_L_ Stringified version of LONG_L for use in asm() statement > + * LONG_S_ Stringified version of LONG_S for use in asm() statement > + * PTR_LA_ Stringified version of PTR_LA for use in asm() statement > + * REG_SIZE Number of 8-bit bytes in a full width register > + */ > +#define LONG_L_ VAL(LONG_L) " " > +#define LONG_S_ VAL(LONG_S) " " > +#define PTR_LA_ VAL(PTR_LA) " " > + > +#ifdef CONFIG_64BIT > +#warning TODO: 64-bit code needs to be verified > +#define REG_SIZE "8" /* In bytes */ > +#endif > + > +#ifdef CONFIG_32BIT > +#define REG_SIZE "4" /* In bytes */ > +#endif > + > +static void register_panic_notifier(void); > +static int panic_handler(struct notifier_block *notifier_block, > + unsigned long event, void *cause_string); > + > +/* > + * Install a panic notifier for platform-specific diagnostics > + */ > +static void register_panic_notifier() > +{ > + static struct notifier_block panic_notifier = { > + .notifier_call = panic_handler, > + .next = NULL, > + .priority = INT_MAX > + }; > + atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier); > +} > + > +static int panic_handler(struct notifier_block *notifier_block, > + unsigned long event, void *cause_string) > +{ > + struct pt_regs my_regs; > + > + /* Save all of the registers */ > + { > + unsigned long at, v0, v1; /* Must be on the stack */ > + > + /* Start by saving $at and v0 on the stack. We use $at > + * ourselves, but it looks like the compiler may use v0 or v1 > + * to load the address of the pt_regs structure. We'll come > + * back later to store the registers in the pt_regs > + * structure. */ > + __asm__ __volatile__(".set noat\n" > + LONG_S_ "$at, %[at]\n" Copied from PowerTV :) I somehow doubt saving registers at this late stage provides much useful information. > + pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " > + "zzzz... \n"); This is a panic so pr_emerg() would see more apropriate to express the urgency of this nap :-) > --- linux-2.6.36-vanilla/arch/mips/rtd128x/common/time.c 1970-01-01 01:00:00.000000000 +0100 > +++ linux-2.6.36/arch/mips/rtd128x/common/time.c 2010-11-19 18:11:27.000000000 +0100 > @@ -0,0 +1,87 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include Eh... You said you have a 24K. There is no way you then could use any of the definitions in this file. > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +extern void platform_setup(void); Declaration but the symbol platform_setup() is not being used anywhere. And another file also declared platform_setup() without using it ... > + > +unsigned long cpu_khz; Unused junk. > diff -uNr linux-2.6.36-vanilla/arch/mips/rtd128x/Kconfig linux-2.6.36/arch/mips/rtd128x/Kconfig > --- linux-2.6.36-vanilla/arch/mips/rtd128x/Kconfig 1970-01-01 01:00:00.000000000 +0100 > +++ linux-2.6.36/arch/mips/rtd128x/Kconfig 2010-11-19 18:09:41.000000000 +0100 > @@ -0,0 +1,14 @@ > +config RTD128X_RECLAIM_BOOT_MEMORY > + bool "reclaim memory from bootloader" > + > +# > +# FIXME: do we really need this? > +# > +#config RTD128X_EXTERNAL_TIMER > +# bool "use external timer interrupt" You certainly don't want to expose such stuff to the Kconfig user who most likely has no clue whatsoever what this option means. Especially not without a help text but that's besides the point. The option should simply not exist. > --- linux-2.6.36-vanilla/arch/mips/rtd128x/Platform 1970-01-01 01:00:00.000000000 +0100 > +++ linux-2.6.36/arch/mips/rtd128x/Platform 2010-11-16 01:16:43.000000000 +0100 > @@ -0,0 +1,8 @@ > +# > +# Realtek Galaxy SoC boards > +# > + > +platform-${CONFIG_RTD128X} += rtd128x/ > +cflags-${CONFIG_RTD128X} += -I$(srctree)/arch/mips/include/asm/mach-rtd128x/ > +load-${CONFIG_RTD128X} := 0xffffffff80100000 > +all-$(CONFIG_RTD128X) := $(COMPRESSION_FNAME).bin Ralf From lacombar@gmail.com Mon Nov 22 04:04:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 04:04:59 +0100 (CET) Received: from mail-iw0-f177.google.com ([209.85.214.177]:58140 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491952Ab0KVDE4 (ORCPT ); Mon, 22 Nov 2010 04:04:56 +0100 Received: by iwn8 with SMTP id 8so7701243iwn.36 for ; Sun, 21 Nov 2010 19:04:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:cc:content-type; bh=xzyUEZce49BGW97sOMfKA4y900SSRClU+oZqqsRZobo=; b=vWTihsQelSYfHaY8Ezr0z7OM10y0r9az0d9QpMfhsCVgpxmCBNaULWBOZPJtbbNeN7 pv46X97NIl1tLaQtIiBM/WymZQAT1Aoxv/kZI5WE5mvc+xL9WzhlJ8xOy3vYdTO5n8Fh naVZhfgcnQtJ+h/8eEviLfrkkd6f4DsWTR2KI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; b=kKTzJE4WKZbBNDtt60VdzicEnH2pabi4StoBM/npshgIcYeB3vYMo+Z/TQVs4KY1fo NZv2NqIlX42PhA8iKMSx1JiiL91o2jhB6jzNcvbskGSoZlHA+1ABYYYKGqo54BgwXii8 +Rg4tlgMk7CbDcByuj8o4VxZhDKENxSWtQOR4= MIME-Version: 1.0 Received: by 10.231.32.129 with SMTP id c1mr6277040ibd.60.1290395093787; Sun, 21 Nov 2010 19:04:53 -0800 (PST) Received: by 10.42.166.129 with HTTP; Sun, 21 Nov 2010 19:04:53 -0800 (PST) Date: Sun, 21 Nov 2010 22:04:53 -0500 Message-ID: Subject: Build failure triggered by recordmcount From: Arnaud Lacombe To: John Reiser , Steven Rostedt Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28441 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lacombar@gmail.com Precedence: bulk X-list: linux-mips Hi, The build of an `allyesconfig' configuration from v2.6.37-rc3 is failing relatively soon on the following: [...] LD init/mounts.o /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld: init/do_mounts.o: bad reloc symbol index (0x20200 >= 0x84) for offset 0x0 in section `__mcount_loc' /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld -v GNU ld version 2.17 The toolchain originated from OpenWRT Kamikaze and is available on their FTP[0]. I've not been able to locate the exact point of failure. - Arnaud [0]: http://downloads.openwrt.org/kamikaze/8.09.2/ar71xx/ From ralf@linux-mips.org Mon Nov 22 04:41:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 04:41:48 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47949 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490962Ab0KVDlp (ORCPT ); Mon, 22 Nov 2010 04:41:45 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oAM3fgOj026642; Mon, 22 Nov 2010 03:41:42 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oAM3ff08026640; Mon, 22 Nov 2010 03:41:41 GMT Date: Mon, 22 Nov 2010 03:41:41 +0000 From: Ralf Baechle To: Maksim Rayskiy , "Kevin D. Kissell" Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: ASID conflict after CPU hotplug Message-ID: <20101122034141.GA13138@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28442 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 17, 2010 at 10:49:09AM -0800, Maksim Rayskiy wrote: > This is a repost of my original message which somehow did not reach > the mailing list (filtered out?). Yes indeed. In particular the previous posting was HTML which the list robot is configured to exterminate. > I am running SMP Linux 2.6.37-rc1 on BMIPS5000 (single core dual > thread) and observe some abnormalities when doing system > suspend/resume which I narrowed down to cpu hotplugging. The suspend > brings the second thread processor down and then restarts it, after > which I see memory corruption in userspace. I started digging and > found out that problem occurs because while doing execve() the child > process is getting the same ASID as the parent, which obviously > corrupts parent's address space. > > Further digging showed that: > activate_mm() calls get_new_mmu_context() to get a new ASID, but at > this time ASID field in entryHi is 1, and asid_cache(cpu) is 0x100 (it > was just reset to ASID_FIRST_VERSION when the secondary TP was > booting). > So, get_new_mmu_context() increments the asid_cache(cpu) value to > 0x101, and thus puts 0x01 into entryHi. The result - ASID field does > not get changed as it was supposed to. > > My solution was very simple - do not reset asid_cache(cpu) on TP warm > restart. But I would welcome any comments because my understanding of > the code is somewhat fuzzy. Unfortunately I haven't yet found a BMIPS board or manual in my mailbox so I can't really give a definitate answer. But let me describe how the MIPS34K handles it. The 34K supports two TLB modes, shared and split TLB. The VSMP kernel uses the TLB in split mode in which half of the TLB entries is available to each of the two threads aka VPEs. So with a 64 entry TLB that's 32 entries per VPE then. Each VPE (or rather TC but see further down) has it's own c0_entryhi register, thus it's own ASID. So no ASID collisions possible, ever. This is the same as on a conventional SMP system where TLB and ASID number space are also per CPU. The SMTC kernel model (usually) uses the shared model, that is all the 64 entries are now available to all threads and the ASID space is shared. This means allocation of the same ASID to multiple TCs needs to be avoided. It seems BMIPS falls into the latter class? Need to think a little about potencial consequences of your suggested patch. It seems ok. Kevin, what do you think? Ralf From wuzhangjin@gmail.com Mon Nov 22 12:42:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 12:42:12 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:48751 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491958Ab0KVLmJ convert rfc822-to-8bit (ORCPT ); Mon, 22 Nov 2010 12:42:09 +0100 Received: by wyf22 with SMTP id 22so7063520wyf.36 for ; Mon, 22 Nov 2010 03:42:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=BfOXwt7hHTThjkDxr8aOOQ/lIpYGmZbqDsQInOHIYL8=; b=dx0mRfc3/ckQLOUrERBh0sYfkjT0SX6PdhLEcxCQ3yRGSv+VC+sGkgtFbNSIhndoPk oFTXvx/kEmhB5Jj/vWXu/AjxqNt6x0OSo1nieEGRtamCXYLEgm3tTroSH6yn6x22yD/R zAnbTZUZ9u0B7Rk+bWgGrjrb/a2z8ul+pW5+g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=i9uGoP+D4WmteRP8BdkAO+QQbZHrOHwV1u5XS2VJSvdcDXqDS2Yx7rhOVgTC0+j6I0 7IROGSvpYjMEjITp+11LSBsvgcvGHlil+KISRh2KDDrSgltiFQF+j/PP8M8IYukeyT1b ugZ96keJL9ewYx4GzD8GAnbA6LKz1mKcQhyoM= MIME-Version: 1.0 Received: by 10.216.142.131 with SMTP id i3mr3956048wej.5.1290426122883; Mon, 22 Nov 2010 03:42:02 -0800 (PST) Received: by 10.216.131.88 with HTTP; Mon, 22 Nov 2010 03:42:02 -0800 (PST) In-Reply-To: References: Date: Mon, 22 Nov 2010 19:42:02 +0800 Message-ID: Subject: Re: Build failure triggered by recordmcount From: wu zhangjin To: Arnaud Lacombe Cc: John Reiser , Steven Rostedt , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28443 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, Arnaud This only happen at 32bit + big endian, so, perhaps, the symbol reltype of bitendian 32bit differs from little endian 32bit, I will check it later, thanks! Regards, Wu Zhangjin On Mon, Nov 22, 2010 at 11:04 AM, Arnaud Lacombe wrote: > Hi, > > The build of an `allyesconfig' configuration from v2.6.37-rc3 is > failing relatively soon on the following: > > [...] >  LD      init/mounts.o > /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld: > init/do_mounts.o: bad reloc symbol index (0x20200 >= 0x84) for offset > 0x0 in section `__mcount_loc' > > /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld > -v > GNU ld version 2.17 > > The toolchain originated from OpenWRT Kamikaze and is available on their FTP[0]. > > I've not been able to locate the exact point of failure. > >  - Arnaud > > [0]: http://downloads.openwrt.org/kamikaze/8.09.2/ar71xx/ > > From rmh.aybabtu@gmail.com Mon Nov 22 13:44:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 13:44:50 +0100 (CET) Received: from mail-gw0-f49.google.com ([74.125.83.49]:51383 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491996Ab0KVMor (ORCPT ); Mon, 22 Nov 2010 13:44:47 +0100 Received: by gwj18 with SMTP id 18so1345763gwj.36 for ; Mon, 22 Nov 2010 04:44:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type; bh=bLfoNQXYAQ2t6lO0ial1vV7vRKv4D4nfs2zuJPY8t7o=; b=pG9lm+rqr/LFKI6ORt72gcIUZALq7Cg5N9noP+lYIRd2V86kgBADjo0J13HNbGfEzf qTWINwK8MAkT255hisgPU28+0ckurP51rkkZQBNdAwzmm6EfkVI3J65GZGXKNB6cWoqu TQ52ZxTkVj4Dk+24lBTOrNnqVJvRtvMmVQG5Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; b=iCAtjE7Xthx0eWUj9iLMI+K2m4YhR5HeiMBIZ9ae3Ic3qMqeQVeKLowUMAvW5jaXSd C8oOFQrlGyJ/5W93sur6iZo8MsMYEowTcNRRVRu7wG6/LajlVzbHOwXveWAajjtLl8kI QoLvjfv8QjE8WLZ1YH+LDTiO8gC6ZcXU9XeOo= MIME-Version: 1.0 Received: by 10.231.36.197 with SMTP id u5mr6830328ibd.110.1290429880035; Mon, 22 Nov 2010 04:44:40 -0800 (PST) Received: by 10.231.170.70 with HTTP; Mon, 22 Nov 2010 04:44:39 -0800 (PST) In-Reply-To: <4CE1C96F.1030909@caviumnetworks.com> References: <20101109154055.GD10799@linux-mips.org> <1289486855.14828.0@thorin> <1289865028.9277.0@thorin> <4CE1C96F.1030909@caviumnetworks.com> Date: Mon, 22 Nov 2010 13:44:39 +0100 X-Google-Sender-Auth: Vl0YHPd2b8wSUOvN0015_ZD1s3k Message-ID: Subject: Re: [PATCH] Enable AT_PLATFORM for Loongson 2F CPU From: Robert Millan To: David Daney Cc: Ralf Baechle , wu zhangjin , Aurelien Jarno , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28444 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmh@gnu.org Precedence: bulk X-list: linux-mips > Acked-by: David Daney Any news about this one? Is it good already? -- Robert Millan From wuzhangjin@gmail.com Mon Nov 22 15:57:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 15:58:01 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:51085 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492018Ab0KVO5x convert rfc822-to-8bit (ORCPT ); Mon, 22 Nov 2010 15:57:53 +0100 Received: by wwb31 with SMTP id 31so238375wwb.24 for ; Mon, 22 Nov 2010 06:57:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=mOwD1iujYtIouRxIuTjztCbUzd7dDwEpzM3An4DJKmA=; b=QhvHCs5OKJ3audrJkfueA6V+uXdE9DKuIIP3Mw/BFMBXzEoptTNKImpwaHTxlscdrQ DPh35dv1NVxyM5mQxgSTPf106PxxGek0KkHknnYWg912z4+UPy05eoC0CwMaQdxsHbUq Pif6J5zVAZnQr9T7aao/xFQO8F1UYjZEn/pFQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=t5b+lJ6zYvkvCsoQ0H7nIr8c9j+Jlbf96tSDyJvR3kyDEJHOi3ab/loBCwOPq0NN3i p4PpIR235Y1AIUE1MDdya3TKUcTDMJeP6IGPhGjL42U1lHNkrxzQgCAuItlBtXyJxb7i q6ReW/sjIfkWbo3E7Bm1nW2grNStwQ64pCV50= MIME-Version: 1.0 Received: by 10.216.157.6 with SMTP id n6mr5230642wek.35.1290437860646; Mon, 22 Nov 2010 06:57:40 -0800 (PST) Received: by 10.216.131.88 with HTTP; Mon, 22 Nov 2010 06:57:40 -0800 (PST) In-Reply-To: References: Date: Mon, 22 Nov 2010 22:57:40 +0800 Message-ID: Subject: Re: Build failure triggered by recordmcount From: wu zhangjin To: Arnaud Lacombe Cc: John Reiser , Steven Rostedt , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28445 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, The cause should be the endian problem, I guess you were cross-compiling it? If we compile the kernel for (32bit + big endian) target on an x86 machine(little endian) or reversely, then, it will fail. Since the scripts/recordmcount is compiled with the local toolchain, the data structs will be explained according to the local configuration(endian...). So, we may need to custom our own elf.h for recordmcount according to the target type(endian here) of the kernel image: At first, pass the target information to recordmcount(only a demo here, we may need to clear it carefully): diff --git a/scripts/Makefile b/scripts/Makefile index 2e08810..151fe3e 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -11,6 +11,9 @@ hostprogs-$(CONFIG_KALLSYMS) += kallsyms hostprogs-$(CONFIG_LOGO) += pnmtologo hostprogs-$(CONFIG_VT) += conmakehash hostprogs-$(CONFIG_IKCONFIG) += bin2c +HOSTCFLAGS_recordmcount.o += -DARCH=__$(ARCH)__ \ + -DBIT=__$(if $(CONFIG_64BIT),64,32)__ \ + -DENDIAN=__$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)__ hostprogs-$(BUILD_C_RECORDMCOUNT) += recordmcount always := $(hostprogs-y) $(hostprogs-m) Then, custom the related data struct(Elf...) for the specific target(Perhaps we can steal some code from glibc...) and as a result, no need to check the targets at run-time... just like what we have done for the Perl version of recordmcount, but for the C version of recordmcount, we only need to pass the information for one time. Regard, Wu Zhangjin On Mon, Nov 22, 2010 at 7:42 PM, wu zhangjin wrote: > Hi, Arnaud > > This only happen at 32bit + big endian, so, perhaps, the symbol > reltype of bitendian 32bit differs from little endian 32bit, I will > check it later, thanks! > > Regards, > Wu Zhangjin > > On Mon, Nov 22, 2010 at 11:04 AM, Arnaud Lacombe wrote: >> Hi, >> >> The build of an `allyesconfig' configuration from v2.6.37-rc3 is >> failing relatively soon on the following: >> >> [...] >>  LD      init/mounts.o >> /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld: >> init/do_mounts.o: bad reloc symbol index (0x20200 >= 0x84) for offset >> 0x0 in section `__mcount_loc' >> >> /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld >> -v >> GNU ld version 2.17 >> >> The toolchain originated from OpenWRT Kamikaze and is available on their FTP[0]. >> >> I've not been able to locate the exact point of failure. >> >>  - Arnaud >> >> [0]: http://downloads.openwrt.org/kamikaze/8.09.2/ar71xx/ >> >> > From wuzhangjin@gmail.com Mon Nov 22 16:00:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 16:00:23 +0100 (CET) Received: from mail-ww0-f43.google.com ([74.125.82.43]:42590 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492018Ab0KVPAQ convert rfc822-to-8bit (ORCPT ); Mon, 22 Nov 2010 16:00:16 +0100 Received: by wwb31 with SMTP id 31so240927wwb.24 for ; Mon, 22 Nov 2010 07:00:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=n68ec5zlJ8wkw+C2EAx3Lo7tsuo1Rw6AhyfVL0OwHJg=; b=fRtfoe6XG3gM69oeWeDm3ezZnfQGnWE6kGXN8x4otjr6+0YZ3rz9xQBJVQssVqJyE7 FwMssrO09dmRyClsT99QVHqFIrhW80SnfWuauMtlNnt5BYzh3l6gN037nG9BckLS3X9b TlYg2CRK03Ybx6hOxteTGgaEmZfcfXika/8bI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=LEsi2Obu/dmUxql7xV9UPdHk0irwQdj/8GnuYh+yyQS1AeUiDeht1dFS5bdHfca+MF fQz8AU5x5dOG035QprdxU4laMRo9bsCvIVoOYcu1S3txRGQ8fpBriJZYof3Jnlx5fzQ4 EiR5cfRt1LpZ1J+XCmlkHpaqH6t6kRV6FAJEU= MIME-Version: 1.0 Received: by 10.216.173.7 with SMTP id u7mr4170125wel.50.1290438006535; Mon, 22 Nov 2010 07:00:06 -0800 (PST) Received: by 10.216.131.88 with HTTP; Mon, 22 Nov 2010 07:00:06 -0800 (PST) In-Reply-To: References: Date: Mon, 22 Nov 2010 23:00:06 +0800 Message-ID: Subject: Re: Build failure triggered by recordmcount From: wu zhangjin To: Arnaud Lacombe Cc: Steven Rostedt , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28446 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips (Change the wrong Email address jreiseer@bitwagon.com to jreiser@BitWagon.com) On Mon, Nov 22, 2010 at 10:57 PM, wu zhangjin wrote: > Hi, > > The cause should be the endian problem, I guess you were cross-compiling it? > > If we compile the kernel for (32bit + big endian) target on an x86 > machine(little endian) or reversely, then, it will fail. > > Since the scripts/recordmcount is compiled with the local toolchain, > the data structs will be explained according to the local > configuration(endian...). > > So, we may need to custom our own elf.h for recordmcount according to > the target type(endian here) of the kernel image: > > At first, pass the target information to recordmcount(only a demo > here, we may need to clear it carefully): > > diff --git a/scripts/Makefile b/scripts/Makefile > index 2e08810..151fe3e 100644 > --- a/scripts/Makefile > +++ b/scripts/Makefile > @@ -11,6 +11,9 @@ hostprogs-$(CONFIG_KALLSYMS)     += kallsyms >  hostprogs-$(CONFIG_LOGO)         += pnmtologo >  hostprogs-$(CONFIG_VT)           += conmakehash >  hostprogs-$(CONFIG_IKCONFIG)     += bin2c > +HOSTCFLAGS_recordmcount.o        += -DARCH=__$(ARCH)__ \ > +       -DBIT=__$(if $(CONFIG_64BIT),64,32)__           \ > +       -DENDIAN=__$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)__ >  hostprogs-$(BUILD_C_RECORDMCOUNT) += recordmcount > >  always         := $(hostprogs-y) $(hostprogs-m) > > Then, custom the related data struct(Elf...) for the specific > target(Perhaps we can steal some code from glibc...) and as a result, > no need to check the targets at run-time... just like what we have > done for the Perl version of recordmcount, but for the C version of > recordmcount, we only need to pass the information for one time. > > Regard, > Wu Zhangjin > > On Mon, Nov 22, 2010 at 7:42 PM, wu zhangjin wrote: >> Hi, Arnaud >> >> This only happen at 32bit + big endian, so, perhaps, the symbol >> reltype of bitendian 32bit differs from little endian 32bit, I will >> check it later, thanks! >> >> Regards, >> Wu Zhangjin >> >> On Mon, Nov 22, 2010 at 11:04 AM, Arnaud Lacombe wrote: >>> Hi, >>> >>> The build of an `allyesconfig' configuration from v2.6.37-rc3 is >>> failing relatively soon on the following: >>> >>> [...] >>>  LD      init/mounts.o >>> /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld: >>> init/do_mounts.o: bad reloc symbol index (0x20200 >= 0x84) for offset >>> 0x0 in section `__mcount_loc' >>> >>> /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld >>> -v >>> GNU ld version 2.17 >>> >>> The toolchain originated from OpenWRT Kamikaze and is available on their FTP[0]. >>> >>> I've not been able to locate the exact point of failure. >>> >>>  - Arnaud >>> >>> [0]: http://downloads.openwrt.org/kamikaze/8.09.2/ar71xx/ >>> >>> >> > From wuzhangjin@gmail.com Mon Nov 22 16:00:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 16:00:48 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:48646 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492023Ab0KVPAm convert rfc822-to-8bit (ORCPT ); Mon, 22 Nov 2010 16:00:42 +0100 Received: by wyf22 with SMTP id 22so7270660wyf.36 for ; Mon, 22 Nov 2010 07:00:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=n68ec5zlJ8wkw+C2EAx3Lo7tsuo1Rw6AhyfVL0OwHJg=; b=Q/x/EPZ9RQeLxXxzAE5rxkgf+sZiVJPtz3c/HXoEWJBY4uFTDi37hI3jCwAgb1TjgC O3awsqjk+6+7v8LUCuyUlPFsajaZka6yNqZGWq9uYeZwZ2TIGKRS0VCvx/gRPjJ5wVh0 t+jA5sep0t+aZvER9114xw8PhRaQUweZaPBus= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=gHS4XfaBZYPBu34XnvNsmBmzi57Q4fdq5cDhqt92M3hORnpTunb57KiyWpNfBBTUyl HdGyA0aFUNX3wfDbsmOfwV3dBor3effa39OVQ6/Z1EaR24gpL/B3b+6d+8CRehjIv/+q Khyn4VliuM4uSIr2nNRqduMY8j8xOdHqNsKGU= MIME-Version: 1.0 Received: by 10.216.157.6 with SMTP id n6mr5234393wek.35.1290438031553; Mon, 22 Nov 2010 07:00:31 -0800 (PST) Received: by 10.216.131.88 with HTTP; Mon, 22 Nov 2010 07:00:31 -0800 (PST) In-Reply-To: References: Date: Mon, 22 Nov 2010 23:00:31 +0800 Message-ID: Subject: Re: Build failure triggered by recordmcount From: wu zhangjin To: Arnaud Lacombe Cc: John Reiser , Steven Rostedt , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28447 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips (Change the wrong Email address jreiseer@bitwagon.com to jreiser@BitWagon.com) On Mon, Nov 22, 2010 at 10:57 PM, wu zhangjin wrote: > Hi, > > The cause should be the endian problem, I guess you were cross-compiling it? > > If we compile the kernel for (32bit + big endian) target on an x86 > machine(little endian) or reversely, then, it will fail. > > Since the scripts/recordmcount is compiled with the local toolchain, > the data structs will be explained according to the local > configuration(endian...). > > So, we may need to custom our own elf.h for recordmcount according to > the target type(endian here) of the kernel image: > > At first, pass the target information to recordmcount(only a demo > here, we may need to clear it carefully): > > diff --git a/scripts/Makefile b/scripts/Makefile > index 2e08810..151fe3e 100644 > --- a/scripts/Makefile > +++ b/scripts/Makefile > @@ -11,6 +11,9 @@ hostprogs-$(CONFIG_KALLSYMS)     += kallsyms >  hostprogs-$(CONFIG_LOGO)         += pnmtologo >  hostprogs-$(CONFIG_VT)           += conmakehash >  hostprogs-$(CONFIG_IKCONFIG)     += bin2c > +HOSTCFLAGS_recordmcount.o        += -DARCH=__$(ARCH)__ \ > +       -DBIT=__$(if $(CONFIG_64BIT),64,32)__           \ > +       -DENDIAN=__$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)__ >  hostprogs-$(BUILD_C_RECORDMCOUNT) += recordmcount > >  always         := $(hostprogs-y) $(hostprogs-m) > > Then, custom the related data struct(Elf...) for the specific > target(Perhaps we can steal some code from glibc...) and as a result, > no need to check the targets at run-time... just like what we have > done for the Perl version of recordmcount, but for the C version of > recordmcount, we only need to pass the information for one time. > > Regard, > Wu Zhangjin > > On Mon, Nov 22, 2010 at 7:42 PM, wu zhangjin wrote: >> Hi, Arnaud >> >> This only happen at 32bit + big endian, so, perhaps, the symbol >> reltype of bitendian 32bit differs from little endian 32bit, I will >> check it later, thanks! >> >> Regards, >> Wu Zhangjin >> >> On Mon, Nov 22, 2010 at 11:04 AM, Arnaud Lacombe wrote: >>> Hi, >>> >>> The build of an `allyesconfig' configuration from v2.6.37-rc3 is >>> failing relatively soon on the following: >>> >>> [...] >>>  LD      init/mounts.o >>> /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld: >>> init/do_mounts.o: bad reloc symbol index (0x20200 >= 0x84) for offset >>> 0x0 in section `__mcount_loc' >>> >>> /OpenWrt-SDK-ar71xx-for-Linux-i686/staging_dir/toolchain-mips_gcc4.1.2/bin/mips-linux-ld >>> -v >>> GNU ld version 2.17 >>> >>> The toolchain originated from OpenWRT Kamikaze and is available on their FTP[0]. >>> >>> I've not been able to locate the exact point of failure. >>> >>>  - Arnaud >>> >>> [0]: http://downloads.openwrt.org/kamikaze/8.09.2/ar71xx/ >>> >>> >> > From Andrei.Ardelean@idt.com Mon Nov 22 17:38:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 17:38:14 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:56179 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491981Ab0KVQiH convert rfc822-to-8bit (ORCPT ); Mon, 22 Nov 2010 17:38:07 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oAMGbuPM031895; Mon, 22 Nov 2010 08:37:58 -0800 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oAMGbtLd029838; Mon, 22 Nov 2010 08:37:56 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oAMGbs213378; Mon, 22 Nov 2010 08:37:54 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: The new "real" console doesn't display printk() messages like "early" console! Date: Mon, 22 Nov 2010 08:37:53 -0800 Message-ID: In-Reply-To: <4CE6A103.8030009@mvista.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: The new "real" console doesn't display printk() messages like "early" console! Thread-Index: AcuIBEWDEyxDvHP6TbaTKBiFLvofTACXasVA References: <4CE57C92.6030705@mvista.com> <4CE6A103.8030009@mvista.com> From: "Ardelean, Andrei" To: "Sergei Shtylyov" Cc: "Ricardo Mendoza" , X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28448 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi Sergei, - I will clean up the things you highlighted in the code, they come from octeon code. - Regarding PORT_GD, I added it in driver/serial/8250.c like octeon model: [PORT_OCTEON] = { .name = "OCTEON", .fifo_size = 64, .tx_loadsz = 64, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, .flags = UART_CAP_FIFO, }, [PORT_GD] = { .name = "GD", .fifo_size = 16, .tx_loadsz = 16, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, .flags = UART_CAP_FIFO, }, Thanks, Andrei -----Original Message----- From: Sergei Shtylyov [mailto:sshtylyov@mvista.com] Sent: Friday, November 19, 2010 11:09 AM To: Ardelean, Andrei Cc: Ricardo Mendoza; linux-mips@linux-mips.org Subject: Re: The new "real" console doesn't display printk() messages like "early" console! Ardelean, Andrei wrote: > Hi Ricardo, > I implemented serial platform driver taking as model serial.c from > cavium-octeon. I think you should really have used something simpler as an example. > Here is my code: > /* > * This file is subject to the terms and conditions of the GNU General > Public > * License. See the file "COPYING" in the main directory of this > archive > * for more details. > * > * Copyright (C) 2004-2007 Cavium Networks > */ > > #include > #include > #include > #include > #include > #include > #include > #include > #include > #include > > > #ifdef CONFIG_GDB_CONSOLE This is never defined for MIPS. And there shouldn't be such dependencies. > #define DEBUG_UART 0 > #else > #define DEBUG_UART 1 > #endif > > unsigned int gd_serial_in(struct uart_port *up, int offset) > { > int rv = inl((unsigned int)(up->membase + (offset << 2))); Should be an empty line here. > if (offset == UART_IIR && (rv & 0xf) == 7) { Are you sure this Octeon specific quirk also allpies to your UART? > /* Busy interrupt, read the USR (39) and try again. */ > inl((unsigned int)(up->membase + (39 << 2))); > rv = inl((unsigned int)(up->membase + (offset << 2))); > } > return rv; > } > > void gd_serial_out(struct uart_port *up, int offset, int value) > { > outl( value & 0xff, (unsigned int)(up->membase + (offset << No spaces allowed after (. > 2))); > } > > /* > * Allocated in .bss, so it is all zeroed. > */ > #define GD_MAX_UARTS 1 Then how DEBUG_UART can be 1? > static struct plat_serial8250_port gd_uart8250_data[GD_MAX_UARTS + 1]; > static struct platform_device gd_uart8250_device = { > .name = "serial8250", > .id = PLAT8250_DEV_PLATFORM, > .dev = { > .platform_data = gd_uart8250_data, Where is 'gd_uart8250_data'? > }, > }; > static void __init gd_uart_set_common(struct plat_serial8250_port *p) > { > p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; > p->type = PORT_GD; What is PORT_GD? > p->iotype = UPIO_MEM; Judging from your code, it should be UPIO_MEM32. > p->regshift = 2; /* I/O addresses are every 4 bytes */ > p->uartclk = UART_CLK; > p->serial_in = gd_serial_in; > p->serial_out = gd_serial_out; > } > > static int __init gd_serial_init(void) > { > int enable_uart0; > struct plat_serial8250_port *p; > > enable_uart0 = 1; What's the point in existence of this variable? > p = gd_uart8250_data; > if (enable_uart0) { > /* Add a ttyS device for hardware uart 0 */ > gd_uart_set_common(p); > p->membase = (void *) offMCU_UART_THR_OR_RBR_OR_DLL; > p->mapbase = offMCU_UART_THR_OR_RBR_OR_DLL; Are your UART registers identity mapped to virtual address space? You are not obliged to pass 'membase', unless you have pre-existing mapping but in this case you also need to pass UPF_IOREMAP in 'flags'. > p->irq = MIPSCPU_INT_UART; > p++; > } > return platform_device_register(&gd_uart8250_device); > } > > device_initcall(gd_serial_init); > ------------------------------------------------------------------------ > ----------------------- > > Thanks, > Andrei WBR, Sergei From maksim.rayskiy@gmail.com Mon Nov 22 19:38:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 19:39:04 +0100 (CET) Received: from mail-gy0-f177.google.com ([209.85.160.177]:61698 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492049Ab0KVSi5 convert rfc822-to-8bit (ORCPT ); Mon, 22 Nov 2010 19:38:57 +0100 Received: by gyg8 with SMTP id 8so236245gyg.36 for ; Mon, 22 Nov 2010 10:38:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Dg4wyOokvUfrWP3M1Y8b88c+WZO+V1NhrP0nmBdvRlE=; b=UKwS97ILb0C1wfkFnsBlWtDCUVaz2R2vm9FyR3kh3q1GB/hRgiYdvftn+arXZTsG8m KEcKJyzYwL72/HJ5ZaRR7N0MxpLt42mgz5aJUQKCC53u/8hNAs+6jOJh52VE4bageCy+ 8tt0C0NkYDic1nModiVXqRcK6YOoPQNPNWfjo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=wC0QCH+91AIDO3pAXg51Sv87dQVeqE7X2KlI6bC3fbXFL2FIasrfetLzeP4uoyADCW nYdjq2SGe40EzjVmyRT3L2Bohi+TTDvZfP7H6sofUcrXvVfLDeb+7pzJfcLv9cO+FYhZ MsITSoJnkh4NUPa7E5PEDnV4g400kuwj8wGGk= MIME-Version: 1.0 Received: by 10.100.255.8 with SMTP id c8mr4338063ani.154.1290451130484; Mon, 22 Nov 2010 10:38:50 -0800 (PST) Received: by 10.100.209.10 with HTTP; Mon, 22 Nov 2010 10:38:50 -0800 (PST) In-Reply-To: <20101122034141.GA13138@linux-mips.org> References: <20101122034141.GA13138@linux-mips.org> Date: Mon, 22 Nov 2010 10:38:50 -0800 Message-ID: Subject: Re: [PATCH] MIPS: ASID conflict after CPU hotplug From: Maksim Rayskiy To: Ralf Baechle Cc: "Kevin D. Kissell" , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28449 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maksim.rayskiy@gmail.com Precedence: bulk X-list: linux-mips On Sun, Nov 21, 2010 at 7:41 PM, Ralf Baechle wrote: > Unfortunately I haven't yet found a BMIPS board or manual in my mailbox > so I can't really give a definitate answer.  But let me describe how > the MIPS34K handles it. > > The 34K supports two TLB modes, shared and split TLB.  The VSMP kernel > uses the TLB in split mode in which half of the TLB entries is available > to each of the two threads aka VPEs.  So with a 64 entry TLB that's 32 > entries per VPE then.  Each VPE (or rather TC but see further down) has > it's own c0_entryhi register, thus it's own ASID.  So no ASID collisions > possible, ever.  This is the same as on a conventional SMP system where > TLB and ASID number space are also per CPU. > > The SMTC kernel model (usually) uses the shared model, that is all the 64 > entries are now available to all threads and the ASID space is shared. > This means allocation of the same ASID to multiple TCs needs to be avoided. > > It seems BMIPS falls into the latter class? > No, each thread has a separate TLB and all TLB-related registers are also per thread. The conflict I have found was the same ASID for two different processes on the second TP. I still do not understand all the details, but what I saw was after the second TP is brought back online init process runs on (migrates to ?) it with entryHi=1. If it tries to spawn another process, the child gets the same ASID, because current asid_cache value is 0 (well it is actually 0x100, but only lower 8 bits matter). > Need to think a little about potencial consequences of your suggested > patch.  It seems ok.  Kevin, what do you think? > >  Ralf > Thanks, Maksim. From lacombar@gmail.com Mon Nov 22 19:47:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 19:47:08 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:62755 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492049Ab0KVSrC convert rfc822-to-8bit (ORCPT ); Mon, 22 Nov 2010 19:47:02 +0100 Received: by pwj8 with SMTP id 8so1828497pwj.36 for ; Mon, 22 Nov 2010 10:46:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=vpyPoD86GmieFhbJ5NE8lrs8DREBvIGxXxNh5DY4D9c=; b=N/v2fE6cWZqxCYBxeR3/xM1kkKzFxxIeD6cAE4yk7SwV2eqlmwEfppUghM4A6K18ZW RZIg4QJIgtBKnTM0zOlrxguuButeHi8i9VQ8QWgxCFKkZBr6ZOeKRrZjKeUoYB/+beWh rxPTWk0ROHqGSlCy4NvKgbYjxdiEVOH1cRhXI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=AmYTM8vGDKipSk1X/4kF1CPwRMwW+y/Oq1aoEJxeiTe7yWHMMQvGkpIfoCF4IQ0Dw1 tVCYF6SmkF0fDTVa86Vofg75Eu96gG1QfP0D5oTKYsJrxgfG6hOy5j58JXMT8KBeU3r/ CpoitqzA1a8QXYRDrj9SIV807jaDbOZqhfsZs= MIME-Version: 1.0 Received: by 10.229.184.8 with SMTP id ci8mr5392603qcb.72.1290451615082; Mon, 22 Nov 2010 10:46:55 -0800 (PST) Received: by 10.229.182.3 with HTTP; Mon, 22 Nov 2010 10:46:54 -0800 (PST) In-Reply-To: References: Date: Mon, 22 Nov 2010 13:46:54 -0500 Message-ID: Subject: Re: Build failure triggered by recordmcount From: Arnaud Lacombe To: wu zhangjin Cc: John Reiser , Steven Rostedt , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28450 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lacombar@gmail.com Precedence: bulk X-list: linux-mips Hi, On Mon, Nov 22, 2010 at 9:57 AM, wu zhangjin wrote: > Hi, > > The cause should be the endian problem, I guess you were cross-compiling it? > yes. > If we compile the kernel for (32bit + big endian) target on an x86 > machine(little endian) or reversely, then, it will fail. > > Since the scripts/recordmcount is compiled with the local toolchain, > the data structs will be explained according to the local > configuration(endian...). > will it ? recordmcount.c does not switch endianness based on the host, but based on format of the object file, see the switch (ehdr->e_ident[EI_DATA]) { ... } in do_file(), the result does also depend a runtime endianness check. > So, we may need to custom our own elf.h for recordmcount according to > the target type(endian here) of the kernel image: > > At first, pass the target information to recordmcount(only a demo > here, we may need to clear it carefully): > > diff --git a/scripts/Makefile b/scripts/Makefile > index 2e08810..151fe3e 100644 > --- a/scripts/Makefile > +++ b/scripts/Makefile > @@ -11,6 +11,9 @@ hostprogs-$(CONFIG_KALLSYMS)     += kallsyms >  hostprogs-$(CONFIG_LOGO)         += pnmtologo >  hostprogs-$(CONFIG_VT)           += conmakehash >  hostprogs-$(CONFIG_IKCONFIG)     += bin2c > +HOSTCFLAGS_recordmcount.o        += -DARCH=__$(ARCH)__ \ > +       -DBIT=__$(if $(CONFIG_64BIT),64,32)__           \ > +       -DENDIAN=__$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)__ >  hostprogs-$(BUILD_C_RECORDMCOUNT) += recordmcount > >  always         := $(hostprogs-y) $(hostprogs-m) > hum, % grep "BIT\|ENDIAN" scripts/recordmcount.* scripts/recordmcount.h: mcsec.sh_type = w(SHT_PROGBITS); scripts/recordmcount.h: if (SHT_PROGBITS != w(txthdr->sh_type) || so none these macro are not checked explicitly, and headers included should not either. - Arnaud From ralf@linux-mips.org Mon Nov 22 19:47:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 19:47:50 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52318 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492049Ab0KVSrr (ORCPT ); Mon, 22 Nov 2010 19:47:47 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oAMIlk5M014549; Mon, 22 Nov 2010 18:47:46 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oAMIlkDl014538; Mon, 22 Nov 2010 18:47:46 GMT Date: Mon, 22 Nov 2010 18:47:46 +0000 From: Ralf Baechle To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: JZ4740: Fix pcm device name Message-ID: <20101122184745.GB8802@linux-mips.org> References: <1289498933-12836-1-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1289498933-12836-1-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28451 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Mon Nov 22 21:28:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 21:28:42 +0100 (CET) Received: from h5.dl5rb.org.uk ([81.2.74.5]:55673 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492068Ab0KVU2j (ORCPT ); Mon, 22 Nov 2010 21:28:39 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id oAMKSZ0s016348; Mon, 22 Nov 2010 20:28:35 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id oAMKSYl8016333; Mon, 22 Nov 2010 20:28:34 GMT Date: Mon, 22 Nov 2010 20:28:34 +0000 From: Ralf Baechle To: Joe Perches Cc: Jiri Kosina , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 02/14] arch/mips: Use printf extension %pR for struct resource Message-ID: <20101122202834.GC8802@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28452 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.38. Ralf From Andrei.Ardelean@idt.com Mon Nov 22 21:52:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 21:52:14 +0100 (CET) Received: from mxout1.idt.com ([157.165.5.25]:39368 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492039Ab0KVUwL convert rfc822-to-8bit (ORCPT ); Mon, 22 Nov 2010 21:52:11 +0100 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id oAMKq08U017768; Mon, 22 Nov 2010 12:52:00 -0800 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id oAMKpwjY003538; Mon, 22 Nov 2010 12:51:58 -0800 (PST) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id oAMKpw201700; Mon, 22 Nov 2010 12:51:58 -0800 (PST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: The new "real" console doesn't display printk() messages like "early" console! Date: Mon, 22 Nov 2010 12:51:56 -0800 Message-ID: In-Reply-To: <4CE6A103.8030009@mvista.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: The new "real" console doesn't display printk() messages like "early" console! Thread-Index: AcuIBEWDEyxDvHP6TbaTKBiFLvofTACf6kPg References: <4CE57C92.6030705@mvista.com> <4CE6A103.8030009@mvista.com> From: "Ardelean, Andrei" To: "Sergei Shtylyov" Cc: "Ricardo Mendoza" , X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28453 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi Sergei, " Are your UART registers identity mapped to virtual address space?" My system has DDR memory 0x80000000..0x90000000 (kseg0) and UART is mapped starting with bbf01000 (kseg1). Can you give me some details about your question? I didn't do anything special for the port other than set_io_port_base(GD_PORT_BASE); in gd-init.c Thanks, Andrei -----Original Message----- From: Sergei Shtylyov [mailto:sshtylyov@mvista.com] Sent: Friday, November 19, 2010 11:09 AM To: Ardelean, Andrei Cc: Ricardo Mendoza; linux-mips@linux-mips.org Subject: Re: The new "real" console doesn't display printk() messages like "early" console! Ardelean, Andrei wrote: > Hi Ricardo, > I implemented serial platform driver taking as model serial.c from > cavium-octeon. I think you should really have used something simpler as an example. > Here is my code: > /* > * This file is subject to the terms and conditions of the GNU General > Public > * License. See the file "COPYING" in the main directory of this > archive > * for more details. > * > * Copyright (C) 2004-2007 Cavium Networks > */ > > #include > #include > #include > #include > #include > #include > #include > #include > #include > #include > > > #ifdef CONFIG_GDB_CONSOLE This is never defined for MIPS. And there shouldn't be such dependencies. > #define DEBUG_UART 0 > #else > #define DEBUG_UART 1 > #endif > > unsigned int gd_serial_in(struct uart_port *up, int offset) > { > int rv = inl((unsigned int)(up->membase + (offset << 2))); Should be an empty line here. > if (offset == UART_IIR && (rv & 0xf) == 7) { Are you sure this Octeon specific quirk also allpies to your UART? > /* Busy interrupt, read the USR (39) and try again. */ > inl((unsigned int)(up->membase + (39 << 2))); > rv = inl((unsigned int)(up->membase + (offset << 2))); > } > return rv; > } > > void gd_serial_out(struct uart_port *up, int offset, int value) > { > outl( value & 0xff, (unsigned int)(up->membase + (offset << No spaces allowed after (. > 2))); > } > > /* > * Allocated in .bss, so it is all zeroed. > */ > #define GD_MAX_UARTS 1 Then how DEBUG_UART can be 1? > static struct plat_serial8250_port gd_uart8250_data[GD_MAX_UARTS + 1]; > static struct platform_device gd_uart8250_device = { > .name = "serial8250", > .id = PLAT8250_DEV_PLATFORM, > .dev = { > .platform_data = gd_uart8250_data, Where is 'gd_uart8250_data'? > }, > }; > static void __init gd_uart_set_common(struct plat_serial8250_port *p) > { > p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; > p->type = PORT_GD; What is PORT_GD? > p->iotype = UPIO_MEM; Judging from your code, it should be UPIO_MEM32. > p->regshift = 2; /* I/O addresses are every 4 bytes */ > p->uartclk = UART_CLK; > p->serial_in = gd_serial_in; > p->serial_out = gd_serial_out; > } > > static int __init gd_serial_init(void) > { > int enable_uart0; > struct plat_serial8250_port *p; > > enable_uart0 = 1; What's the point in existence of this variable? > p = gd_uart8250_data; > if (enable_uart0) { > /* Add a ttyS device for hardware uart 0 */ > gd_uart_set_common(p); > p->membase = (void *) offMCU_UART_THR_OR_RBR_OR_DLL; > p->mapbase = offMCU_UART_THR_OR_RBR_OR_DLL; Are your UART registers identity mapped to virtual address space? You are not obliged to pass 'membase', unless you have pre-existing mapping but in this case you also need to pass UPF_IOREMAP in 'flags'. > p->irq = MIPSCPU_INT_UART; > p++; > } > return platform_device_register(&gd_uart8250_device); > } > > device_initcall(gd_serial_init); > ------------------------------------------------------------------------ > ----------------------- > > Thanks, > Andrei WBR, Sergei From David.Daney@caviumnetworks.com Mon Nov 22 22:03:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 22:03:08 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19521 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492039Ab0KVVDB (ORCPT ); Mon, 22 Nov 2010 22:03:01 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 22 Nov 2010 13:03:38 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 22 Nov 2010 13:03:50 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 22 Nov 2010 13:03:50 -0800 Message-ID: <4CEADA80.8030605@caviumnetworks.com> Date: Mon, 22 Nov 2010 13:02:56 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10 MIME-Version: 1.0 To: "Ardelean, Andrei" CC: Sergei Shtylyov , Ricardo Mendoza , linux-mips@linux-mips.org Subject: Re: The new "real" console doesn't display printk() messages like "early" console! References: <4CE57C92.6030705@mvista.com> <4CE6A103.8030009@mvista.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 22 Nov 2010 21:03:50.0884 (UTC) FILETIME=[C3696240:01CB8A88] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28454 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 11/22/2010 12:51 PM, Ardelean, Andrei wrote: > Hi Sergei, > > " Are your UART registers identity mapped to virtual address space?" > > My system has DDR memory 0x80000000..0x90000000 (kseg0) and UART is > mapped starting with bbf01000 (kseg1). Can you give me some details > about your question? > > I didn't do anything special for the port other than > set_io_port_base(GD_PORT_BASE); > in gd-init.c > > I think you need to reset your process here. First you should probably get a prom_putchar() function working. Then enable CONFIG_EARLY_PRINTK. That will enable you to debug many things. If need be, you can write a trivial prom_puts() to go with your prom_putchar(). If you have two serial ports available, all the better. Use one for printing debugging information and the other as the port you are trying to debug. Asking people to stare at the thousands of lines of code that make up the serial I/O system and spot the error in your configuration will probably be less fruitful than tracing through it to find the problem. David Daney From kevink@paralogos.com Mon Nov 22 22:34:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2010 22:34:49 +0100 (CET) Received: from gateway06.websitewelcome.com ([69.56.148.7]:45150 "HELO gateway06.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492049Ab0KVVeq (ORCPT ); Mon, 22 Nov 2010 22:34:46 +0100 Received: (qmail 23542 invoked from network); 22 Nov 2010 21:34:48 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway06.websitewelcome.com with SMTP; 22 Nov 2010 21:34:48 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Source:X-Source-Args:X-Source-Dir; b=VCrQ0AskfF9/KOCtXqaP3mw0R8P14Z4NBH/QaTSXC4XHtpxtCbiebj3nCvjclpN6KU8dhETG3C8zmDeZpoKd0KyC0OXTRdSvedFV4BUVtM5ng3bJQ4xLmyM1niT6NqjP; Received: from [216.239.45.4] (port=1473 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1PKe22-0007T4-Ri; Mon, 22 Nov 2010 15:34:38 -0600 Message-ID: <4CEAE1EE.9020406@paralogos.com> Date: Mon, 22 Nov 2010 13:34:38 -0800 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 MIME-Version: 1.0 To: Ralf Baechle CC: Maksim Rayskiy , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: ASID conflict after CPU hotplug References: <20101122034141.GA13138@linux-mips.org> In-Reply-To: <20101122034141.GA13138@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28455 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips On 11/21/10 19:41, Ralf Baechle wrote: > ... > Need to think a little about potencial consequences of your suggested > patch. It seems ok. Kevin, what do you think? > Since you ask, while I would imagine that Maksim's patch works fine for him, I'm not sure that it's really the right fix. I never did succeed in getting CPU hotplugging working back in the 2.6.18 days, so I don't know as much about it as I'd like, but if per_cpu_trap_init() needs to be invoked on a hot plugin event, and if its behavior needs to be different , I'd really, really prefer to see that state propagated explicitly, rather than inferring it from whatever happens to be in cache/memory at cpu_data[cpu].asid_cache. But beyond that, if the problem arises because setting cpu_data[cpu].asid_cache to a known initial state on a plugin event can conflict with the residual content of EntryHi, rather than creating a special case where we don't initialize the ASID cache, since we seem to be (re)initializing a lot of other privileged state, why aren't we also setting a known sane initial EntryHi value? Wouldn't that be a cleaner fix? (And I don't mean that as a rhetorical question - there may be very good reasons to let EntryHi values persist across hot unplug/plug events. I just can't imagine them offhand over coffee.) /K. From jreiser@bitwagon.com Tue Nov 23 04:42:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 04:42:30 +0100 (CET) Received: from bitwagon.com ([74.82.39.175]:49821 "HELO bitwagon.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1490975Ab0KWDmX (ORCPT ); Tue, 23 Nov 2010 04:42:23 +0100 Received: from f11-64.local ([67.171.188.169]) by bitwagon.com for ; Mon, 22 Nov 2010 19:42:10 -0800 Message-ID: <4CEB37F8.1050504@bitwagon.com> Date: Mon, 22 Nov 2010 19:41:44 -0800 From: John Reiser Organization: - User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc11 Thunderbird/3.0.4 MIME-Version: 1.0 To: Arnaud Lacombe CC: Steven Rostedt , linux-mips@linux-mips.org, wu zhangjin Subject: Re: Build failure triggered by recordmcount References: In-Reply-To: X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28456 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jreiser@bitwagon.com Precedence: bulk X-list: linux-mips It looks to me like the change which introduced "virtual functions" forgot about cross-platform endianness. Can anyone please test this patch? Thank you to Arnaud for supplying before+after data files do_mounts*.o. recordmcount: Honor endianness in fn_ELF_R_INFO --- scripts/recordmcount.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/scripts/recordmcount.h b/scripts/recordmcount.h index 58e933a..3966717 100644 --- a/scripts/recordmcount.h +++ b/scripts/recordmcount.h @@ -119,7 +119,7 @@ static uint_t (*Elf_r_sym)(Elf_Rel const *rp) = fn_ELF_R_SYM; static void fn_ELF_R_INFO(Elf_Rel *const rp, unsigned sym, unsigned type) { - rp->r_info = ELF_R_INFO(sym, type); + rp->r_info = _w(ELF_R_INFO(sym, type)); } static void (*Elf_r_info)(Elf_Rel *const rp, unsigned sym, unsigned type) = fn_ELF_R_INFO; -- 1.7.3.2 -- From wuzhangjin@gmail.com Tue Nov 23 05:56:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 05:56:20 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:43193 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491064Ab0KWE4R convert rfc822-to-8bit (ORCPT ); Tue, 23 Nov 2010 05:56:17 +0100 Received: by wyf22 with SMTP id 22so8026746wyf.36 for ; Mon, 22 Nov 2010 20:56:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=FtHr4avgQlvEjwV6TUvb9s/69vjFRdAw0yCRzKo99GE=; b=R4eGOd+Rb0HAdtiv/MSlIHfv1wVg67hrn7ciotpHua8j4tHSh2q1BikdZpoocxhwnY yeHNNiJtz/KBQs0s78aFgU+wA5wKLJXkqbl0UoXgxG+R8xJIxOy1HZe8h7xtZCWdDQ3K 4+EAfgSyC8oHCPvD+o3ndLSbUrrVgFAq9H/Qc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=BsXd6SNUPOsimpcCjpj5DPRlAMw9ZVrHKrTZbXWIZ4ogJGKAT22Rxdc8P/kprS/MLy iellVIgtdVvRP4KD5sOj19E1+gYT5xJIY8Xo7oLlVbPBBncdh60JAaUvEnpF27ZntKRV MQlTFp7LZGYyAIcSaST8u5BBNcMTvSmiPbXqg= MIME-Version: 1.0 Received: by 10.216.142.131 with SMTP id i3mr495752wej.5.1290488171743; Mon, 22 Nov 2010 20:56:11 -0800 (PST) Received: by 10.216.131.88 with HTTP; Mon, 22 Nov 2010 20:56:11 -0800 (PST) In-Reply-To: <4CEB37F8.1050504@bitwagon.com> References: <4CEB37F8.1050504@bitwagon.com> Date: Tue, 23 Nov 2010 12:56:11 +0800 Message-ID: Subject: Re: Build failure triggered by recordmcount From: wu zhangjin To: John Reiser Cc: Arnaud Lacombe , Steven Rostedt , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28457 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This does solve the problem, now we get the right result: $ readelf -a init/do_mounts.o Relocation section '.rel__mcount_loc' at offset 0x2f60 contains 2 entries: Offset Info Type Sym.Value Sym. Name 00000000 00000202 R_MIPS_32 00000000 .text 00000004 00000202 R_MIPS_32 00000000 .text On Tue, Nov 23, 2010 at 11:41 AM, John Reiser wrote: > It looks to me like the change which introduced "virtual functions" > forgot about cross-platform endianness.  Can anyone please test this patch? > Thank you to Arnaud for supplying before+after data files do_mounts*.o. > > > recordmcount: Honor endianness in fn_ELF_R_INFO > > --- >  scripts/recordmcount.h |    2 +- >  1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/scripts/recordmcount.h b/scripts/recordmcount.h > index 58e933a..3966717 100644 > --- a/scripts/recordmcount.h > +++ b/scripts/recordmcount.h > @@ -119,7 +119,7 @@ static uint_t (*Elf_r_sym)(Elf_Rel const *rp) = fn_ELF_R_SYM; >  static void fn_ELF_R_INFO(Elf_Rel *const rp, unsigned sym, unsigned type) >  { > -       rp->r_info = ELF_R_INFO(sym, type); > +       rp->r_info = _w(ELF_R_INFO(sym, type)); >  } >  static void (*Elf_r_info)(Elf_Rel *const rp, unsigned sym, unsigned type) = fn_ELF_R_INFO; >  -- 1.7.3.2 > > > -- > From wuzhangjin@gmail.com Tue Nov 23 06:20:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 06:21:02 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:61144 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491063Ab0KWFUz convert rfc822-to-8bit (ORCPT ); Tue, 23 Nov 2010 06:20:55 +0100 Received: by wyf22 with SMTP id 22so8042369wyf.36 for ; Mon, 22 Nov 2010 21:20:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=K9YB+Bnm76Yq9/OSteyQ+oCmNErk/nVlswFass1VxCg=; b=unIp3YyUdriIz6gR1/4WQvi1W1sE3BHUTyHShZZM4UEex60N9rXaIpZk/RrPZYeunW xW1K01hKQ+4eMEy8y1xAqo1KJbc1Lx4b33ZwCAQ5nH3WGj0eblP0I06HbNoBp9CwVOG2 aodRg2b4Bg52J3TW304hI6AjyVmRqN4DguDHk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=gJp2rJghul6JLfB8wxlR+Mn6y3upIb6V77ff6WMLojHb6xjlBjCpjvo7ocnaP6HnOB fzXk8RVEAMBHxdAgKe6jNlvKdSHyUV2udV3h03pnAd0mseRPl0ry1xp6zJRzk+S6O56D iAa6crbzwQiStX2BUCeRmm927w08SvQ2p+gJA= MIME-Version: 1.0 Received: by 10.216.30.65 with SMTP id j43mr6074841wea.20.1290489648999; Mon, 22 Nov 2010 21:20:48 -0800 (PST) Received: by 10.216.131.88 with HTTP; Mon, 22 Nov 2010 21:20:28 -0800 (PST) In-Reply-To: References: Date: Tue, 23 Nov 2010 13:20:28 +0800 Message-ID: Subject: Re: Build failure triggered by recordmcount From: wu zhangjin To: Arnaud Lacombe Cc: John Reiser , Steven Rostedt , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28458 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Tue, Nov 23, 2010 at 2:46 AM, Arnaud Lacombe wrote: > Hi, > > On Mon, Nov 22, 2010 at 9:57 AM, wu zhangjin wrote: >> Hi, >> >> The cause should be the endian problem, I guess you were cross-compiling it? >> > yes. > >> If we compile the kernel for (32bit + big endian) target on an x86 >> machine(little endian) or reversely, then, it will fail. >> >> Since the scripts/recordmcount is compiled with the local toolchain, >> the data structs will be explained according to the local >> configuration(endian...). >> > will it ? recordmcount.c does not switch endianness based on the host, > but based on format of the object file, see the switch > (ehdr->e_ident[EI_DATA]) { ... } in do_file(), the result does also > depend a runtime endianness check. Yes ;-) > >> So, we may need to custom our own elf.h for recordmcount according to >> the target type(endian here) of the kernel image: >> >> At first, pass the target information to recordmcount(only a demo >> here, we may need to clear it carefully): >> >> diff --git a/scripts/Makefile b/scripts/Makefile >> index 2e08810..151fe3e 100644 >> --- a/scripts/Makefile >> +++ b/scripts/Makefile >> @@ -11,6 +11,9 @@ hostprogs-$(CONFIG_KALLSYMS)     += kallsyms >>  hostprogs-$(CONFIG_LOGO)         += pnmtologo >>  hostprogs-$(CONFIG_VT)           += conmakehash >>  hostprogs-$(CONFIG_IKCONFIG)     += bin2c >> +HOSTCFLAGS_recordmcount.o        += -DARCH=__$(ARCH)__ \ >> +       -DBIT=__$(if $(CONFIG_64BIT),64,32)__           \ >> +       -DENDIAN=__$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)__ >>  hostprogs-$(BUILD_C_RECORDMCOUNT) += recordmcount >> >>  always         := $(hostprogs-y) $(hostprogs-m) >> > hum, > > % grep "BIT\|ENDIAN" scripts/recordmcount.* > scripts/recordmcount.h: mcsec.sh_type = w(SHT_PROGBITS); > scripts/recordmcount.h: if (SHT_PROGBITS != w(txthdr->sh_type) || > > so none these macro are not checked explicitly, and headers included > should not either. John have already abstracted w, w2, w8 to handle the endianess problem, I just forgot looking to them, sorry ;-) BTW, 1. But check the endianess and ARCH before compiling the scripts/recordmcount.c may speedup it a lot for after issuing "make ARCH=XXX", everything including the endianess and ARCH of the object files are definite, so, we may don't need to check them at runtime. of course, check them at runtime can avoid compiling it for different ARCHs but who will use this for different ARCHs at the same time ;-) 2. In the long run, we may be possible to add a new option(with -pg) to gcc and ask it to create a __mcount_loc section for us, then, we will be able to use it in kernel directly. I think gcc will be easier to put the _mcount calling sites into a section because it adds them and therefore knows 'more'(where, endianess, type... are definite) about them, but in kernel, we need extra/complex search, check and relocation... Thanks & Regards, Wu Zhangjin From dengcheng.zhu@gmail.com Tue Nov 23 08:06:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 08:06:31 +0100 (CET) Received: from mail-wy0-f177.google.com ([74.125.82.177]:59699 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491121Ab0KWHGX convert rfc822-to-8bit (ORCPT ); Tue, 23 Nov 2010 08:06:23 +0100 Received: by wyf22 with SMTP id 22so8113344wyf.36 for ; Mon, 22 Nov 2010 23:06:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=fa5+JN7Vnmc6ILXELWRTUdO/QRPi0Gj7o3hFjuTtmfE=; b=VvYd4tAeqogKcz7zwMu42/sc8MaL/oSzCk1I+Y8rClJCH+5c7j6qlAmX9IvsItVS2/ u3nSFAXnDSgS/KBRajdpspue+bb4FK5bKxu+EOtjg6B3w1PKQRYq9U9vSk0O/iwKmvua OYGYT3hHPgowktWNcLgPJfLOYoua0W/e4T4iU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=OojGxKHTZeDKqf/CzjWgh/rE0Sj7lkQBpo+Zx7pWsiUv3wWCJNnQ6PqiiKIAudyfWS F1pG1pw3+hQYbuqUZeJT6anzQuyUXr/qpNkAST/3USXRuVPDopO2loodZQHAwDmwDdxL Kw5U4VKTajnmKR9HyASrrVr0dAg9IYra0R+6o= MIME-Version: 1.0 Received: by 10.216.54.147 with SMTP id i19mr544641wec.59.1290495977373; Mon, 22 Nov 2010 23:06:17 -0800 (PST) Received: by 10.216.236.138 with HTTP; Mon, 22 Nov 2010 23:06:17 -0800 (PST) In-Reply-To: <20101119143416.GA5558@nowhere> References: <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-5-git-send-email-dengcheng.zhu@gmail.com> <20101119143416.GA5558@nowhere> Date: Tue, 23 Nov 2010 15:06:17 +0800 Message-ID: Subject: Re: [PATCH 4/5] MIPS/Perf-events: Work with the new callchain interface From: Deng-Cheng Zhu To: Frederic Weisbecker Cc: ralf@linux-mips.org, a.p.zijlstra@chello.nl, will.deacon@arm.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28459 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Yes, MIPS Perf-events got added in recently and missed some important commits. Thanks! Deng-Cheng 2010/11/19 Frederic Weisbecker : > On Thu, Nov 18, 2010 at 02:56:40PM +0800, Deng-Cheng Zhu wrote: >> This is the MIPS part of the following commits by Frederic Weisbecker: >> >> f72c1a931e311bb7780fee19e41a89ac42cab50e >>       perf: Factorize callchain context handling >> 56962b4449af34070bb1994621ef4f0265eed4d8 >>       perf: Generalize some arch callchain code >> 70791ce9ba68a5921c9905ef05d23f62a90bc10c >>       perf: Generalize callchain_store() >> c1a65932fd7216fdc9a0db8bbffe1d47842f862c >>       perf: Drop unappropriate tests on arch callchains >> >> Signed-off-by: Deng-Cheng Zhu >> --- > > > Acked-by: Frederic Weisbecker > > Why did I miss this arch? I did a grep on HAVE_PERF_EVENT or something, > may be it hadn't it at that time? > > Thanks! > > From dmitri.vorobiev@movial.com Tue Nov 23 12:32:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 12:33:02 +0100 (CET) Received: from smtp-68.nebula.fi ([83.145.220.68]:42036 "EHLO smtp-68.nebula.fi" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491894Ab0KWLcz (ORCPT ); Tue, 23 Nov 2010 12:32:55 +0100 Received: from localhost.localdomain (dyn-xdsl-83-150-115-228.nebulazone.fi [83.150.115.228]) by smtp-68.nebula.fi (Postfix) with ESMTP id BE41A43F0497; Tue, 23 Nov 2010 13:32:43 +0200 (EET) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Dmitri Vorobiev Subject: [PATCH] MIPS: Fix build failure for IP22 Date: Tue, 23 Nov 2010 13:32:28 +0200 Message-Id: <1290511948-10347-1-git-send-email-dmitri.vorobiev@movial.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28460 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.com Precedence: bulk X-list: linux-mips Commit 48e1fd5a81416a037f5a48120bf281102f2584e2 changed the name of the MIPS-specific dma_cache_sync() routine by prefixing it with `mips_', and removed the export for its symbol. Two drivers, which did use dma_cache_sync(), namely, sgiseeq and sgiwd93, were not converted to use the new function, which led to build failure for the IP22 platform. This patch fixes the build failure by fixing the call sites of mips_dma_cache_sync() and exporting the symbol for this routine as a GPL symbol. While at it, some minor changes to improve Kconfig help entries were done. Signed-off-by: Dmitri Vorobiev --- arch/mips/include/asm/dma-mapping.h | 2 +- arch/mips/mm/dma-default.c | 1 + drivers/net/Kconfig | 3 +++ drivers/net/sgiseeq.c | 8 ++++---- drivers/scsi/Kconfig | 3 +++ drivers/scsi/sgiwd93.c | 2 +- 6 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 655f849..ecf669d 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -52,7 +52,7 @@ dma_set_mask(struct device *dev, u64 mask) return 0; } -extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, +extern void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction); static inline void *dma_alloc_coherent(struct device *dev, size_t size, diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 4fc1a0f..114e9bb 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -297,6 +297,7 @@ void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size, if (!plat_device_is_coherent(dev)) __dma_sync((unsigned long)vaddr, size, direction); } +EXPORT_SYMBOL_GPL(mips_dma_cache_sync); static struct dma_map_ops mips_default_dma_map_ops = { .alloc_coherent = mips_dma_alloc_coherent, diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f6668cd..fe64edc 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1925,6 +1925,9 @@ config SGISEEQ Say Y here if you have an Seeq based Ethernet network card. This is used in many Silicon Graphics machines. + To compile this driver as a module, choose M here: the module + will be called sgiseeq. + config DECLANCE tristate "DEC LANCE ethernet controller support" depends on MACH_DECSTATION diff --git a/drivers/net/sgiseeq.c b/drivers/net/sgiseeq.c index 3a0cc63..6ecefd2 100644 --- a/drivers/net/sgiseeq.c +++ b/drivers/net/sgiseeq.c @@ -111,14 +111,14 @@ struct sgiseeq_private { static inline void dma_sync_desc_cpu(struct net_device *dev, void *addr) { - dma_cache_sync(dev->dev.parent, addr, sizeof(struct sgiseeq_rx_desc), - DMA_FROM_DEVICE); + mips_dma_cache_sync(dev->dev.parent, addr, + sizeof(struct sgiseeq_rx_desc), DMA_FROM_DEVICE); } static inline void dma_sync_desc_dev(struct net_device *dev, void *addr) { - dma_cache_sync(dev->dev.parent, addr, sizeof(struct sgiseeq_rx_desc), - DMA_TO_DEVICE); + mips_dma_cache_sync(dev->dev.parent, addr, + sizeof(struct sgiseeq_rx_desc), DMA_TO_DEVICE); } static inline void hpc3_eth_reset(struct hpc3_ethregs *hregs) diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 8616496..2d868bf 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -390,6 +390,9 @@ config SGIWD93_SCSI If you have a Western Digital WD93 SCSI controller on an SGI MIPS system, say Y. Otherwise, say N. + To compile this driver as a module, choose M here: the + module will be called sgiwd93. + config BLK_DEV_3W_XXXX_RAID tristate "3ware 5/6/7/8xxx ATA-RAID support" depends on PCI && SCSI diff --git a/drivers/scsi/sgiwd93.c b/drivers/scsi/sgiwd93.c index fef0e3c..be9fc40 100644 --- a/drivers/scsi/sgiwd93.c +++ b/drivers/scsi/sgiwd93.c @@ -95,7 +95,7 @@ void fill_hpc_entries(struct ip22_hostdata *hd, struct scsi_cmnd *cmd, int din) */ hcp->desc.pbuf = 0; hcp->desc.cntinfo = HPCDMA_EOX; - dma_cache_sync(hd->dev, hd->cpu, + mips_dma_cache_sync(hd->dev, hd->cpu, (unsigned long)(hcp + 1) - (unsigned long)hd->cpu, DMA_TO_DEVICE); } -- 1.7.0.4 From sshtylyov@mvista.com Tue Nov 23 13:07:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 13:07:15 +0100 (CET) Received: from mail-ey0-f177.google.com ([209.85.215.177]:57287 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491911Ab0KWMHI (ORCPT ); Tue, 23 Nov 2010 13:07:08 +0100 Received: by eyd9 with SMTP id 9so4504657eyd.36 for ; Tue, 23 Nov 2010 04:07:07 -0800 (PST) Received: by 10.213.9.212 with SMTP id m20mr6575008ebm.11.1290514026792; Tue, 23 Nov 2010 04:07:06 -0800 (PST) Received: from [192.168.2.2] ([91.79.70.65]) by mx.google.com with ESMTPS id x54sm5739316eeh.23.2010.11.23.04.07.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 23 Nov 2010 04:07:05 -0800 (PST) Message-ID: <4CEBADFB.7040003@mvista.com> Date: Tue, 23 Nov 2010 15:05:15 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 To: Dmitri Vorobiev CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: Fix build failure for IP22 References: <1290511948-10347-1-git-send-email-dmitri.vorobiev@movial.com> In-Reply-To: <1290511948-10347-1-git-send-email-dmitri.vorobiev@movial.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28461 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. On 23-11-2010 14:32, Dmitri Vorobiev wrote: > Commit 48e1fd5a81416a037f5a48120bf281102f2584e2 changed the name Linus has asled to also specify the commit summary in parens. > of the MIPS-specific dma_cache_sync() routine by prefixing it with > `mips_', and removed the export for its symbol. Two drivers, which > did use dma_cache_sync(), namely, sgiseeq and sgiwd93, were not > converted to use the new function, which led to build failure for > the IP22 platform. > This patch fixes the build failure by fixing the call sites of > mips_dma_cache_sync() and exporting the symbol for this routine as > a GPL symbol. While at it, some minor changes to improve Kconfig > help entries were done. > Signed-off-by: Dmitri Vorobiev [...] > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index f6668cd..fe64edc 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -1925,6 +1925,9 @@ config SGISEEQ > Say Y here if you have an Seeq based Ethernet network card. This is > used in many Silicon Graphics machines. > > + To compile this driver as a module, choose M here: the module > + will be called sgiseeq. > + This change is not metioned in the patch description... > diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig > index 8616496..2d868bf 100644 > --- a/drivers/scsi/Kconfig > +++ b/drivers/scsi/Kconfig > @@ -390,6 +390,9 @@ config SGIWD93_SCSI > If you have a Western Digital WD93 SCSI controller on > an SGI MIPS system, say Y. Otherwise, say N. > > + To compile this driver as a module, choose M here: the > + module will be called sgiwd93. > + This change is not metioned in the patch description... > diff --git a/drivers/scsi/sgiwd93.c b/drivers/scsi/sgiwd93.c > index fef0e3c..be9fc40 100644 > --- a/drivers/scsi/sgiwd93.c > +++ b/drivers/scsi/sgiwd93.c > @@ -95,7 +95,7 @@ void fill_hpc_entries(struct ip22_hostdata *hd, struct scsi_cmnd *cmd, int din) > */ > hcp->desc.pbuf = 0; > hcp->desc.cntinfo = HPCDMA_EOX; > - dma_cache_sync(hd->dev, hd->cpu, > + mips_dma_cache_sync(hd->dev, hd->cpu, > (unsigned long)(hcp + 1) - (unsigned long)hd->cpu, > DMA_TO_DEVICE); Don't you want to move the aboev 2 lines to the right also? You're breaking the existing alignments and leaving alignment spaces intact... WBR, Sergei From akinobu.mita@gmail.com Tue Nov 23 14:40:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 14:40:53 +0100 (CET) Received: from mail-pw0-f49.google.com ([209.85.160.49]:49718 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491925Ab0KWNkq (ORCPT ); Tue, 23 Nov 2010 14:40:46 +0100 Received: by pwj8 with SMTP id 8so2048378pwj.36 for ; Tue, 23 Nov 2010 05:40:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=IQIxxY2CIgtMVg1940hN1VNUR+Va3+da8u0nHf7MtN4=; b=YzQ2qqXTsdS4D3oYL/ihQaT4GDu3lgrEu+T9IvW0uJrPewNOZxlrzZUEvlOeU3c2sK YL9UhEVxXcDexusrETGWPOXsNB8Y9ffmVoIhrzy741nNTUnF1xGG8Ojebuu/iTHnNq88 v+n+qpexQZ0oakM3Di77Kyr6mP0SmZT7zv2vU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=GGpJfvcO2TINvihcBwKCkFLI04/NNE52R0tjYRsGMxEhVHWAA9IgcqaK7ArrPLm07V Q1TzQy1yPMobHcTHMtYCyf3tNJItqi2P+t8LzRXhR+7vb33QtYpvjssxjGyiWruV1CNi gxm/iXjmeixAk6ZmRzKBA81bw+6YQQhyMnrCI= Received: by 10.142.133.21 with SMTP id g21mr6701476wfd.163.1290519637263; Tue, 23 Nov 2010 05:40:37 -0800 (PST) Received: from localhost.localdomain (p8025-adsao01yokonib2-acca.kanagawa.ocn.ne.jp [219.161.30.25]) by mx.google.com with ESMTPS id x35sm7930281wfd.1.2010.11.23.05.40.30 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 23 Nov 2010 05:40:36 -0800 (PST) From: Akinobu Mita To: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Andrew Morton Cc: Akinobu Mita , Geert Uytterhoeven , Roman Zippel , Andreas Schwab , linux-m68k@lists.linux-m68k.org, Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, linux-s390@vger.kernel.org, Yoshinori Sato , Michal Simek , microblaze-uclinux@itee.uq.edu.au, "David S. Miller" , sparclinux@vger.kernel.org, Hirokazu Takata , linux-m32r@ml.linux-m32r.org, Ralf Baechle , linux-mips@linux-mips.org, Paul Mundt , linux-sh@vger.kernel.org, Chris Zankel Subject: [PATCH v3 22/22] bitops: remove minix bitops from asm/bitops.h Date: Tue, 23 Nov 2010 22:38:24 +0900 Message-Id: <1290519504-3958-23-git-send-email-akinobu.mita@gmail.com> X-Mailer: git-send-email 1.7.3.2 In-Reply-To: <1290519504-3958-1-git-send-email-akinobu.mita@gmail.com> References: <1290519504-3958-1-git-send-email-akinobu.mita@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28462 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akinobu.mita@gmail.com Precedence: bulk X-list: linux-mips minix bit operations are only used by minix filesystem and useless by other modules. Because byte order of inode and block bitmaps is defferent on each architecture like below: m68k: big-endian 16bit indexed bitmaps h8300, microblaze, s390, sparc, m68knommu: big-endian 32 or 64bit indexed bitmaps m32r, mips, sh, xtensa: big-endian 32 or 64bit indexed bitmaps for big-endian mode little-endian bitmaps for little-endian mode Others: little-endian bitmaps In order to move minix bit operations from asm/bitops.h to architecture independent code in minix file system, this provides two config options. CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED is only selected by m68k. CONFIG_MINIX_FS_NATIVE_ENDIAN is selected by the architectures which use native byte order bitmaps (h8300, microblaze, s390, sparc, m68knommu, m32r, mips, sh, xtensa). The architectures which always use little-endian bitmaps do not select these options. Finally, we can remove minix bit operations from asm/bitops.h for all architectures. Signed-off-by: Akinobu Mita Acked-by: Arnd Bergmann Acked-by: Greg Ungerer Cc: Geert Uytterhoeven Cc: Roman Zippel Cc: Andreas Schwab Cc: linux-m68k@lists.linux-m68k.org Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Yoshinori Sato Cc: Michal Simek Cc: microblaze-uclinux@itee.uq.edu.au Cc: "David S. Miller" Cc: sparclinux@vger.kernel.org Cc: Hirokazu Takata Cc: linux-m32r@ml.linux-m32r.org Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: Paul Mundt Cc: linux-sh@vger.kernel.org Cc: Chris Zankel --- No change from previous submission arch/alpha/include/asm/bitops.h | 2 - arch/arm/include/asm/bitops.h | 14 ------ arch/avr32/include/asm/bitops.h | 1 - arch/blackfin/include/asm/bitops.h | 1 - arch/cris/include/asm/bitops.h | 1 - arch/frv/include/asm/bitops.h | 2 - arch/h8300/include/asm/bitops.h | 1 - arch/ia64/include/asm/bitops.h | 1 - arch/m32r/include/asm/bitops.h | 1 - arch/m68k/include/asm/bitops_mm.h | 30 ------------ arch/mips/include/asm/bitops.h | 1 - arch/mn10300/include/asm/bitops.h | 1 - arch/parisc/include/asm/bitops.h | 2 - arch/powerpc/include/asm/bitops.h | 14 ------ arch/s390/include/asm/bitops.h | 1 - arch/sh/include/asm/bitops.h | 1 - arch/sparc/include/asm/bitops_32.h | 1 - arch/sparc/include/asm/bitops_64.h | 2 - arch/tile/include/asm/bitops.h | 1 - arch/x86/include/asm/bitops.h | 2 - arch/xtensa/include/asm/bitops.h | 1 - fs/minix/Kconfig | 8 +++ fs/minix/minix.h | 79 +++++++++++++++++++++++++++++++++ include/asm-generic/bitops.h | 1 - include/asm-generic/bitops/minix-le.h | 15 ------ include/asm-generic/bitops/minix.h | 15 ------ 26 files changed, 87 insertions(+), 112 deletions(-) delete mode 100644 include/asm-generic/bitops/minix-le.h delete mode 100644 include/asm-generic/bitops/minix.h diff --git a/arch/alpha/include/asm/bitops.h b/arch/alpha/include/asm/bitops.h index 822433a..85b8152 100644 --- a/arch/alpha/include/asm/bitops.h +++ b/arch/alpha/include/asm/bitops.h @@ -459,8 +459,6 @@ sched_find_first_bit(const unsigned long b[2]) #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) -#include - #endif /* __KERNEL__ */ #endif /* _ALPHA_BITOPS_H */ diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index ac2edb4..59a2a2b 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -332,20 +332,6 @@ static inline int fls(int x) #define ext2_clear_bit_atomic(lock,nr,p) \ test_and_clear_le_bit(nr, (unsigned long *)(p)) -/* - * Minix is defined to use little-endian byte ordering. - * These do not need to be atomic. - */ -#define minix_set_bit(nr,p) \ - __set_le_bit(nr, (unsigned long *)(p)) -#define minix_test_bit(nr,p) \ - test_le_bit(nr, (unsigned long *)(p)) -#define minix_test_and_set_bit(nr,p) \ - __test_and_set_le_bit(nr, (unsigned long *)(p)) -#define minix_test_and_clear_bit(nr,p) \ - __test_and_clear_le_bit(nr, (unsigned long *)(p)) -#define minix_find_first_zero_bit(p,sz) \ - find_first_zero_le_bit((unsigned long *)(p), sz) #endif /* __KERNEL__ */ diff --git a/arch/avr32/include/asm/bitops.h b/arch/avr32/include/asm/bitops.h index 73a163a..72444d9 100644 --- a/arch/avr32/include/asm/bitops.h +++ b/arch/avr32/include/asm/bitops.h @@ -301,6 +301,5 @@ static inline int ffs(unsigned long word) #include #include -#include #endif /* __ASM_AVR32_BITOPS_H */ diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 2c549f7..68843fa 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -27,7 +27,6 @@ #include #include -#include #ifndef CONFIG_SMP #include diff --git a/arch/cris/include/asm/bitops.h b/arch/cris/include/asm/bitops.h index 71bea40..310e0de 100644 --- a/arch/cris/include/asm/bitops.h +++ b/arch/cris/include/asm/bitops.h @@ -159,7 +159,6 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) -#include #include #endif /* __KERNEL__ */ diff --git a/arch/frv/include/asm/bitops.h b/arch/frv/include/asm/bitops.h index e3ea644..a1d00b0 100644 --- a/arch/frv/include/asm/bitops.h +++ b/arch/frv/include/asm/bitops.h @@ -406,8 +406,6 @@ int __ilog2_u64(u64 n) #define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit ((nr) ^ 0x18, (addr)) #define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr) ^ 0x18, (addr)) -#include - #endif /* __KERNEL__ */ #endif /* _ASM_BITOPS_H */ diff --git a/arch/h8300/include/asm/bitops.h b/arch/h8300/include/asm/bitops.h index 23cea66..e856c1b 100644 --- a/arch/h8300/include/asm/bitops.h +++ b/arch/h8300/include/asm/bitops.h @@ -202,7 +202,6 @@ static __inline__ unsigned long __ffs(unsigned long word) #include #include #include -#include #endif /* __KERNEL__ */ diff --git a/arch/ia64/include/asm/bitops.h b/arch/ia64/include/asm/bitops.h index 336984a..b76f7e0 100644 --- a/arch/ia64/include/asm/bitops.h +++ b/arch/ia64/include/asm/bitops.h @@ -461,7 +461,6 @@ static __inline__ unsigned long __arch_hweight64(unsigned long x) #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) -#include #include #endif /* __KERNEL__ */ diff --git a/arch/m32r/include/asm/bitops.h b/arch/m32r/include/asm/bitops.h index cdfb4c8..6300f22 100644 --- a/arch/m32r/include/asm/bitops.h +++ b/arch/m32r/include/asm/bitops.h @@ -268,7 +268,6 @@ static __inline__ int test_and_change_bit(int nr, volatile void * addr) #include #include -#include #endif /* __KERNEL__ */ diff --git a/arch/m68k/include/asm/bitops_mm.h b/arch/m68k/include/asm/bitops_mm.h index f31ed5a..5f06275 100644 --- a/arch/m68k/include/asm/bitops_mm.h +++ b/arch/m68k/include/asm/bitops_mm.h @@ -325,36 +325,6 @@ static inline int __fls(int x) #include #include -/* Bitmap functions for the minix filesystem */ - -static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size) -{ - const unsigned short *p = vaddr, *addr = vaddr; - unsigned short num; - - if (!size) - return 0; - - size = (size >> 4) + ((size & 15) > 0); - while (*p++ == 0xffff) { - if (--size == 0) - return (p - addr) << 4; - } - - num = *--p; - return ((p - addr) << 4) + ffz(num); -} - -#define minix_test_and_set_bit(nr, addr) __test_and_set_bit((nr) ^ 16, (unsigned long *)(addr)) -#define minix_set_bit(nr,addr) __set_bit((nr) ^ 16, (unsigned long *)(addr)) -#define minix_test_and_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr)) - -static inline int minix_test_bit(int nr, const void *vaddr) -{ - const unsigned short *p = vaddr; - return (p[nr >> 4] & (1U << (nr & 15))) != 0; -} - /* Bitmap functions for little endian. */ #define __set_le_bit(nr, addr) \ diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index e062718..2e1ad4c 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -678,7 +678,6 @@ static inline int ffs(int word) #include #include -#include #endif /* __KERNEL__ */ diff --git a/arch/mn10300/include/asm/bitops.h b/arch/mn10300/include/asm/bitops.h index a5f460c..0939462 100644 --- a/arch/mn10300/include/asm/bitops.h +++ b/arch/mn10300/include/asm/bitops.h @@ -234,7 +234,6 @@ int ffs(int x) test_and_clear_bit((nr), (addr)) #include -#include #endif /* __KERNEL__ */ #endif /* __ASM_BITOPS_H */ diff --git a/arch/parisc/include/asm/bitops.h b/arch/parisc/include/asm/bitops.h index 919d7ed..43c516f 100644 --- a/arch/parisc/include/asm/bitops.h +++ b/arch/parisc/include/asm/bitops.h @@ -234,6 +234,4 @@ static __inline__ int fls(int x) #endif /* __KERNEL__ */ -#include - #endif /* _PARISC_BITOPS_H */ diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index eb9ce7f..bf5ccfc 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -308,20 +308,6 @@ unsigned long find_next_le_bit(const unsigned long *addr, #define ext2_clear_bit_atomic(lock, nr, addr) \ test_and_clear_le_bit((nr), (unsigned long*)addr) -/* Bitmap functions for the minix filesystem. */ - -#define minix_test_and_set_bit(nr,addr) \ - __test_and_set_le_bit(nr, (unsigned long *)addr) -#define minix_set_bit(nr,addr) \ - __set_le_bit(nr, (unsigned long *)addr) -#define minix_test_and_clear_bit(nr,addr) \ - __test_and_clear_le_bit(nr, (unsigned long *)addr) -#define minix_test_bit(nr,addr) \ - test_le_bit(nr, (unsigned long *)addr) - -#define minix_find_first_zero_bit(addr,size) \ - find_first_zero_le_bit((unsigned long *)addr, size) - #include #endif /* __KERNEL__ */ diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h index 1bd1e11..e537613 100644 --- a/arch/s390/include/asm/bitops.h +++ b/arch/s390/include/asm/bitops.h @@ -842,7 +842,6 @@ static inline int find_next_le_bit(void *vaddr, unsigned long size, #define ext2_clear_bit_atomic(lock, nr, addr) \ test_and_clear_le_bit((nr), (unsigned long *)(addr)) -#include #endif /* __KERNEL__ */ diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h index fc5cd5b..90fa3e4 100644 --- a/arch/sh/include/asm/bitops.h +++ b/arch/sh/include/asm/bitops.h @@ -96,7 +96,6 @@ static inline unsigned long ffz(unsigned long word) #include #include #include -#include #include #include #include diff --git a/arch/sparc/include/asm/bitops_32.h b/arch/sparc/include/asm/bitops_32.h index 75da6f8..25a6766 100644 --- a/arch/sparc/include/asm/bitops_32.h +++ b/arch/sparc/include/asm/bitops_32.h @@ -105,7 +105,6 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) #include #include #include -#include #endif /* __KERNEL__ */ diff --git a/arch/sparc/include/asm/bitops_64.h b/arch/sparc/include/asm/bitops_64.h index 66db28e..38e9aa1 100644 --- a/arch/sparc/include/asm/bitops_64.h +++ b/arch/sparc/include/asm/bitops_64.h @@ -96,8 +96,6 @@ static inline unsigned int __arch_hweight8(unsigned int w) #define ext2_clear_bit_atomic(lock,nr,addr) \ test_and_clear_bit((nr) ^ 0x38,(unsigned long *)(addr)) -#include - #endif /* __KERNEL__ */ #endif /* defined(_SPARC64_BITOPS_H) */ diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h index 5447add..132e6bb 100644 --- a/arch/tile/include/asm/bitops.h +++ b/arch/tile/include/asm/bitops.h @@ -123,6 +123,5 @@ static inline unsigned long __arch_hweight64(__u64 w) #include #include #include -#include #endif /* _ASM_TILE_BITOPS_H */ diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 3c95e07..69d5813 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -463,7 +463,5 @@ static inline int fls(int x) #define ext2_clear_bit_atomic(lock, nr, addr) \ test_and_clear_bit((nr), (unsigned long *)(addr)) -#include - #endif /* __KERNEL__ */ #endif /* _ASM_X86_BITOPS_H */ diff --git a/arch/xtensa/include/asm/bitops.h b/arch/xtensa/include/asm/bitops.h index a56b7b5..c8fac8d 100644 --- a/arch/xtensa/include/asm/bitops.h +++ b/arch/xtensa/include/asm/bitops.h @@ -125,7 +125,6 @@ static inline unsigned long __fls(unsigned long word) #include #include #include -#include #endif /* __KERNEL__ */ diff --git a/fs/minix/Kconfig b/fs/minix/Kconfig index 0fd7ca9..6624684 100644 --- a/fs/minix/Kconfig +++ b/fs/minix/Kconfig @@ -15,3 +15,11 @@ config MINIX_FS module will be called minix. Note that the file system of your root partition (the one containing the directory /) cannot be compiled as a module. + +config MINIX_FS_NATIVE_ENDIAN + def_bool MINIX_FS + depends on H8300 || M32R || MICROBLAZE || MIPS || S390 || SUPERH || SPARC || XTENSA || (M68K && !MMU) + +config MINIX_FS_BIG_ENDIAN_16BIT_INDEXED + def_bool MINIX_FS + depends on M68K && MMU diff --git a/fs/minix/minix.h b/fs/minix/minix.h index 407b1c8..9dfd62c 100644 --- a/fs/minix/minix.h +++ b/fs/minix/minix.h @@ -88,4 +88,83 @@ static inline struct minix_inode_info *minix_i(struct inode *inode) return list_entry(inode, struct minix_inode_info, vfs_inode); } +#if defined(CONFIG_MINIX_FS_NATIVE_ENDIAN) && \ + defined(CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED) + +#error Minix file system byte order broken + +#elif defined(CONFIG_MINIX_FS_NATIVE_ENDIAN) + +/* + * big-endian 32 or 64 bit indexed bitmaps on big-endian system or + * little-endian bitmaps on little-endian system + */ + +#define minix_test_and_set_bit(nr, addr) \ + __test_and_set_bit((nr), (unsigned long *)(addr)) +#define minix_set_bit(nr, addr) \ + __set_bit((nr), (unsigned long *)(addr)) +#define minix_test_and_clear_bit(nr, addr) \ + __test_and_clear_bit((nr), (unsigned long *)(addr)) +#define minix_test_bit(nr, addr) \ + test_bit((nr), (unsigned long *)(addr)) +#define minix_find_first_zero_bit(addr, size) \ + find_first_zero_bit((unsigned long *)(addr), (size)) + +#elif defined(CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED) + +/* + * big-endian 16bit indexed bitmaps + */ + +static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size) +{ + const unsigned short *p = vaddr, *addr = vaddr; + unsigned short num; + + if (!size) + return 0; + + size = (size >> 4) + ((size & 15) > 0); + while (*p++ == 0xffff) { + if (--size == 0) + return (p - addr) << 4; + } + + num = *--p; + return ((p - addr) << 4) + ffz(num); +} + +#define minix_test_and_set_bit(nr, addr) \ + __test_and_set_bit((nr) ^ 16, (unsigned long *)(addr)) +#define minix_set_bit(nr, addr) \ + __set_bit((nr) ^ 16, (unsigned long *)(addr)) +#define minix_test_and_clear_bit(nr, addr) \ + __test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr)) + +static inline int minix_test_bit(int nr, const void *vaddr) +{ + const unsigned short *p = vaddr; + return (p[nr >> 4] & (1U << (nr & 15))) != 0; +} + +#else + +/* + * little-endian bitmaps + */ + +#define minix_test_and_set_bit(nr, addr) \ + __test_and_set_le_bit((nr), (unsigned long *)(addr)) +#define minix_set_bit(nr, addr) \ + __set_le_bit((nr), (unsigned long *)(addr)) +#define minix_test_and_clear_bit(nr, addr) \ + __test_and_clear_le_bit((nr), (unsigned long *)(addr)) +#define minix_test_bit(nr, addr) \ + test_le_bit((nr), (unsigned long *)(addr)) +#define minix_find_first_zero_bit(addr, size) \ + find_first_zero_le_bit((unsigned long *)(addr), (size)) + +#endif + #endif /* FS_MINIX_H */ diff --git a/include/asm-generic/bitops.h b/include/asm-generic/bitops.h index dd7c014..280ca7a 100644 --- a/include/asm-generic/bitops.h +++ b/include/asm-generic/bitops.h @@ -40,6 +40,5 @@ #include #include #include -#include #endif /* __ASM_GENERIC_BITOPS_H */ diff --git a/include/asm-generic/bitops/minix-le.h b/include/asm-generic/bitops/minix-le.h deleted file mode 100644 index f366cfa..0000000 --- a/include/asm-generic/bitops/minix-le.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _ASM_GENERIC_BITOPS_MINIX_LE_H_ -#define _ASM_GENERIC_BITOPS_MINIX_LE_H_ - -#define minix_test_and_set_bit(nr,addr) \ - __test_and_set_le_bit((nr), (unsigned long *)(addr)) -#define minix_set_bit(nr,addr) \ - __set_le_bit((nr), (unsigned long *)(addr)) -#define minix_test_and_clear_bit(nr,addr) \ - __test_and_clear_le_bit((nr), (unsigned long *)(addr)) -#define minix_test_bit(nr,addr) \ - test_le_bit((nr), (unsigned long *)(addr)) -#define minix_find_first_zero_bit(addr,size) \ - find_first_zero_le_bit((unsigned long *)(addr), (size)) - -#endif /* _ASM_GENERIC_BITOPS_MINIX_LE_H_ */ diff --git a/include/asm-generic/bitops/minix.h b/include/asm-generic/bitops/minix.h deleted file mode 100644 index 91f42e8..0000000 --- a/include/asm-generic/bitops/minix.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _ASM_GENERIC_BITOPS_MINIX_H_ -#define _ASM_GENERIC_BITOPS_MINIX_H_ - -#define minix_test_and_set_bit(nr,addr) \ - __test_and_set_bit((nr),(unsigned long *)(addr)) -#define minix_set_bit(nr,addr) \ - __set_bit((nr),(unsigned long *)(addr)) -#define minix_test_and_clear_bit(nr,addr) \ - __test_and_clear_bit((nr),(unsigned long *)(addr)) -#define minix_test_bit(nr,addr) \ - test_bit((nr),(unsigned long *)(addr)) -#define minix_find_first_zero_bit(addr,size) \ - find_first_zero_bit((unsigned long *)(addr),(size)) - -#endif /* _ASM_GENERIC_BITOPS_MINIX_H_ */ -- 1.7.3.2 From wg@grandegger.com Tue Nov 23 16:00:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:00:30 +0100 (CET) Received: from mail-out.m-online.net ([212.18.0.10]:40970 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491914Ab0KWPAW (ORCPT ); Tue, 23 Nov 2010 16:00:22 +0100 Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 1CCAE186DECA; Tue, 23 Nov 2010 16:00:20 +0100 (CET) X-Auth-Info: tAqK5jgpP1sZqrDOl7Xf7VkI4rmaPnN3sPn2j2EbyJU= Received: from lancy.mylan.de (p4FF05130.dip.t-dialin.net [79.240.81.48]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 77D191C001E1; Tue, 23 Nov 2010 16:00:20 +0100 (CET) Message-ID: <4CEBD751.7090807@grandegger.com> Date: Tue, 23 Nov 2010 16:01:37 +0100 From: Wolfgang Grandegger User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100907 Fedora/3.0.7-1.fc12 Thunderbird/3.0.7 MIME-Version: 1.0 To: Florian Fainelli CC: Linux-MIPS , Netdev@vger.kernel.org Subject: Re: alchemy/gpr: au1000_eth regression with v2.6.37rc2 References: <4CE58593.50509@grandegger.com> <201011182330.08488.florian@openwrt.org> <4CE65199.7030007@grandegger.com> <201011191146.01454.florian@openwrt.org> In-Reply-To: <201011191146.01454.florian@openwrt.org> X-Enigmail-Version: 1.0.1 Content-Type: multipart/mixed; boundary="------------080703020109020809040101" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28463 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------080703020109020809040101 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Hi Florian, On 11/19/2010 11:46 AM, Florian Fainelli wrote: > Hello Wolfgang, > > On Friday 19 November 2010 11:29:45 Wolfgang Grandegger wrote: >> Hello Florian, >> >> On 11/18/2010 11:30 PM, Florian Fainelli wrote: >>> Hello Wolfgang, >>> >>> Le Thursday 18 November 2010 20:59:15, Wolfgang Grandegger a écrit : >>>> Hello, >>>> >>>> I just realized that the v2.6.37-rc2 kernel does not boot any more on >>>> the Alchemy GPR board. It works fine with v2.6.36. It hangs in the >>>> probe function of the au1000_eth driver when probing the second >>>> >>>> ethernet port (eth1): >>>> au1000_eth_mii: probed >>>> au1000-eth au1000-eth.0: (unregistered net_device): attached PHY >>>> driver >>>> >>>> [Generic PHY] (mii_bus:phy_addr=0:00, irq=-1) au1000-eth au1000-eth.0: >>>> eth0: Au1xx0 Ethernet found at 0x10500000, irq 35 au1000_eth: au1000_eth >>>> version 1.7 Pete Popov ... hangs ... >>>> >>>> Similar messages should follow for eth1. I narrowed down (bisect'ed) the >>>> >>>> problem to commit: >>>> commit d0e7cb5d401695809ba8c980124ab1d8c66efc8b >>>> Author: Florian Fainelli >>>> Date: Wed Sep 8 11:15:13 2010 +0000 >>>> >>>> au1000-eth: remove volatiles, switch to I/O accessors >>>> >>>> Remove all the volatile keywords where they were used, switch to >>>> using >>>> >>>> the proper readl/writel accessors. >>>> >>>> Signed-off-by: Florian Fainelli >>>> Signed-off-by: David S. Miller >>>> >>>> The kernel actually hangs when accessing "&aup->mac->mii_control" in >>>> au1000_mdio_read(), but only for eth1. Any idea what does go wrong? >>> >>> I do not understand so far while it hangs only for eth1. My device only >>> has one ethernet MAC, so I could not notice the problem. Looking at this >>> close, there are a couple of u32 const* usages in >>> au1000_mdio_{read,write} which are looking wrong to me now. Can you try >>> to remove these? >> >> That did not help. > > I suspected it, but thanks for the confirmation. > >> >>>> In principle, I do not want to access the MII regs of the MAC because >>>> eth0 and eth1 are connected to switches. But that's not possible, even >>>> with "aup->phy_static_config=1" and "aup->phy_addr=0". >>> >>> If you think this is another issue, I will fix it in another patch. >> >> Accessing the MII registers of the MAC should not hang the system even >> if I do not need to. First I want to understand why. Looks like a wired >> optimizer issue. > > I definitively agree, furthermore since there is a timeout for read and write > operations. I will look at the assembly and see if I can see anything > different. The attached patch fixes the issue. It's caused by a simple porting error. I'm going to prepare a proper patch later today. Wolfgang. --------------080703020109020809040101 Content-Type: text/x-diff; name="au1000-eth-mac-enable.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="au1000-eth-mac-enable.patch" diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c index 43489f8..53eff9b 100644 --- a/drivers/net/au1000_eth.c +++ b/drivers/net/au1000_eth.c @@ -155,10 +155,10 @@ static void au1000_enable_mac(struct net_device *dev, int force_reset) spin_lock_irqsave(&aup->lock, flags); if (force_reset || (!aup->mac_enabled)) { - writel(MAC_EN_CLOCK_ENABLE, &aup->enable); + writel(MAC_EN_CLOCK_ENABLE, aup->enable); au_sync_delay(2); writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 - | MAC_EN_CLOCK_ENABLE), &aup->enable); + | MAC_EN_CLOCK_ENABLE), aup->enable); au_sync_delay(2); aup->mac_enabled = 1; @@ -503,9 +503,9 @@ static void au1000_reset_mac_unlocked(struct net_device *dev) au1000_hard_stop(dev); - writel(MAC_EN_CLOCK_ENABLE, &aup->enable); + writel(MAC_EN_CLOCK_ENABLE, aup->enable); au_sync_delay(2); - writel(0, &aup->enable); + writel(0, aup->enable); au_sync_delay(2); aup->tx_full = 0; @@ -1119,7 +1119,7 @@ static int __devinit au1000_probe(struct platform_device *pdev) /* set a random MAC now in case platform_data doesn't provide one */ random_ether_addr(dev->dev_addr); - writel(0, &aup->enable); + writel(0, aup->enable); aup->mac_enabled = 0; pd = pdev->dev.platform_data; --------------080703020109020809040101-- From juhosg@openwrt.org Tue Nov 23 16:06:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:06:59 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43882 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491925Ab0KWPGz (ORCPT ); Tue, 23 Nov 2010 16:06:55 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 26BD741C001; Tue, 23 Nov 2010 16:06:50 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id A09731F0001; Tue, 23 Nov 2010 16:06:49 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, kaloz@openwrt.org, "Luis R. Rodriguez" , Cliff Holden , Gabor Juhos Subject: [PATCH 00/18] MIPS: initial support for the Atheros AR71XX/AR724X/AR913X SoCs Date: Tue, 23 Nov 2010 16:06:22 +0100 Message-Id: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 X-VBMS: A14B1AE5A1A | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28464 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch set contains initial support for the Atheros AR71XX/AR724X/AR913X SoCs. Gabor Juhos (18): MIPS: add initial support for the Atheros AR71XX/AR724X/AR931X SoCs MIPS: ath79: add GPIOLIB support MIPS: add generic support for multiple machines within a single kernel MIPS: ath79: utilize the MIPS multi-machine support MIPS: ath79: add initial support for the Atheros PB44 reference board MIPS: ath79: add common GPIO LEDs device watchdog: add driver for the Atheros AR71XX/AR724X/AR913X SoCs MIPS: ath79: add common watchdog device input: add input driver for polled GPIO buttons MIPS: ath79: add common GPIO buttons device spi: add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs MIPS: ath79: add common SPI controller device USB: ehci: add workaround for Synopsys HC bug USB: ehci: add bus glue for the Atheros AR71XX/AR724X/AR913X SoCs USB: ohci: add bus glue for the Atheros AR71XX/AR7240 SoCs MIPS: ath79: add common USB Host Controller device MIPS: ath79: add initial support for the Atheros AP81 reference board MIPS: ath79: add common WMAC device for AR913X based boards arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 20 ++ arch/mips/ath79/Kconfig | 60 ++++ arch/mips/ath79/Makefile | 29 ++ arch/mips/ath79/Platform | 7 + arch/mips/ath79/common.c | 113 ++++++++ arch/mips/ath79/common.h | 67 +++++ arch/mips/ath79/dev-ar913x-wmac.c | 60 ++++ arch/mips/ath79/dev-ar913x-wmac.h | 17 ++ arch/mips/ath79/dev-common.c | 69 +++++ arch/mips/ath79/dev-common.h | 18 ++ arch/mips/ath79/dev-gpio-buttons.c | 58 ++++ arch/mips/ath79/dev-gpio-buttons.h | 23 ++ arch/mips/ath79/dev-leds-gpio.c | 56 ++++ arch/mips/ath79/dev-leds-gpio.h | 21 ++ arch/mips/ath79/dev-spi.c | 38 +++ arch/mips/ath79/dev-spi.h | 22 ++ arch/mips/ath79/dev-usb.c | 192 +++++++++++++ arch/mips/ath79/dev-usb.h | 17 ++ arch/mips/ath79/early_printk.c | 36 +++ arch/mips/ath79/gpio.c | 196 +++++++++++++ arch/mips/ath79/irq.c | 187 +++++++++++++ arch/mips/ath79/mach-ap81.c | 98 +++++++ arch/mips/ath79/mach-pb44.c | 119 ++++++++ arch/mips/ath79/machtypes.h | 23 ++ arch/mips/ath79/prom.c | 57 ++++ arch/mips/ath79/setup.c | 279 +++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 248 +++++++++++++++++ arch/mips/include/asm/mach-ath79/ath79.h | 50 ++++ .../include/asm/mach-ath79/ath79_ehci_platform.h | 18 ++ .../include/asm/mach-ath79/ath79_spi_platform.h | 19 ++ .../include/asm/mach-ath79/cpu-feature-overrides.h | 56 ++++ arch/mips/include/asm/mach-ath79/gpio.h | 26 ++ arch/mips/include/asm/mach-ath79/irq.h | 36 +++ .../include/asm/mach-ath79/kernel-entry-init.h | 32 +++ arch/mips/include/asm/mach-ath79/war.h | 25 ++ arch/mips/include/asm/mips_machine.h | 54 ++++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/mips_machine.c | 86 ++++++ arch/mips/kernel/proc.c | 7 +- arch/mips/kernel/vmlinux.lds.S | 7 + drivers/input/misc/Kconfig | 16 + drivers/input/misc/Makefile | 1 + drivers/input/misc/gpio_buttons.c | 232 ++++++++++++++++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 290 +++++++++++++++++++ drivers/usb/host/Kconfig | 16 + drivers/usb/host/ehci-ath79.c | 176 ++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-q.c | 3 + drivers/usb/host/ehci.h | 1 + drivers/usb/host/ohci-ath79.c | 162 +++++++++++ drivers/usb/host/ohci-hcd.c | 5 + drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ath79_wdt.c | 293 ++++++++++++++++++++ include/linux/gpio_buttons.h | 33 +++ 58 files changed, 3798 insertions(+), 1 deletions(-) create mode 100644 arch/mips/ath79/Kconfig create mode 100644 arch/mips/ath79/Makefile create mode 100644 arch/mips/ath79/Platform create mode 100644 arch/mips/ath79/common.c create mode 100644 arch/mips/ath79/common.h create mode 100644 arch/mips/ath79/dev-ar913x-wmac.c create mode 100644 arch/mips/ath79/dev-ar913x-wmac.h create mode 100644 arch/mips/ath79/dev-common.c create mode 100644 arch/mips/ath79/dev-common.h create mode 100644 arch/mips/ath79/dev-gpio-buttons.c create mode 100644 arch/mips/ath79/dev-gpio-buttons.h create mode 100644 arch/mips/ath79/dev-leds-gpio.c create mode 100644 arch/mips/ath79/dev-leds-gpio.h create mode 100644 arch/mips/ath79/dev-spi.c create mode 100644 arch/mips/ath79/dev-spi.h create mode 100644 arch/mips/ath79/dev-usb.c create mode 100644 arch/mips/ath79/dev-usb.h create mode 100644 arch/mips/ath79/early_printk.c create mode 100644 arch/mips/ath79/gpio.c create mode 100644 arch/mips/ath79/irq.c create mode 100644 arch/mips/ath79/mach-ap81.c create mode 100644 arch/mips/ath79/mach-pb44.c create mode 100644 arch/mips/ath79/machtypes.h create mode 100644 arch/mips/ath79/prom.c create mode 100644 arch/mips/ath79/setup.c create mode 100644 arch/mips/include/asm/mach-ath79/ar71xx_regs.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79_ehci_platform.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h create mode 100644 arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-ath79/gpio.h create mode 100644 arch/mips/include/asm/mach-ath79/irq.h create mode 100644 arch/mips/include/asm/mach-ath79/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-ath79/war.h create mode 100644 arch/mips/include/asm/mips_machine.h create mode 100644 arch/mips/kernel/mips_machine.c create mode 100644 drivers/input/misc/gpio_buttons.c create mode 100644 drivers/spi/ath79_spi.c create mode 100644 drivers/usb/host/ehci-ath79.c create mode 100644 drivers/usb/host/ohci-ath79.c create mode 100644 drivers/watchdog/ath79_wdt.c create mode 100644 include/linux/gpio_buttons.h -- 1.7.2.1 From juhosg@openwrt.org Tue Nov 23 16:07:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:07:32 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43890 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491930Ab0KWPG4 (ORCPT ); Tue, 23 Nov 2010 16:06:56 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 8C33145C003; Tue, 23 Nov 2010 16:06:51 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id EDC1B1F0001; Tue, 23 Nov 2010 16:06:49 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, kaloz@openwrt.org, "Luis R. Rodriguez" , Cliff Holden , Gabor Juhos Subject: [PATCH 01/18] MIPS: add initial support for the Atheros AR71XX/AR724X/AR931X SoCs Date: Tue, 23 Nov 2010 16:06:23 +0100 Message-Id: <1290524800-21419-2-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> References: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> X-VBMS: A14B1E1BF40 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28465 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- Changes since RFC: - the ATH79_DEV_UART Kconfig option is removed, and the URT platform code has been moved into dev-common[ch] arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 15 ++ arch/mips/ath79/Kconfig | 12 + arch/mips/ath79/Makefile | 18 ++ arch/mips/ath79/Platform | 7 + arch/mips/ath79/common.c | 113 +++++++++ arch/mips/ath79/common.h | 62 +++++ arch/mips/ath79/dev-common.c | 59 +++++ arch/mips/ath79/dev-common.h | 17 ++ arch/mips/ath79/early_printk.c | 36 +++ arch/mips/ath79/irq.c | 187 ++++++++++++++ arch/mips/ath79/prom.c | 57 +++++ arch/mips/ath79/setup.c | 263 ++++++++++++++++++++ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 207 +++++++++++++++ arch/mips/include/asm/mach-ath79/ath79.h | 50 ++++ .../include/asm/mach-ath79/cpu-feature-overrides.h | 56 ++++ arch/mips/include/asm/mach-ath79/irq.h | 36 +++ .../include/asm/mach-ath79/kernel-entry-init.h | 32 +++ arch/mips/include/asm/mach-ath79/war.h | 25 ++ 19 files changed, 1253 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/Kconfig create mode 100644 arch/mips/ath79/Makefile create mode 100644 arch/mips/ath79/Platform create mode 100644 arch/mips/ath79/common.c create mode 100644 arch/mips/ath79/common.h create mode 100644 arch/mips/ath79/dev-common.c create mode 100644 arch/mips/ath79/dev-common.h create mode 100644 arch/mips/ath79/early_printk.c create mode 100644 arch/mips/ath79/irq.c create mode 100644 arch/mips/ath79/prom.c create mode 100644 arch/mips/ath79/setup.c create mode 100644 arch/mips/include/asm/mach-ath79/ar71xx_regs.h create mode 100644 arch/mips/include/asm/mach-ath79/ath79.h create mode 100644 arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-ath79/irq.h create mode 100644 arch/mips/include/asm/mach-ath79/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-ath79/war.h diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 78439b8..7ff9b54 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -2,6 +2,7 @@ platforms += alchemy platforms += ar7 +platforms += ath79 platforms += bcm47xx platforms += bcm63xx platforms += cavium-octeon diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7fc6bd1..50d4f5d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -65,6 +65,20 @@ config AR7 Support for the Texas Instruments AR7 System-on-a-Chip family: TNETD7100, 7200 and 7300. +config ATH79 + bool "Atheros AR71XX/AR724X/AR913X based boards" + select BOOT_RAW + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + Support for the Atheros AR71XX/AR724X/AR913X SoCs. + config BCM47XX bool "Broadcom BCM47XX based boards" select CEVT_R4K @@ -717,6 +731,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD endchoice source "arch/mips/alchemy/Kconfig" +source "arch/mips/ath79/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig new file mode 100644 index 0000000..50b9334 --- /dev/null +++ b/arch/mips/ath79/Kconfig @@ -0,0 +1,12 @@ +if ATH79 + +config SOC_AR71XX + def_bool n + +config SOC_AR724X + def_bool n + +config SOC_AR913X + def_bool n + +endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile new file mode 100644 index 0000000..b4ec9c2 --- /dev/null +++ b/arch/mips/ath79/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the Atheros AR71XX/AR724X/AR913X specific parts of the kernel +# +# Copyright (C) 2008-2010 Gabor Juhos +# Copyright (C) 2008 Imre Kaloz +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := prom.o setup.o irq.o common.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +# +# Devices +# +obj-y += dev-common.o diff --git a/arch/mips/ath79/Platform b/arch/mips/ath79/Platform new file mode 100644 index 0000000..2bd6636 --- /dev/null +++ b/arch/mips/ath79/Platform @@ -0,0 +1,7 @@ +# +# Atheros AR71xx/AR724x/AR913x +# + +platform-$(CONFIG_ATH79) += ath79/ +cflags-$(CONFIG_ATH79) += -I$(srctree)/arch/mips/include/asm/mach-ath79 +load-$(CONFIG_ATH79) = 0xffffffff80060000 diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c new file mode 100644 index 0000000..b6eaaf5 --- /dev/null +++ b/arch/mips/ath79/common.c @@ -0,0 +1,113 @@ +/* + * Atheros AR71XX/AR724X/AR913X common routines + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include "common.h" + +static DEFINE_SPINLOCK(ath79_device_lock); + +u32 ath79_cpu_freq; +EXPORT_SYMBOL_GPL(ath79_cpu_freq); + +u32 ath79_ahb_freq; +EXPORT_SYMBOL_GPL(ath79_ahb_freq); + +u32 ath79_ddr_freq; +EXPORT_SYMBOL_GPL(ath79_ddr_freq); + +enum ath79_soc_type ath79_soc; + +void __iomem *ath79_pll_base; +void __iomem *ath79_reset_base; +EXPORT_SYMBOL_GPL(ath79_reset_base); +void __iomem *ath79_ddr_base; + +void ath79_ddr_wb_flush(u32 reg) +{ + void __iomem *flush_reg = ath79_ddr_base + reg; + + /* Flush the DDR write buffer. */ + __raw_writel(0x1, flush_reg); + while (__raw_readl(flush_reg) & 0x1) + ; + + /* It must be run twice. */ + __raw_writel(0x1, flush_reg); + while (__raw_readl(flush_reg) & 0x1) + ; +} +EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush); + +void ath79_device_stop(u32 mask) +{ + unsigned long flags; + u32 mask_inv; + u32 t; + + if (soc_is_ar71xx()) { + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR71XX_RESET_REG_RESET_MODULE); + ath79_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else if (soc_is_ar724x()) { + mask_inv = mask & AR724X_RESET_OHCI_DLL; + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE); + t |= mask; + t &= ~mask_inv; + ath79_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else if (soc_is_ar913x()) { + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR913X_RESET_REG_RESET_MODULE); + ath79_reset_wr(AR913X_RESET_REG_RESET_MODULE, t | mask); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else { + BUG(); + } +} +EXPORT_SYMBOL_GPL(ath79_device_stop); + +void ath79_device_start(u32 mask) +{ + unsigned long flags; + u32 mask_inv; + u32 t; + + if (soc_is_ar71xx()) { + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR71XX_RESET_REG_RESET_MODULE); + ath79_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else if (soc_is_ar724x()) { + mask_inv = mask & AR724X_RESET_OHCI_DLL; + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE); + t &= ~mask; + t |= mask_inv; + ath79_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else if (soc_is_ar913x()) { + spin_lock_irqsave(&ath79_device_lock, flags); + t = ath79_reset_rr(AR913X_RESET_REG_RESET_MODULE); + ath79_reset_wr(AR913X_RESET_REG_RESET_MODULE, t & ~mask); + spin_unlock_irqrestore(&ath79_device_lock, flags); + } else { + BUG(); + } +} +EXPORT_SYMBOL_GPL(ath79_device_start); diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h new file mode 100644 index 0000000..62d7503 --- /dev/null +++ b/arch/mips/ath79/common.h @@ -0,0 +1,62 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ATH79_COMMON_H +#define __ATH79_COMMON_H + +#include +#include +#include +#include + +#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) +#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) + +extern void __iomem *ath79_ddr_base; +void ath79_ddr_wb_flush(unsigned int reg); + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132 +}; + +extern enum ath79_soc_type ath79_soc; + +static inline int soc_is_ar71xx(void) +{ + return (ath79_soc == ATH79_SOC_AR7130 || + ath79_soc == ATH79_SOC_AR7141 || + ath79_soc == ATH79_SOC_AR7161); +} + +static inline int soc_is_ar724x(void) +{ + return (ath79_soc == ATH79_SOC_AR7240 || + ath79_soc == ATH79_SOC_AR7241 || + ath79_soc == ATH79_SOC_AR7242); +} + +static inline int soc_is_ar913x(void) +{ + return (ath79_soc == ATH79_SOC_AR9130 || + ath79_soc == ATH79_SOC_AR9132); +} + +#endif /* __ATH79_COMMON_H */ diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c new file mode 100644 index 0000000..897522c --- /dev/null +++ b/arch/mips/ath79/dev-common.c @@ -0,0 +1,59 @@ +/* + * Atheros AR71XX/AR724X/AR913X common devices + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include "common.h" +#include "dev-common.h" + +static struct resource ath79_uart_resources[] = { + { + .start = AR71XX_UART_BASE, + .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) +static struct plat_serial8250_port ath79_uart_data[] = { + { + .mapbase = AR71XX_UART_BASE, + .irq = ATH79_MISC_IRQ_UART, + .flags = AR71XX_UART_FLAGS, + .iotype = UPIO_MEM32, + .regshift = 2, + }, { + /* terminating entry */ + } +}; + +static struct platform_device ath79_uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .resource = ath79_uart_resources, + .num_resources = ARRAY_SIZE(ath79_uart_resources), + .dev = { + .platform_data = ath79_uart_data + }, +}; + +void __init ath79_register_uart(void) +{ + ath79_uart_data[0].uartclk = ath79_ahb_freq; + platform_device_register(&ath79_uart_device); +} diff --git a/arch/mips/ath79/dev-common.h b/arch/mips/ath79/dev-common.h new file mode 100644 index 0000000..1cec894 --- /dev/null +++ b/arch/mips/ath79/dev-common.h @@ -0,0 +1,17 @@ +/* + * Atheros AR71XX/AR724X/AR913X common devices + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_COMMON_H +#define _ATH79_DEV_COMMON_H + +void ath79_register_uart(void) __init; + +#endif /* _ATH79_DEV_COMMON_H */ diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c new file mode 100644 index 0000000..7499b0e --- /dev/null +++ b/arch/mips/ath79/early_printk.c @@ -0,0 +1,36 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC early printk support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +static inline void prom_wait_thre(void __iomem *base) +{ + u32 lsr; + + do { + lsr = __raw_readl(base + UART_LSR * 4); + if (lsr & UART_LSR_THRE) + break; + } while (1); +} + +void prom_putchar(unsigned char ch) +{ + void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); + + prom_wait_thre(base); + __raw_writel(ch, base + UART_TX * 4); + prom_wait_thre(base); +} diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c new file mode 100644 index 0000000..1bf7f71 --- /dev/null +++ b/arch/mips/ath79/irq.c @@ -0,0 +1,187 @@ +/* + * Atheros AR71xx/AR724x/AR913x specific interrupt handling + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "common.h" + +static unsigned int ath79_ip2_flush_reg; +static unsigned int ath79_ip3_flush_reg; + +static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *base = ath79_reset_base; + u32 pending; + + pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + if (pending & MISC_INT_UART) + generic_handle_irq(ATH79_MISC_IRQ_UART); + + else if (pending & MISC_INT_DMA) + generic_handle_irq(ATH79_MISC_IRQ_DMA); + + else if (pending & MISC_INT_PERFC) + generic_handle_irq(ATH79_MISC_IRQ_PERFC); + + else if (pending & MISC_INT_TIMER) + generic_handle_irq(ATH79_MISC_IRQ_TIMER); + + else if (pending & MISC_INT_OHCI) + generic_handle_irq(ATH79_MISC_IRQ_OHCI); + + else if (pending & MISC_INT_ERROR) + generic_handle_irq(ATH79_MISC_IRQ_ERROR); + + else if (pending & MISC_INT_GPIO) + generic_handle_irq(ATH79_MISC_IRQ_GPIO); + + else if (pending & MISC_INT_WDOG) + generic_handle_irq(ATH79_MISC_IRQ_WDOG); + + else + spurious_interrupt(); +} + +static void ar71xx_misc_irq_unmask(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + +static void ar71xx_misc_irq_mask(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + +static void ar724x_misc_irq_ack(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); +} + +static struct irq_chip ath79_misc_irq_chip = { + .name = "MISC", + .unmask = ar71xx_misc_irq_unmask, + .mask = ar71xx_misc_irq_mask, +}; + +static void __init ath79_misc_irq_init(void) +{ + void __iomem *base = ath79_reset_base; + int i; + + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); + + if (soc_is_ar71xx() || soc_is_ar913x()) + ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; + else if (soc_is_ar724x()) + ath79_misc_irq_chip.ack = ar724x_misc_irq_ack; + else + BUG(); + + for (i = ATH79_MISC_IRQ_BASE; + i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { + irq_desc[i].status = IRQ_DISABLED; + set_irq_chip_and_handler(i, &ath79_misc_irq_chip, + handle_level_irq); + } + + set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(ATH79_CPU_IRQ_TIMER); + + else if (pending & STATUSF_IP2) { + ath79_ddr_wb_flush(ath79_ip2_flush_reg); + do_IRQ(ATH79_CPU_IRQ_IP2); + } + + else if (pending & STATUSF_IP4) + do_IRQ(ATH79_CPU_IRQ_GE0); + + else if (pending & STATUSF_IP5) + do_IRQ(ATH79_CPU_IRQ_GE1); + + else if (pending & STATUSF_IP3) { + ath79_ddr_wb_flush(ath79_ip3_flush_reg); + do_IRQ(ATH79_CPU_IRQ_USB); + } + + else if (pending & STATUSF_IP6) + do_IRQ(ATH79_CPU_IRQ_MISC); + + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + if (soc_is_ar71xx()) { + ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; + ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; + } else if (soc_is_ar724x()) { + ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; + ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; + } else if (soc_is_ar913x()) { + ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; + ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; + } else + BUG(); + + cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + mips_cpu_irq_init(); + ath79_misc_irq_init(); +} diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c new file mode 100644 index 0000000..e9cbd7c --- /dev/null +++ b/arch/mips/ath79/prom.c @@ -0,0 +1,57 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific prom routines + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "common.h" + +static inline int is_valid_ram_addr(void *addr) +{ + if (((u32) addr > KSEG0) && + ((u32) addr < (KSEG0 + ATH79_MEM_SIZE_MAX))) + return 1; + + if (((u32) addr > KSEG1) && + ((u32) addr < (KSEG1 + ATH79_MEM_SIZE_MAX))) + return 1; + + return 0; +} + +static __init void ath79_prom_init_cmdline(int argc, char **argv) +{ + int i; + + if (!is_valid_ram_addr(argv)) + return; + + for (i = 0; i < argc; i++) + if (is_valid_ram_addr(argv[i])) { + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); + } +} + +void __init prom_init(void) +{ + ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); +} + +void __init prom_free_prom_memory(void) +{ + /* We do not have to prom memory to free */ +} diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c new file mode 100644 index 0000000..ee620e1 --- /dev/null +++ b/arch/mips/ath79/setup.c @@ -0,0 +1,263 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific setup + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include /* for mips_hpt_frequency */ +#include /* for _machine_{restart,halt} */ + +#include +#include +#include "common.h" +#include "dev-common.h" + +#define ATH79_SYS_TYPE_LEN 64 + +#define AR71XX_BASE_FREQ 40000000 +#define AR724X_BASE_FREQ 5000000 +#define AR913X_BASE_FREQ 5000000 + +static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; + +static void ath79_restart(char *command) +{ + ath79_device_stop(AR71XX_RESET_FULL_CHIP); + for (;;) + if (cpu_wait) + cpu_wait(); +} + +static void ath79_halt(void) +{ + while (1) + cpu_wait(); +} + +static void __init ath79_detect_mem_size(void) +{ + unsigned long size; + + for (size = ATH79_MEM_SIZE_MIN; size < ATH79_MEM_SIZE_MAX; + size <<= 1) { + if (!memcmp(ath79_detect_mem_size, + ath79_detect_mem_size + size, 1024)) + break; + } + + add_memory_region(0, size, BOOT_MEM_RAM); +} + +static void __init ath79_detect_sys_type(void) +{ + char *chip = "????"; + u32 id; + u32 major; + u32 minor; + u32 rev = 0; + + id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + ath79_soc = ATH79_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + ath79_soc = ATH79_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + ath79_soc = ATH79_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + ath79_soc = ATH79_SOC_AR7240; + chip = "7240"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7241: + ath79_soc = ATH79_SOC_AR7241; + chip = "7241"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7242: + ath79_soc = ATH79_SOC_AR7242; + chip = "7242"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; + rev &= AR913X_REV_ID_REVISION_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + ath79_soc = ATH79_SOC_AR9130; + chip = "9130"; + break; + + case AR913X_REV_ID_MINOR_AR9132: + ath79_soc = ATH79_SOC_AR9132; + chip = "9132"; + break; + } + break; + + default: + panic("ath79: unknown SoC, id:0x%08x\n", id); + } + + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); +} + +static void __init ar71xx_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; + freq = div * AR71XX_BASE_FREQ; + + div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; + ath79_cpu_freq = freq / div; + + div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ar724x_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * AR724X_BASE_FREQ; + + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); + freq *= div; + + ath79_cpu_freq = freq; + + div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ar913x_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); + freq = div * AR913X_BASE_FREQ; + + ath79_cpu_freq = freq; + + div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; + ath79_ddr_freq = freq / div; + + div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_freq = ath79_cpu_freq / div; +} + +static void __init ath79_detect_sys_frequency(void) +{ + if (soc_is_ar71xx()) + ar71xx_detect_sys_frequency(); + else if (soc_is_ar724x()) + ar724x_detect_sys_frequency(); + else if (soc_is_ar913x()) + ar913x_detect_sys_frequency(); + else + BUG(); +} + +const char *get_system_type(void) +{ + return ath79_sys_type; +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(KSEG1); + + ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE); + ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, + AR71XX_PLL_SIZE); + + ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, + AR71XX_DDR_CTRL_SIZE); + + ath79_detect_sys_type(); + ath79_detect_mem_size(); + ath79_detect_sys_frequency(); + + pr_info("SoC: %s, CPU:%u.%03u MHz, DDR:%u.%03u MHz, AHB:%u.%03u MHz\n", + ath79_sys_type, + ath79_cpu_freq / 1000000, (ath79_cpu_freq / 1000) % 1000, + ath79_ddr_freq / 1000000, (ath79_ddr_freq / 1000) % 1000, + ath79_ahb_freq / 1000000, (ath79_ahb_freq / 1000) % 1000); + + _machine_restart = ath79_restart; + _machine_halt = ath79_halt; + pm_power_off = ath79_halt; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = ath79_cpu_freq / 2; +} + +static int __init ath79_setup(void) +{ + ath79_register_uart(); + return 0; +} + +arch_initcall(ath79_setup); diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h new file mode 100644 index 0000000..5a9e5e1 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -0,0 +1,207 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#include +#include +#include +#include + +#define AR71XX_APB_BASE 0x18000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_OHCI_DLL BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +#endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h new file mode 100644 index 0000000..14248c9 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -0,0 +1,50 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include +#include + +extern u32 ath79_ahb_freq; +extern u32 ath79_cpu_freq; +extern u32 ath79_ddr_freq; + +extern void __iomem *ath79_pll_base; +extern void __iomem *ath79_reset_base; + +static inline void ath79_pll_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ath79_pll_base + reg); +} + +static inline u32 ath79_pll_rr(unsigned reg) +{ + return __raw_readl(ath79_pll_base + reg); +} + +static inline void ath79_reset_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ath79_reset_base + reg); +} + +static inline u32 ath79_reset_rr(unsigned reg) +{ + return __raw_readl(ath79_reset_base + reg); +} + +void ath79_device_stop(u32 mask); +void ath79_device_start(u32 mask); + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h new file mode 100644 index 0000000..4476fa0 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific CPU feature overrides + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h new file mode 100644 index 0000000..189bc6e --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_ATH79_IRQ_H +#define __ASM_MACH_ATH79_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 16 + +#define ATH79_MISC_IRQ_BASE 8 +#define ATH79_MISC_IRQ_COUNT 8 + +#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) +#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) +#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) +#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) +#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) +#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7) + +#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) +#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) +#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) +#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3) +#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4) +#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) +#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) +#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) + +#include_next + +#endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h new file mode 100644 index 0000000..d8d046b --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h @@ -0,0 +1,32 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific kernel entry setup + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ATH79_KERNEL_ENTRY_H +#define __ASM_MACH_ATH79_KERNEL_ENTRY_H + + /* + * Some bootloaders set the 'Kseg0 coherency algorithm' to + * 'Cacheable, noncoherent, write-through, no write allocate' + * and this cause performance issues. Let's go and change it to + * 'Cacheable, noncoherent, write-back, write allocate' + */ + .macro kernel_entry_setup + mfc0 t0, CP0_CONFIG + li t1, ~CONF_CM_CMASK + and t0, t1 + ori t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + nop + .endm + + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_ATH79_KERNEL_ENTRY_H */ diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h new file mode 100644 index 0000000..323d9f1 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_ATH79_WAR_H +#define __ASM_MACH_ATH79_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_ATH79_WAR_H */ -- 1.7.2.1 From juhosg@openwrt.org Tue Nov 23 16:07:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:08:02 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43894 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491931Ab0KWPG4 (ORCPT ); Tue, 23 Nov 2010 16:06:56 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id AF2CD4DC006; Tue, 23 Nov 2010 16:06:51 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 2397A1F0001; Tue, 23 Nov 2010 16:06:51 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, kaloz@openwrt.org, "Luis R. Rodriguez" , Cliff Holden , Gabor Juhos , David Brownell Subject: [PATCH 02/18] MIPS: ath79: add GPIOLIB support Date: Tue, 23 Nov 2010 16:06:24 +0100 Message-Id: <1290524800-21419-3-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> References: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> X-VBMS: A14B2174A37 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28466 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch implements generic GPIO routines for the built-in GPIO controllers of the Atheros AR71XX/AR724X/AR913X SoCs. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz Cc: David Brownell --- Changes since RFC: --- arch/mips/Kconfig | 1 + arch/mips/ath79/Makefile | 2 +- arch/mips/ath79/common.h | 5 + arch/mips/ath79/gpio.c | 196 ++++++++++++++++++++++++ arch/mips/ath79/setup.c | 2 +- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 21 +++ arch/mips/include/asm/mach-ath79/gpio.h | 26 +++ 7 files changed, 251 insertions(+), 2 deletions(-) create mode 100644 arch/mips/ath79/gpio.c create mode 100644 arch/mips/include/asm/mach-ath79/gpio.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 50d4f5d..ec69df5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -67,6 +67,7 @@ config AR7 config ATH79 bool "Atheros AR71XX/AR724X/AR913X based boards" + select ARCH_REQUIRE_GPIOLIB select BOOT_RAW select CEVT_R4K select CSRC_R4K diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index b4ec9c2..facbb70 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -8,7 +8,7 @@ # under the terms of the GNU General Public License version 2 as published # by the Free Software Foundation. -obj-y := prom.o setup.o irq.o common.o +obj-y := prom.o setup.o irq.o common.o gpio.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h index 62d7503..041ca7e 100644 --- a/arch/mips/ath79/common.h +++ b/arch/mips/ath79/common.h @@ -59,4 +59,9 @@ static inline int soc_is_ar913x(void) ath79_soc == ATH79_SOC_AR9132); } +void ath79_gpio_function_enable(u32 mask); +void ath79_gpio_function_disable(u32 mask); +void ath79_gpio_function_setup(u32 set, u32 clear); +void ath79_gpio_init(void) __init; + #endif /* __ATH79_COMMON_H */ diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c new file mode 100644 index 0000000..fd88c64 --- /dev/null +++ b/arch/mips/ath79/gpio.c @@ -0,0 +1,196 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "common.h" + +static void __iomem *ath79_gpio_base; +static unsigned long ath79_gpio_count; +static DEFINE_SPINLOCK(ath79_gpio_lock); + +static void __ath79_gpio_set_value(unsigned gpio, int value) +{ + void __iomem *base = ath79_gpio_base; + + if (value) + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); +} + +static int __ath79_gpio_get_value(unsigned gpio) +{ + return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1; +} + +static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + return __ath79_gpio_get_value(offset); +} + +static void ath79_gpio_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + __ath79_gpio_set_value(offset, value); +} + +static int ath79_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static int ath79_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + if (value) + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, + .set = ath79_gpio_set_value, + .direction_input = ath79_gpio_direction_input, + .direction_output = ath79_gpio_direction_output, + .base = 0, +}; + +void ath79_gpio_function_enable(u32 mask) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void ath79_gpio_function_disable(u32 mask) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void ath79_gpio_function_setup(u32 set, u32 clear) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void __init ath79_gpio_init(void) +{ + int err; + + if (soc_is_ar71xx()) + ath79_gpio_count = AR71XX_GPIO_COUNT; + else if (soc_is_ar724x()) + ath79_gpio_count = AR724X_GPIO_COUNT; + else if (soc_is_ar913x()) + ath79_gpio_count = AR913X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; + + err = gpiochip_add(&ath79_gpio_chip); + if (err) + panic("cannot add AR71xx GPIO chip, error=%d", err); +} + +int gpio_get_value(unsigned gpio) +{ + if (gpio < ath79_gpio_count) + return __ath79_gpio_get_value(gpio); + + return __gpio_get_value(gpio); +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int value) +{ + if (gpio < ath79_gpio_count) + __ath79_gpio_set_value(gpio, value); + else + __gpio_set_value(gpio, value); +} +EXPORT_SYMBOL(gpio_set_value); + +int gpio_to_irq(unsigned gpio) +{ + /* FIXME */ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int irq_to_gpio(unsigned irq) +{ + /* FIXME */ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index ee620e1..dbbf050 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -230,7 +230,6 @@ void __init plat_mem_setup(void) AR71XX_RESET_SIZE); ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); - ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE); @@ -256,6 +255,7 @@ void __init plat_time_init(void) static int __init ath79_setup(void) { + ath79_gpio_init(); ath79_register_uart(); return 0; } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 5a9e5e1..7f2933d 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -25,6 +25,8 @@ #define AR71XX_DDR_CTRL_SIZE 0x100 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR71XX_UART_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) #define AR71XX_PLL_SIZE 0x100 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) @@ -204,4 +206,23 @@ #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ AR71XX_SPI_IOC_CS2) +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +#define AR71XX_GPIO_COUNT 16 +#define AR724X_GPIO_COUNT 18 +#define AR913X_GPIO_COUNT 22 + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/arch/mips/include/asm/mach-ath79/gpio.h b/arch/mips/include/asm/mach-ath79/gpio.h new file mode 100644 index 0000000..60dcb62 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/gpio.h @@ -0,0 +1,26 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MACH_ATH79_GPIO_H +#define __ASM_MACH_ATH79_GPIO_H + +#define ARCH_NR_GPIOS 64 +#include + +int gpio_to_irq(unsigned gpio); +int irq_to_gpio(unsigned irq); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); + +#define gpio_cansleep __gpio_cansleep + +#endif /* __ASM_MACH_ATH79_GPIO_H */ -- 1.7.2.1 From juhosg@openwrt.org Tue Nov 23 16:08:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:08:25 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43903 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491932Ab0KWPG5 (ORCPT ); Tue, 23 Nov 2010 16:06:57 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id EE1E14DC009; Tue, 23 Nov 2010 16:06:51 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 7C6E51F0001; Tue, 23 Nov 2010 16:06:51 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, kaloz@openwrt.org, "Luis R. Rodriguez" , Cliff Holden , Gabor Juhos Subject: [PATCH 03/18] MIPS: add generic support for multiple machines within a single kernel Date: Tue, 23 Nov 2010 16:06:25 +0100 Message-Id: <1290524800-21419-4-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> References: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> X-VBMS: A14B2CC0BA0 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28467 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips This patch adds a generic solution to support multiple machines based on a given SoC within a single kernel image. It is implemented already for several other architectures but MIPS has no generic support for that yet. Signed-off-by: Gabor Juhos --- Changes since RFC: --- arch/mips/Kconfig | 3 + arch/mips/include/asm/mips_machine.h | 54 +++++++++++++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/mips_machine.c | 86 ++++++++++++++++++++++++++++++++++ arch/mips/kernel/proc.c | 7 ++- arch/mips/kernel/vmlinux.lds.S | 7 +++ 6 files changed, 157 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/mips_machine.h create mode 100644 arch/mips/kernel/mips_machine.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ec69df5..307c2e4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -899,6 +899,9 @@ config MIPS_DISABLE_OBSOLETE_IDE config SYNC_R4K bool +config MIPS_MACHINE + def_bool n + config NO_IOPORT def_bool n diff --git a/arch/mips/include/asm/mips_machine.h b/arch/mips/include/asm/mips_machine.h new file mode 100644 index 0000000..363bb35 --- /dev/null +++ b/arch/mips/include/asm/mips_machine.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MIPS_MACHINE_H +#define __ASM_MIPS_MACHINE_H + +#include +#include + +#include + +struct mips_machine { + unsigned long mach_type; + const char *mach_id; + const char *mach_name; + void (*mach_setup)(void); +}; + +#define MIPS_MACHINE(_type, _id, _name, _setup) \ +static const char machine_name_##_type[] __initconst \ + __aligned(1) = _name; \ +static const char machine_id_##_type[] __initconst \ + __aligned(1) = _id; \ +static struct mips_machine machine_##_type \ + __used __section(.mips.machines.init) = \ +{ \ + .mach_type = _type, \ + .mach_id = machine_id_##_type, \ + .mach_name = machine_name_##_type, \ + .mach_setup = _setup, \ +}; + +extern long __mips_machines_start; +extern long __mips_machines_end; + +#ifdef CONFIG_MIPS_MACHINE +int mips_machtype_setup(char *id) __init; +void mips_machine_setup(void) __init; +void mips_set_machine_name(const char *name) __init; +char *mips_get_machine_name(void); +#else +static inline int mips_machtype_setup(char *id) { return 1; } +static inline void mips_machine_setup(void) { } +static inline void mips_set_machine_name(const char *name) { } +static inline char *mips_get_machine_name(void) { return NULL; } +#endif /* CONFIG_MIPS_MACHINE */ + +#endif /* __ASM_MIPS_MACHINE_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 22b2e0e..3977397 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o +obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o obj-$(CONFIG_OF) += prom.o diff --git a/arch/mips/kernel/mips_machine.c b/arch/mips/kernel/mips_machine.c new file mode 100644 index 0000000..411a058 --- /dev/null +++ b/arch/mips/kernel/mips_machine.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#include +#include +#include + +#include + +static struct mips_machine *mips_machine __initdata; +static char *mips_machine_name = "Unknown"; + +#define for_each_machine(mach) \ + for ((mach) = (struct mips_machine *)&__mips_machines_start; \ + (mach) && \ + (unsigned long)(mach) < (unsigned long)&__mips_machines_end; \ + (mach)++) + +__init void mips_set_machine_name(const char *name) +{ + char *p; + + if (name == NULL) + return; + + p = kstrdup(name, GFP_KERNEL); + if (!p) + pr_err("MIPS: no memory for machine_name\n"); + + mips_machine_name = p; +} + +char *mips_get_machine_name(void) +{ + return mips_machine_name; +} + +__init int mips_machtype_setup(char *id) +{ + struct mips_machine *mach; + + for_each_machine(mach) { + if (mach->mach_id == NULL) + continue; + + if (strcmp(mach->mach_id, id) == 0) { + mips_machtype = mach->mach_type; + return 0; + } + } + + pr_err("MIPS: no machine found for id '%s', supported machines:\n", id); + pr_err("%-24s %s\n", "id", "name"); + for_each_machine(mach) + pr_err("%-24s %s\n", mach->mach_id, mach->mach_name); + + return 1; +} + +__setup("machtype=", mips_machtype_setup); + +__init void mips_machine_setup(void) +{ + struct mips_machine *mach; + + for_each_machine(mach) { + if (mips_machtype == mach->mach_type) { + mips_machine = mach; + break; + } + } + + if (!mips_machine) + return; + + mips_set_machine_name(mips_machine->mach_name); + pr_info("MIPS: machine is %s\n", mips_machine_name); + + if (mips_machine->mach_setup) + mips_machine->mach_setup(); +} diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 26109c4..4195abb 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -12,6 +12,7 @@ #include #include #include +#include unsigned int vced_count, vcei_count; @@ -31,8 +32,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) /* * For the first processor also print the system type */ - if (n == 0) + if (n == 0) { seq_printf(m, "system type\t\t: %s\n", get_system_type()); + if (mips_get_machine_name()) + seq_printf(m, "machine\t\t\t: %s\n", + mips_get_machine_name()); + } seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index f25df73..570607b 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -98,6 +98,13 @@ SECTIONS INIT_TEXT_SECTION(PAGE_SIZE) INIT_DATA_SECTION(16) + . = ALIGN(4); + .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) { + __mips_machines_start = .; + *(.mips.machines.init) + __mips_machines_end = .; + } + /* .exit.text is discarded at runtime, not link time, to deal with * references from .rodata */ -- 1.7.2.1 From juhosg@openwrt.org Tue Nov 23 16:08:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:08:50 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43908 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491939Ab0KWPG5 (ORCPT ); Tue, 23 Nov 2010 16:06:57 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 37FC94DC00E; Tue, 23 Nov 2010 16:06:52 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id C7A371F0001; Tue, 23 Nov 2010 16:06:51 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, kaloz@openwrt.org, "Luis R. Rodriguez" , Cliff Holden , Gabor Juhos Subject: [PATCH 04/18] MIPS: ath79: utilize the MIPS multi-machine support Date: Tue, 23 Nov 2010 16:06:26 +0100 Message-Id: <1290524800-21419-5-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> References: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> X-VBMS: A14B300F3D1 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28468 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Signed-off-by: Gabor Juhos --- Changes since RFC: --- arch/mips/Kconfig | 1 + arch/mips/ath79/machtypes.h | 21 +++++++++++++++++++++ arch/mips/ath79/setup.c | 15 +++++++++++++++ 3 files changed, 37 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/machtypes.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 307c2e4..047b8f7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -73,6 +73,7 @@ config ATH79 select CSRC_R4K select DMA_NONCOHERENT select IRQ_CPU + select MIPS_MACHINE select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h new file mode 100644 index 0000000..fac0e26 --- /dev/null +++ b/arch/mips/ath79/machtypes.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71XX/AR724X/AR913X machine type definitions + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_MACHTYPE_H +#define _ATH79_MACHTYPE_H + +#include + +enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, +}; + +#endif /* _ATH79_MACHTYPE_H */ diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index dbbf050..8600044 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -18,11 +18,13 @@ #include #include /* for mips_hpt_frequency */ #include /* for _machine_{restart,halt} */ +#include #include #include #include "common.h" #include "dev-common.h" +#include "machtypes.h" #define ATH79_SYS_TYPE_LEN 64 @@ -257,7 +259,20 @@ static int __init ath79_setup(void) { ath79_gpio_init(); ath79_register_uart(); + + mips_machine_setup(); + return 0; } arch_initcall(ath79_setup); + +static void __init ath79_generic_init(void) +{ + /* Nothing to do */ +} + +MIPS_MACHINE(ATH79_MACH_GENERIC, + "Generic", + "Generic AR71XX/AR724X/AR913X based board", + ath79_generic_init); -- 1.7.2.1 From juhosg@openwrt.org Tue Nov 23 16:09:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:09:18 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43967 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492042Ab0KWPHA (ORCPT ); Tue, 23 Nov 2010 16:07:00 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id 7D9594DC016; Tue, 23 Nov 2010 16:06:52 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 164721F0001; Tue, 23 Nov 2010 16:06:52 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, kaloz@openwrt.org, "Luis R. Rodriguez" , Cliff Holden , Gabor Juhos Subject: [PATCH 05/18] MIPS: ath79: add initial support for the Atheros PB44 reference board Date: Tue, 23 Nov 2010 16:06:27 +0100 Message-Id: <1290524800-21419-6-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> References: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> X-VBMS: A14B3850ED7 | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28469 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Signed-off-by: Gabor Juhos --- Changes since RFC: - don't use 'default n' for the ATH79_MACH_PB44 Kconfig option arch/mips/ath79/Kconfig | 11 ++++++++ arch/mips/ath79/Makefile | 5 ++++ arch/mips/ath79/mach-pb44.c | 56 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/machtypes.h | 1 + 4 files changed, 73 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/mach-pb44.c diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 50b9334..fabb2b0 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -1,5 +1,16 @@ if ATH79 +menu "Atheros AR71XX/AR724X/AR913X machine selection" + +config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX + help + Say 'Y' here if you want your kernel to support the + Atheros PB44 reference board. + +endmenu + config SOC_AR71XX def_bool n diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index facbb70..a9ba120 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -16,3 +16,8 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o # Devices # obj-y += dev-common.o + +# +# Machines +# +obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c new file mode 100644 index 0000000..ffc24d7 --- /dev/null +++ b/arch/mips/ath79/mach-pb44.c @@ -0,0 +1,56 @@ +/* + * Atheros PB44 reference board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "machtypes.h" + +#define PB44_GPIO_I2C_SCL 0 +#define PB44_GPIO_I2C_SDA 1 + +#define PB44_GPIO_EXP_BASE 16 + +static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { + .sda_pin = PB44_GPIO_I2C_SDA, + .scl_pin = PB44_GPIO_I2C_SCL, +}; + +static struct platform_device pb44_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &pb44_i2c_gpio_data, + } +}; + +static struct pcf857x_platform_data pb44_pcf857x_data = { + .gpio_base = PB44_GPIO_EXP_BASE, +}; + +static struct i2c_board_info pb44_i2c_board_info[] __initdata = { + { + I2C_BOARD_INFO("pcf8575", 0x20), + .platform_data = &pb44_pcf857x_data, + }, +}; + +static void __init pb44_init(void) +{ + i2c_register_board_info(0, pb44_i2c_board_info, + ARRAY_SIZE(pb44_i2c_board_info)); + platform_device_register(&pb44_i2c_gpio_device); +} + +MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", + pb44_init); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h index fac0e26..a796fa3 100644 --- a/arch/mips/ath79/machtypes.h +++ b/arch/mips/ath79/machtypes.h @@ -16,6 +16,7 @@ enum ath79_mach_type { ATH79_MACH_GENERIC = 0, + ATH79_MACH_PB44, /* Atheros PB44 reference board */ }; #endif /* _ATH79_MACHTYPE_H */ -- 1.7.2.1 From juhosg@openwrt.org Tue Nov 23 16:09:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:09:46 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43968 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492020Ab0KWPHA (ORCPT ); Tue, 23 Nov 2010 16:07:00 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id C5BC14DC017; Tue, 23 Nov 2010 16:06:52 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 55E831F0001; Tue, 23 Nov 2010 16:06:52 +0100 (CET) From: Gabor Juhos To: Ralf Baechle Cc: linux-mips@linux-mips.org, kaloz@openwrt.org, "Luis R. Rodriguez" , Cliff Holden , Gabor Juhos Subject: [PATCH 06/18] MIPS: ath79: add common GPIO LEDs device Date: Tue, 23 Nov 2010 16:06:28 +0100 Message-Id: <1290524800-21419-7-git-send-email-juhosg@openwrt.org> X-Mailer: git-send-email 1.7.2.1 In-Reply-To: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> References: <1290524800-21419-1-git-send-email-juhosg@openwrt.org> X-VBMS: A14B3C97CCF | phoenix3 | 127.0.0.1 | | | Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28470 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: juhosg@openwrt.org Precedence: bulk X-list: linux-mips Almost all boards have one or more LEDs connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the LEDs on the PB44 board. Signed-off-by: Gabor Juhos Signed-off-by: Imre Kaloz --- Changes since RFC: --- arch/mips/ath79/Kconfig | 4 +++ arch/mips/ath79/Makefile | 1 + arch/mips/ath79/dev-leds-gpio.c | 56 +++++++++++++++++++++++++++++++++++++++ arch/mips/ath79/dev-leds-gpio.h | 21 ++++++++++++++ arch/mips/ath79/mach-pb44.c | 18 ++++++++++++ 5 files changed, 100 insertions(+), 0 deletions(-) create mode 100644 arch/mips/ath79/dev-leds-gpio.c create mode 100644 arch/mips/ath79/dev-leds-gpio.h diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index fabb2b0..5bc480e 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -5,6 +5,7 @@ menu "Atheros AR71XX/AR724X/AR913X machine selection" config ATH79_MACH_PB44 bool "Atheros PB44 reference board" select SOC_AR71XX + select ATH79_DEV_LEDS_GPIO help Say 'Y' here if you want your kernel to support the Atheros PB44 reference board. @@ -20,4 +21,7 @@ config SOC_AR724X config SOC_AR913X def_bool n +config ATH79_DEV_LEDS_GPIO + def_bool n + endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index a9ba120..d14b597 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o # Devices # obj-y += dev-common.o +obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o # # Machines diff --git a/arch/mips/ath79/dev-leds-gpio.c b/arch/mips/ath79/dev-leds-gpio.c new file mode 100644 index 0000000..cdade68 --- /dev/null +++ b/arch/mips/ath79/dev-leds-gpio.c @@ -0,0 +1,56 @@ +/* + * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include "dev-leds-gpio.h" + +void __init ath79_register_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds) +{ + struct platform_device *pdev; + struct gpio_led_platform_data pdata; + struct gpio_led *p; + int err; + + p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, leds, num_leds * sizeof(*p)); + + pdev = platform_device_alloc("leds-gpio", id); + if (!pdev) + goto err_free_leds; + + memset(&pdata, 0, sizeof(pdata)); + pdata.num_leds = num_leds; + pdata.leds = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_leds: + kfree(p); +} diff --git a/arch/mips/ath79/dev-leds-gpio.h b/arch/mips/ath79/dev-leds-gpio.h new file mode 100644 index 0000000..0fb0ed1 --- /dev/null +++ b/arch/mips/ath79/dev-leds-gpio.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_LEDS_GPIO_H +#define _ATH79_DEV_LEDS_GPIO_H + +#include + +void ath79_register_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds) __init; + +#endif /* _ATH79_DEV_LEDS_GPIO_H */ diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c index ffc24d7..e176779 100644 --- a/arch/mips/ath79/mach-pb44.c +++ b/arch/mips/ath79/mach-pb44.c @@ -15,11 +15,14 @@ #include #include "machtypes.h" +#include "dev-leds-gpio.h" #define PB44_GPIO_I2C_SCL 0 #define PB44_GPIO_I2C_SDA 1 #define PB44_GPIO_EXP_BASE 16 +#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) +#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { .sda_pin = PB44_GPIO_I2C_SDA, @@ -45,11 +48,26 @@ static struct i2c_board_info pb44_i2c_board_info[] __initdata = { }, }; +static struct gpio_led pb44_leds_gpio[] __initdata = { + { + .name = "pb44:amber:jump1", + .gpio = PB44_GPIO_LED_JUMP1, + .active_low = 1, + }, { + .name = "pb44:green:jump2", + .gpio = PB44_GPIO_LED_JUMP2, + .active_low = 1, + }, +}; + static void __init pb44_init(void) { i2c_register_board_info(0, pb44_i2c_board_info, ARRAY_SIZE(pb44_i2c_board_info)); platform_device_register(&pb44_i2c_gpio_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), + pb44_leds_gpio); } MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", -- 1.7.2.1 From juhosg@openwrt.org Tue Nov 23 16:10:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Nov 2010 16:10:10 +0100 (CET) Received: from phoenix3.szarvasnet.hu ([87.101.127.16]:43967 "EHLO phoenix3.szarvasnet.hu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492043Ab0KWPHA (ORCPT ); Tue, 23 Nov 2010 16:07:00 +0100 Received: from mail.szarvas.hu (localhost [127.0.0.1]) by phoenix3.szarvasnet.hu (Postfix) with SMTP id EA47D41C004; Tue, 23 Nov 2010 16:06:55 +0100 (CET) Received: from localhost.localdomain (catvpool-576570d8.szarvasnet.hu [87.101.112.216]) by phoenix3.szarvasnet.hu (Postfix) with ESMTPA id 65FAE1F0001; Tue, 23 Nov 2010 16:06:55 +0100 (CET) From: Gabor Juhos To: Ralf Baech