From rostedt@goodmis.org Wed Sep 1 02:06:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Sep 2010 02:06:38 +0200 (CEST) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.123]:43178 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490991Ab0IAAGb (ORCPT ); Wed, 1 Sep 2010 02:06:31 +0200 X-Authority-Analysis: v=1.1 cv=8rLOhk8wZGSvnaCM3aW+9DxbPzg0bBAKX0Qt8NUyFX0= c=1 sm=0 a=vpGvh0kIRgkA:10 a=Q9fys5e9bTEA:10 a=OPBmh+XkhLl+Enan7BmTLg==:17 a=UVBnVOq77BREf0-VBfcA:9 a=pYSEPj7oK5rFuqYse6kA:7 a=dJkidqD3Sk6vsfd-eoJqwkJQ2rUA:4 a=PUjeQqilurYA:10 a=OPBmh+XkhLl+Enan7BmTLg==:117 X-Cloudmark-Score: 0 X-Originating-IP: 67.242.120.143 Received: from [67.242.120.143] ([67.242.120.143:48763] helo=[192.168.23.10]) by hrndva-oedge03.mail.rr.com (envelope-from ) (ecelerity 2.2.2.39 r()) with ESMTP id D8/B5-15146-EF89D7C4; Wed, 01 Sep 2010 00:06:23 +0000 Subject: Re: Ftrace for MIPS may hang on SMP system From: Steven Rostedt To: wu zhangjin Cc: David Daney , Ralf Baechle , linux-mips In-Reply-To: References: <4C72B16B.5000101@caviumnetworks.com> <1283201505.3656.25.camel@gandalf.stny.rr.com> Content-Type: text/plain; charset="ISO-8859-15" Date: Tue, 31 Aug 2010 20:06:22 -0400 Message-ID: <1283299582.1377.859.camel@gandalf.stny.rr.com> Mime-Version: 1.0 X-Mailer: Evolution 2.30.2 Content-Transfer-Encoding: 7bit X-archive-position: 27706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18 Content-Length: 4070 Lines: 118 On Tue, 2010-08-31 at 11:33 +0800, wu zhangjin wrote: > We have called ftace_modify_code() with irq disabled(the same to > stop_machine()): > > kernel/trace/ftrace.c: > > /* disable interrupts to prevent kstop machine */ > local_irq_save(flags); > ftrace_update_code(mod); > local_irq_restore(flags); > > This may introduce the warning in the smp_call_func_many() if we call > flush_icache_range() in ftrace_modify_code() on SMP: Hmm, I think preempt_disable() will do the same thing. Would that work? > > kernel/smp.c: > > void smp_call_function_many(const struct cpumask *mask, > void (*func)(void *), void *info, bool wait) > { > struct call_function_data *data; > unsigned long flags; > int cpu, next_cpu, this_cpu = smp_processor_id(); > > /* > * Can deadlock when called with interrupts disabled. > * We allow cpu's that are not yet online though, as no one else can > * send smp call function interrupt to this cpu and as such deadlocks > * can't happen. > */ > WARN_ON_ONCE(cpu_online(this_cpu) && irqs_disabled() > && !oops_in_progress); > > Actually, for the other cpus' irq are not disabled here, there will be > no real deadlock, but this warning may show there are really potential > problems, if the irqs of the other cpus are disabled by something > else, we may really get the deadlock. > > So, If want to fix this problem eventually, my patch is not enough, we > may need to move the flush_icache_range() out of the > ftrace_modify_code() and after the irq is enabled, for example: > > /* disable interrupts to prevent kstop machine */ > local_irq_save(flags); > ftrace_update_code(mod); > local_irq_restore(flags); > + __flush_icache_all(); > > and similarly, we add this __flush_icache_all() after the stop_machine() too: > > static void ftrace_run_update_code(int command) > { > int ret; > > ret = ftrace_arch_code_modify_prepare(); > FTRACE_WARN_ON(ret); > if (ret) > return; > > stop_machine(__ftrace_modify_code, &command, NULL); > + __flush_icache_all(); > > ret = ftrace_arch_code_modify_post_process(); > FTRACE_WARN_ON(ret); > } > > I'm not sure whether this is needed for all of the architectures, but > this may be needed by MIPS and powerpc. > > If X86 doesn't need it, we can add a macro > NEED_FTRACE_FLUSH_ICACHE_ALL for MIPS and powerpc and introduce a > wrapper ftrace_flush_icache_all() for __flush_icache_all(). Perhaps just changing the above to preempt disable() and adding the __flush_icache_all() > > static inline ftrace_flush_icache_all() > { > #ifdef NEED_FTRACE_FLUSH_ICACHE_ALL > __flush_icache_all(); > #endif > } Hmm, maybe we could just add another weak function called ftrace_arch_module_post_process() and have the archs do the flush themselves. I'm not sure that function is common even for the archs that would need it. > > Can we apply this method on X86 too? I'm not sure the performance of > the current sync_core() ;-) If it is not good(especially when we use > it for 22,000 times as you mentioned above), we may be possible to > apply this method on X86 to improve the performance too. Well, we also need it for NMI than do run, thus it should be fine. The 22,000 updates does not seem to be an issue. > > And a side effect is: after moving flush_icache_range() out of the > ftrace_modify_code(), we may need to ensure every caller of > ftrace_modify_code() must flush the icaches themselves, sometimes we > may need to call __flush_icache_full() If we don't know which range we > need to flush, sometimes we may be possible to call > flush_icache_range() to flush the indicated range of the icaches > realted to ftrace_modify_code(). Perhaps just be safe and call the flush_icache_full() after the modifications. Thus I think it would be best to have the ftrace_arch_* functions. -- Steve From chris@notav8.com Wed Sep 1 10:59:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Sep 2010 10:59:58 +0200 (CEST) Received: from notav8.com ([66.160.168.115]:57473 "HELO notav8.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491023Ab0IAI7y (ORCPT ); Wed, 1 Sep 2010 10:59:54 +0200 Received: from www.notav8.com ([66.160.168.115]) by notav8.com for ; Wed, 1 Sep 2010 01:59:44 -0700 Received: from 98.248.135.54 (SquirrelMail authenticated user chris) by www.notav8.com with HTTP; Wed, 1 Sep 2010 01:59:44 -0700 (PDT) Message-ID: <1341.98.248.135.54.1283331584.squirrel@www.notav8.com> Date: Wed, 1 Sep 2010 01:59:44 -0700 (PDT) Subject: Network Inst From: chris@notav8.com To: linux-mips@linux-mips.org User-Agent: SquirrelMail/1.5.1 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT X-archive-position: 27707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chris@notav8.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 277 Content-Length: 427 Lines: 13 I've been trying to do a network install of Debian on an SGI Indigo2 without success. Using tcpdump I can see the BOOTP request go out and the reply come back. I don't think the reply is being fragmented. The SGI is responding to ARP requests so I know it's receiving. I'd like to compare my BOOTP response with a known working one. Can someone send me a trace of a successful BOOTP transaction? Thanks, Chris Rhodin From shmulik.ladkani@gmail.com Wed Sep 1 11:17:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Sep 2010 11:17:56 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:64527 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490993Ab0IAJRw (ORCPT ); Wed, 1 Sep 2010 11:17:52 +0200 Received: by fxm12 with SMTP id 12so5533031fxm.36 for ; Wed, 01 Sep 2010 02:17:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to:cc :subject:x-mailer:mime-version:content-type :content-transfer-encoding; bh=7x0e6Oc62S5BwzMU3nYcvtYKUsskzgZ8eULEbgBFf1U=; b=kLq+k2DV1yGESuVI88MNS13tBotWk4157nPHPzvEn75gIXfwj/lFMG/VzluXSOclk1 kR/mLOUxP1Yy4uvKGSSvGTdUqCwe3G3iRUWXIbWvhOtLUHr9QC9vpHUrVMl4z077hLLK HCrkWrLeRYt2o66eDS7ENrqac7oepj6h6iWP4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:cc:subject:x-mailer:mime-version :content-type:content-transfer-encoding; b=HXosbwylVB0tx1e1TSosUebQve4ZmBVheVCMYj2A9Mf4xBc+aBhMV4F96KZbLe/XCi /QYqUf+UpnOiK3blbog1W7mv2XOMKifty2BlkAI3WitnIerMeVP+BqGtt3QGvCF9yrJ/ CALFggNj6nLZZsp0pDUxo8FY1XWuPhM4DqqpE= Received: by 10.223.105.76 with SMTP id s12mr6581425fao.107.1283332667331; Wed, 01 Sep 2010 02:17:47 -0700 (PDT) Received: from pixies.home.jungo.com (pptp-il.jungo.com [194.90.113.98]) by mx.google.com with ESMTPS id u8sm4478022fah.36.2010.09.01.02.17.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Sep 2010 02:17:46 -0700 (PDT) Message-ID: <4c7e1a3a.c83ddf0a.5918.ffffcf6a@mx.google.com> Date: Wed, 1 Sep 2010 12:17:43 +0300 From: Shmulik Ladkani To: ralf@linux-mips.org, wuzhangjin@gmail.com, linux-mips@linux-mips.org Cc: alex@digriz.org.uk, manuel.lauss@googlemail.com, sam@ravnborg.org, linux-kernel@vger.kernel.org Subject: [PATCH] MIPS: Fix vmlinuz to flush the caches after kernel decompression X-Mailer: Sylpheed 3.0.2 (GTK+ 2.18.3; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-archive-position: 27708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shmulik.ladkani@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 292 Content-Length: 4163 Lines: 148 Flush caches after kernel decompression. When writing instructions, the D-cache should be written-back, and I-cache should be invalidated. The patch implements L1 cache flushing, for r4k style caches - suitable for all MIPS32 CPUs (and probably for other CPUs too). Signed-off-by: Shmulik Ladkani --- diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index ed9bb70..9a8d2da 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -30,6 +30,9 @@ targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o # decompressor objects (linked with vmlinuz) vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o +targets += $(obj)/c-r4k.o +vmlinuzobjs-$(CONFIG_CPU_MIPS32) += $(obj)/c-r4k.o + ifdef CONFIG_DEBUG_ZBOOT vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o diff --git a/arch/mips/boot/compressed/c-r4k.c b/arch/mips/boot/compressed/c-r4k.c new file mode 100644 index 0000000..1959cdc --- /dev/null +++ b/arch/mips/boot/compressed/c-r4k.c @@ -0,0 +1,92 @@ +#include +#include + +#include +#include +#include +#include + +#define INDEX_BASE CKSEG0 + +extern void puts(const char *s); +extern void puthex(unsigned long long val); + +#define cache_op(op, addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0(%0) \n" \ + " .set pop \n" \ + : \ + : "r" (addr), "i" (op)) + +#define cache_all_index_op(cachesz, linesz, op) do { \ + unsigned long addr = INDEX_BASE; \ + for (; addr < INDEX_BASE + (cachesz); addr += (linesz)) \ + cache_op(op, addr); \ +} while (0) + +static void dcache_writeback(const unsigned long cache_size, + const unsigned long line_size) +{ +#ifdef DEBUG + puts("dcache writeback, cachesize "); + puthex(cache_size); + puts(" linesize "); + puthex(line_size); + puts("\n"); +#endif + + cache_all_index_op(cache_size, line_size, Index_Writeback_Inv_D); +} + +static void icache_invalidate(const unsigned long cache_size, + const unsigned long line_size) +{ +#ifdef DEBUG + puts("icache invalidate, cachesize "); + puthex(cache_size); + puts(" linesize "); + puthex(line_size); + puts("\n"); +#endif + + cache_all_index_op(cache_size, line_size, Index_Invalidate_I); +} + +void cache_flush(void) +{ + volatile unsigned long config1; + unsigned long tmp; + unsigned long line_size; + unsigned long ways; + unsigned long sets; + unsigned long cache_size; + + if (!(read_c0_config() & MIPS_CONF_M)) { + puts("cache_flush error: Config1 unavailable\n"); + return; + } + config1 = read_c0_config1(); + + /* calculate D-cache line-size and cache-size, then writeback */ + tmp = (config1 >> 10) & 7; + if (tmp) { + line_size = 2 << tmp; + sets = 64 << ((config1 >> 13) & 7); + ways = 1 + ((config1 >> 7) & 7); + cache_size = sets * ways * line_size; + dcache_writeback(cache_size, line_size); + } + + /* calculate I-cache line-size and cache-size, then invalidate */ + tmp = (config1 >> 19) & 7; + if (tmp) { + line_size = 2 << tmp; + sets = 64 << ((config1 >> 22) & 7); + ways = 1 + ((config1 >> 16) & 7); + cache_size = sets * ways * line_size; + icache_invalidate(cache_size, line_size); + } +} diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c index 5cad0fa..c86f9bd 100644 --- a/arch/mips/boot/compressed/decompress.c +++ b/arch/mips/boot/compressed/decompress.c @@ -30,6 +30,10 @@ extern unsigned char __image_begin, __image_end; extern void puts(const char *s); extern void puthex(unsigned long long val); +void __weak cache_flush(void) +{ +} + void error(char *x) { puts("\n\n"); @@ -105,6 +109,7 @@ void decompress_kernel(unsigned long boot_heap_start) decompress((char *)zimage_start, zimage_size, 0, 0, (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error); - /* FIXME: should we flush cache here? */ + cache_flush(); + puts("Now, booting the kernel...\n"); } -- Shmulik Ladkani From wuzhangjin@gmail.com Thu Sep 2 07:54:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Sep 2010 07:54:35 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:43001 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490957Ab0IBFyb (ORCPT ); Thu, 2 Sep 2010 07:54:31 +0200 Received: by wyb29 with SMTP id 29so11114wyb.36 for ; Wed, 01 Sep 2010 22:54:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=oo8imHThhVQ8J4HI2D9SDWCN6xcSMyii9PkKcQqNnAc=; b=Zdl/nsCi/ZdNU0OqwLJ4Li2fdYQ2Jfjjnedkspmk1JI9yJfOsSmbCmqVi2Z87klCll 0pXJkhm40Y9Spn/Vah/vdlsZeKqO8TyETCOvZd5CLSo3GxVdQJ0JRaaZ28AW009lWw7p hyswaGhs9dkw0MRYzRk8MGc8cp0M+NAi9b1S4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=I3KLDiTjhou5NtrxCoHmwtGpVp28uafmXBqyto7bT3pyZDzHjmsUx4LZGKdcgOzRAx hUWDxWkNQnSBk5qrGvCWzvHTirn4l/4RVyepH3RHg+STKxfRYxTGiYkeEIhQ+4iRSt/x w0AWQj8FpcHF7eYmnmOJj2RCCUCr47icWibmE= MIME-Version: 1.0 Received: by 10.216.7.78 with SMTP id 56mr830719weo.96.1283406865333; Wed, 01 Sep 2010 22:54:25 -0700 (PDT) Received: by 10.216.166.69 with HTTP; Wed, 1 Sep 2010 22:54:24 -0700 (PDT) In-Reply-To: <1283299582.1377.859.camel@gandalf.stny.rr.com> References: <4C72B16B.5000101@caviumnetworks.com> <1283201505.3656.25.camel@gandalf.stny.rr.com> <1283299582.1377.859.camel@gandalf.stny.rr.com> Date: Thu, 2 Sep 2010 13:54:24 +0800 Message-ID: Subject: Re: Ftrace for MIPS may hang on SMP system From: wu zhangjin To: Steven Rostedt Cc: David Daney , Ralf Baechle , linux-mips Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27709 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 1127 Content-Length: 4354 Lines: 126 On 9/1/10, Steven Rostedt wrote: > On Tue, 2010-08-31 at 11:33 +0800, wu zhangjin wrote: > >> We have called ftace_modify_code() with irq disabled(the same to >> stop_machine()): >> >> kernel/trace/ftrace.c: >> >> /* disable interrupts to prevent kstop machine */ >> local_irq_save(flags); >> ftrace_update_code(mod); >> local_irq_restore(flags); >> >> This may introduce the warning in the smp_call_func_many() if we call >> flush_icache_range() in ftrace_modify_code() on SMP: > > Hmm, I think preempt_disable() will do the same thing. Would that work? > >> >> kernel/smp.c: >> >> void smp_call_function_many(const struct cpumask *mask, >> void (*func)(void *), void *info, bool wait) >> { >> struct call_function_data *data; >> unsigned long flags; >> int cpu, next_cpu, this_cpu = smp_processor_id(); >> >> /* >> * Can deadlock when called with interrupts disabled. >> * We allow cpu's that are not yet online though, as no one else >> can >> * send smp call function interrupt to this cpu and as such >> deadlocks >> * can't happen. >> */ >> WARN_ON_ONCE(cpu_online(this_cpu) && irqs_disabled() >> && !oops_in_progress); >> >> Actually, for the other cpus' irq are not disabled here, there will be >> no real deadlock, but this warning may show there are really potential >> problems, if the irqs of the other cpus are disabled by something >> else, we may really get the deadlock. >> >> So, If want to fix this problem eventually, my patch is not enough, we >> may need to move the flush_icache_range() out of the >> ftrace_modify_code() and after the irq is enabled, for example: >> >> /* disable interrupts to prevent kstop machine */ >> local_irq_save(flags); >> ftrace_update_code(mod); >> local_irq_restore(flags); >> + __flush_icache_all(); >> >> and similarly, we add this __flush_icache_all() after the stop_machine() >> too: >> >> static void ftrace_run_update_code(int command) >> { >> int ret; >> >> ret = ftrace_arch_code_modify_prepare(); >> FTRACE_WARN_ON(ret); >> if (ret) >> return; >> >> stop_machine(__ftrace_modify_code, &command, NULL); >> + __flush_icache_all(); >> >> ret = ftrace_arch_code_modify_post_process(); >> FTRACE_WARN_ON(ret); >> } >> >> I'm not sure whether this is needed for all of the architectures, but >> this may be needed by MIPS and powerpc. >> >> If X86 doesn't need it, we can add a macro >> NEED_FTRACE_FLUSH_ICACHE_ALL for MIPS and powerpc and introduce a >> wrapper ftrace_flush_icache_all() for __flush_icache_all(). > > Perhaps just changing the above to preempt disable() and adding the > __flush_icache_all() > >> >> static inline ftrace_flush_icache_all() >> { >> #ifdef NEED_FTRACE_FLUSH_ICACHE_ALL >> __flush_icache_all(); >> #endif >> } > > Hmm, maybe we could just add another weak function called > ftrace_arch_module_post_process() and have the archs do the flush > themselves. I'm not sure that function is common even for the archs that > would need it. > > >> >> Can we apply this method on X86 too? I'm not sure the performance of >> the current sync_core() ;-) If it is not good(especially when we use >> it for 22,000 times as you mentioned above), we may be possible to >> apply this method on X86 to improve the performance too. > > Well, we also need it for NMI than do run, thus it should be fine. The > 22,000 updates does not seem to be an issue. > >> >> And a side effect is: after moving flush_icache_range() out of the >> ftrace_modify_code(), we may need to ensure every caller of >> ftrace_modify_code() must flush the icaches themselves, sometimes we >> may need to call __flush_icache_full() If we don't know which range we >> need to flush, sometimes we may be possible to call >> flush_icache_range() to flush the indicated range of the icaches >> realted to ftrace_modify_code(). > > Perhaps just be safe and call the flush_icache_full() after the > modifications. Thus I think it would be best to have the ftrace_arch_* > functions. Ok, I will add the ftrace_arch_module_prepare/post_process() to kernel/trace/ftrace.c. Thanks Steve! Regards, Wu Zhangjin From fujita.tomonori@lab.ntt.co.jp Fri Sep 3 02:51:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Sep 2010 02:51:48 +0200 (CEST) Received: from sh.osrg.net ([192.16.179.4]:55615 "EHLO sh.osrg.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491070Ab0ICAvo (ORCPT ); Fri, 3 Sep 2010 02:51:44 +0200 Received: from localhost (rose.osrg.net [10.76.0.1]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o830pVZt020267; Fri, 3 Sep 2010 09:51:34 +0900 From: FUJITA Tomonori To: akpm@linux-foundation.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, fujita.tomonori@lab.ntt.co.jp, linux-mips@linux-mips.org Subject: [PATCH -mm 4/8] mips: enable ARCH_DMA_ADDR_T_64BIT with (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT Date: Fri, 3 Sep 2010 09:49:12 +0900 Message-Id: <1283474956-14710-4-git-send-email-fujita.tomonori@lab.ntt.co.jp> X-Mailer: git-send-email 1.7.1 In-Reply-To: <20100903094753S.fujita.tomonori@lab.ntt.co.jp> References: <20100903094753S.fujita.tomonori@lab.ntt.co.jp> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Fri, 03 Sep 2010 09:51:35 +0900 (JST) X-Virus-Scanned: clamav-milter 0.96.1 at sh X-Virus-Status: Clean X-archive-position: 27710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fujita.tomonori@lab.ntt.co.jp Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2141 Content-Length: 487 Lines: 23 Signed-off-by: FUJITA Tomonori Cc: linux-mips@linux-mips.org --- arch/mips/Kconfig | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ad59dd..3e9db47 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -830,6 +830,9 @@ config GPIO_TXX9 config CFE bool +config ARCH_DMA_ADDR_T_64BIT + def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT + config DMA_COHERENT bool -- 1.7.1 From walle@corscience.de Fri Sep 3 10:16:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Sep 2010 10:16:20 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:62153 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491079Ab0ICIQQ (ORCPT ); Fri, 3 Sep 2010 10:16:16 +0200 Received: from corscience.de (DSL01.212.114.252.242.ip-pool.NEFkom.net [212.114.252.242]) by mrelayeu.kundenserver.de (node=mreu1) with ESMTP (Nemesis) id 0LupVN-1OioZ53QMz-010Zi7; Fri, 03 Sep 2010 10:15:34 +0200 Received: from localhost.localdomain (unknown [192.168.102.58]) by corscience.de (Postfix) with ESMTP id 54B2651FA1; Fri, 3 Sep 2010 10:15:34 +0200 (CEST) From: Bernhard Walle To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, ddaney@caviumnetworks.com, akpm@linux-foundation.org, ebiederm@xmission.com, hch@lst.de, linux-kernel@vger.kernel.org Subject: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 Date: Fri, 3 Sep 2010 10:15:34 +0200 Message-Id: <1283501734-6532-1-git-send-email-walle@corscience.de> X-Mailer: git-send-email 1.7.0.4 X-Provags-ID: V02:K0:80V1Up6k0zdnJ31H8L7+4YcvYB5b3HphSFXeOchfLvB PJmxnxjDizFnOMFLZy6OrXoa52hfKBImRO3aRy97PkVqsYVHQl X5F+qmtAHvlY89sVlzRbTEED21n0yWVU1XEvDvUrQWjoXsSoTG bFGlYRWtVTMZHYxxGigMHmQfUDUn705ztv33ubL24z5IrbSNlm +LYQRSUBr+lwyaPK+I6jQ== X-archive-position: 27711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: walle@corscience.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2385 Content-Length: 913 Lines: 27 Commit 31c984a5acabea5d8c7224dc226453022be46f33 introduced a new syscall getdents64. However, in the syscall table, the new syscall still refers to the old getdents which doesn't work. The problem appeared with a system that uses the eglibc 2.12-r11187 (that utilizes that new syscall) is very confused. The fix has been tested with that eglibc version. Signed-off-by: Bernhard Walle --- arch/mips/kernel/scall64-n32.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index a3d6613..dfa8cbc 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -419,5 +419,5 @@ EXPORT(sysn32_call_table) PTR sys_perf_event_open PTR sys_accept4 PTR compat_sys_recvmmsg - PTR sys_getdents + PTR sys_getdents64 .size sysn32_call_table,.-sysn32_call_table -- 1.7.0.4 From hch@lst.de Fri Sep 3 10:42:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Sep 2010 10:42:25 +0200 (CEST) Received: from verein.lst.de ([213.95.11.210]:33245 "EHLO verein.lst.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490999Ab0ICImU (ORCPT ); Fri, 3 Sep 2010 10:42:20 +0200 Received: from verein.lst.de (localhost [127.0.0.1]) by verein.lst.de (8.12.3/8.12.3/Debian-7.1) with ESMTP id o838gEWY032372 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Fri, 3 Sep 2010 10:42:14 +0200 Received: (from hch@localhost) by verein.lst.de (8.12.3/8.12.3/Debian-7.2) id o838gDX9032370; Fri, 3 Sep 2010 10:42:13 +0200 Date: Fri, 3 Sep 2010 10:42:13 +0200 From: Christoph Hellwig To: Bernhard Walle Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, ddaney@caviumnetworks.com, akpm@linux-foundation.org, ebiederm@xmission.com, hch@lst.de, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 Message-ID: <20100903084213.GA32339@lst.de> References: <1283501734-6532-1-git-send-email-walle@corscience.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1283501734-6532-1-git-send-email-walle@corscience.de> User-Agent: Mutt/1.3.28i X-Scanned-By: MIMEDefang 2.39 X-archive-position: 27712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@lst.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2402 Content-Length: 129 Lines: 3 I'm not sure why people suddenly started Ccing me on utterly random patches, but could you guys please bloody stop it? Thanks! From apatard@mandriva.com Fri Sep 3 10:53:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Sep 2010 10:53:06 +0200 (CEST) Received: from mx1.moondrake.net ([212.85.150.166]:55787 "EHLO mx1.mandriva.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491068Ab0ICIxD (ORCPT ); Fri, 3 Sep 2010 10:53:03 +0200 Received: by mx1.mandriva.com (Postfix, from userid 501) id 1E5B7274128; Fri, 3 Sep 2010 10:53:01 +0200 (CEST) Received: from office-abk.mandriva.com (unknown [195.7.104.248]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.mandriva.com (Postfix) with ESMTP id 5DCF2274005; Fri, 3 Sep 2010 10:53:00 +0200 (CEST) Received: from anduin.mandriva.com (fw2.mandriva.com [192.168.2.3]) by office-abk.mandriva.com (Postfix) with ESMTP id 9E43985701; Fri, 3 Sep 2010 11:14:17 +0200 (CEST) Received: from anduin.mandriva.com (localhost [127.0.0.1]) by anduin.mandriva.com (Postfix) with ESMTP id 678CEFF855; Fri, 3 Sep 2010 10:53:31 +0200 (CEST) From: Arnaud Patard To: Christoph Hellwig Cc: Bernhard Walle , linux-mips@linux-mips.org, ralf@linux-mips.org, ddaney@caviumnetworks.com, akpm@linux-foundation.org, ebiederm@xmission.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 References: <1283501734-6532-1-git-send-email-walle@corscience.de> <20100903084213.GA32339@lst.de> Organization: Mandriva Date: Fri, 03 Sep 2010 10:53:31 +0200 In-Reply-To: <20100903084213.GA32339@lst.de> (Christoph Hellwig's message of "Fri, 3 Sep 2010 10:42:13 +0200") Message-ID: User-Agent: Gnus/5.1008 (Gnus v5.10.8) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-archive-position: 27713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: apatard@mandriva.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2408 Content-Length: 542 Lines: 20 Christoph Hellwig writes: Hi, > I'm not sure why people suddenly started Ccing me on utterly random > patches, but could you guys please bloody stop it? Thanks! I guess the explanation is the one below : $ ./scripts/get_maintainer.pl -f arch/mips/kernel/scall64-n32.S Ralf Baechle David Daney Andrew Morton "Eric W. Biederman" Christoph Hellwig linux-mips@linux-mips.org linux-kernel@vger.kernel.org Arnaud From hch@lst.de Fri Sep 3 10:55:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Sep 2010 10:55:31 +0200 (CEST) Received: from verein.lst.de ([213.95.11.210]:58487 "EHLO verein.lst.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491083Ab0ICIz1 (ORCPT ); Fri, 3 Sep 2010 10:55:27 +0200 Received: from verein.lst.de (localhost [127.0.0.1]) by verein.lst.de (8.12.3/8.12.3/Debian-7.1) with ESMTP id o838tLWY000342 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Fri, 3 Sep 2010 10:55:21 +0200 Received: (from hch@localhost) by verein.lst.de (8.12.3/8.12.3/Debian-7.2) id o838tL7w000341; Fri, 3 Sep 2010 10:55:21 +0200 Date: Fri, 3 Sep 2010 10:55:21 +0200 From: Christoph Hellwig To: Arnaud Patard Cc: Christoph Hellwig , Bernhard Walle , linux-mips@linux-mips.org, ralf@linux-mips.org, ddaney@caviumnetworks.com, akpm@linux-foundation.org, ebiederm@xmission.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 Message-ID: <20100903085521.GA304@lst.de> References: <1283501734-6532-1-git-send-email-walle@corscience.de> <20100903084213.GA32339@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.3.28i X-Scanned-By: MIMEDefang 2.39 X-archive-position: 27714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@lst.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2411 Content-Length: 509 Lines: 15 On Fri, Sep 03, 2010 at 10:53:31AM +0200, Arnaud Patard wrote: > Christoph Hellwig writes: > > Hi, > > > I'm not sure why people suddenly started Ccing me on utterly random > > patches, but could you guys please bloody stop it? Thanks! > > I guess the explanation is the one below : > > $ ./scripts/get_maintainer.pl -f arch/mips/kernel/scall64-n32.S I'm certainly not the maintainer of it, nor anything near it. Whoever wrote such a stupid script really needs to be beaten up seriously. From walle@corscience.de Fri Sep 3 11:14:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Sep 2010 11:14:14 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.10]:52346 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491084Ab0ICJOK (ORCPT ); Fri, 3 Sep 2010 11:14:10 +0200 Received: from corscience.de (DSL01.212.114.252.242.ip-pool.NEFkom.net [212.114.252.242]) by mrelayeu.kundenserver.de (node=mreu0) with ESMTP (Nemesis) id 0MXCef-1PNdvi2qJR-00WFTx; Fri, 03 Sep 2010 11:13:32 +0200 Received: from [192.168.102.58] (unknown [192.168.102.58]) by corscience.de (Postfix) with ESMTP id 31FF051FA1; Fri, 3 Sep 2010 11:13:31 +0200 (CEST) Message-ID: <4C80BC3A.7010406@corscience.de> Date: Fri, 03 Sep 2010 11:13:30 +0200 From: Bernhard Walle User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100713 Thunderbird/3.0.6 MIME-Version: 1.0 To: Arnaud Patard CC: Christoph Hellwig , linux-mips@linux-mips.org, ralf@linux-mips.org, ddaney@caviumnetworks.com, akpm@linux-foundation.org, ebiederm@xmission.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 References: <1283501734-6532-1-git-send-email-walle@corscience.de> <20100903084213.GA32339@lst.de> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Provags-ID: V02:K0:R8n2dqZbSo1xc86ONWX6R7PJJuLEVGlBZwPViS+/OGh 523htMkIdbHbIkOqda0TIPPN4JyDI7383qOLwUNK342kBNRpba RlUPBnCwU53qneUJtvpdL95qE1sZPDzHzHOzY1T/UQOsCqb0VX 2oVyEQidoZ1JfsIgMa1TUkVIy3E89nZKOwwcxBggcZMXo/cqiz LXrzoU8SA2i88F6SXPI1A== X-archive-position: 27715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: walle@corscience.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2430 Content-Length: 506 Lines: 18 Am 03.09.2010 10:53, schrieb Arnaud Patard: > > I guess the explanation is the one below : > > $ ./scripts/get_maintainer.pl -f arch/mips/kernel/scall64-n32.S > Ralf Baechle > David Daney > Andrew Morton > "Eric W. Biederman" > Christoph Hellwig > linux-mips@linux-mips.org > linux-kernel@vger.kernel.org Yes, I just used that script and trusted the results. Sorry for that. Regards, Bernhard From ralf@linux-mips.org Fri Sep 3 12:01:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Sep 2010 12:01:50 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1490956Ab0ICKBm (ORCPT ); Fri, 3 Sep 2010 12:01:42 +0200 Date: Fri, 3 Sep 2010 12:01:40 +0200 From: Ralf Baechle To: Bernhard Walle Cc: Arnaud Patard , Christoph Hellwig , linux-mips@linux-mips.org, ddaney@caviumnetworks.com, akpm@linux-foundation.org, ebiederm@xmission.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 Message-ID: <20100903100140.GA29187@linux-mips.org> References: <1283501734-6532-1-git-send-email-walle@corscience.de> <20100903084213.GA32339@lst.de> <4C80BC3A.7010406@corscience.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C80BC3A.7010406@corscience.de> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2490 Content-Length: 1070 Lines: 30 On Fri, Sep 03, 2010 at 11:13:30AM +0200, Bernhard Walle wrote: > >I guess the explanation is the one below : > > > >$ ./scripts/get_maintainer.pl -f arch/mips/kernel/scall64-n32.S > >Ralf Baechle > >David Daney > >Andrew Morton > >"Eric W. Biederman" > >Christoph Hellwig > >linux-mips@linux-mips.org > >linux-kernel@vger.kernel.org > > Yes, I just used that script and trusted the results. Sorry for that. I'm certainly not interested on getting cc'ed half of I2C patches or Itanium framebuffer drivers. The defaults are idiotic. Anybody who touched a file in the past year will get spammed. Throw in a --nogit to disable the history search and you get: Ralf Baechle linux-mips@linux-mips.org linux-kernel@vger.kernel.org cc'ing lkml is a bit pointless in many cases as well but the simplistic filename pattern system in MAINTAINERS doesn't allow entries entries to match only if no other previous entries are matching. Ralf From walle@corscience.de Fri Sep 3 13:27:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Sep 2010 13:27:40 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:59814 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491085Ab0ICL1h (ORCPT ); Fri, 3 Sep 2010 13:27:37 +0200 Received: from corscience.de (DSL01.212.114.252.242.ip-pool.NEFkom.net [212.114.252.242]) by mrelayeu.kundenserver.de (node=mreu0) with ESMTP (Nemesis) id 0MUAOE-1PIOyq2F98-00R2oP; Fri, 03 Sep 2010 13:27:26 +0200 Received: from [192.168.102.58] (unknown [192.168.102.58]) by corscience.de (Postfix) with ESMTP id 10FC751FA1; Fri, 3 Sep 2010 13:27:26 +0200 (CEST) Message-ID: <4C80DB9C.8060403@corscience.de> Date: Fri, 03 Sep 2010 13:27:24 +0200 From: Bernhard Walle User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100713 Thunderbird/3.0.6 MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 References: <1283501734-6532-1-git-send-email-walle@corscience.de> <20100903084213.GA32339@lst.de> <4C80BC3A.7010406@corscience.de> <20100903100140.GA29187@linux-mips.org> In-Reply-To: <20100903100140.GA29187@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Provags-ID: V02:K0:qPuc5Y8f3gR++0NuCwaWEf9AH4CK/3cwO8raOiGzX3K k10jLq63x4j6y+0vcH88RbKLi7vkJjD/BxBuOQC5fzZdhEBw4n sShmSpCv88N1Tuq6vXgiNks6ej3bMcYTWSAt/my8kgjuTxL6no AKUmctS6a5pbPpUepEgISBwW3dCoi5WdWaC0C0nyvxCo2MhFz4 xnUBLPUBrAUdD9bf3guBg== X-archive-position: 27717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: walle@corscience.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 2666 Content-Length: 394 Lines: 13 Am 03.09.2010 12:01, schrieb Ralf Baechle: > > I'm certainly not interested on getting cc'ed half of I2C patches or > Itanium framebuffer drivers. The defaults are idiotic. Anybody who > touched a file in the past year will get spammed. > > Throw in a --nogit to disable the history search and you get: Ok, I will use that in the future. But what about the patch itself? Regards, Bernhard From cernekee@gmail.com Tue Sep 7 06:14:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 06:14:35 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:44676 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1490963Ab0IGEOc (ORCPT ); Tue, 7 Sep 2010 06:14:32 +0200 Received: (qmail 29828 invoked from network); 7 Sep 2010 04:14:26 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 7 Sep 2010 04:14:26 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Mon, 06 Sep 2010 21:14:26 -0700 From: Kevin Cernekee Date: Mon, 6 Sep 2010 21:03:42 -0700 Subject: [PATCH 0/5] MIPS: HIGHMEM DMA on noncoherent MIPS32 processors To: Ralf Baechle Cc: , , , Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4954 Content-Length: 7895 Lines: 181 I had some time this weekend to revisit an old problem: http://www.linux-mips.org/archives/linux-mips/2010-05/msg00009.html PROBLEM #1: When testing Dezhong's patch, I found that un-kmapped pages could get passed into dma_map_sg(). The original patch did not handle this case. This resulted in serious DMA coherency issues on my system, along the lines of "/sbin/init segfaults on boot." I found that this calling sequence, seen during SATA disk I/O, was the culprit: [<8002b3d4>] dma_map_sg+0x2ac/0x2b8 [<802cdb70>] ata_qc_issue+0x274/0x37c [<802d383c>] ata_scsi_translate+0xb0/0x1e8 [<802d7274>] ata_scsi_queuecmd+0xc8/0x2b8 [<802b0630>] scsi_dispatch_cmd+0x118/0x2b8 [<802b6c64>] scsi_request_fn+0x420/0x4d8 [<80239550>] __blk_run_queue+0x84/0x19c [<802364a0>] elv_insert+0x158/0x2e4 [<8023a398>] __make_request+0x11c/0x4d0 [<80238144>] generic_make_request+0x348/0x4a0 [<80238330>] submit_bio+0x94/0x13c [<80114024>] mpage_bio_submit+0x30/0x40 [<80115a2c>] mpage_readpages+0x134/0x170 [<800a4fd4>] __do_page_cache_readahead+0x214/0x314 __do_page_cache_readahead() allocates a bunch of pages for the I/O requests, but I do not see them getting mapped to kernel addresses via kmap() / kmap_atomic(). This explains why (PageHighMem(page) && !kmap_high_get(page)) can be true. I do not think there is anything wrong with this behavior, so it seems like dma_map_sg() will need to handle it somehow. Looking at other architectures: The PPC approach (__dma_sync_page_highmem()) is to disable IRQs and call kmap_atomic() to create a temporary mapping for the page. Disabling IRQs is necessary because it is possible (but not required) for the dma_* functions to be invoked from interrupt context; it also disables preemption. kmap_atomic() guarantees a unique mapping per CPU. Interestingly, PPC does not use kmap_high_get() at all. The ARM approach (kmap_high_l1_vipt()) recognizes that it is not always desirable to keep IRQs disabled during DMA flushes, so the ARM maintainers implemented a sort of "reentrant kmap_atomic()" that allows multiple contexts to share the same pte by saving and restoring whatever was there prior to the DMA sync. Due to its use of kmap_high_get(), the ARM approach suffers from problem #2, below. It is also more complex and harder to test. I'm not sure how to recreate some of the worst corner cases, e.g. hardirq cacheflush interrupts a softirq cacheflush which interrupted a user cacheflush. Dezhong's patch was largely based on the ARM scheme, minus the kmap_high_l1_vipt() logic. I am sending an update to this patch which attempts to imitate the PPC approach instead. There is a considerable amount of reuse since both strategies require similar modifications to dma-default.c, in order to get that code to pass around "struct page" pointers rather than kseg0 addresses. PROBLEM #2: Consider this sequence: mm/highmem.c:kmap_high() mm/highmem.c:map_new_virtual() mm/highmem.c:flush_all_zero_pkmaps() arch/mips/kernel/smp.c:flush_tlb_kernel_range() kernel/softirq.c:on_each_cpu() kernel/smp.c:smp_call_function() The first thing kmap_high() does is lock_kmap(), which disables interrupts on kmap_high_get() architectures: #ifdef ARCH_NEEDS_KMAP_HIGH_GET #define lock_kmap() spin_lock_irq(&kmap_lock) ... #else #define lock_kmap() spin_lock(&kmap_lock) #endif smp_call_function() may not be called with interrupts disabled: * You must not call this function with disabled interrupts or from a * hardware interrupt handler or from a bottom half handler. So, on SMP, we get warnings like: ------------[ cut here ]------------ WARNING: at kernel/smp.c:293 smp_call_function_single+0x17c/0x260() Modules linked in: Call Trace: [<800160f0>] dump_stack+0x8/0x34 [<8004a544>] warn_slowpath_common+0x78/0xa4 [<8004a588>] warn_slowpath_null+0x18/0x24 [<800876e4>] smp_call_function_single+0x17c/0x260 [<80087ca8>] smp_call_function+0x28/0x38 [<800531b4>] on_each_cpu+0x1c/0x80 [<80026d20>] flush_tlb_kernel_range+0x28/0x34 [<800b95f4>] kmap_high+0x1dc/0x270 [<8002a570>] __kmap+0x60/0x7c [<801f15b4>] do_readpage+0x68/0x540 [<801f218c>] ubifs_write_begin+0xbc/0x53c [<8009a558>] generic_perform_write+0xd4/0x1f0 [<8009a6e4>] generic_file_buffered_write+0x70/0xbc [<8009dd3c>] __generic_file_aio_write+0x2fc/0x600 [<8009e0b0>] generic_file_aio_write+0x70/0xf4 [<800da864>] do_sync_write+0xc4/0x13c [<800db50c>] vfs_write+0xc0/0x168 [<800db6ac>] sys_write+0x4c/0xa4 [<80003d9c>] stack_done+0x20/0x3c ---[ end trace 8abde6adefbcc81f ]--- I did some digging and found that ARM runs into the same problem. For processors that cannot "broadcast" TLB operations, SMP + HIGHMEM are deemed incompatible: http://www.spinics.net/lists/arm-kernel/msg74563.html So, I would opt for the PPC approach in order to avoid this conflict. Disabling SMP will result in a much nastier performance problem than blocking interrupts during flushes. PROBLEM #3: Regarding David's flush_data_cache_page() concern: http://www.linux-mips.org/archives/linux-mips/2008-03/msg00011.html There are at least 4 reasons to flush the cache: 1) Boot time (cache contents are undefined at reset) 2) DMA coherence 3) I$/D$ coherence (self-modifying code) 4) Zap cache aliases My interpretation of the code is that flush_dcache_page() is only called for #3 and #4: #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 static inline void flush_dcache_page(struct page *page) { if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) __flush_dcache_page(page); } The fact that the L2 / board cache is not flushed in c-r4k.c leads me to believe that #2 is not an intended use of this function: static inline void local_r4k_flush_data_cache_page(void * addr) { r4k_blast_dcache_page((unsigned long) addr); } Besides, we already have a standard, documented DMA API that should be used instead. Since this is not boot time, and HIGHMEM is incompatible with cache aliases, that leaves #3 as a possible issue. Is this function ever used for I$/D$ coherence? I should note that ARM has special handling in __flush_dcache_page() for high pages. IIRC, at one point they tried to support HIGHMEM on systems with cache aliases, before deciding it was not feasible. Maybe this code is just a relic - or maybe it's really needed for something. From cernekee@gmail.com Tue Sep 7 06:15:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 06:15:19 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:44831 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1490963Ab0IGEPN (ORCPT ); Tue, 7 Sep 2010 06:15:13 +0200 Received: (qmail 32572 invoked from network); 7 Sep 2010 04:15:09 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 7 Sep 2010 04:15:09 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Mon, 06 Sep 2010 21:15:09 -0700 From: Kevin Cernekee Date: Mon, 6 Sep 2010 21:03:44 -0700 Subject: [PATCH 1/5] MIPS: HIGHMEM DMA on noncoherent MIPS32 processors To: Ralf Baechle Cc: , , , Message-Id: <7d28a475591d9522bd1841a95fe21260@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4955 Content-Length: 9200 Lines: 310 The MIPS DMA coherency functions do not work properly (i.e. kernel oops) when HIGHMEM pages are passed in as arguments. This patch uses the PPC approach of calling kmap_atomic() with IRQs disabled to temporarily map high pages, in order to flush them out to memory. Signed-off-by: Dezhong Diao Signed-off-by: Kevin Cernekee --- arch/mips/mm/dma-default.c | 159 ++++++++++++++++++++++---------------------- 1 files changed, 80 insertions(+), 79 deletions(-) diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 469d401..3f23952 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -15,18 +15,18 @@ #include #include #include +#include #include #include #include -static inline unsigned long dma_addr_to_virt(struct device *dev, +static inline struct page *dma_addr_to_page(struct device *dev, dma_addr_t dma_addr) { - unsigned long addr = plat_dma_addr_to_phys(dev, dma_addr); - - return (unsigned long)phys_to_virt(addr); + return pfn_to_page( + plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); } /* @@ -153,20 +153,20 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, EXPORT_SYMBOL(dma_free_coherent); -static inline void __dma_sync(unsigned long addr, size_t size, +static inline void __dma_sync_virtual(void *addr, size_t size, enum dma_data_direction direction) { switch (direction) { case DMA_TO_DEVICE: - dma_cache_wback(addr, size); + dma_cache_wback((unsigned long)addr, size); break; case DMA_FROM_DEVICE: - dma_cache_inv(addr, size); + dma_cache_inv((unsigned long)addr, size); break; case DMA_BIDIRECTIONAL: - dma_cache_wback_inv(addr, size); + dma_cache_wback_inv((unsigned long)addr, size); break; default: @@ -174,13 +174,53 @@ static inline void __dma_sync(unsigned long addr, size_t size, } } +/* + * A single sg entry may refer to multiple physically contiguous + * pages. But we still need to process highmem pages individually. + * If highmem is not configured then the bulk of this loop gets + * optimized out. + */ +static inline void __dma_sync(struct page *page, + unsigned long offset, size_t size, enum dma_data_direction direction) +{ + size_t left = size; + + BUG_ON(direction == DMA_NONE); + + do { + size_t len = left; + + if (PageHighMem(page)) { + unsigned long flags; + void *addr; + + if (offset + len > PAGE_SIZE) { + if (offset >= PAGE_SIZE) { + page += offset >> PAGE_SHIFT; + offset &= ~PAGE_MASK; + } + len = PAGE_SIZE - offset; + } + + local_irq_save(flags); + addr = kmap_atomic(page, KM_SYNC_DCACHE); + __dma_sync_virtual(addr + offset, len, direction); + kunmap_atomic(addr, KM_SYNC_DCACHE); + local_irq_restore(flags); + } else + __dma_sync_virtual(page_address(page) + offset, + size, direction); + offset = 0; + page++; + left -= len; + } while (left); +} + dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, enum dma_data_direction direction) { - unsigned long addr = (unsigned long) ptr; - if (!plat_device_is_coherent(dev)) - __dma_sync(addr, size, direction); + __dma_sync_virtual(ptr, size, direction); return plat_map_dma_mem(dev, ptr, size); } @@ -191,8 +231,8 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction) { if (cpu_is_noncoherent_r10000(dev)) - __dma_sync(dma_addr_to_virt(dev, dma_addr), size, - direction); + __dma_sync(dma_addr_to_page(dev, dma_addr), + (dma_addr & ~PAGE_MASK), size, direction); plat_unmap_dma_mem(dev, dma_addr, size, direction); } @@ -204,16 +244,12 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, { int i; - BUG_ON(direction == DMA_NONE); - for (i = 0; i < nents; i++, sg++) { - unsigned long addr; - - addr = (unsigned long) sg_virt(sg); - if (!plat_device_is_coherent(dev) && addr) - __dma_sync(addr, sg->length, direction); - sg->dma_address = plat_map_dma_mem(dev, - (void *)addr, sg->length); + if (!plat_device_is_coherent(dev)) + __dma_sync(sg_page(sg), sg->offset, sg->length, + direction); + sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + + sg->offset; } return nents; @@ -224,14 +260,8 @@ EXPORT_SYMBOL(dma_map_sg); dma_addr_t dma_map_page(struct device *dev, struct page *page, unsigned long offset, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - - if (!plat_device_is_coherent(dev)) { - unsigned long addr; - - addr = (unsigned long) page_address(page) + offset; - __dma_sync(addr, size, direction); - } + if (!plat_device_is_coherent(dev)) + __dma_sync(page, offset, size, direction); return plat_map_dma_mem_page(dev, page) + offset; } @@ -241,18 +271,13 @@ EXPORT_SYMBOL(dma_map_page); void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, enum dma_data_direction direction) { - unsigned long addr; int i; - BUG_ON(direction == DMA_NONE); - for (i = 0; i < nhwentries; i++, sg++) { if (!plat_device_is_coherent(dev) && - direction != DMA_TO_DEVICE) { - addr = (unsigned long) sg_virt(sg); - if (addr) - __dma_sync(addr, sg->length, direction); - } + direction != DMA_TO_DEVICE) + __dma_sync(sg_page(sg), sg->offset, sg->length, + direction); plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction); } } @@ -262,14 +287,9 @@ EXPORT_SYMBOL(dma_unmap_sg); void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - - if (cpu_is_noncoherent_r10000(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr, size, direction); - } + if (cpu_is_noncoherent_r10000(dev)) + __dma_sync(dma_addr_to_page(dev, dma_handle), + (dma_handle & ~PAGE_MASK), size, direction); } EXPORT_SYMBOL(dma_sync_single_for_cpu); @@ -277,15 +297,10 @@ EXPORT_SYMBOL(dma_sync_single_for_cpu); void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); - if (!plat_device_is_coherent(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr, size, direction); - } + if (!plat_device_is_coherent(dev)) + __dma_sync(dma_addr_to_page(dev, dma_handle), + (dma_handle & ~PAGE_MASK), size, direction); } EXPORT_SYMBOL(dma_sync_single_for_device); @@ -293,14 +308,9 @@ EXPORT_SYMBOL(dma_sync_single_for_device); void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - - if (cpu_is_noncoherent_r10000(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr + offset, size, direction); - } + if (cpu_is_noncoherent_r10000(dev)) + __dma_sync(dma_addr_to_page(dev, dma_handle), offset, size, + direction); } EXPORT_SYMBOL(dma_sync_single_range_for_cpu); @@ -308,15 +318,10 @@ EXPORT_SYMBOL(dma_sync_single_range_for_cpu); void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); - if (!plat_device_is_coherent(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr + offset, size, direction); - } + if (!plat_device_is_coherent(dev)) + __dma_sync(dma_addr_to_page(dev, dma_handle), offset, size, + direction); } EXPORT_SYMBOL(dma_sync_single_range_for_device); @@ -326,13 +331,11 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, { int i; - BUG_ON(direction == DMA_NONE); - /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) { if (cpu_is_noncoherent_r10000(dev)) - __dma_sync((unsigned long)page_address(sg_page(sg)), - sg->length, direction); + __dma_sync(sg_page(sg), sg->offset, sg->length, + direction); } } @@ -343,13 +346,11 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele { int i; - BUG_ON(direction == DMA_NONE); - /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) { if (!plat_device_is_coherent(dev)) - __dma_sync((unsigned long)page_address(sg_page(sg)), - sg->length, direction); + __dma_sync(sg_page(sg), sg->offset, sg->length, + direction); } } @@ -376,7 +377,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) - __dma_sync((unsigned long)vaddr, size, direction); + __dma_sync_virtual(vaddr, size, direction); } EXPORT_SYMBOL(dma_cache_sync); -- 1.7.0.4 From cernekee@gmail.com Tue Sep 7 06:15:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 06:15:59 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:44959 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1490963Ab0IGEPz (ORCPT ); Tue, 7 Sep 2010 06:15:55 +0200 Received: (qmail 3663 invoked from network); 7 Sep 2010 04:15:52 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 7 Sep 2010 04:15:52 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Mon, 06 Sep 2010 21:15:52 -0700 From: Kevin Cernekee Date: Mon, 6 Sep 2010 21:03:46 -0700 Subject: [PATCH 2/5] MIPS: sync after cacheflush To: Ralf Baechle Cc: , Message-Id: <72d10d33beedb9d877a7373dafc04a75@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4956 Content-Length: 1882 Lines: 68 On processors with deep write buffers, it is likely that many cycles will pass between a CACHE instruction and the time the data actually gets written out to DRAM. Add a SYNC instruction to ensure that the buffers get emptied before the flush functions return. Actual problem seen in the wild: 1) dma_alloc_coherent() allocates cached memory 2) memset() is called to clear the new pages 3) dma_cache_wback_inv() is called to flush the zero data out to memory 4) dma_alloc_coherent() returns an uncached (kseg1) pointer to the freshly allocated pages 5) Caller writes data through the kseg1 pointer 6) Buffered writeback data finally gets flushed out to DRAM 7) Part of caller's data is inexplicably zeroed out This patch adds SYNC between steps 3 and 4, which fixed the problem. Signed-off-by: Kevin Cernekee --- arch/mips/mm/c-r4k.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 6721ee2..05c3de3 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -605,6 +605,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) r4k_blast_scache(); else blast_scache_range(addr, addr + size); + __sync(); return; } @@ -621,6 +622,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) } bc_wback_inv(addr, size); + __sync(); } static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) @@ -648,6 +650,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) (addr + size - 1) & almask); blast_inv_scache_range(addr, addr + size); } + __sync(); return; } @@ -664,6 +667,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) } bc_inv(addr, size); + __sync(); } #endif /* CONFIG_DMA_NONCOHERENT */ -- 1.7.0.4 From cernekee@gmail.com Tue Sep 7 06:16:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 06:16:26 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:45053 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1490963Ab0IGEQW (ORCPT ); Tue, 7 Sep 2010 06:16:22 +0200 Received: (qmail 5908 invoked from network); 7 Sep 2010 04:16:19 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 7 Sep 2010 04:16:19 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Mon, 06 Sep 2010 21:16:19 -0700 From: Kevin Cernekee Date: Mon, 6 Sep 2010 21:03:48 -0700 Subject: [PATCH RESEND 3/5] MIPS: pfn_valid() is broken on low memory HIGHMEM systems To: Ralf Baechle Cc: , Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4957 Content-Length: 1395 Lines: 45 pfn_valid() compares the PFN to max_mapnr: __pfn >= min_low_pfn && __pfn < max_mapnr; On HIGHMEM kernels, highend_pfn is used to set the value of max_mapnr. Unfortunately, highend_pfn is left at zero if the system does not actually have enough RAM to reach into the HIGHMEM range. This causes pfn_valid() to always return false, and when debug checks are enabled the kernel will fail catastrophically: Memory: 22432k/32768k available (2249k kernel code, 10336k reserved, 653k data, 1352k init, 0k highmem) NR_IRQS:128 kfree_debugcheck: out of range ptr 81c02900h. Kernel bug detected[#1]: Cpu 0 $ 0 : 00000000 10008400 00000034 00000000 $ 4 : 8003e160 802a0000 8003e160 00000000 $ 8 : 00000000 0000003e 00000747 00000747 ... On such a configuration, max_low_pfn should be used to set max_mapnr. This was seen on 2.6.34. Signed-off-by: Kevin Cernekee --- arch/mips/mm/init.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 2efcbd2..18183a4 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -370,7 +370,7 @@ void __init mem_init(void) #ifdef CONFIG_DISCONTIGMEM #error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet" #endif - max_mapnr = highend_pfn; + max_mapnr = highend_pfn ? : max_low_pfn; #else max_mapnr = max_low_pfn; #endif -- 1.7.0.4 From cernekee@gmail.com Tue Sep 7 06:16:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 06:16:52 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:45082 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491118Ab0IGEQo (ORCPT ); Tue, 7 Sep 2010 06:16:44 +0200 Received: (qmail 7846 invoked from network); 7 Sep 2010 04:16:41 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 7 Sep 2010 04:16:41 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Mon, 06 Sep 2010 21:16:41 -0700 From: Kevin Cernekee Date: Mon, 6 Sep 2010 21:03:50 -0700 Subject: [PATCH 4/5] MIPS: Honor L2 bypass bit To: Ralf Baechle Cc: , Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27722 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4958 Content-Length: 680 Lines: 27 If CP0 CONFIG2 bit 12 (L2B) is set, the L2 cache is disabled and therefore Linux should not attempt to use it. Signed-off-by: Kevin Cernekee --- arch/mips/mm/sc-mips.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 5ab5fa8..d072b25 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -79,6 +79,11 @@ static inline int __init mips_sc_probe(void) return 0; config2 = read_c0_config2(); + + /* bypass bit */ + if (config2 & (1 << 12)) + return 0; + tmp = (config2 >> 4) & 0x0f; if (0 < tmp && tmp <= 7) c->scache.linesz = 2 << tmp; -- 1.7.0.4 From cernekee@gmail.com Tue Sep 7 06:17:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 06:17:30 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:45154 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491157Ab0IGERZ (ORCPT ); Tue, 7 Sep 2010 06:17:25 +0200 Received: (qmail 11306 invoked from network); 7 Sep 2010 04:17:22 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 7 Sep 2010 04:17:22 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Mon, 06 Sep 2010 21:17:22 -0700 From: Kevin Cernekee Date: Mon, 6 Sep 2010 21:03:52 -0700 Subject: [PATCH 5/5] MIPS: Move FIXADDR_TOP into spaces.h To: Ralf Baechle Cc: , Message-Id: User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27723 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 4960 Content-Length: 4477 Lines: 130 Memory maps and addressing quirks are normally defined in . There are already three targets that need to override FIXADDR_TOP, and others exist. This will be a cleaner approach than adding lots of ifdefs in fixmap.h . Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/fixmap.h | 10 +--------- arch/mips/include/asm/mach-bcm63xx/spaces.h | 17 +++++++++++++++++ arch/mips/include/asm/mach-generic/spaces.h | 4 ++++ arch/mips/include/asm/mach-tx39xx/spaces.h | 17 +++++++++++++++++ arch/mips/include/asm/mach-tx49xx/spaces.h | 17 +++++++++++++++++ 5 files changed, 56 insertions(+), 9 deletions(-) create mode 100644 arch/mips/include/asm/mach-bcm63xx/spaces.h create mode 100644 arch/mips/include/asm/mach-tx39xx/spaces.h create mode 100644 arch/mips/include/asm/mach-tx49xx/spaces.h diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h index 0b89b83..98bcc98 100644 --- a/arch/mips/include/asm/fixmap.h +++ b/arch/mips/include/asm/fixmap.h @@ -14,6 +14,7 @@ #define _ASM_FIXMAP_H #include +#include #ifdef CONFIG_HIGHMEM #include #include @@ -67,15 +68,6 @@ enum fixed_addresses { * the start of the fixmap, and leave one page empty * at the top of mem.. */ -#ifdef CONFIG_BCM63XX -#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000) -#else -#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX) -#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000)) -#else -#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) -#endif -#endif #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) diff --git a/arch/mips/include/asm/mach-bcm63xx/spaces.h b/arch/mips/include/asm/mach-bcm63xx/spaces.h new file mode 100644 index 0000000..cb8d2ab --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/spaces.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_BCM63XX_SPACES_H +#define _ASM_BCM63XX_SPACES_H + +#define FIXADDR_TOP _AC(0xff000000, UL) + +#include + +#endif /* __ASM_BCM63XX_SPACES_H */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index c9fa4b1..77c36ee 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -82,4 +82,8 @@ #define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET) #endif +#ifndef FIXADDR_TOP +#define FIXADDR_TOP _AC(0xfffe0000, UL) +#endif + #endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/arch/mips/include/asm/mach-tx39xx/spaces.h b/arch/mips/include/asm/mach-tx39xx/spaces.h new file mode 100644 index 0000000..0cf322b --- /dev/null +++ b/arch/mips/include/asm/mach-tx39xx/spaces.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_TX39XX_SPACES_H +#define _ASM_TX39XX_SPACES_H + +#define FIXADDR_TOP _AC(0xfefe0000, UL) + +#include + +#endif /* __ASM_TX39XX_SPACES_H */ diff --git a/arch/mips/include/asm/mach-tx49xx/spaces.h b/arch/mips/include/asm/mach-tx49xx/spaces.h new file mode 100644 index 0000000..455e042 --- /dev/null +++ b/arch/mips/include/asm/mach-tx49xx/spaces.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_TX49XX_SPACES_H +#define _ASM_TX49XX_SPACES_H + +#define FIXADDR_TOP _AC(0xfefe0000, UL) + +#include + +#endif /* __ASM_TX49XX_SPACES_H */ -- 1.7.0.4 From sshtylyov@mvista.com Tue Sep 7 11:13:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 11:13:10 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:33589 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491090Ab0IGJNG (ORCPT ); Tue, 7 Sep 2010 11:13:06 +0200 Received: by eye22 with SMTP id 22so2531599eye.36 for ; Tue, 07 Sep 2010 02:13:06 -0700 (PDT) Received: by 10.213.13.142 with SMTP id c14mr1695032eba.84.1283850786103; Tue, 07 Sep 2010 02:13:06 -0700 (PDT) Received: from [192.168.2.2] (ppp91-77-55-37.pppoe.mtu-net.ru [91.77.55.37]) by mx.google.com with ESMTPS id z55sm9557319eeh.15.2010.09.07.02.13.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 07 Sep 2010 02:13:04 -0700 (PDT) Message-ID: <4C8601C0.40001@mvista.com> Date: Tue, 07 Sep 2010 13:11:28 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.8) Gecko/20100802 Thunderbird/3.1.2 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , dediao@cisco.com, dvomlehn@cisco.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/5] MIPS: HIGHMEM DMA on noncoherent MIPS32 processors References: <7d28a475591d9522bd1841a95fe21260@localhost> In-Reply-To: <7d28a475591d9522bd1841a95fe21260@localhost> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 27724 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5082 Content-Length: 1776 Lines: 51 Hello. On 07-09-2010 8:03, Kevin Cernekee wrote: > The MIPS DMA coherency functions do not work properly (i.e. kernel oops) > when HIGHMEM pages are passed in as arguments. This patch uses the PPC > approach of calling kmap_atomic() with IRQs disabled to temporarily map > high pages, in order to flush them out to memory. > Signed-off-by: Dezhong Diao > Signed-off-by: Kevin Cernekee > --- > arch/mips/mm/dma-default.c | 159 ++++++++++++++++++++++---------------------- > 1 files changed, 80 insertions(+), 79 deletions(-) > diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c > index 469d401..3f23952 100644 > --- a/arch/mips/mm/dma-default.c > +++ b/arch/mips/mm/dma-default.c [...] > @@ -191,8 +231,8 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, > enum dma_data_direction direction) > { > if (cpu_is_noncoherent_r10000(dev)) > - __dma_sync(dma_addr_to_virt(dev, dma_addr), size, > - direction); > + __dma_sync(dma_addr_to_page(dev, dma_addr), > + (dma_addr & ~PAGE_MASK), size, direction); Parens are not needed here. > @@ -277,15 +297,10 @@ EXPORT_SYMBOL(dma_sync_single_for_cpu); > void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, > size_t size, enum dma_data_direction direction) > { > - BUG_ON(direction == DMA_NONE); > - > plat_extra_sync_for_device(dev); > - if (!plat_device_is_coherent(dev)) { > - unsigned long addr; > - > - addr = dma_addr_to_virt(dev, dma_handle); > - __dma_sync(addr, size, direction); > - } > + if (!plat_device_is_coherent(dev)) > + __dma_sync(dma_addr_to_page(dev, dma_handle), > + (dma_handle & ~PAGE_MASK), size, direction); Here as well... WBR, Sergei From naren.mehra@gmail.com Tue Sep 7 13:34:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 13:34:24 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:61499 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490978Ab0IGLeV (ORCPT ); Tue, 7 Sep 2010 13:34:21 +0200 Received: by wyb38 with SMTP id 38so6391879wyb.36 for ; Tue, 07 Sep 2010 04:34:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=lDmUtaW36SPyzY862UeLMWwJzpR740yTX32Vlb3q3PY=; b=bKZhaD34xz7NHSTGBHWDP6gAO4r+qNom365FRKncbVLh9J6U9JBkuETaRBwJ2z5JEJ DbPdeGEg/DDLzqbTT2zUtBD//Ask+9xZRlo+3YQcSYC/tNBGLWU/EK5XH5+Ts76u8fFq g5RjW6MjEvy1GMCnczMLoBecU0h+ZZzQaH0Gg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=sGB/+Gdmb2UPeM7URlZL+mkZcOGZUjdlt7Yy6et71JGJluCB+mC03D2/e9wbM54rgx Vmkqts8wDu71AxwLtBM2x5ztXGVORNW+T6af/UslLmOHNmvbWgcCxX9XSflpmZF5WqyJ Rs70pOJdczQIrr/hNRe7aF7xLpI3ileKPFzVY= MIME-Version: 1.0 Received: by 10.216.59.131 with SMTP id s3mr1304000wec.71.1283859255791; Tue, 07 Sep 2010 04:34:15 -0700 (PDT) Received: by 10.216.29.148 with HTTP; Tue, 7 Sep 2010 04:34:15 -0700 (PDT) Date: Tue, 7 Sep 2010 17:04:15 +0530 Message-ID: Subject: Memory regression test tool on MIPS needed From: naren.mehra@gmail.com To: msundius@cisco.com, dvomlehn@cisco.com, ralf@linux-mips.org, linux-mips@linux-mips.org, sshtylyov@mvista.com Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27725 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: naren.mehra@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5173 Content-Length: 338 Lines: 11 Hi, I have recently applied the sparsemem patch on my mips board. Now I intend to write a detail analysis with its performance before and after the patch and whether it has broken anything in the memory management system. For that I need a memory regression tool that works on mips board. Can anybody help me with that ? Regards, Naren From brian.foster@innova-card.com Tue Sep 7 14:05:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 14:05:52 +0200 (CEST) Received: from 6-61.252-81.static-ip.oleane.fr ([81.252.61.6]:59332 "EHLO zebulon.innova-card.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1490978Ab0IGMFs convert rfc822-to-8bit (ORCPT ); Tue, 7 Sep 2010 14:05:48 +0200 Received: from [88.173.184.45] ([88.173.184.45]) by zebulon.innova-card.com; Tue, 7 Sep 2010 14:04:37 +0200 To: naren.mehra@gmail.com Cc: msundius@cisco.com, dvomlehn@cisco.com, ralf@linux-mips.org, linux-mips@linux-mips.org, sshtylyov@mvista.com From: "Brian FOSTER" Subject: Re: Memory regression test tool on MIPS needed In-Reply-To: AANLkTikya-sDVRLpPisSWs15EU_zphm==z0hEB45tLH5@mail.gmail.com Message-ID: <20100907120437.a3d0bb0d@zebulon.innova-card.com> Date: Tue, 07 Sep 2010 14:04:37 +0200 X-User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.8) Gecko/20100723 Ubuntu/9.10 (karmic) Firefox/3.6.8 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-archive-position: 27726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5184 Content-Length: 846 Lines: 26 > Sent: Tue, 07 Sep 2010 13:34:15 +0200 > Subject: Memory regression test tool on MIPS needed > From: naren.mehra@gmail.com > To: msundius@cisco.com, dvomlehn@cisco.com, ralf@linux-mips.org, > linux-mips@linux-mips.org, sshtylyov@mvista.com > > Hi, > > I have recently applied the sparsemem patch on my mips board. > Now I intend to write a detail analysis with its performance before > and after the patch and whether it has broken anything in the memory > management system. > For that I need a memory regression tool that works on mips board. > Can anybody help me with that ? Naren, It may or may not be helpful, but take a look at ‘memtester’, http://pyropus.ca/software/memtester/ (It is also in BuildRoot.) We've successfully used v4.12 as part the validation of a H/W memory controller on a new SoC. cheers! -blf- From anemo@mba.ocn.ne.jp Tue Sep 7 15:13:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 15:13:14 +0200 (CEST) Received: from mv-drv-hcb003.ocn.ad.jp ([118.23.109.133]:50455 "EHLO mv-drv-hcb003.ocn.ad.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491018Ab0IGNNL (ORCPT ); Tue, 7 Sep 2010 15:13:11 +0200 Received: from vcmba.ocn.ne.jp (localhost.localdomain [127.0.0.1]) by mv-drv-hcb003.ocn.ad.jp (Postfix) with ESMTP id 5F94756421D; Tue, 7 Sep 2010 22:13:06 +0900 (JST) Received: from localhost (softbank221040169135.bbtec.net [221.40.169.135]) by vcmba.ocn.ne.jp (Postfix) with ESMTP; Tue, 7 Sep 2010 22:13:06 +0900 (JST) Date: Tue, 07 Sep 2010 22:13:07 +0900 (JST) Message-Id: <20100907.221307.39158422.anemo@mba.ocn.ne.jp> To: cernekee@gmail.com Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/5] MIPS: Move FIXADDR_TOP into spaces.h From: Atsushi Nemoto In-Reply-To: References: X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-archive-position: 27727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5229 Content-Length: 379 Lines: 13 On Mon, 6 Sep 2010 21:03:52 -0700, Kevin Cernekee wrote: > -#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) ... > +#define FIXADDR_TOP _AC(0xfffe0000, UL) For 64-bit kernel, FIXADDR_TOP should be 0xfffffffffffe0000UL not 0x00000000fffe0000UL. The magical casts are used to sign-extend the address. Please do not drop them. --- Atsushi Nemoto From cernekee@gmail.com Tue Sep 7 22:09:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Sep 2010 22:10:04 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:35508 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491157Ab0IGUJ7 (ORCPT ); Tue, 7 Sep 2010 22:09:59 +0200 Received: (qmail 19738 invoked from network); 7 Sep 2010 20:09:55 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 7 Sep 2010 20:09:55 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Tue, 07 Sep 2010 13:09:55 -0700 From: Kevin Cernekee Date: Tue, 7 Sep 2010 12:59:15 -0700 Subject: [PATCH v2 5/5] MIPS: Move FIXADDR_TOP into spaces.h To: Ralf Baechle Cc: Atsushi Nemoto , , Message-Id: <55645e13fcf442f6641b3eb187cab302@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27728 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5666 Content-Length: 4553 Lines: 130 Memory maps and addressing quirks are normally defined in . There are already three targets that need to override FIXADDR_TOP, and others exist. This will be a cleaner approach than adding lots of ifdefs in fixmap.h . Signed-off-by: Kevin Cernekee --- arch/mips/include/asm/fixmap.h | 10 +--------- arch/mips/include/asm/mach-bcm63xx/spaces.h | 17 +++++++++++++++++ arch/mips/include/asm/mach-generic/spaces.h | 4 ++++ arch/mips/include/asm/mach-tx39xx/spaces.h | 17 +++++++++++++++++ arch/mips/include/asm/mach-tx49xx/spaces.h | 17 +++++++++++++++++ 5 files changed, 56 insertions(+), 9 deletions(-) create mode 100644 arch/mips/include/asm/mach-bcm63xx/spaces.h create mode 100644 arch/mips/include/asm/mach-tx39xx/spaces.h create mode 100644 arch/mips/include/asm/mach-tx49xx/spaces.h diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h index 0b89b83..98bcc98 100644 --- a/arch/mips/include/asm/fixmap.h +++ b/arch/mips/include/asm/fixmap.h @@ -14,6 +14,7 @@ #define _ASM_FIXMAP_H #include +#include #ifdef CONFIG_HIGHMEM #include #include @@ -67,15 +68,6 @@ enum fixed_addresses { * the start of the fixmap, and leave one page empty * at the top of mem.. */ -#ifdef CONFIG_BCM63XX -#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000) -#else -#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX) -#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000)) -#else -#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) -#endif -#endif #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) diff --git a/arch/mips/include/asm/mach-bcm63xx/spaces.h b/arch/mips/include/asm/mach-bcm63xx/spaces.h new file mode 100644 index 0000000..61e750f --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/spaces.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_BCM63XX_SPACES_H +#define _ASM_BCM63XX_SPACES_H + +#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000) + +#include + +#endif /* __ASM_BCM63XX_SPACES_H */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index c9fa4b1..d7a9efd 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -82,4 +82,8 @@ #define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET) #endif +#ifndef FIXADDR_TOP +#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) +#endif + #endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/arch/mips/include/asm/mach-tx39xx/spaces.h b/arch/mips/include/asm/mach-tx39xx/spaces.h new file mode 100644 index 0000000..151fe7a --- /dev/null +++ b/arch/mips/include/asm/mach-tx39xx/spaces.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_TX39XX_SPACES_H +#define _ASM_TX39XX_SPACES_H + +#define FIXADDR_TOP ((unsigned long)(long)(int)0xfefe0000) + +#include + +#endif /* __ASM_TX39XX_SPACES_H */ diff --git a/arch/mips/include/asm/mach-tx49xx/spaces.h b/arch/mips/include/asm/mach-tx49xx/spaces.h new file mode 100644 index 0000000..0cb10a6 --- /dev/null +++ b/arch/mips/include/asm/mach-tx49xx/spaces.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_TX49XX_SPACES_H +#define _ASM_TX49XX_SPACES_H + +#define FIXADDR_TOP ((unsigned long)(long)(int)0xfefe0000) + +#include + +#endif /* __ASM_TX49XX_SPACES_H */ -- 1.7.0.4 From gerg@snapgear.com Wed Sep 8 08:00:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Sep 2010 08:00:32 +0200 (CEST) Received: from dalsmrelay2.nai.com ([205.227.136.216]:49091 "HELO dalsmrelay2.nai.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1490945Ab0IHGA2 (ORCPT ); Wed, 8 Sep 2010 08:00:28 +0200 Received: from (unknown [10.64.5.51]) by dalsmrelay2.nai.com with smtp id 1e3f_00de_5ce01d0a_bb0e_11df_b4bd_00219b929abd; Wed, 08 Sep 2010 06:00:20 +0000 Received: from dalexbr1.corp.nai.org (161.69.111.81) by DALEXHT1.corp.nai.org (10.64.5.51) with Microsoft SMTP Server id 8.2.254.0; Wed, 8 Sep 2010 00:50:58 -0500 Received: from sncexbr1.corp.nai.org ([161.69.5.246]) by dalexbr1.corp.nai.org with Microsoft SMTPSVC(6.0.3790.3959); Wed, 8 Sep 2010 00:50:57 -0500 Received: from STPSMTP01.scur.com ([10.96.96.163]) by sncexbr1.corp.nai.org with Microsoft SMTPSVC(6.0.3790.3959); Tue, 7 Sep 2010 22:50:56 -0700 Received: from cyberguard.com.au ([10.46.129.16]) by STPSMTP01.scur.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 8 Sep 2010 00:50:55 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by bne.snapgear.com (Postfix) with ESMTP id 8CD45EBAB4; Wed, 8 Sep 2010 15:50:54 +1000 (EST) X-Virus-Scanned: amavisd-new at snapgear.com Received: from bne.snapgear.com ([127.0.0.1]) by localhost (bne.snapgear.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HQQB+XihlkWu; Wed, 8 Sep 2010 15:50:46 +1000 (EST) Received: from snapgear.com (bnelabfw.scur.com [10.46.129.16]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by bne.snapgear.com (Postfix) with ESMTP; Wed, 8 Sep 2010 15:50:46 +1000 (EST) Received: from goober.internal.moreton.com.au (localhost [127.0.0.1]) by snapgear.com (8.14.3/8.14.3/Debian-9ubuntu1) with ESMTP id o885onrY014189; Wed, 8 Sep 2010 15:50:49 +1000 Received: (from gerg@localhost) by goober.internal.moreton.com.au (8.14.3/8.14.3/Submit) id o885ohjD014188; Wed, 8 Sep 2010 15:50:43 +1000 Date: Wed, 8 Sep 2010 15:50:43 +1000 From: Greg Ungerer Message-ID: <201009080550.o885ohjD014188@goober.internal.moreton.com.au> CC: Subject: [PATCH] mips: fix start of free memory when using initrd To: X-Mailer: mail (GNU Mailutils 2.0) X-OriginalArrivalTime: 08 Sep 2010 05:50:56.0231 (UTC) FILETIME=[CE315F70:01CB4F19] MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gerg@snapgear.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 5981 Content-Length: 3345 Lines: 84 Hi All, I have a typical Cavium/Octeon (5010) based system, that I sometimes use a kernel and traditional initrd setup on. In a typical layout the kernel is loaded into low physical RAM (via boot loader) and the initrd is loaded somewhere above it. Everything runs fine, but the region occupied by the initrd is effectively lost from usable RAM. For example, with these boot args "rd_start=0x84000000 rd_size=0x00206000" where the initrd is loaded at 64MB (and is just over 2MB in size) I end up with: Memory: 59620k/127152k available (2193k kernel code, 67532k reserved, 563k data, 192k init, 0k highmem) Ouch! A lot of RAM not usable. It looks to me that the logic of setting the bootmem is not quite right for the initrd case. If I patch arch/mips/kernel/setup.c with the patch below I get all that memory back, and everything seems to work: Memory: 121044k/127152k available (2193k kernel code, 6108k reserved, 563k data, 192k init, 0k highmem) The patch just sets the bootmem map to always be the end of the kernel. Then the bootmem reserve initrd logic does its work as expected. (A little more cleaning up could be done I guess, but I want to know the approach is correct first :-) Am I mis-understanding how this is supposed to work? Other architectures seem to set the bootmem to the end of the kernel. Sparc has some extra checks to make sure that the bootmem setup data doesn't overwrite the initrd, but otherwise is similar. Regards Greg mips: fix start of free memory when using initrd Currently when using an initrd on a MIPS system the start of the bootmem region of memory is set to the larger of the end of the kernel bss region (_end) or the end of the initrd. In a typical memory layout where the initrd is at some address above the kernel image this means that the start of the bootmem region will be the end of the initrd. But when we are done processing/loading the initrd we have no way to reclaim the memory region it occupied, and we lose a large chunk of now otherwise empty RAM from our final running system. The bootmem code is designed to allow this initrd to be reserved (and the code in finalize_initrd() currently does this). When the initrd is finally processed/loaded its reserved memory is freed. Fix the setting of the start of the bootmem map to be the end of the kernel. Signed-off-by: Greg Ungerer --- arch/mips/kernel/setup.c | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 85aef3f..df8ed83 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -259,12 +259,13 @@ static void __init bootmem_init(void) int i; /* - * Init any data related to initrd. It's a nop if INITRD is - * not selected. Once that done we can determine the low bound - * of usable memory. + * Sanity check any INITRD first. We don't take it into account + * for bootmem setup initially, rely on the end-of-kernel-code + * as our memory range starting point. Once bootmem is inited we + * will reserve the area used for the initrd. */ - reserved_end = max(init_initrd(), - (unsigned long) PFN_UP(__pa_symbol(&_end))); + init_initrd(); + reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end)); /* * max_low_pfn is not a number of pages. The number of pages From walle@corscience.de Wed Sep 8 09:36:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Sep 2010 09:36:10 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.8]:63774 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490945Ab0IHHgH (ORCPT ); Wed, 8 Sep 2010 09:36:07 +0200 Received: from corscience.de (DSL01.212.114.252.242.ip-pool.NEFkom.net [212.114.252.242]) by mrelayeu.kundenserver.de (node=mreu0) with ESMTP (Nemesis) id 0LaHU2-1OTUId3jbS-00m15V; Wed, 08 Sep 2010 09:35:58 +0200 Received: from localhost.localdomain (unknown [192.168.102.58]) by corscience.de (Postfix) with ESMTP id 5D0D851FB1; Wed, 8 Sep 2010 09:35:57 +0200 (CEST) From: Bernhard Walle To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 Date: Wed, 8 Sep 2010 09:35:57 +0200 Message-Id: <1283931357-4550-1-git-send-email-walle@corscience.de> X-Mailer: git-send-email 1.7.0.4 X-Provags-ID: V02:K0:A88FcoG+4ETwZjSdVb6m4bq/PACEGxvt/d7rR0O5oLq teWV2Q7vdDH6EDzManA8+RHXqIyOWflBoAW+YzmmbUkhkoLEQH B61bYmD/1PnMWo1yvCwx1lNdC4ObulzPrB8ucO0DONN1QEvBzg O2nZnRfs5iIq1zcCyuSQ3/jZpaQLwv00vhSemHzeGrIu5ATWz5 ExlFdct7AQmmGsBh7fj6Q== X-archive-position: 27730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: walle@corscience.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6041 Content-Length: 913 Lines: 27 Commit 31c984a5acabea5d8c7224dc226453022be46f33 introduced a new syscall getdents64. However, in the syscall table, the new syscall still refers to the old getdents which doesn't work. The problem appeared with a system that uses the eglibc 2.12-r11187 (that utilizes that new syscall) is very confused. The fix has been tested with that eglibc version. Signed-off-by: Bernhard Walle --- arch/mips/kernel/scall64-n32.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index a3d6613..dfa8cbc 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -419,5 +419,5 @@ EXPORT(sysn32_call_table) PTR sys_perf_event_open PTR sys_accept4 PTR compat_sys_recvmmsg - PTR sys_getdents + PTR sys_getdents64 .size sysn32_call_table,.-sysn32_call_table -- 1.7.0.4 From cernekee@gmail.com Thu Sep 9 01:11:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 01:11:24 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:50041 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491026Ab0IHXLT (ORCPT ); Thu, 9 Sep 2010 01:11:19 +0200 Received: (qmail 30518 invoked from network); 8 Sep 2010 23:11:13 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 8 Sep 2010 23:11:13 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Wed, 08 Sep 2010 16:11:13 -0700 From: Kevin Cernekee Date: Wed, 8 Sep 2010 16:02:12 -0700 Subject: [PATCH v2 1/3] MIPS: HIGHMEM DMA on noncoherent MIPS32 processors To: Ralf Baechle Cc: , , , , Message-Id: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27731 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6791 Content-Length: 9226 Lines: 312 [v2: Formatting changes only.] The MIPS DMA coherency functions do not work properly (i.e. kernel oops) when HIGHMEM pages are passed in as arguments. This patch uses the PPC approach of calling kmap_atomic() with IRQs disabled to temporarily map high pages, in order to flush them out to memory. Signed-off-by: Dezhong Diao Signed-off-by: Kevin Cernekee --- arch/mips/mm/dma-default.c | 159 ++++++++++++++++++++++---------------------- 1 files changed, 80 insertions(+), 79 deletions(-) diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 469d401..79dfb9c 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -15,18 +15,18 @@ #include #include #include +#include #include #include #include -static inline unsigned long dma_addr_to_virt(struct device *dev, +static inline struct page *dma_addr_to_page(struct device *dev, dma_addr_t dma_addr) { - unsigned long addr = plat_dma_addr_to_phys(dev, dma_addr); - - return (unsigned long)phys_to_virt(addr); + return pfn_to_page( + plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); } /* @@ -153,20 +153,20 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, EXPORT_SYMBOL(dma_free_coherent); -static inline void __dma_sync(unsigned long addr, size_t size, +static inline void __dma_sync_virtual(void *addr, size_t size, enum dma_data_direction direction) { switch (direction) { case DMA_TO_DEVICE: - dma_cache_wback(addr, size); + dma_cache_wback((unsigned long)addr, size); break; case DMA_FROM_DEVICE: - dma_cache_inv(addr, size); + dma_cache_inv((unsigned long)addr, size); break; case DMA_BIDIRECTIONAL: - dma_cache_wback_inv(addr, size); + dma_cache_wback_inv((unsigned long)addr, size); break; default: @@ -174,13 +174,53 @@ static inline void __dma_sync(unsigned long addr, size_t size, } } +/* + * A single sg entry may refer to multiple physically contiguous + * pages. But we still need to process highmem pages individually. + * If highmem is not configured then the bulk of this loop gets + * optimized out. + */ +static inline void __dma_sync(struct page *page, + unsigned long offset, size_t size, enum dma_data_direction direction) +{ + size_t left = size; + + BUG_ON(direction == DMA_NONE); + + do { + size_t len = left; + + if (PageHighMem(page)) { + unsigned long flags; + void *addr; + + if (offset + len > PAGE_SIZE) { + if (offset >= PAGE_SIZE) { + page += offset >> PAGE_SHIFT; + offset &= ~PAGE_MASK; + } + len = PAGE_SIZE - offset; + } + + local_irq_save(flags); + addr = kmap_atomic(page, KM_SYNC_DCACHE); + __dma_sync_virtual(addr + offset, len, direction); + kunmap_atomic(addr, KM_SYNC_DCACHE); + local_irq_restore(flags); + } else + __dma_sync_virtual(page_address(page) + offset, + size, direction); + offset = 0; + page++; + left -= len; + } while (left); +} + dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, enum dma_data_direction direction) { - unsigned long addr = (unsigned long) ptr; - if (!plat_device_is_coherent(dev)) - __dma_sync(addr, size, direction); + __dma_sync_virtual(ptr, size, direction); return plat_map_dma_mem(dev, ptr, size); } @@ -191,8 +231,8 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction) { if (cpu_is_noncoherent_r10000(dev)) - __dma_sync(dma_addr_to_virt(dev, dma_addr), size, - direction); + __dma_sync(dma_addr_to_page(dev, dma_addr), + dma_addr & ~PAGE_MASK, size, direction); plat_unmap_dma_mem(dev, dma_addr, size, direction); } @@ -204,16 +244,12 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, { int i; - BUG_ON(direction == DMA_NONE); - for (i = 0; i < nents; i++, sg++) { - unsigned long addr; - - addr = (unsigned long) sg_virt(sg); - if (!plat_device_is_coherent(dev) && addr) - __dma_sync(addr, sg->length, direction); - sg->dma_address = plat_map_dma_mem(dev, - (void *)addr, sg->length); + if (!plat_device_is_coherent(dev)) + __dma_sync(sg_page(sg), sg->offset, sg->length, + direction); + sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + + sg->offset; } return nents; @@ -224,14 +260,8 @@ EXPORT_SYMBOL(dma_map_sg); dma_addr_t dma_map_page(struct device *dev, struct page *page, unsigned long offset, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - - if (!plat_device_is_coherent(dev)) { - unsigned long addr; - - addr = (unsigned long) page_address(page) + offset; - __dma_sync(addr, size, direction); - } + if (!plat_device_is_coherent(dev)) + __dma_sync(page, offset, size, direction); return plat_map_dma_mem_page(dev, page) + offset; } @@ -241,18 +271,13 @@ EXPORT_SYMBOL(dma_map_page); void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, enum dma_data_direction direction) { - unsigned long addr; int i; - BUG_ON(direction == DMA_NONE); - for (i = 0; i < nhwentries; i++, sg++) { if (!plat_device_is_coherent(dev) && - direction != DMA_TO_DEVICE) { - addr = (unsigned long) sg_virt(sg); - if (addr) - __dma_sync(addr, sg->length, direction); - } + direction != DMA_TO_DEVICE) + __dma_sync(sg_page(sg), sg->offset, sg->length, + direction); plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction); } } @@ -262,14 +287,9 @@ EXPORT_SYMBOL(dma_unmap_sg); void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - - if (cpu_is_noncoherent_r10000(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr, size, direction); - } + if (cpu_is_noncoherent_r10000(dev)) + __dma_sync(dma_addr_to_page(dev, dma_handle), + dma_handle & ~PAGE_MASK, size, direction); } EXPORT_SYMBOL(dma_sync_single_for_cpu); @@ -277,15 +297,10 @@ EXPORT_SYMBOL(dma_sync_single_for_cpu); void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); - if (!plat_device_is_coherent(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr, size, direction); - } + if (!plat_device_is_coherent(dev)) + __dma_sync(dma_addr_to_page(dev, dma_handle), + dma_handle & ~PAGE_MASK, size, direction); } EXPORT_SYMBOL(dma_sync_single_for_device); @@ -293,14 +308,9 @@ EXPORT_SYMBOL(dma_sync_single_for_device); void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - - if (cpu_is_noncoherent_r10000(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr + offset, size, direction); - } + if (cpu_is_noncoherent_r10000(dev)) + __dma_sync(dma_addr_to_page(dev, dma_handle), offset, size, + direction); } EXPORT_SYMBOL(dma_sync_single_range_for_cpu); @@ -308,15 +318,10 @@ EXPORT_SYMBOL(dma_sync_single_range_for_cpu); void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); - if (!plat_device_is_coherent(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr + offset, size, direction); - } + if (!plat_device_is_coherent(dev)) + __dma_sync(dma_addr_to_page(dev, dma_handle), offset, size, + direction); } EXPORT_SYMBOL(dma_sync_single_range_for_device); @@ -326,13 +331,11 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, { int i; - BUG_ON(direction == DMA_NONE); - /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) { if (cpu_is_noncoherent_r10000(dev)) - __dma_sync((unsigned long)page_address(sg_page(sg)), - sg->length, direction); + __dma_sync(sg_page(sg), sg->offset, sg->length, + direction); } } @@ -343,13 +346,11 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele { int i; - BUG_ON(direction == DMA_NONE); - /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) { if (!plat_device_is_coherent(dev)) - __dma_sync((unsigned long)page_address(sg_page(sg)), - sg->length, direction); + __dma_sync(sg_page(sg), sg->offset, sg->length, + direction); } } @@ -376,7 +377,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) - __dma_sync((unsigned long)vaddr, size, direction); + __dma_sync_virtual(vaddr, size, direction); } EXPORT_SYMBOL(dma_cache_sync); -- 1.7.0.4 From cernekee@gmail.com Thu Sep 9 01:12:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 01:12:26 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:50152 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491026Ab0IHXMX (ORCPT ); Thu, 9 Sep 2010 01:12:23 +0200 Received: (qmail 4012 invoked from network); 8 Sep 2010 23:12:19 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 8 Sep 2010 23:12:19 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Wed, 08 Sep 2010 16:12:19 -0700 From: Kevin Cernekee Date: Wed, 8 Sep 2010 16:02:14 -0700 Subject: [PATCH 2/3] MIPS: Allow UserLocal on MIPS_R1 processors To: Ralf Baechle Cc: , Message-Id: In-Reply-To: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27732 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6795 Content-Length: 1352 Lines: 45 Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate programs that make extensive use of thread-local storage. Therefore, setting up the HWRENA register should not depend on cpu_has_mips_r2. Signed-off-by: Kevin Cernekee --- arch/mips/kernel/traps.c | 13 +++++++------ 1 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 03ec001..ec6cbd2 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1469,6 +1469,7 @@ void __cpuinit per_cpu_trap_init(void) { unsigned int cpu = smp_processor_id(); unsigned int status_set = ST0_CU0; + unsigned int hwrena = cpu_hwrena_impl_bits; #ifdef CONFIG_MIPS_MT_SMTC int secondaryTC = 0; int bootTC = (cpu == 0); @@ -1501,14 +1502,14 @@ void __cpuinit per_cpu_trap_init(void) change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, status_set); - if (cpu_has_mips_r2) { - unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits; + if (cpu_has_mips_r2) + hwrena |= 0x0000000f; - if (!noulri && cpu_has_userlocal) - enable |= (1 << 29); + if (!noulri && cpu_has_userlocal) + hwrena |= (1 << 29); - write_c0_hwrena(enable); - } + if (hwrena) + write_c0_hwrena(hwrena); #ifdef CONFIG_MIPS_MT_SMTC if (!secondaryTC) { -- 1.7.0.4 From cernekee@gmail.com Thu Sep 9 01:12:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 01:12:49 +0200 (CEST) Received: from [69.28.251.93] ([69.28.251.93]:50208 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491055Ab0IHXMj (ORCPT ); Thu, 9 Sep 2010 01:12:39 +0200 Received: (qmail 5586 invoked from network); 8 Sep 2010 23:12:35 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 8 Sep 2010 23:12:35 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Wed, 08 Sep 2010 16:12:35 -0700 From: Kevin Cernekee Date: Wed, 8 Sep 2010 16:02:16 -0700 Subject: [PATCH 3/3] MIPS: DMA: Add plat_extra_sync_for_cpu() To: Ralf Baechle Cc: , Message-Id: <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> In-Reply-To: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-archive-position: 27733 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 6796 Content-Length: 7636 Lines: 215 On noncoherent processors with a readahead cache, an extra platform- specific invalidation is required during the dma_sync_*_for_cpu() operations to keep drivers from seeing stale prefetched data. Signed-off-by: Kevin Cernekee --- .../include/asm/mach-cavium-octeon/dma-coherence.h | 13 +++++++++++++ arch/mips/include/asm/mach-generic/dma-coherence.h | 13 +++++++++++++ arch/mips/include/asm/mach-ip27/dma-coherence.h | 13 +++++++++++++ arch/mips/include/asm/mach-ip32/dma-coherence.h | 13 +++++++++++++ arch/mips/include/asm/mach-jazz/dma-coherence.h | 13 +++++++++++++ .../mips/include/asm/mach-loongson/dma-coherence.h | 13 +++++++++++++ arch/mips/include/asm/mach-powertv/dma-coherence.h | 13 +++++++++++++ arch/mips/mm/dma-default.c | 3 +++ 8 files changed, 94 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h index 17d5794..8192683 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -52,6 +52,19 @@ static inline void plat_extra_sync_for_device(struct device *dev) mb(); } +static inline void plat_extra_sync_for_cpu(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + return; +} + +static inline void plat_extra_sync_for_cpu_sg(struct device *dev, + struct scatterlist *sg, enum dma_data_direction direction) +{ + return; +} + static inline int plat_device_is_coherent(struct device *dev) { return 1; diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 8da9807..20728eb 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -52,6 +52,19 @@ static inline void plat_extra_sync_for_device(struct device *dev) return; } +static inline void plat_extra_sync_for_cpu(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + return; +} + +static inline void plat_extra_sync_for_cpu_sg(struct device *dev, + struct scatterlist *sg, enum dma_data_direction direction) +{ + return; +} + static inline int plat_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h index d3d0401..b1cb862 100644 --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h @@ -62,6 +62,19 @@ static inline void plat_extra_sync_for_device(struct device *dev) return; } +static inline void plat_extra_sync_for_cpu(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + return; +} + +static inline void plat_extra_sync_for_cpu_sg(struct device *dev, + struct scatterlist *sg, enum dma_data_direction direction) +{ + return; +} + static inline int plat_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h index 3785595..c870003 100644 --- a/arch/mips/include/asm/mach-ip32/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h @@ -84,6 +84,19 @@ static inline void plat_extra_sync_for_device(struct device *dev) return; } +static inline void plat_extra_sync_for_cpu(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + return; +} + +static inline void plat_extra_sync_for_cpu_sg(struct device *dev, + struct scatterlist *sg, enum dma_data_direction direction) +{ + return; +} + static inline int plat_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h index f93aee5..dd7b8e3 100644 --- a/arch/mips/include/asm/mach-jazz/dma-coherence.h +++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h @@ -52,6 +52,19 @@ static inline void plat_extra_sync_for_device(struct device *dev) return; } +static inline void plat_extra_sync_for_cpu(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + return; +} + +static inline void plat_extra_sync_for_cpu_sg(struct device *dev, + struct scatterlist *sg, enum dma_data_direction direction) +{ + return; +} + static inline int plat_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index 981c75f..7565bbc 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -58,6 +58,19 @@ static inline void plat_extra_sync_for_device(struct device *dev) return; } +static inline void plat_extra_sync_for_cpu(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + return; +} + +static inline void plat_extra_sync_for_cpu_sg(struct device *dev, + struct scatterlist *sg, enum dma_data_direction direction) +{ + return; +} + static inline int plat_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h index f76029c..1134961 100644 --- a/arch/mips/include/asm/mach-powertv/dma-coherence.h +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h @@ -105,6 +105,19 @@ static inline void plat_extra_sync_for_device(struct device *dev) return; } +static inline void plat_extra_sync_for_cpu(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + return; +} + +static inline void plat_extra_sync_for_cpu_sg(struct device *dev, + struct scatterlist *sg, enum dma_data_direction direction) +{ + return; +} + static inline int plat_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 79dfb9c..ed1baaf 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -287,6 +287,7 @@ EXPORT_SYMBOL(dma_unmap_sg); void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { + plat_extra_sync_for_cpu(dev, dma_handle, 0, size, direction); if (cpu_is_noncoherent_r10000(dev)) __dma_sync(dma_addr_to_page(dev, dma_handle), dma_handle & ~PAGE_MASK, size, direction); @@ -308,6 +309,7 @@ EXPORT_SYMBOL(dma_sync_single_for_device); void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) { + plat_extra_sync_for_cpu(dev, dma_handle, offset, size, direction); if (cpu_is_noncoherent_r10000(dev)) __dma_sync(dma_addr_to_page(dev, dma_handle), offset, size, direction); @@ -333,6 +335,7 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) { + plat_extra_sync_for_cpu_sg(dev, sg, direction); if (cpu_is_noncoherent_r10000(dev)) __dma_sync(sg_page(sg), sg->offset, sg->length, direction); -- 1.7.0.4 From sshtylyov@mvista.com Thu Sep 9 11:36:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 11:36:16 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:58546 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490970Ab0IIJgJ (ORCPT ); Thu, 9 Sep 2010 11:36:09 +0200 Received: by ewy9 with SMTP id 9so784666ewy.36 for ; Thu, 09 Sep 2010 02:36:09 -0700 (PDT) Received: by 10.213.10.195 with SMTP id q3mr619704ebq.29.1284024968861; Thu, 09 Sep 2010 02:36:08 -0700 (PDT) Received: from [192.168.2.2] (ppp85-140-115-148.pppoe.mtu-net.ru [85.140.115.148]) by mx.google.com with ESMTPS id v59sm1688327eeh.22.2010.09.09.02.36.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 09 Sep 2010 02:36:07 -0700 (PDT) Message-ID: <4C88AA27.5070206@mvista.com> Date: Thu, 09 Sep 2010 13:34:31 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.9) Gecko/20100825 Thunderbird/3.1.3 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] MIPS: DMA: Add plat_extra_sync_for_cpu() References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> In-Reply-To: <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 27734 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7067 Content-Length: 950 Lines: 27 Hello. On 09-09-2010 3:02, Kevin Cernekee wrote: > On noncoherent processors with a readahead cache, an extra platform- > specific invalidation is required during the dma_sync_*_for_cpu() > operations to keep drivers from seeing stale prefetched data. > Signed-off-by: Kevin Cernekee [...] > diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h > index 17d5794..8192683 100644 > --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h > +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h > @@ -52,6 +52,19 @@ static inline void plat_extra_sync_for_device(struct device *dev) > mb(); > } > > +static inline void plat_extra_sync_for_cpu(struct device *dev, > + dma_addr_t dma_handle, unsigned long offset, size_t size, > + enum dma_data_direction direction) > +{ > + return; Why not just empty function bodies? WBR, Sergei From ralf@linux-mips.org Thu Sep 9 11:54:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 11:54:04 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1490970Ab0IIJyB (ORCPT ); Thu, 9 Sep 2010 11:54:01 +0200 Date: Thu, 9 Sep 2010 11:53:59 +0200 From: Ralf Baechle To: Kevin Cernekee Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] MIPS: Allow UserLocal on MIPS_R1 processors Message-ID: <20100909095359.GA27815@linux-mips.org> References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7083 Content-Length: 394 Lines: 10 On Wed, Sep 08, 2010 at 04:02:14PM -0700, Kevin Cernekee wrote: > Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate > programs that make extensive use of thread-local storage. Therefore, > setting up the HWRENA register should not depend on cpu_has_mips_r2. Interesting - which R1 processor has RDHWR? When UserLocal was conceived R2 was already long released. Ralf From cernekee@gmail.com Thu Sep 9 14:39:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 14:39:43 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:62195 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491026Ab0IIMjj convert rfc822-to-8bit (ORCPT ); Thu, 9 Sep 2010 14:39:39 +0200 Received: by vws11 with SMTP id 11so1366501vws.36 for ; Thu, 09 Sep 2010 05:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=C99ma2XRo3DimD789TGakcCo2S3orvkvNWsD4/LyiEM=; b=KJULi9Q3mQ9ghwbup+xvpfthe1YTtYSZjN1geTpjCm8+DirkbungdUZU8PfnxZaA0Q uv41Aa8XmtX1Pty5LmyrkfW/UYPCAoBoID/rk4q21fmrTC0LdZzdoE3NUkikKzae/AeQ EwY+Dnnql84YULxoupF3xpEkiclvHpr7Spn4s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=SRLKX9+jxvO57eKhXyMUQ9EWjepHhbPIlqO9xfir6bBYnNxM7Ca114NR9booTlurFq vhyfLXONa9lQsqxUA9dpasH01uIujTlRoUVgtvXeDZNssaP8ZnIo8xx3hG9q9li8ScVD yU67PvJGaVUo4GRyEYojbK2DYHtqZBelScW0w= MIME-Version: 1.0 Received: by 10.220.75.200 with SMTP id z8mr175377vcj.57.1284035972952; Thu, 09 Sep 2010 05:39:32 -0700 (PDT) Received: by 10.220.114.141 with HTTP; Thu, 9 Sep 2010 05:39:32 -0700 (PDT) In-Reply-To: <4C88AA27.5070206@mvista.com> References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> <4C88AA27.5070206@mvista.com> Date: Thu, 9 Sep 2010 05:39:32 -0700 Message-ID: Subject: Re: [PATCH 3/3] MIPS: DMA: Add plat_extra_sync_for_cpu() From: Kevin Cernekee To: Sergei Shtylyov Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 27736 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7219 Content-Length: 389 Lines: 10 On Thu, Sep 9, 2010 at 2:34 AM, Sergei Shtylyov wrote: >> +static inline void plat_extra_sync_for_cpu(struct device *dev, >> +       dma_addr_t dma_handle, unsigned long offset, size_t size, >> +       enum dma_data_direction direction) >> +{ >> +       return; > >   Why not just empty function bodies? For consistency with plat_extra_sync_for_device(). From anemo@mba.ocn.ne.jp Thu Sep 9 16:24:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 16:25:01 +0200 (CEST) Received: from mv-drv-hcb003.ocn.ad.jp ([118.23.109.133]:42428 "EHLO mv-drv-hcb003.ocn.ad.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491043Ab0IIOY6 (ORCPT ); Thu, 9 Sep 2010 16:24:58 +0200 Received: from vcmba.ocn.ne.jp (localhost.localdomain [127.0.0.1]) by mv-drv-hcb003.ocn.ad.jp (Postfix) with ESMTP id E161F56421D; Thu, 9 Sep 2010 23:24:53 +0900 (JST) Received: from localhost (softbank221040169135.bbtec.net [221.40.169.135]) by vcmba.ocn.ne.jp (Postfix) with ESMTP; Thu, 9 Sep 2010 23:24:53 +0900 (JST) Date: Thu, 09 Sep 2010 23:24:53 +0900 (JST) Message-Id: <20100909.232453.31646362.anemo@mba.ocn.ne.jp> To: cernekee@gmail.com Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 5/5] MIPS: Move FIXADDR_TOP into spaces.h From: Atsushi Nemoto In-Reply-To: <55645e13fcf442f6641b3eb187cab302@localhost> References: <55645e13fcf442f6641b3eb187cab302@localhost> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-archive-position: 27737 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7330 Content-Length: 362 Lines: 10 On Tue, 7 Sep 2010 12:59:15 -0700, Kevin Cernekee wrote: > Memory maps and addressing quirks are normally defined in . > There are already three targets that need to override FIXADDR_TOP, and > others exist. This will be a cleaner approach than adding lots of > ifdefs in fixmap.h . Looks OK for me. Thanks. --- Atsushi Nemoto From ddaney@caviumnetworks.com Thu Sep 9 19:10:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 19:10:08 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4926 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491085Ab0IIRKE (ORCPT ); Thu, 9 Sep 2010 19:10:04 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 09 Sep 2010 10:10:35 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 9 Sep 2010 10:10:00 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 9 Sep 2010 10:10:00 -0700 Message-ID: <4C8914E8.5030002@caviumnetworks.com> Date: Thu, 09 Sep 2010 10:10:00 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Kevin Cernekee CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] MIPS: DMA: Add plat_extra_sync_for_cpu() References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> In-Reply-To: <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 09 Sep 2010 17:10:00.0893 (UTC) FILETIME=[D65126D0:01CB5041] X-archive-position: 27738 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7428 Content-Length: 1137 Lines: 24 On 09/08/2010 04:02 PM, Kevin Cernekee wrote: > On noncoherent processors with a readahead cache, an extra platform- > specific invalidation is required during the dma_sync_*_for_cpu() > operations to keep drivers from seeing stale prefetched data. > > Signed-off-by: Kevin Cernekee > --- > .../include/asm/mach-cavium-octeon/dma-coherence.h | 13 +++++++++++++ > arch/mips/include/asm/mach-generic/dma-coherence.h | 13 +++++++++++++ > arch/mips/include/asm/mach-ip27/dma-coherence.h | 13 +++++++++++++ > arch/mips/include/asm/mach-ip32/dma-coherence.h | 13 +++++++++++++ > arch/mips/include/asm/mach-jazz/dma-coherence.h | 13 +++++++++++++ > .../mips/include/asm/mach-loongson/dma-coherence.h | 13 +++++++++++++ > arch/mips/include/asm/mach-powertv/dma-coherence.h | 13 +++++++++++++ > arch/mips/mm/dma-default.c | 3 +++ > 8 files changed, 94 insertions(+), 0 deletions(-) > [...] But as far as I can see, none of your plat_extra_sync_for_cpu() do anything. Perhaps adding this hook should be deferred until there is actually a user. David Daney From ddaney@caviumnetworks.com Thu Sep 9 19:24:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 19:24:57 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5407 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491106Ab0IIRYx (ORCPT ); Thu, 9 Sep 2010 19:24:53 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 09 Sep 2010 10:25:26 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 9 Sep 2010 10:24:52 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 9 Sep 2010 10:24:52 -0700 Message-ID: <4C891863.1080602@caviumnetworks.com> Date: Thu, 09 Sep 2010 10:24:51 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Greg Ungerer CC: linux-mips@linux-mips.org, gerg@uclinux.org Subject: Re: [PATCH] mips: fix start of free memory when using initrd References: <201009080550.o885ohjD014188@goober.internal.moreton.com.au> In-Reply-To: <201009080550.o885ohjD014188@goober.internal.moreton.com.au> Content-Type: multipart/mixed; boundary="------------090501000204010407060404" X-OriginalArrivalTime: 09 Sep 2010 17:24:52.0040 (UTC) FILETIME=[E97B6480:01CB5043] X-archive-position: 27739 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7433 Content-Length: 8804 Lines: 263 This is a multi-part message in MIME format. --------------090501000204010407060404 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On 09/07/2010 10:50 PM, Greg Ungerer wrote: > > Hi All, > > I have a typical Cavium/Octeon (5010) based system, that I sometimes > use a kernel and traditional initrd setup on. In a typical layout the > kernel is loaded into low physical RAM (via boot loader) and the initrd > is loaded somewhere above it. Everything runs fine, but the region > occupied by the initrd is effectively lost from usable RAM. > > For example, with these boot args "rd_start=0x84000000 rd_size=0x00206000" > where the initrd is loaded at 64MB (and is just over 2MB in size) I end > up with: > > Memory: 59620k/127152k available (2193k kernel code, 67532k reserved, 563k data, 192k init, 0k highmem) > > Ouch! A lot of RAM not usable. > > It looks to me that the logic of setting the bootmem is not quite right > for the initrd case. If I patch arch/mips/kernel/setup.c with the patch > below I get all that memory back, and everything seems to work: > > Memory: 121044k/127152k available (2193k kernel code, 6108k reserved, 563k data, 192k init, 0k highmem) > > The patch just sets the bootmem map to always be the end of the kernel. > Then the bootmem reserve initrd logic does its work as expected. > (A little more cleaning up could be done I guess, but I want to know > the approach is correct first :-) > > Am I mis-understanding how this is supposed to work? > Other architectures seem to set the bootmem to the end of the kernel. > Sparc has some extra checks to make sure that the bootmem setup data > doesn't overwrite the initrd, but otherwise is similar. > > Regards > Greg > > > > mips: fix start of free memory when using initrd > > Currently when using an initrd on a MIPS system the start of the bootmem > region of memory is set to the larger of the end of the kernel bss region > (_end) or the end of the initrd. In a typical memory layout where the > initrd is at some address above the kernel image this means that the > start of the bootmem region will be the end of the initrd. But when > we are done processing/loading the initrd we have no way to reclaim the > memory region it occupied, and we lose a large chunk of now otherwise > empty RAM from our final running system. > > The bootmem code is designed to allow this initrd to be reserved (and > the code in finalize_initrd() currently does this). When the initrd is > finally processed/loaded its reserved memory is freed. > > Fix the setting of the start of the bootmem map to be the end of the > kernel. > > Signed-off-by: Greg Ungerer > --- > arch/mips/kernel/setup.c | 11 ++++++----- > 1 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c > index 85aef3f..df8ed83 100644 > --- a/arch/mips/kernel/setup.c > +++ b/arch/mips/kernel/setup.c > @@ -259,12 +259,13 @@ static void __init bootmem_init(void) > int i; > > /* > - * Init any data related to initrd. It's a nop if INITRD is > - * not selected. Once that done we can determine the low bound > - * of usable memory. > + * Sanity check any INITRD first. We don't take it into account > + * for bootmem setup initially, rely on the end-of-kernel-code > + * as our memory range starting point. Once bootmem is inited we > + * will reserve the area used for the initrd. > */ > - reserved_end = max(init_initrd(), > - (unsigned long) PFN_UP(__pa_symbol(&_end))); > + init_initrd(); > + reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end)); > > /* > * max_low_pfn is not a number of pages. The number of pages > > We have the attached patch (plus a few more hacks), I don't think it is universally safe to change the calculation of reserved_end. Although the patch has some code formatting problems you might consider using it as a starting point. David Daney --------------090501000204010407060404 Content-Type: text/plain; name="initrd.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="initrd.patch" commit 465b46e1f44e95c01e9a848ec061a6e6385cac4c Author: Chandrakala Chavva Date: Fri May 14 14:57:41 2010 -0700 MIPS: Octeon: Add Initrd from named memory block Boot rootfs from 'linux.initrd' named memory block if it is present. Signed-off-by: Chandrakala Chavva diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 2cfe38b..c0bc62b 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -20,6 +20,9 @@ #include #include #include +#ifdef CONFIG_BLK_DEV_INITRD +#include +#endif #include #include @@ -769,10 +772,22 @@ void __init prom_init(void) void __init plat_mem_setup(void) { uint64_t mem_alloc_size; - uint64_t total; + uint64_t total = 0; int64_t memory; - total = 0; +#ifdef CONFIG_BLK_DEV_INITRD + const cvmx_bootmem_named_block_desc_t *initrd_block; + + initrd_block = cvmx_bootmem_find_named_block("linux.initrd"); + if (initrd_block) { + initrd_start = initrd_block->base_addr + PAGE_OFFSET; + initrd_end = initrd_start + initrd_block->size; + add_memory_region(initrd_block->base_addr, initrd_block->size, + BOOT_MEM_INIT_RAM); + initrd_in_reserved = 1; + total += initrd_block->size; + } +#endif /* First add the init memory we will be returning. */ memory = __pa_symbol(&__init_begin) & PAGE_MASK; diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index f5dfaf6..2bd1e75 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -80,6 +80,7 @@ extern unsigned long mips_machtype; #define BOOT_MEM_RAM 1 #define BOOT_MEM_ROM_DATA 2 #define BOOT_MEM_RESERVED 3 +#define BOOT_MEM_INIT_RAM 4 /* * A memory map that's built upon what was determined @@ -95,6 +96,7 @@ struct boot_mem_map { }; extern struct boot_mem_map boot_mem_map; +extern int initrd_in_reserved; extern void add_memory_region(phys_t start, phys_t size, long type); diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 2b290d7..dc41417 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -57,6 +57,7 @@ unsigned long mips_machtype __read_mostly = MACH_UNKNOWN; EXPORT_SYMBOL(mips_machtype); struct boot_mem_map boot_mem_map; +int initrd_in_reserved; static char command_line[CL_SIZE]; char arcs_cmdline[CL_SIZE]=CONFIG_CMDLINE; @@ -116,6 +117,9 @@ static void __init print_memory_map(void) case BOOT_MEM_RAM: printk(KERN_CONT "(usable)\n"); break; + case BOOT_MEM_INIT_RAM: + printk("(usable after init)\n"); + break; case BOOT_MEM_ROM_DATA: printk(KERN_CONT "(ROM data)\n"); break; @@ -277,8 +281,13 @@ static void __init bootmem_init(void) * not selected. Once that done we can determine the low bound * of usable memory. */ - reserved_end = max(init_initrd(), - (unsigned long) PFN_UP(__pa_symbol(&_end))); + if (initrd_in_reserved) { + init_initrd(); + reserved_end = PFN_UP(__pa_symbol(&_end)); + } else { + reserved_end = max(init_initrd(), + (unsigned long) PFN_UP(__pa_symbol(&_end))); + } /* * max_low_pfn is not a number of pages. The number of pages @@ -293,8 +302,14 @@ static void __init bootmem_init(void) for (i = 0; i < boot_mem_map.nr_map; i++) { unsigned long start, end; - if (boot_mem_map.map[i].type != BOOT_MEM_RAM) + switch (boot_mem_map.map[i].type) { + case BOOT_MEM_RAM: + case BOOT_MEM_INIT_RAM: + break; + default: + /* Not usable memory */ continue; + } start = PFN_UP(boot_mem_map.map[i].addr); end = PFN_DOWN(boot_mem_map.map[i].addr @@ -522,6 +537,7 @@ static void __init resource_init(void) res = alloc_bootmem(sizeof(struct resource)); switch (boot_mem_map.map[i].type) { case BOOT_MEM_RAM: + case BOOT_MEM_INIT_RAM: case BOOT_MEM_ROM_DATA: res->name = "System RAM"; break; diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 3d90ccc..67fc152 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -305,9 +305,14 @@ static int __init page_is_ram(unsigned long pagenr) for (i = 0; i < boot_mem_map.nr_map; i++) { unsigned long addr, end; - if (boot_mem_map.map[i].type != BOOT_MEM_RAM) + switch (boot_mem_map.map[i].type) { + case BOOT_MEM_RAM: + case BOOT_MEM_INIT_RAM: + break; + default: /* not usable memory */ continue; + } addr = PFN_UP(boot_mem_map.map[i].addr); end = PFN_DOWN(boot_mem_map.map[i].addr + --------------090501000204010407060404-- From tsbogend@alpha.franken.de Thu Sep 9 19:37:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 19:37:07 +0200 (CEST) Received: from elvis.franken.de ([193.175.24.41]:37112 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491101Ab0IIRhE (ORCPT ); Thu, 9 Sep 2010 19:37:04 +0200 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1Otl3X-000126-00; Thu, 09 Sep 2010 19:37:03 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 17ADB2397F0; Thu, 9 Sep 2010 19:34:27 +0200 (CEST) Date: Thu, 9 Sep 2010 19:34:27 +0200 From: Thomas Bogendoerfer To: David Daney Cc: Kevin Cernekee , Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] MIPS: DMA: Add plat_extra_sync_for_cpu() Message-ID: <20100909173426.GA14371@alpha.franken.de> References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> <4C8914E8.5030002@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C8914E8.5030002@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) X-archive-position: 27740 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7443 Content-Length: 846 Lines: 19 On Thu, Sep 09, 2010 at 10:10:00AM -0700, David Daney wrote: > On 09/08/2010 04:02 PM, Kevin Cernekee wrote: >> On noncoherent processors with a readahead cache, an extra platform- >> specific invalidation is required during the dma_sync_*_for_cpu() >> operations to keep drivers from seeing stale prefetched data. > > But as far as I can see, none of your plat_extra_sync_for_cpu() do anything. > > Perhaps adding this hook should be deferred until there is actually a user. looks like this is doing what the non_coherent_r10000 case does. So IMHO either which make non_coheren check more generic or could use the new plat_sync thingie for IP28 and other non coherent r10k boxes. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From cernekee@gmail.com Thu Sep 9 20:35:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 20:35:22 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:45556 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491085Ab0IISfT (ORCPT ); Thu, 9 Sep 2010 20:35:19 +0200 Received: by vws11 with SMTP id 11so1770886vws.36 for ; Thu, 09 Sep 2010 11:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=9prrGczyq+hxuazqWX0xVbLVJcrXgVvnjO4mjef1lU8=; b=A0ylXPQl48iKyKfR9L0dyoueiOnqX8od4GtqG8LK4pSWdsqHlpxGWLxhNjz1DWVzm/ T4EoHI61fcWIfWcXkLyDijYlAz513h+v8PcqDUC55mYUl/WCzQ+MGd5wCb87Tix5/WcN Xd9lwsiqDZM3VCdHiZBbxl0ECbEoGNZXcKw+Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=ZX+T85pV0V2A4qDPVndjlV4qmY8yjK9AjQb83nExhhdE1WyyzFI8rZy8oI/kNNF6CH TenCgAQrUNlM1jbsgNYvkB2DtnvSM5+2+wqDAuSGI+xu4UhCmjzf172Rd08kPIaqDavf 7zcYtz9u072am5hzeUuKZlL4X/osaVEANA/6g= MIME-Version: 1.0 Received: by 10.220.127.93 with SMTP id f29mr24056vcs.127.1284057308333; Thu, 09 Sep 2010 11:35:08 -0700 (PDT) Received: by 10.220.114.141 with HTTP; Thu, 9 Sep 2010 11:35:08 -0700 (PDT) In-Reply-To: <20100909173426.GA14371@alpha.franken.de> References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> <4C8914E8.5030002@caviumnetworks.com> <20100909173426.GA14371@alpha.franken.de> Date: Thu, 9 Sep 2010 11:35:08 -0700 Message-ID: Subject: Re: [PATCH 3/3] MIPS: DMA: Add plat_extra_sync_for_cpu() From: Kevin Cernekee To: Thomas Bogendoerfer Cc: David Daney , Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 X-archive-position: 27741 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7468 Content-Length: 783 Lines: 16 On Thu, Sep 9, 2010 at 10:34 AM, Thomas Bogendoerfer wrote: > looks like this is doing what the non_coherent_r10000 case does. So IMHO My code is not currently in the tree, but I have 3 different hooks for 3 different processor types. The generic __dma_sync() workaround used on R10K is not sufficient. > either which make non_coheren check more generic or could use the new > plat_sync thingie for IP28 and other non coherent r10k boxes. That is a good idea. One thing I'd like to do is continue sharing the same R10K code for IP27 / IP28 / IP32 / SNI_RM, and move all of it out of dma-default.c . Do you have any suggestions on how to define the plat_* handlers on a per-cpu-type basis instead of making 4 identical copies of the R10K workaround? From ddaney@caviumnetworks.com Thu Sep 9 20:58:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Sep 2010 20:58:33 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8676 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491101Ab0IIS6a (ORCPT ); Thu, 9 Sep 2010 20:58:30 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 09 Sep 2010 11:59:00 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 9 Sep 2010 11:58:26 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 9 Sep 2010 11:58:26 -0700 Message-ID: <4C892E51.9050901@caviumnetworks.com> Date: Thu, 09 Sep 2010 11:58:25 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Kevin Cernekee CC: Thomas Bogendoerfer , Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] MIPS: DMA: Add plat_extra_sync_for_cpu() References: <064bb0722da5d8c271c2bd9fe0a521cc@localhost> <99a0868bdbcfa8785a92b4af4f6d9b99@localhost> <4C8914E8.5030002@caviumnetworks.com> <20100909173426.GA14371@alpha.franken.de> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 09 Sep 2010 18:58:26.0216 (UTC) FILETIME=[FBCAAA80:01CB5050] X-archive-position: 27742 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 7486 Content-Length: 1343 Lines: 33 On 09/09/2010 11:35 AM, Kevin Cernekee wrote: > On Thu, Sep 9, 2010 at 10:34 AM, Thomas Bogendoerfer > wrote: >> looks like this is doing what the non_coherent_r10000 case does. So IMHO > > My code is not currently in the tree, but I have 3 different hooks for > 3 different processor types. The generic __dma_sync() workaround used > on R10K is not sufficient. > >> either which make non_coheren check more generic or could use the new >> plat_sync thingie for IP28 and other non coherent r10k boxes. > > That is a good idea. One thing I'd like to do is continue sharing the > same R10K code for IP27 / IP28 / IP32 / SNI_RM, and move all of it out > of dma-default.c . Do you have any suggestions on how to define the > plat_* handlers on a per-cpu-type basis instead of making 4 identical > copies of the R10K workaround? > I am working on patches that use asm-generic/dma-mapping-common.h. This dispatches all DMA operations via a dma_map_ops vector. It adds some function call overhead, but makes it easy to mix and match different implementations. My main motivation is to integrate the swiotlb.c bounce buffer management for devices that have small dma_masks. It is still a work in progress, and is not ready to publish yet. I foresee a lot of churn in this area in the near future. David Daney From gerg@snapgear.com Fri Sep 10 08:11:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Sep 2010 08:11:26 +0200 (CEST) Received: from dalsmrelay2.nai.com ([205.227.136.216]:53123 "HELO dalsmrelay2.nai.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491013Ab0IJGLW (ORCPT ); Fri, 10 Sep 2010 08:11:22 +0200 Received: from (unknown [10.64.5.51]) by dalsmrelay2.nai.com with smtp id 2782_191d_37f50286_bca2_11df_b885_00219b929abd; Fri, 10 Sep 2010 06:11:15 +0000 Received: from dalexbr1.corp.nai.org (161.69.111.81) by DALEXHT1.corp.nai.org (10.64.5.51) with Microsoft SMTP Server id 8.2.254.0; Fri, 10 Sep 2010 01:11:08 -0500 Received: from STPSMTP01.scur.com ([10.96.96.163]) by dalexbr1.corp.nai.org with Microsoft SMTPSVC(6.0.3790.3959); Fri, 10 Sep 2010 01:11:06 -0500 Received: from cyberguard.com.au ([10.46.129.16]) by STPSMTP01.scur.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 10 Sep 2010 01:11:06 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by bne.snapgear.com (Postfix) with ESMTP id EA254EBAD0; Fri, 10 Sep 2010 16:11:04 +1000 (EST) X-Virus-Scanned: amavisd-new at snapgear.com Received: from bne.snapgear.com ([127.0.0.1]) by localhost (bne.snapgear.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id A1O6MaRU5aYu; Fri, 10 Sep 2010 16:10:55 +1000 (EST) Received: from [172.22.196.222] (bnelabfw.scur.com [10.46.129.16]) by bne.snapgear.com (Postfix) with ESMTP; Fri, 10 Sep 2010 16:10:55 +1000 (EST) Message-ID: <4C89CBDA.1030309@snapgear.com> Date: Fri, 10 Sep 2010 16:10:34 +1000 From: Greg Ungerer User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org Subject: Re: [PATCH] mips: fix start of free memory when using initrd References: <201009080550.o885ohjD014188@goober.internal.moreton.com.au> <4C891863.1080602@caviumnetworks.com> In-Reply-To: <4C891863.1080602@caviumnetworks.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 10 Sep 2010 06:11:06.0620 (UTC) FILETIME=[F47793C0:01CB50AE] X-archive-position: 27743 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gerg@snapgear.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8081 Content-Length: 4784 Lines: 118 Hi David, David Daney wrote: > On 09/07/2010 10:50 PM, Greg Ungerer wrote: >> I have a typical Cavium/Octeon (5010) based system, that I sometimes >> use a kernel and traditional initrd setup on. In a typical layout the >> kernel is loaded into low physical RAM (via boot loader) and the initrd >> is loaded somewhere above it. Everything runs fine, but the region >> occupied by the initrd is effectively lost from usable RAM. >> >> For example, with these boot args "rd_start=0x84000000 >> rd_size=0x00206000" >> where the initrd is loaded at 64MB (and is just over 2MB in size) I end >> up with: >> >> Memory: 59620k/127152k available (2193k kernel code, 67532k reserved, >> 563k data, 192k init, 0k highmem) >> >> Ouch! A lot of RAM not usable. >> >> It looks to me that the logic of setting the bootmem is not quite right >> for the initrd case. If I patch arch/mips/kernel/setup.c with the patch >> below I get all that memory back, and everything seems to work: >> >> Memory: 121044k/127152k available (2193k kernel code, 6108k reserved, >> 563k data, 192k init, 0k highmem) >> >> The patch just sets the bootmem map to always be the end of the kernel. >> Then the bootmem reserve initrd logic does its work as expected. >> (A little more cleaning up could be done I guess, but I want to know >> the approach is correct first :-) >> >> Am I mis-understanding how this is supposed to work? >> Other architectures seem to set the bootmem to the end of the kernel. >> Sparc has some extra checks to make sure that the bootmem setup data >> doesn't overwrite the initrd, but otherwise is similar. >> >> Regards >> Greg >> >> >> >> mips: fix start of free memory when using initrd >> >> Currently when using an initrd on a MIPS system the start of the bootmem >> region of memory is set to the larger of the end of the kernel bss region >> (_end) or the end of the initrd. In a typical memory layout where the >> initrd is at some address above the kernel image this means that the >> start of the bootmem region will be the end of the initrd. But when >> we are done processing/loading the initrd we have no way to reclaim the >> memory region it occupied, and we lose a large chunk of now otherwise >> empty RAM from our final running system. >> >> The bootmem code is designed to allow this initrd to be reserved (and >> the code in finalize_initrd() currently does this). When the initrd is >> finally processed/loaded its reserved memory is freed. >> >> Fix the setting of the start of the bootmem map to be the end of the >> kernel. >> >> Signed-off-by: Greg Ungerer >> --- >> arch/mips/kernel/setup.c | 11 ++++++----- >> 1 files changed, 6 insertions(+), 5 deletions(-) >> >> diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c >> index 85aef3f..df8ed83 100644 >> --- a/arch/mips/kernel/setup.c >> +++ b/arch/mips/kernel/setup.c >> @@ -259,12 +259,13 @@ static void __init bootmem_init(void) >> int i; >> >> /* >> - * Init any data related to initrd. It's a nop if INITRD is >> - * not selected. Once that done we can determine the low bound >> - * of usable memory. >> + * Sanity check any INITRD first. We don't take it into account >> + * for bootmem setup initially, rely on the end-of-kernel-code >> + * as our memory range starting point. Once bootmem is inited we >> + * will reserve the area used for the initrd. >> */ >> - reserved_end = max(init_initrd(), >> - (unsigned long) PFN_UP(__pa_symbol(&_end))); >> + init_initrd(); >> + reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end)); >> >> /* >> * max_low_pfn is not a number of pages. The number of pages >> >> > > We have the attached patch (plus a few more hacks), I don't think it is > universally safe to change the calculation of reserved_end. Although > the patch has some code formatting problems you might consider using it > as a starting point. I don't use the Cavium u-boot boot loader on this. (And don't use any of the named blocks, or other data struct passing from the boot loader to the kernel). So the patch is not really useful for me. But I am interested, why do you think it is not safe to change reserved_end? There is the possible overlap of the kernels bootmem setup data that is not checked (which sparc does for example). But otherwise what problems do you see here? Regards Greg ------------------------------------------------------------------------ Greg Ungerer -- Principal Engineer EMAIL: gerg@snapgear.com SnapGear Group, McAfee PHONE: +61 7 3435 2888 8 Gardner Close FAX: +61 7 3217 5323 Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com From ddaney@caviumnetworks.com Fri Sep 10 21:11:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Sep 2010 21:11:50 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14176 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491127Ab0IJTLq (ORCPT ); Fri, 10 Sep 2010 21:11:46 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 10 Sep 2010 09:23:42 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 10 Sep 2010 09:23:08 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 10 Sep 2010 09:23:08 -0700 Message-ID: <4C8A5B6C.5080405@caviumnetworks.com> Date: Fri, 10 Sep 2010 09:23:08 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Greg Ungerer CC: linux-mips@linux-mips.org Subject: Re: [PATCH] mips: fix start of free memory when using initrd References: <201009080550.o885ohjD014188@goober.internal.moreton.com.au> <4C891863.1080602@caviumnetworks.com> <4C89CBDA.1030309@snapgear.com> In-Reply-To: <4C89CBDA.1030309@snapgear.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 10 Sep 2010 16:23:08.0583 (UTC) FILETIME=[74767370:01CB5104] X-archive-position: 27744 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 8672 Content-Length: 1153 Lines: 32 On 09/09/2010 11:10 PM, Greg Ungerer wrote: > > Hi David, > > David Daney wrote: [...] >> We have the attached patch (plus a few more hacks), I don't think it >> is universally safe to change the calculation of reserved_end. >> Although the patch has some code formatting problems you might >> consider using it as a starting point.> > I don't use the Cavium u-boot boot loader on this. (And don't use any > of the named blocks, or other data struct passing from the boot loader > to the kernel). So the patch is not really useful for me. > > But I am interested, why do you think it is not safe to change > reserved_end? For Octeon it is probably safe, but there is a reason that this complex logic for restricting the usable memory ranges exists. Other targets require it, so great care must be taken not to break the non-octeon targets. > > There is the possible overlap of the kernels bootmem setup data > that is not checked (which sparc does for example). But otherwise > what problems do you see here? > I lack the imagination necessary to come up with a failing scenario, but I am also paranoid, so I see danger everywhere. David Daney From andy.shevchenko@gmail.com Sat Sep 11 15:33:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 11 Sep 2010 15:33:53 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:45970 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491016Ab0IKNdr (ORCPT ); Sat, 11 Sep 2010 15:33:47 +0200 Received: by eye22 with SMTP id 22so2595888eye.36 for ; Sat, 11 Sep 2010 06:33:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=oVborOrv6sF1qWewRUmCF/JFKm48zwCfCAMSLlRnau0=; b=sKW9Ub2u3iMWFwD5ySt4GMkyGi/7hws1icU5zJoDfGaUOBbkC+lNnspaOXeNHW6Xps xMiJkfvHJYG4JnkchsSpaoay1fVfLRwxE6mN3ky3syrA6Wim+afwT2gIl12tjaXH0jNu ymgXyG/Q5gHrahyIkG7G4mYV5r59h+o+h7rEM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=cw1AhabBzBAE9w64Rphy+XfmNVEAg83nn1XoRXvmTxqI+RjdLQpoFhynYFCZRPGrgr CSVJ++yfKIC2Dj7qvOezwBkcJ5HcC2s2UxDk5A5cosBnK+m8jXUnjslZH3ZWrzUpHFVa MzxADZNE3azUF7TK0vtxLFlUo86cgZ4STwO4E= Received: by 10.213.7.131 with SMTP id d3mr340980ebd.55.1284212024831; Sat, 11 Sep 2010 06:33:44 -0700 (PDT) Received: from localhost.localdomain (79-134-110-186.cust.suomicom.fi [79.134.110.186]) by mx.google.com with ESMTPS id z55sm5736289eeh.9.2010.09.11.06.33.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 11 Sep 2010 06:33:44 -0700 (PDT) From: Andy Shevchenko To: linux-kernel@vger.kernel.org Cc: Andy Shevchenko , Ralf Baechle , linux-mips@linux-mips.org Subject: [PATCH] arch: mips: use newly introduced hex_to_bin() Date: Sat, 11 Sep 2010 16:33:29 +0300 Message-Id: <1284212009-25708-1-git-send-email-andy.shevchenko@gmail.com> X-Mailer: git-send-email 1.7.2.2 X-archive-position: 27745 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: andy.shevchenko@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9019 Content-Length: 1204 Lines: 54 Remove custom implementation of hex_to_bin(). Signed-off-by: Andy Shevchenko Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/rb532/devices.c | 24 +++++++++--------------- 1 files changed, 9 insertions(+), 15 deletions(-) diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 041fc1a..a969eb8 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -251,28 +251,22 @@ static struct platform_device *rb532_devs[] = { static void __init parse_mac_addr(char *macstr) { - int i, j; - unsigned char result, value; + int i, h, l; for (i = 0; i < 6; i++) { - result = 0; - if (i != 5 && *(macstr + 2) != ':') return; - for (j = 0; j < 2; j++) { - if (isxdigit(*macstr) - && (value = - isdigit(*macstr) ? *macstr - - '0' : toupper(*macstr) - 'A' + 10) < 16) { - result = result * 16 + value; - macstr++; - } else - return; - } + h = hex_to_bin(*macstr++); + if (h == -1) + return; + + l = hex_to_bin(*macstr++); + if (l == -1) + return; macstr++; - korina_dev0_data.mac[i] = result; + korina_dev0_data.mac[i] = (h << 4) + l; } } -- 1.7.2.2 From joe@perches.com Sun Sep 12 07:11:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 12 Sep 2010 07:11:17 +0200 (CEST) Received: from mail.perches.com ([173.55.12.10]:1757 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490984Ab0ILFLO (ORCPT ); Sun, 12 Sep 2010 07:11:14 +0200 Received: from Joe-Laptop.home (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id 260D42436E; Sat, 11 Sep 2010 22:10:56 -0700 (PDT) From: Joe Perches To: Jiri Kosina Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/11] arch/mips: Remove pr_ uses of KERN_ Date: Sat, 11 Sep 2010 22:10:52 -0700 Message-Id: X-Mailer: git-send-email 1.7.3.rc1 In-Reply-To: References: X-archive-position: 27746 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9211 Content-Length: 1160 Lines: 35 Signed-off-by: Joe Perches --- arch/mips/kernel/irq-gic.c | 2 +- arch/mips/pci/pci-rc32434.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index b181f2f..8d8a6ba 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -131,7 +131,7 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) int i; irq -= _irqbase; - pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq); + pr_debug("%s(%d) called\n", __func__, irq); cpumask_and(&tmp, cpumask, cpu_online_mask); if (cpus_empty(tmp)) return -1; diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c index 71f7d27..f31218e 100644 --- a/arch/mips/pci/pci-rc32434.c +++ b/arch/mips/pci/pci-rc32434.c @@ -118,7 +118,7 @@ static int __init rc32434_pcibridge_init(void) if (!((pcicvalue == PCIM_H_EA) || (pcicvalue == PCIM_H_IA_FIX) || (pcicvalue == PCIM_H_IA_RR))) { - pr_err(KERN_ERR "PCI init error!!!\n"); + pr_err("PCI init error!!!\n"); /* Not in Host Mode, return ERROR */ return -1; } -- 1.7.3.rc1 From joe@perches.com Sun Sep 12 07:11:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 12 Sep 2010 07:11:40 +0200 (CEST) Received: from mail.perches.com ([173.55.12.10]:1755 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490961Ab0ILFLO (ORCPT ); Sun, 12 Sep 2010 07:11:14 +0200 Received: from Joe-Laptop.home (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id 0E68224368; Sat, 11 Sep 2010 22:10:52 -0700 (PDT) From: Joe Perches To: Jiri Kosina Cc: Eric Miao , Russell King , Haavard Skinnemoen , Michal Simek , Ralf Baechle , Avi Kivity , Marcelo Tosatti , Alexander Graf , Benjamin Herrenschmidt , Paul Mackerras , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Tom Tucker , Steve Wise , Roland Dreier , Sean Hefty , Hal Rosenstock , Greg Kroah-Hartman , David Brownell , Geoff Levand , Jaroslav Kysela , Takashi Iwai , Liam Girdwood , Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, microblaze-uclinux@itee.uq.edu.au, linux-mips@linux-mips.org, kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-rdma@vger.kernel.org, netdev@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, cbe-oss-dev@lists.ozlabs.org, alsa-devel@alsa-project.org Subject: [PATCH 00/11] treewide: Remove pr_ uses with KERN_ Date: Sat, 11 Sep 2010 22:10:48 -0700 Message-Id: X-Mailer: git-send-email 1.7.3.rc1 X-archive-position: 27747 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9212 Content-Length: 1539 Lines: 35 Most of these are pr_debug(KERN_. pr_(KERN_ is unnecessary. Joe Perches (11): arch/arm: Remove pr_ uses of KERN_ arch/avr32: Remove pr_ uses of KERN_ arch/microblaze: Remove pr_ uses of KERN_ arch/mips: Remove pr_ uses of KERN_ arch/powerpc: Remove pr_ uses of KERN_ arch/x86: Remove pr_ uses of KERN_ drivers/infiniband: Remove pr_ uses of KERN_ drivers/net/skfp: Remove pr_ uses of KERN_ drivers/staging/msm: Remove pr_ uses of KERN_ drivers/usb/gadget: Remove pr_ uses of KERN_ sound: Remove pr_ uses of KERN_ arch/arm/mach-pxa/cpufreq-pxa2xx.c | 3 +- arch/avr32/mach-at32ap/at32ap700x.c | 4 +- arch/microblaze/kernel/exceptions.c | 16 ++---- arch/mips/kernel/irq-gic.c | 2 +- arch/mips/pci/pci-rc32434.c | 2 +- arch/powerpc/kvm/emulate.c | 4 +- arch/powerpc/sysdev/pmi.c | 2 +- arch/x86/kernel/apb_timer.c | 4 +- drivers/infiniband/hw/amso1100/c2_intr.c | 4 +- drivers/net/skfp/skfddi.c | 84 +++++++++++++++--------------- drivers/staging/msm/staging-devices.c | 2 +- drivers/usb/gadget/r8a66597-udc.c | 2 +- sound/ppc/snd_ps3.c | 2 +- sound/soc/s3c24xx/s3c-dma.c | 3 +- 14 files changed, 64 insertions(+), 70 deletions(-) -- 1.7.3.rc1 From florian@openwrt.org Sun Sep 12 19:12:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 12 Sep 2010 19:12:26 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:41123 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491075Ab0ILRMX convert rfc822-to-8bit (ORCPT ); Sun, 12 Sep 2010 19:12:23 +0200 Received: by wyb38 with SMTP id 38so5846223wyb.36 for ; Sun, 12 Sep 2010 10:12:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:reply-to:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=xKwZOE9eIcLeIUSBqeuXB+brHfvRKp3XTGMBqvuEK40=; b=Jw38lS64OqbvQO5Yb7VilyHG7FfqzlhIfPYnp80lpHjNaMTEmWBcbKNI9EbvmtQ+Tw LEaot/vTgq1SxhY434fGjs+P2yz52pO3Kd5CfVnfOf2pTgCcBaKCrQhvjfzWK1BKxM+m GJpKhKjL0yUfrAE3CothcVzBOIGDRsAs5YY1c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:reply-to:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=CvrE98wmHRkuXT5z693XqslDWiqdGCU6VgUw1fNSMXyBdUyu+4RpuyTYmlTNEnifIy I+7jY71ihK6Q8w93wNvvL0Zto55wKknI9n3/JyDzq65tNHNEMHWKWjWJ9rk/ij5Radqq Ef/QlQaQIJiuLBZwjrSVE+AzQyYd2Bhsbi5Bo= Received: by 10.216.176.83 with SMTP id a61mr3370673wem.47.1284311537205; Sun, 12 Sep 2010 10:12:17 -0700 (PDT) Received: from lenovo.localnet (129.199.66-86.rev.gaoland.net [86.66.199.129]) by mx.google.com with ESMTPS id k83sm3266568weq.14.2010.09.12.10.12.13 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 12 Sep 2010 10:12:14 -0700 (PDT) From: Florian Fainelli Reply-To: Florian Fainelli To: wuzhangjin@gmail.com Subject: Re: zboot for brcm Date: Sun, 12 Sep 2010 19:13:28 +0200 User-Agent: KMail/1.13.5 (Linux/2.6.35-trunk-amd64; KDE/4.4.5; x86_64; ; ) Cc: Waldemar Brodkorb , Ralf Baechle , "linux-mips" References: <20100609153831.GA27461@waldemar-brodkorb.de> <201006171438.15832.florian@openwrt.org> <1276781479.4271.8.camel@localhost> In-Reply-To: <1276781479.4271.8.camel@localhost> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Message-Id: <201009121913.29339.florian@openwrt.org> X-archive-position: 27748 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9368 Content-Length: 1353 Lines: 37 Hi Wu, Le Thursday 17 June 2010 15:31:19, Wu Zhangjin a écrit : > Hi, > > On Thu, 2010-06-17 at 14:38 +0200, Florian Fainelli wrote: > > Hi, > > > > On Thursday 17 June 2010 14:20:49 wu zhangjin wrote: > > > Hi, > > > > > > I just got a bcm1250a board, it also uses the CFE as the bootloader, I > > > compiled a compressed vmlinuz-2.6.34 for it and boot with the > > > following command, it works well: > > > > > > CFE> setenv bootargs root=/dev/nfs rw > > > nfsroot=$nfs_server_ip:/path/to/nfs_root_fs ip=dhcp > > > CFE> ifconfig -auto eth0 > > > CFE> boot -elf $tftp_server_ip:/path/to/vmlinuz > > > > > > With -elf, the boot command of CFE can parse the vmlinuz and boot it > > > normally. I think you have used the wrong options of the boot command. > > > > CFE on bcm12xx, on bcm47xx and bcm63xx are all three slightly different > > flavors which may not behave exactly the same way wrt the load command. > > > > Also, you are on a development board so there are no reasons to restrict > > CFE commands, this is not the case with end-user products like WRT54G > > and such. > > Hmm, Maybe, I have no such products to test, anybody have such products, > welcome to test it ;) I just ran into the issue described by Waldemar on a BCM6348 board. You mentionned you were writing a patch, do you have one I could test on BCM63xx? -- Florian From gerg@snapgear.com Mon Sep 13 08:27:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Sep 2010 08:27:34 +0200 (CEST) Received: from dalsmrelay2.nai.com ([205.227.136.216]:31070 "HELO dalsmrelay2.nai.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491093Ab0IMG11 (ORCPT ); Mon, 13 Sep 2010 08:27:27 +0200 Received: from (unknown [10.64.5.51]) by dalsmrelay2.nai.com with smtp id 7a50_17dc_f1442bae_beff_11df_acd8_00219b929abd; Mon, 13 Sep 2010 06:27:15 +0000 Received: from dalexbr1.corp.nai.org (161.69.111.81) by DALEXHT1.corp.nai.org (10.64.5.51) with Microsoft SMTP Server id 8.2.254.0; Mon, 13 Sep 2010 01:26:31 -0500 Received: from sncexbr1.corp.nai.org ([161.69.5.246]) by dalexbr1.corp.nai.org with Microsoft SMTPSVC(6.0.3790.3959); Mon, 13 Sep 2010 01:26:30 -0500 Received: from STPSMTP01.scur.com ([10.96.96.163]) by sncexbr1.corp.nai.org with Microsoft SMTPSVC(6.0.3790.3959); Sun, 12 Sep 2010 23:26:28 -0700 Received: from cyberguard.com.au ([10.46.129.16]) by STPSMTP01.scur.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 13 Sep 2010 01:26:28 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by bne.snapgear.com (Postfix) with ESMTP id 9ADCAEBACC; Mon, 13 Sep 2010 16:26:26 +1000 (EST) X-Virus-Scanned: amavisd-new at snapgear.com Received: from bne.snapgear.com ([127.0.0.1]) by localhost (bne.snapgear.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9PTK4kC2wECb; Mon, 13 Sep 2010 16:26:18 +1000 (EST) Received: from [172.22.196.222] (bnelabfw.scur.com [10.46.129.16]) by bne.snapgear.com (Postfix) with ESMTP; Mon, 13 Sep 2010 16:26:18 +1000 (EST) Message-ID: <4C8DC3CF.6030909@snapgear.com> Date: Mon, 13 Sep 2010 16:25:19 +1000 From: Greg Ungerer User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org Subject: Re: [PATCH] mips: fix start of free memory when using initrd References: <201009080550.o885ohjD014188@goober.internal.moreton.com.au> <4C891863.1080602@caviumnetworks.com> <4C89CBDA.1030309@snapgear.com> <4C8A5B6C.5080405@caviumnetworks.com> In-Reply-To: <4C8A5B6C.5080405@caviumnetworks.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 13 Sep 2010 06:26:28.0353 (UTC) FILETIME=[991A1F10:01CB530C] X-archive-position: 27749 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gerg@snapgear.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 9655 Content-Length: 1598 Lines: 43 David Daney wrote: > On 09/09/2010 11:10 PM, Greg Ungerer wrote: >> >> Hi David, >> >> David Daney wrote: > [...] >>> We have the attached patch (plus a few more hacks), I don't think it >>> is universally safe to change the calculation of reserved_end. >>> Although the patch has some code formatting problems you might >>> consider using it as a starting point.> >> I don't use the Cavium u-boot boot loader on this. (And don't use any >> of the named blocks, or other data struct passing from the boot loader >> to the kernel). So the patch is not really useful for me. >> >> But I am interested, why do you think it is not safe to change >> reserved_end? > > For Octeon it is probably safe, but there is a reason that this complex > logic for restricting the usable memory ranges exists. Other targets > require it, so great care must be taken not to break the non-octeon > targets. > >> >> There is the possible overlap of the kernels bootmem setup data >> that is not checked (which sparc does for example). But otherwise >> what problems do you see here? >> > > I lack the imagination necessary to come up with a failing scenario, but > I am also paranoid, so I see danger everywhere. Good answer :-) Regards Greg ------------------------------------------------------------------------ Greg Ungerer -- Principal Engineer EMAIL: gerg@snapgear.com SnapGear Group, McAfee PHONE: +61 7 3435 2888 8 Gardner Close FAX: +61 7 3217 5323 Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com From joe@perches.com Mon Sep 13 21:48:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Sep 2010 21:48:33 +0200 (CEST) Received: from mail.perches.com ([173.55.12.10]:1857 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490954Ab0IMTsa (ORCPT ); Mon, 13 Sep 2010 21:48:30 +0200 Received: from Joe-Laptop.home (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id 35B3A2436B; Mon, 13 Sep 2010 12:48:21 -0700 (PDT) From: Joe Perches To: linux-kernel@vger.kernel.org Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: [PATCH 01/25] arch/mips: Use static const char arrays Date: Mon, 13 Sep 2010 12:47:39 -0700 Message-Id: <8fcec0d2a48e806558e6bc39d5aa98518a97f8c7.1284406638.git.joe@perches.com> X-Mailer: git-send-email 1.7.3.rc1 In-Reply-To: References: X-archive-position: 27750 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10273 Content-Length: 740 Lines: 23 Signed-off-by: Joe Perches --- arch/mips/pnx8550/common/reset.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c index fadd874..e0ac0b2 100644 --- a/arch/mips/pnx8550/common/reset.c +++ b/arch/mips/pnx8550/common/reset.c @@ -27,8 +27,8 @@ void pnx8550_machine_restart(char *command) { - char head[] = "************* Machine restart *************"; - char foot[] = "*******************************************"; + static const char head[] = "************* Machine restart *************"; + static const char foot[] = "*******************************************"; printk("\n\n"); printk("%s\n", head); -- 1.7.3.rc1 From joe@perches.com Mon Sep 13 21:48:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Sep 2010 21:48:58 +0200 (CEST) Received: from mail.perches.com ([173.55.12.10]:1884 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491072Ab0IMTsd (ORCPT ); Mon, 13 Sep 2010 21:48:33 +0200 Received: from Joe-Laptop.home (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id C8C0324368; Mon, 13 Sep 2010 12:48:19 -0700 (PDT) From: Joe Perches To: linux-kernel@vger.kernel.org Cc: Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Len Brown , Linus Walleij , "Jean Delvare (PC drivers, core)" , "Ben Dooks (embedded platforms)" , Karsten Keil , Mauro Carvalho Chehab , Jeff Kirsher , Jesse Brandeburg , Bruce Allan , Alex Duyck , PJ Waskiewicz , John Ronciak , Amit Kumar Salecha , Anirban Chakraborty , linux-driver@qlogic.com, Ishizaki Kou , Jens Osterkamp , Shreyas Bhatewara , "VMware, Inc." , "John W. Linville" , Martin Schwidefsky , Heiko Carstens , linux390@de.ibm.com, "James E.J. Bottomley" , James Smart , Neela Syam Kolli , "David S. Miller" , Brett Rudley , Henry Ptasinski , Nohee Ko , Greg Kroah-Hartman , Thomas Winischhofer , Joseph Chan , Florian Tobias Schandinat , "J. Bruce Fields" , Neil Brown , Trond Myklebust , Jaroslav Kysela , Takashi Iwai , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, mjpeg-users@lists.sourceforge.net, linux-media@vger.kernel.org, e1000-devel@lists.sourceforge.net, linux-wireless@vger.kernel.org, linux-s390@vger.kernel.org, linux-scsi@vger.kernel.org, sparclinux@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-nfs@vger.kernel.org, alsa-devel@alsa-project.org Subject: [PATCH 00/25] treewide-next: Use static const char arrays Date: Mon, 13 Sep 2010 12:47:38 -0700 Message-Id: X-Mailer: git-send-email 1.7.3.rc1 X-archive-position: 27751 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10279 Content-Length: 5496 Lines: 106 Using static const char foo[] = "bar" can save some code and text space, so change the places where it's possible. Also change the places that use char foo[] = "barX"; ... foo[3] = value + '0'; where X is typically changed char foo[sizeof("barX")]; ... sprintf(foo, "bar%c", value + '0'); Joe Perches (25): arch/mips: Use static const char arrays arch/powerpc: Use static const char arrays drivers/acpi: Use static const char arrays drivers/char: Use static const char arrays drivers/i2c: Use static const char arrays drivers/isdn: Use static const char arrays drivers/media: Use static const char arrays drivers/net/atl1c: Use static const char arrays drivers/net/atl1e: Use static const char arrays drivers/net/(intel): Use static const char arrays drivers/net/netxen: Use static const char arrays drivers/net/qlcnic: Use static const char arrays drivers/net/spider_net.c: Use static const char arrays drivers/net/vnxnet3: Use static const char arrays drivers/net/wireless/ipw2x00: Use static const char arrays drivers/s390/char: Use static const char arrays drivers/scsi: Use static const char arrays drivers/serial/suncore.c: Use static const char arrays drivers/staging: Use static const char arrays drivers/usb: Use static const char arrays drivers/video: Use static const char arrays net/dsa: Use static const char arrays net/sunrpc: Use static const char arrays sound: Use static const char arrays tools/perf/util: Use static const char arrays arch/mips/pnx8550/common/reset.c | 4 ++-- arch/powerpc/boot/addnote.c | 4 ++-- arch/powerpc/boot/cuboot-c2k.c | 4 ++-- arch/powerpc/kernel/irq.c | 2 +- drivers/acpi/sleep.c | 4 ++-- drivers/char/hvc_vio.c | 2 +- drivers/i2c/busses/i2c-stu300.c | 4 ++-- drivers/isdn/hysdn/hycapi.c | 2 +- drivers/isdn/mISDN/dsp_cmx.c | 2 +- drivers/media/video/zoran/zoran_device.c | 5 ++--- drivers/net/atl1c/atl1c.h | 4 ++-- drivers/net/atl1c/atl1c_main.c | 4 ++-- drivers/net/atl1e/atl1e.h | 4 ++-- drivers/net/atl1e/atl1e_main.c | 4 ++-- drivers/net/e1000/e1000.h | 2 +- drivers/net/e1000/e1000_main.c | 4 ++-- drivers/net/e1000e/e1000.h | 2 +- drivers/net/e1000e/netdev.c | 2 +- drivers/net/igb/igb.h | 4 ++-- drivers/net/igb/igb_main.c | 4 ++-- drivers/net/igbvf/igbvf.h | 2 +- drivers/net/igbvf/netdev.c | 2 +- drivers/net/ixgb/ixgb.h | 2 +- drivers/net/ixgb/ixgb_main.c | 2 +- drivers/net/ixgbe/ixgbe.h | 2 +- drivers/net/ixgbe/ixgbe_main.c | 4 ++-- drivers/net/ixgbevf/ixgbevf.h | 2 +- drivers/net/ixgbevf/ixgbevf_main.c | 2 +- drivers/net/netxen/netxen_nic.h | 2 +- drivers/net/netxen/netxen_nic_main.c | 2 +- drivers/net/qlcnic/qlcnic.h | 2 +- drivers/net/qlcnic/qlcnic_main.c | 2 +- drivers/net/spider_net.c | 2 +- drivers/net/vmxnet3/vmxnet3_drv.c | 2 +- drivers/net/vmxnet3/vmxnet3_int.h | 2 +- drivers/net/wireless/ipw2x00/ipw2100.c | 2 +- drivers/net/wireless/ipw2x00/ipw2200.c | 2 +- drivers/net/wireless/ipw2x00/libipw_module.c | 2 +- drivers/s390/char/vmlogrdr.c | 4 ++-- drivers/scsi/bnx2i/bnx2i_hwi.c | 6 +++--- drivers/scsi/lpfc/lpfc_init.c | 2 +- drivers/scsi/megaraid/megaraid_mbox.c | 6 +++--- drivers/serial/suncore.c | 4 ++-- drivers/staging/brcm80211/util/bcmutils.c | 2 +- drivers/staging/comedi/drivers/comedi_bond.c | 2 +- drivers/staging/cxt1e1/ossiRelease.c | 2 +- drivers/staging/go7007/go7007-driver.c | 2 +- drivers/staging/msm/mdp.c | 2 +- .../staging/rtl8192e/ieee80211/ieee80211_module.c | 2 +- .../staging/rtl8192u/ieee80211/ieee80211_module.c | 2 +- drivers/staging/tidspbridge/rmgr/dbdcd.c | 6 +++--- drivers/usb/atm/ueagle-atm.c | 14 +++++--------- drivers/usb/otg/langwell_otg.c | 2 +- drivers/video/sh_mipi_dsi.c | 4 ++-- drivers/video/sis/sis_main.c | 10 +++++----- drivers/video/via/viafbdev.c | 2 +- net/dsa/dsa.c | 2 +- net/dsa/dsa_priv.h | 2 +- net/sunrpc/auth_gss/gss_krb5_mech.c | 2 +- sound/core/misc.c | 5 ++++- tools/perf/util/ui/setup.c | 3 ++- tools/perf/util/ui/util.c | 3 ++- 62 files changed, 98 insertions(+), 98 deletions(-) -- 1.7.3.rc1 From dhowells@redhat.com Tue Sep 14 11:16:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Sep 2010 11:16:47 +0200 (CEST) Received: from mx1.redhat.com ([209.132.183.28]:44786 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491095Ab0INJQn (ORCPT ); Tue, 14 Sep 2010 11:16:43 +0200 Received: from int-mx08.intmail.prod.int.phx2.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.21]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id o8E9FElb031305 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 14 Sep 2010 05:15:14 -0400 Received: from redhat.com ([10.3.112.2]) by int-mx08.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id o8E9EjUt018637; Tue, 14 Sep 2010 05:14:46 -0400 Organization: Red Hat UK Ltd. Registered Address: Red Hat UK Ltd, Amberley Place, 107-111 Peascod Street, Windsor, Berkshire, SI4 1TE, United Kingdom. Registered in England and Wales under Company Registration No. 3798903 From: David Howells In-Reply-To: References: To: Joe Perches Cc: dhowells@redhat.com, linux-kernel@vger.kernel.org, Amit Kumar Salecha , linux-fbdev@vger.kernel.org, Greg Kroah-Hartman , James Smart , linux-mips@linux-mips.org, "VMware, Inc." , PJ Waskiewicz , Shreyas Bhatewara , alsa-devel@alsa-project.org, Jaroslav Kysela , "J. Bruce Fields" , "James E.J. Bottomley" , Paul Mackerras , linux-i2c@vger.kernel.org, Brett Rudley , sparclinux@vger.kernel.org, Martin Schwidefsky , devel@driverdev.osuosl.org, linux-s390@vger.kernel.org, linux-acpi@vger.kernel.org, linux-scsi@vger.kernel.org, Florian Tobias Schandinat , e1000-devel@lists.sourceforge.net, Trond Myklebust , Jesse Brandeburg , Neil Brown , Jeff Kirsher , linux-wireless@vger.kernel.org, Ingo Molnar , linux-usb@vger.kernel.org, Len Brown , Alex Duyck , Peter Zijlstra , Henry Ptasinski , Heiko Carstens , Thomas Winischhofer , Mauro Carvalho Chehab , Arnaldo Carvalho de Melo , "Jean Delvare \(PC drivers, core\)" , mjpeg-users@lists.sourceforge.net, "Ben Dooks \(embedded platforms\)" , linux-nfs@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neela Syam Kolli , Karsten Keil , Linus Walleij , netdev@vger.kernel.org, Anirban Chakraborty , Bruce Allan Date: Tue, 14 Sep 2010 10:14:45 +0100 Message-ID: <28081.1284455685@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.21 X-archive-position: 27752 Subject: (no subject) X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dhowells@redhat.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 10737 Content-Length: 488 Lines: 20 Joe Perches wrote: > Using static const char foo[] = "bar" can save some > code and text space, so change the places where it's possible. That's reasonable. > Also change the places that use > char foo[] = "barX"; > ... > foo[3] = value + '0'; > where X is typically changed > char foo[sizeof("barX")]; > ... > sprintf(foo, "bar%c", value + '0'); You haven't said what this gains. I can see what it may cost, though (depending on how gcc loads foo[]). David From ralf@linux-mips.org Wed Sep 15 15:28:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Sep 2010 15:28:16 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1490951Ab0ION2M (ORCPT ); Wed, 15 Sep 2010 15:28:12 +0200 Date: Wed, 15 Sep 2010 15:28:11 +0200 From: Ralf Baechle To: Florian Fainelli Cc: wuzhangjin@gmail.com, Waldemar Brodkorb , linux-mips Subject: Re: zboot for brcm Message-ID: <20100915132811.GA6704@linux-mips.org> References: <20100609153831.GA27461@waldemar-brodkorb.de> <201006171438.15832.florian@openwrt.org> <1276781479.4271.8.camel@localhost> <201009121913.29339.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201009121913.29339.florian@openwrt.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27753 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 11783 Content-Length: 468 Lines: 10 On Sun, Sep 12, 2010 at 07:13:28PM +0200, Florian Fainelli wrote: Be careful with the firmware. On Sibyte systems Linux queries the firmware for available memory ranges. The memory ranges are based on the sizes of the sizes of the ELF file as loaded. That means after decompression it is possible that the kernel will treat some memory as free even though it it is actually used. Due to various other circumstances this does not actually hit all systems. Ralf From ddaney@caviumnetworks.com Wed Sep 15 17:58:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Sep 2010 17:58:10 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4456 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491099Ab0IOP6C (ORCPT ); Wed, 15 Sep 2010 17:58:02 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 15 Sep 2010 08:58:28 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 15 Sep 2010 08:57:57 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 15 Sep 2010 08:57:57 -0700 Message-ID: <4C90ECFF.8010903@caviumnetworks.com> Date: Wed, 15 Sep 2010 08:57:51 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Gregory Giraud CC: mlistz@gmail.com, linux-mips@linux-mips.org Subject: Re: cavium reference board, sdk 1.9.0 and the latest linux kernel References: <490843.51422.qm@web28307.mail.ukl.yahoo.com> In-Reply-To: <490843.51422.qm@web28307.mail.ukl.yahoo.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 15 Sep 2010 15:57:57.0394 (UTC) FILETIME=[C3CA0F20:01CB54EE] X-archive-position: 27754 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 11937 Content-Length: 7705 Lines: 193 On 09/15/2010 05:15 AM, Gregory Giraud wrote: > Hi, > > I found your post on > http://www.linux-mips.org/archives/linux-mips/2010-02/msg00005.html. > I have the same problem on CN31xx with updating kernel to 2.6.29. > > Have you solve it? > Yes. The root filesystem binaries (including init) that come as part of the Octeon SDK are not compatible with generic Linux kernels. Any attempt to use the binaries of the SDK rootfs with a generic kernel will result in the behavior you observe. You need to use root filesystem binaries that are compatible with the standard MIPS Linux ABIs. I would suggest Debian as a starting point. David Daney > Thx > > Grégory GIRAUD > > > > > > > Hi, > > Currently I am working on a cavium CN56xx reference board using cavium > sdk 1.9.0. the linux kernel bundled in sdk is 2.6.27. which works fine > on the reference board. > > but while i am trying to use the latest linux kernel, ie. 2.6.31, > 2.6.32, 2.6.33-rc4, i encountered the same problem: "Kernel panic - > not syncing: Attempted to kill init!". > > here is the boot log (initramfs is compiled into the kernel, the linux > config file is attached to this mail): > > Bytes transferred = 66099593 (3f09989 hex), 1965 Kbytes/sec > argv[2]: root=/dev/ram0 > argv[3]: rw > argv[4]: panic=1 > argv[5]: init=/linuxrc > argv[6]: coremask=0xfff > argv[7]: console=ttyS1,115200 > ELF file is 64 bit > Attempting to allocate memory for ELF segment: addr: > 0xffffffff81100000 (adjusted to: 0x0000000001100000), size 0x25e6e30 > Allocated memory for ELF segment: addr: 0xffffffff81100000, size 0x25e6e30 > Processing PHDR 0 > Loading 25b5a80 bytes at ffffffff81100000 > Clearing 313b0 bytes at ffffffff836b5a80 > ## Loading Linux kernel with entry point: 0xffffffff81105f10 ... > Bootloader: Done loading app on coremask: 0xfff > Linux version 2.6.31 (root@R710) (gcc version 4.3.3 (Cavium Networks > Version: 1_9_0 build 80) ) #17 SMP PREEMPT Tue Jan 19 01:19:220 > CVMSEG size: 2 cache lines (256 bytes) > CPU revision is: 000d0409 (Cavium Octeon) > Checking for the multiply/shift bug... no. > Checking for the daddiu bug... no. > Determined physical RAM map: > memory: 00000000022ce000 @ 00000000013e8000 (usable) > memory: 000000000c800000 @ 0000000003700000 (usable) > memory: 0000000011800000 @ 0000000020000000 (usable) > Wasting 326144 bytes for tracking 5096 unused pages > Initrd not found or empty - disabling initrd > Zone PFN ranges: > Normal 0x000013e8 -> 0x00031800 > Movable zone start PFN for each node > early_node_map[3] active PFN ranges > 0: 0x000013e8 -> 0x000036b6 > 0: 0x00003700 -> 0x0000ff00 > 0: 0x00020000 -> 0x00031800 > Built 1 zonelists in Zone order, mobility grouping on. Total pages: 128701 > Kernel command line: bootoctlinux 0x20000000 root=/dev/ram0 rw > panic=1 init=/linuxrc coremask=0xfff console=ttyS1,115200 > PID hash table entries: 2048 (order: 11, 16384 bytes) > Dentry cache hash table entries: 65536 (order: 7, 524288 bytes) > Inode-cache hash table entries: 32768 (order: 6, 262144 bytes) > Primary instruction cache 32kB, virtually tagged, 4 way, 64 sets, > linesize 128 bytes. > Primary data cache 16kB, 64-way, 2 sets, linesize 128 bytes. > Memory: 477572k/527160k available (2185k kernel code, 49004k reserved, > 788k data, 35640k init, 0k highmem) > NR_IRQS:152 > console [ttyS1] enabled > Calibrating delay using timer specific routine.. 1602.37 BogoMIPS (lpj=3204755) > Security Framework initialized > Mount-cache hash table entries: 256 > Checking for the daddi bug... no. > SMP: Booting CPU01 (CoreId 1)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.69 BogoMIPS (lpj=3203395) > SMP: Booting CPU02 (CoreId 2)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203612) > SMP: Booting CPU03 (CoreId 3)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.68 BogoMIPS (lpj=3203378) > SMP: Booting CPU04 (CoreId 4)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203610) > SMP: Booting CPU05 (CoreId 5)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.68 BogoMIPS (lpj=3203375) > SMP: Booting CPU06 (CoreId 6)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203606) > SMP: Booting CPU07 (CoreId 7)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.68 BogoMIPS (lpj=3203376) > SMP: Booting CPU08 (CoreId 8)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203607) > SMP: Booting CPU09 (CoreId 9)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.68 BogoMIPS (lpj=3203376) > SMP: Booting CPU10 (CoreId 10)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203605) > SMP: Booting CPU11 (CoreId 11)... > CPU revision is: 000d0409 (Cavium Octeon) > Calibrating delay using timer specific routine.. 1601.61 BogoMIPS (lpj=3203229) > Brought up 12 CPUs > NET: Registered protocol family 16 > bio: create slab at 0 > NET: Registered protocol family 2 > IP route cache hash table entries: 16384 (order: 5, 131072 bytes) > TCP established hash table entries: 65536 (order: 8, 1048576 bytes) > TCP bind hash table entries: 65536 (order: 9, 2097152 bytes) > TCP: Hash tables configured (established 65536 bind 65536) > TCP reno registered > NET: Registered protocol family 1 > msgmni has been set to 933 > alg: No test for stdrng (krng) > io scheduler noop registered > io scheduler anticipatory registered > io scheduler deadline registered > io scheduler cfq registered (default) > Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled > serial8250.0: ttyS1 at MMIO 0x1180000000c00 (irq = 59) is a OCTEON > brd: module loaded > loop: module loaded > TCP cubic registered > NET: Registered protocol family 17 > Bootbus flash: Setting flash for 64MB flash at 0x1bc00000 > drivers/mtd/chips/cfi_probe.c:166 > phys_mapped_flash: Found 1 x16 devices at 0x0 in 16-bit bank > Amd/Fujitsu Extended Query Table at 0x0040 > phys_mapped_flash: CFI does not contain boot bank location. Assuming top. > number of CFI chips: 1 > cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. > Creating 4 MTD partitions on "phys_mapped_flash": > 0x000000080000-0x000000680000 : "O60H BOOT" > 0x000000680000-0x000003f80000 : "O60H ROOT" > 0x000000000000-0x000000080000 : "U-BOOT" > 0x000003f80000-0x000004000000 : "U-BOOT(env)" > Freeing unused kernel memory: 35640k freed > Kernel panic - not syncing: Attempted to kill init! > Rebooting in 1 seconds.. > > U-Boot 1.1.1 (Development build) (Build time: May 25 2009 - 16:32:17) > > EBH5600 board revision major:1, minor:0 > OCTEON CN5650-NSP pass 2.1, Core clock: 800 MHz, DDR clock: 400 MHz > (800 Mhz data rate) > Warning: Board descriptor tuple not found in eeprom, using defaults > DRAM: 4096 MB > Flash: 64 MB > Clearing DRAM........ done > BIST check passed. > > > My question is, what is the current status of octeon plus cn56xx > support in official linux kernel release? Is cavium cn56xx reference > board supported? If the answer is 'yes', how can I make the latest > kernel and boot it successfully on the reference board? > > Thanks very much. I will be glad to provide more information if required. > > Zhuang Yuyao > > > > From Andrei.Ardelean@idt.com Wed Sep 15 21:46:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Sep 2010 21:46:59 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:45028 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491194Ab0IOTqw convert rfc822-to-8bit (ORCPT ); Wed, 15 Sep 2010 21:46:52 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o8FJkgpL000926 for ; Wed, 15 Sep 2010 12:46:44 -0700 Received: from corpml3.corp.idt.com (corpml3.corp.idt.com [157.165.140.25]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o8FJkfS1015830 for ; Wed, 15 Sep 2010 12:46:41 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml3.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o8FJkee08207 for ; Wed, 15 Sep 2010 12:46:41 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: What is CONFIG_MIPS_MT_SMTC configuration and when is this recommended to be used? Date: Wed, 15 Sep 2010 12:46:21 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: What is CONFIG_MIPS_MT_SMTC configuration and when is this recommended to be used? thread-index: ActVDqxAIq/93GROQ4+Q0liIrF0MFw== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 X-archive-position: 27755 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12154 Content-Length: 193 Lines: 9 Hi, I use Linux on MALTA board. My final goal is to port Linux on new board based on MIPS. What is CONFIG_MIPS_MT_SMTC configuration and when is this recommended to be used? Thanks, Andrei From Andrei.Ardelean@idt.com Wed Sep 15 22:04:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Sep 2010 22:04:19 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:45751 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491199Ab0IOUEP convert rfc822-to-8bit (ORCPT ); Wed, 15 Sep 2010 22:04:15 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o8FK4531002083 for ; Wed, 15 Sep 2010 13:04:05 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o8FK44KA017633 for ; Wed, 15 Sep 2010 13:04:04 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o8FK44V11060 for ; Wed, 15 Sep 2010 13:04:04 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Porting Linux MIPS issue: maltaint.h files Date: Wed, 15 Sep 2010 13:04:02 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: Porting Linux MIPS issue: maltaint.h files thread-index: ActVESSR6exOsg8YQTCwq46yvftflQ== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 X-archive-position: 27756 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12172 Content-Length: 387 Lines: 15 Hi, I am porting LINUX MIPS from MALTA on a new board. The problem is that .../mips-boards/maltaint.h files is included in a non-MALTA specific file, irq-gic.c, without #ifdef CONFIG_MALTA protection. The only need there is for the following constant: #define X 0xdead What is the recommended way to follow since I will replace maltaint.h with my new file gdint.h? Thanks, Andrei From kevink@paralogos.com Wed Sep 15 22:56:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Sep 2010 22:56:19 +0200 (CEST) Received: from gateway01.websitewelcome.com ([69.93.106.19]:47653 "HELO gateway01.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491132Ab0IOU4Q (ORCPT ); Wed, 15 Sep 2010 22:56:16 +0200 Received: (qmail 32379 invoked from network); 15 Sep 2010 20:56:09 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway01.websitewelcome.com with SMTP; 15 Sep 2010 20:56:09 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding; b=dDLtasOHIwCZdb+ZaVoWZSXu0g7HwJP+MXeIVgAA2M7Dv6FGZ2VO4FfhnXqwIydC8m7Uu5mqw8JApH7g4CKYJIjH7PuyOh+iXbKk4F3VPx8851590k0r62ewOlPPMGdc; Received: from [216.239.45.4] (port=57636 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1Ovz1S-0008W2-Mb; Wed, 15 Sep 2010 15:56:06 -0500 Message-ID: <4C9132E9.6060807@paralogos.com> Date: Wed, 15 Sep 2010 13:56:09 -0700 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.12) Gecko/20100826 Thunderbird/3.0.7 MIME-Version: 1.0 To: "Ardelean, Andrei" CC: linux-mips@linux-mips.org Subject: Re: What is CONFIG_MIPS_MT_SMTC configuration and when is this recommended to be used? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-archive-position: 27757 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12202 Content-Length: 516 Lines: 19 SMTC is a kernel for the 34K (and, just maybe, with some mods, 1004K) that turns TC microthreads into virtual SMP CPUs. See http://tree.celinuxforum.org/CelfPubWiki/ELC2006Presentations?action=AttachFile&do=view&target=CELF_SMTC_April_2006_v0.3.pdf /K. On 09/15/10 12:46, Ardelean, Andrei wrote: > Hi, > > I use Linux on MALTA board. My final goal is to port Linux on new board > based on MIPS. What is CONFIG_MIPS_MT_SMTC configuration and when is > this recommended to be used? > > Thanks, > Andrei > > > From ralf@linux-mips.org Thu Sep 16 12:34:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Sep 2010 12:35:01 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491040Ab0IPKes (ORCPT ); Thu, 16 Sep 2010 12:34:48 +0200 Date: Thu, 16 Sep 2010 11:34:46 +0100 From: Ralf Baechle To: "Kevin D. Kissell" Cc: "Ardelean, Andrei" , linux-mips@linux-mips.org Subject: Re: What is CONFIG_MIPS_MT_SMTC configuration and when is this recommended to be used? Message-ID: <20100916103446.GA13219@linux-mips.org> References: <4C9132E9.6060807@paralogos.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C9132E9.6060807@paralogos.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27758 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 12645 Content-Length: 636 Lines: 14 On Wed, Sep 15, 2010 at 01:56:09PM -0700, Kevin D. Kissell wrote: > SMTC is a kernel for the 34K (and, just maybe, with some mods, > 1004K) that turns TC microthreads into virtual SMP CPUs. See > http://tree.celinuxforum.org/CelfPubWiki/ELC2006Presentations?action=AttachFile&do=view&target=CELF_SMTC_April_2006_v0.3.pdf The help text provided for the MIPS_MT_SMP (VSMP) and MIPS_MT_SMTC options didn't make it easier to understand what SMTC is by incorrectly stating that MIPS marketing had renamed both to SMVP. I used the opportunity to rewrite the help text and slightly polish http://www.linux-mips.org/wiki/SMTC#SMTC Ralf From ralf@linux-mips.org Fri Sep 17 01:57:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Sep 2010 01:57:45 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491076Ab0IPX5l (ORCPT ); Fri, 17 Sep 2010 01:57:41 +0200 Date: Fri, 17 Sep 2010 00:57:39 +0100 From: Ralf Baechle To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Subject: Re: Porting Linux MIPS issue: maltaint.h files Message-ID: <20100916235739.GA16949@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27759 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13241 Content-Length: 1064 Lines: 26 On Wed, Sep 15, 2010 at 01:04:02PM -0700, Ardelean, Andrei wrote: > I am porting LINUX MIPS from MALTA on a new board. The problem is that > .../mips-boards/maltaint.h files is included in a non-MALTA specific > file, irq-gic.c, without #ifdef CONFIG_MALTA protection. The only need > there is for the following constant: > #define X 0xdead That's just poor programming style. 1 character long names in headers are begging for conflicts and with few exceptions as the universal loop index variables i, j, k are not descriptive. Including system specific headers hinders code reusability and reusability is the reason why most of the irq-*.c files are in arch/mips/kernel and not hidden away in some platform specific directory. > What is the recommended way to follow since I will replace maltaint.h > with my new file gdint.h? Post a patch to cleanup the mess. In this case (and I haven't looked at it for more than 30s ...) it seems that the constant X should be moved into after which the inclusion of the Malta header can go away. Ralf From arrow.ebd@gmail.com Fri Sep 17 14:55:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Sep 2010 14:55:55 +0200 (CEST) Received: from mail-qy0-f170.google.com ([209.85.216.170]:43148 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491769Ab0IQMzv (ORCPT ); Fri, 17 Sep 2010 14:55:51 +0200 Received: by qyk35 with SMTP id 35so973684qyk.15 for ; Fri, 17 Sep 2010 05:55:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=9GlNtSkt+8zU6R0CwxsaAJebwMZBrjUSz2wKRfQlots=; b=KWp2eElQBKvVqSojZXIcQHo7TScvVqpWzGD//KNvbwXX/4eUODcfSVbqoQRU+/Ka7S yc4smW/W8ncMtl2IVoGVRFpzm0nqQtpiDmIVy2eMIwZPPCuwmGrn0candX2iuD0WaaXI auP1Xpv6Lr0+x3Wze4FKpFBKsBlvF0ftgD7/U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=g9cP7pBLSDUGsF1RL+acWcwzO2ZAl4Zg3I+vfeLHOW9wLY6OUqcaTcgR3iL/L743BR /wCnsOzxKTkDiRSs+ts0dP+L9iGDAjXaF1IawB0/jGZfRRXG9wxeM82Zh1EoIpQUa/iY nGc1OHbkfvb8hLf8KGiyFCjkojuWdeQZdfdqE= MIME-Version: 1.0 Received: by 10.224.67.65 with SMTP id q1mr3326524qai.243.1284728145700; Fri, 17 Sep 2010 05:55:45 -0700 (PDT) Received: by 10.229.19.129 with HTTP; Fri, 17 Sep 2010 05:55:43 -0700 (PDT) Date: Fri, 17 Sep 2010 20:55:43 +0800 Message-ID: Subject: [HELP] Oops when insmod iptable_filter From: arrow zhang To: linux-mips@linux-mips.org, OpenWrt Content-Type: text/plain; charset=UTF-8 X-archive-position: 27760 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arrow.ebd@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13595 Content-Length: 3885 Lines: 107 Here has a difficult problem for me, would like anyone give some advice On a mips r3000 cpu, here has a kernel crash when doing the insmod iptable_filter, The phenomenon is same as https://dev.openwrt.org/ticket/6129 1, the FW is at openwrt versoin r23057 2, the crash occurs if insmod automatically by preinit 3, but not has crash if insmod within "failsafe mode" 4, the crash address is random in the "iptable_filter_init" progress, seems the symbol or page address invalidate and sometime may crash at any other modules, (e.g. iptable_mangle/raw, but iptable_filter module is crash every time) 5, refer from the "crash log" "Cause : 00000008", maybe is a TLB issue, but I have no idea about the debug direction I have try something as these * check the irq routine * double check file arch/mips/mm/c-r3k.c * double check file arch/mips/mm/tlb-r3k.c * try to remove the patch : target/linux/generic/patches-2.6.35/027-mips_module_reloc.patch * try to remove the patch : target/linux/generic/patches-2.6.35/028-module_exports.patch * try to remove the patch : target/linux/generic/patches-2.6.35/202-mips_mem_functions_performance.patch but all can not fix this bug next is the crash log (some printk added at sys_init_module) {{{ device eth0 entered promiscuous mode br-lan: port 1(eth0) entering forwarding state br-lan: port 1(eth0) entering forwarding state sys_init_module 2626, name: crc_ccitt sys_init_module 2636 sys_init_module 2641 sys_init_module 2626, name: slhc sys_init_module 2636 sys_init_module 2641 sys_init_module 2626, name: ppp_generic sys_init_module 2636 sys_init_module 2638 PPP generic driver version 2.4.2 sys_init_module 2641 sys_init_module 2626, name: ppp_async sys_init_module 2636 sys_init_module 2638 sys_init_module 2641 sys_init_module 2626, name: x_tables sys_init_module 2636 sys_init_module 2638 sys_init_module 2641 sys_init_module 2626, name: xt_tcpudp sys_init_module 2636 sys_init_module 2638 sys_init_module 2641 sys_init_module 2626, name: ip_tables sys_init_module 2636 sys_init_module 2638 ip_tables: (C) 2000-2006 Netfilter Core Team sys_init_module 2641 sys_init_module 2626, name: iptable_filter sys_init_module 2636 sys_init_module 2638 CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 81a6e030, ra == 81a6e024 Oops[#1]: Cpu 0 $ 0 : 00000000 00000000 00000000 00005200 $ 4 : 000000b0 81a90000 81a9224c 000012ce $ 8 : 00000030 800042c0 00000001 00000000 $12 : 00000003 ffffffff 00000000 745f7375 $16 : 819e5200 802f3260 81a30000 81a2e174 $20 : 81a6e090 802b0000 004085c4 00000002 $24 : 00000000 81a6e000 $28 : 81a86000 81a87e30 7fbef508 81a6e024 Hi : 00000000 Lo : 000000c7 epc : 81a6e030 __this_module+0x3fea0/0x3ff00 [iptable_filter] Not tainted ra : 81a6e024 __this_module+0x3fe94/0x3ff00 [iptable_filter] Status: 1000ff04 IEp Cause : 00000008 BadVA : 00000000 PrId : 0000cf01 (rtl) Modules linked in: iptable_filter(+) ip_tables xt_tcpudp x_tables ppp_async ppp_generic slhc crc_ccitt Process insmod (pid: 282, threadinfo=81a86000, task=81a08108, tls=00000000) Stack : 802eac4c 81a2e174 802c0000 802e0000 81a2e174 802c0000 802e0000 801b0b1c 00000034 8001e944 00000001 00000000 81a2e174 802c0000 802e0000 00000000 81a6e090 801b0c94 8025148c 0000002a 0000002a c016c9e8 c016c47c 00000001 81a30000 81a6e0c0 00000310 000002f0 0000001a 00000019 1000ff01 00000001 81a2e190 80008b50 80280000 80250000 81a2e19c 802b0000 004085c4 00000002 ... Call Trace: [<81a6e030>] __this_module+0x3fea0/0x3ff00 [iptable_filter] [<81a6e024>] __this_module+0x3fe94/0x3ff00 [iptable_filter] Code: 10400018 00408021 3c0281a3 <8c43e170> 2645e120 00031827 ae030188 02202021 0c6a478e Disabling lock debugging due to kernel taint sys_init_module 2626, name: iptable_mangle sys_init_module 2636 sys_init_module 2638 }}} From ralf@linux-mips.org Fri Sep 17 17:57:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Sep 2010 17:57:14 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491078Ab0IQP5L (ORCPT ); Fri, 17 Sep 2010 17:57:11 +0200 Date: Fri, 17 Sep 2010 16:57:10 +0100 From: Ralf Baechle To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Subject: Re: Porting Linux MIPS issue: maltaint.h files Message-ID: <20100917155710.GA15030@linux-mips.org> References: <20100916235739.GA16949@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100916235739.GA16949@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27761 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13754 Content-Length: 2917 Lines: 86 On Fri, Sep 17, 2010 at 12:57:39AM +0100, Ralf Baechle wrote: > Post a patch to cleanup the mess. > > In this case (and I haven't looked at it for more than 30s ...) it seems > that the constant X should be moved into after which the > inclusion of the Malta header can go away. So here it is. Ralf arch/mips/include/asm/gic.h | 1 + arch/mips/include/asm/mips-boards/maltaint.h | 3 --- arch/mips/kernel/irq-gic.c | 3 +-- arch/mips/mti-malta/malta-int.c | 3 +++ 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 9b9436a..86548da 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -321,6 +321,7 @@ struct gic_intrmask_regs { */ struct gic_intr_map { unsigned int cpunum; /* Directed to this CPU */ +#define GIC_UNUSED 0xdead /* Dummy data */ unsigned int pin; /* Directed to this Pin */ unsigned int polarity; /* Polarity : +/- */ unsigned int trigtype; /* Trigger : Edge/Levl */ diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index cea872f..d11aa02 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -88,9 +88,6 @@ #define GIC_EXT_INTR(x) x -/* Dummy data */ -#define X 0xdead - /* External Interrupts used for IPI */ #define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index b181f2f..3e57e29 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -222,7 +221,7 @@ static void __init gic_basic_init(int numintrs, int numvpes, /* Setup specifics */ for (i = 0; i < mapsize; i++) { cpu = intrmap[i].cpunum; - if (cpu == X) + if (cpu == GIC_UNUSED) continue; if (cpu == 0 && i != 0 && intrmap[i].flags == 0) continue; diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 15949b0..b79b24a 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -385,6 +385,8 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); */ #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK +#define X GIC_UNUSED + static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { { X, X, X, X, 0 }, { X, X, X, X, 0 }, @@ -404,6 +406,7 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { { X, X, X, X, 0 }, /* The remainder of this table is initialised by fill_ipi_map */ }; +#undef X /* * GCMP needs to be detected before any SMP initialisation From maciej@drobniuch.pl Fri Sep 17 20:53:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Sep 2010 20:53:13 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:46393 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491087Ab0IQSxK (ORCPT ); Fri, 17 Sep 2010 20:53:10 +0200 Received: by bwz19 with SMTP id 19so4111328bwz.36 for ; Fri, 17 Sep 2010 11:53:10 -0700 (PDT) MIME-Version: 1.0 Received: by 10.204.76.205 with SMTP id d13mr4191146bkk.93.1284749590093; Fri, 17 Sep 2010 11:53:10 -0700 (PDT) Received: by 10.204.102.19 with HTTP; Fri, 17 Sep 2010 11:53:10 -0700 (PDT) X-Originating-IP: [77.88.138.58] Date: Fri, 17 Sep 2010 20:53:10 +0200 Message-ID: Subject: mips64-octeon-linux-gnu From: Maciej Drobniuch To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27762 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maciej@drobniuch.pl Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13900 Content-Length: 183 Lines: 9 Hi ALL! I'm new to linux-mips world! I'm looking for a toolchain called mips64-octeon-linux-gnu Does anyone know where i could get one ? BIG THANKS! -- Pozdrawiam! Maciej Drobniuch From ddaney@caviumnetworks.com Fri Sep 17 21:03:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Sep 2010 21:03:13 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14974 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491087Ab0IQTDK (ORCPT ); Fri, 17 Sep 2010 21:03:10 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 17 Sep 2010 12:03:38 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 17 Sep 2010 12:03:07 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 17 Sep 2010 12:03:07 -0700 Message-ID: <4C93BB61.7000004@caviumnetworks.com> Date: Fri, 17 Sep 2010 12:02:57 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Maciej Drobniuch CC: linux-mips@linux-mips.org Subject: Re: mips64-octeon-linux-gnu References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 17 Sep 2010 19:03:07.0031 (UTC) FILETIME=[F679A270:01CB569A] X-archive-position: 27763 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13906 Content-Length: 462 Lines: 18 On 09/17/2010 11:53 AM, Maciej Drobniuch wrote: > Hi ALL! > I'm new to linux-mips world! > I'm looking for a toolchain called mips64-octeon-linux-gnu > Does anyone know where i could get one ? > BIG THANKS! There are several options: 1) It is supplied as part of the Octeon SDK which may be obtained from the vendor. 2) You can build it yourself (How to do this is left as an exercise for the reader). 3) Use mips64-unknown-linux-gnu instead. David Daney From ddaney@caviumnetworks.com Fri Sep 17 22:27:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Sep 2010 22:27:43 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17841 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491087Ab0IQU1k (ORCPT ); Fri, 17 Sep 2010 22:27:40 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 17 Sep 2010 13:28:07 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 17 Sep 2010 13:27:36 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 17 Sep 2010 13:27:35 -0700 Message-ID: <4C93CF37.9030805@caviumnetworks.com> Date: Fri, 17 Sep 2010 13:27:35 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Maciej Drobniuch , linux-mips Subject: Re: mips64-octeon-linux-gnu References: <4C93BB61.7000004@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 17 Sep 2010 20:27:35.0941 (UTC) FILETIME=[C3C7EB50:01CB56A6] X-archive-position: 27764 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13939 Content-Length: 928 Lines: 46 On 09/17/2010 12:06 PM, Maciej Drobniuch wrote: > 2010/9/17 David Daney: >> On 09/17/2010 11:53 AM, Maciej Drobniuch wrote: >>> >>> Hi ALL! >>> I'm new to linux-mips world! >>> I'm looking for a toolchain called mips64-octeon-linux-gnu >>> Does anyone know where i could get one ? >>> BIG THANKS! >> >> There are several options: >> >> 1) It is supplied as part of the Octeon SDK which may be obtained from the >> vendor. >> > It is free to download? No. >> 2) You can build it yourself (How to do this is left as an exercise for the >> reader). >> > If you could give me a link to the manual/doc/how to it, and tell how > to learn about it, it would be great! http://www.google.com/search?q=cross+Linux+from+scratch >> 3) Use mips64-unknown-linux-gnu instead. >> > Where i can find mips64-unknown-linux-gnu? > See #2 > Sorry for my lame questions! > >> David Daney > Thanks David! >> > > > From Andrei.Ardelean@idt.com Fri Sep 17 23:41:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Sep 2010 23:42:01 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:58528 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491816Ab0IQVl5 convert rfc822-to-8bit (ORCPT ); Fri, 17 Sep 2010 23:41:57 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o8HLfmto001742; Fri, 17 Sep 2010 14:41:49 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o8HLfl5L004821; Fri, 17 Sep 2010 14:41:47 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o8HLfkI26619; Fri, 17 Sep 2010 14:41:46 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: Porting Linux MIPS issue: maltaint.h files Date: Fri, 17 Sep 2010 14:41:44 -0700 Message-ID: In-Reply-To: <20100917155710.GA15030@linux-mips.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: Porting Linux MIPS issue: maltaint.h files thread-index: ActWgJDdDFH4JZZCSLeMOWUkH1aRsAAMIb0g References: <20100916235739.GA16949@linux-mips.org> <20100917155710.GA15030@linux-mips.org> From: "Ardelean, Andrei" To: "Ralf Baechle" Cc: X-Scanned-By: MIMEDefang 2.43 X-archive-position: 27765 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 13976 Content-Length: 3166 Lines: 103 Thanks a lot, Andrei -----Original Message----- From: Ralf Baechle [mailto:ralf@linux-mips.org] Sent: Friday, September 17, 2010 11:57 AM To: Ardelean, Andrei Cc: linux-mips@linux-mips.org Subject: Re: Porting Linux MIPS issue: maltaint.h files On Fri, Sep 17, 2010 at 12:57:39AM +0100, Ralf Baechle wrote: > Post a patch to cleanup the mess. > > In this case (and I haven't looked at it for more than 30s ...) it seems > that the constant X should be moved into after which the > inclusion of the Malta header can go away. So here it is. Ralf arch/mips/include/asm/gic.h | 1 + arch/mips/include/asm/mips-boards/maltaint.h | 3 --- arch/mips/kernel/irq-gic.c | 3 +-- arch/mips/mti-malta/malta-int.c | 3 +++ 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 9b9436a..86548da 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -321,6 +321,7 @@ struct gic_intrmask_regs { */ struct gic_intr_map { unsigned int cpunum; /* Directed to this CPU */ +#define GIC_UNUSED 0xdead /* Dummy data */ unsigned int pin; /* Directed to this Pin */ unsigned int polarity; /* Polarity : +/- */ unsigned int trigtype; /* Trigger : Edge/Levl */ diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index cea872f..d11aa02 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -88,9 +88,6 @@ #define GIC_EXT_INTR(x) x -/* Dummy data */ -#define X 0xdead - /* External Interrupts used for IPI */ #define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index b181f2f..3e57e29 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -222,7 +221,7 @@ static void __init gic_basic_init(int numintrs, int numvpes, /* Setup specifics */ for (i = 0; i < mapsize; i++) { cpu = intrmap[i].cpunum; - if (cpu == X) + if (cpu == GIC_UNUSED) continue; if (cpu == 0 && i != 0 && intrmap[i].flags == 0) continue; diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 15949b0..b79b24a 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -385,6 +385,8 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); */ #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK +#define X GIC_UNUSED + static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { { X, X, X, X, 0 }, { X, X, X, X, 0 }, @@ -404,6 +406,7 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { { X, X, X, X, 0 }, /* The remainder of this table is initialised by fill_ipi_map */ }; +#undef X /* * GCMP needs to be detected before any SMP initialisation From ralf@linux-mips.org Sun Sep 19 00:54:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Sep 2010 00:54:51 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491081Ab0IRWys (ORCPT ); Sun, 19 Sep 2010 00:54:48 +0200 Date: Sat, 18 Sep 2010 23:54:47 +0100 From: Ralf Baechle To: Joe Perches Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH 01/25] arch/mips: Use static const char arrays Message-ID: <20100918225447.GA4739@linux-mips.org> References: <8fcec0d2a48e806558e6bc39d5aa98518a97f8c7.1284406638.git.joe@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8fcec0d2a48e806558e6bc39d5aa98518a97f8c7.1284406638.git.joe@perches.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27766 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14621 Content-Length: 832 Lines: 24 On Mon, Sep 13, 2010 at 12:47:39PM -0700, Joe Perches wrote: > diff --git a/arch/mips/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c > index fadd874..e0ac0b2 100644 > --- a/arch/mips/pnx8550/common/reset.c > +++ b/arch/mips/pnx8550/common/reset.c > @@ -27,8 +27,8 @@ > > void pnx8550_machine_restart(char *command) > { > - char head[] = "************* Machine restart *************"; > - char foot[] = "*******************************************"; > + static const char head[] = "************* Machine restart *************"; > + static const char foot[] = "*******************************************"; > > printk("\n\n"); > printk("%s\n", head); NAK. The printks should have been taken out and shot. And while at it line use the space on the other side of the wall for pnx8550_machine_power_off. Ralf From joe@perches.com Sun Sep 19 01:45:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Sep 2010 01:45:14 +0200 (CEST) Received: from mail.perches.com ([173.55.12.10]:2103 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491081Ab0IRXpH (ORCPT ); Sun, 19 Sep 2010 01:45:07 +0200 Received: from [192.168.1.162] (unknown [192.168.1.162]) by mail.perches.com (Postfix) with ESMTP id 8A3FF24368; Sat, 18 Sep 2010 16:44:55 -0700 (PDT) Subject: Re: [PATCH 01/25] arch/mips: Use static const char arrays From: Joe Perches To: Ralf Baechle Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org In-Reply-To: <20100918225447.GA4739@linux-mips.org> References: <8fcec0d2a48e806558e6bc39d5aa98518a97f8c7.1284406638.git.joe@perches.com> <20100918225447.GA4739@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Sat, 18 Sep 2010 16:44:59 -0700 Message-ID: <1284853499.1778.83.camel@Joe-Laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit X-archive-position: 27767 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14632 Content-Length: 1153 Lines: 31 On Sat, 2010-09-18 at 23:54 +0100, Ralf Baechle wrote: > On Mon, Sep 13, 2010 at 12:47:39PM -0700, Joe Perches wrote: > > diff --git a/arch/mips/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c > > index fadd874..e0ac0b2 100644 > > --- a/arch/mips/pnx8550/common/reset.c > > +++ b/arch/mips/pnx8550/common/reset.c > > @@ -27,8 +27,8 @@ > > > > void pnx8550_machine_restart(char *command) > > { > > - char head[] = "************* Machine restart *************"; > > - char foot[] = "*******************************************"; > > + static const char head[] = "************* Machine restart *************"; > > + static const char foot[] = "*******************************************"; > > > > printk("\n\n"); > > printk("%s\n", head); > NAK. > The printks should have been taken out and shot. And while at it line > use the space on the other side of the wall for pnx8550_machine_power_off. Fix them up as you see fit Ralf. I don't have the hardware and was simply moving stuff that should be const into const ro sections. There are a lot of defects in that file, for instance the printks don't use KERN_. cheers, Joe From ralf@linux-mips.org Sun Sep 19 01:59:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 19 Sep 2010 01:59:28 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491081Ab0IRX7V (ORCPT ); Sun, 19 Sep 2010 01:59:21 +0200 Date: Sun, 19 Sep 2010 00:59:20 +0100 From: Ralf Baechle To: Joe Perches , g@linux-mips.org Cc: Jiri Kosina , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 04/11] arch/mips: Remove pr_ uses of KERN_ Message-ID: <20100918235920.GA31231@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27768 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14637 Content-Length: 25 Lines: 3 Thanks, applied. Ralf From ralf@linux-mips.org Mon Sep 20 01:51:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Sep 2010 01:51:52 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491001Ab0ISXvp (ORCPT ); Mon, 20 Sep 2010 01:51:45 +0200 Date: Mon, 20 Sep 2010 00:51:32 +0100 From: Ralf Baechle To: Bernhard Walle Cc: linux-mips@linux-mips.org, ddaney@caviumnetworks.com, akpm@linux-foundation.org, ebiederm@xmission.com, hch@lst.de, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 Message-ID: <20100919235131.GA29977@linux-mips.org> References: <1283501734-6532-1-git-send-email-walle@corscience.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1283501734-6532-1-git-send-email-walle@corscience.de> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27769 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 14968 Content-Length: 460 Lines: 13 On Fri, Sep 03, 2010 at 10:15:34AM +0200, Bernhard Walle wrote: > Commit 31c984a5acabea5d8c7224dc226453022be46f33 introduced a new syscall > getdents64. However, in the syscall table, the new syscall still refers > to the old getdents which doesn't work. > > The problem appeared with a system that uses the eglibc 2.12-r11187 > (that utilizes that new syscall) is very confused. The fix has been > tested with that eglibc version. Thanks Bernhard! Ralf From tom.parkin@gmail.com Mon Sep 20 11:23:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Sep 2010 11:23:47 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:49636 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490967Ab0ITJXo (ORCPT ); Mon, 20 Sep 2010 11:23:44 +0200 Received: by vws11 with SMTP id 11so3612933vws.36 for ; Mon, 20 Sep 2010 02:23:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=cRJWS/HL0te7crIe1ENyLVp3rnXWDE5/Ec0ZzzyYthk=; b=kh4R7iB6SSC7hfh1CTndEUqFHKoOHVqYMVK0Wba/SqhJFfnkjIkiielU8IHA2+Qnru MxschsRMPfbFWZ1ASmCcij9WdMDQFYyyCgtn0JxkPsQRQDdxC8Iaf7Is3ZbUhYnhIeoU J6VmKBuOrkFP91XmSBLz0tNe0B7N8B6v5se/c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=R5pKxchrpJVSyqnxM/LDmMVefLZE79XUR5mSnboVOkh9bDgrMz/wpPtIrkuReZVhGw eBHANQm5U+K2zcnGAytVxCjmkVSrOAAqCzYVKzrN5YvvqV5f2kZYZPdM+Sybrt8HLXCw R2uvfwjjMreFOILCG93fiHoxJnbXfslo4p/w0= MIME-Version: 1.0 Received: by 10.220.157.200 with SMTP id c8mr4474413vcx.160.1284974618020; Mon, 20 Sep 2010 02:23:38 -0700 (PDT) Received: by 10.220.195.3 with HTTP; Mon, 20 Sep 2010 02:23:37 -0700 (PDT) In-Reply-To: References: Date: Mon, 20 Sep 2010 10:23:37 +0100 Message-ID: Subject: Re: mips64-octeon-linux-gnu From: Tom Parkin To: Maciej Drobniuch Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27770 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tom.parkin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 15183 Content-Length: 621 Lines: 20 On 17 September 2010 19:53, Maciej Drobniuch wrote: > Hi ALL! > I'm new to linux-mips world! > I'm looking for a toolchain called mips64-octeon-linux-gnu > Does anyone know where i could get one ? If you go down the route of compiling your own, you may want to take a look at the crosstool-ng project: http://ymorin.is-a-geek.org/projects/crosstool I'm not sure whether mips64-octeon is currently supported, but if it is crosstool-ng could save you a lot of legwork on building the toolchain by hand. Tom -- Tom Parkin www.thhp.org.uk Morality, like art, means drawing a line someplace /Wilde/ From ralf@linux-mips.org Mon Sep 20 14:43:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Sep 2010 14:43:03 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491000Ab0ITMnA (ORCPT ); Mon, 20 Sep 2010 14:43:00 +0200 Date: Mon, 20 Sep 2010 13:42:59 +0100 From: Ralf Baechle To: FUJITA Tomonori Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, anemo@mba.ocn.ne.jp Subject: Re: [PATCH] MIPS: TX49xx: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN Message-ID: <20100920124259.GA11736@linux-mips.org> References: <20100814160128H.fujita.tomonori@lab.ntt.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100814160128H.fujita.tomonori@lab.ntt.co.jp> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27771 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 15266 Content-Length: 25 Lines: 3 Thanks, applied. Ralf From ralf@linux-mips.org Mon Sep 20 15:08:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Sep 2010 15:08:43 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491000Ab0ITNIk (ORCPT ); Mon, 20 Sep 2010 15:08:40 +0200 Date: Mon, 20 Sep 2010 14:08:39 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Hookup fanotify_init, fanotify_mark, and prlimit64 syscalls. Message-ID: <20100920130839.GA15938@linux-mips.org> References: <1282597837-5988-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1282597837-5988-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27772 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 15289 Content-Length: 25 Lines: 3 Thanks, applied. Ralf From pjohn@mvista.com Mon Sep 20 15:20:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Sep 2010 15:20:04 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:60287 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491000Ab0ITNUB (ORCPT ); Mon, 20 Sep 2010 15:20:01 +0200 Received: by pwj3 with SMTP id 3so1642754pwj.36 for ; Mon, 20 Sep 2010 06:19:54 -0700 (PDT) Received: by 10.114.27.2 with SMTP id a2mr10018584waa.25.1284988794449; Mon, 20 Sep 2010 06:19:54 -0700 (PDT) Received: from [10.161.2.200] ([122.181.19.78]) by mx.google.com with ESMTPS id d2sm13506398wam.14.2010.09.20.06.19.52 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 20 Sep 2010 06:19:53 -0700 (PDT) Subject: [PATCH] MIPS: Fix syscall 64 bit number comments From: Philby John Reply-To: pjohn@mvista.com To: linux-mips@linux-mips.org Cc: David Daney Content-Type: text/plain Date: Mon, 20 Sep 2010 18:50:04 +0530 Message-Id: <1284988804.4442.4.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.24.5 (2.24.5-2.fc10) Content-Transfer-Encoding: 7bit X-archive-position: 27773 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pjohn@mvista.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 15296 Content-Length: 822 Lines: 29 >From 4e2dbfb145d898b8f3fa1798e0ec10ac3f34d6c6 Mon Sep 17 00:00:00 2001 From: Philby John Date: Mon, 20 Sep 2010 18:44:48 +0530 Subject: [PATCH] MIPS: Fix syscall 64 bit number comments Signed-off-by: Philby John Cc: David Daney --- arch/mips/kernel/scall64-64.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index a8a6c59..b16db4b 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -416,7 +416,7 @@ sys_call_table: PTR sys_pipe2 PTR sys_inotify_init1 PTR sys_preadv - PTR sys_pwritev /* 5390 */ + PTR sys_pwritev /* 5290 */ PTR sys_rt_tgsigqueueinfo PTR sys_perf_event_open PTR sys_accept4 -- 1.6.3.3.333.g4d53f From ralf@linux-mips.org Mon Sep 20 15:34:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Sep 2010 15:34:39 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491000Ab0ITNef (ORCPT ); Mon, 20 Sep 2010 15:34:35 +0200 Date: Mon, 20 Sep 2010 14:34:35 +0100 From: Ralf Baechle To: FUJITA Tomonori Cc: akpm@linux-foundation.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH -mm 4/8] mips: enable ARCH_DMA_ADDR_T_64BIT with (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT Message-ID: <20100920133434.GB15938@linux-mips.org> References: <20100903094753S.fujita.tomonori@lab.ntt.co.jp> <1283474956-14710-4-git-send-email-fujita.tomonori@lab.ntt.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1283474956-14710-4-git-send-email-fujita.tomonori@lab.ntt.co.jp> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27774 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 15308 Content-Length: 410 Lines: 16 On Fri, Sep 03, 2010 at 09:49:12AM +0900, FUJITA Tomonori wrote: > Signed-off-by: FUJITA Tomonori > Cc: linux-mips@linux-mips.org Looks good: Acked-by: Ralf Baechle As this patch by itself doesn't make any sense in the MIPS tree and would only cry for a janitor to remove it again I suggest you merge this with the rest of the series. Thanks, Ralf From ralf@linux-mips.org Mon Sep 20 15:55:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Sep 2010 15:55:52 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491827Ab0ITNzt (ORCPT ); Mon, 20 Sep 2010 15:55:49 +0200 Date: Mon, 20 Sep 2010 14:55:48 +0100 From: Ralf Baechle To: Philby John Cc: linux-mips@linux-mips.org, David Daney Subject: Re: [PATCH] MIPS: Fix syscall 64 bit number comments Message-ID: <20100920135548.GC15938@linux-mips.org> References: <1284988804.4442.4.camel@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1284988804.4442.4.camel@localhost.localdomain> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27775 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 15317 Content-Length: 204 Lines: 6 On Mon, Sep 20, 2010 at 06:50:04PM +0530, Philby John wrote: You've posted a minute too early - David's latest patch which I applied adds another wrong syscall number comment. I'll fix that up. Ralf From ralf@linux-mips.org Mon Sep 20 17:05:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Sep 2010 17:05:41 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491832Ab0ITPFi (ORCPT ); Mon, 20 Sep 2010 17:05:38 +0200 Date: Mon, 20 Sep 2010 16:05:37 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: [PATCH] MIPS: Alchemy: resolve prom section mismatches Message-ID: <20100920150535.GD15938@linux-mips.org> References: <1282217833-27119-1-git-send-email-manuel.lauss@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1282217833-27119-1-git-send-email-manuel.lauss@googlemail.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27776 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 15368 Content-Length: 26 Lines: 3 Thanks, applied. Ralf From walle@corscience.de Tue Sep 21 09:49:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Sep 2010 09:50:06 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.17.8]:57216 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491002Ab0IUHt7 (ORCPT ); Tue, 21 Sep 2010 09:49:59 +0200 Received: from corscience.de (DSL01.212.114.252.242.ip-pool.NEFkom.net [212.114.252.242]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0LaYSx-1OXOpV0smt-00liE3; Tue, 21 Sep 2010 09:49:50 +0200 Received: from [192.168.102.58] (unknown [192.168.102.58]) by corscience.de (Postfix) with ESMTP id A07CA51FBD; Tue, 21 Sep 2010 09:49:49 +0200 (CEST) Message-ID: <4C98639D.107@corscience.de> Date: Tue, 21 Sep 2010 09:49:49 +0200 From: Bernhard Walle User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.12) Gecko/20100915 Thunderbird/3.0.8 MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: N32: Fix getdents64 syscall for n32 References: <1283501734-6532-1-git-send-email-walle@corscience.de> <20100919235131.GA29977@linux-mips.org> In-Reply-To: <20100919235131.GA29977@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Provags-ID: V02:K0:85h7Ft0wYTX2bqeIzUUE0GJ6ICUJ1tqHNddVuUkkUcJ Pm6D5CEDsF2dwNwq+cjIOQaKKsDYCDYB8Es07iOsbMok1t0ln/ LwGpFmlUG3mqastfqi4t7o8VF7/3cxvRwHb9q464KpHpPS5dUB DuDwdiyxJeujGkTeSJiSB472veXvSz4u+R+auWm9yCBbq51HTu gHU4jZUkw/UbWt4dol2OQ== X-archive-position: 27777 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: walle@corscience.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16113 Content-Length: 603 Lines: 18 Am 20.09.2010 01:51, schrieb Ralf Baechle: > On Fri, Sep 03, 2010 at 10:15:34AM +0200, Bernhard Walle wrote: > >> Commit 31c984a5acabea5d8c7224dc226453022be46f33 introduced a new syscall >> getdents64. However, in the syscall table, the new syscall still refers >> to the old getdents which doesn't work. >> >> The problem appeared with a system that uses the eglibc 2.12-r11187 >> (that utilizes that new syscall) is very confused. The fix has been >> tested with that eglibc version. > > Thanks Bernhard! Wouldn't it make sense to put that fix also in the stable tree (2.6.35.6)? Regards, Bernhard From ralf@linux-mips.org Tue Sep 21 12:11:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Sep 2010 12:11:10 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1490976Ab0IUKLG (ORCPT ); Tue, 21 Sep 2010 12:11:06 +0200 Date: Tue, 21 Sep 2010 11:11:05 +0100 From: Ralf Baechle To: Shmulik Ladkani Cc: wuzhangjin@gmail.com, linux-mips@linux-mips.org, alex@digriz.org.uk, manuel.lauss@googlemail.com, sam@ravnborg.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: Fix vmlinuz to flush the caches after kernel decompression Message-ID: <20100921101105.GA32343@linux-mips.org> References: <4c7e1a3a.c83ddf0a.5918.ffffcf6a@mx.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4c7e1a3a.c83ddf0a.5918.ffffcf6a@mx.google.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27778 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16183 Content-Length: 3336 Lines: 102 On Wed, Sep 01, 2010 at 12:17:43PM +0300, Shmulik Ladkani wrote: > Flush caches after kernel decompression. > > When writing instructions, the D-cache should be written-back, and I-cache > should be invalidated. Correct - but it's also a can of worms which is why I intentionally ignored the issue so far. An I-cache is refilled from L2/L3 (if available) or memory. The large amounts of data written by the CPU during decompression of the kernel virtually guarantee that all code will be written back to L2/L3 or memory and the I-cache has been flushed by firmware before the decompressor was entered. Does this assumption fail for you? The real can of worms is SMP - none of the other processors have been detected etc. At this early stage we just don't know if and how to flush caches of other processors. The only good news is that we know they don't have any not written back kernel code in their D-caches. > The patch implements L1 cache flushing, for r4k style caches - suitable for > all MIPS32 CPUs (and probably for other CPUs too). No - you only compile the code for MIPS32 CPUs and check for MIPS_CONF_M which - at least with this meaning - only exists on MIPS32 and MIPS64 CPUs. > +#define INDEX_BASE CKSEG0 > + > +extern void puts(const char *s); > +extern void puthex(unsigned long long val); > + > +#define cache_op(op, addr) \ > + __asm__ __volatile__( \ > + " .set push \n" \ > + " .set noreorder \n" \ > + " .set mips3 \n" \ > + " cache %1, 0(%0) \n" \ > + " .set pop \n" \ > + : \ > + : "r" (addr), "i" (op)) This duplicates the definition of arch/mips/include/asm/r4kcache.h. Why? > +#define cache_all_index_op(cachesz, linesz, op) do { \ > + unsigned long addr = INDEX_BASE; \ > + for (; addr < INDEX_BASE + (cachesz); addr += (linesz)) \ > + cache_op(op, addr); \ > +} while (0) For consistence in formatting please move the "do {" to the beginning of the next line. > +void cache_flush(void) > +{ > + volatile unsigned long config1; I don't know why you're using volatile here - but it won't work as you intended. Just drop the keyword. > + unsigned long tmp; > + unsigned long line_size; > + unsigned long ways; > + unsigned long sets; > + unsigned long cache_size; Make these int variables. The code here is fine for MIPS64 as well but there is no point in having 64-bit variables and multiplies. > + if (!(read_c0_config() & MIPS_CONF_M)) { > + puts("cache_flush error: Config1 unavailable\n"); > + return; > + } > + config1 = read_c0_config1(); > + > + /* calculate D-cache line-size and cache-size, then writeback */ > + tmp = (config1 >> 10) & 7; > + if (tmp) { > + line_size = 2 << tmp; > + sets = 64 << ((config1 >> 13) & 7); > + ways = 1 + ((config1 >> 7) & 7); > + cache_size = sets * ways * line_size; > + dcache_writeback(cache_size, line_size); > + } > + > + /* calculate I-cache line-size and cache-size, then invalidate */ > + tmp = (config1 >> 19) & 7; > + if (tmp) { > + line_size = 2 << tmp; > + sets = 64 << ((config1 >> 22) & 7); > + ways = 1 + ((config1 >> 16) & 7); > + cache_size = sets * ways * line_size; > + icache_invalidate(cache_size, line_size); > + } Eww... You copied (my ...) old sin from c-r4k.c and use all the magic numbers. Anyway, does this actually fix a bug for you or is it more a theoretical convern? Ralf From arrow.ebd@gmail.com Tue Sep 21 15:04:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Sep 2010 15:05:01 +0200 (CEST) Received: from mail-qy0-f177.google.com ([209.85.216.177]:47627 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491018Ab0IUNE6 (ORCPT ); Tue, 21 Sep 2010 15:04:58 +0200 Received: by qyk34 with SMTP id 34so6282354qyk.15 for ; Tue, 21 Sep 2010 06:04:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:content-type; bh=Su8itA51Pf3e8hBd1vuisyyKzDcRgVB+g+JpyomKSic=; b=PazmJdI/8bNChweBqTc2TZq0IrpKJS8vFDX9KYBt2DyHjsYUN0b+tuAZhe7n/A1E6l 2PqoVd1eCwMbHp3p4/rMylEnRSQiVA89ahElbcC/eAA6uTIR0+FK0FlTyCE6NDBpKArP fIMF1+hwt4+89vx8fFwYb3W5UtMZr5F9zetA8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type; b=Q4eUpFtZADo5IzdiVNtGErTDoW9/Nr9HIv+QAIv6AYEIU4DhfT/JcEt+gDtL0elOiT r6fy16GImkLbkMsdcCQUe1FwkjStgs47g4BZNhplsYcvWTB8ff12aPkpHiRgmsfFmgdz XcYLTFoMNP7JNpcWF2KjO1uBlS/x9VTjsM4ks= MIME-Version: 1.0 Received: by 10.229.232.14 with SMTP id js14mr7254350qcb.103.1285074292564; Tue, 21 Sep 2010 06:04:52 -0700 (PDT) Received: by 10.229.25.139 with HTTP; Tue, 21 Sep 2010 06:04:52 -0700 (PDT) In-Reply-To: References: Date: Tue, 21 Sep 2010 21:04:52 +0800 Message-ID: Subject: Re: [HELP] Oops when insmod iptable_filter From: arrow zhang To: linux-mips@linux-mips.org, OpenWrt Content-Type: text/plain; charset=UTF-8 X-archive-position: 27779 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arrow.ebd@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16255 Content-Length: 1442 Lines: 42 On Fri, Sep 17, 2010 at 8:55 PM, arrow zhang wrote: > Here has a difficult problem for me, would like anyone give some advice > > On a mips r3000 cpu, here has a kernel crash when doing the insmod > iptable_filter, > The phenomenon is same as https://dev.openwrt.org/ticket/6129 > > 1, the FW is at openwrt versoin r23057 > 2, the crash occurs if insmod automatically by preinit > 3, but not has crash if insmod within "failsafe mode" ---- good news: 1, work fine if start "init" without "env, like this: exec $pi_init_cmd 2>&0 2, test patch: {{{ diff --git a/package/base-files/files/lib/preinit/99_10_run_init b/package/base-files/files/lib/preinit/99_10_run_init index fef3a50..7db1e72 100644 --- a/package/base-files/files/lib/preinit/99_10_run_init +++ b/package/base-files/files/lib/preinit/99_10_run_init @@ -6,9 +6,11 @@ run_init() { preinit_echo "- init -" preinit_ip_deconfig if [ "$pi_init_suppress_stderr" = "y" ]; then - exec env - PATH=$pi_init_path $pi_init_env $pi_init_cmd 2>&0 + #exec env - PATH=$pi_init_path $pi_init_env $pi_init_cmd 2>&0 + exec $pi_init_cmd 2>&0 else - exec env - PATH=$pi_init_path $pi_init_env $pi_init_cmd + #exec env - PATH=$pi_init_path $pi_init_env $pi_init_cmd + exec $pi_init_cmd fi } }}}} 3, I do not know why, I think it's a my mips SOC porting issue, but I tried to modify TLB and cache, not find out yet, would like someone have advice From ralf@linux-mips.org Tue Sep 21 15:33:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Sep 2010 15:33:15 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491070Ab0IUNdI (ORCPT ); Tue, 21 Sep 2010 15:33:08 +0200 Date: Tue, 21 Sep 2010 14:33:07 +0100 From: Ralf Baechle To: arrow zhang Cc: linux-mips@linux-mips.org, OpenWrt Subject: Re: [HELP] Oops when insmod iptable_filter Message-ID: <20100921133307.GA3855@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27780 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16271 Content-Length: 4637 Lines: 125 On Fri, Sep 17, 2010 at 08:55:43PM +0800, arrow zhang wrote: > Here has a difficult problem for me, would like anyone give some advice > > On a mips r3000 cpu, here has a kernel crash when doing the insmod > iptable_filter, Are you sure you really have an R3000? That's an very old processor released in 1988. > The phenomenon is same as https://dev.openwrt.org/ticket/6129 > > 1, the FW is at openwrt versoin r23057 > 2, the crash occurs if insmod automatically by preinit > 3, but not has crash if insmod within "failsafe mode" > > 4, the crash address is random in the "iptable_filter_init" progress, > seems the symbol or page address invalidate > and sometime may crash at any other modules, (e.g. > iptable_mangle/raw, but iptable_filter module is crash every time) > > 5, refer from the "crash log" "Cause : 00000008", maybe is a TLB > issue, but I have no idea about the debug direction That could be a fairly generic sympthom for dereferencing a bad pointer. > I have try something as these > * check the irq routine > * double check file arch/mips/mm/c-r3k.c > * double check file arch/mips/mm/tlb-r3k.c > * try to remove the patch : > target/linux/generic/patches-2.6.35/027-mips_module_reloc.patch > * try to remove the patch : > target/linux/generic/patches-2.6.35/028-module_exports.patch > * try to remove the patch : > target/linux/generic/patches-2.6.35/202-mips_mem_functions_performance.patch > but all can not fix this bug > > next is the crash log (some printk added at sys_init_module) > {{{ > device eth0 entered promiscuous mode > br-lan: port 1(eth0) entering forwarding state > br-lan: port 1(eth0) entering forwarding state > sys_init_module 2626, name: crc_ccitt > sys_init_module 2636 > sys_init_module 2641 > sys_init_module 2626, name: slhc > sys_init_module 2636 > sys_init_module 2641 > sys_init_module 2626, name: ppp_generic > sys_init_module 2636 > sys_init_module 2638 > PPP generic driver version 2.4.2 > sys_init_module 2641 > sys_init_module 2626, name: ppp_async > sys_init_module 2636 > sys_init_module 2638 > sys_init_module 2641 > sys_init_module 2626, name: x_tables > sys_init_module 2636 > sys_init_module 2638 > sys_init_module 2641 > sys_init_module 2626, name: xt_tcpudp > sys_init_module 2636 > sys_init_module 2638 > sys_init_module 2641 > sys_init_module 2626, name: ip_tables > sys_init_module 2636 > sys_init_module 2638 > ip_tables: (C) 2000-2006 Netfilter Core Team > sys_init_module 2641 > sys_init_module 2626, name: iptable_filter > sys_init_module 2636 > sys_init_module 2638 > CPU 0 Unable to handle kernel paging request at virtual address > 00000000, epc == 81a6e030, ra == 81a6e024 > Oops[#1]: > Cpu 0 > $ 0 : 00000000 00000000 00000000 00005200 > $ 4 : 000000b0 81a90000 81a9224c 000012ce > $ 8 : 00000030 800042c0 00000001 00000000 > $12 : 00000003 ffffffff 00000000 745f7375 > $16 : 819e5200 802f3260 81a30000 81a2e174 > $20 : 81a6e090 802b0000 004085c4 00000002 > $24 : 00000000 81a6e000 > $28 : 81a86000 81a87e30 7fbef508 81a6e024 > Hi : 00000000 > Lo : 000000c7 > epc : 81a6e030 __this_module+0x3fea0/0x3ff00 [iptable_filter] > Not tainted > ra : 81a6e024 __this_module+0x3fe94/0x3ff00 [iptable_filter] The big difference between your issue and the old issue in openwrt is that your system dies in the kernel itself; the old openwrt case blows up while executing code of the module. So they're probably something different. (I think the openwrt issue was actually something specific to 64-bit kernels.) > Status: 1000ff04 IEp > Cause : 00000008 > BadVA : 00000000 > PrId : 0000cf01 (rtl) > Modules linked in: iptable_filter(+) ip_tables xt_tcpudp x_tables > ppp_async ppp_generic slhc crc_ccitt > Process insmod (pid: 282, threadinfo=81a86000, task=81a08108, tls=00000000) > Stack : 802eac4c 81a2e174 802c0000 802e0000 81a2e174 802c0000 802e0000 801b0b1c > 00000034 8001e944 00000001 00000000 81a2e174 802c0000 802e0000 00000000 > 81a6e090 801b0c94 8025148c 0000002a 0000002a c016c9e8 c016c47c 00000001 > 81a30000 81a6e0c0 00000310 000002f0 0000001a 00000019 1000ff01 00000001 > 81a2e190 80008b50 80280000 80250000 81a2e19c 802b0000 004085c4 00000002 > ... > Call Trace: > [<81a6e030>] __this_module+0x3fea0/0x3ff00 [iptable_filter] > [<81a6e024>] __this_module+0x3fe94/0x3ff00 [iptable_filter] > > > Code: 10400018 00408021 3c0281a3 <8c43e170> 2645e120 00031827 > ae030188 02202021 0c6a478e > Disabling lock debugging due to kernel taint > sys_init_module 2626, name: iptable_mangle > sys_init_module 2636 > sys_init_module 2638 > }}} Ralf From justinmattock@gmail.com Wed Sep 22 03:29:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 03:29:40 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:46989 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491076Ab0IVB3d (ORCPT ); Wed, 22 Sep 2010 03:29:33 +0200 Received: by iwn36 with SMTP id 36so57563iwn.36 for ; Tue, 21 Sep 2010 18:29:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=sXrpddjXKUf3EI6mXmhMaveVKLD4uMLo7XVowWf2r6k=; b=qw6NdTg4AWR4kRYAPZbL/KHVxSo+q8vSydIbCom4hFynMGtZGcpGGPFD4aTuwmhn7h i45N6Y2W80PYj6rNF6178NsSI8t7mAXrDsq+DpEnZAbNsiswl/zNzpLWD8OjboRMS8iP GHfeNCXH6pTANV8y1n9heOAuyP8URU+RrQ5Dc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=x3SJTe5eRF059phDhR/qCWmNjVTCRh8lqFVUtVaN25d03BLknlt/ea92AgwKPdgzR0 hyLZJoPI4FcvJQj/hOBGNVGouDyjt38shs8Qdc7Sqex2aTxHtrgoKvNsU16YFVwh+0Fr 0fmu0LYrINiqEcjO/wD4/8WV/rM4jLj+cECaM= Received: by 10.231.30.76 with SMTP id t12mr12862909ibc.161.1285118969626; Tue, 21 Sep 2010 18:29:29 -0700 (PDT) Received: from localhost.localdomain ([76.91.45.220]) by mx.google.com with ESMTPS id i6sm9807344iba.8.2010.09.21.18.29.24 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 21 Sep 2010 18:29:28 -0700 (PDT) From: "Justin P. Mattock" To: trivial@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-laptop@vger.kernel.org, "Justin P. Mattock" , "Maciej W. Rozycki" , Finn Thain , Randy Dunlap Subject: =?UTF-8?q?=5BPATCH=201/2=20v3=5DUpdate=20broken=20web=20addresses=2E?= Date: Tue, 21 Sep 2010 18:29:16 -0700 Message-Id: <1285118957-24965-1-git-send-email-justinmattock@gmail.com> X-Mailer: git-send-email 1.7.2.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-archive-position: 27781 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: justinmattock@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16850 Content-Length: 41184 Lines: 1086 Below is an update from the original, with changes to the broken web addresses and removal of archive.org and moved to a seperate patch for you guys to decide if you want to use this and/or just leave the old url in and leave it at that.. Please dont apply this to anything just comments and fixes for now, then when the time is right, I can bunch everything all into one big patch. Signed-off-by: Justin P. Mattock Cc: Maciej W. Rozycki Cc: Finn Thain Cc: Randy Dunlap --- arch/arm/Kconfig | 4 ++-- arch/arm/common/icst.c | 2 +- arch/arm/include/asm/hardware/icst.h | 2 +- arch/arm/mach-at91/Kconfig | 6 +++--- arch/arm/mach-omap1/Kconfig | 2 +- arch/arm/mach-pxa/am200epd.c | 2 +- arch/arm/mach-pxa/am300epd.c | 2 +- arch/arm/mach-s3c2440/mach-at2440evb.c | 2 +- arch/arm/mach-sa1100/Kconfig | 6 +++--- arch/arm/mach-sa1100/cpu-sa1100.c | 2 +- arch/arm/mm/Kconfig | 2 +- arch/arm/mm/proc-xscale.S | 2 +- arch/arm/nwfpe/milieu.h | 4 ++-- arch/arm/nwfpe/softfloat-macros | 4 ++-- arch/arm/nwfpe/softfloat-specialize | 4 ++-- arch/arm/nwfpe/softfloat.c | 4 ++-- arch/arm/nwfpe/softfloat.h | 4 ++-- arch/arm/plat-samsung/include/plat/adc.h | 2 +- arch/avr32/Kconfig | 2 +- arch/h8300/Kconfig.cpu | 12 ++++++------ arch/h8300/README | 6 +++--- arch/m32r/Kconfig | 2 +- arch/m68k/mac/macboing.c | 3 ++- arch/m68k/q40/README | 2 +- arch/mips/Kconfig | 12 ++++++++---- arch/mips/math-emu/cp1emu.c | 1 - arch/mips/math-emu/dp_add.c | 1 - arch/mips/math-emu/dp_cmp.c | 1 - arch/mips/math-emu/dp_div.c | 1 - arch/mips/math-emu/dp_fint.c | 1 - arch/mips/math-emu/dp_flong.c | 1 - arch/mips/math-emu/dp_frexp.c | 1 - arch/mips/math-emu/dp_fsp.c | 1 - arch/mips/math-emu/dp_logb.c | 1 - arch/mips/math-emu/dp_modf.c | 1 - arch/mips/math-emu/dp_mul.c | 1 - arch/mips/math-emu/dp_scalb.c | 1 - arch/mips/math-emu/dp_simple.c | 1 - arch/mips/math-emu/dp_sqrt.c | 1 - arch/mips/math-emu/dp_sub.c | 1 - arch/mips/math-emu/dp_tint.c | 1 - arch/mips/math-emu/dp_tlong.c | 1 - arch/mips/math-emu/ieee754.c | 1 - arch/mips/math-emu/ieee754.h | 1 - arch/mips/math-emu/ieee754d.c | 1 - arch/mips/math-emu/ieee754dp.c | 1 - arch/mips/math-emu/ieee754dp.h | 1 - arch/mips/math-emu/ieee754int.h | 1 - arch/mips/math-emu/ieee754m.c | 1 - arch/mips/math-emu/ieee754sp.c | 1 - arch/mips/math-emu/ieee754sp.h | 1 - arch/mips/math-emu/ieee754xcpt.c | 1 - arch/mips/math-emu/sp_add.c | 1 - arch/mips/math-emu/sp_cmp.c | 1 - arch/mips/math-emu/sp_div.c | 1 - arch/mips/math-emu/sp_fdp.c | 1 - arch/mips/math-emu/sp_fint.c | 1 - arch/mips/math-emu/sp_flong.c | 1 - arch/mips/math-emu/sp_frexp.c | 1 - arch/mips/math-emu/sp_logb.c | 1 - arch/mips/math-emu/sp_modf.c | 1 - arch/mips/math-emu/sp_mul.c | 1 - arch/mips/math-emu/sp_scalb.c | 1 - arch/mips/math-emu/sp_simple.c | 1 - arch/mips/math-emu/sp_sqrt.c | 1 - arch/mips/math-emu/sp_sub.c | 1 - arch/mips/math-emu/sp_tint.c | 1 - arch/mips/math-emu/sp_tlong.c | 1 - arch/powerpc/include/asm/hydra.h | 2 +- arch/x86/kernel/apm_32.c | 4 ++-- arch/x86/kernel/microcode_core.c | 2 +- arch/x86/kernel/microcode_intel.c | 2 +- 72 files changed, 55 insertions(+), 93 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 553b7cf..c562c68 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -647,7 +647,7 @@ config ARCH_S3C2410 select HAVE_S3C2410_I2C help Samsung S3C2410X CPU based systems, such as the Simtec Electronics - BAST (), the IPAQ 1940 or + BAST (), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). Note, the S3C2416 and the S3C2450 are so close that they even share @@ -1162,7 +1162,7 @@ config SMP See also , and the SMP-HOWTO available at - . + . If you don't know what to do here, say N. diff --git a/arch/arm/common/icst.c b/arch/arm/common/icst.c index 9a7f09c..2dc6da70 100644 --- a/arch/arm/common/icst.c +++ b/arch/arm/common/icst.c @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * * Support functions for calculating clocks/divisors for the ICST307 - * clock generators. See http://www.icst.com/ for more information + * clock generators. See http://www.idt.com/ for more information * on these devices. * * This is an almost identical implementation to the ICST525 clock generator. diff --git a/arch/arm/include/asm/hardware/icst.h b/arch/arm/include/asm/hardware/icst.h index 10382a3..794220b 100644 --- a/arch/arm/include/asm/hardware/icst.h +++ b/arch/arm/include/asm/hardware/icst.h @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * * Support functions for calculating clocks/divisors for the ICST - * clock generators. See http://www.icst.com/ for more information + * clock generators. See http://www.idt.com/ for more information * on these devices. */ #ifndef ASMARM_HARDWARE_ICST_H diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 939bccd..c0bcfb8 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -105,7 +105,7 @@ config MACH_ONEARM bool "Ajeco 1ARM Single Board Computer" help Select this if you are using Ajeco's 1ARM Single Board Computer. - + config ARCH_AT91RM9200DK bool "Atmel AT91RM9200-DK Development board" @@ -137,7 +137,7 @@ config MACH_CARMEVA bool "Conitec ARM&EVA" help Select this if you are using Conitec's AT91RM9200-MCU-Module. - + config MACH_ATEB9200 bool "Embest ATEB9200" @@ -149,7 +149,7 @@ config MACH_KB9200 bool "KwikByte KB920x" help Select this if you are using KwikByte's KB920x board. - + config MACH_PICOTUX2XX bool "picotux 200" diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 3b02d3b..5f64963 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -128,7 +128,7 @@ config MACH_OMAP_PALMTT help Support for the Palm Tungsten|T PDA. To boot the kernel, you'll need a PalmOS compatible bootloader (Garux); check out - http://www.hackndev.com/palm/tt/ for more information. + http://garux.sourceforge.net/ for more information. Say Y here if you have this PDA model, say N otherwise. config MACH_SX1 diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index 3499fad..0fd6a08 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c @@ -10,7 +10,7 @@ * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven. * * This work was made possible by help and equipment support from E-Ink - * Corporation. http://support.eink.com/community + * Corporation. http://www.support.eink.com/ * * This driver is written to be used with the Metronome display controller. * on the AM200 EPD prototype kit/development kit with an E-Ink 800x600 diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index 993d75e..01aa021 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c @@ -8,7 +8,7 @@ * more details. * * This work was made possible by help and equipment support from E-Ink - * Corporation. http://support.eink.com/community + * Corporation. http://www.support.eink.com/ * * This driver is written to be used with the Broadsheet display controller. * on the AM300 EPD prototype kit/development kit with an E-Ink 800x600 diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index 8472579..67b6ba0 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -5,7 +5,7 @@ * and modifications by SBZ and * Weibing * - * For product information, visit http://www.arm9e.com/ + * For product information, visit http://www.arm.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index fd4c52b..5da8c35 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig @@ -90,8 +90,8 @@ config SA1100_JORNADA720 # FIXME: select CPU_FREQ_SA11x0 help Say Y here if you want to build a kernel for the HP Jornada 720 - handheld computer. See - for details. + handheld computer. See + config SA1100_JORNADA720_SSP bool "HP Jornada 720 Extended SSP driver" @@ -145,7 +145,7 @@ config SA1100_SIMPAD FLASH. The SL4 version got 64 MB RAM and 32 MB FLASH and a PCMCIA-Slot. The version for the Germany Telecom (DTAG) is the same like CL4 in additional it has a PCMCIA-Slot. For more information - visit or . + visit or . config SA1100_SSP tristate "Generic PIO SSP" diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index ef81787..c0a13ef 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c @@ -13,7 +13,7 @@ * This software has been developed while working on the LART * computing board (http://www.lartmaker.nl/), which is * sponsored by the Mobile Multi-media Communications - * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications + * (http://www.mobimedia.org/) and Ubiquitous Communications * (http://www.ubicom.tudelft.nl/) projects. * * The authors can be reached at: diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index a0a2928..c1a68af 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -314,7 +314,7 @@ config CPU_SA110 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and is available at five speeds ranging from 100 MHz to 233 MHz. More information is available at - . + . Say Y if you want support for the SA-110 processor. Otherwise, say N. diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 1407597..25d03fa 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -418,7 +418,7 @@ ENTRY(xscale_cache_fns) * * See erratum #25 of "Intel 80200 Processor Specification Update", * revision January 22, 2003, available at: - * http://www.intel.com/design/iio/specupdt/273415.htm + * http://www.intel.com/design/support/faq/io_processors/iq80310_chipset.htm */ ENTRY(xscale_80200_A0_A1_cache_fns) .long xscale_flush_kern_cache_all diff --git a/arch/arm/nwfpe/milieu.h b/arch/arm/nwfpe/milieu.h index a3892ab..09a4f2d 100644 --- a/arch/arm/nwfpe/milieu.h +++ b/arch/arm/nwfpe/milieu.h @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat-macros b/arch/arm/nwfpe/softfloat-macros index 5a060f9..cf2a617 100644 --- a/arch/arm/nwfpe/softfloat-macros +++ b/arch/arm/nwfpe/softfloat-macros @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat-specialize b/arch/arm/nwfpe/softfloat-specialize index d4a4c8e..679a026 100644 --- a/arch/arm/nwfpe/softfloat-specialize +++ b/arch/arm/nwfpe/softfloat-specialize @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat.c b/arch/arm/nwfpe/softfloat.c index 0f9656e..ffa6b43 100644 --- a/arch/arm/nwfpe/softfloat.c +++ b/arch/arm/nwfpe/softfloat.c @@ -11,8 +11,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h index 13e479c..df4d243 100644 --- a/arch/arm/nwfpe/softfloat.h +++ b/arch/arm/nwfpe/softfloat.h @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h index e8382c7..b258a08 100644 --- a/arch/arm/plat-samsung/include/plat/adc.h +++ b/arch/arm/plat-samsung/include/plat/adc.h @@ -1,7 +1,7 @@ /* arch/arm/plat-samsung/include/plat/adc.h * * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simnte.co.uk/ + * http://armlinux.simtec.co.uk/ * Ben Dooks * * S3C ADC driver information diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index f515727..787dcba 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -145,7 +145,7 @@ config BOARD_HAMMERHEAD will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. - For more information see: http://www.miromico.com/hammerhead + For more information see: http://www.hammerhead.ch/index.php/getting-started.html config BOARD_FAVR_32 bool "Favr-32 LCD-board" diff --git a/arch/h8300/Kconfig.cpu b/arch/h8300/Kconfig.cpu index 6e2ecff..8de966a 100644 --- a/arch/h8300/Kconfig.cpu +++ b/arch/h8300/Kconfig.cpu @@ -17,7 +17,7 @@ config H8300H_AKI3068NET help AKI-H8/3068F / AKI-H8/3069F Flashmicom LAN Board Support More Information. (Japanese Only) - + AE-3068/69 Evaluation Board Support More Information. @@ -28,7 +28,7 @@ config H8300H_H8MAX help H8MAX Evaluation Board Support More Information. (Japanese Only) - + config H8300H_SIM bool "H8/300H Simulator" @@ -36,7 +36,7 @@ config H8300H_SIM help GDB Simulator Support More Information. - arch/h8300/Doc/simulator.txt + config H8S_GENERIC bool "H8S Generic" @@ -49,15 +49,15 @@ config H8S_EDOSK2674 help Renesas EDOSK-2674 Evaluation Board Support More Information. - - + + config H8S_SIM bool "H8S Simulator" help GDB Simulator Support More Information. - arch/h8300/Doc/simulator.txt + endchoice diff --git a/arch/h8300/README b/arch/h8300/README index 2fd6f6d..7dac451 100644 --- a/arch/h8300/README +++ b/arch/h8300/README @@ -14,11 +14,11 @@ H8/300H and H8S Akizuki Denshi Tsusho Ltd. (Japanese Only) 3.H8MAX - see http://ip-sol.jp/h8max/ (Japanese Only) + see http://strawberry-linux.com/h8/h8max.html (Japanese Only) 4.EDOSK2674 - see http://www.eu.renesas.com/products/mpumcu/tool/edk/support/edosk2674.html - http://www.azpower.com/H8-uClinux/ + see http://www.uclinux.org/pub/uClinux/ports/h8/HITACHI-EDOSK2674-HOWTO + http://h8-uclinux.sourceforge.net/ * Toolchain Version gcc-3.1 or higher and patch diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig index 836abbb..3867fd2 100644 --- a/arch/m32r/Kconfig +++ b/arch/m32r/Kconfig @@ -315,7 +315,7 @@ config SMP Management" code will be disabled if you say Y here. See also the SMP-HOWTO available at - . + . If you don't know what to do here, say N. diff --git a/arch/m68k/mac/macboing.c b/arch/m68k/mac/macboing.c index 8f06408..234d9ee 100644 --- a/arch/m68k/mac/macboing.c +++ b/arch/m68k/mac/macboing.c @@ -114,7 +114,8 @@ static void mac_init_asc( void ) * 16-bit I/O functionality. The PowerBook 500 series computers * support 16-bit stereo output, but only mono input." * - * http://til.info.apple.com/techinfo.nsf/artnum/n16405 + * Article number 16405: + * http://support.apple.com/kb/TA32601 * * --David Kilzer */ diff --git a/arch/m68k/q40/README b/arch/m68k/q40/README index 6bdbf48..92806c0 100644 --- a/arch/m68k/q40/README +++ b/arch/m68k/q40/README @@ -3,7 +3,7 @@ Linux for the Q40 You may try http://www.geocities.com/SiliconValley/Bay/2602/ for some up to date information. Booter and other tools will be also -available from this place or ftp.uni-erlangen.de/linux/680x0/q40/ +available from this place or http://www.linux-m68k.org/mail.html and mirrors. Hints to documentation usually refer to the linux source tree in diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ad59dd..4606248 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2175,10 +2175,14 @@ config TC bool "TURBOchannel support" depends on MACH_DECSTATION help - TurboChannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS - processors. Documentation on writing device drivers for TurboChannel - is available at: - . + TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS + processors. TURBOchannel programming specifications are available + at: + + and: + + Linux driver support status is documented at: + #config ACCESSBUS # bool "Access.Bus support" diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 47842b7..ec3faa4 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -3,7 +3,6 @@ * * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. diff --git a/arch/mips/math-emu/dp_add.c b/arch/mips/math-emu/dp_add.c index bcf73bb..b422fca 100644 --- a/arch/mips/math-emu/dp_add.c +++ b/arch/mips/math-emu/dp_add.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_cmp.c b/arch/mips/math-emu/dp_cmp.c index 8ab4f32..0f32486 100644 --- a/arch/mips/math-emu/dp_cmp.c +++ b/arch/mips/math-emu/dp_cmp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_div.c b/arch/mips/math-emu/dp_div.c index 6acedce..a1bce1b 100644 --- a/arch/mips/math-emu/dp_div.c +++ b/arch/mips/math-emu/dp_div.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_fint.c b/arch/mips/math-emu/dp_fint.c index 39a71de1..8857128 100644 --- a/arch/mips/math-emu/dp_fint.c +++ b/arch/mips/math-emu/dp_fint.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_flong.c b/arch/mips/math-emu/dp_flong.c index f08f223..14fc01e 100644 --- a/arch/mips/math-emu/dp_flong.c +++ b/arch/mips/math-emu/dp_flong.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_frexp.c b/arch/mips/math-emu/dp_frexp.c index e650cb1..cb15a5e 100644 --- a/arch/mips/math-emu/dp_frexp.c +++ b/arch/mips/math-emu/dp_frexp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_fsp.c b/arch/mips/math-emu/dp_fsp.c index 494d19a..1dfbd92 100644 --- a/arch/mips/math-emu/dp_fsp.c +++ b/arch/mips/math-emu/dp_fsp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_logb.c b/arch/mips/math-emu/dp_logb.c index 6033886..151127e 100644 --- a/arch/mips/math-emu/dp_logb.c +++ b/arch/mips/math-emu/dp_logb.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_modf.c b/arch/mips/math-emu/dp_modf.c index a8570e5..b01f9cf 100644 --- a/arch/mips/math-emu/dp_modf.c +++ b/arch/mips/math-emu/dp_modf.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c index 48908a8..aa566e7 100644 --- a/arch/mips/math-emu/dp_mul.c +++ b/arch/mips/math-emu/dp_mul.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_scalb.c b/arch/mips/math-emu/dp_scalb.c index b84e633..6f5df43 100644 --- a/arch/mips/math-emu/dp_scalb.c +++ b/arch/mips/math-emu/dp_scalb.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c index b909742..79ce267 100644 --- a/arch/mips/math-emu/dp_simple.c +++ b/arch/mips/math-emu/dp_simple.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c index 032328c..a2a51b8 100644 --- a/arch/mips/math-emu/dp_sqrt.c +++ b/arch/mips/math-emu/dp_sqrt.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_sub.c b/arch/mips/math-emu/dp_sub.c index a2127d6..0de098c 100644 --- a/arch/mips/math-emu/dp_sub.c +++ b/arch/mips/math-emu/dp_sub.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_tint.c b/arch/mips/math-emu/dp_tint.c index 2447862..0ebe859 100644 --- a/arch/mips/math-emu/dp_tint.c +++ b/arch/mips/math-emu/dp_tint.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_tlong.c b/arch/mips/math-emu/dp_tlong.c index 0f07ec2..133ce2b 100644 --- a/arch/mips/math-emu/dp_tlong.c +++ b/arch/mips/math-emu/dp_tlong.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c index cb1b682..30554e1 100644 --- a/arch/mips/math-emu/ieee754.c +++ b/arch/mips/math-emu/ieee754.c @@ -9,7 +9,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h index dd91733..22796e0 100644 --- a/arch/mips/math-emu/ieee754.h +++ b/arch/mips/math-emu/ieee754.h @@ -1,7 +1,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as diff --git a/arch/mips/math-emu/ieee754d.c b/arch/mips/math-emu/ieee754d.c index a032533..9599bdd 100644 --- a/arch/mips/math-emu/ieee754d.c +++ b/arch/mips/math-emu/ieee754d.c @@ -4,7 +4,6 @@ * MIPS floating point support * * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c index 2f22fd7..080b5ca 100644 --- a/arch/mips/math-emu/ieee754dp.c +++ b/arch/mips/math-emu/ieee754dp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754dp.h b/arch/mips/math-emu/ieee754dp.h index 7627865..f139c72 100644 --- a/arch/mips/math-emu/ieee754dp.h +++ b/arch/mips/math-emu/ieee754dp.h @@ -5,7 +5,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h index 1a846c5..2701d95 100644 --- a/arch/mips/math-emu/ieee754int.h +++ b/arch/mips/math-emu/ieee754int.h @@ -5,7 +5,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754m.c b/arch/mips/math-emu/ieee754m.c index d66896c..24190f3 100644 --- a/arch/mips/math-emu/ieee754m.c +++ b/arch/mips/math-emu/ieee754m.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c index a19b721..271d00d 100644 --- a/arch/mips/math-emu/ieee754sp.c +++ b/arch/mips/math-emu/ieee754sp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h index d9e3586..754fd54 100644 --- a/arch/mips/math-emu/ieee754sp.h +++ b/arch/mips/math-emu/ieee754sp.h @@ -5,7 +5,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754xcpt.c b/arch/mips/math-emu/ieee754xcpt.c index e02423a..b99a693 100644 --- a/arch/mips/math-emu/ieee754xcpt.c +++ b/arch/mips/math-emu/ieee754xcpt.c @@ -1,7 +1,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_add.c b/arch/mips/math-emu/sp_add.c index d8c4211..ae1a327 100644 --- a/arch/mips/math-emu/sp_add.c +++ b/arch/mips/math-emu/sp_add.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_cmp.c b/arch/mips/math-emu/sp_cmp.c index d3eff6b..716cf37 100644 --- a/arch/mips/math-emu/sp_cmp.c +++ b/arch/mips/math-emu/sp_cmp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_div.c b/arch/mips/math-emu/sp_div.c index 2b437fc..d774792 100644 --- a/arch/mips/math-emu/sp_div.c +++ b/arch/mips/math-emu/sp_div.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_fdp.c b/arch/mips/math-emu/sp_fdp.c index 4093723..e1515aa 100644 --- a/arch/mips/math-emu/sp_fdp.c +++ b/arch/mips/math-emu/sp_fdp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_fint.c b/arch/mips/math-emu/sp_fint.c index e88e125..9694d6c 100644 --- a/arch/mips/math-emu/sp_fint.c +++ b/arch/mips/math-emu/sp_fint.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_flong.c b/arch/mips/math-emu/sp_flong.c index 26d6919..16a651f 100644 --- a/arch/mips/math-emu/sp_flong.c +++ b/arch/mips/math-emu/sp_flong.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_frexp.c b/arch/mips/math-emu/sp_frexp.c index 359c648..5bc993c 100644 --- a/arch/mips/math-emu/sp_frexp.c +++ b/arch/mips/math-emu/sp_frexp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_logb.c b/arch/mips/math-emu/sp_logb.c index 3c33721..9c14e0c 100644 --- a/arch/mips/math-emu/sp_logb.c +++ b/arch/mips/math-emu/sp_logb.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_modf.c b/arch/mips/math-emu/sp_modf.c index 7656894..25a0fba 100644 --- a/arch/mips/math-emu/sp_modf.c +++ b/arch/mips/math-emu/sp_modf.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c index 3f070f8..c06bb40 100644 --- a/arch/mips/math-emu/sp_mul.c +++ b/arch/mips/math-emu/sp_mul.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_scalb.c b/arch/mips/math-emu/sp_scalb.c index 44ceb87..dd76196 100644 --- a/arch/mips/math-emu/sp_scalb.c +++ b/arch/mips/math-emu/sp_scalb.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c index 2fd53c9..ae4fcfa 100644 --- a/arch/mips/math-emu/sp_simple.c +++ b/arch/mips/math-emu/sp_simple.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_sqrt.c b/arch/mips/math-emu/sp_sqrt.c index 8a934b9..fed2017 100644 --- a/arch/mips/math-emu/sp_sqrt.c +++ b/arch/mips/math-emu/sp_sqrt.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_sub.c b/arch/mips/math-emu/sp_sub.c index dbb802c..886ed5b 100644 --- a/arch/mips/math-emu/sp_sub.c +++ b/arch/mips/math-emu/sp_sub.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_tint.c b/arch/mips/math-emu/sp_tint.c index 352dc3a..0fe9acc 100644 --- a/arch/mips/math-emu/sp_tint.c +++ b/arch/mips/math-emu/sp_tint.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_tlong.c b/arch/mips/math-emu/sp_tlong.c index 92cd9c5..d0ca6e2 100644 --- a/arch/mips/math-emu/sp_tlong.c +++ b/arch/mips/math-emu/sp_tlong.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/powerpc/include/asm/hydra.h b/arch/powerpc/include/asm/hydra.h index 1ad4eed..d529a2c 100644 --- a/arch/powerpc/include/asm/hydra.h +++ b/arch/powerpc/include/asm/hydra.h @@ -10,7 +10,7 @@ * * © Copyright 1995 Apple Computer, Inc. All rights reserved. * - * It's available online from http://chrp.apple.com/MacTech.pdf. + * It's available online from http://www.cpu.lu/~mlan/ftp/MacTech.pdf. * You can obtain paper copies of this book from computer bookstores or by * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San * Francisco, CA 94104. Reference ISBN 1-55860-393-X. diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index 4c9c67b..9fed1cc 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -189,8 +189,8 @@ * Intel Order Number 241704-001. Microsoft Part Number 781-110-X01. * * [This document is available free from Intel by calling 800.628.8686 (fax - * 916.356.6100) or 800.548.4725; or via anonymous ftp from - * ftp://ftp.intel.com/pub/IAL/software_specs/apmv11.doc. It is also + * 916.356.6100) or 800.548.4725; or from + * http://www.microsoft.com/whdc/archive/amp_12.mspx It is also * available from Microsoft by calling 206.882.8080.] * * APM 1.2 Reference: diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index fa6551d..b9c5c54 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -12,7 +12,7 @@ * Software Developer's Manual * Order Number 253668 or free download from: * - * http://developer.intel.com/design/pentium4/manuals/253668.htm + * http://developer.intel.com/Assets/PDF/manual/253668.pdf * * For more information, go to http://www.urbanmyth.org/microcode * diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c index 3561702..dcb65cc 100644 --- a/arch/x86/kernel/microcode_intel.c +++ b/arch/x86/kernel/microcode_intel.c @@ -12,7 +12,7 @@ * Software Developer's Manual * Order Number 253668 or free download from: * - * http://developer.intel.com/design/pentium4/manuals/253668.htm + * http://developer.intel.com/Assets/PDF/manual/253668.pdf * * For more information, go to http://www.urbanmyth.org/microcode * -- 1.7.2.1 From fthain@telegraphics.com.au Wed Sep 22 05:25:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 05:26:01 +0200 (CEST) Received: from www.telegraphics.com.au ([204.15.192.19]:34977 "EHLO mail.telegraphics.com.au" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490946Ab0IVDZ5 (ORCPT ); Wed, 22 Sep 2010 05:25:57 +0200 Received: by mail.telegraphics.com.au (Postfix, from userid 101) id DC13C2AE71; Tue, 21 Sep 2010 23:25:51 -0400 (EDT) Date: Wed, 22 Sep 2010 13:25:46 +1000 (EST) From: Finn Thain To: "Justin P. Mattock" cc: trivial@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-laptop@vger.kernel.org, "Maciej W. Rozycki" , Randy Dunlap Subject: Re: [PATCH 1/2 v3]Update broken web addresses. In-Reply-To: <1285118957-24965-1-git-send-email-justinmattock@gmail.com> Message-ID: References: <1285118957-24965-1-git-send-email-justinmattock@gmail.com> User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-archive-position: 27782 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fthain@telegraphics.com.au Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16888 Content-Length: 1859 Lines: 50 On Tue, 21 Sep 2010, Justin P. Mattock wrote: > Below is an update from the original, with changes to the broken web > addresses and removal of archive.org and moved to a seperate patch for > you guys to decide if you want to use this and/or just leave the old url > in and leave it at that.. > Please dont apply this to anything just comments and fixes for now, You can use [RFC] in the Subject line instead of [PATCH] to indicate this. > diff --git a/arch/m68k/mac/macboing.c b/arch/m68k/mac/macboing.c > index 8f06408..234d9ee 100644 > --- a/arch/m68k/mac/macboing.c > +++ b/arch/m68k/mac/macboing.c > @@ -114,7 +114,8 @@ static void mac_init_asc( void ) > * 16-bit I/O functionality. The PowerBook 500 series computers > * support 16-bit stereo output, but only mono input." > * > - * http://til.info.apple.com/techinfo.nsf/artnum/n16405 > + * Article number 16405: > + * http://support.apple.com/kb/TA32601 > * > * --David Kilzer > */ "TIL article number 16405" would allow people to find the document by number... > diff --git a/arch/m68k/q40/README b/arch/m68k/q40/README > index 6bdbf48..92806c0 100644 > --- a/arch/m68k/q40/README > +++ b/arch/m68k/q40/README > @@ -3,7 +3,7 @@ Linux for the Q40 > > You may try http://www.geocities.com/SiliconValley/Bay/2602/ for > some up to date information. Booter and other tools will be also > -available from this place or ftp.uni-erlangen.de/linux/680x0/q40/ > +available from this place or http://www.linux-m68k.org/mail.html > and mirrors. > > Hints to documentation usually refer to the linux source tree in No. We already discussed this change. Please refer back to my review of the first version of the patch. You got it right in the second version (that I also reviewed), but now you've gone back to the first version... Finn From justinmattock@gmail.com Wed Sep 22 05:57:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 05:57:12 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:34867 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490946Ab0IVD5J (ORCPT ); Wed, 22 Sep 2010 05:57:09 +0200 Received: by pvg12 with SMTP id 12so36280pvg.36 for ; Tue, 21 Sep 2010 20:57:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; bh=DkFtJ5c7VTh35MXUu0BAePY+sOZReMzGm40rVe7kM7c=; b=gZvWGc0A96G9+FMsNNXjtuq4dliDwWKsoV5Gq5BvLRnq5xXHYv3rK+huUy6LN00033 3OavRviVVnkIjMn7d193FfIQUeTR5+kHxoQmzFIbmVEqsGyXEOIa3AgLFiTQ9ao1MHPX g4QTmcDR9gL6H6a+HjFVEJneGLlyjgv2FLtdM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=aq27OSPTaiKf7+LcsRVDpKsmDKj30BkAkoZx3cwUO9nwIkTKyuumcaVMTFBk67RcC3 wbND0mcvN9rQbp6tYEgfxhIZ5luzwnjLvmXY2p4EvKoSyRUNRa7sRVPNVUr+zKG/uNt+ vqQwN5JbzccevyrdSEITWgxwZ1RXyMJKo4mp8= Received: by 10.114.60.3 with SMTP id i3mr13083487waa.88.1285127822374; Tue, 21 Sep 2010 20:57:02 -0700 (PDT) Received: from [10.0.0.98] ([76.91.45.220]) by mx.google.com with ESMTPS id d39sm16754924wam.16.2010.09.21.20.56.59 (version=SSLv3 cipher=RC4-MD5); Tue, 21 Sep 2010 20:57:01 -0700 (PDT) Message-ID: <4C997E94.8070407@gmail.com> Date: Tue, 21 Sep 2010 20:57:08 -0700 From: "Justin P. Mattock" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:2.0b5pre) Gecko/20100827 Thunderbird/3.2a1pre MIME-Version: 1.0 To: Finn Thain CC: trivial@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-laptop@vger.kernel.org, "Maciej W. Rozycki" , Randy Dunlap Subject: Re: [PATCH 1/2 v3]Update broken web addresses. References: <1285118957-24965-1-git-send-email-justinmattock@gmail.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 27783 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: justinmattock@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16894 Content-Length: 2130 Lines: 64 On 09/21/2010 08:25 PM, Finn Thain wrote: > > On Tue, 21 Sep 2010, Justin P. Mattock wrote: > >> Below is an update from the original, with changes to the broken web >> addresses and removal of archive.org and moved to a seperate patch for >> you guys to decide if you want to use this and/or just leave the old url >> in and leave it at that.. >> Please dont apply this to anything just comments and fixes for now, > > You can use [RFC] in the Subject line instead of [PATCH] to indicate this. > alright.. > >> diff --git a/arch/m68k/mac/macboing.c b/arch/m68k/mac/macboing.c >> index 8f06408..234d9ee 100644 >> --- a/arch/m68k/mac/macboing.c >> +++ b/arch/m68k/mac/macboing.c >> @@ -114,7 +114,8 @@ static void mac_init_asc( void ) >> * 16-bit I/O functionality. The PowerBook 500 series computers >> * support 16-bit stereo output, but only mono input." >> * >> - * http://til.info.apple.com/techinfo.nsf/artnum/n16405 >> + * Article number 16405: >> + * http://support.apple.com/kb/TA32601 >> * >> * --David Kilzer >> */ > > "TIL article number 16405" would allow people to find the document by > number... > so putting this "TIL article number 16405" is correct instead of Article number 16405: > >> diff --git a/arch/m68k/q40/README b/arch/m68k/q40/README >> index 6bdbf48..92806c0 100644 >> --- a/arch/m68k/q40/README >> +++ b/arch/m68k/q40/README >> @@ -3,7 +3,7 @@ Linux for the Q40 >> >> You may try http://www.geocities.com/SiliconValley/Bay/2602/ for >> some up to date information. Booter and other tools will be also >> -available from this place or ftp.uni-erlangen.de/linux/680x0/q40/ >> +available from this place or http://www.linux-m68k.org/mail.html >> and mirrors. >> >> Hints to documentation usually refer to the linux source tree in > > No. We already discussed this change. Please refer back to my review of > the first version of the patch. You got it right in the second version > (that I also reviewed), but now you've gone back to the first version... > > Finn > pretty bad.. I don't know what happened there.. Justin P. Mattock From wuzhangjin@gmail.com Wed Sep 22 07:59:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 07:59:31 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:50480 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491110Ab0IVF72 (ORCPT ); Wed, 22 Sep 2010 07:59:28 +0200 Received: by pxi4 with SMTP id 4so56066pxi.36 for ; Tue, 21 Sep 2010 22:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=ssRZFJeCCsp93LN6oHwpYBERanbTUUzmIn8qmqrdT9k=; b=GNTYnrfnL9D3Ep1LK/scxy1vtzNK+2UUVv3bihN+ICOviYoEFWVD/+8OfFj3ieTX9X r9zCR/RhoQ1zBJHwL0opEiQZH285HAnV3x1GIbGZzS/69PEREsMWttJ+ZYvxg9eKUEdH XtteFSaZdvGTu5Ts3wz2w81kk+Cb3BNtYWTA8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=B0sb9qn03o+/3SD3iBrYnEAmfsy+k/pUTetWbM6GjSrxsmPe5zSxUWKCTnpOH7kJaO C73WGu9GGomUwD0eGOk/t/hiXuoLC0FtFV9lIm0UQQ+Kh2kyUAC5vNQde7Ft89Gsmn1y d4AYu5cqzVuFg6ZwaB36BjMbKin+2nKfwpbNY= Received: by 10.142.9.22 with SMTP id 22mr3525279wfi.170.1285135162159; Tue, 21 Sep 2010 22:59:22 -0700 (PDT) Received: from localhost.localdomain ([61.48.59.181]) by mx.google.com with ESMTPS id v3sm9945139wfv.11.2010.09.21.22.59.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 21 Sep 2010 22:59:20 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin Subject: [PATCH] MIPS: Make EARLY_PRINTK selectable for !EMBEDDED Date: Wed, 22 Sep 2010 13:59:10 +0800 Message-Id: <1285135150-14772-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 X-archive-position: 27784 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16940 Content-Length: 928 Lines: 32 From: Wu Zhangjin When EMBEDDED is disabled, the EARLY_PRINTK option will be hiden and we have no way to disable it. For EARLY_PRINTK is not necessary for !EMBEDDED, we should make it selectable and only enable it by default for EMBEDDED. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig.debug | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 43dc279..77eba81 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -7,9 +7,9 @@ config TRACE_IRQFLAGS_SUPPORT source "lib/Kconfig.debug" config EARLY_PRINTK - bool "Early printk" if EMBEDDED + bool "Early printk" depends on SYS_HAS_EARLY_PRINTK - default y + default y if EMBEDDED help This option enables special console drivers which allow the kernel to print messages very early in the bootup process. -- 1.7.1 From wuzhangjin@gmail.com Wed Sep 22 08:03:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 08:03:19 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:64915 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490968Ab0IVGDQ (ORCPT ); Wed, 22 Sep 2010 08:03:16 +0200 Received: by pxi4 with SMTP id 4so56717pxi.36 for ; Tue, 21 Sep 2010 23:03:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=CjnhvHLU/fPFFgpcPcQSVT1GUJFUOjr2xoa/UipirT0=; b=u66inKFnq4jDS5JKzqZUxDInoND05y3y2PQJwItcuxu6/2q9x/1UEXZ2a7eGyukhM3 iWb0TTvG3sz77GEmzA/JRhfIfH24IzjtXCcbM8pqC1NKFVF3T1mW8wGfA5tPxc36Qgsr BtOrDka8ziltuegGtbaKoy8ApavV7MK3VCAdQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=EoOe82vgi7QwFzBmtOzpCYXihCrwBp4vJjoEca2RD+oP+E+74qQzxezYoqfZME3WKu kUXohNbUJOjHZlUDQgpZcLZE+W8QybhUmryP9BSlcYKgx8lfuHgcAUaPdZS3mj7FXwgu y2GpVPUxglMZLbNrmdK3VtyYLqofXT7P7aD6I= Received: by 10.114.112.6 with SMTP id k6mr13121025wac.194.1285135389844; Tue, 21 Sep 2010 23:03:09 -0700 (PDT) Received: from localhost.localdomain ([61.48.59.181]) by mx.google.com with ESMTPS id o17sm16926219wal.21.2010.09.21.23.03.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 21 Sep 2010 23:03:09 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin Subject: [PATCH] MIPS: Loongson: Update lemote2f_defconfig Date: Wed, 22 Sep 2010 14:02:58 +0800 Message-Id: <1285135378-15725-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 X-archive-position: 27785 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16942 Content-Length: 8785 Lines: 355 From: Wu Zhangjin Changes: - Remove the deprecated CONFIG_SYSFS_DEPRECATED_V2=y - Enable KSM for page merging - Replace the deprecated IDE support by libata support - Remove CONFIG_EMBEDDED=y - The other trivial changes Signed-off-by: Wu Zhangjin --- arch/mips/configs/lemote2f_defconfig | 165 +++++++++++++++++++++------------ 1 files changed, 105 insertions(+), 60 deletions(-) diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index f7033f3..5839488 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -2,26 +2,26 @@ CONFIG_MACH_LOONGSON=y CONFIG_LEMOTE_MACH2F=y CONFIG_CS5536_MFGPT=y CONFIG_64BIT=y +CONFIG_KSM=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_KEXEC=y -# CONFIG_SECCOMP is not set CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y CONFIG_AUDIT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y CONFIG_PROFILING=y CONFIG_OPROFILE=m CONFIG_MODULES=y @@ -47,7 +47,6 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_USERSPACE=m CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_LOONGSON2_CPUFREQ=m -CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_XFRM_USER=m @@ -103,22 +102,93 @@ CONFIG_LIB80211_DEBUG=y CONFIG_MAC80211=m CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_IDE_TASK_IOCTL=y -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -CONFIG_BLK_DEV_AMD74XX=y -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_FC_TGT_ATTRS=y +CONFIG_SCSI_SAS_ATA=y +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_SRP_TGT_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +CONFIG_SCSI_AIC7XXX_OLD=m +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_RESET_DELAY_MS=15000 +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_HPTIOP=m +CONFIG_FCOE=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_LPFC=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_SRP=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_DH=m +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_SIL24=m +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_PIIX=m +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +CONFIG_PATA_AMD=y +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_TOSHIBA=m +CONFIG_ATA_GENERIC=m CONFIG_MD=y CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m @@ -129,7 +199,6 @@ CONFIG_MD_RAID456=m CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_BLK_DEV_DM=m -CONFIG_DM_DEBUG=y CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m @@ -140,42 +209,40 @@ CONFIG_DM_MULTIPATH_QL=m CONFIG_DM_MULTIPATH_ST=m CONFIG_DM_DELAY=m CONFIG_DM_UEVENT=y -CONFIG_NETDEVICES=y +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=40 +CONFIG_FUSION_CTL=m CONFIG_DUMMY=m CONFIG_TUN=m CONFIG_VETH=m CONFIG_NET_ETHERNET=y +CONFIG_MII=y CONFIG_NET_PCI=y -CONFIG_8139TOO=y -# CONFIG_8139TOO_PIO is not set -CONFIG_R8169=y +CONFIG_8139TOO=m +CONFIG_R8169=m CONFIG_R8169_VLAN=y -# CONFIG_NETDEV_10000 is not set CONFIG_USB_USBNET=m CONFIG_USB_NET_CDC_EEM=m CONFIG_NETCONSOLE=m CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_INPUT_POLLDEV=m -CONFIG_INPUT_EVDEV=y -# CONFIG_MOUSE_PS2_ALPS is not set -# CONFIG_MOUSE_PS2_LOGIPS2PP is not set -# CONFIG_MOUSE_PS2_TRACKPOINT is not set +CONFIG_INPUT_EVDEV=m +CONFIG_KEYBOARD_ATKBD=m +CONFIG_MOUSE_PS2=m CONFIG_MOUSE_APPLETOUCH=m -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_NONSTANDARD=y CONFIG_SERIAL_8250=m -# CONFIG_SERIAL_8250_PCI is not set CONFIG_SERIAL_8250_NR_UARTS=16 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_FOURPORT=y CONFIG_LEGACY_PTY_COUNT=16 CONFIG_HW_RANDOM=y -CONFIG_RTC=y CONFIG_THERMAL=y CONFIG_MEDIA_SUPPORT=m CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y CONFIG_VIDEO_VIVI=m CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_M5602=m @@ -211,7 +278,6 @@ CONFIG_USB_SN9C102=m CONFIG_USB_ZR364XX=m CONFIG_USB_STKWEBCAM=m CONFIG_USB_S2255=m -# CONFIG_RADIO_ADAPTERS is not set CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y @@ -221,7 +287,6 @@ CONFIG_FB_SIS=y CONFIG_FB_SIS_300=y CONFIG_FB_SIS_315=y CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=m # CONFIG_VGA_CONSOLE is not set @@ -237,9 +302,6 @@ CONFIG_FONT_MINI_4x6=y CONFIG_FONT_SUN8x16=y CONFIG_FONT_SUN12x22=y CONFIG_FONT_10x18=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_SOUND=m CONFIG_SND=m CONFIG_SND_SEQUENCER=m @@ -255,30 +317,17 @@ CONFIG_SND_MPU401=m CONFIG_SND_AC97_POWER_SAVE=y CONFIG_SND_AC97_POWER_SAVE_DEFAULT=10 CONFIG_SND_CS5535AUDIO=m -# CONFIG_SND_MIPS is not set CONFIG_SND_USB_AUDIO=m CONFIG_SND_USB_CAIAQ=m CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_HIDRAW=y CONFIG_USB_HIDDEV=y -CONFIG_HID_A4TECH=m -CONFIG_HID_APPLE=m -CONFIG_HID_BELKIN=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CYPRESS=m CONFIG_HID_DRAGONRISE=m CONFIG_DRAGONRISE_FF=y -CONFIG_HID_EZKEY=m -CONFIG_HID_KYE=m CONFIG_HID_GYRATION=m CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=m -CONFIG_HID_LOGITECH=m CONFIG_LOGITECH_FF=y CONFIG_LOGIRUMBLEPAD2_FF=y -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m CONFIG_HID_NTRIG=m CONFIG_HID_PANTHERLORD=m CONFIG_PANTHERLORD_FF=y @@ -296,17 +345,12 @@ CONFIG_THRUSTMASTER_FF=y CONFIG_HID_WACOM=m CONFIG_HID_ZEROPLUS=m CONFIG_ZEROPLUS_FF=y -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG_WHITELIST=y -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MON=m +CONFIG_USB_EHCI_HCD=m CONFIG_USB_EHCI_ROOT_HUB_TT=y -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD=m CONFIG_USB_UHCI_HCD=m CONFIG_USB_WHCI_HCD=m CONFIG_USB_HWA_HCD=m @@ -330,12 +374,13 @@ CONFIG_USB_GADGET=m CONFIG_USB_GADGET_M66592=y CONFIG_MMC=m CONFIG_LEDS_CLASS=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y CONFIG_STAGING=y # CONFIG_STAGING_EXCLUDE_BUILD is not set CONFIG_FB_SM7XX=y CONFIG_EXT2_FS=m CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y @@ -352,6 +397,8 @@ CONFIG_QUOTA=y CONFIG_QFMT_V2=m CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_FSCACHE=m CONFIG_CACHEFILES=m CONFIG_ISO9660_FS=m @@ -373,6 +420,7 @@ CONFIG_NFS_V3_ACL=y CONFIG_NFSD=m CONFIG_NFSD_V4=y CONFIG_CIFS=m +CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=m @@ -412,11 +460,9 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=y -CONFIG_PRINTK_TIME=y CONFIG_FRAME_WARN=1024 CONFIG_STRIP_ASM_SYMS=y CONFIG_DEBUG_FS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y @@ -458,4 +504,3 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=m -CONFIG_CRC_T10DIF=y -- 1.7.1 From wuzhangjin@gmail.com Wed Sep 22 08:04:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 08:04:17 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:58204 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490968Ab0IVGEO (ORCPT ); Wed, 22 Sep 2010 08:04:14 +0200 Received: by pvg12 with SMTP id 12so57161pvg.36 for ; Tue, 21 Sep 2010 23:04:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=cRwt6c7y6APDIaP7pj6J+GmScdBcYfoTipyQQktwMBI=; b=XmwHlkqeFUppigM89VyXab2Q9x0lTDQXlX4ulILmizWZZTvTkAYtMqUJvCKfgk/Nfi +s2I3UnaJ+3hLcxP4GGgU9XD7QQ6Z/SKxEt4vEyOdYaS7JgUbE1Lo1RYqUNOvjZEAdhv yXwdzoAR1/ABYKx9Y/+1uDLa5knMyXlOR10iI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=Odf9SB1hJOKSdj2yWJHufvvaeu8YNWZfufqSAjOmpVuzAuUmCWL8k/vSTOxY1xguqI iHAF/VUPbpN37fz5NqxPigj3MubByKyta9nVLyYkgujv13WfMhHmFPPxzHuqBEhcpIMQ RUQuL5SdOEI2y3YzrizupP8DW4KqT4IKiBHCw= Received: by 10.142.251.3 with SMTP id y3mr10090375wfh.140.1285135448127; Tue, 21 Sep 2010 23:04:08 -0700 (PDT) Received: from localhost.localdomain ([61.48.59.181]) by mx.google.com with ESMTPS id y36sm9216160wfd.18.2010.09.21.23.04.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 21 Sep 2010 23:04:06 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin Subject: [PATCH] MIPS: Fixes "make clean" Date: Wed, 22 Sep 2010 14:03:57 +0800 Message-Id: <1285135437-15783-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.1 X-archive-position: 27786 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 16943 Content-Length: 712 Lines: 23 From: Wu Zhangjin When we do "make clean", vmlinuz will not be cleaned, we need to use vmlinuz* instead of vmlinuz.* to include it. Signed-off-by: Wu Zhangjin --- arch/mips/boot/compressed/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index ed9bb70..5c1eb68 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -105,4 +105,4 @@ OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec vmlinuz.srec: vmlinuz $(call cmd,objcopy) -clean-files := $(objtree)/vmlinuz.* +clean-files := $(objtree)/vmlinuz* -- 1.7.1 From fujita.tomonori@lab.ntt.co.jp Wed Sep 22 11:19:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 11:19:10 +0200 (CEST) Received: from sh.osrg.net ([192.16.179.4]:57348 "EHLO sh.osrg.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491112Ab0IVJTH (ORCPT ); Wed, 22 Sep 2010 11:19:07 +0200 Received: from localhost (rose.osrg.net [10.76.0.1]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o8M9IQoc012248; Wed, 22 Sep 2010 18:18:27 +0900 Date: Wed, 22 Sep 2010 18:18:26 +0900 To: ralf@linux-mips.org Cc: fujita.tomonori@lab.ntt.co.jp, akpm@linux-foundation.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH -mm 4/8] mips: enable ARCH_DMA_ADDR_T_64BIT with (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT From: FUJITA Tomonori In-Reply-To: <20100920133434.GB15938@linux-mips.org> References: <20100903094753S.fujita.tomonori@lab.ntt.co.jp> <1283474956-14710-4-git-send-email-fujita.tomonori@lab.ntt.co.jp> <20100920133434.GB15938@linux-mips.org> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-Id: <20100922181454N.fujita.tomonori@lab.ntt.co.jp> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Wed, 22 Sep 2010 18:18:27 +0900 (JST) X-Virus-Scanned: clamav-milter 0.96.1 at sh X-Virus-Status: Clean X-archive-position: 27787 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fujita.tomonori@lab.ntt.co.jp Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17051 Content-Length: 544 Lines: 20 On Mon, 20 Sep 2010 14:34:35 +0100 Ralf Baechle wrote: > On Fri, Sep 03, 2010 at 09:49:12AM +0900, FUJITA Tomonori wrote: > > > Signed-off-by: FUJITA Tomonori > > Cc: linux-mips@linux-mips.org > > Looks good: > > Acked-by: Ralf Baechle Thanks, > As this patch by itself doesn't make any sense in the MIPS tree and would > only cry for a janitor to remove it again I suggest you merge this with > the rest of the series. I expect akpm to merge all the patches. From ralf@linux-mips.org Wed Sep 22 12:07:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 12:07:06 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491153Ab0IVKHC (ORCPT ); Wed, 22 Sep 2010 12:07:02 +0200 Date: Wed, 22 Sep 2010 11:07:01 +0100 From: Ralf Baechle To: jiang.adam@gmail.com Cc: dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V2] mips: irq: add stackoverflow detection Message-ID: <20100922100701.GA4710@linux-mips.org> References: <1282901526-28405-1-git-send-email-jiang.adam@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1282901526-28405-1-git-send-email-jiang.adam@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27788 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17080 Content-Length: 1552 Lines: 52 On Fri, Aug 27, 2010 at 06:32:06PM +0900, jiang.adam@gmail.com wrote: > diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > index 43dc279..f437cd1 100644 > --- a/arch/mips/Kconfig.debug > +++ b/arch/mips/Kconfig.debug > @@ -67,6 +67,15 @@ config CMDLINE_OVERRIDE > > Normally, you will choose 'N' here. > > +config DEBUG_STACKOVERFLOW > + bool "Check for stack overflows" > + depends on DEBUG_KERNEL > + help > + This option will cause messages to be printed if free stack space > + drops below a certain limit(2GB on MIPS). The debugging option I better upgrade my meory then. 2GB is a LOTS :) > + provides another way to check stack overflow happened on kernel mode > + stack usually caused by nested interruption. > + > config DEBUG_STACK_USAGE > bool "Enable stack utilization instrumentation" > depends on DEBUG_KERNEL > diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c > index c6345f5..d0b924d 100644 > --- a/arch/mips/kernel/irq.c > +++ b/arch/mips/kernel/irq.c > @@ -151,6 +151,26 @@ void __init init_IRQ(void) > #endif > } > > +#ifdef DEBUG_STACKOVERFLOW > +static inline void check_stack_overflow(void) > +{ > + long sp; Addresses in Linux should always be unsigned long. > + > + __asm__ __volatile__("move %0, $sp" : "=r" (sp)); > + sp = sp & (THREAD_SIZE-1); For THREAD_SIZE - 1 there is the symbol THREAD_MASK. > + /* check for stack overflow: is there less than 2KB free? */ > + if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { Looks good otherwise, will queue. Ralf From ralf@linux-mips.org Wed Sep 22 12:58:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 12:58:56 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491112Ab0IVK6x (ORCPT ); Wed, 22 Sep 2010 12:58:53 +0200 Date: Wed, 22 Sep 2010 11:58:52 +0100 From: Ralf Baechle To: patchwork@lists.ozlabs.org Cc: "Justin P. Mattock" , trivial@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-laptop@vger.kernel.org, "Maciej W. Rozycki" , Finn Thain , Randy Dunlap Subject: Re: [PATCH 1/2 v3]Update broken web addresses. Message-ID: <20100922105852.GC4710@linux-mips.org> References: <1285118957-24965-1-git-send-email-justinmattock@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1285118957-24965-1-git-send-email-justinmattock@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27789 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17120 Content-Length: 876 Lines: 20 On Tue, Sep 21, 2010 at 06:29:16PM -0700, Justin P. Mattock wrote: > Date: Tue, 21 Sep 2010 18:29:16 -0700 > From: "Justin P. Mattock" > To: trivial@kernel.org > Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, > linux-omap@vger.kernel.org, linux-m32r@ml.linux-m32r.org, > linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, > linuxppc-dev@lists.ozlabs.org, linux-laptop@vger.kernel.org, "Justin P. > Mattock" , "Maciej W. Rozycki" > , Finn Thain , Randy > Dunlap > Subject: [PATCH 1/2 v3]Update broken web addresses. > Content-Type: text/plain; charset=UTF-8 Patchwork MIME butchers the subject of this patch, see https://patchwork.linux-mips.org/patch/1587/ https://patchwork.kernel.org/patch/198382/ Ralf From matt@console-pimps.org Wed Sep 22 13:38:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 13:38:46 +0200 (CEST) Received: from arkanian.console-pimps.org ([212.110.184.194]:48235 "EHLO arkanian.console-pimps.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491112Ab0IVLin (ORCPT ); Wed, 22 Sep 2010 13:38:43 +0200 Received: by arkanian.console-pimps.org (Postfix, from userid 1002) id 6848B4432F; Wed, 22 Sep 2010 12:38:40 +0100 (BST) Received: from localhost (87-194-181-196.bethere.co.uk [87.194.181.196]) by arkanian.console-pimps.org (Postfix) with ESMTPSA id 1099B4432D; Wed, 22 Sep 2010 12:38:40 +0100 (BST) Date: Wed, 22 Sep 2010 12:38:39 +0100 From: Matt Fleming To: Deng-Cheng Zhu Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Subject: Re: [PATCH v6 3/7] MIPS: add support for software performance events Message-ID: <20100922113839.GA6392@console-pimps.org> References: <1276058130-25851-1-git-send-email-dengcheng.zhu@gmail.com> <1276058130-25851-4-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276058130-25851-4-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 27790 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matt@console-pimps.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17153 Content-Length: 510 Lines: 15 On Wed, Jun 09, 2010 at 12:35:26PM +0800, Deng-Cheng Zhu wrote: > Software events are required as part of the measurable stuff by the > Linux performance counter subsystem. Here is the list of events added by > this patch: > PERF_COUNT_SW_PAGE_FAULTS > PERF_COUNT_SW_PAGE_FAULTS_MIN > PERF_COUNT_SW_PAGE_FAULTS_MAJ > PERF_COUNT_SW_ALIGNMENT_FAULTS > PERF_COUNT_SW_EMULATION_FAULTS > > Signed-off-by: Deng-Cheng Zhu This looks OK. Reviewed-by: Matt Fleming From matt@console-pimps.org Wed Sep 22 14:27:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 14:27:16 +0200 (CEST) Received: from arkanian.console-pimps.org ([212.110.184.194]:57719 "EHLO arkanian.console-pimps.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491194Ab0IVM1N (ORCPT ); Wed, 22 Sep 2010 14:27:13 +0200 Received: by arkanian.console-pimps.org (Postfix, from userid 1002) id EF10D4432F; Wed, 22 Sep 2010 13:27:12 +0100 (BST) Received: from localhost (87-194-181-196.bethere.co.uk [87.194.181.196]) by arkanian.console-pimps.org (Postfix) with ESMTPSA id 06FFB4432D; Wed, 22 Sep 2010 13:27:11 +0100 (BST) Date: Wed, 22 Sep 2010 13:27:11 +0100 From: Matt Fleming To: Deng-Cheng Zhu Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Subject: Re: [PATCH v6 4/7] MIPS: add support for hardware performance events (skeleton) Message-ID: <20100922122711.GB6392@console-pimps.org> References: <1276058130-25851-1-git-send-email-dengcheng.zhu@gmail.com> <1276058130-25851-5-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276058130-25851-5-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 27791 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matt@console-pimps.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17189 Content-Length: 4772 Lines: 155 On Wed, Jun 09, 2010 at 12:35:27PM +0800, Deng-Cheng Zhu wrote: [...] > +static void mipspmu_event_update(struct perf_event *event, > + struct hw_perf_event *hwc, > + int idx) > +{ > + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); > + unsigned long flags; > + int shift = 64 - TOTAL_BITS; > + s64 prev_raw_count, new_raw_count; > + s64 delta; > + > +again: > + prev_raw_count = atomic64_read(&hwc->prev_count); > + local_irq_save(flags); > + /* Make the counter value be a "real" one. */ > + new_raw_count = mipspmu->read_counter(idx); > + if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) { > + new_raw_count &= VALID_COUNT; > + clear_bit(idx, cpuc->msbs); > + } else > + new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT); > + local_irq_restore(flags); I'm probably just being stupid but I can't figure out what this snippet of code is doing. You're checking to see if the counter has overflowed, and if it has then you just clear the overflow bit? I would have expected you to reset the counter to 0. > + if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, > + new_raw_count) != prev_raw_count) > + goto again; > + > + delta = (new_raw_count << shift) - (prev_raw_count << shift); > + delta >>= shift; > + > + atomic64_add(delta, &event->count); > + atomic64_sub(delta, &hwc->period_left); > + > + return; > +} > + > +static void mipspmu_disable(struct perf_event *event) > +{ > + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); > + struct hw_perf_event *hwc = &event->hw; > + int idx = hwc->idx; > + > + > + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); > + > + /* We are working on a local event. */ > + mipspmu->disable_event(idx); > + > + barrier(); > + > + mipspmu_event_update(event, hwc, idx); > + cpuc->events[idx] = NULL; > + clear_bit(idx, cpuc->used_mask); Shouldn't you also clear the overflow bit in ->msbs here? > + > + perf_event_update_userpage(event); > +} > + > +static void mipspmu_unthrottle(struct perf_event *event) > +{ > + struct hw_perf_event *hwc = &event->hw; > + > + mipspmu->enable_event(hwc, hwc->idx); > +} > + > +static void mipspmu_read(struct perf_event *event) > +{ > + struct hw_perf_event *hwc = &event->hw; > + > + /* Don't read disabled counters! */ > + if (hwc->idx < 0) > + return; > + > + mipspmu_event_update(event, hwc, hwc->idx); > +} > + > +static struct pmu pmu = { > + .enable = mipspmu_enable, > + .disable = mipspmu_disable, > + .unthrottle = mipspmu_unthrottle, > + .read = mipspmu_read, > +}; > + > +static atomic_t active_events = ATOMIC_INIT(0); > +static DEFINE_MUTEX(pmu_reserve_mutex); > +static int mips_pmu_irq = -1; > +static int (*save_perf_irq)(void); > + > +static int mipspmu_get_irq(void) > +{ > + int err; > + > + if (cpu_has_veic) { > + /* > + * Using platform specific interrupt controller defines. > + */ > +#ifdef MSC01E_INT_BASE > + mips_pmu_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; > +#endif > + } else if (cp0_perfcount_irq >= 0) { > + /* > + * Some CPUs have explicitly defined their perfcount irq. > + */ > +#if defined(CONFIG_CPU_RM9000) > + mips_pmu_irq = rm9000_perfcount_irq; > +#elif defined(CONFIG_CPU_LOONGSON2) > + mips_pmu_irq = LOONGSON2_PERFCNT_IRQ; > +#else > + mips_pmu_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; > +#endif > + } Having conditional code like this is a pretty sure sign that you haven't separated support for the various performance hardware properly. Have you had a look at how SH uses a registration interface to register sh_pmus? Ideally all the internals for each type of perfcounter hardware should be in their own file. > + > + if (mips_pmu_irq >= 0) { > + /* Request my own irq handler. */ > + err = request_irq(mips_pmu_irq, mipspmu->handle_irq, > + IRQF_DISABLED | IRQF_NOBALANCING, > + "mips_perf_pmu", NULL); > + if (err) { > + pr_warning("Unable to request IRQ%d for MIPS " > + "performance counters!\n", mips_pmu_irq); > + } > + } else if (cp0_perfcount_irq < 0) { > + /* > + * We are sharing the irq number with the timer interrupt. > + */ > + save_perf_irq = perf_irq; > + perf_irq = mipspmu->handle_shared_irq; > + err = 0; SH also has this problem that it doesn't have any sort of performance counter interrupt and so can't check for overflow. This lack of interrupt really needs to be solved generically in perf as it's a problem that effects quite a few architectures. I suspect that using a hrtimer instead of piggy-backing the timer interrupt would make the core perf guys happier. Writing support for this is on my ever-growing list of things todo. I've already started on some patches for the perf tool so that it's possible to sample counters even though there is no periodic interrupt (but that's a different problem). From matt@console-pimps.org Wed Sep 22 14:32:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 14:32:25 +0200 (CEST) Received: from arkanian.console-pimps.org ([212.110.184.194]:56507 "EHLO arkanian.console-pimps.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491197Ab0IVMcW (ORCPT ); Wed, 22 Sep 2010 14:32:22 +0200 Received: by arkanian.console-pimps.org (Postfix, from userid 1000) id 0B8C04432D; Wed, 22 Sep 2010 13:32:22 +0100 (BST) Date: Wed, 22 Sep 2010 13:32:22 +0100 From: Matt Fleming To: Deng-Cheng Zhu Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Subject: Re: [PATCH v6 7/7] MIPS: define local_xchg from xchg_local to atomic_long_xchg Message-ID: <20100922123221.GA16333@console-pimps.org> References: <1276058130-25851-1-git-send-email-dengcheng.zhu@gmail.com> <1276058130-25851-8-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276058130-25851-8-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) X-archive-position: 27792 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matt@console-pimps.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17192 Content-Length: 575 Lines: 11 On Wed, Jun 09, 2010 at 12:35:30PM +0800, Deng-Cheng Zhu wrote: > Perf-events is now using local_t helper functions internally. There is a > use of local_xchg(). On MIPS, this is defined to xchg_local() which is > missing in asm/system.h. This patch re-defines local_xchg() in asm/local.h > to atomic_long_xchg(). Then Perf-events can pass the build. > > Signed-off-by: Deng-Cheng Zhu Is this a separate issue from the rest of this patch series? In any event, it's probably worth moving this earlier in the patch series so as not to break bisect. From jk@ozlabs.org Wed Sep 22 15:06:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 15:06:54 +0200 (CEST) Received: from ozlabs.org ([203.10.76.45]:51355 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491200Ab0IVNGu (ORCPT ); Wed, 22 Sep 2010 15:06:50 +0200 Received: from [192.168.0.126] (ppp121-45-251-169.lns20.per2.internode.on.net [121.45.251.169]) (using SSLv3 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPSA id C7576B70DA; Wed, 22 Sep 2010 23:06:46 +1000 (EST) Subject: Re: [PATCH 1/2 v3]Update broken web addresses. From: Jeremy Kerr To: Ralf Baechle Cc: patchwork@lists.ozlabs.org, linux-mips@linux-mips.org, Randy Dunlap , linux-m32r@ml.linux-m32r.org, trivial@kernel.org, "Maciej W. Rozycki" , linux-laptop@vger.kernel.org, linux-kernel@vger.kernel.org, Finn Thain , linux-m68k@lists.linux-m68k.org, "Justin P. Mattock" , linux-omap@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org In-Reply-To: <20100922105852.GC4710@linux-mips.org> References: <1285118957-24965-1-git-send-email-justinmattock@gmail.com> <20100922105852.GC4710@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Wed, 22 Sep 2010 21:06:45 +0800 Message-ID: <1285160805.2796.0.camel@pororo> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Content-Transfer-Encoding: 7bit X-archive-position: 27793 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jk@ozlabs.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17202 Content-Length: 1020 Lines: 30 Hi Ralf, > On Tue, Sep 21, 2010 at 06:29:16PM -0700, Justin P. Mattock wrote: > > Date: Tue, 21 Sep 2010 18:29:16 -0700 > > From: "Justin P. Mattock" > > To: trivial@kernel.org > > Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, > > linux-omap@vger.kernel.org, linux-m32r@ml.linux-m32r.org, > > linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, > > linuxppc-dev@lists.ozlabs.org, linux-laptop@vger.kernel.org, "Justin P. > > Mattock" , "Maciej W. Rozycki" > > , Finn Thain , Randy > > Dunlap > > Subject: [PATCH 1/2 v3]Update broken web addresses. > > Content-Type: text/plain; charset=UTF-8 > > Patchwork MIME butchers the subject of this patch, see > > https://patchwork.linux-mips.org/patch/1587/ > https://patchwork.kernel.org/patch/198382/ > Thanks for the heads-up - I'll see what's happening with the header decoding here. Cheers, Jeremy From ddaney@caviumnetworks.com Wed Sep 22 18:44:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 18:44:58 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1146 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491112Ab0IVQoy (ORCPT ); Wed, 22 Sep 2010 18:44:54 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 22 Sep 2010 09:45:24 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 22 Sep 2010 09:44:51 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 22 Sep 2010 09:44:51 -0700 Message-ID: <4C9A327E.6030109@caviumnetworks.com> Date: Wed, 22 Sep 2010 09:44:46 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: wuzhangjin@gmail.com CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: Make EARLY_PRINTK selectable for !EMBEDDED References: <1285135150-14772-1-git-send-email-wuzhangjin@gmail.com> In-Reply-To: <1285135150-14772-1-git-send-email-wuzhangjin@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 22 Sep 2010 16:44:51.0697 (UTC) FILETIME=[7A22DE10:01CB5A75] X-archive-position: 27794 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17361 Content-Length: 1327 Lines: 42 On 09/21/2010 10:59 PM, wuzhangjin@gmail.com wrote: > From: Wu Zhangjin > > When EMBEDDED is disabled, the EARLY_PRINTK option will be hiden and we > have no way to disable it. > > For EARLY_PRINTK is not necessary for !EMBEDDED, we should make it > selectable and only enable it by default for EMBEDDED. > > Signed-off-by: Wu Zhangjin > --- > arch/mips/Kconfig.debug | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > index 43dc279..77eba81 100644 > --- a/arch/mips/Kconfig.debug > +++ b/arch/mips/Kconfig.debug > @@ -7,9 +7,9 @@ config TRACE_IRQFLAGS_SUPPORT > source "lib/Kconfig.debug" > > config EARLY_PRINTK > - bool "Early printk" if EMBEDDED > + bool "Early printk" > depends on SYS_HAS_EARLY_PRINTK > - default y > + default y if EMBEDDED I hate to be a pedant, but how about if we don't make it depend on EMBEDDED at all? I.E. just: 'default y' If the system has SYS_HAS_EARLY_PRINTK, the overhead of enabling EARLY_PRINTK is low, although it may slow down booting. But it is really not at all related to EMBEDDED. David Daney > help > This option enables special console drivers which allow the kernel > to print messages very early in the bootup process. From geert@linux-m68k.org Wed Sep 22 19:16:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 19:16:26 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:51934 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491078Ab0IVRQX convert rfc822-to-8bit (ORCPT ); Wed, 22 Sep 2010 19:16:23 +0200 Received: by fxm4 with SMTP id 4so624383fxm.36 for ; Wed, 22 Sep 2010 10:16:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type:content-transfer-encoding; bh=MYfrTL9Mf0jqxdZ7TY0xlBnTA6Jy5fUNbUi4mBFZauI=; b=dy8XXLppDJID3QtkFjv406Osy+1IwNtKQ3AR93dW7UX4BWqtU/scEmACPBFW8gZ4tv /SoNPTBGVb1+JQFz80BSUKlOxOux5g6V42JiNHszHXeZbzBzm19QEwQkuOJX9aiCnvlt pVWlOxOO+Lu5Sd+o3c24gmA99MS503IgVkQ/c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=aPx7F2INxMQ5uuUMVUVvJl9r8/BmtGg6CxEGAb8XUrokRVZonQgBlLBulv3rcrLjgy Utnam0889TkKaqjfCQpPxMBW2e9wLToenaycZdi/e/wJbDD12+8G29EZstzMj85tmQ4i 3e3dhXrJnRIQ1HnGGRWinjAsU6nAR7UatBqXA= MIME-Version: 1.0 Received: by 10.223.107.20 with SMTP id z20mr650322fao.37.1285175777323; Wed, 22 Sep 2010 10:16:17 -0700 (PDT) Received: by 10.223.126.141 with HTTP; Wed, 22 Sep 2010 10:16:17 -0700 (PDT) In-Reply-To: <4C9A327E.6030109@caviumnetworks.com> References: <1285135150-14772-1-git-send-email-wuzhangjin@gmail.com> <4C9A327E.6030109@caviumnetworks.com> Date: Wed, 22 Sep 2010 19:16:17 +0200 X-Google-Sender-Auth: 5JohCMEFDUdlVxmQ5u29lVf-DYk Message-ID: Subject: Re: [PATCH] MIPS: Make EARLY_PRINTK selectable for !EMBEDDED From: Geert Uytterhoeven To: David Daney Cc: wuzhangjin@gmail.com, linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 27795 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17386 Content-Length: 1831 Lines: 52 On Wed, Sep 22, 2010 at 18:44, David Daney wrote: > On 09/21/2010 10:59 PM, wuzhangjin@gmail.com wrote: >> >> From: Wu Zhangjin >> >> When EMBEDDED is disabled, the EARLY_PRINTK option will be hiden and we >> have no way to disable it. >> >> For EARLY_PRINTK is not necessary for !EMBEDDED, we should make it >> selectable and only enable it by default for EMBEDDED. >> >> Signed-off-by: Wu Zhangjin >> --- >>  arch/mips/Kconfig.debug |    4 ++-- >>  1 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug >> index 43dc279..77eba81 100644 >> --- a/arch/mips/Kconfig.debug >> +++ b/arch/mips/Kconfig.debug >> @@ -7,9 +7,9 @@ config TRACE_IRQFLAGS_SUPPORT >>  source "lib/Kconfig.debug" >> >>  config EARLY_PRINTK >> -       bool "Early printk" if EMBEDDED >> +       bool "Early printk" >>        depends on SYS_HAS_EARLY_PRINTK >> -       default y >> +       default y if EMBEDDED > > I hate to be a pedant, but how about if we don't make it depend on EMBEDDED > at all?  I.E. just: 'default y' That's what it was. > If the system has SYS_HAS_EARLY_PRINTK, the overhead of enabling > EARLY_PRINTK is low, although it may slow down booting.  But it is really > not at all related to EMBEDDED. Originally, not the _value_ of EARLY_PRINTK depended on EMBEDDED, but the option to _change_ the value. Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds From Andrei.Ardelean@idt.com Wed Sep 22 20:49:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Sep 2010 20:49:42 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:34984 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491199Ab0IVStj convert rfc822-to-8bit (ORCPT ); Wed, 22 Sep 2010 20:49:39 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o8MInVWI003714 for ; Wed, 22 Sep 2010 11:49:31 -0700 Received: from corpml3.corp.idt.com (corpml3.corp.idt.com [157.165.140.25]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o8MInSea016459 for ; Wed, 22 Sep 2010 11:49:30 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml3.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o8MInQk10343 for ; Wed, 22 Sep 2010 11:49:27 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Which Linux driver (source code) is used for tty0 (console) on MALTA? Date: Wed, 22 Sep 2010 11:49:25 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: Which Linux driver (source code) is used for tty0 (console) on MALTA? thread-index: ActahuDesXg48CQ3SXaBAu+lo68aZA== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 X-archive-position: 27796 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17445 Content-Length: 564 Lines: 16 Hi, I am using MALTA and my goal is to port MIPS Linux on a new platform. Which driver (source code) is used for tty0 (console)? I see the support for "early console" but I think that this is not the real Linux driver used after boot stage. More general, how to find which code source is used for an embedded driver (part of the Kernel at compiling time) for each h/w resource. MIPS Linux distribution comes with a lot of drivers but I have difficulties to figure out which one is used for MALTA. Is it a files where all those are registered? Thanks, Andrei From Tiejun.Chen@windriver.com Thu Sep 23 03:14:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Sep 2010 03:14:23 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:45961 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491200Ab0IWBOU convert rfc822-to-8bit (ORCPT ); Thu, 23 Sep 2010 03:14:20 +0200 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id o8N1E3pq012793; Wed, 22 Sep 2010 18:14:03 -0700 (PDT) Received: from ism-mail03.corp.ad.wrs.com ([128.224.200.20]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 22 Sep 2010 18:14:03 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 8BIT Subject: RE: Which Linux driver (source code) is used for tty0 (console) on MALTA? Date: Thu, 23 Sep 2010 03:13:57 +0200 Message-ID: <52CF90264091A14888078A031D780F4306C8C0F6@ism-mail03.corp.ad.wrs.com> In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Which Linux driver (source code) is used for tty0 (console) on MALTA? Thread-Index: ActahuDesXg48CQ3SXaBAu+lo68aZAANJwAg References: From: "Chen, Tiejun" To: "Ardelean, Andrei" , X-OriginalArrivalTime: 23 Sep 2010 01:14:03.0020 (UTC) FILETIME=[9C24CCC0:01CB5ABC] X-archive-position: 27797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Tiejun.Chen@windriver.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 17830 Content-Length: 1295 Lines: 44 > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of > Ardelean, Andrei > Sent: Thursday, September 23, 2010 2:49 AM > To: linux-mips@linux-mips.org > Subject: Which Linux driver (source code) is used for tty0 > (console) on MALTA? > > Hi, > > I am using MALTA and my goal is to port MIPS Linux on a new platform. > Which driver (source code) is used for tty0 (console)? I see > the support for "early console" but I think that this is not > the real Linux driver used after boot stage. $ cat arch/mips/configs/malta_defconfig | grep SERIAL # CONFIG_SERIAL_NONSTANDARD is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set Cheers Tiejun > > More general, how to find which code source is used for an > embedded driver (part of the Kernel at compiling time) for > each h/w resource. > MIPS Linux distribution comes with a lot of drivers but I > have difficulties to figure out which one is used for MALTA. > Is it a files where all those are registered? > > Thanks, > Andrei > > > From mfm@muteddisk.com Thu Sep 23 08:52:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Sep 2010 08:52:04 +0200 (CEST) Received: from qmta10.emeryville.ca.mail.comcast.net ([76.96.30.17]:51049 "EHLO qmta10.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490949Ab0IWGwA (ORCPT ); Thu, 23 Sep 2010 08:52:00 +0200 Received: from omta07.emeryville.ca.mail.comcast.net ([76.96.30.59]) by qmta10.emeryville.ca.mail.comcast.net with comcast id A6k01f0041GXsucAA6rscU; Thu, 23 Sep 2010 06:51:52 +0000 Received: from haskell.muteddisk.com ([98.239.78.58]) by omta07.emeryville.ca.mail.comcast.net with comcast id A6rr1f00A1FUwZe8U6rrUD; Thu, 23 Sep 2010 06:51:52 +0000 Received: by haskell.muteddisk.com (Postfix, from userid 1000) id A39AE412AC; Wed, 22 Sep 2010 23:51:03 -0700 (PDT) From: matt mooney To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH 10/20] mips: change to new flag variable Date: Wed, 22 Sep 2010 23:51:01 -0700 Message-Id: <1285224661-29797-1-git-send-email-mfm@muteddisk.com> X-Mailer: git-send-email 1.6.4.2 X-archive-position: 27798 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mfm@muteddisk.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18017 Content-Length: 3940 Lines: 115 Replace EXTRA_CFLAGS with ccflags-y. Signed-off-by: matt mooney --- arch/mips/Makefile | 4 ++-- arch/mips/bcm63xx/boards/Makefile | 2 +- arch/mips/fw/arc/Makefile | 2 +- arch/mips/jz4740/Makefile | 2 +- arch/mips/oprofile/Makefile | 2 +- arch/mips/pmc-sierra/yosemite/Makefile | 2 +- arch/mips/powertv/Makefile | 2 +- arch/mips/powertv/asic/Makefile | 2 +- arch/mips/powertv/pci/Makefile | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index f4a4b66..c14c392 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -288,11 +288,11 @@ CLEAN_FILES += vmlinux.32 vmlinux.64 archprepare: ifdef CONFIG_MIPS32_N32 @echo ' Checking missing-syscalls for N32' - $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=n32" + $(Q)$(MAKE) $(build)=. missing-syscalls ccflags-y="-mabi=n32" endif ifdef CONFIG_MIPS32_O32 @echo ' Checking missing-syscalls for O32' - $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32" + $(Q)$(MAKE) $(build)=. missing-syscalls ccflags-y="-mabi=32" endif install: diff --git a/arch/mips/bcm63xx/boards/Makefile b/arch/mips/bcm63xx/boards/Makefile index e5cc86d..9f64fb4 100644 --- a/arch/mips/bcm63xx/boards/Makefile +++ b/arch/mips/bcm63xx/boards/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/mips/fw/arc/Makefile b/arch/mips/fw/arc/Makefile index e0aaad4..5314b37 100644 --- a/arch/mips/fw/arc/Makefile +++ b/arch/mips/fw/arc/Makefile @@ -9,4 +9,4 @@ lib-$(CONFIG_ARC_MEMORY) += memory.o lib-$(CONFIG_ARC_CONSOLE) += arc_con.o lib-$(CONFIG_ARC_PROMLIB) += promlib.o -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile index a604eae..a9dff33 100644 --- a/arch/mips/jz4740/Makefile +++ b/arch/mips/jz4740/Makefile @@ -17,4 +17,4 @@ obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o obj-$(CONFIG_PM) += pm.o -EXTRA_CFLAGS += -Werror -Wall +ccflags-y := -Werror -Wall diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 02cc65e..4b9d704 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -1,4 +1,4 @@ -EXTRA_CFLAGS := -Werror +ccflags-y := -Werror obj-$(CONFIG_OPROFILE) += oprofile.o diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile index b16f95c..02f5fb9 100644 --- a/arch/mips/pmc-sierra/yosemite/Makefile +++ b/arch/mips/pmc-sierra/yosemite/Makefile @@ -6,4 +6,4 @@ obj-y += irq.o prom.o py-console.o setup.o obj-$(CONFIG_SMP) += smp.o -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile index baf6e90..348d2e8 100644 --- a/arch/mips/powertv/Makefile +++ b/arch/mips/powertv/Makefile @@ -28,4 +28,4 @@ obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \ obj-$(CONFIG_USB) += powertv-usb.o -EXTRA_CFLAGS += -Wall +ccflags-y := -Wall diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile index f0e95dc..d810a33 100644 --- a/arch/mips/powertv/asic/Makefile +++ b/arch/mips/powertv/asic/Makefile @@ -20,4 +20,4 @@ obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \ asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \ prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o -EXTRA_CFLAGS += -Wall -Werror +ccflags-y := -Wall -Werror diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile index f5c6246..5783201 100644 --- a/arch/mips/powertv/pci/Makefile +++ b/arch/mips/powertv/pci/Makefile @@ -18,4 +18,4 @@ obj-$(CONFIG_PCI) += fixup-powertv.o -EXTRA_CFLAGS += -Wall -Werror +ccflags-y := -Wall -Werror -- 1.7.2.1 From dengcheng.zhu@gmail.com Thu Sep 23 09:39:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Sep 2010 09:40:01 +0200 (CEST) Received: from mail-qy0-f170.google.com ([209.85.216.170]:35516 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491044Ab0IWHj6 (ORCPT ); Thu, 23 Sep 2010 09:39:58 +0200 Received: by qyk35 with SMTP id 35so7426356qyk.15 for ; Thu, 23 Sep 2010 00:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=nES+7llkeG8pq8652Pa6DRmziB5bSY4s5wVMNlH5TAI=; b=RY7YOt1TNcRqSLuYdqGMc07tlH9JQ+0Gt7JQtcQEWIIKxWUNqUP3UWQWODRN40TUYI d4UaCBtoOE8nsRmip4Rg0kJZWyDRX1FUsjGAUQKYUxVUgN6kgiNip/q4TYjsW5wQZZfd zsDielN2tvICQ0hC3PWYKhdopjlIcOiYx8hlw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=wby6/0Ihak9tIkxCKsgUdUo1WQqVlDryLyVRGLlQgbFLO5Bfip26C4CbZeq+/P5e43 YrgM915tIOuOfqZ4HBkfyiMucCycNWFOGFPCB0489EoSs0NEPWFhNyDyDn5NXRCY47V3 osLBzqxpNJeUSs/DRdphrzOs43gyHYBeTkT0s= MIME-Version: 1.0 Received: by 10.229.215.76 with SMTP id hd12mr1019630qcb.44.1285227591572; Thu, 23 Sep 2010 00:39:51 -0700 (PDT) Received: by 10.229.25.208 with HTTP; Thu, 23 Sep 2010 00:39:51 -0700 (PDT) In-Reply-To: <20100922122711.GB6392@console-pimps.org> References: <1276058130-25851-1-git-send-email-dengcheng.zhu@gmail.com> <1276058130-25851-5-git-send-email-dengcheng.zhu@gmail.com> <20100922122711.GB6392@console-pimps.org> Date: Thu, 23 Sep 2010 15:39:51 +0800 Message-ID: Subject: Re: [PATCH v6 4/7] MIPS: add support for hardware performance events (skeleton) From: Deng-Cheng Zhu To: Matt Fleming Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27799 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18048 Content-Length: 2133 Lines: 42 2010/9/22 Matt Fleming : > I'm probably just being stupid but I can't figure out what this snippet > of code is doing. You're checking to see if the counter has overflowed, > and if it has then you just clear the overflow bit? I would have > expected you to reset the counter to 0. [DC]: Maybe my original code comment for the member msbs of the struct cpu_hw_events is too simple. And here is more: Unlike the perf counters in some other architectures, a 32bit MIPS perf counter, for example, will generate an interrupt after 0x7fffffff. But we want the operation to look like: 0x0 -> 0xffffffff -> interrupt. So there's a "pseudo" signal halfway. Please also note that the counter value will be brought back to 0 soon after it reaches 0x80000000 *each time*. > Shouldn't you also clear the overflow bit in ->msbs here? [DC]: See my comment above. > Having conditional code like this is a pretty sure sign that you haven't > separated support for the various performance hardware properly. Have > you had a look at how SH uses a registration interface to register > sh_pmus? Ideally all the internals for each type of perfcounter > hardware should be in their own file. [DC]: It does look ugly. It should be easy to put conditional code into perf_event_[mipsxx|loongson2|rm9000].c. I'll post a patch to fix it when the whole thing is accepted. > SH also has this problem that it doesn't have any sort of performance > counter interrupt and so can't check for overflow. This lack of > interrupt really needs to be solved generically in perf as it's a > problem that effects quite a few architectures. I suspect that using a > hrtimer instead of piggy-backing the timer interrupt would make the core > perf guys happier. Writing support for this is on my ever-growing list > of things todo. I've already started on some patches for the perf tool > so that it's possible to sample counters even though there is no > periodic interrupt (but that's a different problem). [DC]: Please add me into your post list when your patches are ready :-) Finally, thanks for your time to review the code. Deng-Cheng From dengcheng.zhu@gmail.com Thu Sep 23 09:56:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Sep 2010 09:56:43 +0200 (CEST) Received: from mail-qy0-f177.google.com ([209.85.216.177]:57848 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491044Ab0IWH4k (ORCPT ); Thu, 23 Sep 2010 09:56:40 +0200 Received: by qyk34 with SMTP id 34so2182852qyk.15 for ; Thu, 23 Sep 2010 00:56:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=hC7dxC8GWn7nxnUv+8v6jdbc8XjJFOA9KC4BfMFoJ3w=; b=k2R++S1KOWNaiGtqQ2XBr4c92GGf3GH94LekSO+O/POvT1i7JBLO/0Xc2Yk847S43D +i849HjO6MkVp2jYqS0Gg3r6TQ1b3t7lax27bffLRDlbfGb7utk/p5Zr95+je2/Huaj3 HCj9/DtgyGVtQ24VaFkl6T/dTKmRUfNwB9oyg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=XzWqtNyEfJuGPNyMJw+YGbwgrOxLjR+fdgOfQlZ0ouxREnO6D6xMVnYNDWJO1GkE4z Y7wNGDZx37WN5ar8qfCW2e0c2MyjoT39F5TMWH1NaEeQ3J6WZ7xTD2wao6Ol67L4JNFc yN8gCKq7PuKzSFvizOcApxU4q+YuGNQ/5q6EY= MIME-Version: 1.0 Received: by 10.229.236.74 with SMTP id kj10mr999450qcb.221.1285228593837; Thu, 23 Sep 2010 00:56:33 -0700 (PDT) Received: by 10.229.25.208 with HTTP; Thu, 23 Sep 2010 00:56:33 -0700 (PDT) In-Reply-To: <20100922123221.GA16333@console-pimps.org> References: <1276058130-25851-1-git-send-email-dengcheng.zhu@gmail.com> <1276058130-25851-8-git-send-email-dengcheng.zhu@gmail.com> <20100922123221.GA16333@console-pimps.org> Date: Thu, 23 Sep 2010 15:56:33 +0800 Message-ID: Subject: Re: [PATCH v6 7/7] MIPS: define local_xchg from xchg_local to atomic_long_xchg From: Deng-Cheng Zhu To: Matt Fleming Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27800 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18051 Content-Length: 863 Lines: 21 Yes, it's here only to pass the compiling (coz the Perf core had evolved since the v5 of this patchset). Since the file it touches is stand-alone, it can be applied earlier than the rest (like the patch #2). Deng-Cheng 2010/9/22 Matt Fleming : > On Wed, Jun 09, 2010 at 12:35:30PM +0800, Deng-Cheng Zhu wrote: >> Perf-events is now using local_t helper functions internally. There is a >> use of local_xchg(). On MIPS, this is defined to xchg_local() which is >> missing in asm/system.h. This patch re-defines local_xchg() in asm/local.h >> to atomic_long_xchg(). Then Perf-events can pass the build. >> >> Signed-off-by: Deng-Cheng Zhu > > Is this a separate issue from the rest of this patch series? In any > event, it's probably worth moving this earlier in the patch series so > as not to break bisect. > From wuzhangjin@gmail.com Thu Sep 23 16:24:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Sep 2010 16:24:54 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:55589 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491055Ab0IWOYw (ORCPT ); Thu, 23 Sep 2010 16:24:52 +0200 Received: by wyb38 with SMTP id 38so1864668wyb.36 for ; Thu, 23 Sep 2010 07:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=Whd5V5j5K1jkZvAcqpTMezZHYLc6Bhqb0h+2pTTQrSU=; b=Xal/IhmEjydwltkwAISqPh7LuUv/ooGzqYZAOxnLdDbg36wQLdWX8PnpsmwcsQ7C5p iVpsY/zLNRgEMmx3Ca9vDoiXT7ORpnjt5si6BqHzuy/qvz4WKrRgzK1fJPYayMM/1tdI 9YntIDtOi3/mZwRkhsu7BSD/4qJJDX1Jl30Fs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=rHbZRdxzPcuy3hlZqdSoHg1nDixNzWkDUX7FOm0WXWMpFipPUktUia3XiXrOhWzWE7 YVuDW1/3VjnnAo8nS6YwZ2Cy/5dfRV7DA/Vs3tv7MroLpS6m4U+fjFz93WMB2wNzHmHa TlUCF48HV8ixPwHmBq8mV8zhvIR3rPPRpaW04= MIME-Version: 1.0 Received: by 10.216.72.209 with SMTP id t59mr8294597wed.83.1285251884908; Thu, 23 Sep 2010 07:24:44 -0700 (PDT) Received: by 10.216.156.197 with HTTP; Thu, 23 Sep 2010 07:24:44 -0700 (PDT) In-Reply-To: <4C9A327E.6030109@caviumnetworks.com> References: <1285135150-14772-1-git-send-email-wuzhangjin@gmail.com> <4C9A327E.6030109@caviumnetworks.com> Date: Thu, 23 Sep 2010 22:24:44 +0800 Message-ID: Subject: Re: [PATCH] MIPS: Make EARLY_PRINTK selectable for !EMBEDDED From: wu zhangjin To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27801 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18332 Content-Length: 1550 Lines: 51 On 9/23/10, David Daney wrote: > On 09/21/2010 10:59 PM, wuzhangjin@gmail.com wrote: >> From: Wu Zhangjin >> >> When EMBEDDED is disabled, the EARLY_PRINTK option will be hiden and we >> have no way to disable it. >> >> For EARLY_PRINTK is not necessary for !EMBEDDED, we should make it >> selectable and only enable it by default for EMBEDDED. >> >> Signed-off-by: Wu Zhangjin >> --- >> arch/mips/Kconfig.debug | 4 ++-- >> 1 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug >> index 43dc279..77eba81 100644 >> --- a/arch/mips/Kconfig.debug >> +++ b/arch/mips/Kconfig.debug >> @@ -7,9 +7,9 @@ config TRACE_IRQFLAGS_SUPPORT >> source "lib/Kconfig.debug" >> >> config EARLY_PRINTK >> - bool "Early printk" if EMBEDDED >> + bool "Early printk" >> depends on SYS_HAS_EARLY_PRINTK >> - default y >> + default y if EMBEDDED > > I hate to be a pedant, but how about if we don't make it depend on > EMBEDDED at all? I.E. just: 'default y' > > If the system has SYS_HAS_EARLY_PRINTK, the overhead of enabling > EARLY_PRINTK is low, although it may slow down booting. But it is > really not at all related to EMBEDDED. Yeah, we should remove this dependency eventually, will send a new revision later. Thanks & Regards, Wu Zhangjin > > David Daney > > >> help >> This option enables special console drivers which allow the kernel >> to print messages very early in the bootup process. > > From wuzhangjin@gmail.com Thu Sep 23 16:40:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Sep 2010 16:40:25 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:42576 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491114Ab0IWOkU (ORCPT ); Thu, 23 Sep 2010 16:40:20 +0200 Received: by wyb38 with SMTP id 38so1884448wyb.36 for ; Thu, 23 Sep 2010 07:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=855Kanb4iLjSnc44fO4lvfNhiK3EGvFz/CuZ96qO40Y=; b=PxOW2yYhZUpq3949IF6BMsL807MnANsTGPmHC0vJFaMn8jqtsPbCbqRC7yrArK3I/Q xJ/mjBR2w6azDoSb3jE2BqOOov4D2LMBD+dem/F6CXSjug188F31fqOC4Swm4WLC8BfK t1+obOUZcRqQ9LBQ4QyexcYys2Msug2+4iQaY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=bZ/IoLZzlWnQFaTlzN5JMWhgozXphUoYLzBW0yOPg+mYIXGGBWF3Lm3gKY9y6FjQYb rpGcuS3MTrhwHAKgd7CUmmAIDXNs71bXOYx8FzGbNqZ7HXHETKQhwCKg8i8zNgBl2KaQ DVleU0VGBDKYk7VeRKldnxsgpsQHbtgqBMjWE= MIME-Version: 1.0 Received: by 10.227.144.206 with SMTP id a14mr1621105wbv.112.1285252815386; Thu, 23 Sep 2010 07:40:15 -0700 (PDT) Received: by 10.216.156.197 with HTTP; Thu, 23 Sep 2010 07:40:15 -0700 (PDT) In-Reply-To: References: <1285135150-14772-1-git-send-email-wuzhangjin@gmail.com> <4C9A327E.6030109@caviumnetworks.com> Date: Thu, 23 Sep 2010 22:40:15 +0800 Message-ID: Subject: Re: [PATCH] MIPS: Make EARLY_PRINTK selectable for !EMBEDDED From: wu zhangjin To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27802 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18337 Content-Length: 2422 Lines: 72 On 9/23/10, wu zhangjin wrote: > On 9/23/10, David Daney wrote: >> On 09/21/2010 10:59 PM, wuzhangjin@gmail.com wrote: >>> From: Wu Zhangjin >>> >>> When EMBEDDED is disabled, the EARLY_PRINTK option will be hiden and we >>> have no way to disable it. >>> >>> For EARLY_PRINTK is not necessary for !EMBEDDED, we should make it >>> selectable and only enable it by default for EMBEDDED. >>> >>> Signed-off-by: Wu Zhangjin >>> --- >>> arch/mips/Kconfig.debug | 4 ++-- >>> 1 files changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug >>> index 43dc279..77eba81 100644 >>> --- a/arch/mips/Kconfig.debug >>> +++ b/arch/mips/Kconfig.debug >>> @@ -7,9 +7,9 @@ config TRACE_IRQFLAGS_SUPPORT >>> source "lib/Kconfig.debug" >>> >>> config EARLY_PRINTK >>> - bool "Early printk" if EMBEDDED >>> + bool "Early printk" >>> depends on SYS_HAS_EARLY_PRINTK >>> - default y >>> + default y if EMBEDDED >> >> I hate to be a pedant, but how about if we don't make it depend on >> EMBEDDED at all? I.E. just: 'default y' >> >> If the system has SYS_HAS_EARLY_PRINTK, the overhead of enabling >> EARLY_PRINTK is low, although it may slow down booting. But it is >> really not at all related to EMBEDDED. > > Yeah, we should remove this dependency eventually, will send a new > revision later. But for !EMBEDDED, most of the boards may don't need this option(although no big influence on the booting, but why not disable it?), if this 'default y' is there, they need to add an extra "# CONFIG_EARLY_PRINTK is not set" in their defconfig, one board one such line in the defconfig, as a result, keep this dependency there may save more lines and avoid adding this extra line to the defconfig ;-) And some embedded devices may only provide the serial port output, I guess, this is the possible reason why it is enabled by default for EMBEDDED before. this is similar to the reason why CONFIG_SERIAL_8250_CONSOLE is always enabled for most of the embedded devices. So, keep this dependency there and no new revision for this patch. Regards, Wu Zhangjin > > Thanks & Regards, > Wu Zhangjin > >> >> David Daney >> >> >>> help >>> This option enables special console drivers which allow the kernel >>> to print messages very early in the bootup process. >> >> > From ddaney@caviumnetworks.com Thu Sep 23 20:23:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Sep 2010 20:23:43 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17273 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491144Ab0IWSXj (ORCPT ); Thu, 23 Sep 2010 20:23:39 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 11:24:08 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 11:23:35 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 11:23:35 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NINXah012866; Thu, 23 Sep 2010 11:23:33 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NINV3g012865; Thu, 23 Sep 2010 11:23:32 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Don't place cu2 notifiers in __cpuinitdata Date: Thu, 23 Sep 2010 11:23:29 -0700 Message-Id: <1285266209-12822-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 X-OriginalArrivalTime: 23 Sep 2010 18:23:35.0651 (UTC) FILETIME=[6F804330:01CB5B4C] X-archive-position: 27803 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18554 Content-Length: 739 Lines: 24 The notifiers may be called at any time, so the notifier_block cannot be in init memory. Signed-off-by: David Daney --- arch/mips/include/asm/cop2.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h index 2cb2f0c..3532e2c 100644 --- a/arch/mips/include/asm/cop2.h +++ b/arch/mips/include/asm/cop2.h @@ -24,7 +24,7 @@ extern int cu2_notifier_call_chain(unsigned long val, void *v); #define cu2_notifier(fn, pri) \ ({ \ - static struct notifier_block fn##_nb __cpuinitdata = { \ + static struct notifier_block fn##_nb = { \ .notifier_call = fn, \ .priority = pri \ }; \ -- 1.7.2.2 From ddaney@caviumnetworks.com Thu Sep 23 20:24:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 23 Sep 2010 20:24:19 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17290 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491144Ab0IWSYQ (ORCPT ); Thu, 23 Sep 2010 20:24:16 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 11:24:47 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 11:24:14 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 11:24:14 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NIOCwr012945; Thu, 23 Sep 2010 11:24:12 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NIOAQP012944; Thu, 23 Sep 2010 11:24:10 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Octeon: Place cnmips_cu2_setup in __init memory. Date: Thu, 23 Sep 2010 11:24:09 -0700 Message-Id: <1285266249-12912-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 X-OriginalArrivalTime: 23 Sep 2010 18:24:14.0385 (UTC) FILETIME=[86969A10:01CB5B4C] X-archive-position: 27804 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18555 Content-Length: 688 Lines: 23 It is an early_initcall, so it should be in __init memory. Signed-off-by: David Daney --- arch/mips/cavium-octeon/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c index c664c8c..a5b4279 100644 --- a/arch/mips/cavium-octeon/cpu.c +++ b/arch/mips/cavium-octeon/cpu.c @@ -41,7 +41,7 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action, return NOTIFY_OK; /* Let default notifier send signals */ } -static int cnmips_cu2_setup(void) +static int __init cnmips_cu2_setup(void) { return cu2_notifier(cnmips_cu2_call, 0); } -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:38:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:38:34 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5471 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491123Ab0IWWib (ORCPT ); Fri, 24 Sep 2010 00:38:31 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:39:01 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:29 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:29 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMcNL9024738; Thu, 23 Sep 2010 15:38:23 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMcIXL024737; Thu, 23 Sep 2010 15:38:18 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH 0/9] MIPS: Use dma-mapping-common.h and use swiotlb for Octeon. Date: Thu, 23 Sep 2010 15:38:07 -0700 Message-Id: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 23 Sep 2010 22:38:29.0221 (UTC) FILETIME=[0B2DD950:01CB5B70] X-archive-position: 27805 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18806 Content-Length: 2356 Lines: 57 The Octeon family of SOCs support physical memory outside of the 32-bit addressing range. To support 32-bit devices, we need to use the swiotlb bounce buffer mechanism. There are several parts to the patch set. 1 - Set the proper dma_masks for the octeon_mgmt platform device so that it continues to function with the rewritten dma mapping code to follow. 2,3,4 - Establish a properly constrained DMA32 zone for Octeon. 5 - Convert MIPS to use dma-mapping-common.h 6,7 - Trivial swiotlb changes. 8 - Get MIPS ready to use swiotlb. 9 - Rewrite Octeon dma mapping code. Since the only non-MIPS parts of this patch set are trivial changes to swiotlb, I would suggest that they could all be merged via Ralf's tree if deemed acceptable. David Daney (9): MIPS: Octeon: Set dma_masks for octeon_mgmt device. MIPS: Allow MAX_DMA32_PFN to be overridden. MIPS: Octeon: Adjust top of DMA32 zone. MIPS: Octeon: Select ZONE_DMA32 MIPS: Convert DMA to use dma-mapping-common.h swiotlb: Declare swiotlb_init_with_default_size() swiotlb: Make bounce buffer bounds non-static. MIPS: Add a platform hook for swiotlb setup. MIPS: Octeon: Rewrite DMA mapping functions. arch/mips/Kconfig | 3 + arch/mips/cavium-octeon/Kconfig | 12 + arch/mips/cavium-octeon/dma-octeon.c | 529 +++++++++----------- arch/mips/cavium-octeon/octeon-platform.c | 5 + arch/mips/include/asm/bootinfo.h | 5 + arch/mips/include/asm/device.h | 15 +- arch/mips/include/asm/dma-mapping.h | 125 ++++-- arch/mips/include/asm/dma.h | 3 + .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 + .../include/asm/mach-cavium-octeon/dma-coherence.h | 19 +- arch/mips/include/asm/octeon/pci-octeon.h | 10 + arch/mips/kernel/setup.c | 5 + arch/mips/mm/dma-default.c | 179 +++---- arch/mips/pci/pci-octeon.c | 60 ++- arch/mips/pci/pcie-octeon.c | 5 + include/linux/swiotlb.h | 7 + lib/swiotlb.c | 62 ++-- 17 files changed, 571 insertions(+), 479 deletions(-) -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:38:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:38:57 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5473 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491144Ab0IWWib (ORCPT ); Fri, 24 Sep 2010 00:38:31 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:39:02 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:29 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:29 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMcOAZ024742; Thu, 23 Sep 2010 15:38:24 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMcOGp024741; Thu, 23 Sep 2010 15:38:24 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH 1/9] MIPS: Octeon: Set dma_masks for octeon_mgmt device. Date: Thu, 23 Sep 2010 15:38:08 -0700 Message-Id: <1285281496-24696-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 23 Sep 2010 22:38:29.0549 (UTC) FILETIME=[0B5FE5D0:01CB5B70] X-archive-position: 27806 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18812 Content-Length: 1001 Lines: 34 This allows follow-on patches to dma mapping functions to work with the octeon mgmt device.. Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-platform.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 62ac30e..c32d40d 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -301,6 +302,10 @@ static int __init octeon_mgmt_device_init(void) ret = -ENOMEM; goto out; } + /* No DMA restrictions */ + pd->dev.coherent_dma_mask = DMA_BIT_MASK(64); + pd->dev.dma_mask = &pd->dev.coherent_dma_mask; + switch (port) { case 0: mgmt_port_resource.start = OCTEON_IRQ_MII0; -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:38:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:39:20 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5474 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491166Ab0IWWic (ORCPT ); Fri, 24 Sep 2010 00:38:32 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:39:03 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:30 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:30 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMcPD9024746; Thu, 23 Sep 2010 15:38:25 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMcPbR024745; Thu, 23 Sep 2010 15:38:25 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH 2/9] MIPS: Allow MAX_DMA32_PFN to be overridden. Date: Thu, 23 Sep 2010 15:38:09 -0700 Message-Id: <1285281496-24696-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 23 Sep 2010 22:38:30.0409 (UTC) FILETIME=[0BE31F90:01CB5B70] X-archive-position: 27807 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18813 Content-Length: 741 Lines: 26 DMA mapping may reduce the usable physical address range usable for 32-bit DMA. Signed-off-by: David Daney --- arch/mips/include/asm/dma.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h index 1353c81..2d47da6 100644 --- a/arch/mips/include/asm/dma.h +++ b/arch/mips/include/asm/dma.h @@ -91,7 +91,10 @@ #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) #endif #define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS)) + +#ifndef MAX_DMA32_PFN #define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT)) +#endif /* 8237 DMA controllers */ #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:38:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:39:43 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5477 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491167Ab0IWWid (ORCPT ); Fri, 24 Sep 2010 00:38:33 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:39:04 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:31 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:31 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMcQ56024750; Thu, 23 Sep 2010 15:38:26 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMcPfM024749; Thu, 23 Sep 2010 15:38:25 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH 3/9] MIPS: Octeon: Adjust top of DMA32 zone. Date: Thu, 23 Sep 2010 15:38:10 -0700 Message-Id: <1285281496-24696-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 23 Sep 2010 22:38:31.0706 (UTC) FILETIME=[0CA907A0:01CB5B70] X-archive-position: 27808 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18814 Content-Length: 952 Lines: 27 On OCTEON, we reserve the last 256MB of 32-bit PCI address space, mapping the RAM in this region at a high DMA address. This makes memory in this region unavailable for 32-bit DMA. Signed-off-by: David Daney --- .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index b952fc7..c84ed74 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -81,4 +81,10 @@ static inline int octeon_has_saa(void) return id >= 0x000d0300; } +/* + * The last 256MB are reserved for device to device mappings and the + * BAR1 hole. + */ +#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT) + #endif -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:38:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:40:07 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5479 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491168Ab0IWWie (ORCPT ); Fri, 24 Sep 2010 00:38:34 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:39:05 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:33 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:32 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMcRwY024754; Thu, 23 Sep 2010 15:38:27 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMcRhZ024753; Thu, 23 Sep 2010 15:38:27 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH 4/9] MIPS: Octeon: Select ZONE_DMA32 Date: Thu, 23 Sep 2010 15:38:11 -0700 Message-Id: <1285281496-24696-5-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 23 Sep 2010 22:38:32.0971 (UTC) FILETIME=[0D6A0DB0:01CB5B70] X-archive-position: 27809 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18818 Content-Length: 652 Lines: 23 Give us a nice place to allocate coherent DMA memory for 32-bit devices. Signed-off-by: David Daney --- arch/mips/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5526faa..6c33709 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -693,6 +693,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD select SWAP_IO_SPACE select HW_HAS_PCI select ARCH_SUPPORTS_MSI + select ZONE_DMA32 help This option supports all of the Octeon reference boards from Cavium Networks. It builds a kernel that dynamically determines the Octeon -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:38:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:40:33 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5481 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491169Ab0IWWif (ORCPT ); Fri, 24 Sep 2010 00:38:35 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:39:05 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:33 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:33 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMcSSQ024758; Thu, 23 Sep 2010 15:38:28 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMcSD0024757; Thu, 23 Sep 2010 15:38:28 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH 5/9] MIPS: Convert DMA to use dma-mapping-common.h Date: Thu, 23 Sep 2010 15:38:12 -0700 Message-Id: <1285281496-24696-6-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 23 Sep 2010 22:38:33.0096 (UTC) FILETIME=[0D7D2080:01CB5B70] X-archive-position: 27810 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18821 Content-Length: 16525 Lines: 512 Use asm-generic/dma-mapping-common.h to handle all DMA mapping operations and establish a default get_dma_ops() that forwards all operations to the existing code. Augment dev_archdata to carry a pointer to the struct dma_map_ops, allowing DMA operations to be overridden on a per device basis. Currently this is never filled in, so the default dma_map_ops are used. A follow-on patch sets this for Octeon PCI devices. Also initialize the dma_debug system as it is now used if it is configured. Signed-off-by: David Daney --- arch/mips/Kconfig | 2 + arch/mips/include/asm/device.h | 15 +++- arch/mips/include/asm/dma-mapping.h | 125 +++++++++++++++++-------- arch/mips/mm/dma-default.c | 179 +++++++++++++--------------------- 4 files changed, 172 insertions(+), 149 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6c33709..e68b89f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -14,6 +14,8 @@ config MIPS select HAVE_KRETPROBES select RTC_LIB if !MACH_LOONGSON select GENERIC_ATOMIC64 if !64BIT + select HAVE_DMA_ATTRS + select HAVE_DMA_API_DEBUG mainmenu "Linux/MIPS Kernel Configuration" diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h index 06746c5..65bf274 100644 --- a/arch/mips/include/asm/device.h +++ b/arch/mips/include/asm/device.h @@ -3,4 +3,17 @@ * * This file is released under the GPLv2 */ -#include +#ifndef _ASM_MIPS_DEVICE_H +#define _ASM_MIPS_DEVICE_H + +struct mips_dma_map_ops; + +struct dev_archdata { + /* DMA operations on that device */ + struct mips_dma_map_ops *dma_ops; +}; + +struct pdev_archdata { +}; + +#endif /* _ASM_MIPS_DEVICE_H*/ diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 18fbf7a..9a4c307 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -5,51 +5,67 @@ #include #include -void *dma_alloc_noncoherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag); +struct mips_dma_map_ops { + struct dma_map_ops dma_map_ops; + dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr); + phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr); +}; -void dma_free_noncoherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); +extern struct mips_dma_map_ops *mips_dma_map_ops; -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag); +static inline struct dma_map_ops *get_dma_ops(struct device *dev) +{ + struct mips_dma_map_ops *ops; -void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); + if (dev && dev->archdata.dma_ops) + ops = dev->archdata.dma_ops; + else + ops = mips_dma_map_ops; + + return &ops->dma_map_ops; +} + +static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + struct mips_dma_map_ops *ops = container_of(get_dma_ops(dev), + struct mips_dma_map_ops, + dma_map_ops); + + return ops->phys_to_dma(dev, paddr); +} + +static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + struct mips_dma_map_ops *ops = container_of(get_dma_ops(dev), + struct mips_dma_map_ops, + dma_map_ops); + + return ops->dma_to_phys(dev, daddr); +} + +static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) +{ + if (!dev->dma_mask) + return 0; + + return addr + size <= *dev->dma_mask; +} + +static inline void dma_mark_clean(void *addr, size_t size) {} -extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction); -extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction); -extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction); -extern dma_addr_t dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, enum dma_data_direction direction); - -static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, - size_t size, enum dma_data_direction direction) +#include + +static inline int dma_supported(struct device *dev, u64 mask) { - dma_unmap_single(dev, dma_address, size, direction); + struct dma_map_ops *ops = get_dma_ops(dev); + return ops->dma_supported(dev, mask); } -extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, - int nhwentries, enum dma_data_direction direction); -extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction); -extern void dma_sync_single_for_device(struct device *dev, - dma_addr_t dma_handle, size_t size, enum dma_data_direction direction); -extern void dma_sync_single_range_for_cpu(struct device *dev, - dma_addr_t dma_handle, unsigned long offset, size_t size, - enum dma_data_direction direction); -extern void dma_sync_single_range_for_device(struct device *dev, - dma_addr_t dma_handle, unsigned long offset, size_t size, - enum dma_data_direction direction); -extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, - int nelems, enum dma_data_direction direction); -extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, - int nelems, enum dma_data_direction direction); -extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr); -extern int dma_supported(struct device *dev, u64 mask); +static inline int dma_mapping_error(struct device *dev, u64 mask) +{ + struct dma_map_ops *ops = get_dma_ops(dev); + return ops->mapping_error(dev, mask); +} static inline int dma_set_mask(struct device *dev, u64 mask) @@ -65,4 +81,37 @@ dma_set_mask(struct device *dev, u64 mask) extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction); +static inline void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp) +{ + void *ret; + struct dma_map_ops *ops = get_dma_ops(dev); + + ret = ops->alloc_coherent(dev, size, dma_handle, gfp); + + debug_dma_alloc_coherent(dev, size, *dma_handle, ret); + + return ret; +} + +static inline void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + struct dma_map_ops *ops = get_dma_ops(dev); + + ops->free_coherent(dev, size, vaddr, dma_handle); + + debug_dma_free_coherent(dev, size, vaddr, dma_handle); +} + + +void *dma_alloc_noncoherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag); + +void dma_free_noncoherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle); + +dma_addr_t mips_unity_phys_to_dma(struct device *dev, phys_addr_t paddr); +phys_addr_t mips_unity_dma_to_phys(struct device *dev, dma_addr_t daddr); + #endif /* _ASM_DMA_MAPPING_H */ diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 469d401..4aeae57 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -95,10 +95,9 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size, return ret; } - EXPORT_SYMBOL(dma_alloc_noncoherent); -void *dma_alloc_coherent(struct device *dev, size_t size, +static void *mips_dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t * dma_handle, gfp_t gfp) { void *ret; @@ -123,7 +122,6 @@ void *dma_alloc_coherent(struct device *dev, size_t size, return ret; } -EXPORT_SYMBOL(dma_alloc_coherent); void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) @@ -131,10 +129,9 @@ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); free_pages((unsigned long) vaddr, get_order(size)); } - EXPORT_SYMBOL(dma_free_noncoherent); -void dma_free_coherent(struct device *dev, size_t size, void *vaddr, +static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { unsigned long addr = (unsigned long) vaddr; @@ -151,8 +148,6 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, free_pages(addr, get_order(size)); } -EXPORT_SYMBOL(dma_free_coherent); - static inline void __dma_sync(unsigned long addr, size_t size, enum dma_data_direction direction) { @@ -174,21 +169,8 @@ static inline void __dma_sync(unsigned long addr, size_t size, } } -dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction) -{ - unsigned long addr = (unsigned long) ptr; - - if (!plat_device_is_coherent(dev)) - __dma_sync(addr, size, direction); - - return plat_map_dma_mem(dev, ptr, size); -} - -EXPORT_SYMBOL(dma_map_single); - -void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) +static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, + size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) { if (cpu_is_noncoherent_r10000(dev)) __dma_sync(dma_addr_to_virt(dev, dma_addr), size, @@ -197,15 +179,11 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, plat_unmap_dma_mem(dev, dma_addr, size, direction); } -EXPORT_SYMBOL(dma_unmap_single); - -int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) +static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction direction, struct dma_attrs *attrs) { int i; - BUG_ON(direction == DMA_NONE); - for (i = 0; i < nents; i++, sg++) { unsigned long addr; @@ -219,33 +197,27 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, return nents; } -EXPORT_SYMBOL(dma_map_sg); - -dma_addr_t dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, enum dma_data_direction direction) +static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs) { - BUG_ON(direction == DMA_NONE); + unsigned long addr; - if (!plat_device_is_coherent(dev)) { - unsigned long addr; + addr = (unsigned long) page_address(page) + offset; - addr = (unsigned long) page_address(page) + offset; + if (!plat_device_is_coherent(dev)) __dma_sync(addr, size, direction); - } - return plat_map_dma_mem_page(dev, page) + offset; + return plat_map_dma_mem(dev, (void *)addr, size); } -EXPORT_SYMBOL(dma_map_page); - -void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, - enum dma_data_direction direction) +static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, enum dma_data_direction direction, + struct dma_attrs *attrs) { unsigned long addr; int i; - BUG_ON(direction == DMA_NONE); - for (i = 0; i < nhwentries; i++, sg++) { if (!plat_device_is_coherent(dev) && direction != DMA_TO_DEVICE) { @@ -257,13 +229,9 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, } } -EXPORT_SYMBOL(dma_unmap_sg); - -void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction) +static void mips_dma_sync_single_for_cpu(struct device *dev, + dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - if (cpu_is_noncoherent_r10000(dev)) { unsigned long addr; @@ -272,13 +240,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, } } -EXPORT_SYMBOL(dma_sync_single_for_cpu); - -void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction) +static void mips_dma_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) { unsigned long addr; @@ -288,46 +252,11 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, } } -EXPORT_SYMBOL(dma_sync_single_for_device); - -void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - - if (cpu_is_noncoherent_r10000(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr + offset, size, direction); - } -} - -EXPORT_SYMBOL(dma_sync_single_range_for_cpu); - -void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - - plat_extra_sync_for_device(dev); - if (!plat_device_is_coherent(dev)) { - unsigned long addr; - - addr = dma_addr_to_virt(dev, dma_handle); - __dma_sync(addr + offset, size, direction); - } -} - -EXPORT_SYMBOL(dma_sync_single_range_for_device); - -void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) +static void mips_dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, int nelems, enum dma_data_direction direction) { int i; - BUG_ON(direction == DMA_NONE); - /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) { if (cpu_is_noncoherent_r10000(dev)) @@ -336,15 +265,11 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, } } -EXPORT_SYMBOL(dma_sync_sg_for_cpu); - -void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) +static void mips_dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, int nelems, enum dma_data_direction direction) { int i; - BUG_ON(direction == DMA_NONE); - /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) { if (!plat_device_is_coherent(dev)) @@ -353,24 +278,18 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele } } -EXPORT_SYMBOL(dma_sync_sg_for_device); - -int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { return plat_dma_mapping_error(dev, dma_addr); } -EXPORT_SYMBOL(dma_mapping_error); - -int dma_supported(struct device *dev, u64 mask) +int mips_dma_supported(struct device *dev, u64 mask) { return plat_dma_supported(dev, mask); } -EXPORT_SYMBOL(dma_supported); - -void dma_cache_sync(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction direction) +void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) { BUG_ON(direction == DMA_NONE); @@ -379,4 +298,44 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, __dma_sync((unsigned long)vaddr, size, direction); } -EXPORT_SYMBOL(dma_cache_sync); +dma_addr_t mips_unity_phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + return paddr; +} + +phys_addr_t mips_unity_dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + return daddr; +} + +static struct mips_dma_map_ops mips_default_dma_map_ops = { + .dma_map_ops = { + .alloc_coherent = mips_dma_alloc_coherent, + .free_coherent = mips_dma_free_coherent, + .map_page = mips_dma_map_page, + .unmap_page = mips_dma_unmap_page, + .map_sg = mips_dma_map_sg, + .unmap_sg = mips_dma_unmap_sg, + .sync_single_for_cpu = mips_dma_sync_single_for_cpu, + .sync_single_for_device = mips_dma_sync_single_for_device, + .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu, + .sync_sg_for_device = mips_dma_sync_sg_for_device, + .mapping_error = mips_dma_mapping_error, + .dma_supported = mips_dma_supported + }, + .phys_to_dma = mips_unity_phys_to_dma, + .dma_to_phys = mips_unity_dma_to_phys +}; + +struct mips_dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops; +EXPORT_SYMBOL(mips_dma_map_ops); + +#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) + +static int __init mips_dma_init(void) +{ + dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); + + return 0; +} +fs_initcall(mips_dma_init); -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:38:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:40:59 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5482 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491084Ab0IWWih (ORCPT ); Fri, 24 Sep 2010 00:38:37 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:39:08 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:36 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:35 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMcVOA024772; Thu, 23 Sep 2010 15:38:31 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMcVb4024771; Thu, 23 Sep 2010 15:38:31 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH 8/9] MIPS: Add a platform hook for swiotlb setup. Date: Thu, 23 Sep 2010 15:38:15 -0700 Message-Id: <1285281496-24696-9-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 23 Sep 2010 22:38:35.0956 (UTC) FILETIME=[0F318740:01CB5B70] X-archive-position: 27811 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18822 Content-Length: 1073 Lines: 41 This allows platforms that are using the swiotlb to initialize it. Signed-off-by: David Daney --- arch/mips/include/asm/bootinfo.h | 5 +++++ arch/mips/kernel/setup.c | 5 +++++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index 15a8ef0..b3cf989 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -125,4 +125,9 @@ extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; */ extern void plat_mem_setup(void); +/* + * Optional platform hook to call swiotlb_setup(). + */ +extern void plat_swiotlb_setup(void); + #endif /* _ASM_BOOTINFO_H */ diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 85aef3f..8b650da 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -488,6 +488,11 @@ static void __init arch_mem_init(char **cmdline_p) bootmem_init(); sparse_init(); + +#ifdef CONFIG_SWIOTLB + plat_swiotlb_setup(); +#endif + paging_init(); } -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:38:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:41:24 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5484 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491171Ab0IWWii (ORCPT ); Fri, 24 Sep 2010 00:38:38 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:39:08 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:36 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:38:36 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMcVVJ024776; Thu, 23 Sep 2010 15:38:31 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMcVFP024775; Thu, 23 Sep 2010 15:38:31 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH 9/9] MIPS: Octeon: Rewrite DMA mapping functions. Date: Thu, 23 Sep 2010 15:38:16 -0700 Message-Id: <1285281496-24696-10-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 23 Sep 2010 22:38:36.0096 (UTC) FILETIME=[0F46E400:01CB5B70] X-archive-position: 27812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18823 Content-Length: 26320 Lines: 854 All Octeon chips can support more than 4GB of RAM. Also due to how Octeon PCI is setup, even some configurations with less than 4GB of RAM will have portions that are not accessible from 32-bit devices. Enable the swiotlb code to handle the cases where a device cannot directly do DMA. This is a complete rewrite of the Octeon DMA mapping code. Signed-off-by: David Daney --- arch/mips/cavium-octeon/Kconfig | 12 + arch/mips/cavium-octeon/dma-octeon.c | 529 +++++++++----------- .../include/asm/mach-cavium-octeon/dma-coherence.h | 19 +- arch/mips/include/asm/octeon/pci-octeon.h | 10 + arch/mips/pci/pci-octeon.c | 60 ++- arch/mips/pci/pcie-octeon.c | 5 + 6 files changed, 336 insertions(+), 299 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 47323ca..475156b 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -87,3 +87,15 @@ config ARCH_SPARSEMEM_ENABLE config CAVIUM_OCTEON_HELPER def_bool y depends on OCTEON_ETHERNET || PCI + +config IOMMU_HELPER + bool + +config NEED_SG_DMA_LENGTH + bool + +config SWIOTLB + def_bool y + depends on CPU_CAVIUM_OCTEON + select IOMMU_HELPER + select NEED_SG_DMA_LENGTH diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index d22b5a2..b94730a 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -8,335 +8,296 @@ * Copyright (C) 2005 Ilya A. Volynets-Evenbakh * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. * IP32 changes by Ilya. - * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on - * the kernels original. + * Copyright (C) 2010 Cavium Networks, Inc. */ #include #include -#include -#include +#include #include -#include +#include #include -#include -#include +#include #include -#include -#include #include #ifdef CONFIG_PCI #include -#endif +#include +#include -#define BAR2_PCI_ADDRESS 0x8000000000ul +static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr) +{ + if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) + return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE; + else + return paddr; +} -struct bar1_index_state { - int16_t ref_count; /* Number of PCI mappings using this index */ - uint16_t address_bits; /* Upper bits of physical address. This is - shifted 22 bits */ -}; +static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr) +{ + if (daddr >= CVMX_PCIE_BAR1_RC_BASE) + return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE; + else + return daddr; +} -#ifdef CONFIG_PCI -static DEFINE_RAW_SPINLOCK(bar1_lock); -static struct bar1_index_state bar1_state[32]; -#endif +static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + if (paddr >= 0x410000000ull && paddr < 0x420000000ull) + paddr -= 0x400000000ull; + return octeon_hole_phys_to_dma(paddr); +} + +static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + daddr = octeon_hole_dma_to_phys(daddr); + + if (daddr >= 0x10000000ull && daddr < 0x20000000ull) + daddr += 0x400000000ull; + + return daddr; +} + +static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + if (paddr >= 0x410000000ull && paddr < 0x420000000ull) + paddr -= 0x400000000ull; + + /* Anything in the BAR1 hole or above goes via BAR2 */ + if (paddr >= 0xf0000000ull) + paddr = OCTEON_BAR2_PCI_ADDRESS + paddr; + + return paddr; +} -dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size) +static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr) { -#ifndef CONFIG_PCI - /* Without PCI/PCIe this function can be called for Octeon internal - devices such as USB. These devices all support 64bit addressing */ + if (daddr >= OCTEON_BAR2_PCI_ADDRESS) + daddr -= OCTEON_BAR2_PCI_ADDRESS; + + if (daddr >= 0x10000000ull && daddr < 0x20000000ull) + daddr += 0x400000000ull; + return daddr; +} + +static dma_addr_t octeon_small_phys_to_dma(struct device *dev, + phys_addr_t paddr) +{ + if (paddr >= 0x410000000ull && paddr < 0x420000000ull) + paddr -= 0x400000000ull; + + /* Anything not in the BAR1 range goes via BAR2 */ + if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull) + paddr = paddr - octeon_bar1_pci_phys; + else + paddr = OCTEON_BAR2_PCI_ADDRESS + paddr; + + return paddr; +} + +static phys_addr_t octeon_small_dma_to_phys(struct device *dev, + dma_addr_t daddr) +{ + if (daddr >= OCTEON_BAR2_PCI_ADDRESS) + daddr -= OCTEON_BAR2_PCI_ADDRESS; + else + daddr += octeon_bar1_pci_phys; + + if (daddr >= 0x10000000ull && daddr < 0x20000000ull) + daddr += 0x400000000ull; + return daddr; +} + +#endif /* CONFIG_PCI */ + +static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs) +{ + dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size, + direction, attrs); mb(); - return virt_to_phys(ptr); -#else - unsigned long flags; - uint64_t dma_mask; - int64_t start_index; - dma_addr_t result = -1; - uint64_t physical = virt_to_phys(ptr); - int64_t index; + return daddr; +} + +static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction direction, struct dma_attrs *attrs) +{ + int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs); mb(); - /* - * Use the DMA masks to determine the allowed memory - * region. For us it doesn't limit the actual memory, just the - * address visible over PCI. Devices with limits need to use - * lower indexed Bar1 entries. - */ - if (dev) { - dma_mask = dev->coherent_dma_mask; - if (dev->dma_mask) - dma_mask = *dev->dma_mask; - } else { - dma_mask = 0xfffffffful; - } + return r; +} - /* - * Platform devices, such as the internal USB, skip all - * translation and use Octeon physical addresses directly. - */ - if (!dev || dev->bus == &platform_bus_type) - return physical; +static void octeon_dma_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +{ + swiotlb_sync_single_for_device(dev, dma_handle, size, direction); + mb(); +} - switch (octeon_dma_bar_type) { - case OCTEON_DMA_BAR_TYPE_PCIE: - if (unlikely(physical < (16ul << 10))) - panic("dma_map_single: Not allowed to map first 16KB." - " It interferes with BAR0 special area\n"); - else if ((physical + size >= (256ul << 20)) && - (physical < (512ul << 20))) - panic("dma_map_single: Not allowed to map bootbus\n"); - else if ((physical + size >= 0x400000000ull) && - physical < 0x410000000ull) - panic("dma_map_single: " - "Attempt to map illegal memory address 0x%llx\n", - physical); - else if (physical >= 0x420000000ull) - panic("dma_map_single: " - "Attempt to map illegal memory address 0x%llx\n", - physical); - else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE && - physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) { - result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE; - - if (((result+size-1) & dma_mask) != result+size-1) - panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n", - physical, physical+size-1, dma_mask); - goto done; - } - - /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */ - if ((physical >= 0x410000000ull) && physical < 0x420000000ull) - result = physical - 0x400000000ull; - else - result = physical; - if (((result+size-1) & dma_mask) != result+size-1) - panic("dma_map_single: Attempt to map address " - "0x%llx-0x%llx, which can't be accessed " - "according to the dma mask 0x%llx\n", - physical, physical+size-1, dma_mask); - goto done; +static void octeon_dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, int nelems, enum dma_data_direction direction) +{ + swiotlb_sync_sg_for_device(dev, sg, nelems, direction); + mb(); +} - case OCTEON_DMA_BAR_TYPE_BIG: -#ifdef CONFIG_64BIT - /* If the device supports 64bit addressing, then use BAR2 */ - if (dma_mask > BAR2_PCI_ADDRESS) { - result = physical + BAR2_PCI_ADDRESS; - goto done; - } -#endif - if (unlikely(physical < (4ul << 10))) { - panic("dma_map_single: Not allowed to map first 4KB. " - "It interferes with BAR0 special area\n"); - } else if (physical < (256ul << 20)) { - if (unlikely(physical + size > (256ul << 20))) - panic("dma_map_single: Requested memory spans " - "Bar0 0:256MB and bootbus\n"); - result = physical; - goto done; - } else if (unlikely(physical < (512ul << 20))) { - panic("dma_map_single: Not allowed to map bootbus\n"); - } else if (physical < (2ul << 30)) { - if (unlikely(physical + size > (2ul << 30))) - panic("dma_map_single: Requested memory spans " - "Bar0 512MB:2GB and BAR1\n"); - result = physical; - goto done; - } else if (physical < (2ul << 30) + (128 << 20)) { - /* Fall through */ - } else if (physical < - (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) { - if (unlikely - (physical + size > - (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))) - panic("dma_map_single: Requested memory " - "extends past Bar1 (4GB-%luMB)\n", - OCTEON_PCI_BAR1_HOLE_SIZE); - result = physical; - goto done; - } else if ((physical >= 0x410000000ull) && - (physical < 0x420000000ull)) { - if (unlikely(physical + size > 0x420000000ull)) - panic("dma_map_single: Requested memory spans " - "non existant memory\n"); - /* BAR0 fixed mapping 256MB:512MB -> - * 16GB+256MB:16GB+512MB */ - result = physical - 0x400000000ull; - goto done; - } else { - /* Continued below switch statement */ - } - break; +static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp) +{ + void *ret; - case OCTEON_DMA_BAR_TYPE_SMALL: -#ifdef CONFIG_64BIT - /* If the device supports 64bit addressing, then use BAR2 */ - if (dma_mask > BAR2_PCI_ADDRESS) { - result = physical + BAR2_PCI_ADDRESS; - goto done; - } + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) + return ret; + + /* ignore region specifiers */ + gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); + +#ifdef CONFIG_ZONE_DMA + if (dev == NULL) + gfp |= __GFP_DMA; + else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24)) + gfp |= __GFP_DMA; + else #endif - /* Continued below switch statement */ - break; +#ifdef CONFIG_ZONE_DMA32 + if (dev->coherent_dma_mask <= DMA_BIT_MASK(32)) + gfp |= __GFP_DMA32; + else +#endif + ; - default: - panic("dma_map_single: Invalid octeon_dma_bar_type\n"); - } + /* Don't invoke OOM killer */ + gfp |= __GFP_NORETRY; - /* Don't allow mapping to span multiple Bar entries. The hardware guys - won't guarantee that DMA across boards work */ - if (unlikely((physical >> 22) != ((physical + size - 1) >> 22))) - panic("dma_map_single: " - "Requested memory spans more than one Bar1 entry\n"); + ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp); - if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) - start_index = 31; - else if (unlikely(dma_mask < (1ul << 27))) - start_index = (dma_mask >> 22); - else - start_index = 31; - - /* Only one processor can access the Bar register at once */ - raw_spin_lock_irqsave(&bar1_lock, flags); - - /* Look through Bar1 for existing mapping that will work */ - for (index = start_index; index >= 0; index--) { - if ((bar1_state[index].address_bits == physical >> 22) && - (bar1_state[index].ref_count)) { - /* An existing mapping will work, use it */ - bar1_state[index].ref_count++; - if (unlikely(bar1_state[index].ref_count < 0)) - panic("dma_map_single: " - "Bar1[%d] reference count overflowed\n", - (int) index); - result = (index << 22) | (physical & ((1 << 22) - 1)); - /* Large BAR1 is offset at 2GB */ - if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) - result += 2ul << 30; - goto done_unlock; - } - } + mb(); - /* No existing mappings, look for a free entry */ - for (index = start_index; index >= 0; index--) { - if (unlikely(bar1_state[index].ref_count == 0)) { - union cvmx_pci_bar1_indexx bar1_index; - /* We have a free entry, use it */ - bar1_state[index].ref_count = 1; - bar1_state[index].address_bits = physical >> 22; - bar1_index.u32 = 0; - /* Address bits[35:22] sent to L2C */ - bar1_index.s.addr_idx = physical >> 22; - /* Don't put PCI accesses in L2. */ - bar1_index.s.ca = 1; - /* Endian Swap Mode */ - bar1_index.s.end_swp = 1; - /* Set '1' when the selected address range is valid. */ - bar1_index.s.addr_v = 1; - octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), - bar1_index.u32); - /* An existing mapping will work, use it */ - result = (index << 22) | (physical & ((1 << 22) - 1)); - /* Large BAR1 is offset at 2GB */ - if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) - result += 2ul << 30; - goto done_unlock; - } - } + return ret; +} + +static void octeon_dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + int order = get_order(size); - pr_err("dma_map_single: " - "Can't find empty BAR1 index for physical mapping 0x%llx\n", - (unsigned long long) physical); + if (dma_release_from_coherent(dev, order, vaddr)) + return; -done_unlock: - raw_spin_unlock_irqrestore(&bar1_lock, flags); -done: - pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result); - return result; -#endif + swiotlb_free_coherent(dev, size, vaddr, dma_handle); } -void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +static struct mips_dma_map_ops octeon_linear_dma_map_ops = { + .dma_map_ops = { + .alloc_coherent = octeon_dma_alloc_coherent, + .free_coherent = octeon_dma_free_coherent, + .map_page = octeon_dma_map_page, + .unmap_page = swiotlb_unmap_page, + .map_sg = octeon_dma_map_sg, + .unmap_sg = swiotlb_unmap_sg_attrs, + .sync_single_for_cpu = swiotlb_sync_single_for_cpu, + .sync_single_for_device = octeon_dma_sync_single_for_device, + .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, + .sync_sg_for_device = octeon_dma_sync_sg_for_device, + .mapping_error = swiotlb_dma_mapping_error, + .dma_supported = swiotlb_dma_supported + }, + .phys_to_dma = mips_unity_phys_to_dma, + .dma_to_phys = mips_unity_dma_to_phys +}; + +void __init plat_swiotlb_setup(void) { -#ifndef CONFIG_PCI - /* - * Without PCI/PCIe this function can be called for Octeon internal - * devices such as USB. These devices all support 64bit addressing. - */ - return; -#else - unsigned long flags; - uint64_t index; + int i; + phys_t max_addr; + phys_t addr_size; + size_t swiotlbsize; + max_addr = 0; + addr_size = 0; + + for (i = 0 ; i < boot_mem_map.nr_map; i++) { + struct boot_mem_map_entry *e = &boot_mem_map.map[i]; + if (e->type != BOOT_MEM_RAM) + continue; + + /* These addresses map low for PCI. */ + if (e->addr > 0x410000000ull) + continue; + + addr_size += e->size; + + if (max_addr < e->addr + e->size) + max_addr = e->addr + e->size; + + } + + swiotlbsize = PAGE_SIZE; + +#ifdef CONFIG_PCI /* - * Platform devices, such as the internal USB, skip all - * translation and use Octeon physical addresses directly. + * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory + * size to a maximum of 64MB */ - if (dev->bus == &platform_bus_type) - return; + if (OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) { + swiotlbsize = addr_size / 4; + if (swiotlbsize > 64 * (1<<20)) + swiotlbsize = 64 * (1<<20); + } else if (max_addr > 0xf0000000ul) { + /* + * Otherwise only allocate a big iotlb if there is + * memory past the BAR1 hole. + */ + swiotlbsize = 64 * (1<<20); + } +#endif + + swiotlb_init_with_default_size(swiotlbsize, 1); + + mips_dma_map_ops = &octeon_linear_dma_map_ops; +} + +#ifdef CONFIG_PCI +struct mips_dma_map_ops octeon_pci_dma_map_ops = { + .dma_map_ops = { + .alloc_coherent = octeon_dma_alloc_coherent, + .free_coherent = octeon_dma_free_coherent, + .map_page = octeon_dma_map_page, + .unmap_page = swiotlb_unmap_page, + .map_sg = octeon_dma_map_sg, + .unmap_sg = swiotlb_unmap_sg_attrs, + .sync_single_for_cpu = swiotlb_sync_single_for_cpu, + .sync_single_for_device = octeon_dma_sync_single_for_device, + .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, + .sync_sg_for_device = octeon_dma_sync_sg_for_device, + .mapping_error = swiotlb_dma_mapping_error, + .dma_supported = swiotlb_dma_supported + }, +}; +void __init octeon_pci_dma_init(void) +{ switch (octeon_dma_bar_type) { case OCTEON_DMA_BAR_TYPE_PCIE: - /* Nothing to do, all mappings are static */ - goto done; - + octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma; + octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys; + break; case OCTEON_DMA_BAR_TYPE_BIG: -#ifdef CONFIG_64BIT - /* Nothing to do for addresses using BAR2 */ - if (dma_addr >= BAR2_PCI_ADDRESS) - goto done; -#endif - if (unlikely(dma_addr < (4ul << 10))) - panic("dma_unmap_single: Unexpect DMA address 0x%llx\n", - dma_addr); - else if (dma_addr < (2ul << 30)) - /* Nothing to do for addresses using BAR0 */ - goto done; - else if (dma_addr < (2ul << 30) + (128ul << 20)) - /* Need to unmap, fall through */ - index = (dma_addr - (2ul << 30)) >> 22; - else if (dma_addr < - (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) - goto done; /* Nothing to do for the rest of BAR1 */ - else - panic("dma_unmap_single: Unexpect DMA address 0x%llx\n", - dma_addr); - /* Continued below switch statement */ + octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma; + octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys; break; - case OCTEON_DMA_BAR_TYPE_SMALL: -#ifdef CONFIG_64BIT - /* Nothing to do for addresses using BAR2 */ - if (dma_addr >= BAR2_PCI_ADDRESS) - goto done; -#endif - index = dma_addr >> 22; - /* Continued below switch statement */ + octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma; + octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys; break; - default: - panic("dma_unmap_single: Invalid octeon_dma_bar_type\n"); + break; } - - if (unlikely(index > 31)) - panic("dma_unmap_single: " - "Attempt to unmap an invalid address (0x%llx)\n", - dma_addr); - - raw_spin_lock_irqsave(&bar1_lock, flags); - bar1_state[index].ref_count--; - if (bar1_state[index].ref_count == 0) - octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0); - else if (unlikely(bar1_state[index].ref_count < 0)) - panic("dma_unmap_single: Bar1[%u] reference count < 0\n", - (int) index); - raw_spin_unlock_irqrestore(&bar1_lock, flags); -done: - pr_debug("dma_unmap_single 0x%llx\n", dma_addr); - return; -#endif } +#endif /* CONFIG_PCI */ diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h index 17d5794..a0058fb 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -15,41 +15,40 @@ struct device; -dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t); -void octeon_unmap_dma_mem(struct device *, dma_addr_t); +void octeon_pci_dma_init(void); static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) { - return octeon_map_dma_mem(dev, addr, size); + BUG(); } static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) { - return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE); + BUG(); } static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { - return dma_addr; + BUG(); } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction) { - octeon_unmap_dma_mem(dev, dma_addr); + BUG(); } static inline int plat_dma_supported(struct device *dev, u64 mask) { - return 1; + BUG(); } static inline void plat_extra_sync_for_device(struct device *dev) { - mb(); + BUG(); } static inline int plat_device_is_coherent(struct device *dev) @@ -60,7 +59,9 @@ static inline int plat_device_is_coherent(struct device *dev) static inline int plat_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { - return dma_addr == -1; + BUG(); } +extern struct mips_dma_map_ops octeon_pci_dma_map_ops; + #endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h index ece7804..fba2ba2 100644 --- a/arch/mips/include/asm/octeon/pci-octeon.h +++ b/arch/mips/include/asm/octeon/pci-octeon.h @@ -36,6 +36,16 @@ extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); /* + * For PCI (not PCIe) the BAR2 base address. + */ +#define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull + +/* + * For PCI (not PCIe) the base of the memory mapped by BAR1 + */ +extern u64 octeon_bar1_pci_phys; + +/* * The following defines are used when octeon_dma_bar_type = * OCTEON_DMA_BAR_TYPE_BIG */ diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index d248b70..311d808 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -11,6 +11,7 @@ #include #include #include +#include #include @@ -19,6 +20,8 @@ #include #include +#include + #define USE_OCTEON_INTERNAL_ARBITER /* @@ -32,6 +35,8 @@ /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */ #define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull) +u64 octeon_bar1_pci_phys; + /** * This is the bit decoding used for the Octeon PCI controller addresses */ @@ -170,6 +175,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev) pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); } + dev->dev.archdata.dma_ops = &octeon_pci_dma_map_ops; + return 0; } @@ -618,12 +625,10 @@ static int __init octeon_pci_setup(void) * before the readl()'s below. We don't want BAR2 overlapping * with BAR0/BAR1 during these reads. */ - octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0); - octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80); - - /* Disable the BAR1 movable mappings */ - for (index = 0; index < 32; index++) - octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0); + octeon_npi_write32(CVMX_NPI_PCI_CFG08, + (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull)); + octeon_npi_write32(CVMX_NPI_PCI_CFG09, + (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32)); if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { /* Remap the Octeon BAR 0 to 0-2GB */ @@ -637,6 +642,25 @@ static int __init octeon_pci_setup(void) octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30); octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); + /* BAR1 movable mappings set for identity mapping */ + octeon_bar1_pci_phys = 0x80000000ull; + for (index = 0; index < 32; index++) { + union cvmx_pci_bar1_indexx bar1_index; + + bar1_index.u32 = 0; + /* Address bits[35:22] sent to L2C */ + bar1_index.s.addr_idx = + (octeon_bar1_pci_phys >> 22) + index; + /* Don't put PCI accesses in L2. */ + bar1_index.s.ca = 1; + /* Endian Swap Mode */ + bar1_index.s.end_swp = 1; + /* Set '1' when the selected address range is valid. */ + bar1_index.s.addr_v = 1; + octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), + bar1_index.u32); + } + /* Devices go after BAR1 */ octeon_pci_mem_resource.start = OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) - @@ -652,6 +676,27 @@ static int __init octeon_pci_setup(void) octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0); octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); + /* BAR1 movable regions contiguous to cover the swiotlb */ + octeon_bar1_pci_phys = + virt_to_phys(swiotlb_start) & ~((1ull << 22) - 1); + + for (index = 0; index < 32; index++) { + union cvmx_pci_bar1_indexx bar1_index; + + bar1_index.u32 = 0; + /* Address bits[35:22] sent to L2C */ + bar1_index.s.addr_idx = + (octeon_bar1_pci_phys >> 22) + index; + /* Don't put PCI accesses in L2. */ + bar1_index.s.ca = 1; + /* Endian Swap Mode */ + bar1_index.s.end_swp = 1; + /* Set '1' when the selected address range is valid. */ + bar1_index.s.addr_v = 1; + octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), + bar1_index.u32); + } + /* Devices go after BAR0 */ octeon_pci_mem_resource.start = OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) + @@ -667,6 +712,9 @@ static int __init octeon_pci_setup(void) * was setup properly. */ cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); + + octeon_pci_dma_init(); + return 0; } diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 861361e..385f035 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -75,6 +75,8 @@ union cvmx_pcie_address { } mem; }; +#include + /** * Return the Core virtual base address for PCIe IO access. IOs are * read/written as an offset from this address. @@ -1391,6 +1393,9 @@ static int __init octeon_pcie_setup(void) cvmx_pcie_get_io_size(1) - 1; register_pci_controller(&octeon_pcie1_controller); } + + octeon_pci_dma_init(); + return 0; } -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:47:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:47:50 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5675 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491171Ab0IWWrq (ORCPT ); Fri, 24 Sep 2010 00:47:46 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:48:16 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:47:43 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:47:43 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMldTA024942; Thu, 23 Sep 2010 15:47:39 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMlc8M024941; Thu, 23 Sep 2010 15:47:38 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney , Andrew Morton , FUJITA Tomonori , Konrad Rzeszutek Wilk , Ingo Molnar , Andre Goddard Rosa Subject: [PATCH 6/9] swiotlb: Declare swiotlb_init_with_default_size() Date: Thu, 23 Sep 2010 15:47:30 -0700 Message-Id: <1285282051-24907-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 23 Sep 2010 22:47:43.0322 (UTC) FILETIME=[5572F3A0:01CB5B71] X-archive-position: 27813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18828 Content-Length: 874 Lines: 27 It comes from swiotlb.c and must be called by external code, so declare it. Signed-off-by: David Daney Cc: Andrew Morton Cc: FUJITA Tomonori Cc: Konrad Rzeszutek Wilk Cc: Ingo Molnar Cc: Andre Goddard Rosa --- include/linux/swiotlb.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h index 8c0e349..dba51fe 100644 --- a/include/linux/swiotlb.h +++ b/include/linux/swiotlb.h @@ -23,6 +23,7 @@ extern int swiotlb_force; #define IO_TLB_SHIFT 11 extern void swiotlb_init(int verbose); +extern void swiotlb_init_with_default_size(size_t, int); extern void swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose); /* -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 00:47:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 00:48:14 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5663 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491172Ab0IWWrs (ORCPT ); Fri, 24 Sep 2010 00:47:48 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 15:48:15 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:47:43 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 15:47:43 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8NMleaF024946; Thu, 23 Sep 2010 15:47:40 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8NMle7L024945; Thu, 23 Sep 2010 15:47:40 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney , Andrew Morton , FUJITA Tomonori , Konrad Rzeszutek Wilk , Ingo Molnar , Andre Goddard Rosa Subject: [PATCH 7/9] swiotlb: Make bounce buffer bounds non-static. Date: Thu, 23 Sep 2010 15:47:31 -0700 Message-Id: <1285282051-24907-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 23 Sep 2010 22:47:43.0150 (UTC) FILETIME=[5558B4E0:01CB5B71] X-archive-position: 27814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18829 Content-Length: 7894 Lines: 223 Octeon PCI mapping has to be established to cover the bounce buffers, so it has to have access to the bounds. Rename the bounds variables to match the names of other parts of swiotlb. Signed-off-by: David Daney Cc: Andrew Morton Cc: FUJITA Tomonori Cc: Konrad Rzeszutek Wilk Cc: Ingo Molnar Cc: Andre Goddard Rosa --- include/linux/swiotlb.h | 6 ++++ lib/swiotlb.c | 62 +++++++++++++++++++++++----------------------- 2 files changed, 37 insertions(+), 31 deletions(-) diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h index dba51fe..0b8fbe9 100644 --- a/include/linux/swiotlb.h +++ b/include/linux/swiotlb.h @@ -22,6 +22,12 @@ extern int swiotlb_force; */ #define IO_TLB_SHIFT 11 +/* + * The memory range used by the swiotlb + */ +extern char *swiotlb_start; +extern char *swiotlb_end; + extern void swiotlb_init(int verbose); extern void swiotlb_init_with_default_size(size_t, int); extern void swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose); diff --git a/lib/swiotlb.c b/lib/swiotlb.c index 34e3082..4cb4ad7 100644 --- a/lib/swiotlb.c +++ b/lib/swiotlb.c @@ -57,11 +57,11 @@ int swiotlb_force; * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this * API. */ -static char *io_tlb_start, *io_tlb_end; +char *swiotlb_start, *swiotlb_end; /* - * The number of IO TLB blocks (in groups of 64) betweeen io_tlb_start and - * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. + * The number of IO TLB blocks (in groups of 64) betweeen swiotlb_start and + * swiotlb_end. This is command line adjustable via setup_io_tlb_npages. */ static unsigned long io_tlb_nslabs; @@ -122,11 +122,11 @@ void swiotlb_print_info(void) unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; phys_addr_t pstart, pend; - pstart = virt_to_phys(io_tlb_start); - pend = virt_to_phys(io_tlb_end); + pstart = virt_to_phys(swiotlb_start); + pend = virt_to_phys(swiotlb_end); printk(KERN_INFO "Placing %luMB software IO TLB between %p - %p\n", - bytes >> 20, io_tlb_start, io_tlb_end); + bytes >> 20, swiotlb_start, swiotlb_end); printk(KERN_INFO "software IO TLB at phys %#llx - %#llx\n", (unsigned long long)pstart, (unsigned long long)pend); @@ -139,13 +139,13 @@ void __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) bytes = nslabs << IO_TLB_SHIFT; io_tlb_nslabs = nslabs; - io_tlb_start = tlb; - io_tlb_end = io_tlb_start + bytes; + swiotlb_start = tlb; + swiotlb_end = swiotlb_start + bytes; /* * Allocate and initialize the free list array. This array is used * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE - * between io_tlb_start and io_tlb_end. + * between swiotlb_start and swiotlb_end. */ io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int)); for (i = 0; i < io_tlb_nslabs; i++) @@ -182,11 +182,11 @@ swiotlb_init_with_default_size(size_t default_size, int verbose) /* * Get IO TLB memory from the low pages */ - io_tlb_start = alloc_bootmem_low_pages(bytes); - if (!io_tlb_start) + swiotlb_start = alloc_bootmem_low_pages(bytes); + if (!swiotlb_start) panic("Cannot allocate SWIOTLB buffer"); - swiotlb_init_with_tbl(io_tlb_start, io_tlb_nslabs, verbose); + swiotlb_init_with_tbl(swiotlb_start, io_tlb_nslabs, verbose); } void __init @@ -219,14 +219,14 @@ swiotlb_late_init_with_default_size(size_t default_size) bytes = io_tlb_nslabs << IO_TLB_SHIFT; while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { - io_tlb_start = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, - order); - if (io_tlb_start) + swiotlb_start = + (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, order); + if (swiotlb_start) break; order--; } - if (!io_tlb_start) + if (!swiotlb_start) goto cleanup1; if (order != get_order(bytes)) { @@ -235,13 +235,13 @@ swiotlb_late_init_with_default_size(size_t default_size) io_tlb_nslabs = SLABS_PER_PAGE << order; bytes = io_tlb_nslabs << IO_TLB_SHIFT; } - io_tlb_end = io_tlb_start + bytes; - memset(io_tlb_start, 0, bytes); + swiotlb_end = swiotlb_start + bytes; + memset(swiotlb_start, 0, bytes); /* * Allocate and initialize the free list array. This array is used * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE - * between io_tlb_start and io_tlb_end. + * between swiotlb_start and swiotlb_end. */ io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, get_order(io_tlb_nslabs * sizeof(int))); @@ -284,9 +284,9 @@ cleanup3: sizeof(int))); io_tlb_list = NULL; cleanup2: - io_tlb_end = NULL; - free_pages((unsigned long)io_tlb_start, order); - io_tlb_start = NULL; + swiotlb_end = NULL; + free_pages((unsigned long)swiotlb_start, order); + swiotlb_start = NULL; cleanup1: io_tlb_nslabs = req_nslabs; return -ENOMEM; @@ -304,7 +304,7 @@ void __init swiotlb_free(void) get_order(io_tlb_nslabs * sizeof(phys_addr_t))); free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * sizeof(int))); - free_pages((unsigned long)io_tlb_start, + free_pages((unsigned long)swiotlb_start, get_order(io_tlb_nslabs << IO_TLB_SHIFT)); } else { free_bootmem_late(__pa(io_tlb_overflow_buffer), @@ -313,15 +313,15 @@ void __init swiotlb_free(void) io_tlb_nslabs * sizeof(phys_addr_t)); free_bootmem_late(__pa(io_tlb_list), io_tlb_nslabs * sizeof(int)); - free_bootmem_late(__pa(io_tlb_start), + free_bootmem_late(__pa(swiotlb_start), io_tlb_nslabs << IO_TLB_SHIFT); } } static int is_swiotlb_buffer(phys_addr_t paddr) { - return paddr >= virt_to_phys(io_tlb_start) && - paddr < virt_to_phys(io_tlb_end); + return paddr >= virt_to_phys(swiotlb_start) && + paddr < virt_to_phys(swiotlb_end); } /* @@ -435,7 +435,7 @@ void *swiotlb_tbl_map_single(struct device *hwdev, dma_addr_t tbl_dma_addr, io_tlb_list[i] = 0; for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) io_tlb_list[i] = ++count; - dma_addr = io_tlb_start + (index << IO_TLB_SHIFT); + dma_addr = swiotlb_start + (index << IO_TLB_SHIFT); /* * Update the indices to avoid searching in the next @@ -479,7 +479,7 @@ static void * map_single(struct device *hwdev, phys_addr_t phys, size_t size, enum dma_data_direction dir) { - dma_addr_t start_dma_addr = swiotlb_virt_to_bus(hwdev, io_tlb_start); + dma_addr_t start_dma_addr = swiotlb_virt_to_bus(hwdev, swiotlb_start); return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, dir); } @@ -493,7 +493,7 @@ swiotlb_tbl_unmap_single(struct device *hwdev, char *dma_addr, size_t size, { unsigned long flags; int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; - int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; + int index = (dma_addr - swiotlb_start) >> IO_TLB_SHIFT; phys_addr_t phys = io_tlb_orig_addr[index]; /* @@ -534,7 +534,7 @@ swiotlb_tbl_sync_single(struct device *hwdev, char *dma_addr, size_t size, enum dma_data_direction dir, enum dma_sync_target target) { - int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; + int index = (dma_addr - swiotlb_start) >> IO_TLB_SHIFT; phys_addr_t phys = io_tlb_orig_addr[index]; phys += ((unsigned long)dma_addr & ((1 << IO_TLB_SHIFT) - 1)); @@ -918,6 +918,6 @@ EXPORT_SYMBOL(swiotlb_dma_mapping_error); int swiotlb_dma_supported(struct device *hwdev, u64 mask) { - return swiotlb_virt_to_bus(hwdev, io_tlb_end - 1) <= mask; + return swiotlb_virt_to_bus(hwdev, swiotlb_end - 1) <= mask; } EXPORT_SYMBOL(swiotlb_dma_supported); -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 03:03:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 03:03:43 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8608 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491117Ab0IXBDk (ORCPT ); Fri, 24 Sep 2010 03:03:40 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 18:04:09 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 18:03:37 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 18:03:36 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8O13XT3004261; Thu, 23 Sep 2010 18:03:33 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8O13UAJ004260; Thu, 23 Sep 2010 18:03:30 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney , Wu Zhangjin , David VomLehn Subject: [PATCH] MIPS: Remove plat_map_dma_mem_page(). Date: Thu, 23 Sep 2010 18:03:21 -0700 Message-Id: <1285290201-4226-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-6-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-6-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 24 Sep 2010 01:03:36.0958 (UTC) FILETIME=[516511E0:01CB5B84] X-archive-position: 27815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18947 Content-Length: 4643 Lines: 129 It is now unused. Signed-off-by: David Daney Cc: Wu Zhangjin Cc: David VomLehn --- This is a small addition to the rest of the patch set. It could be rolled into [PATCH 5/9] MIPS: Convert DMA to use dma-mapping-common.h arch/mips/include/asm/mach-generic/dma-coherence.h | 6 ------ arch/mips/include/asm/mach-ip27/dma-coherence.h | 7 ------- arch/mips/include/asm/mach-ip32/dma-coherence.h | 12 ------------ arch/mips/include/asm/mach-jazz/dma-coherence.h | 5 ----- .../mips/include/asm/mach-loongson/dma-coherence.h | 6 ------ arch/mips/include/asm/mach-powertv/dma-coherence.h | 6 ------ 6 files changed, 0 insertions(+), 42 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 8da9807..8259966 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -17,12 +17,6 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, return virt_to_phys(addr); } -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return page_to_phys(page); -} - static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h index d3d0401..e35bfbc 100644 --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h @@ -26,13 +26,6 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, return pa; } -static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -{ - dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page)); - - return pa; -} - static unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h index 3785595..7dd1907 100644 --- a/arch/mips/include/asm/mach-ip32/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h @@ -37,18 +37,6 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, return pa; } -static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -{ - dma_addr_t pa; - - pa = page_to_phys(page) & RAM_OFFSET_MASK; - - if (dev == NULL) - pa += CRIME_HI_MEM_BASE; - - return pa; -} - /* This is almost certainly wrong but it's what dma-ip32.c used to use */ static unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h index f93aee5..e0d340b 100644 --- a/arch/mips/include/asm/mach-jazz/dma-coherence.h +++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h @@ -17,11 +17,6 @@ static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) return vdma_alloc(virt_to_phys(addr), size); } -static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -{ - return vdma_alloc(page_to_phys(page), PAGE_SIZE); -} - static unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index 981c75f..8daeaee 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -19,12 +19,6 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, return virt_to_phys(addr) | 0x80000000; } -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return page_to_phys(page) | 0x80000000; -} - static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h index f76029c..647de8c 100644 --- a/arch/mips/include/asm/mach-powertv/dma-coherence.h +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h @@ -70,12 +70,6 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, return phys_to_dma(virt_to_phys(addr)); } -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return phys_to_dma(page_to_phys(page)); -} - static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { -- 1.7.2.2 From ddaney@caviumnetworks.com Fri Sep 24 03:06:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 03:06:56 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8629 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491117Ab0IXBGx (ORCPT ); Fri, 24 Sep 2010 03:06:53 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 23 Sep 2010 18:07:24 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 18:06:51 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 23 Sep 2010 18:06:51 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8O16jUu004391; Thu, 23 Sep 2010 18:06:45 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8O16h0p004390; Thu, 23 Sep 2010 18:06:43 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Cc: David Daney Subject: [PATCH] MIPS: Octeon: Remove plat_map_dma_mem_page(). Date: Thu, 23 Sep 2010 18:06:38 -0700 Message-Id: <1285290398-4358-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: <1285281496-24696-10-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-10-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 24 Sep 2010 01:06:51.0273 (UTC) FILETIME=[C5372F90:01CB5B84] X-archive-position: 27816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 18949 Content-Length: 942 Lines: 31 It is now unused. Signed-off-by: David Daney --- This is a small addition to the rest of the patch set. It could be rolled into [PATCH 9/9] MIPS: Octeon: Rewrite DMA mapping functions. .../include/asm/mach-cavium-octeon/dma-coherence.h | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h index a0058fb..cedf254 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -23,12 +23,6 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, BUG(); } -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - BUG(); -} - static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { -- 1.7.2.2 From matt@console-pimps.org Fri Sep 24 10:36:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 10:36:43 +0200 (CEST) Received: from arkanian.console-pimps.org ([212.110.184.194]:35345 "EHLO arkanian.console-pimps.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490962Ab0IXIgk (ORCPT ); Fri, 24 Sep 2010 10:36:40 +0200 Received: by arkanian.console-pimps.org (Postfix, from userid 1000) id 5BAAD4432D; Fri, 24 Sep 2010 09:36:38 +0100 (BST) Date: Fri, 24 Sep 2010 09:36:38 +0100 From: Matt Fleming To: Deng-Cheng Zhu Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Subject: Re: [PATCH v6 4/7] MIPS: add support for hardware performance events (skeleton) Message-ID: <20100924083638.GA7503@console-pimps.org> References: <1276058130-25851-1-git-send-email-dengcheng.zhu@gmail.com> <1276058130-25851-5-git-send-email-dengcheng.zhu@gmail.com> <20100922122711.GB6392@console-pimps.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) X-archive-position: 27817 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matt@console-pimps.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19121 Content-Length: 2428 Lines: 43 On Thu, Sep 23, 2010 at 03:39:51PM +0800, Deng-Cheng Zhu wrote: > 2010/9/22 Matt Fleming : > > I'm probably just being stupid but I can't figure out what this snippet > > of code is doing. You're checking to see if the counter has overflowed, > > and if it has then you just clear the overflow bit? I would have > > expected you to reset the counter to 0. > [DC]: Maybe my original code comment for the member msbs of the struct > cpu_hw_events is too simple. And here is more: Unlike the perf counters in > some other architectures, a 32bit MIPS perf counter, for example, will > generate an interrupt after 0x7fffffff. But we want the operation to look > like: 0x0 -> 0xffffffff -> interrupt. So there's a "pseudo" signal halfway. > Please also note that the counter value will be brought back to 0 soon > after it reaches 0x80000000 *each time*. Ah OK, thanks. > > Having conditional code like this is a pretty sure sign that you haven't > > separated support for the various performance hardware properly. Have > > you had a look at how SH uses a registration interface to register > > sh_pmus? Ideally all the internals for each type of perfcounter > > hardware should be in their own file. > [DC]: It does look ugly. It should be easy to put conditional code into > perf_event_[mipsxx|loongson2|rm9000].c. I'll post a patch to fix it when > the whole thing is accepted. The potential problem with doing a cleanup patch after this series has been merged is that it will modify most of the code in this patch series - essentially rewriting it. I don't have a strong opinion either way but Ralf may. > > SH also has this problem that it doesn't have any sort of performance > > counter interrupt and so can't check for overflow. This lack of > > interrupt really needs to be solved generically in perf as it's a > > problem that effects quite a few architectures. I suspect that using a > > hrtimer instead of piggy-backing the timer interrupt would make the core > > perf guys happier. Writing support for this is on my ever-growing list > > of things todo. I've already started on some patches for the perf tool > > so that it's possible to sample counters even though there is no > > periodic interrupt (but that's a different problem). > [DC]: Please add me into your post list when your patches are ready :-) > Finally, thanks for your time to review the code. Sure, I will do. No problem! From ralf@linux-mips.org Fri Sep 24 13:29:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 13:29:26 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491012Ab0IXL3W (ORCPT ); Fri, 24 Sep 2010 13:29:22 +0200 Date: Fri, 24 Sep 2010 12:29:21 +0100 From: Ralf Baechle To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Subject: Re: Which Linux driver (source code) is used for tty0 (console) on MALTA? Message-ID: <20100924112921.GA17964@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19201 Content-Length: 1426 Lines: 34 On Wed, Sep 22, 2010 at 11:49:25AM -0700, Ardelean, Andrei wrote: > I am using MALTA and my goal is to port MIPS Linux on a new platform. > Which driver (source code) is used for tty0 (console)? I see the support > for "early console" but I think that this is not the real Linux driver > used after boot stage. Correct. Early console uses an extremly simple driver which in general is separate from the full blown driver that takes over later. > More general, how to find which code source is used for an embedded > driver (part of the Kernel at compiling time) for each h/w resource. > MIPS Linux distribution comes with a lot of drivers but I have > difficulties to figure out which one is used for MALTA. Is it a files > where all those are registered? For any modern style driver that information is available through sysfs. For example on this laptop here: # cd /sys/devices/platform/serial8250 # ls -l total 0 lrwxrwxrwx. 1 root root 0 Sep 24 12:20 driver -> ../../../bus/platform/drivers/serial8250 -r--r--r--. 1 root root 4096 Sep 24 12:20 modalias drwxr-xr-x. 2 root root 0 Sep 24 12:20 power lrwxrwxrwx. 1 root root 0 Sep 24 12:20 subsystem -> ../../../bus/platform drwxr-xr-x. 5 root root 0 Sep 24 12:20 tty -rw-r--r--. 1 root root 4096 Sep 24 12:20 uevent # So you see the driver being used is the 8250 driver. Similar you can find the driver for a PCI device in /sys/devices/pci* etc. Ralf From sshtylyov@mvista.com Fri Sep 24 18:09:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 18:09:48 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:55675 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491046Ab0IXQJo (ORCPT ); Fri, 24 Sep 2010 18:09:44 +0200 Received: by eye22 with SMTP id 22so991963eye.36 for ; Fri, 24 Sep 2010 09:09:43 -0700 (PDT) Received: by 10.213.12.196 with SMTP id y4mr3218037eby.89.1285344583292; Fri, 24 Sep 2010 09:09:43 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id u9sm3304223eeh.23.2010.09.24.09.09.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 24 Sep 2010 09:09:42 -0700 (PDT) Message-ID: <4C9CCD1B.506@mvista.com> Date: Fri, 24 Sep 2010 20:08:59 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 8/9] MIPS: Add a platform hook for swiotlb setup. References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> <1285281496-24696-9-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1285281496-24696-9-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 27819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19420 Content-Length: 1280 Lines: 44 Hello. David Daney wrote: > This allows platforms that are using the swiotlb to initialize it. > Signed-off-by: David Daney > --- > arch/mips/include/asm/bootinfo.h | 5 +++++ > arch/mips/kernel/setup.c | 5 +++++ > 2 files changed, 10 insertions(+), 0 deletions(-) > diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h > index 15a8ef0..b3cf989 100644 > --- a/arch/mips/include/asm/bootinfo.h > +++ b/arch/mips/include/asm/bootinfo.h > @@ -125,4 +125,9 @@ extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; > */ > extern void plat_mem_setup(void); > > +/* > + * Optional platform hook to call swiotlb_setup(). > + */ > +extern void plat_swiotlb_setup(void); > + > #endif /* _ASM_BOOTINFO_H */ > diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c > index 85aef3f..8b650da 100644 > --- a/arch/mips/kernel/setup.c > +++ b/arch/mips/kernel/setup.c > @@ -488,6 +488,11 @@ static void __init arch_mem_init(char **cmdline_p) > > bootmem_init(); > sparse_init(); > + > +#ifdef CONFIG_SWIOTLB > + plat_swiotlb_setup(); > +#endif We should avoid #ifdef's in function bodies. Why not defile an empty 'inline' in the header above if CONFIG_SWIOTLB is not defined? WBR, Sergei From ddaney@caviumnetworks.com Fri Sep 24 18:13:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 18:14:02 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5456 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491046Ab0IXQN7 (ORCPT ); Fri, 24 Sep 2010 18:13:59 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 24 Sep 2010 09:14:27 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 24 Sep 2010 09:13:54 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 24 Sep 2010 09:13:54 -0700 Message-ID: <4C9CCE42.3030309@caviumnetworks.com> Date: Fri, 24 Sep 2010 09:13:54 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Sergei Shtylyov CC: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 8/9] MIPS: Add a platform hook for swiotlb setup. References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> <1285281496-24696-9-git-send-email-ddaney@caviumnetworks.com> <4C9CCD1B.506@mvista.com> In-Reply-To: <4C9CCD1B.506@mvista.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 24 Sep 2010 16:13:54.0621 (UTC) FILETIME=[7C0F0ED0:01CB5C03] X-archive-position: 27820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19427 Content-Length: 1444 Lines: 50 On 09/24/2010 09:08 AM, Sergei Shtylyov wrote: > Hello. > > David Daney wrote: > >> This allows platforms that are using the swiotlb to initialize it. > >> Signed-off-by: David Daney >> --- >> arch/mips/include/asm/bootinfo.h | 5 +++++ >> arch/mips/kernel/setup.c | 5 +++++ >> 2 files changed, 10 insertions(+), 0 deletions(-) > >> diff --git a/arch/mips/include/asm/bootinfo.h >> b/arch/mips/include/asm/bootinfo.h >> index 15a8ef0..b3cf989 100644 >> --- a/arch/mips/include/asm/bootinfo.h >> +++ b/arch/mips/include/asm/bootinfo.h >> @@ -125,4 +125,9 @@ extern unsigned long fw_arg0, fw_arg1, fw_arg2, >> fw_arg3; >> */ >> extern void plat_mem_setup(void); >> >> +/* >> + * Optional platform hook to call swiotlb_setup(). >> + */ >> +extern void plat_swiotlb_setup(void); >> + >> #endif /* _ASM_BOOTINFO_H */ >> diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c >> index 85aef3f..8b650da 100644 >> --- a/arch/mips/kernel/setup.c >> +++ b/arch/mips/kernel/setup.c >> @@ -488,6 +488,11 @@ static void __init arch_mem_init(char **cmdline_p) >> >> bootmem_init(); >> sparse_init(); >> + >> +#ifdef CONFIG_SWIOTLB >> + plat_swiotlb_setup(); >> +#endif > > We should avoid #ifdef's in function bodies. Why not defile an empty > 'inline' in the header above if CONFIG_SWIOTLB is not defined? > Good idea. I will wait several days and collect any more feedback and generate a new patch set. David Daney From ralf@linux-mips.org Fri Sep 24 18:32:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 18:32:20 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by eddie.linux-mips.org id S1491046Ab0IXQcP (ORCPT ); Fri, 24 Sep 2010 18:32:15 +0200 Date: Fri, 24 Sep 2010 17:32:14 +0100 From: Ralf Baechle To: David Daney Cc: Sergei Shtylyov , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 8/9] MIPS: Add a platform hook for swiotlb setup. Message-ID: <20100924163214.GA29252@linux-mips.org> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> <1285281496-24696-9-git-send-email-ddaney@caviumnetworks.com> <4C9CCD1B.506@mvista.com> <4C9CCE42.3030309@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C9CCE42.3030309@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-archive-position: 27821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19473 Content-Length: 501 Lines: 17 On Fri, Sep 24, 2010 at 09:13:54AM -0700, David Daney wrote: > >>+#ifdef CONFIG_SWIOTLB > >>+ plat_swiotlb_setup(); > >>+#endif > > > >We should avoid #ifdef's in function bodies. Why not defile an empty > >'inline' in the header above if CONFIG_SWIOTLB is not defined? > > > > Good idea. I will wait several days and collect any more feedback > and generate a new patch set. I'd also wait for a few more days so interested parties outside of the MIPS world will have a chance to comment. Ralf From gregkh@suse.de Fri Sep 24 18:36:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 18:36:04 +0200 (CEST) Received: from kroah.org ([198.145.64.141]:38962 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491105Ab0IXQgB (ORCPT ); Fri, 24 Sep 2010 18:36:01 +0200 Received: from localhost (c-24-16-163-131.hsd1.wa.comcast.net [24.16.163.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id 0893848B0F; Fri, 24 Sep 2010 09:35:56 -0700 (PDT) X-Mailbox-Line: From gregkh@clark.site Fri Sep 24 09:33:49 2010 Message-Id: <20100924163349.429885482@clark.site> User-Agent: quilt/0.48-11.2 Date: Fri, 24 Sep 2010 09:32:25 -0700 From: Greg KH To: linux-kernel@vger.kernel.org, stable@kernel.org Cc: stable-review@kernel.org, torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@lxorguk.ukuu.org.uk, Ben Hutchings , linux-mips@linux-mips.org, Martin Michlmayr , Aurelien Jarno , 584784@bugs.debian.org, Ralf Baechle Subject: [61/68] MIPS: Set io_map_base for several PCI bridges lacking it In-Reply-To: <20100924163357.GA15741@kroah.com> X-archive-position: 27822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19486 Content-Length: 2738 Lines: 84 2.6.32-stable review patch. If anyone has any objections, please let us know. ------------------ From: Ben Hutchings commit 8faf2e6c201d95b780cd3b4674b7a55ede6dcbbb upstream. Several MIPS platforms don't set pci_controller::io_map_base for their PCI bridges. This results in a panic in pci_iomap(). (The panic is conditional on CONFIG_PCI_DOMAINS, but that is now enabled for all PCI MIPS systems.) Signed-off-by: Ben Hutchings Cc: linux-mips@linux-mips.org Cc: Martin Michlmayr Cc: Aurelien Jarno Cc: 584784@bugs.debian.org Patchwork: https://patchwork.linux-mips.org/patch/1377/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/mti-malta/malta-pci.c | 2 ++ arch/mips/nxp/pnx8550/common/pci.c | 1 + arch/mips/nxp/pnx8550/common/setup.c | 2 +- arch/mips/pci/ops-pmcmsp.c | 1 + arch/mips/pci/pci-yosemite.c | 1 + 5 files changed, 6 insertions(+), 1 deletion(-) --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -247,6 +247,8 @@ void __init mips_pcibios_init(void) iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; + controller->io_map_base = mips_io_port_base; + register_pci_controller(controller); } --- a/arch/mips/nxp/pnx8550/common/pci.c +++ b/arch/mips/nxp/pnx8550/common/pci.c @@ -44,6 +44,7 @@ extern struct pci_ops pnx8550_pci_ops; static struct pci_controller pnx8550_controller = { .pci_ops = &pnx8550_pci_ops, + .io_map_base = PNX8550_PORT_BASE, .io_resource = &pci_io_resource, .mem_resource = &pci_mem_resource, }; --- a/arch/mips/nxp/pnx8550/common/setup.c +++ b/arch/mips/nxp/pnx8550/common/setup.c @@ -113,7 +113,7 @@ void __init plat_mem_setup(void) PNX8550_GLB2_ENAB_INTA_O = 0; /* IO/MEM resources. */ - set_io_port_base(KSEG1); + set_io_port_base(PNX8550_PORT_BASE); ioport_resource.start = 0; ioport_resource.end = ~0; iomem_resource.start = 0; --- a/arch/mips/pci/ops-pmcmsp.c +++ b/arch/mips/pci/ops-pmcmsp.c @@ -944,6 +944,7 @@ static struct pci_controller msp_pci_con .pci_ops = &msp_pci_ops, .mem_resource = &pci_mem_resource, .mem_offset = 0, + .io_map_base = MSP_PCI_IOSPACE_BASE, .io_resource = &pci_io_resource, .io_offset = 0 }; --- a/arch/mips/pci/pci-yosemite.c +++ b/arch/mips/pci/pci-yosemite.c @@ -54,6 +54,7 @@ static int __init pmc_yosemite_setup(voi panic(ioremap_failed); set_io_port_base(io_v_base); + py_controller.io_map_base = io_v_base; TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1); ioport_resource.end = TITAN_IO_SIZE - 1; From gregkh@suse.de Fri Sep 24 18:36:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 18:36:29 +0200 (CEST) Received: from kroah.org ([198.145.64.141]:38965 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491046Ab0IXQgB (ORCPT ); Fri, 24 Sep 2010 18:36:01 +0200 Received: from localhost (c-24-16-163-131.hsd1.wa.comcast.net [24.16.163.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id C87E148B0D; Fri, 24 Sep 2010 09:35:55 -0700 (PDT) X-Mailbox-Line: From gregkh@clark.site Fri Sep 24 09:33:49 2010 Message-Id: <20100924163349.342404390@clark.site> User-Agent: quilt/0.48-11.2 Date: Fri, 24 Sep 2010 09:32:24 -0700 From: Greg KH To: linux-kernel@vger.kernel.org, stable@kernel.org, linux-mips@linux-mips.org Cc: stable-review@kernel.org, torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@lxorguk.ukuu.org.uk, David Daney , Ralf Baechle Subject: [60/68] MIPS: Quit using undefined behavior of ADDU in 64-bit atomic operations. In-Reply-To: <20100924163357.GA15741@kroah.com> X-archive-position: 27823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19488 Content-Length: 3427 Lines: 112 2.6.32-stable review patch. If anyone has any objections, please let us know. ------------------ From: David Daney commit f2a68272d799bf4092443357142f63b74f7669a1 upstream. For 64-bit, we must use DADDU and DSUBU. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1483/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/include/asm/atomic.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -434,7 +434,7 @@ static __inline__ void atomic64_add(long __asm__ __volatile__( " .set mips3 \n" "1: lld %0, %1 # atomic64_add \n" - " addu %0, %2 \n" + " daddu %0, %2 \n" " scd %0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" @@ -446,7 +446,7 @@ static __inline__ void atomic64_add(long __asm__ __volatile__( " .set mips3 \n" "1: lld %0, %1 # atomic64_add \n" - " addu %0, %2 \n" + " daddu %0, %2 \n" " scd %0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" @@ -479,7 +479,7 @@ static __inline__ void atomic64_sub(long __asm__ __volatile__( " .set mips3 \n" "1: lld %0, %1 # atomic64_sub \n" - " subu %0, %2 \n" + " dsubu %0, %2 \n" " scd %0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" @@ -491,7 +491,7 @@ static __inline__ void atomic64_sub(long __asm__ __volatile__( " .set mips3 \n" "1: lld %0, %1 # atomic64_sub \n" - " subu %0, %2 \n" + " dsubu %0, %2 \n" " scd %0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" @@ -524,10 +524,10 @@ static __inline__ long atomic64_add_retu __asm__ __volatile__( " .set mips3 \n" "1: lld %1, %2 # atomic64_add_return \n" - " addu %0, %1, %3 \n" + " daddu %0, %1, %3 \n" " scd %0, %2 \n" " beqzl %0, 1b \n" - " addu %0, %1, %3 \n" + " daddu %0, %1, %3 \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) @@ -538,10 +538,10 @@ static __inline__ long atomic64_add_retu __asm__ __volatile__( " .set mips3 \n" "1: lld %1, %2 # atomic64_add_return \n" - " addu %0, %1, %3 \n" + " daddu %0, %1, %3 \n" " scd %0, %2 \n" " beqz %0, 2f \n" - " addu %0, %1, %3 \n" + " daddu %0, %1, %3 \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" @@ -576,10 +576,10 @@ static __inline__ long atomic64_sub_retu __asm__ __volatile__( " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_return \n" - " subu %0, %1, %3 \n" + " dsubu %0, %1, %3 \n" " scd %0, %2 \n" " beqzl %0, 1b \n" - " subu %0, %1, %3 \n" + " dsubu %0, %1, %3 \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) @@ -590,10 +590,10 @@ static __inline__ long atomic64_sub_retu __asm__ __volatile__( " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_return \n" - " subu %0, %1, %3 \n" + " dsubu %0, %1, %3 \n" " scd %0, %2 \n" " beqz %0, 2f \n" - " subu %0, %1, %3 \n" + " dsubu %0, %1, %3 \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" From Andrei.Ardelean@idt.com Fri Sep 24 23:45:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 24 Sep 2010 23:45:31 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:46718 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491122Ab0IXVp2 convert rfc822-to-8bit (ORCPT ); Fri, 24 Sep 2010 23:45:28 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o8OLjKhX013172 for ; Fri, 24 Sep 2010 14:45:21 -0700 Received: from corpml3.corp.idt.com (corpml3.corp.idt.com [157.165.140.25]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o8OLjEmb012192 for ; Fri, 24 Sep 2010 14:45:15 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml3.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o8OLjCI28208 for ; Fri, 24 Sep 2010 14:45:13 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Does Linux MIPS use scratch pad ram? Date: Fri, 24 Sep 2010 14:45:11 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: Does Linux MIPS use scratch pad ram? thread-index: ActcMcOJBpiOIZoqRD+qRmrUDINcAQ== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 X-archive-position: 27824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19910 Content-Length: 492 Lines: 14 Hi, I am using MALTA platform and try to port Linux on a new platform. It seems to me that in spram.c the sprams are probed if they are available or not but I cannot see Linux really using those afterwards. My platform has no spram so I am trying to avoid this probing. The problem is that spram.c is not MALTA specific but as the comment says in spram.c there are some MALTA specific addresses. Unfortunately I have some Flash at those addresses. How to fix this issue? Thanks, Andrei From kevink@paralogos.com Sat Sep 25 01:16:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Sep 2010 01:16:42 +0200 (CEST) Received: from gateway16.websitewelcome.com ([69.93.82.10]:43630 "HELO gateway16.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491206Ab0IXXQj (ORCPT ); Sat, 25 Sep 2010 01:16:39 +0200 Received: (qmail 9254 invoked from network); 24 Sep 2010 23:16:35 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway16.websitewelcome.com with SMTP; 24 Sep 2010 23:16:35 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding; b=bY7+aiRDkdxA+9DGpQsLHa1wRkg0r7oePtrOD4GzO4YbRtSNQCdZUEa/xOLjLzkbeV9ncitkbyTpH9DaxuFCt9rME5bXmfKYUy750J3Lvc0ex6gRMfPnqM6D52gAxmMJ; Received: from [216.239.45.4] (port=2037 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1OzHVG-0000Vk-Mi; Fri, 24 Sep 2010 18:16:30 -0500 Message-ID: <4C9D3153.8020901@paralogos.com> Date: Fri, 24 Sep 2010 16:16:35 -0700 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.12) Gecko/20100915 Thunderbird/3.0.8 MIME-Version: 1.0 To: "Ardelean, Andrei" CC: linux-mips@linux-mips.org Subject: Re: Does Linux MIPS use scratch pad ram? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com X-archive-position: 27825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 19946 Content-Length: 669 Lines: 21 I find it hard to believe that you've got Flash responding in place of the CP0 cache tag registers. On 09/24/10 14:45, Ardelean, Andrei wrote: > Hi, > > I am using MALTA platform and try to port Linux on a new platform. > It seems to me that in spram.c the sprams are probed if they are > available or not but I cannot see Linux really using those afterwards. > My platform has no spram so I am trying to avoid this probing. The > problem is that spram.c is not MALTA specific but as the comment says in > spram.c there are some MALTA specific addresses. Unfortunately I have > some Flash at those addresses. > How to fix this issue? > > Thanks, > Andrei > > > From dengcheng.zhu@gmail.com Sat Sep 25 04:53:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Sep 2010 04:53:45 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:40881 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490975Ab0IYCxl (ORCPT ); Sat, 25 Sep 2010 04:53:41 +0200 Received: by qwe4 with SMTP id 4so76142qwe.36 for ; Fri, 24 Sep 2010 19:53:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=2k50RZZzSm+r2Nmcou6aEyagI7yhT71Bluuz3iVc2gI=; b=Wtr5Pv5Q5v43FzF9+Y9ibui/PTOnrsoDUoSGjFFf72DUtjiIXimtyNHFSvdpIxIn3M iVw1U/VYiqLoYKaq6bw5YUHiD4H5pisezK1hkzFwKLL0DP0WNdlGqpNoEUNaNawhT04+ DkzA9afq3o9Y7upGNkLN0AD7ZSDCVLdhijxm8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=rSny/jN/eecfJO94r/zctSKiQTme6VzuY/owUC4cM56Y5/lG6KECnsS681ZuLAIYIN wJJyhHufgNcDTG9h5ZR9ZALOXdY3mcDNs2TEptZobBxr4l3INNIhSyx35eYEsxo7nbTI K8jztYRbaIKyWMblK+4VUzs7Hy7E/edxLdY5E= MIME-Version: 1.0 Received: by 10.224.80.203 with SMTP id u11mr2998720qak.384.1285383214548; Fri, 24 Sep 2010 19:53:34 -0700 (PDT) Received: by 10.229.25.208 with HTTP; Fri, 24 Sep 2010 19:53:34 -0700 (PDT) In-Reply-To: <20100924083638.GA7503@console-pimps.org> References: <1276058130-25851-1-git-send-email-dengcheng.zhu@gmail.com> <1276058130-25851-5-git-send-email-dengcheng.zhu@gmail.com> <20100922122711.GB6392@console-pimps.org> <20100924083638.GA7503@console-pimps.org> Date: Sat, 25 Sep 2010 10:53:34 +0800 Message-ID: Subject: Re: [PATCH v6 4/7] MIPS: add support for hardware performance events (skeleton) From: Deng-Cheng Zhu To: Matt Fleming Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 20042 Content-Length: 552 Lines: 12 2010/9/24 Matt Fleming : > The potential problem with doing a cleanup patch after this series has > been merged is that it will modify most of the code in this patch > series - essentially rewriting it. I don't have a strong opinion > either way but Ralf may. [DC]: No, the situation is not that serious. The mips_pmu registration mechanism had already been implemented. You may take a look at the bottom of perf_event_mipsxx.c (patch #6). The ugly conditional code (mips_pmu_irq) could be fixed easily, I suppose. Deng-Cheng From dragos.tatulea@gmail.com Sat Sep 25 21:20:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Sep 2010 21:20:26 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:53892 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491182Ab0IYTUX (ORCPT ); Sat, 25 Sep 2010 21:20:23 +0200 Received: by iwn36 with SMTP id 36so4052135iwn.36 for ; Sat, 25 Sep 2010 12:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:from:date :message-id:subject:to:content-type; bh=gzWwSA/jANMypSfr7AomUIMcWlalqeQnv4Uep8OALLA=; b=sX5GaPjklehcIFNjPlLD6Sr57+N4d8yoNUHgMyUUl3DCN0/AfZnaH0ahvLlnzl0rDp bVlOpCXeR3SDdl624ge88Zc6C2VQnezefeVRHdEc8eretsLgI/Ky3bGSZROFzYmXRXUE alJV9PdkLP2GHWTVceqNKmMoY0CAMW+UWmq04= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type; b=gNYiJVqk327p07VJ5NSupLG6mN0i44uEr4xX3HonEnNv/mlmCK2kbA9MyxQX30dtgD HFIVKAoU3jTY4ciZ5X5AQDub6F/ml2XxMixsfkrizJThm+oaGDmx2tZzwfvZNzPJMrku SrFX4GlS5BOGnuUELsHpWZRSmAkIUBrQ2huVA= Received: by 10.231.155.7 with SMTP id q7mr6166813ibw.105.1285442421302; Sat, 25 Sep 2010 12:20:21 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.140.6 with HTTP; Sat, 25 Sep 2010 12:20:01 -0700 (PDT) From: Dragos Tatulea Date: Sat, 25 Sep 2010 21:20:01 +0200 Message-ID: Subject: [PATCH] Fix MIPS math-emu -Werror compile failure encountered while doing a Malta build. To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27827 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dragos.tatulea@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 20301 Content-Length: 630 Lines: 21 Signed-off-by: Dragos Tatulea --- arch/mips/math-emu/cp1emu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 47842b7..c0af7f1 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -1243,7 +1243,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu) { unsigned long oldepc, prevepc; - mips_instruction insn; + mips_instruction uninitialized_var(insn); int sig = 0; oldepc = xcp->cp0_epc; -- 1.7.2.3 From dragos.tatulea@gmail.com Sat Sep 25 21:20:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 25 Sep 2010 21:20:50 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:53892 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491754Ab0IYTU0 (ORCPT ); Sat, 25 Sep 2010 21:20:26 +0200 Received: by mail-iw0-f177.google.com with SMTP id 36so4052135iwn.36 for ; Sat, 25 Sep 2010 12:20:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:from:date :message-id:subject:to:content-type; bh=CasjPLKHNM4aBvIKKMAy9zCFE5fE1mF9t+/3ebz+F4M=; b=Pq3q27l6W3r8mLCZzO6eWG0hj+1GhLfE4DMAUPpUMw47iaym8LNZNDKISMA296FYUo SZQYNFNoE7gFYaz6DdFvupfyZB47SFhxlI7O6L4idx9DXhtiSgd+JWUIiYC0uehd1BE1 mXhlK9tXXQoDl7ST1pbYMWQeS3ITjDpgqTk8M= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type; b=vejG9YQPdMTjtQuzWhEAA8EVu2Xz+eUVeULCmrzS5kSXy9Yi2GFWE9FcVxYlN6KLdI IHuG7DBxvPmyhsDf7XwACmEAeext9dQKQRYR9mUc5MtS4phVsoD/R+BQwQxpJxG5hLWU Jitqbf6orEDUm292eqr7XgGG+5WCnsaIaBzPk= Received: by 10.231.157.11 with SMTP id z11mr6008882ibw.147.1285442425756; Sat, 25 Sep 2010 12:20:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.140.6 with HTTP; Sat, 25 Sep 2010 12:20:05 -0700 (PDT) From: Dragos Tatulea Date: Sat, 25 Sep 2010 21:20:05 +0200 Message-ID: Subject: [PATCH] Fix oprofile -Werror compile failure encountered while doing a MIPS Malta build. To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dragos.tatulea@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 20304 Content-Length: 633 Lines: 20 Signed-off-by: Dragos Tatulea --- drivers/oprofile/buffer_sync.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/oprofile/buffer_sync.c b/drivers/oprofile/buffer_sync.c index b7e755f..a832644 100644 --- a/drivers/oprofile/buffer_sync.c +++ b/drivers/oprofile/buffer_sync.c @@ -500,7 +500,7 @@ void sync_buffer(int cpu) { struct mm_struct *mm = NULL; struct mm_struct *oldmm; - unsigned long val; + unsigned long uninitialized_var(val); struct task_struct *new; unsigned long cookie = 0; int in_kernel = 1; -- 1.7.2.3 From fujita.tomonori@lab.ntt.co.jp Mon Sep 27 07:21:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 27 Sep 2010 07:21:20 +0200 (CEST) Received: from sh.osrg.net ([192.16.179.4]:51468 "EHLO sh.osrg.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491041Ab0I0FVR (ORCPT ); Mon, 27 Sep 2010 07:21:17 +0200 Received: from localhost (rose.osrg.net [10.76.0.1]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o8R5KGUP026873; Mon, 27 Sep 2010 14:20:16 +0900 Date: Mon, 27 Sep 2010 14:20:16 +0900 To: ddaney@caviumnetworks.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, akpm@linux-foundation.org, fujita.tomonori@lab.ntt.co.jp, konrad.wilk@oracle.com, mingo@elte.hu, andre.goddard@gmail.com Subject: Re: [PATCH 7/9] swiotlb: Make bounce buffer bounds non-static. From: FUJITA Tomonori In-Reply-To: <1285282051-24907-2-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> <1285282051-24907-2-git-send-email-ddaney@caviumnetworks.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-Id: <20100927141616S.fujita.tomonori@lab.ntt.co.jp> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Mon, 27 Sep 2010 14:20:21 +0900 (JST) X-Virus-Scanned: clamav-milter 0.96.1 at sh X-Virus-Status: Clean X-archive-position: 27829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fujita.tomonori@lab.ntt.co.jp Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 20853 Content-Length: 249 Lines: 7 On Thu, 23 Sep 2010 15:47:31 -0700 David Daney wrote: > Octeon PCI mapping has to be established to cover the bounce buffers, > so it has to have access to the bounds. Why can't you use swiotlb_init_with_tbl() instead? From fujita.tomonori@lab.ntt.co.jp Mon Sep 27 07:30:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 27 Sep 2010 07:30:55 +0200 (CEST) Received: from sh.osrg.net ([192.16.179.4]:35700 "EHLO sh.osrg.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491041Ab0I0Faw (ORCPT ); Mon, 27 Sep 2010 07:30:52 +0200 Received: from localhost (rose.osrg.net [10.76.0.1]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o8R5UjZE026935; Mon, 27 Sep 2010 14:30:45 +0900 Date: Mon, 27 Sep 2010 14:30:45 +0900 To: ddaney@caviumnetworks.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/9] MIPS: Convert DMA to use dma-mapping-common.h From: FUJITA Tomonori In-Reply-To: <1285281496-24696-6-git-send-email-ddaney@caviumnetworks.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> <1285281496-24696-6-git-send-email-ddaney@caviumnetworks.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-Id: <20100927142628X.fujita.tomonori@lab.ntt.co.jp> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Mon, 27 Sep 2010 14:30:46 +0900 (JST) X-Virus-Scanned: clamav-milter 0.96.1 at sh X-Virus-Status: Clean X-archive-position: 27830 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fujita.tomonori@lab.ntt.co.jp Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 20861 Content-Length: 2785 Lines: 79 On Thu, 23 Sep 2010 15:38:12 -0700 David Daney wrote: > Use asm-generic/dma-mapping-common.h to handle all DMA mapping > operations and establish a default get_dma_ops() that forwards all > operations to the existing code. > > Augment dev_archdata to carry a pointer to the struct dma_map_ops, > allowing DMA operations to be overridden on a per device basis. > Currently this is never filled in, so the default dma_map_ops are > used. A follow-on patch sets this for Octeon PCI devices. > > Also initialize the dma_debug system as it is now used if it is > configured. > > Signed-off-by: David Daney > --- > arch/mips/Kconfig | 2 + > arch/mips/include/asm/device.h | 15 +++- > arch/mips/include/asm/dma-mapping.h | 125 +++++++++++++++++-------- > arch/mips/mm/dma-default.c | 179 +++++++++++++--------------------- > 4 files changed, 172 insertions(+), 149 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 6c33709..e68b89f 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -14,6 +14,8 @@ config MIPS > select HAVE_KRETPROBES > select RTC_LIB if !MACH_LOONGSON > select GENERIC_ATOMIC64 if !64BIT > + select HAVE_DMA_ATTRS > + select HAVE_DMA_API_DEBUG > > mainmenu "Linux/MIPS Kernel Configuration" > > diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h > index 06746c5..65bf274 100644 > --- a/arch/mips/include/asm/device.h > +++ b/arch/mips/include/asm/device.h > @@ -3,4 +3,17 @@ > * > * This file is released under the GPLv2 > */ > -#include > +#ifndef _ASM_MIPS_DEVICE_H > +#define _ASM_MIPS_DEVICE_H > + > +struct mips_dma_map_ops; > + > +struct dev_archdata { > + /* DMA operations on that device */ > + struct mips_dma_map_ops *dma_ops; > +}; > + > +struct pdev_archdata { > +}; > + > +#endif /* _ASM_MIPS_DEVICE_H*/ > diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h > index 18fbf7a..9a4c307 100644 > --- a/arch/mips/include/asm/dma-mapping.h > +++ b/arch/mips/include/asm/dma-mapping.h > @@ -5,51 +5,67 @@ > #include > #include > > -void *dma_alloc_noncoherent(struct device *dev, size_t size, > - dma_addr_t *dma_handle, gfp_t flag); > +struct mips_dma_map_ops { > + struct dma_map_ops dma_map_ops; > + dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr); > + phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr); > +}; The above code doesn't look great but we don't want to add phys_to_dma and dma_to_phys to dma_map_ops struct, and these functions on MIPS looks too complicated for ifdef. So I guess that we need to live with the above code. From Andrei.Ardelean@idt.com Mon Sep 27 16:00:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 27 Sep 2010 16:00:46 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:42601 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491919Ab0I0OAn convert rfc822-to-8bit (ORCPT ); Mon, 27 Sep 2010 16:00:43 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o8RE0YGr005593; Mon, 27 Sep 2010 07:00:35 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o8RE0XB9010087; Mon, 27 Sep 2010 07:00:33 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o8RE0WQ26568; Mon, 27 Sep 2010 07:00:32 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: Does Linux MIPS use scratch pad ram? Date: Mon, 27 Sep 2010 07:00:30 -0700 Message-ID: In-Reply-To: <4C9D3153.8020901@paralogos.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: Does Linux MIPS use scratch pad ram? thread-index: ActcPwdQCurd/eumR6WDFFf2IEYQcgCDJpCQ References: <4C9D3153.8020901@paralogos.com> From: "Ardelean, Andrei" To: "Kevin D. Kissell" Cc: X-Scanned-By: MIMEDefang 2.43 X-archive-position: 27831 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 21271 Content-Length: 1247 Lines: 41 Hi Kevin, I don't have the new h/w yet so I don't know how the Flash will react. In the mem map of the new board I see Flash at 0x1c000000 where MALTA Linux probes for spram and my job so far is to port Linux for the new board. So, I understand from your email that spram probing will not mess up with my Flash and I should ignore it. Thanks, Andrei -----Original Message----- From: Kevin D. Kissell [mailto:kevink@paralogos.com] Sent: Friday, September 24, 2010 7:17 PM To: Ardelean, Andrei Cc: linux-mips@linux-mips.org Subject: Re: Does Linux MIPS use scratch pad ram? I find it hard to believe that you've got Flash responding in place of the CP0 cache tag registers. On 09/24/10 14:45, Ardelean, Andrei wrote: > Hi, > > I am using MALTA platform and try to port Linux on a new platform. > It seems to me that in spram.c the sprams are probed if they are > available or not but I cannot see Linux really using those afterwards. > My platform has no spram so I am trying to avoid this probing. The > problem is that spram.c is not MALTA specific but as the comment says in > spram.c there are some MALTA specific addresses. Unfortunately I have > some Flash at those addresses. > How to fix this issue? > > Thanks, > Andrei > > > From konrad.wilk@oracle.com Mon Sep 27 18:54:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 27 Sep 2010 18:54:47 +0200 (CEST) Received: from rcsinet10.oracle.com ([148.87.113.121]:33982 "EHLO rcsinet10.oracle.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491196Ab0I0Qyn (ORCPT >); Mon, 27 Sep 2010 18:54:43 +0200 Received: from acsinet15.oracle.com (acsinet15.oracle.com [141.146.126.227]) by rcsinet10.oracle.com (Switch-3.4.2/Switch-3.4.2) with ESMTP id o8RGs20m019513 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 27 Sep 2010 16:54:03 GMT Received: from acsmt355.oracle.com (acsmt355.oracle.com [141.146.40.155]) by acsinet15.oracle.com (Switch-3.4.2/Switch-3.4.1) with ESMTP id o8QNLL7F024019; Mon, 27 Sep 2010 16:54:00 GMT Received: from abhmt013.oracle.com by acsmt355.oracle.com with ESMTP id 633788711285606431; Mon, 27 Sep 2010 09:53:51 -0700 Received: from phenom (/209.6.55.207) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Mon, 27 Sep 2010 09:53:46 -0700 Received: by phenom (Postfix, from userid 1000) id 9F74D1E66; Mon, 27 Sep 2010 12:53:40 -0400 (EDT) Date: Mon, 27 Sep 2010 12:53:40 -0400 From: Konrad Rzeszutek Wilk To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton , FUJITA Tomonori , Ingo Molnar , Andre Goddard Rosa Subject: Re: [PATCH 6/9] swiotlb: Declare swiotlb_init_with_default_size() Message-ID: <20100927165340.GA5644@dumpdata.com> References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> <1285282051-24907-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1285282051-24907-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 27832 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: konrad.wilk@oracle.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 21437 Content-Length: 1085 Lines: 26 On Thu, Sep 23, 2010 at 03:47:30PM -0700, David Daney wrote: > It comes from swiotlb.c and must be called by external code, so declare it. > > Signed-off-by: David Daney > Cc: Andrew Morton > Cc: FUJITA Tomonori > Cc: Konrad Rzeszutek Wilk > Cc: Ingo Molnar > Cc: Andre Goddard Rosa > --- > include/linux/swiotlb.h | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h > index 8c0e349..dba51fe 100644 > --- a/include/linux/swiotlb.h > +++ b/include/linux/swiotlb.h > @@ -23,6 +23,7 @@ extern int swiotlb_force; > #define IO_TLB_SHIFT 11 > > extern void swiotlb_init(int verbose); > +extern void swiotlb_init_with_default_size(size_t, int); > extern void swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose); Just use the swiotlb_init_with_tbl. If you need an example of how it is utilized, take a look at how swiotlb-xen.c does it. From ddaney@caviumnetworks.com Mon Sep 27 19:35:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 27 Sep 2010 19:35:21 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4030 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491931Ab0I0RfS (ORCPT ); Mon, 27 Sep 2010 19:35:18 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 27 Sep 2010 10:35:49 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 27 Sep 2010 10:35:15 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 27 Sep 2010 10:35:15 -0700 Message-ID: <4CA0D5D3.3040700@caviumnetworks.com> Date: Mon, 27 Sep 2010 10:35:15 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: FUJITA Tomonori CC: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/9] MIPS: Convert DMA to use dma-mapping-common.h References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> <1285281496-24696-6-git-send-email-ddaney@caviumnetworks.com> <20100927142628X.fujita.tomonori@lab.ntt.co.jp> In-Reply-To: <20100927142628X.fujita.tomonori@lab.ntt.co.jp> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 27 Sep 2010 17:35:15.0241 (UTC) FILETIME=[585FD190:01CB5E6A] X-archive-position: 27833 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 21474 Content-Length: 3127 Lines: 88 On 09/26/2010 10:30 PM, FUJITA Tomonori wrote: > On Thu, 23 Sep 2010 15:38:12 -0700 > David Daney wrote: > >> Use asm-generic/dma-mapping-common.h to handle all DMA mapping >> operations and establish a default get_dma_ops() that forwards all >> operations to the existing code. >> >> Augment dev_archdata to carry a pointer to the struct dma_map_ops, >> allowing DMA operations to be overridden on a per device basis. >> Currently this is never filled in, so the default dma_map_ops are >> used. A follow-on patch sets this for Octeon PCI devices. >> >> Also initialize the dma_debug system as it is now used if it is >> configured. >> >> Signed-off-by: David Daney >> --- >> arch/mips/Kconfig | 2 + >> arch/mips/include/asm/device.h | 15 +++- >> arch/mips/include/asm/dma-mapping.h | 125 +++++++++++++++++-------- >> arch/mips/mm/dma-default.c | 179 +++++++++++++--------------------- >> 4 files changed, 172 insertions(+), 149 deletions(-) >> >> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig >> index 6c33709..e68b89f 100644 >> --- a/arch/mips/Kconfig >> +++ b/arch/mips/Kconfig >> @@ -14,6 +14,8 @@ config MIPS >> select HAVE_KRETPROBES >> select RTC_LIB if !MACH_LOONGSON >> select GENERIC_ATOMIC64 if !64BIT >> + select HAVE_DMA_ATTRS >> + select HAVE_DMA_API_DEBUG >> >> mainmenu "Linux/MIPS Kernel Configuration" >> >> diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h >> index 06746c5..65bf274 100644 >> --- a/arch/mips/include/asm/device.h >> +++ b/arch/mips/include/asm/device.h >> @@ -3,4 +3,17 @@ >> * >> * This file is released under the GPLv2 >> */ >> -#include >> +#ifndef _ASM_MIPS_DEVICE_H >> +#define _ASM_MIPS_DEVICE_H >> + >> +struct mips_dma_map_ops; >> + >> +struct dev_archdata { >> + /* DMA operations on that device */ >> + struct mips_dma_map_ops *dma_ops; >> +}; >> + >> +struct pdev_archdata { >> +}; >> + >> +#endif /* _ASM_MIPS_DEVICE_H*/ >> diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h >> index 18fbf7a..9a4c307 100644 >> --- a/arch/mips/include/asm/dma-mapping.h >> +++ b/arch/mips/include/asm/dma-mapping.h >> @@ -5,51 +5,67 @@ >> #include >> #include >> >> -void *dma_alloc_noncoherent(struct device *dev, size_t size, >> - dma_addr_t *dma_handle, gfp_t flag); >> +struct mips_dma_map_ops { >> + struct dma_map_ops dma_map_ops; >> + dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr); >> + phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr); >> +}; > > The above code doesn't look great but we don't want to add phys_to_dma > and dma_to_phys to dma_map_ops struct, and these functions on MIPS > looks too complicated for ifdef. So I guess that we need to live with > the above code. > I think you have a point here. I will attempt to move these two into a chip specific operations vector, and leave the more generic MIPS version with the simplified static definition. Thanks, David Daney From ddaney@caviumnetworks.com Mon Sep 27 19:39:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 27 Sep 2010 19:39:24 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4173 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491931Ab0I0RjV (ORCPT ); Mon, 27 Sep 2010 19:39:21 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 27 Sep 2010 10:39:52 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 27 Sep 2010 10:39:18 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 27 Sep 2010 10:39:18 -0700 Message-ID: <4CA0D6C2.7030901@caviumnetworks.com> Date: Mon, 27 Sep 2010 10:39:14 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: FUJITA Tomonori CC: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, akpm@linux-foundation.org, konrad.wilk@oracle.com, mingo@elte.hu, andre.goddard@gmail.com, konrad.wilk@oracle.com Subject: Re: [PATCH 7/9] swiotlb: Make bounce buffer bounds non-static. References: <1285281496-24696-1-git-send-email-ddaney@caviumnetworks.com> <1285282051-24907-2-git-send-email-ddaney@caviumnetworks.com> <20100927141616S.fujita.tomonori@lab.ntt.co.jp> In-Reply-To: <20100927141616S.fujita.tomonori@lab.ntt.co.jp> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 27 Sep 2010 17:39:18.0510 (UTC) FILETIME=[E95FB8E0:01CB5E6A] X-archive-position: 27834 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 21482 Content-Length: 668 Lines: 20 On 09/26/2010 10:20 PM, FUJITA Tomonori wrote: > On Thu, 23 Sep 2010 15:47:31 -0700 > David Daney wrote: > >> Octeon PCI mapping has to be established to cover the bounce buffers, >> so it has to have access to the bounds. > > Why can't you use swiotlb_init_with_tbl() instead? > Yes, as pointed out be several people, that would be better. The swiotlb_init_with_tbl() didn't exist in earlier kernel versions and this simplification was missed when I forward ported the patch set. By using this function, I think the entire patch set will be MIPS specific, making it unnecessary to touch the generic swiotlb code. Thanks, David Daney From fujita.tomonori@lab.ntt.co.jp Tue Sep 28 02:12:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 02:12:28 +0200 (CEST) Received: from sh.osrg.net ([192.16.179.4]:60388 "EHLO sh.osrg.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491938Ab0I1AMZ (ORCPT ); Tue, 28 Sep 2010 02:12:25 +0200 Received: from localhost (rose.osrg.net [10.76.0.1]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o8S0CHWQ001323; Tue, 28 Sep 2010 09:12:17 +0900 Date: Tue, 28 Sep 2010 09:12:17 +0900 To: ddaney@caviumnetworks.com Cc: fujita.tomonori@lab.ntt.co.jp, linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/9] MIPS: Convert DMA to use dma-mapping-common.h From: FUJITA Tomonori In-Reply-To: <4CA0D5D3.3040700@caviumnetworks.com> References: <1285281496-24696-6-git-send-email-ddaney@caviumnetworks.com> <20100927142628X.fujita.tomonori@lab.ntt.co.jp> <4CA0D5D3.3040700@caviumnetworks.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-Id: <20100928090805M.fujita.tomonori@lab.ntt.co.jp> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Tue, 28 Sep 2010 09:12:18 +0900 (JST) X-Virus-Scanned: clamav-milter 0.96.1 at sh X-Virus-Status: Clean X-archive-position: 27835 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fujita.tomonori@lab.ntt.co.jp Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 21846 Content-Length: 1238 Lines: 30 On Mon, 27 Sep 2010 10:35:15 -0700 David Daney wrote: > >> diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h > >> index 18fbf7a..9a4c307 100644 > >> --- a/arch/mips/include/asm/dma-mapping.h > >> +++ b/arch/mips/include/asm/dma-mapping.h > >> @@ -5,51 +5,67 @@ > >> #include > >> #include > >> > >> -void *dma_alloc_noncoherent(struct device *dev, size_t size, > >> - dma_addr_t *dma_handle, gfp_t flag); > >> +struct mips_dma_map_ops { > >> + struct dma_map_ops dma_map_ops; > >> + dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr); > >> + phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr); > >> +}; > > > > The above code doesn't look great but we don't want to add phys_to_dma > > and dma_to_phys to dma_map_ops struct, and these functions on MIPS > > looks too complicated for ifdef. So I guess that we need to live with > > the above code. > > > > I think you have a point here. I will attempt to move these two into a > chip specific operations vector, and leave the more generic MIPS version > with the simplified static definition. Yeah, that sounds a better (cleaner) approach. From arun.murthy@stericsson.com Tue Sep 28 09:44:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 09:44:41 +0200 (CEST) Received: from eu1sys200aog102.obsmtp.com ([207.126.144.113]:50180 "EHLO eu1sys200aog102.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1Hoh (ORCPT ); Tue, 28 Sep 2010 09:44:37 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob102.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGcdbo/8jY49Fh3etmfNaoWIPZ/Arit@postini.com; Tue, 28 Sep 2010 07:44:37 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5376C88; Tue, 28 Sep 2010 07:41:09 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 05EA6194D; Tue, 28 Sep 2010 07:41:00 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 2FC19A809E; Tue, 28 Sep 2010 09:40:52 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 09:40:55 +0200 From: Arun Murthy To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Cc: , , , , , Subject: [PATCHv2 0/7] PWM core driver for pwm based led and backlight driver Date: Tue, 28 Sep 2010 13:10:41 +0530 Message-ID: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27836 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22112 Content-Length: 3450 Lines: 70 The series of patch add a new pwm core driver. Align the existing pwm drivers to make use of the pwm core driver. Arun Murthy (7): pwm: Add pwm core driver backlight:pwm: add an element 'name' to platform data leds: pwm: add a new element 'name' to platform data pwm: Align existing pwm drivers with pwm-core driver platform: Update the pwm based led and backlight platform data pwm: move existing pwm driver to drivers/pwm pwm: Modify backlight and led Kconfig aligning to pwm core arch/arm/mach-pxa/cm-x300.c | 1 + arch/arm/mach-pxa/colibri-pxa270-income.c | 1 + arch/arm/mach-pxa/ezx.c | 1 + arch/arm/mach-pxa/hx4700.c | 1 + arch/arm/mach-pxa/lpd270.c | 1 + arch/arm/mach-pxa/magician.c | 1 + arch/arm/mach-pxa/mainstone.c | 1 + arch/arm/mach-pxa/mioa701.c | 1 + arch/arm/mach-pxa/palm27x.c | 1 + arch/arm/mach-pxa/palmtc.c | 1 + arch/arm/mach-pxa/palmte2.c | 1 + arch/arm/mach-pxa/pcm990-baseboard.c | 1 + arch/arm/mach-pxa/raumfeld.c | 1 + arch/arm/mach-pxa/tavorevb.c | 2 + arch/arm/mach-pxa/viper.c | 1 + arch/arm/mach-pxa/z2.c | 2 + arch/arm/mach-pxa/zylonite.c | 1 + arch/arm/mach-s3c2410/mach-h1940.c | 1 + arch/arm/mach-s3c2440/mach-rx1950.c | 1 + arch/arm/mach-s3c64xx/mach-hmt.c | 1 + arch/arm/mach-s3c64xx/mach-smartq.c | 1 + arch/arm/plat-mxc/pwm.c | 166 +++++++++------------ arch/arm/plat-pxa/pwm.c | 210 ++++++++++++-------------- arch/arm/plat-samsung/pwm.c | 235 +++++++++++++---------------- arch/mips/jz4740/pwm.c | 2 +- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/leds/Kconfig | 2 +- drivers/leds/leds-pwm.c | 4 +- drivers/mfd/Kconfig | 9 - drivers/mfd/Makefile | 1 - drivers/mfd/twl-core.c | 13 ++ drivers/mfd/twl6030-pwm.c | 163 -------------------- drivers/misc/Kconfig | 9 - drivers/misc/Makefile | 1 - drivers/misc/ab8500-pwm.c | 168 -------------------- drivers/pwm/Kconfig | 33 ++++ drivers/pwm/Makefile | 4 + drivers/pwm/pwm-ab8500.c | 157 +++++++++++++++++++ drivers/pwm/pwm-core.c | 124 +++++++++++++++ drivers/pwm/pwm-twl6040.c | 196 ++++++++++++++++++++++++ drivers/video/backlight/Kconfig | 2 +- drivers/video/backlight/pwm_bl.c | 4 +- include/linux/leds_pwm.h | 1 + include/linux/pwm.h | 29 ++++- include/linux/pwm_backlight.h | 1 + 46 files changed, 864 insertions(+), 696 deletions(-) delete mode 100644 drivers/mfd/twl6030-pwm.c delete mode 100644 drivers/misc/ab8500-pwm.c create mode 100644 drivers/pwm/Kconfig create mode 100644 drivers/pwm/Makefile create mode 100644 drivers/pwm/pwm-ab8500.c create mode 100644 drivers/pwm/pwm-core.c create mode 100644 drivers/pwm/pwm-twl6040.c -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 09:44:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 09:45:06 +0200 (CEST) Received: from eu1sys200aog113.obsmtp.com ([207.126.144.135]:50912 "EHLO eu1sys200aog113.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491944Ab0I1Hoi (ORCPT ); Tue, 28 Sep 2010 09:44:38 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob113.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGcdbo/8jY49Fh3etmfNaoWIPZ/Arit@postini.com; Tue, 28 Sep 2010 07:44:38 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 121457F; Tue, 28 Sep 2010 07:41:28 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7E8BB1956; Tue, 28 Sep 2010 07:41:20 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 43C2624C2F6; Tue, 28 Sep 2010 09:41:12 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 09:41:15 +0200 From: Arun Murthy To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Cc: , , , , , Subject: [PATCH 5/7] platform: Update the pwm based led and backlight platform data Date: Tue, 28 Sep 2010 13:10:46 +0530 Message-ID: <1285659648-21409-6-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27837 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22113 Content-Length: 11534 Lines: 300 mxc-pwm: Update the platform data with pwm name for backlight s3c24xx-pwm: update platform data for backlight with pwm name Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- arch/arm/mach-pxa/cm-x300.c | 1 + arch/arm/mach-pxa/colibri-pxa270-income.c | 1 + arch/arm/mach-pxa/ezx.c | 1 + arch/arm/mach-pxa/hx4700.c | 1 + arch/arm/mach-pxa/lpd270.c | 1 + arch/arm/mach-pxa/magician.c | 1 + arch/arm/mach-pxa/mainstone.c | 1 + arch/arm/mach-pxa/mioa701.c | 1 + arch/arm/mach-pxa/palm27x.c | 1 + arch/arm/mach-pxa/palmtc.c | 1 + arch/arm/mach-pxa/palmte2.c | 1 + arch/arm/mach-pxa/pcm990-baseboard.c | 1 + arch/arm/mach-pxa/raumfeld.c | 1 + arch/arm/mach-pxa/tavorevb.c | 2 ++ arch/arm/mach-pxa/viper.c | 1 + arch/arm/mach-pxa/z2.c | 2 ++ arch/arm/mach-pxa/zylonite.c | 1 + arch/arm/mach-s3c2410/mach-h1940.c | 1 + arch/arm/mach-s3c2440/mach-rx1950.c | 1 + arch/arm/mach-s3c64xx/mach-hmt.c | 1 + arch/arm/mach-s3c64xx/mach-smartq.c | 1 + 21 files changed, 23 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index c70e6c2..ddf763b 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -301,6 +301,7 @@ static inline void cm_x300_init_lcd(void) {} #if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) static struct platform_pwm_backlight_data cm_x300_backlight_data = { .pwm_id = 2, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 10000, diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index 37f0f3e..d5b5874 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -234,6 +234,7 @@ static inline void income_lcd_init(void) {} #if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM__MODULE) static struct platform_pwm_backlight_data income_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 0x3ff, .dft_brightness = 0x1ff, .pwm_period_ns = 1000000, diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 626c82b..747f217 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -49,6 +49,7 @@ static struct platform_pwm_backlight_data ezx_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 848c861..8e4905a 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -565,6 +565,7 @@ static struct platform_device hx4700_lcd = { static struct platform_pwm_backlight_data backlight_data = { .pwm_id = 1, + .name = "pxa25x-pwm", .max_brightness = 200, .dft_brightness = 100, .pwm_period_ns = 30923, diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index d279507..91efade 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -273,6 +273,7 @@ static struct platform_device lpd270_flash_device[2] = { static struct platform_pwm_backlight_data lpd270_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 1, .dft_brightness = 1, .pwm_period_ns = 78770, diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index e81dd0c..bb657a4 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -382,6 +382,7 @@ static void magician_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 272, .dft_brightness = 100, .pwm_period_ns = 30923, diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 5543c64..cbd359c 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -342,6 +342,7 @@ static struct platform_device mst_flash_device[2] = { #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static struct platform_pwm_backlight_data mainstone_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index dc66942..e442088 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -224,6 +224,7 @@ static void mio_gpio_free(struct gpio_ress *gpios, int size) /* LCD Screen and Backlight */ static struct platform_pwm_backlight_data mioa701_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 50, .pwm_period_ns = 4000 * 1024, /* Fl = 250kHz */ diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c index 77ad6d3..46677a4 100644 --- a/arch/arm/mach-pxa/palm27x.c +++ b/arch/arm/mach-pxa/palm27x.c @@ -321,6 +321,7 @@ static void palm27x_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data palm27x_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 0xfe, .dft_brightness = 0x7e, .pwm_period_ns = 3500, diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index ce1104d..385a0b5 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -180,6 +180,7 @@ static void palmtc_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data palmtc_backlight_data = { .pwm_id = 1, + .name = "pxa25x-pwm", .max_brightness = PALMTC_MAX_INTENSITY, .dft_brightness = PALMTC_MAX_INTENSITY, .pwm_period_ns = PALMTC_PERIOD_NS, diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 93c11a0..b7e95f4 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -177,6 +177,7 @@ static void palmte2_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data palmte2_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = PALMTE2_MAX_INTENSITY, .dft_brightness = PALMTE2_MAX_INTENSITY, .pwm_period_ns = PALMTE2_PERIOD_NS, diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index f56ae10..29c7e88 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -138,6 +138,7 @@ static struct pxafb_mach_info pcm990_fbinfo __initdata = { static struct platform_pwm_backlight_data pcm990_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 67e04f4..98dc2e3 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -535,6 +535,7 @@ static void __init raumfeld_w1_init(void) /* PWM controlled backlight */ static struct platform_pwm_backlight_data raumfeld_pwm_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, /* 10000 ns = 10 ms ^= 100 kHz */ diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index f02dcb5..3164de8 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -168,6 +168,7 @@ static struct platform_pwm_backlight_data tavorevb_backlight_data[] = { [0] = { /* primary backlight */ .pwm_id = 2, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 100000, @@ -175,6 +176,7 @@ static struct platform_pwm_backlight_data tavorevb_backlight_data[] = { [1] = { /* secondary backlight */ .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 100000, diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index e90114a..fdb768c 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -397,6 +397,7 @@ static void viper_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data viper_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 1000000, diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index f0d0228..bb3d821 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -204,6 +204,7 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { [0] = { /* Keypad Backlight */ .pwm_id = 1, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 512, .pwm_period_ns = 1260320, @@ -211,6 +212,7 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { [1] = { /* LCD Backlight */ .pwm_id = 2, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 512, .pwm_period_ns = 1260320, diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 5ba9d99..29492bf 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -122,6 +122,7 @@ static inline void zylonite_init_leds(void) {} #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static struct platform_pwm_backlight_data zylonite_backlight_data = { .pwm_id = 3, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 10000, diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 3ba3bab..357342f 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -224,6 +224,7 @@ static void h1940_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data backlight_data = { .pwm_id = 0, + .name = "s3c24xx-pwm", .max_brightness = 100, .dft_brightness = 50, /* tcnt = 0x31 */ diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 142d1f9..6d993de 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -291,6 +291,7 @@ static int rx1950_backlight_notify(struct device *dev, int brightness) static struct platform_pwm_backlight_data rx1950_backlight_data = { .pwm_id = 0, + .name = "s3c24xx-pwm", .max_brightness = 24, .dft_brightness = 4, .pwm_period_ns = 48000, diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index fba9022..14e9011 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -109,6 +109,7 @@ static void hmt_bl_exit(struct device *dev) static struct platform_pwm_backlight_data hmt_backlight_data = { .pwm_id = 1, + .name = "s3c24xx-pwm", .max_brightness = 100 * 256, .dft_brightness = 40 * 256, .pwm_period_ns = 1000000000 / (100 * 256 * 20), diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index cb1ebeb..20999d5 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -145,6 +145,7 @@ static int smartq_bl_init(struct device *dev) static struct platform_pwm_backlight_data smartq_backlight_data = { .pwm_id = 1, + .name = "s3c24xx-pwm", .max_brightness = 1000, .dft_brightness = 600, .pwm_period_ns = 1000000000 / (1000 * 20), -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 09:44:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 09:45:32 +0200 (CEST) Received: from eu1sys200aog104.obsmtp.com ([207.126.144.117]:40159 "EHLO eu1sys200aog104.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491947Ab0I1Hoi (ORCPT ); Tue, 28 Sep 2010 09:44:38 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob104.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGcdlUkMtiotuJ/PcE8HFK9GNKqeWE7@postini.com; Tue, 28 Sep 2010 07:44:38 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4DA008B; Tue, 28 Sep 2010 07:41:24 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AAF8A1926; Tue, 28 Sep 2010 07:41:19 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 9DA54A8065; Tue, 28 Sep 2010 09:41:08 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 09:41:11 +0200 From: Arun Murthy To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Cc: , , , , , Subject: [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core driver Date: Tue, 28 Sep 2010 13:10:45 +0530 Message-ID: <1285659648-21409-5-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27838 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22114 Content-Length: 39085 Lines: 1533 pwm-core: make the driver visible for ARM only Align ab8500 pwm with the pwm core driver Align twl6030 pwm driver with pwm core driver Align Freescale mxc pwm driver with pwm core driver Align pxa pwm driver with pwm core driver Align samsung(s3c) pwm driver with pwm core driver mips-jz4740: pwm: Align with new pwm core driver PWM core driver has been added and has been enabled only for ARM platform. The same can be utilised for mips also. Please align with the pwm core driver(drivers/pwm-core.c). Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- arch/arm/plat-mxc/pwm.c | 166 +++++++++++++----------------- arch/arm/plat-pxa/pwm.c | 210 ++++++++++++++++++-------------------- arch/arm/plat-samsung/pwm.c | 235 +++++++++++++++++++------------------------ arch/mips/jz4740/pwm.c | 2 +- drivers/mfd/twl-core.c | 13 +++ drivers/mfd/twl6030-pwm.c | 111 +++++++++++++------- drivers/misc/ab8500-pwm.c | 87 +++++++--------- drivers/pwm/Kconfig | 1 + drivers/pwm/pwm-core.c | 9 +-- include/linux/pwm.h | 21 ++++- 10 files changed, 418 insertions(+), 437 deletions(-) diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index c36f263..b259ba9 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -38,22 +38,16 @@ -struct pwm_device { - struct list_head node; - struct platform_device *pdev; - - const char *label; +struct mxc_pwm_device { struct clk *clk; - int clk_enabled; void __iomem *mmio_base; - - unsigned int use_count; - unsigned int pwm_id; }; -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +static int mxc_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { + struct mxc_pwm_device *mxc_pwm = pwm->data; + if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; @@ -62,7 +56,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) unsigned long period_cycles, duty_cycles, prescale; u32 cr; - c = clk_get_rate(pwm->clk); + c = clk_get_rate(mxc_pwm->clk); c = c * period_ns; do_div(c, 1000000000); period_cycles = c; @@ -74,8 +68,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) do_div(c, period_ns); duty_cycles = c; - writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); - writel(period_cycles, pwm->mmio_base + MX3_PWMPR); + writel(duty_cycles, mxc_pwm->mmio_base + MX3_PWMSAR); + writel(period_cycles, mxc_pwm->mmio_base + MX3_PWMPR); cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN; @@ -84,7 +78,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) else cr |= MX3_PWMCR_CLKSRC_IPG_HIGH; - writel(cr, pwm->mmio_base + MX3_PWMCR); + writel(cr, mxc_pwm->mmio_base + MX3_PWMCR); } else if (cpu_is_mx1() || cpu_is_mx21()) { /* The PWM subsystem allows for exact frequencies. However, * I cannot connect a scope on my device to the PWM line and @@ -102,110 +96,76 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) * both the prescaler (/1 .. /128) and then by CLKSEL * (/2 .. /16). */ - u32 max = readl(pwm->mmio_base + MX1_PWMP); + u32 max = readl(mxc_pwm->mmio_base + MX1_PWMP); u32 p = max * duty_ns / period_ns; - writel(max - p, pwm->mmio_base + MX1_PWMS); + writel(max - p, mxc_pwm->mmio_base + MX1_PWMS); } else { BUG(); } return 0; } -EXPORT_SYMBOL(pwm_config); -int pwm_enable(struct pwm_device *pwm) +static int mxc_pwm_enable(struct pwm_device *pwm) { + struct mxc_pwm_device *mxc_pwm = pwm->data; int rc = 0; - if (!pwm->clk_enabled) { - rc = clk_enable(pwm->clk); + if (!mxc_pwm->clk_enabled) { + rc = clk_enable(mxc_pwm->clk); if (!rc) - pwm->clk_enabled = 1; + mxc_pwm->clk_enabled = 1; } return rc; } -EXPORT_SYMBOL(pwm_enable); - -void pwm_disable(struct pwm_device *pwm) -{ - writel(0, pwm->mmio_base + MX3_PWMCR); - - if (pwm->clk_enabled) { - clk_disable(pwm->clk); - pwm->clk_enabled = 0; - } -} -EXPORT_SYMBOL(pwm_disable); - -static DEFINE_MUTEX(pwm_lock); -static LIST_HEAD(pwm_list); -struct pwm_device *pwm_request(int pwm_id, const char *label) +static int mxc_pwm_disable(struct pwm_device *pwm) { - struct pwm_device *pwm; - int found = 0; + struct mxc_pwm_device *mxc_pwm = pwm->data; - mutex_lock(&pwm_lock); + writel(0, mxc_pwm->mmio_base + MX3_PWMCR); - list_for_each_entry(pwm, &pwm_list, node) { - if (pwm->pwm_id == pwm_id) { - found = 1; - break; - } + if (mxc_pwm->clk_enabled) { + clk_disable(mxc_pwm->clk); + mxc_pwm->clk_enabled = 0; } - - if (found) { - if (pwm->use_count == 0) { - pwm->use_count++; - pwm->label = label; - } else - pwm = ERR_PTR(-EBUSY); - } else - pwm = ERR_PTR(-ENOENT); - - mutex_unlock(&pwm_lock); - return pwm; -} -EXPORT_SYMBOL(pwm_request); - -void pwm_free(struct pwm_device *pwm) -{ - mutex_lock(&pwm_lock); - - if (pwm->use_count) { - pwm->use_count--; - pwm->label = NULL; - } else - pr_warning("PWM device already freed\n"); - - mutex_unlock(&pwm_lock); + return 0; } -EXPORT_SYMBOL(pwm_free); static int __devinit mxc_pwm_probe(struct platform_device *pdev) { + struct mxc_pwm_device *mxc_pwm; struct pwm_device *pwm; + struct pwm_ops *pops; struct resource *r; int ret = 0; + mxc_pwm = kzalloc(sizeof(struct mxc_pwm_device), GFP_KERNEL); + if (mxc_pwm == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (pwm == NULL) { dev_err(&pdev->dev, "failed to allocate memory\n"); - return -ENOMEM; + ret = -ENOMEM; + goto err_free1; + } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + ret = -ENOMEM; + goto err_free2; } - pwm->clk = clk_get(&pdev->dev, "pwm"); + mxc_pwm->clk = clk_get(&pdev->dev, "pwm"); - if (IS_ERR(pwm->clk)) { - ret = PTR_ERR(pwm->clk); - goto err_free; + if (IS_ERR(mxc_pwm->clk)) { + ret = PTR_ERR(mxc_pwm->clk); + goto err_free3; } - pwm->clk_enabled = 0; - - pwm->use_count = 0; - pwm->pwm_id = pdev->id; - pwm->pdev = pdev; + mxc_pwm->clk_enabled = 0; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (r == NULL) { @@ -221,16 +181,27 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) goto err_free_clk; } - pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); - if (pwm->mmio_base == NULL) { + mxc_pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); + if (mxc_pwm->mmio_base == NULL) { dev_err(&pdev->dev, "failed to ioremap() registers\n"); ret = -ENODEV; goto err_free_mem; } - mutex_lock(&pwm_lock); - list_add_tail(&pwm->node, &pwm_list); - mutex_unlock(&pwm_lock); + pops->pwm_config = mxc_pwm_config; + pops->pwm_enable = mxc_pwm_enable; + pops->pwm_disable = mxc_pwm_disable; + pops->name = pdev->name; + + pwm->pwm_id = pdev->id; + pwm->dev = &pdev->dev; + pwm->pops = pops; + pwm->data = mxc_pwm; + ret = pwm_device_register(pwm); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + goto err_free_mem; + } platform_set_drvdata(pdev, pwm); return 0; @@ -238,33 +209,38 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) err_free_mem: release_mem_region(r->start, r->end - r->start + 1); err_free_clk: - clk_put(pwm->clk); -err_free: + clk_put(mxc_pwm->clk); +err_free3: + kfree(pops); +err_free2: kfree(pwm); +err_free1: + kfree(mxc_pwm); return ret; } static int __devexit mxc_pwm_remove(struct platform_device *pdev) { struct pwm_device *pwm; + struct mxc_pwm_device *mxc_pwm; struct resource *r; pwm = platform_get_drvdata(pdev); if (pwm == NULL) return -ENODEV; + mxc_pwm = pwm->data; - mutex_lock(&pwm_lock); - list_del(&pwm->node); - mutex_unlock(&pwm_lock); - - iounmap(pwm->mmio_base); + pwm_device_unregister(pwm); + iounmap(mxc_pwm->mmio_base); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); release_mem_region(r->start, r->end - r->start + 1); - clk_put(pwm->clk); + clk_put(mxc_pwm->clk); + kfree(pwm->pops); kfree(pwm); + kfree(mxc_pwm); return 0; } diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c index ef32686..1de902a 100644 --- a/arch/arm/plat-pxa/pwm.c +++ b/arch/arm/plat-pxa/pwm.c @@ -43,33 +43,27 @@ MODULE_DEVICE_TABLE(platform, pwm_id_table); #define PWMCR_SD (1 << 6) #define PWMDCR_FD (1 << 10) -struct pwm_device { - struct list_head node; - struct pwm_device *secondary; - struct platform_device *pdev; - - const char *label; +struct pxa_pwm_device { + struct pxa_pwm_device *sec; struct clk *clk; int clk_enabled; void __iomem *mmio_base; - - unsigned int use_count; - unsigned int pwm_id; }; /* * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE */ -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +int pxa_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { unsigned long long c; unsigned long period_cycles, prescale, pv, dc; + struct pxa_pwm_device *pxa_pwm = pwm->data; if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; - c = clk_get_rate(pwm->clk); + c = clk_get_rate(pxa_pwm->clk); c = c * period_ns; do_div(c, 1000000000); period_cycles = c; @@ -90,94 +84,45 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) /* NOTE: the clock to PWM has to be enabled first * before writing to the registers */ - clk_enable(pwm->clk); - __raw_writel(prescale, pwm->mmio_base + PWMCR); - __raw_writel(dc, pwm->mmio_base + PWMDCR); - __raw_writel(pv, pwm->mmio_base + PWMPCR); - clk_disable(pwm->clk); + clk_enable(pxa_pwm->clk); + __raw_writel(prescale, pxa_pwm->mmio_base + PWMCR); + __raw_writel(dc, pxa_pwm->mmio_base + PWMDCR); + __raw_writel(pv, pxa_pwm->mmio_base + PWMPCR); + clk_disable(pxa_pwm->clk); return 0; } -EXPORT_SYMBOL(pwm_config); -int pwm_enable(struct pwm_device *pwm) +int pxa_pwm_enable(struct pwm_device *pwm) { + struct pxa_pwm_device *pxa_pwm = pwm->data; int rc = 0; - if (!pwm->clk_enabled) { - rc = clk_enable(pwm->clk); + if (!pxa_pwm->clk_enabled) { + rc = clk_enable(pxa_pwm->clk); if (!rc) - pwm->clk_enabled = 1; + pxa_pwm->clk_enabled = 1; } return rc; } -EXPORT_SYMBOL(pwm_enable); -void pwm_disable(struct pwm_device *pwm) +int pxa_pwm_disable(struct pwm_device *pwm) { - if (pwm->clk_enabled) { - clk_disable(pwm->clk); - pwm->clk_enabled = 0; - } -} -EXPORT_SYMBOL(pwm_disable); - -static DEFINE_MUTEX(pwm_lock); -static LIST_HEAD(pwm_list); + struct pxa_pwm_device *pxa_pwm = pwm->data; -struct pwm_device *pwm_request(int pwm_id, const char *label) -{ - struct pwm_device *pwm; - int found = 0; - - mutex_lock(&pwm_lock); - - list_for_each_entry(pwm, &pwm_list, node) { - if (pwm->pwm_id == pwm_id) { - found = 1; - break; - } + if (pxa_pwm->clk_enabled) { + clk_disable(pxa_pwm->clk); + pxa_pwm->clk_enabled = 0; } - - if (found) { - if (pwm->use_count == 0) { - pwm->use_count++; - pwm->label = label; - } else - pwm = ERR_PTR(-EBUSY); - } else - pwm = ERR_PTR(-ENOENT); - - mutex_unlock(&pwm_lock); - return pwm; -} -EXPORT_SYMBOL(pwm_request); - -void pwm_free(struct pwm_device *pwm) -{ - mutex_lock(&pwm_lock); - - if (pwm->use_count) { - pwm->use_count--; - pwm->label = NULL; - } else - pr_warning("PWM device already freed\n"); - - mutex_unlock(&pwm_lock); -} -EXPORT_SYMBOL(pwm_free); - -static inline void __add_pwm(struct pwm_device *pwm) -{ - mutex_lock(&pwm_lock); - list_add_tail(&pwm->node, &pwm_list); - mutex_unlock(&pwm_lock); + return 0; } static int __devinit pwm_probe(struct platform_device *pdev) { const struct platform_device_id *id = platform_get_device_id(pdev); + struct pxa_pwm_device *pxa_pwm, *pxa_pwm_sec; struct pwm_device *pwm, *secondary = NULL; + struct pwm_ops *pops; struct resource *r; int ret = 0; @@ -186,17 +131,26 @@ static int __devinit pwm_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to allocate memory\n"); return -ENOMEM; } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pwm); + return -ENOMEM; + } + pxa_pwm = kzalloc(sizeof(struct pxa_pwm_device), GFP_KERNEL); + if (pxa_pwm == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pops); + kfree(pwm); + return -ENOMEM; + } - pwm->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(pwm->clk)) { - ret = PTR_ERR(pwm->clk); + pxa_pwm->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(pxa_pwm->clk)) { + ret = PTR_ERR(pxa_pwm->clk); goto err_free; } - pwm->clk_enabled = 0; - - pwm->use_count = 0; - pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id; - pwm->pdev = pdev; + pxa_pwm->clk_enabled = 0; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (r == NULL) { @@ -212,69 +166,105 @@ static int __devinit pwm_probe(struct platform_device *pdev) goto err_free_clk; } - pwm->mmio_base = ioremap(r->start, resource_size(r)); - if (pwm->mmio_base == NULL) { + pxa_pwm->mmio_base = ioremap(r->start, resource_size(r)); + if (pxa_pwm->mmio_base == NULL) { dev_err(&pdev->dev, "failed to ioremap() registers\n"); ret = -ENODEV; goto err_free_mem; } + pops->pwm_config = pxa_pwm_config; + pops->pwm_enable = pxa_pwm_enable; + pops->pwm_disable = pxa_pwm_disable; + pops->name = pdev->name; + + pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id; + pwm->dev = &pdev->dev; + pwm->pops = pops; + pwm->data = pxa_pwm; + + ret = pwm_device_register(pwm); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + goto err_free_mem; + } + if (id->driver_data & HAS_SECONDARY_PWM) { secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (secondary == NULL) { ret = -ENOMEM; - goto err_free_mem; + goto err_pwm; + } + pxa_pwm_sec = kzalloc(sizeof(struct pxa_pwm_device), + GFP_KERNEL); + if (pxa_pwm_sec == NULL) { + ret = -ENOMEM; + goto err_free_mem2; } *secondary = *pwm; - pwm->secondary = secondary; + *pxa_pwm_sec = *pxa_pwm; + pxa_pwm->sec = pxa_pwm_sec; /* registers for the second PWM has offset of 0x10 */ - secondary->mmio_base = pwm->mmio_base + 0x10; + pxa_pwm_sec->mmio_base = pxa_pwm->mmio_base + 0x10; secondary->pwm_id = pdev->id + 2; - } + secondary->data = pxa_pwm_sec; - __add_pwm(pwm); - if (secondary) - __add_pwm(secondary); + ret = pwm_device_register(secondary); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + goto err_free_mem3; + } + } platform_set_drvdata(pdev, pwm); return 0; - +err_free_mem3: + kfree(pxa_pwm_sec); +err_free_mem2: + kfree(secondary); +err_pwm: + pwm_device_unregister(pwm); err_free_mem: release_mem_region(r->start, resource_size(r)); err_free_clk: - clk_put(pwm->clk); + clk_put(pxa_pwm->clk); err_free: + kfree(pxa_pwm); + kfree(pops); kfree(pwm); return ret; } static int __devexit pwm_remove(struct platform_device *pdev) { - struct pwm_device *pwm; + struct pwm_device *pwm, *secondary; + struct pxa_pwm_device *pxa_pwm, *pxa_pwm_sec; struct resource *r; pwm = platform_get_drvdata(pdev); if (pwm == NULL) return -ENODEV; - - mutex_lock(&pwm_lock); - - if (pwm->secondary) { - list_del(&pwm->secondary->node); - kfree(pwm->secondary); + pxa_pwm = pwm->data; + secondary = pwm_request((pdev->id + 2), pdev->name); + pxa_pwm_sec = secondary->data; + + pwm_device_unregister(pwm); + iounmap(pxa_pwm->mmio_base); + if (secondary) { + pwm_device_unregister(secondary); + iounmap(pxa_pwm->mmio_base); + kfree(pxa_pwm_sec); + kfree(secondary); } - list_del(&pwm->node); - mutex_unlock(&pwm_lock); - - iounmap(pwm->mmio_base); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); release_mem_region(r->start, resource_size(r)); - clk_put(pwm->clk); + clk_put(pxa_pwm->clk); + kfree(pxa_pwm); + kfree(pwm->pops); kfree(pwm); return 0; } diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c index 2eeb49f..63fba01 100644 --- a/arch/arm/plat-samsung/pwm.c +++ b/arch/arm/plat-samsung/pwm.c @@ -26,25 +26,19 @@ #include #include -struct pwm_device { - struct list_head list; +struct s3c_pwm_device { struct platform_device *pdev; struct clk *clk_div; struct clk *clk; - const char *label; unsigned int period_ns; unsigned int duty_ns; unsigned char tcon_base; unsigned char running; - unsigned char use_count; - unsigned char pwm_id; }; -#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) - static struct clk *clk_scaler[2]; /* Standard setup for a timer block. */ @@ -78,108 +72,61 @@ struct platform_device s3c_device_timer[] = { [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, }; -static inline int pwm_is_tdiv(struct pwm_device *pwm) +static inline int pwm_is_tdiv(struct s3c_pwm_device *s3c_pwm) { - return clk_get_parent(pwm->clk) == pwm->clk_div; + return clk_get_parent(s3c_pwm->clk) == s3c_pwm->clk_div; } -static DEFINE_MUTEX(pwm_lock); -static LIST_HEAD(pwm_list); +#define pwm_tcon_start(s3c_pwm) (1 << (s3c_pwm->tcon_base + 0)) +#define pwm_tcon_invert(s3c_pwm) (1 << (s3c_pwm->tcon_base + 2)) +#define pwm_tcon_autoreload(s3c_pwm) (1 << (s3c_pwm->tcon_base + 3)) +#define pwm_tcon_manulupdate(s3c_pwm) (1 << (s3c_pwm->tcon_base + 1)) -struct pwm_device *pwm_request(int pwm_id, const char *label) -{ - struct pwm_device *pwm; - int found = 0; - - mutex_lock(&pwm_lock); - - list_for_each_entry(pwm, &pwm_list, list) { - if (pwm->pwm_id == pwm_id) { - found = 1; - break; - } - } - - if (found) { - if (pwm->use_count == 0) { - pwm->use_count = 1; - pwm->label = label; - } else - pwm = ERR_PTR(-EBUSY); - } else - pwm = ERR_PTR(-ENOENT); - - mutex_unlock(&pwm_lock); - return pwm; -} - -EXPORT_SYMBOL(pwm_request); - - -void pwm_free(struct pwm_device *pwm) -{ - mutex_lock(&pwm_lock); - - if (pwm->use_count) { - pwm->use_count--; - pwm->label = NULL; - } else - printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id); - - mutex_unlock(&pwm_lock); -} - -EXPORT_SYMBOL(pwm_free); - -#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) -#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) -#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) -#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) - -int pwm_enable(struct pwm_device *pwm) +int s3c_pwm_enable(struct pwm_device *pwm) { unsigned long flags; unsigned long tcon; + struct s3c_pwm_device *s3c_pwm = pwm->data; local_irq_save(flags); tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_start(pwm); + tcon |= pwm_tcon_start(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); local_irq_restore(flags); - pwm->running = 1; + s3c_pwm->running = 1; return 0; } -EXPORT_SYMBOL(pwm_enable); - -void pwm_disable(struct pwm_device *pwm) +int s3c_pwm_disable(struct pwm_device *pwm) { unsigned long flags; unsigned long tcon; + struct s3c_pwm_device *s3c_pwm = pwm->data; local_irq_save(flags); tcon = __raw_readl(S3C2410_TCON); - tcon &= ~pwm_tcon_start(pwm); + tcon &= ~pwm_tcon_start(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); local_irq_restore(flags); - pwm->running = 0; + s3c_pwm->running = 0; + return 0; } -EXPORT_SYMBOL(pwm_disable); - -static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) +static unsigned long pwm_calc_tin(struct pwm_device *pwm, + unsigned long freq) { unsigned long tin_parent_rate; unsigned int div; + struct s3c_pwm_device *s3c_pwm = pwm->data; - tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div)); - pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate); + tin_parent_rate = clk_get_rate(clk_get_parent(s3c_pwm->clk_div)); + dev_dbg(pwm->dev, "tin parent at %lu\n", tin_parent_rate); for (div = 2; div <= 16; div *= 2) { if ((tin_parent_rate / (div << 16)) < freq) @@ -191,7 +138,7 @@ static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) #define NS_IN_HZ (1000000000UL) -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +int s3c_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { unsigned long tin_rate; unsigned long tin_ns; @@ -200,6 +147,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) unsigned long tcon; unsigned long tcnt; long tcmp; + struct s3c_pwm_device *s3c_pwm = pwm->data; /* We currently avoid using 64bit arithmetic by using the * fact that anything faster than 1Hz is easily representable @@ -211,8 +159,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (duty_ns > period_ns) return -EINVAL; - if (period_ns == pwm->period_ns && - duty_ns == pwm->duty_ns) + if (period_ns == s3c_pwm->period_ns && + duty_ns == s3c_pwm->duty_ns) return 0; /* The TCMP and TCNT can be read without a lock, they're not @@ -223,26 +171,26 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) period = NS_IN_HZ / period_ns; - pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n", + dev_dbg(pwm->dev, "duty_ns=%d, period_ns=%d (%lu)\n", duty_ns, period_ns, period); /* Check to see if we are changing the clock rate of the PWM */ - if (pwm->period_ns != period_ns) { - if (pwm_is_tdiv(pwm)) { + if (s3c_pwm->period_ns != period_ns) { + if (pwm_is_tdiv(s3c_pwm)) { tin_rate = pwm_calc_tin(pwm, period); - clk_set_rate(pwm->clk_div, tin_rate); + clk_set_rate(s3c_pwm->clk_div, tin_rate); } else - tin_rate = clk_get_rate(pwm->clk); + tin_rate = clk_get_rate(s3c_pwm->clk); - pwm->period_ns = period_ns; + s3c_pwm->period_ns = period_ns; - pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate); + dev_dbg(pwm->dev, "tin_rate=%lu\n", tin_rate); tin_ns = NS_IN_HZ / tin_rate; tcnt = period_ns / tin_ns; } else - tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk); + tin_ns = NS_IN_HZ / clk_get_rate(s3c_pwm->clk); /* Note, counters count down */ @@ -253,7 +201,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (tcmp == tcnt) tcmp--; - pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); + dev_dbg(pwm->dev, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); if (tcmp < 0) tcmp = 0; @@ -266,11 +214,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id)); tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_manulupdate(pwm); - tcon |= pwm_tcon_autoreload(pwm); + tcon |= pwm_tcon_manulupdate(s3c_pwm); + tcon |= pwm_tcon_autoreload(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); - tcon &= ~pwm_tcon_manulupdate(pwm); + tcon &= ~pwm_tcon_manulupdate(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); local_irq_restore(flags); @@ -278,103 +226,122 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) return 0; } -EXPORT_SYMBOL(pwm_config); - -static int pwm_register(struct pwm_device *pwm) -{ - pwm->duty_ns = -1; - pwm->period_ns = -1; - - mutex_lock(&pwm_lock); - list_add_tail(&pwm->list, &pwm_list); - mutex_unlock(&pwm_lock); - - return 0; -} - static int s3c_pwm_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct s3c_pwm_device *s3c_pwm; struct pwm_device *pwm; + struct pwm_ops *pops; unsigned long flags; unsigned long tcon; unsigned int id = pdev->id; - int ret; + int ret = 0; if (id == 4) { dev_err(dev, "TIMER4 is currently not supported\n"); return -ENXIO; } + s3c_pwm = kzalloc(sizeof(struct s3c_pwm_device), GFP_KERNEL); + if (s3c_pwm == NULL) { + dev_err(dev, "failed to allocate pwm_device\n"); + return -ENOMEM; + } + s3c_pwm->pdev = pdev; pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (pwm == NULL) { dev_err(dev, "failed to allocate pwm_device\n"); - return -ENOMEM; + goto err_alloc; + ret = -ENOMEM; + } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(dev, "failed to allocate memory\n"); + goto err_alloc1; + ret = -ENOMEM; } - - pwm->pdev = pdev; - pwm->pwm_id = id; /* calculate base of control bits in TCON */ - pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; + s3c_pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; - pwm->clk = clk_get(dev, "pwm-tin"); - if (IS_ERR(pwm->clk)) { + s3c_pwm->clk = clk_get(dev, "pwm-tin"); + if (IS_ERR(s3c_pwm->clk)) { dev_err(dev, "failed to get pwm tin clk\n"); - ret = PTR_ERR(pwm->clk); - goto err_alloc; + ret = PTR_ERR(s3c_pwm->clk); + goto err_alloc2; } - pwm->clk_div = clk_get(dev, "pwm-tdiv"); - if (IS_ERR(pwm->clk_div)) { + s3c_pwm->clk_div = clk_get(dev, "pwm-tdiv"); + if (IS_ERR(s3c_pwm->clk_div)) { dev_err(dev, "failed to get pwm tdiv clk\n"); - ret = PTR_ERR(pwm->clk_div); + ret = PTR_ERR(s3c_pwm->clk_div); goto err_clk_tin; } local_irq_save(flags); tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_invert(pwm); + tcon |= pwm_tcon_invert(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); local_irq_restore(flags); + pops->pwm_config = s3c_pwm_config; + pops->pwm_enable = s3c_pwm_enable; + pops->pwm_disable = s3c_pwm_disable; + pops->name = pdev->name; + + pwm->dev = dev; + pwm->pwm_id = id; + pwm->pops = pops; + pwm->data = s3c_pwm; - ret = pwm_register(pwm); + s3c_pwm->duty_ns = -1; + s3c_pwm->period_ns = -1; + ret = pwm_device_register(pwm); if (ret) { dev_err(dev, "failed to register pwm\n"); goto err_clk_tdiv; } - pwm_dbg(pwm, "config bits %02x\n", - (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f); + dev_dbg(dev, "config bits %02x\n", + (__raw_readl(S3C2410_TCON) >> s3c_pwm->tcon_base) & 0x0f); dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", - clk_get_rate(pwm->clk), - clk_get_rate(pwm->clk_div), - pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base); + clk_get_rate(s3c_pwm->clk), + clk_get_rate(s3c_pwm->clk_div), + pwm_is_tdiv(s3c_pwm) ? "div" : "ext", s3c_pwm->tcon_base); platform_set_drvdata(pdev, pwm); return 0; - err_clk_tdiv: - clk_put(pwm->clk_div); +err_clk_tdiv: + clk_put(s3c_pwm->clk_div); - err_clk_tin: - clk_put(pwm->clk); +err_clk_tin: + clk_put(s3c_pwm->clk); - err_alloc: +err_alloc2: + kfree(pops); + +err_alloc1: kfree(pwm); + +err_alloc: + kfree(s3c_pwm); return ret; } static int __devexit s3c_pwm_remove(struct platform_device *pdev) { struct pwm_device *pwm = platform_get_drvdata(pdev); + struct s3c_pwm_device *s3c_pwm = pwm->data; - clk_put(pwm->clk_div); - clk_put(pwm->clk); + pwm_device_unregister(pwm); + clk_put(s3c_pwm->clk_div); + clk_put(s3c_pwm->clk); + kfree(s3c_pwm); + kfree(pwm->pops); kfree(pwm); return 0; @@ -384,13 +351,14 @@ static int __devexit s3c_pwm_remove(struct platform_device *pdev) static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state) { struct pwm_device *pwm = platform_get_drvdata(pdev); + struct s3c_pwm_device *s3c_pwm = pwm->data; /* No one preserve these values during suspend so reset them * Otherwise driver leaves PWM unconfigured if same values * passed to pwm_config */ - pwm->period_ns = 0; - pwm->duty_ns = 0; + s3c_pwm->period_ns = 0; + s3c_pwm->duty_ns = 0; return 0; } @@ -398,11 +366,12 @@ static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state) static int s3c_pwm_resume(struct platform_device *pdev) { struct pwm_device *pwm = platform_get_drvdata(pdev); + struct s3c_pwm_device *s3c_pwm = pwm->data; unsigned long tcon; /* Restore invertion */ tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_invert(pwm); + tcon |= pwm_tcon_invert(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); return 0; diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c index a26a6fa..9f46767 100644 --- a/arch/mips/jz4740/pwm.c +++ b/arch/mips/jz4740/pwm.c @@ -152,7 +152,7 @@ int pwm_enable(struct pwm_device *pwm) return 0; } -void pwm_disable(struct pwm_device *pwm) +int pwm_disable(struct pwm_device *pwm) { uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index b0f2c00..6a6ea41 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -129,6 +129,12 @@ #define twl_has_pwrbutton() false #endif +#if defined CONFIG_TWL6030_PWM +#define twl_has_pwm() true +#else +#define twl_has_pwm() false +#endif + #define SUB_CHIP_ID0 0 #define SUB_CHIP_ID1 1 #define SUB_CHIP_ID2 2 @@ -825,6 +831,13 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features) if (IS_ERR(child)) return PTR_ERR(child); } + if (twl_has_pwm()) { + child = add_child(SUB_CHIP_ID2, "twl6030_pwm", + NULL, 0, + false, 0, 0); + if (IS_ERR(child)) + return PTR_ERR(child); + } return 0; } diff --git a/drivers/mfd/twl6030-pwm.c b/drivers/mfd/twl6030-pwm.c index 5d25bdc..b78324b 100644 --- a/drivers/mfd/twl6030-pwm.c +++ b/drivers/mfd/twl6030-pwm.c @@ -20,8 +20,10 @@ #include #include -#include #include +#include +#include +#include #define LED_PWM_CTRL1 0xF4 #define LED_PWM_CTRL2 0xF5 @@ -45,15 +47,10 @@ #define PWM_CTRL2_MODE_MASK 0x3 -struct pwm_device { - const char *label; - unsigned int pwm_id; -}; - -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +int twl6030_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { u8 duty_cycle; - int ret; + int ret = 0; if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; @@ -69,12 +66,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) } return 0; } -EXPORT_SYMBOL(pwm_config); -int pwm_enable(struct pwm_device *pwm) +int twl6030_pwm_enable(struct pwm_device *pwm) { u8 val; - int ret; + int ret = 0; ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); if (ret < 0) { @@ -95,18 +91,17 @@ int pwm_enable(struct pwm_device *pwm) twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); return 0; } -EXPORT_SYMBOL(pwm_enable); -void pwm_disable(struct pwm_device *pwm) +int twl6030_pwm_disable(struct pwm_device *pwm) { u8 val; - int ret; + int ret = 0; ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); if (ret < 0) { pr_err("%s: Failed to disable PWM, Error %d\n", pwm->label, ret); - return; + return ret; } val &= ~PWM_CTRL2_MODE_MASK; @@ -116,48 +111,86 @@ void pwm_disable(struct pwm_device *pwm) if (ret < 0) { pr_err("%s: Failed to disable PWM, Error %d\n", pwm->label, ret); - return; } - return; + return ret; } -EXPORT_SYMBOL(pwm_disable); -struct pwm_device *pwm_request(int pwm_id, const char *label) +static int __devinit twl6030_pwm_probe(struct platform_device *pdev) { - u8 val; - int ret; struct pwm_device *pwm; + struct pwm_ops *pops; + int ret; + u8 val; pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (pwm == NULL) { - pr_err("%s: failed to allocate memory\n", label); - return NULL; + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pwm); + return -ENOMEM; } - pwm->label = label; - pwm->pwm_id = pwm_id; - + pops->pwm_config = twl6030_pwm_config; + pops->pwm_enable = twl6030_pwm_enable; + pops->pwm_disable = twl6030_pwm_disable; + pops->name = &pdev->name; + pwm->dev = &pdev->dev; + pwm->pwm_id = pdev->id; + pwm->pops = pops; + ret = pwm_device_register(pwm); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + kfree(pwm); + kfree(pops); + return ret; + } + platform_set_drvdata(pdev, pwm); /* Configure PWM */ val = PWM_CTRL2_DIS_PD | PWM_CTRL2_CURR_02 | PWM_CTRL2_SRC_VAC | - PWM_CTRL2_MODE_HW; + PWM_CTRL2_MODE_HW; ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); - if (ret < 0) { - pr_err("%s: Failed to configure PWM, Error %d\n", - pwm->label, ret); - - kfree(pwm); - return NULL; + dev_err(&pdev->dev, "Failed to configure PWM, Error %d\n", ret); + return ret; } - - return pwm; + dev_dbg(&pdev->dev, "pwm probe successful\n"); + return ret; } -EXPORT_SYMBOL(pwm_request); -void pwm_free(struct pwm_device *pwm) +static int __devexit twl6030_pwm_remove(struct platform_device *pdev) { - pwm_disable(pwm); + struct pwm_device *pwm = platform_get_drvdata(pdev); + + pwm_device_unregister(pwm); + kfree(pwm->pops); kfree(pwm); + dev_dbg(&pdev->dev, "pwm driver removed\n"); + return 0; } -EXPORT_SYMBOL(pwm_free); + +static struct platform_driver twl6030_pwm_driver = { + .driver = { + .name = "twl6030_pwm", + .owner = THIS_MODULE, + }, + .probe = twl6030_pwm_probe, + .remove = __devexit_p(twl6030_pwm_remove), +}; + +static int __init twl6030_pwm_init(void) +{ + return platform_driver_register(&twl6030_pwm_driver); +} + +static void __exit twl6030_pwm_deinit(void) +{ + platform_driver_unregister(&twl6030_pwm_driver); +} + +subsys_initcall(twl6030_pwm_init); +module_exit(twl6030_pwm_deinit); diff --git a/drivers/misc/ab8500-pwm.c b/drivers/misc/ab8500-pwm.c index 54e3d05..d2b23b6 100644 --- a/drivers/misc/ab8500-pwm.c +++ b/drivers/misc/ab8500-pwm.c @@ -23,16 +23,9 @@ #define ENABLE_PWM 1 #define DISABLE_PWM 0 -struct pwm_device { - struct device *dev; - struct list_head node; - const char *label; - unsigned int pwm_id; -}; - static LIST_HEAD(pwm_list); -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +int ab8500_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { int ret = 0; unsigned int higher_val, lower_val; @@ -60,23 +53,21 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) return ret; } -EXPORT_SYMBOL(pwm_config); -int pwm_enable(struct pwm_device *pwm) +int ab8500_pwm_enable(struct pwm_device *pwm) { int ret; ret = abx500_mask_and_set_register_interruptible(pwm->dev, AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, - 1 << (pwm->pwm_id-1), ENABLE_PWM); + 1 << (pwm->pwm_id-1), 1 << (pwm->pwm_id-1)); if (ret < 0) dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", pwm->label, ret); return ret; } -EXPORT_SYMBOL(pwm_enable); -void pwm_disable(struct pwm_device *pwm) +int ab8500_pwm_disable(struct pwm_device *pwm) { int ret; @@ -86,58 +77,56 @@ void pwm_disable(struct pwm_device *pwm) if (ret < 0) dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", pwm->label, ret); - return; -} -EXPORT_SYMBOL(pwm_disable); - -struct pwm_device *pwm_request(int pwm_id, const char *label) -{ - struct pwm_device *pwm; - - list_for_each_entry(pwm, &pwm_list, node) { - if (pwm->pwm_id == pwm_id) { - pwm->label = label; - pwm->pwm_id = pwm_id; - return pwm; - } - } - - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(pwm_request); - -void pwm_free(struct pwm_device *pwm) -{ - pwm_disable(pwm); + return ret; } -EXPORT_SYMBOL(pwm_free); static int __devinit ab8500_pwm_probe(struct platform_device *pdev) { - struct pwm_device *pwm; + int ret = 0; + struct pwm_ops *pops; + struct pwm_device *pwm_dev; /* * Nothing to be done in probe, this is required to get the * device which is required for ab8500 read and write */ - pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); - if (pwm == NULL) { + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { dev_err(&pdev->dev, "failed to allocate memory\n"); return -ENOMEM; } - pwm->dev = &pdev->dev; - pwm->pwm_id = pdev->id; - list_add_tail(&pwm->node, &pwm_list); - platform_set_drvdata(pdev, pwm); - dev_dbg(pwm->dev, "pwm probe successful\n"); - return 0; + pwm_dev = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (pwm_dev == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pops); + return -ENOMEM; + } + pops->pwm_config = ab8500_pwm_config; + pops->pwm_enable = ab8500_pwm_enable; + pops->pwm_disable = ab8500_pwm_disable; + pops->name = "ab8500"; + pwm_dev->dev = &pdev->dev; + pwm_dev->pwm_id = pdev->id; + pwm_dev->pops = pops; + ret = pwm_device_register(pwm_dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + kfree(pwm_dev); + kfree(pops); + return ret; + } + platform_set_drvdata(pdev, pwm_dev); + dev_dbg(&pdev->dev, "pwm probe successful\n"); + return ret; } static int __devexit ab8500_pwm_remove(struct platform_device *pdev) { - struct pwm_device *pwm = platform_get_drvdata(pdev); - list_del(&pwm->node); + struct pwm_device *pwm_dev = platform_get_drvdata(pdev); + + pwm_device_unregister(pwm_dev); dev_dbg(&pdev->dev, "pwm driver removed\n"); - kfree(pwm); + kfree(pwm_dev->pops); + kfree(pwm_dev); return 0; } diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 5d10106..a88640c 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -4,6 +4,7 @@ menuconfig PWM_DEVICES bool "PWM devices" + depends on ARM default y ---help--- Say Y here to get to see options for device drivers from various diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c index b84027a..3a0d426 100644 --- a/drivers/pwm/pwm-core.c +++ b/drivers/pwm/pwm-core.c @@ -11,11 +11,6 @@ #include #include -struct pwm_device { - struct pwm_ops *pops; - int pwm_id; -}; - struct pwm_dev_info { struct pwm_device *pwm_dev; struct list_head list; @@ -40,9 +35,9 @@ int pwm_enable(struct pwm_device *pwm) } EXPORT_SYMBOL(pwm_enable); -void pwm_disable(struct pwm_device *pwm) +int pwm_disable(struct pwm_device *pwm) { - pwm->pops->pwm_disable(pwm); + return pwm->pops->pwm_disable(pwm); } EXPORT_SYMBOL(pwm_disable); diff --git a/include/linux/pwm.h b/include/linux/pwm.h index 6e7da1f..4344c0b 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -1,14 +1,29 @@ #ifndef __LINUX_PWM_H #define __LINUX_PWM_H -struct pwm_device; +/* + * TODO: #if defined CONFIG_PWM_CORE has to be removed after mips jz4740 + * pwm driver aligning with pwm-core.c driver. + */ +#if defined CONFIG_PWM_CORE +struct pwm_device { + struct pwm_ops *pops; + struct device *dev; + struct list_head node; + const char *label; + unsigned int pwm_id; + void *data; +}; struct pwm_ops { int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int period_ns); int (*pwm_enable)(struct pwm_device *pwm); int (*pwm_disable)(struct pwm_device *pwm); - char *name; + const char *name; }; +#else +struct pwm_device; +#endif /* * pwm_request - request a PWM device @@ -33,7 +48,7 @@ int pwm_enable(struct pwm_device *pwm); /* * pwm_disable - stop a PWM output toggling */ -void pwm_disable(struct pwm_device *pwm); +int pwm_disable(struct pwm_device *pwm); int pwm_device_register(struct pwm_device *pwm_dev); int pwm_device_unregister(struct pwm_device *pwm_dev); -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 09:44:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 09:45:57 +0200 (CEST) Received: from eu1sys200aog119.obsmtp.com ([207.126.144.147]:33798 "EHLO eu1sys200aog119.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491945Ab0I1Hok (ORCPT ); Tue, 28 Sep 2010 09:44:40 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob119.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGceJENVUyqwiwhrwB8c90VeFE0LSjU@postini.com; Tue, 28 Sep 2010 07:44:39 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9DA8A89; Tue, 28 Sep 2010 07:41:20 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B3F121948; Tue, 28 Sep 2010 07:41:12 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 88FF224C2AB; Tue, 28 Sep 2010 09:40:59 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 09:41:03 +0200 From: Arun Murthy To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Cc: , , , , , Subject: [PATCH 2/7] backlight:pwm: add an element 'name' to platform data Date: Tue, 28 Sep 2010 13:10:43 +0530 Message-ID: <1285659648-21409-3-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27839 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22115 Content-Length: 1334 Lines: 40 A new element 'name' is added to pwm backlight platform data structure. This is required to identify the pwm device. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/video/backlight/pwm_bl.c | 4 +++- include/linux/pwm_backlight.h | 1 + 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c index 5504435..b0978a8 100644 --- a/drivers/video/backlight/pwm_bl.c +++ b/drivers/video/backlight/pwm_bl.c @@ -94,7 +94,9 @@ static int pwm_backlight_probe(struct platform_device *pdev) pb->notify = data->notify; pb->dev = &pdev->dev; - pb->pwm = pwm_request(data->pwm_id, "backlight"); + if (!data->name) + data->name = "backlight"; + pb->pwm = pwm_request(data->pwm_id, data->name); if (IS_ERR(pb->pwm)) { dev_err(&pdev->dev, "unable to request PWM for backlight\n"); ret = PTR_ERR(pb->pwm); diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h index 01b3d75..c2ce8f8 100644 --- a/include/linux/pwm_backlight.h +++ b/include/linux/pwm_backlight.h @@ -6,6 +6,7 @@ struct platform_pwm_backlight_data { int pwm_id; + char *name; unsigned int max_brightness; unsigned int dft_brightness; unsigned int pwm_period_ns; -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 09:46:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 09:46:44 +0200 (CEST) Received: from eu1sys200aog107.obsmtp.com ([207.126.144.123]:34106 "EHLO eu1sys200aog107.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491950Ab0I1Hql (ORCPT ); Tue, 28 Sep 2010 09:46:41 +0200 Received: from source ([167.4.1.35]) (using TLSv1) by eu1sys200aob107.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGc+HOiAQ16kf1JvFtQBNKuJo7VSCZU@postini.com; Tue, 28 Sep 2010 07:46:40 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.80.115]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 0C2DDBB; Tue, 28 Sep 2010 07:37:54 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 4C26631F; Tue, 28 Sep 2010 07:41:09 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 6D46624C2FA; Tue, 28 Sep 2010 09:41:04 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 09:41:08 +0200 From: Arun Murthy To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Cc: , , , , , Subject: [PATCH 3/7] leds: pwm: add a new element 'name' to platform data Date: Tue, 28 Sep 2010 13:10:44 +0530 Message-ID: <1285659648-21409-4-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27840 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22117 Content-Length: 1199 Lines: 41 A new element 'name' is added to pwm led platform data structure. This is required to identify the pwm device. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/leds/leds-pwm.c | 4 +++- include/linux/leds_pwm.h | 1 + 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c index da3fa8d..8da2be6 100644 --- a/drivers/leds/leds-pwm.c +++ b/drivers/leds/leds-pwm.c @@ -66,8 +66,10 @@ static int led_pwm_probe(struct platform_device *pdev) cur_led = &pdata->leds[i]; led_dat = &leds_data[i]; + if (!pdata->name) + pdata->name = cur_led->name; led_dat->pwm = pwm_request(cur_led->pwm_id, - cur_led->name); + pdata->name); if (IS_ERR(led_dat->pwm)) { dev_err(&pdev->dev, "unable to request PWM %d\n", cur_led->pwm_id); diff --git a/include/linux/leds_pwm.h b/include/linux/leds_pwm.h index 33a0711..7a847a0 100644 --- a/include/linux/leds_pwm.h +++ b/include/linux/leds_pwm.h @@ -16,6 +16,7 @@ struct led_pwm { struct led_pwm_platform_data { int num_leds; struct led_pwm *leds; + char *name; }; #endif -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 09:46:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 09:47:08 +0200 (CEST) Received: from eu1sys200aog120.obsmtp.com ([207.126.144.149]:51219 "EHLO eu1sys200aog120.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491948Ab0I1Hqs (ORCPT ); Tue, 28 Sep 2010 09:46:48 +0200 Received: from source ([167.4.1.35]) (using TLSv1) by eu1sys200aob120.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGc+HOiAQ16kf1JvFtQBNKuJo7VSCZU@postini.com; Tue, 28 Sep 2010 07:46:48 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.80.115]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 19CEDBA; Tue, 28 Sep 2010 07:37:45 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id CF50A31B; Tue, 28 Sep 2010 07:41:00 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id A1B6FA8095; Tue, 28 Sep 2010 09:40:56 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 09:41:00 +0200 From: Arun Murthy To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Cc: , , , , , Subject: [PATCH 1/7] pwm: Add pwm core driver Date: Tue, 28 Sep 2010 13:10:42 +0530 Message-ID: <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27841 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22118 Content-Length: 6306 Lines: 249 The existing pwm based led and backlight driver makes use of the pwm(include/linux/pwm.h). So all the board specific pwm drivers will be exposing the same set of function name as in include/linux/pwm.h. As a result build fails. In order to overcome this issue all the pwm drivers must register to some core pwm driver with function pointers for pwm operations (i.e pwm_config, pwm_enable, pwm_disable). The clients of pwm device will have to call pwm_request, wherein they will get the pointer to struct pwm_ops. This structure include function pointers for pwm_config, pwm_enable and pwm_disable. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/pwm/Kconfig | 16 ++++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-core.c | 129 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pwm.h | 12 ++++- 6 files changed, 160 insertions(+), 1 deletions(-) create mode 100644 drivers/pwm/Kconfig create mode 100644 drivers/pwm/Makefile create mode 100644 drivers/pwm/pwm-core.c diff --git a/drivers/Kconfig b/drivers/Kconfig index a2b902f..e042f27 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -111,4 +111,6 @@ source "drivers/xen/Kconfig" source "drivers/staging/Kconfig" source "drivers/platform/Kconfig" + +source "drivers/pwm/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 4ca727d..0061ec4 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -116,3 +116,4 @@ obj-$(CONFIG_STAGING) += staging/ obj-y += platform/ obj-y += ieee802154/ obj-y += vbus/ +obj-$(CONFIG_PWM_DEVICES) += pwm/ diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig new file mode 100644 index 0000000..5d10106 --- /dev/null +++ b/drivers/pwm/Kconfig @@ -0,0 +1,16 @@ +# +# PWM devices +# + +menuconfig PWM_DEVICES + bool "PWM devices" + default y + ---help--- + Say Y here to get to see options for device drivers from various + different categories. This option alone does not add any kernel code. + + If you say N, all options in this submenu will be skipped and disabled. + +if PWM_DEVICES + +endif # PWM_DEVICES diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile new file mode 100644 index 0000000..552f969 --- /dev/null +++ b/drivers/pwm/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PWM_DEVICES) += pwm-core.o diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c new file mode 100644 index 0000000..b84027a --- /dev/null +++ b/drivers/pwm/pwm-core.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * Author: Arun R Murthy + */ +#include +#include +#include +#include +#include +#include + +struct pwm_device { + struct pwm_ops *pops; + int pwm_id; +}; + +struct pwm_dev_info { + struct pwm_device *pwm_dev; + struct list_head list; +}; +static struct pwm_dev_info *di; + +DECLARE_RWSEM(pwm_list_lock); + +void __deprecated pwm_free(struct pwm_device *pwm) +{ +} + +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + return pwm->pops->pwm_config(pwm, duty_ns, period_ns); +} +EXPORT_SYMBOL(pwm_config); + +int pwm_enable(struct pwm_device *pwm) +{ + return pwm->pops->pwm_enable(pwm); +} +EXPORT_SYMBOL(pwm_enable); + +void pwm_disable(struct pwm_device *pwm) +{ + pwm->pops->pwm_disable(pwm); +} +EXPORT_SYMBOL(pwm_disable); + +int pwm_device_register(struct pwm_device *pwm_dev) +{ + struct pwm_dev_info *pwm; + + down_write(&pwm_list_lock); + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); + if (!pwm) { + up_write(&pwm_list_lock); + return -ENOMEM; + } + pwm->pwm_dev = pwm_dev; + list_add_tail(&pwm->list, &di->list); + up_write(&pwm_list_lock); + + return 0; +} +EXPORT_SYMBOL(pwm_device_register); + +int pwm_device_unregister(struct pwm_device *pwm_dev) +{ + struct pwm_dev_info *tmp; + struct list_head *pos, *tmp_lst; + + down_write(&pwm_list_lock); + list_for_each_safe(pos, tmp_lst, &di->list) { + tmp = list_entry(pos, struct pwm_dev_info, list); + if (tmp->pwm_dev == pwm_dev) { + list_del(pos); + kfree(tmp); + up_write(&pwm_list_lock); + return 0; + } + } + up_write(&pwm_list_lock); + return -ENOENT; +} +EXPORT_SYMBOL(pwm_device_unregister); + +struct pwm_device *pwm_request(int pwm_id, const char *name) +{ + struct pwm_dev_info *pwm; + struct list_head *pos; + + down_read(&pwm_list_lock); + list_for_each(pos, &di->list) { + pwm = list_entry(pos, struct pwm_dev_info, list); + if ((!strcmp(pwm->pwm_dev->pops->name, name)) && + (pwm->pwm_dev->pwm_id == pwm_id)) { + up_read(&pwm_list_lock); + return pwm->pwm_dev; + } + } + up_read(&pwm_list_lock); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(pwm_request); + +static int __init pwm_init(void) +{ + struct pwm_dev_info *pwm; + + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + INIT_LIST_HEAD(&pwm->list); + di = pwm; + return 0; +} + +static void __exit pwm_exit(void) +{ + kfree(di); +} + +subsys_initcall(pwm_init); +module_exit(pwm_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Arun R Murthy"); +MODULE_ALIAS("core:pwm"); +MODULE_DESCRIPTION("Core pwm driver"); diff --git a/include/linux/pwm.h b/include/linux/pwm.h index 7c77575..6e7da1f 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -3,6 +3,13 @@ struct pwm_device; +struct pwm_ops { + int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int period_ns); + int (*pwm_enable)(struct pwm_device *pwm); + int (*pwm_disable)(struct pwm_device *pwm); + char *name; +}; + /* * pwm_request - request a PWM device */ @@ -11,7 +18,7 @@ struct pwm_device *pwm_request(int pwm_id, const char *label); /* * pwm_free - free a PWM device */ -void pwm_free(struct pwm_device *pwm); +void __deprecated pwm_free(struct pwm_device *pwm); /* * pwm_config - change a PWM device configuration @@ -28,4 +35,7 @@ int pwm_enable(struct pwm_device *pwm); */ void pwm_disable(struct pwm_device *pwm); +int pwm_device_register(struct pwm_device *pwm_dev); +int pwm_device_unregister(struct pwm_device *pwm_dev); + #endif /* __LINUX_PWM_H */ -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 09:47:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 09:47:35 +0200 (CEST) Received: from eu1sys200aog107.obsmtp.com ([207.126.144.123]:34709 "EHLO eu1sys200aog107.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491956Ab0I1Hr0 (ORCPT ); Tue, 28 Sep 2010 09:47:26 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob107.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGdRHE3V4jMpp3sqOWWIWN/rHutnDlf@postini.com; Tue, 28 Sep 2010 07:47:24 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EBD1A14E; Tue, 28 Sep 2010 07:41:21 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A7967396; Tue, 28 Sep 2010 07:41:20 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id CBDD224C2F7; Tue, 28 Sep 2010 09:41:15 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 09:41:19 +0200 From: Arun Murthy To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Cc: , , , , , Subject: [PATCH 6/7] pwm: move existing pwm driver to drivers/pwm Date: Tue, 28 Sep 2010 13:10:47 +0530 Message-ID: <1285659648-21409-7-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27842 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22119 Content-Length: 22788 Lines: 852 As of now only ab8500 and twl6030 are moved. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/mfd/Kconfig | 9 -- drivers/mfd/Makefile | 1 - drivers/mfd/twl6030-pwm.c | 196 --------------------------------------------- drivers/misc/Kconfig | 9 -- drivers/misc/Makefile | 1 - drivers/misc/ab8500-pwm.c | 157 ------------------------------------ drivers/pwm/Kconfig | 18 ++++ drivers/pwm/Makefile | 3 + drivers/pwm/pwm-ab8500.c | 157 ++++++++++++++++++++++++++++++++++++ drivers/pwm/pwm-twl6040.c | 196 +++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 374 insertions(+), 373 deletions(-) delete mode 100644 drivers/mfd/twl6030-pwm.c delete mode 100644 drivers/misc/ab8500-pwm.c create mode 100644 drivers/pwm/pwm-ab8500.c create mode 100644 drivers/pwm/pwm-twl6040.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 256fabd..ab1d376 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -186,15 +186,6 @@ config TWL4030_CODEC select MFD_CORE default n -config TWL6030_PWM - tristate "TWL6030 PWM (Pulse Width Modulator) Support" - depends on TWL4030_CORE - select HAVE_PWM - default n - help - Say yes here if you want support for TWL6030 PWM. - This is used to control charging LED brightness. - config MFD_STMPE bool "Support STMicroelectronics STMPE" depends on I2C=y && GENERIC_HARDIRQS diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index d5968cd..1a89dbf 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -37,7 +37,6 @@ obj-$(CONFIG_MENELAUS) += menelaus.o obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o obj-$(CONFIG_TWL4030_CODEC) += twl4030-codec.o -obj-$(CONFIG_TWL6030_PWM) += twl6030-pwm.o obj-$(CONFIG_MFD_MC13783) += mc13783-core.o diff --git a/drivers/mfd/twl6030-pwm.c b/drivers/mfd/twl6030-pwm.c deleted file mode 100644 index b78324b..0000000 --- a/drivers/mfd/twl6030-pwm.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * twl6030_pwm.c - * Driver for PHOENIX (TWL6030) Pulse Width Modulator - * - * Copyright (C) 2010 Texas Instruments - * Author: Hemanth V - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -#define LED_PWM_CTRL1 0xF4 -#define LED_PWM_CTRL2 0xF5 - -/* Max value for CTRL1 register */ -#define PWM_CTRL1_MAX 255 - -/* Pull down disable */ -#define PWM_CTRL2_DIS_PD (1 << 6) - -/* Current control 2.5 milli Amps */ -#define PWM_CTRL2_CURR_02 (2 << 4) - -/* LED supply source */ -#define PWM_CTRL2_SRC_VAC (1 << 2) - -/* LED modes */ -#define PWM_CTRL2_MODE_HW (0 << 0) -#define PWM_CTRL2_MODE_SW (1 << 0) -#define PWM_CTRL2_MODE_DIS (2 << 0) - -#define PWM_CTRL2_MODE_MASK 0x3 - -int twl6030_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) -{ - u8 duty_cycle; - int ret = 0; - - if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) - return -EINVAL; - - duty_cycle = (duty_ns * PWM_CTRL1_MAX) / period_ns; - - ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, duty_cycle, LED_PWM_CTRL1); - - if (ret < 0) { - pr_err("%s: Failed to configure PWM, Error %d\n", - pwm->label, ret); - return ret; - } - return 0; -} - -int twl6030_pwm_enable(struct pwm_device *pwm) -{ - u8 val; - int ret = 0; - - ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); - if (ret < 0) { - pr_err("%s: Failed to enable PWM, Error %d\n", pwm->label, ret); - return ret; - } - - /* Change mode to software control */ - val &= ~PWM_CTRL2_MODE_MASK; - val |= PWM_CTRL2_MODE_SW; - - ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); - if (ret < 0) { - pr_err("%s: Failed to enable PWM, Error %d\n", pwm->label, ret); - return ret; - } - - twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); - return 0; -} - -int twl6030_pwm_disable(struct pwm_device *pwm) -{ - u8 val; - int ret = 0; - - ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); - if (ret < 0) { - pr_err("%s: Failed to disable PWM, Error %d\n", - pwm->label, ret); - return ret; - } - - val &= ~PWM_CTRL2_MODE_MASK; - val |= PWM_CTRL2_MODE_HW; - - ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); - if (ret < 0) { - pr_err("%s: Failed to disable PWM, Error %d\n", - pwm->label, ret); - } - return ret; -} - -static int __devinit twl6030_pwm_probe(struct platform_device *pdev) -{ - struct pwm_device *pwm; - struct pwm_ops *pops; - int ret; - u8 val; - - pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); - if (pwm == NULL) { - dev_err(&pdev->dev, "failed to allocate memory\n"); - return -ENOMEM; - } - pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); - if (pops == NULL) { - dev_err(&pdev->dev, "failed to allocate memory\n"); - kfree(pwm); - return -ENOMEM; - } - - pops->pwm_config = twl6030_pwm_config; - pops->pwm_enable = twl6030_pwm_enable; - pops->pwm_disable = twl6030_pwm_disable; - pops->name = &pdev->name; - pwm->dev = &pdev->dev; - pwm->pwm_id = pdev->id; - pwm->pops = pops; - ret = pwm_device_register(pwm); - if (ret < 0) { - dev_err(&pdev->dev, "failed to register pwm device\n"); - kfree(pwm); - kfree(pops); - return ret; - } - platform_set_drvdata(pdev, pwm); - /* Configure PWM */ - val = PWM_CTRL2_DIS_PD | PWM_CTRL2_CURR_02 | PWM_CTRL2_SRC_VAC | - PWM_CTRL2_MODE_HW; - - ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to configure PWM, Error %d\n", ret); - return ret; - } - dev_dbg(&pdev->dev, "pwm probe successful\n"); - return ret; -} - -static int __devexit twl6030_pwm_remove(struct platform_device *pdev) -{ - struct pwm_device *pwm = platform_get_drvdata(pdev); - - pwm_device_unregister(pwm); - kfree(pwm->pops); - kfree(pwm); - dev_dbg(&pdev->dev, "pwm driver removed\n"); - return 0; -} - -static struct platform_driver twl6030_pwm_driver = { - .driver = { - .name = "twl6030_pwm", - .owner = THIS_MODULE, - }, - .probe = twl6030_pwm_probe, - .remove = __devexit_p(twl6030_pwm_remove), -}; - -static int __init twl6030_pwm_init(void) -{ - return platform_driver_register(&twl6030_pwm_driver); -} - -static void __exit twl6030_pwm_deinit(void) -{ - platform_driver_unregister(&twl6030_pwm_driver); -} - -subsys_initcall(twl6030_pwm_init); -module_exit(twl6030_pwm_deinit); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ff8ea55..2c38d4e 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -62,15 +62,6 @@ config ATMEL_PWM purposes including software controlled power-efficient backlights on LCD displays, motor control, and waveform generation. -config AB8500_PWM - bool "AB8500 PWM support" - depends on AB8500_CORE - select HAVE_PWM - help - This driver exports functions to enable/disble/config/free Pulse - Width Modulation in the Analog Baseband Chip AB8500. - It is used by led and backlight driver to control the intensity. - config ATMEL_TCLIB bool "Atmel AT32/AT91 Timer/Counter Library" depends on (AVR32 || ARCH_AT91) diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 5da82965..21b4761 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -35,5 +35,4 @@ obj-y += eeprom/ obj-y += cb710/ obj-$(CONFIG_VMWARE_BALLOON) += vmware_balloon.o obj-$(CONFIG_ARM_CHARLCD) += arm-charlcd.o -obj-$(CONFIG_AB8500_PWM) += ab8500-pwm.o obj-$(CONFIG_PCH_PHUB) += pch_phub.o diff --git a/drivers/misc/ab8500-pwm.c b/drivers/misc/ab8500-pwm.c deleted file mode 100644 index d2b23b6..0000000 --- a/drivers/misc/ab8500-pwm.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Arun R Murthy - * License terms: GNU General Public License (GPL) version 2 - */ -#include -#include -#include -#include -#include -#include - -/* - * PWM Out generators - * Bank: 0x10 - */ -#define AB8500_PWM_OUT_CTRL1_REG 0x60 -#define AB8500_PWM_OUT_CTRL2_REG 0x61 -#define AB8500_PWM_OUT_CTRL7_REG 0x66 - -/* backlight driver constants */ -#define ENABLE_PWM 1 -#define DISABLE_PWM 0 - -static LIST_HEAD(pwm_list); - -int ab8500_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) -{ - int ret = 0; - unsigned int higher_val, lower_val; - u8 reg; - - /* - * get the first 8 bits that are be written to - * AB8500_PWM_OUT_CTRL1_REG[0:7] - */ - lower_val = duty_ns & 0x00FF; - /* - * get bits [9:10] that are to be written to - * AB8500_PWM_OUT_CTRL2_REG[0:1] - */ - higher_val = ((duty_ns & 0x0300) >> 8); - - reg = AB8500_PWM_OUT_CTRL1_REG + ((pwm->pwm_id - 1) * 2); - - ret = abx500_set_register_interruptible(pwm->dev, AB8500_MISC, - reg, (u8)lower_val); - if (ret < 0) - return ret; - ret = abx500_set_register_interruptible(pwm->dev, AB8500_MISC, - (reg + 1), (u8)higher_val); - - return ret; -} - -int ab8500_pwm_enable(struct pwm_device *pwm) -{ - int ret; - - ret = abx500_mask_and_set_register_interruptible(pwm->dev, - AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, - 1 << (pwm->pwm_id-1), 1 << (pwm->pwm_id-1)); - if (ret < 0) - dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", - pwm->label, ret); - return ret; -} - -int ab8500_pwm_disable(struct pwm_device *pwm) -{ - int ret; - - ret = abx500_mask_and_set_register_interruptible(pwm->dev, - AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, - 1 << (pwm->pwm_id-1), DISABLE_PWM); - if (ret < 0) - dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", - pwm->label, ret); - return ret; -} - -static int __devinit ab8500_pwm_probe(struct platform_device *pdev) -{ - int ret = 0; - struct pwm_ops *pops; - struct pwm_device *pwm_dev; - /* - * Nothing to be done in probe, this is required to get the - * device which is required for ab8500 read and write - */ - pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); - if (pops == NULL) { - dev_err(&pdev->dev, "failed to allocate memory\n"); - return -ENOMEM; - } - pwm_dev = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); - if (pwm_dev == NULL) { - dev_err(&pdev->dev, "failed to allocate memory\n"); - kfree(pops); - return -ENOMEM; - } - pops->pwm_config = ab8500_pwm_config; - pops->pwm_enable = ab8500_pwm_enable; - pops->pwm_disable = ab8500_pwm_disable; - pops->name = "ab8500"; - pwm_dev->dev = &pdev->dev; - pwm_dev->pwm_id = pdev->id; - pwm_dev->pops = pops; - ret = pwm_device_register(pwm_dev); - if (ret < 0) { - dev_err(&pdev->dev, "failed to register pwm device\n"); - kfree(pwm_dev); - kfree(pops); - return ret; - } - platform_set_drvdata(pdev, pwm_dev); - dev_dbg(&pdev->dev, "pwm probe successful\n"); - return ret; -} - -static int __devexit ab8500_pwm_remove(struct platform_device *pdev) -{ - struct pwm_device *pwm_dev = platform_get_drvdata(pdev); - - pwm_device_unregister(pwm_dev); - dev_dbg(&pdev->dev, "pwm driver removed\n"); - kfree(pwm_dev->pops); - kfree(pwm_dev); - return 0; -} - -static struct platform_driver ab8500_pwm_driver = { - .driver = { - .name = "ab8500-pwm", - .owner = THIS_MODULE, - }, - .probe = ab8500_pwm_probe, - .remove = __devexit_p(ab8500_pwm_remove), -}; - -static int __init ab8500_pwm_init(void) -{ - return platform_driver_register(&ab8500_pwm_driver); -} - -static void __exit ab8500_pwm_exit(void) -{ - platform_driver_unregister(&ab8500_pwm_driver); -} - -subsys_initcall(ab8500_pwm_init); -module_exit(ab8500_pwm_exit); -MODULE_AUTHOR("Arun MURTHY "); -MODULE_DESCRIPTION("AB8500 Pulse Width Modulation Driver"); -MODULE_ALIAS("AB8500 PWM driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a88640c..e347365 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -14,4 +14,22 @@ menuconfig PWM_DEVICES if PWM_DEVICES +config AB8500_PWM + bool "AB8500 PWM support" + depends on AB8500_CORE + select HAVE_PWM + help + This driver exports functions to enable/disble/config/free Pulse + Width Modulation in the Analog Baseband Chip AB8500. + It is used by led and backlight driver to control the intensity. + +config TWL6030_PWM + tristate "TWL6030 PWM (Pulse Width Modulator) Support" + depends on TWL4030_CORE + select HAVE_PWM + default n + help + Say yes here if you want support for TWL6030 PWM. + This is used to control charging LED brightness. + endif # PWM_DEVICES diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 552f969..f35afb4 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -1 +1,4 @@ obj-$(CONFIG_PWM_DEVICES) += pwm-core.o + +obj-$(CONFIG_AB8500_PWM) += pwm-ab8500.o +obj-$(CONFIG_TWL6030_PWM) += pwm-twl6030.o diff --git a/drivers/pwm/pwm-ab8500.c b/drivers/pwm/pwm-ab8500.c new file mode 100644 index 0000000..d2b23b6 --- /dev/null +++ b/drivers/pwm/pwm-ab8500.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Arun R Murthy + * License terms: GNU General Public License (GPL) version 2 + */ +#include +#include +#include +#include +#include +#include + +/* + * PWM Out generators + * Bank: 0x10 + */ +#define AB8500_PWM_OUT_CTRL1_REG 0x60 +#define AB8500_PWM_OUT_CTRL2_REG 0x61 +#define AB8500_PWM_OUT_CTRL7_REG 0x66 + +/* backlight driver constants */ +#define ENABLE_PWM 1 +#define DISABLE_PWM 0 + +static LIST_HEAD(pwm_list); + +int ab8500_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + int ret = 0; + unsigned int higher_val, lower_val; + u8 reg; + + /* + * get the first 8 bits that are be written to + * AB8500_PWM_OUT_CTRL1_REG[0:7] + */ + lower_val = duty_ns & 0x00FF; + /* + * get bits [9:10] that are to be written to + * AB8500_PWM_OUT_CTRL2_REG[0:1] + */ + higher_val = ((duty_ns & 0x0300) >> 8); + + reg = AB8500_PWM_OUT_CTRL1_REG + ((pwm->pwm_id - 1) * 2); + + ret = abx500_set_register_interruptible(pwm->dev, AB8500_MISC, + reg, (u8)lower_val); + if (ret < 0) + return ret; + ret = abx500_set_register_interruptible(pwm->dev, AB8500_MISC, + (reg + 1), (u8)higher_val); + + return ret; +} + +int ab8500_pwm_enable(struct pwm_device *pwm) +{ + int ret; + + ret = abx500_mask_and_set_register_interruptible(pwm->dev, + AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, + 1 << (pwm->pwm_id-1), 1 << (pwm->pwm_id-1)); + if (ret < 0) + dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", + pwm->label, ret); + return ret; +} + +int ab8500_pwm_disable(struct pwm_device *pwm) +{ + int ret; + + ret = abx500_mask_and_set_register_interruptible(pwm->dev, + AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, + 1 << (pwm->pwm_id-1), DISABLE_PWM); + if (ret < 0) + dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", + pwm->label, ret); + return ret; +} + +static int __devinit ab8500_pwm_probe(struct platform_device *pdev) +{ + int ret = 0; + struct pwm_ops *pops; + struct pwm_device *pwm_dev; + /* + * Nothing to be done in probe, this is required to get the + * device which is required for ab8500 read and write + */ + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + pwm_dev = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (pwm_dev == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pops); + return -ENOMEM; + } + pops->pwm_config = ab8500_pwm_config; + pops->pwm_enable = ab8500_pwm_enable; + pops->pwm_disable = ab8500_pwm_disable; + pops->name = "ab8500"; + pwm_dev->dev = &pdev->dev; + pwm_dev->pwm_id = pdev->id; + pwm_dev->pops = pops; + ret = pwm_device_register(pwm_dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + kfree(pwm_dev); + kfree(pops); + return ret; + } + platform_set_drvdata(pdev, pwm_dev); + dev_dbg(&pdev->dev, "pwm probe successful\n"); + return ret; +} + +static int __devexit ab8500_pwm_remove(struct platform_device *pdev) +{ + struct pwm_device *pwm_dev = platform_get_drvdata(pdev); + + pwm_device_unregister(pwm_dev); + dev_dbg(&pdev->dev, "pwm driver removed\n"); + kfree(pwm_dev->pops); + kfree(pwm_dev); + return 0; +} + +static struct platform_driver ab8500_pwm_driver = { + .driver = { + .name = "ab8500-pwm", + .owner = THIS_MODULE, + }, + .probe = ab8500_pwm_probe, + .remove = __devexit_p(ab8500_pwm_remove), +}; + +static int __init ab8500_pwm_init(void) +{ + return platform_driver_register(&ab8500_pwm_driver); +} + +static void __exit ab8500_pwm_exit(void) +{ + platform_driver_unregister(&ab8500_pwm_driver); +} + +subsys_initcall(ab8500_pwm_init); +module_exit(ab8500_pwm_exit); +MODULE_AUTHOR("Arun MURTHY "); +MODULE_DESCRIPTION("AB8500 Pulse Width Modulation Driver"); +MODULE_ALIAS("AB8500 PWM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pwm/pwm-twl6040.c b/drivers/pwm/pwm-twl6040.c new file mode 100644 index 0000000..b78324b --- /dev/null +++ b/drivers/pwm/pwm-twl6040.c @@ -0,0 +1,196 @@ +/* + * twl6030_pwm.c + * Driver for PHOENIX (TWL6030) Pulse Width Modulator + * + * Copyright (C) 2010 Texas Instruments + * Author: Hemanth V + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#define LED_PWM_CTRL1 0xF4 +#define LED_PWM_CTRL2 0xF5 + +/* Max value for CTRL1 register */ +#define PWM_CTRL1_MAX 255 + +/* Pull down disable */ +#define PWM_CTRL2_DIS_PD (1 << 6) + +/* Current control 2.5 milli Amps */ +#define PWM_CTRL2_CURR_02 (2 << 4) + +/* LED supply source */ +#define PWM_CTRL2_SRC_VAC (1 << 2) + +/* LED modes */ +#define PWM_CTRL2_MODE_HW (0 << 0) +#define PWM_CTRL2_MODE_SW (1 << 0) +#define PWM_CTRL2_MODE_DIS (2 << 0) + +#define PWM_CTRL2_MODE_MASK 0x3 + +int twl6030_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + u8 duty_cycle; + int ret = 0; + + if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) + return -EINVAL; + + duty_cycle = (duty_ns * PWM_CTRL1_MAX) / period_ns; + + ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, duty_cycle, LED_PWM_CTRL1); + + if (ret < 0) { + pr_err("%s: Failed to configure PWM, Error %d\n", + pwm->label, ret); + return ret; + } + return 0; +} + +int twl6030_pwm_enable(struct pwm_device *pwm) +{ + u8 val; + int ret = 0; + + ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); + if (ret < 0) { + pr_err("%s: Failed to enable PWM, Error %d\n", pwm->label, ret); + return ret; + } + + /* Change mode to software control */ + val &= ~PWM_CTRL2_MODE_MASK; + val |= PWM_CTRL2_MODE_SW; + + ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); + if (ret < 0) { + pr_err("%s: Failed to enable PWM, Error %d\n", pwm->label, ret); + return ret; + } + + twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); + return 0; +} + +int twl6030_pwm_disable(struct pwm_device *pwm) +{ + u8 val; + int ret = 0; + + ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); + if (ret < 0) { + pr_err("%s: Failed to disable PWM, Error %d\n", + pwm->label, ret); + return ret; + } + + val &= ~PWM_CTRL2_MODE_MASK; + val |= PWM_CTRL2_MODE_HW; + + ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); + if (ret < 0) { + pr_err("%s: Failed to disable PWM, Error %d\n", + pwm->label, ret); + } + return ret; +} + +static int __devinit twl6030_pwm_probe(struct platform_device *pdev) +{ + struct pwm_device *pwm; + struct pwm_ops *pops; + int ret; + u8 val; + + pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (pwm == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pwm); + return -ENOMEM; + } + + pops->pwm_config = twl6030_pwm_config; + pops->pwm_enable = twl6030_pwm_enable; + pops->pwm_disable = twl6030_pwm_disable; + pops->name = &pdev->name; + pwm->dev = &pdev->dev; + pwm->pwm_id = pdev->id; + pwm->pops = pops; + ret = pwm_device_register(pwm); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + kfree(pwm); + kfree(pops); + return ret; + } + platform_set_drvdata(pdev, pwm); + /* Configure PWM */ + val = PWM_CTRL2_DIS_PD | PWM_CTRL2_CURR_02 | PWM_CTRL2_SRC_VAC | + PWM_CTRL2_MODE_HW; + + ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to configure PWM, Error %d\n", ret); + return ret; + } + dev_dbg(&pdev->dev, "pwm probe successful\n"); + return ret; +} + +static int __devexit twl6030_pwm_remove(struct platform_device *pdev) +{ + struct pwm_device *pwm = platform_get_drvdata(pdev); + + pwm_device_unregister(pwm); + kfree(pwm->pops); + kfree(pwm); + dev_dbg(&pdev->dev, "pwm driver removed\n"); + return 0; +} + +static struct platform_driver twl6030_pwm_driver = { + .driver = { + .name = "twl6030_pwm", + .owner = THIS_MODULE, + }, + .probe = twl6030_pwm_probe, + .remove = __devexit_p(twl6030_pwm_remove), +}; + +static int __init twl6030_pwm_init(void) +{ + return platform_driver_register(&twl6030_pwm_driver); +} + +static void __exit twl6030_pwm_deinit(void) +{ + platform_driver_unregister(&twl6030_pwm_driver); +} + +subsys_initcall(twl6030_pwm_init); +module_exit(twl6030_pwm_deinit); -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 09:47:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 09:47:58 +0200 (CEST) Received: from eu1sys200aog116.obsmtp.com ([207.126.144.141]:42501 "EHLO eu1sys200aog116.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491951Ab0I1Hr1 (ORCPT ); Tue, 28 Sep 2010 09:47:27 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob116.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGdRHE3V4jMpp3sqOWWIWN/rHutnDlf@postini.com; Tue, 28 Sep 2010 07:47:27 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C5375152; Tue, 28 Sep 2010 07:41:24 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 984475C3; Tue, 28 Sep 2010 07:41:23 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 5DA0824C2F9; Tue, 28 Sep 2010 09:41:18 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 09:41:22 +0200 From: Arun Murthy To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Cc: , , , , , Subject: [PATCH 7/7] pwm: Modify backlight and led Kconfig aligning to pwm core Date: Tue, 28 Sep 2010 13:10:48 +0530 Message-ID: <1285659648-21409-8-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27843 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22120 Content-Length: 1887 Lines: 60 PWM based backlight and led driver will not be calling the pwm drivers through the pwm core driver and hence adding dependancy on the same. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/leds/Kconfig | 2 +- drivers/pwm/Kconfig | 2 -- drivers/video/backlight/Kconfig | 2 +- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index e411262..eba388f 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -244,7 +244,7 @@ config LEDS_DAC124S085 config LEDS_PWM tristate "PWM driven LED Support" - depends on HAVE_PWM + depends on HAVE_PWM || PWM_CORE help This option enables support for pwm driven LEDs diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e347365..1f8cbc0 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -17,7 +17,6 @@ if PWM_DEVICES config AB8500_PWM bool "AB8500 PWM support" depends on AB8500_CORE - select HAVE_PWM help This driver exports functions to enable/disble/config/free Pulse Width Modulation in the Analog Baseband Chip AB8500. @@ -26,7 +25,6 @@ config AB8500_PWM config TWL6030_PWM tristate "TWL6030 PWM (Pulse Width Modulator) Support" depends on TWL4030_CORE - select HAVE_PWM default n help Say yes here if you want support for TWL6030 PWM. diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index e54a337..73fc17b 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -217,7 +217,7 @@ config BACKLIGHT_CARILLO_RANCH config BACKLIGHT_PWM tristate "Generic PWM based Backlight Driver" - depends on HAVE_PWM + depends on HAVE_PWM || PWM_CORE help If you have a LCD backlight adjustable by PWM, say Y to enable this driver. -- 1.7.2.dirty From eric.y.miao@gmail.com Tue Sep 28 10:01:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:01:52 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:59415 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1IBt convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 10:01:49 +0200 Received: by iwn41 with SMTP id 41so1877059iwn.36 for ; Tue, 28 Sep 2010 01:01:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:in-reply-to :references:from:date:message-id:subject:to:cc:content-type :content-transfer-encoding; bh=GQorPI/iT8zE2mUyigczCZNbwdlqq87w1aFasDRthME=; b=DpW9I1kXYF7ec8isgNfI8STaMQP9/tO0+IKwNOf03+GKJUSPc2o444Q+43AStxNwNz bXB/0vwPKRYAkKX2vn72cBAGC98J0yC5ra4oO9LuQhcOL7bSmR8YrYyRgDcy68JmYpiw ykvf/E7L5L24ZrYsm0nrK7cYzJg8iGWrGR7ro= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=HGbwTC5LkQhDCMvu769U8FH9ZaheRAaD9ShietUjlbKC94MGm9TkCRxj1h2fRzN8Zw WbRPmbBghcnVU8IvjZG6ZTvJfHeDSIFjdvhyH9wbNOrQfHXP41FtK9CnMazdPrukIWul NET6B8iy0S7bn93uhrYnalBJf+6EYNr87k6Ao= Received: by 10.231.146.141 with SMTP id h13mr10314409ibv.1.1285660903500; Tue, 28 Sep 2010 01:01:43 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.199.141 with HTTP; Tue, 28 Sep 2010 01:01:22 -0700 (PDT) In-Reply-To: <1285659648-21409-4-git-send-email-arun.murthy@stericsson.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-4-git-send-email-arun.murthy@stericsson.com> From: Eric Miao Date: Tue, 28 Sep 2010 16:01:22 +0800 Message-ID: Subject: Re: [PATCH 3/7] leds: pwm: add a new element 'name' to platform data To: Arun Murthy Cc: linux@arm.linux.org.uk, grinberg@compulab.co.il, mike@compulab.co.il, robert.jarzmik@free.fr, marek.vasut@gmail.com, drwyrm@gmail.com, stefan@openezx.org, laforge@openezx.org, ospite@studenti.unina.it, philipp.zabel@gmail.com, mad_soft@inbox.ru, maz@misterjones.org, daniel@caiaq.de, haojian.zhuang@marvell.com, timur@freescale.com, ben-linux@fluff.org, support@simtec.co.uk, arnaud.patard@rtp-net.org, dgreenday@gmail.com, anarsoul@gmail.com, akpm@linux-foundation.org, mcuelenaere@gmail.com, kernel@pengutronix.de, andre.goddard@gmail.com, jkosina@suse.cz, tj@kernel.org, hsweeten@visionengravers.com, u.kleine-koenig@pengutronix.de, kgene.kim@samsung.com, ralf@linux-mips.org, lars@metafoo.de, dilinger@collabora.co.uk, mroth@nessie.de, randy.dunlap@oracle.com, lethal@linux-sh.org, rusty@rustcorp.com.au, damm@opensource.se, mst@redhat.com, rpurdie@rpsys.net, sguinot@lacie.co, sameo@linux.intel.com, broonie@opensource.wolfsonmicro.com, balajitk@ti.com, rnayak@ti.com, santosh.shilimkar@ti.com, hemanthv@ti.com, michael.hennerich@analog.com, vapier@gentoo.org, khali@linux-fr.org, jic23@cam.ac.uk, re.emese@gmail.com, linux@simtec.co.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linus.walleij@stericsson.com, mattias.wallin@stericsson.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-archive-position: 27844 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: eric.y.miao@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22127 Content-Length: 1766 Lines: 46 On Tue, Sep 28, 2010 at 3:40 PM, Arun Murthy wrote: > A new element 'name' is added to pwm led platform data structure. > This is required to identify the pwm device. I cannot see what this name is used for? > > Signed-off-by: Arun Murthy > Acked-by: Linus Walleij > --- >  drivers/leds/leds-pwm.c  |    4 +++- >  include/linux/leds_pwm.h |    1 + >  2 files changed, 4 insertions(+), 1 deletions(-) > > diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c > index da3fa8d..8da2be6 100644 > --- a/drivers/leds/leds-pwm.c > +++ b/drivers/leds/leds-pwm.c > @@ -66,8 +66,10 @@ static int led_pwm_probe(struct platform_device *pdev) >                cur_led = &pdata->leds[i]; >                led_dat = &leds_data[i]; > > +               if (!pdata->name) > +                       pdata->name = cur_led->name; >                led_dat->pwm = pwm_request(cur_led->pwm_id, > -                               cur_led->name); > +                               pdata->name); >                if (IS_ERR(led_dat->pwm)) { >                        dev_err(&pdev->dev, "unable to request PWM %d\n", >                                        cur_led->pwm_id); > diff --git a/include/linux/leds_pwm.h b/include/linux/leds_pwm.h > index 33a0711..7a847a0 100644 > --- a/include/linux/leds_pwm.h > +++ b/include/linux/leds_pwm.h > @@ -16,6 +16,7 @@ struct led_pwm { >  struct led_pwm_platform_data { >        int                     num_leds; >        struct led_pwm  *leds; > +       char *name; >  }; > >  #endif > -- > 1.7.2.dirty > > From anarsoul@gmail.com Tue Sep 28 10:16:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:16:10 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:57331 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1IQG (ORCPT ); Tue, 28 Sep 2010 10:16:06 +0200 Received: by ewy9 with SMTP id 9so2048031ewy.36 for ; Tue, 28 Sep 2010 01:16:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:message-id; bh=+1bhSm8bVhkwqfbc96FVTbmg6cruYzKFhzU+V9l9k+o=; b=GFLu5iJZEerDp+2q9RCpieGpCFHRX6pvaElVffDbxoK15rOZrR+C+Vm3+6clWLZmIN Eo+n9lc6msP3XGPiRjhRofb0CgcuV+Shr5r5Sfq4voc7cqrigCC1rmUq9hieSxgOgM9T rsj9WIQ55/FrlPNZ5qPOousnHjgOyTWFsc3rc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding:message-id; b=B+f7zuexsvmbhDnuoF6DHOup0y8D3n8G4PruiAS7Ijybteb2oBuuRVQTgVGyxPERTO xfSfKOCT0JbUmHPwuROracPkZ28VPyoYBGI+j+jYqdf6cF+rhJCiPa06PFXa7AXUp/80 bBOnR8s7AqkrwhZBzg9AuXaDJWuKWMCKozHVM= Received: by 10.213.34.83 with SMTP id k19mr7170777ebd.34.1285661760913; Tue, 28 Sep 2010 01:16:00 -0700 (PDT) Received: from anarsoul-laptop.localnet ([86.57.155.118]) by mx.google.com with ESMTPS id v8sm10045584eeh.2.2010.09.28.01.15.53 (version=SSLv3 cipher=RC4-MD5); Tue, 28 Sep 2010 01:15:55 -0700 (PDT) From: Vasily Khoruzhick To: Arun Murthy Subject: Re: [PATCH 1/7] pwm: Add pwm core driver Date: Tue, 28 Sep 2010 11:14:30 +0300 User-Agent: KMail/1.13.5 (Linux/2.6.35-gentoo-r8-anarsoul; KDE/4.5.1; i686; ; ) Cc: eric.y.miao@gmail.com, linux@arm.linux.org.uk, grinberg@compulab.co.il, mike@compulab.co.il, robert.jarzmik@free.fr, marek.vasut@gmail.com, drwyrm@gmail.com, stefan@openezx.org, laforge@openezx.org, ospite@studenti.unina.it, philipp.zabel@gmail.com, mad_soft@inbox.ru, maz@misterjones.org, daniel@caiaq.de, haojian.zhuang@marvell.com, timur@freescale.com, ben-linux@fluff.org, support@simtec.co.uk, arnaud.patard@rtp-net.org, dgreenday@gmail.com, akpm@linux-foundation.org, mcuelenaere@gmail.com, kernel@pengutronix.de, andre.goddard@gmail.com, jkosina@suse.cz, tj@kernel.org, hsweeten@visionengravers.com, u.kleine-koenig@pengutronix.de, kgene.kim@samsung.com, ralf@linux-mips.org, lars@metafoo.de, dilinger@collabora.co.uk, mroth@nessie.de, randy.dunlap@oracle.com, lethal@linux-sh.org, rusty@rustcorp.com.au, damm@opensource.se, mst@redhat.com, rpurdie@rpsys.net, sguinot@lacie.co, sameo@linux.intel.com, broonie@opensource.wolfsonmicro.com, balajitk@ti.com, rnayak@ti.com, santosh.shilimkar@ti.com, hemanthv@ti.com, michael.hennerich@analog.com, vapier@gentoo.org, khali@linux-fr.org, jic23@cam.ac.uk, re.emese@gmail.com, linux@simtec.co.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linus.walleij@stericsson.com, mattias.wallin@stericsson.com References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> In-Reply-To: <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Message-Id: <201009281114.31223.anarsoul@gmail.com> X-archive-position: 27845 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anarsoul@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22139 Content-Length: 6961 Lines: 253 On 28 of September 2010 10:40:42 Arun Murthy wrote: > The existing pwm based led and backlight driver makes use of the > pwm(include/linux/pwm.h). So all the board specific pwm drivers will > be exposing the same set of function name as in include/linux/pwm.h. > As a result build fails. Which build fails? One with multi-SoC support? Please be more specific. > In order to overcome this issue all the pwm drivers must register to > some core pwm driver with function pointers for pwm operations (i.e > pwm_config, pwm_enable, pwm_disable). > > The clients of pwm device will have to call pwm_request, wherein > they will get the pointer to struct pwm_ops. This structure include > function pointers for pwm_config, pwm_enable and pwm_disable. > > Signed-off-by: Arun Murthy > Acked-by: Linus Walleij > --- > drivers/Kconfig | 2 + > drivers/Makefile | 1 + > drivers/pwm/Kconfig | 16 ++++++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-core.c | 129 > ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pwm.h | > 12 ++++- > 6 files changed, 160 insertions(+), 1 deletions(-) > create mode 100644 drivers/pwm/Kconfig > create mode 100644 drivers/pwm/Makefile > create mode 100644 drivers/pwm/pwm-core.c > > diff --git a/drivers/Kconfig b/drivers/Kconfig > index a2b902f..e042f27 100644 > --- a/drivers/Kconfig > +++ b/drivers/Kconfig > @@ -111,4 +111,6 @@ source "drivers/xen/Kconfig" > source "drivers/staging/Kconfig" > > source "drivers/platform/Kconfig" > + > +source "drivers/pwm/Kconfig" > endmenu > diff --git a/drivers/Makefile b/drivers/Makefile > index 4ca727d..0061ec4 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -116,3 +116,4 @@ obj-$(CONFIG_STAGING) += staging/ > obj-y += platform/ > obj-y += ieee802154/ > obj-y += vbus/ > +obj-$(CONFIG_PWM_DEVICES) += pwm/ > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > new file mode 100644 > index 0000000..5d10106 > --- /dev/null > +++ b/drivers/pwm/Kconfig > @@ -0,0 +1,16 @@ > +# > +# PWM devices > +# > + > +menuconfig PWM_DEVICES > + bool "PWM devices" > + default y > + ---help--- > + Say Y here to get to see options for device drivers from various > + different categories. This option alone does not add any kernel code. > + > + If you say N, all options in this submenu will be skipped and disabled. > + > +if PWM_DEVICES > + > +endif # PWM_DEVICES > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > new file mode 100644 > index 0000000..552f969 > --- /dev/null > +++ b/drivers/pwm/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_PWM_DEVICES) += pwm-core.o > diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c > new file mode 100644 > index 0000000..b84027a > --- /dev/null > +++ b/drivers/pwm/pwm-core.c > @@ -0,0 +1,129 @@ > +/* > + * Copyright (C) ST-Ericsson SA 2010 > + * > + * License Terms: GNU General Public License v2 > + * Author: Arun R Murthy > + */ > +#include > +#include > +#include > +#include > +#include > +#include > + > +struct pwm_device { > + struct pwm_ops *pops; > + int pwm_id; > +}; > + > +struct pwm_dev_info { > + struct pwm_device *pwm_dev; > + struct list_head list; > +}; > +static struct pwm_dev_info *di; > + > +DECLARE_RWSEM(pwm_list_lock); > + > +void __deprecated pwm_free(struct pwm_device *pwm) > +{ > +} Why pwm_free is marked __deprecated? What is its successor? > + > +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > +{ > + return pwm->pops->pwm_config(pwm, duty_ns, period_ns); > +} > +EXPORT_SYMBOL(pwm_config); > + > +int pwm_enable(struct pwm_device *pwm) > +{ > + return pwm->pops->pwm_enable(pwm); > +} > +EXPORT_SYMBOL(pwm_enable); > + > +void pwm_disable(struct pwm_device *pwm) > +{ > + pwm->pops->pwm_disable(pwm); > +} > +EXPORT_SYMBOL(pwm_disable); > + > +int pwm_device_register(struct pwm_device *pwm_dev) > +{ > + struct pwm_dev_info *pwm; > + > + down_write(&pwm_list_lock); > + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); > + if (!pwm) { > + up_write(&pwm_list_lock); > + return -ENOMEM; > + } > + pwm->pwm_dev = pwm_dev; > + list_add_tail(&pwm->list, &di->list); > + up_write(&pwm_list_lock); > + > + return 0; > +} > +EXPORT_SYMBOL(pwm_device_register); > + > +int pwm_device_unregister(struct pwm_device *pwm_dev) > +{ > + struct pwm_dev_info *tmp; > + struct list_head *pos, *tmp_lst; > + > + down_write(&pwm_list_lock); > + list_for_each_safe(pos, tmp_lst, &di->list) { > + tmp = list_entry(pos, struct pwm_dev_info, list); > + if (tmp->pwm_dev == pwm_dev) { > + list_del(pos); > + kfree(tmp); > + up_write(&pwm_list_lock); > + return 0; > + } > + } > + up_write(&pwm_list_lock); > + return -ENOENT; > +} > +EXPORT_SYMBOL(pwm_device_unregister); > + > +struct pwm_device *pwm_request(int pwm_id, const char *name) > +{ > + struct pwm_dev_info *pwm; > + struct list_head *pos; > + > + down_read(&pwm_list_lock); > + list_for_each(pos, &di->list) { > + pwm = list_entry(pos, struct pwm_dev_info, list); > + if ((!strcmp(pwm->pwm_dev->pops->name, name)) && > + (pwm->pwm_dev->pwm_id == pwm_id)) { > + up_read(&pwm_list_lock); > + return pwm->pwm_dev; > + } > + } > + up_read(&pwm_list_lock); > + return ERR_PTR(-ENOENT); > +} > +EXPORT_SYMBOL(pwm_request); > + > +static int __init pwm_init(void) > +{ > + struct pwm_dev_info *pwm; > + > + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); > + if (!pwm) > + return -ENOMEM; > + INIT_LIST_HEAD(&pwm->list); > + di = pwm; > + return 0; > +} > + > +static void __exit pwm_exit(void) > +{ > + kfree(di); > +} > + > +subsys_initcall(pwm_init); > +module_exit(pwm_exit); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Arun R Murthy"); > +MODULE_ALIAS("core:pwm"); > +MODULE_DESCRIPTION("Core pwm driver"); > diff --git a/include/linux/pwm.h b/include/linux/pwm.h > index 7c77575..6e7da1f 100644 > --- a/include/linux/pwm.h > +++ b/include/linux/pwm.h > @@ -3,6 +3,13 @@ > > struct pwm_device; > > +struct pwm_ops { > + int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int period_ns); > + int (*pwm_enable)(struct pwm_device *pwm); > + int (*pwm_disable)(struct pwm_device *pwm); > + char *name; > +}; > + > /* > * pwm_request - request a PWM device > */ > @@ -11,7 +18,7 @@ struct pwm_device *pwm_request(int pwm_id, const char > *label); /* > * pwm_free - free a PWM device > */ > -void pwm_free(struct pwm_device *pwm); > +void __deprecated pwm_free(struct pwm_device *pwm); > > /* > * pwm_config - change a PWM device configuration > @@ -28,4 +35,7 @@ int pwm_enable(struct pwm_device *pwm); > */ > void pwm_disable(struct pwm_device *pwm); > > +int pwm_device_register(struct pwm_device *pwm_dev); > +int pwm_device_unregister(struct pwm_device *pwm_dev); > + > #endif /* __LINUX_PWM_H */ From arun.murthy@stericsson.com Tue Sep 28 10:39:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:39:44 +0200 (CEST) Received: from eu1sys200aog114.obsmtp.com ([207.126.144.137]:54418 "EHLO eu1sys200aog114.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1Ijk (ORCPT ); Tue, 28 Sep 2010 10:39:40 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob114.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGpXLbe34iOL7YAyQiVTctRRCUMdRKP@postini.com; Tue, 28 Sep 2010 08:39:40 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CE13597; Tue, 28 Sep 2010 08:37:09 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CE5D61BC8; Tue, 28 Sep 2010 08:37:04 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 6F04BA80BF; Tue, 28 Sep 2010 10:36:58 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm003.EQ1STM.local ([10.230.100.1]) with mapi; Tue, 28 Sep 2010 10:36:30 +0200 From: Arun MURTHY To: Eric Miao Cc: "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "anarsoul@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 10:36:29 +0200 Subject: RE: [PATCH 3/7] leds: pwm: add a new element 'name' to platform data Thread-Topic: [PATCH 3/7] leds: pwm: add a new element 'name' to platform data Thread-Index: Acte47A/2gbEiNzRRGuHZJjrYfXSgwAA/DCQ Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-4-git-send-email-arun.murthy@stericsson.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 X-archive-position: 27846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22158 Content-Length: 693 Lines: 9 PiBPbiBUdWUsIFNlcCAyOCwgMjAxMCBhdCAzOjQwIFBNLCBBcnVuIE11cnRoeQ0KPiA8YXJ1bi5t dXJ0aHlAc3Rlcmljc3Nvbi5jb20+IHdyb3RlOg0KPiA+IEEgbmV3IGVsZW1lbnQgJ25hbWUnIGlz IGFkZGVkIHRvIHB3bSBsZWQgcGxhdGZvcm0gZGF0YSBzdHJ1Y3R1cmUuDQo+ID4gVGhpcyBpcyBy ZXF1aXJlZCB0byBpZGVudGlmeSB0aGUgcHdtIGRldmljZS4NCj4gDQo+IEkgY2Fubm90IHNlZSB3 aGF0IHRoaXMgbmFtZSBpcyB1c2VkIGZvcj8NCj4gDQpUaGlzIG5hbWUgaXMgcmVmZXJlbmNlZCBp biBsZWRzLXB3bS5jIGFuZCBwd21fYmwuYy4gSXQgaXMgcGFzc2VkIGFzIGEgcGFyYW1ldGVyIGlu IHB3bV9yZXF1ZXN0KCkgZnVuY3Rpb24uKHBsZWFzZSByZWZlciB0aGUgbmV4dCBwYXRjaCBpLmUg UEFUSEMgNC83KQ0KSXQgaXMgdXNlZCB0byBpZGVudGlmeSB0aGUgcHdtIGRyaXZlciBieSBuYW1l Lg0KDQpUaGFua3MgYW5kIFJlZ2FyZHMsDQpBcnVuIFIgTXVydGh5DQotLS0tLS0tLS0tLS0tDQo= From arun.murthy@stericsson.com Tue Sep 28 10:40:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:40:52 +0200 (CEST) Received: from eu1sys200aog105.obsmtp.com ([207.126.144.119]:48495 "EHLO eu1sys200aog105.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491950Ab0I1Ikq convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 10:40:46 +0200 Received: from source ([167.4.1.35]) (using TLSv1) by eu1sys200aob105.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGpuTm1VwWt0fxDTPDLOueyCHEHnjvF@postini.com; Tue, 28 Sep 2010 08:40:45 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.80.115]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 5DB0BDA; Tue, 28 Sep 2010 08:35:14 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 5E7962F5; Tue, 28 Sep 2010 08:38:29 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 7DC0AA80A9; Tue, 28 Sep 2010 10:38:24 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm003.EQ1STM.local ([10.230.100.1]) with mapi; Tue, 28 Sep 2010 10:38:27 +0200 From: Arun MURTHY To: Vasily Khoruzhick Cc: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 10:38:26 +0200 Subject: RE: [PATCH 1/7] pwm: Add pwm core driver Thread-Topic: [PATCH 1/7] pwm: Add pwm core driver Thread-Index: Acte5whwPqrutDCHTLy9xp7mcp09gAAATmFw Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <201009281114.31223.anarsoul@gmail.com> In-Reply-To: <201009281114.31223.anarsoul@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22161 Content-Length: 620 Lines: 21 > On 28 of September 2010 10:40:42 Arun Murthy wrote: > > The existing pwm based led and backlight driver makes use of the > > pwm(include/linux/pwm.h). So all the board specific pwm drivers will > > be exposing the same set of function name as in include/linux/pwm.h. > > As a result build fails. > > Which build fails? One with multi-SoC support? Please be more specific. Sure will add this in v2. > > +void __deprecated pwm_free(struct pwm_device *pwm) > > +{ > > +} > > Why pwm_free is marked __deprecated? What is its successor? This function is to be removed. Thanks and Regards, Arun R Murthy ------------- From anarsoul@gmail.com Tue Sep 28 10:48:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:48:55 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:52191 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1Isv (ORCPT ); Tue, 28 Sep 2010 10:48:51 +0200 Received: by bwz19 with SMTP id 19so5478521bwz.36 for ; Tue, 28 Sep 2010 01:48:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:message-id; bh=AncmpYgrnyE5ZzhwIYTiD8W4S54tK6jVhT0VurwK03U=; b=egQi47Dnb+cOCXShsZFNC59fUNumHJQ3tZ16Jf506IMEGiFAZckqM4SNhmQ5gw6Af5 LEC13f/Psmw/stfscOSwDBvqZZuWEF8TAPVQkfjJp0lAQ8EvJQinEW2fZSZZUEYVBJbV cZ9AG8BrLSHE+aBZh6+qCiE4jQYpFnQNVo7wc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding:message-id; b=MgUBfxusFExesGK51bfp/L1rOsx5WqvkneUrpzKRLoxNi08Xmpm/ZRxHcZsw9igvF+ nBPJIjyjysrLFsTvoLH5gTgEHNywq032a3ixmdqBKzlsWvEORJlhVOkgBx9/j0sk3T9v moFkY9oymgzHdS0v45hriUdlp6v44aEOrk7tE= Received: by 10.204.54.199 with SMTP id r7mr2555640bkg.106.1285663725484; Tue, 28 Sep 2010 01:48:45 -0700 (PDT) Received: from anarsoul-laptop.localnet ([86.57.155.118]) by mx.google.com with ESMTPS id 24sm5332253bkr.19.2010.09.28.01.48.38 (version=SSLv3 cipher=RC4-MD5); Tue, 28 Sep 2010 01:48:43 -0700 (PDT) From: Vasily Khoruzhick To: Arun MURTHY Subject: Re: [PATCH 1/7] pwm: Add pwm core driver Date: Tue, 28 Sep 2010 11:47:20 +0300 User-Agent: KMail/1.13.5 (Linux/2.6.35-gentoo-r8-anarsoul; KDE/4.5.1; i686; ; ) Cc: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <201009281114.31223.anarsoul@gmail.com> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201009281147.20871.anarsoul@gmail.com> X-archive-position: 27848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anarsoul@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22165 Content-Length: 212 Lines: 11 On 28 of September 2010 11:38:26 Arun MURTHY wrote: > > > > Why pwm_free is marked __deprecated? What is its successor? > > This function is to be removed. What should be used as replacement? Regards Vasily From hemanthv@ti.com Tue Sep 28 10:51:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:51:04 +0200 (CEST) Received: from arroyo.ext.ti.com ([192.94.94.40]:36183 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1IvC (ORCPT ); Tue, 28 Sep 2010 10:51:02 +0200 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o8S8oGsX021111 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 28 Sep 2010 03:50:18 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o8S8nv5f027993; Tue, 28 Sep 2010 03:49:58 -0500 (CDT) Received: from 10.24.255.18 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Tue, 28 Sep 2010 14:20:15 +0530 (IST) Message-ID: <63731.10.24.255.18.1285663815.squirrel@dbdmail.itg.ti.com> In-Reply-To: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <201009281114.31223.anarsoul@gmail.com> Date: Tue, 28 Sep 2010 14:20:15 +0530 (IST) Subject: RE: [PATCH 1/7] pwm: Add pwm core driver From: "Hemanth V" To: "Arun MURTHY" Cc: "Vasily Khoruzhick" , "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "Linus WALLEIJ" , "Mattias WALLIN" User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT X-Priority: 3 (Normal) Importance: Normal X-archive-position: 27849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hemanthv@ti.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22169 Content-Length: 530 Lines: 16 > >> On 28 of September 2010 10:40:42 Arun Murthy wrote: >> > The existing pwm based led and backlight driver makes use of the >> > pwm(include/linux/pwm.h). So all the board specific pwm drivers will >> > be exposing the same set of function name as in include/linux/pwm.h. >> > As a result build fails. >> >> Which build fails? One with multi-SoC support? Please be more specific. > Sure will add this in v2. > Could you clarify for the benefit of all, which specific issues you are trying to address with this patch series From lars@metafoo.de Tue Sep 28 10:55:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:55:31 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:48079 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1Iz1 (ORCPT ); Tue, 28 Sep 2010 10:55:27 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 0A1E1F38; Tue, 28 Sep 2010 10:55:20 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id MC2RyLGMoOPB; Tue, 28 Sep 2010 10:55:18 +0200 (CEST) Received: from [192.168.0.213] (e177160142.adsl.alicedsl.de [85.177.160.142]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 7C597F31; Tue, 28 Sep 2010 10:54:21 +0200 (CEST) Message-ID: <4CA1AD2B.8000905@metafoo.de> Date: Tue, 28 Sep 2010 10:54:03 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Arun Murthy CC: eric.y.miao@gmail.com, linux@arm.linux.org.uk, grinberg@compulab.co.il, mike@compulab.co.il, robert.jarzmik@free.fr, marek.vasut@gmail.com, drwyrm@gmail.com, stefan@openezx.org, laforge@openezx.org, ospite@studenti.unina.it, philipp.zabel@gmail.com, mad_soft@inbox.ru, maz@misterjones.org, daniel@caiaq.de, haojian.zhuang@marvell.com, timur@freescale.com, ben-linux@fluff.org, support@simtec.co.uk, arnaud.patard@rtp-net.org, dgreenday@gmail.com, anarsoul@gmail.com, akpm@linux-foundation.org, mcuelenaere@gmail.com, kernel@pengutronix.de, andre.goddard@gmail.com, jkosina@suse.cz, tj@kernel.org, hsweeten@visionengravers.com, u.kleine-koenig@pengutronix.de, kgene.kim@samsung.com, ralf@linux-mips.org, dilinger@collabora.co.uk, mroth@nessie.de, randy.dunlap@oracle.com, lethal@linux-sh.org, rusty@rustcorp.com.au, damm@opensource.se, mst@redhat.com, rpurdie@rpsys.net, sguinot@lacie.co, sameo@linux.intel.com, broonie@opensource.wolfsonmicro.com, balajitk@ti.com, rnayak@ti.com, santosh.shilimkar@ti.com, hemanthv@ti.com, michael.hennerich@analog.com, vapier@gentoo.org, khali@linux-fr.org, jic23@cam.ac.uk, re.emese@gmail.com, linux@simtec.co.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linus.walleij@stericsson.com, mattias.wallin@stericsson.com Subject: Re: [PATCH 1/7] pwm: Add pwm core driver References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> In-Reply-To: <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 27850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22175 Content-Length: 7221 Lines: 264 Arun Murthy wrote: > The existing pwm based led and backlight driver makes use of the > pwm(include/linux/pwm.h). So all the board specific pwm drivers will > be exposing the same set of function name as in include/linux/pwm.h. > As a result build fails. > > In order to overcome this issue all the pwm drivers must register to > some core pwm driver with function pointers for pwm operations (i.e > pwm_config, pwm_enable, pwm_disable). > > The clients of pwm device will have to call pwm_request, wherein > they will get the pointer to struct pwm_ops. This structure include > function pointers for pwm_config, pwm_enable and pwm_disable. > > Signed-off-by: Arun Murthy > Acked-by: Linus Walleij > --- > drivers/Kconfig | 2 + > drivers/Makefile | 1 + > drivers/pwm/Kconfig | 16 ++++++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-core.c | 129 ++++++++++++++++++++++++++++++++++++++++++++++++ > include/linux/pwm.h | 12 ++++- > 6 files changed, 160 insertions(+), 1 deletions(-) > create mode 100644 drivers/pwm/Kconfig > create mode 100644 drivers/pwm/Makefile > create mode 100644 drivers/pwm/pwm-core.c > > diff --git a/drivers/Kconfig b/drivers/Kconfig > index a2b902f..e042f27 100644 > --- a/drivers/Kconfig > +++ b/drivers/Kconfig > @@ -111,4 +111,6 @@ source "drivers/xen/Kconfig" > source "drivers/staging/Kconfig" > > source "drivers/platform/Kconfig" > + > +source "drivers/pwm/Kconfig" > endmenu > diff --git a/drivers/Makefile b/drivers/Makefile > index 4ca727d..0061ec4 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -116,3 +116,4 @@ obj-$(CONFIG_STAGING) += staging/ > obj-y += platform/ > obj-y += ieee802154/ > obj-y += vbus/ > +obj-$(CONFIG_PWM_DEVICES) += pwm/ > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > new file mode 100644 > index 0000000..5d10106 > --- /dev/null > +++ b/drivers/pwm/Kconfig > @@ -0,0 +1,16 @@ > +# > +# PWM devices > +# > + > +menuconfig PWM_DEVICES > + bool "PWM devices" > + default y > + ---help--- > + Say Y here to get to see options for device drivers from various > + different categories. This option alone does not add any kernel code. > + > + If you say N, all options in this submenu will be skipped and disabled. > + Shouldn't PWM_DEVICES select HAVE_PWM? > +if PWM_DEVICES > + > +endif # PWM_DEVICES > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > new file mode 100644 > index 0000000..552f969 > --- /dev/null > +++ b/drivers/pwm/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_PWM_DEVICES) += pwm-core.o > diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c > new file mode 100644 > index 0000000..b84027a > --- /dev/null > +++ b/drivers/pwm/pwm-core.c > @@ -0,0 +1,129 @@ > +/* > + * Copyright (C) ST-Ericsson SA 2010 > + * > + * License Terms: GNU General Public License v2 > + * Author: Arun R Murthy > + */ > +#include > +#include > +#include > +#include > +#include > +#include > + > +struct pwm_device { > + struct pwm_ops *pops; > + int pwm_id; > +}; > + > +struct pwm_dev_info { > + struct pwm_device *pwm_dev; > + struct list_head list; > +}; > +static struct pwm_dev_info *di; Why not embed the list head into pwm_device. That would certainly make pwm_device_unregister much simpler. > + > +DECLARE_RWSEM(pwm_list_lock); > + > +void __deprecated pwm_free(struct pwm_device *pwm) > +{ > +} > + > +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > +{ > + return pwm->pops->pwm_config(pwm, duty_ns, period_ns); > +} > +EXPORT_SYMBOL(pwm_config); > + > +int pwm_enable(struct pwm_device *pwm) > +{ > + return pwm->pops->pwm_enable(pwm); > +} > +EXPORT_SYMBOL(pwm_enable); > + > +void pwm_disable(struct pwm_device *pwm) > +{ > + pwm->pops->pwm_disable(pwm); > +} > +EXPORT_SYMBOL(pwm_disable); > + > +int pwm_device_register(struct pwm_device *pwm_dev) > +{ > + struct pwm_dev_info *pwm; > + > + down_write(&pwm_list_lock); > + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); > + if (!pwm) { > + up_write(&pwm_list_lock); > + return -ENOMEM; > + } > + pwm->pwm_dev = pwm_dev; > + list_add_tail(&pwm->list, &di->list); > + up_write(&pwm_list_lock); > + I guess you only need to lock the list when accessing the list and adding the new pwm_dev. > + return 0; > +} > +EXPORT_SYMBOL(pwm_device_register); > + > +int pwm_device_unregister(struct pwm_device *pwm_dev) > +{ > + struct pwm_dev_info *tmp; > + struct list_head *pos, *tmp_lst; > + > + down_write(&pwm_list_lock); > + list_for_each_safe(pos, tmp_lst, &di->list) { > + tmp = list_entry(pos, struct pwm_dev_info, list); > + if (tmp->pwm_dev == pwm_dev) { > + list_del(pos); > + kfree(tmp); > + up_write(&pwm_list_lock); > + return 0; > + } > + } > + up_write(&pwm_list_lock); > + return -ENOENT; > +} > +EXPORT_SYMBOL(pwm_device_unregister); > + > +struct pwm_device *pwm_request(int pwm_id, const char *name) > +{ > + struct pwm_dev_info *pwm; > + struct list_head *pos; > + > + down_read(&pwm_list_lock); > + list_for_each(pos, &di->list) { > + pwm = list_entry(pos, struct pwm_dev_info, list); > + if ((!strcmp(pwm->pwm_dev->pops->name, name)) && > + (pwm->pwm_dev->pwm_id == pwm_id)) { > + up_read(&pwm_list_lock); > + return pwm->pwm_dev; > + } > + } > + up_read(&pwm_list_lock); > + return ERR_PTR(-ENOENT); > +} > +EXPORT_SYMBOL(pwm_request); > + > +static int __init pwm_init(void) > +{ > + struct pwm_dev_info *pwm; > + > + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); > + if (!pwm) > + return -ENOMEM; > + INIT_LIST_HEAD(&pwm->list); > + di = pwm; > + return 0; > +} > + > +static void __exit pwm_exit(void) > +{ > + kfree(di); > +} > + > +subsys_initcall(pwm_init); > +module_exit(pwm_exit); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Arun R Murthy"); > +MODULE_ALIAS("core:pwm"); > +MODULE_DESCRIPTION("Core pwm driver"); > diff --git a/include/linux/pwm.h b/include/linux/pwm.h > index 7c77575..6e7da1f 100644 > --- a/include/linux/pwm.h > +++ b/include/linux/pwm.h > @@ -3,6 +3,13 @@ > > struct pwm_device; > > +struct pwm_ops { > + int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int period_ns); > + int (*pwm_enable)(struct pwm_device *pwm); > + int (*pwm_disable)(struct pwm_device *pwm); > + char *name; > +}; > + Shouldn't name be part of the pwm_device? That would allow the ops to be shared between different devices. > /* > * pwm_request - request a PWM device > */ > @@ -11,7 +18,7 @@ struct pwm_device *pwm_request(int pwm_id, const char *label); > /* > * pwm_free - free a PWM device > */ > -void pwm_free(struct pwm_device *pwm); > +void __deprecated pwm_free(struct pwm_device *pwm); > > /* > * pwm_config - change a PWM device configuration > @@ -28,4 +35,7 @@ int pwm_enable(struct pwm_device *pwm); > */ > void pwm_disable(struct pwm_device *pwm); > > +int pwm_device_register(struct pwm_device *pwm_dev); > +int pwm_device_unregister(struct pwm_device *pwm_dev); > + > #endif /* __LINUX_PWM_H */ It might be also a good idea to add a device class for pwm devices. From lars@metafoo.de Tue Sep 28 10:58:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:58:47 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:48396 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491955Ab0I1I6m (ORCPT ); Tue, 28 Sep 2010 10:58:42 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 0EFECF68; Tue, 28 Sep 2010 10:58:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id YpChXuJHkfJR; Tue, 28 Sep 2010 10:58:33 +0200 (CEST) Received: from [192.168.0.213] (e177160142.adsl.alicedsl.de [85.177.160.142]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 45BFAF64; Tue, 28 Sep 2010 10:58:27 +0200 (CEST) Message-ID: <4CA1AE21.8070306@metafoo.de> Date: Tue, 28 Sep 2010 10:58:09 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Arun Murthy CC: eric.y.miao@gmail.com, linux@arm.linux.org.uk, grinberg@compulab.co.il, mike@compulab.co.il, robert.jarzmik@free.fr, marek.vasut@gmail.com, drwyrm@gmail.com, stefan@openezx.org, laforge@openezx.org, ospite@studenti.unina.it, philipp.zabel@gmail.com, mad_soft@inbox.ru, maz@misterjones.org, daniel@caiaq.de, haojian.zhuang@marvell.com, timur@freescale.com, ben-linux@fluff.org, support@simtec.co.uk, arnaud.patard@rtp-net.org, dgreenday@gmail.com, anarsoul@gmail.com, akpm@linux-foundation.org, mcuelenaere@gmail.com, kernel@pengutronix.de, andre.goddard@gmail.com, jkosina@suse.cz, tj@kernel.org, hsweeten@visionengravers.com, u.kleine-koenig@pengutronix.de, kgene.kim@samsung.com, ralf@linux-mips.org, dilinger@collabora.co.uk, mroth@nessie.de, randy.dunlap@oracle.com, lethal@linux-sh.org, rusty@rustcorp.com.au, damm@opensource.se, mst@redhat.com, rpurdie@rpsys.net, sguinot@lacie.co, sameo@linux.intel.com, broonie@opensource.wolfsonmicro.com, balajitk@ti.com, rnayak@ti.com, santosh.shilimkar@ti.com, hemanthv@ti.com, michael.hennerich@analog.com, vapier@gentoo.org, khali@linux-fr.org, jic23@cam.ac.uk, re.emese@gmail.com, linux@simtec.co.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linus.walleij@stericsson.com, mattias.wallin@stericsson.com Subject: Re: [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core driver References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-5-git-send-email-arun.murthy@stericsson.com> In-Reply-To: <1285659648-21409-5-git-send-email-arun.murthy@stericsson.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 27851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22176 Content-Length: 42281 Lines: 1541 Arun Murthy wrote: > pwm-core: make the driver visible for ARM only > > Align ab8500 pwm with the pwm core driver > Align twl6030 pwm driver with pwm core driver > Align Freescale mxc pwm driver with pwm core driver > Align pxa pwm driver with pwm core driver > Align samsung(s3c) pwm driver with pwm core driver > > mips-jz4740: pwm: Align with new pwm core driver > > PWM core driver has been added and has been enabled only for ARM > platform. The same can be utilised for mips also. > Please align with the pwm core driver(drivers/pwm-core.c). Is there any reason for artificially limiting it to ARM? > > Signed-off-by: Arun Murthy > Acked-by: Linus Walleij > --- > arch/arm/plat-mxc/pwm.c | 166 +++++++++++++----------------- > arch/arm/plat-pxa/pwm.c | 210 ++++++++++++++++++-------------------- > arch/arm/plat-samsung/pwm.c | 235 +++++++++++++++++++------------------------ > arch/mips/jz4740/pwm.c | 2 +- > drivers/mfd/twl-core.c | 13 +++ > drivers/mfd/twl6030-pwm.c | 111 +++++++++++++------- > drivers/misc/ab8500-pwm.c | 87 +++++++--------- > drivers/pwm/Kconfig | 1 + > drivers/pwm/pwm-core.c | 9 +-- > include/linux/pwm.h | 21 ++++- > 10 files changed, 418 insertions(+), 437 deletions(-) > > diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c > index c36f263..b259ba9 100644 > --- a/arch/arm/plat-mxc/pwm.c > +++ b/arch/arm/plat-mxc/pwm.c > @@ -38,22 +38,16 @@ > > > > -struct pwm_device { > - struct list_head node; > - struct platform_device *pdev; > - > - const char *label; > +struct mxc_pwm_device { > struct clk *clk; > - > int clk_enabled; > void __iomem *mmio_base; > - > - unsigned int use_count; > - unsigned int pwm_id; > }; > > -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > +static int mxc_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > { > + struct mxc_pwm_device *mxc_pwm = pwm->data; > + > if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) > return -EINVAL; > > @@ -62,7 +56,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > unsigned long period_cycles, duty_cycles, prescale; > u32 cr; > > - c = clk_get_rate(pwm->clk); > + c = clk_get_rate(mxc_pwm->clk); > c = c * period_ns; > do_div(c, 1000000000); > period_cycles = c; > @@ -74,8 +68,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > do_div(c, period_ns); > duty_cycles = c; > > - writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); > - writel(period_cycles, pwm->mmio_base + MX3_PWMPR); > + writel(duty_cycles, mxc_pwm->mmio_base + MX3_PWMSAR); > + writel(period_cycles, mxc_pwm->mmio_base + MX3_PWMPR); > > cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN; > > @@ -84,7 +78,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > else > cr |= MX3_PWMCR_CLKSRC_IPG_HIGH; > > - writel(cr, pwm->mmio_base + MX3_PWMCR); > + writel(cr, mxc_pwm->mmio_base + MX3_PWMCR); > } else if (cpu_is_mx1() || cpu_is_mx21()) { > /* The PWM subsystem allows for exact frequencies. However, > * I cannot connect a scope on my device to the PWM line and > @@ -102,110 +96,76 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > * both the prescaler (/1 .. /128) and then by CLKSEL > * (/2 .. /16). > */ > - u32 max = readl(pwm->mmio_base + MX1_PWMP); > + u32 max = readl(mxc_pwm->mmio_base + MX1_PWMP); > u32 p = max * duty_ns / period_ns; > - writel(max - p, pwm->mmio_base + MX1_PWMS); > + writel(max - p, mxc_pwm->mmio_base + MX1_PWMS); > } else { > BUG(); > } > > return 0; > } > -EXPORT_SYMBOL(pwm_config); > > -int pwm_enable(struct pwm_device *pwm) > +static int mxc_pwm_enable(struct pwm_device *pwm) > { > + struct mxc_pwm_device *mxc_pwm = pwm->data; > int rc = 0; > > - if (!pwm->clk_enabled) { > - rc = clk_enable(pwm->clk); > + if (!mxc_pwm->clk_enabled) { > + rc = clk_enable(mxc_pwm->clk); > if (!rc) > - pwm->clk_enabled = 1; > + mxc_pwm->clk_enabled = 1; > } > return rc; > } > -EXPORT_SYMBOL(pwm_enable); > - > -void pwm_disable(struct pwm_device *pwm) > -{ > - writel(0, pwm->mmio_base + MX3_PWMCR); > - > - if (pwm->clk_enabled) { > - clk_disable(pwm->clk); > - pwm->clk_enabled = 0; > - } > -} > -EXPORT_SYMBOL(pwm_disable); > - > -static DEFINE_MUTEX(pwm_lock); > -static LIST_HEAD(pwm_list); > > -struct pwm_device *pwm_request(int pwm_id, const char *label) > +static int mxc_pwm_disable(struct pwm_device *pwm) > { > - struct pwm_device *pwm; > - int found = 0; > + struct mxc_pwm_device *mxc_pwm = pwm->data; > > - mutex_lock(&pwm_lock); > + writel(0, mxc_pwm->mmio_base + MX3_PWMCR); > > - list_for_each_entry(pwm, &pwm_list, node) { > - if (pwm->pwm_id == pwm_id) { > - found = 1; > - break; > - } > + if (mxc_pwm->clk_enabled) { > + clk_disable(mxc_pwm->clk); > + mxc_pwm->clk_enabled = 0; > } > - > - if (found) { > - if (pwm->use_count == 0) { > - pwm->use_count++; > - pwm->label = label; > - } else > - pwm = ERR_PTR(-EBUSY); > - } else > - pwm = ERR_PTR(-ENOENT); > - > - mutex_unlock(&pwm_lock); > - return pwm; > -} > -EXPORT_SYMBOL(pwm_request); > - > -void pwm_free(struct pwm_device *pwm) > -{ > - mutex_lock(&pwm_lock); > - > - if (pwm->use_count) { > - pwm->use_count--; > - pwm->label = NULL; > - } else > - pr_warning("PWM device already freed\n"); > - > - mutex_unlock(&pwm_lock); > + return 0; > } > -EXPORT_SYMBOL(pwm_free); > > static int __devinit mxc_pwm_probe(struct platform_device *pdev) > { > + struct mxc_pwm_device *mxc_pwm; > struct pwm_device *pwm; > + struct pwm_ops *pops; > struct resource *r; > int ret = 0; > > + mxc_pwm = kzalloc(sizeof(struct mxc_pwm_device), GFP_KERNEL); > + if (mxc_pwm == NULL) { > + dev_err(&pdev->dev, "failed to allocate memory\n"); > + return -ENOMEM; > + } > pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); > if (pwm == NULL) { > dev_err(&pdev->dev, "failed to allocate memory\n"); > - return -ENOMEM; > + ret = -ENOMEM; > + goto err_free1; > + } > + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); > + if (pops == NULL) { > + dev_err(&pdev->dev, "failed to allocate memory\n"); > + ret = -ENOMEM; > + goto err_free2; > } > > - pwm->clk = clk_get(&pdev->dev, "pwm"); > + mxc_pwm->clk = clk_get(&pdev->dev, "pwm"); > > - if (IS_ERR(pwm->clk)) { > - ret = PTR_ERR(pwm->clk); > - goto err_free; > + if (IS_ERR(mxc_pwm->clk)) { > + ret = PTR_ERR(mxc_pwm->clk); > + goto err_free3; > } > > - pwm->clk_enabled = 0; > - > - pwm->use_count = 0; > - pwm->pwm_id = pdev->id; > - pwm->pdev = pdev; > + mxc_pwm->clk_enabled = 0; > > r = platform_get_resource(pdev, IORESOURCE_MEM, 0); > if (r == NULL) { > @@ -221,16 +181,27 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) > goto err_free_clk; > } > > - pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); > - if (pwm->mmio_base == NULL) { > + mxc_pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); > + if (mxc_pwm->mmio_base == NULL) { > dev_err(&pdev->dev, "failed to ioremap() registers\n"); > ret = -ENODEV; > goto err_free_mem; > } > > - mutex_lock(&pwm_lock); > - list_add_tail(&pwm->node, &pwm_list); > - mutex_unlock(&pwm_lock); > + pops->pwm_config = mxc_pwm_config; > + pops->pwm_enable = mxc_pwm_enable; > + pops->pwm_disable = mxc_pwm_disable; > + pops->name = pdev->name; > + > + pwm->pwm_id = pdev->id; > + pwm->dev = &pdev->dev; > + pwm->pops = pops; > + pwm->data = mxc_pwm; > + ret = pwm_device_register(pwm); > + if (ret < 0) { > + dev_err(&pdev->dev, "failed to register pwm device\n"); > + goto err_free_mem; > + } > > platform_set_drvdata(pdev, pwm); > return 0; > @@ -238,33 +209,38 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) > err_free_mem: > release_mem_region(r->start, r->end - r->start + 1); > err_free_clk: > - clk_put(pwm->clk); > -err_free: > + clk_put(mxc_pwm->clk); > +err_free3: > + kfree(pops); > +err_free2: > kfree(pwm); > +err_free1: > + kfree(mxc_pwm); > return ret; > } > > static int __devexit mxc_pwm_remove(struct platform_device *pdev) > { > struct pwm_device *pwm; > + struct mxc_pwm_device *mxc_pwm; > struct resource *r; > > pwm = platform_get_drvdata(pdev); > if (pwm == NULL) > return -ENODEV; > + mxc_pwm = pwm->data; > > - mutex_lock(&pwm_lock); > - list_del(&pwm->node); > - mutex_unlock(&pwm_lock); > - > - iounmap(pwm->mmio_base); > + pwm_device_unregister(pwm); > + iounmap(mxc_pwm->mmio_base); > > r = platform_get_resource(pdev, IORESOURCE_MEM, 0); > release_mem_region(r->start, r->end - r->start + 1); > > - clk_put(pwm->clk); > + clk_put(mxc_pwm->clk); > > + kfree(pwm->pops); > kfree(pwm); > + kfree(mxc_pwm); > return 0; > } > > diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c > index ef32686..1de902a 100644 > --- a/arch/arm/plat-pxa/pwm.c > +++ b/arch/arm/plat-pxa/pwm.c > @@ -43,33 +43,27 @@ MODULE_DEVICE_TABLE(platform, pwm_id_table); > #define PWMCR_SD (1 << 6) > #define PWMDCR_FD (1 << 10) > > -struct pwm_device { > - struct list_head node; > - struct pwm_device *secondary; > - struct platform_device *pdev; > - > - const char *label; > +struct pxa_pwm_device { > + struct pxa_pwm_device *sec; > struct clk *clk; > int clk_enabled; > void __iomem *mmio_base; > - > - unsigned int use_count; > - unsigned int pwm_id; > }; > > /* > * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE > * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE > */ > -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > +int pxa_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > { > unsigned long long c; > unsigned long period_cycles, prescale, pv, dc; > + struct pxa_pwm_device *pxa_pwm = pwm->data; > > if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) > return -EINVAL; > > - c = clk_get_rate(pwm->clk); > + c = clk_get_rate(pxa_pwm->clk); > c = c * period_ns; > do_div(c, 1000000000); > period_cycles = c; > @@ -90,94 +84,45 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > /* NOTE: the clock to PWM has to be enabled first > * before writing to the registers > */ > - clk_enable(pwm->clk); > - __raw_writel(prescale, pwm->mmio_base + PWMCR); > - __raw_writel(dc, pwm->mmio_base + PWMDCR); > - __raw_writel(pv, pwm->mmio_base + PWMPCR); > - clk_disable(pwm->clk); > + clk_enable(pxa_pwm->clk); > + __raw_writel(prescale, pxa_pwm->mmio_base + PWMCR); > + __raw_writel(dc, pxa_pwm->mmio_base + PWMDCR); > + __raw_writel(pv, pxa_pwm->mmio_base + PWMPCR); > + clk_disable(pxa_pwm->clk); > > return 0; > } > -EXPORT_SYMBOL(pwm_config); > > -int pwm_enable(struct pwm_device *pwm) > +int pxa_pwm_enable(struct pwm_device *pwm) > { > + struct pxa_pwm_device *pxa_pwm = pwm->data; > int rc = 0; > > - if (!pwm->clk_enabled) { > - rc = clk_enable(pwm->clk); > + if (!pxa_pwm->clk_enabled) { > + rc = clk_enable(pxa_pwm->clk); > if (!rc) > - pwm->clk_enabled = 1; > + pxa_pwm->clk_enabled = 1; > } > return rc; > } > -EXPORT_SYMBOL(pwm_enable); > > -void pwm_disable(struct pwm_device *pwm) > +int pxa_pwm_disable(struct pwm_device *pwm) > { > - if (pwm->clk_enabled) { > - clk_disable(pwm->clk); > - pwm->clk_enabled = 0; > - } > -} > -EXPORT_SYMBOL(pwm_disable); > - > -static DEFINE_MUTEX(pwm_lock); > -static LIST_HEAD(pwm_list); > + struct pxa_pwm_device *pxa_pwm = pwm->data; > > -struct pwm_device *pwm_request(int pwm_id, const char *label) > -{ > - struct pwm_device *pwm; > - int found = 0; > - > - mutex_lock(&pwm_lock); > - > - list_for_each_entry(pwm, &pwm_list, node) { > - if (pwm->pwm_id == pwm_id) { > - found = 1; > - break; > - } > + if (pxa_pwm->clk_enabled) { > + clk_disable(pxa_pwm->clk); > + pxa_pwm->clk_enabled = 0; > } > - > - if (found) { > - if (pwm->use_count == 0) { > - pwm->use_count++; > - pwm->label = label; > - } else > - pwm = ERR_PTR(-EBUSY); > - } else > - pwm = ERR_PTR(-ENOENT); > - > - mutex_unlock(&pwm_lock); > - return pwm; > -} > -EXPORT_SYMBOL(pwm_request); > - > -void pwm_free(struct pwm_device *pwm) > -{ > - mutex_lock(&pwm_lock); > - > - if (pwm->use_count) { > - pwm->use_count--; > - pwm->label = NULL; > - } else > - pr_warning("PWM device already freed\n"); > - > - mutex_unlock(&pwm_lock); > -} > -EXPORT_SYMBOL(pwm_free); > - > -static inline void __add_pwm(struct pwm_device *pwm) > -{ > - mutex_lock(&pwm_lock); > - list_add_tail(&pwm->node, &pwm_list); > - mutex_unlock(&pwm_lock); > + return 0; > } > > static int __devinit pwm_probe(struct platform_device *pdev) > { > const struct platform_device_id *id = platform_get_device_id(pdev); > + struct pxa_pwm_device *pxa_pwm, *pxa_pwm_sec; > struct pwm_device *pwm, *secondary = NULL; > + struct pwm_ops *pops; > struct resource *r; > int ret = 0; > > @@ -186,17 +131,26 @@ static int __devinit pwm_probe(struct platform_device *pdev) > dev_err(&pdev->dev, "failed to allocate memory\n"); > return -ENOMEM; > } > + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); > + if (pops == NULL) { > + dev_err(&pdev->dev, "failed to allocate memory\n"); > + kfree(pwm); > + return -ENOMEM; > + } > + pxa_pwm = kzalloc(sizeof(struct pxa_pwm_device), GFP_KERNEL); > + if (pxa_pwm == NULL) { > + dev_err(&pdev->dev, "failed to allocate memory\n"); > + kfree(pops); > + kfree(pwm); > + return -ENOMEM; > + } > > - pwm->clk = clk_get(&pdev->dev, NULL); > - if (IS_ERR(pwm->clk)) { > - ret = PTR_ERR(pwm->clk); > + pxa_pwm->clk = clk_get(&pdev->dev, NULL); > + if (IS_ERR(pxa_pwm->clk)) { > + ret = PTR_ERR(pxa_pwm->clk); > goto err_free; > } > - pwm->clk_enabled = 0; > - > - pwm->use_count = 0; > - pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id; > - pwm->pdev = pdev; > + pxa_pwm->clk_enabled = 0; > > r = platform_get_resource(pdev, IORESOURCE_MEM, 0); > if (r == NULL) { > @@ -212,69 +166,105 @@ static int __devinit pwm_probe(struct platform_device *pdev) > goto err_free_clk; > } > > - pwm->mmio_base = ioremap(r->start, resource_size(r)); > - if (pwm->mmio_base == NULL) { > + pxa_pwm->mmio_base = ioremap(r->start, resource_size(r)); > + if (pxa_pwm->mmio_base == NULL) { > dev_err(&pdev->dev, "failed to ioremap() registers\n"); > ret = -ENODEV; > goto err_free_mem; > } > > + pops->pwm_config = pxa_pwm_config; > + pops->pwm_enable = pxa_pwm_enable; > + pops->pwm_disable = pxa_pwm_disable; > + pops->name = pdev->name; > + > + pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id; > + pwm->dev = &pdev->dev; > + pwm->pops = pops; > + pwm->data = pxa_pwm; > + > + ret = pwm_device_register(pwm); > + if (ret < 0) { > + dev_err(&pdev->dev, "failed to register pwm device\n"); > + goto err_free_mem; > + } > + > if (id->driver_data & HAS_SECONDARY_PWM) { > secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); > if (secondary == NULL) { > ret = -ENOMEM; > - goto err_free_mem; > + goto err_pwm; > + } > + pxa_pwm_sec = kzalloc(sizeof(struct pxa_pwm_device), > + GFP_KERNEL); > + if (pxa_pwm_sec == NULL) { > + ret = -ENOMEM; > + goto err_free_mem2; > } > > *secondary = *pwm; > - pwm->secondary = secondary; > + *pxa_pwm_sec = *pxa_pwm; > + pxa_pwm->sec = pxa_pwm_sec; > > /* registers for the second PWM has offset of 0x10 */ > - secondary->mmio_base = pwm->mmio_base + 0x10; > + pxa_pwm_sec->mmio_base = pxa_pwm->mmio_base + 0x10; > secondary->pwm_id = pdev->id + 2; > - } > + secondary->data = pxa_pwm_sec; > > - __add_pwm(pwm); > - if (secondary) > - __add_pwm(secondary); > + ret = pwm_device_register(secondary); > + if (ret < 0) { > + dev_err(&pdev->dev, "failed to register pwm device\n"); > + goto err_free_mem3; > + } > + } > > platform_set_drvdata(pdev, pwm); > return 0; > - > +err_free_mem3: > + kfree(pxa_pwm_sec); > +err_free_mem2: > + kfree(secondary); > +err_pwm: > + pwm_device_unregister(pwm); > err_free_mem: > release_mem_region(r->start, resource_size(r)); > err_free_clk: > - clk_put(pwm->clk); > + clk_put(pxa_pwm->clk); > err_free: > + kfree(pxa_pwm); > + kfree(pops); > kfree(pwm); > return ret; > } > > static int __devexit pwm_remove(struct platform_device *pdev) > { > - struct pwm_device *pwm; > + struct pwm_device *pwm, *secondary; > + struct pxa_pwm_device *pxa_pwm, *pxa_pwm_sec; > struct resource *r; > > pwm = platform_get_drvdata(pdev); > if (pwm == NULL) > return -ENODEV; > - > - mutex_lock(&pwm_lock); > - > - if (pwm->secondary) { > - list_del(&pwm->secondary->node); > - kfree(pwm->secondary); > + pxa_pwm = pwm->data; > + secondary = pwm_request((pdev->id + 2), pdev->name); > + pxa_pwm_sec = secondary->data; > + > + pwm_device_unregister(pwm); > + iounmap(pxa_pwm->mmio_base); > + if (secondary) { > + pwm_device_unregister(secondary); > + iounmap(pxa_pwm->mmio_base); > + kfree(pxa_pwm_sec); > + kfree(secondary); > } > > - list_del(&pwm->node); > - mutex_unlock(&pwm_lock); > - > - iounmap(pwm->mmio_base); > - > r = platform_get_resource(pdev, IORESOURCE_MEM, 0); > release_mem_region(r->start, resource_size(r)); > > - clk_put(pwm->clk); > + clk_put(pxa_pwm->clk); > + kfree(pxa_pwm); > + kfree(pwm->pops); > kfree(pwm); > return 0; > } > diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c > index 2eeb49f..63fba01 100644 > --- a/arch/arm/plat-samsung/pwm.c > +++ b/arch/arm/plat-samsung/pwm.c > @@ -26,25 +26,19 @@ > #include > #include > > -struct pwm_device { > - struct list_head list; > +struct s3c_pwm_device { > struct platform_device *pdev; > > struct clk *clk_div; > struct clk *clk; > - const char *label; > > unsigned int period_ns; > unsigned int duty_ns; > > unsigned char tcon_base; > unsigned char running; > - unsigned char use_count; > - unsigned char pwm_id; > }; > > -#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) > - > static struct clk *clk_scaler[2]; > > /* Standard setup for a timer block. */ > @@ -78,108 +72,61 @@ struct platform_device s3c_device_timer[] = { > [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, > }; > > -static inline int pwm_is_tdiv(struct pwm_device *pwm) > +static inline int pwm_is_tdiv(struct s3c_pwm_device *s3c_pwm) > { > - return clk_get_parent(pwm->clk) == pwm->clk_div; > + return clk_get_parent(s3c_pwm->clk) == s3c_pwm->clk_div; > } > > -static DEFINE_MUTEX(pwm_lock); > -static LIST_HEAD(pwm_list); > +#define pwm_tcon_start(s3c_pwm) (1 << (s3c_pwm->tcon_base + 0)) > +#define pwm_tcon_invert(s3c_pwm) (1 << (s3c_pwm->tcon_base + 2)) > +#define pwm_tcon_autoreload(s3c_pwm) (1 << (s3c_pwm->tcon_base + 3)) > +#define pwm_tcon_manulupdate(s3c_pwm) (1 << (s3c_pwm->tcon_base + 1)) > > -struct pwm_device *pwm_request(int pwm_id, const char *label) > -{ > - struct pwm_device *pwm; > - int found = 0; > - > - mutex_lock(&pwm_lock); > - > - list_for_each_entry(pwm, &pwm_list, list) { > - if (pwm->pwm_id == pwm_id) { > - found = 1; > - break; > - } > - } > - > - if (found) { > - if (pwm->use_count == 0) { > - pwm->use_count = 1; > - pwm->label = label; > - } else > - pwm = ERR_PTR(-EBUSY); > - } else > - pwm = ERR_PTR(-ENOENT); > - > - mutex_unlock(&pwm_lock); > - return pwm; > -} > - > -EXPORT_SYMBOL(pwm_request); > - > - > -void pwm_free(struct pwm_device *pwm) > -{ > - mutex_lock(&pwm_lock); > - > - if (pwm->use_count) { > - pwm->use_count--; > - pwm->label = NULL; > - } else > - printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id); > - > - mutex_unlock(&pwm_lock); > -} > - > -EXPORT_SYMBOL(pwm_free); > - > -#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) > -#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) > -#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) > -#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) > - > -int pwm_enable(struct pwm_device *pwm) > +int s3c_pwm_enable(struct pwm_device *pwm) > { > unsigned long flags; > unsigned long tcon; > + struct s3c_pwm_device *s3c_pwm = pwm->data; > > local_irq_save(flags); > > tcon = __raw_readl(S3C2410_TCON); > - tcon |= pwm_tcon_start(pwm); > + tcon |= pwm_tcon_start(s3c_pwm); > __raw_writel(tcon, S3C2410_TCON); > > local_irq_restore(flags); > > - pwm->running = 1; > + s3c_pwm->running = 1; > return 0; > } > > -EXPORT_SYMBOL(pwm_enable); > - > -void pwm_disable(struct pwm_device *pwm) > +int s3c_pwm_disable(struct pwm_device *pwm) > { > unsigned long flags; > unsigned long tcon; > + struct s3c_pwm_device *s3c_pwm = pwm->data; > > local_irq_save(flags); > > tcon = __raw_readl(S3C2410_TCON); > - tcon &= ~pwm_tcon_start(pwm); > + tcon &= ~pwm_tcon_start(s3c_pwm); > __raw_writel(tcon, S3C2410_TCON); > > local_irq_restore(flags); > > - pwm->running = 0; > + s3c_pwm->running = 0; > + return 0; > } > > -EXPORT_SYMBOL(pwm_disable); > - > -static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) > +static unsigned long pwm_calc_tin(struct pwm_device *pwm, > + unsigned long freq) > { > unsigned long tin_parent_rate; > unsigned int div; > + struct s3c_pwm_device *s3c_pwm = pwm->data; > > - tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div)); > - pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate); > + tin_parent_rate = clk_get_rate(clk_get_parent(s3c_pwm->clk_div)); > + dev_dbg(pwm->dev, "tin parent at %lu\n", tin_parent_rate); > > for (div = 2; div <= 16; div *= 2) { > if ((tin_parent_rate / (div << 16)) < freq) > @@ -191,7 +138,7 @@ static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) > > #define NS_IN_HZ (1000000000UL) > > -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > +int s3c_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > { > unsigned long tin_rate; > unsigned long tin_ns; > @@ -200,6 +147,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > unsigned long tcon; > unsigned long tcnt; > long tcmp; > + struct s3c_pwm_device *s3c_pwm = pwm->data; > > /* We currently avoid using 64bit arithmetic by using the > * fact that anything faster than 1Hz is easily representable > @@ -211,8 +159,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > if (duty_ns > period_ns) > return -EINVAL; > > - if (period_ns == pwm->period_ns && > - duty_ns == pwm->duty_ns) > + if (period_ns == s3c_pwm->period_ns && > + duty_ns == s3c_pwm->duty_ns) > return 0; > > /* The TCMP and TCNT can be read without a lock, they're not > @@ -223,26 +171,26 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > > period = NS_IN_HZ / period_ns; > > - pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n", > + dev_dbg(pwm->dev, "duty_ns=%d, period_ns=%d (%lu)\n", > duty_ns, period_ns, period); > > /* Check to see if we are changing the clock rate of the PWM */ > > - if (pwm->period_ns != period_ns) { > - if (pwm_is_tdiv(pwm)) { > + if (s3c_pwm->period_ns != period_ns) { > + if (pwm_is_tdiv(s3c_pwm)) { > tin_rate = pwm_calc_tin(pwm, period); > - clk_set_rate(pwm->clk_div, tin_rate); > + clk_set_rate(s3c_pwm->clk_div, tin_rate); > } else > - tin_rate = clk_get_rate(pwm->clk); > + tin_rate = clk_get_rate(s3c_pwm->clk); > > - pwm->period_ns = period_ns; > + s3c_pwm->period_ns = period_ns; > > - pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate); > + dev_dbg(pwm->dev, "tin_rate=%lu\n", tin_rate); > > tin_ns = NS_IN_HZ / tin_rate; > tcnt = period_ns / tin_ns; > } else > - tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk); > + tin_ns = NS_IN_HZ / clk_get_rate(s3c_pwm->clk); > > /* Note, counters count down */ > > @@ -253,7 +201,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > if (tcmp == tcnt) > tcmp--; > > - pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); > + dev_dbg(pwm->dev, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); > > if (tcmp < 0) > tcmp = 0; > @@ -266,11 +214,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id)); > > tcon = __raw_readl(S3C2410_TCON); > - tcon |= pwm_tcon_manulupdate(pwm); > - tcon |= pwm_tcon_autoreload(pwm); > + tcon |= pwm_tcon_manulupdate(s3c_pwm); > + tcon |= pwm_tcon_autoreload(s3c_pwm); > __raw_writel(tcon, S3C2410_TCON); > > - tcon &= ~pwm_tcon_manulupdate(pwm); > + tcon &= ~pwm_tcon_manulupdate(s3c_pwm); > __raw_writel(tcon, S3C2410_TCON); > > local_irq_restore(flags); > @@ -278,103 +226,122 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > return 0; > } > > -EXPORT_SYMBOL(pwm_config); > - > -static int pwm_register(struct pwm_device *pwm) > -{ > - pwm->duty_ns = -1; > - pwm->period_ns = -1; > - > - mutex_lock(&pwm_lock); > - list_add_tail(&pwm->list, &pwm_list); > - mutex_unlock(&pwm_lock); > - > - return 0; > -} > - > static int s3c_pwm_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > + struct s3c_pwm_device *s3c_pwm; > struct pwm_device *pwm; > + struct pwm_ops *pops; > unsigned long flags; > unsigned long tcon; > unsigned int id = pdev->id; > - int ret; > + int ret = 0; > > if (id == 4) { > dev_err(dev, "TIMER4 is currently not supported\n"); > return -ENXIO; > } > > + s3c_pwm = kzalloc(sizeof(struct s3c_pwm_device), GFP_KERNEL); > + if (s3c_pwm == NULL) { > + dev_err(dev, "failed to allocate pwm_device\n"); > + return -ENOMEM; > + } > + s3c_pwm->pdev = pdev; > pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); > if (pwm == NULL) { > dev_err(dev, "failed to allocate pwm_device\n"); > - return -ENOMEM; > + goto err_alloc; > + ret = -ENOMEM; > + } > + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); > + if (pops == NULL) { > + dev_err(dev, "failed to allocate memory\n"); > + goto err_alloc1; > + ret = -ENOMEM; > } > - > - pwm->pdev = pdev; > - pwm->pwm_id = id; > > /* calculate base of control bits in TCON */ > - pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; > + s3c_pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; > > - pwm->clk = clk_get(dev, "pwm-tin"); > - if (IS_ERR(pwm->clk)) { > + s3c_pwm->clk = clk_get(dev, "pwm-tin"); > + if (IS_ERR(s3c_pwm->clk)) { > dev_err(dev, "failed to get pwm tin clk\n"); > - ret = PTR_ERR(pwm->clk); > - goto err_alloc; > + ret = PTR_ERR(s3c_pwm->clk); > + goto err_alloc2; > } > > - pwm->clk_div = clk_get(dev, "pwm-tdiv"); > - if (IS_ERR(pwm->clk_div)) { > + s3c_pwm->clk_div = clk_get(dev, "pwm-tdiv"); > + if (IS_ERR(s3c_pwm->clk_div)) { > dev_err(dev, "failed to get pwm tdiv clk\n"); > - ret = PTR_ERR(pwm->clk_div); > + ret = PTR_ERR(s3c_pwm->clk_div); > goto err_clk_tin; > } > > local_irq_save(flags); > > tcon = __raw_readl(S3C2410_TCON); > - tcon |= pwm_tcon_invert(pwm); > + tcon |= pwm_tcon_invert(s3c_pwm); > __raw_writel(tcon, S3C2410_TCON); > > local_irq_restore(flags); > > + pops->pwm_config = s3c_pwm_config; > + pops->pwm_enable = s3c_pwm_enable; > + pops->pwm_disable = s3c_pwm_disable; > + pops->name = pdev->name; > + > + pwm->dev = dev; > + pwm->pwm_id = id; > + pwm->pops = pops; > + pwm->data = s3c_pwm; > > - ret = pwm_register(pwm); > + s3c_pwm->duty_ns = -1; > + s3c_pwm->period_ns = -1; > + ret = pwm_device_register(pwm); > if (ret) { > dev_err(dev, "failed to register pwm\n"); > goto err_clk_tdiv; > } > > - pwm_dbg(pwm, "config bits %02x\n", > - (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f); > + dev_dbg(dev, "config bits %02x\n", > + (__raw_readl(S3C2410_TCON) >> s3c_pwm->tcon_base) & 0x0f); > > dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", > - clk_get_rate(pwm->clk), > - clk_get_rate(pwm->clk_div), > - pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base); > + clk_get_rate(s3c_pwm->clk), > + clk_get_rate(s3c_pwm->clk_div), > + pwm_is_tdiv(s3c_pwm) ? "div" : "ext", s3c_pwm->tcon_base); > > platform_set_drvdata(pdev, pwm); > return 0; > > - err_clk_tdiv: > - clk_put(pwm->clk_div); > +err_clk_tdiv: > + clk_put(s3c_pwm->clk_div); > > - err_clk_tin: > - clk_put(pwm->clk); > +err_clk_tin: > + clk_put(s3c_pwm->clk); > > - err_alloc: > +err_alloc2: > + kfree(pops); > + > +err_alloc1: > kfree(pwm); > + > +err_alloc: > + kfree(s3c_pwm); > return ret; > } > > static int __devexit s3c_pwm_remove(struct platform_device *pdev) > { > struct pwm_device *pwm = platform_get_drvdata(pdev); > + struct s3c_pwm_device *s3c_pwm = pwm->data; > > - clk_put(pwm->clk_div); > - clk_put(pwm->clk); > + pwm_device_unregister(pwm); > + clk_put(s3c_pwm->clk_div); > + clk_put(s3c_pwm->clk); > + kfree(s3c_pwm); > + kfree(pwm->pops); > kfree(pwm); > > return 0; > @@ -384,13 +351,14 @@ static int __devexit s3c_pwm_remove(struct platform_device *pdev) > static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state) > { > struct pwm_device *pwm = platform_get_drvdata(pdev); > + struct s3c_pwm_device *s3c_pwm = pwm->data; > > /* No one preserve these values during suspend so reset them > * Otherwise driver leaves PWM unconfigured if same values > * passed to pwm_config > */ > - pwm->period_ns = 0; > - pwm->duty_ns = 0; > + s3c_pwm->period_ns = 0; > + s3c_pwm->duty_ns = 0; > > return 0; > } > @@ -398,11 +366,12 @@ static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state) > static int s3c_pwm_resume(struct platform_device *pdev) > { > struct pwm_device *pwm = platform_get_drvdata(pdev); > + struct s3c_pwm_device *s3c_pwm = pwm->data; > unsigned long tcon; > > /* Restore invertion */ > tcon = __raw_readl(S3C2410_TCON); > - tcon |= pwm_tcon_invert(pwm); > + tcon |= pwm_tcon_invert(s3c_pwm); > __raw_writel(tcon, S3C2410_TCON); > > return 0; > diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c > index a26a6fa..9f46767 100644 > --- a/arch/mips/jz4740/pwm.c > +++ b/arch/mips/jz4740/pwm.c > @@ -152,7 +152,7 @@ int pwm_enable(struct pwm_device *pwm) > return 0; > } > > -void pwm_disable(struct pwm_device *pwm) > +int pwm_disable(struct pwm_device *pwm) > { > uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); > > diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c > index b0f2c00..6a6ea41 100644 > --- a/drivers/mfd/twl-core.c > +++ b/drivers/mfd/twl-core.c > @@ -129,6 +129,12 @@ > #define twl_has_pwrbutton() false > #endif > > +#if defined CONFIG_TWL6030_PWM > +#define twl_has_pwm() true > +#else > +#define twl_has_pwm() false > +#endif > + > #define SUB_CHIP_ID0 0 > #define SUB_CHIP_ID1 1 > #define SUB_CHIP_ID2 2 > @@ -825,6 +831,13 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features) > if (IS_ERR(child)) > return PTR_ERR(child); > } > + if (twl_has_pwm()) { > + child = add_child(SUB_CHIP_ID2, "twl6030_pwm", > + NULL, 0, > + false, 0, 0); > + if (IS_ERR(child)) > + return PTR_ERR(child); > + } > > return 0; > } > diff --git a/drivers/mfd/twl6030-pwm.c b/drivers/mfd/twl6030-pwm.c > index 5d25bdc..b78324b 100644 > --- a/drivers/mfd/twl6030-pwm.c > +++ b/drivers/mfd/twl6030-pwm.c > @@ -20,8 +20,10 @@ > > #include > #include > -#include > #include > +#include > +#include > +#include > > #define LED_PWM_CTRL1 0xF4 > #define LED_PWM_CTRL2 0xF5 > @@ -45,15 +47,10 @@ > > #define PWM_CTRL2_MODE_MASK 0x3 > > -struct pwm_device { > - const char *label; > - unsigned int pwm_id; > -}; > - > -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > +int twl6030_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > { > u8 duty_cycle; > - int ret; > + int ret = 0; > > if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) > return -EINVAL; > @@ -69,12 +66,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > } > return 0; > } > -EXPORT_SYMBOL(pwm_config); > > -int pwm_enable(struct pwm_device *pwm) > +int twl6030_pwm_enable(struct pwm_device *pwm) > { > u8 val; > - int ret; > + int ret = 0; > > ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); > if (ret < 0) { > @@ -95,18 +91,17 @@ int pwm_enable(struct pwm_device *pwm) > twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); > return 0; > } > -EXPORT_SYMBOL(pwm_enable); > > -void pwm_disable(struct pwm_device *pwm) > +int twl6030_pwm_disable(struct pwm_device *pwm) > { > u8 val; > - int ret; > + int ret = 0; > > ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); > if (ret < 0) { > pr_err("%s: Failed to disable PWM, Error %d\n", > pwm->label, ret); > - return; > + return ret; > } > > val &= ~PWM_CTRL2_MODE_MASK; > @@ -116,48 +111,86 @@ void pwm_disable(struct pwm_device *pwm) > if (ret < 0) { > pr_err("%s: Failed to disable PWM, Error %d\n", > pwm->label, ret); > - return; > } > - return; > + return ret; > } > -EXPORT_SYMBOL(pwm_disable); > > -struct pwm_device *pwm_request(int pwm_id, const char *label) > +static int __devinit twl6030_pwm_probe(struct platform_device *pdev) > { > - u8 val; > - int ret; > struct pwm_device *pwm; > + struct pwm_ops *pops; > + int ret; > + u8 val; > > pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); > if (pwm == NULL) { > - pr_err("%s: failed to allocate memory\n", label); > - return NULL; > + dev_err(&pdev->dev, "failed to allocate memory\n"); > + return -ENOMEM; > + } > + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); > + if (pops == NULL) { > + dev_err(&pdev->dev, "failed to allocate memory\n"); > + kfree(pwm); > + return -ENOMEM; > } > > - pwm->label = label; > - pwm->pwm_id = pwm_id; > - > + pops->pwm_config = twl6030_pwm_config; > + pops->pwm_enable = twl6030_pwm_enable; > + pops->pwm_disable = twl6030_pwm_disable; > + pops->name = &pdev->name; > + pwm->dev = &pdev->dev; > + pwm->pwm_id = pdev->id; > + pwm->pops = pops; > + ret = pwm_device_register(pwm); > + if (ret < 0) { > + dev_err(&pdev->dev, "failed to register pwm device\n"); > + kfree(pwm); > + kfree(pops); > + return ret; > + } > + platform_set_drvdata(pdev, pwm); > /* Configure PWM */ > val = PWM_CTRL2_DIS_PD | PWM_CTRL2_CURR_02 | PWM_CTRL2_SRC_VAC | > - PWM_CTRL2_MODE_HW; > + PWM_CTRL2_MODE_HW; > > ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); > - > if (ret < 0) { > - pr_err("%s: Failed to configure PWM, Error %d\n", > - pwm->label, ret); > - > - kfree(pwm); > - return NULL; > + dev_err(&pdev->dev, "Failed to configure PWM, Error %d\n", ret); > + return ret; > } > - > - return pwm; > + dev_dbg(&pdev->dev, "pwm probe successful\n"); > + return ret; > } > -EXPORT_SYMBOL(pwm_request); > > -void pwm_free(struct pwm_device *pwm) > +static int __devexit twl6030_pwm_remove(struct platform_device *pdev) > { > - pwm_disable(pwm); > + struct pwm_device *pwm = platform_get_drvdata(pdev); > + > + pwm_device_unregister(pwm); > + kfree(pwm->pops); > kfree(pwm); > + dev_dbg(&pdev->dev, "pwm driver removed\n"); > + return 0; > } > -EXPORT_SYMBOL(pwm_free); > + > +static struct platform_driver twl6030_pwm_driver = { > + .driver = { > + .name = "twl6030_pwm", > + .owner = THIS_MODULE, > + }, > + .probe = twl6030_pwm_probe, > + .remove = __devexit_p(twl6030_pwm_remove), > +}; > + > +static int __init twl6030_pwm_init(void) > +{ > + return platform_driver_register(&twl6030_pwm_driver); > +} > + > +static void __exit twl6030_pwm_deinit(void) > +{ > + platform_driver_unregister(&twl6030_pwm_driver); > +} > + > +subsys_initcall(twl6030_pwm_init); > +module_exit(twl6030_pwm_deinit); > diff --git a/drivers/misc/ab8500-pwm.c b/drivers/misc/ab8500-pwm.c > index 54e3d05..d2b23b6 100644 > --- a/drivers/misc/ab8500-pwm.c > +++ b/drivers/misc/ab8500-pwm.c > @@ -23,16 +23,9 @@ > #define ENABLE_PWM 1 > #define DISABLE_PWM 0 > > -struct pwm_device { > - struct device *dev; > - struct list_head node; > - const char *label; > - unsigned int pwm_id; > -}; > - > static LIST_HEAD(pwm_list); > > -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > +int ab8500_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > { > int ret = 0; > unsigned int higher_val, lower_val; > @@ -60,23 +53,21 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > > return ret; > } > -EXPORT_SYMBOL(pwm_config); > > -int pwm_enable(struct pwm_device *pwm) > +int ab8500_pwm_enable(struct pwm_device *pwm) > { > int ret; > > ret = abx500_mask_and_set_register_interruptible(pwm->dev, > AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, > - 1 << (pwm->pwm_id-1), ENABLE_PWM); > + 1 << (pwm->pwm_id-1), 1 << (pwm->pwm_id-1)); > if (ret < 0) > dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", > pwm->label, ret); > return ret; > } > -EXPORT_SYMBOL(pwm_enable); > > -void pwm_disable(struct pwm_device *pwm) > +int ab8500_pwm_disable(struct pwm_device *pwm) > { > int ret; > > @@ -86,58 +77,56 @@ void pwm_disable(struct pwm_device *pwm) > if (ret < 0) > dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", > pwm->label, ret); > - return; > -} > -EXPORT_SYMBOL(pwm_disable); > - > -struct pwm_device *pwm_request(int pwm_id, const char *label) > -{ > - struct pwm_device *pwm; > - > - list_for_each_entry(pwm, &pwm_list, node) { > - if (pwm->pwm_id == pwm_id) { > - pwm->label = label; > - pwm->pwm_id = pwm_id; > - return pwm; > - } > - } > - > - return ERR_PTR(-ENOENT); > -} > -EXPORT_SYMBOL(pwm_request); > - > -void pwm_free(struct pwm_device *pwm) > -{ > - pwm_disable(pwm); > + return ret; > } > -EXPORT_SYMBOL(pwm_free); > > static int __devinit ab8500_pwm_probe(struct platform_device *pdev) > { > - struct pwm_device *pwm; > + int ret = 0; > + struct pwm_ops *pops; > + struct pwm_device *pwm_dev; > /* > * Nothing to be done in probe, this is required to get the > * device which is required for ab8500 read and write > */ > - pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); > - if (pwm == NULL) { > + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); > + if (pops == NULL) { > dev_err(&pdev->dev, "failed to allocate memory\n"); > return -ENOMEM; > } > - pwm->dev = &pdev->dev; > - pwm->pwm_id = pdev->id; > - list_add_tail(&pwm->node, &pwm_list); > - platform_set_drvdata(pdev, pwm); > - dev_dbg(pwm->dev, "pwm probe successful\n"); > - return 0; > + pwm_dev = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); > + if (pwm_dev == NULL) { > + dev_err(&pdev->dev, "failed to allocate memory\n"); > + kfree(pops); > + return -ENOMEM; > + } > + pops->pwm_config = ab8500_pwm_config; > + pops->pwm_enable = ab8500_pwm_enable; > + pops->pwm_disable = ab8500_pwm_disable; > + pops->name = "ab8500"; > + pwm_dev->dev = &pdev->dev; > + pwm_dev->pwm_id = pdev->id; > + pwm_dev->pops = pops; > + ret = pwm_device_register(pwm_dev); > + if (ret < 0) { > + dev_err(&pdev->dev, "failed to register pwm device\n"); > + kfree(pwm_dev); > + kfree(pops); > + return ret; > + } > + platform_set_drvdata(pdev, pwm_dev); > + dev_dbg(&pdev->dev, "pwm probe successful\n"); > + return ret; > } > > static int __devexit ab8500_pwm_remove(struct platform_device *pdev) > { > - struct pwm_device *pwm = platform_get_drvdata(pdev); > - list_del(&pwm->node); > + struct pwm_device *pwm_dev = platform_get_drvdata(pdev); > + > + pwm_device_unregister(pwm_dev); > dev_dbg(&pdev->dev, "pwm driver removed\n"); > - kfree(pwm); > + kfree(pwm_dev->pops); > + kfree(pwm_dev); > return 0; > } > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 5d10106..a88640c 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -4,6 +4,7 @@ > > menuconfig PWM_DEVICES > bool "PWM devices" > + depends on ARM > default y > ---help--- > Say Y here to get to see options for device drivers from various > diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c > index b84027a..3a0d426 100644 Why can't these changes be in the initial patch which adds pwm-core? > --- a/drivers/pwm/pwm-core.c > +++ b/drivers/pwm/pwm-core.c > @@ -11,11 +11,6 @@ > #include > #include > > -struct pwm_device { > - struct pwm_ops *pops; > - int pwm_id; > -}; > - > struct pwm_dev_info { > struct pwm_device *pwm_dev; > struct list_head list; > @@ -40,9 +35,9 @@ int pwm_enable(struct pwm_device *pwm) > } > EXPORT_SYMBOL(pwm_enable); > > -void pwm_disable(struct pwm_device *pwm) > +int pwm_disable(struct pwm_device *pwm) > { > - pwm->pops->pwm_disable(pwm); > + return pwm->pops->pwm_disable(pwm); > } > EXPORT_SYMBOL(pwm_disable); > > diff --git a/include/linux/pwm.h b/include/linux/pwm.h > index 6e7da1f..4344c0b 100644 > --- a/include/linux/pwm.h > +++ b/include/linux/pwm.h > @@ -1,14 +1,29 @@ > #ifndef __LINUX_PWM_H > #define __LINUX_PWM_H > > -struct pwm_device; > +/* > + * TODO: #if defined CONFIG_PWM_CORE has to be removed after mips jz4740 > + * pwm driver aligning with pwm-core.c driver. > + */ > +#if defined CONFIG_PWM_CORE > +struct pwm_device { > + struct pwm_ops *pops; > + struct device *dev; > + struct list_head node; > + const char *label; > + unsigned int pwm_id; > + void *data; > +}; > > struct pwm_ops { > int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int period_ns); > int (*pwm_enable)(struct pwm_device *pwm); > int (*pwm_disable)(struct pwm_device *pwm); > - char *name; > + const char *name; > }; > +#else > +struct pwm_device; > +#endif > > /* > * pwm_request - request a PWM device > @@ -33,7 +48,7 @@ int pwm_enable(struct pwm_device *pwm); > /* > * pwm_disable - stop a PWM output toggling > */ > -void pwm_disable(struct pwm_device *pwm); > +int pwm_disable(struct pwm_device *pwm); > > int pwm_device_register(struct pwm_device *pwm_dev); > int pwm_device_unregister(struct pwm_device *pwm_dev); From arun.murthy@stericsson.com Tue Sep 28 10:59:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 10:59:12 +0200 (CEST) Received: from eu1sys200aog101.obsmtp.com ([207.126.144.111]:61000 "EHLO eu1sys200aog101.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1I7B convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 10:59:01 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob101.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGuEAlDNVeKDWL80OJXJTPsizfuNZQ0@postini.com; Tue, 28 Sep 2010 08:59:01 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8D750C0; Tue, 28 Sep 2010 08:57:18 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 23DA11CFE; Tue, 28 Sep 2010 08:57:17 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id DFADC24C2F3; Tue, 28 Sep 2010 10:57:11 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm004.EQ1STM.local ([10.230.100.2]) with mapi; Tue, 28 Sep 2010 10:57:16 +0200 From: Arun MURTHY To: Vasily Khoruzhick Cc: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 10:57:15 +0200 Subject: RE: [PATCH 1/7] pwm: Add pwm core driver Thread-Topic: [PATCH 1/7] pwm: Add pwm core driver Thread-Index: Acte6fbiw3ucXUNBSmSbn8Gxg33PBAAABYaQ Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <201009281114.31223.anarsoul@gmail.com> <201009281147.20871.anarsoul@gmail.com> In-Reply-To: <201009281147.20871.anarsoul@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22178 Content-Length: 683 Lines: 17 > On 28 of September 2010 11:38:26 Arun MURTHY wrote: > > > > > > > Why pwm_free is marked __deprecated? What is its successor? > > > > This function is to be removed. > > What should be used as replacement? > No replacement, this function is not required. In the existing scenario, pwm_request will add to the list and pwm_free will remove the driver from list. Not all the pwm drivers register with the pwm core driver and hence pwm core driver maintains a list, wherein it keeps adding the registered pwm drivers to the list. This is removed from the list by unregistering with the core driver. Hence pwm_free is not required. Thanks and Regards, Arun R Murthy ------------- From arun.murthy@stericsson.com Tue Sep 28 11:07:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 11:07:09 +0200 (CEST) Received: from eu1sys200aog119.obsmtp.com ([207.126.144.147]:60635 "EHLO eu1sys200aog119.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1JHF convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 11:07:05 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob119.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGv7Yy7lkR2CLa33MjLl4mjE3rCufCM@postini.com; Tue, 28 Sep 2010 09:07:05 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5BF33156; Tue, 28 Sep 2010 09:03:37 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id AA67D443; Tue, 28 Sep 2010 09:03:35 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 539A8A8065; Tue, 28 Sep 2010 11:03:30 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm004.EQ1STM.local ([10.230.100.2]) with mapi; Tue, 28 Sep 2010 11:03:34 +0200 From: Arun MURTHY To: Hemanth V Cc: Vasily Khoruzhick , "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 11:03:34 +0200 Subject: RE: [PATCH 1/7] pwm: Add pwm core driver Thread-Topic: [PATCH 1/7] pwm: Add pwm core driver Thread-Index: Acte6n0b5OsB6Z8wQWiCKhEEjIKoyQAALhOA Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <201009281114.31223.anarsoul@gmail.com> <63731.10.24.255.18.1285663815.squirrel@dbdmail.itg.ti.com> In-Reply-To: <63731.10.24.255.18.1285663815.squirrel@dbdmail.itg.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22186 Content-Length: 1279 Lines: 22 > >> On 28 of September 2010 10:40:42 Arun Murthy wrote: > >> > The existing pwm based led and backlight driver makes use of the > >> > pwm(include/linux/pwm.h). So all the board specific pwm drivers > will > >> > be exposing the same set of function name as in > include/linux/pwm.h. > >> > As a result build fails. > >> > >> Which build fails? One with multi-SoC support? Please be more > specific. > > Sure will add this in v2. > > > > Could you clarify for the benefit of all, which specific issues you are > trying to address with this patch series 1. Now since all the pwm driver export same set of function(pwm_enable, pwm_disable,..), if it happens that there are two pwm driver enabled this leads to re-declaration and results in build failure. The proper way to handle this would be to have a pwm core function, and let all the pwm drivers register to the pwm core driver. 2. The above scenario also occurs in place of multi-soc environment. Lets say OMAP has a pwm module and that is being used for primary lcd backlight and twl has a backlight that is being used for controlling the charging led brightness. In this case there exists 2 pwm drivers and one pwm driver will be used by pwm_bl.c and other by leds-pwm.c Thanks and Regards, Arun R Murthy ------------- From arun.murthy@stericsson.com Tue Sep 28 11:20:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 11:20:45 +0200 (CEST) Received: from eu1sys200aog114.obsmtp.com ([207.126.144.137]:53440 "EHLO eu1sys200aog114.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1JUl convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 11:20:41 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob114.postini.com ([207.126.147.11]) with SMTP ID DSNKTKGzCT1TrG+M8d+vNByNVLfJFg50ZMWo@postini.com; Tue, 28 Sep 2010 09:20:40 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 2E852148; Tue, 28 Sep 2010 09:18:44 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E5E75552; Tue, 28 Sep 2010 09:18:42 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 6F381A8095; Tue, 28 Sep 2010 11:18:37 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm022.EQ1STM.local ([10.230.100.30]) with mapi; Tue, 28 Sep 2010 11:18:41 +0200 From: Arun MURTHY To: Lars-Peter Clausen Cc: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "anarsoul@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 11:18:40 +0200 Subject: RE: [PATCH 1/7] pwm: Add pwm core driver Thread-Topic: [PATCH 1/7] pwm: Add pwm core driver Thread-Index: Acte6uSD+s6Qv9t7RkupdCzcufRZxAAATqJA Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <4CA1AD2B.8000905@metafoo.de> In-Reply-To: <4CA1AD2B.8000905@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22194 Content-Length: 2475 Lines: 69 > > +menuconfig PWM_DEVICES > > + bool "PWM devices" > > + default y > > + ---help--- > > + Say Y here to get to see options for device drivers from > various > > + different categories. This option alone does not add any kernel > code. > > + > > + If you say N, all options in this submenu will be skipped and > disabled. > > + > > Shouldn't PWM_DEVICES select HAVE_PWM? No not required, the entire concept is to remove HAVE_PWM and use PWM_CORE. > > +struct pwm_dev_info { > > + struct pwm_device *pwm_dev; > > + struct list_head list; > > +}; > > +static struct pwm_dev_info *di; > > Why not embed the list head into pwm_device. That would certainly make > pwm_device_unregister much simpler. pwm_device will be passed to each and every pwm driver that are registered as client with pwm core. The list consists of the registered pwm drivers and is to be handled by pwm core. Why should each and every pwm driver get to know about the entire pwm driver list? And also since the pwm_request/register/unregister are the one which require this list having this list inst in local/static device information structure seems to be right. > > + } > > + pwm->pwm_dev = pwm_dev; > > + list_add_tail(&pwm->list, &di->list); > > + up_write(&pwm_list_lock); > > + > > I guess you only need to lock the list when accessing the list and > adding the new > pwm_dev. Oops, thanks for pointing out, will implement this in the v2 patch. > > +struct pwm_ops { > > + int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int > period_ns); > > + int (*pwm_enable)(struct pwm_device *pwm); > > + int (*pwm_disable)(struct pwm_device *pwm); > > + char *name; > > +}; > > + > > Shouldn't name be part of the pwm_device? That would allow the ops to > be shared > between different devices. Good catch, the reason being that 2 or more devices can share the same ops and get registered to pwm core. But the catch lies while identifying the pwm device while the clients are requesting for. The pwm backlight will request the pwm driver by name. This is parameter that distinguishes among different pwm devices irrespective of same ops or not. > > +int pwm_device_register(struct pwm_device *pwm_dev); > > +int pwm_device_unregister(struct pwm_device *pwm_dev); > > + > > #endif /* __LINUX_PWM_H */ > > It might be also a good idea to add a device class for pwm devices. Sure, but can you please explain with an example the use case. Thanks and Regards, Arun R Murthy ------------- From arun.murthy@stericsson.com Tue Sep 28 11:28:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 11:28:27 +0200 (CEST) Received: from eu1sys200aog117.obsmtp.com ([207.126.144.143]:52897 "EHLO eu1sys200aog117.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1J2X convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 11:28:23 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob117.postini.com ([207.126.147.11]) with SMTP ID DSNKTKG07GxtssnrVeJPfLJnrM/H1w0K5g2Y@postini.com; Tue, 28 Sep 2010 09:28:23 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 12C86FC; Tue, 28 Sep 2010 09:27:03 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E36A75B8; Tue, 28 Sep 2010 09:27:01 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 65BF3A8095; Tue, 28 Sep 2010 11:26:56 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm022.EQ1STM.local ([10.230.100.30]) with mapi; Tue, 28 Sep 2010 11:27:00 +0200 From: Arun MURTHY To: Lars-Peter Clausen Cc: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "anarsoul@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 11:26:59 +0200 Subject: RE: [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core driver Thread-Topic: [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core driver Thread-Index: Acte61tsF5aNwHgNRsyYLqPwiibNcQAAsuRQ Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-5-git-send-email-arun.murthy@stericsson.com> <4CA1AE21.8070306@metafoo.de> In-Reply-To: <4CA1AE21.8070306@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22203 Content-Length: 1491 Lines: 39 > > mips-jz4740: pwm: Align with new pwm core driver > > > > PWM core driver has been added and has been enabled only for ARM > > platform. The same can be utilised for mips also. > > Please align with the pwm core driver(drivers/pwm-core.c). > > > Is there any reason for artificially limiting it to ARM? No not at all, right now I have aligned all existing pwm drivers in ARM to make use of the pwm core driver. But faced difficulty in aligning the mips-jz4740 pwm driver, without having much knowledge about the device/data sheet. Hence I have let it to the maintainer of that driver to align and thereafter this limitation will be removed. Have also comments the same as TODO in the driver. > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > > index 5d10106..a88640c 100644 > > --- a/drivers/pwm/Kconfig > > +++ b/drivers/pwm/Kconfig > > @@ -4,6 +4,7 @@ > > > > menuconfig PWM_DEVICES > > bool "PWM devices" > > + depends on ARM > > default y > > ---help--- > > Say Y here to get to see options for device drivers from > various > > diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c > > index b84027a..3a0d426 100644 > > > > Why can't these changes be in the initial patch which adds pwm-core? > Since by default this driver is enabled, and if there is some other pwm driver enabled, both happen to export the same function(pwm_enable/pwm_disable,..) After applying the first patch build may fail. Thanks and Regards, Arun R Murthy ------------- From hemanthv@ti.com Tue Sep 28 11:36:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 11:36:09 +0200 (CEST) Received: from devils.ext.ti.com ([198.47.26.153]:51400 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1JgG (ORCPT ); Tue, 28 Sep 2010 11:36:06 +0200 Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o8S9Yios017982 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 28 Sep 2010 04:34:53 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o8S9YPX1020463; Tue, 28 Sep 2010 04:34:26 -0500 (CDT) Received: from 10.24.255.18 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Tue, 28 Sep 2010 15:04:43 +0530 (IST) Message-ID: <19145.10.24.255.18.1285666483.squirrel@dbdmail.itg.ti.com> In-Reply-To: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <201009281114.31223.anarsoul@gmail.com> <63731.10.24.255.18.1285663815.squirrel@dbdmail.itg.ti.com> Date: Tue, 28 Sep 2010 15:04:43 +0530 (IST) Subject: RE: [PATCH 1/7] pwm: Add pwm core driver From: "Hemanth V" To: "Arun MURTHY" , linux-omap@vger.kernel.org Cc: "Vasily Khoruzhick" , "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "Linus WALLEIJ" , "Mattias WALLIN" User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT X-Priority: 3 (Normal) Importance: Normal X-archive-position: 27856 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hemanthv@ti.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22208 Content-Length: 1708 Lines: 32 >> >> On 28 of September 2010 10:40:42 Arun Murthy wrote: >> >> > The existing pwm based led and backlight driver makes use of the >> >> > pwm(include/linux/pwm.h). So all the board specific pwm drivers >> will >> >> > be exposing the same set of function name as in >> include/linux/pwm.h. >> >> > As a result build fails. >> >> >> >> Which build fails? One with multi-SoC support? Please be more >> specific. >> > Sure will add this in v2. >> > >> >> Could you clarify for the benefit of all, which specific issues you are >> trying to address with this patch series > 1. Now since all the pwm driver export same set of function(pwm_enable, pwm_disable,..), if it happens that there are two pwm driver enabled this > leads to re-declaration and results in build failure. The proper way to handle this would be to have a pwm core function, and let all the pwm > drivers register to the pwm core driver. > 2. The above scenario also occurs in place of multi-soc environment. Lets say OMAP has a pwm module and that is being used for primary lcd backlight > and twl has a backlight that is being used for controlling the charging led brightness. In this case there exists 2 pwm drivers and one pwm driver > will be used by pwm_bl.c and other by leds-pwm.c Speaking specifically of OMAP4, twl6030 supports multiple PWMs i.e for display/keypad backlight, charging led. But there should not be need for multiple drivers since twl6030-pwm should be able to support all these (currently it doesnot though). So there would single pwm_enable, pwm_disable exported and driver internally takes care configuring the correct PWM based on id. Would it not be similar situation for other hardware also. Thanks Hemanth From arun.murthy@stericsson.com Tue Sep 28 11:52:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 11:52:39 +0200 (CEST) Received: from eu1sys200aog111.obsmtp.com ([207.126.144.131]:57512 "EHLO eu1sys200aog111.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1Jwf convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 11:52:35 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob111.postini.com ([207.126.147.11]) with SMTP ID DSNKTKG6bz46PdH1ySBaXghSt3DWmW6Zzl1x@postini.com; Tue, 28 Sep 2010 09:52:34 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 2280D12D; Tue, 28 Sep 2010 09:49:55 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 048BD67A; Tue, 28 Sep 2010 09:49:54 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 51207A8065; Tue, 28 Sep 2010 11:49:48 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm003.EQ1STM.local ([10.230.100.1]) with mapi; Tue, 28 Sep 2010 11:49:53 +0200 From: Arun MURTHY To: Hemanth V , "linux-omap@vger.kernel.org" Cc: Vasily Khoruzhick , "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 11:49:53 +0200 Subject: RE: [PATCH 1/7] pwm: Add pwm core driver Thread-Topic: [PATCH 1/7] pwm: Add pwm core driver Thread-Index: Acte8WpGgHNoa48STXabXheNk4HgBwAACbbg Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <201009281114.31223.anarsoul@gmail.com> <63731.10.24.255.18.1285663815.squirrel@dbdmail.itg.ti.com> <19145.10.24.255.18.1285666483.squirrel@dbdmail.itg.ti.com> In-Reply-To: <19145.10.24.255.18.1285666483.squirrel@dbdmail.itg.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22218 Content-Length: 2668 Lines: 56 > >> >> On 28 of September 2010 10:40:42 Arun Murthy wrote: > >> >> > The existing pwm based led and backlight driver makes use of > the > >> >> > pwm(include/linux/pwm.h). So all the board specific pwm drivers > >> will > >> >> > be exposing the same set of function name as in > >> include/linux/pwm.h. > >> >> > As a result build fails. > >> >> > >> >> Which build fails? One with multi-SoC support? Please be more > >> specific. > >> > Sure will add this in v2. > >> > > >> > >> Could you clarify for the benefit of all, which specific issues you > are > >> trying to address with this patch series > > 1. Now since all the pwm driver export same set of > function(pwm_enable, pwm_disable,..), if it happens that there are two > pwm driver enabled this > > leads to re-declaration and results in build failure. The proper way > to handle this would be to have a pwm core function, and let all the > pwm > > drivers register to the pwm core driver. > > 2. The above scenario also occurs in place of multi-soc environment. > Lets say OMAP has a pwm module and that is being used for primary lcd > backlight > > and twl has a backlight that is being used for controlling the > charging led brightness. In this case there exists 2 pwm drivers and > one pwm driver > > will be used by pwm_bl.c and other by leds-pwm.c > > Speaking specifically of OMAP4, twl6030 supports multiple PWMs i.e for > display/keypad backlight, charging > led. But there should not be need for multiple drivers since twl6030- > pwm should be able to support > all these (currently it doesnot though). So there would single > pwm_enable, pwm_disable exported and driver > internally takes care configuring the correct PWM based on id. Would it > not be similar > situation for other hardware also. > You are right, there is only one pwm module in twl4030/twl6030 and this module might have any number or pwm's line PWM1, PWM2, PWM3 etc. My consideration is when you have two separate pwm modules on different soc. Its not in case of OMAP boards. But that was just an example that I gave. Let me be more specific, consider an environment where there is an APE and Power Management subsystem(separate IC but on same board/platform) APE has a pwm module and Power Management SubSystem also has pwm module. Both are part of the platform. Not there exists two drivers in a single platform and both of them are enabled. Building such a kernel results in re-declaration build error. Hope I am clear, I am not trying to distinguish the number of pwm in a pwm module, but trying to distinguish the number of pwm modules in an environment/platform. Thanks and Regards, Arun R Murthy ------------ From lars@metafoo.de Tue Sep 28 11:58:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 11:58:40 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:52624 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1J6g (ORCPT ); Tue, 28 Sep 2010 11:58:36 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id D1B333D4; Tue, 28 Sep 2010 11:58:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id ij0ftXqtgWQz; Tue, 28 Sep 2010 11:58:28 +0200 (CEST) Received: from [192.168.0.213] (e177160142.adsl.alicedsl.de [85.177.160.142]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id CA88B3CE; Tue, 28 Sep 2010 11:57:59 +0200 (CEST) Message-ID: <4CA1BC16.3020702@metafoo.de> Date: Tue, 28 Sep 2010 11:57:42 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Arun MURTHY CC: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "anarsoul@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Subject: Re: [PATCH 1/7] pwm: Add pwm core driver References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <4CA1AD2B.8000905@metafoo.de> In-Reply-To: X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 27858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22226 Content-Length: 3567 Lines: 91 Arun MURTHY wrote: >>> +menuconfig PWM_DEVICES >>> + bool "PWM devices" >>> + default y >>> + ---help--- >>> + Say Y here to get to see options for device drivers from >> various >>> + different categories. This option alone does not add any kernel >> code. >>> + >>> + If you say N, all options in this submenu will be skipped and >> disabled. >>> + >> Shouldn't PWM_DEVICES select HAVE_PWM? > > > No not required, the entire concept is to remove HAVE_PWM and use PWM_CORE. Well in patch 4 you say that PWM_CORE is currently limited to ARM. Furthermore you change the pwm-backlight and pwm-led Kconfig entries to depend on HAVE_PWM || PWM_CORE. Adding a select HAVE_PWM here would make those changes unnecessary. HAVE_PWM should be set, when pwm_* functions are available. When your pwm-core driver is selected they are available. > >>> +struct pwm_dev_info { >>> + struct pwm_device *pwm_dev; >>> + struct list_head list; >>> +}; >>> +static struct pwm_dev_info *di; >> Why not embed the list head into pwm_device. That would certainly make >> pwm_device_unregister much simpler. > pwm_device will be passed to each and every pwm driver that are registered as client with pwm core. > The list consists of the registered pwm drivers and is to be handled by pwm core. > Why should each and every pwm driver get to know about the entire pwm driver list? Declare the list field to be private, by saying that it should only be touched by the core. Right now you allocate a rather small additional structure for each registered device. This could be easily be avoided by embedding the list field into the pwm_device struct. > And also since the pwm_request/register/unregister are the one which require this list having this list inst in local/static device information structure seems to be right. > >>> + } >>> + pwm->pwm_dev = pwm_dev; >>> + list_add_tail(&pwm->list, &di->list); >>> + up_write(&pwm_list_lock); >>> + >> I guess you only need to lock the list when accessing the list and >> adding the new >> pwm_dev. > > Oops, thanks for pointing out, will implement this in the v2 patch. >>> +struct pwm_ops { >>> + int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int >> period_ns); >>> + int (*pwm_enable)(struct pwm_device *pwm); >>> + int (*pwm_disable)(struct pwm_device *pwm); >>> + char *name; >>> +}; >>> + >> Shouldn't name be part of the pwm_device? That would allow the ops to >> be shared >> between different devices. > Good catch, the reason being that 2 or more devices can share the same ops and get registered to pwm core. > But the catch lies while identifying the pwm device while the clients are requesting for. > The pwm backlight will request the pwm driver by name. This is parameter that distinguishes among different pwm devices irrespective of same ops or not. Yes. And thats why it should go into the pwm_device struct itself. If an additional ops struct is allocated for each device anyway we would be better of embedding it directly into the device struct instead of just holding a pointer to it. > >>> +int pwm_device_register(struct pwm_device *pwm_dev); >>> +int pwm_device_unregister(struct pwm_device *pwm_dev); >>> + >>> #endif /* __LINUX_PWM_H */ >> It might be also a good idea to add a device class for pwm devices. > Sure, but can you please explain with an example the use case. > Well, for one it helps to keep data structured. And there would be functions to traverse all devices of a class, so you could get rid of your "di" list. > Thanks and Regards, > Arun R Murthy > ------------- > - Lars From lars@metafoo.de Tue Sep 28 12:11:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:11:34 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:53658 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1KLb (ORCPT ); Tue, 28 Sep 2010 12:11:31 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id DA42F48D; Tue, 28 Sep 2010 12:11:23 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id VqGlauhtW-yL; Tue, 28 Sep 2010 12:11:22 +0200 (CEST) Received: from [192.168.0.213] (e177160142.adsl.alicedsl.de [85.177.160.142]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 9767B48A; Tue, 28 Sep 2010 12:11:11 +0200 (CEST) Message-ID: <4CA1BF2D.2070609@metafoo.de> Date: Tue, 28 Sep 2010 12:10:53 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Arun MURTHY CC: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "anarsoul@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Subject: Re: [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core driver References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-5-git-send-email-arun.murthy@stericsson.com> <4CA1AE21.8070306@metafoo.de> In-Reply-To: X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 27859 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22230 Content-Length: 2016 Lines: 52 Arun MURTHY wrote: >>> mips-jz4740: pwm: Align with new pwm core driver >>> >>> PWM core driver has been added and has been enabled only for ARM >>> platform. The same can be utilised for mips also. >>> Please align with the pwm core driver(drivers/pwm-core.c). >> >> Is there any reason for artificially limiting it to ARM? > > No not at all, right now I have aligned all existing pwm drivers in ARM to make use of the pwm core driver. > But faced difficulty in aligning the mips-jz4740 pwm driver, without having much knowledge about the device/data sheet. > Hence I have let it to the maintainer of that driver to align and thereafter this limitation will be removed. > Have also comments the same as TODO in the driver. > Ok, I'll take care of adjusting the jz4740 pwm driver once the pwm-core is in proper shape. But I still think it would be better to have a config symbol which would be selected by SoC code and on which PWM_CORE would depend. Then it would be possible for SoC implementation to device whether it wants to provide it's own PWM API implementation or use pwm-core. >>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig >>> index 5d10106..a88640c 100644 >>> --- a/drivers/pwm/Kconfig >>> +++ b/drivers/pwm/Kconfig >>> @@ -4,6 +4,7 @@ >>> >>> menuconfig PWM_DEVICES >>> bool "PWM devices" >>> + depends on ARM >>> default y >>> ---help--- >>> Say Y here to get to see options for device drivers from >> various >>> diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c >>> index b84027a..3a0d426 100644 >> >> >> Why can't these changes be in the initial patch which adds pwm-core? >> > Since by default this driver is enabled, and if there is some other pwm driver enabled, both happen to export the same function(pwm_enable/pwm_disable,..) After applying the first patch build may fail. > I would understand that if you were just moving code around, but the pwm_device struct looks completly different now. > Thanks and Regards, > Arun R Murthy > ------------- > From arun.murthy@stericsson.com Tue Sep 28 12:31:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:31:06 +0200 (CEST) Received: from eu1sys200aog105.obsmtp.com ([207.126.144.119]:40984 "EHLO eu1sys200aog105.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1KbC convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 12:31:02 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob105.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHDhiTe8N8AjkvQi0g1GTS9nLpqaJjM@postini.com; Tue, 28 Sep 2010 10:31:01 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 71372111; Tue, 28 Sep 2010 10:28:17 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 40FE565E; Tue, 28 Sep 2010 10:28:16 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id B520D24C2AB; Tue, 28 Sep 2010 12:28:09 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm004.EQ1STM.local ([10.230.100.2]) with mapi; Tue, 28 Sep 2010 12:28:14 +0200 From: Arun MURTHY To: Lars-Peter Clausen Cc: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "anarsoul@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 12:28:08 +0200 Subject: RE: [PATCH 1/7] pwm: Add pwm core driver Thread-Topic: [PATCH 1/7] pwm: Add pwm core driver Thread-Index: Acte87k9pXeI51kzQh2cKWeAjSXglwAAFawg Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <4CA1AD2B.8000905@metafoo.de> <4CA1BC16.3020702@metafoo.de> In-Reply-To: <4CA1BC16.3020702@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22247 Content-Length: 4059 Lines: 91 > >> Shouldn't PWM_DEVICES select HAVE_PWM? > > > > > > No not required, the entire concept is to remove HAVE_PWM and use > PWM_CORE. > > Well in patch 4 you say that PWM_CORE is currently limited to ARM. > Furthermore you > change the pwm-backlight and pwm-led Kconfig entries to depend on > HAVE_PWM || > PWM_CORE. Adding a select HAVE_PWM here would make those changes > unnecessary. HAVE_PWM is retained just because the mips pwm driver is not aligned with the pwm core driver. On mips pwm driver aligning to the pwm core driver HAVE_PWM will be replaced by PWM_CORE. > HAVE_PWM should be set, when pwm_* functions are available. When your > pwm-core driver > is selected they are available. On applying this patch set pwm_* function will be exported in pwm_core driver and in mips pwm driver. Since mips pwm driver is not aligned with the pwm core, HAVE_PWM is retained and removed in places where pwm drivers register to pwm core driver. > > pwm_device will be passed to each and every pwm driver that are > registered as client with pwm core. > > The list consists of the registered pwm drivers and is to be handled > by pwm core. > > Why should each and every pwm driver get to know about the entire pwm > driver list? > Declare the list field to be private, by saying that it should only be > touched by the > core. Right now you allocate a rather small additional structure for > each registered > device. This could be easily be avoided by embedding the list field > into the > pwm_device struct. The one that is being allocated in register is the pwm_device and this has to. Because each pwm driver will have their own data related to ops, pwm_id. Also note that there exists an element "data" that points to the pwm device specific information. Hence this allocation is required. > >>> + } > >>> + pwm->pwm_dev = pwm_dev; > >>> + list_add_tail(&pwm->list, &di->list); > >>> + up_write(&pwm_list_lock); > >>> + > >> I guess you only need to lock the list when accessing the list and > >> adding the new > >> pwm_dev. > > > > Oops, thanks for pointing out, will implement this in the v2 patch. Coming back to this, I guess the locking has to be done while traversing the list also, as my present pointer in the list my get over written by the time I add an element to list. Please let me know if I am wrong. > >>> +struct pwm_ops { > >>> + int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int > >> period_ns); > >>> + int (*pwm_enable)(struct pwm_device *pwm); > >>> + int (*pwm_disable)(struct pwm_device *pwm); > >>> + char *name; > >>> +}; > >>> + > >> Shouldn't name be part of the pwm_device? That would allow the ops > to > >> be shared > >> between different devices. > > Good catch, the reason being that 2 or more devices can share the > same ops and get registered to pwm core. > > But the catch lies while identifying the pwm device while the clients > are requesting for. > > The pwm backlight will request the pwm driver by name. This is > parameter that distinguishes among different pwm devices irrespective > of same ops or not. > Yes. And thats why it should go into the pwm_device struct itself. > > If an additional ops struct is allocated for each device anyway we > would be better of > embedding it directly into the device struct instead of just holding a > pointer to it. Yes ops structure will be allocated. But how can we get access to the ops structure of another driver? And moreover two pwm driver sharing same ops ideally means a single pwm module. If not everything atleast the pwm registers of two different modules changes. So this scenario can never occur. > >>> #endif /* __LINUX_PWM_H */ > >> It might be also a good idea to add a device class for pwm devices. > > Sure, but can you please explain with an example the use case. > > > Well, for one it helps to keep data structured. > And there would be functions to traverse all devices of a class, so you > could get rid > of your "di" list. Sorry, I didn't get you can you please elaborate more? Thanks and Regards, Arun R Murthy ------------- From arun.murthy@stericsson.com Tue Sep 28 12:35:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:35:29 +0200 (CEST) Received: from eu1sys200aog117.obsmtp.com ([207.126.144.143]:41426 "EHLO eu1sys200aog117.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1KfV convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 12:35:21 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob117.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHEm8qVVsRTvBOxjOfqpluw9Yg/34iF@postini.com; Tue, 28 Sep 2010 10:35:21 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2B70785; Tue, 28 Sep 2010 10:33:15 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C0EA421C3; Tue, 28 Sep 2010 10:33:13 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 5DF71A8094; Tue, 28 Sep 2010 12:33:08 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm003.EQ1STM.local ([10.230.100.1]) with mapi; Tue, 28 Sep 2010 12:33:13 +0200 From: Arun MURTHY To: Lars-Peter Clausen Cc: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "anarsoul@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "hemanthv@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Linus WALLEIJ , Mattias WALLIN Date: Tue, 28 Sep 2010 12:33:08 +0200 Subject: RE: [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core driver Thread-Topic: [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core driver Thread-Index: Acte9YREgVS2Eek2RwSBOuSpkmCbJgAAlbJA Message-ID: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-5-git-send-email-arun.murthy@stericsson.com> <4CA1AE21.8070306@metafoo.de> <4CA1BF2D.2070609@metafoo.de> In-Reply-To: <4CA1BF2D.2070609@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27861 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22248 Content-Length: 2072 Lines: 49 > Arun MURTHY wrote: > >>> mips-jz4740: pwm: Align with new pwm core driver > >>> > >>> PWM core driver has been added and has been enabled only for ARM > >>> platform. The same can be utilised for mips also. > >>> Please align with the pwm core driver(drivers/pwm-core.c). > >> > >> Is there any reason for artificially limiting it to ARM? > > > > No not at all, right now I have aligned all existing pwm drivers in > ARM to make use of the pwm core driver. > > But faced difficulty in aligning the mips-jz4740 pwm driver, without > having much knowledge about the device/data sheet. > > Hence I have let it to the maintainer of that driver to align and > thereafter this limitation will be removed. > > Have also comments the same as TODO in the driver. > > > > Ok, I'll take care of adjusting the jz4740 pwm driver once the pwm-core > is in proper > shape. > But I still think it would be better to have a config symbol which > would be selected > by SoC code and on which PWM_CORE would depend. Then it would be > possible for SoC > implementation to device whether it wants to provide it's own PWM API > implementation > or use pwm-core. My intention is to make it a generic pwm driver. Like the one we do to register a led class driver / backlight class driver. > >> > >> Why can't these changes be in the initial patch which adds pwm-core? > >> > > Since by default this driver is enabled, and if there is some other > pwm driver enabled, both happen to export the same > function(pwm_enable/pwm_disable,..) After applying the first patch > build may fail. > > > I would understand that if you were just moving code around, but the > pwm_device > struct looks completly different now. Yes, that's the reason, I have modified all the existing pwm drivers except the mips to align with this. And this looks more generic. For example the element pwm_id, dev, data in pwm_device are all specific to a device and irrespective of any number of pwm devices each and every device will require this information, hence so. Thanks and Regards, Arun R Murthy ------------- From arun.murthy@stericsson.com Tue Sep 28 12:35:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:35:58 +0200 (CEST) Received: from eu1sys200aog111.obsmtp.com ([207.126.144.131]:33294 "EHLO eu1sys200aog111.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491956Ab0I1Kfy (ORCPT ); Tue, 28 Sep 2010 12:35:54 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob111.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHE/SceZEO2YvDPz6nUv7LIkpx18kZ3@postini.com; Tue, 28 Sep 2010 10:35:54 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6354079; Tue, 28 Sep 2010 10:35:40 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E41E821EE; Tue, 28 Sep 2010 10:35:39 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 82283A8065; Tue, 28 Sep 2010 12:35:34 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 12:35:39 +0200 From: Arun Murthy To: , , , , , , , , , , Cc: , , , , Subject: [PATCH 0/7] PWM core driver for pwm based led and backlight driver Date: Tue, 28 Sep 2010 16:05:27 +0530 Message-ID: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27862 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22250 Content-Length: 3450 Lines: 70 The series of patch add a new pwm core driver. Align the existing pwm drivers to make use of the pwm core driver. Arun Murthy (7): pwm: Add pwm core driver backlight:pwm: add an element 'name' to platform data leds: pwm: add a new element 'name' to platform data pwm: Align existing pwm drivers with pwm-core driver platform: Update the pwm based led and backlight platform data pwm: move existing pwm driver to drivers/pwm pwm: Modify backlight and led Kconfig aligning to pwm core arch/arm/mach-pxa/cm-x300.c | 1 + arch/arm/mach-pxa/colibri-pxa270-income.c | 1 + arch/arm/mach-pxa/ezx.c | 1 + arch/arm/mach-pxa/hx4700.c | 1 + arch/arm/mach-pxa/lpd270.c | 1 + arch/arm/mach-pxa/magician.c | 1 + arch/arm/mach-pxa/mainstone.c | 1 + arch/arm/mach-pxa/mioa701.c | 1 + arch/arm/mach-pxa/palm27x.c | 1 + arch/arm/mach-pxa/palmtc.c | 1 + arch/arm/mach-pxa/palmte2.c | 1 + arch/arm/mach-pxa/pcm990-baseboard.c | 1 + arch/arm/mach-pxa/raumfeld.c | 1 + arch/arm/mach-pxa/tavorevb.c | 2 + arch/arm/mach-pxa/viper.c | 1 + arch/arm/mach-pxa/z2.c | 2 + arch/arm/mach-pxa/zylonite.c | 1 + arch/arm/mach-s3c2410/mach-h1940.c | 1 + arch/arm/mach-s3c2440/mach-rx1950.c | 1 + arch/arm/mach-s3c64xx/mach-hmt.c | 1 + arch/arm/mach-s3c64xx/mach-smartq.c | 1 + arch/arm/plat-mxc/pwm.c | 166 +++++++++------------ arch/arm/plat-pxa/pwm.c | 210 ++++++++++++-------------- arch/arm/plat-samsung/pwm.c | 235 +++++++++++++---------------- arch/mips/jz4740/pwm.c | 2 +- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/leds/Kconfig | 2 +- drivers/leds/leds-pwm.c | 4 +- drivers/mfd/Kconfig | 9 - drivers/mfd/Makefile | 1 - drivers/mfd/twl-core.c | 13 ++ drivers/mfd/twl6030-pwm.c | 163 -------------------- drivers/misc/Kconfig | 9 - drivers/misc/Makefile | 1 - drivers/misc/ab8500-pwm.c | 168 -------------------- drivers/pwm/Kconfig | 33 ++++ drivers/pwm/Makefile | 4 + drivers/pwm/pwm-ab8500.c | 157 +++++++++++++++++++ drivers/pwm/pwm-core.c | 124 +++++++++++++++ drivers/pwm/pwm-twl6040.c | 196 ++++++++++++++++++++++++ drivers/video/backlight/Kconfig | 2 +- drivers/video/backlight/pwm_bl.c | 4 +- include/linux/leds_pwm.h | 1 + include/linux/pwm.h | 29 ++++- include/linux/pwm_backlight.h | 1 + 46 files changed, 864 insertions(+), 696 deletions(-) delete mode 100644 drivers/mfd/twl6030-pwm.c delete mode 100644 drivers/misc/ab8500-pwm.c create mode 100644 drivers/pwm/Kconfig create mode 100644 drivers/pwm/Makefile create mode 100644 drivers/pwm/pwm-ab8500.c create mode 100644 drivers/pwm/pwm-core.c create mode 100644 drivers/pwm/pwm-twl6040.c -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 12:36:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:36:23 +0200 (CEST) Received: from eu1sys200aog105.obsmtp.com ([207.126.144.119]:44960 "EHLO eu1sys200aog105.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491049Ab0I1KgB (ORCPT ); Tue, 28 Sep 2010 12:36:01 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob105.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHFBXaQwiNgHNo+6opxTIZcbMb5SsK/@postini.com; Tue, 28 Sep 2010 10:36:01 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 658BA73; Tue, 28 Sep 2010 10:35:48 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F353521EE; Tue, 28 Sep 2010 10:35:47 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 0345024C2F1; Tue, 28 Sep 2010 12:35:42 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 12:35:47 +0200 From: Arun Murthy To: , , , , , , , , , , Cc: , , , , Subject: [PATCH 3/7] leds: pwm: add a new element 'name' to platform data Date: Tue, 28 Sep 2010 16:05:30 +0530 Message-ID: <1285670134-18063-4-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27863 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22256 Content-Length: 1199 Lines: 41 A new element 'name' is added to pwm led platform data structure. This is required to identify the pwm device. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/leds/leds-pwm.c | 4 +++- include/linux/leds_pwm.h | 1 + 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c index da3fa8d..8da2be6 100644 --- a/drivers/leds/leds-pwm.c +++ b/drivers/leds/leds-pwm.c @@ -66,8 +66,10 @@ static int led_pwm_probe(struct platform_device *pdev) cur_led = &pdata->leds[i]; led_dat = &leds_data[i]; + if (!pdata->name) + pdata->name = cur_led->name; led_dat->pwm = pwm_request(cur_led->pwm_id, - cur_led->name); + pdata->name); if (IS_ERR(led_dat->pwm)) { dev_err(&pdev->dev, "unable to request PWM %d\n", cur_led->pwm_id); diff --git a/include/linux/leds_pwm.h b/include/linux/leds_pwm.h index 33a0711..7a847a0 100644 --- a/include/linux/leds_pwm.h +++ b/include/linux/leds_pwm.h @@ -16,6 +16,7 @@ struct led_pwm { struct led_pwm_platform_data { int num_leds; struct led_pwm *leds; + char *name; }; #endif -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 12:36:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:36:53 +0200 (CEST) Received: from eu1sys200aog118.obsmtp.com ([207.126.144.145]:53350 "EHLO eu1sys200aog118.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491094Ab0I1KgG (ORCPT ); Tue, 28 Sep 2010 12:36:06 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHFCViISg52J2jYm5lbKIWsO4dcbWdE@postini.com; Tue, 28 Sep 2010 10:36:05 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2451581; Tue, 28 Sep 2010 10:35:52 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 907B221EE; Tue, 28 Sep 2010 10:35:51 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 97A8624C07D; Tue, 28 Sep 2010 12:35:45 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 12:35:49 +0200 From: Arun Murthy To: , , , , , , , , , , Cc: , , , , Subject: [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core driver Date: Tue, 28 Sep 2010 16:05:31 +0530 Message-ID: <1285670134-18063-5-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27864 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22257 Content-Length: 39085 Lines: 1533 pwm-core: make the driver visible for ARM only Align ab8500 pwm with the pwm core driver Align twl6030 pwm driver with pwm core driver Align Freescale mxc pwm driver with pwm core driver Align pxa pwm driver with pwm core driver Align samsung(s3c) pwm driver with pwm core driver mips-jz4740: pwm: Align with new pwm core driver PWM core driver has been added and has been enabled only for ARM platform. The same can be utilised for mips also. Please align with the pwm core driver(drivers/pwm-core.c). Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- arch/arm/plat-mxc/pwm.c | 166 +++++++++++++----------------- arch/arm/plat-pxa/pwm.c | 210 ++++++++++++++++++-------------------- arch/arm/plat-samsung/pwm.c | 235 +++++++++++++++++++------------------------ arch/mips/jz4740/pwm.c | 2 +- drivers/mfd/twl-core.c | 13 +++ drivers/mfd/twl6030-pwm.c | 111 +++++++++++++------- drivers/misc/ab8500-pwm.c | 87 +++++++--------- drivers/pwm/Kconfig | 1 + drivers/pwm/pwm-core.c | 9 +-- include/linux/pwm.h | 21 ++++- 10 files changed, 418 insertions(+), 437 deletions(-) diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index c36f263..b259ba9 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -38,22 +38,16 @@ -struct pwm_device { - struct list_head node; - struct platform_device *pdev; - - const char *label; +struct mxc_pwm_device { struct clk *clk; - int clk_enabled; void __iomem *mmio_base; - - unsigned int use_count; - unsigned int pwm_id; }; -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +static int mxc_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { + struct mxc_pwm_device *mxc_pwm = pwm->data; + if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; @@ -62,7 +56,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) unsigned long period_cycles, duty_cycles, prescale; u32 cr; - c = clk_get_rate(pwm->clk); + c = clk_get_rate(mxc_pwm->clk); c = c * period_ns; do_div(c, 1000000000); period_cycles = c; @@ -74,8 +68,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) do_div(c, period_ns); duty_cycles = c; - writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); - writel(period_cycles, pwm->mmio_base + MX3_PWMPR); + writel(duty_cycles, mxc_pwm->mmio_base + MX3_PWMSAR); + writel(period_cycles, mxc_pwm->mmio_base + MX3_PWMPR); cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN; @@ -84,7 +78,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) else cr |= MX3_PWMCR_CLKSRC_IPG_HIGH; - writel(cr, pwm->mmio_base + MX3_PWMCR); + writel(cr, mxc_pwm->mmio_base + MX3_PWMCR); } else if (cpu_is_mx1() || cpu_is_mx21()) { /* The PWM subsystem allows for exact frequencies. However, * I cannot connect a scope on my device to the PWM line and @@ -102,110 +96,76 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) * both the prescaler (/1 .. /128) and then by CLKSEL * (/2 .. /16). */ - u32 max = readl(pwm->mmio_base + MX1_PWMP); + u32 max = readl(mxc_pwm->mmio_base + MX1_PWMP); u32 p = max * duty_ns / period_ns; - writel(max - p, pwm->mmio_base + MX1_PWMS); + writel(max - p, mxc_pwm->mmio_base + MX1_PWMS); } else { BUG(); } return 0; } -EXPORT_SYMBOL(pwm_config); -int pwm_enable(struct pwm_device *pwm) +static int mxc_pwm_enable(struct pwm_device *pwm) { + struct mxc_pwm_device *mxc_pwm = pwm->data; int rc = 0; - if (!pwm->clk_enabled) { - rc = clk_enable(pwm->clk); + if (!mxc_pwm->clk_enabled) { + rc = clk_enable(mxc_pwm->clk); if (!rc) - pwm->clk_enabled = 1; + mxc_pwm->clk_enabled = 1; } return rc; } -EXPORT_SYMBOL(pwm_enable); - -void pwm_disable(struct pwm_device *pwm) -{ - writel(0, pwm->mmio_base + MX3_PWMCR); - - if (pwm->clk_enabled) { - clk_disable(pwm->clk); - pwm->clk_enabled = 0; - } -} -EXPORT_SYMBOL(pwm_disable); - -static DEFINE_MUTEX(pwm_lock); -static LIST_HEAD(pwm_list); -struct pwm_device *pwm_request(int pwm_id, const char *label) +static int mxc_pwm_disable(struct pwm_device *pwm) { - struct pwm_device *pwm; - int found = 0; + struct mxc_pwm_device *mxc_pwm = pwm->data; - mutex_lock(&pwm_lock); + writel(0, mxc_pwm->mmio_base + MX3_PWMCR); - list_for_each_entry(pwm, &pwm_list, node) { - if (pwm->pwm_id == pwm_id) { - found = 1; - break; - } + if (mxc_pwm->clk_enabled) { + clk_disable(mxc_pwm->clk); + mxc_pwm->clk_enabled = 0; } - - if (found) { - if (pwm->use_count == 0) { - pwm->use_count++; - pwm->label = label; - } else - pwm = ERR_PTR(-EBUSY); - } else - pwm = ERR_PTR(-ENOENT); - - mutex_unlock(&pwm_lock); - return pwm; -} -EXPORT_SYMBOL(pwm_request); - -void pwm_free(struct pwm_device *pwm) -{ - mutex_lock(&pwm_lock); - - if (pwm->use_count) { - pwm->use_count--; - pwm->label = NULL; - } else - pr_warning("PWM device already freed\n"); - - mutex_unlock(&pwm_lock); + return 0; } -EXPORT_SYMBOL(pwm_free); static int __devinit mxc_pwm_probe(struct platform_device *pdev) { + struct mxc_pwm_device *mxc_pwm; struct pwm_device *pwm; + struct pwm_ops *pops; struct resource *r; int ret = 0; + mxc_pwm = kzalloc(sizeof(struct mxc_pwm_device), GFP_KERNEL); + if (mxc_pwm == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (pwm == NULL) { dev_err(&pdev->dev, "failed to allocate memory\n"); - return -ENOMEM; + ret = -ENOMEM; + goto err_free1; + } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + ret = -ENOMEM; + goto err_free2; } - pwm->clk = clk_get(&pdev->dev, "pwm"); + mxc_pwm->clk = clk_get(&pdev->dev, "pwm"); - if (IS_ERR(pwm->clk)) { - ret = PTR_ERR(pwm->clk); - goto err_free; + if (IS_ERR(mxc_pwm->clk)) { + ret = PTR_ERR(mxc_pwm->clk); + goto err_free3; } - pwm->clk_enabled = 0; - - pwm->use_count = 0; - pwm->pwm_id = pdev->id; - pwm->pdev = pdev; + mxc_pwm->clk_enabled = 0; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (r == NULL) { @@ -221,16 +181,27 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) goto err_free_clk; } - pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); - if (pwm->mmio_base == NULL) { + mxc_pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); + if (mxc_pwm->mmio_base == NULL) { dev_err(&pdev->dev, "failed to ioremap() registers\n"); ret = -ENODEV; goto err_free_mem; } - mutex_lock(&pwm_lock); - list_add_tail(&pwm->node, &pwm_list); - mutex_unlock(&pwm_lock); + pops->pwm_config = mxc_pwm_config; + pops->pwm_enable = mxc_pwm_enable; + pops->pwm_disable = mxc_pwm_disable; + pops->name = pdev->name; + + pwm->pwm_id = pdev->id; + pwm->dev = &pdev->dev; + pwm->pops = pops; + pwm->data = mxc_pwm; + ret = pwm_device_register(pwm); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + goto err_free_mem; + } platform_set_drvdata(pdev, pwm); return 0; @@ -238,33 +209,38 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) err_free_mem: release_mem_region(r->start, r->end - r->start + 1); err_free_clk: - clk_put(pwm->clk); -err_free: + clk_put(mxc_pwm->clk); +err_free3: + kfree(pops); +err_free2: kfree(pwm); +err_free1: + kfree(mxc_pwm); return ret; } static int __devexit mxc_pwm_remove(struct platform_device *pdev) { struct pwm_device *pwm; + struct mxc_pwm_device *mxc_pwm; struct resource *r; pwm = platform_get_drvdata(pdev); if (pwm == NULL) return -ENODEV; + mxc_pwm = pwm->data; - mutex_lock(&pwm_lock); - list_del(&pwm->node); - mutex_unlock(&pwm_lock); - - iounmap(pwm->mmio_base); + pwm_device_unregister(pwm); + iounmap(mxc_pwm->mmio_base); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); release_mem_region(r->start, r->end - r->start + 1); - clk_put(pwm->clk); + clk_put(mxc_pwm->clk); + kfree(pwm->pops); kfree(pwm); + kfree(mxc_pwm); return 0; } diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c index ef32686..1de902a 100644 --- a/arch/arm/plat-pxa/pwm.c +++ b/arch/arm/plat-pxa/pwm.c @@ -43,33 +43,27 @@ MODULE_DEVICE_TABLE(platform, pwm_id_table); #define PWMCR_SD (1 << 6) #define PWMDCR_FD (1 << 10) -struct pwm_device { - struct list_head node; - struct pwm_device *secondary; - struct platform_device *pdev; - - const char *label; +struct pxa_pwm_device { + struct pxa_pwm_device *sec; struct clk *clk; int clk_enabled; void __iomem *mmio_base; - - unsigned int use_count; - unsigned int pwm_id; }; /* * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE */ -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +int pxa_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { unsigned long long c; unsigned long period_cycles, prescale, pv, dc; + struct pxa_pwm_device *pxa_pwm = pwm->data; if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; - c = clk_get_rate(pwm->clk); + c = clk_get_rate(pxa_pwm->clk); c = c * period_ns; do_div(c, 1000000000); period_cycles = c; @@ -90,94 +84,45 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) /* NOTE: the clock to PWM has to be enabled first * before writing to the registers */ - clk_enable(pwm->clk); - __raw_writel(prescale, pwm->mmio_base + PWMCR); - __raw_writel(dc, pwm->mmio_base + PWMDCR); - __raw_writel(pv, pwm->mmio_base + PWMPCR); - clk_disable(pwm->clk); + clk_enable(pxa_pwm->clk); + __raw_writel(prescale, pxa_pwm->mmio_base + PWMCR); + __raw_writel(dc, pxa_pwm->mmio_base + PWMDCR); + __raw_writel(pv, pxa_pwm->mmio_base + PWMPCR); + clk_disable(pxa_pwm->clk); return 0; } -EXPORT_SYMBOL(pwm_config); -int pwm_enable(struct pwm_device *pwm) +int pxa_pwm_enable(struct pwm_device *pwm) { + struct pxa_pwm_device *pxa_pwm = pwm->data; int rc = 0; - if (!pwm->clk_enabled) { - rc = clk_enable(pwm->clk); + if (!pxa_pwm->clk_enabled) { + rc = clk_enable(pxa_pwm->clk); if (!rc) - pwm->clk_enabled = 1; + pxa_pwm->clk_enabled = 1; } return rc; } -EXPORT_SYMBOL(pwm_enable); -void pwm_disable(struct pwm_device *pwm) +int pxa_pwm_disable(struct pwm_device *pwm) { - if (pwm->clk_enabled) { - clk_disable(pwm->clk); - pwm->clk_enabled = 0; - } -} -EXPORT_SYMBOL(pwm_disable); - -static DEFINE_MUTEX(pwm_lock); -static LIST_HEAD(pwm_list); + struct pxa_pwm_device *pxa_pwm = pwm->data; -struct pwm_device *pwm_request(int pwm_id, const char *label) -{ - struct pwm_device *pwm; - int found = 0; - - mutex_lock(&pwm_lock); - - list_for_each_entry(pwm, &pwm_list, node) { - if (pwm->pwm_id == pwm_id) { - found = 1; - break; - } + if (pxa_pwm->clk_enabled) { + clk_disable(pxa_pwm->clk); + pxa_pwm->clk_enabled = 0; } - - if (found) { - if (pwm->use_count == 0) { - pwm->use_count++; - pwm->label = label; - } else - pwm = ERR_PTR(-EBUSY); - } else - pwm = ERR_PTR(-ENOENT); - - mutex_unlock(&pwm_lock); - return pwm; -} -EXPORT_SYMBOL(pwm_request); - -void pwm_free(struct pwm_device *pwm) -{ - mutex_lock(&pwm_lock); - - if (pwm->use_count) { - pwm->use_count--; - pwm->label = NULL; - } else - pr_warning("PWM device already freed\n"); - - mutex_unlock(&pwm_lock); -} -EXPORT_SYMBOL(pwm_free); - -static inline void __add_pwm(struct pwm_device *pwm) -{ - mutex_lock(&pwm_lock); - list_add_tail(&pwm->node, &pwm_list); - mutex_unlock(&pwm_lock); + return 0; } static int __devinit pwm_probe(struct platform_device *pdev) { const struct platform_device_id *id = platform_get_device_id(pdev); + struct pxa_pwm_device *pxa_pwm, *pxa_pwm_sec; struct pwm_device *pwm, *secondary = NULL; + struct pwm_ops *pops; struct resource *r; int ret = 0; @@ -186,17 +131,26 @@ static int __devinit pwm_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to allocate memory\n"); return -ENOMEM; } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pwm); + return -ENOMEM; + } + pxa_pwm = kzalloc(sizeof(struct pxa_pwm_device), GFP_KERNEL); + if (pxa_pwm == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pops); + kfree(pwm); + return -ENOMEM; + } - pwm->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(pwm->clk)) { - ret = PTR_ERR(pwm->clk); + pxa_pwm->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(pxa_pwm->clk)) { + ret = PTR_ERR(pxa_pwm->clk); goto err_free; } - pwm->clk_enabled = 0; - - pwm->use_count = 0; - pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id; - pwm->pdev = pdev; + pxa_pwm->clk_enabled = 0; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (r == NULL) { @@ -212,69 +166,105 @@ static int __devinit pwm_probe(struct platform_device *pdev) goto err_free_clk; } - pwm->mmio_base = ioremap(r->start, resource_size(r)); - if (pwm->mmio_base == NULL) { + pxa_pwm->mmio_base = ioremap(r->start, resource_size(r)); + if (pxa_pwm->mmio_base == NULL) { dev_err(&pdev->dev, "failed to ioremap() registers\n"); ret = -ENODEV; goto err_free_mem; } + pops->pwm_config = pxa_pwm_config; + pops->pwm_enable = pxa_pwm_enable; + pops->pwm_disable = pxa_pwm_disable; + pops->name = pdev->name; + + pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id; + pwm->dev = &pdev->dev; + pwm->pops = pops; + pwm->data = pxa_pwm; + + ret = pwm_device_register(pwm); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + goto err_free_mem; + } + if (id->driver_data & HAS_SECONDARY_PWM) { secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (secondary == NULL) { ret = -ENOMEM; - goto err_free_mem; + goto err_pwm; + } + pxa_pwm_sec = kzalloc(sizeof(struct pxa_pwm_device), + GFP_KERNEL); + if (pxa_pwm_sec == NULL) { + ret = -ENOMEM; + goto err_free_mem2; } *secondary = *pwm; - pwm->secondary = secondary; + *pxa_pwm_sec = *pxa_pwm; + pxa_pwm->sec = pxa_pwm_sec; /* registers for the second PWM has offset of 0x10 */ - secondary->mmio_base = pwm->mmio_base + 0x10; + pxa_pwm_sec->mmio_base = pxa_pwm->mmio_base + 0x10; secondary->pwm_id = pdev->id + 2; - } + secondary->data = pxa_pwm_sec; - __add_pwm(pwm); - if (secondary) - __add_pwm(secondary); + ret = pwm_device_register(secondary); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + goto err_free_mem3; + } + } platform_set_drvdata(pdev, pwm); return 0; - +err_free_mem3: + kfree(pxa_pwm_sec); +err_free_mem2: + kfree(secondary); +err_pwm: + pwm_device_unregister(pwm); err_free_mem: release_mem_region(r->start, resource_size(r)); err_free_clk: - clk_put(pwm->clk); + clk_put(pxa_pwm->clk); err_free: + kfree(pxa_pwm); + kfree(pops); kfree(pwm); return ret; } static int __devexit pwm_remove(struct platform_device *pdev) { - struct pwm_device *pwm; + struct pwm_device *pwm, *secondary; + struct pxa_pwm_device *pxa_pwm, *pxa_pwm_sec; struct resource *r; pwm = platform_get_drvdata(pdev); if (pwm == NULL) return -ENODEV; - - mutex_lock(&pwm_lock); - - if (pwm->secondary) { - list_del(&pwm->secondary->node); - kfree(pwm->secondary); + pxa_pwm = pwm->data; + secondary = pwm_request((pdev->id + 2), pdev->name); + pxa_pwm_sec = secondary->data; + + pwm_device_unregister(pwm); + iounmap(pxa_pwm->mmio_base); + if (secondary) { + pwm_device_unregister(secondary); + iounmap(pxa_pwm->mmio_base); + kfree(pxa_pwm_sec); + kfree(secondary); } - list_del(&pwm->node); - mutex_unlock(&pwm_lock); - - iounmap(pwm->mmio_base); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); release_mem_region(r->start, resource_size(r)); - clk_put(pwm->clk); + clk_put(pxa_pwm->clk); + kfree(pxa_pwm); + kfree(pwm->pops); kfree(pwm); return 0; } diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c index 2eeb49f..63fba01 100644 --- a/arch/arm/plat-samsung/pwm.c +++ b/arch/arm/plat-samsung/pwm.c @@ -26,25 +26,19 @@ #include #include -struct pwm_device { - struct list_head list; +struct s3c_pwm_device { struct platform_device *pdev; struct clk *clk_div; struct clk *clk; - const char *label; unsigned int period_ns; unsigned int duty_ns; unsigned char tcon_base; unsigned char running; - unsigned char use_count; - unsigned char pwm_id; }; -#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) - static struct clk *clk_scaler[2]; /* Standard setup for a timer block. */ @@ -78,108 +72,61 @@ struct platform_device s3c_device_timer[] = { [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, }; -static inline int pwm_is_tdiv(struct pwm_device *pwm) +static inline int pwm_is_tdiv(struct s3c_pwm_device *s3c_pwm) { - return clk_get_parent(pwm->clk) == pwm->clk_div; + return clk_get_parent(s3c_pwm->clk) == s3c_pwm->clk_div; } -static DEFINE_MUTEX(pwm_lock); -static LIST_HEAD(pwm_list); +#define pwm_tcon_start(s3c_pwm) (1 << (s3c_pwm->tcon_base + 0)) +#define pwm_tcon_invert(s3c_pwm) (1 << (s3c_pwm->tcon_base + 2)) +#define pwm_tcon_autoreload(s3c_pwm) (1 << (s3c_pwm->tcon_base + 3)) +#define pwm_tcon_manulupdate(s3c_pwm) (1 << (s3c_pwm->tcon_base + 1)) -struct pwm_device *pwm_request(int pwm_id, const char *label) -{ - struct pwm_device *pwm; - int found = 0; - - mutex_lock(&pwm_lock); - - list_for_each_entry(pwm, &pwm_list, list) { - if (pwm->pwm_id == pwm_id) { - found = 1; - break; - } - } - - if (found) { - if (pwm->use_count == 0) { - pwm->use_count = 1; - pwm->label = label; - } else - pwm = ERR_PTR(-EBUSY); - } else - pwm = ERR_PTR(-ENOENT); - - mutex_unlock(&pwm_lock); - return pwm; -} - -EXPORT_SYMBOL(pwm_request); - - -void pwm_free(struct pwm_device *pwm) -{ - mutex_lock(&pwm_lock); - - if (pwm->use_count) { - pwm->use_count--; - pwm->label = NULL; - } else - printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id); - - mutex_unlock(&pwm_lock); -} - -EXPORT_SYMBOL(pwm_free); - -#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) -#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) -#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) -#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) - -int pwm_enable(struct pwm_device *pwm) +int s3c_pwm_enable(struct pwm_device *pwm) { unsigned long flags; unsigned long tcon; + struct s3c_pwm_device *s3c_pwm = pwm->data; local_irq_save(flags); tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_start(pwm); + tcon |= pwm_tcon_start(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); local_irq_restore(flags); - pwm->running = 1; + s3c_pwm->running = 1; return 0; } -EXPORT_SYMBOL(pwm_enable); - -void pwm_disable(struct pwm_device *pwm) +int s3c_pwm_disable(struct pwm_device *pwm) { unsigned long flags; unsigned long tcon; + struct s3c_pwm_device *s3c_pwm = pwm->data; local_irq_save(flags); tcon = __raw_readl(S3C2410_TCON); - tcon &= ~pwm_tcon_start(pwm); + tcon &= ~pwm_tcon_start(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); local_irq_restore(flags); - pwm->running = 0; + s3c_pwm->running = 0; + return 0; } -EXPORT_SYMBOL(pwm_disable); - -static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) +static unsigned long pwm_calc_tin(struct pwm_device *pwm, + unsigned long freq) { unsigned long tin_parent_rate; unsigned int div; + struct s3c_pwm_device *s3c_pwm = pwm->data; - tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div)); - pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate); + tin_parent_rate = clk_get_rate(clk_get_parent(s3c_pwm->clk_div)); + dev_dbg(pwm->dev, "tin parent at %lu\n", tin_parent_rate); for (div = 2; div <= 16; div *= 2) { if ((tin_parent_rate / (div << 16)) < freq) @@ -191,7 +138,7 @@ static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) #define NS_IN_HZ (1000000000UL) -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +int s3c_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { unsigned long tin_rate; unsigned long tin_ns; @@ -200,6 +147,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) unsigned long tcon; unsigned long tcnt; long tcmp; + struct s3c_pwm_device *s3c_pwm = pwm->data; /* We currently avoid using 64bit arithmetic by using the * fact that anything faster than 1Hz is easily representable @@ -211,8 +159,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (duty_ns > period_ns) return -EINVAL; - if (period_ns == pwm->period_ns && - duty_ns == pwm->duty_ns) + if (period_ns == s3c_pwm->period_ns && + duty_ns == s3c_pwm->duty_ns) return 0; /* The TCMP and TCNT can be read without a lock, they're not @@ -223,26 +171,26 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) period = NS_IN_HZ / period_ns; - pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n", + dev_dbg(pwm->dev, "duty_ns=%d, period_ns=%d (%lu)\n", duty_ns, period_ns, period); /* Check to see if we are changing the clock rate of the PWM */ - if (pwm->period_ns != period_ns) { - if (pwm_is_tdiv(pwm)) { + if (s3c_pwm->period_ns != period_ns) { + if (pwm_is_tdiv(s3c_pwm)) { tin_rate = pwm_calc_tin(pwm, period); - clk_set_rate(pwm->clk_div, tin_rate); + clk_set_rate(s3c_pwm->clk_div, tin_rate); } else - tin_rate = clk_get_rate(pwm->clk); + tin_rate = clk_get_rate(s3c_pwm->clk); - pwm->period_ns = period_ns; + s3c_pwm->period_ns = period_ns; - pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate); + dev_dbg(pwm->dev, "tin_rate=%lu\n", tin_rate); tin_ns = NS_IN_HZ / tin_rate; tcnt = period_ns / tin_ns; } else - tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk); + tin_ns = NS_IN_HZ / clk_get_rate(s3c_pwm->clk); /* Note, counters count down */ @@ -253,7 +201,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (tcmp == tcnt) tcmp--; - pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); + dev_dbg(pwm->dev, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); if (tcmp < 0) tcmp = 0; @@ -266,11 +214,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id)); tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_manulupdate(pwm); - tcon |= pwm_tcon_autoreload(pwm); + tcon |= pwm_tcon_manulupdate(s3c_pwm); + tcon |= pwm_tcon_autoreload(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); - tcon &= ~pwm_tcon_manulupdate(pwm); + tcon &= ~pwm_tcon_manulupdate(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); local_irq_restore(flags); @@ -278,103 +226,122 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) return 0; } -EXPORT_SYMBOL(pwm_config); - -static int pwm_register(struct pwm_device *pwm) -{ - pwm->duty_ns = -1; - pwm->period_ns = -1; - - mutex_lock(&pwm_lock); - list_add_tail(&pwm->list, &pwm_list); - mutex_unlock(&pwm_lock); - - return 0; -} - static int s3c_pwm_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct s3c_pwm_device *s3c_pwm; struct pwm_device *pwm; + struct pwm_ops *pops; unsigned long flags; unsigned long tcon; unsigned int id = pdev->id; - int ret; + int ret = 0; if (id == 4) { dev_err(dev, "TIMER4 is currently not supported\n"); return -ENXIO; } + s3c_pwm = kzalloc(sizeof(struct s3c_pwm_device), GFP_KERNEL); + if (s3c_pwm == NULL) { + dev_err(dev, "failed to allocate pwm_device\n"); + return -ENOMEM; + } + s3c_pwm->pdev = pdev; pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (pwm == NULL) { dev_err(dev, "failed to allocate pwm_device\n"); - return -ENOMEM; + goto err_alloc; + ret = -ENOMEM; + } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(dev, "failed to allocate memory\n"); + goto err_alloc1; + ret = -ENOMEM; } - - pwm->pdev = pdev; - pwm->pwm_id = id; /* calculate base of control bits in TCON */ - pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; + s3c_pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; - pwm->clk = clk_get(dev, "pwm-tin"); - if (IS_ERR(pwm->clk)) { + s3c_pwm->clk = clk_get(dev, "pwm-tin"); + if (IS_ERR(s3c_pwm->clk)) { dev_err(dev, "failed to get pwm tin clk\n"); - ret = PTR_ERR(pwm->clk); - goto err_alloc; + ret = PTR_ERR(s3c_pwm->clk); + goto err_alloc2; } - pwm->clk_div = clk_get(dev, "pwm-tdiv"); - if (IS_ERR(pwm->clk_div)) { + s3c_pwm->clk_div = clk_get(dev, "pwm-tdiv"); + if (IS_ERR(s3c_pwm->clk_div)) { dev_err(dev, "failed to get pwm tdiv clk\n"); - ret = PTR_ERR(pwm->clk_div); + ret = PTR_ERR(s3c_pwm->clk_div); goto err_clk_tin; } local_irq_save(flags); tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_invert(pwm); + tcon |= pwm_tcon_invert(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); local_irq_restore(flags); + pops->pwm_config = s3c_pwm_config; + pops->pwm_enable = s3c_pwm_enable; + pops->pwm_disable = s3c_pwm_disable; + pops->name = pdev->name; + + pwm->dev = dev; + pwm->pwm_id = id; + pwm->pops = pops; + pwm->data = s3c_pwm; - ret = pwm_register(pwm); + s3c_pwm->duty_ns = -1; + s3c_pwm->period_ns = -1; + ret = pwm_device_register(pwm); if (ret) { dev_err(dev, "failed to register pwm\n"); goto err_clk_tdiv; } - pwm_dbg(pwm, "config bits %02x\n", - (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f); + dev_dbg(dev, "config bits %02x\n", + (__raw_readl(S3C2410_TCON) >> s3c_pwm->tcon_base) & 0x0f); dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", - clk_get_rate(pwm->clk), - clk_get_rate(pwm->clk_div), - pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base); + clk_get_rate(s3c_pwm->clk), + clk_get_rate(s3c_pwm->clk_div), + pwm_is_tdiv(s3c_pwm) ? "div" : "ext", s3c_pwm->tcon_base); platform_set_drvdata(pdev, pwm); return 0; - err_clk_tdiv: - clk_put(pwm->clk_div); +err_clk_tdiv: + clk_put(s3c_pwm->clk_div); - err_clk_tin: - clk_put(pwm->clk); +err_clk_tin: + clk_put(s3c_pwm->clk); - err_alloc: +err_alloc2: + kfree(pops); + +err_alloc1: kfree(pwm); + +err_alloc: + kfree(s3c_pwm); return ret; } static int __devexit s3c_pwm_remove(struct platform_device *pdev) { struct pwm_device *pwm = platform_get_drvdata(pdev); + struct s3c_pwm_device *s3c_pwm = pwm->data; - clk_put(pwm->clk_div); - clk_put(pwm->clk); + pwm_device_unregister(pwm); + clk_put(s3c_pwm->clk_div); + clk_put(s3c_pwm->clk); + kfree(s3c_pwm); + kfree(pwm->pops); kfree(pwm); return 0; @@ -384,13 +351,14 @@ static int __devexit s3c_pwm_remove(struct platform_device *pdev) static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state) { struct pwm_device *pwm = platform_get_drvdata(pdev); + struct s3c_pwm_device *s3c_pwm = pwm->data; /* No one preserve these values during suspend so reset them * Otherwise driver leaves PWM unconfigured if same values * passed to pwm_config */ - pwm->period_ns = 0; - pwm->duty_ns = 0; + s3c_pwm->period_ns = 0; + s3c_pwm->duty_ns = 0; return 0; } @@ -398,11 +366,12 @@ static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state) static int s3c_pwm_resume(struct platform_device *pdev) { struct pwm_device *pwm = platform_get_drvdata(pdev); + struct s3c_pwm_device *s3c_pwm = pwm->data; unsigned long tcon; /* Restore invertion */ tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_invert(pwm); + tcon |= pwm_tcon_invert(s3c_pwm); __raw_writel(tcon, S3C2410_TCON); return 0; diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c index a26a6fa..9f46767 100644 --- a/arch/mips/jz4740/pwm.c +++ b/arch/mips/jz4740/pwm.c @@ -152,7 +152,7 @@ int pwm_enable(struct pwm_device *pwm) return 0; } -void pwm_disable(struct pwm_device *pwm) +int pwm_disable(struct pwm_device *pwm) { uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index b0f2c00..6a6ea41 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -129,6 +129,12 @@ #define twl_has_pwrbutton() false #endif +#if defined CONFIG_TWL6030_PWM +#define twl_has_pwm() true +#else +#define twl_has_pwm() false +#endif + #define SUB_CHIP_ID0 0 #define SUB_CHIP_ID1 1 #define SUB_CHIP_ID2 2 @@ -825,6 +831,13 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features) if (IS_ERR(child)) return PTR_ERR(child); } + if (twl_has_pwm()) { + child = add_child(SUB_CHIP_ID2, "twl6030_pwm", + NULL, 0, + false, 0, 0); + if (IS_ERR(child)) + return PTR_ERR(child); + } return 0; } diff --git a/drivers/mfd/twl6030-pwm.c b/drivers/mfd/twl6030-pwm.c index 5d25bdc..b78324b 100644 --- a/drivers/mfd/twl6030-pwm.c +++ b/drivers/mfd/twl6030-pwm.c @@ -20,8 +20,10 @@ #include #include -#include #include +#include +#include +#include #define LED_PWM_CTRL1 0xF4 #define LED_PWM_CTRL2 0xF5 @@ -45,15 +47,10 @@ #define PWM_CTRL2_MODE_MASK 0x3 -struct pwm_device { - const char *label; - unsigned int pwm_id; -}; - -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +int twl6030_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { u8 duty_cycle; - int ret; + int ret = 0; if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; @@ -69,12 +66,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) } return 0; } -EXPORT_SYMBOL(pwm_config); -int pwm_enable(struct pwm_device *pwm) +int twl6030_pwm_enable(struct pwm_device *pwm) { u8 val; - int ret; + int ret = 0; ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); if (ret < 0) { @@ -95,18 +91,17 @@ int pwm_enable(struct pwm_device *pwm) twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); return 0; } -EXPORT_SYMBOL(pwm_enable); -void pwm_disable(struct pwm_device *pwm) +int twl6030_pwm_disable(struct pwm_device *pwm) { u8 val; - int ret; + int ret = 0; ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2); if (ret < 0) { pr_err("%s: Failed to disable PWM, Error %d\n", pwm->label, ret); - return; + return ret; } val &= ~PWM_CTRL2_MODE_MASK; @@ -116,48 +111,86 @@ void pwm_disable(struct pwm_device *pwm) if (ret < 0) { pr_err("%s: Failed to disable PWM, Error %d\n", pwm->label, ret); - return; } - return; + return ret; } -EXPORT_SYMBOL(pwm_disable); -struct pwm_device *pwm_request(int pwm_id, const char *label) +static int __devinit twl6030_pwm_probe(struct platform_device *pdev) { - u8 val; - int ret; struct pwm_device *pwm; + struct pwm_ops *pops; + int ret; + u8 val; pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (pwm == NULL) { - pr_err("%s: failed to allocate memory\n", label); - return NULL; + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pwm); + return -ENOMEM; } - pwm->label = label; - pwm->pwm_id = pwm_id; - + pops->pwm_config = twl6030_pwm_config; + pops->pwm_enable = twl6030_pwm_enable; + pops->pwm_disable = twl6030_pwm_disable; + pops->name = &pdev->name; + pwm->dev = &pdev->dev; + pwm->pwm_id = pdev->id; + pwm->pops = pops; + ret = pwm_device_register(pwm); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + kfree(pwm); + kfree(pops); + return ret; + } + platform_set_drvdata(pdev, pwm); /* Configure PWM */ val = PWM_CTRL2_DIS_PD | PWM_CTRL2_CURR_02 | PWM_CTRL2_SRC_VAC | - PWM_CTRL2_MODE_HW; + PWM_CTRL2_MODE_HW; ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2); - if (ret < 0) { - pr_err("%s: Failed to configure PWM, Error %d\n", - pwm->label, ret); - - kfree(pwm); - return NULL; + dev_err(&pdev->dev, "Failed to configure PWM, Error %d\n", ret); + return ret; } - - return pwm; + dev_dbg(&pdev->dev, "pwm probe successful\n"); + return ret; } -EXPORT_SYMBOL(pwm_request); -void pwm_free(struct pwm_device *pwm) +static int __devexit twl6030_pwm_remove(struct platform_device *pdev) { - pwm_disable(pwm); + struct pwm_device *pwm = platform_get_drvdata(pdev); + + pwm_device_unregister(pwm); + kfree(pwm->pops); kfree(pwm); + dev_dbg(&pdev->dev, "pwm driver removed\n"); + return 0; } -EXPORT_SYMBOL(pwm_free); + +static struct platform_driver twl6030_pwm_driver = { + .driver = { + .name = "twl6030_pwm", + .owner = THIS_MODULE, + }, + .probe = twl6030_pwm_probe, + .remove = __devexit_p(twl6030_pwm_remove), +}; + +static int __init twl6030_pwm_init(void) +{ + return platform_driver_register(&twl6030_pwm_driver); +} + +static void __exit twl6030_pwm_deinit(void) +{ + platform_driver_unregister(&twl6030_pwm_driver); +} + +subsys_initcall(twl6030_pwm_init); +module_exit(twl6030_pwm_deinit); diff --git a/drivers/misc/ab8500-pwm.c b/drivers/misc/ab8500-pwm.c index 54e3d05..d2b23b6 100644 --- a/drivers/misc/ab8500-pwm.c +++ b/drivers/misc/ab8500-pwm.c @@ -23,16 +23,9 @@ #define ENABLE_PWM 1 #define DISABLE_PWM 0 -struct pwm_device { - struct device *dev; - struct list_head node; - const char *label; - unsigned int pwm_id; -}; - static LIST_HEAD(pwm_list); -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +int ab8500_pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { int ret = 0; unsigned int higher_val, lower_val; @@ -60,23 +53,21 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) return ret; } -EXPORT_SYMBOL(pwm_config); -int pwm_enable(struct pwm_device *pwm) +int ab8500_pwm_enable(struct pwm_device *pwm) { int ret; ret = abx500_mask_and_set_register_interruptible(pwm->dev, AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, - 1 << (pwm->pwm_id-1), ENABLE_PWM); + 1 << (pwm->pwm_id-1), 1 << (pwm->pwm_id-1)); if (ret < 0) dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", pwm->label, ret); return ret; } -EXPORT_SYMBOL(pwm_enable); -void pwm_disable(struct pwm_device *pwm) +int ab8500_pwm_disable(struct pwm_device *pwm) { int ret; @@ -86,58 +77,56 @@ void pwm_disable(struct pwm_device *pwm) if (ret < 0) dev_err(pwm->dev, "%s: Failed to disable PWM, Error %d\n", pwm->label, ret); - return; -} -EXPORT_SYMBOL(pwm_disable); - -struct pwm_device *pwm_request(int pwm_id, const char *label) -{ - struct pwm_device *pwm; - - list_for_each_entry(pwm, &pwm_list, node) { - if (pwm->pwm_id == pwm_id) { - pwm->label = label; - pwm->pwm_id = pwm_id; - return pwm; - } - } - - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(pwm_request); - -void pwm_free(struct pwm_device *pwm) -{ - pwm_disable(pwm); + return ret; } -EXPORT_SYMBOL(pwm_free); static int __devinit ab8500_pwm_probe(struct platform_device *pdev) { - struct pwm_device *pwm; + int ret = 0; + struct pwm_ops *pops; + struct pwm_device *pwm_dev; /* * Nothing to be done in probe, this is required to get the * device which is required for ab8500 read and write */ - pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); - if (pwm == NULL) { + pops = kzalloc(sizeof(struct pwm_ops), GFP_KERNEL); + if (pops == NULL) { dev_err(&pdev->dev, "failed to allocate memory\n"); return -ENOMEM; } - pwm->dev = &pdev->dev; - pwm->pwm_id = pdev->id; - list_add_tail(&pwm->node, &pwm_list); - platform_set_drvdata(pdev, pwm); - dev_dbg(pwm->dev, "pwm probe successful\n"); - return 0; + pwm_dev = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (pwm_dev == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + kfree(pops); + return -ENOMEM; + } + pops->pwm_config = ab8500_pwm_config; + pops->pwm_enable = ab8500_pwm_enable; + pops->pwm_disable = ab8500_pwm_disable; + pops->name = "ab8500"; + pwm_dev->dev = &pdev->dev; + pwm_dev->pwm_id = pdev->id; + pwm_dev->pops = pops; + ret = pwm_device_register(pwm_dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register pwm device\n"); + kfree(pwm_dev); + kfree(pops); + return ret; + } + platform_set_drvdata(pdev, pwm_dev); + dev_dbg(&pdev->dev, "pwm probe successful\n"); + return ret; } static int __devexit ab8500_pwm_remove(struct platform_device *pdev) { - struct pwm_device *pwm = platform_get_drvdata(pdev); - list_del(&pwm->node); + struct pwm_device *pwm_dev = platform_get_drvdata(pdev); + + pwm_device_unregister(pwm_dev); dev_dbg(&pdev->dev, "pwm driver removed\n"); - kfree(pwm); + kfree(pwm_dev->pops); + kfree(pwm_dev); return 0; } diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 5d10106..a88640c 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -4,6 +4,7 @@ menuconfig PWM_DEVICES bool "PWM devices" + depends on ARM default y ---help--- Say Y here to get to see options for device drivers from various diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c index b84027a..3a0d426 100644 --- a/drivers/pwm/pwm-core.c +++ b/drivers/pwm/pwm-core.c @@ -11,11 +11,6 @@ #include #include -struct pwm_device { - struct pwm_ops *pops; - int pwm_id; -}; - struct pwm_dev_info { struct pwm_device *pwm_dev; struct list_head list; @@ -40,9 +35,9 @@ int pwm_enable(struct pwm_device *pwm) } EXPORT_SYMBOL(pwm_enable); -void pwm_disable(struct pwm_device *pwm) +int pwm_disable(struct pwm_device *pwm) { - pwm->pops->pwm_disable(pwm); + return pwm->pops->pwm_disable(pwm); } EXPORT_SYMBOL(pwm_disable); diff --git a/include/linux/pwm.h b/include/linux/pwm.h index 6e7da1f..4344c0b 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -1,14 +1,29 @@ #ifndef __LINUX_PWM_H #define __LINUX_PWM_H -struct pwm_device; +/* + * TODO: #if defined CONFIG_PWM_CORE has to be removed after mips jz4740 + * pwm driver aligning with pwm-core.c driver. + */ +#if defined CONFIG_PWM_CORE +struct pwm_device { + struct pwm_ops *pops; + struct device *dev; + struct list_head node; + const char *label; + unsigned int pwm_id; + void *data; +}; struct pwm_ops { int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int period_ns); int (*pwm_enable)(struct pwm_device *pwm); int (*pwm_disable)(struct pwm_device *pwm); - char *name; + const char *name; }; +#else +struct pwm_device; +#endif /* * pwm_request - request a PWM device @@ -33,7 +48,7 @@ int pwm_enable(struct pwm_device *pwm); /* * pwm_disable - stop a PWM output toggling */ -void pwm_disable(struct pwm_device *pwm); +int pwm_disable(struct pwm_device *pwm); int pwm_device_register(struct pwm_device *pwm_dev); int pwm_device_unregister(struct pwm_device *pwm_dev); -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 12:36:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:37:18 +0200 (CEST) Received: from eu1sys200aog118.obsmtp.com ([207.126.144.145]:53337 "EHLO eu1sys200aog118.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491949Ab0I1KgH (ORCPT ); Tue, 28 Sep 2010 12:36:07 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHFBXaQwiNgHNo+6opxTIZcbMb5SsK/@postini.com; Tue, 28 Sep 2010 10:36:06 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 55F23CB; Tue, 28 Sep 2010 10:35:46 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id F0C2367E; Tue, 28 Sep 2010 10:35:45 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 68FE624C07D; Tue, 28 Sep 2010 12:35:39 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 12:35:44 +0200 From: Arun Murthy To: , , , , , , , , , , Cc: , , , , Subject: [PATCH 2/7] backlight:pwm: add an element 'name' to platform data Date: Tue, 28 Sep 2010 16:05:29 +0530 Message-ID: <1285670134-18063-3-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27865 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22258 Content-Length: 1334 Lines: 40 A new element 'name' is added to pwm backlight platform data structure. This is required to identify the pwm device. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/video/backlight/pwm_bl.c | 4 +++- include/linux/pwm_backlight.h | 1 + 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c index 5504435..b0978a8 100644 --- a/drivers/video/backlight/pwm_bl.c +++ b/drivers/video/backlight/pwm_bl.c @@ -94,7 +94,9 @@ static int pwm_backlight_probe(struct platform_device *pdev) pb->notify = data->notify; pb->dev = &pdev->dev; - pb->pwm = pwm_request(data->pwm_id, "backlight"); + if (!data->name) + data->name = "backlight"; + pb->pwm = pwm_request(data->pwm_id, data->name); if (IS_ERR(pb->pwm)) { dev_err(&pdev->dev, "unable to request PWM for backlight\n"); ret = PTR_ERR(pb->pwm); diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h index 01b3d75..c2ce8f8 100644 --- a/include/linux/pwm_backlight.h +++ b/include/linux/pwm_backlight.h @@ -6,6 +6,7 @@ struct platform_pwm_backlight_data { int pwm_id; + char *name; unsigned int max_brightness; unsigned int dft_brightness; unsigned int pwm_period_ns; -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 12:36:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:37:51 +0200 (CEST) Received: from eu1sys200aog108.obsmtp.com ([207.126.144.125]:52344 "EHLO eu1sys200aog108.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491957Ab0I1KgM (ORCPT ); Tue, 28 Sep 2010 12:36:12 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob108.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHFA+uBOH+8LBb3hDKdVIq7y7AntmOA@postini.com; Tue, 28 Sep 2010 10:36:11 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 103A0114; Tue, 28 Sep 2010 10:35:44 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 57FDF681; Tue, 28 Sep 2010 10:35:43 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 58A19A8065; Tue, 28 Sep 2010 12:35:37 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 12:35:41 +0200 From: Arun Murthy To: , , , , , , , , , , Cc: , , , , Subject: [PATCH 1/7] pwm: Add pwm core driver Date: Tue, 28 Sep 2010 16:05:28 +0530 Message-ID: <1285670134-18063-2-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27866 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22266 Content-Length: 6378 Lines: 250 The existing pwm based led and backlight driver makes use of the pwm(include/linux/pwm.h). So all the board specific pwm drivers will be exposing the same set of function name as in include/linux/pwm.h. As a result build fails in case of multi soc environments where each soc has a pwm device in it. In order to overcome this issue all the pwm drivers must register to some core pwm driver with function pointers for pwm operations (i.e pwm_config, pwm_enable, pwm_disable). The clients of pwm device will have to call pwm_request, wherein they will get the pointer to struct pwm_ops. This structure include function pointers for pwm_config, pwm_enable and pwm_disable. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/pwm/Kconfig | 16 ++++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-core.c | 129 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pwm.h | 12 ++++- 6 files changed, 160 insertions(+), 1 deletions(-) create mode 100644 drivers/pwm/Kconfig create mode 100644 drivers/pwm/Makefile create mode 100644 drivers/pwm/pwm-core.c diff --git a/drivers/Kconfig b/drivers/Kconfig index a2b902f..e042f27 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -111,4 +111,6 @@ source "drivers/xen/Kconfig" source "drivers/staging/Kconfig" source "drivers/platform/Kconfig" + +source "drivers/pwm/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 4ca727d..0061ec4 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -116,3 +116,4 @@ obj-$(CONFIG_STAGING) += staging/ obj-y += platform/ obj-y += ieee802154/ obj-y += vbus/ +obj-$(CONFIG_PWM_DEVICES) += pwm/ diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig new file mode 100644 index 0000000..5d10106 --- /dev/null +++ b/drivers/pwm/Kconfig @@ -0,0 +1,16 @@ +# +# PWM devices +# + +menuconfig PWM_DEVICES + bool "PWM devices" + default y + ---help--- + Say Y here to get to see options for device drivers from various + different categories. This option alone does not add any kernel code. + + If you say N, all options in this submenu will be skipped and disabled. + +if PWM_DEVICES + +endif # PWM_DEVICES diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile new file mode 100644 index 0000000..552f969 --- /dev/null +++ b/drivers/pwm/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PWM_DEVICES) += pwm-core.o diff --git a/drivers/pwm/pwm-core.c b/drivers/pwm/pwm-core.c new file mode 100644 index 0000000..b84027a --- /dev/null +++ b/drivers/pwm/pwm-core.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * Author: Arun R Murthy + */ +#include +#include +#include +#include +#include +#include + +struct pwm_device { + struct pwm_ops *pops; + int pwm_id; +}; + +struct pwm_dev_info { + struct pwm_device *pwm_dev; + struct list_head list; +}; +static struct pwm_dev_info *di; + +DECLARE_RWSEM(pwm_list_lock); + +void __deprecated pwm_free(struct pwm_device *pwm) +{ +} + +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + return pwm->pops->pwm_config(pwm, duty_ns, period_ns); +} +EXPORT_SYMBOL(pwm_config); + +int pwm_enable(struct pwm_device *pwm) +{ + return pwm->pops->pwm_enable(pwm); +} +EXPORT_SYMBOL(pwm_enable); + +void pwm_disable(struct pwm_device *pwm) +{ + pwm->pops->pwm_disable(pwm); +} +EXPORT_SYMBOL(pwm_disable); + +int pwm_device_register(struct pwm_device *pwm_dev) +{ + struct pwm_dev_info *pwm; + + down_write(&pwm_list_lock); + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); + if (!pwm) { + up_write(&pwm_list_lock); + return -ENOMEM; + } + pwm->pwm_dev = pwm_dev; + list_add_tail(&pwm->list, &di->list); + up_write(&pwm_list_lock); + + return 0; +} +EXPORT_SYMBOL(pwm_device_register); + +int pwm_device_unregister(struct pwm_device *pwm_dev) +{ + struct pwm_dev_info *tmp; + struct list_head *pos, *tmp_lst; + + down_write(&pwm_list_lock); + list_for_each_safe(pos, tmp_lst, &di->list) { + tmp = list_entry(pos, struct pwm_dev_info, list); + if (tmp->pwm_dev == pwm_dev) { + list_del(pos); + kfree(tmp); + up_write(&pwm_list_lock); + return 0; + } + } + up_write(&pwm_list_lock); + return -ENOENT; +} +EXPORT_SYMBOL(pwm_device_unregister); + +struct pwm_device *pwm_request(int pwm_id, const char *name) +{ + struct pwm_dev_info *pwm; + struct list_head *pos; + + down_read(&pwm_list_lock); + list_for_each(pos, &di->list) { + pwm = list_entry(pos, struct pwm_dev_info, list); + if ((!strcmp(pwm->pwm_dev->pops->name, name)) && + (pwm->pwm_dev->pwm_id == pwm_id)) { + up_read(&pwm_list_lock); + return pwm->pwm_dev; + } + } + up_read(&pwm_list_lock); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(pwm_request); + +static int __init pwm_init(void) +{ + struct pwm_dev_info *pwm; + + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + INIT_LIST_HEAD(&pwm->list); + di = pwm; + return 0; +} + +static void __exit pwm_exit(void) +{ + kfree(di); +} + +subsys_initcall(pwm_init); +module_exit(pwm_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Arun R Murthy"); +MODULE_ALIAS("core:pwm"); +MODULE_DESCRIPTION("Core pwm driver"); diff --git a/include/linux/pwm.h b/include/linux/pwm.h index 7c77575..6e7da1f 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -3,6 +3,13 @@ struct pwm_device; +struct pwm_ops { + int (*pwm_config)(struct pwm_device *pwm, int duty_ns, int period_ns); + int (*pwm_enable)(struct pwm_device *pwm); + int (*pwm_disable)(struct pwm_device *pwm); + char *name; +}; + /* * pwm_request - request a PWM device */ @@ -11,7 +18,7 @@ struct pwm_device *pwm_request(int pwm_id, const char *label); /* * pwm_free - free a PWM device */ -void pwm_free(struct pwm_device *pwm); +void __deprecated pwm_free(struct pwm_device *pwm); /* * pwm_config - change a PWM device configuration @@ -28,4 +35,7 @@ int pwm_enable(struct pwm_device *pwm); */ void pwm_disable(struct pwm_device *pwm); +int pwm_device_register(struct pwm_device *pwm_dev); +int pwm_device_unregister(struct pwm_device *pwm_dev); + #endif /* __LINUX_PWM_H */ -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 12:36:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:38:20 +0200 (CEST) Received: from eu1sys200aog103.obsmtp.com ([207.126.144.115]:59210 "EHLO eu1sys200aog103.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491958Ab0I1KgM (ORCPT ); Tue, 28 Sep 2010 12:36:12 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob103.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHFD0RwNLFhcejHSK1LG8rkfjd7Nsrm@postini.com; Tue, 28 Sep 2010 10:36:12 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 89E3677; Tue, 28 Sep 2010 10:35:58 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2D83B21F3; Tue, 28 Sep 2010 10:35:58 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 5A7CDA8095; Tue, 28 Sep 2010 12:35:52 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 12:35:56 +0200 From: Arun Murthy To: , , , , , , , , , , Cc: , , , , Subject: [PATCH 6/7] pwm: move existing pwm driver to drivers/pwm Date: Tue, 28 Sep 2010 16:05:33 +0530 Message-ID: <1285670134-18063-7-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27867 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22267 Content-Length: 4334 Lines: 126 As of now only ab8500 and twl6030 are moved. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/mfd/Kconfig | 9 --------- drivers/mfd/Makefile | 1 - drivers/misc/Kconfig | 9 --------- drivers/misc/Makefile | 1 - drivers/pwm/Kconfig | 18 ++++++++++++++++++ drivers/pwm/Makefile | 3 +++ drivers/{misc/ab8500-pwm.c => pwm/pwm-ab8500.c} | 0 drivers/{mfd/twl6030-pwm.c => pwm/pwm-twl6040.c} | 0 8 files changed, 21 insertions(+), 20 deletions(-) rename drivers/{misc/ab8500-pwm.c => pwm/pwm-ab8500.c} (100%) rename drivers/{mfd/twl6030-pwm.c => pwm/pwm-twl6040.c} (100%) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 256fabd..ab1d376 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -186,15 +186,6 @@ config TWL4030_CODEC select MFD_CORE default n -config TWL6030_PWM - tristate "TWL6030 PWM (Pulse Width Modulator) Support" - depends on TWL4030_CORE - select HAVE_PWM - default n - help - Say yes here if you want support for TWL6030 PWM. - This is used to control charging LED brightness. - config MFD_STMPE bool "Support STMicroelectronics STMPE" depends on I2C=y && GENERIC_HARDIRQS diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index d5968cd..1a89dbf 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -37,7 +37,6 @@ obj-$(CONFIG_MENELAUS) += menelaus.o obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o obj-$(CONFIG_TWL4030_CODEC) += twl4030-codec.o -obj-$(CONFIG_TWL6030_PWM) += twl6030-pwm.o obj-$(CONFIG_MFD_MC13783) += mc13783-core.o diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ff8ea55..2c38d4e 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -62,15 +62,6 @@ config ATMEL_PWM purposes including software controlled power-efficient backlights on LCD displays, motor control, and waveform generation. -config AB8500_PWM - bool "AB8500 PWM support" - depends on AB8500_CORE - select HAVE_PWM - help - This driver exports functions to enable/disble/config/free Pulse - Width Modulation in the Analog Baseband Chip AB8500. - It is used by led and backlight driver to control the intensity. - config ATMEL_TCLIB bool "Atmel AT32/AT91 Timer/Counter Library" depends on (AVR32 || ARCH_AT91) diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 5da82965..21b4761 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -35,5 +35,4 @@ obj-y += eeprom/ obj-y += cb710/ obj-$(CONFIG_VMWARE_BALLOON) += vmware_balloon.o obj-$(CONFIG_ARM_CHARLCD) += arm-charlcd.o -obj-$(CONFIG_AB8500_PWM) += ab8500-pwm.o obj-$(CONFIG_PCH_PHUB) += pch_phub.o diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a88640c..e347365 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -14,4 +14,22 @@ menuconfig PWM_DEVICES if PWM_DEVICES +config AB8500_PWM + bool "AB8500 PWM support" + depends on AB8500_CORE + select HAVE_PWM + help + This driver exports functions to enable/disble/config/free Pulse + Width Modulation in the Analog Baseband Chip AB8500. + It is used by led and backlight driver to control the intensity. + +config TWL6030_PWM + tristate "TWL6030 PWM (Pulse Width Modulator) Support" + depends on TWL4030_CORE + select HAVE_PWM + default n + help + Say yes here if you want support for TWL6030 PWM. + This is used to control charging LED brightness. + endif # PWM_DEVICES diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 552f969..f35afb4 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -1 +1,4 @@ obj-$(CONFIG_PWM_DEVICES) += pwm-core.o + +obj-$(CONFIG_AB8500_PWM) += pwm-ab8500.o +obj-$(CONFIG_TWL6030_PWM) += pwm-twl6030.o diff --git a/drivers/misc/ab8500-pwm.c b/drivers/pwm/pwm-ab8500.c similarity index 100% rename from drivers/misc/ab8500-pwm.c rename to drivers/pwm/pwm-ab8500.c diff --git a/drivers/mfd/twl6030-pwm.c b/drivers/pwm/pwm-twl6040.c similarity index 100% rename from drivers/mfd/twl6030-pwm.c rename to drivers/pwm/pwm-twl6040.c -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 12:36:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:38:46 +0200 (CEST) Received: from eu1sys200aog109.obsmtp.com ([207.126.144.127]:43765 "EHLO eu1sys200aog109.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491960Ab0I1KgR (ORCPT ); Tue, 28 Sep 2010 12:36:17 +0200 Received: from source ([138.198.100.35]) (using TLSv1) by eu1sys200aob109.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHFDrH9RId+ZuGgKbhPnlUZaZybEiAm@postini.com; Tue, 28 Sep 2010 10:36:16 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C882D118; Tue, 28 Sep 2010 10:35:55 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 103C1687; Tue, 28 Sep 2010 10:35:55 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 7AD2A24C2AB; Tue, 28 Sep 2010 12:35:48 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 12:35:53 +0200 From: Arun Murthy To: , , , , , , , , , , Cc: , , , , Subject: [PATCH 5/7] platform: Update the pwm based led and backlight platform data Date: Tue, 28 Sep 2010 16:05:32 +0530 Message-ID: <1285670134-18063-6-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27868 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22268 Content-Length: 11534 Lines: 300 mxc-pwm: Update the platform data with pwm name for backlight s3c24xx-pwm: update platform data for backlight with pwm name Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- arch/arm/mach-pxa/cm-x300.c | 1 + arch/arm/mach-pxa/colibri-pxa270-income.c | 1 + arch/arm/mach-pxa/ezx.c | 1 + arch/arm/mach-pxa/hx4700.c | 1 + arch/arm/mach-pxa/lpd270.c | 1 + arch/arm/mach-pxa/magician.c | 1 + arch/arm/mach-pxa/mainstone.c | 1 + arch/arm/mach-pxa/mioa701.c | 1 + arch/arm/mach-pxa/palm27x.c | 1 + arch/arm/mach-pxa/palmtc.c | 1 + arch/arm/mach-pxa/palmte2.c | 1 + arch/arm/mach-pxa/pcm990-baseboard.c | 1 + arch/arm/mach-pxa/raumfeld.c | 1 + arch/arm/mach-pxa/tavorevb.c | 2 ++ arch/arm/mach-pxa/viper.c | 1 + arch/arm/mach-pxa/z2.c | 2 ++ arch/arm/mach-pxa/zylonite.c | 1 + arch/arm/mach-s3c2410/mach-h1940.c | 1 + arch/arm/mach-s3c2440/mach-rx1950.c | 1 + arch/arm/mach-s3c64xx/mach-hmt.c | 1 + arch/arm/mach-s3c64xx/mach-smartq.c | 1 + 21 files changed, 23 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index c70e6c2..ddf763b 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -301,6 +301,7 @@ static inline void cm_x300_init_lcd(void) {} #if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) static struct platform_pwm_backlight_data cm_x300_backlight_data = { .pwm_id = 2, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 10000, diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index 37f0f3e..d5b5874 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -234,6 +234,7 @@ static inline void income_lcd_init(void) {} #if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM__MODULE) static struct platform_pwm_backlight_data income_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 0x3ff, .dft_brightness = 0x1ff, .pwm_period_ns = 1000000, diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 626c82b..747f217 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -49,6 +49,7 @@ static struct platform_pwm_backlight_data ezx_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 848c861..8e4905a 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -565,6 +565,7 @@ static struct platform_device hx4700_lcd = { static struct platform_pwm_backlight_data backlight_data = { .pwm_id = 1, + .name = "pxa25x-pwm", .max_brightness = 200, .dft_brightness = 100, .pwm_period_ns = 30923, diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index d279507..91efade 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -273,6 +273,7 @@ static struct platform_device lpd270_flash_device[2] = { static struct platform_pwm_backlight_data lpd270_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 1, .dft_brightness = 1, .pwm_period_ns = 78770, diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index e81dd0c..bb657a4 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -382,6 +382,7 @@ static void magician_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 272, .dft_brightness = 100, .pwm_period_ns = 30923, diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 5543c64..cbd359c 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -342,6 +342,7 @@ static struct platform_device mst_flash_device[2] = { #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static struct platform_pwm_backlight_data mainstone_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index dc66942..e442088 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -224,6 +224,7 @@ static void mio_gpio_free(struct gpio_ress *gpios, int size) /* LCD Screen and Backlight */ static struct platform_pwm_backlight_data mioa701_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 50, .pwm_period_ns = 4000 * 1024, /* Fl = 250kHz */ diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c index 77ad6d3..46677a4 100644 --- a/arch/arm/mach-pxa/palm27x.c +++ b/arch/arm/mach-pxa/palm27x.c @@ -321,6 +321,7 @@ static void palm27x_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data palm27x_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 0xfe, .dft_brightness = 0x7e, .pwm_period_ns = 3500, diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index ce1104d..385a0b5 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -180,6 +180,7 @@ static void palmtc_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data palmtc_backlight_data = { .pwm_id = 1, + .name = "pxa25x-pwm", .max_brightness = PALMTC_MAX_INTENSITY, .dft_brightness = PALMTC_MAX_INTENSITY, .pwm_period_ns = PALMTC_PERIOD_NS, diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 93c11a0..b7e95f4 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -177,6 +177,7 @@ static void palmte2_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data palmte2_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = PALMTE2_MAX_INTENSITY, .dft_brightness = PALMTE2_MAX_INTENSITY, .pwm_period_ns = PALMTE2_PERIOD_NS, diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index f56ae10..29c7e88 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -138,6 +138,7 @@ static struct pxafb_mach_info pcm990_fbinfo __initdata = { static struct platform_pwm_backlight_data pcm990_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 67e04f4..98dc2e3 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -535,6 +535,7 @@ static void __init raumfeld_w1_init(void) /* PWM controlled backlight */ static struct platform_pwm_backlight_data raumfeld_pwm_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, /* 10000 ns = 10 ms ^= 100 kHz */ diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index f02dcb5..3164de8 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -168,6 +168,7 @@ static struct platform_pwm_backlight_data tavorevb_backlight_data[] = { [0] = { /* primary backlight */ .pwm_id = 2, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 100000, @@ -175,6 +176,7 @@ static struct platform_pwm_backlight_data tavorevb_backlight_data[] = { [1] = { /* secondary backlight */ .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 100000, diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index e90114a..fdb768c 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -397,6 +397,7 @@ static void viper_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data viper_backlight_data = { .pwm_id = 0, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 1000000, diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index f0d0228..bb3d821 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -204,6 +204,7 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { [0] = { /* Keypad Backlight */ .pwm_id = 1, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 512, .pwm_period_ns = 1260320, @@ -211,6 +212,7 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { [1] = { /* LCD Backlight */ .pwm_id = 2, + .name = "pxa25x-pwm", .max_brightness = 1023, .dft_brightness = 512, .pwm_period_ns = 1260320, diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 5ba9d99..29492bf 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -122,6 +122,7 @@ static inline void zylonite_init_leds(void) {} #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static struct platform_pwm_backlight_data zylonite_backlight_data = { .pwm_id = 3, + .name = "pxa25x-pwm", .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 10000, diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 3ba3bab..357342f 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -224,6 +224,7 @@ static void h1940_backlight_exit(struct device *dev) static struct platform_pwm_backlight_data backlight_data = { .pwm_id = 0, + .name = "s3c24xx-pwm", .max_brightness = 100, .dft_brightness = 50, /* tcnt = 0x31 */ diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 142d1f9..6d993de 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -291,6 +291,7 @@ static int rx1950_backlight_notify(struct device *dev, int brightness) static struct platform_pwm_backlight_data rx1950_backlight_data = { .pwm_id = 0, + .name = "s3c24xx-pwm", .max_brightness = 24, .dft_brightness = 4, .pwm_period_ns = 48000, diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index fba9022..14e9011 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -109,6 +109,7 @@ static void hmt_bl_exit(struct device *dev) static struct platform_pwm_backlight_data hmt_backlight_data = { .pwm_id = 1, + .name = "s3c24xx-pwm", .max_brightness = 100 * 256, .dft_brightness = 40 * 256, .pwm_period_ns = 1000000000 / (100 * 256 * 20), diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index cb1ebeb..20999d5 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -145,6 +145,7 @@ static int smartq_bl_init(struct device *dev) static struct platform_pwm_backlight_data smartq_backlight_data = { .pwm_id = 1, + .name = "s3c24xx-pwm", .max_brightness = 1000, .dft_brightness = 600, .pwm_period_ns = 1000000000 / (1000 * 20), -- 1.7.2.dirty From arun.murthy@stericsson.com Tue Sep 28 12:36:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:39:11 +0200 (CEST) Received: from eu1sys200aog116.obsmtp.com ([207.126.144.141]:44510 "EHLO eu1sys200aog116.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491962Ab0I1KgS (ORCPT ); Tue, 28 Sep 2010 12:36:18 +0200 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob116.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHFEgM2vnWF/zDoKUU58Vz4e/PHAYfm@postini.com; Tue, 28 Sep 2010 10:36:18 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D8ED387; Tue, 28 Sep 2010 10:36:01 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8644921EE; Tue, 28 Sep 2010 10:36:01 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 1D4D7A8094; Tue, 28 Sep 2010 12:35:56 +0200 (CEST) Received: from localhost (10.201.54.119) by exdcvycastm022.EQ1STM.local (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.1.393.1; Tue, 28 Sep 2010 12:36:00 +0200 From: Arun Murthy To: , , , , , , , , , , Cc: , , , , Subject: [PATCH 7/7] pwm: Modify backlight and led Kconfig aligning to pwm core Date: Tue, 28 Sep 2010 16:05:34 +0530 Message-ID: <1285670134-18063-8-git-send-email-arun.murthy@stericsson.com> X-Mailer: git-send-email 1.7.2.dirty In-Reply-To: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain X-archive-position: 27869 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22269 Content-Length: 1887 Lines: 60 PWM based backlight and led driver will not be calling the pwm drivers through the pwm core driver and hence adding dependancy on the same. Signed-off-by: Arun Murthy Acked-by: Linus Walleij --- drivers/leds/Kconfig | 2 +- drivers/pwm/Kconfig | 2 -- drivers/video/backlight/Kconfig | 2 +- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index e411262..eba388f 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -244,7 +244,7 @@ config LEDS_DAC124S085 config LEDS_PWM tristate "PWM driven LED Support" - depends on HAVE_PWM + depends on HAVE_PWM || PWM_CORE help This option enables support for pwm driven LEDs diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e347365..1f8cbc0 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -17,7 +17,6 @@ if PWM_DEVICES config AB8500_PWM bool "AB8500 PWM support" depends on AB8500_CORE - select HAVE_PWM help This driver exports functions to enable/disble/config/free Pulse Width Modulation in the Analog Baseband Chip AB8500. @@ -26,7 +25,6 @@ config AB8500_PWM config TWL6030_PWM tristate "TWL6030 PWM (Pulse Width Modulator) Support" depends on TWL4030_CORE - select HAVE_PWM default n help Say yes here if you want support for TWL6030 PWM. diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index e54a337..73fc17b 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -217,7 +217,7 @@ config BACKLIGHT_CARILLO_RANCH config BACKLIGHT_PWM tristate "Generic PWM based Backlight Driver" - depends on HAVE_PWM + depends on HAVE_PWM || PWM_CORE help If you have a LCD backlight adjustable by PWM, say Y to enable this driver. -- 1.7.2.dirty From hemanthv@ti.com Tue Sep 28 12:43:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:43:18 +0200 (CEST) Received: from comal.ext.ti.com ([198.47.26.152]:37341 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491958Ab0I1KnP (ORCPT ); Tue, 28 Sep 2010 12:43:15 +0200 Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o8SAfuTh021276 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 28 Sep 2010 05:42:01 -0500 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o8SAfbiv025720; Tue, 28 Sep 2010 05:41:38 -0500 (CDT) Received: from 10.24.255.18 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Tue, 28 Sep 2010 16:11:55 +0530 (IST) Message-ID: <48808.10.24.255.18.1285670515.squirrel@dbdmail.itg.ti.com> In-Reply-To: References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <201009281114.31223.anarsoul@gmail.com> <63731.10.24.255.18.1285663815.squirrel@dbdmail.itg.ti.com> <19145.10.24.255.18.1285666483.squirrel@dbdmail.itg.ti.com> Date: Tue, 28 Sep 2010 16:11:55 +0530 (IST) Subject: RE: [PATCH 1/7] pwm: Add pwm core driver From: "Hemanth V" To: "Arun MURTHY" Cc: "linux-omap@vger.kernel.org" , "Vasily Khoruzhick" , "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , "grinberg@compulab.co.il" , "mike@compulab.co.il" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "drwyrm@gmail.com" , "stefan@openezx.org" , "laforge@openezx.org" , "ospite@studenti.unina.it" , "philipp.zabel@gmail.com" , "mad_soft@inbox.ru" , "maz@misterjones.org" , "daniel@caiaq.de" , "haojian.zhuang@marvell.com" , "timur@freescale.com" , "ben-linux@fluff.org" , "support@simtec.co.uk" , "arnaud.patard@rtp-net.org" , "dgreenday@gmail.com" , "akpm@linux-foundation.org" , "mcuelenaere@gmail.com" , "kernel@pengutronix.de" , "andre.goddard@gmail.com" , "jkosina@suse.cz" , "tj@kernel.org" , "hsweeten@visionengravers.com" , "u.kleine-koenig@pengutronix.de" , "kgene.kim@samsung.com" , "ralf@linux-mips.org" , "lars@metafoo.de" , "dilinger@collabora.co.uk" , "mroth@nessie.de" , "randy.dunlap@oracle.com" , "lethal@linux-sh.org" , "rusty@rustcorp.com.au" , "damm@opensource.se" , "mst@redhat.com" , "rpurdie@rpsys.net" , "sguinot@lacie.co" , "sameo@linux.intel.com" , "broonie@opensource.wolfsonmicro.com" , "balajitk@ti.com" , "rnayak@ti.com" , "santosh.shilimkar@ti.com" , "michael.hennerich@analog.com" , "vapier@gentoo.org" , "khali@linux-fr.org" , "jic23@cam.ac.uk" , "re.emese@gmail.com" , "linux@simtec.co.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "Linus WALLEIJ" , "Mattias WALLIN" User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT X-Priority: 3 (Normal) Importance: Normal X-archive-position: 27870 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hemanthv@ti.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22273 Content-Length: 2632 Lines: 56 >> >> >> On 28 of September 2010 10:40:42 Arun Murthy wrote: >> >> >> > The existing pwm based led and backlight driver makes use of >> the >> >> >> > pwm(include/linux/pwm.h). So all the board specific pwm drivers >> >> will >> >> >> > be exposing the same set of function name as in >> >> include/linux/pwm.h. >> >> >> > As a result build fails. >> >> >> >> >> >> Which build fails? One with multi-SoC support? Please be more >> >> specific. >> >> > Sure will add this in v2. >> >> > >> >> >> >> Could you clarify for the benefit of all, which specific issues you >> are >> >> trying to address with this patch series >> > 1. Now since all the pwm driver export same set of >> function(pwm_enable, pwm_disable,..), if it happens that there are two >> pwm driver enabled this >> > leads to re-declaration and results in build failure. The proper way >> to handle this would be to have a pwm core function, and let all the >> pwm >> > drivers register to the pwm core driver. >> > 2. The above scenario also occurs in place of multi-soc environment. >> Lets say OMAP has a pwm module and that is being used for primary lcd >> backlight >> > and twl has a backlight that is being used for controlling the >> charging led brightness. In this case there exists 2 pwm drivers and >> one pwm driver >> > will be used by pwm_bl.c and other by leds-pwm.c >> >> Speaking specifically of OMAP4, twl6030 supports multiple PWMs i.e for >> display/keypad backlight, charging >> led. But there should not be need for multiple drivers since twl6030- >> pwm should be able to support >> all these (currently it doesnot though). So there would single >> pwm_enable, pwm_disable exported and driver >> internally takes care configuring the correct PWM based on id. Would it >> not be similar >> situation for other hardware also. >> > You are right, there is only one pwm module in twl4030/twl6030 and this module might have any number or pwm's line PWM1, PWM2, PWM3 etc. > My consideration is when you have two separate pwm modules on different soc. Its not in case of OMAP boards. But that was just an example that I > gave. > > Let me be more specific, consider an environment where there is an APE and Power Management subsystem(separate IC but on same board/platform) > APE has a pwm module and Power Management SubSystem also has pwm module. Both are part of the platform. > Not there exists two drivers in a single platform and both of them are enabled. Building such a kernel results in re-declaration build error. > Is this something specific to ST chipsets or do you know of any other chips which might use this feature. Thanks Hemanth From sshtylyov@mvista.com Tue Sep 28 12:44:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:45:12 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:45701 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491958Ab0I1Ko7 (ORCPT ); Tue, 28 Sep 2010 12:44:59 +0200 Received: by ewy9 with SMTP id 9so2076933ewy.36 for ; Tue, 28 Sep 2010 03:44:59 -0700 (PDT) Received: by 10.213.89.196 with SMTP id f4mr1090422ebm.3.1285670698977; Tue, 28 Sep 2010 03:44:58 -0700 (PDT) Received: from [192.168.2.2] (ppp83-237-248-241.pppoe.mtu-net.ru [83.237.248.241]) by mx.google.com with ESMTPS id u9sm10222466eeh.17.2010.09.28.03.44.56 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 28 Sep 2010 03:44:57 -0700 (PDT) Message-ID: <4CA1C6C4.20504@mvista.com> Date: Tue, 28 Sep 2010 14:43:16 +0400 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 MIME-Version: 1.0 To: Arun Murthy CC: lars@metafoo.de, akpm@linux-foundation.org, kernel@pengutronix.de, philipp.zabel@gmail.com, robert.jarzmik@free.fr, marek.vasut@gmail.com, eric.y.miao@gmail.com, rpurdie@rpsys.net, sameo@linux.intel.com, kgene.kim@samsung.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, STEricsson_nomadik_linux@list.st.com Subject: Re: [PATCH 3/7] leds: pwm: add a new element 'name' to platform data References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> <1285670134-18063-4-git-send-email-arun.murthy@stericsson.com> In-Reply-To: <1285670134-18063-4-git-send-email-arun.murthy@stericsson.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-archive-position: 27871 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22275 Content-Length: 664 Lines: 26 Hello. On 28-09-2010 14:35, Arun Murthy wrote: > A new element 'name' is added to pwm led platform data structure. > This is required to identify the pwm device. > Signed-off-by: Arun Murthy > Acked-by: Linus Walleij [...] > diff --git a/include/linux/leds_pwm.h b/include/linux/leds_pwm.h > index 33a0711..7a847a0 100644 > --- a/include/linux/leds_pwm.h > +++ b/include/linux/leds_pwm.h > @@ -16,6 +16,7 @@ struct led_pwm { > struct led_pwm_platform_data { > int num_leds; > struct led_pwm *leds; > + char *name; > }; Shouldn't '*name'be aligned, at least with '*leds'? WBR, Sergei From arun.murthy@stericsson.com Tue Sep 28 12:48:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 12:48:57 +0200 (CEST) Received: from eu1sys200aog109.obsmtp.com ([207.126.144.127]:51933 "EHLO eu1sys200aog109.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491958Ab0I1Ksx convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 12:48:53 +0200 Received: from source ([167.4.1.35]) (using TLSv1) by eu1sys200aob109.postini.com ([207.126.147.11]) with SMTP ID DSNKTKHIBFVjFZzB0DsSl+C+sr2G986NGhQx@postini.com; Tue, 28 Sep 2010 10:48:53 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.80.115]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id DD62EC3; Tue, 28 Sep 2010 10:45:01 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 0E09734C; Tue, 28 Sep 2010 10:48:16 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 4E659A8096; Tue, 28 Sep 2010 12:48:10 +0200 (CEST) Received: from EXDCVYMBSTM006.EQ1STM.local ([10.230.100.3]) by exdcvycastm003.EQ1STM.local ([10.230.100.1]) with mapi; Tue, 28 Sep 2010 12:48:15 +0200 From: Arun MURTHY To: Sergei Shtylyov Cc: "lars@metafoo.de" , "akpm@linux-foundation.org" , "kernel@pengutronix.de" , "philipp.zabel@gmail.com" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "eric.y.miao@gmail.com" , "rpurdie@rpsys.net" , "sameo@linux.intel.com" , "kgene.kim@samsung.com" , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , STEricsson_nomadik_linux Date: Tue, 28 Sep 2010 12:48:12 +0200 Subject: RE: [PATCH 3/7] leds: pwm: add a new element 'name' to platform data Thread-Topic: [PATCH 3/7] leds: pwm: add a new element 'name' to platform data Thread-Index: Acte+jRWeNi88ekyQ5KOTcl29A0fyAAAFG4A Message-ID: References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> <1285670134-18063-4-git-send-email-arun.murthy@stericsson.com> <4CA1C6C4.20504@mvista.com> In-Reply-To: <4CA1C6C4.20504@mvista.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-archive-position: 27872 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arun.murthy@stericsson.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22278 Content-Length: 311 Lines: 13 > > @@ -16,6 +16,7 @@ struct led_pwm { > > struct led_pwm_platform_data { > > int num_leds; > > struct led_pwm *leds; > > + char *name; > > }; > > Shouldn't '*name'be aligned, at least with '*leds'? Sure, will take care of this in the v2 patch. Thanks and Regards, Arun R Murthy ------------- From sameo@linux.intel.com Tue Sep 28 15:06:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 15:06:05 +0200 (CEST) Received: from mga01.intel.com ([192.55.52.88]:17698 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491094Ab0I1NGC (ORCPT ); Tue, 28 Sep 2010 15:06:02 +0200 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 28 Sep 2010 06:05:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.57,247,1283756400"; d="scan'208";a="841620498" Received: from unknown (HELO sortiz-mobl) ([10.255.18.134]) by fmsmga001.fm.intel.com with ESMTP; 28 Sep 2010 06:05:48 -0700 Date: Tue, 28 Sep 2010 15:06:11 +0200 From: Samuel Ortiz To: Hemanth V Cc: Arun Murthy , lars@metafoo.de, Andrew Morton , kernel@pengutronix.de, philipp.zabel@gmail.com, robert.jarzmik@free.fr, marek.vasut@gmail.com, eric.y.miao@gmail.com, rpurdie@rpsys.net, kgene.kim@samsung.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, STEricsson_nomadik_linux@list.st.com Subject: Re: [PATCH 1/7] pwm: Add pwm core driver Message-ID: <20100928130610.GB20749@sortiz-mobl> References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> <1285670134-18063-2-git-send-email-arun.murthy@stericsson.com> <040c01cb5f0c$29bcb3b0$LocalHost@wipblrx0099946> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <040c01cb5f0c$29bcb3b0$LocalHost@wipblrx0099946> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 27873 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sameo@linux.intel.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22350 Content-Length: 1440 Lines: 40 On Tue, Sep 28, 2010 at 06:23:24PM +0530, Hemanth V wrote: > ----- Original Message ----- From: "Arun Murthy" > > > > >The existing pwm based led and backlight driver makes use of the > >pwm(include/linux/pwm.h). So all the board specific pwm drivers will > >be exposing the same set of function name as in include/linux/pwm.h. > >As a result build fails in case of multi soc environments where each soc > >has a pwm device in it. > > This seems very specific to ST environment, No it's not. It's an issue Arun has hit while enabling one of the ST MFD chip, but he's tackling a generic issue. > looking at the driver list from > ( [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core ) it seems > most multi SOC environments might support PWM in either one of the SOC. > > arch/arm/plat-mxc/pwm.c > arch/arm/plat-pxa/pwm.c > arch/arm/plat-samsung/pwm.c > arch/mips/jz4740/pwm.c > drivers/mfd/twl6030-pwm.c > > Unless people have examples of other SOCs which might use this, > the better approach might be to go for a custom driver rather than changing > the framework. I wouldn't call the current pwm code a framework. It's a bunch of header definitions that happens to work in the specific case of 1 pwm per sub architecture. What Arun is proposing is an actual framework. And it seems to be clean and simple enough. Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ From balbi@ti.com Tue Sep 28 15:35:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 15:35:51 +0200 (CEST) Received: from devils.ext.ti.com ([198.47.26.153]:33522 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491895Ab0I1Nfs (ORCPT ); Tue, 28 Sep 2010 15:35:48 +0200 Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o8SDZ6DT008861 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 28 Sep 2010 08:35:06 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o8SDZ5tv017859; Tue, 28 Sep 2010 08:35:05 -0500 (CDT) Received: from localhost (h0-167.vpn.ti.com [172.24.0.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o8SDZ1f27901; Tue, 28 Sep 2010 08:35:02 -0500 (CDT) Date: Tue, 28 Sep 2010 16:35:01 +0300 From: Felipe Balbi To: Samuel Ortiz Cc: "V, Hemanth" , Arun Murthy , "lars@metafoo.de" , Andrew Morton , "kernel@pengutronix.de" , "philipp.zabel@gmail.com" , "robert.jarzmik@free.fr" , "marek.vasut@gmail.com" , "eric.y.miao@gmail.com" , "rpurdie@rpsys.net" , "kgene.kim@samsung.com" , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , "STEricsson_nomadik_linux@list.st.com" Subject: Re: [PATCH 1/7] pwm: Add pwm core driver Message-ID: <20100928133501.GB8575@legolas.emea.dhcp.ti.com> Reply-To: balbi@ti.com References: <1285670134-18063-1-git-send-email-arun.murthy@stericsson.com> <1285670134-18063-2-git-send-email-arun.murthy@stericsson.com> <040c01cb5f0c$29bcb3b0$LocalHost@wipblrx0099946> <20100928130610.GB20749@sortiz-mobl> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20100928130610.GB20749@sortiz-mobl> User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 27874 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: balbi@ti.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22377 Content-Length: 1531 Lines: 39 On Tue, Sep 28, 2010 at 08:06:11AM -0500, Samuel Ortiz wrote: >On Tue, Sep 28, 2010 at 06:23:24PM +0530, Hemanth V wrote: >> ----- Original Message ----- From: "Arun Murthy" >> >> >> >> >The existing pwm based led and backlight driver makes use of the >> >pwm(include/linux/pwm.h). So all the board specific pwm drivers will >> >be exposing the same set of function name as in include/linux/pwm.h. >> >As a result build fails in case of multi soc environments where each soc >> >has a pwm device in it. >> >> This seems very specific to ST environment, >No it's not. It's an issue Arun has hit while enabling one of the ST MFD chip, >but he's tackling a generic issue. > >> looking at the driver list from >> ( [PATCH 4/7] pwm: Align existing pwm drivers with pwm-core ) it seems >> most multi SOC environments might support PWM in either one of the SOC. >> >> arch/arm/plat-mxc/pwm.c >> arch/arm/plat-pxa/pwm.c >> arch/arm/plat-samsung/pwm.c >> arch/mips/jz4740/pwm.c >> drivers/mfd/twl6030-pwm.c >> >> Unless people have examples of other SOCs which might use this, >> the better approach might be to go for a custom driver rather than changing >> the framework. >I wouldn't call the current pwm code a framework. It's a bunch of header >definitions that happens to work in the specific case of 1 pwm per >sub architecture. >What Arun is proposing is an actual framework. And it seems to be clean and >simple enough. FWIW, I agree with you Sam. Sooner or later, this will hit other SoCs. -- balbi From Andrei.Ardelean@idt.com Tue Sep 28 16:40:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 16:40:40 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:43822 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491958Ab0I1Okh convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2010 16:40:37 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o8SEeRql004180 for ; Tue, 28 Sep 2010 07:40:30 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o8SEePPa015521 for ; Tue, 28 Sep 2010 07:40:27 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o8SEePM17411 for ; Tue, 28 Sep 2010 07:40:25 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: License file header for a new file Date: Tue, 28 Sep 2010 07:40:23 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: License file header for a new file thread-index: ActfGxVMdmrazCfoRDOpQaqquZBnYA== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 X-archive-position: 27875 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22435 Content-Length: 1174 Lines: 39 Hi, I am porting MIPS Linux from Malta to a new platform. I created a new file gd-memory.c from the original malta-memory.c and I modified the code to match the new platform. The original malta-memory.c has the following header: /* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * * PROM library functions for acquiring/using memory descriptors given to * us from the YAMON. */ What should be the correct header for gd-memory.c? Thanks, Andrei From wilbur512@gmail.com Tue Sep 28 18:00:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 18:00:36 +0200 (CEST) Received: from mail-qy0-f177.google.com ([209.85.216.177]:46503 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491131Ab0I1QAd (ORCPT ); Tue, 28 Sep 2010 18:00:33 +0200 Received: by qyk34 with SMTP id 34so10482929qyk.15 for ; Tue, 28 Sep 2010 09:00:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:cc:content-type; bh=0LV5Mxf22Qt3mPpkzR8uOW3SfR5eVkuEw27qoViWNBo=; b=sN7YQCOWfdoYWYwHeKlTw6IibnZgv/i9AqJ6tP9mp9b7Vm1QMKXjuucx7mYX+AZUIb ESrgz/bZ91gEeayhPKUvEcn7cWsk0fDwcjlTUu1u1/JLz7ByMP9inHNv/JtSz/pQL1rE Z+YPYF+Jv1f6c0GmDVyuzJnu39hUFqxx61Zxg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; b=WMWo/vvIEluoLSAIGoUkc4ZIHU9MKdpkvbGNc5tvTSE3N0Py3bWNBTDtBFQGMK3HD3 A14QH+GOHXhgULY8Qs8FNrpzqVEJgP2wjaAGQ8voNxZzDqlMLQxeA2I/xbpcN5U7A/kN XJYHnSWmFxUApueINhO9HXXFi4gvmVrbOzgY0= MIME-Version: 1.0 Received: by 10.229.233.142 with SMTP id jy14mr118575qcb.77.1285689627424; Tue, 28 Sep 2010 09:00:27 -0700 (PDT) Received: by 10.229.221.146 with HTTP; Tue, 28 Sep 2010 09:00:26 -0700 (PDT) Date: Wed, 29 Sep 2010 00:00:26 +0800 Message-ID: Subject: Why mips eret failed? From: "wilbur.chan" To: Linux MIPS Mailing List Cc: chelly wilbur Content-Type: text/plain; charset=ISO-8859-1 X-archive-position: 27876 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22505 Content-Length: 1526 Lines: 79 HI all! I'm learning to write a timer interrupt handler by my own on mips32(xls416 with 32bits cross compiled) , but to find that, eret failed to quit. detail: I took the following steps: 1) copy exception vector to the physical address 0x180, then set ebase with it. that is , memcpy these three instructions to 0x80000180,with size 0x80 bytes: lui k1, HIGH(handle_int) addiu k1, k1, LOW(handle_int) jr k1 2) this is handle_int , which is the entry of interrupts LEAF(handle_int) nop la t9,do_IRQ nop jalr t9 nop eret nop END(handle_int) ps: 'nop' is used to avoid delay slot, and I did not add 'SAVE_ALL' or 'RESTORE_ALL' in handle_int, because it is just a demo, I want the interrupt return immediately. 3) this is do_IRQ void do_IRQ(void) { ack_irq(); /* ack with compare register ,which is used to generate timer interrupt*/ print("do_irq enter\n"); } 4) there is a main loop like this: void main_loop() { local_irq_enable(); /* enable timer interrupt*/ while(1) { print("loop...\n"); } } I found that , the message in do_IRQ prints every 4s (I' ve set timer of 4 seconds), however, the message in main_loop did not appear q1: does that mean, the timer interrupt has never quit to main_loop , but a nested interrupt? q2: that is to say, eret in handle_int failed to quit to main_loop? q3: why this happend? Thank you ! From ddaney@caviumnetworks.com Tue Sep 28 18:50:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 18:50:26 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16877 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491961Ab0I1QuX (ORCPT ); Tue, 28 Sep 2010 18:50:23 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 28 Sep 2010 09:50:53 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 28 Sep 2010 09:50:19 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 28 Sep 2010 09:50:19 -0700 Message-ID: <4CA21CC6.9050101@caviumnetworks.com> Date: Tue, 28 Sep 2010 09:50:14 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: "Ardelean, Andrei" CC: linux-mips@linux-mips.org Subject: Re: License file header for a new file References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 28 Sep 2010 16:50:19.0448 (UTC) FILETIME=[3BF83380:01CB5F2D] X-archive-position: 27877 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22544 Content-Length: 1485 Lines: 44 On 09/28/2010 07:40 AM, Ardelean, Andrei wrote: > Hi, > > I am porting MIPS Linux from Malta to a new platform. I created a new > file gd-memory.c from the original malta-memory.c and I modified the > code to match the new platform. The original malta-memory.c has the > following header: > /* > * Carsten Langgaard, carstenl@mips.com > * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. > * > * This program is free software; you can distribute it and/or modify > it > * under the terms of the GNU General Public License (Version 2) as > * published by the Free Software Foundation. > * > * This program is distributed in the hope it will be useful, but > WITHOUT > * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY > or > * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > License > * for more details. > * > * You should have received a copy of the GNU General Public License > along > * with this program; if not, write to the Free Software Foundation, > Inc., > * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > * > * PROM library functions for acquiring/using memory descriptors given > to > * us from the YAMON. > */ > > What should be the correct header for gd-memory.c? > If there is code from the original file remaining, you should keep the original copyright message If you made material changes to it, you could *add* your own copyright line. David Daney From ddaney@caviumnetworks.com Tue Sep 28 18:57:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 18:57:06 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17046 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491961Ab0I1Q5D (ORCPT ); Tue, 28 Sep 2010 18:57:03 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 28 Sep 2010 09:57:35 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 28 Sep 2010 09:57:01 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 28 Sep 2010 09:57:01 -0700 Message-ID: <4CA21E5D.7080905@caviumnetworks.com> Date: Tue, 28 Sep 2010 09:57:01 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: "wilbur.chan" CC: Linux MIPS Mailing List Subject: Re: Why mips eret failed? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 28 Sep 2010 16:57:01.0059 (UTC) FILETIME=[2B592D30:01CB5F2E] X-archive-position: 27878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22559 Content-Length: 2067 Lines: 98 On 09/28/2010 09:00 AM, wilbur.chan wrote: > HI all! > > I'm learning to write a timer interrupt handler by my own on > mips32(xls416 with 32bits cross compiled) , but to find that, eret > failed to quit. > > detail: > > I took the following steps: > > 1) copy exception vector to the physical address 0x180, then set ebase with it. > > that is , memcpy these three instructions to 0x80000180,with > size 0x80 bytes: > > lui k1, HIGH(handle_int) > addiu k1, k1, LOW(handle_int) > jr k1 > > > 2) this is handle_int , which is the entry of interrupts > > LEAF(handle_int) > nop > la t9,do_IRQ > nop > jalr t9 > nop > eret > nop > END(handle_int) > > ps: > > 'nop' is used to avoid delay slot, and I did not add 'SAVE_ALL' or > 'RESTORE_ALL' in handle_int, Probably not a good choice. > because it is just a demo, If you want your demo to work, you cannot clobber all the registers in an exception handler. Most ABIs allow you to clobber only k0 and k1. In general any exception handler must save and restore all registers it modifies except for k0 and k1. That is the function of SAVE_ALL and RESTORE_ALL. > I want the > interrupt return > > immediately. > > 3) this is do_IRQ > > void do_IRQ(void) > { > ack_irq(); /* ack with compare register ,which is used to > generate timer interrupt*/ > print("do_irq enter\n"); > } > > > > 4) there is a main loop like this: > > > void main_loop() > { > local_irq_enable(); /* enable timer interrupt*/ > while(1) > { > print("loop...\n"); > > } > } > > I found that , the message in do_IRQ prints every 4s (I' ve set > timer of 4 seconds), however, the message in main_loop did not appear > > > q1: does that mean, the timer interrupt has never quit to main_loop , > but a nested interrupt? > > > > q2: that is to say, eret in handle_int failed to quit to main_loop? > > q3: why this happend? > > > Thank you ! > > From broonie@opensource.wolfsonmicro.com Tue Sep 28 19:46:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 19:46:12 +0200 (CEST) Received: from opensource.wolfsonmicro.com ([80.75.67.52]:55057 "EHLO opensource2.wolfsonmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491139Ab0I1RqJ (ORCPT ); Tue, 28 Sep 2010 19:46:09 +0200 Received: from finisterre.wolfsonmicro.main (216-75-233-70.static.wiline.com [216.75.233.70]) by opensource2.wolfsonmicro.com (Postfix) with ESMTPSA id 9B79F114727; Tue, 28 Sep 2010 18:45:59 +0100 (BST) Received: from broonie by finisterre.wolfsonmicro.main with local (Exim 4.72) (envelope-from ) id 1P0eFu-00030H-90; Tue, 28 Sep 2010 10:46:18 -0700 Date: Tue, 28 Sep 2010 10:46:18 -0700 From: Mark Brown To: Arun Murthy Cc: eric.y.miao@gmail.com, linux@arm.linux.org.uk, grinberg@compulab.co.il, mike@compulab.co.il, robert.jarzmik@free.fr, marek.vasut@gmail.com, drwyrm@gmail.com, stefan@openezx.org, laforge@openezx.org, ospite@studenti.unina.it, philipp.zabel@gmail.com, mad_soft@inbox.ru, maz@misterjones.org, daniel@caiaq.de, haojian.zhuang@marvell.com, timur@freescale.com, ben-linux@fluff.org, support@simtec.co.uk, arnaud.patard@rtp-net.org, dgreenday@gmail.com, anarsoul@gmail.com, akpm@linux-foundation.org, mcuelenaere@gmail.com, kernel@pengutronix.de, andre.goddard@gmail.com, jkosina@suse.cz, tj@kernel.org, hsweeten@visionengravers.com, u.kleine-koenig@pengutronix.de, kgene.kim@samsung.com, ralf@linux-mips.org, lars@metafoo.de, dilinger@collabora.co.uk, mroth@nessie.de, randy.dunlap@oracle.com, lethal@linux-sh.org, rusty@rustcorp.com.au, damm@opensource.se, mst@redhat.com, rpurdie@rpsys.net, sguinot@lacie.co, sameo@linux.intel.com, balajitk@ti.com, rnayak@ti.com, santosh.shilimkar@ti.com, hemanthv@ti.com, michael.hennerich@analog.com, vapier@gentoo.org, khali@linux-fr.org, jic23@cam.ac.uk, re.emese@gmail.com, linux@simtec.co.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linus.walleij@stericsson.com, mattias.wallin@stericsson.com, Bill Gatliff Subject: Re: [PATCH 1/7] pwm: Add pwm core driver Message-ID: <20100928174617.GE10739@opensource.wolfsonmicro.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> X-Cookie: Excellent day to have a rotten day. User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 27879 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: broonie@opensource.wolfsonmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22616 Content-Length: 1611 Lines: 57 On Tue, Sep 28, 2010 at 01:10:42PM +0530, Arun Murthy wrote: > The existing pwm based led and backlight driver makes use of the > pwm(include/linux/pwm.h). So all the board specific pwm drivers will > be exposing the same set of function name as in include/linux/pwm.h. > As a result build fails. As others have said it's *really* not clear what the problem is here... Please also take a look at the work which Bill Gatliff was doing on a similar PWM core API and the resulting discussion - how does your code differ from his, and is any of the feedback on his proposal relevant to yours? > +void __deprecated pwm_free(struct pwm_device *pwm) > +{ > +} > + Shouldn't this either be an inline function directly in the header or exported? > +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) > +{ > + return pwm->pops->pwm_config(pwm, duty_ns, period_ns); > +} > +EXPORT_SYMBOL(pwm_config); I'd expect some handling of fixed function PWMs (though I'd expect those to be rare). > + down_write(&pwm_list_lock); > + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); > + if (!pwm) { > + up_write(&pwm_list_lock); > + return -ENOMEM; > + } No need to take the lock until the allocation succeeded. > +static int __init pwm_init(void) > +{ > + struct pwm_dev_info *pwm; > + > + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); > + if (!pwm) > + return -ENOMEM; > + INIT_LIST_HEAD(&pwm->list); > + di = pwm; > + return 0; Why not just use static data for the list head? > +subsys_initcall(pwm_init); > +module_exit(pwm_exit); Usually these are located next to the functions. From broonie@opensource.wolfsonmicro.com Tue Sep 28 19:47:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 19:47:37 +0200 (CEST) Received: from opensource.wolfsonmicro.com ([80.75.67.52]:55085 "EHLO opensource2.wolfsonmicro.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491139Ab0I1Rre (ORCPT ); Tue, 28 Sep 2010 19:47:34 +0200 Received: from finisterre.wolfsonmicro.main (216-75-233-70.static.wiline.com [216.75.233.70]) by opensource2.wolfsonmicro.com (Postfix) with ESMTPSA id 9A6D111472C; Tue, 28 Sep 2010 18:47:26 +0100 (BST) Received: from broonie by finisterre.wolfsonmicro.main with local (Exim 4.72) (envelope-from ) id 1P0eHJ-00030N-9H; Tue, 28 Sep 2010 10:47:45 -0700 Date: Tue, 28 Sep 2010 10:47:45 -0700 From: Mark Brown To: Arun Murthy Cc: eric.y.miao@gmail.com, linux@arm.linux.org.uk, grinberg@compulab.co.il, mike@compulab.co.il, robert.jarzmik@free.fr, marek.vasut@gmail.com, drwyrm@gmail.com, stefan@openezx.org, laforge@openezx.org, ospite@studenti.unina.it, philipp.zabel@gmail.com, mad_soft@inbox.ru, maz@misterjones.org, daniel@caiaq.de, haojian.zhuang@marvell.com, timur@freescale.com, ben-linux@fluff.org, support@simtec.co.uk, arnaud.patard@rtp-net.org, dgreenday@gmail.com, anarsoul@gmail.com, akpm@linux-foundation.org, mcuelenaere@gmail.com, kernel@pengutronix.de, andre.goddard@gmail.com, jkosina@suse.cz, tj@kernel.org, hsweeten@visionengravers.com, u.kleine-koenig@pengutronix.de, kgene.kim@samsung.com, ralf@linux-mips.org, lars@metafoo.de, dilinger@collabora.co.uk, mroth@nessie.de, randy.dunlap@oracle.com, lethal@linux-sh.org, rusty@rustcorp.com.au, damm@opensource.se, mst@redhat.com, rpurdie@rpsys.net, sguinot@lacie.co, sameo@linux.intel.com, balajitk@ti.com, rnayak@ti.com, santosh.shilimkar@ti.com, hemanthv@ti.com, michael.hennerich@analog.com, vapier@gentoo.org, khali@linux-fr.org, jic23@cam.ac.uk, re.emese@gmail.com, linux@simtec.co.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linus.walleij@stericsson.com, mattias.wallin@stericsson.com Subject: Re: [PATCH 2/7] backlight:pwm: add an element 'name' to platform data Message-ID: <20100928174744.GF10739@opensource.wolfsonmicro.com> References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-3-git-send-email-arun.murthy@stericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1285659648-21409-3-git-send-email-arun.murthy@stericsson.com> X-Cookie: Excellent day to have a rotten day. User-Agent: Mutt/1.5.20 (2009-06-14) X-archive-position: 27880 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: broonie@opensource.wolfsonmicro.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22617 Content-Length: 543 Lines: 12 On Tue, Sep 28, 2010 at 01:10:43PM +0530, Arun Murthy wrote: > A new element 'name' is added to pwm backlight platform data structure. > This is required to identify the pwm device. > - pb->pwm = pwm_request(data->pwm_id, "backlight"); > + if (!data->name) > + data->name = "backlight"; > + pb->pwm = pwm_request(data->pwm_id, data->name); If we're going to go through and require that all PWM API users be updated to take platform data for the name might it not be better to switch over to the clock API style request by device interface? From ddaney@caviumnetworks.com Tue Sep 28 20:10:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 20:10:45 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19705 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491139Ab0I1SKl (ORCPT ); Tue, 28 Sep 2010 20:10:41 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 28 Sep 2010 11:11:12 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 28 Sep 2010 11:10:39 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 28 Sep 2010 11:10:38 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o8SIAaWq029277; Tue, 28 Sep 2010 11:10:36 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o8SIAYuI029276; Tue, 28 Sep 2010 11:10:34 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, rostedt@goodmis.org, jbaron@redhat.com Cc: David Daney Subject: [PATCH] jump label: Add MIPS support. Date: Tue, 28 Sep 2010 11:10:32 -0700 Message-Id: <1285697432-29244-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.2 X-OriginalArrivalTime: 28 Sep 2010 18:10:38.0935 (UTC) FILETIME=[749B8E70:01CB5F38] X-archive-position: 27881 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22649 Content-Length: 5357 Lines: 193 When in Rome... In order not to be left behind, we add jump label support for MIPS. Tested on 64-bit big endian (Octeon), and 32-bit little endian (malta/qemu). Signed-off-by: David Daney Cc: Steven Rostedt Cc: Jason Baron Cc: Ralf Baechle --- arch/mips/Kconfig | 1 + arch/mips/include/asm/jump_label.h | 48 ++++++++++++++++++++++++++++ arch/mips/kernel/Makefile | 3 +- arch/mips/kernel/jump_label.c | 60 ++++++++++++++++++++++++++++++++++++ arch/mips/kernel/module.c | 5 +++ 5 files changed, 116 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/jump_label.h create mode 100644 arch/mips/kernel/jump_label.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ad59dd..6b3bdb5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -13,6 +13,7 @@ config MIPS select HAVE_KPROBES select HAVE_KRETPROBES select RTC_LIB if !MACH_LOONGSON + select HAVE_ARCH_JUMP_LABEL mainmenu "Linux/MIPS Kernel Configuration" diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h new file mode 100644 index 0000000..7622ccf --- /dev/null +++ b/arch/mips/include/asm/jump_label.h @@ -0,0 +1,48 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2010 Cavium Networks, Inc. + */ +#ifndef _ASM_MIPS_JUMP_LABEL_H +#define _ASM_MIPS_JUMP_LABEL_H + +#include + +#ifdef __KERNEL__ + +#define JUMP_LABEL_NOP_SIZE 4 + +#ifdef CONFIG_64BIT +#define WORD_INSN ".dword" +#else +#define WORD_INSN ".word" +#endif + +#define JUMP_LABEL(key, label) \ + do { \ + asm goto("1:\tnop\n\t" \ + "nop\n\t" \ + ".pushsection __jump_table, \"a\"\n\t" \ + WORD_INSN " 1b, %l[" #label "], %0\n\t" \ + ".popsection\n\t" \ + : : "i" (key) : : label); \ + } while (0) + + +#endif /* __KERNEL__ */ + +#ifdef CONFIG_64BIT +typedef u64 jump_label_t; +#else +typedef u32 jump_label_t; +#endif + +struct jump_entry { + jump_label_t code; + jump_label_t target; + jump_label_t key; +}; + +#endif /* _ASM_MIPS_JUMP_LABEL_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 06f8482..db4feb9 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -6,7 +6,8 @@ extra-y := head.o init_task.o vmlinux.lds obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ ptrace.o reset.o setup.o signal.o syscall.o \ - time.o topology.o traps.o unaligned.o watch.o vdso.o + time.o topology.o traps.o unaligned.o watch.o vdso.o \ + jump_label.o ifdef CONFIG_FUNCTION_TRACER CFLAGS_REMOVE_ftrace.o = -pg diff --git a/arch/mips/kernel/jump_label.c b/arch/mips/kernel/jump_label.c new file mode 100644 index 0000000..3c145a8 --- /dev/null +++ b/arch/mips/kernel/jump_label.c @@ -0,0 +1,60 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2010 Cavium Networks, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define J_RANGE_MASK ((1ul << 28) - 1) + +void arch_jump_label_transform(struct jump_entry *e, + enum jump_label_type type) +{ + union mips_instruction insn; + union mips_instruction *insn_p = + (union mips_instruction *)(unsigned long)e->code; + + /* Jump only works within a 256MB aligned region. */ + BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK)); + + /* Target must have 4 byte alignment. */ + BUG_ON((e->target & 3) != 0); + + if (type == JUMP_LABEL_ENABLE) { + insn.j_format.opcode = j_op; + insn.j_format.target = (e->target & J_RANGE_MASK) >> 2; + } else { + insn.word = 0; /* nop */ + } + + get_online_cpus(); + mutex_lock(&text_mutex); + *insn_p = insn; + + flush_icache_range((unsigned long)insn_p, + (unsigned long)insn_p + sizeof(*insn_p)); + + mutex_unlock(&text_mutex); + put_online_cpus(); +} + +void arch_jump_label_text_poke_early(jump_label_t addr) +{ + union mips_instruction *insn_p = + (union mips_instruction *)(unsigned long)addr; + + insn_p->word = 0; /* nop */ + flush_icache_range((unsigned long)insn_p, + (unsigned long)insn_p + sizeof(*insn_p)); +} diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index 6f51dda..bb9cde4 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -30,6 +30,8 @@ #include #include #include +#include + #include /* MODULE_START */ struct mips_hi16 { @@ -390,6 +392,9 @@ int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *s; char *secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; + /* Make jump label nops. */ + jump_label_apply_nops(me); + INIT_LIST_HEAD(&me->arch.dbe_list); for (s = sechdrs; s < sechdrs + hdr->e_shnum; s++) { if (strcmp("__dbe_table", secstrings + s->sh_name) != 0) -- 1.7.2.2 From ryan@bluewatersys.com Tue Sep 28 21:42:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 21:42:10 +0200 (CEST) Received: from mail.bluewatersys.com ([202.124.120.130]:63315 "EHLO hayes.bluewaternz.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491165Ab0I1TmG (ORCPT ); Tue, 28 Sep 2010 21:42:06 +0200 Received: (qmail 22761 invoked by uid 89); 28 Sep 2010 19:40:22 -0000 Received: from unknown (HELO ?192.168.2.96?) (ryan@192.168.2.96) by 0 with ESMTPA; 28 Sep 2010 19:40:22 -0000 Message-ID: <4CA2450D.8090104@bluewatersys.com> Date: Wed, 29 Sep 2010 08:42:05 +1300 From: Ryan Mallon User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.12) Gecko/20100915 Thunderbird/3.0.8 MIME-Version: 1.0 To: Arun Murthy CC: eric.y.miao@gmail.com, linux@arm.linux.org.uk, grinberg@compulab.co.il, mike@compulab.co.il, robert.jarzmik@free.fr, marek.vasut@gmail.com, drwyrm@gmail.com, stefan@openezx.org, laforge@openezx.org, ospite@studenti.unina.it, philipp.zabel@gmail.com, mad_soft@inbox.ru, maz@misterjones.org, daniel@caiaq.de, haojian.zhuang@marvell.com, timur@freescale.com, ben-linux@fluff.org, support@simtec.co.uk, arnaud.patard@rtp-net.org, dgreenday@gmail.com, anarsoul@gmail.com, akpm@linux-foundation.org, mcuelenaere@gmail.com, kernel@pengutronix.de, andre.goddard@gmail.com, jkosina@suse.cz, tj@kernel.org, hsweeten@visionengravers.com, u.kleine-koenig@pengutronix.de, kgene.kim@samsung.com, ralf@linux-mips.org, lars@metafoo.de, dilinger@collabora.co.uk, mroth@nessie.de, randy.dunlap@oracle.com, lethal@linux-sh.org, rusty@rustcorp.com.au, damm@opensource.se, mst@redhat.com, rpurdie@rpsys.net, sguinot@lacie.co, sameo@linux.intel.com, broonie@opensource.wolfsonmicro.com, balajitk@ti.com, rnayak@ti.com, santosh.shilimkar@ti.com, hemanthv@ti.com, michael.hennerich@analog.com, vapier@gentoo.org, khali@linux-fr.org, jic23@cam.ac.uk, re.emese@gmail.com, linux@simtec.co.uk, linux-mips@linux-mips.org, linus.walleij@stericsson.com, linux-kernel@vger.kernel.org, mattias.wallin@stericsson.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/7] pwm: Add pwm core driver References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> In-Reply-To: <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 27882 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ryan@bluewatersys.com Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22732 Content-Length: 3010 Lines: 101 On 09/28/2010 08:40 PM, Arun Murthy wrote: > The existing pwm based led and backlight driver makes use of the > pwm(include/linux/pwm.h). So all the board specific pwm drivers will > be exposing the same set of function name as in include/linux/pwm.h. > As a result build fails. > > In order to overcome this issue all the pwm drivers must register to > some core pwm driver with function pointers for pwm operations (i.e > pwm_config, pwm_enable, pwm_disable). The other major benefit of this patch set is that it allows non-soc pwms, such as those provided on an i2c or spi device, to be added easily. > The clients of pwm device will have to call pwm_request, wherein > they will get the pointer to struct pwm_ops. This structure include > function pointers for pwm_config, pwm_enable and pwm_disable. > > Signed-off-by: Arun Murthy > Acked-by: Linus Walleij > --- > +menuconfig PWM_DEVICES > + bool "PWM devices" > + default y > + ---help--- > + Say Y here to get to see options for device drivers from various > + different categories. This option alone does not add any kernel code. This help text doesn't really explain what the option does. > +struct pwm_device { > + struct pwm_ops *pops; > + int pwm_id; > +}; > + > +struct pwm_dev_info { > + struct pwm_device *pwm_dev; > + struct list_head list; > +}; These two structures can be merged into one which will make the code much simpler. > +static struct pwm_dev_info *di; This appears to be used as just a list, and could be replaced by: static LIST_HEAD(pwm_list); > +struct pwm_device *pwm_request(int pwm_id, const char *name) > +{ > + struct pwm_dev_info *pwm; > + struct list_head *pos; > + > + down_read(&pwm_list_lock); > + list_for_each(pos, &di->list) { > + pwm = list_entry(pos, struct pwm_dev_info, list); > + if ((!strcmp(pwm->pwm_dev->pops->name, name)) && > + (pwm->pwm_dev->pwm_id == pwm_id)) { > + up_read(&pwm_list_lock); > + return pwm->pwm_dev; > + } > + } > + up_read(&pwm_list_lock); > + return ERR_PTR(-ENOENT); > +} Is it by design that multiple users can request and use the same pwm or should pwms have a use count and return -EBUSY if already requested? > +static int __init pwm_init(void) > +{ > + struct pwm_dev_info *pwm; > + > + pwm = kzalloc(sizeof(struct pwm_dev_info), GFP_KERNEL); > + if (!pwm) > + return -ENOMEM; > + INIT_LIST_HEAD(&pwm->list); > + di = pwm; > + return 0; If di is changed to a list as suggested above this function does not need to exist. > +static void __exit pwm_exit(void) > +{ > + kfree(di); Do you need to ensure the list is empty first or do module dependencies ensure that? ~Ryan -- Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan@bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934 From lars@metafoo.de Tue Sep 28 23:04:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 28 Sep 2010 23:04:42 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:36765 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491165Ab0I1VEi (ORCPT ); Tue, 28 Sep 2010 23:04:38 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id E7226E3D; Tue, 28 Sep 2010 23:04:30 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 0PTfF5P7tnuq; Tue, 28 Sep 2010 23:04:30 +0200 (CEST) Received: from [172.31.16.254] (d125181.adsl.hansenet.de [80.171.125.181]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 07059E3C; Tue, 28 Sep 2010 23:04:18 +0200 (CEST) Message-ID: <4CA25841.4090702@metafoo.de> Date: Tue, 28 Sep 2010 23:04:01 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Arun MURTHY CC: "eric.y.miao@gmail.com" , "linux@arm.linux.org.uk" , Andrew Morton , "kernel@pengutronix.de" , "philipp.zabel@gmail.com" , "robert.jarzmik@free.fr" , Marek Vasut , "rpurdie@rpsys.net" , Samuel Ortiz , "kgene.kim@samsung.com" , linux-omap@vger.kernel.org, "broonie@opensource.wolfsonmicro.com" , "linux-kernel@vger.kernel.org" , Linus WALLEIJ , Mattias WALLIN , linux-arm-kernel , "linux-mips@linux-mips.org" , Arun Murthy , STEricsson_nomadik_linux@list.st.com Subject: Re: [PATCH 1/7] pwm: Add pwm core driver References: <1285659648-21409-1-git-send-email-arun.murthy@stericsson.com> <1285659648-21409-2-git-send-email-arun.murthy@stericsson.com> <4CA1AD2B.8000905@metafoo.de> <4CA1BC16.3020702@metafoo.de> In-Reply-To: X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-archive-position: 27883 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Return-Path: X-Keywords: X-UID: 22789 Content-Length: 6278 Lines: 129 Arun MURTHY wrote: >>>> Shouldn't PWM_DEVICES select HAVE_PWM? >>> >>> No not required, the entire concept is to remove HAVE_PWM and use >> PWM_CORE. >> >> Well in patch 4 you say that PWM_CORE is currently limited to ARM. >> Furthermore you >> change the pwm-backlight and pwm-led Kconfig entries to depend on >> HAVE_PWM || >> PWM_CORE. Adding a select HAVE_PWM here would make those changes >> unnecessary. > HAVE_PWM is retained just because the mips pwm driver is not aligned with the pwm core driver. > On mips pwm driver aligning to the pwm core driver HAVE_PWM will be replaced by PWM_CORE. > >> HAVE_PWM should be set, when pwm_* functions are available. When your >> pwm-core driver >> is selected they are available. > On applying this patch set pwm_* function will be exported in pwm_core driver and in mips pwm driver. > Since mips pwm driver is not aligned with the pwm core, HAVE_PWM is retained and removed in places where pwm drivers register to pwm core driver. pwm_{enable,disable,request,free} are the interface of the pwm api. Your pwm-core is one implementation of that interface. A somewhat special though, because it tries to be a generic implementation. There are still other implementations though. For example right now the mips jz4740 one. In my opinion HAVE_PWM should be defined if there is a implementation for the pwm interface is available. I know that your plan is that in the end pwm-core is the only implementation of the pwm interface. But right now it is not and on the other hand some SoC implementors might choose that they want to provide their own minimal pwm interface implementation. Furthermore this would allow you to start with pwm-core for one SoC which you have on your desk and where