From wim@iguana.be Mon Aug 2 14:38:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 14:38:07 +0200 (CEST) Received: from mailrelay003.isp.belgacom.be ([195.238.6.53]:18702 "EHLO mailrelay003.isp.belgacom.be" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492496Ab0HBMiB (ORCPT ); Mon, 2 Aug 2010 14:38:01 +0200 X-Belgacom-Dynamic: yes X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEABNZVkxQycSE/2dsb2JhbACgDXLBAg2FLAQ Received: from 132.196-201-80.adsl-dyn.isp.belgacom.be (HELO infomag) ([80.201.196.132]) by relay.skynet.be with ESMTP; 02 Aug 2010 14:37:55 +0200 Received: from wim by infomag with local (Exim 4.69) (envelope-from ) id 1OfuHD-0001yH-6i; Mon, 02 Aug 2010 14:37:55 +0200 Date: Mon, 2 Aug 2010 14:37:55 +0200 From: Wim Van Sebroeck To: David Daney , ralf@linux-mips.org Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Morton , Russell King , Tony Lindgren , Marc Zyngier , Thierry Reding , Sam Ravnborg Subject: Re: [PATCH] watchdog: Add watchdog driver for OCTEON SOCs (v2). Message-ID: <20100802123755.GV30740@infomag.iguana.be> References: <20100724035826.GA27516@merkur.ravnborg.org> <1279991765-23962-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1279991765-23962-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27526 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk X-list: linux-mips Hi David, Ralf, > The OCTEON is a MIPS64 based SOC family with an on chip watchdog unit. > > The driver is split into two source files one for the C code and one > for assembly. Assembly is needed to handle the NMI and then print the > machine state before the reboot is triggered. > > v2: Stylistic changes suggested by Sam Ravnborg. This v2 looks good. only small remark is: > +static struct notifier_block octeon_wdt_cpu_notifier = { > + .notifier_call = octeon_wdt_cpu_callback > +}; Add a comma after octeon_wdt_cpu_callback. > Signed-off-by: David Daney > Cc: Wim Van Sebroeck Signed-off-by: Wim Van Sebroeck > Cc: Andrew Morton > Cc: Russell King > Cc: Tony Lindgren > Cc: Marc Zyngier > Cc: Thierry Reding > Cc: Sam Ravnborg Kind regards, Wim. From ralf@linux-mips.org Mon Aug 2 14:57:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 14:57:42 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57254 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492719Ab0HBM5h (ORCPT ); Mon, 2 Aug 2010 14:57:37 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72CvFx3011353; Mon, 2 Aug 2010 13:57:15 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72Cv9DQ011351; Mon, 2 Aug 2010 13:57:09 +0100 Date: Mon, 2 Aug 2010 13:57:08 +0100 From: Ralf Baechle To: Wim Van Sebroeck Cc: David Daney , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Morton , Russell King , Tony Lindgren , Marc Zyngier , Thierry Reding , Sam Ravnborg Subject: Re: [PATCH] watchdog: Add watchdog driver for OCTEON SOCs (v2). Message-ID: <20100802125708.GA5209@linux-mips.org> References: <20100724035826.GA27516@merkur.ravnborg.org> <1279991765-23962-1-git-send-email-ddaney@caviumnetworks.com> <20100802123755.GV30740@infomag.iguana.be> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100802123755.GV30740@infomag.iguana.be> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27527 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Aug 02, 2010 at 02:37:55PM +0200, Wim Van Sebroeck wrote: > > Signed-off-by: David Daney > > Cc: Wim Van Sebroeck > > Signed-off-by: Wim Van Sebroeck Patch updated. Thanks Wim! Ralf From Anoop_P.A@pmc-sierra.com Mon Aug 2 15:30:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 15:30:14 +0200 (CEST) Received: from bby1mta02.pmc-sierra.com ([216.241.235.117]:48745 "EHLO bby1mta02.pmc-sierra.bc.ca" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492258Ab0HBNaK convert rfc822-to-8bit (ORCPT ); Mon, 2 Aug 2010 15:30:10 +0200 Received: from bby1mta02.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id CC6058E00AE; Mon, 2 Aug 2010 06:29:58 -0700 (PDT) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (BBY1EXG02.pmc-sierra.bc.ca [216.241.231.167]) by bby1mta02.pmc-sierra.bc.ca (Postfix) with SMTP id B8F848E00AD; Mon, 2 Aug 2010 06:29:58 -0700 (PDT) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.157]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.4675); Mon, 2 Aug 2010 06:29:58 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 8BIT Subject: file corruption with highmem kernel Date: Mon, 2 Aug 2010 06:29:56 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: file corruption with highmem kernel Thread-Index: AcsyRsvJtdIm2QULSF2xEZbUAQ5rPA== From: "Anoop P.A." To: "linux-mips" , "Ralf Baechle" X-OriginalArrivalTime: 02 Aug 2010 13:29:58.0732 (UTC) FILETIME=[CD84C0C0:01CB3246] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27528 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips List, I am running 2.6.18 (highmem) kernel in RM9000 based SOC with 2 Gig RAM. I have observed file corruption and system hangs (Easily reproducible on remounting file system) when doing file copy to SATA disk / USB disk ( SATA/ USB controller over PCI) . How ever when I limit memory with option mem=512M from command line everything seems to be working fine. Issue is reproducible with 2.6.18-stable lmo git sources . I have modified dma-noncoherent.c as follows and I am no more experiencing system hang. But file's are getting corrupted (observed bus error / segmentation fault / illegal instruction error few times) occasionally. One more observation I have made is file corruption is more if I use root file system from onboard USB flash, than running a NFS root mount. --- arch/mips/mm/dma-noncoherent.c.orig 2010-08-02 23:53:17.000000000 +0530 +++ arch/mips/mm/dma-noncoherent.c 2010-08-02 23:56:19.000000000 +0530 @@ -132,12 +132,13 @@ for (i = 0; i < nents; i++, sg++) { unsigned long addr; - addr = (unsigned long) page_address(sg->page); - if (addr) { - __dma_sync(addr + sg->offset, sg->length, direction); - sg->dma_address = (dma_addr_t)page_to_phys(sg->page) - + sg->offset; - } + addr = (unsigned long) page_address(sg->page) + sg->offset; + if (addr) + __dma_sync(addr, sg->length, direction); + + sg->dma_address = (dma_addr_t)page_to_phys(sg->page) + + sg->offset; + } return nents; @@ -187,9 +188,9 @@ return; for (i = 0; i < nhwentries; i++, sg++) { - addr = (unsigned long) page_address(sg->page); + addr = (unsigned long) page_address(sg->page) + sg->offset; if (addr) - __dma_sync(addr + sg->offset, sg->length, direction); + __dma_sync(addr , sg->length, direction); } } It will be great if any body can give me some pointers / help to fix the issue. Thanks Anoop From ralf@linux-mips.org Mon Aug 2 15:30:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 15:30:39 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60918 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492511Ab0HBNaU (ORCPT ); Mon, 2 Aug 2010 15:30:20 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72DUA4B016749; Mon, 2 Aug 2010 14:30:10 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72DU8l6016748; Mon, 2 Aug 2010 14:30:08 +0100 Date: Mon, 2 Aug 2010 14:30:08 +0100 From: Ralf Baechle To: Jason Wessel Cc: linux-kernel@vger.kernel.org, kgdb-bugreport@lists.sourceforge.net, mingo@elte.hu, linux-mips@linux-mips.org Subject: Re: [PATCH 05/15] mips,kgdb: Individual register get/set for mips Message-ID: <20100802133008.GB5209@linux-mips.org> References: <1280517456-1167-1-git-send-email-jason.wessel@windriver.com> <1280517456-1167-6-git-send-email-jason.wessel@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280517456-1167-6-git-send-email-jason.wessel@windriver.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27529 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jul 30, 2010 at 02:17:26PM -0500, Jason Wessel wrote: > Implement the ability to individually get and set registers for kdb > and kgdb for mips. > > Signed-off-by: Jason Wessel > CC: Ralf Baechle > CC: linux-mips@linux-mips.org Looks good; I think this should be be merged with the rest of your stuff. Acked-by: Ralf Baechle Ralf From ralf@linux-mips.org Mon Aug 2 16:37:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 16:37:55 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:37742 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492563Ab0HBOhv (ORCPT ); Mon, 2 Aug 2010 16:37:51 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72EblIL028601; Mon, 2 Aug 2010 15:37:48 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72EblKp028599; Mon, 2 Aug 2010 15:37:47 +0100 Date: Mon, 2 Aug 2010 15:37:46 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Fix n32 syscall number comments. Message-ID: <20100802143746.GA27360@linux-mips.org> References: <1280436184-24092-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280436184-24092-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27530 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jul 29, 2010 at 01:43:04PM -0700, David Daney wrote: Thanks, applied. Ralf From ralf@linux-mips.org Mon Aug 2 16:59:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 16:59:12 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44171 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492728Ab0HBO7I (ORCPT ); Mon, 2 Aug 2010 16:59:08 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72Ex5qt006567; Mon, 2 Aug 2010 15:59:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72Ex5hw006565; Mon, 2 Aug 2010 15:59:05 +0100 Date: Mon, 2 Aug 2010 15:59:04 +0100 From: Ralf Baechle To: David Daney Cc: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH] OCTEON: workaround linking failures with gcc-4.4.x 32-bits toolchains Message-ID: <20100802145904.GA6123@linux-mips.org> References: <201007290013.08797.florian@openwrt.org> <4C50AC0C.9010507@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C50AC0C.9010507@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27531 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jul 28, 2010 at 03:15:40PM -0700, David Daney wrote: > >executables by default, we will produce __lshrti3 in sched_clock() which is > >never resolved so the kernel fails to link. Unconditionally use the inline > >assembly version as suggested by David Daney, which works around the issue. > > > >CC: David Daney > >Signed-off-by: Florian Fainelli > > Acked-by: David Daney Applied - but maybe we should just add lshrti3 instead? We already have ashldi3, ashrdi3 and lshrdi3. Ralf From ralf@linux-mips.org Mon Aug 2 17:20:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 17:20:28 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:37639 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492510Ab0HBPUU (ORCPT ); Mon, 2 Aug 2010 17:20:20 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72FKGVX012140; Mon, 2 Aug 2010 16:20:16 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72FKFmI012139; Mon, 2 Aug 2010 16:20:15 +0100 Date: Mon, 2 Aug 2010 16:20:15 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/4] MIPS: BCM47xx: Really fix 128MB RAM problem Message-ID: <20100802152015.GA11598@linux-mips.org> References: <1280261566-8247-1-git-send-email-hauke@hauke-m.de> <1280261566-8247-2-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280261566-8247-2-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27532 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Mon Aug 2 17:31:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 17:31:15 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58627 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493061Ab0HBPbK (ORCPT ); Mon, 2 Aug 2010 17:31:10 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72FV4g2015235; Mon, 2 Aug 2010 16:31:04 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72FV3EI015201; Mon, 2 Aug 2010 16:31:03 +0100 Date: Mon, 2 Aug 2010 16:31:03 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/4] MIPS: BCM47xx: Fill values for b43 into ssb sprom Message-ID: <20100802153103.GB11598@linux-mips.org> References: <1280261566-8247-1-git-send-email-hauke@hauke-m.de> <1280261566-8247-3-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280261566-8247-3-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27533 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Mon Aug 2 17:35:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 17:35:49 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:37256 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491030Ab0HBPfp (ORCPT ); Mon, 2 Aug 2010 17:35:45 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72FZgHn021943; Mon, 2 Aug 2010 16:35:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72FZgYH021887; Mon, 2 Aug 2010 16:35:42 +0100 Date: Mon, 2 Aug 2010 16:35:41 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/4] MIPS: BCM47xx: Activate SSB_B43_PCI_BRIDGE by default Message-ID: <20100802153541.GC11598@linux-mips.org> References: <1280261566-8247-1-git-send-email-hauke@hauke-m.de> <1280261566-8247-4-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280261566-8247-4-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27534 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Mon Aug 2 17:37:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 17:37:55 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:37271 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492569Ab0HBPhv (ORCPT ); Mon, 2 Aug 2010 17:37:51 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72Fbn05022765; Mon, 2 Aug 2010 16:37:49 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72Fbn0b022763; Mon, 2 Aug 2010 16:37:49 +0100 Date: Mon, 2 Aug 2010 16:37:49 +0100 From: Ralf Baechle To: Sergei Shtylyov Cc: Hauke Mehrtens , linux-mips@linux-mips.org Subject: Re: [PATCH 4/4] MIPS: BCM47xx: Setup and register serial early Message-ID: <20100802153748.GD11598@linux-mips.org> References: <1280261566-8247-1-git-send-email-hauke@hauke-m.de> <1280261566-8247-5-git-send-email-hauke@hauke-m.de> <4C502F65.2020701@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C502F65.2020701@mvista.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27535 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Hauke, can you sort out the issues raised by Sergei and repost? I'll drop this patch for now. Thanks, Ralf From David.Daney@caviumnetworks.com Mon Aug 2 18:51:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 18:51:49 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12151 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493127Ab0HBQvp (ORCPT ); Mon, 2 Aug 2010 18:51:45 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 02 Aug 2010 09:52:10 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 2 Aug 2010 09:51:41 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 2 Aug 2010 09:51:41 -0700 Message-ID: <4C56F79D.3090709@caviumnetworks.com> Date: Mon, 02 Aug 2010 09:51:41 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Ralf Baechle CC: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH] OCTEON: workaround linking failures with gcc-4.4.x 32-bits toolchains References: <201007290013.08797.florian@openwrt.org> <4C50AC0C.9010507@caviumnetworks.com> <20100802145904.GA6123@linux-mips.org> In-Reply-To: <20100802145904.GA6123@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Aug 2010 16:51:41.0566 (UTC) FILETIME=[FB5EA9E0:01CB3262] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27536 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 08/02/2010 07:59 AM, Ralf Baechle wrote: > On Wed, Jul 28, 2010 at 03:15:40PM -0700, David Daney wrote: > >>> executables by default, we will produce __lshrti3 in sched_clock() which is >>> never resolved so the kernel fails to link. Unconditionally use the inline >>> assembly version as suggested by David Daney, which works around the issue. >>> >>> CC: David Daney >>> Signed-off-by: Florian Fainelli >> >> Acked-by: David Daney > > Applied - but maybe we should just add lshrti3 instead? We already have > ashldi3, ashrdi3 and lshrdi3. Too slow I think. If we are doing 128-bit arithmetic, it should only be for tricky things that we are optimizing to go real fast. In this case, we don't want to be making function calls. Well that is my $0.02 David Daney From dvomlehn@cisco.com Mon Aug 2 20:44:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 20:44:25 +0200 (CEST) Received: from sj-iport-5.cisco.com ([171.68.10.87]:31711 "EHLO sj-iport-5.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492744Ab0HBSoP (ORCPT ); Mon, 2 Aug 2010 20:44:15 +0200 Authentication-Results: sj-iport-5.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAAqvVkyrR7Hu/2dsb2JhbACgA3GpF5tGgmiCUQSEFg X-IronPort-AV: E=Sophos;i="4.55,304,1278288000"; d="scan'208";a="234311169" Received: from sj-core-5.cisco.com ([171.71.177.238]) by sj-iport-5.cisco.com with ESMTP; 02 Aug 2010 18:43:59 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-5.cisco.com (8.13.8/8.14.3) with ESMTP id o72IhxJM021638; Mon, 2 Aug 2010 18:43:59 GMT Date: Mon, 2 Aug 2010 11:44:00 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH][MIPS] PowerTV: add Gaia platform definitions Message-ID: <20100802184359.GA10915@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27537 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Add definitions to support the Gaia platform Define ASIC address, memory preallocations, and initialization code for the Gaia platform. Signed-off-by: David VomLehn --- arch/mips/include/asm/mach-powertv/asic.h | 4 + arch/mips/include/asm/mach-powertv/asic_regs.h | 4 +- arch/mips/powertv/asic/Makefile | 6 +- arch/mips/powertv/asic/asic-gaia.c | 96 ++++ arch/mips/powertv/asic/asic_devices.c | 20 +- arch/mips/powertv/asic/prealloc-gaia.c | 589 ++++++++++++++++++++++++ 6 files changed, 708 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h index bcad43a..df33d93 100644 --- a/arch/mips/include/asm/mach-powertv/asic.h +++ b/arch/mips/include/asm/mach-powertv/asic.h @@ -40,19 +40,23 @@ enum family_type { FAMILY_8600VZB, FAMILY_1500VZE, FAMILY_1500VZF, + FAMILY_8700, FAMILIES }; /* Register maps for each ASIC */ extern const struct register_map calliope_register_map; extern const struct register_map cronus_register_map; +extern const struct register_map gaia_register_map; extern const struct register_map zeus_register_map; extern struct resource dvr_cronus_resources[]; +extern struct resource dvr_gaia_resources[]; extern struct resource dvr_zeus_resources[]; extern struct resource non_dvr_calliope_resources[]; extern struct resource non_dvr_cronus_resources[]; extern struct resource non_dvr_cronuslite_resources[]; +extern struct resource non_dvr_gaia_resources[]; extern struct resource non_dvr_vz_calliope_resources[]; extern struct resource non_dvr_vze_calliope_resources[]; extern struct resource non_dvr_vzf_calliope_resources[]; diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h index 1e11236..2657ae6 100644 --- a/arch/mips/include/asm/mach-powertv/asic_regs.h +++ b/arch/mips/include/asm/mach-powertv/asic_regs.h @@ -27,7 +27,8 @@ enum asic_type { ASIC_CALLIOPE, ASIC_CRONUS, ASIC_CRONUSLITE, - ASICS + ASIC_GAIA, + ASICS /* Number of supported ASICs */ }; /* hardcoded values read from Chip Version registers */ @@ -37,6 +38,7 @@ enum asic_type { #define NAND_FLASH_BASE 0x03000000 #define CALLIOPE_IO_BASE 0x08000000 +#define GAIA_IO_BASE 0x09000000 #define CRONUS_IO_BASE 0x09000000 #define ZEUS_IO_BASE 0x09000000 diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile index bebfdcf..f0e95dc 100644 --- a/arch/mips/powertv/asic/Makefile +++ b/arch/mips/powertv/asic/Makefile @@ -16,8 +16,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \ - irq_asic.o prealloc-calliope.o prealloc-cronus.o \ - prealloc-cronuslite.o prealloc-zeus.o +obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \ + asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \ + prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o EXTRA_CFLAGS += -Wall -Werror diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c new file mode 100644 index 0000000..91dda68 --- /dev/null +++ b/arch/mips/powertv/asic/asic-gaia.c @@ -0,0 +1,96 @@ +/* + * Locations of devices in the Gaia ASIC + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#include +#include + +const struct register_map gaia_register_map __initdata = { + .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000}, + .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038}, + .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C}, + + .chipver3 = {.phys = GAIA_IO_BASE + 0x2A0800}, + .chipver2 = {.phys = GAIA_IO_BASE + 0x2A0804}, + .chipver1 = {.phys = GAIA_IO_BASE + 0x2A0808}, + .chipver0 = {.phys = GAIA_IO_BASE + 0x2A080C}, + + /* The registers of IRBlaster */ + .uart1_intstat = {.phys = GAIA_IO_BASE + 0x2A1800}, + .uart1_inten = {.phys = GAIA_IO_BASE + 0x2A1804}, + .uart1_config1 = {.phys = GAIA_IO_BASE + 0x2A1808}, + .uart1_config2 = {.phys = GAIA_IO_BASE + 0x2A180C}, + .uart1_divisorhi = {.phys = GAIA_IO_BASE + 0x2A1810}, + .uart1_divisorlo = {.phys = GAIA_IO_BASE + 0x2A1814}, + .uart1_data = {.phys = GAIA_IO_BASE + 0x2A1818}, + .uart1_status = {.phys = GAIA_IO_BASE + 0x2A181C}, + + .int_stat_3 = {.phys = GAIA_IO_BASE + 0x2A2800}, + .int_stat_2 = {.phys = GAIA_IO_BASE + 0x2A2804}, + .int_stat_1 = {.phys = GAIA_IO_BASE + 0x2A2808}, + .int_stat_0 = {.phys = GAIA_IO_BASE + 0x2A280C}, + .int_config = {.phys = GAIA_IO_BASE + 0x2A2810}, + .int_int_scan = {.phys = GAIA_IO_BASE + 0x2A2818}, + .ien_int_3 = {.phys = GAIA_IO_BASE + 0x2A2830}, + .ien_int_2 = {.phys = GAIA_IO_BASE + 0x2A2834}, + .ien_int_1 = {.phys = GAIA_IO_BASE + 0x2A2838}, + .ien_int_0 = {.phys = GAIA_IO_BASE + 0x2A283C}, + .int_level_3_3 = {.phys = GAIA_IO_BASE + 0x2A2880}, + .int_level_3_2 = {.phys = GAIA_IO_BASE + 0x2A2884}, + .int_level_3_1 = {.phys = GAIA_IO_BASE + 0x2A2888}, + .int_level_3_0 = {.phys = GAIA_IO_BASE + 0x2A288C}, + .int_level_2_3 = {.phys = GAIA_IO_BASE + 0x2A2890}, + .int_level_2_2 = {.phys = GAIA_IO_BASE + 0x2A2894}, + .int_level_2_1 = {.phys = GAIA_IO_BASE + 0x2A2898}, + .int_level_2_0 = {.phys = GAIA_IO_BASE + 0x2A289C}, + .int_level_1_3 = {.phys = GAIA_IO_BASE + 0x2A28A0}, + .int_level_1_2 = {.phys = GAIA_IO_BASE + 0x2A28A4}, + .int_level_1_1 = {.phys = GAIA_IO_BASE + 0x2A28A8}, + .int_level_1_0 = {.phys = GAIA_IO_BASE + 0x2A28AC}, + .int_level_0_3 = {.phys = GAIA_IO_BASE + 0x2A28B0}, + .int_level_0_2 = {.phys = GAIA_IO_BASE + 0x2A28B4}, + .int_level_0_1 = {.phys = GAIA_IO_BASE + 0x2A28B8}, + .int_level_0_0 = {.phys = GAIA_IO_BASE + 0x2A28BC}, + .int_docsis_en = {.phys = GAIA_IO_BASE + 0x2A28F4}, + + .mips_pll_setup = {.phys = GAIA_IO_BASE + 0x1C0000}, + .fs432x4b4_usb_ctl = {.phys = GAIA_IO_BASE + 0x1C0024}, + .test_bus = {.phys = GAIA_IO_BASE + 0x1C00CC}, + .crt_spare = {.phys = GAIA_IO_BASE + 0x1c0108}, + .usb2_ohci_int_mask = {.phys = GAIA_IO_BASE + 0x20000C}, + .usb2_strap = {.phys = GAIA_IO_BASE + 0x200014}, + .ehci_hcapbase = {.phys = GAIA_IO_BASE + 0x21FE00}, + .ohci_hc_revision = {.phys = GAIA_IO_BASE + 0x21fc00}, + .bcm1_bs_lmi_steer = {.phys = GAIA_IO_BASE + 0x2E0004}, + .usb2_control = {.phys = GAIA_IO_BASE + 0x2E004C}, + .usb2_stbus_obc = {.phys = GAIA_IO_BASE + 0x21FF00}, + .usb2_stbus_mess_size = {.phys = GAIA_IO_BASE + 0x21FF04}, + .usb2_stbus_chunk_size = {.phys = GAIA_IO_BASE + 0x21FF08}, + + .pcie_regs = {.phys = GAIA_IO_BASE + 0x220000}, + .tim_ch = {.phys = GAIA_IO_BASE + 0x2A2C10}, + .tim_cl = {.phys = GAIA_IO_BASE + 0x2A2C14}, + .gpio_dout = {.phys = GAIA_IO_BASE + 0x2A2C20}, + .gpio_din = {.phys = GAIA_IO_BASE + 0x2A2C24}, + .gpio_dir = {.phys = GAIA_IO_BASE + 0x2A2C2C}, + .watchdog = {.phys = GAIA_IO_BASE + 0x2A2C30}, + .front_panel = {.phys = GAIA_IO_BASE + 0x2A3800}, +}; diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c index 006285c..095a887 100644 --- a/arch/mips/powertv/asic/asic_devices.c +++ b/arch/mips/powertv/asic/asic_devices.c @@ -1,7 +1,6 @@ /* - * ASIC Device List Intialization * - * Description: Defines the platform resources for the SA settop. + * Description: Defines the platform resources for Gaia-based settops. * * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. * @@ -19,11 +18,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * - * Author: Ken Eppinett - * David Schleef - * - * Description: Defines the platform resources for the SA settop. - * * NOTE: The bootloader allocates persistent memory at an address which is * 16 MiB below the end of the highest address in KSEG0. All fixed * address memory reservations must avoid this region. @@ -289,6 +283,9 @@ static __init noinline void platform_set_family(void) case BOOTLDRFAMILY('F', '1'): platform_family = FAMILY_1500VZF; break; + case BOOTLDRFAMILY('8', '7'): + platform_family = FAMILY_8700; + break; default: platform_family = -1; } @@ -526,6 +523,15 @@ void __init configure_platform(void) "DVR_CAPABLE\n"); break; + case FAMILY_8700: + platform_features = FFS_CAPABLE | PCIE_CAPABLE; + asic = ASIC_GAIA; + set_register_map(GAIA_IO_BASE, &gaia_register_map); + gp_resources = dvr_gaia_resources; + + pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n"); + break; + default: pr_crit("Platform: UNKNOWN PLATFORM\n"); break; diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c new file mode 100644 index 0000000..8ac8c7a --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-gaia.c @@ -0,0 +1,589 @@ +/* + * Memory pre-allocations for Gaia boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#include +#include + +/* + * DVR_CAPABLE GAIA RESOURCES + */ +struct resource dvr_gaia_resources[] __initdata = { + /* + * + * VIDEO1 / LX1 + * + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x241FFFFF, /* 2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24201FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /* + * + * VIDEO2 / LX2 + * + */ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + */ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x64180000 - 1, /* 12 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + */ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x00280000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + */ + { + .name = "DisplayBins1", + .start = 0x64AD4000, + .end = 0x64AD5000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * ITFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "ITFS", + .start = 0x64180000, + /* 815,104 bytes each for 2 ITFS partitions. */ + .end = 0x6430DFFF, + .flags = IORESOURCE_IO, + }, + /* + * + * AVFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "AvfsDmaMem", + .start = 0x6430E000, + /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ + .end = 0x64AD0000 - 1, + .flags = IORESOURCE_IO, + }, + { + .name = "AvfsFileSys", + .start = 0x64AD0000, + .end = 0x64AD1000 - 1, /* 4K */ + .flags = IORESOURCE_IO, + }, + /* + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + */ + { + .name = "SmartCardInfo", + .start = 0x64AD1000, + .end = 0x64AD3800 - 1, + .flags = IORESOURCE_IO, + }, + /* + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + */ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + /* + * Add other resources here + */ + { }, +}; + +/* + * NON_DVR_CAPABLE GAIA RESOURCES + */ +struct resource non_dvr_gaia_resources[] __initdata = { + /* + * + * VIDEO1 / LX1 + * + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x241FFFFF, /* 2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24201FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /* + * + * VIDEO2 / LX2 + * + */ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + */ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x64180000 - 1, /* 12 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + */ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + */ + { + .name = "DisplayBins1", + .start = 0x64AD4000, + .end = 0x64AD5000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * AVFS: player HAL memory + * + * + */ + { + .name = "AvfsDmaMem", + .start = 0x6430E000, + .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_IO, + }, + /* + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + */ + { + .name = "SmartCardInfo", + .start = 0x64AD1000, + .end = 0x64AD3800 - 1, + .flags = IORESOURCE_IO, + }, + /* + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + */ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + { }, +}; From ralf@linux-mips.org Mon Aug 2 21:25:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 21:25:56 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:50519 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492729Ab0HBTZw (ORCPT ); Mon, 2 Aug 2010 21:25:52 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o72JPjjU032287; Mon, 2 Aug 2010 20:25:45 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o72JPiTX032212; Mon, 2 Aug 2010 20:25:44 +0100 Date: Mon, 2 Aug 2010 20:25:44 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/4] MIPS: BCM47xx: Fill values for b43 into ssb sprom Message-ID: <20100802192543.GA31070@linux-mips.org> References: <1280261566-8247-1-git-send-email-hauke@hauke-m.de> <1280261566-8247-3-git-send-email-hauke@hauke-m.de> <20100802153103.GB11598@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100802153103.GB11598@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27538 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Aug 02, 2010 at 04:31:03PM +0100, Ralf Baechle wrote: > Date: Mon, 2 Aug 2010 16:31:03 +0100 > From: Ralf Baechle > To: Hauke Mehrtens > Cc: linux-mips@linux-mips.org > Subject: Re: [PATCH 2/4] MIPS: BCM47xx: Fill values for b43 into ssb sprom > Content-Type: text/plain; charset=us-ascii > > Thanks, applied. Causes warnings which then break the build. Dropped. Ralf From hauke@hauke-m.de Mon Aug 2 23:46:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 23:47:01 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:60923 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492789Ab0HBVq6 (ORCPT ); Mon, 2 Aug 2010 23:46:58 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 63FAC85E2; Mon, 2 Aug 2010 23:46:55 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pG8X+-82jwhn; Mon, 2 Aug 2010 23:46:51 +0200 (CEST) Received: from [192.168.0.200] (host-091-096-211-123.ewe-ip-backbone.de [91.96.211.123]) by hauke-m.de (Postfix) with ESMTPSA id 5E6BD85E1; Mon, 2 Aug 2010 23:46:51 +0200 (CEST) Message-ID: <4C573CC9.7020608@hauke-m.de> Date: Mon, 02 Aug 2010 23:46:49 +0200 From: Hauke Mehrtens User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100713 Lightning/1.0b1 Thunderbird/3.0.6 MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH 2/4] MIPS: BCM47xx: Fill values for b43 into ssb sprom References: <1280261566-8247-1-git-send-email-hauke@hauke-m.de> <1280261566-8247-3-git-send-email-hauke@hauke-m.de> <20100802153103.GB11598@linux-mips.org> <20100802192543.GA31070@linux-mips.org> In-Reply-To: <20100802192543.GA31070@linux-mips.org> X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27539 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Am 02.08.2010 21:25, schrieb Ralf Baechle: > On Mon, Aug 02, 2010 at 04:31:03PM +0100, Ralf Baechle wrote: >> Date: Mon, 2 Aug 2010 16:31:03 +0100 >> From: Ralf Baechle >> To: Hauke Mehrtens >> Cc: linux-mips@linux-mips.org >> Subject: Re: [PATCH 2/4] MIPS: BCM47xx: Fill values for b43 into ssb sprom >> Content-Type: text/plain; charset=us-ascii >> >> Thanks, applied. > > Causes warnings which then break the build. Dropped. > > Ralf Hi, what warnings and error messages do you get? Hauke From hauke@hauke-m.de Mon Aug 2 23:56:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Aug 2010 23:56:33 +0200 (CEST) Received: from server19320154104.serverpool.info ([193.201.54.104]:37911 "EHLO hauke-m.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492134Ab0HBV43 (ORCPT ); Mon, 2 Aug 2010 23:56:29 +0200 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 57F2985E2; Mon, 2 Aug 2010 23:56:29 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fPW+vg8D379S; Mon, 2 Aug 2010 23:56:25 +0200 (CEST) Received: from localhost.localdomain (host-091-096-211-123.ewe-ip-backbone.de [91.96.211.123]) by hauke-m.de (Postfix) with ESMTPSA id 2607B85E1; Mon, 2 Aug 2010 23:56:25 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Hauke Mehrtens , Waldemar Brodkorb Subject: [PATCH] MIPS: BCM47xx: nvram_getenv fix return value. Date: Mon, 2 Aug 2010 23:56:22 +0200 Message-Id: <1280786182-6100-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27540 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips nvram_getenv should behave like cfe_getenv. For now it is used like cfe_getenv. cfe_getenv returns 0 on success and -9 if the value was not found. If the input was wrong -8 will be returned by cfe_getenv. Change nvram_getenv to do the same. The code using nvram_getenv expects it to behave like cfe_getenv does. CC: Waldemar Brodkorb Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/nvram.c | 4 ++-- arch/mips/include/asm/mach-bcm47xx/nvram.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index 06e03b2..e5b6615 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -69,7 +69,7 @@ int nvram_getenv(char *name, char *val, size_t val_len) char *var, *value, *end, *eq; if (!name) - return 1; + return NVRAM_ERR_INV_PARAM; if (!nvram_buf[0]) early_nvram_init(); @@ -89,6 +89,6 @@ int nvram_getenv(char *name, char *val, size_t val_len) return 0; } } - return 1; + return NVRAM_ERR_ENVNOTFOUND; } EXPORT_SYMBOL(nvram_getenv); diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h index 0d8cc14..c58ebd8 100644 --- a/arch/mips/include/asm/mach-bcm47xx/nvram.h +++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h @@ -31,6 +31,9 @@ struct nvram_header { #define NVRAM_MAX_VALUE_LEN 255 #define NVRAM_MAX_PARAM_LEN 64 +#define NVRAM_ERR_INV_PARAM -8 +#define NVRAM_ERR_ENVNOTFOUND -9 + extern int nvram_getenv(char *name, char *val, size_t val_len); #endif -- 1.7.0.4 From dvomlehn@cisco.com Tue Aug 3 03:41:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 03:41:08 +0200 (CEST) Received: from sj-iport-4.cisco.com ([171.68.10.86]:62440 "EHLO sj-iport-4.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493069Ab0HCBlC (ORCPT ); Tue, 3 Aug 2010 03:41:02 +0200 Authentication-Results: sj-iport-4.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAAIRV0yrRN+J/2dsb2JhbACgBnGpKZtoghiDIQSEFg X-IronPort-AV: E=Sophos;i="4.55,306,1278288000"; d="scan'208";a="166566270" Received: from sj-core-3.cisco.com ([171.68.223.137]) by sj-iport-4.cisco.com with ESMTP; 03 Aug 2010 01:40:54 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-3.cisco.com (8.13.8/8.14.3) with ESMTP id o731esOK015916; Tue, 3 Aug 2010 01:40:54 GMT Date: Mon, 2 Aug 2010 18:40:54 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: greg@kroah.com, linux-usb@vger.kernel.org, ralf@linux-mips.org Subject: [PATCH 1/2][USB] USB/PowerTV: Add support for PowerTV USB interface Message-ID: <20100803014054.GA31524@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27541 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Add support for the Cisco PowerTV USB interface. This is a very simple set of glue functions, apparently derived some time ago from the au1xxx driver by Matt Porter. Signed-off-by: David VomLehn --- drivers/usb/host/ehci-hcd.c | 5 + drivers/usb/host/ehci-powertv.c | 196 ++++++++++++++++++++++++++++++++ drivers/usb/host/ohci-hcd.c | 5 + drivers/usb/host/ohci-powertv.c | 237 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 443 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index a3ef2a9..1dca632 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1158,6 +1158,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_atmel_driver #endif +#ifdef CONFIG_POWERTV +#include "ehci-powertv.c" +#define PLATFORM_DRIVER ehci_hcd_powertv_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-powertv.c b/drivers/usb/host/ehci-powertv.c new file mode 100644 index 0000000..92fe201 --- /dev/null +++ b/drivers/usb/host/ehci-powertv.c @@ -0,0 +1,196 @@ +/* + * EHCI HCD (Host Controller Driver) for USB. + * + * Bus Glue for PowerTV USB interface + * + * Based on "ohci-au1xxx.c" by Matt Porter + * + * Modified for AMD Alchemy Au1200 EHC + * by K.Boge + * Modified for PowerTV USB interface + * by D. VomLehn + * + * This file is licenced under the GPL. + */ + +#include +#include +#include + +#ifndef CONFIG_POWERTV +#error "This file is POWERTV bus glue. CONFIG_POWERTV must be defined." +#endif + +static void powertv_start_ehc(struct usb_hcd *hcd) +{ + platform_configure_usb_ehci(); + udelay(10); /* Is this necessary? */ +} + +static void powertv_stop_ehc(struct usb_hcd *hcd) +{ + platform_unconfigure_usb_ehci(); + udelay(10); /* Is this necessary? */ +} + +static const struct hc_driver ehci_powertv_hc_driver = { + .description = hcd_name, + .product_desc = "POWERTV EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + * + * FIXME -- ehci_init() doesn't do enough here. + * See ehci-ppc-soc for a complete implementation. + */ + .reset = ehci_init, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, +}; + +/* configure so an HC device and id are always provided */ +/* always called with process context; sleeping is OK */ + + +/** + * usb_hcd_powertv_probe - initialize asic-based HCDs + * Context: !in_interrupt() + * + * Allocates basic resources for this USB host controller, and + * then invokes the start() method for the HCD associated with it + * through the hotplug entry's driver_data. + * + */ +static int ehci_hcd_powertv_drv_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct ehci_hcd *ehci; + int ret; + + if (usb_disabled()) + return -ENODEV; + + if (pdev->resource[1].flags != IORESOURCE_IRQ) { + pr_debug("resource[1] is not IORESOURCE_IRQ"); + return -ENOMEM; + } + hcd = usb_create_hcd(&ehci_powertv_hc_driver, &pdev->dev, + "powertv-ehci"); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = pdev->resource[0].start; + hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; + +#ifdef DO_MEMORY_REGION + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_debug("request_mem_region failed"); + ret = -EBUSY; + goto err1; + } + +#endif + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed"); + ret = -ENOMEM; +#ifdef DO_MEMORY_REGION + goto err2; +#else + goto err1; +#endif + } + + powertv_start_ehc(hcd); + + ehci = hcd_to_ehci(hcd); + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = readl(&ehci->caps->hcs_params); + + ret = usb_add_hcd(hcd, pdev->resource[1].start, + IRQF_DISABLED | IRQF_SHARED); + if (ret == 0) { + platform_set_drvdata(pdev, hcd); + return ret; + } + + powertv_stop_ehc(hcd); + iounmap(hcd->regs); +#ifdef DO_MEMORY_REGION +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +#endif +err1: + usb_put_hcd(hcd); + return ret; +} + +/* may be called without controller electrically present */ +/* may be called with controller, bus, and devices active */ + +/** + * usb_hcd_powertv_remove - shutdown processing for asic-based HCDs + * @dev: USB Host Controller being removed + * Context: !in_interrupt() + * + * Reverses the effect of usb_hcd_powertv_probe(), first invoking + * the HCD's stop() method. It is always called from a thread + * context, normally "rmmod", "apmd", or something similar. + * + */ +static int ehci_hcd_powertv_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + powertv_stop_ehc(hcd); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver ehci_hcd_powertv_driver = { + .probe = ehci_hcd_powertv_drv_probe, + .remove = ehci_hcd_powertv_drv_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "powertv-ehci", + .owner = THIS_MODULE, + } +}; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index fc57655..86992a0 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1095,6 +1095,11 @@ MODULE_LICENSE ("GPL"); #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver #endif +#ifdef CONFIG_POWERTV +#include "ohci-powertv.c" +#define PLATFORM_DRIVER ohci_hcd_powertv_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ diff --git a/drivers/usb/host/ohci-powertv.c b/drivers/usb/host/ohci-powertv.c new file mode 100644 index 0000000..1f48ca6 --- /dev/null +++ b/drivers/usb/host/ohci-powertv.c @@ -0,0 +1,237 @@ +/* + * OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * (C) Copyright 2002 Hewlett-Packard Company + * + * Bus Glue for PowerTV USB interface + * + * Written by Christopher Hoover + * Based on fragments of previous driver by Russell King et al. + * + * Modified for LH7A404 from ohci-sa1111.c + * by Durgesh Pattamatta + * Modified for AMD Alchemy Au1xxx + * by Matt Porter + * + * This file is licenced under the GPL. + */ + +#include +#include +#include + +#ifndef CONFIG_POWERTV +#error "This file is POWERTV bus glue. CONFIG_POWERTV must be defined." +#endif + +/* + * Enable the controller interface + */ +static void powertv_start_ohc(struct usb_hcd *hcd) +{ + int rc; + + platform_configure_usb_ohci(); + + rc = ohci_init(hcd_to_ohci(hcd)); + + if (rc == 0) { + __hc32 a; + struct ohci_hcd *ohci; + + /* ensure the state is one consistent with that expected by the + * OHCI-specific driver */ + ohci = hcd_to_ohci(hcd); + a = ohci_readl(ohci, &ohci->regs->roothub.a); + a &= ~(RH_A_NOCP | RH_A_NPS); + ohci_writel(ohci, a, &ohci->regs->roothub.a); + } + udelay(10); /* Is this necessary? */ +} + +/* + * Disable the controller interface + */ +static void powertv_stop_ohc(struct usb_hcd *hcd) +{ + platform_unconfigure_usb_ohci(); + udelay(10); /* Is this necessary? */ +} + +static int __devinit ohci_powertv_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int ret; + + ohci_dbg(ohci, "ohci_powertv_start, ohci:%p", ohci); + + ret = ohci_init(ohci); + + if (ret < 0) + return ret; + + ret = ohci_run(ohci); + + if (ret < 0) { + err("can't start %s", hcd->self.bus_name); + ohci_stop(hcd); + return ret; + } + + return 0; +} + +static const struct hc_driver ohci_powertv_hc_driver = { + .description = hcd_name, + .product_desc = "POWERTV OHCI", + .hcd_priv_size = sizeof(struct ohci_hcd), + + /* + * generic hardware linkage + */ + .irq = ohci_irq, + .flags = HCD_USB11 | HCD_MEMORY, + + /* + * basic lifecycle operations + */ + .start = ohci_powertv_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ohci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ohci_bus_suspend, + .bus_resume = ohci_bus_resume, +#endif + .start_port_reset = ohci_start_port_reset, +}; + +/* configure so an HC device and id are always provided */ +/* always called with process context; sleeping is OK */ + + +/** + * usb_hcd_powertv_probe - initialize asic-based HCDs + * Context: !in_interrupt() + * + * Allocates basic resources for this USB host controller, and + * then invokes the start() method for the HCD associated with it + * through the hotplug entry's driver_data. + * + */ +static int ohci_hcd_powertv_drv_probe(struct platform_device *pdev) +{ + int ret; + struct usb_hcd *hcd; + + if (usb_disabled()) + return -ENODEV; + + if (pdev->resource[1].flags != IORESOURCE_IRQ) { + pr_debug("resource[1] is not IORESOURCE_IRQ\n"); + return -ENOMEM; + } + + hcd = usb_create_hcd(&ohci_powertv_hc_driver, &pdev->dev, + "powertv-ohci"); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = pdev->resource[0].start; + hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; + +#ifdef DO_MEMORY_REGION + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_debug("request_mem_region failed\n"); + ret = -EBUSY; + goto err1; + } + +#endif + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed\n"); + ret = -ENOMEM; +#ifdef DO_MEMORY_REGION + goto err2; +#else + goto err1; +#endif + } + + powertv_start_ohc(hcd); + ohci_hcd_init(hcd_to_ohci(hcd)); + + ret = usb_add_hcd(hcd, pdev->resource[1].start, + IRQF_DISABLED | IRQF_SHARED); + if (ret == 0) { + platform_set_drvdata(pdev, hcd); + return ret; + } + + powertv_stop_ohc(hcd); + iounmap(hcd->regs); +#ifdef DO_MEMORY_REGION +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +#endif +err1: + usb_put_hcd(hcd); + return ret; +} + +/* may be called without controller electrically present */ +/* may be called with controller, bus, and devices active */ + +/** + * usb_hcd_powertv_drv_remove - shutdown processing for asic-based HCDs + * @pdev: Pointer to platform device for USB Host Controller being removed + * Context: !in_interrupt() + * + * Reverses the effect of usb_hcd_powertv_probe(), first invoking + * the HCD's stop() method. It is always called from a thread + * context, normally "rmmod", "apmd", or something similar. + * + */ +static int ohci_hcd_powertv_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + powertv_stop_ohc(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver ohci_hcd_powertv_driver = { + .probe = ohci_hcd_powertv_drv_probe, + .remove = ohci_hcd_powertv_drv_remove, + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "powertv-ohci", + .owner = THIS_MODULE, + }, +}; From dvomlehn@cisco.com Tue Aug 3 03:41:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 03:41:35 +0200 (CEST) Received: from sj-iport-5.cisco.com ([171.68.10.87]:46095 "EHLO sj-iport-5.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492148Ab0HCBlH (ORCPT ); Tue, 3 Aug 2010 03:41:07 +0200 Authentication-Results: sj-iport-5.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAB0QV0yrR7Ht/2dsb2JhbACgBnGpIJtnghiDIQSEFg X-IronPort-AV: E=Sophos;i="4.55,306,1278288000"; d="scan'208";a="234533612" Received: from sj-core-1.cisco.com ([171.71.177.237]) by sj-iport-5.cisco.com with ESMTP; 03 Aug 2010 01:40:57 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-1.cisco.com (8.13.8/8.14.3) with ESMTP id o731evl9024822; Tue, 3 Aug 2010 01:40:57 GMT Date: Mon, 2 Aug 2010 18:40:58 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: greg@kroah.com, linux-usb@vger.kernel.org, ralf@linux-mips.org Subject: [PATCH 2/2][MIPS] USB/PowerTV: Separate PowerTV USB support from non-USB code Message-ID: <20100803014058.GA31552@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27542 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Separate USB code into a file separate from asic/asic_devices. Separating the USB code from everything else in asic/asic_devices.c goes a long way toward reducing the use of that file as a dumping ground for everything that didn't seem to fit anywhere else. Signed-off-by: David VomLehn --- arch/mips/include/asm/mach-powertv/asic.h | 17 +- arch/mips/include/asm/mach-powertv/asic_regs.h | 1 + arch/mips/powertv/Makefile | 2 + arch/mips/powertv/asic/asic_devices.c | 238 +------------- arch/mips/powertv/powertv-usb.c | 403 ++++++++++++++++++++++++ 5 files changed, 432 insertions(+), 229 deletions(-) diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h index df33d93..c7077a6 100644 --- a/arch/mips/include/asm/mach-powertv/asic.h +++ b/arch/mips/include/asm/mach-powertv/asic.h @@ -20,6 +20,7 @@ #define _ASM_MACH_POWERTV_ASIC_H #include +#include #include #define DVR_CAPABLE (1<<0) @@ -71,16 +72,24 @@ extern int platform_supports_ffs(void); extern int platform_supports_pcie(void); extern int platform_supports_display(void); extern void configure_platform(void); -extern void platform_configure_usb_ehci(void); -extern void platform_unconfigure_usb_ehci(void); -extern void platform_configure_usb_ohci(void); -extern void platform_unconfigure_usb_ohci(void); /* Platform Resources */ #define ASIC_RESOURCE_GET_EXISTS 1 extern struct resource *asic_resource_get(const char *name); extern void platform_release_memory(void *baddr, int size); +/* USB configuration */ +struct usb_hcd; /* Forward reference */ +extern void platform_configure_usb_ehci(void); +extern void platform_unconfigure_usb_ehci(void); +extern void platform_configure_usb_ohci(void); +extern void platform_unconfigure_usb_ohci(void); + +/* Resource for ASIC registers */ +extern struct resource asic_resource; +extern int platform_usb_devices_init(struct platform_device **echi_dev, + struct platform_device **ohci_dev); + /* Reboot Cause */ extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); extern void set_locked_reboot_cause(char code, unsigned int data, diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h index 2657ae6..deecb26 100644 --- a/arch/mips/include/asm/mach-powertv/asic_regs.h +++ b/arch/mips/include/asm/mach-powertv/asic_regs.h @@ -101,6 +101,7 @@ static inline void register_map_virtualize(struct register_map *map) } extern struct register_map _asic_register_map; +extern unsigned long asic_phy_base; /* * Macros to interface to registers through their ioremapped address diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile index e9fe1c6..c914c2b 100644 --- a/arch/mips/powertv/Makefile +++ b/arch/mips/powertv/Makefile @@ -26,4 +26,6 @@ obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \ asic/ pci/ +obj-$(CONFIG_USB) += powertv-usb.o + EXTRA_CFLAGS += -Wall -Werror diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c index 095a887..e56fa61 100644 --- a/arch/mips/powertv/asic/asic_devices.c +++ b/arch/mips/powertv/asic/asic_devices.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #include @@ -68,7 +67,6 @@ unsigned long asic_phy_base; unsigned long asic_base; EXPORT_SYMBOL(asic_base); /* Exported for testing */ struct resource *gp_resources; -static bool usb_configured; /* * Don't recommend to use it directly, it is usually used by kernel internally. @@ -91,101 +89,19 @@ struct resource asic_resource = { }; /* - * - * USB Host Resource Definition - * - */ - -static struct resource ehci_resources[] = { - { - .parent = &asic_resource, - .start = 0, - .end = 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = irq_usbehci, - .end = irq_usbehci, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device ehci_device = { - .name = "powertv-ehci", - .id = 0, - .num_resources = 2, - .resource = ehci_resources, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource ohci_resources[] = { - { - .parent = &asic_resource, - .start = 0, - .end = 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = irq_usbohci, - .end = irq_usbohci, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ohci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device ohci_device = { - .name = "powertv-ohci", - .id = 0, - .num_resources = 2, - .resource = ohci_resources, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct platform_device *platform_devices[] = { - &ehci_device, - &ohci_device, -}; - -/* - * - * Platform Configuration and Device Initialization - * - */ -static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3) -{ - int en_prg, byp, pwr, nsb, val; - int sout; - - sout = 1; - en_prg = 1; - byp = 0; - nsb = 1; - pwr = 1; - - val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) | - (nsb<<1) | (disable_div_by_3<<5)); - - asic_write(val, fs432x4b4_usb_ctl); - asic_write(val | (en_prg<<4), fs432x4b4_usb_ctl); - asic_write(val | (en_prg<<4) | pwr, fs432x4b4_usb_ctl); -} - -/* * Allow override of bootloader-specified model + * Returns zero on success, a negative errno value on failure. This parameter + * allows overriding of the bootloader-specified model. */ static char __initdata cmdline[COMMAND_LINE_SIZE]; #define FORCEFAMILY_PARAM "forcefamily" +/* + * check_forcefamily - check for, and parse, forcefamily command line parameter + * @forced_family: Pointer to two-character array in which to store the + * value of the forcedfamily parameter, if any. + */ static __init int check_forcefamily(unsigned char forced_family[2]) { const char *p; @@ -225,14 +141,10 @@ static __init int check_forcefamily(unsigned char forced_family[2]) */ static __init noinline void platform_set_family(void) { -#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) - unsigned char forced_family[2]; unsigned short bootldr_family; - check_forcefamily(forced_family); - - if (forced_family[0] != '\0' && forced_family[1] != '\0') + if (check_forcefamily(forced_family) == 0) bootldr_family = BOOTLDRFAMILY(forced_family[0], forced_family[1]); else { @@ -298,24 +210,9 @@ unsigned int platform_get_family(void) EXPORT_SYMBOL(platform_get_family); /* - * \brief usb_eye_configure() for optimizing the USB eye on Calliope. - * - * \param unsigned int value saved to the register. - * - * \return none - * - */ -static void __init usb_eye_configure(unsigned int value) -{ - asic_write(asic_read(crt_spare) | value, crt_spare); -} - -/* * platform_get_asic - determine the ASIC type. * - * \param none - * - * \return ASIC type; ASIC_UNKNOWN if none + * Returns the ASIC type, or ASIC_UNKNOWN if unknown * */ enum asic_type platform_get_asic(void) @@ -325,93 +222,10 @@ enum asic_type platform_get_asic(void) EXPORT_SYMBOL(platform_get_asic); /* - * platform_configure_usb - usb configuration based on platform type. - * @bcm1_usb2_ctl: value for the BCM1_USB2_CTL register, which is - * quirky - */ -static void __init platform_configure_usb(void) -{ - u32 bcm1_usb2_ctl; - - if (usb_configured) - return; - - switch (asic) { - case ASIC_ZEUS: - case ASIC_CRONUS: - case ASIC_CRONUSLITE: - fs_update(0x0000, 0x11, 0x02, 0); - bcm1_usb2_ctl = 0x803; - break; - - case ASIC_CALLIOPE: - fs_update(0x0000, 0x11, 0x02, 1); - - switch (platform_family) { - case FAMILY_1500VZE: - break; - - case FAMILY_1500VZF: - usb_eye_configure(0x003c0000); - break; - - default: - usb_eye_configure(0x00300000); - break; - } - - bcm1_usb2_ctl = 0x803; - break; - - default: - pr_err("Unknown ASIC type: %d\n", asic); - break; - } - - /* turn on USB power */ - asic_write(0, usb2_strap); - /* Enable all OHCI interrupts */ - asic_write(bcm1_usb2_ctl, usb2_control); - /* USB2_STBUS_OBC store32/load32 */ - asic_write(3, usb2_stbus_obc); - /* USB2_STBUS_MESS_SIZE 2 packets */ - asic_write(1, usb2_stbus_mess_size); - /* USB2_STBUS_CHUNK_SIZE 2 packets */ - asic_write(1, usb2_stbus_chunk_size); - - usb_configured = true; -} - -/* - * Set up the USB EHCI interface - */ -void platform_configure_usb_ehci() -{ - platform_configure_usb(); -} - -/* - * Set up the USB OHCI interface - */ -void platform_configure_usb_ohci() -{ - platform_configure_usb(); -} - -/* - * Shut the USB EHCI interface down--currently a NOP + * set_register_map - set ASIC register configuration + * @phys_base: Physical address of the base of the ASIC registers + * @map: Description of key ASIC registers */ -void platform_unconfigure_usb_ehci() -{ -} - -/* - * Shut the USB OHCI interface down--currently a NOP - */ -void platform_unconfigure_usb_ohci() -{ -} - static void __init set_register_map(unsigned long phys_base, const struct register_map *map) { @@ -560,34 +374,8 @@ void __init configure_platform(void) } } -/** - * platform_devices_init - sets up USB device resourse. - */ -static int __init platform_devices_init(void) -{ - pr_notice("%s: ----- Initializing USB resources -----\n", __func__); - - asic_resource.start = asic_phy_base; - asic_resource.end += asic_resource.start; - - ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase); - ehci_resources[0].end += ehci_resources[0].start; - - ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision); - ohci_resources[0].end += ohci_resources[0].start; - - set_io_port_base(0); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - - return 0; -} - -arch_initcall(platform_devices_init); - /* - * - * BOOTMEM ALLOCATION + * RESOURCE ALLOCATION * */ /* diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c new file mode 100644 index 0000000..6ac85cf --- /dev/null +++ b/arch/mips/powertv/powertv-usb.c @@ -0,0 +1,403 @@ +/* + * powertv-usb.c + * + * Description: ASIC-specific USB device setup and shutdown + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef + * + * NOTE: The bootloader allocates persistent memory at an address which is + * 16 MiB below the end of the highest address in KSEG0. All fixed + * address memory reservations must avoid this region. + */ + +#include +#include +#include +#include +#include + +/* misc_clk_ctl1 values */ +#define MCC1_30MHZ_POWERUP_SELECT (1 << 14) +#define MCC1_DIV9 (1 << 13) +#define MCC1_ETHMIPS_POWERUP_SELECT (1 << 11) +#define MCC1_USB_POWERUP_SELECT (1 << 1) +#define MCC1_CLOCK108_POWERUP_SELECT (1 << 0) + +/* Possible values for clock select */ +#define MCC1_USB_CLOCK_HIGH_Z (0 << 4) +#define MCC1_USB_CLOCK_48MHZ (1 << 4) +#define MCC1_USB_CLOCK_24MHZ (2 << 4) +#define MCC1_USB_CLOCK_6MHZ (3 << 4) + +#define MCC1_CONFIG (MCC1_30MHZ_POWERUP_SELECT | \ + MCC1_DIV9 | \ + MCC1_ETHMIPS_POWERUP_SELECT | \ + MCC1_USB_POWERUP_SELECT | \ + MCC1_CLOCK108_POWERUP_SELECT) + +/* misc_clk_ctl2 values */ +#define MCC2_GMII_GCLK_TO_PAD (1 << 31) +#define MCC2_ETHER125_0_CLOCK_SELECT (1 << 29) +#define MCC2_RMII_0_CLOCK_SELECT (1 << 28) +#define MCC2_GMII_TX0_CLOCK_SELECT (1 << 27) +#define MCC2_GMII_RX0_CLOCK_SELECT (1 << 26) +#define MCC2_ETHER125_1_CLOCK_SELECT (1 << 24) +#define MCC2_RMII_1_CLOCK_SELECT (1 << 23) +#define MCC2_GMII_TX1_CLOCK_SELECT (1 << 22) +#define MCC2_GMII_RX1_CLOCK_SELECT (1 << 21) +#define MCC2_ETHER125_2_CLOCK_SELECT (1 << 19) +#define MCC2_RMII_2_CLOCK_SELECT (1 << 18) +#define MCC2_GMII_TX2_CLOCK_SELECT (1 << 17) +#define MCC2_GMII_RX2_CLOCK_SELECT (1 << 16) + +#define ETHER_CLK_CONFIG (MCC2_GMII_GCLK_TO_PAD | \ + MCC2_ETHER125_0_CLOCK_SELECT | \ + MCC2_RMII_0_CLOCK_SELECT | \ + MCC2_GMII_TX0_CLOCK_SELECT | \ + MCC2_GMII_RX0_CLOCK_SELECT | \ + MCC2_ETHER125_1_CLOCK_SELECT | \ + MCC2_RMII_1_CLOCK_SELECT | \ + MCC2_GMII_TX1_CLOCK_SELECT | \ + MCC2_GMII_RX1_CLOCK_SELECT | \ + MCC2_ETHER125_2_CLOCK_SELECT | \ + MCC2_RMII_2_CLOCK_SELECT | \ + MCC2_GMII_TX2_CLOCK_SELECT | \ + MCC2_GMII_RX2_CLOCK_SELECT) + +/* misc_clk_ctl2 definitions for Gaia */ +#define FSX4A_REF_SELECT (1 << 16) +#define FSX4B_REF_SELECT (1 << 17) +#define FSX4C_REF_SELECT (1 << 18) +#define DDR_PLL_REF_SELECT (1 << 19) +#define MIPS_PLL_REF_SELECT (1 << 20) + +/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */ +#define QAM_FS_SDIV_SHIFT 29 +#define QAM_FS_MD_SHIFT 24 +#define QAM_FS_MD_MASK 0x1f /* Cut down to 5 bits */ +#define QAM_FS_PE_SHIFT 8 + +#define QAM_FS_DISABLE_DIVIDE_BY_3 (1 << 5) +#define QAM_FS_ENABLE_PROGRAM (1 << 4) +#define QAM_FS_ENABLE_OUTPUT (1 << 3) +#define QAM_FS_SELECT_TEST_BYPASS (1 << 2) +#define QAM_FS_DISABLE_DIGITAL_STANDBY (1 << 1) +#define QAM_FS_CHOOSE_FS (1 << 0) + +/* Definitions for fs432x4a_ctl register */ +#define QAM_FS_NSDIV_54MHZ (1 << 2) + +/* Definitions for bcm1_usb2_ctl register */ +#define BCM1_USB2_CTL_BISTOK (1 << 11) +#define BCM1_USB2_CTL_PORT2_SHIFT_JK (1 << 7) +#define BCM1_USB2_CTL_PORT1_SHIFT_JK (1 << 6) +#define BCM1_USB2_CTL_PORT2_FAST_EDGE (1 << 5) +#define BCM1_USB2_CTL_PORT1_FAST_EDGE (1 << 4) +#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH (1 << 1) +#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH (1 << 0) + +/* Definitions for crt_spare register */ +#define CRT_SPARE_PORT2_SHIFT_JK (1 << 21) +#define CRT_SPARE_PORT1_SHIFT_JK (1 << 20) +#define CRT_SPARE_PORT2_FAST_EDGE (1 << 19) +#define CRT_SPARE_PORT1_FAST_EDGE (1 << 18) +#define CRT_SPARE_DIVIDE_BY_9_FROM_432 (1 << 17) +#define CRT_SPARE_USB_DIVIDE_BY_9 (1 << 16) + +/* Definitions for usb2_stbus_obc register */ +#define USB_STBUS_OBC_STORE32_LOAD32 0x3 + +/* Definitions for usb2_stbus_mess_size register */ +#define USB2_STBUS_MESS_SIZE_2 0x1 /* 2 packets */ + +/* Definitions for usb2_stbus_chunk_size register */ +#define USB2_STBUS_CHUNK_SIZE_2 0x1 /* 2 packets */ + +/* Definitions for usb2_strap register */ +#define USB2_STRAP_HFREQ_SELECT 0x1 + +/* + * USB Host Resource Definition + */ + +static struct resource ehci_resources[] = { + { + .parent = &asic_resource, + .start = 0, + .end = 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = irq_usbehci, + .end = irq_usbehci, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = 0xffffffffULL; + +static struct platform_device ehci_device = { + .name = "powertv-ehci", + .id = 0, + .num_resources = 2, + .resource = ehci_resources, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct resource ohci_resources[] = { + { + .parent = &asic_resource, + .start = 0, + .end = 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = irq_usbohci, + .end = irq_usbohci, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ohci_dmamask = 0xffffffffULL; + +static struct platform_device ohci_device = { + .name = "powertv-ohci", + .id = 0, + .num_resources = 2, + .resource = ohci_resources, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +static unsigned usb_users; +static DEFINE_SPINLOCK(usb_regs_lock); + +/* + * + * fs_update - set frequency synthesizer for USB + * @pe_bits Phase tap setting + * @md_bits Coarse selector bus for algorithm of phase tap + * @sdiv_bits Output divider setting + * @disable_div_by_3 Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero + * @standby Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero + * + * QAM frequency selection code, which affects the frequency at which USB + * runs. The frequency is calculated as: + * 2^15 * ndiv * Fin + * Fout = ------------------------------------------------------------ + * (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32))) + * where: + * Fin 54 MHz + * ndiv QAM_FS_NSDIV_54MHZ ? 8 : 16 + * sdiv 1 << (sdiv_bits + 1) + * ipe Same as pe_bits + * md A five-bit, two's-complement integer (range [-16, 15]), which + * is the lower 5 bits of md_bits. + */ +static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits, + u32 disable_div_by_3, u32 standby) +{ + u32 val; + + val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) | + ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) | + (pe_bits << QAM_FS_PE_SHIFT) | + QAM_FS_ENABLE_OUTPUT | + standby | + disable_div_by_3); + asic_write(val, fs432x4b4_usb_ctl); + asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl); + asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS, + fs432x4b4_usb_ctl); +} + +/* + * usb_eye_configure - for optimizing the shape USB eye waveform + * @set: Bits to set in the register + * @clear: Bits to clear in the register; each bit with a one will + * be set in the register, zero bits will not be modified + */ +static void usb_eye_configure(u32 set, u32 clear) +{ + u32 old; + + old = asic_read(crt_spare); + old |= set; + old &= ~clear; + asic_write(old, crt_spare); +} + +/* + * platform_configure_usb - usb configuration based on platform type. + */ +static void platform_configure_usb(void) +{ + u32 bcm1_usb2_ctl_value; + enum asic_type asic_type; + unsigned long flags; + + spin_lock_irqsave(&usb_regs_lock, flags); + usb_users++; + + if (usb_users != 1) { + spin_unlock_irqrestore(&usb_regs_lock, flags); + return; + } + + asic_type = platform_get_asic(); + + switch (asic_type) { + case ASIC_ZEUS: + fs_update(0x0000, -15, 0x02, 0, 0); + bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | + BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; + break; + + case ASIC_CRONUS: + case ASIC_CRONUSLITE: + usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9); + fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3, + QAM_FS_DISABLE_DIGITAL_STANDBY); + bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | + BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; + break; + + case ASIC_CALLIOPE: + fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3, + QAM_FS_DISABLE_DIGITAL_STANDBY); + + switch (platform_get_family()) { + case FAMILY_1500VZE: + break; + + case FAMILY_1500VZF: + usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK | + CRT_SPARE_PORT1_SHIFT_JK | + CRT_SPARE_PORT2_FAST_EDGE | + CRT_SPARE_PORT1_FAST_EDGE, 0); + break; + + default: + usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK | + CRT_SPARE_PORT1_SHIFT_JK, 0); + break; + } + + bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK | + BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | + BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; + break; + + case ASIC_GAIA: + fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3, + QAM_FS_DISABLE_DIGITAL_STANDBY); + bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK | + BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | + BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; + break; + + default: + pr_err("Unknown ASIC type: %d\n", asic_type); + bcm1_usb2_ctl_value = 0; + break; + } + + /* turn on USB power */ + asic_write(0, usb2_strap); + /* Enable all OHCI interrupts */ + asic_write(bcm1_usb2_ctl_value, usb2_control); + /* usb2_stbus_obc store32/load32 */ + asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc); + /* usb2_stbus_mess_size 2 packets */ + asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size); + /* usb2_stbus_chunk_size 2 packets */ + asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size); + spin_unlock_irqrestore(&usb_regs_lock, flags); +} + +static void platform_unconfigure_usb(void) +{ + unsigned long flags; + + spin_lock_irqsave(&usb_regs_lock, flags); + usb_users--; + if (usb_users == 0) + asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap); + spin_unlock_irqrestore(&usb_regs_lock, flags); +} + +/* + * Set up the USB EHCI interface + */ +void platform_configure_usb_ehci() +{ + platform_configure_usb(); +} +EXPORT_SYMBOL(platform_configure_usb_ehci); + +/* + * Set up the USB OHCI interface + */ +void platform_configure_usb_ohci() +{ + platform_configure_usb(); +} +EXPORT_SYMBOL(platform_configure_usb_ohci); + +/* + * Shut the USB EHCI interface down + */ +void platform_unconfigure_usb_ehci() +{ + platform_unconfigure_usb(); +} +EXPORT_SYMBOL(platform_unconfigure_usb_ehci); + +/* + * Shut the USB OHCI interface down + */ +void platform_unconfigure_usb_ohci() +{ + platform_unconfigure_usb(); +} +EXPORT_SYMBOL(platform_unconfigure_usb_ohci); + +/** + * platform_devices_init - sets up USB device resourse. + */ +int __init platform_usb_devices_init(struct platform_device **ehci_dev, + struct platform_device **ohci_dev) +{ + *ehci_dev = &ehci_device; + ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase); + ehci_resources[0].end += ehci_resources[0].start; + + *ohci_dev = &ohci_device; + ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision); + ohci_resources[0].end += ohci_resources[0].start; + + return 0; +} From lars@metafoo.de Tue Aug 3 18:33:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 18:33:25 +0200 (CEST) Received: from smtp-out-105.synserver.de ([212.40.180.105]:1202 "EHLO smtp-out-103.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1493144Ab0HCQdS (ORCPT ); Tue, 3 Aug 2010 18:33:18 +0200 Received: (qmail 7998 invoked by uid 0); 3 Aug 2010 16:33:02 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 7684 Received: from d076134.adsl.hansenet.de (HELO localhost.localdomain) [80.171.76.134] by 217.119.54.87 with SMTP; 3 Aug 2010 16:33:02 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-mmc@vger.kernel.org, Maarten ter Huurne , Lars-Peter Clausen Subject: [PATCH] MMC: jz4740: Fixed card change detection. Date: Tue, 3 Aug 2010 18:32:44 +0200 Message-Id: <1280853164-19900-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27543 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips From: Maarten ter Huurne The GPIO validity check was reversed. Also removed some dead code. Signed-off-by: Maarten ter Huurne Signed-off-by: Lars-Peter Clausen --- drivers/mmc/host/jz4740_mmc.c | 8 ++------ 1 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c index 12efd9c..ad4f987 100644 --- a/drivers/mmc/host/jz4740_mmc.c +++ b/drivers/mmc/host/jz4740_mmc.c @@ -761,24 +761,20 @@ err: static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev, struct jz4740_mmc_host *host) { - int ret; struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; - if (gpio_is_valid(pdata->gpio_card_detect)) + if (!gpio_is_valid(pdata->gpio_card_detect)) return 0; host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect); - if (host->card_detect_irq < 0) { dev_warn(&pdev->dev, "Failed to get card detect irq\n"); return 0; } + return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC card detect", host); - - - return ret; } static void jz4740_mmc_free_gpios(struct platform_device *pdev) -- 1.5.6.5 From David.Daney@caviumnetworks.com Tue Aug 3 20:22:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 20:22:45 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19452 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491888Ab0HCSWl (ORCPT ); Tue, 3 Aug 2010 20:22:41 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 11:23:05 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:36 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:36 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73IMWEK026410; Tue, 3 Aug 2010 11:22:32 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73IMRgu026400; Tue, 3 Aug 2010 11:22:27 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org, hschauhan@nulltrace.org, David Daney Subject: [PATCH 0/5] KProbes support for MIPS Date: Tue, 3 Aug 2010 11:22:17 -0700 Message-Id: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 X-OriginalArrivalTime: 03 Aug 2010 18:22:36.0641 (UTC) FILETIME=[D942CD10:01CB3338] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27544 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This patch set adds KProbs, JProbs and KRetProbes support for the MIPS archetecture. It was tested on a 64-bit big-endian kernel (Octeon), but should work equally well on 32-bit and little-endian as well. As you can see from the patches it is partially based on previous work by Sony and Himanshu Chauhan. David Daney (5): MIPS: Define regs_return_value() MIPS: Add instrunction format for BREAK and SYSCALL MIPS: Add KProbe support. samples: kprobe_example: Make it print something on MIPS. documentation: Mention that KProbes is supported on MIPS Documentation/kprobes.txt | 1 + arch/mips/Kconfig | 2 + arch/mips/Makefile | 3 + arch/mips/include/asm/break.h | 2 + arch/mips/include/asm/inst.h | 15 +- arch/mips/include/asm/kdebug.h | 3 + arch/mips/include/asm/kprobes.h | 91 ++++++ arch/mips/include/asm/ptrace.h | 1 + arch/mips/kernel/Makefile | 1 + arch/mips/kernel/kprobes.c | 562 ++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/traps.c | 22 ++- arch/mips/mm/fault.c | 15 +- samples/kprobes/kprobe_example.c | 9 + 13 files changed, 724 insertions(+), 3 deletions(-) create mode 100644 arch/mips/include/asm/kprobes.h create mode 100644 arch/mips/kernel/kprobes.c From David.Daney@caviumnetworks.com Tue Aug 3 20:23:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 20:23:08 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19456 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493163Ab0HCSWr (ORCPT ); Tue, 3 Aug 2010 20:22:47 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 11:23:13 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:44 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:44 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73IMcmT026418; Tue, 3 Aug 2010 11:22:38 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73IMcPj026417; Tue, 3 Aug 2010 11:22:38 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org, hschauhan@nulltrace.org, David Daney Subject: [PATCH 2/5] MIPS: Add instrunction format for BREAK and SYSCALL Date: Tue, 3 Aug 2010 11:22:19 -0700 Message-Id: <1280859742-26364-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 03 Aug 2010 18:22:44.0688 (UTC) FILETIME=[DE0EAD00:01CB3338] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27545 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/include/asm/inst.h | 15 ++++++++++++++- 1 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 6489f00..444ff71 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -247,6 +247,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */ unsigned int fmt : 2; }; +struct b_format { /* BREAK and SYSCALL */ + unsigned int opcode:6; + unsigned int code:20; + unsigned int func:6; +}; + #elif defined(__MIPSEL__) struct j_format { /* Jump format */ @@ -314,6 +320,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */ unsigned int opcode : 6; }; +struct b_format { /* BREAK and SYSCALL */ + unsigned int func:6; + unsigned int code:20; + unsigned int opcode:6; +}; + #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" #endif @@ -328,7 +340,8 @@ union mips_instruction { struct c_format c_format; struct r_format r_format; struct f_format f_format; - struct ma_format ma_format; + struct ma_format ma_format; + struct b_format b_format; }; /* HACHACHAHCAHC ... */ -- 1.7.1.1 From David.Daney@caviumnetworks.com Tue Aug 3 20:23:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 20:23:36 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19468 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493173Ab0HCSWt (ORCPT ); Tue, 3 Aug 2010 20:22:49 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 11:23:15 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:46 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:46 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73IMfv2026422; Tue, 3 Aug 2010 11:22:41 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73IMe6O026421; Tue, 3 Aug 2010 11:22:40 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org, hschauhan@nulltrace.org, David Daney Subject: [PATCH 3/5] MIPS: Add KProbe support. Date: Tue, 3 Aug 2010 11:22:20 -0700 Message-Id: <1280859742-26364-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 03 Aug 2010 18:22:46.0266 (UTC) FILETIME=[DEFF75A0:01CB3338] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27546 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This patch is based on previous work by Sony and Himanshu Chauhan. I have done some cleanup and implemented JProbes and KRETPROBES. The KRETPROBES part is pretty much copied verbatim from powerpc. A possible future enhance might be to factor out the common code. Signed-off-by: David Daney Cc: Himanshu Chauhan --- arch/mips/Kconfig | 2 + arch/mips/Makefile | 3 + arch/mips/include/asm/break.h | 2 + arch/mips/include/asm/kdebug.h | 3 + arch/mips/include/asm/kprobes.h | 91 +++++++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/kprobes.c | 562 +++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/traps.c | 22 ++- arch/mips/mm/fault.c | 15 +- 9 files changed, 699 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/kprobes.h create mode 100644 arch/mips/kernel/kprobes.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index aaca439..36642df 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -10,6 +10,8 @@ config MIPS select HAVE_DYNAMIC_FTRACE select HAVE_FTRACE_MCOUNT_RECORD select HAVE_FUNCTION_GRAPH_TRACER + select HAVE_KPROBES + select HAVE_KRETPROBES select RTC_LIB if !MACH_LOONGSON mainmenu "Linux/MIPS Kernel Configuration" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 9296cbf..f0d1960 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -259,6 +259,9 @@ endif vmlinux.32: vmlinux $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ + +#obj-$(CONFIG_KPROBES) += kprobes.o + # # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit # ELF files from 32-bit files by conversion. diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 44437ed..9161e68 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -30,6 +30,8 @@ #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ #define BRK_MEMU 514 /* Used by FPU emulator */ +#define BRK_KPROBE_BP 515 /* Kprobe break */ +#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */ #define BRK_MULOVF 1023 /* Multiply overflow */ #endif /* __ASM_BREAK_H */ diff --git a/arch/mips/include/asm/kdebug.h b/arch/mips/include/asm/kdebug.h index 5bf62aa..6a9af5f 100644 --- a/arch/mips/include/asm/kdebug.h +++ b/arch/mips/include/asm/kdebug.h @@ -8,6 +8,9 @@ enum die_val { DIE_FP, DIE_TRAP, DIE_RI, + DIE_PAGE_FAULT, + DIE_BREAK, + DIE_SSTEPBP }; #endif /* _ASM_MIPS_KDEBUG_H */ diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h new file mode 100644 index 0000000..fe58e08 --- /dev/null +++ b/arch/mips/include/asm/kprobes.h @@ -0,0 +1,91 @@ +/* + * Kernel Probes (KProbes) + * include/asm-mips/kprobes.h + * + * Copyright 2006 Sony Corp. + * Copyright 2010 Cavium Networks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _ASM_KPROBES_H +#define _ASM_KPROBES_H + +#include +#include + +#include +#include + +#define __ARCH_WANT_KPROBES_INSN_SLOT + +struct kprobe; +struct pt_regs; + +typedef union mips_instruction kprobe_opcode_t; + +#define MAX_INSN_SIZE 2 + +#define flush_insn_slot(p) \ +do { \ + flush_icache_range((unsigned long)p->addr, \ + (unsigned long)p->addr + \ + (MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); \ +} while (0) + + +#define kretprobe_blacklist_size 0 + +void arch_remove_kprobe(struct kprobe *p); + +/* Architecture specific copy of original instruction*/ +struct arch_specific_insn { + /* copy of the original instruction */ + kprobe_opcode_t *insn; +}; + +struct prev_kprobe { + struct kprobe *kp; + unsigned long status; + unsigned long old_SR; + unsigned long saved_SR; + unsigned long saved_epc; +}; + +#define MAX_JPROBES_STACK_SIZE 128 +#define MAX_JPROBES_STACK_ADDR \ + (((unsigned long)current_thread_info()) + THREAD_SIZE - 32 - sizeof(struct pt_regs)) + +#define MIN_JPROBES_STACK_SIZE(ADDR) \ + ((((ADDR) + MAX_JPROBES_STACK_SIZE) > MAX_JPROBES_STACK_ADDR) \ + ? MAX_JPROBES_STACK_ADDR - (ADDR) \ + : MAX_JPROBES_STACK_SIZE) + + +/* per-cpu kprobe control block */ +struct kprobe_ctlblk { + unsigned long kprobe_status; + unsigned long kprobe_old_SR; + unsigned long kprobe_saved_SR; + unsigned long kprobe_saved_epc; + unsigned long jprobe_saved_sp; + struct pt_regs jprobe_saved_regs; + u8 jprobes_stack[MAX_JPROBES_STACK_SIZE]; + struct prev_kprobe prev_kprobe; +}; + +extern int kprobe_exceptions_notify(struct notifier_block *self, + unsigned long val, void *data); + +#endif /* _ASM_KPROBES_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index ff5ec2e..06f8482 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o obj-$(CONFIG_IRQ_GIC) += irq-gic.o +obj-$(CONFIG_KPROBES) += kprobes.o obj-$(CONFIG_32BIT) += scall32-o32.o obj-$(CONFIG_64BIT) += scall64-64.o obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c new file mode 100644 index 0000000..a74ccd2 --- /dev/null +++ b/arch/mips/kernel/kprobes.c @@ -0,0 +1,562 @@ +/* + * Kernel Probes (KProbes) + * arch/mips/kernel/kprobes.c + * + * Copyright 2006 Sony Corp. + * Copyright 2010 Cavium Networks + * + * Some portions copied from the powerpc version. + * + * Copyright (C) IBM Corporation, 2002, 2004 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +static const union mips_instruction breakpoint_insn = { + .b_format = { + .opcode = spec_op, + .code = BRK_KPROBE_BP, + .func = break_op + } +}; + +static const union mips_instruction breakpoint2_insn = { + .b_format = { + .opcode = spec_op, + .code = BRK_KPROBE_SSTEPBP, + .func = break_op + } +}; + +DEFINE_PER_CPU(struct kprobe *, current_kprobe); +DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); + +static int __kprobes insn_has_delayslot(union mips_instruction insn) +{ + switch (insn.i_format.opcode) { + + /* + * This group contains: + * jr and jalr are in r_format format. + */ + case spec_op: + switch (insn.r_format.func) { + case jr_op: + case jalr_op: + break; + default: + goto insn_ok; + } + + /* + * This group contains: + * bltz_op, bgez_op, bltzl_op, bgezl_op, + * bltzal_op, bgezal_op, bltzall_op, bgezall_op. + */ + case bcond_op: + + /* + * These are unconditional and in j_format. + */ + case jal_op: + case j_op: + + /* + * These are conditional and in i_format. + */ + case beq_op: + case beql_op: + case bne_op: + case bnel_op: + case blez_op: + case blezl_op: + case bgtz_op: + case bgtzl_op: + + /* + * These are the FPA/cp1 branch instructions. + */ + case cop1_op: + +#ifdef CONFIG_CPU_CAVIUM_OCTEON + case lwc2_op: /* This is bbit0 on Octeon */ + case ldc2_op: /* This is bbit032 on Octeon */ + case swc2_op: /* This is bbit1 on Octeon */ + case sdc2_op: /* This is bbit132 on Octeon */ +#endif + return 1; + default: + break; + } +insn_ok: + return 0; +} + +int __kprobes arch_prepare_kprobe(struct kprobe *p) +{ + union mips_instruction insn; + union mips_instruction prev_insn; + int ret = 0; + + prev_insn = p->addr[-1]; + insn = p->addr[0]; + + if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) { + pr_notice("Kprobes for branch and jump instructions are not supported\n"); + ret = -EINVAL; + goto out; + } + + /* insn: must be on special executable page on mips. */ + p->ainsn.insn = get_insn_slot(); + if (!p->ainsn.insn) { + ret = -ENOMEM; + goto out; + } + + /* + * In the kprobe->ainsn.insn[] array we store the original + * instruction at index zero and a break trap instruction at + * index one. + */ + + memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t)); + p->ainsn.insn[1] = breakpoint2_insn; + p->opcode = *p->addr; + +out: + return ret; +} + +void __kprobes arch_arm_kprobe(struct kprobe *p) +{ + *(p->addr) = breakpoint_insn; + flush_icache_range((unsigned long)p->addr, + (unsigned long)p->addr + + (MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); +} + +void __kprobes arch_disarm_kprobe(struct kprobe *p) +{ + *p->addr = p->opcode; + flush_icache_range((unsigned long)p->addr, + (unsigned long)p->addr + + (MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); +} + +void __kprobes arch_remove_kprobe(struct kprobe *p) +{ + free_insn_slot(p->ainsn.insn, 0); +} + +static void save_previous_kprobe(struct kprobe_ctlblk *kcb) +{ + kcb->prev_kprobe.kp = kprobe_running(); + kcb->prev_kprobe.status = kcb->kprobe_status; + kcb->prev_kprobe.old_SR = kcb->kprobe_old_SR; + kcb->prev_kprobe.saved_SR = kcb->kprobe_saved_SR; + kcb->prev_kprobe.saved_epc = kcb->kprobe_saved_epc; +} + +static void restore_previous_kprobe(struct kprobe_ctlblk *kcb) +{ + __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp; + kcb->kprobe_status = kcb->prev_kprobe.status; + kcb->kprobe_old_SR = kcb->prev_kprobe.old_SR; + kcb->kprobe_saved_SR = kcb->prev_kprobe.saved_SR; + kcb->kprobe_saved_epc = kcb->prev_kprobe.saved_epc; +} + +static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs, + struct kprobe_ctlblk *kcb) +{ + __get_cpu_var(current_kprobe) = p; + kcb->kprobe_saved_SR = kcb->kprobe_old_SR = (regs->cp0_status & ST0_IE); + kcb->kprobe_saved_epc = regs->cp0_epc; +} + +static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs) +{ + regs->cp0_status &= ~ST0_IE; + + /* single step inline if the instruction is a break */ + if (p->opcode.word == breakpoint_insn.word || + p->opcode.word == breakpoint2_insn.word) + regs->cp0_epc = (unsigned long)p->addr; + else + regs->cp0_epc = (unsigned long)&p->ainsn.insn[0]; +} + +static int __kprobes kprobe_handler(struct pt_regs *regs) +{ + struct kprobe *p; + int ret = 0; + kprobe_opcode_t *addr; + struct kprobe_ctlblk *kcb; + + addr = (kprobe_opcode_t *) regs->cp0_epc; + + /* + * We don't want to be preempted for the entire + * duration of kprobe processing + */ + preempt_disable(); + kcb = get_kprobe_ctlblk(); + + /* Check we're not actually recursing */ + if (kprobe_running()) { + p = get_kprobe(addr); + if (p) { + if (kcb->kprobe_status == KPROBE_HIT_SS && + p->ainsn.insn->word == breakpoint_insn.word) { + regs->cp0_status &= ~ST0_IE; + regs->cp0_status |= kcb->kprobe_saved_SR; + goto no_kprobe; + } + /* + * We have reentered the kprobe_handler(), since + * another probe was hit while within the handler. + * We here save the original kprobes variables and + * just single step on the instruction of the new probe + * without calling any user handlers. + */ + save_previous_kprobe(kcb); + set_current_kprobe(p, regs, kcb); + kprobes_inc_nmissed_count(p); + prepare_singlestep(p, regs); + kcb->kprobe_status = KPROBE_REENTER; + return 1; + } else { + if (addr->word != breakpoint_insn.word) { + /* + * The breakpoint instruction was removed by + * another cpu right after we hit, no further + * handling of this interrupt is appropriate + */ + ret = 1; + goto no_kprobe; + } + p = __get_cpu_var(current_kprobe); + if (p->break_handler && p->break_handler(p, regs)) + goto ss_probe; + } + goto no_kprobe; + } + + p = get_kprobe(addr); + if (!p) { + if (addr->word != breakpoint_insn.word) { + /* + * The breakpoint instruction was removed right + * after we hit it. Another cpu has removed + * either a probepoint or a debugger breakpoint + * at this address. In either case, no further + * handling of this interrupt is appropriate. + */ + ret = 1; + } + /* Not one of ours: let kernel handle it */ + goto no_kprobe; + } + + set_current_kprobe(p, regs, kcb); + kcb->kprobe_status = KPROBE_HIT_ACTIVE; + + if (p->pre_handler && p->pre_handler(p, regs)) { + /* handler has already set things up, so skip ss setup */ + return 1; + } + +ss_probe: + prepare_singlestep(p, regs); + kcb->kprobe_status = KPROBE_HIT_SS; + return 1; + +no_kprobe: + preempt_enable_no_resched(); + return ret; + +} + +/* + * Called after single-stepping. p->addr is the address of the + * instruction whose first byte has been replaced by the "break 0" + * instruction. To avoid the SMP problems that can occur when we + * temporarily put back the original opcode to single-step, we + * single-stepped a copy of the instruction. The address of this + * copy is p->ainsn.insn. + * + * This function prepares to return from the post-single-step + * breakpoint trap. + */ +static void __kprobes resume_execution(struct kprobe *p, + struct pt_regs *regs, + struct kprobe_ctlblk *kcb) +{ + unsigned long orig_epc = kcb->kprobe_saved_epc; + regs->cp0_epc = orig_epc + 4; +} + +static inline int post_kprobe_handler(struct pt_regs *regs) +{ + struct kprobe *cur = kprobe_running(); + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + + if (!cur) + return 0; + + if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) { + kcb->kprobe_status = KPROBE_HIT_SSDONE; + cur->post_handler(cur, regs, 0); + } + + resume_execution(cur, regs, kcb); + + regs->cp0_status |= kcb->kprobe_saved_SR; + + /* Restore back the original saved kprobes variables and continue. */ + if (kcb->kprobe_status == KPROBE_REENTER) { + restore_previous_kprobe(kcb); + goto out; + } + reset_current_kprobe(); +out: + preempt_enable_no_resched(); + + return 1; +} + +static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr) +{ + struct kprobe *cur = kprobe_running(); + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + + if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr)) + return 1; + + if (kcb->kprobe_status & KPROBE_HIT_SS) { + resume_execution(cur, regs, kcb); + regs->cp0_status |= kcb->kprobe_old_SR; + + reset_current_kprobe(); + preempt_enable_no_resched(); + } + return 0; +} + +/* + * Wrapper routine for handling exceptions. + */ +int __kprobes kprobe_exceptions_notify(struct notifier_block *self, + unsigned long val, void *data) +{ + + struct die_args *args = (struct die_args *)data; + int ret = NOTIFY_DONE; + + switch (val) { + case DIE_BREAK: + if (kprobe_handler(args->regs)) + ret = NOTIFY_STOP; + break; + case DIE_SSTEPBP: + if (post_kprobe_handler(args->regs)) + ret = NOTIFY_STOP; + break; + + case DIE_PAGE_FAULT: + /* kprobe_running() needs smp_processor_id() */ + preempt_disable(); + + if (kprobe_running() + && kprobe_fault_handler(args->regs, args->trapnr)) + ret = NOTIFY_STOP; + preempt_enable(); + break; + default: + break; + } + return ret; +} + +int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs) +{ + struct jprobe *jp = container_of(p, struct jprobe, kp); + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + + kcb->jprobe_saved_regs = *regs; + kcb->jprobe_saved_sp = regs->regs[29]; + + memcpy(kcb->jprobes_stack, (void *)kcb->jprobe_saved_sp, + MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp)); + + regs->cp0_epc = (unsigned long)(jp->entry); + + return 1; +} + +/* Defined in the inline asm below. */ +void jprobe_return_end(void); + +void __kprobes jprobe_return(void) +{ + /* Assembler quirk necessitates this '0,code' business. */ + asm volatile( + "break 0,%0\n\t" + ".globl jprobe_return_end\n" + "jprobe_return_end:\n" + : : "n" (BRK_KPROBE_BP) : "memory"); +} + +int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs) +{ + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + + if (regs->cp0_epc >= (unsigned long)jprobe_return && + regs->cp0_epc <= (unsigned long)jprobe_return_end) { + *regs = kcb->jprobe_saved_regs; + memcpy((void *)kcb->jprobe_saved_sp, kcb->jprobes_stack, + MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp)); + preempt_enable_no_resched(); + + return 1; + } + return 0; +} + +/* + * Function return probe trampoline: + * - init_kprobes() establishes a probepoint here + * - When the probed function returns, this probe causes the + * handlers to fire + */ +static void __used kretprobe_trampoline_holder(void) +{ + asm volatile( + ".set push\n\t" + /* Keep the assembler from reordering and placing JR here. */ + ".set noreorder\n\t" + "nop\n\t" + ".global kretprobe_trampoline\n" + "kretprobe_trampoline:\n\t" + "nop\n\t" + ".set pop" + : : : "memory"); +} + +void kretprobe_trampoline(void); + +void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri, + struct pt_regs *regs) +{ + ri->ret_addr = (kprobe_opcode_t *) regs->regs[31]; + + /* Replace the return addr with trampoline addr */ + regs->regs[31] = (unsigned long)kretprobe_trampoline; +} + +/* + * Called when the probe at kretprobe trampoline is hit + */ +static int __kprobes trampoline_probe_handler(struct kprobe *p, + struct pt_regs *regs) +{ + struct kretprobe_instance *ri = NULL; + struct hlist_head *head, empty_rp; + struct hlist_node *node, *tmp; + unsigned long flags, orig_ret_address = 0; + unsigned long trampoline_address = (unsigned long)kretprobe_trampoline; + + INIT_HLIST_HEAD(&empty_rp); + kretprobe_hash_lock(current, &head, &flags); + + /* + * It is possible to have multiple instances associated with a given + * task either because an multiple functions in the call path + * have a return probe installed on them, and/or more than one return + * return probe was registered for a target function. + * + * We can handle this because: + * - instances are always inserted at the head of the list + * - when multiple return probes are registered for the same + * function, the first instance's ret_addr will point to the + * real return address, and all the rest will point to + * kretprobe_trampoline + */ + hlist_for_each_entry_safe(ri, node, tmp, head, hlist) { + if (ri->task != current) + /* another task is sharing our hash bucket */ + continue; + + if (ri->rp && ri->rp->handler) + ri->rp->handler(ri, regs); + + orig_ret_address = (unsigned long)ri->ret_addr; + recycle_rp_inst(ri, &empty_rp); + + if (orig_ret_address != trampoline_address) + /* + * This is the real return address. Any other + * instances associated with this task are for + * other calls deeper on the call stack + */ + break; + } + + kretprobe_assert(ri, orig_ret_address, trampoline_address); + instruction_pointer(regs) = orig_ret_address; + + reset_current_kprobe(); + kretprobe_hash_unlock(current, &flags); + preempt_enable_no_resched(); + + hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) { + hlist_del(&ri->hlist); + kfree(ri); + } + /* + * By returning a non-zero value, we are telling + * kprobe_handler() that we don't want the post_handler + * to run (and have re-enabled preemption) + */ + return 1; +} + +int __kprobes arch_trampoline_kprobe(struct kprobe *p) +{ + if (p->addr == (kprobe_opcode_t *)kretprobe_trampoline) + return 1; + + return 0; +} + +static struct kprobe trampoline_p = { + .addr = (kprobe_opcode_t *)kretprobe_trampoline, + .pre_handler = trampoline_probe_handler +}; + +int __init arch_init_kprobes(void) +{ + return register_kprobe(&trampoline_p); +} diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 1515b67..4c6079f 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -334,7 +335,7 @@ void show_regs(struct pt_regs *regs) __show_regs((struct pt_regs *)regs); } -void show_registers(const struct pt_regs *regs) +void show_registers(struct pt_regs *regs) { const int field = 2 * sizeof(unsigned long); @@ -783,6 +784,25 @@ asmlinkage void do_bp(struct pt_regs *regs) if (bcode >= (1 << 10)) bcode >>= 10; + /* + * notify the kprobe handlers, if instruction is likely to + * pertain to them. + */ + switch (bcode) { + case BRK_KPROBE_BP: + if (notify_die(DIE_BREAK, "debug", regs, bcode, 0, 0) == NOTIFY_STOP) + return; + else + break; + case BRK_KPROBE_SSTEPBP: + if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 0, 0) == NOTIFY_STOP) + return; + else + break; + default: + break; + } + do_trap_or_bp(regs, bcode, "Break"); return; diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index b4aac42..783ad00 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -24,13 +25,14 @@ #include #include #include /* For VMALLOC_END */ +#include /* * This routine handles page faults. It determines the address, * and the problem, and then passes it off to one of the appropriate * routines. */ -asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, +asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long write, unsigned long address) { struct vm_area_struct * vma = NULL; @@ -46,6 +48,17 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, field, regs->cp0_epc); #endif +#ifdef CONFIG_KPROBES + /* + * This is to notify the fault handler of the kprobes. The + * exception code is redundant as it is also carried in REGS, + * but we pass it anyhow. + */ + if (notify_die(DIE_PAGE_FAULT, "page fault", regs, -1, + (regs->cp0_cause >> 2) & 0x1f, SIGSEGV) == NOTIFY_STOP) + return; +#endif + info.si_code = SEGV_MAPERR; /* -- 1.7.1.1 From David.Daney@caviumnetworks.com Tue Aug 3 20:23:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 20:24:04 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19479 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493175Ab0HCSWu (ORCPT ); Tue, 3 Aug 2010 20:22:50 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 11:23:16 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:47 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:47 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73IMZBm026414; Tue, 3 Aug 2010 11:22:35 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73IMYBT026413; Tue, 3 Aug 2010 11:22:34 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org, hschauhan@nulltrace.org, David Daney Subject: [PATCH 1/5] MIPS: Define regs_return_value() Date: Tue, 3 Aug 2010 11:22:18 -0700 Message-Id: <1280859742-26364-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 03 Aug 2010 18:22:47.0079 (UTC) FILETIME=[DF7B8370:01CB3338] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27547 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/include/asm/ptrace.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index cdc6a46..593b097 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -137,6 +137,7 @@ extern int ptrace_set_watch_regs(struct task_struct *child, */ #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) +#define regs_return_value(regs) ((regs)->regs[2]) #define instruction_pointer(regs) ((regs)->cp0_epc) #define profile_pc(regs) instruction_pointer(regs) -- 1.7.1.1 From David.Daney@caviumnetworks.com Tue Aug 3 20:24:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 20:24:33 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19491 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493179Ab0HCSWu (ORCPT ); Tue, 3 Aug 2010 20:22:50 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 11:23:17 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:48 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:48 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73IMiS3026430; Tue, 3 Aug 2010 11:22:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73IMhnN026429; Tue, 3 Aug 2010 11:22:43 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org, hschauhan@nulltrace.org, David Daney Subject: [PATCH 5/5] documentation: Mention that KProbes is supported on MIPS Date: Tue, 3 Aug 2010 11:22:22 -0700 Message-Id: <1280859742-26364-6-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 03 Aug 2010 18:22:48.0266 (UTC) FILETIME=[E030A2A0:01CB3338] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27548 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips MIPS now has KProbes support, so kprobes.txt should reflect it. Signed-off-by: David Daney --- Documentation/kprobes.txt | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/Documentation/kprobes.txt b/Documentation/kprobes.txt index 6653017..1762b81 100644 --- a/Documentation/kprobes.txt +++ b/Documentation/kprobes.txt @@ -285,6 +285,7 @@ architectures: - sparc64 (Return probes not yet implemented.) - arm - ppc +- mips 3. Configuring Kprobes -- 1.7.1.1 From David.Daney@caviumnetworks.com Tue Aug 3 20:24:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 20:24:57 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19507 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491992Ab0HCSWw (ORCPT ); Tue, 3 Aug 2010 20:22:52 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 11:23:17 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:48 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 11:22:48 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73IMf0o026426; Tue, 3 Aug 2010 11:22:41 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73IMfDK026425; Tue, 3 Aug 2010 11:22:41 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org, hschauhan@nulltrace.org, David Daney Subject: [PATCH 4/5] samples: kprobe_example: Make it print something on MIPS. Date: Tue, 3 Aug 2010 11:22:21 -0700 Message-Id: <1280859742-26364-5-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 03 Aug 2010 18:22:48.0266 (UTC) FILETIME=[E030A2A0:01CB3338] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27549 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This KProbes example is a little useless if it doesn't print anything. For MIPS print similar messages to those produced on x86 and PPC. Signed-off-by: David Daney --- samples/kprobes/kprobe_example.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/samples/kprobes/kprobe_example.c b/samples/kprobes/kprobe_example.c index a681998..ebf5e0c 100644 --- a/samples/kprobes/kprobe_example.c +++ b/samples/kprobes/kprobe_example.c @@ -32,6 +32,11 @@ static int handler_pre(struct kprobe *p, struct pt_regs *regs) " msr = 0x%lx\n", p->addr, regs->nip, regs->msr); #endif +#ifdef CONFIG_MIPS + printk(KERN_INFO "pre_handler: p->addr = 0x%p, epc = 0x%lx," + " status = 0x%lx\n", + p->addr, regs->cp0_epc, regs->cp0_status); +#endif /* A dump_stack() here will give a stack backtrace */ return 0; @@ -49,6 +54,10 @@ static void handler_post(struct kprobe *p, struct pt_regs *regs, printk(KERN_INFO "post_handler: p->addr = 0x%p, msr = 0x%lx\n", p->addr, regs->msr); #endif +#ifdef CONFIG_MIPS + printk(KERN_INFO "post_handler: p->addr = 0x%p, status = 0x%lx\n", + p->addr, regs->cp0_status); +#endif } /* -- 1.7.1.1 From Ryan_D_Phillips@Dell.com Tue Aug 3 21:07:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 21:07:53 +0200 (CEST) Received: from ausxipps301.us.dell.com ([143.166.148.223]:53803 "EHLO ausxipps301.us.dell.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491981Ab0HCTHp (ORCPT ); Tue, 3 Aug 2010 21:07:45 +0200 X-Loopcount0: from 10.166.72.158 From: To: Date: Tue, 3 Aug 2010 14:07:30 -0500 Subject: mips, eglibc, and toolchain compilation error Thread-Topic: mips, eglibc, and toolchain compilation error Thread-Index: AcszPx7DpCEQ+lTOTRSdAzgzAaP7/w== Message-ID: <017987BD9AB15445B9968338EC889BB107D3ECEC72@AUSX7MCPS301.AMER.DELL.COM> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: multipart/alternative; boundary="_000_017987BD9AB15445B9968338EC889BB107D3ECEC72AUSX7MCPS301A_" MIME-Version: 1.0 X-OriginalArrivalTime: 03 Aug 2010 19:07:31.0972 (UTC) FILETIME=[1FCDAC40:01CB333F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27550 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Ryan_D_Phillips@Dell.com Precedence: bulk X-list: linux-mips --_000_017987BD9AB15445B9968338EC889BB107D3ECEC72AUSX7MCPS301A_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi All, I'm trying to get openembedded to build me a 32bit MIPS toolchain using EGL= IBC. GCC 4.4.4 seems to compile ok, but when I get to eglibc 2.10 and 2.11 = the compiler spits this error: | /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/= eglibc-2.11-r11.6/build-mips-angstrom-linux/libc_pic.os: In function `_mcou= nt': | (.debug_macinfo+0x5d7a7a8): relocation truncated to fit: R_MIPS_HI16 agai= nst `_gp_disp' | collect2: ld returned 1 exit status | make[1]: *** [/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-a= ngstrom-linux/eglibc-2.11-r11.6/build-mips-angstrom-linux/libc.so] Error 1 | make[1]: Leaving directory `/home/rphillips/sdk/build-dell-tor-angstrom/t= mp/work/mips-angstrom-linux/eglibc-2.11-r11.6/eglibc-2_11/libc' | make: *** [all] Error 2 | FATAL: oe_runmake failed NOTE: Task failed: /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mip= s-angstrom-linux/eglibc-2.11-r11.6/temp/log.do_compile.10164 ERROR: TaskFailed event exception, aborting ERROR: Build of /home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/e= glibc_2.11.bb do_compile failed ERROR: Task 9 (/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eg= libc_2.11.bb, do_compile) failed NOTE: Tasks Summary: Attempted 475 tasks of which 159 didn't need to be rer= un and 1 failed. ERROR: '/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.= 11.bb' failed It appears the Debian MIPS stack uses EGLIBC and GCC 4 successfully. Does a= nyone know what the problem is, and how I can fix it? Google has been of limited use for this error. Regards, Ryan Phillips --_000_017987BD9AB15445B9968338EC889BB107D3ECEC72AUSX7MCPS301A_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi All,

 

I’m trying to get openembedded to build me a 32b= it MIPS toolchain using EGLIBC. GCC 4.4.4 seems to compile ok, but when I get = to eglibc 2.10 and 2.11 the compiler spits this error:

 

| /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work= /mips-angstrom-linux/eglibc-2.11-r11.6/build-mips-angstrom-linux/libc_pic.o= s: In function `_mcount':

| (.debug_macinfo+0x5d7a7a8): relocation truncated to = fit: R_MIPS_HI16 against `_gp_disp'

| collect2: ld returned 1 exit status

| make[1]: *** [/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/e= glibc-2.11-r11.6/build-mips-angstrom-linux/libc.so] Error 1

| make[1]: Leaving directory `/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/e= glibc-2.11-r11.6/eglibc-2_11/libc'

| make: *** [all] Error 2

| FATAL: oe_runmake failed

NOTE: Task failed: /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eg= libc-2.11-r11.6/temp/log.do_compile.10164

ERROR: TaskFailed event exception, aborting=

ERROR: Build of /home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb do_compile failed

ERROR: Task 9 (/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb, do_compile) failed

NOTE: Tasks Summary: Attempted 475 tasks of which 159 = didn't need to be rerun and 1 failed.

ERROR: '/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb' failed

 

It appears the Debian MIPS stack uses EGLIBC and GCC 4 successfully. Does anyone know what the problem is, and how I can fix it? <= o:p>

 

Google has been of limited use for this error.

 

Regards,

Ryan Phillips

 

--_000_017987BD9AB15445B9968338EC889BB107D3ECEC72AUSX7MCPS301A_-- From David.Daney@caviumnetworks.com Tue Aug 3 21:14:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 21:14:33 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1917 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493163Ab0HCTOa (ORCPT ); Tue, 3 Aug 2010 21:14:30 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 12:14:57 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 12:14:28 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 12:14:28 -0700 Message-ID: <4C586A94.2030409@caviumnetworks.com> Date: Tue, 03 Aug 2010 12:14:28 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Ryan_D_Phillips@Dell.com CC: linux-mips@linux-mips.org Subject: Re: mips, eglibc, and toolchain compilation error References: <017987BD9AB15445B9968338EC889BB107D3ECEC72@AUSX7MCPS301.AMER.DELL.COM> In-Reply-To: <017987BD9AB15445B9968338EC889BB107D3ECEC72@AUSX7MCPS301.AMER.DELL.COM> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Aug 2010 19:14:28.0708 (UTC) FILETIME=[18328A40:01CB3340] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27551 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Which version of Binutils? If it is up to date, I don't know what the problem is. You would have to look at the exact commands being passed to the linker as well as look at the objects involved. David Daney On 08/03/2010 12:07 PM, Ryan_D_Phillips@Dell.com wrote: > Hi All, > > I'm trying to get openembedded to build me a 32bit MIPS toolchain using EGLIBC. GCC 4.4.4 seems to compile ok, but when I get to eglibc 2.10 and 2.11 the compiler spits this error: > > | /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/build-mips-angstrom-linux/libc_pic.os: In function `_mcount': > | (.debug_macinfo+0x5d7a7a8): relocation truncated to fit: R_MIPS_HI16 against `_gp_disp' > | collect2: ld returned 1 exit status > | make[1]: *** [/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/build-mips-angstrom-linux/libc.so] Error 1 > | make[1]: Leaving directory `/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/eglibc-2_11/libc' > | make: *** [all] Error 2 > | FATAL: oe_runmake failed > NOTE: Task failed: /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/temp/log.do_compile.10164 > ERROR: TaskFailed event exception, aborting > ERROR: Build of /home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb do_compile failed > ERROR: Task 9 (/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb, do_compile) failed > NOTE: Tasks Summary: Attempted 475 tasks of which 159 didn't need to be rerun and 1 failed. > ERROR: '/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb' failed > > It appears the Debian MIPS stack uses EGLIBC and GCC 4 successfully. Does anyone know what the problem is, and how I can fix it? > > Google has been of limited use for this error. > > Regards, > Ryan Phillips > > From janr@adax.com Tue Aug 3 22:11:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 22:11:28 +0200 (CEST) Received: from mail1.adax.com ([208.201.231.104]:23307 "EHLO mail1.adax.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492081Ab0HCULX (ORCPT ); Tue, 3 Aug 2010 22:11:23 +0200 Received: from static-151-204-189-187.pskn.east.verizon.net (static-151-204-189-187.pskn.east.verizon.net [151.204.189.187]) by mail1.adax.com (Postfix) with ESMTP id 81F70120C48; Tue, 3 Aug 2010 13:11:12 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by static-151-204-189-187.pskn.east.verizon.net (Postfix) with ESMTP id B48D5201EA; Tue, 3 Aug 2010 16:11:11 -0400 (EDT) X-Virus-Scanned: Debian amavisd-new at static-151-204-189-187.pskn.east.verizon.net Received: from static-151-204-189-187.pskn.east.verizon.net ([127.0.0.1]) by localhost (static-151-204-189-187.pskn.east.verizon.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4kR5oRwNlE2G; Tue, 3 Aug 2010 16:11:06 -0400 (EDT) Received: from [192.168.1.76] (jr001327.mtl-nj.adax [192.168.1.76]) by static-151-204-189-187.pskn.east.verizon.net (Postfix) with ESMTPS id 45613201DD; Tue, 3 Aug 2010 16:11:06 -0400 (EDT) Message-ID: <4C5877F1.2010004@adax.com> Date: Tue, 03 Aug 2010 16:11:29 -0400 From: Jan Rovins Organization: Adax Inc. User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 To: David Daney CC: Ryan_D_Phillips@Dell.com, linux-mips@linux-mips.org Subject: Re: mips, eglibc, and toolchain compilation error References: <017987BD9AB15445B9968338EC889BB107D3ECEC72@AUSX7MCPS301.AMER.DELL.COM> <4C586A94.2030409@caviumnetworks.com> In-Reply-To: <4C586A94.2030409@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27552 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: janr@adax.com Precedence: bulk X-list: linux-mips Looks like a similar problim is documented here: http://www.mail-archive.com/openembedded-devel@lists.openembedded.org/msg00090.html (their solution was to rebuild GCC without the -fno-omit-frame-pointer option) Jan David Daney wrote: > Which version of Binutils? > > If it is up to date, I don't know what the problem is. > > You would have to look at the exact commands being passed to the > linker as well as look at the objects involved. > > David Daney > > > On 08/03/2010 12:07 PM, Ryan_D_Phillips@Dell.com wrote: >> Hi All, >> >> I'm trying to get openembedded to build me a 32bit MIPS toolchain >> using EGLIBC. GCC 4.4.4 seems to compile ok, but when I get to eglibc >> 2.10 and 2.11 the compiler spits this error: >> >> | >> /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/build-mips-angstrom-linux/libc_pic.os: >> In function `_mcount': >> | (.debug_macinfo+0x5d7a7a8): relocation truncated to fit: >> R_MIPS_HI16 against `_gp_disp' >> | collect2: ld returned 1 exit status >> | make[1]: *** >> [/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/build-mips-angstrom-linux/libc.so] >> Error 1 >> | make[1]: Leaving directory >> `/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/eglibc-2_11/libc' >> >> | make: *** [all] Error 2 >> | FATAL: oe_runmake failed >> NOTE: Task failed: >> /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/temp/log.do_compile.10164 >> >> ERROR: TaskFailed event exception, aborting >> ERROR: Build of >> /home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb >> do_compile failed >> ERROR: Task 9 >> (/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb, >> do_compile) failed >> NOTE: Tasks Summary: Attempted 475 tasks of which 159 didn't need to >> be rerun and 1 failed. >> ERROR: >> '/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb' >> failed >> >> It appears the Debian MIPS stack uses EGLIBC and GCC 4 successfully. >> Does anyone know what the problem is, and how I can fix it? >> >> Google has been of limited use for this error. >> >> Regards, >> Ryan Phillips >> >> > From Ryan_D_Phillips@Dell.com Tue Aug 3 22:19:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 22:19:33 +0200 (CEST) Received: from ausc60ps301.us.dell.com ([143.166.148.206]:50123 "EHLO ausc60ps301.us.dell.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493173Ab0HCUT3 convert rfc822-to-8bit (ORCPT ); Tue, 3 Aug 2010 22:19:29 +0200 X-Loopcount0: from 10.166.62.177 From: To: , CC: Date: Tue, 3 Aug 2010 15:18:17 -0500 Subject: RE: mips, eglibc, and toolchain compilation error Thread-Topic: mips, eglibc, and toolchain compilation error Thread-Index: AcszSAn9YEyRd+ehQHuFjivxFSyQugAANuyQ Message-ID: <017987BD9AB15445B9968338EC889BB107D3ECEE33@AUSX7MCPS301.AMER.DELL.COM> References: <017987BD9AB15445B9968338EC889BB107D3ECEC72@AUSX7MCPS301.AMER.DELL.COM> <4C586A94.2030409@caviumnetworks.com> <4C5877F1.2010004@adax.com> In-Reply-To: <4C5877F1.2010004@adax.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginalArrivalTime: 03 Aug 2010 20:18:19.0383 (UTC) FILETIME=[03752870:01CB3349] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27553 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Ryan_D_Phillips@Dell.com Precedence: bulk X-list: linux-mips Thanks Jan. I will try this. David: For reference the binutils version is 2.20.1. Regards, Ryan -----Original Message----- From: Jan Rovins [mailto:janr@adax.com] Sent: Tuesday, August 03, 2010 3:11 PM To: David Daney Cc: Phillips, Ryan D; linux-mips@linux-mips.org Subject: Re: mips, eglibc, and toolchain compilation error Looks like a similar problim is documented here: http://www.mail-archive.com/openembedded-devel@lists.openembedded.org/msg00090.html (their solution was to rebuild GCC without the -fno-omit-frame-pointer option) Jan David Daney wrote: > Which version of Binutils? > > If it is up to date, I don't know what the problem is. > > You would have to look at the exact commands being passed to the > linker as well as look at the objects involved. > > David Daney > > > On 08/03/2010 12:07 PM, Ryan_D_Phillips@Dell.com wrote: >> Hi All, >> >> I'm trying to get openembedded to build me a 32bit MIPS toolchain >> using EGLIBC. GCC 4.4.4 seems to compile ok, but when I get to eglibc >> 2.10 and 2.11 the compiler spits this error: >> >> | >> /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/build-mips-angstrom-linux/libc_pic.os: >> In function `_mcount': >> | (.debug_macinfo+0x5d7a7a8): relocation truncated to fit: >> R_MIPS_HI16 against `_gp_disp' >> | collect2: ld returned 1 exit status >> | make[1]: *** >> [/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/build-mips-angstrom-linux/libc.so] >> Error 1 >> | make[1]: Leaving directory >> `/home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/eglibc-2_11/libc' >> >> | make: *** [all] Error 2 >> | FATAL: oe_runmake failed >> NOTE: Task failed: >> /home/rphillips/sdk/build-dell-tor-angstrom/tmp/work/mips-angstrom-linux/eglibc-2.11-r11.6/temp/log.do_compile.10164 >> >> ERROR: TaskFailed event exception, aborting >> ERROR: Build of >> /home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb >> do_compile failed >> ERROR: Task 9 >> (/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb, >> do_compile) failed >> NOTE: Tasks Summary: Attempted 475 tasks of which 159 didn't need to >> be rerun and 1 failed. >> ERROR: >> '/home/rphillips/work/mips/sdk/openembedded/recipes/eglibc/eglibc_2.11.bb' >> failed >> >> It appears the Debian MIPS stack uses EGLIBC and GCC 4 successfully. >> Does anyone know what the problem is, and how I can fix it? >> >> Google has been of limited use for this error. >> >> Regards, >> Ryan Phillips >> >> > From ralf@linux-mips.org Tue Aug 3 22:26:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 22:26:39 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52592 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492865Ab0HCU0c (ORCPT ); Tue, 3 Aug 2010 22:26:32 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o73KQAVU025648; Tue, 3 Aug 2010 21:26:10 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o73KQ8hH025646; Tue, 3 Aug 2010 21:26:08 +0100 Date: Tue, 3 Aug 2010 21:26:07 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH 1/5] MIPS: Define regs_return_value() Message-ID: <20100803202607.GA25233@linux-mips.org> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> <1280859742-26364-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280859742-26364-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27554 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Aug 03, 2010 at 11:22:18AM -0700, David Daney wrote: > +#define regs_return_value(regs) ((regs)->regs[2]) This will probably only work if the argument happens to be "regs" otherwise the things will likely go splat. Ralf From David.Daney@caviumnetworks.com Tue Aug 3 22:53:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 22:53:46 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4306 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492858Ab0HCUxi (ORCPT ); Tue, 3 Aug 2010 22:53:38 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 13:54:02 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 13:53:33 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 13:53:33 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73KrU1W002627; Tue, 3 Aug 2010 13:53:30 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73KrRTX002626; Tue, 3 Aug 2010 13:53:27 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org, hschauhan@nulltrace.org, David Daney Subject: [PATCH] MIPS: Define regs_return_value() Date: Tue, 3 Aug 2010 13:53:24 -0700 Message-Id: <1280868804-2595-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <20100803202607.GA25233@linux-mips.org> References: <20100803202607.GA25233@linux-mips.org> X-OriginalArrivalTime: 03 Aug 2010 20:53:33.0512 (UTC) FILETIME=[EF93A480:01CB334D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27555 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- Use this version instead of the original 1/5 arch/mips/include/asm/ptrace.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index cdc6a46..9f1b8db 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -137,6 +137,7 @@ extern int ptrace_set_watch_regs(struct task_struct *child, */ #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) +#define regs_return_value(_regs) ((_regs)->regs[2]) #define instruction_pointer(regs) ((regs)->cp0_epc) #define profile_pc(regs) instruction_pointer(regs) -- 1.7.1.1 From macro@linux-mips.org Tue Aug 3 22:54:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 22:54:43 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:44702 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492840Ab0HCUyj (ORCPT ); Tue, 3 Aug 2010 22:54:39 +0200 Date: Tue, 3 Aug 2010 21:54:39 +0100 (BST) From: "Maciej W. Rozycki" To: David Daney cc: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH 2/5] MIPS: Add instrunction format for BREAK and SYSCALL In-Reply-To: <1280859742-26364-3-git-send-email-ddaney@caviumnetworks.com> Message-ID: References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> <1280859742-26364-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27556 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, 3 Aug 2010, David Daney wrote: > diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h > index 6489f00..444ff71 100644 > --- a/arch/mips/include/asm/inst.h > +++ b/arch/mips/include/asm/inst.h > @@ -247,6 +247,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */ > unsigned int fmt : 2; > }; > > +struct b_format { /* BREAK and SYSCALL */ > + unsigned int opcode:6; > + unsigned int code:20; > + unsigned int func:6; > +}; > + > #elif defined(__MIPSEL__) > > struct j_format { /* Jump format */ Please note the code field of the BREAK instruction is by toolchain convention (bug-compatibility with the original MIPS assembler or suchlike) treated as a pair of swapped 10-bit fields -- you may want to double-check consistency of interpretation with usage elsewhere. Maciej From David.Daney@caviumnetworks.com Tue Aug 3 22:59:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 22:59:50 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4441 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493182Ab0HCU7p (ORCPT ); Tue, 3 Aug 2010 22:59:45 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 14:00:12 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 13:59:43 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 13:59:43 -0700 Message-ID: <4C58833F.1080409@caviumnetworks.com> Date: Tue, 03 Aug 2010 13:59:43 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH 2/5] MIPS: Add instrunction format for BREAK and SYSCALL References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> <1280859742-26364-3-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Aug 2010 20:59:43.0827 (UTC) FILETIME=[CC4D3A30:01CB334E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27557 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 08/03/2010 01:54 PM, Maciej W. Rozycki wrote: > On Tue, 3 Aug 2010, David Daney wrote: > >> diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h >> index 6489f00..444ff71 100644 >> --- a/arch/mips/include/asm/inst.h >> +++ b/arch/mips/include/asm/inst.h >> @@ -247,6 +247,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */ >> unsigned int fmt : 2; >> }; >> >> +struct b_format { /* BREAK and SYSCALL */ >> + unsigned int opcode:6; >> + unsigned int code:20; >> + unsigned int func:6; >> +}; >> + >> #elif defined(__MIPSEL__) >> >> struct j_format { /* Jump format */ > > Please note the code field of the BREAK instruction is by toolchain > convention (bug-compatibility with the original MIPS assembler or > suchlike) treated as a pair of swapped 10-bit fields -- you may want to > double-check consistency of interpretation with usage elsewhere. > Indeed, I am familiar with that fact. From patch 3/5 we have: . . . +void __kprobes jprobe_return(void) +{ + /* Assembler quirk necessitates this '0,code' business. */ + asm volatile( + "break 0,%0\n\t" + ".globl jprobe_return_end\n" + "jprobe_return_end:\n" + : : "n" (BRK_KPROBE_BP) : "memory"); +} . . . The 'break 0,code' construct causes gas to emit values that are compatible with the other use of struct b_format in the patch set. David Daney From David.Daney@caviumnetworks.com Tue Aug 3 23:00:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 23:01:01 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4463 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492865Ab0HCVAx (ORCPT ); Tue, 3 Aug 2010 23:00:53 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 14:01:21 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 14:00:52 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 14:00:51 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73L0lIP002819; Tue, 3 Aug 2010 14:00:47 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73L0lhk002818; Tue, 3 Aug 2010 14:00:47 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org, hschauhan@nulltrace.org, David Daney Subject: [PATCH] MIPS: KProbes: Use flush_insn_slot() where possible. Date: Tue, 3 Aug 2010 14:00:45 -0700 Message-Id: <1280869245-2786-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1280859742-26364-4-git-send-email-ddaney@caviumnetworks.com> References: <1280859742-26364-4-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 03 Aug 2010 21:00:51.0999 (UTC) FILETIME=[F4EF72F0:01CB334E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27558 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- This is a small cleanup that could either be folded into the original 3/5 or applied in addition to it. arch/mips/include/asm/kprobes.h | 1 + arch/mips/kernel/kprobes.c | 11 +++-------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h index fe58e08..e6ea4d4 100644 --- a/arch/mips/include/asm/kprobes.h +++ b/arch/mips/include/asm/kprobes.h @@ -25,6 +25,7 @@ #include #include +#include #include #include diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index a74ccd2..ee28683 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -28,7 +28,6 @@ #include #include -#include #include #include #include @@ -151,18 +150,14 @@ out: void __kprobes arch_arm_kprobe(struct kprobe *p) { - *(p->addr) = breakpoint_insn; - flush_icache_range((unsigned long)p->addr, - (unsigned long)p->addr + - (MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); + *p->addr = breakpoint_insn; + flush_insn_slot(p); } void __kprobes arch_disarm_kprobe(struct kprobe *p) { *p->addr = p->opcode; - flush_icache_range((unsigned long)p->addr, - (unsigned long)p->addr + - (MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); + flush_insn_slot(p); } void __kprobes arch_remove_kprobe(struct kprobe *p) -- 1.7.1.1 From David.Daney@caviumnetworks.com Tue Aug 3 23:57:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2010 23:57:53 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5589 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492182Ab0HCV5s (ORCPT ); Tue, 3 Aug 2010 23:57:48 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 14:58:14 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 14:57:45 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 14:57:45 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73Lvg6L027414; Tue, 3 Aug 2010 14:57:42 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73LveMZ027413; Tue, 3 Aug 2010 14:57:40 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Remove unused task_struct.trap_no field. Date: Tue, 3 Aug 2010 14:57:39 -0700 Message-Id: <1280872659-27372-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 X-OriginalArrivalTime: 03 Aug 2010 21:57:45.0380 (UTC) FILETIME=[E7780E40:01CB3356] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27559 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips It is initialized to zero and only ever read. Remove it, and pass zero in its place. Signed-off-by: David Daney --- arch/mips/include/asm/processor.h | 2 -- arch/mips/kernel/asm-offsets.c | 1 - arch/mips/kernel/traps.c | 2 +- 3 files changed, 1 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 24d91f8..0d629bb 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -229,7 +229,6 @@ struct thread_struct { unsigned long cp0_badvaddr; /* Last user fault */ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; - unsigned long trap_no; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; #ifdef CONFIG_CPU_CAVIUM_OCTEON @@ -301,7 +300,6 @@ struct thread_struct { .cp0_badvaddr = 0, \ .cp0_baduaddr = 0, \ .error_code = 0, \ - .trap_no = 0, \ .irix_trampoline = 0, \ .irix_oldctx = 0, \ /* \ diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index ca6c832..6b30fb2 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -126,7 +126,6 @@ void output_thread_defines(void) thread.cp0_baduaddr); OFFSET(THREAD_ECODE, task_struct, \ thread.error_code); - OFFSET(THREAD_TRAPNO, task_struct, thread.trap_no); OFFSET(THREAD_TRAMP, task_struct, \ thread.irix_trampoline); OFFSET(THREAD_OLDCTX, task_struct, \ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index fb6e93b..9d71774 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -388,7 +388,7 @@ void __noreturn die(const char * str, struct pt_regs * regs) mips_mt_regdump(dvpret); #endif /* CONFIG_MIPS_MT_SMTC */ - if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_no, SIGSEGV) == NOTIFY_STOP) + if (notify_die(DIE_OOPS, str, regs, 0, 0, SIGSEGV) == NOTIFY_STOP) sig = 0; printk("%s[#%d]:\n", str, ++die_counter); -- 1.7.1.1 From David.Daney@caviumnetworks.com Wed Aug 4 00:44:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Aug 2010 00:44:54 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:6367 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492872Ab0HCWou (ORCPT ); Wed, 4 Aug 2010 00:44:50 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 03 Aug 2010 15:45:16 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 15:44:47 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 3 Aug 2010 15:44:47 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o73MijwL018582; Tue, 3 Aug 2010 15:44:45 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o73MiiFp018581; Tue, 3 Aug 2010 15:44:44 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Clean up notify_die() usage. Date: Tue, 3 Aug 2010 15:44:43 -0700 Message-Id: <1280875483-18540-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 X-OriginalArrivalTime: 03 Aug 2010 22:44:47.0664 (UTC) FILETIME=[79AE6B00:01CB335D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27560 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The sixth argument of notify_die() is a signal number, the fifth is a trap number. Instead of passing a signal number in a randomly selected argument, pass it in the sixth. Extract the exception code from regs and pass that as the trap number. Get rid of redundant cast, and remove some gratuitous spaces. Nobody actually does anything with the signal number or trap number, but we might as well populate them with sensible values. Signed-off-by: David Daney --- arch/mips/kernel/traps.c | 25 +++++++++++++++---------- 1 files changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 9d71774..62a53c7 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -369,9 +369,14 @@ void show_registers(struct pt_regs *regs) printk("\n"); } +static int regs_to_trapnr(struct pt_regs *regs) +{ + return (regs->cp0_cause >> 2) & 0x1f; +} + static DEFINE_SPINLOCK(die_lock); -void __noreturn die(const char * str, struct pt_regs * regs) +void __noreturn die(const char *str, struct pt_regs *regs) { static int die_counter; int sig = SIGSEGV; @@ -379,7 +384,7 @@ void __noreturn die(const char * str, struct pt_regs * regs) unsigned long dvpret = dvpe(); #endif /* CONFIG_MIPS_MT_SMTC */ - notify_die(DIE_OOPS, str, (struct pt_regs *)regs, SIGSEGV, 0, 0); + notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV); console_verbose(); spin_lock_irq(&die_lock); @@ -388,7 +393,7 @@ void __noreturn die(const char * str, struct pt_regs * regs) mips_mt_regdump(dvpret); #endif /* CONFIG_MIPS_MT_SMTC */ - if (notify_die(DIE_OOPS, str, regs, 0, 0, SIGSEGV) == NOTIFY_STOP) + if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) sig = 0; printk("%s[#%d]:\n", str, ++die_counter); @@ -462,7 +467,7 @@ asmlinkage void do_be(struct pt_regs *regs) printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", data ? "Data" : "Instruction", field, regs->cp0_epc, field, regs->regs[31]); - if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) + if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) == NOTIFY_STOP) return; @@ -690,7 +695,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) { siginfo_t info; - if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) + if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) == NOTIFY_STOP) return; die_if_kernel("FP exception in kernel code", regs); @@ -753,11 +758,11 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, char b[40]; #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP - if (kgdb_ll_trap(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) + if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) return; #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ - if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) + if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) return; /* @@ -829,12 +834,12 @@ asmlinkage void do_bp(struct pt_regs *regs) */ switch (bcode) { case BRK_KPROBE_BP: - if (notify_die(DIE_BREAK, "debug", regs, bcode, 0, 0) == NOTIFY_STOP) + if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) return; else break; case BRK_KPROBE_SSTEPBP: - if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 0, 0) == NOTIFY_STOP) + if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) return; else break; @@ -874,7 +879,7 @@ asmlinkage void do_ri(struct pt_regs *regs) unsigned int opcode = 0; int status = -1; - if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) + if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) == NOTIFY_STOP) return; -- 1.7.1.1 From ananth@in.ibm.com Wed Aug 4 06:43:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Aug 2010 06:43:59 +0200 (CEST) Received: from e4.ny.us.ibm.com ([32.97.182.144]:59918 "EHLO e4.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493202Ab0HDEny (ORCPT ); Wed, 4 Aug 2010 06:43:54 +0200 Received: from d01relay07.pok.ibm.com (d01relay07.pok.ibm.com [9.56.227.147]) by e4.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id o744TOhJ025492; Wed, 4 Aug 2010 00:29:24 -0400 Received: from d01av02.pok.ibm.com (d01av02.pok.ibm.com [9.56.224.216]) by d01relay07.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id o744hkNX2175110; Wed, 4 Aug 2010 00:43:46 -0400 Received: from d01av02.pok.ibm.com (loopback [127.0.0.1]) by d01av02.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id o744hhXP027833; Wed, 4 Aug 2010 01:43:46 -0300 Received: from thinktux.in.ibm.com ([9.124.46.166]) by d01av02.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id o744hgNi027764; Wed, 4 Aug 2010 01:43:43 -0300 Received: by thinktux.in.ibm.com (Postfix, from userid 500) id F38C9C33AC; Wed, 4 Aug 2010 10:13:35 +0530 (IST) Date: Wed, 4 Aug 2010 10:13:35 +0530 From: Ananth N Mavinakayanahalli To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH 0/5] KProbes support for MIPS Message-ID: <20100804044335.GA23536@in.ibm.com> Reply-To: ananth@in.ibm.com References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27561 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ananth@in.ibm.com Precedence: bulk X-list: linux-mips On Tue, Aug 03, 2010 at 11:22:17AM -0700, David Daney wrote: > This patch set adds KProbs, JProbs and KRetProbes support for the MIPS > archetecture. > > It was tested on a 64-bit big-endian kernel (Octeon), but should work > equally well on 32-bit and little-endian as well. > > As you can see from the patches it is partially based on previous work > by Sony and Himanshu Chauhan. > > David Daney (5): > MIPS: Define regs_return_value() > MIPS: Add instrunction format for BREAK and SYSCALL > MIPS: Add KProbe support. > samples: kprobe_example: Make it print something on MIPS. > documentation: Mention that KProbes is supported on MIPS David, Thanks for the port! I do not know enough about MIPS internals to be able to review the arcane architecture specific details in the implementation. It would help if you add yourself to the MAINTAINERS list for the MIPS port. If people hit an issue, they'll know to cc you. Ananth From dengcheng.zhu@gmail.com Wed Aug 4 09:02:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Aug 2010 09:02:06 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:59088 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491077Ab0HDHCD (ORCPT ); Wed, 4 Aug 2010 09:02:03 +0200 Received: by eyd10 with SMTP id 10so2157324eyd.36 for ; Wed, 04 Aug 2010 00:02:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=uWhoO6JscEUxA34AtG5sacAEYm2IL37D9yq0zGRAhX0=; b=SnCiW0A089C1N1CjGghOoWmjJmhO+pRMAlZw1bFNoHEVGLEli7zV+R8fY7trI5mYQv cvICSDsInuNN++MnOc9LvFS/ht8n1oH2WrA/mM/qSFZ9uLu8Ivc5L9Z5ZDcdEiKw9ZU8 wERHy+QjL//2lWdPX9eZkHYNlqFLKKPu+8LmA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=jVPTkxS0Ip5w60mi9NTWAOBi5nwy4GiT1YcPt4Mgmhib+iKkg7wmBfnwtcEawTkumU MvkX81Yop7XesPpdfJ5G23eh3X6YTmCGjpa/v1oggARl0CTR+7O5tCANW9aLIBRd4vfH tc7ZBXOWVirC16iTuZzVyEmk2CQ7oKrckxGxg= MIME-Version: 1.0 Received: by 10.213.48.131 with SMTP id r3mr6266498ebf.69.1280905321100; Wed, 04 Aug 2010 00:02:01 -0700 (PDT) Received: by 10.14.127.13 with HTTP; Wed, 4 Aug 2010 00:02:01 -0700 (PDT) Date: Wed, 4 Aug 2010 15:02:01 +0800 Message-ID: Subject: [Q] enabling FPU for vpe1 From: Deng-Cheng Zhu To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27562 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Hi, I'm working on a 34Kf CPU. I understand that only one TC can use the FPU at any given time. My question is: If a TC is attached to the 2nd VPE (i.e. VPE1), can I enable FPU for it? I experimented on this, but failed to do it. Am I missing something? Thanks Deng-Cheng From kevink@paralogos.com Wed Aug 4 10:09:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Aug 2010 10:09:22 +0200 (CEST) Received: from gateway09.websitewelcome.com ([69.93.243.4]:39451 "HELO gateway09.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492887Ab0HDIJR (ORCPT ); Wed, 4 Aug 2010 10:09:17 +0200 Received: (qmail 16589 invoked from network); 4 Aug 2010 08:17:25 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway09.websitewelcome.com with SMTP; 4 Aug 2010 08:17:25 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding; b=C0iklcMrKFFQnDLzIkSVf8c1xyL63Gk62KhDUGRNEFhvr18bemBb8EHWyHd5pCu3qBrSTKquj/Orikc1ciJHU3ZNxNX2b4FWSj+RUj8UDnzIHOgiszIqCfopAzTggisg; Received: from c-98-207-157-135.hsd1.ca.comcast.net ([98.207.157.135]:1576 helo=[127.0.0.1]) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1OgZ2A-00067a-Oi; Wed, 04 Aug 2010 03:09:07 -0500 Message-ID: <4C592027.8010902@paralogos.com> Date: Wed, 04 Aug 2010 01:09:11 -0700 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 To: Deng-Cheng Zhu CC: linux-mips@linux-mips.org Subject: Re: [Q] enabling FPU for vpe1 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27563 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Check the MIPS MT spec. If I recall correctly, it's possible to enable access to the FPU by either VPE by setting the right bits while the processor is in the MT configuration mode. Deng-Cheng Zhu wrote: > Hi, > > > I'm working on a 34Kf CPU. I understand that only one TC can use the > FPU at any given time. > > My question is: If a TC is attached to the 2nd VPE (i.e. VPE1), can I > enable FPU for it? > > I experimented on this, but failed to do it. Am I missing something? > > > Thanks > > Deng-Cheng > > From dengcheng.zhu@gmail.com Wed Aug 4 12:14:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Aug 2010 12:14:31 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:48187 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491818Ab0HDKO1 convert rfc822-to-8bit (ORCPT ); Wed, 4 Aug 2010 12:14:27 +0200 Received: by eyd10 with SMTP id 10so2196927eyd.36 for ; Wed, 04 Aug 2010 03:14:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=c9nl+vBptVSKMPqPFRNSq3aMcr9lTCzwHdQnlkXDU6g=; b=jzr2UANF4/r6Wg7/xFEaVyvQe1GPwcCth0TVmzzACaG1jzLE3J+9ELqaku/p/sEJOp th5nALQfh0D5wMfjSIf96be6e5iZ1QEqwmpQiGDHv4SpQy6YLDgZaMmK8eP6Cu2uxYRM Kws58IZqacGHhlSVqcaSyhiEOcrWfx5bCgOXk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=imZOcxLyoj36QFQhJmXQPikosyioEHRylYLfHo91k25M0bHAshXzXlyK/E1r71ce9X uTogwz5M177acFKVixdVSAEoQXe5pOJFkZYKigPMf8B3a/T7b8hKbKBZJ0BKtuwEqnJb hKvKRGjUgCbm2wCODWkz/2CBP3OpY7wly7UxI= MIME-Version: 1.0 Received: by 10.213.105.207 with SMTP id u15mr6475266ebo.83.1280916867345; Wed, 04 Aug 2010 03:14:27 -0700 (PDT) Received: by 10.14.127.13 with HTTP; Wed, 4 Aug 2010 03:14:27 -0700 (PDT) In-Reply-To: <4C592027.8010902@paralogos.com> References: <4C592027.8010902@paralogos.com> Date: Wed, 4 Aug 2010 18:14:27 +0800 Message-ID: Subject: Re: [Q] enabling FPU for vpe1 From: Deng-Cheng Zhu To: "Kevin D. Kissell" Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27564 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Thanks for looking into this. I did do that. But the CU1 bit of TC#1 (in VPE#1) can not be set by TC#0 or itself. Looks like VPE#1 is not seeing the FPU at all... Deng-Cheng 2010/8/4 Kevin D. Kissell : > Check the MIPS MT spec.  If I recall correctly, it's possible to enable > access to the FPU by either VPE by setting the right bits while the > processor is in the MT configuration mode. > > Deng-Cheng Zhu wrote: >> Hi, >> >> >> I'm working on a 34Kf CPU. I understand that only one TC can use the >> FPU at any given time. >> >> My question is: If a TC is attached to the 2nd VPE (i.e. VPE1), can I >> enable FPU for it? >> >> I experimented on this, but failed to do it. Am I missing something? >> >> >> Thanks >> >> Deng-Cheng >> >> > > From ralf@linux-mips.org Wed Aug 4 16:04:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Aug 2010 16:04:34 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51919 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491102Ab0HDOEa (ORCPT ); Wed, 4 Aug 2010 16:04:30 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o74E4TnF026002 for ; Wed, 4 Aug 2010 15:04:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o74E4TCd026000 for linux-mips@linux-mips.org; Wed, 4 Aug 2010 15:04:29 +0100 Resent-From: ralf@linux-mips.org Resent-Date: Wed, 4 Aug 2010 15:04:29 +0100 Resent-Message-ID: <20100804140429.GB21004@linux-mips.org> Resent-To: linux-mips@linux-mips.org Received: from vger.kernel.org ([209.132.180.67]:48190 "EHLO vger.kernel.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493090Ab0HCHeV (ORCPT ); Tue, 3 Aug 2010 09:34:21 +0200 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752000Ab0HCHeJ (ORCPT + 1 other); Tue, 3 Aug 2010 03:34:09 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:42036 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751074Ab0HCHeG (ORCPT ); Tue, 3 Aug 2010 03:34:06 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o737XRti026925 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 3 Aug 2010 02:33:30 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o737XQNY004485; Tue, 3 Aug 2010 13:03:26 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde70.ent.ti.com ([172.24.170.148]) with mapi; Tue, 3 Aug 2010 13:03:26 +0530 From: "Shilimkar, Santosh" To: Andrew Morton CC: Kevin Cernekee , "linux-kernel@vger.kernel.org" , Russell King - ARM Linux Date: Tue, 3 Aug 2010 13:03:25 +0530 Subject: RE: Additional fix : (was [v2]printk: fix delayed messages from CPU hotplug events) Thread-Topic: Additional fix : (was [v2]printk: fix delayed messages from CPU hotplug events) Thread-Index: AcsylFIglA7ghRZ+SOeN2I36O9G8vQANWtcA Message-ID: References: <20100802154434.5615bcf9.akpm@linux-foundation.org> In-Reply-To: <20100802154434.5615bcf9.akpm@linux-foundation.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: multipart/mixed; boundary="_002_EAF47CD23C76F840A9E7FCE10091EFAB02C641D8ECdbde02enttico_" MIME-Version: 1.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27565 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips --_002_EAF47CD23C76F840A9E7FCE10091EFAB02C641D8ECdbde02enttico_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Andrew for looking into this. > -----Original Message----- > From: Andrew Morton [mailto:akpm@linux-foundation.org] > Sent: Tuesday, August 03, 2010 4:15 AM > To: Shilimkar, Santosh > Cc: Kevin Cernekee; linux-kernel@vger.kernel.org; Russell King - ARM Linu= x > Subject: Re: Additional fix : (was [v2]printk: fix delayed messages from > CPU hotplug events) >=20 > On Tue, 29 Jun 2010 14:22:26 +0530 > "Shilimkar, Santosh" wrote: >=20 > > Hi, > > > > I have faced similar issue as what is being described in below with > > latest kernel. > > > > ------------------------------------------------ > > https://patchwork.kernel.org/patch/103347/ > > > > When a secondary CPU is being brought up, it is not uncommon for > > printk() to be invoked when cpu_online(smp_processor_id()) =3D=3D 0. T= he > > case that I witnessed personally was on MIPS: > > > > http://lkml.org/lkml/2010/5/30/4 > > > > If (can_use_console() =3D=3D 0), printk() will spool its output to log_= buf > > and it will be visible in "dmesg", but that output will NOT be echoed t= o > > the console until somebody calls release_console_sem() from a CPU that > > is online. Therefore, the boot time messages from the new CPU can get > > stuck in "limbo" for a long time, and might suddenly appear on the > > screen when a completely unrelated event (e.g. "eth0: link is down") > > occurs. > > > > This patch modifies the console code so that any pending messages are > > automatically flushed out to the console whenever a CPU hotplug > > operation completes successfully or aborts. > > > > ----------------------------------------------- > > > > Above patch fixes only half of the problem. I mean the cpu online > > path prints are coming on the console. > > > > But similar problem also exist if there are prints in the cpu offline > > path. I got that fixed by adding below patch on top of you patch. > > > > diff --git a/kernel/printk.c b/kernel/printk.c > > index d370b74..f4d7352 100644 > > --- a/kernel/printk.c > > +++ b/kernel/printk.c > > @@ -982,6 +982,9 @@ static int __cpuinit console_cpu_notify(struct > notifier_bloc > > switch (action) { > > case CPU_ONLINE: > > case CPU_UP_CANCELED: > > + case CPU_DEAD: > > + case CPU_DYING: > > + case CPU_DOWN_FAILED: > > if (try_acquire_console_sem() =3D=3D 0) > > release_console_sem(); > > } >=20 > The patch lacked a suitable title. I called it "console: flush log > messages for more cpu-hotplug events". > This diff was on top of already posted RFC patch. I will combine them > The patch lacks a Signed-off-by:. Please send one. >=20 > The patch has its tabs replaced with spaces. I fixed that. Please > reconfigure your email client for next time. >=20 > The code which is being patch has changed. It now does >=20 > acquire_console_sem(); > release_console_sem(); >=20 > so the code may no longer work - perhaps it now deadlocks (unlikely). > Please retest? Retested. No deadlock observed >=20 > Finally, I don't understand the patch :( Who is sending out CPU_DEAD, > CPU_DYING or CPU_DOWN_FAILED events during kernel boot? I'd have > thought that those events simply aren't occurring, and that the patch > has no effect. Confused - please explain further. These events can come during the CPU hotplug(offline). Below is the complete patch. Also attaching it in case some email format screw up. ----------------------------------------------- >From b99271ce43cc82cda28447444004933d0f218ee3 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Tue, 3 Aug 2010 12:58:22 +0530 Subject: [PATCH] console: flush delayed log messages from cpu-hotplug event= s When a secondary CPU is being brought up, it is not uncommon for printk() to be invoked when cpu_online(smp_processor_id()) =3D=3D 0. The case that I witnessed personally was on MIPS: http://lkml.org/lkml/2010/5/30/4 If (can_use_console() =3D=3D 0), printk() will spool its output to log_buf and it will be visible in "dmesg", but that output will NOT be echoed to the console until somebody calls release_console_sem() from a CPU that is online. Therefore, the boot time messages from the new CPU can get stuck in "limbo" for a long time, and might suddenly appear on the screen when a completely unrelated event (e.g. "eth0: link is down") occurs. This patch modifies the console code so that any pending messages are automatically flushed out to the console whenever a CPU hotplug operation completes successfully or aborts. This is true even when CPU is getting hot-plugged out(offline) so need to add additional hotplug events. The issue was seen on 2.6.34. Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Cernekee --- kernel/printk.c | 36 ++++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+), 0 deletions(-) diff --git a/kernel/printk.c b/kernel/printk.c index 444b770..a884d81 100644 --- a/kernel/printk.c +++ b/kernel/printk.c @@ -37,6 +37,8 @@ #include #include #include +#include +#include =20 #include =20 @@ -985,6 +987,40 @@ void resume_console(void) } =20 /** + * console_cpu_notify - print deferred console messages after CPU hotplug + * + * If printk() is called from a CPU that is not online yet, the messages + * will be spooled but will not show up on the console. This function is + * called when a new CPU comes online and ensures that any such output + * gets printed. + */ +static int __cpuinit console_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + switch (action) { + case CPU_ONLINE: + case CPU_DEAD: + case CPU_DYING: + case CPU_DOWN_FAILED: + case CPU_UP_CANCELED: + if (try_acquire_console_sem() =3D=3D 0) + release_console_sem(); + } + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata console_nb =3D { + .notifier_call =3D console_cpu_notify, +}; + +static int __init console_notifier_init(void) +{ + register_cpu_notifier(&console_nb); + return 0; +} +late_initcall(console_notifier_init); + +/** * acquire_console_sem - lock the console system for exclusive use. * * Acquires a semaphore which guarantees that the caller has --=20 1.6.0.4 ----------------------------------------------- --_002_EAF47CD23C76F840A9E7FCE10091EFAB02C641D8ECdbde02enttico_ Content-Type: application/octet-stream; name="console-flush-delayed-log-messages-from-cpu-hotplug.patch" Content-Description: console-flush-delayed-log-messages-from-cpu-hotplug.patch Content-Disposition: attachment; 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list linux-mips); Wed, 04 Aug 2010 17:24:33 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41513 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492874Ab0HDPY1 (ORCPT ); Wed, 4 Aug 2010 17:24:27 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o74FNjOd019110; Wed, 4 Aug 2010 16:23:46 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o74FNhGf019108; Wed, 4 Aug 2010 16:23:43 +0100 Date: Wed, 4 Aug 2010 16:23:42 +0100 From: Ralf Baechle To: Paul Mundt Cc: Andrew Morton , "Shilimkar, Santosh" , Kevin Cernekee , "linux-kernel@vger.kernel.org" , Russell King - ARM Linux , linux-mips@linux-mips.org Subject: Re: Additional fix : (was [v2]printk: fix delayed messages from CPU hotplug events) Message-ID: <20100804152342.GC21004@linux-mips.org> References: <20100802154434.5615bcf9.akpm@linux-foundation.org> <20100803165926.2e37d355.akpm@linux-foundation.org> <20100804033034.GA15098@linux-sh.org> <20100804135145.GA21004@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100804135145.GA21004@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27566 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Santosh's patch was lacking akpm's cleanup patch. So I created the following from all contributions. Ralf From 040f52ce2a3cab374bfed036ccd8ecf4b1fb7add Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 3 Jun 2010 22:11:25 -0700 Subject: [PATCH] printk: fix delayed messages from CPU hotplug events When a secondary CPU is being brought up, it is not uncommon for printk() to be invoked when cpu_online(smp_processor_id()) == 0. The case that I witnessed personally was on MIPS: http://lkml.org/lkml/2010/5/30/4 If (can_use_console() == 0), printk() will spool its output to log_buf and it will be visible in "dmesg", but that output will NOT be echoed to the console until somebody calls release_console_sem() from a CPU that is online. Therefore, the boot time messages from the new CPU can get stuck in "limbo" for a long time, and might suddenly appear on the screen when a completely unrelated event (e.g. "eth0: link is down") occurs. This patch modifies the console code so that any pending messages are automatically flushed out to the console whenever a CPU hotplug operation completes successfully or aborts. The issue was seen on 2.6.34. Original patch by Kevin Cernekee with cleanups by akpm and additional fixes by Santosh Shilimkar. This patch superseeds https://patchwork.linux-mips.org/patch/1357/. Signed-off-by: Kevin Cernekee To: To: To: To: To: Cc: Cc: Reviewed-by: Paul Mundt Signed-off-by: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/1533/ LKML-Reference: LKML-Reference: Signed-off-by: Ralf Baechle diff --git a/kernel/printk.c b/kernel/printk.c index 444b770..4ab0164 100644 --- a/kernel/printk.c +++ b/kernel/printk.c @@ -37,6 +37,8 @@ #include #include #include +#include +#include #include @@ -985,6 +987,32 @@ void resume_console(void) } /** + * console_cpu_notify - print deferred console messages after CPU hotplug + * @self: notifier struct + * @action: CPU hotplug event + * @hcpu: unused + * + * If printk() is called from a CPU that is not online yet, the messages + * will be spooled but will not show up on the console. This function is + * called when a new CPU comes online (or fails to come up), and ensures + * that any such output gets printed. + */ +static int __cpuinit console_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + switch (action) { + case CPU_ONLINE: + case CPU_DEAD: + case CPU_DYING: + case CPU_DOWN_FAILED: + case CPU_UP_CANCELED: + acquire_console_sem(); + release_console_sem(); + } + return NOTIFY_OK; +} + +/** * acquire_console_sem - lock the console system for exclusive use. * * Acquires a semaphore which guarantees that the caller has @@ -1371,7 +1399,7 @@ int unregister_console(struct console *console) } EXPORT_SYMBOL(unregister_console); -static int __init disable_boot_consoles(void) +static int __init printk_late_init(void) { struct console *con; @@ -1382,9 +1410,10 @@ static int __init disable_boot_consoles(void) unregister_console(con); } } + hotcpu_notifier(console_cpu_notify, 0); return 0; } -late_initcall(disable_boot_consoles); +late_initcall(printk_late_init); #if defined CONFIG_PRINTK From kevink@paralogos.com Wed Aug 4 17:26:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Aug 2010 17:27:02 +0200 (CEST) Received: from gateway06.websitewelcome.com ([69.93.164.14]:32940 "HELO gateway06.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492874Ab0HDP06 (ORCPT ); Wed, 4 Aug 2010 17:26:58 +0200 Received: (qmail 29477 invoked from network); 4 Aug 2010 15:37:17 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway06.websitewelcome.com with SMTP; 4 Aug 2010 15:37:17 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=paralogos.com; h=Received:Message-ID:Date:From:User-Agent:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding; b=HRDlOVT2Auv51Zu/kp+GTcvzZWdMmxFTBKhWFkbPd7ega3N5LQJo7s0Bo7uzvnWh1y9fUBk9anfumSq7/tguvrC6AVIij+6b0QPm5PQUis3BeMl1P1cHlVEi8RvWtRHU; Received: from [216.239.45.4] (port=60682 helo=kkissell.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1Ogfrm-0003RN-CK; Wed, 04 Aug 2010 10:26:51 -0500 Message-ID: <4C5986BC.9000307@paralogos.com> Date: Wed, 04 Aug 2010 08:26:52 -0700 From: "Kevin D. Kissell" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100713 Thunderbird/3.0.6 MIME-Version: 1.0 To: Deng-Cheng Zhu CC: linux-mips@linux-mips.org Subject: Re: [Q] enabling FPU for vpe1 References: <4C592027.8010902@paralogos.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27567 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips You can only set the TC's CU bits if the VPE to which the TC is bound has access to the coprocessor. See sections 8.2 andf 6.7 of the currently online spec, and read the MIPS MT Principles of Operation document, if you can find it. On 08/04/10 03:14, Deng-Cheng Zhu wrote: > Thanks for looking into this. > > I did do that. But the CU1 bit of TC#1 (in VPE#1) can not be set by > TC#0 or itself. Looks like VPE#1 is not seeing the FPU at all... > > > Deng-Cheng > > > 2010/8/4 Kevin D. Kissell: > >> Check the MIPS MT spec. If I recall correctly, it's possible to enable >> access to the FPU by either VPE by setting the right bits while the >> processor is in the MT configuration mode. >> >> Deng-Cheng Zhu wrote: >> >>> Hi, >>> >>> >>> I'm working on a 34Kf CPU. I understand that only one TC can use the >>> FPU at any given time. >>> >>> My question is: If a TC is attached to the 2nd VPE (i.e. VPE1), can I >>> enable FPU for it? >>> >>> I experimented on this, but failed to do it. Am I missing something? >>> >>> >>> Thanks >>> >>> Deng-Cheng >>> >>> >>> >> >> From David.Daney@caviumnetworks.com Wed Aug 4 23:54:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Aug 2010 23:54:21 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10917 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491882Ab0HDVyN (ORCPT ); Wed, 4 Aug 2010 23:54:13 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 04 Aug 2010 14:54:39 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 4 Aug 2010 14:54:10 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 4 Aug 2010 14:54:10 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o74Ls1Xb015094; Wed, 4 Aug 2010 14:54:02 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o74Lrw1r015093; Wed, 4 Aug 2010 14:53:58 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Octeon: Allow more than 3.75GB of memory with PCIe Date: Wed, 4 Aug 2010 14:53:57 -0700 Message-Id: <1280958837-15061-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.1.1 X-OriginalArrivalTime: 04 Aug 2010 21:54:10.0114 (UTC) FILETIME=[9192D220:01CB341F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27568 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips We reserve the 3.75GB - 4GB region of PCIe address space for device to device transfers, making the corresponding physical memory under direct mapping unavailable for DMA. To allow for PCIe DMA to all physical memory we map this chunk of physical memory with BAR1. Because of the resulting discontinuity in the mapping function, we remove a page of memory at each end of the range so multi-page DMA buffers can never be allocated that span the range. Signed-off-by: David Daney --- arch/mips/cavium-octeon/dma-octeon.c | 17 ++++++++----- arch/mips/cavium-octeon/setup.c | 34 +++++++++++++++++++++++++- arch/mips/include/asm/octeon/pci-octeon.h | 13 ++++++++++ arch/mips/pci/pcie-octeon.c | 37 ++++++++++++++++++++++++---- 4 files changed, 87 insertions(+), 14 deletions(-) diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index be531ec..d22b5a2 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -99,13 +99,16 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size) panic("dma_map_single: " "Attempt to map illegal memory address 0x%llx\n", physical); - else if ((physical + size >= - (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20)) - && physical < (4ull<<30)) - pr_warning("dma_map_single: Warning: " - "Mapping memory address that might " - "conflict with devices 0x%llx-0x%llx\n", - physical, physical+size-1); + else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE && + physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) { + result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE; + + if (((result+size-1) & dma_mask) != result+size-1) + panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n", + physical, physical+size-1, dma_mask); + goto done; + } + /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */ if ((physical >= 0x410000000ull) && physical < 0x420000000ull) result = physical - 0x400000000ull; diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 041326e..69197cb 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -32,6 +32,7 @@ #include #include +#include #ifdef CONFIG_CAVIUM_DECODE_RSL extern void cvmx_interrupt_rsl_decode(void); @@ -609,6 +610,22 @@ void __init prom_init(void) register_smp_ops(&octeon_smp_ops); } +/* Exclude a single page from the regions obtained in plat_mem_setup. */ +static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) +{ + if (addr > *mem && addr < *mem + *size) { + u64 inc = addr - *mem; + add_memory_region(*mem, inc, BOOT_MEM_RAM); + *mem += inc; + *size -= inc; + } + + if (addr == *mem && *size > PAGE_SIZE) { + *mem += PAGE_SIZE; + *size -= PAGE_SIZE; + } +} + void __init plat_mem_setup(void) { uint64_t mem_alloc_size; @@ -659,12 +676,27 @@ void __init plat_mem_setup(void) CVMX_BOOTMEM_FLAG_NO_LOCKING); #endif if (memory >= 0) { + u64 size = mem_alloc_size; + + /* + * exclude a page at the beginning and end of + * the 256MB PCIe 'hole' so the kernel will not + * try to allocate multi-page buffers that + * span the discontinuity. + */ + memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, + &memory, &size); + memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + + CVMX_PCIE_BAR1_PHYS_SIZE, + &memory, &size); + /* * This function automatically merges address * regions next to each other if they are * received in incrementing order. */ - add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); + if (size) + add_memory_region(memory, size, BOOT_MEM_RAM); total += mem_alloc_size; } else { break; diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h index 6ac5d3e..ece7804 100644 --- a/arch/mips/include/asm/octeon/pci-octeon.h +++ b/arch/mips/include/asm/octeon/pci-octeon.h @@ -15,6 +15,19 @@ #define PCI_CONFIG_SPACE_DELAY 10000 /* + * The physical memory base mapped by BAR1. 256MB at the end of the + * first 4GB. + */ +#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28)) +#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28) + +/* + * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, + * place BAR1 so it is the same for both. + */ +#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41) + +/* * pcibios_map_irq() is defined inside pci-octeon.c. All it does is * call the Octeon specific version pointed to by this variable. This * function needs to change for PCI or PCIe based hosts. diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 6aa5c54..861361e 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -402,6 +402,10 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port) npei_ctl_status2.s.mps = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */ npei_ctl_status2.s.mrrs = 0; + if (pcie_port) + npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */ + else + npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */ cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); /* ECRC Generation (PCIE*_CFG070[GE,CE]) */ @@ -666,6 +670,8 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port) static int cvmx_pcie_rc_initialize(int pcie_port) { int i; + int base; + u64 addr_swizzle; union cvmx_ciu_soft_prst ciu_soft_prst; union cvmx_pescx_bist_status pescx_bist_status; union cvmx_pescx_bist_status2 pescx_bist_status2; @@ -674,6 +680,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port) union cvmx_npei_mem_access_subidx mem_access_subid; union cvmx_npei_dbg_data npei_dbg_data; union cvmx_pescx_ctl_status2 pescx_ctl_status2; + union cvmx_npei_bar1_indexx bar1_index; /* * Make sure we aren't trying to setup a target mode interface @@ -918,12 +925,30 @@ static int cvmx_pcie_rc_initialize(int pcie_port) /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); - /* - * Disable Octeon's BAR1. It isn't needed in RC mode since - * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into - * the 2nd 256MB of memory. - */ - cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1); + /* BAR1 follows BAR2 with a gap. */ + cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); + + bar1_index.u32 = 0; + bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); + bar1_index.s.ca = 1; /* Not Cached */ + bar1_index.s.end_swp = 1; /* Endian Swap mode */ + bar1_index.s.addr_v = 1; /* Valid entry */ + + base = pcie_port ? 16 : 0; + + /* Big endian swizzle for 32-bit PEXP_NCB register. */ +#ifdef __MIPSEB__ + addr_swizzle = 4; +#else + addr_swizzle = 0; +#endif + for (i = 0; i < 16; i++) { + cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle), + bar1_index.u32); + base++; + /* 256MB / 16 >> 22 == 4 */ + bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22); + } /* * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take -- 1.7.1.1 From ralf@linux-mips.org Thu Aug 5 01:30:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 01:30:21 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41038 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493279Ab0HDXaR (ORCPT ); Thu, 5 Aug 2010 01:30:17 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o74NUEAa008549; Thu, 5 Aug 2010 00:30:14 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o74NUDex008537; Thu, 5 Aug 2010 00:30:13 +0100 Date: Thu, 5 Aug 2010 00:30:13 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Remove unused task_struct.trap_no field. Message-ID: <20100804233013.GA28115@linux-mips.org> References: <1280872659-27372-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280872659-27372-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27569 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Thu Aug 5 01:47:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 01:47:05 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47798 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493279Ab0HDXrB (ORCPT ); Thu, 5 Aug 2010 01:47:01 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o74NkOxi009045; Thu, 5 Aug 2010 00:46:24 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o74NkHEc009043; Thu, 5 Aug 2010 00:46:17 +0100 Date: Thu, 5 Aug 2010 00:46:17 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH] MIPS: Define regs_return_value() Message-ID: <20100804234617.GB28115@linux-mips.org> References: <20100803202607.GA25233@linux-mips.org> <1280868804-2595-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280868804-2595-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27570 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Thu Aug 5 01:54:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 01:54:19 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60090 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493293Ab0HDXyQ (ORCPT ); Thu, 5 Aug 2010 01:54:16 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o74NrxhB009310; Thu, 5 Aug 2010 00:53:59 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o74NrwgQ009308; Thu, 5 Aug 2010 00:53:58 +0100 Date: Thu, 5 Aug 2010 00:53:58 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH 2/5] MIPS: Add instrunction format for BREAK and SYSCALL Message-ID: <20100804235358.GC28115@linux-mips.org> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> <1280859742-26364-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280859742-26364-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27571 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Thu Aug 5 01:59:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 01:59:37 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47496 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492983Ab0HDX7e (ORCPT ); Thu, 5 Aug 2010 01:59:34 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o74NxIfx009502; Thu, 5 Aug 2010 00:59:19 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o74NxIEv009500; Thu, 5 Aug 2010 00:59:18 +0100 Date: Thu, 5 Aug 2010 00:59:18 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH 3/5] MIPS: Add KProbe support. Message-ID: <20100804235918.GD28115@linux-mips.org> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> <1280859742-26364-4-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280859742-26364-4-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27572 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Thu Aug 5 02:00:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:00:09 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47510 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493285Ab0HEAAG (ORCPT ); Thu, 5 Aug 2010 02:00:06 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o74Nxngr009510; Thu, 5 Aug 2010 00:59:49 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o74Nxnp5009509; Thu, 5 Aug 2010 00:59:49 +0100 Date: Thu, 5 Aug 2010 00:59:49 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH] MIPS: KProbes: Use flush_insn_slot() where possible. Message-ID: <20100804235949.GE28115@linux-mips.org> References: <1280859742-26364-4-git-send-email-ddaney@caviumnetworks.com> <1280869245-2786-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280869245-2786-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27573 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips > This is a small cleanup that could either be folded into the original > 3/5 or applied in addition to it. I've folded it into 3/5. Thanks! Ralf From ralf@linux-mips.org Thu Aug 5 02:04:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:04:52 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41496 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492983Ab0HEAEs (ORCPT ); Thu, 5 Aug 2010 02:04:48 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7504ZYh009728; Thu, 5 Aug 2010 01:04:35 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7504YTh009726; Thu, 5 Aug 2010 01:04:34 +0100 Date: Thu, 5 Aug 2010 01:04:34 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH 4/5] samples: kprobe_example: Make it print something on MIPS. Message-ID: <20100805000434.GF28115@linux-mips.org> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> <1280859742-26364-5-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280859742-26364-5-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27574 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Thu Aug 5 02:07:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:07:59 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41520 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493287Ab0HEAHz (ORCPT ); Thu, 5 Aug 2010 02:07:55 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7507eEN009937; Thu, 5 Aug 2010 01:07:40 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7507eWY009935; Thu, 5 Aug 2010 01:07:40 +0100 Date: Thu, 5 Aug 2010 01:07:40 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, masami.hiramatsu.pt@hitachi.com, linux-kernel@vger.kernel.org, hschauhan@nulltrace.org Subject: Re: [PATCH 5/5] documentation: Mention that KProbes is supported on MIPS Message-ID: <20100805000740.GG28115@linux-mips.org> References: <1280859742-26364-1-git-send-email-ddaney@caviumnetworks.com> <1280859742-26364-6-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280859742-26364-6-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27575 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied, thanks! Ralf From ralf@linux-mips.org Thu Aug 5 02:14:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:15:00 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40310 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493294Ab0HEAO4 (ORCPT ); Thu, 5 Aug 2010 02:14:56 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o750Es5s010164; Thu, 5 Aug 2010 01:14:54 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o750EskX010162; Thu, 5 Aug 2010 01:14:54 +0100 Date: Thu, 5 Aug 2010 01:14:54 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Clean up notify_die() usage. Message-ID: <20100805001453.GH28115@linux-mips.org> References: <1280875483-18540-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280875483-18540-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27576 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From ralf@linux-mips.org Thu Aug 5 02:23:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:23:12 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48176 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493294Ab0HEAXJ (ORCPT ); Thu, 5 Aug 2010 02:23:09 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o750N6Hp023197; Thu, 5 Aug 2010 01:23:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o750N5ws023172; Thu, 5 Aug 2010 01:23:05 +0100 Date: Thu, 5 Aug 2010 01:23:05 +0100 From: Ralf Baechle To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, linux-mmc@vger.kernel.org, Maarten ter Huurne Subject: Re: [PATCH] MMC: jz4740: Fixed card change detection. Message-ID: <20100805002305.GI28115@linux-mips.org> References: <1280853164-19900-1-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280853164-19900-1-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27577 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied on lmo rsp. folded into the patches pending for Linus and -next. Thanks, Ralf From ralf@linux-mips.org Thu Aug 5 02:29:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:29:51 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60295 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493287Ab0HEA3r (ORCPT ); Thu, 5 Aug 2010 02:29:47 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o750Tji2028116; Thu, 5 Aug 2010 01:29:45 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o750TiRg028113; Thu, 5 Aug 2010 01:29:44 +0100 Date: Thu, 5 Aug 2010 01:29:44 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: Allow more than 3.75GB of memory with PCIe Message-ID: <20100805002944.GJ28115@linux-mips.org> References: <1280958837-15061-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280958837-15061-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27578 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Thu Aug 5 02:35:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:35:47 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54317 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493285Ab0HEAfo (ORCPT ); Thu, 5 Aug 2010 02:35:44 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o750Zd7f028312; Thu, 5 Aug 2010 01:35:39 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o750ZcnT028308; Thu, 5 Aug 2010 01:35:38 +0100 Date: Thu, 5 Aug 2010 01:35:38 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org, Waldemar Brodkorb Subject: Re: [PATCH] MIPS: BCM47xx: nvram_getenv fix return value. Message-ID: <20100805003538.GK28115@linux-mips.org> References: <1280786182-6100-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280786182-6100-1-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27579 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Thu Aug 5 02:46:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:46:13 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33777 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492212Ab0HEAqK (ORCPT ); Thu, 5 Aug 2010 02:46:10 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o750k5Mp028649; Thu, 5 Aug 2010 01:46:05 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o750k5X5028647; Thu, 5 Aug 2010 01:46:05 +0100 Date: Thu, 5 Aug 2010 01:46:05 +0100 From: Ralf Baechle To: David VomLehn Cc: linux-mips@linux-mips.org Subject: Re: [PATCH][MIPS] PowerTV: add Gaia platform definitions Message-ID: <20100805004605.GA28402@linux-mips.org> References: <20100802184359.GA10915@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100802184359.GA10915@dvomlehn-lnx2.corp.sa.net> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27580 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From ralf@linux-mips.org Thu Aug 5 02:51:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 02:51:33 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51389 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492212Ab0HEAva (ORCPT ); Thu, 5 Aug 2010 02:51:30 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o750ngFW028744; Thu, 5 Aug 2010 01:49:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o750nfpU028742; Thu, 5 Aug 2010 01:49:41 +0100 Date: Thu, 5 Aug 2010 01:49:41 +0100 From: Ralf Baechle To: David VomLehn Cc: linux-mips@linux-mips.org, greg@kroah.com, linux-usb@vger.kernel.org Subject: Re: [PATCH 2/2][MIPS] USB/PowerTV: Separate PowerTV USB support from non-USB code Message-ID: <20100805004941.GB28402@linux-mips.org> References: <20100803014058.GA31552@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100803014058.GA31552@dvomlehn-lnx2.corp.sa.net> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27581 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips David, can this patch be safely applied alone until I get an Ack for patch 1/1? Thanks, Ralf From ralf@linux-mips.org Thu Aug 5 03:13:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 03:13:50 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54824 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492212Ab0HEBNq (ORCPT ); Thu, 5 Aug 2010 03:13:46 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o751Di26029394; Thu, 5 Aug 2010 02:13:44 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o751DiDg029392; Thu, 5 Aug 2010 02:13:44 +0100 Date: Thu, 5 Aug 2010 02:13:43 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Clean up arch/mips/boot/compressed/ld.script Message-ID: <20100805011343.GC28402@linux-mips.org> References: <7a966ffadcf2a4600c098c3ac47ef1f645790946.1276674390.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7a966ffadcf2a4600c098c3ac47ef1f645790946.1276674390.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27582 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied - but there was an entirely avoidable reject in that file *grrr* :-) Thanks, Ralf From ralf@linux-mips.org Thu Aug 5 03:21:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 03:21:03 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56951 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492212Ab0HEBVA (ORCPT ); Thu, 5 Aug 2010 03:21:00 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o751KxD9029608; Thu, 5 Aug 2010 02:20:59 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o751KxF1029607; Thu, 5 Aug 2010 02:20:59 +0100 Date: Thu, 5 Aug 2010 02:20:59 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Clean up arch/mips/boot/compressed/decompress.c Message-ID: <20100805012059.GD28402@linux-mips.org> References: <7a966ffadcf2a4600c098c3ac47ef1f645790946.1276674390.git.wuzhangjin@gmail.com> <1276674753-30240-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276674753-30240-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27583 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From ralf@linux-mips.org Thu Aug 5 03:32:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 03:32:31 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:39069 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493076Ab0HEBc2 (ORCPT ); Thu, 5 Aug 2010 03:32:28 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o751WMFU030062; Thu, 5 Aug 2010 02:32:22 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o751WLRk030060; Thu, 5 Aug 2010 02:32:21 +0100 Date: Thu, 5 Aug 2010 02:32:21 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips , Alexander Clouter , Manuel Lauss , Sam Ravnborg Subject: Re: [PATCH v4] MIPS: Clean up the calculation of VMLINUZ_LOAD_ADDRESS Message-ID: <20100805013221.GE28402@linux-mips.org> References: <9890d1383c75ce6df44d357687a9c4e2d6ba4050.1275438553.git.wuzhangjin@gmail.com> <96f3b48ba7f749c4357760008cdae644aa55b92d.1275438520.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <96f3b48ba7f749c4357760008cdae644aa55b92d.1275438520.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27584 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied - but there was a fuzz when applying the patch. Hope that was harmless... Thanks, Ralf From ralf@linux-mips.org Thu Aug 5 03:34:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 03:34:19 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45534 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493296Ab0HEBeQ (ORCPT ); Thu, 5 Aug 2010 03:34:16 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o751YEqd030184; Thu, 5 Aug 2010 02:34:14 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o751YE1E030182; Thu, 5 Aug 2010 02:34:14 +0100 Date: Thu, 5 Aug 2010 02:34:14 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: strip the un-needed sections of vmlinuz Message-ID: <20100805013414.GF28402@linux-mips.org> References: <7a966ffadcf2a4600c098c3ac47ef1f645790946.1276674390.git.wuzhangjin@gmail.com> <1276674753-30240-2-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276674753-30240-2-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27585 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From dengcheng.zhu@gmail.com Thu Aug 5 03:58:15 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 04:00:25 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:63041 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493290Ab0HEB6P convert rfc822-to-8bit (ORCPT ); Thu, 5 Aug 2010 03:58:15 +0200 Received: by ewy9 with SMTP id 9so2582285ewy.36 for ; Wed, 04 Aug 2010 18:58:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=ffF5+c6j4fmYeLHm26OLC/O3Bq0iJNEihdI25s0OI9A=; b=j5wc4n+RzKPw6q7S4vOLmlWmqnqA6hw6qFEIX9MJA1GnXyCkb1Eh1SHnQa9cok060K 61vYL87o8dxrJipRujeYOvSUY+BI+ObHU/Rsn0rT+jimeGHfeU9hzSIF+e8+Faovh1AC tc9hUsy5dWXpnzaFQmvq73nql1cH3ic4iBGqM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=rMrdtocG8mkDBMsvXED4ah/KbdPLiuNEAOJoUFlN2mauS7eBHoVC8lCffRiNAgyYxH 1cIhBe7NIctnpcTsH2MyXXZGbWNDHL7qguip9ynNj+q9BlRs7XAhLP+lM86Vx4MHm0sQ iBGuSl8BIjI9eFQ4zey6fKTyVZr7GduUL8y8w= MIME-Version: 1.0 Received: by 10.14.48.71 with SMTP id u47mr1084654eeb.59.1280973495282; Wed, 04 Aug 2010 18:58:15 -0700 (PDT) Received: by 10.14.127.13 with HTTP; Wed, 4 Aug 2010 18:58:15 -0700 (PDT) In-Reply-To: <4C5986BC.9000307@paralogos.com> References: <4C592027.8010902@paralogos.com> <4C5986BC.9000307@paralogos.com> Date: Thu, 5 Aug 2010 09:58:15 +0800 Message-ID: Subject: Re: [Q] enabling FPU for vpe1 From: Deng-Cheng Zhu To: "Kevin D. Kissell" Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27586 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips You are correct. I did miss something earlier. The NCP1 needs to be set. Thanks, Kevin. Deng-Cheng 2010/8/4 Kevin D. Kissell : > You can only set the TC's CU bits if the VPE to which the TC is bound has > access to the coprocessor.  See sections 8.2 andf 6.7 of the currently > online spec, and read the MIPS MT Principles of Operation document, if you > can find it. > > On 08/04/10 03:14, Deng-Cheng Zhu wrote: >> >> Thanks for looking into this. >> >> I did do that. But the CU1 bit of TC#1 (in VPE#1) can not be set by >> TC#0 or itself. Looks like VPE#1 is not seeing the FPU at all... >> >> >> Deng-Cheng >> >> >> 2010/8/4 Kevin D. Kissell: >> >>> >>> Check the MIPS MT spec.  If I recall correctly, it's possible to enable >>> access to the FPU by either VPE by setting the right bits while the >>> processor is in the MT configuration mode. >>> >>> Deng-Cheng Zhu wrote: >>> >>>> >>>> Hi, >>>> >>>> >>>> I'm working on a 34Kf CPU. I understand that only one TC can use the >>>> FPU at any given time. >>>> >>>> My question is: If a TC is attached to the 2nd VPE (i.e. VPE1), can I >>>> enable FPU for it? >>>> >>>> I experimented on this, but failed to do it. Am I missing something? >>>> >>>> >>>> Thanks >>>> >>>> Deng-Cheng >>>> >>>> >>>> >>> >>> > > From dvomlehn@cisco.com Thu Aug 5 04:32:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 04:32:59 +0200 (CEST) Received: from sj-iport-5.cisco.com ([171.68.10.87]:35508 "EHLO sj-iport-5.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493293Ab0HECcx (ORCPT ); Thu, 5 Aug 2010 04:32:53 +0200 Authentication-Results: sj-iport-5.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAAa/WUyrR7Hu/2dsb2JhbACgK3GpPpshghqDIQSEHg X-IronPort-AV: E=Sophos;i="4.55,318,1278288000"; d="scan'208";a="235756576" Received: from sj-core-5.cisco.com ([171.71.177.238]) by sj-iport-5.cisco.com with ESMTP; 05 Aug 2010 02:32:44 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-5.cisco.com (8.13.8/8.14.3) with ESMTP id o752WipP006839; Thu, 5 Aug 2010 02:32:44 GMT Date: Wed, 4 Aug 2010 19:32:44 -0700 From: David VomLehn To: Ralf Baechle Cc: linux-mips@linux-mips.org, greg@kroah.com, linux-usb@vger.kernel.org Subject: Re: [PATCH 2/2][MIPS] USB/PowerTV: Separate PowerTV USB support from non-USB code Message-ID: <20100805023244.GA6780@dvomlehn-lnx2.corp.sa.net> References: <20100803014058.GA31552@dvomlehn-lnx2.corp.sa.net> <20100805004941.GB28402@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100805004941.GB28402@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27587 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Thu, Aug 05, 2010 at 01:49:41AM +0100, Ralf Baechle wrote: > David, > > can this patch be safely applied alone until I get an Ack for patch 1/1? > > Thanks, > > Ralf Yes. It's the first time I've submitted something that crosses maintainer lines, so I made sure it would work with USB disabled. -- David VL From wuzhangjin@gmail.com Thu Aug 5 04:42:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 04:42:16 +0200 (CEST) Received: from mail-ww0-f41.google.com ([74.125.82.41]:61627 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491090Ab0HECmN (ORCPT ); Thu, 5 Aug 2010 04:42:13 +0200 Received: by wwa36 with SMTP id 36so295754wwa.0 for ; Wed, 04 Aug 2010 19:42:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=VDCL8/GNB3IIqEpFLLb6hwKLRynum78h+mSqVlxBY1c=; b=YY7WJMMzCJozi7uhLo2udqld4rTKYwwWETSm6NurXvUZxWcjhy0SfJ5hnLS6nhpMWZ snwMjtA4vJhGVgpBVUiC2zXlwaitVpgW5zbEylck9N1k06WhHfXtYxWdo8rBLMYm1Pxo sxa15HfJLud+N2mHN6SgfV1Rfu50V1wGFkNtA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=lCZ53CCLUvdjyM5lG8GMW3Hkvolc6ymyG046IE9nr0DFCzXLSK2LWHlcWIWW6oDRQ7 fe93paqcc+HwjGEuO4z9YwiyKligfzHa1QkbMawWOkwOUsS+kqcpRO32c6WKQvKPyYFZ 7Rm42hyvtgYp7xRrAQ7Ee54pAW9YAF7umvKA0= MIME-Version: 1.0 Received: by 10.216.235.104 with SMTP id t82mr2769949weq.103.1280976127653; Wed, 04 Aug 2010 19:42:07 -0700 (PDT) Received: by 10.216.159.204 with HTTP; Wed, 4 Aug 2010 19:42:07 -0700 (PDT) In-Reply-To: <20100805011343.GC28402@linux-mips.org> References: <7a966ffadcf2a4600c098c3ac47ef1f645790946.1276674390.git.wuzhangjin@gmail.com> <20100805011343.GC28402@linux-mips.org> Date: Thu, 5 Aug 2010 10:42:07 +0800 Message-ID: Subject: Re: [PATCH] MIPS: Clean up arch/mips/boot/compressed/ld.script From: wu zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27588 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, Ralf On Thu, Aug 5, 2010 at 9:13 AM, Ralf Baechle wrote: > Applied - but there was an entirely avoidable reject in that file *grrr* :-) > Thanks, Just took a look at your upstream-linus.git git repo and found you have applied them in a wrong order and have forgotten applying the first one of them ;) 1. [v2] MIPS: Unify the suffix of compressed vmlinux.bin http://patchwork.linux-mips.org/patch/1323/ This one should be applied as the first one, but seems this is still in the patchwork ;) 2. [v4] MIPS: Clean up the calculation of VMLINUZ_LOAD_ADDRESS http://patchwork.linux-mips.org/patch/1324/ 3. MIPS: Clean up arch/mips/boot/compressed/ld.script http://patchwork.linux-mips.org/patch/1381/ 4. MIPS: Clean up arch/mips/boot/compressed/decompress.c http://patchwork.linux-mips.org/patch/1382/ 5. MIPS: strip the un-needed sections of vmlinuz http://patchwork.linux-mips.org/patch/1383/ Sould I resend all of them in one patchset? But I can only do it tonight. Thanks & Regards, Wu Zhangjin From ralf@linux-mips.org Thu Aug 5 04:53:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 04:53:55 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49489 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491090Ab0HECxw (ORCPT ); Thu, 5 Aug 2010 04:53:52 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o752rosp020033; Thu, 5 Aug 2010 03:53:50 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o752rn7c020031; Thu, 5 Aug 2010 03:53:49 +0100 Date: Thu, 5 Aug 2010 03:53:49 +0100 From: Ralf Baechle To: wu zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Clean up arch/mips/boot/compressed/ld.script Message-ID: <20100805025349.GB16367@linux-mips.org> References: <7a966ffadcf2a4600c098c3ac47ef1f645790946.1276674390.git.wuzhangjin@gmail.com> <20100805011343.GC28402@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27589 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Aug 05, 2010 at 10:08:47AM +0800, wu zhangjin wrote: > This one should be applied as the first one, but seems this is still in the > patchwork ;) > > 2. [v4] MIPS: Clean up the calculation of VMLINUZ_LOAD_ADDRESS > http://patchwork.linux-mips.org/patch/1324/ > > 3. MIPS: Clean up arch/mips/boot/compressed/ld.script > http://patchwork.linux-mips.org/patch/1381/ > > 4. MIPS: Clean up arch/mips/boot/compressed/decompress.c > http://patchwork.linux-mips.org/patch/1382/ > > 5. MIPS: strip the un-needed sections of vmlinuz > http://patchwork.linux-mips.org/patch/1383/ > > Sould I resend all of them in one patchset? But I can only do it tonight. No need but thanks for the offer. Ralf From ralf@linux-mips.org Thu Aug 5 05:10:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 05:10:51 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44701 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493301Ab0HEDKs (ORCPT ); Thu, 5 Aug 2010 05:10:48 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o753AgEn020517; Thu, 5 Aug 2010 04:10:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o753Ag7R020516; Thu, 5 Aug 2010 04:10:42 +0100 Date: Thu, 5 Aug 2010 04:10:42 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips , Alexander Clouter , Manuel Lauss , Sam Ravnborg Subject: Re: [PATCH v2] MIPS: Unify the suffix of compressed vmlinux.bin Message-ID: <20100805031042.GA20143@linux-mips.org> References: <9890d1383c75ce6df44d357687a9c4e2d6ba4050.1275438553.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9890d1383c75ce6df44d357687a9c4e2d6ba4050.1275438553.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27590 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From wuzhangjin@gmail.com Thu Aug 5 06:50:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 06:50:17 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:44363 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493313Ab0HEEuM convert rfc822-to-8bit (ORCPT ); Thu, 5 Aug 2010 06:50:12 +0200 Received: by wwb22 with SMTP id 22so1411599wwb.24 for ; Wed, 04 Aug 2010 21:50:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=6Zru05XrM7wnoW5s5j9HX343/PdRTArV8CsMOI6NP2k=; b=WeuuORBOYoNnamAXdBHj4nf0nRKMfYmGDgEZDUnSOi57fppOXCP3VivosTk4rz0aUj we2NCo9L+W7N6UBm2qm9mn7HWrL3IDM5CucJhP43ekbcw3/2TjRK9Z+BIeYr/FzIbYZv +aWjkRMDiVcTbtQYU6z9p7PnHrts7SDcq+qNY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=QOozq2VRHRDaTQNKd9zvRySt75HQaYRFLVgUy3mewOf3Id0VhHct290xrME73QZdY8 uXeSeWF9OtKMYNcrE+aREK7kEDWxQfHJ3RJjReY/uc4syv2kuinYzzkSztmWbaXDWQqY AgDQcmVh4oFAmErlAtsGMuZN2B7lXs8szhRb8= MIME-Version: 1.0 Received: by 10.216.5.4 with SMTP id 4mr2970758wek.20.1280983806906; Wed, 04 Aug 2010 21:50:06 -0700 (PDT) Received: by 10.216.159.204 with HTTP; Wed, 4 Aug 2010 21:50:06 -0700 (PDT) In-Reply-To: <20100805013221.GE28402@linux-mips.org> References: <9890d1383c75ce6df44d357687a9c4e2d6ba4050.1275438553.git.wuzhangjin@gmail.com> <96f3b48ba7f749c4357760008cdae644aa55b92d.1275438520.git.wuzhangjin@gmail.com> <20100805013221.GE28402@linux-mips.org> Date: Thu, 5 Aug 2010 12:50:06 +0800 Message-ID: Subject: Re: [PATCH v4] MIPS: Clean up the calculation of VMLINUZ_LOAD_ADDRESS From: wu zhangjin To: Ralf Baechle Cc: linux-mips , Alexander Clouter , Manuel Lauss , Sam Ravnborg Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27591 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, Ralf On Thu, Aug 5, 2010 at 9:32 AM, Ralf Baechle wrote: > Applied - but there was a fuzz when applying the patch.  Hope that was > harmless... Sorry to disturb you again. Just found the key file calc_vmlinuz_load_addr.c is not in your upstream-linus.git, I guess a "git add" was missing for it ;) the commit in upstream: http://git.linux-mips.org/?p=upstream-linus.git;a=commit;h=af86de3e5347c114afd978fbfc16af9a77e24c47 the original patch: http://patchwork.linux-mips.org/patch/1324/ Thanks & Regards, Wu Zhangjin From ralf@linux-mips.org Thu Aug 5 14:28:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 14:28:46 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48289 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493348Ab0HEM2n (ORCPT ); Thu, 5 Aug 2010 14:28:43 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o75CSbPj025142; Thu, 5 Aug 2010 13:28:37 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o75CSaUM025140; Thu, 5 Aug 2010 13:28:36 +0100 Date: Thu, 5 Aug 2010 13:28:35 +0100 From: Ralf Baechle To: David VomLehn Cc: linux-mips@linux-mips.org, greg@kroah.com, linux-usb@vger.kernel.org Subject: Re: [PATCH 2/2][MIPS] USB/PowerTV: Separate PowerTV USB support from non-USB code Message-ID: <20100805122835.GA7364@linux-mips.org> References: <20100803014058.GA31552@dvomlehn-lnx2.corp.sa.net> <20100805004941.GB28402@linux-mips.org> <20100805023244.GA6780@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100805023244.GA6780@dvomlehn-lnx2.corp.sa.net> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27592 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Aug 04, 2010 at 07:32:44PM -0700, David VomLehn wrote: > > can this patch be safely applied alone until I get an Ack for patch 1/1? > > Yes. It's the first time I've submitted something that crosses maintainer > lines, so I made sure it would work with USB disabled. Thanks, 2/2 applied then. I had to fix a trivial reject in arch/mips/powertv/Makefile. Ralf From andrea.gelmini@gmail.com Thu Aug 5 15:51:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 15:51:58 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:40536 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492973Ab0HENvy (ORCPT ); Thu, 5 Aug 2010 15:51:54 +0200 Received: by wyf19 with SMTP id 19so3505736wyf.36 for ; Thu, 05 Aug 2010 06:51:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:cc:subject :date:message-id:x-mailer; bh=nJBF3vaQwmfvIEEYbYGcDouD3hMOUhLj7ja7u/wGjyk=; b=G9cpO8CKskuqLqNaEDBAWL47cpWSscQ7NqVtZ2GinUv6sbwmMmDCjA3ibrLlCX9CB1 Mb+JOum4Mn7P0JkhVGobZf2NV+49gKkZjg6sO1kUMXDgj2QCAd/a/VKCbY4iVDTheA/J iLcBFmdLElY/GLR74SS28D7B0QfVM0qxknq2c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer; b=ra39CsL+k6N1Lz5xGEej0A3f1s+EWNL60rygtRJsBlck2cWptQblBGDGxjVWDLLtZI 7N0KfKdQwUovqSFrlzuUUC3mLO19gtVY0hPoONfI97OdbiUY/f9DAZw64QGMPnn0YMdN JQmGKIypLs7rL8fOT3YWq4NlRBJd0hRMnKgAM= Received: by 10.227.72.139 with SMTP id m11mr9016254wbj.30.1281016309096; Thu, 05 Aug 2010 06:51:49 -0700 (PDT) Received: from localhost.localdomain (adsl203-161-174.mclink.it [213.203.161.174]) by mx.google.com with ESMTPS id w46sm133041weq.43.2010.08.05.06.51.46 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 05 Aug 2010 06:51:47 -0700 (PDT) From: Andrea Gelmini To: gelma@gelma.net Cc: Andrea Gelmini , Ralf Baechle , Jason Wessel , Martin Hicks , linux-mips@linux-mips.org Subject: [PATCH 01/15] arch: mips: kernel: Fix a typo. Date: Thu, 5 Aug 2010 15:51:25 +0200 Message-Id: <1281016299-23958-1-git-send-email-andrea.gelmini@gelma.net> X-Mailer: git-send-email 1.7.2.1.85.g2d089 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27593 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: andrea.gelmini@gelma.net Precedence: bulk X-list: linux-mips "Userpace" -> "Userspace" Signed-off-by: Andrea Gelmini --- arch/mips/kernel/kgdb.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index 9b78ff6..f0f74f4 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -196,7 +196,7 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, struct pt_regs *regs = args->regs; int trap = (regs->cp0_cause & 0x7c) >> 2; - /* Userpace events, ignore. */ + /* Userspace events, ignore. */ if (user_mode(regs)) return NOTIFY_DONE; -- 1.7.2.1.85.g2d089 From Anoop_P.A@pmc-sierra.com Thu Aug 5 16:17:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 16:18:06 +0200 (CEST) Received: from [216.241.235.117] ([216.241.235.117]:40623 "EHLO bby1mta02.pmc-sierra.bc.ca" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491099Ab0HEOR5 convert rfc822-to-8bit (ORCPT ); Thu, 5 Aug 2010 16:17:57 +0200 Received: from bby1mta02.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id 097818E0080; Thu, 5 Aug 2010 06:43:52 -0700 (PDT) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (BBY1EXG02.pmc-sierra.bc.ca [216.241.231.167]) by bby1mta02.pmc-sierra.bc.ca (Postfix) with SMTP id 6BD548E001B; Thu, 5 Aug 2010 06:43:52 -0700 (PDT) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.157]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.4675); Thu, 5 Aug 2010 06:43:52 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 8BIT Subject: RE: file corruption with highmem kernel Date: Thu, 5 Aug 2010 06:43:50 -0700 Message-ID: In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: file corruption with highmem kernel Thread-Index: AcsyRsvJtdIm2QULSF2xEZbUAQ5rPACWmtew References: From: "Anoop P.A." To: "linux-mips" , "Ralf Baechle" X-OriginalArrivalTime: 05 Aug 2010 13:43:52.0230 (UTC) FILETIME=[3D8FB460:01CB34A4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27594 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips List, With a slightly modified patched (copied below) I have reached a point where I am no more seeing errors like segmentation fault, bus error (which was due to memory corruption I believe). How ever I am still seeing some kind of file corruption. I believe this file corruption happening because cache is not getting invalidated before a highmem dma. I am not sure which routine to call to invalidate cache for a highmem address. Hope to see response from linux-mips gurus Thank you, Anoop --- arch/mips/mm/dma-noncoherent.c.orig 2010-08-02 23:53:17.000000000 +0530 +++ arch/mips/mm/dma-noncoherent.c 2010-08-06 00:17:21.000000000 +0530 @@ -131,13 +131,14 @@ for (i = 0; i < nents; i++, sg++) { unsigned long addr; - - addr = (unsigned long) page_address(sg->page); - if (addr) { - __dma_sync(addr + sg->offset, sg->length, direction); - sg->dma_address = (dma_addr_t)page_to_phys(sg->page) - + sg->offset; + if (!PageHighMem(sg->page)){ + addr = (unsigned long)page_address(sg->page) + sg->offset; + __dma_sync(addr , sg->length, direction); } + + sg->dma_address = (dma_addr_t)page_to_phys(sg->page) + + sg->offset; + } return nents; @@ -187,9 +188,10 @@ return; for (i = 0; i < nhwentries; i++, sg++) { - addr = (unsigned long) page_address(sg->page); - if (addr) - __dma_sync(addr + sg->offset, sg->length, direction); + if (!PageHighMem(sg->page)){ + addr = (unsigned long)page_address(sg->page) + sg->offset; + __dma_sync(addr , sg->length, direction); + } } } From jason.wessel@windriver.com Thu Aug 5 16:38:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 16:38:40 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:41141 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491132Ab0HEOig (ORCPT ); Thu, 5 Aug 2010 16:38:36 +0200 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id o75EcFhV000383; Thu, 5 Aug 2010 07:38:15 -0700 (PDT) Received: from ala-mail06.corp.ad.wrs.com ([147.11.57.147]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 5 Aug 2010 07:38:14 -0700 Received: from localhost.localdomain ([172.25.32.35]) by ala-mail06.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 5 Aug 2010 07:38:15 -0700 From: Jason Wessel To: torvalds@linux-foundation.org Cc: linux-kernel@vger.kernel.org, kgdb-bugreport@lists.sourceforge.net, Jason Wessel , linux-mips@linux-mips.org Subject: [PATCH 05/17] kgdb,mips: Individual register get/set for mips Date: Thu, 5 Aug 2010 09:37:46 -0500 Message-Id: <1281019078-6636-6-git-send-email-jason.wessel@windriver.com> X-Mailer: git-send-email 1.6.4.rc1 In-Reply-To: <1281019078-6636-5-git-send-email-jason.wessel@windriver.com> References: <1281019078-6636-1-git-send-email-jason.wessel@windriver.com> <1281019078-6636-2-git-send-email-jason.wessel@windriver.com> <1281019078-6636-3-git-send-email-jason.wessel@windriver.com> <1281019078-6636-4-git-send-email-jason.wessel@windriver.com> <1281019078-6636-5-git-send-email-jason.wessel@windriver.com> X-OriginalArrivalTime: 05 Aug 2010 14:38:15.0136 (UTC) FILETIME=[D667A600:01CB34AB] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27595 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jason.wessel@windriver.com Precedence: bulk X-list: linux-mips Implement the ability to individually get and set registers for kdb and kgdb for mips. Signed-off-by: Jason Wessel Acked-by: Ralf Baechle CC: linux-mips@linux-mips.org --- arch/mips/include/asm/kgdb.h | 19 ++-- arch/mips/kernel/kgdb.c | 203 ++++++++++++++++++++++++++++++------------ 2 files changed, 154 insertions(+), 68 deletions(-) diff --git a/arch/mips/include/asm/kgdb.h b/arch/mips/include/asm/kgdb.h index 19002d6..e6c0b0e 100644 --- a/arch/mips/include/asm/kgdb.h +++ b/arch/mips/include/asm/kgdb.h @@ -8,28 +8,27 @@ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) -#define KGDB_GDB_REG_SIZE 32 +#define KGDB_GDB_REG_SIZE 32 +#define GDB_SIZEOF_REG sizeof(u32) #elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ (_MIPS_ISA == _MIPS_ISA_MIPS64) #ifdef CONFIG_32BIT -#define KGDB_GDB_REG_SIZE 32 +#define KGDB_GDB_REG_SIZE 32 +#define GDB_SIZEOF_REG sizeof(u32) #else /* CONFIG_CPU_32BIT */ -#define KGDB_GDB_REG_SIZE 64 +#define KGDB_GDB_REG_SIZE 64 +#define GDB_SIZEOF_REG sizeof(u64) #endif #else #error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA" #endif /* _MIPS_ISA */ #define BUFMAX 2048 -#if (KGDB_GDB_REG_SIZE == 32) -#define NUMREGBYTES (90*sizeof(u32)) -#define NUMCRITREGBYTES (12*sizeof(u32)) -#else -#define NUMREGBYTES (90*sizeof(u64)) -#define NUMCRITREGBYTES (12*sizeof(u64)) -#endif +#define DBG_MAX_REG_NUM 72 +#define NUMREGBYTES (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG)) +#define NUMCRITREGBYTES (12 * sizeof(GDB_SIZEOF_REG)) #define BREAK_INSTR_SIZE 4 #define CACHE_FLUSH_IS_SAFE 0 diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index 9b78ff6..5e76c2d 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -50,6 +50,151 @@ static struct hard_trap_info { { 0, 0} /* Must be last */ }; +struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = +{ + { "zero", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[0]) }, + { "at", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[1]) }, + { "v0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[2]) }, + { "v1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[3]) }, + { "a0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[4]) }, + { "a1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[5]) }, + { "a2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[6]) }, + { "a3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[7]) }, + { "t0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[8]) }, + { "t1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[9]) }, + { "t2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[10]) }, + { "t3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[11]) }, + { "t4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[12]) }, + { "t5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[13]) }, + { "t6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[14]) }, + { "t7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[15]) }, + { "s0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[16]) }, + { "s1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[17]) }, + { "s2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[18]) }, + { "s3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[19]) }, + { "s4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[20]) }, + { "s5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[21]) }, + { "s6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[22]) }, + { "s7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[23]) }, + { "t8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[24]) }, + { "t9", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[25]) }, + { "k0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[26]) }, + { "k1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[27]) }, + { "gp", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[28]) }, + { "sp", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[29]) }, + { "s8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[30]) }, + { "ra", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[31]) }, + { "sr", GDB_SIZEOF_REG, offsetof(struct pt_regs, cp0_status) }, + { "lo", GDB_SIZEOF_REG, offsetof(struct pt_regs, lo) }, + { "hi", GDB_SIZEOF_REG, offsetof(struct pt_regs, hi) }, + { "bad", GDB_SIZEOF_REG, offsetof(struct pt_regs, cp0_badvaddr) }, + { "cause", GDB_SIZEOF_REG, offsetof(struct pt_regs, cp0_cause) }, + { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, cp0_epc) }, + { "f0", GDB_SIZEOF_REG, 0 }, + { "f1", GDB_SIZEOF_REG, 1 }, + { "f2", GDB_SIZEOF_REG, 2 }, + { "f3", GDB_SIZEOF_REG, 3 }, + { "f4", GDB_SIZEOF_REG, 4 }, + { "f5", GDB_SIZEOF_REG, 5 }, + { "f6", GDB_SIZEOF_REG, 6 }, + { "f7", GDB_SIZEOF_REG, 7 }, + { "f8", GDB_SIZEOF_REG, 8 }, + { "f9", GDB_SIZEOF_REG, 9 }, + { "f10", GDB_SIZEOF_REG, 10 }, + { "f11", GDB_SIZEOF_REG, 11 }, + { "f12", GDB_SIZEOF_REG, 12 }, + { "f13", GDB_SIZEOF_REG, 13 }, + { "f14", GDB_SIZEOF_REG, 14 }, + { "f15", GDB_SIZEOF_REG, 15 }, + { "f16", GDB_SIZEOF_REG, 16 }, + { "f17", GDB_SIZEOF_REG, 17 }, + { "f18", GDB_SIZEOF_REG, 18 }, + { "f19", GDB_SIZEOF_REG, 19 }, + { "f20", GDB_SIZEOF_REG, 20 }, + { "f21", GDB_SIZEOF_REG, 21 }, + { "f22", GDB_SIZEOF_REG, 22 }, + { "f23", GDB_SIZEOF_REG, 23 }, + { "f24", GDB_SIZEOF_REG, 24 }, + { "f25", GDB_SIZEOF_REG, 25 }, + { "f26", GDB_SIZEOF_REG, 26 }, + { "f27", GDB_SIZEOF_REG, 27 }, + { "f28", GDB_SIZEOF_REG, 28 }, + { "f29", GDB_SIZEOF_REG, 29 }, + { "f30", GDB_SIZEOF_REG, 30 }, + { "f31", GDB_SIZEOF_REG, 31 }, + { "fsr", GDB_SIZEOF_REG, 0 }, + { "fir", GDB_SIZEOF_REG, 0 }, +}; + +int dbg_set_reg(int regno, void *mem, struct pt_regs *regs) +{ + int fp_reg; + + if (regno < 0 || regno >= DBG_MAX_REG_NUM) + return -EINVAL; + + if (dbg_reg_def[regno].offset != -1 && regno < 38) { + memcpy((void *)regs + dbg_reg_def[regno].offset, mem, + dbg_reg_def[regno].size); + } else if (current && dbg_reg_def[regno].offset != -1 && regno < 72) { + /* FP registers 38 -> 69 */ + if (!(regs->cp0_status & ST0_CU1)) + return 0; + if (regno == 70) { + /* Process the fcr31/fsr (register 70) */ + memcpy((void *)¤t->thread.fpu.fcr31, mem, + dbg_reg_def[regno].size); + goto out_save; + } else if (regno == 71) { + /* Ignore the fir (register 71) */ + goto out_save; + } + fp_reg = dbg_reg_def[regno].offset; + memcpy((void *)¤t->thread.fpu.fpr[fp_reg], mem, + dbg_reg_def[regno].size); +out_save: + restore_fp(current); + } + + return 0; +} + +char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) +{ + int fp_reg; + + if (regno >= DBG_MAX_REG_NUM || regno < 0) + return NULL; + + if (dbg_reg_def[regno].offset != -1 && regno < 38) { + /* First 38 registers */ + memcpy(mem, (void *)regs + dbg_reg_def[regno].offset, + dbg_reg_def[regno].size); + } else if (current && dbg_reg_def[regno].offset != -1 && regno < 72) { + /* FP registers 38 -> 69 */ + if (!(regs->cp0_status & ST0_CU1)) + goto out; + save_fp(current); + if (regno == 70) { + /* Process the fcr31/fsr (register 70) */ + memcpy(mem, (void *)¤t->thread.fpu.fcr31, + dbg_reg_def[regno].size); + goto out; + } else if (regno == 71) { + /* Ignore the fir (register 71) */ + memset(mem, 0, dbg_reg_def[regno].size); + goto out; + } + fp_reg = dbg_reg_def[regno].offset; + memcpy(mem, (void *)¤t->thread.fpu.fpr[fp_reg], + dbg_reg_def[regno].size); + } + +out: + return dbg_reg_def[regno].name; + +} + void arch_kgdb_breakpoint(void) { __asm__ __volatile__( @@ -84,64 +229,6 @@ static int compute_signal(int tt) return SIGHUP; /* default for things we don't know about */ } -void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - int reg; - -#if (KGDB_GDB_REG_SIZE == 32) - u32 *ptr = (u32 *)gdb_regs; -#else - u64 *ptr = (u64 *)gdb_regs; -#endif - - for (reg = 0; reg < 32; reg++) - *(ptr++) = regs->regs[reg]; - - *(ptr++) = regs->cp0_status; - *(ptr++) = regs->lo; - *(ptr++) = regs->hi; - *(ptr++) = regs->cp0_badvaddr; - *(ptr++) = regs->cp0_cause; - *(ptr++) = regs->cp0_epc; - - /* FP REGS */ - if (!(current && (regs->cp0_status & ST0_CU1))) - return; - - save_fp(current); - for (reg = 0; reg < 32; reg++) - *(ptr++) = current->thread.fpu.fpr[reg]; -} - -void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - int reg; - -#if (KGDB_GDB_REG_SIZE == 32) - const u32 *ptr = (u32 *)gdb_regs; -#else - const u64 *ptr = (u64 *)gdb_regs; -#endif - - for (reg = 0; reg < 32; reg++) - regs->regs[reg] = *(ptr++); - - regs->cp0_status = *(ptr++); - regs->lo = *(ptr++); - regs->hi = *(ptr++); - regs->cp0_badvaddr = *(ptr++); - regs->cp0_cause = *(ptr++); - regs->cp0_epc = *(ptr++); - - /* FP REGS from current */ - if (!(current && (regs->cp0_status & ST0_CU1))) - return; - - for (reg = 0; reg < 32; reg++) - current->thread.fpu.fpr[reg] = *(ptr++); - restore_fp(current); -} - /* * Similar to regs_to_gdb_regs() except that process is sleeping and so * we may not be able to get all the info. -- 1.6.3.3 From jason.wessel@windriver.com Thu Aug 5 16:39:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 16:39:04 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:41181 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493354Ab0HEOin (ORCPT ); Thu, 5 Aug 2010 16:38:43 +0200 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id o75EcN7R000427; Thu, 5 Aug 2010 07:38:23 -0700 (PDT) Received: from ala-mail06.corp.ad.wrs.com ([147.11.57.147]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 5 Aug 2010 07:38:23 -0700 Received: from localhost.localdomain ([172.25.32.35]) by ala-mail06.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 5 Aug 2010 07:38:23 -0700 From: Jason Wessel To: torvalds@linux-foundation.org Cc: linux-kernel@vger.kernel.org, kgdb-bugreport@lists.sourceforge.net, Jason Wessel , Dongdong Deng , linux-mips@linux-mips.org Subject: [PATCH 15/17] kgdb,mips: remove unused kgdb_cpu_doing_single_step operations Date: Thu, 5 Aug 2010 09:37:56 -0500 Message-Id: <1281019078-6636-16-git-send-email-jason.wessel@windriver.com> X-Mailer: git-send-email 1.6.4.rc1 In-Reply-To: <1281019078-6636-15-git-send-email-jason.wessel@windriver.com> References: <1281019078-6636-1-git-send-email-jason.wessel@windriver.com> <1281019078-6636-2-git-send-email-jason.wessel@windriver.com> <1281019078-6636-3-git-send-email-jason.wessel@windriver.com> <1281019078-6636-4-git-send-email-jason.wessel@windriver.com> <1281019078-6636-5-git-send-email-jason.wessel@windriver.com> <1281019078-6636-6-git-send-email-jason.wessel@windriver.com> <1281019078-6636-7-git-send-email-jason.wessel@windriver.com> <1281019078-6636-8-git-send-email-jason.wessel@windriver.com> <1281019078-6636-9-git-send-email-jason.wessel@windriver.com> <1281019078-6636-10-git-send-email-jason.wessel@windriver.com> <1281019078-6636-11-git-send-email-jason.wessel@windriver.com> <1281019078-6636-12-git-send-email-jason.wessel@windriver.com> <1281019078-6636-13-git-send-email-jason.wessel@windriver.com> <1281019078-6636-14-git-send-email-jason.wessel@windriver.com> <1281019078-6636-15-git-send-email-jason.wessel@windriver.com> X-OriginalArrivalTime: 05 Aug 2010 14:38:23.0449 (UTC) FILETIME=[DB5C1C90:01CB34AB] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27596 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jason.wessel@windriver.com Precedence: bulk X-list: linux-mips The mips kgdb specific code does not support software or HW single stepping so it should not implement Signed-off-by: Jason Wessel Signed-off-by: Dongdong Deng Acked-by: Ralf Baechle CC: linux-mips@linux-mips.org --- arch/mips/kernel/kgdb.c | 8 +------- 1 files changed, 1 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index 5e76c2d..1f4e2fa 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -329,7 +329,7 @@ static struct notifier_block kgdb_notifier = { }; /* - * Handle the 's' and 'c' commands + * Handle the 'c' command */ int kgdb_arch_handle_exception(int vector, int signo, int err_code, char *remcom_in_buffer, char *remcom_out_buffer, @@ -337,20 +337,14 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code, { char *ptr; unsigned long address; - int cpu = smp_processor_id(); switch (remcom_in_buffer[0]) { - case 's': case 'c': /* handle the optional parameter */ ptr = &remcom_in_buffer[1]; if (kgdb_hex2long(&ptr, &address)) regs->cp0_epc = address; - atomic_set(&kgdb_cpu_doing_single_step, -1); - if (remcom_in_buffer[0] == 's') - atomic_set(&kgdb_cpu_doing_single_step, cpu); - return 0; } -- 1.6.3.3 From ralf@linux-mips.org Thu Aug 5 20:25:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 20:25:54 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46120 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493382Ab0HESZv (ORCPT ); Thu, 5 Aug 2010 20:25:51 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o75IPnF0007967; Thu, 5 Aug 2010 19:25:49 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o75IPlGN007965; Thu, 5 Aug 2010 19:25:47 +0100 Date: Thu, 5 Aug 2010 19:25:47 +0100 From: Ralf Baechle To: "Anoop P.A." Cc: linux-mips Subject: Re: file corruption with highmem kernel Message-ID: <20100805182547.GB1382@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27597 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Aug 05, 2010 at 06:43:50AM -0700, Anoop P.A. wrote: > With a slightly modified patched (copied below) I have reached a point > where I am no more seeing errors like segmentation fault, bus error > (which was due to memory corruption I believe). > How ever I am still seeing some kind of file corruption. > > I believe this file corruption happening because cache is not getting > invalidated before a highmem dma. I am not sure which routine to call to > invalidate cache for a highmem address. Since you're running on an RM9000 class CPU, why don't just use a 64-bit kernel? Highmem is just so f*cking insane that you want to avoid it like French kisses from a zombie suffering ebola. If you have DMA restrictions then you may consider reusing ZONE_DMA. That said, a word on the history of the MIPS highmem code. It was written for a company who in the early stages of the 64-bit kernel didn't want to be the first through the minefield in 2001. That CPU had full coherency and no cache aliases so arch/mips/mm/dma-*.c did not need any code to support it at all and for many years after that everybody either had a small 32-bit system that didn't need highmem or went 64-bit right away so the gaps in the code while well known were never fixed up ... I'm a bit surprised that the patch posted actually made things work better for you since it entirely avoids flushing of highmem pages. The code as it was originally written using page_address() will perform cacheflushes for highmem pages as well - but only for highmem pages are actually are mapped. That is your code will flush less pages than the existing code. Ralf From julia@diku.dk Thu Aug 5 22:17:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Aug 2010 22:17:32 +0200 (CEST) Received: from mgw2.diku.dk ([130.225.96.92]:52713 "EHLO mgw2.diku.dk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493388Ab0HEURZ (ORCPT ); Thu, 5 Aug 2010 22:17:25 +0200 Received: from localhost (localhost [127.0.0.1]) by mgw2.diku.dk (Postfix) with ESMTP id CFF6219BF02; Thu, 5 Aug 2010 22:17:23 +0200 (CEST) Received: from mgw2.diku.dk ([127.0.0.1]) by localhost (mgw2.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 29930-20; Thu, 5 Aug 2010 22:17:22 +0200 (CEST) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw2.diku.dk (Postfix) with ESMTP id 9703219BF01; Thu, 5 Aug 2010 22:17:22 +0200 (CEST) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id 3CD5B6DFBB6; Thu, 5 Aug 2010 22:16:13 +0200 (CEST) Received: by ask.diku.dk (Postfix, from userid 3767) id 7CA2D200C3; Thu, 5 Aug 2010 22:17:22 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id 72E07200BD; Thu, 5 Aug 2010 22:17:22 +0200 (CEST) Date: Thu, 5 Aug 2010 22:17:22 +0200 (CEST) From: Julia Lawall To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH 2/42] arch/mips/kernel: Adjust confusing if indentation Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27598 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julia@diku.dk Precedence: bulk X-list: linux-mips From: Julia Lawall Indent the branch of an if. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // @r disable braces4@ position p1,p2; statement S1,S2; @@ ( if (...) { ... } | if (...) S1@p1 S2@p2 ) @script:python@ p1 << r.p1; p2 << r.p2; @@ if (p1[0].column == p2[0].column): cocci.print_main("branch",p1) cocci.print_secs("after",p2) // Signed-off-by: Julia Lawall --- arch/mips/kernel/kspd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c index 80e2ba6..29811f0 100644 --- a/arch/mips/kernel/kspd.c +++ b/arch/mips/kernel/kspd.c @@ -251,7 +251,7 @@ void sp_work_handle_request(void) memset(&tz, 0, sizeof(tz)); if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv, (int)&tz, 0, 0)) == 0) - ret.retval = tv.tv_sec; + ret.retval = tv.tv_sec; break; case MTSP_SYSCALL_EXIT: From ralf@linux-mips.org Fri Aug 6 11:22:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Aug 2010 11:22:40 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52490 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492069Ab0HFJWc (ORCPT ); Fri, 6 Aug 2010 11:22:32 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o769MTpA027589; Fri, 6 Aug 2010 10:22:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o769MSMQ027587; Fri, 6 Aug 2010 10:22:28 +0100 Date: Fri, 6 Aug 2010 10:22:28 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Remove unused task_struct.trap_no field. Message-ID: <20100806092227.GA27524@linux-mips.org> References: <1280872659-27372-1-git-send-email-ddaney@caviumnetworks.com> <20100804233013.GA28115@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100804233013.GA28115@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27599 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Aug 05, 2010 at 12:30:13AM +0100, Ralf Baechle wrote: > Thanks, applied. Btw, this field was unused since at least Linux 1.1.68, that is late 1994 :-) Ralf From Anoop_P.A@pmc-sierra.com Fri Aug 6 12:12:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Aug 2010 12:12:18 +0200 (CEST) Received: from bby1mta03.pmc-sierra.com ([216.241.235.118]:60762 "EHLO bby1mta03.pmc-sierra.bc.ca" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493453Ab0HFKMO convert rfc822-to-8bit (ORCPT ); Fri, 6 Aug 2010 12:12:14 +0200 Received: from bby1mta03.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id 1334710700E6; Fri, 6 Aug 2010 03:12:03 -0700 (PDT) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (BBY1EXG02.pmc-sierra.bc.ca [216.241.231.167]) by bby1mta03.pmc-sierra.bc.ca (Postfix) with SMTP id F20A710700EA; Fri, 6 Aug 2010 03:12:02 -0700 (PDT) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.157]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.4675); Fri, 6 Aug 2010 03:12:03 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 8BIT Subject: RE: file corruption with highmem kernel Date: Fri, 6 Aug 2010 03:12:00 -0700 Message-ID: In-Reply-To: <20100805182547.GB1382@linux-mips.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: file corruption with highmem kernel Thread-Index: Acs0y8bnYm14g7FHRaW+W2PRh1m8QQAgmpOA References: <20100805182547.GB1382@linux-mips.org> From: "Anoop P.A." To: "Ralf Baechle" Cc: "linux-mips" X-OriginalArrivalTime: 06 Aug 2010 10:12:03.0058 (UTC) FILETIME=[D0B7B520:01CB354F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27600 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips > > Since you're running on an RM9000 class CPU, why don't just use a 64-bit > kernel? Highmem is just so f*cking insane that you want to avoid it like > French kisses from a zombie suffering ebola. If you have DMA restrictions > then you may consider reusing ZONE_DMA. [Anoop P.A.] I understand that I am working on 64 bit kernel in parallel, DMA issue made me concentrate on highmem support as immediate option. > small 32-bit system that didn't need highmem or went 64-bit right away so > the gaps in the code while well known were never fixed up ... [Anoop P.A.] I presume with decreased value of RAM, more 32 bit machines will come with bulk of memory pretty soon to the world of highmem > > I'm a bit surprised that the patch posted actually made things work better > for you since it entirely avoids flushing of highmem pages. The code as > it > was originally written using page_address() will perform cacheflushes > for highmem pages as well - but only for highmem pages are actually are > mapped. That is your code will flush less pages than the existing code. [Anoop P.A.] I confirmed it, calling __dma_sync for highmem map address occasionally causes memory corruption ( reports bus error , segmentation fault etc..) . Blowing entire scache (I understand it is pain) for highmem pages fixed my file corruption issue --- linux-2.6.18/arch/mips/mm/dma-noncoherent.c 2006-08-23 23:16:07.000000000 +0530 +++ linux-2.6.18/arch/mips/mm/dma-noncoherent.c 2010-08-06 20:48:36.000000000 +0530 @@ -15,6 +15,7 @@ #include #include +#include /* * Warning on the terminology - Linux calls an uncached area coherent; @@ -131,13 +132,21 @@ for (i = 0; i < nents; i++, sg++) { unsigned long addr; + if (!PageHighMem(sg->page)) + { + addr = (unsigned long)page_address(sg->page) + sg->offset; + __dma_sync(addr, sg->length, direction); + } + else + { + /*blasting entire cache for all the highmem page's might be over head + But __dma_sync is failing for mapped highmem pages, so this is the + easiest solution for time being*/ + blast_scache32(); /*RM9000 sc_line=32 */ + } - addr = (unsigned long) page_address(sg->page); - if (addr) { - __dma_sync(addr + sg->offset, sg->length, direction); - sg->dma_address = (dma_addr_t)page_to_phys(sg->page) + sg->dma_address = (dma_addr_t)page_to_phys(sg->page) + sg->offset; - } } return nents; Thanks Anoop From ricmm@gentoo.org Fri Aug 6 17:43:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Aug 2010 17:43:42 +0200 (CEST) Received: from smtp.gentoo.org ([140.211.166.183]:48916 "EHLO smtp.gentoo.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491009Ab0HFPnh (ORCPT ); Fri, 6 Aug 2010 17:43:37 +0200 Received: from localhost.localdomain (unknown [201.208.61.81]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPSA id 04E5A1B406E; Fri, 6 Aug 2010 15:43:23 +0000 (UTC) From: Ricardo Mendoza To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Ricardo Mendoza Subject: [PATCH] MIPS: RM7000: Symbol should be static Date: Fri, 6 Aug 2010 11:12:57 -0430 Message-Id: <1281109377-9576-1-git-send-email-ricmm@gentoo.org> X-Mailer: git-send-email 1.6.4.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27601 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ricmm@gentoo.org Precedence: bulk X-list: linux-mips arch/mips/mm/sc-rm7k.c defines tcache_size globally. Make it static. Signed-off-by: Ricardo Mendoza --- arch/mips/mm/sc-rm7k.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index 1ef75cd..274af3b 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c @@ -30,7 +30,7 @@ #define tc_lsize 32 extern unsigned long icache_way_size, dcache_way_size; -unsigned long tcache_size; +static unsigned long tcache_size; #include -- 1.6.4.4 From ralf@linux-mips.org Fri Aug 6 18:05:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Aug 2010 18:05:14 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:34502 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492582Ab0HFQFG (ORCPT ); Fri, 6 Aug 2010 18:05:06 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o76G42pP004153; Fri, 6 Aug 2010 17:04:02 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o76G403I004151; Fri, 6 Aug 2010 17:04:00 +0100 Date: Fri, 6 Aug 2010 17:04:00 +0100 From: Ralf Baechle To: Andrea Gelmini Cc: gelma@gelma.net, Jason Wessel , Martin Hicks , linux-mips@linux-mips.org Subject: Re: [PATCH 01/15] arch: mips: kernel: Fix a typo. Message-ID: <20100806160400.GA4034@linux-mips.org> References: <1281016299-23958-1-git-send-email-andrea.gelmini@gelma.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1281016299-23958-1-git-send-email-andrea.gelmini@gelma.net> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Fri Aug 6 18:11:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Aug 2010 18:11:44 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46496 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492463Ab0HFQLk (ORCPT ); Fri, 6 Aug 2010 18:11:40 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o76GAtqQ004405; Fri, 6 Aug 2010 17:10:55 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o76GAsbA004399; Fri, 6 Aug 2010 17:10:54 +0100 Date: Fri, 6 Aug 2010 17:10:54 +0100 From: Ralf Baechle To: Julia Lawall Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: Re: [PATCH 2/42] arch/mips/kernel: Adjust confusing if indentation Message-ID: <20100806161054.GB4034@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27603 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks Julia, Ralf From ralf@linux-mips.org Fri Aug 6 18:13:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Aug 2010 18:14:04 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46510 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492463Ab0HFQN5 (ORCPT ); Fri, 6 Aug 2010 18:13:57 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o76GDkkb004560; Fri, 6 Aug 2010 17:13:46 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o76GDkY7004558; Fri, 6 Aug 2010 17:13:46 +0100 Date: Fri, 6 Aug 2010 17:13:46 +0100 From: Ralf Baechle To: Ricardo Mendoza Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: RM7000: Symbol should be static Message-ID: <20100806161346.GC4034@linux-mips.org> References: <1281109377-9576-1-git-send-email-ricmm@gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1281109377-9576-1-git-send-email-ricmm@gentoo.org> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27604 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Fri Aug 6 18:45:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Aug 2010 18:45:45 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60739 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493045Ab0HFQpm (ORCPT ); Fri, 6 Aug 2010 18:45:42 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o76GjTLJ005392; Fri, 6 Aug 2010 17:45:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o76GjQVP005391; Fri, 6 Aug 2010 17:45:26 +0100 Date: Fri, 6 Aug 2010 17:45:26 +0100 From: Ralf Baechle To: Deng-Cheng Zhu Cc: linux-mips@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Subject: Re: [PATCH v6 2/7] MIPS: use generic atomic64 in non-64bit kernels Message-ID: <20100806164526.GD4034@linux-mips.org> References: <1276058130-25851-1-git-send-email-dengcheng.zhu@gmail.com> <1276058130-25851-3-git-send-email-dengcheng.zhu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276058130-25851-3-git-send-email-dengcheng.zhu@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27605 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks Deng-Cheng! Ralf From namhyung@gmail.com Sun Aug 8 21:58:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Aug 2010 21:58:12 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:58649 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491855Ab0HHT6J (ORCPT ); Sun, 8 Aug 2010 21:58:09 +0200 Received: by pxi13 with SMTP id 13so3974339pxi.36 for ; Sun, 08 Aug 2010 12:58:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=5xuStoK5steW+0AhGPQfh17VvJVIIF6bWJ2Ule4q4LA=; b=RWFAS18P76CmhyyJaihIlt+V6e3d/kHu4WSmkn1cn7f0Qqoy/QmcqOAkuR/6fW/0SL eq2km4M1Db8Q7uczjr7k3fuVphZ+A2GEt2kP2IliN6bExgUJl7D4Yl6kWsLrh+S6dvap x+eolbK1V/+jWDmrhK2qjrThp9qI8j082xbt0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=QSsXA1DBtF9BdVsgX3Rn8ZlNzdAdscwe6PYoICFUghlD8JBEhNLxgQFciatTyldVCc caBo/aqT5tvw4VxRvjgs4ndPI44qZ0V4Q6jViM2Ku7VL9JQSbjc5QiUjMvxVlW0G1Djb 4epTBEL6sH7b21ybWJxnO8mgxbCtfWUcP+RWQ= Received: by 10.142.141.8 with SMTP id o8mr12980329wfd.53.1281297482567; Sun, 08 Aug 2010 12:58:02 -0700 (PDT) Received: from localhost.localdomain ([211.178.117.190]) by mx.google.com with ESMTPS id w8sm5494853wfd.19.2010.08.08.12.58.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 08 Aug 2010 12:58:02 -0700 (PDT) From: Namhyung Kim To: Ralf Baechle , linux-kernel@vger.kernel.org Cc: David Daney , linux-mips@linux-mips.org Subject: [PATCH] MIPS: remove RELOC_HIDE on __pa_symbol Date: Mon, 9 Aug 2010 04:57:36 +0900 Message-Id: <1281297456-2711-1-git-send-email-namhyung@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27606 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: namhyung@gmail.com Precedence: bulk X-list: linux-mips remove unneccessary use of RELOC_HIDE(). It does simple addition of ptr and offset and in this case (offset 0) does practically nothing. It does NOT do anything with linker relocation. Signed-off-by: Namhyung Kim --- arch/mips/include/asm/page.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index a16beaf..f7e2684 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -150,7 +150,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) #endif #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) -#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) +#define __pa_symbol(x) __pa(x) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) -- 1.7.0.4 From david.s.daney@gmail.com Mon Aug 9 07:15:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Aug 2010 07:15:17 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:64063 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491151Ab0HIFPN (ORCPT ); Mon, 9 Aug 2010 07:15:13 +0200 Received: by iwn3 with SMTP id 3so3842949iwn.36 for ; Sun, 08 Aug 2010 22:15:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; bh=/gYRndlf6WrC/riBaCbtWWeGawIEObsdB+5/4jtFqxk=; b=ZhJZ76d9SXqEnWkq99x/lhqtGlCkYeFFvAq1bWalp25HbVtfnTKAfjtIXbb6YhEvsI RO913NVAy+l1C6tOVzDinSJZFosNMxG/D6+ChQfePByvete0xbCG3VNLkF/2OcVpxWgQ 0mdt/yNYWENa0s9eZ9frfmdZGO/Lb72RXQCrk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=o5X8c7KeO2Smtvje2x2bucOftwQlAQfzmMSkVYKcMegI3rqbE8VzmAV3Dfy9E1HRFz awb9VGL1qBlm1UeQOxsya1W5E8r9fMNeX7SoSt3uuUS+yQgzlWXv82YRB483246IxgzW DSgOxW1+SufVdujBVBY/9/NrPyHKMZvvnxa/w= Received: by 10.231.152.210 with SMTP id h18mr18656422ibw.18.1281330911034; Sun, 08 Aug 2010 22:15:11 -0700 (PDT) Received: from dd_xps.caveonetworks.com (adsl-67-127-52-52.dsl.pltn13.pacbell.net [67.127.52.52]) by mx.google.com with ESMTPS id g31sm4295492ibh.16.2010.08.08.22.15.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 08 Aug 2010 22:15:09 -0700 (PDT) Message-ID: <4C5F8ED8.90301@gmail.com> Date: Sun, 08 Aug 2010 22:15:04 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.7) Gecko/20100720 Fedora/3.1.1-1.fc13 Thunderbird/3.1.1 MIME-Version: 1.0 To: Namhyung Kim CC: Ralf Baechle , linux-kernel@vger.kernel.org, David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: remove RELOC_HIDE on __pa_symbol References: <1281297456-2711-1-git-send-email-namhyung@gmail.com> In-Reply-To: <1281297456-2711-1-git-send-email-namhyung@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27607 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.s.daney@gmail.com Precedence: bulk X-list: linux-mips On 08/08/2010 12:57 PM, Namhyung Kim wrote: > remove unneccessary use of RELOC_HIDE(). It does simple addition of ptr and > offset and in this case (offset 0) does practically nothing. It does NOT do > anything with linker relocation. > Maybe you could explain in more detail the problems you are having with the current definition of __pa_symbol(). I would be hesitant to change this bit of black magic unless there is a concrete problem you are trying to solve. David Daney > Signed-off-by: Namhyung Kim > --- > arch/mips/include/asm/page.h | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h > index a16beaf..f7e2684 100644 > --- a/arch/mips/include/asm/page.h > +++ b/arch/mips/include/asm/page.h > @@ -150,7 +150,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; > ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) > #endif > #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) > -#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) > +#define __pa_symbol(x) __pa(x) > > #define pfn_to_kaddr(pfn) __va((pfn)<< PAGE_SHIFT) > From ralf@linux-mips.org Mon Aug 9 14:21:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Aug 2010 14:21:59 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59175 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491992Ab0HIMVz (ORCPT ); Mon, 9 Aug 2010 14:21:55 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o79CLnUQ023187; Mon, 9 Aug 2010 13:21:50 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o79CLm2K023185; Mon, 9 Aug 2010 13:21:48 +0100 Date: Mon, 9 Aug 2010 13:21:47 +0100 From: Ralf Baechle To: David Daney Cc: Namhyung Kim , linux-kernel@vger.kernel.org, David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: remove RELOC_HIDE on __pa_symbol Message-ID: <20100809122147.GA23053@linux-mips.org> References: <1281297456-2711-1-git-send-email-namhyung@gmail.com> <4C5F8ED8.90301@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C5F8ED8.90301@gmail.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27608 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Aug 08, 2010 at 10:15:04PM -0700, David Daney wrote: > On 08/08/2010 12:57 PM, Namhyung Kim wrote: > >remove unneccessary use of RELOC_HIDE(). It does simple addition of ptr and > >offset and in this case (offset 0) does practically nothing. It does NOT do > >anything with linker relocation. > > > > Maybe you could explain in more detail the problems you are having > with the current definition of __pa_symbol(). I would be hesitant > to change this bit of black magic unless there is a concrete problem > you are trying to solve. RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad (lmo) rsp. 8431fd094d625b94d364fe393076ccef88e6ce18 (kernel.org). A discussion can be found in lkml posting a2ebde260608230500o3407b108hc03debb9da6e62c@mail.gmail.com> which is archived at http://lists.linuxcoding.com/kernel/2006-q3/msg17360.html I felt this was dubious by the time it was added and probably should go? Ralf From namhyung@gmail.com Tue Aug 10 05:07:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Aug 2010 05:07:26 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:51510 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490956Ab0HJDHW (ORCPT ); Tue, 10 Aug 2010 05:07:22 +0200 Received: by pwi9 with SMTP id 9so1893624pwi.36 for ; Mon, 09 Aug 2010 20:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=OJ1dGkoJee+9dW6WkbFF6bBKwwa0ssIwvgFhEXrnlBg=; b=eZynmNr+PuvwG1GgZIzVPWy2s6jyLhoVYPrbVeir2N0yxFfu7aJWR9STdgMA4enayX u5YYEDwbviib+NRVEmZHwQ/OZEM4NABYHW0aumbx+ksZSOi9G4hlg6YYL/4Lp5oh3vij bSi0zUQqS4YVWvxElG2PGgmsaXXSS6mt+fdk4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=u0mUZfVKMfjQMCMlTQUtYrZnrXYF7+g6iTLdj7fENDi8QUvJIZIHD9qS/VJKVrI3OI 4sbW3B9PahnkpHw2Y+/0DyD2tLfDc+3JMQUT9c8x8rbOHy1uXM5dNb+un0WVqAmAeNT+ dUMwzEhqY78u7y8p0BsBtRUJGA+HqBEIwiP1Y= Received: by 10.142.194.15 with SMTP id r15mr14445963wff.306.1281409634291; Mon, 09 Aug 2010 20:07:14 -0700 (PDT) Received: from [192.168.15.10] ([211.178.117.190]) by mx.google.com with ESMTPS id n2sm7232496wfl.1.2010.08.09.20.07.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 09 Aug 2010 20:07:13 -0700 (PDT) Subject: Re: [PATCH] MIPS: remove RELOC_HIDE on __pa_symbol From: Namhyung Kim To: Ralf Baechle Cc: David Daney , linux-kernel@vger.kernel.org, David Daney , linux-mips@linux-mips.org In-Reply-To: <20100809122147.GA23053@linux-mips.org> References: <1281297456-2711-1-git-send-email-namhyung@gmail.com> <4C5F8ED8.90301@gmail.com> <20100809122147.GA23053@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Tue, 10 Aug 2010 12:07:08 +0900 Message-ID: <1281409628.1670.11.camel@leonhard> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27609 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: namhyung@gmail.com Precedence: bulk X-list: linux-mips 2010-08-09 (ì›”), 13:21 +0100, Ralf Baechle: > On Sun, Aug 08, 2010 at 10:15:04PM -0700, David Daney wrote: > > Maybe you could explain in more detail the problems you are having > > with the current definition of __pa_symbol(). I would be hesitant > > to change this bit of black magic unless there is a concrete problem > > you are trying to solve. > > RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad > (lmo) rsp. 8431fd094d625b94d364fe393076ccef88e6ce18 (kernel.org). A > discussion can be found in lkml posting > a2ebde260608230500o3407b108hc03debb9da6e62c@mail.gmail.com> which is > archived at > > http://lists.linuxcoding.com/kernel/2006-q3/msg17360.html > > I felt this was dubious by the time it was added and probably should go? > > Ralf Hi, I've sent basically same patch to x86 folks [1] and they said there is a possiblility of miscompilation on gcc 3. I am not sure the same goes here on mips but it might be safer to keep it. Sorry for the noise ;-( [1] http://lkml.org/lkml/2010/8/8/138 -- Regards, Namhyung Kim From julia@diku.dk Wed Aug 11 12:12:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Aug 2010 12:12:12 +0200 (CEST) Received: from mgw2.diku.dk ([130.225.96.92]:49105 "EHLO mgw2.diku.dk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492325Ab0HKKMG (ORCPT ); Wed, 11 Aug 2010 12:12:06 +0200 Received: from localhost (localhost [127.0.0.1]) by mgw2.diku.dk (Postfix) with ESMTP id 9705D19BEA1; Wed, 11 Aug 2010 12:12:02 +0200 (CEST) Received: from mgw2.diku.dk ([127.0.0.1]) by localhost (mgw2.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 24288-10; Wed, 11 Aug 2010 12:12:00 +0200 (CEST) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw2.diku.dk (Postfix) with ESMTP id 1F36919BE9F; Wed, 11 Aug 2010 12:12:00 +0200 (CEST) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id DBDA96DFD0B; Wed, 11 Aug 2010 12:10:41 +0200 (CEST) Received: by ask.diku.dk (Postfix, from userid 3767) id F3959200C3; Wed, 11 Aug 2010 12:11:59 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id EBEC7200BB; Wed, 11 Aug 2010 12:11:59 +0200 (CEST) Date: Wed, 11 Aug 2010 12:11:59 +0200 (CEST) From: Julia Lawall To: Pat Gefre , linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH 5/5] drivers/serial: Return -ENOMEM on memory allocation failure Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27610 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julia@diku.dk Precedence: bulk X-list: linux-mips From: Julia Lawall In this code, 0 is returned on memory allocation failure, even though other failures return -ENOMEM or other similar values. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // @@ expression ret; expression x,e1,e2,e3; @@ ret = 0 ... when != ret = e1 *x = \(kmalloc\|kcalloc\|kzalloc\)(...) ... when != ret = e2 if (x == NULL) { ... when != ret = e3 return ret; } // Signed-off-by: Julia Lawall --- I believe this code also leaks earlier instances of port, which are only referenced by card_ptr, which is freed in the error handling code at the end of the function. A lot of operations are done on port on each iteration, however, so I'm not sure whether it is good enough to just free them. Perhaps there is some way to call ioc3uart_remove? drivers/serial/ioc3_serial.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/serial/ioc3_serial.c b/drivers/serial/ioc3_serial.c index 93de907..800c546 100644 --- a/drivers/serial/ioc3_serial.c +++ b/drivers/serial/ioc3_serial.c @@ -2044,6 +2044,7 @@ ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd) if (!port) { printk(KERN_WARNING "IOC3 serial memory not available for port\n"); + ret = -ENOMEM; goto out4; } spin_lock_init(&port->ip_lock); From julia@diku.dk Wed Aug 11 18:23:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Aug 2010 18:23:36 +0200 (CEST) Received: from mgw2.diku.dk ([130.225.96.92]:53923 "EHLO mgw2.diku.dk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492319Ab0HKQXb (ORCPT ); Wed, 11 Aug 2010 18:23:31 +0200 Received: from localhost (localhost [127.0.0.1]) by mgw2.diku.dk (Postfix) with ESMTP id B804F19BEA9; Wed, 11 Aug 2010 18:23:29 +0200 (CEST) Received: from mgw2.diku.dk ([127.0.0.1]) by localhost (mgw2.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 02245-20; Wed, 11 Aug 2010 18:23:28 +0200 (CEST) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw2.diku.dk (Postfix) with ESMTP id 7A13219BEA7; Wed, 11 Aug 2010 18:23:28 +0200 (CEST) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id CD5CB6DF894; Wed, 11 Aug 2010 18:22:09 +0200 (CEST) Received: by ask.diku.dk (Postfix, from userid 3767) id 55A32200C3; Wed, 11 Aug 2010 18:23:28 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id 4EE7C200BB; Wed, 11 Aug 2010 18:23:28 +0200 (CEST) Date: Wed, 11 Aug 2010 18:23:28 +0200 (CEST) From: Julia Lawall To: Patrick Gefre Cc: linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: Re: [PATCH 5/5] drivers/serial: Return -ENOMEM on memory allocation failure In-Reply-To: <4C62C8F3.3090405@sgi.com> Message-ID: References: <4C62C8F3.3090405@sgi.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27611 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julia@diku.dk Precedence: bulk X-list: linux-mips > > I believe this code also leaks earlier instances of port, which are only > > referenced by card_ptr, which is freed in the error handling code at the > > end of the function. A lot of operations are done on port on each > > iteration, however, so I'm not sure whether it is good enough to just free > > them. Perhaps there is some way to call ioc3uart_remove? > > > > Yes you are right, there should be something like this for out4: > > out4: > for (phys_port = 0; phys_port < PORTS_PER_CARD; phys_port++) { > port = card_ptr->ic_port[phys_port].icp_port; > if (port) { > pci_free_consistent(port->ip_idd->pdev, > TOTAL_RING_BUF_SIZE, > (void *)port->ip_cpu_ringbuf, > port->ip_dma_ringbuf); > kfree(port); > } > } > kfree(card_ptr); > return ret; Actually, pci_alloc_consistent is only called when phys_port is 0. In the subsequent cases, the ip_dma_ringbuf field is just initialized to the previous value. So it could be: out4: for (phys_port = 0; phys_port < PORTS_PER_CARD; phys_port++) { port = card_ptr->ic_port[phys_port].icp_port; if (port) { if (phys_port == 0) pci_free_consistent(port->ip_idd->pdev, TOTAL_RING_BUF_SIZE, (void *)port->ip_cpu_ringbuf, port->ip_dma_ringbuf); kfree(port); } } kfree(card_ptr); return ret; julia From pfg@sgi.com Wed Aug 11 18:36:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Aug 2010 18:36:11 +0200 (CEST) Received: from relay2.sgi.com ([192.48.179.30]:49849 "EHLO relay.sgi.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492339Ab0HKQgH (ORCPT ); Wed, 11 Aug 2010 18:36:07 +0200 Received: from estes.americas.sgi.com (estes.americas.sgi.com [128.162.236.10]) by relay2.corp.sgi.com (Postfix) with ESMTP id 01F57304075; Wed, 11 Aug 2010 08:59:47 -0700 (PDT) Received: from [128.162.232.67] (pfglinux.americas.sgi.com [128.162.232.67]) by estes.americas.sgi.com (Postfix) with ESMTP id 84D2C700016A; Wed, 11 Aug 2010 10:59:47 -0500 (CDT) Message-ID: <4C62C8F3.3090405@sgi.com> Date: Wed, 11 Aug 2010 10:59:47 -0500 From: Patrick Gefre User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Julia Lawall Cc: linux-ia64@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: Re: [PATCH 5/5] drivers/serial: Return -ENOMEM on memory allocation failure References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27612 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pfg@sgi.com Precedence: bulk X-list: linux-mips Julia Lawall wrote: > From: Julia Lawall > > In this code, 0 is returned on memory allocation failure, even though other > failures return -ENOMEM or other similar values. > > A simplified version of the semantic match that finds this problem is as > follows: (http://coccinelle.lip6.fr/) > > // > @@ > expression ret; > expression x,e1,e2,e3; > @@ > > ret = 0 > ... when != ret = e1 > *x = \(kmalloc\|kcalloc\|kzalloc\)(...) > ... when != ret = e2 > if (x == NULL) { ... when != ret = e3 > return ret; > } > // > > Signed-off-by: Julia Lawall > Signed-off-by: Pat Gefre > --- > I believe this code also leaks earlier instances of port, which are only > referenced by card_ptr, which is freed in the error handling code at the > end of the function. A lot of operations are done on port on each > iteration, however, so I'm not sure whether it is good enough to just free > them. Perhaps there is some way to call ioc3uart_remove? > Yes you are right, there should be something like this for out4: out4: for (phys_port = 0; phys_port < PORTS_PER_CARD; phys_port++) { port = card_ptr->ic_port[phys_port].icp_port; if (port) { pci_free_consistent(port->ip_idd->pdev, TOTAL_RING_BUF_SIZE, (void *)port->ip_cpu_ringbuf, port->ip_dma_ringbuf); kfree(port); } } kfree(card_ptr); return ret; > drivers/serial/ioc3_serial.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/serial/ioc3_serial.c b/drivers/serial/ioc3_serial.c > index 93de907..800c546 100644 > --- a/drivers/serial/ioc3_serial.c > +++ b/drivers/serial/ioc3_serial.c > @@ -2044,6 +2044,7 @@ ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd) > if (!port) { > printk(KERN_WARNING > "IOC3 serial memory not available for port\n"); > + ret = -ENOMEM; > goto out4; > } > spin_lock_init(&port->ip_lock); From biessmann@corscience.de Wed Aug 11 19:30:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Aug 2010 19:31:05 +0200 (CEST) Received: from moutng.kundenserver.de ([212.227.126.187]:62674 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492342Ab0HKRa6 convert rfc822-to-8bit (ORCPT ); Wed, 11 Aug 2010 19:30:58 +0200 Received: from corscience.de (DSL01.212.114.252.242.ip-pool.NEFkom.net [212.114.252.242]) by mrelayeu.kundenserver.de (node=mrbap1) with ESMTP (Nemesis) id 0Mg0GL-1OXJsq1xxd-00NIQg; Wed, 11 Aug 2010 18:50:01 +0200 Received: from localhost (unknown [192.168.102.9]) by corscience.de (Postfix) with ESMTP id 02D0E51F50; Wed, 11 Aug 2010 18:50:01 +0200 (CEST) Received: from abiessmann by localhost with local (Exim 4.72) (envelope-from ) id 1OjEV6-0006Em-WF; Wed, 11 Aug 2010 18:50:01 +0200 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= To: linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= , Ralf Baechle , linux-mips@linux-mips.org Subject: [PATCH] cavium-octeon: determine if helper should build Date: Wed, 11 Aug 2010 18:49:53 +0200 Message-Id: <1281545393-23690-1-git-send-email-biessmann@corscience.de> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-Provags-ID: V02:K0:Jg6lrylfCqiDt0vlsHVd2yft7HU2csdKNh3vg4BJJiD q/q57psZkgKO+xR9MOGijzkCwWxUw/7FZJvU/DyoLpjiwsMSzI hX5D58XzRrblau7jBM8vAB7evzjwrhrsI6AvJxzGcD4rxwQ7pY 6BLYDB7Vnau1Nsz2FtbQkTdWQ+L+9tE5066t2H53O7Auv4LvsR 3pBJcEml1zU61sc7rJF0A== Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27613 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: biessmann@corscience.de Precedence: bulk X-list: linux-mips This patch adds an config switch to determine if we need to build some workaround helper files. The staging driver octeon-ethernet references some symbols which are only built when PCI is enabled. The new config switch enables these symbols in bothe cases. Signed-off-by: Andreas Bießmann --- arch/mips/cavium-octeon/Kconfig | 4 ++++ arch/mips/cavium-octeon/executive/Makefile | 2 +- 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 094c17e..47323ca 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -83,3 +83,7 @@ config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC depends on CPU_CAVIUM_OCTEON + +config CAVIUM_OCTEON_HELPER + def_bool y + depends on OCTEON_ETHERNET || PCI diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile index 2fd66db..7f41c5b 100644 --- a/arch/mips/cavium-octeon/executive/Makefile +++ b/arch/mips/cavium-octeon/executive/Makefile @@ -11,4 +11,4 @@ obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o -obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-jtag.o +obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o -- 1.7.1 From David.Daney@caviumnetworks.com Wed Aug 11 19:41:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Aug 2010 19:41:23 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:6841 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492360Ab0HKRlT (ORCPT ); Wed, 11 Aug 2010 19:41:19 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 11 Aug 2010 09:56:21 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 Aug 2010 09:55:50 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 11 Aug 2010 09:55:50 -0700 Message-ID: <4C62D616.9050000@caviumnetworks.com> Date: Wed, 11 Aug 2010 09:55:50 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: =?UTF-8?B?QW5kcmVhcyBCaWXDn21hbm4=?= CC: linux-kernel@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] cavium-octeon: determine if helper should build References: <1281545393-23690-1-git-send-email-biessmann@corscience.de> In-Reply-To: <1281545393-23690-1-git-send-email-biessmann@corscience.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 11 Aug 2010 16:55:50.0573 (UTC) FILETIME=[0D81DDD0:01CB3976] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27614 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 08/11/2010 09:49 AM, Andreas Bießmann wrote: > This patch adds an config switch to determine if we need to build some > workaround helper files. > > The staging driver octeon-ethernet references some symbols which are only > built when PCI is enabled. The new config switch enables these symbols in > bothe cases. > > Signed-off-by: Andreas Bießmann Acked-by: David Daney > --- > arch/mips/cavium-octeon/Kconfig | 4 ++++ > arch/mips/cavium-octeon/executive/Makefile | 2 +- > 2 files changed, 5 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig > index 094c17e..47323ca 100644 > --- a/arch/mips/cavium-octeon/Kconfig > +++ b/arch/mips/cavium-octeon/Kconfig > @@ -83,3 +83,7 @@ config ARCH_SPARSEMEM_ENABLE > def_bool y > select SPARSEMEM_STATIC > depends on CPU_CAVIUM_OCTEON > + > +config CAVIUM_OCTEON_HELPER > + def_bool y > + depends on OCTEON_ETHERNET || PCI > diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile > index 2fd66db..7f41c5b 100644 > --- a/arch/mips/cavium-octeon/executive/Makefile > +++ b/arch/mips/cavium-octeon/executive/Makefile > @@ -11,4 +11,4 @@ > > obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o > > -obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-jtag.o > +obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o From fujita.tomonori@lab.ntt.co.jp Sat Aug 14 09:02:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 14 Aug 2010 09:02:47 +0200 (CEST) Received: from sh.osrg.net ([192.16.179.4]:55201 "EHLO sh.osrg.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491097Ab0HNHCm (ORCPT ); Sat, 14 Aug 2010 09:02:42 +0200 Received: from localhost (rose.osrg.net [10.76.0.1]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o7E72bxp002949; Sat, 14 Aug 2010 16:02:38 +0900 Date: Sat, 14 Aug 2010 16:02:37 +0900 To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, anemo@mba.ocn.ne.jp Subject: [PATCH] MIPS: TX49xx: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN From: FUJITA Tomonori Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-Id: <20100814160128H.fujita.tomonori@lab.ntt.co.jp> Lines: 25 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Sat, 14 Aug 2010 16:02:38 +0900 (JST) X-Virus-Scanned: clamav-milter 0.96.1 at sh X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27615 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fujita.tomonori@lab.ntt.co.jp Precedence: bulk X-list: linux-mips Architectures need to set ARCH_DMA_MINALIGN to the minimum DMA alignment (the commit a6eb9fe105d5de0053b261148cee56c94b4720ca). Defining ARCH_KMALLOC_MINALIGN doesn't work anymore. Signed-off-by: FUJITA Tomonori --- arch/mips/include/asm/mach-tx49xx/kmalloc.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h index b74caf6..ff9a8b8 100644 --- a/arch/mips/include/asm/mach-tx49xx/kmalloc.h +++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h @@ -1,6 +1,6 @@ #ifndef __ASM_MACH_TX49XX_KMALLOC_H #define __ASM_MACH_TX49XX_KMALLOC_H -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES #endif /* __ASM_MACH_TX49XX_KMALLOC_H */ -- 1.6.5 From wilbur512@gmail.com Sun Aug 15 05:20:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Aug 2010 05:20:28 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:48396 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491074Ab0HODUX (ORCPT ); Sun, 15 Aug 2010 05:20:23 +0200 Received: by qwe4 with SMTP id 4so4464927qwe.36 for ; Sat, 14 Aug 2010 20:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=IVo5kWR7Sjaw3hrcu2Dh2/Kc4+vCz41EeB8q2rPxXKs=; b=FgbX+7F/uVNYWqOXNKL6tcia9qy+aM6bRuNggg90Bek38pPa/+Wq9/TBj0hTpEBfi9 RlbCK4k8GQ4I97+1z5dVFB73bWRYabdl/NvOTbdsldr+lvQNsIw8xi2jj7GqmhELCSpy +nO92PkHjs/7enp6lXowUTlgBagWYin9CtLyo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=rQjF/F0LkwSGBH230pIDrcx0xcOCPfwI10lzaFlIk6i8wvqGNev6JCMny5ARaUzif8 e2X01amSBOGHZm/QhLeIikfbyUvqO8WyVDkDJf8By7576Jv/7WzNUl2KChnxXThIfo7U +1NAtoP7bNKA8obZKH0bmZX3iEXwJRZzyE1CI= MIME-Version: 1.0 Received: by 10.224.36.209 with SMTP id u17mr2204288qad.328.1281838403265; Sat, 14 Aug 2010 19:13:23 -0700 (PDT) Received: by 10.229.55.69 with HTTP; Sat, 14 Aug 2010 19:13:23 -0700 (PDT) Date: Sun, 15 Aug 2010 10:13:23 +0800 Message-ID: Subject: Clock Source in hrtimer From: "wilbur.chan" To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27616 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips I am planning to use linux 2.6.24 with hrtimer enabled and with CONFIG_NO_HZ on mips xlr 732. As we know, a monotomic increasing Clock Source is required to support hrtimer, whose cycles could be retrieved from clocksource->read function. However on xlr 732 ,there is only a 32 bits counter register, which would overflow in 4s ( 2^32 / 1GHZ = 4). How to solve this ? Thanks in advance From wuzhangjin@gmail.com Sun Aug 15 08:14:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Aug 2010 08:14:26 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:34733 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491062Ab0HOGOW (ORCPT ); Sun, 15 Aug 2010 08:14:22 +0200 Received: by wwb34 with SMTP id 34so4149975wwb.24 for ; Sat, 14 Aug 2010 23:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=nftAXQebPIsTErUrYNnz3pLj4zAAyJcRLyk9dzXvtzw=; b=pw5tRifUvRMcW0qWx82rLUG/05X7A0LsWPTSA8RxLZ2nyvkrT0ZwgphXGAbnopERab Ge0nennFHQNXBPkszbKdNzMVD8Bb7FVO7hkiV3Tf9gIzq21is/jfOiQ9pjOPSjOgTEPF ujQqvTb5Y6T2QrG0Ppoo6BbeJFeBN1Pjkaf/Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=t6N3CWiMS9QySea3O1O14fFDVs6Kc+WRsq1z2mYVO6ug0t00ds28cmB6+uOpNo8BYh uaH9EXd91IyTJ2cy5nmXIAkkcs4IQYSQgK+eiTX3TUekv+jwSUYsre86jYU3ZWBjby7B zsji1z389qgVvj7i0BCytIeOwKHWJAQC/PaKk= MIME-Version: 1.0 Received: by 10.216.89.149 with SMTP id c21mr3014466wef.73.1281852857530; Sat, 14 Aug 2010 23:14:17 -0700 (PDT) Received: by 10.216.159.199 with HTTP; Sat, 14 Aug 2010 23:14:17 -0700 (PDT) In-Reply-To: References: Date: Sun, 15 Aug 2010 14:14:17 +0800 Message-ID: Subject: Re: Clock Source in hrtimer From: wu zhangjin To: "wilbur.chan" Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27617 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On 8/15/10, wilbur.chan wrote: > I am planning to use linux 2.6.24 with hrtimer enabled and with > CONFIG_NO_HZ on mips xlr 732. > > > As we know, a monotomic increasing Clock Source is required to > support hrtimer, whose cycles could be retrieved from > clocksource->read function. > > However on xlr 732 ,there is only a 32 bits counter register, which > would overflow in 4s ( 2^32 / 1GHZ = 4). > > How to solve this ? > don't worry about it, the timekeeper solves it: kernel/time/timekeeping.c The r4k timer in most of the MIPS variants also only has a 32bits counter register, no problem with it: arch/mips/kernel/csrc-r4k.c arch/mips/kernel/cevt-r4k.c does xlr 732 also use such a timer (with MIPS count & compare registers of coprocessor0)? If you need to get the time with high resolution, please use: getnstimeofday(), this function will return a linear time with the help of timekeeper(timekeeping_get_ns). Regards, Wu Zhangjin From wilbur512@gmail.com Sun Aug 15 18:00:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Aug 2010 18:00:14 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:37931 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491038Ab0HOQAK convert rfc822-to-8bit (ORCPT ); Sun, 15 Aug 2010 18:00:10 +0200 Received: by qwe4 with SMTP id 4so4748290qwe.36 for ; Sun, 15 Aug 2010 09:00:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=cGAElgvGcakb6UMOg/tPjHsAcYotguqHFMmlfrErspA=; b=uxThSP4B2u0XmsGwgvevv/8bG/tIDy7kVFLrzmv1NHfrex1xVQ/33Iw7x+jovjWLAL 4/Vj10piExhuUsgIq28XrT1K1rkgovK0MCmrqc4zItBaPKJZ2nBSFSZUhOiQUvBbgy6v 3WudbsnTJKoOVVGaK0OYphdN/W241MTYrmra8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=RmnPOAYp+S5Nke0aDTyXc448fiRbwmv7/XUz9WNOaNL5PyWW/3z4NaNwEZ/xpFxk3W ECZZtiT2h6NJcXtTjl/TWcdZfwLfiy7Xz9nsN+2/LkSUGDOcVEsgJsrJbA5DI5cebPeL iAuccYPkAN2AuTNWEYCXaHgM0gr+YObxvqhDs= MIME-Version: 1.0 Received: by 10.229.215.76 with SMTP id hd12mr2930705qcb.44.1281888003603; Sun, 15 Aug 2010 09:00:03 -0700 (PDT) Received: by 10.229.55.69 with HTTP; Sun, 15 Aug 2010 09:00:03 -0700 (PDT) In-Reply-To: References: Date: Mon, 16 Aug 2010 00:00:03 +0800 Message-ID: Subject: Re: Clock Source in hrtimer From: "wilbur.chan" To: wu zhangjin Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27618 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips Hi wu, 2010/8/15 wu zhangjin : > > don't worry about it, the timekeeper solves it: > > kernel/time/timekeeping.c > > The r4k timer in most of the MIPS variants also only has a 32bits > counter register, no problem with it: > > arch/mips/kernel/csrc-r4k.c > arch/mips/kernel/cevt-r4k.c > > does  xlr 732 also use such a timer (with MIPS count & compare > registers of coprocessor0)? > yes, xlr732 use these two registers to generate timer interrupt, with a frequency of 1GHZ > If you need to get the time with high resolution, please use: > getnstimeofday(), this function will return a linear time with the > help of timekeeper(timekeeping_get_ns). > 1) So hrtimer is based on xtime, If CONFIG_NO_HZ is set , would xtime be updated on time and correctly ? 2) some question about __get_nsec_offset : /* read clocksource: */ cycle_now = clocksource_read(clock); /* calculate the delta since the last update_wall_time: */ cycle_delta = (cycle_now - clock->cycle_last) & clock->mask; if cycle_now is smaller than clock->cycle_last , say , cycle_now = 3 , cycle->cycle_last = 2^32-1 , then cycle_delta = 3 - (2^32-1) = ? > Regards, > Wu Zhangjin > From arrow.ebd@gmail.com Mon Aug 16 17:44:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Aug 2010 17:44:49 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:32781 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491941Ab0HPPoq (ORCPT ); Mon, 16 Aug 2010 17:44:46 +0200 Received: by qwe4 with SMTP id 4so5599650qwe.36 for ; Mon, 16 Aug 2010 08:44:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=9FOPE3dHUDWsIaLP3XgRQ95WOMKFH7Ln0HHBsGooi6U=; b=UrEFKdqtGTJwUv18okMuprIOQMYrCh4N3tLBQ5/GuuKKQNZQrHZs7EKtns51A+Vz2C hBP6H1ppTAZQ6CJOdxIINjDhbKUCoK9pHXNhYXj4pbsoeLDqteWv40pdtOhdaps+mN6p dAoZ00v/Qcam7z8BkAyKyL7Vm79owm1AS4Gc0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=VVdv3wMfEKaBZTVrdxYJwJe7JmBCghWY8NaTC4avO0E5uvzxFYqutC8JuLTTGIMD8t DPe0dxZThGYjbN2MkGI6neW8JQ0E6zlMPF5zsmxCcUV7gFYO8YMK04GWI2KfgYBc4p3s yVuCJy5l4a6SFiFw+6AU6JdxU75UpYJCB0X9w= MIME-Version: 1.0 Received: by 10.224.29.16 with SMTP id o16mr3345183qac.294.1281973478700; Mon, 16 Aug 2010 08:44:38 -0700 (PDT) Received: by 10.229.30.195 with HTTP; Mon, 16 Aug 2010 08:44:38 -0700 (PDT) Date: Mon, 16 Aug 2010 23:44:38 +0800 Message-ID: Subject: [Help] R3000 CPU porting, Oops while run app From: arrow zhang To: linux-mips@linux-mips.org Content-Type: multipart/mixed; boundary=0015175ce054cf3a0c048df2b585 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27619 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arrow.ebd@gmail.com Precedence: bulk X-list: linux-mips --0015175ce054cf3a0c048df2b585 Content-Type: text/plain; charset=UTF-8 Dears, * I'm encounter a oops error while run the userspace application * I tried to porting the openwrt to a R3000 cpu, which will be a new router but can not buy on market yet * Would like you give me some advice, thanks * below is some messages (detail refer to enclosed file) {{{ arrow, plat_irq_dispatch: 127, cpuint_ip: 0x800, extint: 0x1000, Call Trace: [<80005388>] dump_stack+0x8/0x38 [<8000924c>] plat_irq_dispatch+0x60/0x294 [<80000424>] ret_from_irq+0x0/0x4 [<80163a7c>] uart_start+0xa4/0xc0 [<80165f6c>] uart_write+0x12c/0x15c [<8015a5e8>] n_tty_write+0x300/0x504 [<80156b30>] tty_write+0x1bc/0x294 [<80096348>] vfs_write+0xc0/0x190 [<80096564>] sys_write+0xa8/0x118 [<800022f4>] stack_done+0x20/0x3c CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 00000000, ra == 800092a4 Oops[#1]: Cpu 0 $ 0 : 00000000 1000ff00 8029b674 00000000 $ 4 : 0000000c 8029b674 00000001 000076fa $ 8 : 0000000a 00000000 00000001 64000000 $12 : 24000000 03bd0000 03bf0000 ac000000 $16 : 00001000 00000800 00000800 80240000 $20 : 1000ff01 81a42c1d 00000fff 8187c000 $24 : ffffffff 80168080 $28 : 81a70000 81a71cf8 8187c0e0 800092a4 Hi : 00000000 Lo : 000003c0 epc : 00000000 (null) Not tainted ra : 800092a4 plat_irq_dispatch+0xb8/0x294 Status: 1000ff00 Cause : 00000808 BadVA : 00000000 }}} * the plat_irq_dispatch code as below {{{ asmlinkage void plat_irq_dispatch(void) { unsigned int cpuint_ip = read_c0_cause() & read_c0_status() & ST0_IM; unsigned int extint_ip = REG32(GIMR) & REG32(GISR); printk("arrow, %s: %d, cpuint_ip: 0x%x, extint: 0x%x, \n", __func__, __LINE__, cpuint_ip, extint_ip); dump_stack(); if (cpuint_ip & CAUSEF_IP7) { /* Timer 0 */ do_IRQ(TC0_IRQ); } else if (cpuint_ip & CAUSEF_IP3) { /* UART 0 */ do_IRQ(UART0_IRQ); } else if (cpuint_ip & CAUSEF_IP6) { /* MAC2- External Ethernet */ do_IRQ(SW_IRQ); } else if (cpuint_ip & CAUSEF_IP2) { /* For shared interrupts */ printk("arrow, %s: %d, extint_ip: 0x%x\n", __func__, __LINE__, extint_ip); if (extint_ip & TC1_IP) { do_IRQ(TC1_IRQ); } else if (extint_ip & UART1_IP) { do_IRQ(UART1_IRQ); } else if (extint_ip & USB_D_IP) { do_IRQ(USB_D_IRQ); } else if (extint_ip & USB_H_IP) { do_IRQ(USB_H_IRQ); } else if (extint_ip & NIC100_IP) { do_IRQ(NIC100_IRQ); } else if (extint_ip & SAR_IP) { do_IRQ(SAR_IRQ); } else if (extint_ip & DMT_IP) { do_IRQ(7); } else { printk("Unknown Interrupt extint_ip (%x)\n", extint_ip); } } else { printk("Unknown Interrupt cpuint_ip (%x)\n", cpuint_ip); } } }}} --0015175ce054cf3a0c048df2b585 Content-Type: application/octet-stream; name="014.dump.open.write.bt" Content-Disposition: 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--0015175ce054cf3a0c048df2b585-- From glikely@secretlab.ca Mon Aug 16 22:42:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Aug 2010 22:42:25 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:48977 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491142Ab0HPUmW (ORCPT ); Mon, 16 Aug 2010 22:42:22 +0200 Received: by pwi9 with SMTP id 9so2339275pwi.36 for ; Mon, 16 Aug 2010 13:42:15 -0700 (PDT) Received: by 10.142.163.19 with SMTP id l19mr4940399wfe.106.1281991334916; Mon, 16 Aug 2010 13:42:14 -0700 (PDT) Received: from angua (S01060002b3d79728.cg.shawcable.net [70.72.87.49]) by mx.google.com with ESMTPS id z1sm8741705wfd.15.2010.08.16.13.42.13 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 16 Aug 2010 13:42:13 -0700 (PDT) Received: by angua (Postfix, from userid 1000) id 0FE683C014C; Mon, 16 Aug 2010 14:42:12 -0600 (MDT) Date: Mon, 16 Aug 2010 14:42:11 -0600 From: Grant Likely To: "Dezhong Diao (dediao)" Cc: David Daney , devicetree-discuss@lists.ozlabs.org, linux-mips@linux-mips.org, ralf@linux-mips.org, "David VomLehn (dvomlehn)" Subject: Re: [PATCH v2 1/2] MIPS: Add device tree support to MIPS Message-ID: <20100816204211.GA17571@angua.secretlab.ca> References: <7A9214B0DEB2074FBCA688B30B04400D013FA46D@XMB-RCD-208.cisco.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <7A9214B0DEB2074FBCA688B30B04400D013FA46D@XMB-RCD-208.cisco.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27620 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: grant.likely@secretlab.ca Precedence: bulk X-list: linux-mips On Wed, Jul 28, 2010 at 03:47:20PM -0500, Dezhong Diao (dediao) wrote: > Grant, > > I agree with your approach. Please go ahead to make changes and get the patches working with latest code in test tree. Or I am able to make changes in terms of your comments too. > > It is best we can have MIPS OF support in 2.6.36, but I have you and Ralf decide it. Wasn't quite ready in time for 2.6.36, but .37 should be no problem. All of the pending devicetree core patches are now in Linus' tree, so it is a good time to rebase. When you repost I can pick them up into my tree to get some build test exposure. I'll also make sure to start build testing on MIPS. Ralf, any suggestions on defconfigs I should use? Cheers, g. > > > Thanks. > > > Dezhong > > -----Original Message----- > From: glikely@secretlab.ca [mailto:glikely@secretlab.ca] On Behalf Of Grant Likely > Sent: Wednesday, July 28, 2010 12:26 PM > To: David Daney > Cc: Dezhong Diao (dediao); devicetree-discuss@lists.ozlabs.org; linux-mips@linux-mips.org; ralf@linux-mips.org; David VomLehn (dvomlehn) > Subject: Re: [PATCH v2 1/2] MIPS: Add device tree support to MIPS > > On Wed, Jul 28, 2010 at 1:19 PM, David Daney wrote: > > On 07/28/2010 11:54 AM, Grant Likely wrote: > >> > >> Hi Dezhong, > > > > [...] > >> > >> Very nice clean patch, thanks!  How/when would you like to see MIPS > >> OF support go into mainline? > >> > > > > I can't speak for the patch authors, but my preference would be to > > have MIPS OF support go in to 2.6.36 if possible. > > > > How? To me it doesn't matter.  I would let you and Ralf fight it out. > > It would probably be best if I at least pick up the first patch into my test tree to give it a spin with the latest changes. I'd be happy to take the 2nd too to avoid ordering issues. > > Cheers, > g. From arrow.ebd@gmail.com Tue Aug 17 02:28:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Aug 2010 02:28:27 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:42443 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491996Ab0HQA2X (ORCPT ); Tue, 17 Aug 2010 02:28:23 +0200 Received: by qwe4 with SMTP id 4so6113570qwe.36 for ; Mon, 16 Aug 2010 17:28:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=xtvXa5VNjRId1BGnH4OCbPXnBO04KBfB0XC3yKsp4yU=; b=TTx7DgS0cSX2QNsUPEFL+NH4K4ZeFLp7US9u751BmR3rlw+CNoQ7w8rBHqiPbkzFQS qUTm1dByJCOQOTmoNeaT/ja41ZJVri6PiJrT3wZrhNzO/ieKem+5Xilpza6Q9c/KV2M1 vHmFeCC8PQfc0DeynnrXWVnNsAJ7JFo3520jg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=BqCsDERYTYeGljLA5U19Ena5XWFoZkqMFKgHjsXF92c3buLF3I3quVzT52fFeaObCc uflAkvcAR20mwcP/Xb0sQPHg/tzYoFEShZYPdO04j1x79SwldRVPXzclBHbfaBl9j0yJ BZcsiE9XyulgLp5E4Rqb1FyU64lykKjrHae1I= MIME-Version: 1.0 Received: by 10.229.189.195 with SMTP id df3mr4256192qcb.143.1282004897478; Mon, 16 Aug 2010 17:28:17 -0700 (PDT) Received: by 10.229.30.195 with HTTP; Mon, 16 Aug 2010 17:28:17 -0700 (PDT) Date: Tue, 17 Aug 2010 08:28:17 +0800 Message-ID: Subject: [Help] R3000 CPU porting, Oops while run app From: arrow zhang To: linux-mips@linux-mips.org Content-Type: multipart/mixed; boundary=00163630ff8f83b8bb048dfa062c Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27621 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arrow.ebd@gmail.com Precedence: bulk X-list: linux-mips --00163630ff8f83b8bb048dfa062c Content-Type: text/plain; charset=UTF-8 Dears, * I'm encounter a oops error while run the userspace application * I tried to porting the openwrt to a R3000 cpu, which will be a new router but can not buy on market yet * Would like you give me some advice, thanks * kernel version linux-2.6.32.16 * below is some messages (detail refer to enclosed file) {{{ arrow, plat_irq_dispatch: 127, cpuint_ip: 0x800, extint: 0x1000, Call Trace: [<80005388>] dump_stack+0x8/0x38 [<8000924c>] plat_irq_dispatch+0x60/0x294 [<80000424>] ret_from_irq+0x0/0x4 [<80163a7c>] uart_start+0xa4/0xc0 [<80165f6c>] uart_write+0x12c/0x15c [<8015a5e8>] n_tty_write+0x300/0x504 [<80156b30>] tty_write+0x1bc/0x294 [<80096348>] vfs_write+0xc0/0x190 [<80096564>] sys_write+0xa8/0x118 [<800022f4>] stack_done+0x20/0x3c CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 00000000, ra == 800092a4 Oops[#1]: Cpu 0 $ 0 : 00000000 1000ff00 8029b674 00000000 $ 4 : 0000000c 8029b674 00000001 000076fa $ 8 : 0000000a 00000000 00000001 64000000 $12 : 24000000 03bd0000 03bf0000 ac000000 $16 : 00001000 00000800 00000800 80240000 $20 : 1000ff01 81a42c1d 00000fff 8187c000 $24 : ffffffff 80168080 $28 : 81a70000 81a71cf8 8187c0e0 800092a4 Hi : 00000000 Lo : 000003c0 epc : 00000000 (null) Not tainted ra : 800092a4 plat_irq_dispatch+0xb8/0x294 Status: 1000ff00 Cause : 00000808 BadVA : 00000000 }}} * the plat_irq_dispatch code as below {{{ asmlinkage void plat_irq_dispatch(void) { unsigned int cpuint_ip = read_c0_cause() & read_c0_status() & ST0_IM; unsigned int extint_ip = REG32(GIMR) & REG32(GISR); printk("arrow, %s: %d, cpuint_ip: 0x%x, extint: 0x%x, \n", __func__, __LINE__, cpuint_ip, extint_ip); dump_stack(); if (cpuint_ip & CAUSEF_IP7) { /* Timer 0 */ do_IRQ(TC0_IRQ); } else if (cpuint_ip & CAUSEF_IP3) { /* UART 0 */ do_IRQ(UART0_IRQ); } else if (cpuint_ip & CAUSEF_IP6) { /* MAC2- External Ethernet */ do_IRQ(SW_IRQ); } else if (cpuint_ip & CAUSEF_IP2) { /* For shared interrupts */ printk("arrow, %s: %d, extint_ip: 0x%x\n", __func__, __LINE__, extint_ip); if (extint_ip & TC1_IP) { do_IRQ(TC1_IRQ); } else if (extint_ip & UART1_IP) { do_IRQ(UART1_IRQ); } else if (extint_ip & USB_D_IP) { do_IRQ(USB_D_IRQ); } else if (extint_ip & USB_H_IP) { do_IRQ(USB_H_IRQ); } else if (extint_ip & NIC100_IP) { do_IRQ(NIC100_IRQ); } else if (extint_ip & SAR_IP) { do_IRQ(SAR_IRQ); } else if (extint_ip & DMT_IP) { do_IRQ(7); } else { printk("Unknown Interrupt extint_ip (%x)\n", extint_ip); } } else { printk("Unknown Interrupt cpuint_ip (%x)\n", cpuint_ip); } } }}} --00163630ff8f83b8bb048dfa062c Content-Type: application/octet-stream; name="014.dump.open.write.bt" Content-Disposition: attachment; filename="014.dump.open.write.bt" Content-Transfer-Encoding: base64 X-Attachment-Id: f_gcy0lo4s0 cHJvbV9tZW1pbml0OjE4DQpwcm9tX21lbWluaXQ6MjINCnByb21fbWVtaW5pdDoyOA0KcHJvbV9t ZW1pbml0OjM0DQpwcm9tX21lbWluaXQ6MzYNCkxpbnV4IHZlcnNpb24gMi42LjMyLjE2IChhcnJv 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S1491195Ab0HQDku (ORCPT ); Tue, 17 Aug 2010 05:40:50 +0200 Received: from canb.auug.org.au (ibmaus65.lnk.telstra.net [165.228.126.9]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtps.tip.net.au (Postfix) with ESMTPSA id A9BE9144002; Tue, 17 Aug 2010 13:40:43 +1000 (EST) Date: Tue, 17 Aug 2010 13:40:39 +1000 From: Stephen Rothwell To: Grant Likely Cc: "Dezhong Diao (dediao)" , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, David Daney , ralf@linux-mips.org, "David VomLehn \(dvomlehn\)" Subject: Re: [PATCH v2 1/2] MIPS: Add device tree support to MIPS Message-Id: <20100817134039.fc1108c7.sfr@canb.auug.org.au> In-Reply-To: <20100816204211.GA17571@angua.secretlab.ca> References: <7A9214B0DEB2074FBCA688B30B04400D013FA46D@XMB-RCD-208.cisco.com> <20100816204211.GA17571@angua.secretlab.ca> X-Mailer: Sylpheed 3.0.2 (GTK+ 2.20.1; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg="PGP-SHA1"; boundary="Signature=_Tue__17_Aug_2010_13_40_39_+1000_loXQi+2twtQLFo7/" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27622 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sfr@canb.auug.org.au Precedence: bulk X-list: linux-mips --Signature=_Tue__17_Aug_2010_13_40_39_+1000_loXQi+2twtQLFo7/ Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Grant, On Mon, 16 Aug 2010 14:42:11 -0600 Grant Likely = wrote: > > I'll also make sure to start build testing on MIPS. Ralf, any suggestion= s on defconfigs I should use? Linux-next does defconfig, allnoconfig, allmodconfig (which has failed for a long time) and ip32_defconfig for mips and mipsel. I am not sure if all these are still relevant. (http://kisskb.ellerman.id.au/kisskb/branch/9/) --=20 Cheers, Stephen Rothwell sfr@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ --Signature=_Tue__17_Aug_2010_13_40_39_+1000_loXQi+2twtQLFo7/ Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQEcBAEBAgAGBQJMagS3AAoJEDMEi1NhKgbsNZsH/A5oh++2w0Bdc0dp0+XzlFXI 5grlYLJ5CKPuCxd1VQ2BBLopeuzUR9YzvdyMkILLTONReWu7KJiUoTnNiZC95V/Z /THxQuHo6gpMxketzgRU+VjfOSe4oVq8Ttk7tzKygIh/2WXbTqbBqI1IHFvWD10+ 56hCEiQHyow0n1ME03urhBwlB5Wq0pHFAvnGKQ/HUmcSlVEzjvkNyP+kM6U1xHry NDUkXk5NEARTWL8VqOT3HR77rg/0bNISmSnIIu6tpDcU4uMz4CkZVG/vgf1Fp75Z lbJBs/DVWqvmGFbaW54FcYUaiuNMs0yCqgrmRUh2M/pJTHtVHBtBp85m9g8emBE= =pXMp -----END PGP SIGNATURE----- --Signature=_Tue__17_Aug_2010_13_40_39_+1000_loXQi+2twtQLFo7/-- From arrow.ebd@gmail.com Tue Aug 17 05:49:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Aug 2010 05:49:36 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:39742 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491821Ab0HQDtd (ORCPT ); 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Mon, 16 Aug 2010 20:49:27 -0700 (PDT) In-Reply-To: References: Date: Tue, 17 Aug 2010 11:49:27 +0800 Message-ID: Subject: Re: [Help] R3000 CPU porting, Oops while run app From: arrow zhang To: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27623 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arrow.ebd@gmail.com Precedence: bulk X-list: linux-mips Dears, yeah, I have known some reason on it: * not call "mips_cpu_irq_init" in function "arch_init_irq" * and did not use "set_irq_chip_and_handler" * before I only setup the "chip" with code "irq_desc[i].chip = &irq_type;", but it is for old kernel(2.6.19) so new code is: void __init arch_init_irq(void) { int i; mips_cpu_irq_init(); for (i = 0; i < 32; ++i) { set_irq_chip_and_handler(i, &irq_type, handle_level_irq); } } From ralf@linux-mips.org Tue Aug 17 14:42:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Aug 2010 14:42:53 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49757 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491985Ab0HQMmt (ORCPT ); Tue, 17 Aug 2010 14:42:49 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7HCgkf5016980; Tue, 17 Aug 2010 13:42:47 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7HCgkFa016978; Tue, 17 Aug 2010 13:42:46 +0100 Date: Tue, 17 Aug 2010 13:42:46 +0100 From: Ralf Baechle To: arrow zhang Cc: linux-mips@linux-mips.org Subject: Re: [Help] R3000 CPU porting, Oops while run app Message-ID: <20100817124246.GA14155@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27624 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Aug 17, 2010 at 11:49:27AM +0800, arrow zhang wrote: > yeah, I have known some reason on it: > * not call "mips_cpu_irq_init" in function "arch_init_irq" > * and did not use "set_irq_chip_and_handler" > * before I only setup the "chip" with code "irq_desc[i].chip = > &irq_type;", but it is for old kernel(2.6.19) > > so new code is: > void __init arch_init_irq(void) > { > int i; > > mips_cpu_irq_init(); > for (i = 0; i < 32; ++i) { > set_irq_chip_and_handler(i, &irq_type, handle_level_irq); > } > } Most systems define MIPS_CPU_IRQ_BASE as 0 so be careful that your set_irq_chip_and_handler loop doesn't overwrite any previous setup by mips_cpu_irq_init. If your interrupt controller has 32 interrupts you probably want to assign interrupts 0..7 to the CPU interrupts and 8..39 to the other controller. Ralf From ralf@linux-mips.org Tue Aug 17 16:34:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Aug 2010 16:34:27 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40987 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492003Ab0HQOeU (ORCPT ); Tue, 17 Aug 2010 16:34:20 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7HEYEXo007757; Tue, 17 Aug 2010 15:34:14 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7HEYEat007755; Tue, 17 Aug 2010 15:34:14 +0100 Date: Tue, 17 Aug 2010 15:34:13 +0100 From: Ralf Baechle To: Andreas =?iso-8859-1?Q?Bie=DFmann?= Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] cavium-octeon: determine if helper should build Message-ID: <20100817143413.GB17861@linux-mips.org> References: <1281545393-23690-1-git-send-email-biessmann@corscience.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1281545393-23690-1-git-send-email-biessmann@corscience.de> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27625 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Danke! Ralf From ralf@linux-mips.org Tue Aug 17 17:00:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Aug 2010 17:00:48 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48661 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492005Ab0HQPAl (ORCPT ); Tue, 17 Aug 2010 17:00:41 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7HF0auq008370; Tue, 17 Aug 2010 16:00:36 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7HF0ZBg008361; Tue, 17 Aug 2010 16:00:35 +0100 Date: Tue, 17 Aug 2010 16:00:35 +0100 From: Ralf Baechle To: Namhyung Kim Cc: David Daney , linux-kernel@vger.kernel.org, David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: remove RELOC_HIDE on __pa_symbol Message-ID: <20100817150035.GC17861@linux-mips.org> References: <1281297456-2711-1-git-send-email-namhyung@gmail.com> <4C5F8ED8.90301@gmail.com> <20100809122147.GA23053@linux-mips.org> <1281409628.1670.11.camel@leonhard> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1281409628.1670.11.camel@leonhard> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27626 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Aug 10, 2010 at 12:07:08PM +0900, Namhyung Kim wrote: > I've sent basically same patch to x86 folks [1] and they said there is a > possiblility of miscompilation on gcc 3. I am not sure the same goes > here on mips but it might be safer to keep it. Sorry for the noise ;-( > > [1] http://lkml.org/lkml/2010/8/8/138 So in a distant future when GCC 3.x will finally be retired we will be able to apply this patch, sigh. I'll drop your patch for the time being and add a comment to the code. Thanks! Ralf From namhyung@gmail.com Tue Aug 17 17:05:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Aug 2010 17:05:54 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:45730 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490960Ab0HQPFv (ORCPT ); Tue, 17 Aug 2010 17:05:51 +0200 Received: by pxi4 with SMTP id 4so2700517pxi.36 for ; Tue, 17 Aug 2010 08:05:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=CoQ3kCpQLF2+507Qdbf1yfproC8kw6WbRvkJMCu9drY=; b=nfz4GX7ljzOpVL++7LX97PDqbM1LyG+Jk26MoLXRHyPWMTtqsGGx38pOeGNB7sE8bE qD2da+0cqFxHifSZ1Kxo0V4joTOrJzNjk5xCq8EaiQ5gpAmK1wsf54Ow9qSXcquGJAQB ZOvt399WGNjpHffHGYf74BAZnU8/NeTrP5dhA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=qiGLEvYbqFJ9QFKNPcpEVdjAd70JwlOgX2JJLnFm17/DfXIIllbhZOuw/1VHN79qna XXF9RTkQowPsThLka4ZncGil/qs2J6P6EYogh+iTYMi35DM6T7W8zC/RYbTrq80K3DHY fdpG48KCgUA8UVhXk7GwuVuDKeSNxAecgHGj0= Received: by 10.142.192.1 with SMTP id p1mr5857196wff.287.1282057542586; Tue, 17 Aug 2010 08:05:42 -0700 (PDT) Received: from [192.168.15.10] ([211.201.183.151]) by mx.google.com with ESMTPS id w4sm7986017wfd.20.2010.08.17.08.05.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 17 Aug 2010 08:05:41 -0700 (PDT) Subject: Re: [PATCH] MIPS: remove RELOC_HIDE on __pa_symbol From: Namhyung Kim To: Ralf Baechle Cc: David Daney , linux-kernel@vger.kernel.org, David Daney , linux-mips@linux-mips.org In-Reply-To: <20100817150035.GC17861@linux-mips.org> References: <1281297456-2711-1-git-send-email-namhyung@gmail.com> <4C5F8ED8.90301@gmail.com> <20100809122147.GA23053@linux-mips.org> <1281409628.1670.11.camel@leonhard> <20100817150035.GC17861@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Date: Wed, 18 Aug 2010 00:05:35 +0900 Message-ID: <1282057535.1635.10.camel@leonhard> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27627 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: namhyung@gmail.com Precedence: bulk X-list: linux-mips 2010-08-17 (í™”), 16:00 +0100, Ralf Baechle: > On Tue, Aug 10, 2010 at 12:07:08PM +0900, Namhyung Kim wrote: > > > I've sent basically same patch to x86 folks [1] and they said there is a > > possiblility of miscompilation on gcc 3. I am not sure the same goes > > here on mips but it might be safer to keep it. Sorry for the noise ;-( > > > > [1] http://lkml.org/lkml/2010/8/8/138 > > So in a distant future when GCC 3.x will finally be retired we will be > able to apply this patch, sigh. I'll drop your patch for the time being > and add a comment to the code. > > Thanks! > > Ralf FYI, the exact version introduced -f[no-]strict-overlow was gcc 4.2. -- Regards, Namhyung Kim From yad.naveen@gmail.com Wed Aug 18 14:37:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 14:37:22 +0200 (CEST) Received: from mail-qy0-f170.google.com ([209.85.216.170]:53830 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491159Ab0HRMhT (ORCPT ); Wed, 18 Aug 2010 14:37:19 +0200 Received: by qyk35 with SMTP id 35so1904997qyk.15 for ; Wed, 18 Aug 2010 05:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=su5K4IYYNSgQup/IYoXE1E7BxIsXA8ZOB1EcahW6diE=; b=hy9aizNtKub/RAgECEud8f3aM7/sF8Q5toxXG1iLCi4A/bzE+3y7zyUopM3HP0iayM 7A0EkE1gNbVmTMdyPvN+21DHcEZuev+S80xk9sHP6dCBm95RcdOmrG1xIQQZKt/xGeHK UEItMTpwPlzph/YjBnjySmiPnhAL2t+1xV0vY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=EtBfCYalAa6eiuHsVmx82co1k+qhXm52wfnV4N9ZC9xBUbyXfTSuwntBVbDisMKs5W iyw4ixu76fcxWjySJC1O+HBqvvmPMSlLtYuewhafPXvvErvf+1g44746G5Hca6eD7U6t 4IKDFGRhMjjnBxnXPlujeSCW+7yuS5f6kDkhY= MIME-Version: 1.0 Received: by 10.224.54.134 with SMTP id q6mr5346829qag.274.1282135032798; Wed, 18 Aug 2010 05:37:12 -0700 (PDT) Received: by 10.229.20.129 with HTTP; Wed, 18 Aug 2010 05:37:12 -0700 (PDT) Date: Wed, 18 Aug 2010 18:07:12 +0530 Message-ID: Subject: kmalloc issue on MIPS target From: naveen yadav To: majordomo@kvack.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27628 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Hi All, We are using MIPS(mips32r2) target. when I alloc memory using kmalloc suppose 28 bytes, the kernel still consume 128 bytes. So when I check File on kernel source mach-ip32/kmalloc.h Since it is allign to 128 bytes so i understand that even if I consume 1 byte it will waste 128 bytes. #ifndef __ASM_MACH_IP32_KMALLOC_H #define __ASM_MACH_IP32_KMALLOC_H #if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000) #define ARCH_KMALLOC_MINALIGN 32 #else #define ARCH_KMALLOC_MINALIGN 128 #endif #endif /* __ASM_MACH_IP32_KMALLOC_H */ So I could not understand why it is allign to 128 bytes. Is there any specific reason for it. ? thanks From yad.naveen@gmail.com Wed Aug 18 14:44:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 14:44:46 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:51580 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491159Ab0HRMom convert rfc822-to-8bit (ORCPT ); Wed, 18 Aug 2010 14:44:42 +0200 Received: by qwe4 with SMTP id 4so475935qwe.36 for ; Wed, 18 Aug 2010 05:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:content-type :content-transfer-encoding; bh=mB6daR4SBSm8/ADaDpthGxmSfH3phc2jfTCE8Jym4lA=; b=TW7BPBs5Y01gskbYipPmNfqVjbCSJBVEy6Nx2l5o7aoRUwkD3FkgxX0QPnOTS0B/fo z+F0uMVWI60hWE9rgjMPDfU+EorsXVQWKQeSYr+AdjkjFUhY5yioIlWaMWivgULwYKdX pXwCywdkfpgRWH/LtWh7q+F1ymY+zob8wBd5Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type:content-transfer-encoding; b=praK0m4I5liaNpO6beMB8EqNFCT3HEThrPhT44NOcQd8dd7jXBOAsGqpuWuXVJ2KIP VVNnaNYVPBrVjNjccbFBk6hVytuqzKy2vlz+vwVdO1DpBUpxn1t438pFnvDCRIz5nzjI nKulaxrIhhB0S8vfSOa+LnVLaYorkga7XW8Ls= MIME-Version: 1.0 Received: by 10.224.19.140 with SMTP id a12mr5324730qab.333.1282135476905; Wed, 18 Aug 2010 05:44:36 -0700 (PDT) Received: by 10.229.20.129 with HTTP; Wed, 18 Aug 2010 05:44:36 -0700 (PDT) In-Reply-To: References: Date: Wed, 18 Aug 2010 18:14:36 +0530 Message-ID: Subject: Re: kmalloc issue on MIPS target From: naveen yadav To: ralf@linux-mips.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27629 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips On Wed, Aug 18, 2010 at 6:07 PM, naveen yadav wrote: > Hi All, > > We are using MIPS(mips32r2) target. when I alloc memory using kmalloc > suppose  28 bytes, the kernel still consume 128 bytes. > > So when I check File on kernel source  mach-ip32/kmalloc.h > > Since it is allign to 128 bytes so i understand that even if  I > consume 1 byte it will waste 128 bytes. > > #ifndef __ASM_MACH_IP32_KMALLOC_H > #define __ASM_MACH_IP32_KMALLOC_H > > > #if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000) > #define ARCH_KMALLOC_MINALIGN   32 > #else > #define ARCH_KMALLOC_MINALIGN   128 > #endif > > #endif /* __ASM_MACH_IP32_KMALLOC_H */ > > > So I could not understand why it is allign to 128 bytes. Is there any > specific reason for it. ? > > thanks > From ralf@linux-mips.org Wed Aug 18 14:57:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 14:57:20 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56670 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491159Ab0HRM5Q (ORCPT ); Wed, 18 Aug 2010 14:57:16 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7IChBn4023787; Wed, 18 Aug 2010 13:43:11 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7IChAJA023785; Wed, 18 Aug 2010 13:43:10 +0100 Date: Wed, 18 Aug 2010 13:43:10 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Cc: Paul Gortmaker Subject: MIPS: Get rid of branches to .subsections. Message-ID: <20100818124310.GA23744@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27630 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips It was a nice optimization - on paper at least. In practice it results in branches that may exceed the maximum legal range for a branch. We can fight that problem with -ffunction-sections but -ffunction-sections again is incompatible with -pg used by the function tracer. By rewriting the loop around all simple LL/SC blocks to C we reduce reduce the amount of inline assembler and at the same time allow GCC to often fill the branch delay slots with something sensible or whever else clever optimization it may have up in its sleeve. With this optimization gone we also no longer need -ffunction-sections, so drop it. This optimization was originall introduced in 2.6.21, commit 5999eca25c1fd4b9b9aca7833b04d10fe4bc877d (linux-mips.org) rsp. f65e4fa8e0c6022ad58dc88d1b11b12589ed7f9f (kernel.org). Original fix for the issues which caused me to pull this optimization by Paul Gortmaker . Signed-off-by: Ralf Baechle --- v2: a bunch of build fixes. arch/mips/Makefile | 3 arch/mips/include/asm/atomic.h | 208 ++++++++++++++---------------- arch/mips/include/asm/bitops.h | 270 +++++++++++++++++----------------------- arch/mips/include/asm/cmpxchg.h | 7 - arch/mips/include/asm/system.h | 52 +++---- 5 files changed, 243 insertions(+), 297 deletions(-) Index: linux-queue/arch/mips/include/asm/atomic.h =================================================================== --- linux-queue.orig/arch/mips/include/asm/atomic.h +++ linux-queue/arch/mips/include/asm/atomic.h @@ -64,18 +64,16 @@ static __inline__ void atomic_add(int i, } else if (kernel_uses_llsc) { int temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %1 # atomic_add \n" - " addu %0, %2 \n" - " sc %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %0, %1 # atomic_add \n" + " addu %0, %2 \n" + " sc %0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); + } while (unlikely(!temp)); } else { unsigned long flags; @@ -109,18 +107,16 @@ static __inline__ void atomic_sub(int i, } else if (kernel_uses_llsc) { int temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %1 # atomic_sub \n" - " subu %0, %2 \n" - " sc %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %0, %1 # atomic_sub \n" + " subu %0, %2 \n" + " sc %0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); + } while (unlikely(!temp)); } else { unsigned long flags; @@ -156,20 +152,19 @@ static __inline__ int atomic_add_return( } else if (kernel_uses_llsc) { int temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_add_return \n" - " addu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqz %0, 2f \n" - " addu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %1, %2 # atomic_add_return \n" + " addu %0, %1, %3 \n" + " sc %0, %2 \n" + " .set mips0 \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); + } while (unlikely(!result)); + + result = temp + i; } else { unsigned long flags; @@ -205,23 +200,24 @@ static __inline__ int atomic_sub_return( : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); + + result = temp - i; } else if (kernel_uses_llsc) { int temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_sub_return \n" - " subu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqz %0, 2f \n" - " subu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %1, %2 # atomic_sub_return \n" + " subu %0, %1, %3 \n" + " sc %0, %2 \n" + " .set mips0 \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); + } while (unlikely(!result)); + + result = temp - i; } else { unsigned long flags; @@ -279,12 +275,9 @@ static __inline__ int atomic_sub_if_posi " bltz %0, 1f \n" " sc %0, %2 \n" " .set noreorder \n" - " beqz %0, 2f \n" + " beqz %0, 1b \n" " subu %0, %1, %3 \n" " .set reorder \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" "1: \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) @@ -443,18 +436,16 @@ static __inline__ void atomic64_add(long } else if (kernel_uses_llsc) { long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %1 # atomic64_add \n" - " daddu %0, %2 \n" - " scd %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + do { + __asm__ __volatile__( + " .set mips3 \n" + "1: lld %0, %1 # atomic64_add \n" + " daddu %0, %2 \n" + " scd %0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); + } while (unlikely(!temp)); } else { unsigned long flags; @@ -488,18 +479,16 @@ static __inline__ void atomic64_sub(long } else if (kernel_uses_llsc) { long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %1 # atomic64_sub \n" - " dsubu %0, %2 \n" - " scd %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + do { + __asm__ __volatile__( + " .set mips3 \n" + "1: lld %0, %1 # atomic64_sub \n" + " dsubu %0, %2 \n" + " scd %0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); + } while (unlikely(!temp)); } else { unsigned long flags; @@ -535,20 +524,19 @@ static __inline__ long atomic64_add_retu } else if (kernel_uses_llsc) { long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_add_return \n" - " daddu %0, %1, %3 \n" - " scd %0, %2 \n" - " beqz %0, 2f \n" - " daddu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + "1: lld %1, %2 # atomic64_add_return \n" + " daddu %0, %1, %3 \n" + " scd %0, %2 \n" + " .set mips0 \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); + } while (unlikely(!result)); + + result = temp + i; } else { unsigned long flags; @@ -587,20 +575,19 @@ static __inline__ long atomic64_sub_retu } else if (kernel_uses_llsc) { long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_sub_return \n" - " dsubu %0, %1, %3 \n" - " scd %0, %2 \n" - " beqz %0, 2f \n" - " dsubu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + "1: lld %1, %2 # atomic64_sub_return \n" + " dsubu %0, %1, %3 \n" + " scd %0, %2 \n" + " .set mips0 \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); + } while (unlikely(!result)); + + result = temp - i; } else { unsigned long flags; @@ -658,12 +645,9 @@ static __inline__ long atomic64_sub_if_p " bltz %0, 1f \n" " scd %0, %2 \n" " .set noreorder \n" - " beqz %0, 2f \n" + " beqz %0, 1b \n" " dsubu %0, %1, %3 \n" " .set reorder \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" "1: \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) Index: linux-queue/arch/mips/include/asm/bitops.h =================================================================== --- linux-queue.orig/arch/mips/include/asm/bitops.h +++ linux-queue/arch/mips/include/asm/bitops.h @@ -73,30 +73,26 @@ static inline void set_bit(unsigned long : "ir" (1UL << bit), "m" (*m)); #ifdef CONFIG_CPU_MIPSR2 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { - __asm__ __volatile__( - "1: " __LL "%0, %1 # set_bit \n" - " " __INS "%0, %4, %2, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m), "r" (~0)); + do { + __asm__ __volatile__( + " " __LL "%0, %1 # set_bit \n" + " " __INS "%0, %3, %2, 1 \n" + " " __SC "%0, %1 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (bit), "r" (~0)); + } while (unlikely(!temp)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (kernel_uses_llsc) { - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # set_bit \n" - " or %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # set_bit \n" + " or %0, %2 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (1UL << bit)); + } while (unlikely(!temp)); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -134,34 +130,30 @@ static inline void clear_bit(unsigned lo " " __SC "%0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << bit)), "m" (*m)); + : "=&r" (temp), "+m" (*m) + : "ir" (~(1UL << bit))); #ifdef CONFIG_CPU_MIPSR2 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { - __asm__ __volatile__( - "1: " __LL "%0, %1 # clear_bit \n" - " " __INS "%0, $0, %2, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m)); + do { + __asm__ __volatile__( + " " __LL "%0, %1 # clear_bit \n" + " " __INS "%0, $0, %2, 1 \n" + " " __SC "%0, %1 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (bit)); + } while (unlikely(!temp)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (kernel_uses_llsc) { - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # clear_bit \n" - " and %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << bit)), "m" (*m)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # clear_bit \n" + " and %0, %2 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (~(1UL << bit))); + } while (unlikely(!temp)); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -213,24 +205,22 @@ static inline void change_bit(unsigned l " " __SC "%0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); + : "=&r" (temp), "+m" (*m) + : "ir" (1UL << bit)); } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # change_bit \n" - " xor %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); + do { + __asm__ __volatile__( + " .set mips3 \n" + "1: " __LL "%0, %1 # change_bit \n" + " xor %0, %2 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (1UL << bit)); + } while (unlikely(!temp)); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -272,30 +262,26 @@ static inline int test_and_set_bit(unsig " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) : "memory"); } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_set_bit \n" - " or %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + "1: " __LL "%0, %1 # test_and_set_bit \n" + " or %2, %0, %3 \n" + " " __SC "%2, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) + : "memory"); + } while (unlikely(!res)); + + res = temp & (1UL << bit); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -340,30 +326,26 @@ static inline int test_and_set_bit_lock( " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) : "memory"); } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_set_bit \n" - " or %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + "1: " __LL "%0, %1 # test_and_set_bit \n" + " or %2, %0, %3 \n" + " " __SC "%2, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) + : "memory"); + } while(unlikely(!res)); + + res = temp & (1UL << bit); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -410,49 +392,43 @@ static inline int test_and_clear_bit(uns " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) : "memory"); #ifdef CONFIG_CPU_MIPSR2 } else if (kernel_uses_llsc && __builtin_constant_p(nr)) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - "1: " __LL "%0, %1 # test_and_clear_bit \n" - " " __EXT "%2, %0, %3, 1 \n" - " " __INS "%0, $0, %3, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "ir" (bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " " __LL "%0, %1 # test_and_clear_bit \n" + " " __EXT "%2, %0, %3, 1 \n" + " " __INS "%0, $0, %3, 1 \n" + " " __SC "%0, %1 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "ir" (bit) + : "memory"); + } while (unlikely(!temp)); #endif } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_clear_bit \n" - " or %2, %0, %3 \n" - " xor %2, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + "1: " __LL "%0, %1 # test_and_clear_bit \n" + " or %2, %0, %3 \n" + " xor %2, %3 \n" + " " __SC "%2, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) + : "memory"); + } while (unlikely(!res)); + + res = temp & (1UL << bit); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -499,30 +475,26 @@ static inline int test_and_change_bit(un " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) : "memory"); } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_change_bit \n" - " xor %2, %0, %3 \n" - " " __SC "\t%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # test_and_change_bit \n" + " xor %2, %0, %3 \n" + " " __SC "\t%2, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) + : "memory"); + } while (unlikely(!res)); + + res = temp & (1UL << bit); } else { volatile unsigned long *a = addr; unsigned long mask; Index: linux-queue/arch/mips/include/asm/cmpxchg.h =================================================================== --- linux-queue.orig/arch/mips/include/asm/cmpxchg.h +++ linux-queue/arch/mips/include/asm/cmpxchg.h @@ -44,12 +44,9 @@ " move $1, %z4 \n" \ " .set mips3 \n" \ " " st " $1, %1 \n" \ - " beqz $1, 3f \n" \ - "2: \n" \ - " .subsection 2 \n" \ - "3: b 1b \n" \ - " .previous \n" \ + " beqz $1, 1b \n" \ " .set pop \n" \ + "2: \n" \ : "=&r" (__ret), "=R" (*m) \ : "R" (*m), "Jr" (old), "Jr" (new) \ : "memory"); \ Index: linux-queue/arch/mips/include/asm/system.h =================================================================== --- linux-queue.orig/arch/mips/include/asm/system.h +++ linux-queue/arch/mips/include/asm/system.h @@ -115,21 +115,19 @@ static inline unsigned long __xchg_u32(v } else if (kernel_uses_llsc) { unsigned long dummy; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %3 # xchg_u32 \n" - " .set mips0 \n" - " move %2, %z4 \n" - " .set mips3 \n" - " sc %2, %1 \n" - " beqz %2, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %0, %3 # xchg_u32 \n" + " .set mips0 \n" + " move %2, %z4 \n" + " .set mips3 \n" + " sc %2, %1 \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } while(unlikely(!dummy)); } else { unsigned long flags; @@ -167,19 +165,17 @@ static inline __u64 __xchg_u64(volatile } else if (kernel_uses_llsc) { unsigned long dummy; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %3 # xchg_u64 \n" - " move %2, %z4 \n" - " scd %2, %1 \n" - " beqz %2, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " lld %0, %3 # xchg_u64 \n" + " move %2, %z4 \n" + " scd %2, %1 \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } while (unlikely(!dummy)); } else { unsigned long flags; Index: linux-queue/arch/mips/Makefile =================================================================== --- linux-queue.orig/arch/mips/Makefile +++ linux-queue/arch/mips/Makefile @@ -48,9 +48,6 @@ ifneq ($(SUBARCH),$(ARCH)) endif endif -ifndef CONFIG_FUNCTION_TRACER -cflags-y := -ffunction-sections -endif ifdef CONFIG_FUNCTION_GRAPH_TRACER ifndef KBUILD_MCOUNT_RA_ADDRESS ifeq ($(call cc-option-yn,-mmcount-ra-address), y) From sshtylyov@mvista.com Wed Aug 18 15:26:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 15:26:18 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:46390 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491159Ab0HRN0M (ORCPT ); Wed, 18 Aug 2010 15:26:12 +0200 Received: by eye22 with SMTP id 22so327879eye.36 for ; Wed, 18 Aug 2010 06:26:09 -0700 (PDT) Received: by 10.213.3.83 with SMTP id 19mr292615ebm.49.1282137969445; Wed, 18 Aug 2010 06:26:09 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id u9sm474737eeh.5.2010.08.18.06.26.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 18 Aug 2010 06:26:08 -0700 (PDT) Message-ID: <4C6BDF40.9050804@mvista.com> Date: Wed, 18 Aug 2010 17:25:20 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org, Paul Gortmaker Subject: Re: MIPS: Get rid of branches to .subsections. References: <20100818124310.GA23744@linux-mips.org> In-Reply-To: <20100818124310.GA23744@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27631 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Ralf Baechle wrote: > It was a nice optimization - on paper at least. In practice it results in > branches that may exceed the maximum legal range for a branch. We can > fight that problem with -ffunction-sections but -ffunction-sections again > is incompatible with -pg used by the function tracer. > By rewriting the loop around all simple LL/SC blocks to C we reduce reduce > the amount of inline assembler and at the same time allow GCC to often > fill the branch delay slots with something sensible or whever else clever ^^^^^^ Whichever? > optimization it may have up in its sleeve. > With this optimization gone we also no longer need -ffunction-sections, > so drop it. > This optimization was originall introduced in 2.6.21, commit ^^^^^^^^^ Originally. > 5999eca25c1fd4b9b9aca7833b04d10fe4bc877d (linux-mips.org) rsp. > f65e4fa8e0c6022ad58dc88d1b11b12589ed7f9f (kernel.org). > Original fix for the issues which caused me to pull this optimization by > Paul Gortmaker . > Signed-off-by: Ralf Baechle > Index: linux-queue/arch/mips/include/asm/atomic.h > =================================================================== > --- linux-queue.orig/arch/mips/include/asm/atomic.h > +++ linux-queue/arch/mips/include/asm/atomic.h [...] > @@ -443,18 +436,16 @@ static __inline__ void atomic64_add(long > } else if (kernel_uses_llsc) { > long temp; > > - __asm__ __volatile__( > - " .set mips3 \n" > - "1: lld %0, %1 # atomic64_add \n" > - " daddu %0, %2 \n" > - " scd %0, %1 \n" > - " beqz %0, 2f \n" > - " .subsection 2 \n" > - "2: b 1b \n" > - " .previous \n" > - " .set mips0 \n" > - : "=&r" (temp), "=m" (v->counter) > - : "Ir" (i), "m" (v->counter)); > + do { > + __asm__ __volatile__( > + " .set mips3 \n" > + "1: lld %0, %1 # atomic64_add \n" You've kept the label here but it seems unused... > + " daddu %0, %2 \n" > + " scd %0, %1 \n" > + " .set mips0 \n" > + : "=&r" (temp), "=m" (v->counter) > + : "Ir" (i), "m" (v->counter)); > + } while (unlikely(!temp)); > } else { > unsigned long flags; > > @@ -488,18 +479,16 @@ static __inline__ void atomic64_sub(long > } else if (kernel_uses_llsc) { > long temp; > > - __asm__ __volatile__( > - " .set mips3 \n" > - "1: lld %0, %1 # atomic64_sub \n" > - " dsubu %0, %2 \n" > - " scd %0, %1 \n" > - " beqz %0, 2f \n" > - " .subsection 2 \n" > - "2: b 1b \n" > - " .previous \n" > - " .set mips0 \n" > - : "=&r" (temp), "=m" (v->counter) > - : "Ir" (i), "m" (v->counter)); > + do { > + __asm__ __volatile__( > + " .set mips3 \n" > + "1: lld %0, %1 # atomic64_sub \n" Same here... > + " dsubu %0, %2 \n" > + " scd %0, %1 \n" > + " .set mips0 \n" > + : "=&r" (temp), "=m" (v->counter) > + : "Ir" (i), "m" (v->counter)); > + } while (unlikely(!temp)); > } else { > unsigned long flags; > > @@ -535,20 +524,19 @@ static __inline__ long atomic64_add_retu > } else if (kernel_uses_llsc) { > long temp; > > - __asm__ __volatile__( > - " .set mips3 \n" > - "1: lld %1, %2 # atomic64_add_return \n" > - " daddu %0, %1, %3 \n" > - " scd %0, %2 \n" > - " beqz %0, 2f \n" > - " daddu %0, %1, %3 \n" > - " .subsection 2 \n" > - "2: b 1b \n" > - " .previous \n" > - " .set mips0 \n" > - : "=&r" (result), "=&r" (temp), "=m" (v->counter) > - : "Ir" (i), "m" (v->counter) > - : "memory"); > + do { > + __asm__ __volatile__( > + " .set mips3 \n" > + "1: lld %1, %2 # atomic64_add_return \n" ... and here. > + " daddu %0, %1, %3 \n" > + " scd %0, %2 \n" > + " .set mips0 \n" > + : "=&r" (result), "=&r" (temp), "=m" (v->counter) > + : "Ir" (i), "m" (v->counter) > + : "memory"); > + } while (unlikely(!result)); > + > + result = temp + i; > } else { > unsigned long flags; > > @@ -587,20 +575,19 @@ static __inline__ long atomic64_sub_retu > } else if (kernel_uses_llsc) { > long temp; > > - __asm__ __volatile__( > - " .set mips3 \n" > - "1: lld %1, %2 # atomic64_sub_return \n" > - " dsubu %0, %1, %3 \n" > - " scd %0, %2 \n" > - " beqz %0, 2f \n" > - " dsubu %0, %1, %3 \n" > - " .subsection 2 \n" > - "2: b 1b \n" > - " .previous \n" > - " .set mips0 \n" > - : "=&r" (result), "=&r" (temp), "=m" (v->counter) > - : "Ir" (i), "m" (v->counter) > - : "memory"); > + do { > + __asm__ __volatile__( > + " .set mips3 \n" > + "1: lld %1, %2 # atomic64_sub_return \n" ... and here. > + " dsubu %0, %1, %3 \n" > + " scd %0, %2 \n" > + " .set mips0 \n" > + : "=&r" (result), "=&r" (temp), "=m" (v->counter) > + : "Ir" (i), "m" (v->counter) > + : "memory"); > + } while (unlikely(!result)); > + > + result = temp - i; > } else { > unsigned long flags; > > Index: linux-queue/arch/mips/include/asm/bitops.h > =================================================================== > --- linux-queue.orig/arch/mips/include/asm/bitops.h > +++ linux-queue/arch/mips/include/asm/bitops.h > @@ -213,24 +205,22 @@ static inline void change_bit(unsigned l > " " __SC "%0, %1 \n" > " beqzl %0, 1b \n" > " .set mips0 \n" > - : "=&r" (temp), "=m" (*m) > - : "ir" (1UL << bit), "m" (*m)); > + : "=&r" (temp), "+m" (*m) > + : "ir" (1UL << bit)); > } else if (kernel_uses_llsc) { > unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); > unsigned long temp; > > - __asm__ __volatile__( > - " .set mips3 \n" > - "1: " __LL "%0, %1 # change_bit \n" > - " xor %0, %2 \n" > - " " __SC "%0, %1 \n" > - " beqz %0, 2f \n" > - " .subsection 2 \n" > - "2: b 1b \n" > - " .previous \n" > - " .set mips0 \n" > - : "=&r" (temp), "=m" (*m) > - : "ir" (1UL << bit), "m" (*m)); > + do { > + __asm__ __volatile__( > + " .set mips3 \n" > + "1: " __LL "%0, %1 # change_bit \n" ... and here too. > + " xor %0, %2 \n" > + " " __SC "%0, %1 \n" > + " .set mips0 \n" > + : "=&r" (temp), "+m" (*m) > + : "ir" (1UL << bit)); > + } while (unlikely(!temp)); > } else { > volatile unsigned long *a = addr; > unsigned long mask; > @@ -272,30 +262,26 @@ static inline int test_and_set_bit(unsig > " beqzl %2, 1b \n" > " and %2, %0, %3 \n" > " .set mips0 \n" > - : "=&r" (temp), "=m" (*m), "=&r" (res) > - : "r" (1UL << bit), "m" (*m) > + : "=&r" (temp), "+m" (*m), "=&r" (res) > + : "r" (1UL << bit) > : "memory"); > } else if (kernel_uses_llsc) { > unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); > unsigned long temp; > > - __asm__ __volatile__( > - " .set push \n" > - " .set noreorder \n" > - " .set mips3 \n" > - "1: " __LL "%0, %1 # test_and_set_bit \n" > - " or %2, %0, %3 \n" > - " " __SC "%2, %1 \n" > - " beqz %2, 2f \n" > - " and %2, %0, %3 \n" > - " .subsection 2 \n" > - "2: b 1b \n" > - " nop \n" > - " .previous \n" > - " .set pop \n" > - : "=&r" (temp), "=m" (*m), "=&r" (res) > - : "r" (1UL << bit), "m" (*m) > - : "memory"); > + do { > + __asm__ __volatile__( > + " .set mips3 \n" > + "1: " __LL "%0, %1 # test_and_set_bit \n" ... and here as well. > + " or %2, %0, %3 \n" > + " " __SC "%2, %1 \n" > + " .set mips0 \n" > + : "=&r" (temp), "+m" (*m), "=&r" (res) > + : "r" (1UL << bit) > + : "memory"); > + } while (unlikely(!res)); > + > + res = temp & (1UL << bit); > } else { > volatile unsigned long *a = addr; > unsigned long mask; > @@ -340,30 +326,26 @@ static inline int test_and_set_bit_lock( > " beqzl %2, 1b \n" > " and %2, %0, %3 \n" > " .set mips0 \n" > - : "=&r" (temp), "=m" (*m), "=&r" (res) > - : "r" (1UL << bit), "m" (*m) > + : "=&r" (temp), "+m" (*m), "=&r" (res) > + : "r" (1UL << bit) > : "memory"); > } else if (kernel_uses_llsc) { > unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); > unsigned long temp; > > - __asm__ __volatile__( > - " .set push \n" > - " .set noreorder \n" > - " .set mips3 \n" > - "1: " __LL "%0, %1 # test_and_set_bit \n" > - " or %2, %0, %3 \n" > - " " __SC "%2, %1 \n" > - " beqz %2, 2f \n" > - " and %2, %0, %3 \n" > - " .subsection 2 \n" > - "2: b 1b \n" > - " nop \n" > - " .previous \n" > - " .set pop \n" > - : "=&r" (temp), "=m" (*m), "=&r" (res) > - : "r" (1UL << bit), "m" (*m) > - : "memory"); > + do { > + __asm__ __volatile__( > + " .set mips3 \n" > + "1: " __LL "%0, %1 # test_and_set_bit \n" ... and here. > + " or %2, %0, %3 \n" > + " " __SC "%2, %1 \n" > + " .set mips0 \n" > + : "=&r" (temp), "+m" (*m), "=&r" (res) > + : "r" (1UL << bit) > + : "memory"); > + } while(unlikely(!res)); > + > + res = temp & (1UL << bit); > } else { > volatile unsigned long *a = addr; > unsigned long mask; > @@ -410,49 +392,43 @@ static inline int test_and_clear_bit(uns [...] > } else if (kernel_uses_llsc) { > unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); > unsigned long temp; > > - __asm__ __volatile__( > - " .set push \n" > - " .set noreorder \n" > - " .set mips3 \n" > - "1: " __LL "%0, %1 # test_and_clear_bit \n" > - " or %2, %0, %3 \n" > - " xor %2, %3 \n" > - " " __SC "%2, %1 \n" > - " beqz %2, 2f \n" > - " and %2, %0, %3 \n" > - " .subsection 2 \n" > - "2: b 1b \n" > - " nop \n" > - " .previous \n" > - " .set pop \n" > - : "=&r" (temp), "=m" (*m), "=&r" (res) > - : "r" (1UL << bit), "m" (*m) > - : "memory"); > + do { > + __asm__ __volatile__( > + " .set mips3 \n" > + "1: " __LL "%0, %1 # test_and_clear_bit \n" ... and here. > + " or %2, %0, %3 \n" > + " xor %2, %3 \n" > + " " __SC "%2, %1 \n" > + " .set mips0 \n" > + : "=&r" (temp), "+m" (*m), "=&r" (res) > + : "r" (1UL << bit) > + : "memory"); > + } while (unlikely(!res)); > + > + res = temp & (1UL << bit); > } else { > volatile unsigned long *a = addr; > unsigned long mask; WBR, Sergei From Andrei.Ardelean@idt.com Wed Aug 18 15:31:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 15:31:56 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:40567 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491159Ab0HRNbv convert rfc822-to-8bit (ORCPT ); Wed, 18 Aug 2010 15:31:51 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o7IDViXf021736 for ; Wed, 18 Aug 2010 06:31:44 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o7IDViwd029479 for ; Wed, 18 Aug 2010 06:31:44 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o7IDVhl22879 for ; Wed, 18 Aug 2010 06:31:43 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Does Mips Linux rely on Yamon h/w initialization (other than DDR memory which is strictly necessary)? Date: Wed, 18 Aug 2010 06:31:42 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: Does Mips Linux rely on Yamon h/w initialization (other than DDR memory which is strictly necessary)? thread-index: Acs+2bHgPx6CyZgoTAC+IXnMlqMzfA== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27632 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, Malta board has Yamon monitor which initializes the DDR memory and other h/w. Does Mips Linux rely on Yamon h/w initialization (except memory) like PCI, NET, UART, etc in order to boot? Does Mips Linux re-initialize the h/w again? I am booting Linux on Malta with a small monitor which initializes only the memory. I pass the environment vars array, command line arguments and memory size as Yamon would do. The ASCII display shows "Linux on Malta" scrolling text so Linux kernel it seems that at least it started but there is no NET activity and no messages on UART. Thanks, Andrei From matt@console-pimps.org Wed Aug 18 15:33:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 15:33:19 +0200 (CEST) Received: from arkanian.console-pimps.org ([212.110.184.194]:35160 "EHLO arkanian.console-pimps.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491159Ab0HRNdL (ORCPT ); Wed, 18 Aug 2010 15:33:11 +0200 Received: by arkanian.console-pimps.org (Postfix, from userid 1000) id 8B88548046; Wed, 18 Aug 2010 14:33:11 +0100 (BST) Date: Wed, 18 Aug 2010 14:33:11 +0100 From: Matt Fleming To: Ralf Baechle Cc: linux-mips@linux-mips.org, Paul Gortmaker , gcc@gcc.gnu.org Subject: Re: MIPS: Get rid of branches to .subsections. Message-ID: <20100818133311.GB17957@console-pimps.org> References: <20100818124310.GA23744@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100818124310.GA23744@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27633 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matt@console-pimps.org Precedence: bulk X-list: linux-mips On Wed, Aug 18, 2010 at 01:43:10PM +0100, Ralf Baechle wrote: > It was a nice optimization - on paper at least. In practice it results in > branches that may exceed the maximum legal range for a branch. We can > fight that problem with -ffunction-sections but -ffunction-sections again > is incompatible with -pg used by the function tracer. I'm pretty sure that this check in GCC is historic. I know it has been discussed in the past but I don't think a solution was ever reached and my google skills are failing me, I can't find the discussion in the archives. We maintain a patch at work that removes this check because we always use -ffunction-sections and also needed to be able to profile things. We've never seen any issues. GCC guys, is this check still needed? Does anyone know which architecture required this restriction? From ralf@linux-mips.org Wed Aug 18 15:33:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 15:33:43 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53075 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491184Ab0HRNdi (ORCPT ); Wed, 18 Aug 2010 15:33:38 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7IDXanc026321; Wed, 18 Aug 2010 14:33:37 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7IDXawF026319; Wed, 18 Aug 2010 14:33:36 +0100 Date: Wed, 18 Aug 2010 14:33:36 +0100 From: Ralf Baechle To: naveen yadav Cc: linux-mips@linux-mips.org Subject: Re: kmalloc issue on MIPS target Message-ID: <20100818133336.GA25740@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27634 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Aug 18, 2010 at 06:07:12PM +0530, naveen yadav wrote: > To: majordomo@kvack.org, linux-mips@linux-mips.org Your sentences are to complex for majordomo to understand. Also its area of expertise is generally limited to mailing list related issues. > We are using MIPS(mips32r2) target. when I alloc memory using kmalloc > suppose 28 bytes, the kernel still consume 128 bytes. > > So when I check File on kernel source mach-ip32/kmalloc.h > > Since it is allign to 128 bytes so i understand that even if I > consume 1 byte it will waste 128 bytes. > > #ifndef __ASM_MACH_IP32_KMALLOC_H > #define __ASM_MACH_IP32_KMALLOC_H Eh... That's an IP32-specific header. I have no idea why you're looking at it. It's not being used for your platform. > So I could not understand why it is allign to 128 bytes. Is there any > specific reason for it. ? Each allocation needs some memory for kmalloc's internal bookkeeping, the memory you actually asked for and for cacheline alignment. For very small allocations the later is likely to be larger than the other two so will be the deciding factor in actual memory allocation. The cacheline aligment results in better performance and on non-coherent platforms such as probably yours it is necessary to get get DMA transfers to work right. It would appear that in your case CONFIG_MIPS_L1_CACHE_SHIFT is set to 7. For a MIPS32-based platform (you didn' say what actual processor core!) that appears to be an excessively large number. 32 bytes would be a more typical figure. Just check the kernel bootup messages for the cacheline size if you don't know. Ralf From ralf@linux-mips.org Wed Aug 18 15:42:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 15:42:33 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:32972 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491159Ab0HRNm2 (ORCPT ); Wed, 18 Aug 2010 15:42:28 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7IDgRK8026941; Wed, 18 Aug 2010 14:42:27 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7IDgQoe026939; Wed, 18 Aug 2010 14:42:26 +0100 Date: Wed, 18 Aug 2010 14:42:26 +0100 From: Ralf Baechle To: Sergei Shtylyov Cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: MIPS: Get rid of branches to .subsections. Message-ID: <20100818134226.GB25740@linux-mips.org> References: <20100818124310.GA23744@linux-mips.org> <4C6BDF40.9050804@mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C6BDF40.9050804@mvista.com> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27635 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips MIPS: Get rid of branches to .subsections. It was a nice optimization - on paper at least. In practice it results in branches that may exceed the maximum legal range for a branch. We can fight that problem with -ffunction-sections but -ffunction-sections again is incompatible with -pg used by the function tracer. By rewriting the loop around all simple LL/SC blocks to C we reduce reduce the amount of inline assembler and at the same time allow GCC to often fill the branch delay slots with something sensible or whatever else clever optimization it may have up in its sleeve. With this optimization gone we also no longer need -ffunction-sections, so drop it. This optimization was originally introduced in 2.6.21, commit 5999eca25c1fd4b9b9aca7833b04d10fe4bc877d (linux-mips.org) rsp. f65e4fa8e0c6022ad58dc88d1b11b12589ed7f9f (kernel.org). Original fix for the issues which caused me to pull this optimization by Paul Gortmaker . Signed-off-by: Ralf Baechle -- v3: Spelling fixes and asm labels that became unused by the changed removed. arch/mips/Makefile | 3 arch/mips/include/asm/atomic.h | 208 ++++++++++++++---------------- arch/mips/include/asm/bitops.h | 270 +++++++++++++++++----------------------- arch/mips/include/asm/cmpxchg.h | 7 - arch/mips/include/asm/system.h | 52 +++---- 5 files changed, 243 insertions(+), 297 deletions(-) Index: linux-queue/arch/mips/include/asm/atomic.h =================================================================== --- linux-queue.orig/arch/mips/include/asm/atomic.h +++ linux-queue/arch/mips/include/asm/atomic.h @@ -64,18 +64,16 @@ static __inline__ void atomic_add(int i, } else if (kernel_uses_llsc) { int temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %1 # atomic_add \n" - " addu %0, %2 \n" - " sc %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %0, %1 # atomic_add \n" + " addu %0, %2 \n" + " sc %0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); + } while (unlikely(!temp)); } else { unsigned long flags; @@ -109,18 +107,16 @@ static __inline__ void atomic_sub(int i, } else if (kernel_uses_llsc) { int temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %1 # atomic_sub \n" - " subu %0, %2 \n" - " sc %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %0, %1 # atomic_sub \n" + " subu %0, %2 \n" + " sc %0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); + } while (unlikely(!temp)); } else { unsigned long flags; @@ -156,20 +152,19 @@ static __inline__ int atomic_add_return( } else if (kernel_uses_llsc) { int temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_add_return \n" - " addu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqz %0, 2f \n" - " addu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %1, %2 # atomic_add_return \n" + " addu %0, %1, %3 \n" + " sc %0, %2 \n" + " .set mips0 \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); + } while (unlikely(!result)); + + result = temp + i; } else { unsigned long flags; @@ -205,23 +200,24 @@ static __inline__ int atomic_sub_return( : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); + + result = temp - i; } else if (kernel_uses_llsc) { int temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_sub_return \n" - " subu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqz %0, 2f \n" - " subu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %1, %2 # atomic_sub_return \n" + " subu %0, %1, %3 \n" + " sc %0, %2 \n" + " .set mips0 \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); + } while (unlikely(!result)); + + result = temp - i; } else { unsigned long flags; @@ -279,12 +275,9 @@ static __inline__ int atomic_sub_if_posi " bltz %0, 1f \n" " sc %0, %2 \n" " .set noreorder \n" - " beqz %0, 2f \n" + " beqz %0, 1b \n" " subu %0, %1, %3 \n" " .set reorder \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" "1: \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) @@ -443,18 +436,16 @@ static __inline__ void atomic64_add(long } else if (kernel_uses_llsc) { long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %1 # atomic64_add \n" - " daddu %0, %2 \n" - " scd %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " lld %0, %1 # atomic64_add \n" + " daddu %0, %2 \n" + " scd %0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); + } while (unlikely(!temp)); } else { unsigned long flags; @@ -488,18 +479,16 @@ static __inline__ void atomic64_sub(long } else if (kernel_uses_llsc) { long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %1 # atomic64_sub \n" - " dsubu %0, %2 \n" - " scd %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " lld %0, %1 # atomic64_sub \n" + " dsubu %0, %2 \n" + " scd %0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); + } while (unlikely(!temp)); } else { unsigned long flags; @@ -535,20 +524,19 @@ static __inline__ long atomic64_add_retu } else if (kernel_uses_llsc) { long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_add_return \n" - " daddu %0, %1, %3 \n" - " scd %0, %2 \n" - " beqz %0, 2f \n" - " daddu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " lld %1, %2 # atomic64_add_return \n" + " daddu %0, %1, %3 \n" + " scd %0, %2 \n" + " .set mips0 \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); + } while (unlikely(!result)); + + result = temp + i; } else { unsigned long flags; @@ -587,20 +575,19 @@ static __inline__ long atomic64_sub_retu } else if (kernel_uses_llsc) { long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_sub_return \n" - " dsubu %0, %1, %3 \n" - " scd %0, %2 \n" - " beqz %0, 2f \n" - " dsubu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " lld %1, %2 # atomic64_sub_return \n" + " dsubu %0, %1, %3 \n" + " scd %0, %2 \n" + " .set mips0 \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); + } while (unlikely(!result)); + + result = temp - i; } else { unsigned long flags; @@ -658,12 +645,9 @@ static __inline__ long atomic64_sub_if_p " bltz %0, 1f \n" " scd %0, %2 \n" " .set noreorder \n" - " beqz %0, 2f \n" + " beqz %0, 1b \n" " dsubu %0, %1, %3 \n" " .set reorder \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" "1: \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) Index: linux-queue/arch/mips/include/asm/bitops.h =================================================================== --- linux-queue.orig/arch/mips/include/asm/bitops.h +++ linux-queue/arch/mips/include/asm/bitops.h @@ -73,30 +73,26 @@ static inline void set_bit(unsigned long : "ir" (1UL << bit), "m" (*m)); #ifdef CONFIG_CPU_MIPSR2 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { - __asm__ __volatile__( - "1: " __LL "%0, %1 # set_bit \n" - " " __INS "%0, %4, %2, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m), "r" (~0)); + do { + __asm__ __volatile__( + " " __LL "%0, %1 # set_bit \n" + " " __INS "%0, %3, %2, 1 \n" + " " __SC "%0, %1 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (bit), "r" (~0)); + } while (unlikely(!temp)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (kernel_uses_llsc) { - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # set_bit \n" - " or %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # set_bit \n" + " or %0, %2 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (1UL << bit)); + } while (unlikely(!temp)); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -134,34 +130,30 @@ static inline void clear_bit(unsigned lo " " __SC "%0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << bit)), "m" (*m)); + : "=&r" (temp), "+m" (*m) + : "ir" (~(1UL << bit))); #ifdef CONFIG_CPU_MIPSR2 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { - __asm__ __volatile__( - "1: " __LL "%0, %1 # clear_bit \n" - " " __INS "%0, $0, %2, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m)); + do { + __asm__ __volatile__( + " " __LL "%0, %1 # clear_bit \n" + " " __INS "%0, $0, %2, 1 \n" + " " __SC "%0, %1 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (bit)); + } while (unlikely(!temp)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (kernel_uses_llsc) { - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # clear_bit \n" - " and %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << bit)), "m" (*m)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # clear_bit \n" + " and %0, %2 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (~(1UL << bit))); + } while (unlikely(!temp)); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -213,24 +205,22 @@ static inline void change_bit(unsigned l " " __SC "%0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); + : "=&r" (temp), "+m" (*m) + : "ir" (1UL << bit)); } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # change_bit \n" - " xor %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # change_bit \n" + " xor %0, %2 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m) + : "ir" (1UL << bit)); + } while (unlikely(!temp)); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -272,30 +262,26 @@ static inline int test_and_set_bit(unsig " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) : "memory"); } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_set_bit \n" - " or %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # test_and_set_bit \n" + " or %2, %0, %3 \n" + " " __SC "%2, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) + : "memory"); + } while (unlikely(!res)); + + res = temp & (1UL << bit); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -340,30 +326,26 @@ static inline int test_and_set_bit_lock( " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) : "memory"); } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_set_bit \n" - " or %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # test_and_set_bit \n" + " or %2, %0, %3 \n" + " " __SC "%2, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) + : "memory"); + } while (unlikely(!res)); + + res = temp & (1UL << bit); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -410,49 +392,43 @@ static inline int test_and_clear_bit(uns " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) : "memory"); #ifdef CONFIG_CPU_MIPSR2 } else if (kernel_uses_llsc && __builtin_constant_p(nr)) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - "1: " __LL "%0, %1 # test_and_clear_bit \n" - " " __EXT "%2, %0, %3, 1 \n" - " " __INS "%0, $0, %3, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "ir" (bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " " __LL "%0, %1 # test_and_clear_bit \n" + " " __EXT "%2, %0, %3, 1 \n" + " " __INS "%0, $0, %3, 1 \n" + " " __SC "%0, %1 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "ir" (bit) + : "memory"); + } while (unlikely(!temp)); #endif } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_clear_bit \n" - " or %2, %0, %3 \n" - " xor %2, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # test_and_clear_bit \n" + " or %2, %0, %3 \n" + " xor %2, %3 \n" + " " __SC "%2, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) + : "memory"); + } while (unlikely(!res)); + + res = temp & (1UL << bit); } else { volatile unsigned long *a = addr; unsigned long mask; @@ -499,30 +475,26 @@ static inline int test_and_change_bit(un " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) : "memory"); } else if (kernel_uses_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_change_bit \n" - " xor %2, %0, %3 \n" - " " __SC "\t%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 # test_and_change_bit \n" + " xor %2, %0, %3 \n" + " " __SC "\t%2, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*m), "=&r" (res) + : "r" (1UL << bit) + : "memory"); + } while (unlikely(!res)); + + res = temp & (1UL << bit); } else { volatile unsigned long *a = addr; unsigned long mask; Index: linux-queue/arch/mips/include/asm/cmpxchg.h =================================================================== --- linux-queue.orig/arch/mips/include/asm/cmpxchg.h +++ linux-queue/arch/mips/include/asm/cmpxchg.h @@ -44,12 +44,9 @@ " move $1, %z4 \n" \ " .set mips3 \n" \ " " st " $1, %1 \n" \ - " beqz $1, 3f \n" \ - "2: \n" \ - " .subsection 2 \n" \ - "3: b 1b \n" \ - " .previous \n" \ + " beqz $1, 1b \n" \ " .set pop \n" \ + "2: \n" \ : "=&r" (__ret), "=R" (*m) \ : "R" (*m), "Jr" (old), "Jr" (new) \ : "memory"); \ Index: linux-queue/arch/mips/include/asm/system.h =================================================================== --- linux-queue.orig/arch/mips/include/asm/system.h +++ linux-queue/arch/mips/include/asm/system.h @@ -115,21 +115,19 @@ static inline unsigned long __xchg_u32(v } else if (kernel_uses_llsc) { unsigned long dummy; - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %3 # xchg_u32 \n" - " .set mips0 \n" - " move %2, %z4 \n" - " .set mips3 \n" - " sc %2, %1 \n" - " beqz %2, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " ll %0, %3 # xchg_u32 \n" + " .set mips0 \n" + " move %2, %z4 \n" + " .set mips3 \n" + " sc %2, %1 \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } while (unlikely(!dummy)); } else { unsigned long flags; @@ -167,19 +165,17 @@ static inline __u64 __xchg_u64(volatile } else if (kernel_uses_llsc) { unsigned long dummy; - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %3 # xchg_u64 \n" - " move %2, %z4 \n" - " scd %2, %1 \n" - " beqz %2, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); + do { + __asm__ __volatile__( + " .set mips3 \n" + " lld %0, %3 # xchg_u64 \n" + " move %2, %z4 \n" + " scd %2, %1 \n" + " .set mips0 \n" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); + } while (unlikely(!dummy)); } else { unsigned long flags; Index: linux-queue/arch/mips/Makefile =================================================================== --- linux-queue.orig/arch/mips/Makefile +++ linux-queue/arch/mips/Makefile @@ -48,9 +48,6 @@ ifneq ($(SUBARCH),$(ARCH)) endif endif -ifndef CONFIG_FUNCTION_TRACER -cflags-y := -ffunction-sections -endif ifdef CONFIG_FUNCTION_GRAPH_TRACER ifndef KBUILD_MCOUNT_RA_ADDRESS ifeq ($(call cc-option-yn,-mmcount-ra-address), y) From ralf@linux-mips.org Wed Aug 18 15:51:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 15:51:45 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41629 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491182Ab0HRNvm (ORCPT ); Wed, 18 Aug 2010 15:51:42 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7IDpGOF027188; Wed, 18 Aug 2010 14:51:16 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7IDpFAf027186; Wed, 18 Aug 2010 14:51:15 +0100 Date: Wed, 18 Aug 2010 14:51:15 +0100 From: Ralf Baechle To: "Ardelean, Andrei" Cc: linux-mips@linux-mips.org Subject: Re: Does Mips Linux rely on Yamon h/w initialization (other than DDR memory which is strictly necessary)? Message-ID: <20100818135115.GC25740@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27636 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Aug 18, 2010 at 06:31:42AM -0700, Ardelean, Andrei wrote: > Malta board has Yamon monitor which initializes the DDR memory and other > h/w. Does Mips Linux rely on Yamon h/w initialization (except memory) > like PCI, NET, UART, etc in order to boot? Does Mips Linux re-initialize > the h/w again? > I am booting Linux on Malta with a small monitor which initializes only > the memory. I pass the environment vars array, command line arguments > and memory size as Yamon would do. The ASCII display shows "Linux on > Malta" scrolling text so Linux kernel it seems that at least it started > but there is no NET activity and no messages on UART. That's a bit of an ugly topic and some black art is involved here. We leave the initialization of CPU, caches and memory controllers entirely to the firmware. For the remainder Linux tries to perform the initilization itself but sometimes by accident not intention a register that was already initialized by firmware will not be initialized by Linux but the omission will not be notized because it already has a correct value. PCI is particularl problem. On some platforms firmware initializes the bus and re-initializing the bus would break the firmware or be very complex. On such a system Linux will just scan the PCI bus and re-use the existing configuration. On most platforms however Linux will do a better job than the existing firmware and fully reinitialize the entire PCI bus hierarchy. Ralf From yad.naveen@gmail.com Wed Aug 18 16:26:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 16:26:26 +0200 (CEST) Received: from mail-qy0-f177.google.com ([209.85.216.177]:46302 "EHLO mail-qy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491168Ab0HRO0X convert rfc822-to-8bit (ORCPT ); Wed, 18 Aug 2010 16:26:23 +0200 Received: by qyk8 with SMTP id 8so692676qyk.15 for ; Wed, 18 Aug 2010 07:26:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=M1d6XEdkkewfSxGV3R1NTfHbqE7YdhPYpchurj706Cs=; b=jIyYM53mHfZ59ZZyGOMCk184lri2Nu2vp+YWB4fT1DSGQ4/UyWNTVaYAZjFiOzWow+ L2/lzjkspQO/BERpNfipbI64eoRBjJjFf+Y0/rlEO0r3CbwpV71olAcAYmsJCDIBx29X aHo4pkj0KK6lsB0yG7F7ubFhhTc65qadPuLyI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=WvS8lWtP22ossfR0MLk2zzrz7tjvqK31ZsRcfMS+1B0yn73wy83gf++FteQqYTtNi+ zAD3D7f3LRg2g6bMSUWFZK5fHw+0RFDDrurhIvkqCtKx7c0X2AwvmxpCVKVbsyEyNAxC xrqEpq2V7xeaOhYp9k0NMnyuABSTIJMdYURcc= MIME-Version: 1.0 Received: by 10.229.96.16 with SMTP id f16mr5975504qcn.255.1282141577135; Wed, 18 Aug 2010 07:26:17 -0700 (PDT) Received: by 10.229.20.129 with HTTP; Wed, 18 Aug 2010 07:26:16 -0700 (PDT) In-Reply-To: <20100818133336.GA25740@linux-mips.org> References: <20100818133336.GA25740@linux-mips.org> Date: Wed, 18 Aug 2010 19:56:16 +0530 Message-ID: Subject: Re: kmalloc issue on MIPS target From: naveen yadav To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27637 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Thanks a lot Mr. Ralf Baechle for Quick answer. I will give more info. CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_DMA_NONCOHERENT=y mips 34kc is processor and File we are using is arch/mips/include/asm/mach-generic/kmalloc.h #ifndef __ASM_MACH_GENERIC_KMALLOC_H #define __ASM_MACH_GENERIC_KMALLOC_H #ifndef CONFIG_DMA_COHERENT /* * Total overkill for most systems but need as a safe default. * Set this one if any device in the system might do non-coherent DMA. */ #define ARCH_KMALLOC_MINALIGN 128 #endif #endif /* __ASM_MACH_GENERIC_KMALLOC_H */ So shall we make value ARCH_KMALLOC_MINALIGN from 128 to 32. is there any problem ? Thanks On Wed, Aug 18, 2010 at 7:03 PM, Ralf Baechle wrote: > On Wed, Aug 18, 2010 at 06:07:12PM +0530, naveen yadav wrote: > >> To: majordomo@kvack.org, linux-mips@linux-mips.org > > Your sentences are to complex for majordomo to understand.  Also its > area of expertise is generally limited to mailing list related issues. > >> We are using MIPS(mips32r2) target. when I alloc memory using kmalloc >> suppose  28 bytes, the kernel still consume 128 bytes. >> >> So when I check File on kernel source  mach-ip32/kmalloc.h >> >> Since it is allign to 128 bytes so i understand that even if  I >> consume 1 byte it will waste 128 bytes. >> >> #ifndef __ASM_MACH_IP32_KMALLOC_H >> #define __ASM_MACH_IP32_KMALLOC_H > > Eh...  That's an IP32-specific header.  I have no idea why you're looking > at it.  It's not being used for your platform. > >> So I could not understand why it is allign to 128 bytes. Is there any >> specific reason for it. ? > > Each allocation needs some memory for kmalloc's internal bookkeeping, > the memory you actually asked for and for cacheline alignment.  For very > small allocations the later is likely to be larger than the other two > so will be the deciding factor in actual memory allocation. > > The cacheline aligment results in better performance and on non-coherent > platforms such as probably yours it is necessary to get get DMA transfers > to work right. > > It would appear that in your case CONFIG_MIPS_L1_CACHE_SHIFT is set to 7. > For a MIPS32-based platform (you didn' say what actual processor core!) > that appears to be an excessively large number.  32 bytes would be a more > typical figure.  Just check the kernel bootup messages for the cacheline > size if you don't know. > >  Ralf > From ralf@linux-mips.org Wed Aug 18 16:40:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 16:40:07 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57579 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491168Ab0HROkD (ORCPT ); Wed, 18 Aug 2010 16:40:03 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7IEdTx2028408; Wed, 18 Aug 2010 15:39:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7IEdQgT028402; Wed, 18 Aug 2010 15:39:26 +0100 Date: Wed, 18 Aug 2010 15:39:26 +0100 From: Ralf Baechle To: Stephen Rothwell Cc: Grant Likely , "Dezhong Diao (dediao)" , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, David Daney , "David VomLehn (dvomlehn)" Subject: Re: [PATCH v2 1/2] MIPS: Add device tree support to MIPS Message-ID: <20100818143926.GB2849@linux-mips.org> References: <7A9214B0DEB2074FBCA688B30B04400D013FA46D@XMB-RCD-208.cisco.com> <20100816204211.GA17571@angua.secretlab.ca> <20100817134039.fc1108c7.sfr@canb.auug.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100817134039.fc1108c7.sfr@canb.auug.org.au> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27638 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Aug 17, 2010 at 01:40:39PM +1000, Stephen Rothwell wrote: > On Mon, 16 Aug 2010 14:42:11 -0600 Grant Likely wrote: > > > > I'll also make sure to start build testing on MIPS. Ralf, any suggestions on defconfigs I should use? > > Linux-next does defconfig, allnoconfig, allmodconfig (which has failed > for a long time) and ip32_defconfig for mips and mipsel. I am not sure > if all these are still relevant. > > (http://kisskb.ellerman.id.au/kisskb/branch/9/) Kconfig will pick the default machine which is an IP22 for allyesconfig and allmodconfig. The makefile will then pick the right flags for the compiler based on machine, processor and endian selection. so it'll happily build a big endian kernel with a little endian compiler. All that's really different between those compilers are the defaults. Building more different defconfigs is a better investments of CPU cycles. An issue with very large functionss for which I've posted a patch earlier today used to break makeallconfig / makeallmodconfig on MIPS. I'll sort those out but right now I just don't have the CPU cycles to regularly build such monster kernel configs. A suggested set of kernel defconfigs to test: bigsur_defconfig cavium-octeon_defconfig ip22_defconfig ip27_defconfig ip32_defconfig malta_defconfig allmodconfig These cover a huge variety of features, UP, SMP & weirdo SMP, flatmem & NUMA, 32-bit, 64-bit, little and big endian. Ralf From ralf@linux-mips.org Wed Aug 18 16:43:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 16:43:09 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57593 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491182Ab0HROnF (ORCPT ); Wed, 18 Aug 2010 16:43:05 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7IEh12t028519; Wed, 18 Aug 2010 15:43:01 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7IEh1Hk028517; Wed, 18 Aug 2010 15:43:01 +0100 Date: Wed, 18 Aug 2010 15:43:01 +0100 From: Ralf Baechle To: naveen yadav Cc: linux-mips@linux-mips.org Subject: Re: kmalloc issue on MIPS target Message-ID: <20100818144301.GC2849@linux-mips.org> References: <20100818133336.GA25740@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27639 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Aug 18, 2010 at 07:56:16PM +0530, naveen yadav wrote: > I will give more info. > > CONFIG_MIPS_L1_CACHE_SHIFT=5 > > CONFIG_DMA_NONCOHERENT=y > > mips 34kc is processor > > and File we are using is arch/mips/include/asm/mach-generic/kmalloc.h > > #ifndef __ASM_MACH_GENERIC_KMALLOC_H > #define __ASM_MACH_GENERIC_KMALLOC_H > > > #ifndef CONFIG_DMA_COHERENT > /* > * Total overkill for most systems but need as a safe default. > * Set this one if any device in the system might do non-coherent DMA. > */ > #define ARCH_KMALLOC_MINALIGN 128 > #endif > > #endif /* __ASM_MACH_GENERIC_KMALLOC_H */ > > > So shall we make value ARCH_KMALLOC_MINALIGN from 128 to 32. is > there any problem ? No, that's just what you should do. You do that by putting a file that defines ARCH_KMALLOC_MINALIGN into your platforms's arch/mips/include/asm/mach-/kmalloc.h just like the ip32 file from your original posting. Ralf From Andrei.Ardelean@idt.com Wed Aug 18 17:08:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 17:08:26 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:44525 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491193Ab0HRPIT convert rfc822-to-8bit (ORCPT ); Wed, 18 Aug 2010 17:08:19 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o7IF8Bma027964; Wed, 18 Aug 2010 08:08:11 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o7IF8ATn009454; Wed, 18 Aug 2010 08:08:11 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o7IF8AY26010; Wed, 18 Aug 2010 08:08:10 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: Does Mips Linux rely on Yamon h/w initialization (other than DDR memory which is strictly necessary)? Date: Wed, 18 Aug 2010 08:08:08 -0700 Message-ID: In-Reply-To: <20100818135115.GC25740@linux-mips.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: Does Mips Linux rely on Yamon h/w initialization (other than DDR memory which is strictly necessary)? thread-index: Acs+3BUcAjUYruQ4TUeN15aGwVMTIQACqR4g References: <20100818135115.GC25740@linux-mips.org> From: "Ardelean, Andrei" To: "Ralf Baechle" Cc: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27640 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi Ralf, Could you point me to some files or folder where I can find the h/w initialization sequence done by Linux for Malta? I would like to take a look maybe I can figure out some details. Thanks, Andrei -----Original Message----- From: Ralf Baechle [mailto:ralf@linux-mips.org] Sent: Wednesday, August 18, 2010 9:51 AM To: Ardelean, Andrei Cc: linux-mips@linux-mips.org Subject: Re: Does Mips Linux rely on Yamon h/w initialization (other than DDR memory which is strictly necessary)? On Wed, Aug 18, 2010 at 06:31:42AM -0700, Ardelean, Andrei wrote: > Malta board has Yamon monitor which initializes the DDR memory and other > h/w. Does Mips Linux rely on Yamon h/w initialization (except memory) > like PCI, NET, UART, etc in order to boot? Does Mips Linux re-initialize > the h/w again? > I am booting Linux on Malta with a small monitor which initializes only > the memory. I pass the environment vars array, command line arguments > and memory size as Yamon would do. The ASCII display shows "Linux on > Malta" scrolling text so Linux kernel it seems that at least it started > but there is no NET activity and no messages on UART. That's a bit of an ugly topic and some black art is involved here. We leave the initialization of CPU, caches and memory controllers entirely to the firmware. For the remainder Linux tries to perform the initilization itself but sometimes by accident not intention a register that was already initialized by firmware will not be initialized by Linux but the omission will not be notized because it already has a correct value. PCI is particularl problem. On some platforms firmware initializes the bus and re-initializing the bus would break the firmware or be very complex. On such a system Linux will just scan the PCI bus and re-use the existing configuration. On most platforms however Linux will do a better job than the existing firmware and fully reinitialize the entire PCI bus hierarchy. Ralf From sfr@canb.auug.org.au Wed Aug 18 17:19:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 17:19:11 +0200 (CEST) Received: from chilli.pcug.org.au ([203.10.76.44]:34290 "EHLO smtps.tip.net.au" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491189Ab0HRPTF (ORCPT ); Wed, 18 Aug 2010 17:19:05 +0200 Received: from canb.auug.org.au (ta-1-1.tip.net.au [203.11.71.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtps.tip.net.au (Postfix) with ESMTPSA id 6BD02144001; Thu, 19 Aug 2010 01:19:01 +1000 (EST) Date: Thu, 19 Aug 2010 01:18:56 +1000 From: Stephen Rothwell To: Ralf Baechle Cc: Grant Likely , "Dezhong Diao (dediao)" , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, David Daney , "David VomLehn (dvomlehn)" Subject: Re: [PATCH v2 1/2] MIPS: Add device tree support to MIPS Message-Id: <20100819011856.bfef5f65.sfr@canb.auug.org.au> In-Reply-To: <20100818143926.GB2849@linux-mips.org> References: <7A9214B0DEB2074FBCA688B30B04400D013FA46D@XMB-RCD-208.cisco.com> <20100816204211.GA17571@angua.secretlab.ca> <20100817134039.fc1108c7.sfr@canb.auug.org.au> <20100818143926.GB2849@linux-mips.org> X-Mailer: Sylpheed 3.0.2 (GTK+ 2.20.1; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg="PGP-SHA1"; boundary="Signature=_Thu__19_Aug_2010_01_18_56_+1000_j7Y8IpmBi+6UQ0n9" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27641 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sfr@canb.auug.org.au Precedence: bulk X-list: linux-mips --Signature=_Thu__19_Aug_2010_01_18_56_+1000_j7Y8IpmBi+6UQ0n9 Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Ralf, On Wed, 18 Aug 2010 15:39:26 +0100 Ralf Baechle wrote: > > Kconfig will pick the default machine which is an IP22 for allyesconfig > and allmodconfig. The makefile will then pick the right flags for the > compiler based on machine, processor and endian selection. so it'll > happily build a big endian kernel with a little endian compiler. All > that's really different between those compilers are the defaults. Buildi= ng > more different defconfigs is a better investments of CPU cycles. >=20 > An issue with very large functionss for which I've posted a patch earlier > today used to break makeallconfig / makeallmodconfig on MIPS. I'll sort > those out but right now I just don't have the CPU cycles to regularly > build such monster kernel configs. >=20 > A suggested set of kernel defconfigs to test: >=20 > bigsur_defconfig > cavium-octeon_defconfig > ip22_defconfig > ip27_defconfig > ip32_defconfig > malta_defconfig > allmodconfig >=20 > These cover a huge variety of features, UP, SMP & weirdo SMP, flatmem & N= UMA, > 32-bit, 64-bit, little and big endian. OK, I will adjust the MIPS builds tomorrow. Thanks for the suggestions. Just be clear, I only need to build with one compiler (presumably what gcc/binutils produces when I ask for a "mips" toolchain) and can drop the other ("mipsel"), correct? --=20 Cheers, Stephen Rothwell sfr@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ --Signature=_Thu__19_Aug_2010_01_18_56_+1000_j7Y8IpmBi+6UQ0n9 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQEcBAEBAgAGBQJMa/ngAAoJEDMEi1NhKgbsiXMH/2bOR2K7i9XtpX6mPxzDxame 8CCWt95rYo1+b2e8bKRvHn8gAnjDPVfrXtOMISaodcLdwuvO8PtbD1uOMO93YUej dK1krXMUYf1GMHkyeydTM5KrLOALfY2QpOCmGg3oC0h+WERe5REXw4uNHxYZ3jD8 okNUbMQMT9y+6VodbpfnLK7sksAkJn//F5gdEe+UZCejMzUyLFG4vGpXwpEcvfpQ LFCT+mzlIdW7kEIiwBICQXq8N/D6sFIzavx+E43mt+zxRz7YXlTuJMTMVp8gJqaO v8HAtkGwhzGsQBDFJkbjqOMqRzUDNvmRsuLEl31qFBzqz45+xbCjwt9ykP4SP/k= =FjZK -----END PGP SIGNATURE----- --Signature=_Thu__19_Aug_2010_01_18_56_+1000_j7Y8IpmBi+6UQ0n9-- From yad.naveen@gmail.com Wed Aug 18 17:22:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 17:22:22 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:54592 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491168Ab0HRPWR convert rfc822-to-8bit (ORCPT ); Wed, 18 Aug 2010 17:22:17 +0200 Received: by qwe4 with SMTP id 4so656932qwe.36 for ; Wed, 18 Aug 2010 08:22:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=0XZmn4fu07WnVqtWvtz2aQ3MaSUWN6pYO3VGCUp63hE=; b=yIckD3j+LgmUAccT5nqOoV7izZ3aiGEF5cXIhoJFZLdgKJC7JRMlaEL9T9PDA/oDr3 3jE/CNU/xyKmqbkRj1EumMZ32H2L/JVkqcFHc0bKaBckmgVkiUkqE4M+Qink6r6GnGwB 9HxKJaMToydF2y4zOER0P9jpEkvdk31hfVnXU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=dPY1o+aSazBqqzPtINm8BQ1SHXtXv/j7R9ixzTZ0p7j7f4fWbTOYtoCEN8pGbGUlwl z7XKPlzptu7UNSfkaoSR244MaOyXzor+DCaO05JULqIdiUx9le2r3juuiGDADFHRoiJV zJ59ZVjw830HHU/z83nUCVcS/y7ECtvQe6gik= MIME-Version: 1.0 Received: by 10.224.19.17 with SMTP id y17mr5450677qaa.374.1282144931569; Wed, 18 Aug 2010 08:22:11 -0700 (PDT) Received: by 10.229.20.129 with HTTP; Wed, 18 Aug 2010 08:22:11 -0700 (PDT) In-Reply-To: <20100818144301.GC2849@linux-mips.org> References: <20100818133336.GA25740@linux-mips.org> <20100818144301.GC2849@linux-mips.org> Date: Wed, 18 Aug 2010 20:52:11 +0530 Message-ID: Subject: Re: kmalloc issue on MIPS target From: naveen yadav To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27642 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Hi Ralf, I understand that that I need to make kmalloc.h in my arch specific folder. But I could not get answer, what should be appropriate value of ARCH_KMALLOC_MINALIGN is it 32 or 128 ? Thanks. On Wed, Aug 18, 2010 at 8:13 PM, Ralf Baechle wrote: > On Wed, Aug 18, 2010 at 07:56:16PM +0530, naveen yadav wrote: > >> I will give more info. >> >> CONFIG_MIPS_L1_CACHE_SHIFT=5 >> >> CONFIG_DMA_NONCOHERENT=y >> >> mips 34kc is processor >> >> and File we are using is  arch/mips/include/asm/mach-generic/kmalloc.h >> >> #ifndef __ASM_MACH_GENERIC_KMALLOC_H >> #define __ASM_MACH_GENERIC_KMALLOC_H >> >> >> #ifndef CONFIG_DMA_COHERENT >> /* >>  * Total overkill for most systems but need as a safe default. >>  * Set this one if any device in the system might do non-coherent DMA. >>  */ >> #define ARCH_KMALLOC_MINALIGN   128 >> #endif >> >> #endif /* __ASM_MACH_GENERIC_KMALLOC_H */ >> >> >> So shall we make value ARCH_KMALLOC_MINALIGN   from 128 to 32. is >> there any problem ? > > No, that's just what you should do.  You do that by putting a file > that defines ARCH_KMALLOC_MINALIGN into your platforms's > arch/mips/include/asm/mach-/kmalloc.h just like the ip32 > file from your original posting. > >  Ralf > From ralf@linux-mips.org Wed Aug 18 17:36:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 17:36:46 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58071 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491193Ab0HRPgi (ORCPT ); Wed, 18 Aug 2010 17:36:38 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7IFaPKB029874; Wed, 18 Aug 2010 16:36:25 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7IFaP1o029872; Wed, 18 Aug 2010 16:36:25 +0100 Date: Wed, 18 Aug 2010 16:36:25 +0100 From: Ralf Baechle To: Stephen Rothwell Cc: Grant Likely , "Dezhong Diao (dediao)" , linux-mips@linux-mips.org, devicetree-discuss@lists.ozlabs.org, David Daney , "David VomLehn (dvomlehn)" Subject: Re: [PATCH v2 1/2] MIPS: Add device tree support to MIPS Message-ID: <20100818153625.GA29740@linux-mips.org> References: <7A9214B0DEB2074FBCA688B30B04400D013FA46D@XMB-RCD-208.cisco.com> <20100816204211.GA17571@angua.secretlab.ca> <20100817134039.fc1108c7.sfr@canb.auug.org.au> <20100818143926.GB2849@linux-mips.org> <20100819011856.bfef5f65.sfr@canb.auug.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100819011856.bfef5f65.sfr@canb.auug.org.au> User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27643 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Aug 19, 2010 at 01:18:56AM +1000, Stephen Rothwell wrote: > > A suggested set of kernel defconfigs to test: > > > > bigsur_defconfig > > cavium-octeon_defconfig > > ip22_defconfig > > ip27_defconfig > > ip32_defconfig > > malta_defconfig > > allmodconfig > > > > These cover a huge variety of features, UP, SMP & weirdo SMP, flatmem & NUMA, > > 32-bit, 64-bit, little and big endian. > > OK, I will adjust the MIPS builds tomorrow. Thanks for the suggestions. > Just be clear, I only need to build with one compiler (presumably what > gcc/binutils produces when I ask for a "mips" toolchain) and can drop the > other ("mipsel"), correct? Yes, that's entirely correct. For the sake of others reading this I should mention that some GCC version apparently had a bug which resulted in bad code generation for the non-default ABI. I don't know which versions were affected but for just doing build tests it really doesn't matter. Ralf From sshtylyov@mvista.com Wed Aug 18 18:10:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Aug 2010 18:10:20 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:37344 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491194Ab0HRQKN (ORCPT ); Wed, 18 Aug 2010 18:10:13 +0200 Received: by ewy9 with SMTP id 9so539202ewy.36 for ; Wed, 18 Aug 2010 09:10:12 -0700 (PDT) Received: by 10.213.48.193 with SMTP id s1mr2241561ebf.20.1282147812739; Wed, 18 Aug 2010 09:10:12 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id v8sm741541eeh.8.2010.08.18.09.10.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 18 Aug 2010 09:10:11 -0700 (PDT) Message-ID: <4C6C05B3.7030908@mvista.com> Date: Wed, 18 Aug 2010 20:09:23 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: naveen yadav CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: kmalloc issue on MIPS target References: <20100818133336.GA25740@linux-mips.org> <20100818144301.GC2849@linux-mips.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27644 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. naveen yadav wrote: > Hi Ralf, > I understand that that I need to make kmalloc.h in my arch specific > folder. But I could not get answer, what should be appropriate > value of ARCH_KMALLOC_MINALIGN is it 32 or 128 ? You've been replied already that you should set it to 32. > Thanks. > On Wed, Aug 18, 2010 at 8:13 PM, Ralf Baechle wrote: >> On Wed, Aug 18, 2010 at 07:56:16PM +0530, naveen yadav wrote: >> >>> I will give more info. >>> >>> CONFIG_MIPS_L1_CACHE_SHIFT=5 >>> >>> CONFIG_DMA_NONCOHERENT=y >>> >>> mips 34kc is processor >>> >>> and File we are using is arch/mips/include/asm/mach-generic/kmalloc.h >>> >>> #ifndef __ASM_MACH_GENERIC_KMALLOC_H >>> #define __ASM_MACH_GENERIC_KMALLOC_H >>> >>> >>> #ifndef CONFIG_DMA_COHERENT >>> /* >>> * Total overkill for most systems but need as a safe default. >>> * Set this one if any device in the system might do non-coherent DMA. >>> */ >>> #define ARCH_KMALLOC_MINALIGN 128 >>> #endif >>> >>> #endif /* __ASM_MACH_GENERIC_KMALLOC_H */ >>> So shall we make value ARCH_KMALLOC_MINALIGN from 128 to 32. is >>> there any problem ? >> No, that's just what you should do. You do that by putting a file >> that defines ARCH_KMALLOC_MINALIGN into your platforms's >> arch/mips/include/asm/mach-/kmalloc.h just like the ip32 >> file from your original posting. >> Ralf WBR, Sergei From manuel.lauss@googlemail.com Thu Aug 19 13:37:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Aug 2010 13:37:26 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:49833 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490955Ab0HSLhS (ORCPT ); Thu, 19 Aug 2010 13:37:18 +0200 Received: by bwz13 with SMTP id 13so1726490bwz.36 for ; Thu, 19 Aug 2010 04:37:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=HAscM9toEXSPG89OQZJl79Ic1/P2tWJKYEhoPjt2ExI=; b=d1WaUVmmgc/gtozp8P20R84zGzKEmAyj+q31VxNs6HiZZW60nxWJL+VoemyAK29nED VEDybbg4/kfPR0gIIpUbUMwiqRIdwBpRGuy+PBcf0/lZmUcRCSvNv/0Ep7WopZPIhRQI +6m90xiCuoCXb/R31ZZe3uEWBXzrNx2M2JTvI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=orRkRAMl+iuDE0v/+ybgADLUvwh6JZp75IrnDualtUaBlj4sZ1GxpQw4WosJFLA/2J w5saE9HZq1EKZZTIAEgA/JNqhbvUeVoJT9EzkT4tvHw3b+Nf4Ey2klb7GCeCmfcx+XQm QAyGRXv5dIQ9vCJOgvEOre5fILdd2mSXkjkSo= Received: by 10.204.39.203 with SMTP id h11mr6471484bke.8.1282217838354; Thu, 19 Aug 2010 04:37:18 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id g12sm1028577bkb.2.2010.08.19.04.37.16 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 19 Aug 2010 04:37:16 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: resolve prom section mismatches Date: Thu, 19 Aug 2010 13:37:13 +0200 Message-Id: <1282217833-27119-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27645 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The function prom_init_cmdline() references the variable __initdata arcs_cmdline. The function prom_get_ethernet_addr() references the variable __initdata arcs_cmdline. Annotate prom_init_cmdline() as __init, unexport and annotate prom_get_ethernet_addr() since it's no longer called from within driver code. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/prom.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c index c29511b..5340210 100644 --- a/arch/mips/alchemy/common/prom.c +++ b/arch/mips/alchemy/common/prom.c @@ -43,7 +43,7 @@ int prom_argc; char **prom_argv; char **prom_envp; -void prom_init_cmdline(void) +void __init prom_init_cmdline(void) { int i; @@ -104,7 +104,7 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str) } } -int prom_get_ethernet_addr(char *ethernet_addr) +int __init prom_get_ethernet_addr(char *ethernet_addr) { char *ethaddr_str; @@ -123,7 +123,6 @@ int prom_get_ethernet_addr(char *ethernet_addr) return 0; } -EXPORT_SYMBOL(prom_get_ethernet_addr); void __init prom_free_prom_memory(void) { -- 1.7.2 From anemo@mba.ocn.ne.jp Thu Aug 19 15:29:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Aug 2010 15:29:41 +0200 (CEST) Received: from mv-drv-hcb004.ocn.ad.jp ([118.23.109.134]:53150 "EHLO mv-drv-hcb004.ocn.ad.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490955Ab0HSN3g (ORCPT ); Thu, 19 Aug 2010 15:29:36 +0200 Received: from vcmba.ocn.ne.jp (localhost.localdomain [127.0.0.1]) by mv-drv-hcb004.ocn.ad.jp (Postfix) with ESMTP id 374821B402E; Thu, 19 Aug 2010 22:29:32 +0900 (JST) Received: from localhost (softbank221040169135.bbtec.net [221.40.169.135]) by vcmba.ocn.ne.jp (Postfix) with ESMTP; Thu, 19 Aug 2010 22:29:32 +0900 (JST) Date: Thu, 19 Aug 2010 22:29:28 +0900 (JST) Message-Id: <20100819.222928.35468456.anemo@mba.ocn.ne.jp> To: fujita.tomonori@lab.ntt.co.jp Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: TX49xx: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN From: Atsushi Nemoto In-Reply-To: <20100814160128H.fujita.tomonori@lab.ntt.co.jp> References: <20100814160128H.fujita.tomonori@lab.ntt.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27646 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sat, 14 Aug 2010 16:02:37 +0900, FUJITA Tomonori wrote: > Architectures need to set ARCH_DMA_MINALIGN to the minimum DMA > alignment (the commit > a6eb9fe105d5de0053b261148cee56c94b4720ca). Defining > ARCH_KMALLOC_MINALIGN doesn't work anymore. Thank you for picking this up. Acked-by: Atsushi Nemoto From arrow.ebd@gmail.com Thu Aug 19 17:14:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Aug 2010 17:14:48 +0200 (CEST) Received: from mail-qy0-f170.google.com ([209.85.216.170]:58998 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491060Ab0HSPOp convert rfc822-to-8bit (ORCPT ); Thu, 19 Aug 2010 17:14:45 +0200 Received: by qyk35 with SMTP id 35so3437407qyk.15 for ; Thu, 19 Aug 2010 08:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=E3kMup3DJ2wSuuoW+7YEU9G8hBm2DOwJj4iEy18Dvaw=; b=b+UfviUF04ovJw/DcAzKyRc8rQJ1dH20aepKIkjMRV/rPDLwd7ZsyVDMA0C0qdVCfh 0DwKauWA4cBVPdIIfMUSD9j5mUWW80QfTtNsVsh9HliaefHklEyWabPguUyrAM50Ilwf C/G8swBmnoXg2U78HOwRgUKN4mthSCuGxAxTs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Ib+3ji6e6RO6x5H+imjKfPqqCK+TgGo6k3HngaJpJsLkf4uUowTp3HKIt8OQHJFWs2 ZMEZN3XGqvbl6TCnN1c0oeHTnDmVQ2Hoi92kVjzqsA+HrXF+fv2v3zZbcQgcOUiZSLDV 6jz6ho0wxlFQJ33MEYFkVa8MNT9MDDmfzTisA= MIME-Version: 1.0 Received: by 10.224.28.134 with SMTP id m6mr6616352qac.150.1282230877431; Thu, 19 Aug 2010 08:14:37 -0700 (PDT) Received: by 10.229.30.195 with HTTP; Thu, 19 Aug 2010 08:14:36 -0700 (PDT) In-Reply-To: <20100817124246.GA14155@linux-mips.org> References: <20100817124246.GA14155@linux-mips.org> Date: Thu, 19 Aug 2010 23:14:36 +0800 Message-ID: Subject: Re: [Help] R3000 CPU porting, Oops while run app From: arrow zhang To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27647 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arrow.ebd@gmail.com Precedence: bulk X-list: linux-mips Dear ralf, > Most systems define MIPS_CPU_IRQ_BASE as 0 so be careful that your > set_irq_chip_and_handler loop doesn't overwrite any previous setup by > mips_cpu_irq_init.  If your interrupt controller has 32 interrupts you > probably want to assign interrupts 0..7 to the CPU interrupts and 8..39 > to the other controller. thanks for the tips, I take a mistake that it could not be overwrite Would like your help on my following question, thanks 1, I found that some CPU(e.g. ar7) does not request_irq on TC0_IRQ, do not deal with the timer interrupt, and do not call function do_timer(1). 2, But I must request a IRQ to deal with TC0_IRQ and call do_timer(1) && update_process_times, (this is porting from vendor released code) 3, How the AR7(or other MIPS SOC) deal with timer interrupt and update the jiffies ? thanks Arrow From yad.naveen@gmail.com Thu Aug 19 17:34:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Aug 2010 17:34:31 +0200 (CEST) Received: from mail-qy0-f170.google.com ([209.85.216.170]:34317 "EHLO mail-qy0-f170.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491056Ab0HSPe1 (ORCPT ); Thu, 19 Aug 2010 17:34:27 +0200 Received: by qyk35 with SMTP id 35so3459758qyk.15 for ; Thu, 19 Aug 2010 08:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=qRAgrTnodrP/YVWk+FP8mGHrHv4s1YXR1mwNYuYmvKA=; b=wRg0nAZDh9bo5/db2olcJBXqpfNWrDg+ggjiX+JfiYI9havaqf6xm4x58wUc8ZiDh3 u6HZE0bAQ8gFEwdN0JypCVtViCV/1l2KpdGvm45PDXncTnFDpjRSbtwGaK0G1vEPbBVE QFuKiE7b0cxOemLTCbvQX4XUU2FIXQNGNB6ps= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=Ft4UZo3bkk9XDzkU67ApA1YBeIgoC0SFLB0eq2rU7cdFIfoVCI89SQgvsQdggUN5mN 053q/6HEkh8J4BokOzZmpycQ74ePX23wEESPQ/Upb/9KW4TKTCddfWXZwwsvcK3Z30PY xA8G6tkh16nSE7o80WPjq4NpdKvBlbe28s1oU= MIME-Version: 1.0 Received: by 10.224.87.1 with SMTP id u1mr6591516qal.292.1282232061626; Thu, 19 Aug 2010 08:34:21 -0700 (PDT) Received: by 10.229.20.129 with HTTP; Thu, 19 Aug 2010 08:34:21 -0700 (PDT) Date: Thu, 19 Aug 2010 21:04:21 +0530 Message-ID: Subject: sparsemem support on MIPS From: naveen yadav To: Ralf Baechle , linux-mips@linux-mips.org, sshtylyov@mvista.com Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27648 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yad.naveen@gmail.com Precedence: bulk X-list: linux-mips Dear all, I build MIPS 32 with sparsemem support to take care of holes in physical memory, this conserve memory but put overhead to speed because of pointer redirection in pfn_to_page(). To prevent this conversion I tried to use CONFIG_SPARSEMEM_VMEMMAP_ENABLE on MIPS 32 but kernel build fails becauase most of the supported functions related to vmemmap are supported for 64 bit architectures only. I wish to compare memory and speed result with / without CONFIG_SPARSEMEM_VMEMMAP_ENABLE in MIPS 32. I need your comment in it ? Thanks From greg@kroah.com Thu Aug 19 19:43:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Aug 2010 19:43:59 +0200 (CEST) Received: from kroah.org ([198.145.64.141]:54713 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491070Ab0HSRny (ORCPT ); Thu, 19 Aug 2010 19:43:54 +0200 Received: from localhost (c-24-16-163-131.hsd1.wa.comcast.net [24.16.163.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id BF916489B2; Thu, 19 Aug 2010 10:43:45 -0700 (PDT) Date: Thu, 19 Aug 2010 10:43:41 -0700 From: Greg KH To: David VomLehn Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, ralf@linux-mips.org Subject: Re: [PATCH 1/2][USB] USB/PowerTV: Add support for PowerTV USB interface Message-ID: <20100819174341.GA13561@kroah.com> References: <20100803014054.GA31524@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100803014054.GA31524@dvomlehn-lnx2.corp.sa.net> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27649 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: greg@kroah.com Precedence: bulk X-list: linux-mips On Mon, Aug 02, 2010 at 06:40:54PM -0700, David VomLehn wrote: > Add support for the Cisco PowerTV USB interface. > > This is a very simple set of glue functions, apparently derived some time > ago from the au1xxx driver by Matt Porter. > > Signed-off-by: David VomLehn Do you want me to take this through the USB tree? It's that useful without the 2/2 patch, right? If so, Ralf, feel free to add this to your tree with an: Acked-by: Greg Kroah-Hartman to the patch. If not, I'll be glad to take it in mine, just let me know. thanks, greg k-h From dvomlehn@cisco.com Fri Aug 20 00:55:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Aug 2010 00:55:49 +0200 (CEST) Received: from sj-iport-4.cisco.com ([171.68.10.86]:46939 "EHLO sj-iport-4.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491099Ab0HSWzo (ORCPT ); Fri, 20 Aug 2010 00:55:44 +0200 Authentication-Results: sj-iport-4.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAF9TbUyrRN+J/2dsb2JhbACgUnGkW5tkghWDIgSEMw X-IronPort-AV: E=Sophos;i="4.56,235,1280707200"; d="scan'208";a="174359479" Received: from sj-core-3.cisco.com ([171.68.223.137]) by sj-iport-4.cisco.com with ESMTP; 19 Aug 2010 22:55:37 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-3.cisco.com (8.13.8/8.14.3) with ESMTP id o7JMtZk5021019; Thu, 19 Aug 2010 22:55:35 GMT Date: Thu, 19 Aug 2010 15:55:37 -0700 From: David VomLehn To: Greg KH Cc: linux-mips@linux-mips.org, linux-usb@vger.kernel.org, ralf@linux-mips.org Subject: Re: [PATCH 1/2][USB] USB/PowerTV: Add support for PowerTV USB interface Message-ID: <20100819225537.GA9830@dvomlehn-lnx2.corp.sa.net> References: <20100803014054.GA31524@dvomlehn-lnx2.corp.sa.net> <20100819174341.GA13561@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100819174341.GA13561@kroah.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27650 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Thu, Aug 19, 2010 at 10:43:41AM -0700, Greg KH wrote: > On Mon, Aug 02, 2010 at 06:40:54PM -0700, David VomLehn wrote: > > Add support for the Cisco PowerTV USB interface. > > > > This is a very simple set of glue functions, apparently derived some time > > ago from the au1xxx driver by Matt Porter. > > > > Signed-off-by: David VomLehn > > Do you want me to take this through the USB tree? It's that useful > without the 2/2 patch, right? Yes, this is not useful without the 2/2 patch. > If so, Ralf, feel free to add this to your tree with an: > Acked-by: Greg Kroah-Hartman > to the patch. > > If not, I'll be glad to take it in mine, just let me know. If it's okay with Ralf, it's okay with me. > thanks, > > greg k-h Thanks! -- David VL From dvomlehn@cisco.com Fri Aug 20 01:06:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Aug 2010 01:06:28 +0200 (CEST) Received: from sj-iport-6.cisco.com ([171.71.176.117]:61084 "EHLO sj-iport-6.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490979Ab0HSXGU (ORCPT ); Fri, 20 Aug 2010 01:06:20 +0200 Authentication-Results: sj-iport-6.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-AV: E=Sophos;i="4.56,235,1280707200"; d="scan'208";a="576108038" Received: from sj-core-4.cisco.com ([171.68.223.138]) by sj-iport-6.cisco.com with ESMTP; 19 Aug 2010 23:06:13 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-4.cisco.com (8.13.8/8.14.3) with ESMTP id o7JN6DIP029676; Thu, 19 Aug 2010 23:06:13 GMT Date: Thu, 19 Aug 2010 16:06:14 -0700 From: David VomLehn To: naveen yadav Cc: Ralf Baechle , linux-mips@linux-mips.org, sshtylyov@mvista.com, Michael Sundius Subject: Re: sparsemem support on MIPS Message-ID: <20100819230613.GA10992@dvomlehn-lnx2.corp.sa.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27651 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Thu, Aug 19, 2010 at 09:04:21PM +0530, naveen yadav wrote: > > Dear all, > > I build MIPS 32 with sparsemem support to take care of holes in > physical memory, this conserve memory but put overhead to speed > because of pointer redirection in pfn_to_page(). > > To prevent this conversion I tried to use > CONFIG_SPARSEMEM_VMEMMAP_ENABLE on MIPS 32 but kernel build fails > becauase most of the supported functions related to vmemmap are > supported for 64 bit architectures only. > > I wish to compare memory and speed result with / without > CONFIG_SPARSEMEM_VMEMMAP_ENABLE in MIPS 32. I need your comment in it > ? We use sparse memory and submitted a patch some while ago to add support, but it died for lack of interest. The patch was relative to a kernel from several released ago; I don't know whether it would apply to the tip. I can see if I track it down. -- David VL From jfraser@broadcom.com Fri Aug 20 01:20:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Aug 2010 01:20:10 +0200 (CEST) Received: from mms2.broadcom.com ([216.31.210.18]:2691 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491018Ab0HSXUG (ORCPT ); Fri, 20 Aug 2010 01:20:06 +0200 Received: from [10.9.200.133] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Thu, 19 Aug 2010 16:19:47 -0700 X-Server-Uuid: D3C04415-6FA8-4F2C-93C1-920E106A2031 Received: from mail-irva-12.broadcom.com (10.11.16.101) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Thu, 19 Aug 2010 16:21:05 -0700 Received: from [10.28.6.13] (lab-mhtb-013.and.broadcom.com [10.28.6.13]) by mail-irva-12.broadcom.com (Postfix) with ESMTP id 98BE169CA8; Thu, 19 Aug 2010 16:19:46 -0700 (PDT) Subject: Re: sparsemem support on MIPS From: "Jon Fraser" Reply-to: jfraser@broadcom.com To: "David VomLehn" cc: jfraser@broadcom.com, "naveen yadav" , "Ralf Baechle" , "linux-mips@linux-mips.org" , "sshtylyov@mvista.com" , "Michael Sundius" In-Reply-To: <20100819230613.GA10992@dvomlehn-lnx2.corp.sa.net> References: <20100819230613.GA10992@dvomlehn-lnx2.corp.sa.net> Date: Thu, 19 Aug 2010 19:19:45 -0400 Message-ID: <1282259985.10583.79.camel@chaos.and.broadcom.com> MIME-Version: 1.0 X-Mailer: Evolution 2.12.3 (2.12.3-5.fc8) X-WSS-ID: 607363993DO9311664-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27652 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jfraser@broadcom.com Precedence: bulk X-list: linux-mips On Thu, 2010-08-19 at 16:06 -0700, David VomLehn wrote: > On Thu, Aug 19, 2010 at 09:04:21PM +0530, naveen yadav wrote: > > > > Dear all, > > > > I build MIPS 32 with sparsemem support to take care of holes in > > physical memory, this conserve memory but put overhead to speed > > because of pointer redirection in pfn_to_page(). > > > > To prevent this conversion I tried to use > > CONFIG_SPARSEMEM_VMEMMAP_ENABLE on MIPS 32 but kernel build fails > > becauase most of the supported functions related to vmemmap are > > supported for 64 bit architectures only. > > > > I wish to compare memory and speed result with / without > > CONFIG_SPARSEMEM_VMEMMAP_ENABLE in MIPS 32. I need your comment in it > > ? > > We use sparse memory and submitted a patch some while ago to add support, > but it died for lack of interest. The patch was relative to a kernel > from several released ago; I don't know whether it would apply to > the tip. I can see if I track it down. I keep thinking we should have a git tree for highmem 'experimental' changes. Some of us are shipping highmem, discontiguous memory systems in high volume. --jfraser From msundius@cisco.com Fri Aug 20 01:30:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Aug 2010 01:30:15 +0200 (CEST) Received: from sj-iport-4.cisco.com ([171.68.10.86]:22336 "EHLO sj-iport-4.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491018Ab0HSXaL (ORCPT ); Fri, 20 Aug 2010 01:30:11 +0200 Authentication-Results: sj-iport-4.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-AV: E=Sophos;i="4.56,236,1280707200"; d="scan'208";a="174372968" Received: from sj-core-1.cisco.com ([171.71.177.237]) by sj-iport-4.cisco.com with ESMTP; 19 Aug 2010 23:30:03 +0000 Received: from msundius-lnx1.corp.sa.net (dhcp-171-71-47-156.cisco.com [171.71.47.156]) by sj-core-1.cisco.com (8.13.8/8.14.3) with ESMTP id o7JNU32N018509; Thu, 19 Aug 2010 23:30:03 GMT Message-ID: <4C6DBE76.8050907@cisco.com> Date: Thu, 19 Aug 2010 16:29:58 -0700 From: Michael Sundius User-Agent: Thunderbird 2.0.0.23 (X11/20090825) MIME-Version: 1.0 To: David VomLehn CC: naveen yadav , Ralf Baechle , linux-mips@linux-mips.org, sshtylyov@mvista.com Subject: Re: sparsemem support on MIPS References: <20100819230613.GA10992@dvomlehn-lnx2.corp.sa.net> In-Reply-To: <20100819230613.GA10992@dvomlehn-lnx2.corp.sa.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27653 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: msundius@cisco.com Precedence: bulk X-list: linux-mips David VomLehn wrote: > On Thu, Aug 19, 2010 at 09:04:21PM +0530, naveen yadav wrote: > >> Dear all, >> >> I build MIPS 32 with sparsemem support to take care of holes in >> physical memory, this conserve memory but put overhead to speed >> because of pointer redirection in pfn_to_page(). >> >> To prevent this conversion I tried to use >> CONFIG_SPARSEMEM_VMEMMAP_ENABLE on MIPS 32 but kernel build fails >> becauase most of the supported functions related to vmemmap are >> supported for 64 bit architectures only. >> >> I wish to compare memory and speed result with / without >> CONFIG_SPARSEMEM_VMEMMAP_ENABLE in MIPS 32. I need your comment in it >> ? >> > > We use sparse memory and submitted a patch some while ago to add support, > but it died for lack of interest. The patch was relative to a kernel > from several released ago; I don't know whether it would apply to > the tip. I can see if I track it down. > Please find my original patch below. Note that we also tried to use the virtually mapped sparsemem but failed. for the vmemmap sparse support, one thing I found was you need to do paging_init() before sparse_init(). I also made lots of changes to arch/mips/mm/init.c (some specific to our own changes others generic) and moved a few things in header files around. I can probably (tomorrow) create a patch of my changes that I made (that never worked) for the vmemmap support. I'd love to revisit this one find day and get it to actually work, but I seemed at the time to get stuck without any clue how to move it forward. some collaboration would be greatfully appreciated. Mike Looks great to me. I can't test it, of course, but I don't see any problems with it. Signed-off-by: Dave Hansen -- Dave > Otherwise it looks good to me. I see from the rest of the thread that > there is some discussion over the sizes of these, with that sorted. > > Acked-by: Andy Whitcroft > > -apw > attached is my most recent patch with I *think* everyones requests for it. ------------------------------------------------------------------------ diff --git a/Documentation/sparsemem.txt b/Documentation/sparsemem.txt new file mode 100644 index 0000000..0b36412 --- /dev/null +++ b/Documentation/sparsemem.txt @@ -0,0 +1,92 @@ +Sparsemem divides up physical memory in your system into N sections of M +bytes. Page tables are created for only those sections that +actually exist (as far as the sparsemem code is concerned). This allows +for holes in the physical memory without having to waste space by +creating page descriptors for those pages that do not exist. +When page_to_pfn() or pfn_to_page() are called there is a bit of overhead to +look up the proper memory section to get to the page_table, but this +is small compared to the memory you are likely to save. So, it's not the +default, but should be used if you have big holes in physical memory. + +Note that discontiguous memory is more closely related to NUMA machines +and if you are a single CPU system use sparsemem and not discontig. +It's much simpler. + +1) CALL MEMORY_PRESENT() +Existing sections are recorded once the bootmem allocator is up and running by +calling the sparsemem function "memory_present(node, pfn_start, pfn_end)" for each +block of memory that exists in your physical address space. The +memory_present() function records valid sections in a data structure called +mem_section[]. + +2) DETERMINE AND SET THE SIZE OF SECTIONS AND PHYSMEM +The size of N and M above depend upon your architecture +and your platform and are specified in the file: + + include/asm-/sparsemem.h + +and you should create the following lines similar to below: + + #ifdef CONFIG_YOUR_PLATFORM + #define SECTION_SIZE_BITS 27 /* 128 MiB */ + #endif + #define MAX_PHYSMEM_BITS 31 /* 2 GiB */ + +if they don't already exist, where: + + * SECTION_SIZE_BITS 2^M: how big each section will be + * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that + space + +3) INITIALIZE SPARSE MEMORY +You should make sure that you initialize the sparse memory code by calling + + bootmem_init(); + + sparse_init(); + paging_init(); + +just before you call paging_init() and after the bootmem_allocator is +turned on in your setup_arch() code. + +4) ENABLE SPARSEMEM IN KCONFIG +Add a line like this: + + select ARCH_SPARSEMEM_ENABLE + +into the config for your platform in arch//Kconfig. This will +ensure that turning on sparsemem is enabled for your platform. + +5) CONFIG +Run make *config, as you like, and turn on the sparsemem +memory model under the "Kernel Type" --> "Memory Model" and then build your +kernel. + + +6) Gotchas + +One trick that I encountered when I was turning this on for MIPS was that there +was some code in mem_init() that set the "reserved" flag for pages that were not +valid RAM. This caused my kernel to crash when I enabled sparsemem since those +pages (and page descriptors) didn't actually exist. I changed my code by adding +lines like below: + + + for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) { + struct page *page = pfn_to_page(tmp); + + + if (!pfn_valid(tmp)) + + continue; + + + if (!page_is_ram(tmp)) { + SetPageReserved(page); + continue; + } + ClearPageReserved(page); + init_page_count(page); + __free_page(page); + physmem_record(PFN_PHYS(tmp), PAGE_SIZE, physmem_highmem); + totalhigh_pages++; + } + + +Once I got that straight, it worked!!!! I saved 10MiB of memory. diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index f8a535a..6ff0f72 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -405,7 +405,6 @@ static void __init bootmem_init(void) /* Register lowmem ranges */ free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT); - memory_present(0, start, end); } /* @@ -417,6 +416,23 @@ static void __init bootmem_init(void) * Reserve initrd memory if needed. */ finalize_initrd(); + + /* call memory present for all the ram */ + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long start, end; + + /* + * * memory present only usable memory. + * */ + if (boot_mem_map.map[i].type != BOOT_MEM_RAM) + continue; + + start = PFN_UP(boot_mem_map.map[i].addr); + end = PFN_DOWN(boot_mem_map.map[i].addr + + boot_mem_map.map[i].size); + + memory_present(0, start, end); + } } #endif /* CONFIG_SGI_IP27 */ diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 480dec0..9bc6d35 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -417,6 +417,9 @@ void __init mem_init(void) for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) { struct page *page = pfn_to_page(tmp); + if (!pfn_valid(tmp)) + continue; + if (!page_is_ram(tmp)) { SetPageReserved(page); continue; diff --git a/include/asm-mips/sparsemem.h b/include/asm-mips/sparsemem.h index 795ac6c..67245cb 100644 --- a/include/asm-mips/sparsemem.h +++ b/include/asm-mips/sparsemem.h @@ -6,7 +6,7 @@ * SECTION_SIZE_BITS 2^N: how big each section will be * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space */ -#define SECTION_SIZE_BITS 28 +#define SECTION_SIZE_BITS 27 #define MAX_PHYSMEM_BITS 35 #endif /* CONFIG_SPARSEMEM */ From miloody@gmail.com Fri Aug 20 15:42:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Aug 2010 15:42:34 +0200 (CEST) Received: from mail-yx0-f177.google.com ([209.85.213.177]:65026 "EHLO mail-yx0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491015Ab0HTNm2 (ORCPT ); Fri, 20 Aug 2010 15:42:28 +0200 Received: by yxf34 with SMTP id 34so1429471yxf.36 for ; Fri, 20 Aug 2010 06:42:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=Oo82OnZOex9sdFJkowtN9hlCzrYAZYI04vwWsrxCwoI=; b=fFguhvN1r5deQ89W6YjaUt6dC2RMbkkdFND1FPaoNgEScq7CijSXDJGYNv0byndp/5 sEbXE/VlX2z8kC5euIy4cJ+mEhMoLRjKObMdHWgH/GF8hrRcCm14+Vi8Xt5D44lX+zKm ES08w3vzMrSF6fJSm6u6AFzgEIp7wa70f0dso= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=XvS0wKvzYnKVO0RGJKOJOIcQ0nDzcSvqiXJCxWQQ9GEbAskx5YKR79Jnj02lehLO4f 3EeDOYsrnijA0C4KMEty50sv4nBqtbst4YiINwezwwp9hfo9/+E+hO3v/M/oyUOi9tJ2 M6Lh/uBYamxrNlr6Sj2D1GfK7d1LDXqTjrYaw= MIME-Version: 1.0 Received: by 10.90.63.18 with SMTP id l18mr1098334aga.140.1282311739798; Fri, 20 Aug 2010 06:42:19 -0700 (PDT) Received: by 10.231.116.148 with HTTP; Fri, 20 Aug 2010 06:42:19 -0700 (PDT) Date: Fri, 20 Aug 2010 21:42:19 +0800 Message-ID: Subject: Some questions about exceptions? From: loody To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27654 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Dear all: When I read mips spec there is an exception called MCheck and my questions are: 1. Does this exception only happen on write? 2. The spec says this exception happens when following conditions matched: a. Existing Page Valid Bit = 1 b. Written Page Valid Bit = 1 what is the correct definition of "Existing Page" and "Written Page"? I guess the definition of "Written Page" is teh PFN we get from TLB. But what is "Existing Page"? 3. I google a paragraph which discuss about this exception, http://www.spinics.net/lists/mips/msg19804.html But I cannot find the reason why it happened from the log. The entries in TLB seems fine. BTW, where I can find kernel 1. first time fill Page blobal directory 2. handle a. tlb refill, invalid and modified? appreciate your help, miloody From dvomlehn@cisco.com Fri Aug 20 22:51:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Aug 2010 22:52:10 +0200 (CEST) Received: from sj-iport-6.cisco.com ([171.71.176.117]:4149 "EHLO sj-iport-6.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491753Ab0HTUvz (ORCPT ); Fri, 20 Aug 2010 22:51:55 +0200 Authentication-Results: sj-iport-6.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAAqIbkyrR7Ht/2dsb2JhbACgPXGgBZtZgmWCUgSENA X-IronPort-AV: E=Sophos;i="4.56,242,1280707200"; d="scan'208";a="576559933" Received: from sj-core-1.cisco.com ([171.71.177.237]) by sj-iport-6.cisco.com with ESMTP; 20 Aug 2010 20:51:42 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-1.cisco.com (8.13.8/8.14.3) with ESMTP id o7KKpg3o005557; Fri, 20 Aug 2010 20:51:42 GMT Date: Fri, 20 Aug 2010 13:51:42 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH][MIPS] PowerTV: Cleanup code to handle early bootmem allocations Message-ID: <20100820205142.GA2543@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27655 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Change how memory is set up, especially before the page allocator is ready Cleanup and divide the work of reserving pre-allocated memory into two pieces: 1. Avoid passing RAM for fixed-address pre-allocated memory to the boot allocator. This is done before the boot allocator is initialized. 2. After the slab allocator is initialized, allocate memory for the pre-allocations that do not have fixed address, then add resources for both fixed and non-fixed address preallocations Also, switch to PREALLOC_* macros in arch/mips/powertv/asic/prealloc-gaia.c to manage their configuration. Signed-off-by: David VomLehn --- arch/mips/include/asm/mach-powertv/asic.h | 30 +- arch/mips/include/asm/mach-powertv/painting.h | 224 ++++++++ .../include/asm/mach-powertv/powertv-prealloc.h | 51 ++ arch/mips/include/asm/mach-powertv/prealloc.h | 121 +++++ arch/mips/powertv/Kconfig | 12 + arch/mips/powertv/asic/Kconfig | 38 +- arch/mips/powertv/asic/Makefile | 6 +- arch/mips/powertv/asic/asic_devices.c | 219 ++------- arch/mips/powertv/asic/asic_int.c | 4 +- arch/mips/powertv/asic/painting.c | 298 ++++++++++ arch/mips/powertv/asic/powertv-prealloc.c | 136 +++++ arch/mips/powertv/asic/prealloc-calliope.c | 9 +- arch/mips/powertv/asic/prealloc-cronus.c | 7 +- arch/mips/powertv/asic/prealloc-cronuslite.c | 5 +- arch/mips/powertv/asic/prealloc-gaia.c | 490 ++++------------- arch/mips/powertv/asic/prealloc-zeus.c | 7 +- arch/mips/powertv/asic/prealloc.c | 566 ++++++++++++++++++++ arch/mips/powertv/asic/prealloc.h | 70 --- arch/mips/powertv/init.c | 4 +- arch/mips/powertv/ioremap.c | 38 +- arch/mips/powertv/memory.c | 203 ++----- arch/mips/powertv/powertv_setup.c | 4 +- 22 files changed, 1690 insertions(+), 852 deletions(-) diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h index c7077a6..0d7f8a5 100644 --- a/arch/mips/include/asm/mach-powertv/asic.h +++ b/arch/mips/include/asm/mach-powertv/asic.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Cisco Systems, Inc. + * Copyright (C) 2009-2010 Cisco Systems, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,20 +51,9 @@ extern const struct register_map cronus_register_map; extern const struct register_map gaia_register_map; extern const struct register_map zeus_register_map; -extern struct resource dvr_cronus_resources[]; -extern struct resource dvr_gaia_resources[]; -extern struct resource dvr_zeus_resources[]; -extern struct resource non_dvr_calliope_resources[]; -extern struct resource non_dvr_cronus_resources[]; -extern struct resource non_dvr_cronuslite_resources[]; -extern struct resource non_dvr_gaia_resources[]; -extern struct resource non_dvr_vz_calliope_resources[]; -extern struct resource non_dvr_vze_calliope_resources[]; -extern struct resource non_dvr_vzf_calliope_resources[]; -extern struct resource non_dvr_zeus_resources[]; - +/* Platform resources management */ +extern void platform_reserve_bootmem(void); extern void powertv_platform_init(void); -extern void platform_alloc_bootmem(void); extern enum asic_type platform_get_asic(void); extern enum family_type platform_get_family(void); extern int platform_supports_dvr(void); @@ -73,11 +62,6 @@ extern int platform_supports_pcie(void); extern int platform_supports_display(void); extern void configure_platform(void); -/* Platform Resources */ -#define ASIC_RESOURCE_GET_EXISTS 1 -extern struct resource *asic_resource_get(const char *name); -extern void platform_release_memory(void *baddr, int size); - /* USB configuration */ struct usb_hcd; /* Forward reference */ extern void platform_configure_usb_ehci(void); @@ -87,8 +71,16 @@ extern void platform_unconfigure_usb_ohci(void); /* Resource for ASIC registers */ extern struct resource asic_resource; +#ifdef CONFIG_USB extern int platform_usb_devices_init(struct platform_device **echi_dev, struct platform_device **ohci_dev); +#else +static inline int platform_usb_devices_init(struct platform_device **echi_dev, + struct platform_device **ohci_dev) +{ + return 0; +} +#endif /* Reboot Cause */ extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); diff --git a/arch/mips/include/asm/mach-powertv/painting.h b/arch/mips/include/asm/mach-powertv/painting.h new file mode 100644 index 0000000..b748c81 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/painting.h @@ -0,0 +1,224 @@ +/* + * painting.h + * + * Definitions to use the paint interface, which allows painting kernel + * memory allocations in order to be able to track memory usage. + * + * Author: David VomLehn + */ +/* + * Copyright (C) 2008-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PAINTING_H_ +#define _PAINTING_H_ +#include +#include +#include +#include +#include + +/* Classifications of relationships between two areas */ +#define MISMATCH_CUR_ENDS_FIRST ((0 << 1) | 0) +#define MISMATCH_CUR_ENDS_LAST ((0 << 1) | 1) +#define MATCH_CUR_ENDS_FIRST ((1 << 1) | 0) +#define MATCH_CUR_ENDS_LAST ((1 << 1) | 1) + +struct painting_desc { + phys_addr_t p; /* Starting location */ + phys_addr_t q; /* Ending location, inclusive */ + const void *color; /* "color" */ +}; + +/* Data structure that holds the information for one painting area */ +struct painting_area { + struct rb_node node; + struct painting_desc desc; +}; + +/* Operations for a particular painting object */ +struct painting_ops { + struct painting_area *(*alloc)(void *ctx); + void (*free)(void *ctx, + const struct painting_area *area); + bool (*equals)(const void *l, const void *r); +}; + +/* Basic paint object */ +struct painting { + struct rb_root root; + struct list_head areas; +}; + +#define PAINTING_INIT(name) \ + { \ + .root = RB_ROOT, \ + .areas = LIST_HEAD_INIT(name.areas), \ + } + +#define PAINTING(name) struct painting name = PAINTING_INIT(name) + +static inline void INIT_PAINTING(struct painting *this) +{ + this->root = RB_ROOT; +} + +#define painting_for_each_area(pos, this) \ + for ((pos) = painting_first(this); \ + (pos) != NULL; \ + (pos) = painting_next(pos)) + +#define painting_for_each_area_save(pos, n, this) \ + for ((pos) = painting_first(this), \ + (n) = (((pos) == NULL) ? NULL : painting_next(pos)); \ + (pos) != NULL; \ + (pos) = (n), \ + (n) = (((pos) == NULL) ? NULL : painting_next(pos))) + +/* Functions */ +extern struct painting_area *find_neighbor(const struct painting *this, + phys_addr_t p); +extern struct painting_area * + painting_do_prev_overlaps_and_abuts(struct painting *this, + struct painting_area *cur, struct painting_desc *new, + struct painting_area *tail); +extern struct painting_area *do_successor(struct painting *this, + struct painting_area *cur, struct painting_desc *new); +extern int finish_new_allocation(struct painting *this, + struct painting_area *newp, struct painting_desc *new); + +/* + * _painting_from_rb - convert an rb_node to the containing &painting_area + * @rb: Pointer to the &struct rb_node + */ +static struct painting_area *__pure _painting_from_rb(struct rb_node *node) +{ + return (node == NULL) ? NULL : + container_of(node, struct painting_area, node); +} + +/** + * painting_area_first - find the first &painting_area in a &painting + * @painting: Pointer to a &struct pointing + * Returns NULL if no areas are in the &painting, otherwise a pointer to + * the first &struct painting_area. + */ +static inline struct painting_area *__pure + painting_first(const struct painting *p) +{ + return _painting_from_rb(rb_first(&p->root)); +} + +/** + * painting_next - find the next &painting_area + * @p: Pointer to a &struct painting_area + * + * Returns a pointer to the next &struct painting_area + */ +static inline struct painting_area *__pure + painting_next(const struct painting_area *p) +{ + return _painting_from_rb(rb_next(&p->node)); +} + +/** + * painting_prev - find the previous &painting_area + * @p: Pointer to a &struct painting_area + * + * Returns a pointer to the previous &struct painting_area + */ +static inline struct painting_area *__pure + painting_prev(const struct painting_area *p) +{ + return _painting_from_rb(rb_prev(&p->node)); +} + +/** + * classify - categorize the relationship between two areas + * @a: Pointer to a &struct painting_desc for the first area + * @b: Pointer to a &struct painting_desc for the second area + */ +static inline int __pure classify(const struct painting_desc *a, + const struct painting_desc *b) +{ + int same_color, b_ends_before_a, result; + + same_color = (a->color == b->color); + b_ends_before_a = (b->q < a->q); + result = ((same_color << 1) | b_ends_before_a); + return result; +} + +/** + * painting_have_prev - see if the current area preceeds the new area + * @cur: Pointer to the &painting_area for the current area + * @new: Pointer to the &painting_desc for the new area + * + * Returns true if the current area exists before the new area, false otherwise + */ +static inline bool __pure painting_have_prev(const struct painting_area *cur, + const struct painting_desc *new) +{ + return cur != NULL && cur->desc.p < new->p; +} + +/** + * painting_prev_overlaps_or_abuts - does prev area overlaps or abuts new area + * @cur: Pointer to &struct painting_desc for the current area + * @new: Pointer to &struct painting_desc for the current area + * + * Returns true of the current area is before the new area and either overlaps + * or abuts the new area. + */ +static inline bool __pure + painting_prev_overlaps_or_abuts(const struct painting_desc *cur, + const struct painting_desc *new) +{ + return cur->p < new->p && cur->q >= new->p - 1; +} + +/** + * painting_must_make_hole - see if new area makes a hole in the current area + * @cur: Pointer to the &struct painting_desc for the current area + * @new: Pointer to the &struct painting_desc for the new area + * + * Returns true if the new area makes a hole in the current area, i.e. the + * current area ends up on both sides of the new area, false otherwise. + */ +static inline bool __pure + painting_must_make_hole(const struct painting_desc *cur, + const struct painting_desc *new) +{ + return classify(cur, new) == MISMATCH_CUR_ENDS_LAST; +} + +/** + * painting_add_area - see if previous area overlaps or abuts the new area + * @cur: Pointer to &struct painting_desc for the current area + * @new: Pointer to &struct painting_desc for the current area + * + * Returns true of the current area is before the new area and either overlaps + * or abuts the new area. + */ +static inline bool __pure +painting_add_area(const struct painting_desc *cur, + const struct painting_desc *new) +{ + return classify(cur, new) != MATCH_CUR_ENDS_LAST; +} +#endif diff --git a/arch/mips/include/asm/mach-powertv/powertv-prealloc.h b/arch/mips/include/asm/mach-powertv/powertv-prealloc.h new file mode 100644 index 0000000..5b4f938 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/powertv-prealloc.h @@ -0,0 +1,51 @@ +/* + * Description: Does platform-specific hardware initialization + * + * Copyright (C) 2005-2010 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _POWERTV_ASIC_PREALLOC_H_ +#define _POWERTV_ASIC_PREALLOC_H_ +#include +#include "prealloc.h" + +/* PLATFORM RESOURCE DEFINITIONS */ +extern const struct dma_resource dvr_cronus_resources[]; +extern const struct dma_resource dvr_gaia_resources[]; +extern const struct dma_resource dvr_zeus_resources[]; +extern const struct dma_resource non_dvr_calliope_resources[]; +extern const struct dma_resource non_dvr_cronus_resources[]; +extern const struct dma_resource non_dvr_cronuslite_resources[]; +extern const struct dma_resource non_dvr_gaia_resources[]; +extern const struct dma_resource non_dvr_vz_calliope_resources[]; +extern const struct dma_resource non_dvr_vze_calliope_resources[]; +extern const struct dma_resource non_dvr_vzf_calliope_resources[]; +extern const struct dma_resource non_dvr_zeus_resources[]; + +extern const struct dma_resource *gp_resources; + +/* Resource for ASIC */ +extern struct resource asic_resource; + +/* Point to resource-s of Low memory and High memory extents */ +extern struct resource *ptv_res_loext_root; +extern struct resource *ptv_res_hiext_root; + +extern void plat_resource_init(void); +extern void register_available_ram(void); +#endif diff --git a/arch/mips/include/asm/mach-powertv/prealloc.h b/arch/mips/include/asm/mach-powertv/prealloc.h new file mode 100644 index 0000000..066c11f --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/prealloc.h @@ -0,0 +1,121 @@ +/* + * Definitions for memory preallocations + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H +#define _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H +#include +#include +#include + +#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ +#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ + +#define IORESOURCE_PTV_RES_LOEXT 0x1 /* Resource must go in low mem */ + +/* "struct resource" array element definition */ +#define PREALLOC(NAME, START, END, FLAGS) { \ + .name = (NAME), \ + .start = (START), \ + .end = (END), \ + .flags = (FLAGS) \ + }, + +/* Individual resources in the preallocated resource arrays are defined using + * macros. These macros are conditionally defined based on their + * corresponding kernel configuration flag: + * - CONFIG_PREALLOC_NORMAL: preallocate resources for a normal settop box + * - CONFIG_PREALLOC_TFTP: preallocate the TFTP download resource + * - CONFIG_PREALLOC_DOCSIS: preallocate the DOCSIS resource + * - CONFIG_PREALLOC_PMEM: reserve space for persistent memory + */ +#ifdef CONFIG_PREALLOC_NORMAL +#define PREALLOC_NORMAL(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_NORMAL(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_TFTP +#define PREALLOC_TFTP(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_TFTP(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_DOCSIS +#define PREALLOC_DOCSIS(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_DOCSIS(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_PMEM +#define PREALLOC_PMEM(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_PMEM(name, start, end, flags) +#endif + +/* + * Drivers really just need to look up the physical addresss of a resource + * name. This is the data we pass back to them + */ +struct bus_resource { + phys_addr_t start; + phys_addr_t end; +}; + +/* + * For describing resources as DMA addresses + */ +struct dma_resource { + dma_addr_t start; + dma_addr_t end; + const char *name; + unsigned long flags; +}; + +/* Predefined physical memory types */ +extern const char physmem_bootloader[]; +extern const char physmem_buddy_high[]; +extern const char physmem_buddy_low[]; +extern const char physmem_mem_map[]; +extern const char physmem_ram[]; +extern const char physmem_reserved[]; +extern const char physmem_reset_vector[]; +extern const char physmem_rom_data[]; +extern const char physmem_unknown[]; +extern const char physmem_zero_page[]; + +/* allow drivers get info but use their data struct instead of passing */ +/* something allocated inside the kernel */ +extern int resource_add_ram(phys_addr_t start, size_t size); +extern void resource_reserve_static_prealloc(size_t size, + const struct dma_resource *dma_res); +extern void resource_add_memory_regions(void); +extern size_t __init resource_request_prealloc(size_t n, + const struct dma_resource *dma_resources); +extern bool platform_resource_override(struct resource *plat_res, + const struct dma_resource *dma_res); +extern int platform_lookup_resource(const char *name, + struct bus_resource *bres_p); +extern unsigned long platform_release_memory(unsigned long baddr, int size); +#endif diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig index ff0e7e3..e327762 100644 --- a/arch/mips/powertv/Kconfig +++ b/arch/mips/powertv/Kconfig @@ -19,3 +19,15 @@ config BOOTLOADER_FAMILY E1 - Class E F1 - Class F 44 - 45xx 46 - 46xx 85 - 85xx 86 - 86xx + +config PREALLOCATED_AREAS_ITEMS + int "Number items for handling driver pre-allocations" + default 100 + depends on POWERTV + help + Very early allocations of large chunks of memory is done before any + of the memory allocators are in use. This requires that any memory + required be statically allocated. It is difficult to calculate the + exact value, but it is roughly twice the number of preallocations + plus two for the kernel and an extra two for each contiguous chunk + of memory. diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig index 2016bfe..1a48e17 100644 --- a/arch/mips/powertv/asic/Kconfig +++ b/arch/mips/powertv/asic/Kconfig @@ -1,28 +1,34 @@ -config MIN_RUNTIME_RESOURCES - bool "Support for minimum runtime resources" - default n +menu "Preallocated resource options" + +config PREALLOC_NORMAL + bool "Preallocate normal resources" depends on POWERTV + default y help - Enables support for minimizing the number of (SA asic) runtime - resources that are preallocated by the kernel. + Enables support for the preallocated kernel resources used in normal + settop operation. This includes all preallocated resources that + aren't individually controlled via a separate CONFIG_PREALLOC_ + option. -config MIN_RUNTIME_DOCSIS - bool "Support for minimum DOCSIS resource" +config PREALLOC_DOCSIS + bool "Preallocate the DOCSIS resource" + depends on POWERTV default y - depends on MIN_RUNTIME_RESOURCES help Enables support for the preallocated DOCSIS resource. -config MIN_RUNTIME_PMEM - bool "Support for minimum PMEM resource" +config PREALLOC_PMEM + bool "Preallocate the PMEM resource" + depends on POWERTV default y - depends on MIN_RUNTIME_RESOURCES help - Enables support for the preallocated Memory resource. + Enables support for the preallocated persistent memory resource. -config MIN_RUNTIME_TFTP - bool "Support for minimum TFTP resource" - default y - depends on MIN_RUNTIME_RESOURCES +config PREALLOC_TFTP + bool "Preallocate the TFTP resource" + depends on POWERTV + default n help Enables support for the preallocated TFTP resource. + +endmenu diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile index f0e95dc..db0846b 100644 --- a/arch/mips/powertv/asic/Makefile +++ b/arch/mips/powertv/asic/Makefile @@ -1,5 +1,6 @@ # # Copyright (C) 2009 Scientific-Atlanta, Inc. +# Copyright (C) 2010 Cisco Systems, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,7 +18,8 @@ # obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \ - asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \ - prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o + asic_devices.o asic_int.o irq_asic.o painting.o \ + powertv-prealloc.o prealloc.o prealloc-calliope.o prealloc-cronus.o \ + prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o EXTRA_CFLAGS += -Wall -Werror diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c index e56fa61..a8c018b 100644 --- a/arch/mips/powertv/asic/asic_devices.c +++ b/arch/mips/powertv/asic/asic_devices.c @@ -1,8 +1,9 @@ /* * - * Description: Defines the platform resources for Gaia-based settops. + * Description: Does platform-specific hardware initialization * * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Systems, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,22 +22,16 @@ * NOTE: The bootloader allocates persistent memory at an address which is * 16 MiB below the end of the highest address in KSEG0. All fixed * address memory reservations must avoid this region. + * + * NOTE: This does not pre-allocate memory areas with dynamic address in + * memory outside of kseg0/kseg1. Dynamic allocation is restricted to + * kseg0/kseg1 memory. It wouldn't really be all that hard to support it; + * it just hasn't been needed. */ -#include #include #include -#include -#include -#include -#include -#include -#include #include -#include -#include -#include -#include #include #include @@ -46,15 +41,11 @@ #include #endif #include +#include #define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) /* - * Forward Prototypes - */ -static void pmem_setup_resource(void); - -/* * Global Variables */ enum asic_type asic; @@ -66,14 +57,6 @@ EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */ unsigned long asic_phy_base; unsigned long asic_base; EXPORT_SYMBOL(asic_base); /* Exported for testing */ -struct resource *gp_resources; - -/* - * Don't recommend to use it directly, it is usually used by kernel internally. - * Portable code should be using interfaces such as ioremp, dma_map_single, etc. - */ -unsigned long phys_to_dma_offset; -EXPORT_SYMBOL(phys_to_dma_offset); /* * @@ -89,6 +72,13 @@ struct resource asic_resource = { }; /* + * Don't recommend to use it directly, it is usually used by kernel internally. + * Portable code should be using interfaces such as ioremp, dma_map_single, etc. + */ +unsigned long phys_to_dma_offset; +EXPORT_SYMBOL(phys_to_dma_offset); + +/* * Allow override of bootloader-specified model * Returns zero on success, a negative errno value on failure. This parameter * allows overriding of the bootloader-specified model. @@ -236,9 +226,9 @@ static void __init set_register_map(unsigned long phys_base, } /** - * configure_platform - configuration based on platform type. + * powertv_platform_init - configuration based on platform type. */ -void __init configure_platform(void) +void __init powertv_platform_init(void) { platform_set_family(); @@ -374,176 +364,35 @@ void __init configure_platform(void) } } -/* - * RESOURCE ALLOCATION - * - */ -/* - * Allocates/reserves the Platform memory resources early in the boot process. - * This ignores any resources that are designated IORESOURCE_IO - */ -void __init platform_alloc_bootmem(void) -{ - int i; - int total = 0; - - /* Get persistent memory data from command line before allocating - * resources. This need to happen before normal command line parsing - * has been done */ - pmem_setup_resource(); - - /* Loop through looking for resources that want a particular address */ - for (i = 0; gp_resources[i].flags != 0; i++) { - int size = gp_resources[i].end - gp_resources[i].start + 1; - if ((gp_resources[i].start != 0) && - ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { - reserve_bootmem(dma_to_phys(gp_resources[i].start), - size, 0); - total += gp_resources[i].end - - gp_resources[i].start + 1; - pr_info("reserve resource %s at %08x (%u bytes)\n", - gp_resources[i].name, gp_resources[i].start, - gp_resources[i].end - - gp_resources[i].start + 1); - } - } - - /* Loop through assigning addresses for those that are left */ - for (i = 0; gp_resources[i].flags != 0; i++) { - int size = gp_resources[i].end - gp_resources[i].start + 1; - if ((gp_resources[i].start == 0) && - ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { - void *mem = alloc_bootmem_pages(size); - - if (mem == NULL) - pr_err("Unable to allocate bootmem pages " - "for %s\n", gp_resources[i].name); - - else { - gp_resources[i].start = - phys_to_dma(virt_to_phys(mem)); - gp_resources[i].end = - gp_resources[i].start + size - 1; - total += size; - pr_info("allocate resource %s at %08x " - "(%u bytes)\n", - gp_resources[i].name, - gp_resources[i].start, size); - } - } - } - - pr_info("Total Platform driver memory allocation: 0x%08x\n", total); - - /* indicate resources that are platform I/O related */ - for (i = 0; gp_resources[i].flags != 0; i++) { - if ((gp_resources[i].start != 0) && - ((gp_resources[i].flags & IORESOURCE_IO) != 0)) { - pr_info("reserved platform resource %s at %08x\n", - gp_resources[i].name, gp_resources[i].start); - } - } -} - -/* - * - * PERSISTENT MEMORY (PMEM) CONFIGURATION - * - */ -static unsigned long pmemaddr __initdata; - -static int __init early_param_pmemaddr(char *p) -{ - pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0); - return 0; -} -early_param("pmemaddr", early_param_pmemaddr); - -static long pmemlen __initdata; - -static int __init early_param_pmemlen(char *p) -{ -/* TODO: we can use this code when and if the bootloader ever changes this */ -#if 0 - pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); +#ifdef CONFIG_USB +#define NUM_USB_IFS 2 #else - pmemlen = 0x20000; +#define NUM_USB_IFS 0 #endif - return 0; -} -early_param("pmemlen", early_param_pmemlen); -/* - * Set up persistent memory. If we were given values, we patch the array of - * resources. Otherwise, persistent memory may be allocated anywhere at all. - */ -static void __init pmem_setup_resource(void) -{ - struct resource *resource; - resource = asic_resource_get("DiagPersistentMemory"); - - if (resource && pmemaddr && pmemlen) { - /* The address provided by bootloader is in kseg0. Convert to - * a bus address. */ - resource->start = phys_to_dma(pmemaddr - 0x80000000); - resource->end = resource->start + pmemlen - 1; - - pr_info("persistent memory: start=0x%x end=0x%x\n", - resource->start, resource->end); - } -} +static struct platform_device *platform_devices[NUM_USB_IFS]; /* - * - * RESOURCE ACCESS FUNCTIONS - * + * platform_devices_init - initialize platform resource usage */ - -/** - * asic_resource_get - retrieves parameters for a platform resource. - * @name: string to match resource - * - * Returns a pointer to a struct resource corresponding to the given name. - * - * CANNOT BE NAMED platform_resource_get, which would be the obvious choice, - * as this function name is already declared - */ -struct resource *asic_resource_get(const char *name) +int __init platform_devices_init(void) { - int i; + int ret; - for (i = 0; gp_resources[i].flags != 0; i++) { - if (strcmp(gp_resources[i].name, name) == 0) - return &gp_resources[i]; - } + asic_resource.start = asic_phy_base; + asic_resource.end += asic_resource.start; - return NULL; -} -EXPORT_SYMBOL(asic_resource_get); - -/** - * platform_release_memory - release pre-allocated memory - * @ptr: pointer to memory to release - * @size: size of resource - * - * This must only be called for memory allocated or reserved via the boot - * memory allocator. - */ -void platform_release_memory(void *ptr, int size) -{ - unsigned long addr; - unsigned long end; + ret = platform_usb_devices_init(&platform_devices[0], + &platform_devices[1]); + if (ret != 0) + return ret; - addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK; - end = ((unsigned long)ptr + size) & PAGE_MASK; + set_io_port_base(0); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - for (; addr < end; addr += PAGE_SIZE) { - ClearPageReserved(virt_to_page(__va(addr))); - init_page_count(virt_to_page(__va(addr))); - free_page((unsigned long)__va(addr)); - } + return 0; } -EXPORT_SYMBOL(platform_release_memory); +arch_initcall(platform_devices_init); /* * diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c index 7362f63..6866302 100644 --- a/arch/mips/powertv/asic/asic_int.c +++ b/arch/mips/powertv/asic/asic_int.c @@ -2,7 +2,7 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. * Copyright (C) 2001 Ralf Baechle - * Portions copyright (C) 2009 Cisco Systems, Inc. + * Portions copyright (C) 2009-2010 Cisco Systems, Inc. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -37,6 +37,7 @@ #include #include +#include static DEFINE_RAW_SPINLOCK(asic_irq_lock); @@ -98,6 +99,7 @@ void __init arch_init_irq(void) { int i; + plat_resource_init(); asic_irq_init(); /* diff --git a/arch/mips/powertv/asic/painting.c b/arch/mips/powertv/asic/painting.c new file mode 100644 index 0000000..306622e --- /dev/null +++ b/arch/mips/powertv/asic/painting.c @@ -0,0 +1,298 @@ +/* + * painting.c + * + * Functions that allow assigning "paints" (really, arbitrary tokens) to + * different areas of a "painting". This is useful for keeping track of + * the usage of given chunks of memory or I/O devices. Areas are + * described using phys_addr_t values to keep the representation as + * abstract as possible. Areas are not intended to wrap around the value + * space, e.g. if an area starts at zero, it won't be consolidated with an area + * of the same color ending at ~0. + * + * Copyright (C) 2008 Scientific-Atlanta, Inc. + * Copyright (C) 2010 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#include +#include +#include + +/** + * painting_link - link a &painting_area into a &painting + * @this: Pointer to &struct painting in which to add the + * &struct painting_area + * @new: Pointer to the &struct painting area to add + * + * Returns zero on success or a negative errno value on error + */ +static int painting_link(struct painting *this, struct painting_area *new) +{ + struct rb_node **n = &(this->root.rb_node), *parent = NULL; + + while (*n) { + struct painting_area *this; + phys_addr_t p; + + this = container_of(*n, struct painting_area, node); + parent = *n; + p = new->desc.p; + + if (p < this->desc.p) + n = &((*n)->rb_left); + else if (p > this->desc.p) + n = &((*n)->rb_right); + else + return false; + } + + rb_link_node(&new->node, parent, n); + rb_insert_color(&new->node, &this->root); + + return true; +} + +/** + * find_neighbor - find a neighbor close to the beginning of a &painting_area + * @this: Pointer to the &struct painting we are coloring + * @p: Location the area about which we are search starts + * + * Returns NULL if it didn't find anything at all. Otherwise it returns + * either a pointer to the last &struct painting_area before @p or, if + * there wasn't one, a pointer to the first &struct painting_area after p. + */ +struct painting_area *find_neighbor(const struct painting *this, + phys_addr_t p) +{ + struct rb_node *n = this->root.rb_node; + struct rb_node *parent; + struct painting_area *parent_area = NULL; + + while (n) { + parent = n; + parent_area = container_of(n, struct painting_area, node); + + if (p < parent_area->desc.p) + n = n->rb_left; + else if (p > parent_area->desc.p) + n = n->rb_right; + else + n = NULL; + } + + if (parent_area != NULL && parent_area->desc.p > p) { + struct painting_area *right; + right = painting_prev(parent_area); + if (right != NULL) + parent_area = right; + } + + return parent_area; +} + +/** + * painting_unlink - remove an area from the tree + * @this: Pointer to the &struct painting in which we are working + * @area: Start of the &struct painting_area + */ +static void painting_unlink(struct painting *this, + struct painting_area *cur) +{ + rb_erase(&cur->node, &this->root); +} + +/** + * make_a_hole - create a hole for new area in current area + * @this: Pointer &struct painting + * @cur: Pointer to current &pointer_area. This might be NULL if we're + * all done. + * @new: Starting location of new area. This has not yet been linked + * @tail: Newly allocated &struct painting_area to hold the end of the + * current area + * + * Returns zero on success, a negative errno value on failure. + */ +static int make_a_hole(struct painting *this, + struct painting_desc *cur, struct painting_desc *new, + struct painting_area *tail) +{ + int retval; + + if (tail == NULL) + retval = -ENOMEM; + else { + tail->desc.p = new->q + 1; + tail->desc.q = cur->q; + tail->desc.color = cur->color; + painting_link(this, tail); + + cur->q = new->p - 1; + retval = 0; + } + + return retval; +} + +/** + * extend_new - extend a new painting area, discarding an overlapping area + * @this: Pointer to a &struct painting in which we are working + * @cur: Pointer to the &struct painting_area for the overlapping + * area to be discarded + * @new: Pointer to the &struct painting_desc of an area to be extended + */ +static void extend_new(struct painting *this, struct painting_area *cur, + struct painting_desc *new) +{ + new->p = cur->desc.p; + painting_unlink(this, cur); +} + +/** + * chop_cur - truncate an area current in the list + * @cur: Pointer to a &struct painting_area for an area in the list + * @new: New area that overwrites the current area + */ +static void chop_cur(struct painting_area *cur, const struct painting_desc *new) +{ + cur->desc.q = new->p - 1; +} + +/** + * painting_do_prev_overlaps_and_abuts - handle previous that overlaps or abuts + * @this: Pointer to &struct painting on which we're working + * @cur: Pointer to &struct painting_area for the current area + * @new: Pointer to the &struct painting_desc for the current area + * @tail: Pointer to storage alloted for the left side of the hole made + * in the current area by the new area + * + * Returns an ERR_PTR if an error occurred, a non-NULL pointer of we have + * a &struct painting_area to free, and a NULL pointer otherwise. + * + * Here we handle a current area that is overlapping and before + * the new area. There are four cases: + * Cur RRRRRR RRRRRRRRRR RRRRRR RRRRRRRR + * New bbbbbb bbbbbb RRRRRR RRRR + * Res RRbbbbbb RRbbbbbbRR RRRRRRRR RRRRRRRR + * Rslt New+Cur Cur+New+Head Cur Cur + * Done No Yes No Yes + */ +struct painting_area * + painting_do_prev_overlaps_and_abuts(struct painting *this, + struct painting_area *cur, struct painting_desc *new, + struct painting_area *tail) +{ + struct painting_area *free_me = NULL; + int retval; + + switch (classify(&cur->desc, new)) { + case MISMATCH_CUR_ENDS_FIRST: + chop_cur(cur, new); + break; + + case MISMATCH_CUR_ENDS_LAST: + retval = make_a_hole(this, &cur->desc, new, tail); + if (retval != 0) + free_me = ERR_PTR(retval); + break; + + case MATCH_CUR_ENDS_FIRST: + extend_new(this, cur, new); + free_me = cur; + break; + + case MATCH_CUR_ENDS_LAST: + /* Nothing to do since all of the new area is already the same + * color as the current area. */ + break; + } + + return free_me; +} + +/** + * do_successor - do an area at or following the new area + * @this: Pointer to the &struct painting we're working on + * @cur: Current area in the area list + * @new: Pointer to the &struct painting_desc we're trying to add + * + * Returns a pointer to a &struct painting_area if it needs to be freed, + * otherwise it returns NULL. + */ +struct painting_area *do_successor(struct painting *this, + struct painting_area *cur, struct painting_desc *new) +{ + struct painting_area *retval = NULL; + + /* + * Every remaining area starts after the new area. Cases are therefore + * Cur RRRRRR RRRRRRRR RRRRRR RRRRRRRR + * New bbbbbbbb bbbbbb RRRRRRRR RRRRRR + * Res bbbbbbbb bbbbbbRR RRRRRRRR RRRRRRRR + * Name past end before end overpaint extend + * Rslt New+Cur New New New + */ + switch (classify(&cur->desc, new)) { + case MISMATCH_CUR_ENDS_FIRST: + painting_unlink(this, cur); + retval = cur; + break; + + case MISMATCH_CUR_ENDS_LAST: + painting_unlink(this, cur); + cur->desc.p = new->q + 1; + painting_link(this, cur); + break; + + case MATCH_CUR_ENDS_FIRST: + painting_unlink(this, cur); + retval = cur; + break; + + case MATCH_CUR_ENDS_LAST: + new->q = cur->desc.q; + painting_unlink(this, cur); + retval = cur; + break; + } + + return retval; +} + +/** + * finish_new_allocation - finish the work for add an area to the list + * @this: Pointer to the &struct painting on which we are working + * @newp: Pointer to the newly allocated &struct painting_area. + * @new: Pointer to the &struct painting_desc values to be stored + * in the new area + * + * Returns 0 in success, otherwise a negative errno value + */ +int finish_new_allocation(struct painting *this, + struct painting_area *newp, struct painting_desc *new) +{ + int retval = 0; + + if (newp == NULL) + retval = -ENOMEM; + else { + newp->desc = *new; + painting_link(this, newp); + } + + return retval; +} diff --git a/arch/mips/powertv/asic/powertv-prealloc.c b/arch/mips/powertv/asic/powertv-prealloc.c new file mode 100644 index 0000000..1047b5b --- /dev/null +++ b/arch/mips/powertv/asic/powertv-prealloc.c @@ -0,0 +1,136 @@ +/* + * Handle platform-specific resources + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +static struct dma_resource base_resources[] __initdata = { + {0x10000000, 0x10000000 + 0x40000 - 1, physmem_bootloader}, + {0x1fc00000, 0x1fc00000 + 0x400000 - 1, physmem_reset_vector}, +}; + +static unsigned long pmemaddr __initdata; + +static int __init early_param_pmemaddr(char *p) +{ + pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0); + return 0; +} +early_param("pmemaddr", early_param_pmemaddr); + +static long pmemlen __initdata; + +static int __init early_param_pmemlen(char *p) +{ +/* TODO: we can use this code when and if the bootloader ever changes this */ +#if 0 + pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); +#else + pmemlen = 0x20000; +#endif + return 0; +} +early_param("pmemlen", early_param_pmemlen); + +/* + * platform_resource_override - override information from platform resources + * @plat_res: Pointer to &struct resource to set if this resource is being + * overridden. + * @res: Pointer to &struct dma_resource to check whether it should be + * overridden. + * + * Returns true if the resource was overridden and should not be further + * processed, false if the resource wasn't overriden and should be processed + * as normal. + */ +bool __init platform_resource_override(struct resource *plat_res, + const struct dma_resource *res) +{ + if (strcmp(res->name, "DiagPersistentMemory") == 0) { + if (pmemaddr && pmemlen) { + /* The address provided by bootloader is in kseg0. + * Convert to a physical address. */ + plat_res->start = __pa(pmemaddr); + plat_res->end = plat_res->start + pmemlen - 1; + pr_info("persistent memory: start=0x%0*x end=0x%0*x\n", + 2 * sizeof(plat_res->start), plat_res->start, + 2 * sizeof(plat_res->end), plat_res->end); + } + return true; + } + + return false; +} + +/* + * dma_resource_count - tallies the number of DMA resources available + * @plat_res: Pointer to an array of &struct dma_resource objects + * + * Returns the number of non empty entries found + */ +static size_t __init dma_resource_count(const struct dma_resource *dma_res) +{ + int i; + /* Count number of resources */ + for (i = 0; dma_res[i].flags != 0; i++) + ; + return i; +} + +/** + * register_available_ram - give RAM minus preallocations to the sytem + */ +void __init register_available_ram() +{ + size_t num_plat_res; + + /* Subtract all of the preallocated RAM at a static address */ + resource_reserve_static_prealloc(ARRAY_SIZE(base_resources), + base_resources); + num_plat_res = dma_resource_count(gp_resources); + resource_reserve_static_prealloc(num_plat_res, gp_resources); + + /* Give all of the remaining RAM to the system */ + resource_add_memory_regions(); +} + +/** + * plat_resource_init - request resources for preallocated memory + */ +void __init plat_resource_init() +{ + size_t size; + size_t total = 0; + size_t num_plat_res; + + size = resource_request_prealloc(ARRAY_SIZE(base_resources), + base_resources); + if (size > 0) + total += size; + + num_plat_res = dma_resource_count(gp_resources); + size = resource_request_prealloc(num_plat_res, gp_resources); + if (size > 0) + total += size; + + pr_info("Total platform driver memory allocation: 0x%08x\n", total); +} diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c index 3fc5d46..d1ad146 100644 --- a/arch/mips/powertv/asic/prealloc-calliope.c +++ b/arch/mips/powertv/asic/prealloc-calliope.c @@ -2,6 +2,7 @@ * Memory pre-allocations for Calliope boxes. * * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Systems, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,12 +25,12 @@ #include #include #include -#include "prealloc.h" +#include /* * NON_DVR_CAPABLE CALLIOPE RESOURCES */ -struct resource non_dvr_calliope_resources[] __initdata = +const struct dma_resource non_dvr_calliope_resources[] __initdata = { /* * VIDEO / LX1 @@ -158,7 +159,7 @@ struct resource non_dvr_calliope_resources[] __initdata = }; -struct resource non_dvr_vze_calliope_resources[] __initdata = +const struct dma_resource non_dvr_vze_calliope_resources[] __initdata = { /* * VIDEO / LX1 @@ -264,7 +265,7 @@ struct resource non_dvr_vze_calliope_resources[] __initdata = }, }; -struct resource non_dvr_vzf_calliope_resources[] __initdata = +const struct dma_resource non_dvr_vzf_calliope_resources[] __initdata = { /* * VIDEO / LX1 diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c index c532b50..cd0d034 100644 --- a/arch/mips/powertv/asic/prealloc-cronus.c +++ b/arch/mips/powertv/asic/prealloc-cronus.c @@ -2,6 +2,7 @@ * Memory pre-allocations for Cronus boxes. * * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Systems, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,12 +25,12 @@ #include #include #include -#include "prealloc.h" +#include /* * DVR_CAPABLE CRONUS RESOURCES */ -struct resource dvr_cronus_resources[] __initdata = +const struct dma_resource dvr_cronus_resources[] __initdata = { /* * VIDEO1 / LX1 @@ -192,7 +193,7 @@ struct resource dvr_cronus_resources[] __initdata = /* * NON_DVR_CAPABLE CRONUS RESOURCES */ -struct resource non_dvr_cronus_resources[] __initdata = +const struct dma_resource non_dvr_cronus_resources[] __initdata = { /* * VIDEO1 / LX1 diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c index b5537e4..851a626 100644 --- a/arch/mips/powertv/asic/prealloc-cronuslite.c +++ b/arch/mips/powertv/asic/prealloc-cronuslite.c @@ -2,6 +2,7 @@ * Memory pre-allocations for Cronus Lite boxes. * * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Sysems, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,12 +25,12 @@ #include #include #include -#include "prealloc.h" +#include /* * NON_DVR_CAPABLE CRONUSLITE RESOURCES */ -struct resource non_dvr_cronuslite_resources[] __initdata = +const struct dma_resource non_dvr_cronuslite_resources[] __initdata = { /* * VIDEO2 / LX2 diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c index 8ac8c7a..d3f6694 100644 --- a/arch/mips/powertv/asic/prealloc-gaia.c +++ b/arch/mips/powertv/asic/prealloc-gaia.c @@ -2,6 +2,7 @@ * Memory pre-allocations for Gaia boxes. * * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Sysems, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,291 +23,154 @@ #include #include +#include /* * DVR_CAPABLE GAIA RESOURCES */ -struct resource dvr_gaia_resources[] __initdata = { +const struct dma_resource dvr_gaia_resources[] __initdata = { /* - * * VIDEO1 / LX1 - * */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x241FFFFF, /* 2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24201FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, + /* Delta-Mu 1 image and RAM (2 MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x241FFFFF, IORESOURCE_MEM) + /* 8KiB block ST231a monitor */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24201FFF, IORESOURCE_MEM) + /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x25FFFFFF, IORESOURCE_MEM) /* - * * VIDEO2 / LX2 - * */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, + /* Delta-Mu 2 image and RAM (2 MiB)*/ + PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x601FFFFF, IORESOURCE_IO) + /* 8KiB block ST231b monitor */ + PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60201FFF, IORESOURCE_IO) + /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x61FFFFFF, IORESOURCE_IO) /* - * * Sysaudio Driver - * * This driver requires: - * * Arbitrary Based Buffers: * DSP_Image_Buff - DSP code and data images (1MB) * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) * ADSC_AUX_Buff - ADSC AUX buffer (16KB) * ADSC_Main_Buff - ADSC Main buffer (16KB) - * */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x000FFFFF, + IORESOURCE_MEM) + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x00009FFF, + IORESOURCE_MEM) + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00003FFF, IORESOURCE_MEM) + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00003FFF, + IORESOURCE_MEM) /* - * * STAVEM driver/STAPI - * * This driver requires: - * * Arbitrary Based Buffers: * This memory area is used for allocating buffers for Video decoding * purposes. Allocation/De-allocation within this buffer is managed * by the STAVMEM driver of the STAPI. They could be Decimated * Picture Buffers, Intermediate Buffers, as deemed necessary for * video decoding purposes, for any video decoders on Zeus. - * */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x64180000 - 1, /* 12 MB total */ - .flags = IORESOURCE_IO, - }, + /* 12 MB total */ + PREALLOC_NORMAL("AVMEMPartition0", 0x63580000, 0x64180000 - 1, + IORESOURCE_IO) /* - * * DOCSIS Subsystem - * * This driver requires: - * * Arbitrary Based Buffers: * Docsis - - * */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, + /* 7 MB total */ + PREALLOC_DOCSIS("Docsis", 0x62000000, 0x62700000 - 1, IORESOURCE_IO) /* - * * GHW HAL Driver - * * This driver requires: - * * Arbitrary Based Buffers: * GraphicsHeap - PowerTV Graphics Heap - * */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, + /* 14 MB total */ + PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000 - 1, + IORESOURCE_IO) /* - * * multi com buffer area - * * This driver requires: - * * Arbitrary Based Buffers: * Docsis - - * */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, + PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000 - 1, + IORESOURCE_MEM) /* - * * DMA Ring buffer - * * This driver requires: - * * Arbitrary Based Buffers: * Docsis - - * */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x00280000 - 1, - .flags = IORESOURCE_MEM, - }, + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000 - 1, + IORESOURCE_MEM) /* - * * Display bins buffer for unit0 - * * This driver requires: - * * Arbitrary Based Buffers: * Display Bins for unit0 - * */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4 KB total */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00000FFF, IORESOURCE_MEM) /* - * * Display bins buffer - * * This driver requires: - * * Arbitrary Based Buffers: * Display Bins for unit1 - * */ - { - .name = "DisplayBins1", - .start = 0x64AD4000, - .end = 0x64AD5000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, + /* 4 KB total */ + PREALLOC_NORMAL("DisplayBins1", 0x64AD4000, 0x64AD5000 - 1, + IORESOURCE_IO) /* - * * ITFS - * * This driver requires: - * * Arbitrary Based Buffers: * Docsis - - * */ - { - .name = "ITFS", - .start = 0x64180000, - /* 815,104 bytes each for 2 ITFS partitions. */ - .end = 0x6430DFFF, - .flags = IORESOURCE_IO, - }, + /* 815, 104 bytes each for 2 ITFS partitions. */ + PREALLOC_NORMAL("ITFS", 0x64180000, 0x6430DFFF, IORESOURCE_IO) /* - * * AVFS - * * This driver requires: - * * Arbitrary Based Buffers: * Docsis - - * */ - { - .name = "AvfsDmaMem", - .start = 0x6430E000, - /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ - .end = 0x64AD0000 - 1, - .flags = IORESOURCE_IO, - }, - { - .name = "AvfsFileSys", - .start = 0x64AD0000, - .end = 0x64AD1000 - 1, /* 4K */ - .flags = IORESOURCE_IO, - }, + /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ + PREALLOC_NORMAL("AvfsDmaMem", 0x6430E000, 0x64AD0000 - 1, IORESOURCE_IO) + /* 4K */ + PREALLOC_NORMAL("AvfsFileSys", 0x64AD0000, 0x64AD1000 - 1, + IORESOURCE_IO) + /* + * PMEM + * This driver requires: + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000 - 1, + IORESOURCE_MEM) /* - * * Smartcard - * * This driver requires: - * * Arbitrary Based Buffers: * Read and write buffers for Internal/External cards - * */ - { - .name = "SmartCardInfo", - .start = 0x64AD1000, - .end = 0x64AD3800 - 1, - .flags = IORESOURCE_IO, - }, + PREALLOC_NORMAL("SmartCardInfo", 0x64AD1000, 0x64AD3800 - 1, + IORESOURCE_IO) /* - * * KAVNET * NP Reset Vector - must be of the form xxCxxxxx * NP Image - must be video bank 1 * NP IPC - must be video bank 2 */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, + PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000 - 1, + IORESOURCE_MEM) + PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27060000 - 1, IORESOURCE_MEM) + PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000 - 1, IORESOURCE_IO) /* * Add other resources here */ @@ -316,274 +180,134 @@ struct resource dvr_gaia_resources[] __initdata = { /* * NON_DVR_CAPABLE GAIA RESOURCES */ -struct resource non_dvr_gaia_resources[] __initdata = { +const struct dma_resource non_dvr_gaia_resources[] __initdata = { /* - * * VIDEO1 / LX1 - * */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x241FFFFF, /* 2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24201FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, + /* Delta-Mu 1 image and ram (2 MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x241FFFFF, IORESOURCE_MEM) + /* 8KiB block ST231a monitor */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24201FFF, IORESOURCE_MEM) + /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x25FFFFFF, IORESOURCE_MEM) /* - * * VIDEO2 / LX2 - * */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, + /* Delta-Mu 2 image and ram (2 MiB)*/ + PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x601FFFFF, IORESOURCE_IO) + /* 8KiB block ST231b monitor */ + PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60201FFF, IORESOURCE_IO) + /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x61FFFFFF, IORESOURCE_IO) /* - * * Sysaudio Driver - * * This driver requires: - * * Arbitrary Based Buffers: * DSP_Image_Buff - DSP code and data images (1MB) * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) * ADSC_AUX_Buff - ADSC AUX buffer (16KB) * ADSC_Main_Buff - ADSC Main buffer (16KB) - * */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x000FFFFF, + IORESOURCE_MEM) + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x00009FFF, + IORESOURCE_MEM) + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00003FFF, IORESOURCE_MEM) + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00003FFF, + IORESOURCE_MEM) /* - * * STAVEM driver/STAPI - * * This driver requires: - * * Arbitrary Based Buffers: * This memory area is used for allocating buffers for Video decoding * purposes. Allocation/De-allocation within this buffer is managed * by the STAVMEM driver of the STAPI. They could be Decimated * Picture Buffers, Intermediate Buffers, as deemed necessary for * video decoding purposes, for any video decoders on Zeus. - * */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x64180000 - 1, /* 12 MB total */ - .flags = IORESOURCE_IO, - }, + /* 12 MB total */ + PREALLOC_NORMAL("AVMEMPartition0", 0x63580000, 0x64180000 - 1, + IORESOURCE_IO) /* - * * DOCSIS Subsystem - * * This driver requires: - * * Arbitrary Based Buffers: * Docsis - - * */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, + /* 7 MB total */ + PREALLOC_DOCSIS("Docsis", 0x62000000, 0x62700000 - 1, IORESOURCE_IO) /* - * * GHW HAL Driver - * * This driver requires: - * * Arbitrary Based Buffers: * GraphicsHeap - PowerTV Graphics Heap - * */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, + /* 14 MB total */ + PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000 - 1, + IORESOURCE_IO) /* - * * multi com buffer area - * * This driver requires: - * * Arbitrary Based Buffers: * Docsis - - * */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, + PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000 - 1, + IORESOURCE_MEM) /* - * * DMA Ring buffer - * * This driver requires: - * * Arbitrary Based Buffers: * Docsis - - * */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000 - 1, + IORESOURCE_MEM) /* - * * Display bins buffer for unit0 - * * This driver requires: - * * Arbitrary Based Buffers: * Display Bins for unit0 - * */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4 KB total */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00000FFF, IORESOURCE_MEM) /* - * * Display bins buffer - * * This driver requires: - * * Arbitrary Based Buffers: * Display Bins for unit1 - * */ - { - .name = "DisplayBins1", - .start = 0x64AD4000, - .end = 0x64AD5000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, + /* 4 KB total */ + PREALLOC_NORMAL("DisplayBins1", 0x64AD4000, 0x64AD5000 - 1, + IORESOURCE_IO) /* - * * AVFS: player HAL memory - * - * */ - { - .name = "AvfsDmaMem", - .start = 0x6430E000, - .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_IO, - }, + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x6430E000, 0x645D2C00 - 1, IORESOURCE_IO) /* - * * PMEM - * * This driver requires: - * * Arbitrary Based Buffers: * Persistent memory for diagnostics. - * */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000 - 1, + IORESOURCE_MEM) /* - * * Smartcard - * * This driver requires: - * * Arbitrary Based Buffers: * Read and write buffers for Internal/External cards - * */ - { - .name = "SmartCardInfo", - .start = 0x64AD1000, - .end = 0x64AD3800 - 1, - .flags = IORESOURCE_IO, - }, + PREALLOC_NORMAL("SmartCardInfo", 0x64AD1000, 0x64AD3800 - 1, + IORESOURCE_IO) /* - * * KAVNET * NP Reset Vector - must be of the form xxCxxxxx * NP Image - must be video bank 1 * NP IPC - must be video bank 2 */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, + PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000 - 1, + IORESOURCE_MEM) + PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27060000 - 1, IORESOURCE_MEM) + PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000 - 1, IORESOURCE_IO) { }, }; diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c index 96480a2..0212f89 100644 --- a/arch/mips/powertv/asic/prealloc-zeus.c +++ b/arch/mips/powertv/asic/prealloc-zeus.c @@ -2,6 +2,7 @@ * Memory pre-allocations for Zeus boxes. * * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Sysems, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,12 +25,12 @@ #include #include #include -#include "prealloc.h" +#include /* * DVR_CAPABLE RESOURCES */ -struct resource dvr_zeus_resources[] __initdata = +const struct dma_resource dvr_zeus_resources[] __initdata = { /* * VIDEO1 / LX1 @@ -182,7 +183,7 @@ struct resource dvr_zeus_resources[] __initdata = /* * NON_DVR_CAPABLE ZEUS RESOURCES */ -struct resource non_dvr_zeus_resources[] __initdata = +const struct dma_resource non_dvr_zeus_resources[] __initdata = { /* * VIDEO1 / LX1 diff --git a/arch/mips/powertv/asic/prealloc.c b/arch/mips/powertv/asic/prealloc.c new file mode 100644 index 0000000..f2b63aa --- /dev/null +++ b/arch/mips/powertv/asic/prealloc.c @@ -0,0 +1,566 @@ +/* + * + * Description: Preallocate large chunks of memory for drivers + * + * Copyright (C) 2005-2010 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Sysems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Type Definitions + */ + +const struct dma_resource *gp_resources __initdata; + +/* Definitions for physical memory area information. We don't have + * kmalloc working at this point. In fact, we don't even have the boot + * memory allocator, so we have no choice but to use a static allocation. + * In the best of all possible worlds, we might have a way to switch to + * the boot memory allocator, and then the slab/slob/slub allocator when + * they become available, but this probably isn't really worth the effort. */ +struct alloc_item { + struct list_head free_areas; + struct painting_area area; +}; + +static struct alloc_item areas[CONFIG_PREALLOCATED_AREAS_ITEMS] __initdata; + +static LIST_HEAD(free_areas); /* List of avail. area allocations */ +static int areas_unallocated = ARRAY_SIZE(areas); /* # never-allocated areas */ +static loff_t num_areas; /* Current count of areas */ +static bool alloc_errors; /* Flag to indicate faulty data */ +static PAINTING(ram_painting); + +/* + * Allocate a painting_area. We do the allocation so early that we can't + * count on running any code to initialize the list of free areas, so we + * also have a counter of the number of items unused in the array of areas. + * + * Returns: Pointer to a struct painting_area, or NULL if none is + * available. + */ +static __init struct painting_area *physmem_alloc(void) +{ + struct alloc_item *item; + struct painting_area *result; + + /* First use anything in the areas array that hasn't been used. If + * that fails, then go to our list of free areas. */ + if (areas_unallocated != 0) { + areas_unallocated--; + item = &areas[areas_unallocated]; + } else if (!list_empty(&free_areas)) { + item = list_first_entry(&free_areas, struct alloc_item, + free_areas); + list_del(&item->free_areas); + } + + else + item = NULL; + + /* If we failed to allocate something, then log it and return NULL. + * Otherwise, return a pointer to the painting_area portion */ + if (!item) { + alloc_errors = true; + result = NULL; + } else { + result = &item->area; + num_areas++; + } + + return result; +} + +/* + * Free a painting area + * @p: Pointer to struct painting_area to free + */ +static __init void physmem_free(const struct painting_area *p) +{ + struct alloc_item *item; + + item = container_of(p, struct alloc_item, area); + list_add(&item->free_areas, &free_areas); + num_areas--; +} + +/* + * mem_painting_add - add a painting area to a painting + * @this: Pointer to the &struct painting on which we are working + * @desc: Pointer to a &struct painting_desc to add. + * + * Returns zere on success, otherwise a negative errno value + * + * The approach is to start with the area preceeding the new area, then any + * areas that start at the same place as the new area, then all of rest of + * areas that start before, at, or right after the end of the new area. + */ +int __init mem_painting_add(struct painting *this, + const struct painting_desc *new_desc) +{ + struct painting_area *newp; /* Area we are adding */ + struct painting_area *cur; /* Current area we are working on */ + struct painting_area *next; + struct painting_desc new; + int retval = 0; + bool add_new = true; + + new = *new_desc; /* Make a copy so we can modify these */ + cur = find_neighbor(this, new.p); + + if (painting_have_prev(cur, &new)) { + next = painting_next(cur); + + if (painting_prev_overlaps_or_abuts(&cur->desc, &new)) { + struct painting_area *tail; + struct painting_area *free_me; + + tail = painting_must_make_hole(&cur->desc, &new) ? + physmem_alloc() : NULL; + free_me = painting_do_prev_overlaps_and_abuts(this, + cur, &new, tail); + if (IS_ERR(free_me)) + retval = PTR_ERR(free_me); + else if (free_me != NULL) + physmem_free(free_me); + add_new = painting_add_area(&cur->desc, &new); + } + + cur = next; + } + + /* TODO: Ensure proper handling of wrap-around of value space here */ + while (retval == 0 && cur != NULL && cur->desc.p <= new.q + 1) { + struct painting_area *ret; + + ret = do_successor(this, cur, &new); + if (ret != NULL) + physmem_free(ret); + + cur = painting_next(cur); + } + + /* + * If the new area wasn't subsumed by another area, we need to allocate + * storage for it and line it in. + */ + if (retval == 0 && add_new) { + newp = physmem_alloc(); + retval = finish_new_allocation(this, newp, &new); + } + + return retval; +} + +/** + * resource_add_ram - add actual RAM + * @start: Physical address of the start of RAM + * @end: Physical address of the last byte of RAM + * + * Returns zero on success, a negative errno value on failure + */ +int __init resource_add_ram(phys_addr_t start, phys_addr_t end) +{ + struct painting_desc desc; + int res; + + desc.p = start; + desc.q = end; + desc.color = physmem_ram; + res = mem_painting_add(&ram_painting, &desc); + return res; +} + +/* + * + * RESOURCE ACCESS FUNCTIONS + * + */ + +/* + * lookup_root_resource - finds the right root resource for a range + * @start: the physical address of start of resource. + * @size: the size of resource in byte + * + * Returns a pointer to the resource or NULL upon failure. It finds the most + * deeply nested resource that can hold the resource we were passed. + */ +static __init struct resource *__init lookup_root_resource(unsigned long start, + unsigned long size) +{ + struct resource *result; + struct resource *res_p; + + result = NULL; + res_p = iomem_resource.child; + + while (res_p) { + /* + * If we have a resource that can hold the resource we + * were passed, remember it and then switch to scanning + * its children. + */ + if ((res_p->start <= start) && + (res_p->end >= (start + size - 1))) { + result = res_p; + res_p = result->child; + } else { + res_p = res_p->sibling; + } + } + + if (result == NULL) + pr_err("Can't find root resource for resource at " + "0x%lx-0x%lx\n", start, start + size - 1); + + return result; +} + +/** + * platform_lookup_resource_entry - finds resource entry by name + * @name: pointer to string containing name of resource + * + * Returns a pointer to the corresponding &struct resource or NULL if it + * couldn't find one. + */ +static struct resource *platform_lookup_resource_entry(const char *name) +{ + struct resource *p; + struct resource *next; + + for (p = iomem_resource.child; p != NULL; p = next) { + if (strcmp(p->name, name) == 0) + return p; + + next = p->child; /* Go deeper, if possible */ + + if (next == NULL) { + next = p->sibling; /* Go sideways, if possible */ + + if (next == NULL) { + /* Go up and, possibly, over */ + for (next = p->parent; next != NULL; + next = p->parent) { + p = next; + next = p->sibling; + if (next != NULL) + break; + } + } + } + } + + return NULL; +} + +/* + * set_resource_addresses - set platform resource address information + * @plat_res: Pointer to &struct resource whose addresses to are + * be set + * @res: Pointer to &struct dma_resource from which to get addresses. + * + * Returns true on success, false on failure. + */ +static __init bool set_resource_addresses(struct resource *plat_res, + const struct dma_resource *dma_res) +{ + if (platform_resource_override(plat_res, dma_res)) + return true; + + if (dma_res->start != 0) { + /* Have a statically defined address */ + plat_res->start = dma_to_phys(dma_res->start); + plat_res->end = dma_to_phys(dma_res->end); + + /* We've already warned about these */ + if (plat_res->start >= HIGHMEM_START) + return false; + } else { + void *virt_start; + size_t size; + + /* Need to allocation an address dynamically */ + + size = dma_res->end; + virt_start = kmalloc(size, GFP_KERNEL); + if (virt_start == NULL) { + pr_err("Unable to allocate memory for %s\n", + dma_res->name); + return false; + } + plat_res->start = virt_to_phys(virt_start); + plat_res->end = plat_res->start + size; + } + + return true; +} + +/** + * plat_reserve_resource_list - reserve a list of dma_resources + * @n: Number of &dma_resources to reserve + * @dma_resources: Pointer to the list of &struct dma_resource items + * + * Adds the list of &dma_resources to the ram_painting. This changes + * color from physmem_ram so that the memory areas won't be given to + * the boot memory allocator. Since this is called before any memory + * allocator is initialized, it can't allocate memory. + */ +void __init resource_reserve_static_prealloc(size_t n, + const struct dma_resource *dma_resources) +{ + int i; + + for (i = 0; i < n; i++) { + const struct dma_resource *dma_res; + struct painting_desc desc; + + dma_res = &dma_resources[i]; + + /* Skip anything with a dynamically-assigned address */ + if (dma_res->start == 0) + continue; + + desc.p = dma_to_phys(dma_res->start); + desc.q = dma_to_phys(dma_res->end); + +#ifndef CONFIG_HIGHMEM + if (desc.p >= HIGHMEM_START) { + pr_warn("No highmem--skipping reservation at %0*x " + "for %s\n", + 2 * sizeof(dma_res->start), dma_res->start, + dma_res->name); + continue; + } +#endif + desc.color = dma_res->name; + mem_painting_add(&ram_painting, &desc); + } +} + +/** + * resource_add_memory_region - add non-preallocated ram + */ +void __init resource_add_memory_regions() +{ + struct painting_area *area; + + painting_for_each_area(area, &ram_painting) { + struct painting_desc *desc; + + desc = &area->desc; + add_memory_region(desc->p, desc->q - desc->p + 1, + (desc->color == physmem_ram) ? BOOT_MEM_RAM : + BOOT_MEM_RESERVED); + } +} + +/* + * init_one_resource - set up resources for one preallocation + * @plat_res: Pointer to &struct resource that we be set up + * @dma_res: Pointer to &struct dma_resource holding the data + * + * On success, returns the number of bytes in the resources. Otherwise, + * returns zero. + */ +int __init init_one_resource(struct resource *plat_res, + const struct dma_resource *dma_res) +{ + struct resource *root_res; + size_t size; + int conflict; + + if (platform_lookup_resource_entry(dma_res->name) != NULL) { + pr_err("resource %s has already been allocated\n", + dma_res->name); + return 0; + } + + if (!set_resource_addresses(plat_res, dma_res)) + return 0; + + plat_res->name = kstrdup(dma_res->name, GFP_KERNEL); + plat_res->flags = dma_res->flags; + size = (plat_res->end - plat_res->start + 1); + + root_res = lookup_root_resource(plat_res->start, size); + + /* If there is no highmem extent root_res_p might be NULL */ + if (root_res) + conflict = request_resource(root_res, plat_res); + else + conflict = -1; + + if (conflict) { + if (request_resource(&iomem_resource, plat_res) != 0) { + pr_err("PTV resource request conflict " + "%s: 0x%x-0x%x\n", + plat_res->name, + plat_res->start, + plat_res->end); + plat_res->start = 0; + plat_res->end = 0; + } + return 0; + } + + plat_res->flags |= IORESOURCE_BUSY; + pr_info("Reserved resource at 0x%0*x for %s (%u bytes)\n", + 2 * sizeof(plat_res->start), plat_res->start, + plat_res->name, size); + return size; +} + +/** + * resource_request_prealloc - reserve resources for a list of preallocs + * @n: Number of resources to request + * @dma_resources: Pointer of DMA resources which are to be requested + * + * Called when we can allocate memory. Requests resources corresponding + * to both statically and dynamically assigned addreses. + * + * Recall that memory for resources at constant addresses was not passed + * to the boot memory allocator, so it is already reserved. Such memory still + * has still has no resource associated with it. We don't have addresses + * for memory whose address can be dynamically defined and will have to + * get them. + * + * Returns the number of bytes of resources successfully requested. + */ +size_t __init resource_request_prealloc(size_t n, + const struct dma_resource *dma_resources) +{ + struct resource *plat_resources; + size_t alloc_size; + size_t total; + int i; + + if (n == 0) + return 0; + + /* Allocate an array for the result */ + alloc_size = sizeof(*plat_resources) * n; + plat_resources = kmalloc(alloc_size, GFP_KERNEL | __GFP_ZERO); + + if (plat_resources == NULL) { + pr_err("could not allocate %d bytes for platform resource " + "structs\n", alloc_size); + return 0; + } + + total = 0; + + /* Populate the array */ + for (i = 0; i < n; i++) { + const struct dma_resource *dma_res; + struct resource *plat_res; + size_t size; + + dma_res = &dma_resources[i]; + plat_res = &plat_resources[i]; + + size = init_one_resource(plat_res, dma_res); + if (size > 0) + total += size; + } + + return total; +} + +/** + * platform_lookup_resource - provides start and end physical addresses + * for preallocated and reserved resources for drivers. + * + * @name: pointer to string containing name of resource + * @bres_p: pointer to callers struct that addrs are copied to + * Returns 0 on success, a negative errno value on failure + * + */ +int platform_lookup_resource(const char *name, struct bus_resource *bres_p) +{ + struct resource *p; + + p = platform_lookup_resource_entry(name); + + if (p == NULL) + return -ENODEV; + + bres_p->start = p->start; + bres_p->end = p->end; + return 0; +} +EXPORT_SYMBOL(platform_lookup_resource); + +/** + * platform_release_memory - release pre-allocated memory + * @ptr: pointer to memory to release + * @size: size of resource + * @baddr: Bus address of memory to release + * @size: size of resource, in bytes + * + * This must only be called for memory allocated or reserved via the boot + * or buddy memory allocators. + * Returns the number of bytes actually released. This must only be called + * for memory allocated or reserved via the boot memory allocator. + */ +unsigned long platform_release_memory(unsigned long baddr, int size) +{ + unsigned long paddr = dma_to_phys(baddr); + unsigned long pfn; + unsigned long end_pfn; + unsigned long pgs = 0; + + pr_info("Platform_release_memory:\n"); + pfn = PFN_UP(paddr); + end_pfn = PFN_DOWN(paddr + size); + + for (; pfn < end_pfn; pfn++) { + struct page *page = pfn_to_page(pfn); + + if (!pfn_valid(pfn)) { + pr_err("Trying to release invalid pfn:0x%lx\n", pfn); + BUG(); + break; + } + + if (!PageReserved(page)) { + pr_err("Trying to release page that is not" + " currently \"reserved\":0x%lx\n", pfn); + BUG(); + break; + } + + ClearPageReserved(page); + init_page_count(page); + __free_page(page); + + totalram_pages++; + num_physpages++; + pgs++; + } + + return pgs << PAGE_SHIFT; +} +EXPORT_SYMBOL(platform_release_memory); diff --git a/arch/mips/powertv/asic/prealloc.h b/arch/mips/powertv/asic/prealloc.h deleted file mode 100644 index 8e682df..0000000 --- a/arch/mips/powertv/asic/prealloc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Definitions for memory preallocations - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H -#define _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H - -#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ -#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ - -/* "struct resource" array element definition */ -#define PREALLOC(NAME, START, END, FLAGS) { \ - .name = (NAME), \ - .start = (START), \ - .end = (END), \ - .flags = (FLAGS) \ - }, - -/* Individual resources in the preallocated resource arrays are defined using - * macros. These macros are conditionally defined based on their - * corresponding kernel configuration flag: - * - CONFIG_PREALLOC_NORMAL: preallocate resources for a normal settop box - * - CONFIG_PREALLOC_TFTP: preallocate the TFTP download resource - * - CONFIG_PREALLOC_DOCSIS: preallocate the DOCSIS resource - * - CONFIG_PREALLOC_PMEM: reserve space for persistent memory - */ -#ifdef CONFIG_PREALLOC_NORMAL -#define PREALLOC_NORMAL(name, start, end, flags) \ - PREALLOC(name, start, end, flags) -#else -#define PREALLOC_NORMAL(name, start, end, flags) -#endif - -#ifdef CONFIG_PREALLOC_TFTP -#define PREALLOC_TFTP(name, start, end, flags) \ - PREALLOC(name, start, end, flags) -#else -#define PREALLOC_TFTP(name, start, end, flags) -#endif - -#ifdef CONFIG_PREALLOC_DOCSIS -#define PREALLOC_DOCSIS(name, start, end, flags) \ - PREALLOC(name, start, end, flags) -#else -#define PREALLOC_DOCSIS(name, start, end, flags) -#endif - -#ifdef CONFIG_PREALLOC_PMEM -#define PREALLOC_PMEM(name, start, end, flags) \ - PREALLOC(name, start, end, flags) -#else -#define PREALLOC_PMEM(name, start, end, flags) -#endif -#endif diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c index 0aac039..6ee3145 100644 --- a/arch/mips/powertv/init.c +++ b/arch/mips/powertv/init.c @@ -3,7 +3,7 @@ * All rights reserved. * Authors: Carsten Langgaard * Maciej W. Rozycki - * Portions copyright (C) 2009 Cisco Systems, Inc. + * Portions copyright (C) 2009-2010 Cisco Systems, Inc. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -122,7 +122,7 @@ void __init prom_init(void) strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE); } - configure_platform(); + powertv_platform_init(); prom_meminit(); #ifndef CONFIG_BOOTLOADER_DRIVER diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c index a77c6f6..22a5c29 100644 --- a/arch/mips/powertv/ioremap.c +++ b/arch/mips/powertv/ioremap.c @@ -4,6 +4,7 @@ * Support for mapping between dma_addr_t values a phys_addr_t values. * * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009-2010 Cisco Sysems, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -80,8 +81,17 @@ static void setup_dma_to_phys(dma_addr_t dma, phys_addr_t delta, dma_addr_t s) first_idx = first >> IOR_LSBITS; /* Convert to indices */ last_idx = last >> IOR_LSBITS; - for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++) - _ior_dma_to_phys[dma_idx].offset = delta >> IOR_DMA_SHIFT; + for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++) { + dma_addr_t offset; + offset = delta >> IOR_DMA_SHIFT; + + if (_ior_dma_to_phys[dma_idx].offset != 0 && + _ior_dma_to_phys[dma_idx].offset != offset) + panic("Memory remapped: DMA %x physical %x size %d\n", + dma, dma + delta, s); + + _ior_dma_to_phys[dma_idx].offset = offset; + } } /** @@ -104,11 +114,21 @@ static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s) */ first = phys & ~IOR_PHYS_GRAIN_MASK; last = (phys + s - 1) & ~IOR_PHYS_GRAIN_MASK; - first_idx = first >> IOR_LSBITS; /* Convert to indices */ + first_idx = first >> IOR_LSBITS; /* Convert to indices */ last_idx = last >> IOR_LSBITS; - for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++) - _ior_phys_to_dma[phys_idx].offset = delta >> IOR_PHYS_SHIFT; + for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++) { + dma_addr_t offset; + + offset = delta >> IOR_PHYS_SHIFT; + + if (_ior_phys_to_dma[phys_idx].offset != 0 && + _ior_phys_to_dma[phys_idx].offset != offset) + panic("Memory remapped: physical %x DMA %x size %d\n", + phys, phys + delta, s); + + _ior_phys_to_dma[phys_idx].offset = offset; + } } /** @@ -120,17 +140,11 @@ static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s) * NOTE: It might be obvious, but the assumption is that all @size bytes have * the same offset between the physical address and the DMA address. */ -void ioremap_add_map(phys_addr_t phys, phys_addr_t dma, phys_addr_t size) +void ioremap_add_map(phys_addr_t phys, dma_addr_t dma, size_t size) { if (size == 0) return; - if ((dma & IOR_DMA_GRAIN_MASK) != 0 || - (phys & IOR_PHYS_GRAIN_MASK) != 0 || - (size & IOR_PHYS_GRAIN_MASK) != 0) - pr_crit("Memory allocation must be in chunks of 0x%x bytes\n", - IOR_PHYS_GRAIN); - setup_dma_to_phys(dma, phys - dma, size); setup_phys_to_dma(phys, dma - phys, size); } diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c index c463cd3..6b0c10e 100644 --- a/arch/mips/powertv/memory.c +++ b/arch/mips/powertv/memory.c @@ -1,7 +1,7 @@ /* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. + * Portions copyright (C) 2009-2010 Cisco Systems, Inc. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -25,28 +25,38 @@ #include #include -#include #include #include +#include +#include #include #include #include +#include #include "init.h" /* Memory constants */ #define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ #define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ +#define GIBIBYTE(n) ((n) * MEBIBYTE(1024)) /* Number of mebibytes */ #define DEFAULT_MEMSIZE MEBIBYTE(128) /* If no memsize provided */ #define BLDR_SIZE KIBIBYTE(256) /* Memory reserved for bldr */ #define RV_SIZE MEBIBYTE(4) /* Size of reset vector */ -#define LOW_MEM_END 0x20000000 /* Highest low memory address */ -#define BLDR_ALIAS 0x10000000 /* Bootloader address */ -#define RV_PHYS 0x1fc00000 /* Reset vector address */ -#define LOW_RAM_END RV_PHYS /* End of real RAM in low mem */ +/* Predefined physical memory types */ +const char physmem_bootloader[] = "bootloader"; +const char physmem_buddy_high[] = "buddy allocator (high)"; +const char physmem_buddy_low[] = "buddy allocator (low)"; +const char physmem_mem_map[] = "page descriptors"; +const char physmem_ram[] = "RAM"; +const char physmem_reserved[] = "reserved"; +const char physmem_reset_vector[] = "reset vector"; +const char physmem_rom_data[] = "ROM data"; +const char physmem_unknown[] = "unknown type"; +const char physmem_zero_page[] = "zero page"; /* * Very low-level conversion from processor physical address to device @@ -57,30 +67,8 @@ unsigned long ptv_memsize; /* - * struct low_mem_reserved - Items in low memmory that are reserved - * @start: Physical address of item - * @size: Size, in bytes, of this item - * @is_aliased: True if this is RAM aliased from another location. If false, - * it is something other than aliased RAM and the RAM in the - * unaliased address is still visible outside of low memory. - */ -struct low_mem_reserved { - phys_addr_t start; - phys_addr_t size; - bool is_aliased; -}; - -/* - * Must be in ascending address order - */ -struct low_mem_reserved low_mem_reserved[] = { - {BLDR_ALIAS, BLDR_SIZE, true}, /* Bootloader RAM */ - {RV_PHYS, RV_SIZE, false}, /* Reset vector */ -}; - -/* * struct mem_layout - layout of a piece of the system RAM - * @phys: Physical address of the start of this piece of RAM. This is the + * @dma: Physical address of the start of this piece of RAM. This is the * address at which both the processor and I/O devices see the * RAM. * @alias: Alias of this piece of memory in order to make it appear in @@ -89,9 +77,9 @@ struct low_mem_reserved low_mem_reserved[] = { * @size: Size, in bytes, of this piece of RAM */ struct mem_layout { - phys_addr_t phys; + dma_addr_t dma; phys_addr_t alias; - phys_addr_t size; + size_t size; }; /* @@ -106,27 +94,32 @@ struct mem_layout_list { struct mem_layout *layout; }; -static struct mem_layout f1500_layout[] = { +static struct mem_layout f1500_layout[] __initdata = { {0x20000000, 0x10000000, MEBIBYTE(256)}, }; -static struct mem_layout f4500_layout[] = { +static struct mem_layout f4500_layout[] __initdata = { {0x40000000, 0x10000000, MEBIBYTE(256)}, {0x20000000, 0x20000000, MEBIBYTE(32)}, }; -static struct mem_layout f8500_layout[] = { +static struct mem_layout f8500_layout[] __initdata = { {0x40000000, 0x10000000, MEBIBYTE(256)}, {0x20000000, 0x20000000, MEBIBYTE(32)}, {0x30000000, 0x30000000, MEBIBYTE(32)}, }; -static struct mem_layout fx600_layout[] = { +static struct mem_layout fx600_layout[] __initdata = { {0x20000000, 0x10000000, MEBIBYTE(256)}, {0x60000000, 0x60000000, MEBIBYTE(128)}, }; -static struct mem_layout_list layout_list[] = { +static struct mem_layout fx700_layout[] __initdata = { + {0x20000000, 0x10000000, GIBIBYTE(1)}, + {0x60000000, 0x60000000, GIBIBYTE(1)}, +}; + +static struct mem_layout_list layout_list[] __initdata = { {FAMILY_1500, ARRAY_SIZE(f1500_layout), f1500_layout}, {FAMILY_1500VZE, ARRAY_SIZE(f1500_layout), f1500_layout}, {FAMILY_1500VZF, ARRAY_SIZE(f1500_layout), f1500_layout}, @@ -137,26 +130,15 @@ static struct mem_layout_list layout_list[] = { {FAMILY_4600VZA, ARRAY_SIZE(fx600_layout), fx600_layout}, {FAMILY_8600, ARRAY_SIZE(fx600_layout), fx600_layout}, {FAMILY_8600VZB, ARRAY_SIZE(fx600_layout), fx600_layout}, + {FAMILY_8700, ARRAY_SIZE(fx600_layout), fx700_layout}, }; /* If we can't determine the layout, use this */ -static struct mem_layout default_layout[] = { +static struct mem_layout default_layout[] __initdata = { {0x20000000, 0x10000000, MEBIBYTE(128)}, }; /** - * register_non_ram - register low memory not available for RAM usage - */ -static __init void register_non_ram(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(low_mem_reserved); i++) - add_memory_region(low_mem_reserved[i].start, - low_mem_reserved[i].size, BOOT_MEM_RESERVED); -} - -/** * get_memsize - get the size of memory as a single bank */ static phys_addr_t get_memsize(void) @@ -201,91 +183,7 @@ static phys_addr_t get_memsize(void) } /** - * register_low_ram - register an aliased section of RAM - * @p: Alias address of memory - * @n: Number of bytes in this section of memory - * - * Returns the number of bytes registered - * - */ -static __init phys_addr_t register_low_ram(phys_addr_t p, phys_addr_t n) -{ - phys_addr_t s; - int i; - phys_addr_t orig_n; - - orig_n = n; - - BUG_ON(p + n > RV_PHYS); - - for (i = 0; n != 0 && i < ARRAY_SIZE(low_mem_reserved); i++) { - phys_addr_t start; - phys_addr_t size; - - start = low_mem_reserved[i].start; - size = low_mem_reserved[i].size; - - /* Handle memory before this low memory section */ - if (p < start) { - phys_addr_t s; - s = min(n, start - p); - add_memory_region(p, s, BOOT_MEM_RAM); - p += s; - n -= s; - } - - /* Handle the low memory section itself. If it's aliased, - * we reduce the number of byes left, but if not, the RAM - * is available elsewhere and we don't reduce the number of - * bytes remaining. */ - if (p == start) { - if (low_mem_reserved[i].is_aliased) { - s = min(n, size); - n -= s; - p += s; - } else - p += n; - } - } - - return orig_n - n; -} - -/* - * register_ram - register real RAM - * @p: Address of memory as seen by devices - * @alias: If the memory is seen at an additional address by the processor, - * this will be the address, otherwise it is the same as @p. - * @n: Number of bytes in this section of memory - */ -static __init void register_ram(phys_addr_t p, phys_addr_t alias, - phys_addr_t n) -{ - /* - * If some or all of this memory has an alias, break it into the - * aliased and non-aliased portion. - */ - if (p != alias) { - phys_addr_t alias_size; - phys_addr_t registered; - - alias_size = min(n, LOW_RAM_END - alias); - registered = register_low_ram(alias, alias_size); - ioremap_add_map(alias, p, n); - n -= registered; - p += registered; - } - -#ifdef CONFIG_HIGHMEM - if (n != 0) { - add_memory_region(p, n, BOOT_MEM_RAM); - ioremap_add_map(p, p, n); - } -#endif -} - -/** - * register_address_space - register things in the address space + * register_raw_ram - register things in the address space * @memsize: Number of bytes of RAM installed * * Takes the given number of bytes of RAM and registers as many of the regions, @@ -294,19 +192,13 @@ static __init void register_ram(phys_addr_t p, phys_addr_t alias, * is 384 MiB, it will register the first region with 256 MiB and the second * with 128 MiB. */ -static __init void register_address_space(phys_addr_t memsize) +static void __init register_raw_ram(phys_addr_t memsize) { - int i; - phys_addr_t size; - size_t n; struct mem_layout *layout; + int num_layouts; enum family_type family; - - /* - * Register all of the things that aren't available to the kernel as - * memory. - */ - register_non_ram(); + int res; + int i; /* Find the appropriate memory description */ family = platform_get_family(); @@ -317,16 +209,27 @@ static __init void register_address_space(phys_addr_t memsize) } if (i == ARRAY_SIZE(layout_list)) { - n = ARRAY_SIZE(default_layout); + num_layouts = ARRAY_SIZE(default_layout); layout = default_layout; } else { - n = layout_list[i].n; + num_layouts = layout_list[i].n; layout = layout_list[i].layout; } - for (i = 0; memsize != 0 && i < n; i++) { + /* Add all possible RAM */ + for (i = 0; memsize != 0 && i < num_layouts; i++) { + dma_addr_t dma; + phys_addr_t alias; + size_t size; + + dma = layout[i].dma; + alias = layout[i].alias; size = min(memsize, layout[i].size); - register_ram(layout[i].phys, layout[i].alias, size); + + ioremap_add_map(alias, dma, size); + res = resource_add_ram(alias, alias + size - 1); + if (res != 0) + break; memsize -= size; } } @@ -334,7 +237,9 @@ static __init void register_address_space(phys_addr_t memsize) void __init prom_meminit(void) { ptv_memsize = get_memsize(); - register_address_space(ptv_memsize); + register_raw_ram(ptv_memsize); + register_available_ram(); + } void __init prom_free_prom_memory(void) diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c index af2cae0..f430156 100644 --- a/arch/mips/powertv/powertv_setup.c +++ b/arch/mips/powertv/powertv_setup.c @@ -1,7 +1,7 @@ /* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. + * Portions copyright (C) 2009-2010 Cisco Systems, Inc. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -36,6 +36,8 @@ #include #include #include +#include +#include #include "reset.h" #define VAL(n) STR(n) From jiang.adam@gmail.com Sat Aug 21 08:29:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Aug 2010 08:29:10 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:64859 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490946Ab0HUG3F (ORCPT ); Sat, 21 Aug 2010 08:29:05 +0200 Received: by pwj3 with SMTP id 3so1149277pwj.36 for ; Fri, 20 Aug 2010 23:28:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=PYAW4zxyOvQTT2W3t9+71gEfqF/1Zd0Oxzm5MA68VME=; b=IxCQvfMMQbvjg15/hkJfLI84rE/bR/VCNhqLfl6ND0O5ZzZPZwe0s3ODF96xJhfO7N gyzJkivu11tFkB2lxreUqs7XSCDl4avAeEfCJPZvslcMpVfg7Sk+4l7kHwGOsVM4nMmP 4Aw48myMA5er8/S5w3TM5TyuOAr4f+r5I014w= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=ODIToE9HmHs/EYhG3LpLgMkOSg8KBRR+ciGZMY289SjiqOvu3KI8jF/owxMTzf3di7 JxEZyGHBmuc4OORJKFn9BtRJTGgkm0OKmIGt+YF34WOjDSyIefJjQM30nWHrPv7aH+46 c8lTvxgiYqgcfgbO6Ble1f2PEVTb8WWd7jsxU= Received: by 10.142.81.19 with SMTP id e19mr1837385wfb.203.1282372139141; Fri, 20 Aug 2010 23:28:59 -0700 (PDT) Received: from localhost (KD118154228076.ppp-bb.dion.ne.jp [118.154.228.76]) by mx.google.com with ESMTPS id 23sm4365966wfa.10.2010.08.20.23.28.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 20 Aug 2010 23:28:57 -0700 (PDT) From: jiang.adam@gmail.com To: ralf@linux-mips.org Cc: dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Adam Jiang Subject: [PATCH] mips: irq: add statckoverflow detection Date: Sat, 21 Aug 2010 15:31:33 +0900 Message-Id: <1282372293-30211-1-git-send-email-jiang.adam@gmail.com> X-Mailer: git-send-email 1.7.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27656 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jiang.adam@gmail.com Precedence: bulk X-list: linux-mips From: Adam Jiang Add stackoverflow detection to mips arch Signed-off-by: Adam Jiang --- arch/mips/Kconfig.debug | 7 +++++++ arch/mips/kernel/irq.c | 19 +++++++++++++++++++ 2 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 43dc279..f1a00a2 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -67,6 +67,13 @@ config CMDLINE_OVERRIDE Normally, you will choose 'N' here. +config DEBUG_STACKOVERFLOW + bool "Check for stack overflows" + depends on DEBUG_KERNEL + help + This option will cause messages to be printed if free stack space + drops below a certain limit. + config DEBUG_STACK_USAGE bool "Enable stack utilization instrumentation" depends on DEBUG_KERNEL diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index c6345f5..6334037 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -151,6 +151,22 @@ void __init init_IRQ(void) #endif } +static inline void check_stack_overflow(void) +{ +#ifdef CONFIG_DEBUG_STACKOVERFLOW + long sp; + + asm volatile("move %0, $sp" : "=r" (sp)); + sp = sp & (THREAD_SIZE-1); + + /* check for stack overflow: is there less then 2KB free? */ + if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { + printk("do_IRQ: stack overflow: %ld\n", + sp - sizeof(struct thread_info)); + dump_stack(); + } +#endif +} /* * do_IRQ handles all normal device IRQ's (the special * SMP cross-CPU interrupts have their own specific @@ -159,6 +175,9 @@ void __init init_IRQ(void) void __irq_entry do_IRQ(unsigned int irq) { irq_enter(); + + check_stack_overflow(); + __DO_IRQ_SMTC_HOOK(irq); generic_handle_irq(irq); irq_exit(); -- 1.7.1 From sshtylyov@mvista.com Sat Aug 21 15:10:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Aug 2010 15:10:08 +0200 (CEST) Received: from mail-ey0-f177.google.com ([209.85.215.177]:42746 "EHLO mail-ey0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490945Ab0HUNKB (ORCPT ); Sat, 21 Aug 2010 15:10:01 +0200 Received: by eye22 with SMTP id 22so3042033eye.36 for ; Sat, 21 Aug 2010 06:10:00 -0700 (PDT) Received: by 10.213.105.77 with SMTP id s13mr2644792ebo.50.1282396199918; Sat, 21 Aug 2010 06:09:59 -0700 (PDT) Received: from [192.168.2.2] ([91.79.54.27]) by mx.google.com with ESMTPS id a48sm6854178eei.13.2010.08.21.06.09.56 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 21 Aug 2010 06:09:57 -0700 (PDT) Message-ID: <4C6FCFC7.7020903@mvista.com> Date: Sat, 21 Aug 2010 17:08:23 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 To: jiang.adam@gmail.com CC: ralf@linux-mips.org, dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: irq: add statckoverflow detection References: <1282372293-30211-1-git-send-email-jiang.adam@gmail.com> In-Reply-To: <1282372293-30211-1-git-send-email-jiang.adam@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27657 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. jiang.adam@gmail.com wrote: > From: Adam Jiang > Add stackoverflow detection to mips arch > Signed-off-by: Adam Jiang [...] > diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c > index c6345f5..6334037 100644 > --- a/arch/mips/kernel/irq.c > +++ b/arch/mips/kernel/irq.c > @@ -151,6 +151,22 @@ void __init init_IRQ(void) > #endif > } > > +static inline void check_stack_overflow(void) > +{ > +#ifdef CONFIG_DEBUG_STACKOVERFLOW #ifdef within function is considered bad style. Better do it this way: #ifdef CONFIG_DEBUG_STACKOVERFLOW static inline void check_stack_overflow(void) { [...] } #else static inline void check_stack_overflow(void) {} #endif > + long sp; > + > + asm volatile("move %0, $sp" : "=r" (sp)); > + sp = sp & (THREAD_SIZE-1); > + > + /* check for stack overflow: is there less then 2KB free? */ Hm, 2KB seems pretty large margin... WBR, Sergei From wuzhangjin@gmail.com Sun Aug 22 14:18:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Aug 2010 14:18:13 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:63620 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491050Ab0HVMSJ (ORCPT ); Sun, 22 Aug 2010 14:18:09 +0200 Received: by wwe15 with SMTP id 15so2784567wwe.24 for ; Sun, 22 Aug 2010 05:18:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:cc:content-type; bh=HE3JUlK8oPc5Xml5ocknOq0aIKEoQwtRHDPvERDoxIo=; b=OJGUF56BqnBoBIXQqyPfhyPqIieMYx+RRdBVHHqltZ9mYXK0j9B0ycD0I5KuSMCCM5 LxvTb7n6AWm9GJpTPyb5oHkDA6fk/vIig2x1bwYJNTNPBHh4psp/4k8diS1IYIK0HRZI ajzkKvPWmXnDsMv++Uv3c8zb8lQZ0fzRvyaTo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; b=Xox32k3/WYeQRqZqoQJ8ubi53QbB88SEcsVSmiyqFb7/+J5sk9r+U3lkjF0d7qYlP2 yPbReC31GUSbNF0v7iCUJf4xBIkc7akVHOWiaHhyTmjIvvR0PihwJ9fJLoBxn0N5b/vH txyJbuBrfPrs81EY4PiyTr7VJuOdHZ9G36pnQ= MIME-Version: 1.0 Received: by 10.216.1.77 with SMTP id 55mr3324057wec.72.1282479483846; Sun, 22 Aug 2010 05:18:03 -0700 (PDT) Received: by 10.216.159.199 with HTTP; Sun, 22 Aug 2010 05:18:03 -0700 (PDT) Date: Sun, 22 Aug 2010 20:18:03 +0800 Message-ID: Subject: Ftrace for MIPS may hang on SMP system From: wu zhangjin To: Ralf Baechle , Steven Rostedt , David Daney Cc: linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27658 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, all For I didn't have a SMP machine, I haven't used Ftrace(in 2.6.34) for MIPS on SMP system before, Yesterday, I got a RMI XLS machine and found Ftrace for MIPS hanged on it after I issued: $ echo function > /debug/tracing/current_tracer I have gotten the root cause, that is: in kernel/trace/ftrace.c: stop_machine() disables the irqs of the other cpus and then modify the codes via calling the arch specific ftrace_modify_code() in __ftrace_modify_code(). As the description about stop_machine() in arch/x86/kernel/ftrace.c shows: /* * Modifying code must take extra care. On an SMP machine, if * the code being modified is also being executed on another CPU * that CPU will have undefined results and possibly take a GPF. * We use kstop_machine to stop other CPUS from exectuing code. [snip] Then, it is reasonable to use stop_machine() here. And in arch/mips/kernel/ftrace.c: flush_icache_range() is called in ftrace_modify_code() to ensure the intructions will be executed are what we want. In UP system, there is no problem for flush_icache_range() simply flush the instruction cache, but In SMP system, this may be different, for flush_icache_range() may also need to ask the other cpus (via sending ipi interrupt) to flush their icaches and will wait for them till the other cpus finish their flushing. But as we know above, the irqs of the other cpus are disabled by stop_machine(), they have no opportunity to flush their icache and will let the current cpu wait for them all the time, then soft lock --> hang. To fix it, there are two potential solutions: 1. replace flush_icache_range() by something else, maybe we can use the similar method in arch/x86/kernel/ftrace.c, x86 uses sync_core() defined in arch/x86/include/asm/processor.h to flush the icache on all processors: /* Stop speculative execution and prefetching of modified code. */ static inline void sync_core(void) { int tmp; #if defined(CONFIG_M386) || defined(CONFIG_M486) if (boot_cpu_data.x86 < 5) /* There is no speculative execution. * jmp is a barrier to prefetching. */ asm volatile("jmp 1f\n1:\n" ::: "memory"); else #endif /* cpuid is a barrier to speculative execution. * Prefetched instructions are automatically * invalidated when modified. */ asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx", "ecx", "edx", "memory"); } But is there a cpuid like hardware instruction in MIPS SMP? As I know, in UP, we may be possible to use prefetch instruction to push the instruction to the cache, but in SMP, is there a instruction to force the other cpus to flush their cache too? 2. Replace the stop_machine() by something else I have written such a patch: diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 2404b59..e4d058f 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -1129,13 +1129,18 @@ static int __ftrace_modify_code(void *data) static void ftrace_run_update_code(int command) { int ret; + unsigned long flags; ret = ftrace_arch_code_modify_prepare(); FTRACE_WARN_ON(ret); if (ret) return; - stop_machine(__ftrace_modify_code, &command, NULL); + preempt_disable(); + local_irq_save(flags); + __ftrace_modify_code(&command); + local_irq_restore(flags); + preempt_enable(); ret = ftrace_arch_code_modify_post_process(); FTRACE_WARN_ON(ret); It works without any hang but I'm not sure whether it will guarantee the "undefined results" problem mentioned above. Here we may need to prevent the other cpus from executing the source code for we are modifying the source code but also need to allow them to get the ipi interrupt and flush their icaches. And I have took a look at the part of code modification in kgdb system, seems it doesn't use stop_machine(). What's your ideas? Thanks & Regards, Wu Zhangjin From wuzhangjin@gmail.com Sun Aug 22 14:20:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Aug 2010 14:20:11 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:54841 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491050Ab0HVMUH (ORCPT ); Sun, 22 Aug 2010 14:20:07 +0200 Received: by wyb34 with SMTP id 34so2749475wyb.36 for ; Sun, 22 Aug 2010 05:20:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=tifRJWGb9/WpALnZ11txK4OA4gGgkUmy+2gM6tucfkY=; b=KfbNhOYebUXMU9cjF2sXMrvAos08wlkXXGLaGg/O2fYaWrIx6Bnm3EzN82HCG0DDWO wWZyvN1pcVcRwVi3CFTmMqruDNPKHBUpwKIJo8Vv+y/UdAIGLmbhpSpEBLKpgapa0sYW JczrNdkq9YvR8qc+xqFkuyDwBr9mc03D+HXSY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=EoPc+muMC8BPwztY+0WA7sdcVnE1HtzobxQPVwg23ZVJYhNW8U5RHtX4C3l4nWhUP0 u1J82/2XUua8Yvt8nCqmbGlPI/3HktDMfUkrH5RyAH1d3Yynhazye7eAamcoWW8fhEDd u+D8V0k7t0dhXfzocIeq2Bm/9QVTTa/+TZiQI= MIME-Version: 1.0 Received: by 10.216.236.197 with SMTP id w47mr1371013weq.114.1282479602274; Sun, 22 Aug 2010 05:20:02 -0700 (PDT) Received: by 10.216.159.199 with HTTP; Sun, 22 Aug 2010 05:20:02 -0700 (PDT) In-Reply-To: References: Date: Sun, 22 Aug 2010 20:20:02 +0800 Message-ID: Subject: Re: Ftrace for MIPS may hang on SMP system From: wu zhangjin To: Ralf Baechle , Steven Rostedt , David Daney Cc: linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27659 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips (Add 'another' Steven in this loop) On 8/22/10, wu zhangjin wrote: > Hi, all > > For I didn't have a SMP machine, I haven't used Ftrace(in 2.6.34) for > MIPS on SMP system before, Yesterday, I got a RMI XLS machine and > found Ftrace for MIPS hanged on it after I issued: > > $ echo function > /debug/tracing/current_tracer > > I have gotten the root cause, that is: > > in kernel/trace/ftrace.c: > > stop_machine() disables the irqs of the other cpus and then modify the > codes via calling the arch specific ftrace_modify_code() in > __ftrace_modify_code(). > > As the description about stop_machine() in arch/x86/kernel/ftrace.c shows: > > /* > * Modifying code must take extra care. On an SMP machine, if > * the code being modified is also being executed on another CPU > * that CPU will have undefined results and possibly take a GPF. > * We use kstop_machine to stop other CPUS from exectuing code. > [snip] > > Then, it is reasonable to use stop_machine() here. > > And in arch/mips/kernel/ftrace.c: > > flush_icache_range() is called in ftrace_modify_code() to ensure the > intructions will be executed are what we want. > > In UP system, there is no problem for flush_icache_range() simply > flush the instruction cache, but In SMP system, this may be different, > for flush_icache_range() may also need to ask the other cpus (via > sending ipi interrupt) to flush their icaches and will wait for them > till the other cpus finish their flushing. > > But as we know above, the irqs of the other cpus are disabled by > stop_machine(), they have no opportunity to flush their icache and > will let the current cpu wait for them all the time, then soft lock > --> hang. > > To fix it, there are two potential solutions: > > 1. replace flush_icache_range() by something else, maybe we can use > the similar method in arch/x86/kernel/ftrace.c, x86 uses sync_core() > defined in arch/x86/include/asm/processor.h to flush the icache on all > processors: > > /* Stop speculative execution and prefetching of modified code. */ > static inline void sync_core(void) > { > int tmp; > > #if defined(CONFIG_M386) || defined(CONFIG_M486) > if (boot_cpu_data.x86 < 5) > /* There is no speculative execution. > * jmp is a barrier to prefetching. */ > asm volatile("jmp 1f\n1:\n" ::: "memory"); > else > #endif > /* cpuid is a barrier to speculative execution. > * Prefetched instructions are automatically > * invalidated when modified. */ > asm volatile("cpuid" : "=a" (tmp) : "0" (1) > : "ebx", "ecx", "edx", "memory"); > } > > But is there a cpuid like hardware instruction in MIPS SMP? As I know, > in UP, we may be possible to use prefetch instruction to push the > instruction to the cache, but in SMP, is there a instruction to force > the other cpus to flush their cache too? > > 2. Replace the stop_machine() by something else > > I have written such a patch: > > diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c > index 2404b59..e4d058f 100644 > --- a/kernel/trace/ftrace.c > +++ b/kernel/trace/ftrace.c > @@ -1129,13 +1129,18 @@ static int __ftrace_modify_code(void *data) > static void ftrace_run_update_code(int command) > { > int ret; > + unsigned long flags; > > ret = ftrace_arch_code_modify_prepare(); > FTRACE_WARN_ON(ret); > if (ret) > return; > > - stop_machine(__ftrace_modify_code, &command, NULL); > + preempt_disable(); > + local_irq_save(flags); > + __ftrace_modify_code(&command); > + local_irq_restore(flags); > + preempt_enable(); > > ret = ftrace_arch_code_modify_post_process(); > FTRACE_WARN_ON(ret); > > It works without any hang but I'm not sure whether it will guarantee > the "undefined results" problem mentioned above. Here we may need to > prevent the other cpus from executing the source code for we are > modifying the source code but also need to allow them to get the ipi > interrupt and flush their icaches. > > And I have took a look at the part of code modification in kgdb > system, seems it doesn't use stop_machine(). > > What's your ideas? > > Thanks & Regards, > Wu Zhangjin > -- MSN+Gtalk: wuzhangjin@gmail.com Blog: http://falcon.oss.lzu.edu.cn Tel:+86-18710032278 From wuzhangjin@gmail.com Sun Aug 22 16:27:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Aug 2010 16:27:29 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:53220 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490953Ab0HVO10 (ORCPT ); Sun, 22 Aug 2010 16:27:26 +0200 Received: by wwe15 with SMTP id 15so2871483wwe.24 for ; Sun, 22 Aug 2010 07:27:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=uMsYgeoIzsXdWE7qBMcGlXvToHs0Tg3coTZXw5kVszI=; b=tMK2brmg+KeWy+yluOewLmN0k5XPLQaM99r/Uoac3zSMSV+WvAO98N9IVbUA7VTUCj PalzzmHrzCqk/uPSFwATH51+HKKe0JOf2j1EkNrvhjJzjsDZZ7bapSsxkPiMoTD6bAmd jT4zB3mi0vUfmc2mIhRqlPK71yVDvXOyZDEh4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=Y/0M84WtnLQE1mfsEUOjp3DQ3hBgW5kVYxqpJsGsYktl2pPMK6ALW6DZb2V/GsUltS Hbnr3ZtWTG2Ht9YJKCJ1frph3miNEVVndRjEin0Bwr+es+6fSZxLLnTG5JWWLPezrsts fzenkF2RTz3PJJ6J4F7ukD0Q/RhshS2yEz8PI= MIME-Version: 1.0 Received: by 10.216.59.131 with SMTP id s3mr3397345wec.71.1282487238565; Sun, 22 Aug 2010 07:27:18 -0700 (PDT) Received: by 10.216.159.199 with HTTP; Sun, 22 Aug 2010 07:27:18 -0700 (PDT) In-Reply-To: References: Date: Sun, 22 Aug 2010 22:27:18 +0800 Message-ID: Subject: Re: Ftrace for MIPS may hang on SMP system From: wu zhangjin To: Ralf Baechle , Steven Rostedt , David Daney Cc: linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27660 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On 8/22/10, wu zhangjin wrote: > (Add 'another' Steven in this loop) > > On 8/22/10, wu zhangjin wrote: >> Hi, all >> >> For I didn't have a SMP machine, I haven't used Ftrace(in 2.6.34) for >> MIPS on SMP system before, Yesterday, I got a RMI XLS machine and >> found Ftrace for MIPS hanged on it after I issued: >> >> $ echo function > /debug/tracing/current_tracer >> >> I have gotten the root cause, that is: >> >> in kernel/trace/ftrace.c: >> >> stop_machine() disables the irqs of the other cpus and then modify the >> codes via calling the arch specific ftrace_modify_code() in >> __ftrace_modify_code(). >> >> As the description about stop_machine() in arch/x86/kernel/ftrace.c >> shows: >> >> /* >> * Modifying code must take extra care. On an SMP machine, if >> * the code being modified is also being executed on another CPU >> * that CPU will have undefined results and possibly take a GPF. >> * We use kstop_machine to stop other CPUS from exectuing code. >> [snip] >> >> Then, it is reasonable to use stop_machine() here. >> >> And in arch/mips/kernel/ftrace.c: >> >> flush_icache_range() is called in ftrace_modify_code() to ensure the >> intructions will be executed are what we want. >> >> In UP system, there is no problem for flush_icache_range() simply >> flush the instruction cache, but In SMP system, this may be different, >> for flush_icache_range() may also need to ask the other cpus (via >> sending ipi interrupt) to flush their icaches and will wait for them >> till the other cpus finish their flushing. >> >> But as we know above, the irqs of the other cpus are disabled by >> stop_machine(), they have no opportunity to flush their icache and >> will let the current cpu wait for them all the time, then soft lock >> --> hang. >> >> To fix it, there are two potential solutions: >> >> 1. replace flush_icache_range() by something else, maybe we can use >> the similar method in arch/x86/kernel/ftrace.c, x86 uses sync_core() >> defined in arch/x86/include/asm/processor.h to flush the icache on all >> processors: >> >> /* Stop speculative execution and prefetching of modified code. */ >> static inline void sync_core(void) >> { >> int tmp; >> >> #if defined(CONFIG_M386) || defined(CONFIG_M486) >> if (boot_cpu_data.x86 < 5) >> /* There is no speculative execution. >> * jmp is a barrier to prefetching. */ >> asm volatile("jmp 1f\n1:\n" ::: "memory"); >> else >> #endif >> /* cpuid is a barrier to speculative execution. >> * Prefetched instructions are automatically >> * invalidated when modified. */ >> asm volatile("cpuid" : "=a" (tmp) : "0" (1) >> : "ebx", "ecx", "edx", "memory"); >> } >> >> But is there a cpuid like hardware instruction in MIPS SMP? As I know, >> in UP, we may be possible to use prefetch instruction to push the >> instruction to the cache, but in SMP, is there a instruction to force >> the other cpus to flush their cache too? >> >> 2. Replace the stop_machine() by something else >> >> I have written such a patch: >> >> diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c >> index 2404b59..e4d058f 100644 >> --- a/kernel/trace/ftrace.c >> +++ b/kernel/trace/ftrace.c >> @@ -1129,13 +1129,18 @@ static int __ftrace_modify_code(void *data) >> static void ftrace_run_update_code(int command) >> { >> int ret; >> + unsigned long flags; >> >> ret = ftrace_arch_code_modify_prepare(); >> FTRACE_WARN_ON(ret); >> if (ret) >> return; >> >> - stop_machine(__ftrace_modify_code, &command, NULL); >> + preempt_disable(); >> + local_irq_save(flags); >> + __ftrace_modify_code(&command); >> + local_irq_restore(flags); >> + preempt_enable(); >> >> ret = ftrace_arch_code_modify_post_process(); >> FTRACE_WARN_ON(ret); >> We may need to protect the __ftrace_modify_code() with raw spin lock. >> It works without any hang but I'm not sure whether it will guarantee >> the "undefined results" problem mentioned above. Here we may need to >> prevent the other cpus from executing the source code for we are >> modifying the source code but also need to allow them to get the ipi >> interrupt and flush their icaches. >> >> And I have took a look at the part of code modification in kgdb >> system, seems it doesn't use stop_machine(). >> >> What's your ideas? >> >> Thanks & Regards, >> Wu Zhangjin >> > > > -- > MSN+Gtalk: wuzhangjin@gmail.com > Blog: http://falcon.oss.lzu.edu.cn > Tel:+86-18710032278 > -- MSN+Gtalk: wuzhangjin@gmail.com Blog: http://falcon.oss.lzu.edu.cn Tel:+86-18710032278 From macro@linux-mips.org Mon Aug 23 02:54:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Aug 2010 02:54:28 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:49570 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490947Ab0HWAyY (ORCPT ); Mon, 23 Aug 2010 02:54:24 +0200 Date: Mon, 23 Aug 2010 01:54:24 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: Re: MIPS: Get rid of branches to .subsections. In-Reply-To: <20100818124310.GA23744@linux-mips.org> Message-ID: References: <20100818124310.GA23744@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27661 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, 18 Aug 2010, Ralf Baechle wrote: > By rewriting the loop around all simple LL/SC blocks to C we reduce reduce > the amount of inline assembler and at the same time allow GCC to often > fill the branch delay slots with something sensible or whever else clever > optimization it may have up in its sleeve. Are you sure it won't reorder anything there that actually relies on the atomic access to have succeeded? I suggest adding barrier() after the loop. Maciej From ralf@linux-mips.org Mon Aug 23 12:13:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Aug 2010 12:13:05 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44035 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490947Ab0HWKNB (ORCPT ); Mon, 23 Aug 2010 12:13:01 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o7NACwdx000871; Mon, 23 Aug 2010 11:12:58 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o7NACv0X000869; Mon, 23 Aug 2010 11:12:57 +0100 Date: Mon, 23 Aug 2010 11:12:57 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: Re: MIPS: Get rid of branches to .subsections. Message-ID: <20100823101257.GA19171@linux-mips.org> References: <20100818124310.GA23744@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27662 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Aug 23, 2010 at 01:54:24AM +0100, Maciej W. Rozycki wrote: > > By rewriting the loop around all simple LL/SC blocks to C we reduce reduce > > the amount of inline assembler and at the same time allow GCC to often > > fill the branch delay slots with something sensible or whever else clever > > optimization it may have up in its sleeve. > > Are you sure it won't reorder anything there that actually relies on the > atomic access to have succeeded? I suggest adding barrier() after the > loop. None of the things that were touched by the code had any barrier functionality Some of the functions such as atomic_add don't provide memory barriers but where needed a barrier was always provided by C code near the end of the function, for example in atomic_add_return. Ralf From macro@linux-mips.org Mon Aug 23 13:25:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Aug 2010 13:25:36 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:60319 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491011Ab0HWLZd (ORCPT ); Mon, 23 Aug 2010 13:25:33 +0200 Date: Mon, 23 Aug 2010 12:25:33 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: linux-mips@linux-mips.org, Paul Gortmaker Subject: Re: MIPS: Get rid of branches to .subsections. In-Reply-To: <20100823101257.GA19171@linux-mips.org> Message-ID: References: <20100818124310.GA23744@linux-mips.org> <20100823101257.GA19171@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27663 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 23 Aug 2010, Ralf Baechle wrote: > > Are you sure it won't reorder anything there that actually relies on the > > atomic access to have succeeded? I suggest adding barrier() after the > > loop. > > None of the things that were touched by the code had any barrier > functionality Some of the functions such as atomic_add don't provide > memory barriers but where needed a barrier was always provided by C code > near the end of the function, for example in atomic_add_return. OK, if you are sure this is safe, then I see no problem here. Maciej From wuzhangjin@gmail.com Mon Aug 23 14:50:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Aug 2010 14:50:45 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:52636 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491032Ab0HWMum (ORCPT ); Mon, 23 Aug 2010 14:50:42 +0200 Received: by fxm12 with SMTP id 12so3545868fxm.36 for ; Mon, 23 Aug 2010 05:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=dIlBgBYfBwts1LWPjasveFR+Suep+44p+qb+dicsJ1k=; b=X3YE51PZAvzx4GCcMfm0AFah9zJFotBJtE8zd8SCSekrO1bpA1zWbumPXgHHbR7l+V rhlqhlqDDiUTf4pt8W3VxSEohQU1iSuZFIRlGFCxx4yWhQQLLpMNW3XD3KaPqB+H1wiL 9pycMGKVsf9TrWybztIYM0BV1ClCZ9k9L0dII= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=UlsTE4E0FRkyn5cfS+qVBtahHMtRPwN70urWhDXpHdanSrUpd1MQKWY5ICtJO1HjyN 1Tn4VgzhAqA9uImFtMldgHYvrLOHQfdbKnY5zPxhYSSjekbkZePpGcQ76jrhiBWTTnQV UFuwsKEFg/4bmBf7QHwA4hTHjXiQqgKvO5Aqw= MIME-Version: 1.0 Received: by 10.216.188.197 with SMTP id a47mr4484860wen.70.1282567836849; Mon, 23 Aug 2010 05:50:36 -0700 (PDT) Received: by 10.216.166.69 with HTTP; Mon, 23 Aug 2010 05:50:36 -0700 (PDT) In-Reply-To: References: Date: Mon, 23 Aug 2010 20:50:36 +0800 Message-ID: Subject: Re: Ftrace for MIPS may hang on SMP system From: wu zhangjin To: Ralf Baechle , Steven Rostedt , David Daney Cc: linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27664 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, To avoid touching the other parts, I have used the following method: delay the cache flushing operation after the stop_machine(). Here is the patch: diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 5a84a1f..f4c9581 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -33,6 +33,25 @@ static inline int in_module(unsigned long ip) return ip & 0x40000000; } +#ifdef CONFIG_SMP +static bool machine_stopped; + +int ftrace_arch_code_modify_prepare(void) +{ + preempt_disable(); + machine_stopped = 1; + return 0; +} + +int ftrace_arch_code_modify_post_process(void) +{ + __flush_cache_all(); + machine_stopped = 0; + preempt_enable(); + return 0; +} +#endif + #ifdef CONFIG_DYNAMIC_FTRACE #define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */ @@ -79,7 +98,12 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) if (unlikely(faulted)) return -EFAULT; - flush_icache_range(ip, ip + 8); +#ifndef CONFIG_SMP + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); +#else + if (!machine_stopped) + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); +#endif return 0; } Regards, Wu Zhangjin On 8/22/10, wu zhangjin wrote: > On 8/22/10, wu zhangjin wrote: >> (Add 'another' Steven in this loop) >> >> On 8/22/10, wu zhangjin wrote: >>> Hi, all >>> >>> For I didn't have a SMP machine, I haven't used Ftrace(in 2.6.34) for >>> MIPS on SMP system before, Yesterday, I got a RMI XLS machine and >>> found Ftrace for MIPS hanged on it after I issued: >>> >>> $ echo function > /debug/tracing/current_tracer >>> >>> I have gotten the root cause, that is: >>> >>> in kernel/trace/ftrace.c: >>> >>> stop_machine() disables the irqs of the other cpus and then modify the >>> codes via calling the arch specific ftrace_modify_code() in >>> __ftrace_modify_code(). >>> >>> As the description about stop_machine() in arch/x86/kernel/ftrace.c >>> shows: >>> >>> /* >>> * Modifying code must take extra care. On an SMP machine, if >>> * the code being modified is also being executed on another CPU >>> * that CPU will have undefined results and possibly take a GPF. >>> * We use kstop_machine to stop other CPUS from exectuing code. >>> [snip] >>> >>> Then, it is reasonable to use stop_machine() here. >>> >>> And in arch/mips/kernel/ftrace.c: >>> >>> flush_icache_range() is called in ftrace_modify_code() to ensure the >>> intructions will be executed are what we want. >>> >>> In UP system, there is no problem for flush_icache_range() simply >>> flush the instruction cache, but In SMP system, this may be different, >>> for flush_icache_range() may also need to ask the other cpus (via >>> sending ipi interrupt) to flush their icaches and will wait for them >>> till the other cpus finish their flushing. >>> >>> But as we know above, the irqs of the other cpus are disabled by >>> stop_machine(), they have no opportunity to flush their icache and >>> will let the current cpu wait for them all the time, then soft lock >>> --> hang. >>> >>> To fix it, there are two potential solutions: >>> >>> 1. replace flush_icache_range() by something else, maybe we can use >>> the similar method in arch/x86/kernel/ftrace.c, x86 uses sync_core() >>> defined in arch/x86/include/asm/processor.h to flush the icache on all >>> processors: >>> >>> /* Stop speculative execution and prefetching of modified code. */ >>> static inline void sync_core(void) >>> { >>> int tmp; >>> >>> #if defined(CONFIG_M386) || defined(CONFIG_M486) >>> if (boot_cpu_data.x86 < 5) >>> /* There is no speculative execution. >>> * jmp is a barrier to prefetching. */ >>> asm volatile("jmp 1f\n1:\n" ::: "memory"); >>> else >>> #endif >>> /* cpuid is a barrier to speculative execution. >>> * Prefetched instructions are automatically >>> * invalidated when modified. */ >>> asm volatile("cpuid" : "=a" (tmp) : "0" (1) >>> : "ebx", "ecx", "edx", "memory"); >>> } >>> >>> But is there a cpuid like hardware instruction in MIPS SMP? As I know, >>> in UP, we may be possible to use prefetch instruction to push the >>> instruction to the cache, but in SMP, is there a instruction to force >>> the other cpus to flush their cache too? >>> >>> 2. Replace the stop_machine() by something else >>> >>> I have written such a patch: >>> >>> diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c >>> index 2404b59..e4d058f 100644 >>> --- a/kernel/trace/ftrace.c >>> +++ b/kernel/trace/ftrace.c >>> @@ -1129,13 +1129,18 @@ static int __ftrace_modify_code(void *data) >>> static void ftrace_run_update_code(int command) >>> { >>> int ret; >>> + unsigned long flags; >>> >>> ret = ftrace_arch_code_modify_prepare(); >>> FTRACE_WARN_ON(ret); >>> if (ret) >>> return; >>> >>> - stop_machine(__ftrace_modify_code, &command, NULL); >>> + preempt_disable(); >>> + local_irq_save(flags); >>> + __ftrace_modify_code(&command); >>> + local_irq_restore(flags); >>> + preempt_enable(); >>> >>> ret = ftrace_arch_code_modify_post_process(); >>> FTRACE_WARN_ON(ret); >>> > > We may need to protect the __ftrace_modify_code() with raw spin lock. > >>> It works without any hang but I'm not sure whether it will guarantee >>> the "undefined results" problem mentioned above. Here we may need to >>> prevent the other cpus from executing the source code for we are >>> modifying the source code but also need to allow them to get the ipi >>> interrupt and flush their icaches. >>> >>> And I have took a look at the part of code modification in kgdb >>> system, seems it doesn't use stop_machine(). >>> >>> What's your ideas? >>> >>> Thanks & Regards, >>> Wu Zhangjin From wuzhangjin@gmail.com Mon Aug 23 16:16:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Aug 2010 16:16:48 +0200 (CEST) Received: from mail-ww0-f41.google.com ([74.125.82.41]:45285 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491030Ab0HWOQl (ORCPT ); Mon, 23 Aug 2010 16:16:41 +0200 Received: by wwb39 with SMTP id 39so265735wwb.0 for ; Mon, 23 Aug 2010 07:16:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=/zdEhQdIcnVc74Bd+syyCEjk3sYZU3oGII50M6dH1Lc=; b=lKCzT1KRag4KTM0nfM+b6TihASdLPcG0LdMOpfjXm59QkFuBV9Pk8CVFWlqru7EhqD AQGNP0KjnfmAz6AIa9ldo64oHxtDoAVqzcLsiCQYgl0TYZtrycO38R7XtYwBwuEjsaWZ pyq7IWWQ4EepfGeRNvDLdwZCCf/6dWwWeFC34= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=yBD9Ea16BmcH3ExJGHJaFm5XkyovSTj3+pGVGU1pe38HWfLMEj0MtHiCCj2bXFq5fE 4mvKh+FDJm/F914ndEz1ldaNYVXcBqvPMpRGECvONxQgYaCCN9Lh6H/4lkhk315BbQpT S3GgRlKCLDm4X/kOafeDu0JQqQQ3/hRR8KzEo= MIME-Version: 1.0 Received: by 10.227.152.149 with SMTP id g21mr4393469wbw.228.1282572993965; Mon, 23 Aug 2010 07:16:33 -0700 (PDT) Received: by 10.216.166.69 with HTTP; Mon, 23 Aug 2010 07:16:33 -0700 (PDT) In-Reply-To: References: Date: Mon, 23 Aug 2010 22:16:33 +0800 Message-ID: Subject: Re: Ftrace for MIPS may hang on SMP system From: wu zhangjin To: Ralf Baechle , Steven Rostedt , David Daney Cc: linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27665 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On 8/23/10, wu zhangjin wrote: > Hi, > > To avoid touching the other parts, I have used the following method: > > delay the cache flushing operation after the stop_machine(). > > Here is the patch: > > diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c > index 5a84a1f..f4c9581 100644 > --- a/arch/mips/kernel/ftrace.c > +++ b/arch/mips/kernel/ftrace.c > @@ -33,6 +33,25 @@ static inline int in_module(unsigned long ip) > return ip & 0x40000000; > } > > +#ifdef CONFIG_SMP > +static bool machine_stopped; > + > +int ftrace_arch_code_modify_prepare(void) > +{ > + preempt_disable(); preempt_disable() is not necessary, and it may introduce the warning about "scheduling in atomic()" Regards, Wu Zhangjin > + machine_stopped = 1; > + return 0; > +} > + > +int ftrace_arch_code_modify_post_process(void) > +{ > + __flush_cache_all(); > + machine_stopped = 0; > + preempt_enable(); > + return 0; > +} > +#endif > + > #ifdef CONFIG_DYNAMIC_FTRACE > > #define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target > */ > @@ -79,7 +98,12 @@ static int ftrace_modify_code(unsigned long ip, > unsigned int new_code) > if (unlikely(faulted)) > return -EFAULT; > > - flush_icache_range(ip, ip + 8); > +#ifndef CONFIG_SMP > + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); > +#else > + if (!machine_stopped) > + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); > +#endif > > return 0; > } > > > Regards, > Wu Zhangjin > > On 8/22/10, wu zhangjin wrote: >> On 8/22/10, wu zhangjin wrote: >>> (Add 'another' Steven in this loop) >>> >>> On 8/22/10, wu zhangjin wrote: >>>> Hi, all >>>> >>>> For I didn't have a SMP machine, I haven't used Ftrace(in 2.6.34) for >>>> MIPS on SMP system before, Yesterday, I got a RMI XLS machine and >>>> found Ftrace for MIPS hanged on it after I issued: >>>> >>>> $ echo function > /debug/tracing/current_tracer >>>> >>>> I have gotten the root cause, that is: >>>> >>>> in kernel/trace/ftrace.c: >>>> >>>> stop_machine() disables the irqs of the other cpus and then modify the >>>> codes via calling the arch specific ftrace_modify_code() in >>>> __ftrace_modify_code(). >>>> >>>> As the description about stop_machine() in arch/x86/kernel/ftrace.c >>>> shows: >>>> >>>> /* >>>> * Modifying code must take extra care. On an SMP machine, if >>>> * the code being modified is also being executed on another CPU >>>> * that CPU will have undefined results and possibly take a GPF. >>>> * We use kstop_machine to stop other CPUS from exectuing code. >>>> [snip] >>>> >>>> Then, it is reasonable to use stop_machine() here. >>>> >>>> And in arch/mips/kernel/ftrace.c: >>>> >>>> flush_icache_range() is called in ftrace_modify_code() to ensure the >>>> intructions will be executed are what we want. >>>> >>>> In UP system, there is no problem for flush_icache_range() simply >>>> flush the instruction cache, but In SMP system, this may be different, >>>> for flush_icache_range() may also need to ask the other cpus (via >>>> sending ipi interrupt) to flush their icaches and will wait for them >>>> till the other cpus finish their flushing. >>>> >>>> But as we know above, the irqs of the other cpus are disabled by >>>> stop_machine(), they have no opportunity to flush their icache and >>>> will let the current cpu wait for them all the time, then soft lock >>>> --> hang. >>>> >>>> To fix it, there are two potential solutions: >>>> >>>> 1. replace flush_icache_range() by something else, maybe we can use >>>> the similar method in arch/x86/kernel/ftrace.c, x86 uses sync_core() >>>> defined in arch/x86/include/asm/processor.h to flush the icache on all >>>> processors: >>>> >>>> /* Stop speculative execution and prefetching of modified code. */ >>>> static inline void sync_core(void) >>>> { >>>> int tmp; >>>> >>>> #if defined(CONFIG_M386) || defined(CONFIG_M486) >>>> if (boot_cpu_data.x86 < 5) >>>> /* There is no speculative execution. >>>> * jmp is a barrier to prefetching. */ >>>> asm volatile("jmp 1f\n1:\n" ::: "memory"); >>>> else >>>> #endif >>>> /* cpuid is a barrier to speculative execution. >>>> * Prefetched instructions are automatically >>>> * invalidated when modified. */ >>>> asm volatile("cpuid" : "=a" (tmp) : "0" (1) >>>> : "ebx", "ecx", "edx", "memory"); >>>> } >>>> >>>> But is there a cpuid like hardware instruction in MIPS SMP? As I know, >>>> in UP, we may be possible to use prefetch instruction to push the >>>> instruction to the cache, but in SMP, is there a instruction to force >>>> the other cpus to flush their cache too? >>>> >>>> 2. Replace the stop_machine() by something else >>>> >>>> I have written such a patch: >>>> >>>> diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c >>>> index 2404b59..e4d058f 100644 >>>> --- a/kernel/trace/ftrace.c >>>> +++ b/kernel/trace/ftrace.c >>>> @@ -1129,13 +1129,18 @@ static int __ftrace_modify_code(void *data) >>>> static void ftrace_run_update_code(int command) >>>> { >>>> int ret; >>>> + unsigned long flags; >>>> >>>> ret = ftrace_arch_code_modify_prepare(); >>>> FTRACE_WARN_ON(ret); >>>> if (ret) >>>> return; >>>> >>>> - stop_machine(__ftrace_modify_code, &command, NULL); >>>> + preempt_disable(); >>>> + local_irq_save(flags); >>>> + __ftrace_modify_code(&command); >>>> + local_irq_restore(flags); >>>> + preempt_enable(); >>>> >>>> ret = ftrace_arch_code_modify_post_process(); >>>> FTRACE_WARN_ON(ret); >>>> >> >> We may need to protect the __ftrace_modify_code() with raw spin lock. >> >>>> It works without any hang but I'm not sure whether it will guarantee >>>> the "undefined results" problem mentioned above. Here we may need to >>>> prevent the other cpus from executing the source code for we are >>>> modifying the source code but also need to allow them to get the ipi >>>> interrupt and flush their icaches. >>>> >>>> And I have took a look at the part of code modification in kgdb >>>> system, seems it doesn't use stop_machine(). >>>> >>>> What's your ideas? >>>> >>>> Thanks & Regards, >>>> Wu Zhangjin > -- MSN+Gtalk: wuzhangjin@gmail.com Blog: http://falcon.oss.lzu.edu.cn Tel:+86-18710032278 From David.Daney@caviumnetworks.com Mon Aug 23 19:35:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Aug 2010 19:35:52 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:3619 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491052Ab0HWRfo (ORCPT ); Mon, 23 Aug 2010 19:35:44 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 23 Aug 2010 10:36:11 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 23 Aug 2010 10:35:39 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 23 Aug 2010 10:35:39 -0700 Message-ID: <4C72B16B.5000101@caviumnetworks.com> Date: Mon, 23 Aug 2010 10:35:39 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: wu zhangjin CC: Ralf Baechle , Steven Rostedt , linux-mips Subject: Re: Ftrace for MIPS may hang on SMP system References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 23 Aug 2010 17:35:39.0328 (UTC) FILETIME=[9A45F400:01CB42E9] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27666 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Can you send a real patch with your proposed complete fix and proper Signed-off-by: header? I would like to test it. Also as a point of reference, I have been using ftrace on 16 way SMP mips64 systems without seeing this issue. David Daney On 08/23/2010 07:16 AM, wu zhangjin wrote: > On 8/23/10, wu zhangjin wrote: >> Hi, >> >> To avoid touching the other parts, I have used the following method: >> >> delay the cache flushing operation after the stop_machine(). >> >> Here is the patch: >> >> diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c >> index 5a84a1f..f4c9581 100644 >> --- a/arch/mips/kernel/ftrace.c >> +++ b/arch/mips/kernel/ftrace.c >> @@ -33,6 +33,25 @@ static inline int in_module(unsigned long ip) >> return ip& 0x40000000; >> } >> >> +#ifdef CONFIG_SMP >> +static bool machine_stopped; >> + >> +int ftrace_arch_code_modify_prepare(void) >> +{ >> + preempt_disable(); > > preempt_disable() is not necessary, and it may introduce the warning > about "scheduling in atomic()" > > Regards, > Wu Zhangjin > >> + machine_stopped = 1; >> + return 0; >> +} >> + >> +int ftrace_arch_code_modify_post_process(void) >> +{ >> + __flush_cache_all(); >> + machine_stopped = 0; >> + preempt_enable(); >> + return 0; >> +} >> +#endif >> + >> #ifdef CONFIG_DYNAMIC_FTRACE >> >> #define JAL 0x0c000000 /* jump& link: ip --> ra, jump to target >> */ >> @@ -79,7 +98,12 @@ static int ftrace_modify_code(unsigned long ip, >> unsigned int new_code) >> if (unlikely(faulted)) >> return -EFAULT; >> >> - flush_icache_range(ip, ip + 8); >> +#ifndef CONFIG_SMP >> + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); >> +#else >> + if (!machine_stopped) >> + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); >> +#endif >> >> return 0; >> } >> >> >> Regards, >> Wu Zhangjin >> >> On 8/22/10, wu zhangjin wrote: >>> On 8/22/10, wu zhangjin wrote: >>>> (Add 'another' Steven in this loop) >>>> >>>> On 8/22/10, wu zhangjin wrote: >>>>> Hi, all >>>>> >>>>> For I didn't have a SMP machine, I haven't used Ftrace(in 2.6.34) for >>>>> MIPS on SMP system before, Yesterday, I got a RMI XLS machine and >>>>> found Ftrace for MIPS hanged on it after I issued: >>>>> >>>>> $ echo function> /debug/tracing/current_tracer >>>>> >>>>> I have gotten the root cause, that is: >>>>> >>>>> in kernel/trace/ftrace.c: >>>>> >>>>> stop_machine() disables the irqs of the other cpus and then modify the >>>>> codes via calling the arch specific ftrace_modify_code() in >>>>> __ftrace_modify_code(). >>>>> >>>>> As the description about stop_machine() in arch/x86/kernel/ftrace.c >>>>> shows: >>>>> >>>>> /* >>>>> * Modifying code must take extra care. On an SMP machine, if >>>>> * the code being modified is also being executed on another CPU >>>>> * that CPU will have undefined results and possibly take a GPF. >>>>> * We use kstop_machine to stop other CPUS from exectuing code. >>>>> [snip] >>>>> >>>>> Then, it is reasonable to use stop_machine() here. >>>>> >>>>> And in arch/mips/kernel/ftrace.c: >>>>> >>>>> flush_icache_range() is called in ftrace_modify_code() to ensure the >>>>> intructions will be executed are what we want. >>>>> >>>>> In UP system, there is no problem for flush_icache_range() simply >>>>> flush the instruction cache, but In SMP system, this may be different, >>>>> for flush_icache_range() may also need to ask the other cpus (via >>>>> sending ipi interrupt) to flush their icaches and will wait for them >>>>> till the other cpus finish their flushing. >>>>> >>>>> But as we know above, the irqs of the other cpus are disabled by >>>>> stop_machine(), they have no opportunity to flush their icache and >>>>> will let the current cpu wait for them all the time, then soft lock >>>>> --> hang. >>>>> >>>>> To fix it, there are two potential solutions: >>>>> >>>>> 1. replace flush_icache_range() by something else, maybe we can use >>>>> the similar method in arch/x86/kernel/ftrace.c, x86 uses sync_core() >>>>> defined in arch/x86/include/asm/processor.h to flush the icache on all >>>>> processors: >>>>> >>>>> /* Stop speculative execution and prefetching of modified code. */ >>>>> static inline void sync_core(void) >>>>> { >>>>> int tmp; >>>>> >>>>> #if defined(CONFIG_M386) || defined(CONFIG_M486) >>>>> if (boot_cpu_data.x86< 5) >>>>> /* There is no speculative execution. >>>>> * jmp is a barrier to prefetching. */ >>>>> asm volatile("jmp 1f\n1:\n" ::: "memory"); >>>>> else >>>>> #endif >>>>> /* cpuid is a barrier to speculative execution. >>>>> * Prefetched instructions are automatically >>>>> * invalidated when modified. */ >>>>> asm volatile("cpuid" : "=a" (tmp) : "0" (1) >>>>> : "ebx", "ecx", "edx", "memory"); >>>>> } >>>>> >>>>> But is there a cpuid like hardware instruction in MIPS SMP? As I know, >>>>> in UP, we may be possible to use prefetch instruction to push the >>>>> instruction to the cache, but in SMP, is there a instruction to force >>>>> the other cpus to flush their cache too? >>>>> >>>>> 2. Replace the stop_machine() by something else >>>>> >>>>> I have written such a patch: >>>>> >>>>> diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c >>>>> index 2404b59..e4d058f 100644 >>>>> --- a/kernel/trace/ftrace.c >>>>> +++ b/kernel/trace/ftrace.c >>>>> @@ -1129,13 +1129,18 @@ static int __ftrace_modify_code(void *data) >>>>> static void ftrace_run_update_code(int command) >>>>> { >>>>> int ret; >>>>> + unsigned long flags; >>>>> >>>>> ret = ftrace_arch_code_modify_prepare(); >>>>> FTRACE_WARN_ON(ret); >>>>> if (ret) >>>>> return; >>>>> >>>>> - stop_machine(__ftrace_modify_code,&command, NULL); >>>>> + preempt_disable(); >>>>> + local_irq_save(flags); >>>>> + __ftrace_modify_code(&command); >>>>> + local_irq_restore(flags); >>>>> + preempt_enable(); >>>>> >>>>> ret = ftrace_arch_code_modify_post_process(); >>>>> FTRACE_WARN_ON(ret); >>>>> >>> >>> We may need to protect the __ftrace_modify_code() with raw spin lock. >>> >>>>> It works without any hang but I'm not sure whether it will guarantee >>>>> the "undefined results" problem mentioned above. Here we may need to >>>>> prevent the other cpus from executing the source code for we are >>>>> modifying the source code but also need to allow them to get the ipi >>>>> interrupt and flush their icaches. >>>>> >>>>> And I have took a look at the part of code modification in kgdb >>>>> system, seems it doesn't use stop_machine(). >>>>> >>>>> What's your ideas? >>>>> >>>>> Thanks& Regards, >>>>> Wu Zhangjin >> > > From David.Daney@caviumnetworks.com Mon Aug 23 23:10:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Aug 2010 23:10:58 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11320 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491073Ab0HWVKx (ORCPT ); Mon, 23 Aug 2010 23:10:53 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 23 Aug 2010 14:11:20 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 23 Aug 2010 14:10:48 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 23 Aug 2010 14:10:48 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o7NLAidx006022; Mon, 23 Aug 2010 14:10:44 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o7NLAf1p006020; Mon, 23 Aug 2010 14:10:41 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Hookup fanotify_init, fanotify_mark, and prlimit64 syscalls. Date: Mon, 23 Aug 2010 14:10:37 -0700 Message-Id: <1282597837-5988-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.7.2.1 X-OriginalArrivalTime: 23 Aug 2010 21:10:48.0728 (UTC) FILETIME=[A8E01180:01CB4307] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27667 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/include/asm/unistd.h | 21 +++++++++++++++------ arch/mips/kernel/linux32.c | 7 +++++++ arch/mips/kernel/scall32-o32.S | 5 ++++- arch/mips/kernel/scall64-64.S | 5 ++++- arch/mips/kernel/scall64-n32.S | 7 +++++-- arch/mips/kernel/scall64-o32.S | 5 ++++- 6 files changed, 39 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index baa318a..550725b 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h @@ -356,16 +356,19 @@ #define __NR_perf_event_open (__NR_Linux + 333) #define __NR_accept4 (__NR_Linux + 334) #define __NR_recvmmsg (__NR_Linux + 335) +#define __NR_fanotify_init (__NR_Linux + 336) +#define __NR_fanotify_mark (__NR_Linux + 337) +#define __NR_prlimit64 (__NR_Linux + 338) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 335 +#define __NR_Linux_syscalls 338 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 335 +#define __NR_O32_Linux_syscalls 338 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -668,16 +671,19 @@ #define __NR_perf_event_open (__NR_Linux + 292) #define __NR_accept4 (__NR_Linux + 293) #define __NR_recvmmsg (__NR_Linux + 294) +#define __NR_fanotify_init (__NR_Linux + 295) +#define __NR_fanotify_mark (__NR_Linux + 296) +#define __NR_prlimit64 (__NR_Linux + 297) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 294 +#define __NR_Linux_syscalls 297 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 294 +#define __NR_64_Linux_syscalls 297 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -985,16 +991,19 @@ #define __NR_accept4 (__NR_Linux + 297) #define __NR_recvmmsg (__NR_Linux + 298) #define __NR_getdents64 (__NR_Linux + 299) +#define __NR_fanotify_init (__NR_Linux + 300) +#define __NR_fanotify_mark (__NR_Linux + 301) +#define __NR_prlimit64 (__NR_Linux + 302) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 299 +#define __NR_Linux_syscalls 302 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 299 +#define __NR_N32_Linux_syscalls 302 #ifdef __KERNEL__ diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index c2dab14..6343b4a 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -341,3 +341,10 @@ asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf, { return sys_lookup_dcookie(merge_64(a0, a1), buf, len); } + +SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags, + u64, a3, u64, a4, int, dfd, const char __user *, pathname) +{ + return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4), + dfd, pathname); +} diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 17202bb..584415e 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -583,7 +583,10 @@ einval: li v0, -ENOSYS sys sys_rt_tgsigqueueinfo 4 sys sys_perf_event_open 5 sys sys_accept4 4 - sys sys_recvmmsg 5 + sys sys_recvmmsg 5 /* 4335 */ + sys sys_fanotify_init 2 + sys sys_fanotify_mark 6 + sys sys_prlimit64 4 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index a8a6c59..f02aeeb 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -420,5 +420,8 @@ sys_call_table: PTR sys_rt_tgsigqueueinfo PTR sys_perf_event_open PTR sys_accept4 - PTR sys_recvmmsg + PTR sys_recvmmsg + PTR sys_fanotify_init /* 5395 */ + PTR sys_fanotify_mark + PTR sys_prlimit64 .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index a3d6613..a2514da 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -418,6 +418,9 @@ EXPORT(sysn32_call_table) PTR compat_sys_rt_tgsigqueueinfo /* 6295 */ PTR sys_perf_event_open PTR sys_accept4 - PTR compat_sys_recvmmsg - PTR sys_getdents + PTR compat_sys_recvmmsg + PTR sys_getdents + PTR sys_fanotify_init /* 6300 */ + PTR sys_fanotify_mark + PTR sys_prlimit64 .size sysn32_call_table,.-sysn32_call_table diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 813689e..171979f 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -538,5 +538,8 @@ sys_call_table: PTR compat_sys_rt_tgsigqueueinfo PTR sys_perf_event_open PTR sys_accept4 - PTR compat_sys_recvmmsg + PTR compat_sys_recvmmsg /* 4335 */ + PTR sys_fanotify_init + PTR sys_32_fanotify_mark + PTR sys_prlimit64 .size sys_call_table,.-sys_call_table -- 1.7.2.1 From wuzhangjin@gmail.com Tue Aug 24 08:05:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Aug 2010 08:05:21 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:63493 "EHLO mail.windriver.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490957Ab0HXGFO (ORCPT ); Tue, 24 Aug 2010 08:05:14 +0200 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.windriver.com (8.14.3/8.14.3) with ESMTP id o7O64u5M020496; Mon, 23 Aug 2010 23:04:56 -0700 (PDT) Received: from ala-mail06.corp.ad.wrs.com ([147.11.57.147]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 23 Aug 2010 23:04:56 -0700 Received: from localhost.localdomain ([128.224.163.135]) by ala-mail06.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 23 Aug 2010 23:04:55 -0700 From: Wu Zhangjin To: Ralf Baechle , Steven Rostedt , David Daney Cc: linux-mips Subject: [PATCH] tracing/ftrace: Fix the potential hang on MIPS SMP Date: Tue, 24 Aug 2010 14:06:51 +0800 Message-Id: <1282630011-23348-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0.4 X-OriginalArrivalTime: 24 Aug 2010 06:04:56.0013 (UTC) FILETIME=[468BAFD0:01CB4352] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27668 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin In Ftrace, we need to flush the icache after code modification to ensure the instructions will be executed are exactly what we want. And for the following reason(arch/x86/kernel/ftrace.c): * Modifying code must take extra care. On an SMP machine, if * the code being modified is also being executed on another CPU * that CPU will have undefined results and possibly take a GPF. * We use kstop_machine to stop other CPUS from exectuing code. In SMP, the code modification are protected by stop_machine(), which will disables the irqs of all cpus and then modify the code, flush the icache. In MIPS SMP, to tell the other cpus to flush their related icache, the IPI interrupt must be sent to them and wait for them exiting from the icache flushing, but for the stop_machine() have disabled interrupts, it will need to wait for the other cpus all the time, then deadlock -> hang. (Note: cavium is an exception, benefit from its synci instruction, it doesn't call smp_call_function() to execute the icache flushing operation but send the ICACHE_FLUSH ipi to the other cpus directly, so, no wait and no hang on cavium, and after the irqs of the cpus are enabled, the pending icache flush interrupt will be filed and synci will flush the icache on every cpu respectively, so, no cache problem). To break this deadlock, the key is: stop calling flush_icache_range() in stop_machine() but delay it after stop_machine(). delaying the icache flushing operation doesn't influence the tracing results even if the other cpus execute the code just modified before the icache flushing, for the kernel tracing will only be enabled after users issuing: $ echo 1 > /path/to/tracing/tracing_enabled Thanks to the weak functions: ftrace_arch_code_modify_prepare() and ftrace_arch_code_modify_post_process(). they are called by ftrace_run_update_code() before and after stop_machine() respectively, with them, ftrace_modify_code() can check whether it is called in stop_machine() and if called in stop_machine(), then delay the operation of icache flushing, as a result, the deadlock is broken. Without this patch, Ftrace for RMI XLS will hang after issuing the following command: $ echo function > /path/to/tracing/current_tracer Exactly, it hangs on kernel/smp.c: void smp_call_function_many(const struct cpumask *mask, { [snip] /* * Can deadlock when called with interrupts disabled. * We allow cpu's that are not yet online though, as no one else can * send smp call function interrupt to this cpu and as such deadlocks * can't happen. */ WARN_ON_ONCE(cpu_online(this_cpu) && irqs_disabled() && !oops_in_progress); [snip] csd_lock(&data->csd); [snip] /* Send a message to all CPUs in the map */ arch_send_call_function_ipi_mask(data->cpumask); /* Optionally wait for the CPUs to complete */ if (wait) csd_lock_wait(&data->csd); --> hang here } Signed-off-by: Wu Zhangjin --- arch/mips/kernel/ftrace.c | 22 +++++++++++++++++++++- 1 files changed, 21 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 5a84a1f..c8ebb13 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -69,6 +69,23 @@ static inline void ftrace_dyn_arch_init_insns(void) #endif } +#ifdef CONFIG_SMP +static int machine_stopped __read_mostly; + +int ftrace_arch_code_modify_prepare(void) +{ + machine_stopped = 1; + return 0; +} + +int ftrace_arch_code_modify_post_process(void) +{ + __flush_cache_all(); + machine_stopped = 0; + return 0; +} +#endif + static int ftrace_modify_code(unsigned long ip, unsigned int new_code) { int faulted; @@ -79,7 +96,10 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) if (unlikely(faulted)) return -EFAULT; - flush_icache_range(ip, ip + 8); +#ifdef CONFIG_SMP + if (!machine_stopped) +#endif + flush_icache_range(ip, ip + 8); return 0; } -- 1.7.0.4 From wuzhangjin@gmail.com Tue Aug 24 08:26:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Aug 2010 08:26:08 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:34415 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490973Ab0HXG0D (ORCPT ); Tue, 24 Aug 2010 08:26:03 +0200 Received: by wwi14 with SMTP id 14so1171287wwi.24 for ; Mon, 23 Aug 2010 23:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=UXb92lB5PraWP/oM9BkY0W1Gb7n9cN9lm1NW/qsvvc4=; b=eDv+oQ2H3EKvy216mGUBaK496e/9rd+YLHb36pp7kB3KptWa5S0CCGYsUnGTTc1mAC 6z1ApikFkqx+Y7EeqzoVKbIz3YKrgAGo/S0dpQQFxqfualjJX8KIZ6SHKUbPvYxVHv6r QLsUJb4Md/2Dv7ul6p0/w6rrbUzUDM+A6Moro= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=Kzg+QwSsvGLBX+/gJC5PVtCFBZjA8XENSs7PtMNo6AKj1lv8g8FfFVQ2yAewUbJbNn NWZvQTucErwmsQpNJ5kCWqcwQ5VjilsZD6SxXQgMIdQTUkjNY5a5H7erNtW89NQybTf0 T4JqfGlvh+v8J9dPbSzqi7oGiongYNqALb98U= MIME-Version: 1.0 Received: by 10.216.186.207 with SMTP id w57mr368068wem.19.1282631157889; Mon, 23 Aug 2010 23:25:57 -0700 (PDT) Received: by 10.216.166.69 with HTTP; Mon, 23 Aug 2010 23:25:57 -0700 (PDT) In-Reply-To: <4C72B16B.5000101@caviumnetworks.com> References: <4C72B16B.5000101@caviumnetworks.com> Date: Tue, 24 Aug 2010 14:25:57 +0800 Message-ID: Subject: Re: Ftrace for MIPS may hang on SMP system From: wu zhangjin To: David Daney Cc: Ralf Baechle , Steven Rostedt , linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27669 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On 8/24/10, David Daney wrote: > Can you send a real patch with your proposed complete fix and proper > Signed-off-by: header? > > I would like to test it. > > Also as a point of reference, I have been using ftrace on 16 way SMP > mips64 systems without seeing this issue. Yes, even without this patch, it works well on cavium, the reason is cavium doesn't use smp_call_function() to send the ipi interrupts, but just send the ipi with octeon_send_ipi_single(): flush_icache_range = octeon_flush_icache_range; /** * Flush a range of kernel addresses out of the icache * */ static void octeon_flush_icache_range(unsigned long start, unsigned long end) { octeon_flush_icache_all_cores(NULL); } octeon_flush_icache_all_cores { [snip] for_each_cpu_mask(cpu, mask) octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); [snip] } static irqreturn_t mailbox_interrupt(int irq, void *dev_id) { [snip] if (action & SMP_CALL_FUNCTION) smp_call_function_interrupt(); /* Check if we've been told to flush the icache */ if (action & SMP_ICACHE_FLUSH) asm volatile ("synci 0($0)\n"); return IRQ_HANDLED; } When the irqs of the cpus are disabled by stop_machine(), the icache of the other cpus will not be flushed till the irqs are enabled, but it is okay for the synci of cavium will flush the whole local icache after the pending ipi is filed: static inline void octeon_local_flush_icache(void) { asm volatile ("synci 0($0)"); } But for RMI XSL, flush_icache_range() will flush the indicated address via the cache instruction, it doesn't flush the whole local icache, so, if too many cache requests are sent to the other cpus, only the icaches of the latest addresses will be flushed after the irqs are enabled, and in RMI XSL, it use the smp_call_function() to send the ipi to the other cpus, if the irqs of the cpus are disabled, there will be deadlock for smp_call_function_many() called by smp_call_function() will wait for the other cpus. So, this patch is necessary to fix the deadlock and icache problem on RMI XLS and it will also improve the performance via reducing the unnecessary ipi interrupt on RML XLS and Cavium. Thanks & Regards, Wu Zhangjin > > David Daney > > On 08/23/2010 07:16 AM, wu zhangjin wrote: >> On 8/23/10, wu zhangjin wrote: >>> Hi, >>> >>> To avoid touching the other parts, I have used the following method: >>> >>> delay the cache flushing operation after the stop_machine(). >>> >>> Here is the patch: >>> >>> diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c >>> index 5a84a1f..f4c9581 100644 >>> --- a/arch/mips/kernel/ftrace.c >>> +++ b/arch/mips/kernel/ftrace.c >>> @@ -33,6 +33,25 @@ static inline int in_module(unsigned long ip) >>> return ip& 0x40000000; >>> } >>> >>> +#ifdef CONFIG_SMP >>> +static bool machine_stopped; >>> + >>> +int ftrace_arch_code_modify_prepare(void) >>> +{ >>> + preempt_disable(); >> >> preempt_disable() is not necessary, and it may introduce the warning >> about "scheduling in atomic()" >> >> Regards, >> Wu Zhangjin >> >>> + machine_stopped = 1; >>> + return 0; >>> +} >>> + >>> +int ftrace_arch_code_modify_post_process(void) >>> +{ >>> + __flush_cache_all(); >>> + machine_stopped = 0; >>> + preempt_enable(); >>> + return 0; >>> +} >>> +#endif >>> + >>> #ifdef CONFIG_DYNAMIC_FTRACE >>> >>> #define JAL 0x0c000000 /* jump& link: ip --> ra, jump to >>> target >>> */ >>> @@ -79,7 +98,12 @@ static int ftrace_modify_code(unsigned long ip, >>> unsigned int new_code) >>> if (unlikely(faulted)) >>> return -EFAULT; >>> >>> - flush_icache_range(ip, ip + 8); >>> +#ifndef CONFIG_SMP >>> + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); >>> +#else >>> + if (!machine_stopped) >>> + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); >>> +#endif >>> >>> return 0; >>> } >>> >>> >>> Regards, >>> Wu Zhangjin >>> >>> On 8/22/10, wu zhangjin wrote: >>>> On 8/22/10, wu zhangjin wrote: >>>>> (Add 'another' Steven in this loop) >>>>> >>>>> On 8/22/10, wu zhangjin wrote: >>>>>> Hi, all >>>>>> >>>>>> For I didn't have a SMP machine, I haven't used Ftrace(in 2.6.34) for >>>>>> MIPS on SMP system before, Yesterday, I got a RMI XLS machine and >>>>>> found Ftrace for MIPS hanged on it after I issued: >>>>>> >>>>>> $ echo function> /debug/tracing/current_tracer >>>>>> >>>>>> I have gotten the root cause, that is: >>>>>> >>>>>> in kernel/trace/ftrace.c: >>>>>> >>>>>> stop_machine() disables the irqs of the other cpus and then modify the >>>>>> codes via calling the arch specific ftrace_modify_code() in >>>>>> __ftrace_modify_code(). >>>>>> >>>>>> As the description about stop_machine() in arch/x86/kernel/ftrace.c >>>>>> shows: >>>>>> >>>>>> /* >>>>>> * Modifying code must take extra care. On an SMP machine, if >>>>>> * the code being modified is also being executed on another CPU >>>>>> * that CPU will have undefined results and possibly take a GPF. >>>>>> * We use kstop_machine to stop other CPUS from exectuing code. >>>>>> [snip] >>>>>> >>>>>> Then, it is reasonable to use stop_machine() here. >>>>>> >>>>>> And in arch/mips/kernel/ftrace.c: >>>>>> >>>>>> flush_icache_range() is called in ftrace_modify_code() to ensure the >>>>>> intructions will be executed are what we want. >>>>>> >>>>>> In UP system, there is no problem for flush_icache_range() simply >>>>>> flush the instruction cache, but In SMP system, this may be different, >>>>>> for flush_icache_range() may also need to ask the other cpus (via >>>>>> sending ipi interrupt) to flush their icaches and will wait for them >>>>>> till the other cpus finish their flushing. >>>>>> >>>>>> But as we know above, the irqs of the other cpus are disabled by >>>>>> stop_machine(), they have no opportunity to flush their icache and >>>>>> will let the current cpu wait for them all the time, then soft lock >>>>>> --> hang. >>>>>> >>>>>> To fix it, there are two potential solutions: >>>>>> >>>>>> 1. replace flush_icache_range() by something else, maybe we can use >>>>>> the similar method in arch/x86/kernel/ftrace.c, x86 uses sync_core() >>>>>> defined in arch/x86/include/asm/processor.h to flush the icache on all >>>>>> processors: >>>>>> >>>>>> /* Stop speculative execution and prefetching of modified code. */ >>>>>> static inline void sync_core(void) >>>>>> { >>>>>> int tmp; >>>>>> >>>>>> #if defined(CONFIG_M386) || defined(CONFIG_M486) >>>>>> if (boot_cpu_data.x86< 5) >>>>>> /* There is no speculative execution. >>>>>> * jmp is a barrier to prefetching. */ >>>>>> asm volatile("jmp 1f\n1:\n" ::: "memory"); >>>>>> else >>>>>> #endif >>>>>> /* cpuid is a barrier to speculative execution. >>>>>> * Prefetched instructions are automatically >>>>>> * invalidated when modified. */ >>>>>> asm volatile("cpuid" : "=a" (tmp) : "0" (1) >>>>>> : "ebx", "ecx", "edx", "memory"); >>>>>> } >>>>>> >>>>>> But is there a cpuid like hardware instruction in MIPS SMP? As I know, >>>>>> in UP, we may be possible to use prefetch instruction to push the >>>>>> instruction to the cache, but in SMP, is there a instruction to force >>>>>> the other cpus to flush their cache too? >>>>>> >>>>>> 2. Replace the stop_machine() by something else >>>>>> >>>>>> I have written such a patch: >>>>>> >>>>>> diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c >>>>>> index 2404b59..e4d058f 100644 >>>>>> --- a/kernel/trace/ftrace.c >>>>>> +++ b/kernel/trace/ftrace.c >>>>>> @@ -1129,13 +1129,18 @@ static int __ftrace_modify_code(void *data) >>>>>> static void ftrace_run_update_code(int command) >>>>>> { >>>>>> int ret; >>>>>> + unsigned long flags; >>>>>> >>>>>> ret = ftrace_arch_code_modify_prepare(); >>>>>> FTRACE_WARN_ON(ret); >>>>>> if (ret) >>>>>> return; >>>>>> >>>>>> - stop_machine(__ftrace_modify_code,&command, NULL); >>>>>> + preempt_disable(); >>>>>> + local_irq_save(flags); >>>>>> + __ftrace_modify_code(&command); >>>>>> + local_irq_restore(flags); >>>>>> + preempt_enable(); >>>>>> >>>>>> ret = ftrace_arch_code_modify_post_process(); >>>>>> FTRACE_WARN_ON(ret); >>>>>> >>>> >>>> We may need to protect the __ftrace_modify_code() with raw spin lock. >>>> >>>>>> It works without any hang but I'm not sure whether it will guarantee >>>>>> the "undefined results" problem mentioned above. Here we may need to >>>>>> prevent the other cpus from executing the source code for we are >>>>>> modifying the source code but also need to allow them to get the ipi >>>>>> interrupt and flush their icaches. >>>>>> >>>>>> And I have took a look at the part of code modification in kgdb >>>>>> system, seems it doesn't use stop_machine(). >>>>>> >>>>>> What's your ideas? >>>>>> >>>>>> Thanks& Regards, >>>>>> Wu Zhangjin >>> >> >> > > -- MSN+Gtalk: wuzhangjin@gmail.com Blog: http://falcon.oss.lzu.edu.cn Tel:+86-18710032278 From David.Daney@caviumnetworks.com Wed Aug 25 22:28:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 25 Aug 2010 22:28:49 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17981 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491015Ab0HYU2p (ORCPT ); Wed, 25 Aug 2010 22:28:45 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 25 Aug 2010 13:29:13 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 25 Aug 2010 13:28:41 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 25 Aug 2010 13:28:41 -0700 Message-ID: <4C757CF4.6010304@caviumnetworks.com> Date: Wed, 25 Aug 2010 13:28:36 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: jiang.adam@gmail.com CC: ralf@linux-mips.org, dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: irq: add statckoverflow detection References: <1282372293-30211-1-git-send-email-jiang.adam@gmail.com> In-Reply-To: <1282372293-30211-1-git-send-email-jiang.adam@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 25 Aug 2010 20:28:41.0754 (UTC) FILETIME=[1B81EFA0:01CB4494] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27670 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips It looks like this patch only checks when processing an interrupt, which doesn't seem like it would give much coverage. Am I missing something? David Daney On 08/20/2010 11:31 PM, jiang.adam@gmail.com wrote: > From: Adam Jiang > > Add stackoverflow detection to mips arch > > Signed-off-by: Adam Jiang > --- > arch/mips/Kconfig.debug | 7 +++++++ > arch/mips/kernel/irq.c | 19 +++++++++++++++++++ > 2 files changed, 26 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > index 43dc279..f1a00a2 100644 > --- a/arch/mips/Kconfig.debug > +++ b/arch/mips/Kconfig.debug > @@ -67,6 +67,13 @@ config CMDLINE_OVERRIDE > > Normally, you will choose 'N' here. > > +config DEBUG_STACKOVERFLOW > + bool "Check for stack overflows" > + depends on DEBUG_KERNEL > + help > + This option will cause messages to be printed if free stack space > + drops below a certain limit. > + > config DEBUG_STACK_USAGE > bool "Enable stack utilization instrumentation" > depends on DEBUG_KERNEL > diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c > index c6345f5..6334037 100644 > --- a/arch/mips/kernel/irq.c > +++ b/arch/mips/kernel/irq.c > @@ -151,6 +151,22 @@ void __init init_IRQ(void) > #endif > } > > +static inline void check_stack_overflow(void) > +{ > +#ifdef CONFIG_DEBUG_STACKOVERFLOW > + long sp; > + > + asm volatile("move %0, $sp" : "=r" (sp)); > + sp = sp& (THREAD_SIZE-1); > + > + /* check for stack overflow: is there less then 2KB free? */ > + if (unlikely(sp< (sizeof(struct thread_info) + 2048))) { > + printk("do_IRQ: stack overflow: %ld\n", > + sp - sizeof(struct thread_info)); > + dump_stack(); > + } > +#endif > +} > /* > * do_IRQ handles all normal device IRQ's (the special > * SMP cross-CPU interrupts have their own specific > @@ -159,6 +175,9 @@ void __init init_IRQ(void) > void __irq_entry do_IRQ(unsigned int irq) > { > irq_enter(); > + > + check_stack_overflow(); > + > __DO_IRQ_SMTC_HOOK(irq); > generic_handle_irq(irq); > irq_exit(); From jiang.adam@gmail.com Thu Aug 26 05:56:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Aug 2010 05:56:23 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:35058 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491101Ab0HZD4T (ORCPT ); Thu, 26 Aug 2010 05:56:19 +0200 Received: by pxi4 with SMTP id 4so553476pxi.36 for ; Wed, 25 Aug 2010 20:56:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=v1NZ4NZf+pmDUUi3/wkmNhxq8OH7//3BGA3cBNzmDU4=; b=Ti/bqr/oBY3GyHG4nnscGDGZyCXdkr/gP6+uMoilWjRHxxBl93HWUVQo8M3zAJdy1T 46SAVvW6R3kkus3Uv6uaYzrdGTP1scf8yhhqaFdrwAGkDDr+Z8xHsu64kY0hbWxPrhsU qBVr42nfhGpfGVLILeJX98PFA0qDf1IWmEZRE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=VsmsUhVZUWdIIDC7Ij46Z1L9BX97IXhr4J+zAbB74GsSddyRElTyqLw1DXqc/lZ26X oLzCb1LQDPpTz+Sr8aI9i3dbxOjIXlq5Q+zVm5TqiH3krS81mXMjVeGLN9GAoL+iM89Q JavGEPnULANToNHigBiDqJocl5j4m2AO1DkDw= Received: by 10.142.127.16 with SMTP id z16mr7744416wfc.50.1282794966066; Wed, 25 Aug 2010 20:56:06 -0700 (PDT) Received: from localhost (KD113150081245.ppp-bb.dion.ne.jp [113.150.81.245]) by mx.google.com with ESMTPS id d4sm2366318wfh.23.2010.08.25.20.56.02 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 25 Aug 2010 20:56:04 -0700 (PDT) From: Adam Jiang To: ralf@linux-mips.org Cc: dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Adam Jiang Subject: [PATCH 3/3] mips: irq: add stackoverflow detection Date: Thu, 26 Aug 2010 12:55:33 +0900 Message-Id: <1282794933-20639-1-git-send-email-jiang.adam@gmail.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27671 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jiang.adam@gmail.com Precedence: bulk X-list: linux-mips Add stackoverflow detection to mips arch --- arch/mips/Kconfig.debug | 7 +++++++ arch/mips/kernel/irq.c | 22 ++++++++++++++++++++++ 2 files changed, 29 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 43dc279..30c58d4 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -67,6 +67,13 @@ config CMDLINE_OVERRIDE Normally, you will choose 'N' here. +config DEBUG_STACKOVERFLOW + bool "Check for stack overflows" + depends on DEBUG_KERNEL + help + This option will cause messages to be printed if free stack + space drops below a certain limit. + config DEBUG_STACK_USAGE bool "Enable stack utilization instrumentation" depends on DEBUG_KERNEL diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index c6345f5..75c584d 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -151,6 +151,25 @@ void __init init_IRQ(void) #endif } +#ifdef CONFIG_DEBUG_STACKOVERFLOW +static inline void check_stack_overflow(void) +{ + long sp; + + asm volatile("move %0, $sp" : "=r" (sp)); + sp = sp & (THREAD_SIZE-1); + + /* check for stack overflow: is there less than 2KB free? */ + if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { + printk("do_IRQ: stack overflow: %ld\n", + sp - sizeof(struct thread_info)); + dump_stack(); + } +} +#else +static inline void check_stack_overflow(void) +#endif + /* * do_IRQ handles all normal device IRQ's (the special * SMP cross-CPU interrupts have their own specific @@ -159,6 +178,9 @@ void __init init_IRQ(void) void __irq_entry do_IRQ(unsigned int irq) { irq_enter(); + + check_stack_overflow(); + __DO_IRQ_SMTC_HOOK(irq); generic_handle_irq(irq); irq_exit(); -- 1.7.0.4 From sshtylyov@mvista.com Thu Aug 26 10:29:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Aug 2010 10:29:13 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:33937 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491180Ab0HZI3J (ORCPT ); Thu, 26 Aug 2010 10:29:09 +0200 Received: by ewy9 with SMTP id 9so1222129ewy.36 for ; Thu, 26 Aug 2010 01:29:08 -0700 (PDT) Received: by 10.213.105.79 with SMTP id s15mr402439ebo.48.1282811347904; Thu, 26 Aug 2010 01:29:07 -0700 (PDT) Received: from [192.168.2.2] ([91.79.54.121]) by mx.google.com with ESMTPS id v8sm3651031eeh.2.2010.08.26.01.29.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 26 Aug 2010 01:29:06 -0700 (PDT) Message-ID: <4C762572.4070509@mvista.com> Date: Thu, 26 Aug 2010 12:27:30 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 To: Adam Jiang CC: ralf@linux-mips.org, dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] mips: irq: add stackoverflow detection References: <1282794933-20639-1-git-send-email-jiang.adam@gmail.com> In-Reply-To: <1282794933-20639-1-git-send-email-jiang.adam@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27672 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Adam Jiang wrote: > Add stackoverflow detection to mips arch [...] > diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c > index c6345f5..75c584d 100644 > --- a/arch/mips/kernel/irq.c > +++ b/arch/mips/kernel/irq.c > @@ -151,6 +151,25 @@ void __init init_IRQ(void) > #endif > } > > +#ifdef CONFIG_DEBUG_STACKOVERFLOW > +static inline void check_stack_overflow(void) > +{ > + long sp; > + > + asm volatile("move %0, $sp" : "=r" (sp)); > + sp = sp & (THREAD_SIZE-1); > + > + /* check for stack overflow: is there less than 2KB free? */ > + if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { > + printk("do_IRQ: stack overflow: %ld\n", > + sp - sizeof(struct thread_info)); > + dump_stack(); > + } > +} > +#else > +static inline void check_stack_overflow(void) You didn't even try to compile with the option disabled -- you've missed {}. > +#endif > + > /* > * do_IRQ handles all normal device IRQ's (the special > * SMP cross-CPU interrupts have their own specific WBR, Sergei From jiang.adam@gmail.com Thu Aug 26 15:15:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Aug 2010 15:15:27 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:60124 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491766Ab0HZNPU convert rfc822-to-8bit (ORCPT ); Thu, 26 Aug 2010 15:15:20 +0200 Received: by wyb38 with SMTP id 38so556860wyb.36 for ; Thu, 26 Aug 2010 06:15:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=zoX8MdZ/so0VKsB3Jcl2bnsX3hxT8ku6pPTYucE5yiY=; b=R2lMRz6FdyH2Udyo1n89LILWg3tYU9iX4S/y6YD49liZYh/8Fbem8O71wcXMxjtuni T+nM7p/M/0bIuw0ibgku9nFz2S7W//8GEJ5LPatrJQCS9z1Sjd+f6parPuQy8mwWh35A wngus+83QXGim4TacyfGtBZ2pVc2RQe5DRgco= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Lga4Kgptqq5xIJNa/RTwJAkiC+qBIFUGcMwU4blixHn9lVf63YADaxJqF3x7HtQ6JE t5CWog7SSEOhLhozwoa7bgzOqOntNmS8cy1/HJvRZDc8QRnLaixypqZ4Y3w2ijLa/WEv shenuGqLlHWYzbbqzRFNRvpUo59RYP2lS68oA= MIME-Version: 1.0 Received: by 10.227.138.76 with SMTP id z12mr9013603wbt.60.1282828509701; Thu, 26 Aug 2010 06:15:09 -0700 (PDT) Received: by 10.227.133.194 with HTTP; Thu, 26 Aug 2010 06:15:09 -0700 (PDT) In-Reply-To: <4C762572.4070509@mvista.com> References: <1282794933-20639-1-git-send-email-jiang.adam@gmail.com> <4C762572.4070509@mvista.com> Date: Thu, 26 Aug 2010 22:15:09 +0900 Message-ID: Subject: Re: [PATCH 3/3] mips: irq: add stackoverflow detection From: Adam Jiang To: Sergei Shtylyov Cc: ralf@linux-mips.org, dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27673 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jiang.adam@gmail.com Precedence: bulk X-list: linux-mips 2010/8/26 Sergei Shtylyov : > Hello. > > Adam Jiang wrote: > >> Add stackoverflow detection to mips arch > > [...] > >> diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c >> index c6345f5..75c584d 100644 >> --- a/arch/mips/kernel/irq.c >> +++ b/arch/mips/kernel/irq.c >> @@ -151,6 +151,25 @@ void __init init_IRQ(void) >>  #endif >>  } >>  +#ifdef CONFIG_DEBUG_STACKOVERFLOW >> +static inline void check_stack_overflow(void) >> +{ >> +       long sp; >> + >> +       asm volatile("move %0, $sp" : "=r" (sp)); >> +       sp = sp & (THREAD_SIZE-1); >> + >> +       /* check for stack overflow: is there less than 2KB free? */ >> +       if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { >> +               printk("do_IRQ: stack overflow: %ld\n", >> +                      sp - sizeof(struct thread_info)); >> +               dump_stack(); >> +       } >> +} >> +#else >> +static inline void check_stack_overflow(void) > >   You didn't even try to compile with the option disabled -- you've missed > {}. Thank your, Sergei. This is my first patch. I realized I have to learn much to summit a good patch. And yes, I have to pay more attention on my code. Anyway, I will try to get a good patch and send it here again. /Adam > >> +#endif >> + >>  /* >>  * do_IRQ handles all normal device IRQ's (the special >>  * SMP cross-CPU interrupts have their own specific > > WBR, Sergei > From jiang.adam@gmail.com Thu Aug 26 15:16:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Aug 2010 15:16:52 +0200 (CEST) Received: from mail-pz0-f49.google.com ([209.85.210.49]:56931 "EHLO mail-pz0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491766Ab0HZNQq (ORCPT ); Thu, 26 Aug 2010 15:16:46 +0200 Received: by pzk3 with SMTP id 3so715790pzk.36 for ; Thu, 26 Aug 2010 06:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=7n52Hu7UghW3rAB/uOaoB2AhgfEZemHKA8QHL1KrJPk=; b=lY0LTNWbEc32hOzwPMY7fa/Wfe1HALCFGl3sw7rW91mdzQTOgUj/OUGCFLPXmqnMcy ssCTdoKJ4zUQ4Xa7ar1gvGowia0HchDDZIMRDKZyDltv7VwHVmWH64WPQxnxlrEZ/w0g oIIH5Hsjk/SKBDY89bU0rW++8YOnaJCfsB4CU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=vlKvj+fX3w+8ask1jk/7sTORUHMXla+c5Y5lRF/NKvKZ1euSz3y8RlyJV9cY4ZEaTP WAasNVlEVt7bf/cuZbDOMjohjn5XSgAyRL0sb14InW41qn2UoCpX3h9kEJWVeg8Tp1gS wTIijIJ1ilwvcrT//k9QCdhzHKbjsgltMgckI= Received: by 10.142.187.6 with SMTP id k6mr8411776wff.3.1282828597144; Thu, 26 Aug 2010 06:16:37 -0700 (PDT) Received: from localhost (KD118154228076.ppp-bb.dion.ne.jp [118.154.228.76]) by mx.google.com with ESMTPS id z1sm2970169wfd.3.2010.08.26.06.16.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 26 Aug 2010 06:16:36 -0700 (PDT) From: Adam Jiang To: ralf@linux-mips.org Cc: dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Adam Jiang Subject: [PATCH] mips: irq: add stackoverflow detection Date: Thu, 26 Aug 2010 22:19:15 +0900 Message-Id: <1282828755-11953-1-git-send-email-jiang.adam@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27674 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jiang.adam@gmail.com Precedence: bulk X-list: linux-mips Add stackoverflow detection to mips arch --- arch/mips/Kconfig.debug | 7 +++++++ arch/mips/kernel/irq.c | 19 +++++++++++++++++++ 2 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 43dc279..f1a00a2 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -67,6 +67,13 @@ config CMDLINE_OVERRIDE Normally, you will choose 'N' here. +config DEBUG_STACKOVERFLOW + bool "Check for stack overflows" + depends on DEBUG_KERNEL + help + This option will cause messages to be printed if free stack space + drops below a certain limit. + config DEBUG_STACK_USAGE bool "Enable stack utilization instrumentation" depends on DEBUG_KERNEL diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index c6345f5..8fdf79e 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -151,6 +151,25 @@ void __init init_IRQ(void) #endif } +#ifdef DEBUG_STACKOVERFLOW +static inline void check_stack_overflow(void) +{ + long sp; + + asm volatile("move %0, $sp" : "=r" (sp)); + sp = sp & (THREAD_SIZE-1); + + /* check for stack overflow: is there less than 2KB free? */ + if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { + printk("do_IRQ: stack overflow: %ld\n", + sp - sizeof(struct thread_info)); + dump_stack(); + } +} +#else +static inline void check_stack_overflow(void) {} +#endif + /* * do_IRQ handles all normal device IRQ's (the special * SMP cross-CPU interrupts have their own specific -- 1.7.1 From manuel.lauss@googlemail.com Thu Aug 26 16:00:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Aug 2010 16:01:00 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:56131 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490967Ab0HZOA5 (ORCPT ); Thu, 26 Aug 2010 16:00:57 +0200 Received: by bwz13 with SMTP id 13so1368199bwz.36 for ; Thu, 26 Aug 2010 07:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=W1cy3JixoOfa3CoG6f3dyj04WVClLI0/gEZFNE3JsJ8=; b=LyKlkK3gWP+mQjQCQWrHzSCtW8a13cUkUgmd5L65mcOl8iXA7OjlARDISnTmWFJhir vWTBqbH94d7Fo7MDoQJL1ZJ/Fyo0DvKfu5IEmSo3MevCWtZI7q6ahahHqGYmhQ1NTNYi miTfAhrY1/V92ljvaFMWylGWDlLozLVXk0kSE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=xgoVd2iMtg1iSsIEUcsh3eZ755+011P3swtQwxRqniK67jLA3fkx7pPicWLFHHpiln PuNjRwE9R+QpxE/wU0/CNqCNkp86lh36ec2gmz3AXnWDXBfXovtW8lOeKnZm9+cPugvE Ja50KpcsZpB1Dlc1liDJlo0b5ywkaSfj5UuEc= Received: by 10.204.52.12 with SMTP id f12mr6169041bkg.212.1282831256097; Thu, 26 Aug 2010 07:00:56 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id s34sm1679797bkk.1.2010.08.26.07.00.54 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 26 Aug 2010 07:00:55 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: update inlinable GPIO API Date: Thu, 26 Aug 2010 16:00:50 +0200 Message-Id: <1282831250-1448-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27675 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The GPIO API has grown a few new functions, add the missing ones to the other inlinables (CONFIG_GPIOLIB=n) Signed-off-by: Manuel Lauss --- gpio_keys is one user of gpio_set_debounce() for example. arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 35 +++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 62d2f13..f26bfe7 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -556,6 +556,16 @@ static inline void gpio_set_value(int gpio, int v) alchemy_gpio_set_value(gpio, v); } +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + static inline int gpio_is_valid(int gpio) { return alchemy_gpio_is_valid(gpio); @@ -585,6 +595,31 @@ static inline void gpio_free(unsigned gpio) { } +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ -- 1.7.2 From David.Daney@caviumnetworks.com Thu Aug 26 18:21:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Aug 2010 18:21:55 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13685 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490967Ab0HZQVs (ORCPT ); Thu, 26 Aug 2010 18:21:48 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 26 Aug 2010 09:22:16 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 26 Aug 2010 09:21:44 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 26 Aug 2010 09:21:44 -0700 Message-ID: <4C769498.9020004@caviumnetworks.com> Date: Thu, 26 Aug 2010 09:21:44 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100720 Fedora/3.0.6-1.fc12 Thunderbird/3.0.6 MIME-Version: 1.0 To: Adam Jiang , linux-mips Subject: Re: [PATCH] mips: irq: add statckoverflow detection References: <1282372293-30211-1-git-send-email-jiang.adam@gmail.com> <4C757CF4.6010304@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 26 Aug 2010 16:21:44.0477 (UTC) FILETIME=[C622A4D0:01CB453A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27676 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 08/25/2010 06:12 PM, Adam Jiang wrote: > 2010/8/26 David Daney: >> It looks like this patch only checks when processing an interrupt, which >> doesn't seem like it would give much coverage. > > Yes, it is. This is only for detection on the situation which may be > caused by nested interruption. No more coverage to any other cases. > Because to do that is much difficult and unpredicted. > Well, since the default is to run interrupt handlers with interrupts disabled, it seems like it is of little use as you will almost never see nested interrupts. A solution that shows overflow in all situations would be of more use. Something that could use GCC's -stack-check or related machinery might be interesting. David Daney > I will revise the bad code style Sergei blamed. > > /Adam > >> >> Am I missing something? >> >> David Daney >> >> >> On 08/20/2010 11:31 PM, jiang.adam@gmail.com wrote: >>> >>> From: Adam Jiang >>> >>> Add stackoverflow detection to mips arch >>> >>> Signed-off-by: Adam Jiang >>> --- >>> arch/mips/Kconfig.debug | 7 +++++++ >>> arch/mips/kernel/irq.c | 19 +++++++++++++++++++ >>> 2 files changed, 26 insertions(+), 0 deletions(-) >>> >>> diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug >>> index 43dc279..f1a00a2 100644 >>> --- a/arch/mips/Kconfig.debug >>> +++ b/arch/mips/Kconfig.debug >>> @@ -67,6 +67,13 @@ config CMDLINE_OVERRIDE >>> >>> Normally, you will choose 'N' here. >>> >>> +config DEBUG_STACKOVERFLOW >>> + bool "Check for stack overflows" >>> + depends on DEBUG_KERNEL >>> + help >>> + This option will cause messages to be printed if free stack >>> space >>> + drops below a certain limit. >>> + >>> config DEBUG_STACK_USAGE >>> bool "Enable stack utilization instrumentation" >>> depends on DEBUG_KERNEL >>> diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c >>> index c6345f5..6334037 100644 >>> --- a/arch/mips/kernel/irq.c >>> +++ b/arch/mips/kernel/irq.c >>> @@ -151,6 +151,22 @@ void __init init_IRQ(void) >>> #endif >>> } >>> >>> +static inline void check_stack_overflow(void) >>> +{ >>> +#ifdef CONFIG_DEBUG_STACKOVERFLOW >>> + long sp; >>> + >>> + asm volatile("move %0, $sp" : "=r" (sp)); >>> + sp = sp& (THREAD_SIZE-1); >>> + >>> + /* check for stack overflow: is there less then 2KB free? */ >>> + if (unlikely(sp< (sizeof(struct thread_info) + 2048))) { >>> + printk("do_IRQ: stack overflow: %ld\n", >>> + sp - sizeof(struct thread_info)); >>> + dump_stack(); >>> + } >>> +#endif >>> +} >>> /* >>> * do_IRQ handles all normal device IRQ's (the special >>> * SMP cross-CPU interrupts have their own specific >>> @@ -159,6 +175,9 @@ void __init init_IRQ(void) >>> void __irq_entry do_IRQ(unsigned int irq) >>> { >>> irq_enter(); >>> + >>> + check_stack_overflow(); >>> + >>> __DO_IRQ_SMTC_HOOK(irq); >>> generic_handle_irq(irq); >>> irq_exit(); >> >> From Andrei.Ardelean@idt.com Thu Aug 26 18:22:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Aug 2010 18:23:04 +0200 (CEST) Received: from mxout1.idt.com ([157.165.5.25]:38263 "EHLO mxout1.idt.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490967Ab0HZQW5 convert rfc822-to-8bit (ORCPT ); Thu, 26 Aug 2010 18:22:57 +0200 Received: from mail.idt.com (localhost [127.0.0.1]) by mxout1.idt.com (8.13.1/8.13.1) with ESMTP id o7QGMowp023432 for ; Thu, 26 Aug 2010 09:22:50 -0700 Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.8/8.13.8) with ESMTP id o7QGMnCe009712 for ; Thu, 26 Aug 2010 09:22:49 -0700 (PDT) Received: from CORPEXCH1.na.ads.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id o7QGMnT01094 for ; Thu, 26 Aug 2010 09:22:49 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Does Linux Mips support compressed Kernel? Date: Thu, 26 Aug 2010 09:22:46 -0700 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: thread-topic: Does Linux Mips support compressed Kernel? thread-index: ActFOus4yLHrNbh4Rfaz/kEHw5h8fw== From: "Ardelean, Andrei" To: X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27677 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Andrei.Ardelean@idt.com Precedence: bulk X-list: linux-mips Hi, Does Linux Mips support compressed Kernel? How can I obtain it? Thanks, Andrei From sshtylyov@mvista.com Thu Aug 26 21:01:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Aug 2010 21:01:45 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:46431 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491773Ab0HZTBi (ORCPT ); Thu, 26 Aug 2010 21:01:38 +0200 Received: by ewy9 with SMTP id 9so1777959ewy.36 for ; Thu, 26 Aug 2010 12:01:37 -0700 (PDT) Received: by 10.213.34.2 with SMTP id j2mr5355676ebd.51.1282849297477; Thu, 26 Aug 2010 12:01:37 -0700 (PDT) Received: from [192.168.11.174] (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id a48sm4545663eei.0.2010.08.26.12.01.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 26 Aug 2010 12:01:36 -0700 (PDT) Message-ID: <4C76B9E1.4080500@mvista.com> Date: Thu, 26 Aug 2010 23:00:49 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Adam Jiang CC: ralf@linux-mips.org, dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mips: irq: add stackoverflow detection References: <1282828755-11953-1-git-send-email-jiang.adam@gmail.com> In-Reply-To: <1282828755-11953-1-git-send-email-jiang.adam@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27678 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Adam Jiang wrote: > Add stackoverflow detection to mips arch [...] > diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c > index c6345f5..8fdf79e 100644 > --- a/arch/mips/kernel/irq.c > +++ b/arch/mips/kernel/irq.c > @@ -151,6 +151,25 @@ void __init init_IRQ(void) > #endif > } > > +#ifdef DEBUG_STACKOVERFLOW > +static inline void check_stack_overflow(void) > +{ > + long sp; > + > + asm volatile("move %0, $sp" : "=r" (sp)); > + sp = sp & (THREAD_SIZE-1); > + > + /* check for stack overflow: is there less than 2KB free? */ > + if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { > + printk("do_IRQ: stack overflow: %ld\n", > + sp - sizeof(struct thread_info)); > + dump_stack(); > + } > +} > +#else > +static inline void check_stack_overflow(void) {} > +#endif > + > /* > * do_IRQ handles all normal device IRQ's (the special > * SMP cross-CPU interrupts have their own specific You've dropped call check_stack_overflow() call in do_IRQ() -- was that intentional? WBR, Sergei From jiang.adam@gmail.com Fri Aug 27 01:40:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Aug 2010 01:40:16 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:36449 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491800Ab0HZXkM (ORCPT ); Fri, 27 Aug 2010 01:40:12 +0200 Received: by pvg12 with SMTP id 12so1001661pvg.36 for ; Thu, 26 Aug 2010 16:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:date:from:to:cc:subject :message-id:references:mime-version:content-type:content-disposition :in-reply-to:user-agent; bh=tBj9qr0GnFIeQPWc1IkxhRKsm2umcUATHyE80aVJXpc=; b=HAr+BFK7UBS6lswOewQ0qIzDgqkbn3Rdj02EIlJ4Dp6brcpFKZj0ddnk6sw7LRKLd5 O2Eh4v3SqS6Wu+brGgZemm4rMtcMVy2WQSD3D7OyLqhxKGu81EluoFS0XsjsharNPzFy ExMM23kK/Bmu282wHnHw0HSAz7bac2Cq187t8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; b=YDNhrlXo7mYMz6jOo3nJ5Vvlf8jZTqWiUCaNU91GxIj4WDjwnebpA5vXdZkt/aFSci IT2eEbf55lPhtQ4128nTUeBnczCxLwhbRNNUzl5jKBlFOLgDKgSfpscJat1jMew1c5Y2 aRLmVrRLYTqLOcKbGTlar4pk7u+CYI/6fFFAc= Received: by 10.142.43.7 with SMTP id q7mr601606wfq.22.1282866005991; Thu, 26 Aug 2010 16:40:05 -0700 (PDT) Received: from localhost (KD118154228076.ppp-bb.dion.ne.jp [118.154.228.76]) by mx.google.com with ESMTPS id x26sm2054054wfd.20.2010.08.26.16.40.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 26 Aug 2010 16:40:04 -0700 (PDT) Date: Fri, 27 Aug 2010 08:42:46 +0900 From: Adam Jiang To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] mips: irq: add statckoverflow detection Message-ID: <20100826234246.GB12367@capricorn-x61> References: <1282372293-30211-1-git-send-email-jiang.adam@gmail.com> <4C757CF4.6010304@caviumnetworks.com> <4C769498.9020004@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C769498.9020004@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27679 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jiang.adam@gmail.com Precedence: bulk X-list: linux-mips On Thu, Aug 26, 2010 at 09:21:44AM -0700, David Daney wrote: > On 08/25/2010 06:12 PM, Adam Jiang wrote: > >2010/8/26 David Daney: > >>It looks like this patch only checks when processing an interrupt, which > >>doesn't seem like it would give much coverage. > > > >Yes, it is. This is only for detection on the situation which may be > >caused by nested interruption. No more coverage to any other cases. > >Because to do that is much difficult and unpredicted. > > > > Well, since the default is to run interrupt handlers with interrupts > disabled, it seems like it is of little use as you will almost never > see nested interrupts. > > A solution that shows overflow in all situations would be of more > use. Something that could use GCC's -stack-check or related > machinery might be interesting. > Yes, you may be right. However, some toolchain has no -stack-check option available. At least, it seems my mispel gcc missed this option. Actually, the issue has been discussed about one month before in mips-linux list. You can see the thread here http://www.spinics.net/lists/mips/msg38198.html I tried to port the same functionality from x86 to mips. This may be another option for checking stackoverflow but not an essential solution. But yes, you are right. Nested interruption never happen unless some really stupid thing. Unfortunately, I have seen such things in a BSP code. I think it is necessary to provide a small function to check it. How do you say? Best regards, /Adam > David Daney > > > >I will revise the bad code style Sergei blamed. > > > >/Adam > > > >> > >>Am I missing something? > >> > >>David Daney > >> > >> > >>On 08/20/2010 11:31 PM, jiang.adam@gmail.com wrote: > >>> > >>>From: Adam Jiang > >>> > >>>Add stackoverflow detection to mips arch > >>> > >>>Signed-off-by: Adam Jiang > >>>--- > >>> arch/mips/Kconfig.debug | 7 +++++++ > >>> arch/mips/kernel/irq.c | 19 +++++++++++++++++++ > >>> 2 files changed, 26 insertions(+), 0 deletions(-) > >>> > >>>diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > >>>index 43dc279..f1a00a2 100644 > >>>--- a/arch/mips/Kconfig.debug > >>>+++ b/arch/mips/Kconfig.debug > >>>@@ -67,6 +67,13 @@ config CMDLINE_OVERRIDE > >>> > >>> Normally, you will choose 'N' here. > >>> > >>>+config DEBUG_STACKOVERFLOW > >>>+ bool "Check for stack overflows" > >>>+ depends on DEBUG_KERNEL > >>>+ help > >>>+ This option will cause messages to be printed if free stack > >>>space > >>>+ drops below a certain limit. > >>>+ > >>> config DEBUG_STACK_USAGE > >>> bool "Enable stack utilization instrumentation" > >>> depends on DEBUG_KERNEL > >>>diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c > >>>index c6345f5..6334037 100644 > >>>--- a/arch/mips/kernel/irq.c > >>>+++ b/arch/mips/kernel/irq.c > >>>@@ -151,6 +151,22 @@ void __init init_IRQ(void) > >>> #endif > >>> } > >>> > >>>+static inline void check_stack_overflow(void) > >>>+{ > >>>+#ifdef CONFIG_DEBUG_STACKOVERFLOW > >>>+ long sp; > >>>+ > >>>+ asm volatile("move %0, $sp" : "=r" (sp)); > >>>+ sp = sp& (THREAD_SIZE-1); > >>>+ > >>>+ /* check for stack overflow: is there less then 2KB free? */ > >>>+ if (unlikely(sp< (sizeof(struct thread_info) + 2048))) { > >>>+ printk("do_IRQ: stack overflow: %ld\n", > >>>+ sp - sizeof(struct thread_info)); > >>>+ dump_stack(); > >>>+ } > >>>+#endif > >>>+} > >>> /* > >>> * do_IRQ handles all normal device IRQ's (the special > >>> * SMP cross-CPU interrupts have their own specific > >>>@@ -159,6 +175,9 @@ void __init init_IRQ(void) > >>> void __irq_entry do_IRQ(unsigned int irq) > >>> { > >>> irq_enter(); > >>>+ > >>>+ check_stack_overflow(); > >>>+ > >>> __DO_IRQ_SMTC_HOOK(irq); > >>> generic_handle_irq(irq); > >>> irq_exit(); > >> > >> > From jiang.adam@gmail.com Fri Aug 27 11:30:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Aug 2010 11:30:19 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:61885 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491809Ab0H0JaN (ORCPT ); Fri, 27 Aug 2010 11:30:13 +0200 Received: by pxi4 with SMTP id 4so1164502pxi.36 for ; Fri, 27 Aug 2010 02:30:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=qsGEjnBSKpml4UIv7ZnA/VEb7qF+OdgxZ6Z8GG+IY3M=; b=Cn33/x+IETh7mOHGPlUDP3J8i+kGrRsrkQgdv0dZPt/z6/V4thEIjrQfRiXfLinarb nIVl2HEr9CCBVaNIROgs1JxTarKeAphq53WMMf+oenyNiMbS70ukYJSLbq6AmsFr7wmm IpmcSJDLXgOjdo0C5G3DK290dGgBAkOhD3iuA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=PvcNEdmhCu4lEkDHwy6d/NXIp27vcTkgHojlYvWqKHqbgUQH7Uy53cEIH5w9rYSJQY PMegxt8NdOZ+A9w4geG18eVQtSSGnnTRI1JSejdnaKuaRrzzaVSQXdhQthPERTKkapH6 Cw+7sNrYgm6U6casRLMRFMALPwVG2hAyJh+Uw= Received: by 10.115.109.6 with SMTP id l6mr175556wam.164.1282901406784; Fri, 27 Aug 2010 02:30:06 -0700 (PDT) Received: from localhost (KD113150081245.ppp-bb.dion.ne.jp [113.150.81.245]) by mx.google.com with ESMTPS id s5sm6245279wak.0.2010.08.27.02.30.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 27 Aug 2010 02:30:05 -0700 (PDT) From: jiang.adam@gmail.com To: ralf@linux-mips.org Cc: dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Adam Jiang Subject: [[PATCH V2]] mips: irq: add stackoverflow detection Date: Fri, 27 Aug 2010 18:29:25 +0900 Message-Id: <1282901365-28364-1-git-send-email-jiang.adam@gmail.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27680 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jiang.adam@gmail.com Precedence: bulk X-list: linux-mips From: Adam Jiang Add stackoverflow detection to mips arch Signed-off-by: Adam Jiang --- arch/mips/Kconfig.debug | 9 +++++++++ arch/mips/kernel/irq.c | 21 +++++++++++++++++++++ 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 43dc279..f437cd1 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -67,6 +67,15 @@ config CMDLINE_OVERRIDE Normally, you will choose 'N' here. +config DEBUG_STACKOVERFLOW + bool "Check for stack overflows" + depends on DEBUG_KERNEL + help + This option will cause messages to be printed if free stack space + drops below a certain limit(2GB on MIPS). The debugging option + provides another way to check stack overflow happened on kernel mode + stack usually caused by nested interruption. + config DEBUG_STACK_USAGE bool "Enable stack utilization instrumentation" depends on DEBUG_KERNEL diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index c6345f5..d0b924d 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -151,6 +151,26 @@ void __init init_IRQ(void) #endif } +#ifdef DEBUG_STACKOVERFLOW +static inline void check_stack_overflow(void) +{ + long sp; + + __asm__ __volatile__("move %0, $sp" : "=r" (sp)); + sp = sp & (THREAD_SIZE-1); + + /* check for stack overflow: is there less than 2KB free? */ + if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { + printk("do_IRQ: stack overflow: %ld\n", + sp - sizeof(struct thread_info)); + dump_stack(); + } +} +#else +static inline void check_stack_overflow(void) {} +#endif + + /* * do_IRQ handles all normal device IRQ's (the special * SMP cross-CPU interrupts have their own specific @@ -159,6 +179,7 @@ void __init init_IRQ(void) void __irq_entry do_IRQ(unsigned int irq) { irq_enter(); + check_stack_overflow(); __DO_IRQ_SMTC_HOOK(irq); generic_handle_irq(irq); irq_exit(); -- 1.7.2.2 From jiang.adam@gmail.com Fri Aug 27 11:32:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Aug 2010 11:32:54 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:40358 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491809Ab0H0Jcu (ORCPT ); Fri, 27 Aug 2010 11:32:50 +0200 Received: by pxi4 with SMTP id 4so1165436pxi.36 for ; Fri, 27 Aug 2010 02:32:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=qsGEjnBSKpml4UIv7ZnA/VEb7qF+OdgxZ6Z8GG+IY3M=; b=Ne+YPG9h5ZRxXct/WdonqBUyza8yDyrj9cx+il+R8WpeI9uVKieRAXAvnQoROhAQT3 omCinuhS/LLbjkuv2Yj2SRgZ9bsz21uK1lrIkjjBBGb42w2M9l7EMT1Mgg4TS8ABgLws iyB8MQ4KVzQqg4UR/VNoVrHn+WP+ydoe6VsKo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=eUx3hpTjZVXrkokisCnvN3WQR8GVX3j6aGR+YaTPaRBRfbiFniPHSRbqoI5j/6I4th tA5yFHsPSh4Qke8Vm6t6PxjRf3TB7vHW3uTjLksuBVpxgRWX/9Binzpg70XKnHIbDlKG gDHJQn3/Bltme448IxfA+oVjCFaAZO+UkkHZA= Received: by 10.142.212.6 with SMTP id k6mr1057036wfg.94.1282901564112; Fri, 27 Aug 2010 02:32:44 -0700 (PDT) Received: from localhost (KD113150081245.ppp-bb.dion.ne.jp [113.150.81.245]) by mx.google.com with ESMTPS id y16sm4148445wff.14.2010.08.27.02.32.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 27 Aug 2010 02:32:43 -0700 (PDT) From: jiang.adam@gmail.com To: ralf@linux-mips.org Cc: dmitri.vorobiev@movial.com, wuzhangjin@gmail.com, ddaney@caviumnetworks.com, peterz@infradead.org, fweisbec@gmail.com, tj@kernel.org, tglx@linutronix.de, mingo@elte.hu, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Adam Jiang Subject: [PATCH V2] mips: irq: add stackoverflow detection Date: Fri, 27 Aug 2010 18:32:06 +0900 Message-Id: <1282901526-28405-1-git-send-email-jiang.adam@gmail.com> X-Mailer: git-send-email 1.7.2.2 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27681 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jiang.adam@gmail.com Precedence: bulk X-list: linux-mips From: Adam Jiang Add stackoverflow detection to mips arch Signed-off-by: Adam Jiang --- arch/mips/Kconfig.debug | 9 +++++++++ arch/mips/kernel/irq.c | 21 +++++++++++++++++++++ 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 43dc279..f437cd1 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -67,6 +67,15 @@ config CMDLINE_OVERRIDE Normally, you will choose 'N' here. +config DEBUG_STACKOVERFLOW + bool "Check for stack overflows" + depends on DEBUG_KERNEL + help + This option will cause messages to be printed if free stack space + drops below a certain limit(2GB on MIPS). The debugging option + provides another way to check stack overflow happened on kernel mode + stack usually caused by nested interruption. + config DEBUG_STACK_USAGE bool "Enable stack utilization instrumentation" depends on DEBUG_KERNEL diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index c6345f5..d0b924d 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -151,6 +151,26 @@ void __init init_IRQ(void) #endif } +#ifdef DEBUG_STACKOVERFLOW +static inline void check_stack_overflow(void) +{ + long sp; + + __asm__ __volatile__("move %0, $sp" : "=r" (sp)); + sp = sp & (THREAD_SIZE-1); + + /* check for stack overflow: is there less than 2KB free? */ + if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { + printk("do_IRQ: stack overflow: %ld\n", + sp - sizeof(struct thread_info)); + dump_stack(); + } +} +#else +static inline void check_stack_overflow(void) {} +#endif + + /* * do_IRQ handles all normal device IRQ's (the special * SMP cross-CPU interrupts have their own specific @@ -159,6 +179,7 @@ void __init init_IRQ(void) void __irq_entry do_IRQ(unsigned int irq) { irq_enter(); + check_stack_overflow(); __DO_IRQ_SMTC_HOOK(irq); generic_handle_irq(irq); irq_exit(); -- 1.7.2.2 From manuel.lauss@googlemail.com Fri Aug 27 17:56:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Aug 2010 17:56:15 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:51968 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491809Ab0H0P4L (ORCPT ); Fri, 27 Aug 2010 17:56:11 +0200 Received: by bwz13 with SMTP id 13so2526676bwz.36 for ; Fri, 27 Aug 2010 08:56:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=ikr75LRn2O2WZGSuKllxYG4jxKdF642zY873ut9MVhk=; b=g6TDjoeQ3bV5ZztFxduwAiv2hHAZum/T60dKSt2c8ESuMh1GOMiq02yrm4rGZWdnTE 9EmNEhBWaxymhZVXypoPUx5WnontjOS5GiHU/He1gFZzkS8FwG4WhOTDwYHHa2JplhYM lDriBtfUULmGNxfOu2r4KNCEjukiOTMQpyFE0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=Tl8Le/k9XeXINwtCAGMXP2dhPfw/tE6CuO5/VEYIAnM+Q914eSmwZIkh/Ait9APVq6 V9gmMw8Rin4jfxtzh/ormeYp8qTIGxL7BHDQpUNIuS9bgd8lEPBlTI5tXWufgNChdSCh wMgoqEz3wjGYyDnxpFOUmlJFQ9Op9cYcYClhU= Received: by 10.204.161.209 with SMTP id s17mr651925bkx.67.1282924570356; Fri, 27 Aug 2010 08:56:10 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id 24sm2683051bkr.19.2010.08.27.08.56.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 27 Aug 2010 08:56:09 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH 0/2] MIPS: Au1300/DB1300 support. Date: Fri, 27 Aug 2010 17:56:03 +0200 Message-Id: <1282924565-16024-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27682 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The following 2 patches add basic Au1300 and DB1300 support. DB1300 core support includes everything required to get either NFSroot or a rootfs on Harddisk/CFcard working. Please consider for 2.6.37. Manuel Lauss (2): MIPS: Alchemy: Au1300 SoC support MIPS: Alchemy: DB1300 support arch/mips/alchemy/Kconfig | 17 + arch/mips/alchemy/Platform | 7 + arch/mips/alchemy/common/Makefile | 2 + arch/mips/alchemy/common/dbdma.c | 48 ++- arch/mips/alchemy/common/gpioint.c | 468 +++++++++++++++++ arch/mips/alchemy/common/gpiolib-au1300.c | 54 ++ arch/mips/alchemy/common/platform.c | 9 + arch/mips/alchemy/common/power.c | 9 +- arch/mips/alchemy/common/sleeper.S | 73 +++ arch/mips/alchemy/common/time.c | 1 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300/Makefile | 1 + arch/mips/alchemy/devboards/db1300/platform.c | 605 ++++++++++++++++++++++ arch/mips/alchemy/devboards/db1300/setup.c | 259 +++++++++ arch/mips/alchemy/devboards/prom.c | 4 + arch/mips/boot/compressed/uart-alchemy.c | 5 +- arch/mips/configs/db1300_defconfig | 280 ++++++++++ arch/mips/include/asm/cpu.h | 8 + arch/mips/include/asm/mach-au1x00/au1000.h | 198 +++++++- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 ++ arch/mips/include/asm/mach-au1x00/gpio-au1300.h | 250 +++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 4 + arch/mips/include/asm/mach-db1x00/bcsr.h | 5 +- arch/mips/include/asm/mach-db1x00/db1300.h | 40 ++ arch/mips/include/asm/mach-db1x00/irq.h | 23 + arch/mips/kernel/cpu-probe.c | 18 + drivers/i2c/busses/Kconfig | 6 +- drivers/pcmcia/Kconfig | 4 +- drivers/pcmcia/db1xxx_ss.c | 30 +- drivers/spi/Kconfig | 2 +- drivers/video/Kconfig | 8 +- sound/soc/au1x/Kconfig | 6 +- 32 files changed, 2450 insertions(+), 28 deletions(-) create mode 100644 arch/mips/alchemy/common/gpioint.c create mode 100644 arch/mips/alchemy/common/gpiolib-au1300.c create mode 100644 arch/mips/alchemy/devboards/db1300/Makefile create mode 100644 arch/mips/alchemy/devboards/db1300/platform.c create mode 100644 arch/mips/alchemy/devboards/db1300/setup.c create mode 100644 arch/mips/configs/db1300_defconfig create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1300.h create mode 100644 arch/mips/include/asm/mach-db1x00/db1300.h create mode 100644 arch/mips/include/asm/mach-db1x00/irq.h -- 1.7.2 From manuel.lauss@googlemail.com Fri Aug 27 17:56:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Aug 2010 17:56:42 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:51968 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491819Ab0H0P4N (ORCPT ); Fri, 27 Aug 2010 17:56:13 +0200 Received: by mail-bw0-f49.google.com with SMTP id 13so2526676bwz.36 for ; Fri, 27 Aug 2010 08:56:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=6c5+t0ySodEtF5utL6g8fov9CX7Mebypoi2GtfY487I=; b=wj2BP7lLRr3DjqiunKw+FkFP1UghEVFhe+AAPHZiY9Tqq7SWw3wvEVCzUPYDjd+TEB +/6N99NgKzr4BrW5bvaZ0mKtSXKpkwUJzWX92WNwh7qP3jxK8UgtqPNh3J1O9Gr23Civ ktwIe3+CGcw7U1PYk966mHkKh8jPeQq1rijIM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=FMLgDYkGKw5g0dC1rWXcIhZtscPXvQ9QANb2q1Hh12EARhCS48E+5ITllt+vmEJ10k ivHug/YhZVXgCtFx9WBMBgvJv/eTiz18EZtqi7pi+UXKCemj2gf82yqLmz40t/rWNiU7 gohozTjAqfeHzO6O3j1GLM87TbN17oY+wSB04= Received: by 10.204.56.84 with SMTP id x20mr654137bkg.68.1282924572929; Fri, 27 Aug 2010 08:56:12 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id 24sm2683051bkr.19.2010.08.27.08.56.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 27 Aug 2010 08:56:11 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH 1/2] MIPS: Alchemy: Au1300 SoC support Date: Fri, 27 Aug 2010 17:56:04 +0200 Message-Id: <1282924565-16024-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.2 In-Reply-To: <1282924565-16024-1-git-send-email-manuel.lauss@googlemail.com> References: <1282924565-16024-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27683 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Add support for the Au1300 SoC: New GPIO/Interrupt controller code, basic integration. Signed-off-by: Manuel Lauss --- The sleepcode has been taken from the RMI sources. arch/mips/alchemy/Kconfig | 9 + arch/mips/alchemy/common/Makefile | 2 + arch/mips/alchemy/common/dbdma.c | 48 ++- arch/mips/alchemy/common/gpioint.c | 468 ++++++++++++++++++++++ arch/mips/alchemy/common/gpiolib-au1300.c | 54 +++ arch/mips/alchemy/common/platform.c | 9 + arch/mips/alchemy/common/power.c | 9 +- arch/mips/alchemy/common/sleeper.S | 73 ++++ arch/mips/alchemy/common/time.c | 1 + arch/mips/include/asm/cpu.h | 8 + arch/mips/include/asm/mach-au1x00/au1000.h | 198 +++++++++- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 ++ arch/mips/include/asm/mach-au1x00/gpio-au1300.h | 250 ++++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 4 + arch/mips/kernel/cpu-probe.c | 18 + drivers/i2c/busses/Kconfig | 6 +- drivers/spi/Kconfig | 2 +- drivers/video/Kconfig | 8 +- sound/soc/au1x/Kconfig | 6 +- 19 files changed, 1187 insertions(+), 19 deletions(-) create mode 100644 arch/mips/alchemy/common/gpioint.c create mode 100644 arch/mips/alchemy/common/gpiolib-au1300.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1300.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 2ccfd4a..21b232c 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -2,6 +2,10 @@ config ALCHEMY_GPIOINT_AU1000 bool +# au1300-style GPIO/INT controller +config ALCHEMY_GPIOINT_AU1300 + bool + # select this in your board config if you don't want to use the gpio # namespace as documented in the manuals. In this case however you need # to create the necessary gpio_* functions in your board code/headers! @@ -158,3 +162,8 @@ config SOC_AU1550 config SOC_AU1200 bool select ALCHEMY_GPIOINT_AU1000 + +config SOC_AU1300 + bool + select SOC_AU1X00 + select ALCHEMY_GPIOINT_AU1300 diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 27811fe..3b3f0ae 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -9,11 +9,13 @@ obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ sleeper.o dma.o dbdma.o obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o +obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpioint.o # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) ifeq ($(CONFIG_GPIOLIB),y) obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o + obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpiolib-au1300.o endif endif diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index ca0506a..aedb7e5 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -40,8 +40,6 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - /* * The Descriptor Based DMA supports up to 16 channels. * @@ -151,6 +149,47 @@ static dbdev_tab_t dbdev_tab[] = { #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU1300 + { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 }, + { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 }, + { DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 }, + { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, +#endif /* CONFIG_SOC_AU1300 */ + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, @@ -1073,6 +1112,9 @@ static int __init au1xxx_dbdma_init(void) case ALCHEMY_CPU_AU1200: irq_nr = AU1200_DDMA_INT; break; + case ALCHEMY_CPU_AU1300: + irq_nr = AU1300_DDMA_INT; + break; default: return -ENODEV; } @@ -1094,5 +1136,3 @@ static int __init au1xxx_dbdma_init(void) return ret; } subsys_initcall(au1xxx_dbdma_init); - -#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ diff --git a/arch/mips/alchemy/common/gpioint.c b/arch/mips/alchemy/common/gpioint.c new file mode 100644 index 0000000..bf2df8d --- /dev/null +++ b/arch/mips/alchemy/common/gpioint.c @@ -0,0 +1,468 @@ +/* + * gpioint.c - Au1300 GPIO+Interrupt controller support. + * + * Copyright (c) 2009-2010 Manuel Lauss + * + * licensed under the GPLv2. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#if 0 +#define DBG(x...) printk(KERN_INFO "GPIC " x) +#else +#define DBG(x...) +#endif + +static int au1300_gpic_settype(unsigned int irq, unsigned int type); + +/* setup for known onchip sources */ +struct gpic_devint_data { + int irq; /* linux IRQ number */ + int type; /* IRQ_TYPE_ */ + int prio; /* irq priority, 0 highest, 3 lowest */ + int internal; /* internal-only source (no ext. pin)? */ +}; + +struct gpic_devint_data au1300_devints[] __initdata = { + /* multifunction: gpio/device */ + { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + /* au1300 internal-only ints */ + { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, }, + { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { -1, }, /* terminator */ +}; + +struct alchemy_gpic_sysdev { + struct sys_device sysdev; + void __iomem *base; + unsigned long icr[6]; + unsigned long pincfg[128]; +}; + + +/* + * au1300_gpic_modcfg - change PIN configuration. + * @gpio: pin to change (0-based GPIO number from datasheet). + * @clr: clear all bits set in 'clr'. + * @set: set these bits. + * + * modifies a pins' configuration register, bits set in @clr will + * be cleared in the register, bits in @set will be set. + * NOTE: according to the datasheet, this should only be called + * for disabled interrupts! + */ +static inline void au1300_gpic_modcfg(unsigned int gpio, + unsigned long clr, + unsigned long set) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long l; + + r += gpio * 4; /* offset into pin config array */ + l = __raw_readl(r + AU1300_GPIC_PINCFG); + l &= ~clr; + l |= set; + __raw_writel(l, r + AU1300_GPIC_PINCFG); + wmb(); + + DBG("MODCFG(%03d) %08lx %08lx -> %08lx\n", gpio, clr, set, l); +} + +/* + * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl). + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to the GPIO controller, so its level can either + * be read or set through the generic GPIO functions. + * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1). + * REVISIT: is this function really necessary? + */ +void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio) +{ + au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE); + + DBG("PIN2GPIN(%03d)\n", (int)gpio); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio); + +/* + * au1300_pinfunc_to_dev - assign a pin to the device function. + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to its associated device function; the pin will be + * driven by the device and not through GPIO functions. + */ +void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + r += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, r + AU1300_GPIC_DEVSEL); + wmb(); + + DBG("PIN2DEV(%03d)\n", (int)gpio); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev); + +/* + * au1300_set_irq_priority - set internal priority of IRQ. + * @irq: irq to set priority (linux irq number). + * @p: priority (0 = highest, 3 = lowest). + */ +void au1300_set_irq_priority(unsigned int irq, int p) +{ + irq -= ALCHEMY_GPIC_INT_BASE; + au1300_gpic_modcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p)); +} +EXPORT_SYMBOL_GPL(au1300_set_irq_priority); + +/* + * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers. + * @dchan: dbdma trigger select (0, 1). + * @gpio: pin to assign as trigger. + * + * DBDMA controller has 2 external trigger sources; this function + * assigns a GPIO to the selected trigger. + */ +void au1300_set_dbdma_gpio(int dchan, unsigned int gpio) +{ + unsigned long r; + + if ((dchan >= 0) && (dchan <= 1)) { + r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + r &= ~(0xff << (8 * dchan)); + r |= (gpio & 0x7f) << (8 * dchan); + __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + wmb(); + } +} + +/**********************************************************************/ + +static void gpic_pin_set_idlewake(unsigned int gpio, int allow) +{ + au1300_gpic_modcfg(gpio, GPIC_CFG_IDLEWAKE, + allow ? GPIC_CFG_IDLEWAKE : 0); + + DBG("SETIDLEWAKE(%03d) %d\n", gpio, allow); +} + +static void au1300_gpic_mask(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IDIS); + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_unmask(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= ALCHEMY_GPIC_INT_BASE; + + gpic_pin_set_idlewake(irq, 1); + + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IEN); + wmb(); +} + +static void au1300_gpic_maskack(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */ + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_ack(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + wmb(); +} + +static struct irq_chip au1300_gpic = { + .name = "Au1300-GPIOINT", + .ack = au1300_gpic_ack, + .mask = au1300_gpic_mask, + .mask_ack = au1300_gpic_maskack, + .unmask = au1300_gpic_unmask, + .set_type = au1300_gpic_settype, +}; + +#define SICHN(i, h, n) \ + set_irq_chip_and_handler_name(i, &au1300_gpic, h, n) + +static int au1300_gpic_settype(unsigned int irq, unsigned int type) +{ + unsigned long s; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + s = GPIC_CFG_IC_LEVEL_HIGH; + SICHN(irq, handle_level_irq, "highlevel"); + break; + case IRQ_TYPE_LEVEL_LOW: + s = GPIC_CFG_IC_LEVEL_LOW; + SICHN(irq, handle_level_irq, "lowlevel"); + break; + case IRQ_TYPE_EDGE_RISING: + s = GPIC_CFG_IC_EDGE_RISE; + SICHN(irq, handle_edge_irq, "riseedge"); + break; + case IRQ_TYPE_EDGE_FALLING: + s = GPIC_CFG_IC_EDGE_FALL; + SICHN(irq, handle_edge_irq, "falledge"); + break; + case IRQ_TYPE_EDGE_BOTH: + s = GPIC_CFG_IC_EDGE_BOTH; + SICHN(irq, handle_edge_irq, "bothedge"); + break; + case IRQ_TYPE_NONE: + s = GPIC_CFG_IC_OFF; + SICHN(irq, handle_level_irq, "disabled"); + break; + default: + return -EINVAL; + } + + au1300_gpic_modcfg(irq - ALCHEMY_GPIC_INT_BASE, + GPIC_CFG_IC_MASK, s); + + return 0; +} + +static void __init alchemy_gpic_init_irq(struct gpic_devint_data *dints) +{ + int i; + void __iomem *bank_base; + + mips_cpu_irq_init(); + + /* disable & ack all possible on-chip sources */ + for (i = 0; i < 4; i++) { + bank_base = AU1300_GPIC_ADDR + (i * 4); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS); + wmb(); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND); + wmb(); + } + + /* register all possible irq sources, with 2nd highest priority */ + bank_base = AU1300_GPIC_ADDR + AU1300_GPIC_PINCFG; + for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) { + au1300_set_irq_priority(i, 1); + au1300_gpic_settype(i, IRQ_TYPE_NONE); + } + + /* setup known on-chip sources */ + while ((i = dints->irq) != -1) { + au1300_gpic_settype(i, dints->type); + au1300_set_irq_priority(i, dints->prio); + + if (dints->internal) + au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE); + + dints++; + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); +} + +static int alchemy_gpic_suspend(struct sys_device *dev, pm_message_t state) +{ + struct alchemy_gpic_sysdev *icdev = + container_of(dev, struct alchemy_gpic_sysdev, sysdev); + void __iomem *addy; + int i; + + /* save pin configuration */ + addy = icdev->base + AU1300_GPIC_PINCFG; + for (i = 0; i < 128; i++) + icdev->pincfg[i] = __raw_readl(addy + (i << 2)); + + /* save interrupt mask status */ + icdev->icr[0] = __raw_readl(icdev->base + AU1300_GPIC_IEN + 0x0); + icdev->icr[1] = __raw_readl(icdev->base + AU1300_GPIC_IEN + 0x4); + icdev->icr[2] = __raw_readl(icdev->base + AU1300_GPIC_IEN + 0x8); + icdev->icr[3] = __raw_readl(icdev->base + AU1300_GPIC_IEN + 0xc); + + /* misc */ + icdev->icr[4] = __raw_readl(icdev->base + AU1300_GPIC_DMASEL); + wmb(); + + return 0; +} + +static int alchemy_gpic_resume(struct sys_device *dev) +{ + struct alchemy_gpic_sysdev *icdev = + container_of(dev, struct alchemy_gpic_sysdev, sysdev); + void __iomem *addy; + int i; + + /* mask all off first */ + __raw_writel(-1, icdev->base + AU1300_GPIC_IDIS + 0x0); + __raw_writel(-1, icdev->base + AU1300_GPIC_IDIS + 0x4); + __raw_writel(-1, icdev->base + AU1300_GPIC_IDIS + 0x8); + __raw_writel(-1, icdev->base + AU1300_GPIC_IDIS + 0xc); + wmb(); + + /* restore pin configurations */ + addy = icdev->base + AU1300_GPIC_PINCFG; + for (i = 0; i < 128; i++) + __raw_writel(icdev->pincfg[i], addy + (i << 2)); + wmb(); + + __raw_writel(icdev->icr[4], icdev->base + AU1300_GPIC_DMASEL); + wmb(); + + /* restore masks */ + addy = icdev->base + AU1300_GPIC_IEN; + __raw_writel(icdev->icr[0], addy + 0x0); + wmb(); + __raw_writel(icdev->icr[1], addy + 0x4); + wmb(); + __raw_writel(icdev->icr[2], addy + 0x8); + wmb(); + __raw_writel(icdev->icr[3], addy + 0xc); + wmb(); + + return 0; +} + +static struct sysdev_class alchemy_gpic_sysdev_class = { + .name = "gpic", + .suspend = alchemy_gpic_suspend, + .resume = alchemy_gpic_resume, +}; + +static int __init alchemy_gpic_sysdev_init(void) +{ + struct alchemy_gpic_sysdev *icdev; + int err; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + break; + default: /* we don't handle these */ + return 0; + } + + err = sysdev_class_register(&alchemy_gpic_sysdev_class); + if (err) + return err; + + icdev = kzalloc(sizeof(struct alchemy_gpic_sysdev), GFP_KERNEL); + if (!icdev) + return -ENOMEM; + + icdev->base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + + icdev->sysdev.id = -1; + icdev->sysdev.cls = &alchemy_gpic_sysdev_class; + err = sysdev_register(&icdev->sysdev); + if (err) + kfree(icdev); + + return err; +} +device_initcall(alchemy_gpic_sysdev_init); + +/**********************************************************************/ + +void __init arch_init_irq(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + alchemy_gpic_init_irq(&au1300_devints[0]); + break; + } +} + +void plat_irq_dispatch(void) +{ + unsigned long c = read_c0_cause(), s = read_c0_status(); + int i; + + DBG("M %08lx S %08lx\n", c, s); + c &= s; + + if (c & CAUSEF_IP7) /* c0 timer */ + i = MIPS_CPU_IRQ_BASE + 7 - ALCHEMY_GPIC_INT_BASE; + else if (c & (CAUSEF_IP2 | CAUSEF_IP3 | CAUSEF_IP4 | CAUSEF_IP5)) { + i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC); + DBG("I %d\n", i); + if (unlikely(i == 127)) + goto spurious; + } else + goto spurious; + + do_IRQ(i + ALCHEMY_GPIC_INT_BASE); + return; +spurious: + spurious_interrupt(); +} diff --git a/arch/mips/alchemy/common/gpiolib-au1300.c b/arch/mips/alchemy/common/gpiolib-au1300.c new file mode 100644 index 0000000..661cc6f --- /dev/null +++ b/arch/mips/alchemy/common/gpiolib-au1300.c @@ -0,0 +1,54 @@ +/* + * Au1300-style GPIO/INT Controller GPIOLIB support + */ + +#include +#include +#include +#include +#include + +#include + +static int _gpic_get(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_get_value(off + AU1300_GPIO_BASE); +} + +static void _gpic_set(struct gpio_chip *chip, unsigned int off, int v) +{ + au1300_gpio_set_value(off + AU1300_GPIO_BASE, v); +} + +static int _gpic_direction_input(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_direction_input(off + AU1300_GPIO_BASE); +} + +static int _gpic_direction_output(struct gpio_chip *chip, unsigned int off, + int v) +{ + return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v); +} + +static int _gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_to_irq(off + AU1300_GPIO_BASE); +} + +static struct gpio_chip au1300_gpiochip = { + .label = "au1300", + .direction_input = _gpic_direction_input, + .direction_output = _gpic_direction_output, + .get = _gpic_get, + .set = _gpic_set, + .to_irq = _gpic_gpio_to_irq, + .base = AU1300_GPIO_BASE, + .ngpio = AU1300_GPIO_NUM, +}; + +static int __init au1300_gpiochip_init(void) +{ + return gpiochip_add(&au1300_gpiochip); +} +arch_initcall(au1300_gpiochip_init); diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 1dc55ee..36ed78c 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -55,6 +55,11 @@ static struct plat_serial8250_port au1x00_uart_data[] = { #elif defined(CONFIG_SOC_AU1200) PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), +#elif defined(CONFIG_SOC_AU1300) + PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT), + PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT), + PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT), + PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT), #endif { }, }; @@ -67,6 +72,7 @@ static struct platform_device au1xx0_uart_device = { }, }; +#ifdef FOR_PLATFORM_C_USB_HOST_INT /* OHCI (USB full speed host controller) */ static struct resource au1xxx_usb_ohci_resources[] = { [0] = { @@ -94,6 +100,7 @@ static struct platform_device au1xxx_usb_ohci_device = { .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), .resource = au1xxx_usb_ohci_resources, }; +#endif /*** AU1100 LCD controller ***/ @@ -413,7 +420,9 @@ void __init au1xxx_override_eth_cfg(unsigned int port, static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, +#ifdef FOR_PLATFORM_C_USB_HOST_INT &au1xxx_usb_ohci_device, +#endif #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 5ef06a1..86a40dc 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -54,7 +54,9 @@ static unsigned int sleep_uart0_fifoctl; static unsigned int sleep_uart0_linectl; static unsigned int sleep_uart0_clkdiv; static unsigned int sleep_uart0_enable; +#ifndef CONFIG_SOC_AU1300 /* ugly but quick fix */ static unsigned int sleep_usb[2]; +#endif static unsigned int sleep_sys_clocks[5]; static unsigned int sleep_sys_pinfunc; static unsigned int sleep_static_memctlr[4][3]; @@ -79,6 +81,7 @@ static void save_core_regs(void) au_sync(); #ifndef CONFIG_SOC_AU1200 +#ifndef CONFIG_SOC_AU1300 /* doesn't apply to Au1300 USB */ /* Shutdown USB host/device. */ sleep_usb[0] = au_readl(USB_HOST_CONFIG); @@ -91,7 +94,7 @@ static void save_core_regs(void) sleep_usb[1] = au_readl(USBD_ENABLE); au_writel(0, USBD_ENABLE); au_sync(); - +#endif /* au1300 */ #else /* AU1200 */ /* enable access to OTG mmio so we can save OTG CAP/MUX. @@ -147,9 +150,11 @@ static void restore_core_regs(void) au_sync(); #ifndef CONFIG_SOC_AU1200 +#ifndef CONFIG_SOC_AU1300 /* doesn't apply to Au1300 either */ au_writel(sleep_usb[0], USB_HOST_CONFIG); au_writel(sleep_usb[1], USBD_ENABLE); au_sync(); +#endif #else /* enable accces to OTG memory */ au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); @@ -200,6 +205,8 @@ void au_sleep(void) alchemy_sleep_au1000(); else if (cpuid <= ALCHEMY_CPU_AU1200) alchemy_sleep_au1550(); + else if (cpuid <= ALCHEMY_CPU_AU1300) + alchemy_sleep_au1300(); restore_core_regs(); } } diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S index 77f3c74..c7bcc7e 100644 --- a/arch/mips/alchemy/common/sleeper.S +++ b/arch/mips/alchemy/common/sleeper.S @@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550) END(alchemy_sleep_au1550) +/* sleepcode for Au1300 memory controller type */ +LEAF(alchemy_sleep_au1300) + + SETUP_SLEEP + + /* cache following instructions, as memory gets put to sleep */ + la t0, 2f + la t1, 4f + subu t2, t1, t0 + + .set mips3 + +1: cache 0x14, 0(t0) + subu t2, t2, 32 + bgez t2, 1b + addu t0, t0, 32 + + .set mips0 + +2: lui a0, 0xb400 /* mem_xxx */ + + /* disable all ports in mem_sdportcfga */ + sw zero, 0x868(a0) /* mem_sdportcfga */ + sync + + /* disable ODT */ + li t0, 0x03010000 + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sync + + /* precharge */ + li t0, 0x23000400 + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sync + + /* auto refresh */ + sw zero, 0x08c8(a0) /* mem_sdautoref */ + sync + + /* block access to the DDR */ + lw t0, 0x0848(a0) /* mem_sdconfigb */ + li t1, (1 << 7 | 0x3F) + or t0, t0, t1 + sw t0, 0x0848(a0) /* mem_sdconfigb */ + sync + + /* issue the Self Refresh command */ + li t0, 0x10000000 + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sync + + /* wait for sdram to enter self-refresh mode */ + lui t0, 0x0300 +3: lw t1, 0x0850(a0) /* mem_sdstat */ + and t2, t1, t0 + bne t2, t0, 3b + nop + + /* disable SDRAM clocks */ + li t0, ~(3<<28) + lw t1, 0x0840(a0) /* mem_sdconfiga */ + and t1, t1, t0 /* clear CE[1:0] */ + sw t1, 0x0840(a0) /* mem_sdconfiga */ + sync + + DO_SLEEP +4: + +END(alchemy_sleep_au1300) + /* This is where we return upon wakeup. * Reload all of the registers and return. diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 2aecb2f..db82325 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -179,6 +179,7 @@ static int alchemy_m2inttab[] __initdata = { AU1100_RTC_MATCH2_INT, AU1550_RTC_MATCH2_INT, AU1200_RTC_MATCH2_INT, + AU1300_RTC_MATCH2_INT, }; void __init plat_time_init(void) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index b201a8f..0304fc8 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_INGENIC 0xd00000 @@ -121,6 +122,13 @@ #define PRID_REV_BCM6368 0x0030 /* + * These are the PRID's for when 23:16 == PRID_COMP_RMI + */ + +#define PRID_IMP_AU13XX 0x8000 + + +/* * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index a697661..9f56925 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void) #define ALCHEMY_CPU_AU1100 2 #define ALCHEMY_CPU_AU1550 3 #define ALCHEMY_CPU_AU1200 4 +#define ALCHEMY_CPU_AU1300 5 static inline int alchemy_get_cputype(void) { @@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void) case 0x05030000: return ALCHEMY_CPU_AU1200; break; + case 0x800c0000: + return ALCHEMY_CPU_AU1300; + break; } return ALCHEMY_CPU_UNKNOWN; @@ -180,6 +184,68 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) wmb(); } +/* Multifunction pins: Each of these pins can either be assigned to the + * GPIO controller or a on-chip peripheral. + * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to + * assign one of these to either the GPIO controller or the device. + */ +enum au1300_multifunc_pins { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, + AU1300_PIN_WAKE3, + /* external clock sources for PSCs: 4-5 */ + AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* aux clk input for freqgen 3: 10 */ + AU1300_PIN_FG3AUX, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 29-31 */ + AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, +}; + +/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */ +extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio); +extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio); +extern void au1300_set_irq_priority(unsigned int irq, int p); +extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); @@ -190,17 +256,22 @@ extern unsigned long au1xxx_calc_clock(void); /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); +void alchemy_sleep_au1300(void); void au_sleep(void); /* SOC Interrupt numbers */ - +/* Au1000-style (IC0/1): 2 controllers with 32 sources each */ #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST +/* Au1300-style (GPIC): 1 controller with up to 128 sources */ +#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) +#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + 127) + enum soc_au1000_ints { AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, AU1000_UART0_INT = AU1000_FIRST_INT, @@ -521,6 +592,43 @@ enum soc_au1200_ints { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ +/* Au1300 peripheral interrupt numbers */ +#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) +#define AU1300_UART1_INT (AU1300_FIRST_INT + 17) +#define AU1300_UART2_INT (AU1300_FIRST_INT + 25) +#define AU1300_UART3_INT (AU1300_FIRST_INT + 27) +#define AU1300_SD1_INT (AU1300_FIRST_INT + 32) +#define AU1300_SD2_INT (AU1300_FIRST_INT + 38) +#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) +#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) +#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) +#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) +#define AU1300_NAND_INT (AU1300_FIRST_INT + 62) +#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) +#define AU1300_MMU_INT (AU1300_FIRST_INT + 76) +#define AU1300_MPU_INT (AU1300_FIRST_INT + 77) +#define AU1300_GPU_INT (AU1300_FIRST_INT + 78) +#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) +#define AU1300_TOY_INT (AU1300_FIRST_INT + 80) +#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) +#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) +#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) +#define AU1300_RTC_INT (AU1300_FIRST_INT + 84) +#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) +#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) +#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) +#define AU1300_UART0_INT (AU1300_FIRST_INT + 88) +#define AU1300_SD0_INT (AU1300_FIRST_INT + 89) +#define AU1300_USB_INT (AU1300_FIRST_INT + 90) +#define AU1300_LCD_INT (AU1300_FIRST_INT + 91) +#define AU1300_BSA_INT (AU1300_FIRST_INT + 92) +#define AU1300_MPE_INT (AU1300_FIRST_INT + 93) +#define AU1300_ITE_INT (AU1300_FIRST_INT + 94) +#define AU1300_AES_INT (AU1300_FIRST_INT + 95) +#define AU1300_CIM_INT (AU1300_FIRST_INT + 96) + +/**********************************************************************/ + /* * SDRAM register offsets */ @@ -808,6 +916,46 @@ enum soc_au1200_ints { #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif +/**********************************************************************/ + +#define AU1300_ROM_PHYS_ADDR 0x10000000 +#define AU1300_OTP_PHYS_ADDR 0x10002000 +#define AU1300_UART0_PHYS_ADDR 0x10100000 +#define AU1300_UART1_PHYS_ADDR 0x10101000 +#define AU1300_UART2_PHYS_ADDR 0x10102000 +#define AU1300_UART3_PHYS_ADDR 0x10103000 +#define AU1300_GPIC_PHYS_ADDR 0x10200000 +#define AU1300_AES_PHYS_ADDR 0x10300000 +#define AU1300_GPU_PHYS_ADDR 0x10500000 +#define AU1300_SD0_PHYS_ADDR 0x10600000 +#define AU1300_SD1_PHYS_ADDR 0x10601000 +#define AU1300_SD2_PHYS_ADDR 0x10602000 +#define AU1300_SYS_PHYS_ADDR 0x10900000 +#define AU1300_PSC0_PHYS_ADDR 0x10A00000 +#define AU1300_PSC1_PHYS_ADDR 0x10A01000 +#define AU1300_PSC2_PHYS_ADDR 0x10A02000 +#define AU1300_PSC3_PHYS_ADDR 0x10A03000 +#define AU1300_VSS_PHYS_ADDR 0x11003000 + +#define AU1300_MEM_PHYS_ADDR 0x14000000 +#define AU1300_STATIC_PHYS_ADDR 0x14001000 +#define AU1300_UDMA_PHYS_ADDR 0x14001800 +#define AU1300_DDMA_PHYS_ADDR 0x14002000 +#define AU1300_CIM_PHYS_ADDR 0x14004000 +#define AU1300_MAEITE_PHYS_ADDR 0x14010000 +#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 +#define AU1300_USB_PHYS_ADDR 0x14020000 +#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 +#define AU1300_LCD_PHYS_ADDR 0x15000000 + +#ifdef CONFIG_SOC_AU1300 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL +#endif + +/**********************************************************************/ + /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 @@ -825,14 +973,12 @@ enum soc_au1200_ints { #define MEM_STTIME3 0xB4001034 #define MEM_STADDR3 0xB4001038 -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) #define MEM_STNDCTL 0xB4001100 #define MEM_STSTAT 0xB4001104 #define MEM_STNAND_CMD 0x0 #define MEM_STNAND_ADDR 0x4 #define MEM_STNAND_DATA 0x20 -#endif /* Interrupt Controller register offsets */ @@ -942,6 +1088,52 @@ enum soc_au1200_ints { #define IC1_TESTBIT 0xB1800080 +/* + * Au1300 GPIO+INT controller (GPIC) register offsets and bits + * Registers are 128bits (0x10 bytes), divided into 4 "banks". + */ +#define AU1300_GPIC_PINVAL 0x0000 +#define AU1300_GPIC_PINVALCLR 0x0010 +#define AU1300_GPIC_IPEND 0x0020 +#define AU1300_GPIC_PRIENC 0x0030 +#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ +#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ +#define AU1300_GPIC_DMASEL 0x0060 +#define AU1300_GPIC_DEVSEL 0x0080 +#define AU1300_GPIC_DEVCLR 0x0090 +#define AU1300_GPIC_RSTVAL 0x00a0 +/* pin configuration space. one 32bit register for up to 128 IRQs */ +#define AU1300_GPIC_PINCFG 0x1000 + +#define GPIC_GPIO_TO_BIT(gpio) \ + (1 << ((gpio) & 0x1f)) + +#define GPIC_GPIO_BANKOFF(gpio) \ + (((gpio) >> 5) * 4) + +/* Pin Control bits: who owns the pin, what does it do */ +#define GPIC_CFG_PC_GPIN 0 +#define GPIC_CFG_PC_DEV 1 +#define GPIC_CFG_PC_GPOLOW 2 +#define GPIC_CFG_PC_GPOHIGH 3 +#define GPIC_CFG_PC_MASK 3 + +/* assign pin to MIPS IRQ line */ +#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) +#define GPIC_CFG_IL_MASK (3 << 2) + +/* pin interrupt type setup */ +#define GPIC_CFG_IC_OFF (0 << 4) +#define GPIC_CFG_IC_LEVEL_LOW (1 << 4) +#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) +#define GPIC_CFG_IC_EDGE_FALL (5 << 4) +#define GPIC_CFG_IC_EDGE_RISE (6 << 4) +#define GPIC_CFG_IC_EDGE_BOTH (7 << 4) +#define GPIC_CFG_IC_MASK (7 << 4) + +/* allow interrupt to wake cpu from 'wait' */ +#define GPIC_CFG_IDLEWAKE (1 << 7) + /* Au1000 */ #ifdef CONFIG_SOC_AU1000 diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index c8a553a3..17101e1 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -195,6 +195,39 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CIM_SYNC 26 #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU1300 +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_UART2_TX 4 +#define DSCR_CMD0_UART2_RX 5 +#define DSCR_CMD0_UART3_TX 6 +#define DSCR_CMD0_UART3_RX 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 12 +#define DSCR_CMD0_AES_RX 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_SDMS_TX2 24 +#define DSCR_CMD0_SDMS_RX2 25 +#define DSCR_CMD0_CIM_SYNC 26 +#define DSCR_CMD0_UDMA 27 +#define DSCR_CMD0_DMA_REQ0 28 +#define DSCR_CMD0_DMA_REQ1 29 +#endif /* CONFIG_SOC_AU1300 */ + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h new file mode 100644 index 0000000..5d3bf5e --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -0,0 +1,250 @@ +/* + * gpio-au1300.h -- GPIO control for Au1300 and compatibles. + * + * Copyright (c) 2009-2010 Manuel Lauss + */ + +#ifndef _GPIO_AU1300_H_ +#define _GPIO_AU1300_H_ + +#include +#include +#include + +#define AU1300_GPIO_BASE 0 +#define AU1300_GPIO_NUM 75 +#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) + +#define AU1300_GPIC_ADDR \ + (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) + +static inline int au1300_gpio_get_value(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + int bit; + + gpio -= AU1300_GPIO_BASE; + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; +} + +static inline int au1300_gpio_direction_input(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); + wmb(); + + return 0; +} + +static inline int au1300_gpio_set_value(unsigned int gpio, int v) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL + : AU1300_GPIC_PINVALCLR)); + wmb(); + + return 0; +} + +static inline int au1300_gpio_direction_output(unsigned int gpio, int v) +{ + /* hw switches to output automatically */ + return au1300_gpio_set_value(gpio, v); +} + +static inline int au1300_gpio_to_irq(unsigned int gpio) +{ + return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); +} + +static inline int au1300_irq_to_gpio(unsigned int irq) +{ + return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; +} + +static inline int au1300_gpio_is_valid(unsigned int gpio) +{ + return ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); +} + +static inline int au1300_gpio_cansleep(unsigned int gpio) +{ + return 0; +} + +static inline void alchemy_gpio1_input_enable(void) +{ + __raw_writel(0, (void __iomem *)KSEG1ADDR(AU1300_SYS_PHYS_ADDR) + 0x110); + wmb(); +} + +/* hardware remembers gpio 0-63 levels on powerup */ +static inline int au1300_gpio_getinitlvl(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long v; + + if (unlikely(gpio > 63)) + return 0; + else if (gpio > 31) { + gpio -= 32; + roff += 4; + } + + v = __raw_readl(roff + AU1300_GPIC_RSTVAL); + return (v >> gpio) & 1; +} + +/**********************************************************************/ + +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifndef CONFIG_GPIOLIB + + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(unsigned int gpio) +{ + return au1300_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned int gpio, int v) +{ + return au1300_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(unsigned int gpio) +{ + return au1300_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int v) +{ + au1300_gpio_set_value(gpio, v); +} + +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + +static inline int gpio_is_valid(unsigned int gpio) +{ + return au1300_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(unsigned int gpio) +{ + return au1300_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned int gpio) +{ + return au1300_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return au1300_irq_to_gpio(irq); +} + +static inline int gpio_request(unsigned int gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned int gpio) +{ +} + +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#else /* CONFIG GPIOLIB */ + + +/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */ +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */ + +/* get everything through gpiolib */ +#define gpio_to_irq __gpio_to_irq +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define irq_to_gpio au1300_irq_to_gpio + +#include + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#endif /* !CONFIG_GPIOLIB */ + +#endif /* _GPIO_AU1300_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index c3f60cd..4d6edea 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -5,6 +5,10 @@ #include +#elif defined(CONFIG_ALCHEMY_GPIOINT_AU1300) + +#include + #endif #endif /* _ALCHEMY_GPIO_H_ */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b1b304e..b456e89 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -854,6 +854,21 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_rmi(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_AU13XX: + c->cputype = CPU_ALCHEMY; + __cpu_name[cpu] = "Au13xx"; + break; + default: + panic("Unknown RMI core!\n"); + break; + } +} + static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); @@ -1011,6 +1026,9 @@ __cpuinit void cpu_probe(void) case PRID_COMP_NXP: cpu_probe_nxp(c, cpu); break; + case PRID_COMP_RMI: + cpu_probe_rmi(c, cpu); + break; case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 6539ac2..17afff8 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -296,11 +296,11 @@ config I2C_AT91 unless your system can cope with those limitations. config I2C_AU1550 - tristate "Au1550/Au1200 SMBus interface" - depends on SOC_AU1550 || SOC_AU1200 + tristate "Au1550/Au1200/Au1300 SMBus interface" + depends on SOC_AU1550 || SOC_AU1200 || SOC_AU1300 help If you say yes to this option, support will be included for the - Au1550 and Au1200 SMBus interface. + Au1550/Au1200/Au1300 SMBus interface. This driver can also be built as a module. If so, the module will be called i2c-au1550. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 91c2f4f..c48908a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -68,7 +68,7 @@ config SPI_BFIN config SPI_AU1550 tristate "Au1550/Au12x0 SPI Controller" - depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL + depends on (SOC_AU1550 || SOC_AU1200 || SOC_AU1300) && EXPERIMENTAL select SPI_BITBANG help If you say yes to this option, support will be included for the diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 8b31fdf..ee23979 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1711,14 +1711,14 @@ config FB_AU1100 config FB_AU1200 bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 + depends on (FB = y) && MIPS && (SOC_AU1200 || SOC_AU1300) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT help - This is the framebuffer driver for the AMD Au1200 SOC. It can drive - various panels and CRTs by passing in kernel cmd line option - au1200fb:panel=. + This is the framebuffer driver for the AMD Au1200/Au1300 SOCs. + It can drive various panels and CRTs by passing in kernel cmd line + option au1200fb:panel=. source "drivers/video/geode/Kconfig" diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 4b67140..09a7216 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -2,12 +2,12 @@ ## Au1200/Au1550 PSC + DBDMA ## config SND_SOC_AU1XPSC - tristate "SoC Audio for Au1200/Au1250/Au1550" - depends on SOC_AU1200 || SOC_AU1550 + tristate "SoC Audio for Au12xx/Au13xx0/Au1550" + depends on SOC_AU1200 || SOC_AU1550 || SOC_AU1300 help This option enables support for the Programmable Serial Controllers in AC97 and I2S mode, and the Descriptor-Based DMA - Controller (DBDMA) as found on the Au1200/Au1250/Au1550 SoC. + Controller (DBDMA) as found on the Au12xx/Au13xx/Au1550 SoC. config SND_SOC_AU1XPSC_I2S tristate -- 1.7.2 From manuel.lauss@googlemail.com Fri Aug 27 17:57:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Aug 2010 17:57:13 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:51968 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491821Ab0H0P4P (ORCPT ); Fri, 27 Aug 2010 17:56:15 +0200 Received: by mail-bw0-f49.google.com with SMTP id 13so2526676bwz.36 for ; Fri, 27 Aug 2010 08:56:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=U7KkxAfeabouqLXlQvhI2/tyILAmo6Rbk42qYs1JLV8=; b=LnBTZv6OpLYBakl+q2gdvNZ2YtqgSHy0Q4WGr8pKyODBDvPGHuZu+mT+RVKi0ZeOhE EwUkHcSIFvgtSFwsHY9QSisNBl72hAilBK6zvYc6puMWw6LkZCiiROuO70QN3mvgFe9r t/lTzi8m5sJ/esOf4OXBPIIOuizra5zM8yE+g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=IlNRKsYApSry+qRNF3I9jtceTqZ4mWvpU0hEXxNxX6O1+M7x0WNwENJ0IgXFqC0ZYy JQsby2/jqyjRLj3YDNb2uRvyBxr+O+R3vZLGCg/0P9W+QJcd3uGyszlQS2Q87wP7gNJX oDJkZ7mCvYvycLAYinvXPkvlDGvYVj/MmpxJU= Received: by 10.204.60.133 with SMTP id p5mr655967bkh.71.1282924575275; Fri, 27 Aug 2010 08:56:15 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id 24sm2683051bkr.19.2010.08.27.08.56.13 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 27 Aug 2010 08:56:13 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH 2/2] MIPS: Alchemy: DB1300 support Date: Fri, 27 Aug 2010 17:56:05 +0200 Message-Id: <1282924565-16024-3-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.2 In-Reply-To: <1282924565-16024-1-git-send-email-manuel.lauss@googlemail.com> References: <1282924565-16024-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27684 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Basic support for the DB1300 board. Signed-off-by: Manuel Lauss --- What works: - Ethernet, PCMCIA, serial ports, IDE connector (PIO only), NOR/NAND flashes, the 5-way switch, RTC, I2C. - Both AC97 and I2S also work, but depend on the ASoC multi-component work scheduled for 2.6.37. A separate patch will be sent in time. - other stuff still missing (MMC/SD needs driver updates, USB requires new glue code, display untested but I see no reason why it should not work). arch/mips/alchemy/Kconfig | 8 + arch/mips/alchemy/Platform | 7 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300/Makefile | 1 + arch/mips/alchemy/devboards/db1300/platform.c | 605 +++++++++++++++++++++++++ arch/mips/alchemy/devboards/db1300/setup.c | 259 +++++++++++ arch/mips/alchemy/devboards/prom.c | 4 + arch/mips/boot/compressed/uart-alchemy.c | 5 +- arch/mips/configs/db1300_defconfig | 280 ++++++++++++ arch/mips/include/asm/mach-db1x00/bcsr.h | 5 +- arch/mips/include/asm/mach-db1x00/db1300.h | 40 ++ arch/mips/include/asm/mach-db1x00/irq.h | 23 + drivers/pcmcia/Kconfig | 4 +- drivers/pcmcia/db1xxx_ss.c | 30 +- 14 files changed, 1263 insertions(+), 9 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1300/Makefile create mode 100644 arch/mips/alchemy/devboards/db1300/platform.c create mode 100644 arch/mips/alchemy/devboards/db1300/setup.c create mode 100644 arch/mips/configs/db1300_defconfig create mode 100644 arch/mips/include/asm/mach-db1x00/db1300.h create mode 100644 arch/mips/include/asm/mach-db1x00/irq.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 21b232c..ec3a8c4 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -56,6 +56,14 @@ config MIPS_DB1200 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK +config MIPS_DB1300 + bool "RMI DB1300 board" + select SOC_AU1300 + select DMA_COHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + config MIPS_DB1500 bool "Alchemy DB1500 board" select SOC_AU1500 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 96e9e41..85699c7 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -75,6 +75,13 @@ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 # +# NetLogic DBAu1300 development platform +# +platform-$(CONFIG_MIPS_DB1300) += alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 + +# # AMD Alchemy Bosporus eval board # platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/ diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 826449c..18193c2 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ +obj-$(CONFIG_MIPS_DB1300) += db1300/ diff --git a/arch/mips/alchemy/devboards/db1300/Makefile b/arch/mips/alchemy/devboards/db1300/Makefile new file mode 100644 index 0000000..b07e182 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/Makefile @@ -0,0 +1 @@ +obj-y := setup.o platform.o diff --git a/arch/mips/alchemy/devboards/db1300/platform.c b/arch/mips/alchemy/devboards/db1300/platform.c new file mode 100644 index 0000000..745f715 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/platform.c @@ -0,0 +1,605 @@ +/* + * DBAu1300 platform initialization + * + * (c) 2009 Manuel Lauss + */ + +#include +#include +#include +#include /* KEY_* codes */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "../platform.h" + +static struct i2c_board_info db1300_i2c_devs[] __initdata = { + { + /* Philips NE1619 temp/voltage sensor (adm1025 drv) */ + I2C_BOARD_INFO("ne1619", 0x2d), + }, + { + /* I2S audio codec WM8731 */ + I2C_BOARD_INFO("wm8731", 0x1b), + }, +}; + +/**********************************************************************/ + +static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; + + ioaddr &= 0xffffff00; + + if (ctrl & NAND_CLE) { + ioaddr += MEM_STNAND_CMD; + } else if (ctrl & NAND_ALE) { + ioaddr += MEM_STNAND_ADDR; + } else { + /* assume we want to r/w real data by default */ + ioaddr += MEM_STNAND_DATA; + } + this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; + if (cmd != NAND_CMD_NONE) { + __raw_writeb(cmd, this->IO_ADDR_W); + wmb(); + } +} + +static int au1300_nand_device_ready(struct mtd_info *mtd) +{ + return __raw_readl((void __iomem *)MEM_STSTAT) & 1; +} + +static const char *db1300_part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition db1300_nand_parts[] = { + { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +struct platform_nand_data db1300_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(db1300_nand_parts), + .partitions = db1300_nand_parts, + .chip_delay = 20, + .part_probe_types = db1300_part_probes, + }, + .ctrl = { + .dev_ready = au1300_nand_device_ready, + .cmd_ctrl = au1300_nand_cmd_ctrl, + }, +}; + +static struct resource db1300_nand_res[] = { + [0] = { + .start = DB1300_NAND_PHYS_ADDR, + .end = DB1300_NAND_PHYS_ADDR + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1300_nand_dev = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(db1300_nand_res), + .resource = db1300_nand_res, + .id = -1, + .dev = { + .platform_data = &db1300_nand_platdata, + } +}; + +/**********************************************************************/ + +static struct resource db1300_eth_res[] = { + [0] = { + .start = DB1300_ETH_PHYS_ADDR, + .end = DB1300_ETH_PHYS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_ETH_INT, + .end = DB1300_ETH_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config db1300_eth_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device db1300_eth_dev = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(db1300_eth_res), + .resource = db1300_eth_res, + .dev = { + .platform_data = &db1300_eth_config, + }, +}; + +/**********************************************************************/ + +static struct resource au1300_psc1_res[] = { + [0] = { + .start = AU1300_PSC1_PHYS_ADDR, + .end = AU1300_PSC1_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC1_INT, + .end = AU1300_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC1_TX, + .end = DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC1_RX, + .end = DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_ac97_dev = { + .name = "au1xpsc_ac97", + .id = 1, + .num_resources = ARRAY_SIZE(au1300_psc1_res), + .resource = au1300_psc1_res, +}; + +/**********************************************************************/ + +static struct resource au1300_psc2_res[] = { + [0] = { + .start = AU1300_PSC2_PHYS_ADDR, + .end = AU1300_PSC2_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC2_INT, + .end = AU1300_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC2_TX, + .end = DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC2_RX, + .end = DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2s_dev = { + .name = "au1xpsc_i2s", + .id = 2, + .num_resources = ARRAY_SIZE(au1300_psc2_res), + .resource = au1300_psc2_res, +}; + +/**********************************************************************/ + +static struct resource au1300_psc3_res[] = { + [0] = { + .start = AU1300_PSC3_PHYS_ADDR, + .end = AU1300_PSC3_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC3_INT, + .end = AU1300_PSC3_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC3_TX, + .end = DSCR_CMD0_PSC3_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC3_RX, + .end = DSCR_CMD0_PSC3_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1300_psc3_res), + .resource = au1300_psc3_res, +}; + +/**********************************************************************/ + +/* key assignment according to db1300 schematic sheet #4 */ +static struct gpio_keys_button db1300_5waysw_buttons[] = { + { + .code = KEY_UP, + .gpio = AU1300_PIN_LCDPWM0, + .type = EV_KEY, + .debounce_interval = 1, + }, + { + .code = KEY_DOWN, + .gpio = AU1300_PIN_PSC2SYNC1, + .type = EV_KEY, + .debounce_interval = 1, + }, + { + .code = KEY_LEFT, + .gpio = AU1300_PIN_WAKE3, + .type = EV_KEY, + .debounce_interval = 1, + }, + { + .code = KEY_RIGHT, + .gpio = AU1300_PIN_WAKE2, + .type = EV_KEY, + .debounce_interval = 1, + }, + { + .code = KEY_ENTER, + .gpio = AU1300_PIN_WAKE1, + .type = EV_KEY, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data db1300_5waysw_data = { + .buttons = db1300_5waysw_buttons, + .nbuttons = ARRAY_SIZE(db1300_5waysw_buttons), + .rep = 1, +}; + +static struct platform_device db1300_5waysw_dev = { + .name = "gpio_keys", + .dev = { + .platform_data = &db1300_5waysw_data, + }, +}; + +/**********************************************************************/ + +static struct platform_device db1300_rtc_dev = { + .name = "rtc-au1xxx", + .id = -1, +}; + +/**********************************************************************/ + +static struct pata_platform_info db1300_ide_info = { + .ioport_shift = DB1300_IDE_REG_SHIFT, +}; + +#define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT) +static struct resource db1300_ide_res[] = { + [0] = { + .start = DB1300_IDE_PHYS_ADDR, + .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START, + .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = DB1300_IDE_INT, + .end = DB1300_IDE_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device db1300_ide_dev = { + .dev = { + .platform_data = &db1300_ide_info, + }, + .name = "pata_platform", + .resource = db1300_ide_res, + .num_resources = ARRAY_SIZE(db1300_ide_res), +}; + +/**********************************************************************/ + +/* same bugs as its 5-year-old predecessor, the db1200 */ +static irqreturn_t db1300_mmc_cd(int irq, void *ptr) +{ + void(*mmc_cd)(struct mmc_host *, unsigned long); + + if (irq == DB1300_SD1_INSERT_INT) { + disable_irq_nosync(DB1300_SD1_INSERT_INT); + enable_irq(DB1300_SD1_EJECT_INT); + } else { + disable_irq_nosync(DB1300_SD1_EJECT_INT); + enable_irq(DB1300_SD1_INSERT_INT); + } + + /* link against CONFIG_MMC=m */ + mmc_cd = symbol_get(mmc_detect_change); + if (mmc_cd) { + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + } + + return IRQ_HANDLED; +} + +static int db1300_mmc_cd_setup(void *mmc_host, int en) +{ + int ret; + + if (en) { + ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, + IRQF_DISABLED, "sd_insert", mmc_host); + if (ret) + goto out; + + ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, + IRQF_DISABLED, "sd_eject", mmc_host); + if (ret) { + free_irq(DB1300_SD1_INSERT_INT, mmc_host); + goto out; + } + + if (bcsr_read(BCSR_SIGSTAT) & (1 << 12)) + enable_irq(DB1300_SD1_EJECT_INT); + else + enable_irq(DB1300_SD1_INSERT_INT); + + } else { + free_irq(DB1300_SD1_INSERT_INT, mmc_host); + free_irq(DB1300_SD1_EJECT_INT, mmc_host); + } + ret = 0; +out: + return ret; +} + +static int db1300_mmc_card_readonly(void *mmc_host) +{ + return !!(bcsr_read(BCSR_STATUS) & (1 << 10)); +} + +static int db1300_mmc_card_inserted(void *mmc_host) +{ + return !!(bcsr_read(BCSR_SIGSTAT) & (1 << 12)); +} + +static void db1300_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); +} + +static struct led_classdev db1300_mmc_led = { + .brightness_set = db1300_mmcled_set, +}; + +struct au1xmmc_platform_data db1300_sd1_platdata = { + .cd_setup = db1300_mmc_cd_setup, + .card_inserted = db1300_mmc_card_inserted, + .card_readonly = db1300_mmc_card_readonly, + .led = &db1300_mmc_led, +}; + +static struct resource au1300_sd1_res[] = { + [0] = { + .start = AU1300_SD1_PHYS_ADDR, + .end = AU1300_SD1_PHYS_ADDR, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_SD1_INT, + .end = AU1300_SD1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX1, + .end = DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX1, + .end = DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_sd1_dev = { + .dev = { + .platform_data = &db1300_sd1_platdata, + }, + .name = "au1xxx-mmc", + .id = 1, + .resource = au1300_sd1_res, + .num_resources = ARRAY_SIZE(au1300_sd1_res), +}; + +/**********************************************************************/ + +static int db1300_movinand_inserted(void *mmc_host) +{ + return 1; /* it's soldered on */ +} + +static int db1300_movinand_readonly(void *mmc_host) +{ + return 0; +} + +static void db1300_movinand_led_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); +} + +static struct led_classdev db1300_movinand_led = { + .brightness_set = db1300_movinand_led_set, +}; + +struct au1xmmc_platform_data db1300_sd0_platdata = { + .card_inserted = db1300_movinand_inserted, + .card_readonly = db1300_movinand_readonly, + .led = &db1300_movinand_led, + .mask_host_caps = MMC_CAP_NEEDS_POLL, +}; + +static struct resource au1300_sd0_res[] = { + [0] = { + .start = AU1300_SD0_PHYS_ADDR, + .end = AU1300_SD0_PHYS_ADDR, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_SD0_INT, + .end = AU1300_SD0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX0, + .end = DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX0, + .end = DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_sd0_dev = { + .dev = { + .platform_data = &db1300_sd0_platdata, + }, + .name = "au1xxx-mmc", + .id = 0, + .resource = au1300_sd0_res, + .num_resources = ARRAY_SIZE(au1300_sd0_res), +}; + +/**********************************************************************/ + +static struct platform_device db1300_wm9715_dev = { + .name = "wm9712-codec", + .id = 1, /* ID of PSC with AC97 controller on it */ +}; + +/**********************************************************************/ + +static struct platform_device *db1300_devs[] = { + &db1300_eth_dev, + &db1300_i2c_dev, + &db1300_5waysw_dev, + &db1300_rtc_dev, + &db1300_nand_dev, + &db1300_ide_dev, + &db1300_sd0_dev, + &db1300_sd1_dev, + &db1300_ac97_dev, + &db1300_i2s_dev, + &db1300_wm9715_dev, +}; + +static int __init db1300_device_init(void) +{ + int swapped; + + /* MAC address is stored by YAMON */ + prom_get_ethernet_addr(&db1300_eth_config.mac[0]); + + i2c_register_board_info(0, db1300_i2c_devs, + ARRAY_SIZE(db1300_i2c_devs)); + + /* Audio PSC clock is supplied by codecs (PSC1, 2) */ + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); + /* I2C uses internal 48MHz EXTCLK1 */ + __raw_writel(PSC_SEL_CLK_INTCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + + db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, + PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, + PCMCIA_MEM_PHYS_ADDR, + PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, + PCMCIA_IO_PHYS_ADDR, + PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, + DB1300_CF_INT, + DB1300_CF_INSERT_INT, + 0, + DB1300_CF_EJECT_INT, + 1); /* regbits of socket 1 */ + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; + db1x_register_norflash(64 * 1024 * 1024, 2, swapped); + + return platform_add_devices(db1300_devs, ARRAY_SIZE(db1300_devs)); +} +device_initcall(db1300_device_init); + +/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ +int board_au1200fb_panel(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} diff --git a/arch/mips/alchemy/devboards/db1300/setup.c b/arch/mips/alchemy/devboards/db1300/setup.c new file mode 100644 index 0000000..b6ff01c --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/setup.c @@ -0,0 +1,259 @@ +/* + * DB1300 board setup + * + * Copyright (c) 2009 Manuel Lauss + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* multifunction pins to assign to GPIO controller */ +static int db1300_gpio_pins[] __initdata = { + AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1, + AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX, + AU1300_PIN_EXTCLK1, + + -1, /* terminator */ +}; + +/* multifunction pins to assign to device functions */ +static int db1300_dev_pins[] __initdata = { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0, + /* external clock sources for PSC0 */ + AU1300_PIN_EXTCLK0, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 30-31 */ + AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, + -1, /* terminator */ +}; + +static void __init db1300_gpio_config(void) +{ + int *i; + + i = &db1300_dev_pins[0]; + while (*i != -1) + au1300_pinfunc_to_dev(*i++); + + i = &db1300_gpio_pins[0]; + while (*i != -1) + au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */ + + au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); +} + +char *get_system_type(void) +{ + return "RMI DBAu1300 Development Platform"; +} + +static inline void enable_uart(unsigned long phys) +{ + void __iomem *addr = (void __iomem *)KSEG1ADDR(phys); + + /* reset, enable clock, deassert reset */ + __raw_writel(0, addr + 0x100); + wmb(); + __raw_writel(1, addr + 0x100); + wmb(); + __raw_writel(3, addr + 0x100); + wmb(); +} + +void __init board_setup(void) +{ + unsigned short whoami; + + db1300_gpio_config(); + bcsr_init(DB1300_BCSR_PHYS_ADDR, + DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "RMI DBAu1300 Development Platform.\n\t" + "BoardID %d CPLD Rev %d DCID %d\n", + BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), + BCSR_WHOAMI_DCID(whoami)); + + /* enable UARTs, YAMON only enables #2 */ + enable_uart(AU1300_UART0_PHYS_ADDR); + enable_uart(AU1300_UART1_PHYS_ADDR); + enable_uart(AU1300_UART3_PHYS_ADDR); +} + +/**********************************************************************/ + +/* + * This code, taken from the RMI sources, seems to be the only way to get + * the DB1300 CPLD irq multiplexer to work reliably under linux. + */ +static struct mutex __cscmtx; +static int __cscirq, __cscfirst, __cscusecnt; +static void __iomem *__bcsr_virt; + +static irqreturn_t db1300_csc_handler(int irq, void *dev_id) +{ + unsigned short bisr = __raw_readw(__bcsr_virt + BCSR_REG_INTSTAT); + + __raw_writew(bisr, __bcsr_virt + BCSR_REG_INTSTAT); + wmb(); + + for ( ; bisr; bisr &= bisr - 1) + generic_handle_irq(__cscfirst + __ffs(bisr)); + + return IRQ_HANDLED; +} +static void db1300_csc_mask(unsigned int irq) +{ + __raw_writew(1 << (irq - __cscfirst), __bcsr_virt + BCSR_REG_MASKCLR); + wmb(); +} + +static void db1300_csc_unmask(unsigned int irq) +{ + __raw_writew(1 << (irq - __cscfirst), __bcsr_virt + BCSR_REG_MASKSET); + wmb(); +} + +static void db1300_csc_enable(unsigned int irq) +{ + __raw_writew(1 << (irq - __cscfirst), __bcsr_virt + BCSR_REG_INTSET); + db1300_csc_unmask(irq); +} + +static void db1300_csc_disable(unsigned int irq) +{ + __raw_writew(1 << (irq - __cscfirst), __bcsr_virt + BCSR_REG_INTCLR); + db1300_csc_mask(irq); +} + +static unsigned int db1300_csc_startup(unsigned int irq) +{ + int retval = 0; + + mutex_lock(&__cscmtx); + if ((++__cscusecnt) == 1) + retval = request_irq(__cscirq, &db1300_csc_handler, + IRQF_TRIGGER_HIGH, "csc", 0); + mutex_unlock(&__cscmtx); + + db1300_csc_enable(irq); + db1300_csc_unmask(irq); + + return retval; +} + +static void db1300_csc_shutdown(unsigned int irq) +{ + db1300_csc_mask(irq); + db1300_csc_disable(irq); + + mutex_lock(&__cscmtx); + if ((--__cscusecnt) == 0) + free_irq(__cscirq, &db1300_csc_handler); + mutex_unlock(&__cscmtx); +} + +static struct irq_chip db1300_csc_irq_type = { + .name = "DB1300", + .startup = db1300_csc_startup, + .shutdown = db1300_csc_shutdown, + .mask = db1300_csc_mask, + .enable = db1300_csc_enable, + .disable = db1300_csc_disable, + .unmask = db1300_csc_unmask, + .mask_ack = db1300_csc_mask +}; + +static void __init db1300_init_irq(int first, int last, int csc) +{ + int irq; + + __bcsr_virt = (void __iomem *)KSEG1ADDR(DB1300_BCSR_PHYS_ADDR); + __cscirq = csc; + __cscfirst = first; + mutex_init(&__cscmtx); + + __raw_writew(0xffff, __bcsr_virt + BCSR_REG_INTCLR); + __raw_writew(0xffff, __bcsr_virt + BCSR_REG_MASKCLR); + __raw_writew(0xffff, __bcsr_virt + BCSR_REG_INTSTAT); + wmb(); + + for (irq = first; irq <= last; irq++) { + set_irq_chip_and_handler(irq, &db1300_csc_irq_type, + handle_level_irq); + db1300_csc_disable(irq); + } +} + + +static int __init db1300_arch_init(void) +{ + int cpldirq; + + cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); + + set_irq_type(cpldirq, IRQF_TRIGGER_HIGH); + au1300_set_irq_priority(cpldirq, 3); + + db1300_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); + + /* insert/eject IRQs: one always triggers so don't enable them + * when doing request_irq() on them. DB1200 has this bug too. + */ + irq_to_desc(DB1300_SD1_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1300_SD1_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1300_CF_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1300_CF_EJECT_INT)->status |= IRQ_NOAUTOEN; + + return 0; +} +arch_initcall(db1300_arch_init); diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index b30df5c..80aef08 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -63,5 +63,9 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else alchemy_uart_putchar(UART0_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c index 1bff22f..e7b1150 100644 --- a/arch/mips/boot/compressed/uart-alchemy.c +++ b/arch/mips/boot/compressed/uart-alchemy.c @@ -2,6 +2,9 @@ void putc(char c) { - /* all current (Jan. 2010) in-kernel boards */ +#ifndef CONFIG_MIPS_DB1300 alchemy_uart_putchar(UART0_PHYS_ADDR, c); +#else + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig new file mode 100644 index 0000000..a11be75 --- /dev/null +++ b/arch/mips/configs/db1300_defconfig @@ -0,0 +1,280 @@ +CONFIG_MIPS=y +CONFIG_MIPS_ALCHEMY=y +CONFIG_ALCHEMY_GPIOINT_AU1300=y +CONFIG_MIPS_DB1300=y +CONFIG_SOC_AU1300=y +CONFIG_LOONGSON_UART_BASE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +CONFIG_GENERIC_GPIO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_CPU_MIPS32_R1=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_32BIT=y +CONFIG_PAGE_SIZE_4KB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_LZMA=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_TINY_RCU=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_SLAB=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_BLOCK=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_INLINE_SPIN_UNLOCK=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_MMU=y +CONFIG_PCCARD=y +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y +CONFIG_BINFMT_ELF=y +CONFIG_TRAD_SIGNALS=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_LRO=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_HAVE_IDE=y +CONFIG_IDE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +CONFIG_BLK_DEV_IDECS=y +CONFIG_IDE_TASK_IOCTL=y +CONFIG_BLK_DEV_PLATFORM=y +CONFIG_SCSI_MOD=y +CONFIG_NETDEVICES=y +CONFIG_PHYLIB=y +CONFIG_SMSC_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMSC911X=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_AU1550=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +CONFIG_SENSORS_ADM1025=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_DRV_AU1XXX=y +CONFIG_EXT2_FS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FAT_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS2,115200" +CONFIG_DEBUG_ZBOOT=y +CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC32=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 618d2de..c8d9820 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -34,6 +34,8 @@ #define PB1200_BCSR_PHYS_ADDR 0x0D800000 #define PB1200_BCSR_HEXLED_OFS 0x00400000 +#define DB1300_BCSR_PHYS_ADDR 0x19800000 +#define DB1300_BCSR_HEXLED_OFS 0x00400000 enum bcsr_id { /* BCSR base 1 */ @@ -105,6 +107,7 @@ enum bcsr_whoami_boards { BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, BCSR_WHOAMI_PB1200_DDR2, BCSR_WHOAMI_DB1200, + BCSR_WHOAMI_DB1300, }; /* STATUS reg. Unless otherwise noted, they're valid on all boards. @@ -118,7 +121,7 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_SRAMWIDTH 0x0080 #define BCSR_STATUS_FLASHBUSY 0x0100 #define BCSR_STATUS_ROMBUSY 0x0400 -#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ +#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */ #define BCSR_STATUS_SD1WP 0x0800 #define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ #define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h new file mode 100644 index 0000000..7fe5fb3 --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/db1300.h @@ -0,0 +1,40 @@ +/* + * NetLogic DB1300 board constants + */ + +#ifndef _DB1300_H_ +#define _DB1300_H_ + +/* FPGA (external mux) interrupt sources */ +#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1) +#define DB1300_IDE_INT (DB1300_FIRST_INT + 0) +#define DB1300_ETH_INT (DB1300_FIRST_INT + 1) +#define DB1300_CF_INT (DB1300_FIRST_INT + 2) +#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) +#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) +#define DB1300_DC_INT (DB1300_FIRST_INT + 6) +#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) +#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) +#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) +#define DB1300_AC97_INT (DB1300_FIRST_INT + 10) +#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) +#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) +#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) +#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) +#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) +#define DB1300_LAST_INT (DB1300_FIRST_INT + 15) + +/* SMSC9210 CS */ +#define DB1300_ETH_PHYS_ADDR 0x19000000 +#define DB1300_ETH_PHYS_END 0x197fffff + +/* ATA CS */ +#define DB1300_IDE_PHYS_ADDR 0x18800000 +#define DB1300_IDE_REG_SHIFT 5 +#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) + +/* NAND CS */ +#define DB1300_NAND_PHYS_ADDR 0x20000000 +#define DB1300_NAND_PHYS_END 0x20000fff + +#endif /* _DB1300_H_ */ diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h new file mode 100644 index 0000000..15b2669 --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/irq.h @@ -0,0 +1,23 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_IRQ_H +#define __ASM_MACH_GENERIC_IRQ_H + + +#ifdef NR_IRQS +#undef NR_IRQS +#endif + +#ifndef MIPS_CPU_IRQ_BASE +#define MIPS_CPU_IRQ_BASE 0 +#endif + +/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */ +#define NR_IRQS 152 + +#endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index c80a7a6..fb247b5 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -165,8 +165,8 @@ config PCMCIA_ALCHEMY_DEVBOARD select 64BIT_PHYS_ADDR help Enable this driver of you want PCMCIA support on your Alchemy - Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200 board. - NOT suitable for the PB1000! + Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200, DB1300 + board. NOT suitable for the PB1000! This driver is also available as a module called db1xxx_ss.ko diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c index 27575e63..7c9ce38 100644 --- a/drivers/pcmcia/db1xxx_ss.c +++ b/drivers/pcmcia/db1xxx_ss.c @@ -7,7 +7,7 @@ /* This is a fairly generic PCMCIA socket driver suitable for the * following Alchemy Development boards: - * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200. + * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200, Db1300 * * The Db1000 is used as a reference: Per-socket card-, carddetect- and * statuschange IRQs connected to SoC GPIOs, control and status register @@ -18,6 +18,7 @@ * - Pb1100/Pb1500: single socket only; voltage key bits VS are * at STATUS[5:4] (instead of STATUS[1:0]). * - Au1200-based: additional card-eject irqs, irqs not gpios! + * - Db1300: Db1200-like, no pwr ctrl, single socket (#1). */ #include @@ -58,11 +59,17 @@ struct db1x_pcmcia_sock { #define BOARD_TYPE_DEFAULT 0 /* most boards */ #define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */ #define BOARD_TYPE_PB1100 2 /* VS bits slightly different */ +#define BOARD_TYPE_DB1300 3 /* no power control */ int board_type; }; #define to_db1x_socket(x) container_of(x, struct db1x_pcmcia_sock, socket) +static int db1300_card_inserted(struct db1x_pcmcia_sock *sock) +{ + return bcsr_read(BCSR_SIGSTAT) & (1 << 8); +} + /* DB/PB1200: check CPLD SIGSTATUS register bit 10/12 */ static int db1200_card_inserted(struct db1x_pcmcia_sock *sock) { @@ -83,6 +90,8 @@ static int db1x_card_inserted(struct db1x_pcmcia_sock *sock) switch (sock->board_type) { case BOARD_TYPE_DB1200: return db1200_card_inserted(sock); + case BOARD_TYPE_DB1300: + return db1300_card_inserted(sock); default: return db1000_card_inserted(sock); } @@ -159,7 +168,8 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) * ejection handler have been registered and the currently * active one disabled. */ - if (sock->board_type == BOARD_TYPE_DB1200) { + if ((sock->board_type == BOARD_TYPE_DB1200) || + (sock->board_type == BOARD_TYPE_DB1300)) { ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq, IRQF_DISABLED, "pcmcia_insert", sock); if (ret) @@ -173,7 +183,7 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) } /* enable the currently silent one */ - if (db1200_card_inserted(sock)) + if (db1x_card_inserted(sock)) enable_irq(sock->eject_irq); else enable_irq(sock->insert_irq); @@ -269,7 +279,8 @@ static int db1x_pcmcia_configure(struct pcmcia_socket *skt, } /* create new voltage code */ - cr_set |= ((v << 2) | p) << (sock->nr * 8); + if (sock->board_type != BOARD_TYPE_DB1300) + cr_set |= ((v << 2) | p) << (sock->nr * 8); changed = state->flags ^ sock->old_flags; @@ -319,7 +330,7 @@ static int db1x_pcmcia_get_status(struct pcmcia_socket *skt, unsigned short cr, sr; unsigned int status; - status = db1x_card_inserted(sock) ? SS_DETECT : 0; + status = 0; cr = bcsr_read(BCSR_PCMCIA); sr = bcsr_read(BCSR_STATUS); @@ -342,6 +353,12 @@ static int db1x_pcmcia_get_status(struct pcmcia_socket *skt, /* if Vcc is not zero, we have applied power to a card */ status |= GET_VCC(cr, sock->nr) ? SS_POWERON : 0; + /* DB1300: power is always on */ + if (sock->board_type == BOARD_TYPE_DB1300) + status = SS_POWERON | SS_3VCARD; + + status |= db1x_card_inserted(sock) ? SS_DETECT : 0; + /* reset de-asserted? then we're ready */ status |= (GET_RESET(cr, sock->nr)) ? SS_READY : SS_RESET; @@ -418,6 +435,9 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev) case BCSR_WHOAMI_PB1200 ... BCSR_WHOAMI_DB1200: sock->board_type = BOARD_TYPE_DB1200; break; + case BCSR_WHOAMI_DB1300: + sock->board_type = BOARD_TYPE_DB1300; + break; default: printk(KERN_INFO "db1xxx-ss: unknown board %d!\n", bid); ret = -ENODEV; -- 1.7.2 From wuzhangjin@gmail.com Fri Aug 27 18:49:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Aug 2010 18:49:27 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:48416 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490969Ab0H0QtW (ORCPT ); Fri, 27 Aug 2010 18:49:22 +0200 Received: by wyb38 with SMTP id 38so2323258wyb.36 for ; Fri, 27 Aug 2010 09:49:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=xM5wn/7XOFNWGWCPCb6J7RfrXHm+hXhDm4M9hRUfej0=; b=Ai3Z9dmEvYHsE/8EI13bn6Axr718404iD74wnzngJOzLI54roTPEAFYjipMLKZ27dC YB3XVhlWdVes1u3EV5Luks/yq8jgJonZKuNCdPlFcVJVayIjq0X+C2GPAhaC3KM+mK/y gPR4QncKuvgMT7EiGawn6pUPDz4+r4cUtRWnk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=AkhOpR0Z0du9t/9+sOoUbgDj9Hq/Auvdy9N9jSBrOjFhg0ZWV8W6XHop/ORbz8tx42 bsbOr7CBCie1TMZHUXeYhERgE7Jev2YOUKNU0nAh4Kr9oe7YkKex9jwDwQlcJfzEkfZA C6uM/onMGCfhsKcAsYEUO6rwy3DLxTdh+Vjp0= MIME-Version: 1.0 Received: by 10.227.142.8 with SMTP id o8mr989100wbu.16.1282927750555; Fri, 27 Aug 2010 09:49:10 -0700 (PDT) Received: by 10.216.166.69 with HTTP; Fri, 27 Aug 2010 09:49:10 -0700 (PDT) In-Reply-To: <1282630011-23348-1-git-send-email-wuzhangjin@gmail.com> References: <1282630011-23348-1-git-send-email-wuzhangjin@gmail.com> Date: Sat, 28 Aug 2010 00:49:10 +0800 Message-ID: Subject: Re: [PATCH] tracing/ftrace: Fix the potential hang on MIPS SMP From: wu zhangjin To: Ralf Baechle , Steven Rostedt , David Daney Cc: linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27685 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, This is not applicable, a revision with the new flag machine_stop_pending instead of machine_stopped will be sent out tomorrow. Regards, Wu Zhangjin On 8/24/10, Wu Zhangjin wrote: > From: Wu Zhangjin > > In Ftrace, we need to flush the icache after code modification to ensure > the instructions will be executed are exactly what we want. > > And for the following reason(arch/x86/kernel/ftrace.c): > > * Modifying code must take extra care. On an SMP machine, if > * the code being modified is also being executed on another CPU > * that CPU will have undefined results and possibly take a GPF. > * We use kstop_machine to stop other CPUS from exectuing code. > > In SMP, the code modification are protected by stop_machine(), which > will disables the irqs of all cpus and then modify the code, flush the > icache. > > In MIPS SMP, to tell the other cpus to flush their related icache, the > IPI interrupt must be sent to them and wait for them exiting from the > icache flushing, but for the stop_machine() have disabled interrupts, it > will need to wait for the other cpus all the time, then deadlock -> > hang. > > (Note: cavium is an exception, benefit from its synci instruction, it > doesn't call smp_call_function() to execute the icache flushing > operation but send the ICACHE_FLUSH ipi to the other cpus directly, so, > no wait and no hang on cavium, and after the irqs of the cpus are > enabled, the pending icache flush interrupt will be filed and synci will > flush the icache on every cpu respectively, so, no cache problem). > > To break this deadlock, the key is: stop calling flush_icache_range() in > stop_machine() but delay it after stop_machine(). delaying the icache > flushing operation doesn't influence the tracing results even if the > other cpus execute the code just modified before the icache flushing, > for the kernel tracing will only be enabled after users issuing: > > $ echo 1 > /path/to/tracing/tracing_enabled > > Thanks to the weak functions: ftrace_arch_code_modify_prepare() and > ftrace_arch_code_modify_post_process(). they are called by > ftrace_run_update_code() before and after stop_machine() respectively, > with them, ftrace_modify_code() can check whether it is called in > stop_machine() and if called in stop_machine(), then delay the operation > of icache flushing, as a result, the deadlock is broken. > > Without this patch, Ftrace for RMI XLS will hang after issuing the > following command: > > $ echo function > /path/to/tracing/current_tracer > > Exactly, it hangs on kernel/smp.c: > > void smp_call_function_many(const struct cpumask *mask, > { > [snip] > /* > * Can deadlock when called with interrupts disabled. > * We allow cpu's that are not yet online though, as no one else can > * send smp call function interrupt to this cpu and as such deadlocks > * can't happen. > */ > WARN_ON_ONCE(cpu_online(this_cpu) && irqs_disabled() > && !oops_in_progress); > [snip] > csd_lock(&data->csd); > > [snip] > /* Send a message to all CPUs in the map */ > arch_send_call_function_ipi_mask(data->cpumask); > > /* Optionally wait for the CPUs to complete */ > if (wait) > csd_lock_wait(&data->csd); --> hang here > } > > Signed-off-by: Wu Zhangjin > --- > arch/mips/kernel/ftrace.c | 22 +++++++++++++++++++++- > 1 files changed, 21 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c > index 5a84a1f..c8ebb13 100644 > --- a/arch/mips/kernel/ftrace.c > +++ b/arch/mips/kernel/ftrace.c > @@ -69,6 +69,23 @@ static inline void ftrace_dyn_arch_init_insns(void) > #endif > } > > +#ifdef CONFIG_SMP > +static int machine_stopped __read_mostly; > + > +int ftrace_arch_code_modify_prepare(void) > +{ > + machine_stopped = 1; > + return 0; > +} > + > +int ftrace_arch_code_modify_post_process(void) > +{ > + __flush_cache_all(); > + machine_stopped = 0; > + return 0; > +} > +#endif > + > static int ftrace_modify_code(unsigned long ip, unsigned int new_code) > { > int faulted; > @@ -79,7 +96,10 @@ static int ftrace_modify_code(unsigned long ip, unsigned > int new_code) > if (unlikely(faulted)) > return -EFAULT; > > - flush_icache_range(ip, ip + 8); > +#ifdef CONFIG_SMP > + if (!machine_stopped) > +#endif > + flush_icache_range(ip, ip + 8); > > return 0; > } > -- > 1.7.0.4 > > > From wuzhangjin@gmail.com Fri Aug 27 19:09:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Aug 2010 19:09:05 +0200 (CEST) Received: from mail-ww0-f43.google.com ([74.125.82.43]:40423 "EHLO mail-ww0-f43.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491809Ab0H0RJC (ORCPT ); Fri, 27 Aug 2010 19:09:02 +0200 Received: by wwb31 with SMTP id 31so3332049wwb.24 for ; Fri, 27 Aug 2010 10:08:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=IkzR1g3GJQH2W5VUflNaY7sfDl5G3/JKO9GyPuC92cc=; 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