From dvomlehn@cisco.com Thu Jul 1 00:01:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Jul 2010 00:01:37 +0200 (CEST) Received: from sj-iport-4.cisco.com ([171.68.10.86]:25707 "EHLO sj-iport-4.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492021Ab0F3WBb (ORCPT ); Thu, 1 Jul 2010 00:01:31 +0200 Authentication-Results: sj-iport-4.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAABcK0yrR7H+/2dsb2JhbACfVXGldppDhSUEg2w X-IronPort-AV: E=Sophos;i="4.53,515,1272844800"; d="scan'208";a="152205575" Received: from sj-core-2.cisco.com ([171.71.177.254]) by sj-iport-4.cisco.com with ESMTP; 30 Jun 2010 22:01:24 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-2.cisco.com (8.13.8/8.14.3) with ESMTP id o5UM1Ogv010968; Wed, 30 Jun 2010 22:01:24 GMT Date: Wed, 30 Jun 2010 15:01:24 -0700 From: David VomLehn To: Shinya Kuribayashi Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required Message-ID: <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> References: <4C2755A3.3080600@pobox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C2755A3.3080600@pobox.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27291 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Sun, Jun 27, 2010 at 08:44:03AM -0500, Shinya Kuribayashi wrote: > fls()/__fls() defined at , doesn't use CLZ unless it's > explicitly requested via . In other words, > as long as depending on cpu_data[0].isa_level, CLZ is nerver used for > fls()/__fls(). ... > It's MIPS32 machine and luckily clz() is left there, then let's go back > to the original shape. > > Signed-off-by: Shinya Kuribayashi Thanks! You are correct in your analysis and make a good point that clz should be used in interrupt handling. I think, though, that it's better to go ahead and supply a full-blown cpu-features-override.h rather than focusing on this one case. This way fls() will be optimized to use clz everywhere and any other optimizations that depend on constant cpu_has_* values will also be used. The following patch provides cpu-features-override.h and removes the unused clz() function in asic_int.c. Signed-off-by: David VomLehn --- .../asm/mach-powertv/cpu-feature-overrides.h | 59 ++++++++++++++++++++ arch/mips/powertv/asic/asic_int.c | 13 ---- 2 files changed, 59 insertions(+), 13 deletions(-) diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h new file mode 100644 index 0000000..f751e3e --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2010 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ +#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_vint 1 +#define cpu_has_veic 1 +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#endif diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c index 529c44a..7362f63 100644 --- a/arch/mips/powertv/asic/asic_int.c +++ b/arch/mips/powertv/asic/asic_int.c @@ -68,19 +68,6 @@ static void asic_irqdispatch(void) do_IRQ(irq); } -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - /* * Version of ffs that only looks at bits 12..15. */ From macro@linux-mips.org Thu Jul 1 00:13:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Jul 2010 00:13:55 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:50712 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492375Ab0F3WNu (ORCPT ); Thu, 1 Jul 2010 00:13:50 +0200 Date: Wed, 30 Jun 2010 23:13:50 +0100 (BST) From: "Maciej W. Rozycki" To: David VomLehn cc: Phil Staub , Adam Jiang , linux-mips@linux-mips.org Subject: Re: How to detect STACKOVEFLOW on mips In-Reply-To: <20100630181627.GB20597@dvomlehn-lnx2.corp.sa.net> Message-ID: References: <4C2B543E.2010309@windriver.com> <20100630181627.GB20597@dvomlehn-lnx2.corp.sa.net> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27292 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, 30 Jun 2010, David VomLehn wrote: > > How about something like: > > > > { > > long x; > > ... > > asm("move %0,$29":"=g"(x)); > > ... > > } > > Depending on the version of gcc you are using, you should also be able > to use __builtin_frame_address(), though I haven't tried this in the kernel. It works just fine with a zero argument; the usual restrictions apply to non-zero arguments. Or alternatively an explicit register variable will do as suggested by Ralf. Both approaches result in a bit better code than an explicit move; the former is portable to other platforms even. :) Maciej From mlistz@gmail.com Thu Jul 1 07:47:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Jul 2010 07:47:28 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:47739 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491015Ab0GAFrX (ORCPT ); Thu, 1 Jul 2010 07:47:23 +0200 Received: by vws8 with SMTP id 8so2237582vws.36 for ; Wed, 30 Jun 2010 22:47:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:cc:content-type; bh=NF8o0SiUcJbJFHhmvKkt2Wkr6dNXin7/5mpXXn3y3Qw=; b=fHrpdtuyYpVMSKx42hUcwe49DkBRVBDiGedQYCZtaOqcetTHYVyyc/lF+Yjtx51elZ PdXEq5mLxQDx0VHQSKcauPG8DqOh4zGVd/5TBxcI7Z7oTosrDF5ja1nYfa6bQ+F9Yco8 +yVcO21sqNTD8+RkgObyW67VExC2WxIW32LS4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; b=ISKt61eTiMB8ABIiGnPNW/0DA4Iz905pv7qqV00Gy2NW80Eb66822zQWp019PLcAOi KtfpVD21IvZXKe7aXJUUgZurFFHA+rgXwsPKBzh2i1YgrdHniN217MVzY8BuIMZXXtaQ aoYxJW20mhojYM+W3Po0Q0m7jCpnxTWFIlDGc= MIME-Version: 1.0 Received: by 10.229.182.20 with SMTP id ca20mr5873890qcb.58.1277963236613; Wed, 30 Jun 2010 22:47:16 -0700 (PDT) Received: by 10.229.211.206 with HTTP; Wed, 30 Jun 2010 22:47:16 -0700 (PDT) Date: Thu, 1 Jul 2010 13:47:16 +0800 Message-ID: Subject: [Kernel Oops] Cavium Octeon, linux 2.6.34 From: Zhuang Yuyao To: linux-mips@linux-mips.org Cc: David Daney Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27293 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlistz@gmail.com Precedence: bulk X-list: linux-mips Hi, While the 2.6.34 kernel works fine on loading and running, but it emits oops everytime while rebooting. / # /sbin/reboot CPU 2 Unable to handle kernel paging request at virtual address 0000005781657c00, epc == ffffffff8115f290, ra == ffffffff8115f380 Oops[#1]: Cpu 2 $ 0 : 0000000000000000 0000000000000018 002bffffffc0af58 015ffffffe057ac0 $ 4 : ffffffe057afee00 0000000000000000 0000005781657c00 00000057ffffff80 $ 8 : 000000182f2de56b 0000000000000000 0000000000000001 0000000000008000 $12 : 0000000000000000 ffffffff81105d44 0000000000000000 0000000000000000 $16 : ffffffff815ebfb8 ffffffff815ec0a0 ffffffff815d0000 ffffffff815ec100 $20 : 0000000000000000 0000000000000000 0000000000000000 0000000000000000 $24 : 0000000000000000 ffffffff811152b8 $28 : a8000000bd180000 a8000000bd183dc0 0000000000000000 ffffffff8115f380 Hi : 0000000000000000 Lo : 0000000000000000 epc : ffffffff8115f290 bit_waitqueue+0x30/0xd0 Not tainted ra : ffffffff8115f380 wake_up_bit+0x18/0x38 Status: 10108ce3 KX SX UX KERNEL EXL IE Cause : 00800008 BadVA : 0000005781657c00 PrId : 000d0409 (Cavium Octeon+) Modules linked in: Process flush-mtd-unmap (pid: 1357, threadinfo=a8000000bd180000, task=a8000000d0256040, tls=0000000000000000) Stack : 0000000000000000 ffffffff815d0000 ffffffff815ebf90 ffffffff8119ce18 0000000000000000 a8000000d0cc7ca0 ffffffff8119cd90 ffffffff815ec0a0 0000000000000000 ffffffff8115eec0 00000000beb2b997 0000000041b4b962 00000000dead4ead ffffffffecbeaa23 ffffffffffffffff a8000000bd183e38 a8000000bd183e38 a8000000044e9200 0000000000000000 0000000000000000 0000000000000000 ffffffff81119348 a8000000044d9200 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 a8000000d0cc7ca0 ffffffff8115ee38 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ... Call Trace: [] bit_waitqueue+0x30/0xd0 [] wake_up_bit+0x18/0x38 [] bdi_start_fn+0x88/0x108 [] kthread+0x88/0x90 [] kernel_thread_helper+0x10/0x18 Code: 000219b8 00c7302d 000210f8 0062102f 2403fffc 24070680 00c31824 00a42025 Disabling lock debugging due to kernel taint Is it a known and fixed bug? Best regards, Zhuang Yuyao From lars@metafoo.de Thu Jul 1 17:46:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Jul 2010 17:46:42 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:43037 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491968Ab0GAPqf (ORCPT ); Thu, 1 Jul 2010 17:46:35 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 4D04F65A; Thu, 1 Jul 2010 17:46:30 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id WPN4xNeURDIx; Thu, 1 Jul 2010 17:46:29 +0200 (CEST) Received: from [172.31.16.228] (d079168.adsl.hansenet.de [80.171.79.168]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 561A4657; Thu, 1 Jul 2010 17:46:18 +0200 (CEST) Message-ID: <4C2CB835.5010106@metafoo.de> Date: Thu, 01 Jul 2010 17:45:57 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Andrew Morton CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Matt Fleming , linux-mmc@vger.kernel.org Subject: Re: [PATCH v3] MMC: Add JZ4740 mmc driver References: <1276924111-11158-19-git-send-email-lars@metafoo.de> <1277688041-23522-1-git-send-email-lars@metafoo.de> <20100630135525.1f6a9704.akpm@linux-foundation.org> In-Reply-To: <20100630135525.1f6a9704.akpm@linux-foundation.org> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27294 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi Andrew Morton wrote: > On Mon, 28 Jun 2010 03:20:41 +0200 > Lars-Peter Clausen wrote: > >> This patch adds support for the mmc controller on JZ4740 SoCs. >> >> Signed-off-by: Lars-Peter Clausen >> Cc: Andrew Morton >> Cc: Matt Fleming >> Cc: linux-mmc@vger.kernel.org >> >> ... >> >> +#define JZ4740_MMC_MAX_TIMEOUT 10000000 > > That was a really big timeout. How long do 1e7 readw's take? Oh well. > Hm, right. It doesn't hurt though. I'll do some tests and to try to come up with a more realistic value. >> ... >> >> +static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) >> +{ >> + uint32_t status; >> + >> + writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); >> + do { >> + status = readl(host->base + JZ_REG_MMC_STATUS); >> + } while (status & JZ_MMC_STATUS_CLK_EN); >> +} >> + >> +static void jz4740_mmc_reset(struct jz4740_mmc_host *host) >> +{ >> + uint32_t status; >> + >> + writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); >> + udelay(10); >> + do { >> + status = readl(host->base + JZ_REG_MMC_STATUS); >> + } while (status & JZ_MMC_STATUS_IS_RESETTING); >> +} > > Maybe these should have a timeout too? Its very unlikely that these will ever timeout. But right, to be on the safe, there should be a timeout as well. > >> ... >> >> +static inline unsigned int jz4740_mmc_wait_irq(struct jz4740_mmc_host *host, >> + unsigned int irq) >> +{ >> + unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT; >> + uint16_t status; >> + >> + do { >> + status = readw(host->base + JZ_REG_MMC_IREG); >> + } while (!(status & irq) && --timeout); >> + >> + return timeout; >> +} > > This guy's too big to inline. Recent gcc's know that and they tend to > uninline such things behind your back anwyay. Actually, even without the inline attribute and compiling with -Os gcc will inline this function by itself. > >> ... >> >> +struct jz4740_mmc_platform_data { >> + int gpio_power; >> + int gpio_card_detect; >> + int gpio_read_only; >> + unsigned card_detect_active_low:1; >> + unsigned read_only_active_low:1; >> + unsigned power_active_low:1; >> + >> + unsigned data_1bit:1; >> +}; > > The bitfields will all share the same word, so modification of one > field can race against modification of another field. Hence some form > of locking which covers *all* the bitfields is needed. > > Is that a problem in this driver? > They are all read-only in the driver. Thanks for reviewing the patch - - Lars -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkwsuDQACgkQBX4mSR26RiOiMACeMMNj4koCYFAUnxyM0LBr+wOZ x6oAnizk5CaAvZjQ2doXrD6ZYgDeNjSr =92D2 -----END PGP SIGNATURE----- From lars@metafoo.de Thu Jul 1 17:48:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Jul 2010 17:48:06 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:43127 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491945Ab0GAPsB (ORCPT ); Thu, 1 Jul 2010 17:48:01 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 7B73166A; Thu, 1 Jul 2010 17:47:56 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id pW4ovkHXKJBI; Thu, 1 Jul 2010 17:47:56 +0200 (CEST) Received: from [172.31.16.228] (d079168.adsl.hansenet.de [80.171.79.168]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 8796F669; Thu, 1 Jul 2010 17:47:55 +0200 (CEST) Message-ID: <4C2CB895.3030402@metafoo.de> Date: Thu, 01 Jul 2010 17:47:33 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Matt Fleming CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton , linux-mmc@vger.kernel.org, Ralf Baechle Subject: Re: [PATCH v3] MMC: Add JZ4740 mmc driver References: <1276924111-11158-19-git-send-email-lars@metafoo.de> <1277688041-23522-1-git-send-email-lars@metafoo.de> <87aaqd1tmr.fsf@linux-g6p1.site> In-Reply-To: <87aaqd1tmr.fsf@linux-g6p1.site> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27295 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Matt Fleming wrote: > On Mon, 28 Jun 2010 03:20:41 +0200, Lars-Peter Clausen wrote: >> This patch adds support for the mmc controller on JZ4740 SoCs. >> >> Signed-off-by: Lars-Peter Clausen >> Cc: Andrew Morton >> Cc: Matt Fleming >> Cc: linux-mmc@vger.kernel.org >> >> --- >> Changes since v1 >> - Do not request IRQ with IRQF_DISABLED since it is a noop now >> - Use a generous slack for the timeout timer. It does not need to be accurate. >> Changes since v2 >> - Use sg_mapping_to iterate over sg elements in mmc read and write functions >> - Use bitops instead of a spinlock and a variable for testing whether a request >> has been finished. >> - Rework irq and timeout handling in order to get rid of locking in hot paths > > Acked-by: Matt Fleming > > Are you planning on maintaining this driver? If so, it'd be a good idea > to update MAINTAINERS. Hi Thanks for reviewing the patch. I guess I should send a MAINTAINERS patch which adds entries for all of the JZ4740 drivers. - - Lars -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkwsuJUACgkQBX4mSR26RiNHVgCfTq+tc2I1QBniqijyUjNDxPIX GsEAn1xgPWz+L0uqHWthzJ+lMtFaUBtY =nVt9 -----END PGP SIGNATURE----- From dvomlehn@cisco.com Thu Jul 1 22:38:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Jul 2010 22:38:10 +0200 (CEST) Received: from sj-iport-4.cisco.com ([171.68.10.86]:17440 "EHLO sj-iport-4.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491129Ab0GAUiA (ORCPT ); Thu, 1 Jul 2010 22:38:00 +0200 Authentication-Results: sj-iport-4.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAIeZLEyrR7H+/2dsb2JhbACfb3GlN5o6hSUEg3E X-IronPort-AV: E=Sophos;i="4.53,522,1272844800"; d="scan'208";a="152728275" Received: from sj-core-2.cisco.com ([171.71.177.254]) by sj-iport-4.cisco.com with ESMTP; 01 Jul 2010 20:37:51 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-2.cisco.com (8.13.8/8.14.3) with ESMTP id o61Kbpfr020377; Thu, 1 Jul 2010 20:37:51 GMT Date: Thu, 1 Jul 2010 13:37:52 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Configuration changes to go along with simplified command line manipulation Message-ID: <20100701203751.GA870@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27296 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Additional changes to Youichi Yuasa's command line simplication code The PowerTV platform uses a non-standard way to get the kernel command line--we insert a built-in command line into arcs_cmdline and to get additional command line information from the bootloader via a pointer in the a1 register. It is necessary to insert a space between to the two strings or the last argument from arcs_cmdline and the first argument from the bootloader may be inadvertantly combined. It is also necessary to set CONFIG_CMDLINE_BOOL to "y" and to set the default command line to an empty string to get the simplified code to work properly in the PowerTV environment. Signed-off-by: David VomLehn diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig index 7291633..af0ab73 100644 --- a/arch/mips/configs/powertv_defconfig +++ b/arch/mips/configs/powertv_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.31-rc5 -# Fri Aug 28 14:49:33 2009 +# Linux kernel version: 2.6.35-rc3 +# Thu Jul 1 11:03:28 2010 # CONFIG_MIPS=y @@ -11,11 +11,12 @@ CONFIG_MIPS=y # CONFIG_MACH_ALCHEMY is not set # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set -# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set @@ -50,7 +51,6 @@ CONFIG_POWERTV=y # CONFIG_MIN_RUNTIME_RESOURCES is not set # CONFIG_BOOTLOADER_DRIVER is not set CONFIG_BOOTLOADER_FAMILY="R2" -CONFIG_CSRC_POWERTV=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set @@ -65,9 +65,9 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y +CONFIG_CSRC_POWERTV=y CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_EARLY_PRINTK is not set +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_SYS_HAS_EARLY_PRINTK=y # CONFIG_NO_IOPORT is not set CONFIG_CPU_BIG_ENDIAN=y @@ -79,7 +79,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y # CONFIG_CPU_MIPS64_R1 is not set @@ -122,7 +123,7 @@ CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -CONFIG_CPU_HAS_LLSC=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_MIPSR2_IRQ_VI=y CONFIG_CPU_MIPSR2_IRQ_EI=y CONFIG_CPU_HAS_SYNC=y @@ -144,8 +145,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y @@ -177,6 +177,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="mips-linux-" CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y # CONFIG_SWAP is not set @@ -190,19 +191,15 @@ CONFIG_SYSVIPC_SYSCTL=y # # RCU Subsystem # -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=16 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set CONFIG_RELAY=y # CONFIG_NAMESPACES is not set @@ -211,6 +208,7 @@ CONFIG_INITRAMFS_SOURCE="" # CONFIG_RD_GZIP is not set # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -234,18 +232,16 @@ CONFIG_SHMEM=y CONFIG_AIO=y # -# Performance Counters +# Kernel Performance Events And Counters # # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_PCI_QUIRKS=y # CONFIG_SLUB_DEBUG is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # @@ -253,7 +249,7 @@ CONFIG_HAVE_OPROFILE=y # # CONFIG_GCOV_KERNEL is not set # CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y @@ -271,15 +267,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" -# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # @@ -289,7 +311,6 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set @@ -318,7 +339,6 @@ CONFIG_NET=y # Networking options # CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set @@ -390,12 +410,26 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NF_CONNTRACK is not set CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set + +# +# Xtables targets +# # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set + +# +# Xtables matches +# # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DSCP is not set @@ -465,10 +499,13 @@ CONFIG_IP6_NF_FILTER=y # CONFIG_IP6_NF_RAW is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set +# CONFIG_L2TP is not set CONFIG_STP=y CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set @@ -526,10 +563,21 @@ CONFIG_NET_SCH_FIFO=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set +# CONFIG_CAIF is not set # # Device Drivers @@ -539,6 +587,7 @@ CONFIG_NET_SCH_FIFO=y # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y @@ -550,9 +599,9 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AR7_PARTS is not set @@ -568,6 +617,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set # CONFIG_MTD_OOPS is not set # @@ -611,11 +661,16 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_SM_COMMON is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_CAFE is not set # CONFIG_MTD_NAND_NANDSIM is not set @@ -641,6 +696,10 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set @@ -658,6 +717,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -693,64 +753,95 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# # CONFIG_SATA_AHCI is not set +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_SATA_INIC162X is not set # CONFIG_SATA_SIL24 is not set CONFIG_ATA_SFF=y -# CONFIG_SATA_SVW is not set + +# +# SFF controllers with custom DMA interface +# +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_SX4 is not set +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# # CONFIG_ATA_PIIX is not set # CONFIG_SATA_MV is not set # CONFIG_SATA_NV is not set -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set # CONFIG_SATA_PROMISE is not set -# CONFIG_SATA_SX4 is not set # CONFIG_SATA_SIL is not set # CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set # CONFIG_SATA_ULI is not set # CONFIG_SATA_VIA is not set # CONFIG_SATA_VITESSE is not set -# CONFIG_SATA_INIC162X is not set + +# +# PATA SFF controllers with BMDMA +# # CONFIG_PATA_ALI is not set # CONFIG_PATA_AMD is not set # CONFIG_PATA_ARTOP is not set # CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_ATP867X is not set # CONFIG_PATA_CMD64X is not set # CONFIG_PATA_CS5520 is not set # CONFIG_PATA_CS5530 is not set # CONFIG_PATA_CYPRESS is not set # CONFIG_PATA_EFAR is not set -# CONFIG_ATA_GENERIC is not set # CONFIG_PATA_HPT366 is not set # CONFIG_PATA_HPT37X is not set # CONFIG_PATA_HPT3X2N is not set # CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT821X is not set # CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set # CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_TRIFLEX is not set # CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_OLDPIIX is not set # CONFIG_PATA_NETCELL is not set # CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87410 is not set # CONFIG_PATA_NS87415 is not set -# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OLDPIIX is not set # CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_RDC is not set # CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set # CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_SIL680 is not set # CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set # CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_SCH is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_LEGACY is not set # CONFIG_MD is not set # CONFIG_FUSION is not set @@ -763,7 +854,7 @@ CONFIG_ATA_SFF=y # # -# See the help texts for more information. +# The newer stack is recommended. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set @@ -787,6 +878,7 @@ CONFIG_MII=y # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set # CONFIG_DNET is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set @@ -800,6 +892,7 @@ CONFIG_MII=y # CONFIG_NET_PCI is not set # CONFIG_B44 is not set # CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set # CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set @@ -829,6 +922,8 @@ CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set CONFIG_CHELSIO_T3_DEPENDS=y # CONFIG_CHELSIO_T3 is not set +CONFIG_CHELSIO_T4_DEPENDS=y +# CONFIG_CHELSIO_T4 is not set # CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set @@ -841,16 +936,12 @@ CONFIG_CHELSIO_T3_DEPENDS=y # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLCNIC is not set # CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_BE2NET is not set # CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set +# CONFIG_WLAN is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -864,6 +955,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y # CONFIG_USB_PEGASUS is not set CONFIG_USB_RTL8150=y # CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -873,6 +965,7 @@ CONFIG_USB_RTL8150=y # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -882,6 +975,7 @@ CONFIG_USB_RTL8150=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -913,6 +1007,7 @@ CONFIG_INPUT_EVDEV=y # CONFIG_VT is not set # CONFIG_DEVKMEM is not set # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # @@ -924,6 +1019,9 @@ CONFIG_INPUT_EVDEV=y # Non-8250 serial port support # # CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set @@ -934,6 +1032,7 @@ CONFIG_UNIX98_PTYS=y # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set # CONFIG_I2C is not set # CONFIG_SPI is not set @@ -945,7 +1044,6 @@ CONFIG_DEVPORT=y # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -953,20 +1051,14 @@ CONFIG_SSB_POSSIBLE=y # Sonics Silicon Backplane # # CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_SUPPORT is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # +# CONFIG_VGA_ARB is not set # CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set @@ -980,7 +1072,6 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y -# CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set # @@ -993,31 +1084,43 @@ CONFIG_USB_HIDDEV=y # # Special HID drivers # +# CONFIG_HID_3M_PCT is not set # CONFIG_HID_A4TECH is not set # CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set # CONFIG_HID_CYPRESS is not set # CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_KYE is not set # CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set # CONFIG_HID_PANTHERLORD is not set # CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set # CONFIG_HID_SAMSUNG is not set # CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set # CONFIG_HID_SUNPLUS is not set # CONFIG_HID_GREENASIA is not set # CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set # CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1032,7 +1135,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set # CONFIG_USB_MON is not set @@ -1050,6 +1152,7 @@ CONFIG_USB_EHCI_HCD=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set @@ -1133,6 +1236,7 @@ CONFIG_USB_SERIAL_CP210X=y # CONFIG_USB_SERIAL_NAVMAN is not set # CONFIG_USB_SERIAL_PL2303 is not set # CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set # CONFIG_USB_SERIAL_QUALCOMM is not set # CONFIG_USB_SERIAL_SPCP8X5 is not set # CONFIG_USB_SERIAL_HP4X is not set @@ -1146,6 +1250,8 @@ CONFIG_USB_SERIAL_CP210X=y # CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -1158,7 +1264,6 @@ CONFIG_USB_SERIAL_CP210X=y # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set @@ -1171,7 +1276,6 @@ CONFIG_USB_SERIAL_CP210X=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set # @@ -1189,10 +1293,6 @@ CONFIG_RTC_LIB=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -1214,6 +1314,7 @@ CONFIG_JBD=y # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set @@ -1274,6 +1375,7 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -1284,7 +1386,6 @@ CONFIG_CRAMFS=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y @@ -1299,6 +1400,7 @@ CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -1360,6 +1462,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set @@ -1393,15 +1496,25 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set # CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set @@ -1410,19 +1523,22 @@ CONFIG_FTRACE=y CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set # CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set +# CONFIG_EARLY_PRINTK is not set CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M" +CONFIG_CMDLINE="" # CONFIG_CMDLINE_OVERRIDE is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_RUNTIME_DEBUG is not set +# CONFIG_SPINLOCK_TEST is not set # # Security options @@ -1430,13 +1546,16 @@ CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10 # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # # Crypto core or helper # -# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y @@ -1479,11 +1598,13 @@ CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c index e18d25c..0aac039 100644 --- a/arch/mips/powertv/init.c +++ b/arch/mips/powertv/init.c @@ -117,8 +117,10 @@ void __init prom_init(void) board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; - if (prom_argc == 1) + if (prom_argc == 1) { + strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE); + } configure_platform(); prom_meminit(); From dediao@cisco.com Thu Jul 1 23:57:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Jul 2010 23:57:09 +0200 (CEST) Received: from rtp-iport-1.cisco.com ([64.102.122.148]:52017 "EHLO rtp-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491778Ab0GAV5B convert rfc822-to-8bit (ORCPT ); Thu, 1 Jul 2010 23:57:01 +0200 Authentication-Results: rtp-iport-1.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAJ2rLEytJV2d/2dsb2JhbACfcHGlC5o+hSUEg3GGXg X-IronPort-AV: E=Sophos;i="4.53,522,1272844800"; d="scan'208";a="127753751" Received: from rcdn-core-6.cisco.com ([173.37.93.157]) by rtp-iport-1.cisco.com with ESMTP; 01 Jul 2010 21:56:54 +0000 Received: from xbh-rcd-101.cisco.com (xbh-rcd-101.cisco.com [72.163.62.138]) by rcdn-core-6.cisco.com (8.14.3/8.14.3) with ESMTP id o61Lusx3031370; Thu, 1 Jul 2010 21:56:54 GMT Received: from xmb-rcd-208.cisco.com ([72.163.62.215]) by xbh-rcd-101.cisco.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 1 Jul 2010 16:56:54 -0500 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH] Apply kmap_high_get with MIPS Date: Thu, 1 Jul 2010 16:56:54 -0500 Message-ID: <7A9214B0DEB2074FBCA688B30B04400D0116BA36@XMB-RCD-208.cisco.com> In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] Apply kmap_high_get with MIPS Thread-Index: Acr9ycy17NGkqChPReO+gQqYaLC/oAbmU6Kw From: "Dezhong Diao (dediao)" To: "Kevin Cernekee" Cc: X-OriginalArrivalTime: 01 Jul 2010 21:56:54.0850 (UTC) FILETIME=[51B80A20:01CB1968] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27297 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dediao@cisco.com Precedence: bulk X-list: linux-mips The issue (addr == 0) you mentioned had been discussed before (http://www.linux-mips.org/archives/linux-mips/2008-03/msg00011.html). For some reasons, the solution couldn't be accepted. Since then, we haven't touched that function until the changes of "kmap_high_get" were involved. The changes we made in "__flush_dcache_page" (below) should fix the problem which has been resolved in ARM. Dezhong void __flush_dcache_page(struct page *page) { struct address_space *mapping = page_mapping(page); void *addr; /* If there is a temporary kernel mapping, i.e. if kmap_atomic was * used to map a page, we only need to flush the page. We can skip * the other work here because it won't be used in any other way. */ if (PageHighMem(page)) { addr = kmap_atomic_to_vaddr(page); if (addr != NULL) { flush_data_cache_page((unsigned long) addr); return; } } /* If page_mapping returned a non-NULL value, then the page is not * in the swap cache and it isn't anonymously mapped. If it's not * already mapped into user space, we can just set the dirty bit to * get the cache flushed later, if needed */ if (mapping && !mapping_mapped(mapping)) { SetPageDcacheDirty(page); return; } /* * We could delay the flush for the !page_mapping case too. But that * case is for exec env/arg pages and those are %99 certainly going to * get faulted into the tlb (and thus flushed) anyways. */ if (!PageHighMem(page)) { addr = page_address(page); flush_data_cache_page((unsigned long) addr); } else { if (!cpu_has_dc_aliases) { addr = kmap_high_get(page); if (addr) { /* The page has been kmapped */ flush_data_cache_page((unsigned long) addr); kunmap_high(page); } else { /* Alright, we need a temporary kernel mapping. Since we are on * a processor that has hardware to eliminate data cache * aliases, we don't have to get an address whose virtual index * into the cache that matches the index originally used to map * the page. This makes the task doable. */ addr = kmap_atomic(page, KM_MIPS_SYNC_PAGE); flush_data_cache_page((unsigned long) addr); kunmap_atomic(addr, KM_MIPS_SYNC_PAGE); } } else { /* Sorry, we may have data cache aliases, which means that we * have to be able to get a virtual address whose virtual index * into cache matches the index used to map this page. This is * hard and so, just like the hard problems in my Physics * classes, is left as an exercise for the reader. */ panic("Unable to flush page 0x%p on processor with data cache " "aliases\n", page); } } } From dediao@cisco.com Fri Jul 2 03:44:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Jul 2010 03:44:20 +0200 (CEST) Received: from rtp-iport-1.cisco.com ([64.102.122.148]:52643 "EHLO rtp-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492124Ab0GBBoQ convert rfc822-to-8bit (ORCPT ); Fri, 2 Jul 2010 03:44:16 +0200 Authentication-Results: rtp-iport-1.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAD/hLEytJV2Y/2dsb2JhbACfcXGkAJowhSUEg3GGXg X-IronPort-AV: E=Sophos;i="4.53,524,1272844800"; d="scan'208";a="127808520" Received: from rcdn-core-1.cisco.com ([173.37.93.152]) by rtp-iport-1.cisco.com with ESMTP; 02 Jul 2010 01:44:08 +0000 Received: from xbh-rcd-202.cisco.com (xbh-rcd-202.cisco.com [72.163.62.201]) by rcdn-core-1.cisco.com (8.14.3/8.14.3) with ESMTP id o621i892001454; Fri, 2 Jul 2010 01:44:08 GMT Received: from xmb-rcd-208.cisco.com ([72.163.62.215]) by xbh-rcd-202.cisco.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 1 Jul 2010 20:44:08 -0500 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH] Apply kmap_high_get with MIPS Date: Thu, 1 Jul 2010 20:44:07 -0500 Message-ID: <7A9214B0DEB2074FBCA688B30B04400D0116BADD@XMB-RCD-208.cisco.com> In-Reply-To: <7A9214B0DEB2074FBCA688B30B04400D0116BA36@XMB-RCD-208.cisco.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] Apply kmap_high_get with MIPS Thread-Index: Acr9ycy17NGkqChPReO+gQqYaLC/oAbmU6KwAAi/quA= From: "Dezhong Diao (dediao)" To: "Kevin Cernekee" Cc: X-OriginalArrivalTime: 02 Jul 2010 01:44:08.0510 (UTC) FILETIME=[100375E0:01CB1988] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27298 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dediao@cisco.com Precedence: bulk X-list: linux-mips In terms of my previous email, the changes are intended to be made in "__dma_sync_contiguous" so that "addr == 0" case can be satisfied. +static inline void __dma_sync_contiguous(struct page *page, + unsigned long offset, size_t size, enum dma_data_direction direction) +{ + unsigned long addr; + + if (!PageHighMem(page)) { + addr = (unsigned long)page_address(page) + offset; + __dma_sync_virtual(addr, size, direction); + } else { + addr = (unsigned long)kmap_high_get(page); + if (addr) { + addr += offset; + __dma_sync_virtual(addr, size, direction); + kunmap_high(page); + } else { + addr = (unsigned long)kmap_atomic(page, KM_MIPS_SYNC_PAGE); + flush_data_cache_page(addr + offset); + kunmap_atomic((void *)addr, KM_MIPS_SYNC_PAGE); + } + } +} + Dezhong -----Original Message----- From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Dezhong Diao (dediao) Sent: Thursday, July 01, 2010 2:57 PM To: Kevin Cernekee Cc: linux-mips@linux-mips.org Subject: RE: [PATCH] Apply kmap_high_get with MIPS The issue (addr == 0) you mentioned had been discussed before (http://www.linux-mips.org/archives/linux-mips/2008-03/msg00011.html). For some reasons, the solution couldn't be accepted. Since then, we haven't touched that function until the changes of "kmap_high_get" were involved. The changes we made in "__flush_dcache_page" (below) should fix the problem which has been resolved in ARM. Dezhong void __flush_dcache_page(struct page *page) { struct address_space *mapping = page_mapping(page); void *addr; /* If there is a temporary kernel mapping, i.e. if kmap_atomic was * used to map a page, we only need to flush the page. We can skip * the other work here because it won't be used in any other way. */ if (PageHighMem(page)) { addr = kmap_atomic_to_vaddr(page); if (addr != NULL) { flush_data_cache_page((unsigned long) addr); return; } } /* If page_mapping returned a non-NULL value, then the page is not * in the swap cache and it isn't anonymously mapped. If it's not * already mapped into user space, we can just set the dirty bit to * get the cache flushed later, if needed */ if (mapping && !mapping_mapped(mapping)) { SetPageDcacheDirty(page); return; } /* * We could delay the flush for the !page_mapping case too. But that * case is for exec env/arg pages and those are %99 certainly going to * get faulted into the tlb (and thus flushed) anyways. */ if (!PageHighMem(page)) { addr = page_address(page); flush_data_cache_page((unsigned long) addr); } else { if (!cpu_has_dc_aliases) { addr = kmap_high_get(page); if (addr) { /* The page has been kmapped */ flush_data_cache_page((unsigned long) addr); kunmap_high(page); } else { /* Alright, we need a temporary kernel mapping. Since we are on * a processor that has hardware to eliminate data cache * aliases, we don't have to get an address whose virtual index * into the cache that matches the index originally used to map * the page. This makes the task doable. */ addr = kmap_atomic(page, KM_MIPS_SYNC_PAGE); flush_data_cache_page((unsigned long) addr); kunmap_atomic(addr, KM_MIPS_SYNC_PAGE); } } else { /* Sorry, we may have data cache aliases, which means that we * have to be able to get a virtual address whose virtual index * into cache matches the index used to map this page. This is * hard and so, just like the hard problems in my Physics * classes, is left as an exercise for the reader. */ panic("Unable to flush page 0x%p on processor with data cache " "aliases\n", page); } } } From skuribay@pobox.com Fri Jul 2 16:14:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Jul 2010 16:14:15 +0200 (CEST) Received: from b-pb-sasl-quonix.pobox.com ([208.72.237.35]:49300 "EHLO sasl.smtp.pobox.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491944Ab0GBOOM (ORCPT ); Fri, 2 Jul 2010 16:14:12 +0200 Received: from sasl.smtp.pobox.com (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 2CDC1B3298; Fri, 2 Jul 2010 10:14:07 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=pobox.com; h=message-id :date:from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; s=sasl; bh=iz44Jx1OG25/ lpXNOpM7Ei8dQac=; b=laNVTGCA5ZQNeg90Jj27u4Ini1AvT4sZ4R6pRsTlKQ5Z Y9yXWohlGpDN/ZcQTT1XnCSSnw3n7XPYEpjZMnlJRDkipXKcPv/havtCEFo349QF BuWqyUwy3W3m4GSy+/GIhxpmzKhJ8V+YbsWaGCGGFs+DbYfl2rL1drOicdtPvtc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=pobox.com; h=message-id:date :from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; q=dns; s=sasl; b=NPfLFN jykAbuRs6KIh5Gz7ey8kJdLIrhn7uJk6RT8MrX417ia7T4ma2vDJyBeD6PFWOGjy Ym0MgKnxXLDs+7nxaHv2MSYKcnIs4TJZLnZSwd7RZyHGzDy2IlZ7Wj40+5679rOl WvtORwT2X3cgPfZbiGd7uVvBOzEghdwhQ84Lk= Received: from b-pb-sasl-quonix. (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 0EC44B3297; Fri, 2 Jul 2010 10:14:06 -0400 (EDT) Received: from [192.168.11.3] (unknown [114.162.174.29]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by b-sasl-quonix.pobox.com (Postfix) with ESMTPSA id 06B77B3296; Fri, 2 Jul 2010 10:14:03 -0400 (EDT) Message-ID: <4C2DF427.7080508@pobox.com> Date: Fri, 02 Jul 2010 23:13:59 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100423 Thunderbird/3.0.4 MIME-Version: 1.0 To: David VomLehn CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> In-Reply-To: <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Pobox-Relay-ID: 12E32E5E-85E4-11DF-A64F-DA91016DD5F0-47602734!b-pb-sasl-quonix.pobox.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27299 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@pobox.com Precedence: bulk X-list: linux-mips Hi, On 07/01/2010 07:01 AM, David VomLehn wrote: > Thanks! You are correct in your analysis and make a good point that > clz should be used in interrupt handling. I think, though, that it's > better to go ahead and supply a full-blown cpu-features-override.h > rather than focusing on this one case. This way fls() will be optimized > to use clz everywhere and any other optimizations that depend on constant > cpu_has_* values will also be used. Your choice, either one will be fine :-) By the way, Malta's clz() and irq_ffs() are very nice, and there are two followers; MIPSSim and PowerTV. And now I'm going to make use of them for emma2rh, too. I've prepared a consolidation patch like this, but have two concerns: 1) irq_ffs() is used to dispatch IRQs, so we'd like to give preference to CONFIG_CPU_xxx over cpu_has_clo_clz, to optimize with CLZ. It's somewhat different for usual fls() and ffs() cases. Or, 2) would it be better to check __builtin_constant_p(cpu_has_clo_clz)? Or, any other good alternatives? diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h index ef6a07c..ad6b416 100644 --- a/arch/mips/include/asm/irq_cpu.h +++ b/arch/mips/include/asm/irq_cpu.h @@ -17,4 +17,47 @@ extern void mips_cpu_irq_init(void); extern void rm7k_cpu_irq_init(void); extern void rm9k_cpu_irq_init(void); +/* + * Version of ffs that only looks at bits 12..15. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + int x; + + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (pending)); + + return -x + 31 - CAUSEB_IP; +#else + unsigned int a0 = 7; + unsigned int t0; + + t0 = pending & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0x8000; + t0 = t0 < 1; + /* t0 = t0 << 2; */ + a0 = a0 - t0; + /* pending = pending << t0; */ + + return a0; +#endif +} + #endif /* _ASM_IRQ_CPU_H */ diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c index 5c779be..5813e7e 100644 --- a/arch/mips/mipssim/sim_int.c +++ b/arch/mips/mipssim/sim_int.c @@ -22,52 +22,6 @@ #include #include -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = s0 & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0x8000; - t0 = t0 < 1; - /* t0 = t0 << 2; */ - a0 = a0 - t0; - /* s0 = s0 << t0; */ - - return a0; -#endif -} - asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 15949b0..656cecf 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -197,52 +197,6 @@ static void corehi_irqdispatch(void) die("CoreHi interrupt", regs); } -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = pending & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - pending = pending << t0; - - t0 = pending & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - pending = pending << t0; - - t0 = pending & 0x8000; - t0 = t0 < 1; - /* t0 = t0 << 2; */ - a0 = a0 - t0; - /* pending = pending << t0; */ - - return a0; -#endif -} - /* * IRQs on the Malta board look basically (barring software IRQs which we * don't use at all and all external interrupt sources are combined together diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c index e3c08a2..06602e7 100644 --- a/arch/mips/powertv/asic/asic_int.c +++ b/arch/mips/powertv/asic/asic_int.c @@ -68,27 +68,6 @@ static void asic_irqdispatch(void) do_IRQ(irq); } -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ - return -clz(pending) + 31 - CAUSEB_IP; -} - /* * TODO: check how it works under EIC mode. */ From dvomlehn@cisco.com Fri Jul 2 23:32:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Jul 2010 23:32:36 +0200 (CEST) Received: from sj-iport-1.cisco.com ([171.71.176.70]:46539 "EHLO sj-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492042Ab0GBVca (ORCPT ); Fri, 2 Jul 2010 23:32:30 +0200 Authentication-Results: sj-iport-1.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAHP3LUyrR7Ht/2dsb2JhbACfZXGlFpo7hSQEg3Q X-IronPort-AV: E=Sophos;i="4.53,528,1272844800"; d="scan'208";a="340773696" Received: from sj-core-1.cisco.com ([171.71.177.237]) by sj-iport-1.cisco.com with ESMTP; 02 Jul 2010 21:32:19 +0000 Received: from dvomlehn-lnx2.corp.sa.net (dhcp-171-71-47-241.cisco.com [171.71.47.241]) by sj-core-1.cisco.com (8.13.8/8.14.3) with ESMTP id o62LWJFH022473; Fri, 2 Jul 2010 21:32:19 GMT Date: Fri, 2 Jul 2010 14:32:19 -0700 From: David VomLehn To: Shinya Kuribayashi Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required Message-ID: <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C2DF427.7080508@pobox.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27300 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Fri, Jul 02, 2010 at 09:13:59AM -0500, Shinya Kuribayashi wrote: > Hi, > > On 07/01/2010 07:01 AM, David VomLehn wrote: > > Thanks! You are correct in your analysis and make a good point that > > clz should be used in interrupt handling. I think, though, that it's > > better to go ahead and supply a full-blown cpu-features-override.h > > rather than focusing on this one case. This way fls() will be optimized > > to use clz everywhere and any other optimizations that depend on constant > > cpu_has_* values will also be used. > > Your choice, either one will be fine :-) I think the cpu-features-override is a a better solution because it allows better code throughout the kernel. > By the way, Malta's clz() and irq_ffs() are very nice, and there are > two followers; MIPSSim and PowerTV. And now I'm going to make use of > them for emma2rh, too. > > I've prepared a consolidation patch like this, but have two concerns: > > 1) irq_ffs() is used to dispatch IRQs, so we'd like to give preference > to CONFIG_CPU_xxx over cpu_has_clo_clz, to optimize with CLZ. It's > somewhat different for usual fls() and ffs() cases. Or, > > 2) would it be better to check __builtin_constant_p(cpu_has_clo_clz)? > > Or, any other good alternatives? Usually it's better to control things on a feature-by-feature basis rather than rely on things like CPU model. This allows you to easily handle case where, for example, you have a different CPU that normally doesn't have a feature but a particular variant does have it. IIRC, the MIPS family has examples of this. So, I think it's better to go with the: __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz used in fls(). -- David VL From skuribay@pobox.com Sat Jul 3 16:31:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Jul 2010 16:32:01 +0200 (CEST) Received: from b-pb-sasl-quonix.pobox.com ([208.72.237.35]:55922 "EHLO sasl.smtp.pobox.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491880Ab0GCOb4 (ORCPT ); Sat, 3 Jul 2010 16:31:56 +0200 Received: from sasl.smtp.pobox.com (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 92F8BB300C; Sat, 3 Jul 2010 10:31:51 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=pobox.com; h=message-id :date:from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; s=sasl; bh=M4j8fO2TEIhC z7/zlLDt/nVagVQ=; b=xH5wioCSigXDLpXLyQQiLvjfk00+xYHs/MkyAHRxIQ3H ctsJJ2IDbfTH8nZeuPSfDLRQSHuBMrGsx3+SRrXETfUJOh5Cn883uSm4bRfv0M9B qPzKxSV5xVtCEqE3SzGpOy4cVzbb+y2DnloO/izQp3DLfvcN4tyoA6/sbE3xx70= DomainKey-Signature: a=rsa-sha1; c=nofws; d=pobox.com; h=message-id:date :from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; q=dns; s=sasl; b=CWvq4I qUtg4uLLk7Z9Q1Q65Y5TLG1A4kl0PdjKm5xUMO8wM/3P23UXjFZ9b9fZ2SuYjrUs ocSNQq87Hi5p63xsisBTBqIJCB209QbZ/40aHWzDLpuTh6EZfIbgT793e8XJOaYY bM9ViJXeGhcrpOajirfL1cqhk95kLKIls851I= Received: from b-pb-sasl-quonix. (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 80C57B300A; Sat, 3 Jul 2010 10:31:50 -0400 (EDT) Received: from [192.168.11.3] (unknown [114.162.174.29]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by b-sasl-quonix.pobox.com (Postfix) with ESMTPSA id 96FE0B3008; Sat, 3 Jul 2010 10:31:48 -0400 (EDT) Message-ID: <4C2F49D0.60200@pobox.com> Date: Sat, 03 Jul 2010 23:31:44 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100423 Thunderbird/3.0.4 MIME-Version: 1.0 To: David VomLehn CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> In-Reply-To: <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Pobox-Relay-ID: B7C5C62C-86AF-11DF-B030-DA91016DD5F0-47602734!b-pb-sasl-quonix.pobox.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27301 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@pobox.com Precedence: bulk X-list: linux-mips On 07/03/2010 06:32 AM, David VomLehn wrote: > Usually it's better to control things on a feature-by-feature basis rather > than rely on things like CPU model. This allows you to easily handle case > where, for example, you have a different CPU that normally doesn't have > a feature but a particular variant does have it. IIRC, the MIPS family has > examples of this. So, I think it's better to go with the: > __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz > used in fls(). Ok, now I've come to the same conclusion. Revised patch will be like this. Malta is a development platform supporting various types of MIPS32/MIPS64 cores, hence use cpu_has_clo_clz directly. The same goes to MIPSSim. Another concern is that, I'm not really sure whether cpu_has_clo_clz is acceptable or not for Malta (and MIPSSim). Hopefully Ralf will help us make things in the right direction. Shinya diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h index ef6a07c..8fa5c2f 100644 --- a/arch/mips/include/asm/irq_cpu.h +++ b/arch/mips/include/asm/irq_cpu.h @@ -13,6 +13,52 @@ #ifndef _ASM_IRQ_CPU_H #define _ASM_IRQ_CPU_H +/** + * irq_ffs - Version of ffs that only looks at bits 12..15 + * @pending: pending interrupt status + * + * @pending is expected to be 32-bit wide, where unwanted bits are + * filtered out using ST0_IM beforehand. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ + unsigned int a0 = 7; + unsigned int t0; + + if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { + int x; + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (pending)); + + return -x + 31 - CAUSEB_IP; + } + + t0 = pending & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0x8000; + t0 = t0 < 1; + /* t0 = t0 << 2; */ + a0 = a0 - t0; + /* pending = pending << t0; */ + + return a0; +} + extern void mips_cpu_irq_init(void); extern void rm7k_cpu_irq_init(void); extern void rm9k_cpu_irq_init(void); diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h index 2848cea..37e3583 100644 --- a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h @@ -32,6 +32,7 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ @@ -58,6 +59,7 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ diff --git a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h index 779b022..27aaaa5 100644 --- a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h @@ -31,6 +31,7 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ @@ -56,6 +57,7 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c index 5c779be..5813e7e 100644 --- a/arch/mips/mipssim/sim_int.c +++ b/arch/mips/mipssim/sim_int.c @@ -22,52 +22,6 @@ #include #include -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = s0 & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0x8000; - t0 = t0 < 1; - /* t0 = t0 << 2; */ - a0 = a0 - t0; - /* s0 = s0 << t0; */ - - return a0; -#endif -} - asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 15949b0..656cecf 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -197,52 +197,6 @@ static void corehi_irqdispatch(void) die("CoreHi interrupt", regs); } -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = pending & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - pending = pending << t0; - - t0 = pending & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - pending = pending << t0; - - t0 = pending & 0x8000; - t0 = t0 < 1; - /* t0 = t0 << 2; */ - a0 = a0 - t0; - /* pending = pending << t0; */ - - return a0; -#endif -} - /* * IRQs on the Malta board look basically (barring software IRQs which we * don't use at all and all external interrupt sources are combined together diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c index 529c44a..06602e7 100644 --- a/arch/mips/powertv/asic/asic_int.c +++ b/arch/mips/powertv/asic/asic_int.c @@ -68,27 +68,6 @@ static void asic_irqdispatch(void) do_IRQ(irq); } -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ - return fls(pending) - 1 + CAUSEB_IP; -} - /* * TODO: check how it works under EIC mode. */ From macro@linux-mips.org Sat Jul 3 19:03:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Jul 2010 19:03:28 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:43887 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491954Ab0GCRDY (ORCPT ); Sat, 3 Jul 2010 19:03:24 +0200 Date: Sat, 3 Jul 2010 18:03:24 +0100 (BST) From: "Maciej W. Rozycki" To: Shinya Kuribayashi cc: David VomLehn , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required In-Reply-To: <4C2F49D0.60200@pobox.com> Message-ID: References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> <4C2F49D0.60200@pobox.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27302 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, 3 Jul 2010, Shinya Kuribayashi wrote: > Ok, now I've come to the same conclusion. Revised patch will be like > this. Malta is a development platform supporting various types of > MIPS32/MIPS64 cores, hence use cpu_has_clo_clz directly. The same goes > to MIPSSim. Malta also supports a couple of MIPS IV processors too, so please be careful about such assumptions. > + if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { > + int x; > + __asm__( > + " .set push \n" > + " .set mips32 \n" > + " clz %0, %1 \n" > + " .set pop \n" > + : "=r" (x) > + : "r" (pending)); > + > + return -x + 31 - CAUSEB_IP; > + } Hmm, ".set mips32" looks dodgy here. For pre-MIPS32/64 platforms this code should never make it to the assembler and if it did, then a build-time error is better than a run-time problem. It might be simpler just to use __builtin_ffs() for this variant though. Inline assembly is better avoided unless absolutely required. Not even mentioning readability. Maciej From lars@metafoo.de Mon Jul 5 00:28:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 00:28:15 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:57396 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491158Ab0GDW2I (ORCPT ); Mon, 5 Jul 2010 00:28:08 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id E339593C; Mon, 5 Jul 2010 00:28:02 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id OYawNrv4TGYb; Mon, 5 Jul 2010 00:28:02 +0200 (CEST) Received: from [192.168.37.31] (port-92973.pppoe.wtnet.de [84.46.75.169]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 1D82093B; Mon, 5 Jul 2010 00:27:43 +0200 (CEST) Message-ID: <4C310ACD.6040604@metafoo.de> Date: Mon, 05 Jul 2010 00:27:25 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Andrew Morton CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle , linux-fbdev@vger.kernel.org Subject: Re: [PATCH v2 16/26] fbdev: Add JZ4740 framebuffer driver References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-17-git-send-email-lars@metafoo.de> In-Reply-To: <1276924111-11158-17-git-send-email-lars@metafoo.de> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27303 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Hi Andrew v2 of this patch has been around for two weeks without any comments. I've fixed all the issues you had with v1. If you this version is ok, an Acked-By would be nice :) Thanks - Lars Lars-Peter Clausen wrote: > This patch adds support for the LCD controller on JZ4740 SoCs. > > Signed-off-by: Lars-Peter Clausen > Cc: Andrew Morton > Cc: linux-fbdev@vger.kernel.org > > --- > Changes since v1 > - Use __packed instead of __attribute__((packed)) > - Make jzfb_fix const > - Only set mode in set_par if it has changed > --- > drivers/video/Kconfig | 9 + > drivers/video/Makefile | 1 + > drivers/video/jz4740_fb.c | 817 +++++++++++++++++++++++++++++++++++++++++++++ > include/linux/jz4740_fb.h | 58 ++++ > 4 files changed, 885 insertions(+), 0 deletions(-) > create mode 100644 drivers/video/jz4740_fb.c > create mode 100644 include/linux/jz4740_fb.h > > diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig > index a9f9e5e..eae4c8a 100644 > --- a/drivers/video/Kconfig > +++ b/drivers/video/Kconfig > @@ -2237,6 +2237,15 @@ config FB_BROADSHEET > and could also have been called by other names when coupled with > a bridge adapter. > > +config FB_JZ4740 > + tristate "JZ4740 LCD framebuffer support" > + depends on FB > + select FB_SYS_FILLRECT > + select FB_SYS_COPYAREA > + select FB_SYS_IMAGEBLIT > + help > + Framebuffer support for the JZ4740 SoC. > + > source "drivers/video/omap/Kconfig" > source "drivers/video/omap2/Kconfig" > > diff --git a/drivers/video/Makefile b/drivers/video/Makefile > index 3c3bf86..fd2df57 100644 > --- a/drivers/video/Makefile > +++ b/drivers/video/Makefile > @@ -132,6 +132,7 @@ obj-$(CONFIG_FB_CARMINE) += carminefb.o > obj-$(CONFIG_FB_MB862XX) += mb862xx/ > obj-$(CONFIG_FB_MSM) += msm/ > obj-$(CONFIG_FB_NUC900) += nuc900fb.o > +obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o > > # Platform or fallback drivers go here > obj-$(CONFIG_FB_UVESA) += uvesafb.o > diff --git a/drivers/video/jz4740_fb.c b/drivers/video/jz4740_fb.c > new file mode 100644 > index 0000000..8d03181 > --- /dev/null > +++ b/drivers/video/jz4740_fb.c > @@ -0,0 +1,817 @@ > +/* > + * Copyright (C) 2009-2010, Lars-Peter Clausen > + * JZ4740 SoC LCD framebuffer driver > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +#include > +#include > + > +#include > + > +#include > +#include > + > +#define JZ_REG_LCD_CFG 0x00 > +#define JZ_REG_LCD_VSYNC 0x04 > +#define JZ_REG_LCD_HSYNC 0x08 > +#define JZ_REG_LCD_VAT 0x0C > +#define JZ_REG_LCD_DAH 0x10 > +#define JZ_REG_LCD_DAV 0x14 > +#define JZ_REG_LCD_PS 0x18 > +#define JZ_REG_LCD_CLS 0x1C > +#define JZ_REG_LCD_SPL 0x20 > +#define JZ_REG_LCD_REV 0x24 > +#define JZ_REG_LCD_CTRL 0x30 > +#define JZ_REG_LCD_STATE 0x34 > +#define JZ_REG_LCD_IID 0x38 > +#define JZ_REG_LCD_DA0 0x40 > +#define JZ_REG_LCD_SA0 0x44 > +#define JZ_REG_LCD_FID0 0x48 > +#define JZ_REG_LCD_CMD0 0x4C > +#define JZ_REG_LCD_DA1 0x50 > +#define JZ_REG_LCD_SA1 0x54 > +#define JZ_REG_LCD_FID1 0x58 > +#define JZ_REG_LCD_CMD1 0x5C > + > +#define JZ_LCD_CFG_SLCD BIT(31) > +#define JZ_LCD_CFG_PS_DISABLE BIT(23) > +#define JZ_LCD_CFG_CLS_DISABLE BIT(22) > +#define JZ_LCD_CFG_SPL_DISABLE BIT(21) > +#define JZ_LCD_CFG_REV_DISABLE BIT(20) > +#define JZ_LCD_CFG_HSYNCM BIT(19) > +#define JZ_LCD_CFG_PCLKM BIT(18) > +#define JZ_LCD_CFG_INV BIT(17) > +#define JZ_LCD_CFG_SYNC_DIR BIT(16) > +#define JZ_LCD_CFG_PS_POLARITY BIT(15) > +#define JZ_LCD_CFG_CLS_POLARITY BIT(14) > +#define JZ_LCD_CFG_SPL_POLARITY BIT(13) > +#define JZ_LCD_CFG_REV_POLARITY BIT(12) > +#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) > +#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) > +#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) > +#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) > +#define JZ_LCD_CFG_18_BIT BIT(7) > +#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) > +#define JZ_LCD_CFG_MODE_MASK 0xf > + > +#define JZ_LCD_CTRL_BURST_4 (0x0 << 28) > +#define JZ_LCD_CTRL_BURST_8 (0x1 << 28) > +#define JZ_LCD_CTRL_BURST_16 (0x2 << 28) > +#define JZ_LCD_CTRL_RGB555 BIT(27) > +#define JZ_LCD_CTRL_OFUP BIT(26) > +#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) > +#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) > +#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) > +#define JZ_LCD_CTRL_PDD_MASK (0xff << 16) > +#define JZ_LCD_CTRL_EOF_IRQ BIT(13) > +#define JZ_LCD_CTRL_SOF_IRQ BIT(12) > +#define JZ_LCD_CTRL_OFU_IRQ BIT(11) > +#define JZ_LCD_CTRL_IFU0_IRQ BIT(10) > +#define JZ_LCD_CTRL_IFU1_IRQ BIT(9) > +#define JZ_LCD_CTRL_DD_IRQ BIT(8) > +#define JZ_LCD_CTRL_QDD_IRQ BIT(7) > +#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) > +#define JZ_LCD_CTRL_LSB_FISRT BIT(5) > +#define JZ_LCD_CTRL_DISABLE BIT(4) > +#define JZ_LCD_CTRL_ENABLE BIT(3) > +#define JZ_LCD_CTRL_BPP_1 0x0 > +#define JZ_LCD_CTRL_BPP_2 0x1 > +#define JZ_LCD_CTRL_BPP_4 0x2 > +#define JZ_LCD_CTRL_BPP_8 0x3 > +#define JZ_LCD_CTRL_BPP_15_16 0x4 > +#define JZ_LCD_CTRL_BPP_18_24 0x5 > + > +#define JZ_LCD_CMD_SOF_IRQ BIT(15) > +#define JZ_LCD_CMD_EOF_IRQ BIT(16) > +#define JZ_LCD_CMD_ENABLE_PAL BIT(12) > + > +#define JZ_LCD_SYNC_MASK 0x3ff > + > +#define JZ_LCD_STATE_DISABLED BIT(0) > + > +struct jzfb_framedesc { > + uint32_t next; > + uint32_t addr; > + uint32_t id; > + uint32_t cmd; > +} __packed; > + > +struct jzfb { > + struct fb_info *fb; > + struct platform_device *pdev; > + void __iomem *base; > + struct resource *mem; > + struct jz4740_fb_platform_data *pdata; > + > + size_t vidmem_size; > + void *vidmem; > + dma_addr_t vidmem_phys; > + struct jzfb_framedesc *framedesc; > + dma_addr_t framedesc_phys; > + > + struct clk *ldclk; > + struct clk *lpclk; > + > + unsigned is_enabled:1; > + struct mutex lock; > + > + uint32_t pseudo_palette[16]; > +}; > + > +static const struct fb_fix_screeninfo jzfb_fix __devinitdata = { > + .id = "JZ4740 FB", > + .type = FB_TYPE_PACKED_PIXELS, > + .visual = FB_VISUAL_TRUECOLOR, > + .xpanstep = 0, > + .ypanstep = 0, > + .ywrapstep = 0, > + .accel = FB_ACCEL_NONE, > +}; > + > +static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = { > + JZ_GPIO_BULK_PIN(LCD_PCLK), > + JZ_GPIO_BULK_PIN(LCD_HSYNC), > + JZ_GPIO_BULK_PIN(LCD_VSYNC), > + JZ_GPIO_BULK_PIN(LCD_DE), > + JZ_GPIO_BULK_PIN(LCD_PS), > + JZ_GPIO_BULK_PIN(LCD_REV), > +}; > + > +static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = { > + JZ_GPIO_BULK_PIN(LCD_DATA0), > + JZ_GPIO_BULK_PIN(LCD_DATA1), > + JZ_GPIO_BULK_PIN(LCD_DATA2), > + JZ_GPIO_BULK_PIN(LCD_DATA3), > + JZ_GPIO_BULK_PIN(LCD_DATA4), > + JZ_GPIO_BULK_PIN(LCD_DATA5), > + JZ_GPIO_BULK_PIN(LCD_DATA6), > + JZ_GPIO_BULK_PIN(LCD_DATA7), > + JZ_GPIO_BULK_PIN(LCD_DATA8), > + JZ_GPIO_BULK_PIN(LCD_DATA9), > + JZ_GPIO_BULK_PIN(LCD_DATA10), > + JZ_GPIO_BULK_PIN(LCD_DATA11), > + JZ_GPIO_BULK_PIN(LCD_DATA12), > + JZ_GPIO_BULK_PIN(LCD_DATA13), > + JZ_GPIO_BULK_PIN(LCD_DATA14), > + JZ_GPIO_BULK_PIN(LCD_DATA15), > + JZ_GPIO_BULK_PIN(LCD_DATA16), > + JZ_GPIO_BULK_PIN(LCD_DATA17), > +}; > + > +static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb) > +{ > + unsigned int num; > + > + switch (jzfb->pdata->lcd_type) { > + case JZ_LCD_TYPE_GENERIC_16_BIT: > + num = 4; > + break; > + case JZ_LCD_TYPE_GENERIC_18_BIT: > + num = 4; > + break; > + case JZ_LCD_TYPE_8BIT_SERIAL: > + num = 3; > + break; > + default: > + num = 0; > + break; > + } > + return num; > +} > + > +static unsigned int jzfb_num_data_pins(struct jzfb *jzfb) > +{ > + unsigned int num; > + > + switch (jzfb->pdata->lcd_type) { > + case JZ_LCD_TYPE_GENERIC_16_BIT: > + num = 16; > + break; > + case JZ_LCD_TYPE_GENERIC_18_BIT: > + num = 18; > + break; > + case JZ_LCD_TYPE_8BIT_SERIAL: > + num = 8; > + break; > + default: > + num = 0; > + break; > + } > + return num; > +} > + > +/* Based on CNVT_TOHW macro from skeletonfb.c */ > +static inline uint32_t jzfb_convert_color_to_hw(unsigned val, > + struct fb_bitfield *bf) > +{ > + return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset; > +} > + > +static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, > + unsigned blue, unsigned transp, struct fb_info *fb) > +{ > + uint32_t color; > + > + if (regno >= 16) > + return -EINVAL; > + > + color = jzfb_convert_color_to_hw(red, &fb->var.red); > + color |= jzfb_convert_color_to_hw(green, &fb->var.green); > + color |= jzfb_convert_color_to_hw(blue, &fb->var.blue); > + color |= jzfb_convert_color_to_hw(transp, &fb->var.transp); > + > + ((uint32_t *)(fb->pseudo_palette))[regno] = color; > + > + return 0; > +} > + > +static int jzfb_get_controller_bpp(struct jzfb *jzfb) > +{ > + switch (jzfb->pdata->bpp) { > + case 18: > + case 24: > + return 32; > + case 15: > + return 16; > + default: > + return jzfb->pdata->bpp; > + } > +} > + > +static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb, > + struct fb_var_screeninfo *var) > +{ > + size_t i; > + struct fb_videomode *mode = jzfb->pdata->modes; > + > + for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) { > + if (mode->xres == var->xres && mode->yres == var->yres) > + return mode; > + } > + > + return NULL; > +} > + > +static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb) > +{ > + struct jzfb *jzfb = fb->par; > + struct fb_videomode *mode; > + > + if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) && > + var->bits_per_pixel != jzfb->pdata->bpp) > + return -EINVAL; > + > + mode = jzfb_get_mode(jzfb, var); > + if (mode == NULL) > + return -EINVAL; > + > + fb_videomode_to_var(var, mode); > + > + switch (jzfb->pdata->bpp) { > + case 8: > + break; > + case 15: > + var->red.offset = 10; > + var->red.length = 5; > + var->green.offset = 6; > + var->green.length = 5; > + var->blue.offset = 0; > + var->blue.length = 5; > + break; > + case 16: > + var->red.offset = 11; > + var->red.length = 5; > + var->green.offset = 5; > + var->green.length = 6; > + var->blue.offset = 0; > + var->blue.length = 5; > + break; > + case 18: > + var->red.offset = 16; > + var->red.length = 6; > + var->green.offset = 8; > + var->green.length = 6; > + var->blue.offset = 0; > + var->blue.length = 6; > + var->bits_per_pixel = 32; > + break; > + case 32: > + case 24: > + var->transp.offset = 24; > + var->transp.length = 8; > + var->red.offset = 16; > + var->red.length = 8; > + var->green.offset = 8; > + var->green.length = 8; > + var->blue.offset = 0; > + var->blue.length = 8; > + var->bits_per_pixel = 32; > + break; > + default: > + break; > + } > + > + return 0; > +} > + > +static int jzfb_set_par(struct fb_info *info) > +{ > + struct jzfb *jzfb = info->par; > + struct fb_var_screeninfo *var = &info->var; > + struct fb_videomode *mode; > + uint16_t hds, vds; > + uint16_t hde, vde; > + uint16_t ht, vt; > + uint32_t ctrl; > + uint32_t cfg; > + unsigned long rate; > + > + mode = jzfb_get_mode(jzfb, var); > + if (mode == NULL) > + return -EINVAL; > + > + if (mode == info->mode) > + return 0; > + > + info->mode = mode; > + > + hds = mode->hsync_len + mode->left_margin; > + hde = hds + mode->xres; > + ht = hde + mode->right_margin; > + > + vds = mode->vsync_len + mode->upper_margin; > + vde = vds + mode->yres; > + vt = vde + mode->lower_margin; > + > + ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16; > + > + switch (jzfb->pdata->bpp) { > + case 1: > + ctrl |= JZ_LCD_CTRL_BPP_1; > + break; > + case 2: > + ctrl |= JZ_LCD_CTRL_BPP_2; > + break; > + case 4: > + ctrl |= JZ_LCD_CTRL_BPP_4; > + break; > + case 8: > + ctrl |= JZ_LCD_CTRL_BPP_8; > + break; > + case 15: > + ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */ > + case 16: > + ctrl |= JZ_LCD_CTRL_BPP_15_16; > + break; > + case 18: > + case 24: > + case 32: > + ctrl |= JZ_LCD_CTRL_BPP_18_24; > + break; > + default: > + break; > + } > + > + cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE | > + JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; > + > + if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) > + cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; > + > + if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) > + cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; > + > + if (jzfb->pdata->pixclk_falling_edge) > + cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; > + > + if (jzfb->pdata->date_enable_active_low) > + cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; > + > + if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT) > + cfg |= JZ_LCD_CFG_18_BIT; > + > + cfg |= jzfb->pdata->lcd_type & 0xf; > + > + if (mode->pixclock) { > + rate = PICOS2KHZ(mode->pixclock) * 1000; > + mode->refresh = rate / vt / ht; > + } else { > + if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) > + rate = mode->refresh * (vt + 2 * mode->xres) * ht; > + else > + rate = mode->refresh * vt * ht; > + > + mode->pixclock = KHZ2PICOS(rate / 1000); > + } > + > + mutex_lock(&jzfb->lock); > + if (!jzfb->is_enabled) > + clk_enable(jzfb->ldclk); > + else > + ctrl |= JZ_LCD_CTRL_ENABLE; > + > + writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC); > + writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC); > + > + writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT); > + > + writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH); > + writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV); > + > + writel(cfg, jzfb->base + JZ_REG_LCD_CFG); > + > + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); > + > + if (!jzfb->is_enabled) > + clk_disable(jzfb->ldclk); > + > + mutex_unlock(&jzfb->lock); > + > + clk_set_rate(jzfb->lpclk, rate); > + clk_set_rate(jzfb->ldclk, rate * 3); > + > + return 0; > +} > + > +static void jzfb_enable(struct jzfb *jzfb) > +{ > + uint32_t ctrl; > + > + clk_enable(jzfb->ldclk); > + > + jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); > + jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); > + > + writel(0, jzfb->base + JZ_REG_LCD_STATE); > + > + writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); > + > + ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); > + ctrl |= JZ_LCD_CTRL_ENABLE; > + ctrl &= ~JZ_LCD_CTRL_DISABLE; > + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); > +} > + > +static void jzfb_disable(struct jzfb *jzfb) > +{ > + uint32_t ctrl; > + > + ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); > + ctrl |= JZ_LCD_CTRL_DISABLE; > + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); > + do { > + ctrl = readl(jzfb->base + JZ_REG_LCD_STATE); > + } while (!(ctrl & JZ_LCD_STATE_DISABLED)); > + > + jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); > + jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); > + > + clk_disable(jzfb->ldclk); > +} > + > +static int jzfb_blank(int blank_mode, struct fb_info *info) > +{ > + struct jzfb *jzfb = info->par; > + > + switch (blank_mode) { > + case FB_BLANK_UNBLANK: > + mutex_lock(&jzfb->lock); > + if (jzfb->is_enabled) { > + mutex_unlock(&jzfb->lock); > + return 0; > + } > + > + jzfb_enable(jzfb); > + jzfb->is_enabled = 1; > + > + mutex_unlock(&jzfb->lock); > + break; > + default: > + mutex_lock(&jzfb->lock); > + if (!jzfb->is_enabled) { > + mutex_unlock(&jzfb->lock); > + return 0; > + } > + > + jzfb_disable(jzfb); > + jzfb->is_enabled = 0; > + > + mutex_unlock(&jzfb->lock); > + break; > + } > + > + return 0; > +} > + > +static int jzfb_alloc_devmem(struct jzfb *jzfb) > +{ > + int max_videosize = 0; > + struct fb_videomode *mode = jzfb->pdata->modes; > + void *page; > + int i; > + > + for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) { > + if (max_videosize < mode->xres * mode->yres) > + max_videosize = mode->xres * mode->yres; > + } > + > + max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3; > + > + jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev, > + sizeof(*jzfb->framedesc), > + &jzfb->framedesc_phys, GFP_KERNEL); > + > + if (!jzfb->framedesc) > + return -ENOMEM; > + > + jzfb->vidmem_size = PAGE_ALIGN(max_videosize); > + jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev, > + jzfb->vidmem_size, > + &jzfb->vidmem_phys, GFP_KERNEL); > + > + if (!jzfb->vidmem) > + goto err_free_framedesc; > + > + for (page = jzfb->vidmem; > + page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size); > + page += PAGE_SIZE) { > + SetPageReserved(virt_to_page(page)); > + } > + > + jzfb->framedesc->next = jzfb->framedesc_phys; > + jzfb->framedesc->addr = jzfb->vidmem_phys; > + jzfb->framedesc->id = 0xdeafbead; > + jzfb->framedesc->cmd = 0; > + jzfb->framedesc->cmd |= max_videosize / 4; > + > + return 0; > + > +err_free_framedesc: > + dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), > + jzfb->framedesc, jzfb->framedesc_phys); > + return -ENOMEM; > +} > + > +static void jzfb_free_devmem(struct jzfb *jzfb) > +{ > + dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size, > + jzfb->vidmem, jzfb->vidmem_phys); > + dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), > + jzfb->framedesc, jzfb->framedesc_phys); > +} > + > +static struct fb_ops jzfb_ops = { > + .owner = THIS_MODULE, > + .fb_check_var = jzfb_check_var, > + .fb_set_par = jzfb_set_par, > + .fb_blank = jzfb_blank, > + .fb_fillrect = sys_fillrect, > + .fb_copyarea = sys_copyarea, > + .fb_imageblit = sys_imageblit, > + .fb_setcolreg = jzfb_setcolreg, > +}; > + > +static int __devinit jzfb_probe(struct platform_device *pdev) > +{ > + int ret; > + struct jzfb *jzfb; > + struct fb_info *fb; > + struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data; > + struct resource *mem; > + > + if (!pdata) { > + dev_err(&pdev->dev, "Missing platform data\n"); > + return -ENOENT; > + } > + > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!mem) { > + dev_err(&pdev->dev, "Failed to get register memory resource\n"); > + return -ENOENT; > + } > + > + mem = request_mem_region(mem->start, resource_size(mem), pdev->name); > + if (!mem) { > + dev_err(&pdev->dev, "Failed to request register memory region\n"); > + return -EBUSY; > + } > + > + fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev); > + if (!fb) { > + dev_err(&pdev->dev, "Failed to allocate framebuffer device\n"); > + ret = -ENOMEM; > + goto err_release_mem_region; > + } > + > + fb->fbops = &jzfb_ops; > + fb->flags = FBINFO_DEFAULT; > + > + jzfb = fb->par; > + jzfb->pdev = pdev; > + jzfb->pdata = pdata; > + jzfb->mem = mem; > + > + jzfb->ldclk = clk_get(&pdev->dev, "lcd"); > + if (IS_ERR(jzfb->ldclk)) { > + ret = PTR_ERR(jzfb->ldclk); > + dev_err(&pdev->dev, "Failed to get lcd clock: %d\n", ret); > + goto err_framebuffer_release; > + } > + > + jzfb->lpclk = clk_get(&pdev->dev, "lcd_pclk"); > + if (IS_ERR(jzfb->lpclk)) { > + ret = PTR_ERR(jzfb->lpclk); > + dev_err(&pdev->dev, "Failed to get lcd pixel clock: %d\n", ret); > + goto err_put_ldclk; > + } > + > + jzfb->base = ioremap(mem->start, resource_size(mem)); > + if (!jzfb->base) { > + dev_err(&pdev->dev, "Failed to ioremap register memory region\n"); > + ret = -EBUSY; > + goto err_put_lpclk; > + } > + > + platform_set_drvdata(pdev, jzfb); > + > + mutex_init(&jzfb->lock); > + > + fb_videomode_to_modelist(pdata->modes, pdata->num_modes, > + &fb->modelist); > + fb_videomode_to_var(&fb->var, pdata->modes); > + fb->var.bits_per_pixel = pdata->bpp; > + jzfb_check_var(&fb->var, fb); > + > + ret = jzfb_alloc_devmem(jzfb); > + if (ret) { > + dev_err(&pdev->dev, "Failed to allocate video memory\n"); > + goto err_iounmap; > + } > + > + fb->fix = jzfb_fix; > + fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8; > + fb->fix.mmio_start = mem->start; > + fb->fix.mmio_len = resource_size(mem); > + fb->fix.smem_start = jzfb->vidmem_phys; > + fb->fix.smem_len = fb->fix.line_length * fb->var.yres; > + fb->screen_base = jzfb->vidmem; > + fb->pseudo_palette = jzfb->pseudo_palette; > + > + fb_alloc_cmap(&fb->cmap, 256, 0); > + > + clk_enable(jzfb->ldclk); > + jzfb->is_enabled = 1; > + > + writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); > + > + fb->mode = NULL; > + jzfb_set_par(fb); > + > + jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); > + jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); > + > + ret = register_framebuffer(fb); > + if (ret) { > + dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret); > + goto err_free_devmem; > + } > + > + jzfb->fb = fb; > + > + return 0; > + > +err_free_devmem: > + jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); > + jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); > + > + fb_dealloc_cmap(&fb->cmap); > + jzfb_free_devmem(jzfb); > +err_iounmap: > + iounmap(jzfb->base); > +err_put_lpclk: > + clk_put(jzfb->lpclk); > +err_put_ldclk: > + clk_put(jzfb->ldclk); > +err_framebuffer_release: > + framebuffer_release(fb); > +err_release_mem_region: > + release_mem_region(mem->start, resource_size(mem)); > + return ret; > +} > + > +static int __devexit jzfb_remove(struct platform_device *pdev) > +{ > + struct jzfb *jzfb = platform_get_drvdata(pdev); > + > + jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb); > + > + jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); > + jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); > + > + iounmap(jzfb->base); > + release_mem_region(jzfb->mem->start, resource_size(jzfb->mem)); > + > + fb_dealloc_cmap(&jzfb->fb->cmap); > + jzfb_free_devmem(jzfb); > + > + platform_set_drvdata(pdev, NULL); > + > + clk_put(jzfb->lpclk); > + clk_put(jzfb->ldclk); > + > + framebuffer_release(jzfb->fb); > + > + return 0; > +} > + > +#ifdef CONFIG_PM > + > +static int jzfb_suspend(struct device *dev) > +{ > + struct jzfb *jzfb = dev_get_drvdata(dev); > + > + acquire_console_sem(); > + fb_set_suspend(jzfb->fb, 1); > + release_console_sem(); > + > + mutex_lock(&jzfb->lock); > + if (jzfb->is_enabled) > + jzfb_disable(jzfb); > + mutex_unlock(&jzfb->lock); > + > + return 0; > +} > + > +static int jzfb_resume(struct device *dev) > +{ > + struct jzfb *jzfb = dev_get_drvdata(dev); > + clk_enable(jzfb->ldclk); > + > + mutex_lock(&jzfb->lock); > + if (jzfb->is_enabled) > + jzfb_enable(jzfb); > + mutex_unlock(&jzfb->lock); > + > + acquire_console_sem(); > + fb_set_suspend(jzfb->fb, 0); > + release_console_sem(); > + > + return 0; > +} > + > +static const struct dev_pm_ops jzfb_pm_ops = { > + .suspend = jzfb_suspend, > + .resume = jzfb_resume, > + .poweroff = jzfb_suspend, > + .restore = jzfb_resume, > +}; > + > +#define JZFB_PM_OPS (&jzfb_pm_ops) > + > +#else > +#define JZFB_PM_OPS NULL > +#endif > + > +static struct platform_driver jzfb_driver = { > + .probe = jzfb_probe, > + .remove = __devexit_p(jzfb_remove), > + .driver = { > + .name = "jz4740-fb", > + .pm = JZFB_PM_OPS, > + }, > +}; > + > +static int __init jzfb_init(void) > +{ > + return platform_driver_register(&jzfb_driver); > +} > +module_init(jzfb_init); > + > +static void __exit jzfb_exit(void) > +{ > + platform_driver_unregister(&jzfb_driver); > +} > +module_exit(jzfb_exit); > + > +MODULE_LICENSE("GPL"); > +MODULE_AUTHOR("Lars-Peter Clausen "); > +MODULE_DESCRIPTION("JZ4740 SoC LCD framebuffer driver"); > +MODULE_ALIAS("platform:jz4740-fb"); > diff --git a/include/linux/jz4740_fb.h b/include/linux/jz4740_fb.h > new file mode 100644 > index 0000000..ab4c963 > --- /dev/null > +++ b/include/linux/jz4740_fb.h > @@ -0,0 +1,58 @@ > +/* > + * Copyright (C) 2009, Lars-Peter Clausen > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > + > +#ifndef __LINUX_JZ4740_FB_H > +#define __LINUX_JZ4740_FB_H > + > +#include > + > +enum jz4740_fb_lcd_type { > + JZ_LCD_TYPE_GENERIC_16_BIT = 0, > + JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4), > + JZ_LCD_TYPE_SPECIAL_TFT_1 = 1, > + JZ_LCD_TYPE_SPECIAL_TFT_2 = 2, > + JZ_LCD_TYPE_SPECIAL_TFT_3 = 3, > + JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5, > + JZ_LCD_TYPE_INTERLACED_CCIR656 = 7, > + JZ_LCD_TYPE_SINGLE_COLOR_STN = 8, > + JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9, > + JZ_LCD_TYPE_DUAL_COLOR_STN = 10, > + JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11, > + JZ_LCD_TYPE_8BIT_SERIAL = 12, > +}; > + > +/* > +* width: width of the lcd display in mm > +* height: height of the lcd display in mm > +* num_modes: size of modes > +* modes: list of valid video modes > +* bpp: bits per pixel for the lcd > +* lcd_type: lcd type > +*/ > + > +struct jz4740_fb_platform_data { > + unsigned int width; > + unsigned int height; > + > + size_t num_modes; > + struct fb_videomode *modes; > + > + unsigned int bpp; > + enum jz4740_fb_lcd_type lcd_type; > + > + unsigned pixclk_falling_edge:1; > + unsigned date_enable_active_low:1; > +}; > + > +#endif From lars@metafoo.de Mon Jul 5 00:35:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 00:35:40 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:57707 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491158Ab0GDWfd (ORCPT ); Mon, 5 Jul 2010 00:35:33 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 536E8962; Mon, 5 Jul 2010 00:35:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id wgRnnzdFf7n6; Mon, 5 Jul 2010 00:35:26 +0200 (CEST) Received: from [192.168.37.31] (port-92973.pppoe.wtnet.de [84.46.75.169]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 34144961; Mon, 5 Jul 2010 00:35:20 +0200 (CEST) Message-ID: <4C310C95.1090902@metafoo.de> Date: Mon, 05 Jul 2010 00:35:01 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: "driver linux-mtd"@lists.infradead.org CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Woodhouse , Ralf Baechle Subject: Re: [PATCH v2 17/26] MTD: Nand: Add JZ4740 NAND References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-18-git-send-email-lars@metafoo.de> In-Reply-To: <1276924111-11158-18-git-send-email-lars@metafoo.de> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27304 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Hi Any comments? Thanks - Lars Lars-Peter Clausen wrote: > This patch adds support for the NAND controller on JZ4740 SoCs. > > Signed-off-by: Lars-Peter Clausen > Cc: David Woodhouse > Cc: linux-mtd@lists.infradead.org > > --- > Changes since v1 > - JZ4740: Remove debug macro > - Fix platform driver remove callback > - Add custom nand read/write callback since we need to support more then 64 ecc > bytes > --- > drivers/mtd/nand/Kconfig | 6 + > drivers/mtd/nand/Makefile | 1 + > drivers/mtd/nand/jz4740_nand.c | 474 +++++++++++++++++++++++++++++++++++++++ > include/linux/mtd/jz4740_nand.h | 34 +++ > 4 files changed, 515 insertions(+), 0 deletions(-) > create mode 100644 drivers/mtd/nand/jz4740_nand.c > create mode 100644 include/linux/mtd/jz4740_nand.h > > diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig > index ffc3720..362d177 100644 > --- a/drivers/mtd/nand/Kconfig > +++ b/drivers/mtd/nand/Kconfig > @@ -526,4 +526,10 @@ config MTD_NAND_NUC900 > This enables the driver for the NAND Flash on evaluation board based > on w90p910 / NUC9xx. > > +config MTD_NAND_JZ4740 > + tristate "Support for JZ4740 SoC NAND controller" > + depends on MACH_JZ4740 > + help > + Enables support for NAND Flash on JZ4740 SoC based boards. > + > endif # MTD_NAND > diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile > index e8ab884..ac83dcd 100644 > --- a/drivers/mtd/nand/Makefile > +++ b/drivers/mtd/nand/Makefile > @@ -46,5 +46,6 @@ obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o > obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o > obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o > obj-$(CONFIG_MTD_NAND_RICOH) += r852.o > +obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o > > nand-objs := nand_base.o nand_bbt.o > diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c > new file mode 100644 > index 0000000..8c55f8a > --- /dev/null > +++ b/drivers/mtd/nand/jz4740_nand.c > @@ -0,0 +1,474 @@ > +/* > + * Copyright (C) 2009-2010, Lars-Peter Clausen > + * JZ4740 SoC NAND controller driver > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include > +#include > + > +#define JZ_REG_NAND_CTRL 0x50 > +#define JZ_REG_NAND_ECC_CTRL 0x100 > +#define JZ_REG_NAND_DATA 0x104 > +#define JZ_REG_NAND_PAR0 0x108 > +#define JZ_REG_NAND_PAR1 0x10C > +#define JZ_REG_NAND_PAR2 0x110 > +#define JZ_REG_NAND_IRQ_STAT 0x114 > +#define JZ_REG_NAND_IRQ_CTRL 0x118 > +#define JZ_REG_NAND_ERR(x) (0x11C + (x << 2)) > + > +#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4) > +#define JZ_NAND_ECC_CTRL_ENCODING BIT(3) > +#define JZ_NAND_ECC_CTRL_RS BIT(2) > +#define JZ_NAND_ECC_CTRL_RESET BIT(1) > +#define JZ_NAND_ECC_CTRL_ENABLE BIT(0) > + > +#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29)) > +#define JZ_NAND_STATUS_PAD_FINISH BIT(4) > +#define JZ_NAND_STATUS_DEC_FINISH BIT(3) > +#define JZ_NAND_STATUS_ENC_FINISH BIT(2) > +#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1) > +#define JZ_NAND_STATUS_ERROR BIT(0) > + > +#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT(x << 1) > +#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT((x << 1) + 1) > + > +#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000) > +#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000) > +#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000) > + > +struct jz_nand { > + struct mtd_info mtd; > + struct nand_chip chip; > + void __iomem *base; > + struct resource *mem; > + > + struct jz_nand_platform_data *pdata; > + bool is_reading; > +}; > + > +static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd) > +{ > + return container_of(mtd, struct jz_nand, mtd); > +} > + > +static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) > +{ > + struct jz_nand *nand = mtd_to_jz_nand(mtd); > + struct nand_chip *chip = mtd->priv; > + uint32_t reg; > + > + if (ctrl & NAND_CTRL_CHANGE) { > + BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE)); > + if (ctrl & NAND_ALE) > + chip->IO_ADDR_W = JZ_NAND_ADDR_ADDR; > + else if (ctrl & NAND_CLE) > + chip->IO_ADDR_W = JZ_NAND_CMD_ADDR; > + else > + chip->IO_ADDR_W = JZ_NAND_DATA_ADDR; > + > + reg = readl(nand->base + JZ_REG_NAND_CTRL); > + if (ctrl & NAND_NCE) > + reg |= JZ_NAND_CTRL_ASSERT_CHIP(0); > + else > + reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0); > + writel(reg, nand->base + JZ_REG_NAND_CTRL); > + } > + if (dat != NAND_CMD_NONE) > + writeb(dat, chip->IO_ADDR_W); > +} > + > +static int jz_nand_dev_ready(struct mtd_info *mtd) > +{ > + struct jz_nand *nand = mtd_to_jz_nand(mtd); > + return gpio_get_value_cansleep(nand->pdata->busy_gpio); > +} > + > +static void jz_nand_hwctl(struct mtd_info *mtd, int mode) > +{ > + struct jz_nand *nand = mtd_to_jz_nand(mtd); > + uint32_t reg; > + > + writel(0, nand->base + JZ_REG_NAND_IRQ_STAT); > + reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); > + > + reg |= JZ_NAND_ECC_CTRL_RESET; > + reg |= JZ_NAND_ECC_CTRL_ENABLE; > + reg |= JZ_NAND_ECC_CTRL_RS; > + > + switch (mode) { > + case NAND_ECC_READ: > + reg &= ~JZ_NAND_ECC_CTRL_ENCODING; > + nand->is_reading = true; > + break; > + case NAND_ECC_WRITE: > + reg |= JZ_NAND_ECC_CTRL_ENCODING; > + nand->is_reading = false; > + break; > + default: > + break; > + } > + > + writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); > +} > + > +static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat, > + uint8_t *ecc_code) > +{ > + struct jz_nand *nand = mtd_to_jz_nand(mtd); > + uint32_t reg, status; > + int i; > + static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4, > + 0x8b, 0xff, 0xb7, 0x6f}; > + > + if (nand->is_reading) > + return 0; > + > + do { > + status = readl(nand->base + JZ_REG_NAND_IRQ_STAT); > + } while (!(status & JZ_NAND_STATUS_ENC_FINISH)); > + > + reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); > + reg &= ~JZ_NAND_ECC_CTRL_ENABLE; > + writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); > + > + for (i = 0; i < 9; ++i) > + ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i); > + > + /* If the written data is completly 0xff, we also want to write 0xff as > + * ecc, otherwise we will get in trouble when doing subpage writes. */ > + if (memcmp(ecc_code, empty_block_ecc, 9) == 0) > + memset(ecc_code, 0xff, 9); > + > + return 0; > +} > + > +static void correct_data(uint8_t *dat, int index, int mask) > +{ > + int offset = index & 0x7; > + uint16_t data; > + > + index += (index >> 3); > + > + data = dat[index]; > + data |= dat[index+1] << 8; > + > + mask ^= (data >> offset) & 0x1ff; > + data &= ~(0x1ff << offset); > + data |= (mask << offset); > + > + dat[index] = data & 0xff; > + dat[index+1] = (data >> 8) & 0xff; > +} > + > +static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat, > + uint8_t *read_ecc, uint8_t *calc_ecc) > +{ > + struct jz_nand *nand = mtd_to_jz_nand(mtd); > + int i, error_count, index; > + uint32_t reg, status, error; > + uint32_t t; > + > + t = read_ecc[0]; > + > + if (t == 0xff) { > + for (i = 1; i < 9; ++i) > + t &= read_ecc[i]; > + > + t &= dat[0]; > + t &= dat[nand->chip.ecc.size / 2]; > + t &= dat[nand->chip.ecc.size - 1]; > + > + if (t == 0xff) { > + for (i = 1; i < nand->chip.ecc.size - 1; ++i) > + t &= dat[i]; > + if (t == 0xff) > + return 0; > + } > + } > + > + for (i = 0; i < 9; ++i) > + writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i); > + > + reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); > + reg |= JZ_NAND_ECC_CTRL_PAR_READY; > + writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); > + > + do { > + status = readl(nand->base + JZ_REG_NAND_IRQ_STAT); > + } while (!(status & JZ_NAND_STATUS_DEC_FINISH)); > + > + reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); > + reg &= ~JZ_NAND_ECC_CTRL_ENABLE; > + writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); > + > + if (status & JZ_NAND_STATUS_ERROR) { > + if (status & JZ_NAND_STATUS_UNCOR_ERROR) > + return -1; > + > + error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29; > + > + for (i = 0; i < error_count; ++i) { > + error = readl(nand->base + JZ_REG_NAND_ERR(i)); > + index = ((error >> 16) & 0x1ff) - 1; > + if (index >= 0 && index < 512) > + correct_data(dat, index, error & 0x1ff); > + } > + > + return error_count; > + } > + > + return 0; > +} > + > + > +/* Copy paste of nand_read_page_hwecc_oob_first except for different eccpos > + * handling. The ecc area is for 4k chips 72 bytes long and thus does not fit > + * into the eccpos array. */ > +static int jz_nand_read_page_hwecc_oob_first(struct mtd_info *mtd, > + struct nand_chip *chip, uint8_t *buf, int page) > +{ > + int i, eccsize = chip->ecc.size; > + int eccbytes = chip->ecc.bytes; > + int eccsteps = chip->ecc.steps; > + uint8_t *p = buf; > + unsigned int ecc_offset = chip->page_shift; > + > + /* Read the OOB area first */ > + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); > + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); > + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); > + > + for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { > + int stat; > + > + chip->ecc.hwctl(mtd, NAND_ECC_READ); > + chip->read_buf(mtd, p, eccsize); > + > + stat = chip->ecc.correct(mtd, p, &chip->oob_poi[i], NULL); > + if (stat < 0) > + mtd->ecc_stats.failed++; > + else > + mtd->ecc_stats.corrected += stat; > + } > + return 0; > +} > + > +/* Copy-and-paste of nand_write_page_hwecc with different eccpos handling. */ > +static void jz_nand_write_page_hwecc(struct mtd_info *mtd, > + struct nand_chip *chip, const uint8_t *buf) > +{ > + int i, eccsize = chip->ecc.size; > + int eccbytes = chip->ecc.bytes; > + int eccsteps = chip->ecc.steps; > + const uint8_t *p = buf; > + unsigned int ecc_offset = chip->page_shift; > + > + for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { > + chip->ecc.hwctl(mtd, NAND_ECC_WRITE); > + chip->write_buf(mtd, p, eccsize); > + chip->ecc.calculate(mtd, p, &chip->oob_poi[i]); > + } > + > + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); > +} > + > +#ifdef CONFIG_MTD_CMDLINE_PARTS > +static const char *part_probes[] = {"cmdline", NULL}; > +#endif > + > +static int __devinit jz_nand_probe(struct platform_device *pdev) > +{ > + int ret; > + struct jz_nand *nand; > + struct nand_chip *chip; > + struct mtd_info *mtd; > + struct jz_nand_platform_data *pdata = pdev->dev.platform_data; > +#ifdef CONFIG_MTD_PARTITIONS > + struct mtd_partition *partition_info; > + int num_partitions = 0; > +#endif > + > + nand = kzalloc(sizeof(*nand), GFP_KERNEL); > + if (!nand) { > + dev_err(&pdev->dev, "Failed to allocate device structure.\n"); > + return -ENOMEM; > + } > + > + nand->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!nand->mem) { > + dev_err(&pdev->dev, "Failed to get platform mmio memory\n"); > + ret = -ENOENT; > + goto err_free; > + } > + > + nand->mem = request_mem_region(nand->mem->start, > + resource_size(nand->mem), pdev->name); > + if (!nand->mem) { > + dev_err(&pdev->dev, "Failed to request mmio memory region\n"); > + ret = -EBUSY; > + goto err_free; > + } > + > + nand->base = ioremap(nand->mem->start, resource_size(nand->mem)); > + if (!nand->base) { > + dev_err(&pdev->dev, "Failed to ioremap mmio memory region\n"); > + ret = -EBUSY; > + goto err_release_mem; > + } > + > + if (pdata && gpio_is_valid(pdata->busy_gpio)) { > + ret = gpio_request(pdata->busy_gpio, "NAND busy pin"); > + if (ret) { > + dev_err(&pdev->dev, > + "Failed to request busy gpio %d: %d\n", > + pdata->busy_gpio, ret); > + goto err_iounmap; > + } > + } > + > + mtd = &nand->mtd; > + chip = &nand->chip; > + mtd->priv = chip; > + mtd->owner = THIS_MODULE; > + mtd->name = "jz4740-nand"; > + > + chip->ecc.hwctl = jz_nand_hwctl; > + chip->ecc.calculate = jz_nand_calculate_ecc_rs; > + chip->ecc.correct = jz_nand_correct_ecc_rs; > + chip->ecc.mode = NAND_ECC_HW_OOB_FIRST; > + chip->ecc.size = 512; > + chip->ecc.bytes = 9; > + > + chip->ecc.read_page = jz_nand_read_page_hwecc_oob_first; > + chip->ecc.write_page = jz_nand_write_page_hwecc; > + > + if (pdata) > + chip->ecc.layout = pdata->ecc_layout; > + > + chip->chip_delay = 50; > + chip->cmd_ctrl = jz_nand_cmd_ctrl; > + > + if (pdata && gpio_is_valid(pdata->busy_gpio)) > + chip->dev_ready = jz_nand_dev_ready; > + > + chip->IO_ADDR_R = JZ_NAND_DATA_ADDR; > + chip->IO_ADDR_W = JZ_NAND_DATA_ADDR; > + > + nand->pdata = pdata; > + platform_set_drvdata(pdev, nand); > + > + ret = nand_scan_ident(mtd, 1, NULL); > + if (ret) { > + dev_err(&pdev->dev, "Failed to scan nand\n"); > + goto err_gpio_free; > + } > + > + if (pdata && pdata->ident_callback) { > + pdata->ident_callback(pdev, chip, &pdata->partitions, > + &pdata->num_partitions); > + } > + > + ret = nand_scan_tail(mtd); > + if (ret) { > + dev_err(&pdev->dev, "Failed to scan nand\n"); > + goto err_gpio_free; > + } > + > +#ifdef CONFIG_MTD_PARTITIONS > +#ifdef CONFIG_MTD_CMDLINE_PARTS > + num_partitions = parse_mtd_partitions(mtd, part_probes, > + &partition_info, 0); > +#endif > + if (num_partitions <= 0 && pdata) { > + num_partitions = pdata->num_partitions; > + partition_info = pdata->partitions; > + } > + > + if (num_partitions > 0) > + ret = add_mtd_partitions(mtd, partition_info, num_partitions); > + else > +#endif > + ret = add_mtd_device(mtd); > + > + if (ret) { > + dev_err(&pdev->dev, "Failed to add mtd device\n"); > + goto err_nand_release; > + } > + > + dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n"); > + > + return 0; > +err_nand_release: > + nand_release(&nand->mtd); > +err_gpio_free: > + platform_set_drvdata(pdev, NULL); > + gpio_free(pdata->busy_gpio); > +err_iounmap: > + iounmap(nand->base); > +err_release_mem: > + release_mem_region(nand->mem->start, resource_size(nand->mem)); > +err_free: > + kfree(nand); > + return ret; > +} > + > +static int __devexit jz_nand_remove(struct platform_device *pdev) > +{ > + struct jz_nand *nand = platform_get_drvdata(pdev); > + > + nand_release(&nand->mtd); > + > + iounmap(nand->base); > + release_mem_region(nand->mem->start, resource_size(nand->mem)); > + > + platform_set_drvdata(pdev, NULL); > + kfree(nand); > + > + return 0; > +} > + > +struct platform_driver jz_nand_driver = { > + .probe = jz_nand_probe, > + .remove = __devexit_p(jz_nand_remove), > + .driver = { > + .name = "jz4740-nand", > + .owner = THIS_MODULE, > + }, > +}; > + > +static int __init jz_nand_init(void) > +{ > + return platform_driver_register(&jz_nand_driver); > +} > +module_init(jz_nand_init); > + > +static void __exit jz_nand_exit(void) > +{ > + platform_driver_unregister(&jz_nand_driver); > +} > +module_exit(jz_nand_exit); > + > +MODULE_LICENSE("GPL"); > +MODULE_AUTHOR("Lars-Peter Clausen "); > +MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC"); > +MODULE_ALIAS("platform:jz4740-nand"); > diff --git a/include/linux/mtd/jz4740_nand.h b/include/linux/mtd/jz4740_nand.h > new file mode 100644 > index 0000000..379f9b6 > --- /dev/null > +++ b/include/linux/mtd/jz4740_nand.h > @@ -0,0 +1,34 @@ > +/* > + * Copyright (C) 2009-2010, Lars-Peter Clausen > + * JZ4740 SoC NAND controller driver > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > + > +#ifndef __JZ_NAND_H__ > +#define __JZ_NAND_H__ > + > +#include > +#include > + > +struct jz_nand_platform_data { > + int num_partitions; > + struct mtd_partition *partitions; > + > + struct nand_ecclayout *ecc_layout; > + > + unsigned int busy_gpio; > + > + void (*ident_callback)(struct platform_device *, struct nand_chip *, > + struct mtd_partition **, int *num_partitions); > +}; > + > +#endif From lars@metafoo.de Mon Jul 5 00:48:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 00:48:18 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:58131 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492144Ab0GDWsM (ORCPT ); Mon, 5 Jul 2010 00:48:12 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id A230298B; Mon, 5 Jul 2010 00:48:05 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 1peHLjPh61FW; Mon, 5 Jul 2010 00:48:05 +0200 (CEST) Received: from [192.168.37.31] (port-92973.pppoe.wtnet.de [84.46.75.169]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 4025098A; Mon, 5 Jul 2010 00:48:03 +0200 (CEST) Message-ID: <4C310F90.5050106@metafoo.de> Date: Mon, 05 Jul 2010 00:47:44 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Samuel Ortiz CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: Re: [PATCH v2 22/26] MFD: Add JZ4740 ADC driver References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-23-git-send-email-lars@metafoo.de> In-Reply-To: <1276924111-11158-23-git-send-email-lars@metafoo.de> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27305 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi Samuel Could you take a look at this driver and say whether this driver looks ok or not? Thanks - - Lars Lars-Peter Clausen wrote: > This patch adds a MFD driver for the JZ4740 ADC unit. The driver is used to > demultiplex IRQs and synchronize access to shared registers between the battery, > hwmon and (future) touchscreen driver. > > Signed-off-by: Lars-Peter Clausen > Cc: Samuel Ortiz > --- > drivers/mfd/Kconfig | 8 + > drivers/mfd/Makefile | 1 + > drivers/mfd/jz4740-adc.c | 392 ++++++++++++++++++++++++++++++++++++++++++++ > include/linux/jz4740-adc.h | 32 ++++ > 4 files changed, 433 insertions(+), 0 deletions(-) > create mode 100644 drivers/mfd/jz4740-adc.c > create mode 100644 include/linux/jz4740-adc.h > > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > index 9da0e50..9cacc39 100644 > --- a/drivers/mfd/Kconfig > +++ b/drivers/mfd/Kconfig > @@ -482,6 +482,14 @@ config MFD_JANZ_CMODIO > host many different types of MODULbus daughterboards, including > CAN and GPIO controllers. > > +config MFD_JZ4740_ADC > + tristate "Support for the JZ4740 SoC ADC core" > + select MFD_CORE > + depends on MACH_JZ4740 > + help > + Say yes here if you want support for the ADC unit in the JZ4740 SoC. > + This driver is necessary for jz4740-battery and jz4740-hwmon driver. > + > endif # MFD_SUPPORT > > menu "Multimedia Capabilities Port drivers" > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > index fb503e7..a1a2765 100644 > --- a/drivers/mfd/Makefile > +++ b/drivers/mfd/Makefile > @@ -71,3 +71,4 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o > obj-$(CONFIG_LPC_SCH) += lpc_sch.o > obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o > obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o > +obj-$(CONFIG_MFD_JZ4740_ADC) += jz4740-adc.o > diff --git a/drivers/mfd/jz4740-adc.c b/drivers/mfd/jz4740-adc.c > new file mode 100644 > index 0000000..cac8a52 > --- /dev/null > +++ b/drivers/mfd/jz4740-adc.c > @@ -0,0 +1,392 @@ > +/* > + * Copyright (C) 2009-2010, Lars-Peter Clausen > + * JZ4740 SoC ADC driver > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + * This driver synchronizes access to the JZ4740 ADC core between the > + * JZ4740 battery and hwmon drivers. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +#include > + > + > +#define JZ_REG_ADC_ENABLE 0x00 > +#define JZ_REG_ADC_CFG 0x04 > +#define JZ_REG_ADC_CTRL 0x08 > +#define JZ_REG_ADC_STATUS 0x0c > + > +#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10 > +#define JZ_REG_ADC_BATTERY_BASE 0x1c > +#define JZ_REG_ADC_HWMON_BASE 0x20 > + > +#define JZ_ADC_ENABLE_TOUCH BIT(2) > +#define JZ_ADC_ENABLE_BATTERY BIT(1) > +#define JZ_ADC_ENABLE_ADCIN BIT(0) > + > +enum { > + JZ_ADC_IRQ_ADCIN = 0, > + JZ_ADC_IRQ_BATTERY, > + JZ_ADC_IRQ_TOUCH, > + JZ_ADC_IRQ_PENUP, > + JZ_ADC_IRQ_PENDOWN, > +}; > + > +struct jz4740_adc { > + struct resource *mem; > + void __iomem *base; > + > + int irq; > + int irq_base; > + > + struct clk *clk; > + unsigned int clk_ref; > + > + spinlock_t lock; > +}; > + > +static inline void jz4740_adc_irq_set_masked(struct jz4740_adc *adc, int irq, > + bool masked) > +{ > + unsigned long flags; > + uint8_t val; > + > + irq -= adc->irq_base; > + > + spin_lock_irqsave(&adc->lock, flags); > + > + val = readb(adc->base + JZ_REG_ADC_CTRL); > + if (masked) > + val |= BIT(irq); > + else > + val &= ~BIT(irq); > + writeb(val, adc->base + JZ_REG_ADC_CTRL); > + > + spin_unlock_irqrestore(&adc->lock, flags); > +} > + > +static void jz4740_adc_irq_mask(unsigned int irq) > +{ > + struct jz4740_adc *adc = get_irq_chip_data(irq); > + jz4740_adc_irq_set_masked(adc, irq, true); > +} > + > +static void jz4740_adc_irq_unmask(unsigned int irq) > +{ > + struct jz4740_adc *adc = get_irq_chip_data(irq); > + jz4740_adc_irq_set_masked(adc, irq, false); > +} > + > +static void jz4740_adc_irq_ack(unsigned int irq) > +{ > + struct jz4740_adc *adc = get_irq_chip_data(irq); > + > + irq -= adc->irq_base; > + writeb(BIT(irq), adc->base + JZ_REG_ADC_STATUS); > +} > + > +static struct irq_chip jz4740_adc_irq_chip = { > + .name = "jz4740-adc", > + .mask = jz4740_adc_irq_mask, > + .unmask = jz4740_adc_irq_unmask, > + .ack = jz4740_adc_irq_ack, > +}; > + > +static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc) > +{ > + struct jz4740_adc *adc = get_irq_desc_data(desc); > + uint8_t status; > + unsigned int i; > + > + status = readb(adc->base + JZ_REG_ADC_STATUS); > + > + for (i = 0; i < 5; ++i) { > + if (status & BIT(i)) > + generic_handle_irq(adc->irq_base + i); > + } > +} > + > +static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) > +{ > + unsigned long flags; > + > + spin_lock_irqsave(&adc->lock, flags); > + if (adc->clk_ref++ == 0) > + clk_enable(adc->clk); > + spin_unlock_irqrestore(&adc->lock, flags); > +} > + > +static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc) > +{ > + unsigned long flags; > + > + spin_lock_irqsave(&adc->lock, flags); > + if (--adc->clk_ref == 0) > + clk_disable(adc->clk); > + spin_unlock_irqrestore(&adc->lock, flags); > +} > + > + > +static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine, > + bool enabled) > +{ > + unsigned long flags; > + uint8_t val; > + > + spin_lock_irqsave(&adc->lock, flags); > + > + val = readb(adc->base + JZ_REG_ADC_ENABLE); > + if (enabled) > + val |= BIT(engine); > + else > + val &= BIT(engine); > + writeb(val, adc->base + JZ_REG_ADC_ENABLE); > + > + spin_unlock_irqrestore(&adc->lock, flags); > +} > + > +static int jz4740_adc_cell_enable(struct platform_device *pdev) > +{ > + struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); > + > + jz4740_adc_clk_enable(adc); > + jz4740_adc_set_enabled(adc, pdev->id, true); > + > + return 0; > +} > + > +static int jz4740_adc_cell_disable(struct platform_device *pdev) > +{ > + struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); > + > + jz4740_adc_set_enabled(adc, pdev->id, false); > + jz4740_adc_clk_disable(adc); > + > + return 0; > +} > + > +int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val) > +{ > + struct jz4740_adc *adc = dev_get_drvdata(dev); > + unsigned long flags; > + uint32_t cfg; > + > + if (!adc) > + return -ENODEV; > + > + spin_lock_irqsave(&adc->lock, flags); > + > + cfg = readl(adc->base + JZ_REG_ADC_CFG); > + > + cfg &= ~mask; > + cfg |= val; > + > + writel(cfg, adc->base + JZ_REG_ADC_CFG); > + > + spin_unlock_irqrestore(&adc->lock, flags); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(jz4740_adc_set_config); > + > +static struct resource jz4740_hwmon_resources[] = { > + { > + .start = JZ_ADC_IRQ_ADCIN, > + .flags = IORESOURCE_IRQ, > + }, > + { > + .start = JZ_REG_ADC_HWMON_BASE, > + .end = JZ_REG_ADC_HWMON_BASE + 3, > + .flags = IORESOURCE_MEM, > + }, > +}; > + > +static struct resource jz4740_battery_resources[] = { > + { > + .start = JZ_ADC_IRQ_BATTERY, > + .flags = IORESOURCE_IRQ, > + }, > + { > + .start = JZ_REG_ADC_BATTERY_BASE, > + .end = JZ_REG_ADC_BATTERY_BASE + 3, > + .flags = IORESOURCE_MEM, > + }, > +}; > + > +const struct mfd_cell jz4740_adc_cells[] = { > + { > + .id = 0, > + .name = "jz4740-hwmon", > + .num_resources = ARRAY_SIZE(jz4740_hwmon_resources), > + .resources = jz4740_hwmon_resources, > + .platform_data = (void *)&jz4740_adc_cells[0], > + .data_size = sizeof(struct mfd_cell), > + > + .enable = jz4740_adc_cell_enable, > + .disable = jz4740_adc_cell_disable, > + }, > + { > + .id = 1, > + .name = "jz4740-battery", > + .num_resources = ARRAY_SIZE(jz4740_battery_resources), > + .resources = jz4740_battery_resources, > + .platform_data = (void *)&jz4740_adc_cells[1], > + .data_size = sizeof(struct mfd_cell), > + > + .enable = jz4740_adc_cell_enable, > + .disable = jz4740_adc_cell_disable, > + }, > +}; > + > +static int __devinit jz4740_adc_probe(struct platform_device *pdev) > +{ > + int ret; > + struct jz4740_adc *adc; > + struct resource *mem_base; > + int irq; > + > + adc = kmalloc(sizeof(*adc), GFP_KERNEL); > + > + adc->irq = platform_get_irq(pdev, 0); > + if (adc->irq < 0) { > + ret = adc->irq; > + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); > + goto err_free; > + } > + > + adc->irq_base = platform_get_irq(pdev, 1); > + if (adc->irq_base < 0) { > + ret = adc->irq_base; > + dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret); > + goto err_free; > + } > + > + mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!mem_base) { > + ret = -ENOENT; > + dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); > + goto err_free; > + } > + > + /* Only request the shared registers for the MFD driver */ > + adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, > + pdev->name); > + if (!adc->mem) { > + ret = -EBUSY; > + dev_err(&pdev->dev, "Failed to request mmio memory region\n"); > + goto err_free; > + } > + > + adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); > + if (!adc->base) { > + ret = -EBUSY; > + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); > + goto err_release_mem_region; > + } > + > + adc->clk = clk_get(&pdev->dev, "adc"); > + if (IS_ERR(adc->clk)) { > + ret = PTR_ERR(adc->clk); > + dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); > + goto err_iounmap; > + } > + > + spin_lock_init(&adc->lock); > + > + adc->clk_ref = 0; > + > + platform_set_drvdata(pdev, adc); > + > + for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) { > + set_irq_chip_data(irq, adc); > + set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip, > + handle_level_irq); > + } > + > + set_irq_data(adc->irq, adc); > + set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux); > + > + writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); > + writeb(0xff, adc->base + JZ_REG_ADC_CTRL); > + > + mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, > + ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base); > + > + return 0; > + > +err_iounmap: > + platform_set_drvdata(pdev, NULL); > + iounmap(adc->base); > +err_release_mem_region: > + release_mem_region(adc->mem->start, resource_size(adc->mem)); > +err_free: > + kfree(adc); > + > + return ret; > +} > + > +static int __devexit jz4740_adc_remove(struct platform_device *pdev) > +{ > + struct jz4740_adc *adc = platform_get_drvdata(pdev); > + > + mfd_remove_devices(&pdev->dev); > + > + set_irq_data(adc->irq, NULL); > + set_irq_chained_handler(adc->irq, NULL); > + > + iounmap(adc->base); > + release_mem_region(adc->mem->start, resource_size(adc->mem)); > + > + clk_put(adc->clk); > + > + platform_set_drvdata(pdev, NULL); > + > + kfree(adc); > + > + return 0; > +} > + > +struct platform_driver jz4740_adc_driver = { > + .probe = jz4740_adc_probe, > + .remove = __devexit_p(jz4740_adc_remove), > + .driver = { > + .name = "jz4740-adc", > + .owner = THIS_MODULE, > + }, > +}; > + > +static int __init jz4740_adc_init(void) > +{ > + return platform_driver_register(&jz4740_adc_driver); > +} > +module_init(jz4740_adc_init); > + > +static void __exit jz4740_adc_exit(void) > +{ > + platform_driver_unregister(&jz4740_adc_driver); > +} > +module_exit(jz4740_adc_exit); > + > +MODULE_DESCRIPTION("JZ4740 SoC ADC driver"); > +MODULE_AUTHOR("Lars-Peter Clausen "); > +MODULE_LICENSE("GPL"); > +MODULE_ALIAS("platform:jz4740-adc"); > diff --git a/include/linux/jz4740-adc.h b/include/linux/jz4740-adc.h > new file mode 100644 > index 0000000..9053f95 > --- /dev/null > +++ b/include/linux/jz4740-adc.h > @@ -0,0 +1,32 @@ > + > +#ifndef __LINUX_JZ4740_ADC > +#define __LINUX_JZ4740_ADC > + > +#include > + > +/* > + * jz4740_adc_set_config - Configure a JZ4740 adc device > + * @dev: Pointer to a jz4740-adc device > + * @mask: Mask for the config value to be set > + * @val: Value to be set > + * > + * This function can be used by the JZ4740 ADC mfd cells to configure their > + * options in the shared config register. > +*/ > +int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val); > + > +#define JZ_ADC_CONFIG_SPZZ BIT(31) > +#define JZ_ADC_CONFIG_EX_IN BIT(30) > +#define JZ_ADC_CONFIG_DNUM_MASK (0x7 << 16) > +#define JZ_ADC_CONFIG_DMA_ENABLE BIT(15) > +#define JZ_ADC_CONFIG_XYZ_MASK (0x2 << 13) > +#define JZ_ADC_CONFIG_SAMPLE_NUM_MASK (0x7 << 10) > +#define JZ_ADC_CONFIG_CLKDIV_MASK (0xf << 5) > +#define JZ_ADC_CONFIG_BAT_MB BIT(4) > + > +#define JZ_ADC_CONFIG_DNUM(dnum) ((dnum) << 16) > +#define JZ_ADC_CONFIG_XYZ_OFFSET(dnum) ((xyz) << 13) > +#define JZ_ADC_CONFIG_SAMPLE_NUM(x) ((x) << 10) > +#define JZ_ADC_CONFIG_CLKDIV(div) ((div) << 5) > + > +#endif -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkwxD5AACgkQBX4mSR26RiN/pgCfbdAlLjaN4Ot91yNDkNs+27TX f90AoIFB5pXsuLK+6lQbqq5WUt8cOhlM =wFGF -----END PGP SIGNATURE----- From shinya.kuribayashi.px@renesas.com Mon Jul 5 02:34:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 02:34:10 +0200 (CEST) Received: from TYO202.gate.nec.co.jp ([202.32.8.206]:50961 "EHLO tyo202.gate.nec.co.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491798Ab0GEAeG (ORCPT ); Mon, 5 Jul 2010 02:34:06 +0200 Received: from mailgate4.nec.co.jp ([10.7.69.184]) by tyo202.gate.nec.co.jp (8.13.8/8.13.4) with ESMTP id o650Y07L015324; Mon, 5 Jul 2010 09:34:00 +0900 (JST) Received: (from root@localhost) by mailgate4.nec.co.jp (8.11.7/3.7W-MAILGATE-NEC) id o650Y0R04374; Mon, 5 Jul 2010 09:34:00 +0900 (JST) Received: from relay61.aps.necel.com ([10.29.19.64]) by vgate02.nec.co.jp (8.11.7/3.7W-MAILSV-NEC) with ESMTP id o650Xx902560; Mon, 5 Jul 2010 09:33:59 +0900 (JST) Received: from realmbox31.aps.necel.com ([10.29.19.28] [10.29.19.28]) by relay61.aps.necel.com with ESMTP; Mon, 5 Jul 2010 09:33:59 +0900 Received: from [10.114.180.181] ([10.114.180.181] [10.114.180.181]) by mbox02.aps.necel.com with ESMTP; Mon, 5 Jul 2010 09:33:59 +0900 Message-ID: <4C312860.3020005@renesas.com> Date: Mon, 05 Jul 2010 09:33:36 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.4) Gecko/20100608 Lightning/1.0b2 Thunderbird/3.1 MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Shinya Kuribayashi , David VomLehn , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> <4C2F49D0.60200@pobox.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27306 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shinya.kuribayashi.px@renesas.com Precedence: bulk X-list: linux-mips Hi, On 7/4/2010 2:03 AM, Maciej W. Rozycki wrote: > Malta also supports a couple of MIPS IV processors too, so please be > careful about such assumptions. Ah, that's the answer I'm looking for, thanks! So current irq_ffs() form (clz() is enabled only when CONFIG_CPU_MIPS32/64 is selected) is well-suited for Malta platform, and it seems better to leave them as they are. I'll drop the patch from my list. >> + if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { >> + int x; >> + __asm__( >> + " .set push \n" >> + " .set mips32 \n" >> + " clz %0, %1 \n" >> + " .set pop \n" >> + : "=r" (x) >> + : "r" (pending)); >> + >> + return -x + 31 - CAUSEB_IP; >> + } > > Hmm, ".set mips32" looks dodgy here. For pre-MIPS32/64 platforms this > code should never make it to the assembler and if it did, then a > build-time error is better than a run-time problem. I see, cpu_has_clo_clz doesn't work well for platforms such as Malta. Malta can support several ISAs at a time, which is very valuable, but hard to be optimized :-) > It might be simpler just to use __builtin_ffs() for this variant though. > Inline assembly is better avoided unless absolutely required. Not even > mentioning readability. Hm. It might be simpler, but it's not the purpose of irq_ffs(), IMHO. -- Shinya Kuribayashi Renesas Electronics From adnan.iqbal@seecs.edu.pk Mon Jul 5 07:27:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 07:27:39 +0200 (CEST) Received: from na3sys009aog102.obsmtp.com ([74.125.149.69]:50975 "HELO na3sys009aog102.obsmtp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491115Ab0GEF1g (ORCPT ); Mon, 5 Jul 2010 07:27:36 +0200 Received: from source ([209.85.214.178]) by na3sys009aob102.postini.com ([74.125.148.12]) with SMTP ID DSNKTDFtRXhlHCXfFhNCq6uksoDF25uci35M@postini.com; Sun, 04 Jul 2010 22:27:35 PDT Received: by iwn9 with SMTP id 9so1138661iwn.9 for ; Sun, 04 Jul 2010 22:27:33 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.14.201 with SMTP id h9mr2942851iba.129.1278307652856; Sun, 04 Jul 2010 22:27:32 -0700 (PDT) Received: by 10.231.173.21 with HTTP; Sun, 4 Jul 2010 22:27:32 -0700 (PDT) Date: Mon, 5 Jul 2010 10:27:32 +0500 Message-ID: Subject: Issue with RLIMIT Identifiers From: adnan iqbal To: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=00221534d4d38fedae048a9d315e Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27307 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: adnan.iqbal@seecs.edu.pk Precedence: bulk X-list: linux-mips --00221534d4d38fedae048a9d315e Content-Type: text/plain; charset=ISO-8859-1 > > Dear all, I am using debian/octeon box. In the file /usr/local/asm-generic.h , RLIMIT_NOFILE is defined to be equal to 7. In /usr/local/Cavium_Networks/OCTEON-SDK/tools/usr/include/asm/resource.h:#define RLIMIT_NOFILE 5 In /usr/local/Cavium_Networks/OCTEON-SDK/tools/usr/include/asm-generic/resource.h:# define RLIMIT_NOFILE 7 i have confirmed through C program that the operating system is using RLIMIT_NOFILE=5. I need help to figure out which header files are actually being used by the kernel to get exact Resource Identifier. Regards Adnan --00221534d4d38fedae048a9d315e Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Dear all,
=A0
I am using debian/octeon box.
=A0
In the file /usr/local/asm-generic.h ,=A0RLIMIT_NOFILE=A0=A0=A0is defi= ned to be equal to 7.
=A0
In /usr/local/Cavium_Networks/OCTEON-SDK/tools/usr/include/asm/resourc= e.h:#define RLIMIT_NOFILE=A0=A0=A0=A0=A0=A0=A0=A0 5
=A0
In /usr/local/Cavium_Networks/OCTEON-SDK/tools/usr/include/asm-generic= /resource.h:# define RLIMIT_NOFILE=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0 7
i have confirmed through C program that the operating system is using = RLIMIT_NOFILE=3D5. I need help to figure out which header files are actuall= y being used by the kernel to get exact Resource Identifier.
=A0
Regards
Adnan
--00221534d4d38fedae048a9d315e-- From ralf@linux-mips.org Mon Jul 5 10:14:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 10:14:19 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48277 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491775Ab0GEIOQ (ORCPT ); Mon, 5 Jul 2010 10:14:16 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o658E5o8004421; Mon, 5 Jul 2010 09:14:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o658E3YB004419; Mon, 5 Jul 2010 09:14:03 +0100 Date: Mon, 5 Jul 2010 09:14:02 +0100 From: Ralf Baechle To: Christoph Egger Cc: Shane McDonald , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, vamos@i4.informatik.uni-erlangen.de Subject: Re: [PATCH 5/9] Removing dead CONFIG_BLK_DEV_IDE Message-ID: <20100705081402.GB740@linux-mips.org> References: <73e9e4bd7615488c9567f02f8962825386956365.1275925108.git.siccegge@cs.fau.de> <20100616113548.GA10065@faui48a.informatik.uni-erlangen.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100616113548.GA10065@faui48a.informatik.uni-erlangen.de> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27308 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 16, 2010 at 01:35:48PM +0200, Christoph Egger wrote: > On Thu, Jun 10, 2010 at 12:23:06PM -0600, Shane McDonald wrote: > > I wonder if, instead of deleting the code, the constant should be > > changed from CONFIG_BLK_DEV_IDE to CONFIG_IDE. The original > > patch that removed CONFIG_BLK_DEV_IDE seemed to make this change: > > http://kerneltrap.org/mailarchive/linux-kernel/2008/8/13/2929444 > > > > Shane > > You're probably right, updated patch below > > ------- > From: Christoph Egger > Date: Mon, 7 Jun 2010 17:29:48 +0200 > Subject: [PATCH 5/9] Removing dead CONFIG_BLK_DEV_IDE > > CONFIG_BLK_DEV_IDE doesn't exist in Kconfig, therefore removing all > references for it from the source code. > > Signed-off-by: Christoph Egger > --- > diff --git a/arch/mips/mti-malta/malta-setup.c > b/arch/mips/mti-malta/malta-setup.c > index b7f37d4..f6a5ea8 100644 > --- a/arch/mips/mti-malta/malta-setup.c > +++ b/arch/mips/mti-malta/malta-setup.c > @@ -105,7 +105,7 @@ static void __init fd_activate(void) > } > #endif > > -#ifdef CONFIG_BLK_DEV_IDE > +#ifdef CONFIG_IDE This doesn't fly too well either. CONFIG_BLK_DEV_IDE was a bool but CONFIG_IDE is tristate. But changing the ifdef to #if defined(CONFIG_IDE) || defined(CONFIG_IDE_MODULE) wouldn't really work either. I think this needs some generic infrastructure to get the PCI clock. Or maybe this is just another reason to scrap IDE support. Ralf From ralf@linux-mips.org Mon Jul 5 10:57:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 10:57:36 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35323 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491970Ab0GEI5b (ORCPT ); Mon, 5 Jul 2010 10:57:31 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o658vNC9006093; Mon, 5 Jul 2010 09:57:24 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o658vKnO006092; Mon, 5 Jul 2010 09:57:20 +0100 Date: Mon, 5 Jul 2010 09:57:20 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Christoph Egger , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, vamos@i4.informatik.uni-erlangen.de Subject: Re: [PATCH 6/9] Removing dead CONFIG_I2C_PNX0105 Message-ID: <20100705085719.GA4461@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27309 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 09, 2010 at 01:47:33PM +0200, Manuel Lauss wrote: > The code should probably just be adjusted to use the i2c-pnx driver. > According to the comments it supports the pnx0105 i2c cell. So something like this then. Signed-off-by: Ralf Baechle arch/mips/pnx833x/common/platform.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) Index: linux-queue/arch/mips/pnx833x/common/platform.c =================================================================== --- linux-queue.orig/arch/mips/pnx833x/common/platform.c +++ linux-queue/arch/mips/pnx833x/common/platform.c @@ -24,6 +24,7 @@ */ #include #include +#include #include #include #include @@ -33,11 +34,6 @@ #include #include -#ifdef CONFIG_I2C_PNX0105 -/* Until i2c driver available in kernel.*/ -#include -#endif - #include #include #include @@ -134,7 +130,6 @@ static struct platform_device pnx833x_us .resource = pnx833x_usb_ehci_resources, }; -#ifdef CONFIG_I2C_PNX0105 static struct resource pnx833x_i2c0_resources[] = { { .start = PNX833X_I2C0_PORTS_START, @@ -188,7 +183,7 @@ static struct platform_device pnx833x_i2 }; static struct platform_device pnx833x_i2c1_device = { - .name = "i2c-pnx0105", + .name = "pnx-i2c", .id = 1, .dev = { .platform_data = &pnx833x_i2c_dev[1], @@ -196,7 +191,6 @@ static struct platform_device pnx833x_i2 .num_resources = ARRAY_SIZE(pnx833x_i2c1_resources), .resource = pnx833x_i2c1_resources, }; -#endif static u64 ethernet_dmamask = DMA_BIT_MASK(32); @@ -297,10 +291,8 @@ static struct platform_device pnx833x_fl static struct platform_device *pnx833x_platform_devices[] __initdata = { &pnx833x_uart_device, &pnx833x_usb_ehci_device, -#ifdef CONFIG_I2C_PNX0105 &pnx833x_i2c0_device, &pnx833x_i2c1_device, -#endif &pnx833x_ethernet_device, &pnx833x_sata_device, &pnx833x_flash_nand, From ralf@linux-mips.org Mon Jul 5 11:11:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 11:11:33 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53198 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491875Ab0GEJL3 (ORCPT ); Mon, 5 Jul 2010 11:11:29 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o659BOWT006474; Mon, 5 Jul 2010 10:11:24 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o659BOMV006473; Mon, 5 Jul 2010 10:11:24 +0100 Date: Mon, 5 Jul 2010 10:11:24 +0100 From: Ralf Baechle To: Shane McDonald Cc: Christoph Egger , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, vamos@i4.informatik.uni-erlangen.de Subject: Re: [PATCH 7/9] Removing dead CONFIG_PMCTWILED Message-ID: <20100705091124.GB4461@linux-mips.org> References: <0a4b5e5841e7842f7b80e368c1d103b5e98d3335.1275925108.git.siccegge@cs.fau.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27310 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 10, 2010 at 01:24:08PM -0600, Shane McDonald wrote: > On Wed, Jun 9, 2010 at 5:22 AM, Christoph Egger wrote: > > CONFIG_PMCTWILED doesn't exist in Kconfig, therefore removing all > > references for it from the source code. > > > > Signed-off-by: Christoph Egger Queued for 2.6.26. Thanks, Ralf From ralf@linux-mips.org Mon Jul 5 11:46:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 11:46:42 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33426 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491884Ab0GEJq2 (ORCPT ); Mon, 5 Jul 2010 11:46:28 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o659kJrn007431; Mon, 5 Jul 2010 10:46:20 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o659kEWD007430; Mon, 5 Jul 2010 10:46:14 +0100 Date: Mon, 5 Jul 2010 10:46:14 +0100 From: Ralf Baechle To: Christoph Egger Cc: David VomLehn , Yoichi Yuasa , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, vamos@i4.informatik.uni-erlangen.de Subject: Re: [PATCH 8/9] Removing dead CONFIG_DIAGNOSTICS Message-ID: <20100705094613.GC4461@linux-mips.org> References: <9193680d40b6545b05e09d4906980397cb29a2fe.1275925108.git.siccegge@cs.fau.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9193680d40b6545b05e09d4906980397cb29a2fe.1275925108.git.siccegge@cs.fau.de> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27311 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 09, 2010 at 01:23:02PM +0200, Christoph Egger wrote: No comments received and seems to make sense so queued for 2.6.36. Thanks, Ralf From ralf@linux-mips.org Mon Jul 5 11:57:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 11:57:44 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40703 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491928Ab0GEJ5l (ORCPT ); Mon, 5 Jul 2010 11:57:41 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o659vVx9009716; Mon, 5 Jul 2010 10:57:32 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o659vUvJ009715; Mon, 5 Jul 2010 10:57:30 +0100 Date: Mon, 5 Jul 2010 10:57:28 +0100 From: Ralf Baechle To: Shane McDonald Cc: Christoph Egger , Yoichi Yuasa , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, vamos@i4.informatik.uni-erlangen.de Subject: Re: [PATCH 9/9] Removing dead CONFIG_MTD_PMC_MSP_RAMROOT Message-ID: <20100705095727.GD4461@linux-mips.org> References: <2f41f9174bd6ba24b5609e06e87c47d5f44446d1.1275925108.git.siccegge@cs.fau.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27312 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, also queued for 2.6.26. Ralf From ralf@linux-mips.org Mon Jul 5 12:25:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 12:25:29 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53742 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491978Ab0GEKZ0 (ORCPT ); Mon, 5 Jul 2010 12:25:26 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o65APKjH012477; Mon, 5 Jul 2010 11:25:21 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o65APK45012475; Mon, 5 Jul 2010 11:25:20 +0100 Date: Mon, 5 Jul 2010 11:25:19 +0100 From: Ralf Baechle To: David VomLehn Cc: linux-mips@linux-mips.org Subject: Re: [PATCH][MIPS] powertv: move device address setup before use Message-ID: <20100705102519.GE4461@linux-mips.org> References: <20100618235149.GA30686@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100618235149.GA30686@dvomlehn-lnx2.corp.sa.net> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27313 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Mon Jul 5 12:56:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 12:56:34 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54263 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491775Ab0GEK4b (ORCPT ); Mon, 5 Jul 2010 12:56:31 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o65AuSHd012989; Mon, 5 Jul 2010 11:56:28 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o65AuRr8012987; Mon, 5 Jul 2010 11:56:27 +0100 Date: Mon, 5 Jul 2010 11:56:27 +0100 From: Ralf Baechle To: Matt Fleming Cc: linux-mips@linux-mips.org, Adam Jiang Subject: Re: How to detect STACKOVEFLOW on mips Message-ID: <20100705105627.GA12699@linux-mips.org> References: <20100630145006.GA31938@linux-mips.org> <87zkycyyi2.fsf@linux-g6p1.site> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87zkycyyi2.fsf@linux-g6p1.site> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27314 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 30, 2010 at 10:57:41PM +0100, Matt Fleming wrote: > On Wed, 30 Jun 2010 15:50:06 +0100, Ralf Baechle wrote: > > > > There used to be some code for other architectures that zeros the stack > > page and counts how much of that has been overwritten by the stack. That > > was never ported to MIPS. > > > > Another helper to find functions that do excessive static allocations is > > "make checkstack". > > Both SH and sparc use the mcount function (enabled with the -pg switch > to gcc) to check the stack has not overflowed. The relevant code is in > arch/{sh,sparc}/lib/mcount.S. This checks the stack pointer value on > every function call. Yeah, it's heavy-weight, but an implementation for > MIPS should be able to catch almost the exact point at which stack > overflow occurs. Which often isn't so helpful. The alarm gets triggered on the last stack pointer decrement but according to murphy the overflow has happened 10 levels up in the callchain. Ralf From ralf@linux-mips.org Mon Jul 5 13:44:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 13:44:04 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44106 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492082Ab0GELoB (ORCPT ); Mon, 5 Jul 2010 13:44:01 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o65Bht5Q013958; Mon, 5 Jul 2010 12:43:56 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o65BhrB9013957; Mon, 5 Jul 2010 12:43:53 +0100 Date: Mon, 5 Jul 2010 12:43:52 +0100 From: Ralf Baechle To: Shinya Kuribayashi Cc: "Maciej W. Rozycki" , Shinya Kuribayashi , David VomLehn , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required Message-ID: <20100705114352.GB12699@linux-mips.org> References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> <4C2F49D0.60200@pobox.com> <4C312860.3020005@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C312860.3020005@renesas.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27315 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jul 05, 2010 at 09:33:36AM +0900, Shinya Kuribayashi wrote: > On 7/4/2010 2:03 AM, Maciej W. Rozycki wrote: > > Malta also supports a couple of MIPS IV processors too, so please be > > careful about such assumptions. > > Ah, that's the answer I'm looking for, thanks! So current irq_ffs() > form (clz() is enabled only when CONFIG_CPU_MIPS32/64 is selected) is > well-suited for Malta platform, and it seems better to leave them as > they are. I'll drop the patch from my list. > > >> + if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { > >> + int x; > >> + __asm__( > >> + " .set push \n" > >> + " .set mips32 \n" > >> + " clz %0, %1 \n" > >> + " .set pop \n" > >> + : "=r" (x) > >> + : "r" (pending)); > >> + > >> + return -x + 31 - CAUSEB_IP; > >> + } > > > > Hmm, ".set mips32" looks dodgy here. For pre-MIPS32/64 platforms this > > code should never make it to the assembler and if it did, then a > > build-time error is better than a run-time problem. For pedantic accuracy - the IDT RC32364 introduced CLO and CLZ; in an act of uglyness the RC64574 then inherited these two instructions but did not add. though it was 64-bit not DCLO and DCLZ; the NEC VR5500 has the full complement of CLO, CLZ, DCLO and DCLZ. > I see, cpu_has_clo_clz doesn't work well for platforms such as Malta. > Malta can support several ISAs at a time, which is very valuable, but > hard to be optimized :-) While MIPS IV CPU cards for the Malta are available hardly anybody is using on of those cards. Thus cpu_has_clo_clz defaults to cpu_has_mips_r and ideally and platform should see cpu_has_mips_r to a constant to allow best possible optimization. Malta doesn't ... > > It might be simpler just to use __builtin_ffs() for this variant though. > > Inline assembly is better avoided unless absolutely required. Not even > > mentioning readability. > > Hm. It might be simpler, but it's not the purpose of irq_ffs(), IMHO. Indeed. Ralf From segooon@gmail.com Mon Jul 5 14:14:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 14:14:06 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:50416 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492082Ab0GEMOD (ORCPT ); Mon, 5 Jul 2010 14:14:03 +0200 Received: by wyb32 with SMTP id 32so3374888wyb.36 for ; Mon, 05 Jul 2010 05:13:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=aDGrzrtzkLyS63uEFBNzI8YGke3/ed8QNRJzQkIrwhs=; b=Falq3ivIqEGY57o2Jm7s3YJ+jEkE6GA1HBOuufaHrwV7KYAFm2C1cY5O9Sn9dyeOXD EYUrRz5PT7EORe+VzKjry/eAB5Tnte0KjubsuXFOYMPTCX7+JAWNSicYbxpkHS7nf+GU 7fZfsA8IJE0kIvx6WyaaPifBbOyzY5jwWi3rQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=P61DgGHO87V0MmsNgv5jBZStXxB5jlL+YZA0Vd8gXxHFvced+V9dW2noLmcwrx1LEQ XbGrN3zhWIkae8ZrnOwpcfYYQOB4YRAC+aJQnVVa4+PoCsgX1C3+9/cLe9VO2997yhYE OVgngVN4Uu10MkaTnSciOvMaeISjZ2sMAJ0Ck= Received: by 10.213.4.203 with SMTP id 11mr2104162ebs.13.1278332036980; Mon, 05 Jul 2010 05:13:56 -0700 (PDT) Received: from localhost (ppp85-140-163-91.pppoe.mtu-net.ru [85.140.163.91]) by mx.google.com with ESMTPS id a48sm34821182eei.0.2010.07.05.05.13.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 05 Jul 2010 05:13:56 -0700 (PDT) From: Kulikov Vasiliy To: Kernel Janitors Cc: Ralf Baechle , "David S. Miller" , Jiri Pirko , Eric Dumazet , Patrick McHardy , Alexey Dobriyan , linux-mips@linux-mips.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] ioc3-eth: Use the instance of net_device_stats from net_device. Date: Mon, 5 Jul 2010 16:13:51 +0400 Message-Id: <1278332034-17122-1-git-send-email-segooon@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27316 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: segooon@gmail.com Precedence: bulk X-list: linux-mips Since net_device has an instance of net_device_stats, we can remove the instance of this from the adapter structure. Signed-off-by: Kulikov Vasiliy --- drivers/net/ioc3-eth.c | 29 ++++++++++++++--------------- 1 files changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/net/ioc3-eth.c b/drivers/net/ioc3-eth.c index e3b5e94..0c005ad 100644 --- a/drivers/net/ioc3-eth.c +++ b/drivers/net/ioc3-eth.c @@ -82,7 +82,6 @@ struct ioc3_private { struct ioc3_etxd *txr; struct sk_buff *rx_skbs[512]; struct sk_buff *tx_skbs[128]; - struct net_device_stats stats; int rx_ci; /* RX consumer index */ int rx_pi; /* RX producer index */ int tx_ci; /* TX consumer index */ @@ -504,8 +503,8 @@ static struct net_device_stats *ioc3_get_stats(struct net_device *dev) struct ioc3_private *ip = netdev_priv(dev); struct ioc3 *ioc3 = ip->regs; - ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK); - return &ip->stats; + dev->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK); + return &dev->stats; } static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len) @@ -604,7 +603,7 @@ static inline void ioc3_rx(struct ioc3_private *ip) if (!new_skb) { /* Ouch, drop packet and just recycle packet to keep the ring filled. */ - ip->stats.rx_dropped++; + dev->stats.rx_dropped++; new_skb = skb; goto next; } @@ -622,19 +621,19 @@ static inline void ioc3_rx(struct ioc3_private *ip) rxb = (struct ioc3_erxbuf *) new_skb->data; skb_reserve(new_skb, RX_OFFSET); - ip->stats.rx_packets++; /* Statistics */ - ip->stats.rx_bytes += len; + dev->stats.rx_packets++; /* Statistics */ + dev->stats.rx_bytes += len; } else { - /* The frame is invalid and the skb never - reached the network layer so we can just - recycle it. */ - new_skb = skb; - ip->stats.rx_errors++; + /* The frame is invalid and the skb never + reached the network layer so we can just + recycle it. */ + new_skb = skb; + dev->stats.rx_errors++; } if (err & ERXBUF_CRCERR) /* Statistics */ - ip->stats.rx_crc_errors++; + dev->stats.rx_crc_errors++; if (err & ERXBUF_FRAMERR) - ip->stats.rx_frame_errors++; + dev->stats.rx_frame_errors++; next: ip->rx_skbs[n_entry] = new_skb; rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1)); @@ -681,8 +680,8 @@ static inline void ioc3_tx(struct ioc3_private *ip) tx_entry = (etcir >> 7) & 127; } - ip->stats.tx_packets += packets; - ip->stats.tx_bytes += bytes; + dev->stats.tx_packets += packets; + dev->stats.tx_bytes += bytes; ip->txqlen -= packets; if (ip->txqlen < 128) -- 1.7.0.4 From ralf@linux-mips.org Mon Jul 5 14:55:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 14:56:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:38121 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492100Ab0GEMz7 (ORCPT ); Mon, 5 Jul 2010 14:55:59 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o65CtrbE031228; Mon, 5 Jul 2010 13:55:54 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o65Ctj5C030974; Mon, 5 Jul 2010 13:55:46 +0100 Date: Mon, 5 Jul 2010 13:55:44 +0100 From: Ralf Baechle To: Kulikov Vasiliy Cc: Kernel Janitors , "David S. Miller" , Jiri Pirko , Eric Dumazet , Patrick McHardy , Alexey Dobriyan , linux-mips@linux-mips.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ioc3-eth: Use the instance of net_device_stats from net_device. Message-ID: <20100705125544.GA28849@linux-mips.org> References: <1278332034-17122-1-git-send-email-segooon@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1278332034-17122-1-git-send-email-segooon@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27317 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jul 05, 2010 at 04:13:51PM +0400, Kulikov Vasiliy wrote: > Since net_device has an instance of net_device_stats, > we can remove the instance of this from the adapter structure. > > Signed-off-by: Kulikov Vasiliy NACK, your patch doesn't compile. I'll post a fixed patch in a separate mail. Ralf From ralf@linux-mips.org Mon Jul 5 14:59:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 14:59:47 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36466 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492100Ab0GEM7o (ORCPT ); Mon, 5 Jul 2010 14:59:44 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o65Cxctl031299; Mon, 5 Jul 2010 13:59:38 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o65CxcHM031297; Mon, 5 Jul 2010 13:59:38 +0100 Date: Mon, 5 Jul 2010 13:59:38 +0100 From: Ralf Baechle To: "David S. Miller" Cc: Kulikov Vasiliy , Kernel Janitors , Jiri Pirko , Eric Dumazet , Patrick McHardy , Alexey Dobriyan , linux-mips@linux-mips.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [NET] ioc3-eth: Use the instance of net_device_stats from net_device. Message-ID: <20100705125938.GB28849@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27318 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Since net_device has an instance of net_device_stats, we can remove the instance of this from the adapter structure. Based on original patch by Kulikov Vasiliy. Signed-off-by: Ralf Baechle Signed-off-by: Kulikov Vasiliy drivers/net/ioc3-eth.c | 49 ++++++++++++++++++++++++----------------------- 1 files changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/net/ioc3-eth.c b/drivers/net/ioc3-eth.c index e3b5e94..0b3f6df 100644 --- a/drivers/net/ioc3-eth.c +++ b/drivers/net/ioc3-eth.c @@ -82,7 +82,6 @@ struct ioc3_private { struct ioc3_etxd *txr; struct sk_buff *rx_skbs[512]; struct sk_buff *tx_skbs[128]; - struct net_device_stats stats; int rx_ci; /* RX consumer index */ int rx_pi; /* RX producer index */ int tx_ci; /* TX consumer index */ @@ -504,8 +503,8 @@ static struct net_device_stats *ioc3_get_stats(struct net_device *dev) struct ioc3_private *ip = netdev_priv(dev); struct ioc3 *ioc3 = ip->regs; - ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK); - return &ip->stats; + dev->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK); + return &dev->stats; } static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len) @@ -576,8 +575,9 @@ static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len) skb->ip_summed = CHECKSUM_UNNECESSARY; } -static inline void ioc3_rx(struct ioc3_private *ip) +static inline void ioc3_rx(struct net_device *dev) { + struct ioc3_private *ip = netdev_priv(dev); struct sk_buff *skb, *new_skb; struct ioc3 *ioc3 = ip->regs; int rx_entry, n_entry, len; @@ -598,13 +598,13 @@ static inline void ioc3_rx(struct ioc3_private *ip) if (err & ERXBUF_GOODPKT) { len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4; skb_trim(skb, len); - skb->protocol = eth_type_trans(skb, priv_netdev(ip)); + skb->protocol = eth_type_trans(skb, dev); new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); if (!new_skb) { /* Ouch, drop packet and just recycle packet to keep the ring filled. */ - ip->stats.rx_dropped++; + dev->stats.rx_dropped++; new_skb = skb; goto next; } @@ -622,19 +622,19 @@ static inline void ioc3_rx(struct ioc3_private *ip) rxb = (struct ioc3_erxbuf *) new_skb->data; skb_reserve(new_skb, RX_OFFSET); - ip->stats.rx_packets++; /* Statistics */ - ip->stats.rx_bytes += len; + dev->stats.rx_packets++; /* Statistics */ + dev->stats.rx_bytes += len; } else { - /* The frame is invalid and the skb never - reached the network layer so we can just - recycle it. */ - new_skb = skb; - ip->stats.rx_errors++; + /* The frame is invalid and the skb never + reached the network layer so we can just + recycle it. */ + new_skb = skb; + dev->stats.rx_errors++; } if (err & ERXBUF_CRCERR) /* Statistics */ - ip->stats.rx_crc_errors++; + dev->stats.rx_crc_errors++; if (err & ERXBUF_FRAMERR) - ip->stats.rx_frame_errors++; + dev->stats.rx_frame_errors++; next: ip->rx_skbs[n_entry] = new_skb; rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1)); @@ -652,8 +652,9 @@ next: ip->rx_ci = rx_entry; } -static inline void ioc3_tx(struct ioc3_private *ip) +static inline void ioc3_tx(struct net_device *dev) { + struct ioc3_private *ip = netdev_priv(dev); unsigned long packets, bytes; struct ioc3 *ioc3 = ip->regs; int tx_entry, o_entry; @@ -681,12 +682,12 @@ static inline void ioc3_tx(struct ioc3_private *ip) tx_entry = (etcir >> 7) & 127; } - ip->stats.tx_packets += packets; - ip->stats.tx_bytes += bytes; + dev->stats.tx_packets += packets; + dev->stats.tx_bytes += bytes; ip->txqlen -= packets; if (ip->txqlen < 128) - netif_wake_queue(priv_netdev(ip)); + netif_wake_queue(dev); ip->tx_ci = o_entry; spin_unlock(&ip->ioc3_lock); @@ -699,9 +700,9 @@ static inline void ioc3_tx(struct ioc3_private *ip) * with such error interrupts if something really goes wrong, so we might * also consider to take the interface down. */ -static void ioc3_error(struct ioc3_private *ip, u32 eisr) +static void ioc3_error(struct net_device *dev, u32 eisr) { - struct net_device *dev = priv_netdev(ip); + struct ioc3_private *ip = netdev_priv(dev); unsigned char *iface = dev->name; spin_lock(&ip->ioc3_lock); @@ -747,11 +748,11 @@ static irqreturn_t ioc3_interrupt(int irq, void *_dev) if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR)) - ioc3_error(ip, eisr); + ioc3_error(dev, eisr); if (eisr & EISR_RXTIMERINT) - ioc3_rx(ip); + ioc3_rx(dev); if (eisr & EISR_TXEXPLICIT) - ioc3_tx(ip); + ioc3_tx(dev); return IRQ_HANDLED; } From matt@console-pimps.org Mon Jul 5 15:09:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 15:09:35 +0200 (CEST) Received: from arkanian.console-pimps.org ([212.110.184.194]:34271 "EHLO arkanian.console-pimps.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492055Ab0GENJc (ORCPT ); Mon, 5 Jul 2010 15:09:32 +0200 Received: by arkanian.console-pimps.org (Postfix, from userid 1000) id 97AB948044; Mon, 5 Jul 2010 14:09:31 +0100 (BST) Date: Mon, 5 Jul 2010 14:09:31 +0100 From: Matt Fleming To: Ralf Baechle Cc: linux-mips@linux-mips.org, Adam Jiang Subject: Re: How to detect STACKOVEFLOW on mips Message-ID: <20100705130931.GA2968@console-pimps.org> References: <20100630145006.GA31938@linux-mips.org> <87zkycyyi2.fsf@linux-g6p1.site> <20100705105627.GA12699@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100705105627.GA12699@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27319 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matt@console-pimps.org Precedence: bulk X-list: linux-mips On Mon, Jul 05, 2010 at 11:56:27AM +0100, Ralf Baechle wrote: > On Wed, Jun 30, 2010 at 10:57:41PM +0100, Matt Fleming wrote: > > > On Wed, 30 Jun 2010 15:50:06 +0100, Ralf Baechle wrote: > > > > > > There used to be some code for other architectures that zeros the stack > > > page and counts how much of that has been overwritten by the stack. That > > > was never ported to MIPS. > > > > > > Another helper to find functions that do excessive static allocations is > > > "make checkstack". > > > > Both SH and sparc use the mcount function (enabled with the -pg switch > > to gcc) to check the stack has not overflowed. The relevant code is in > > arch/{sh,sparc}/lib/mcount.S. This checks the stack pointer value on > > every function call. Yeah, it's heavy-weight, but an implementation for > > MIPS should be able to catch almost the exact point at which stack > > overflow occurs. > > Which often isn't so helpful. The alarm gets triggered on the last stack > pointer decrement but according to murphy the overflow has happened 10 > levels up in the callchain. Last decrement? The alarm should be triggered the next time the function in which the overflow occurs makes a function call. I don't see how you could go down a level of the callchain and not trigger the alarm if the overflow has happened? From macro@linux-mips.org Mon Jul 5 15:35:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 15:35:42 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:58738 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491191Ab0GENfh (ORCPT ); Mon, 5 Jul 2010 15:35:37 +0200 Date: Mon, 5 Jul 2010 14:35:37 +0100 (BST) From: "Maciej W. Rozycki" To: Shinya Kuribayashi cc: Shinya Kuribayashi , David VomLehn , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required In-Reply-To: <4C312860.3020005@renesas.com> Message-ID: References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> <4C2F49D0.60200@pobox.com> <4C312860.3020005@renesas.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27320 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 5 Jul 2010, Shinya Kuribayashi wrote: > Ah, that's the answer I'm looking for, thanks! So current irq_ffs() > form (clz() is enabled only when CONFIG_CPU_MIPS32/64 is selected) is > well-suited for Malta platform, and it seems better to leave them as > they are. I'll drop the patch from my list. You still can and probably want to optimise. You can have configuration dependencies in override files. > >> + if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { > >> + int x; > >> + __asm__( > >> + " .set push \n" > >> + " .set mips32 \n" > >> + " clz %0, %1 \n" > >> + " .set pop \n" > >> + : "=r" (x) > >> + : "r" (pending)); > >> + > >> + return -x + 31 - CAUSEB_IP; > >> + } > > > > Hmm, ".set mips32" looks dodgy here. For pre-MIPS32/64 platforms this > > code should never make it to the assembler and if it did, then a > > build-time error is better than a run-time problem. > > I see, cpu_has_clo_clz doesn't work well for platforms such as Malta. > Malta can support several ISAs at a time, which is very valuable, but > hard to be optimized :-) Well, seems to be getting this right. MIPS IV options are not included as quite rare compared to MIPS32/64 ones and run-time determined defaults apply. For MIPS32/64 configurations compile-time optimisations work as usually. > > It might be simpler just to use __builtin_ffs() for this variant though. > > Inline assembly is better avoided unless absolutely required. Not even > > mentioning readability. > > Hm. It might be simpler, but it's not the purpose of irq_ffs(), IMHO. My point is whenever cpu_has_clo_clz is hardcoded to 1 GCC will expand __builtin_ffs() to CLZ as expected and may potentially be able to optimise it further. For the fallback path I agree you do not want to use __builtin_ffs() as you want to save processing time of the unneeded bits -- there's no 8-bit FFS intrinsic let alone a 4-bit one (I'm assuming there is a reason this piece of code does not check lower 4 interrupt inputs). Maciej From ralf@linux-mips.org Mon Jul 5 15:36:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 15:36:07 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48467 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491802Ab0GENfk (ORCPT ); Mon, 5 Jul 2010 15:35:40 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o65DZYYk001340; Mon, 5 Jul 2010 14:35:35 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o65DZXt9001338; Mon, 5 Jul 2010 14:35:33 +0100 Date: Mon, 5 Jul 2010 14:35:33 +0100 From: Ralf Baechle To: Matt Fleming Cc: linux-mips@linux-mips.org, Adam Jiang Subject: Re: How to detect STACKOVEFLOW on mips Message-ID: <20100705133533.GA1262@linux-mips.org> References: <20100630145006.GA31938@linux-mips.org> <87zkycyyi2.fsf@linux-g6p1.site> <20100705105627.GA12699@linux-mips.org> <20100705130931.GA2968@console-pimps.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100705130931.GA2968@console-pimps.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27321 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jul 05, 2010 at 02:09:31PM +0100, Matt Fleming wrote: > > Which often isn't so helpful. The alarm gets triggered on the last stack > > pointer decrement but according to murphy the overflow has happened 10 > > levels up in the callchain. > > Last decrement? The alarm should be triggered the next time the > function in which the overflow occurs makes a function call. I don't > see how you could go down a level of the callchain and not trigger the > alarm if the overflow has happened? guilt() { char array[6000]; blurb(&array); } blurb(void *p) { frob(p); } With the deep nesting of the current kernel there is a good chance a check in mcount will not be triggered in blurb() but possibly in frob or even further down the callchain. Ralf From matt@console-pimps.org Mon Jul 5 16:08:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 16:08:21 +0200 (CEST) Received: from arkanian.console-pimps.org ([212.110.184.194]:53330 "EHLO arkanian.console-pimps.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492106Ab0GEOIS (ORCPT ); Mon, 5 Jul 2010 16:08:18 +0200 Received: by arkanian.console-pimps.org (Postfix, from userid 1000) id 065E148044; Mon, 5 Jul 2010 15:08:17 +0100 (BST) Date: Mon, 5 Jul 2010 15:08:16 +0100 From: Matt Fleming To: Ralf Baechle Cc: linux-mips@linux-mips.org, Adam Jiang Subject: Re: How to detect STACKOVEFLOW on mips Message-ID: <20100705140816.GB2968@console-pimps.org> References: <20100630145006.GA31938@linux-mips.org> <87zkycyyi2.fsf@linux-g6p1.site> <20100705105627.GA12699@linux-mips.org> <20100705130931.GA2968@console-pimps.org> <20100705133533.GA1262@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100705133533.GA1262@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27322 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matt@console-pimps.org Precedence: bulk X-list: linux-mips On Mon, Jul 05, 2010 at 02:35:33PM +0100, Ralf Baechle wrote: > On Mon, Jul 05, 2010 at 02:09:31PM +0100, Matt Fleming wrote: > > > > Which often isn't so helpful. The alarm gets triggered on the last stack > > > pointer decrement but according to murphy the overflow has happened 10 > > > levels up in the callchain. > > > > Last decrement? The alarm should be triggered the next time the > > function in which the overflow occurs makes a function call. I don't > > see how you could go down a level of the callchain and not trigger the > > alarm if the overflow has happened? > > guilt() > { > char array[6000]; > > blurb(&array); > } > > blurb(void *p) > { > frob(p); > } > > With the deep nesting of the current kernel there is a good chance a > check in mcount will not be triggered in blurb() but possibly in frob > or even further down the callchain. Ah, I think I see what you mean. You're saying that you may not find the culprit function using the massive amount of stack spac, which eventually leads to the overflow? Yeah, that's a fair point. I think if the mcount technique was used in conjunction with CONFIG_DEBUG_STACK_USAGE it might be more helpful in that situation. From ralf@linux-mips.org Mon Jul 5 16:37:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 16:37:03 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:55253 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490949Ab0GEOg7 (ORCPT ); Mon, 5 Jul 2010 16:36:59 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o65Eav3H003089; Mon, 5 Jul 2010 15:36:58 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o65EatAA003088; Mon, 5 Jul 2010 15:36:55 +0100 Date: Mon, 5 Jul 2010 15:36:55 +0100 From: Ralf Baechle To: adnan iqbal Cc: linux-mips@linux-mips.org Subject: Re: Issue with RLIMIT Identifiers Message-ID: <20100705143655.GA3035@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27323 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jul 05, 2010 at 10:27:32AM +0500, adnan iqbal wrote: > In the file /usr/local/asm-generic.h , RLIMIT_NOFILE is defined to be > equal to 7. > > In > /usr/local/Cavium_Networks/OCTEON-SDK/tools/usr/include/asm/resource.h:#define > RLIMIT_NOFILE 5 > > In > /usr/local/Cavium_Networks/OCTEON-SDK/tools/usr/include/asm-generic/resource.h:# > define RLIMIT_NOFILE 7 > i have confirmed through C program that the operating system is using > RLIMIT_NOFILE=5. I need help to figure out which header files are actually > being used by the kernel to get exact Resource Identifier. The non-generic definition, that is RLIMIT_NOFILE is defined as 5. Ralf From sameo@linux.intel.com Mon Jul 5 16:58:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 16:58:23 +0200 (CEST) Received: from mga14.intel.com ([143.182.124.37]:33651 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490949Ab0GEO6S (ORCPT ); Mon, 5 Jul 2010 16:58:18 +0200 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 05 Jul 2010 07:53:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.53,540,1272870000"; d="scan'208";a="296679096" Received: from unknown (HELO sortiz-mobl) ([10.255.17.75]) by azsmga001.ch.intel.com with ESMTP; 05 Jul 2010 07:53:07 -0700 Date: Mon, 5 Jul 2010 16:53:08 +0200 From: Samuel Ortiz To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 22/26] MFD: Add JZ4740 ADC driver Message-ID: <20100705145306.GA3850@sortiz-mobl> References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-23-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276924111-11158-23-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27324 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sameo@linux.intel.com Precedence: bulk X-list: linux-mips Hi Lars, Sorry for the review delay. This one got lost in my inbox :-/ On Sat, Jun 19, 2010 at 07:08:27AM +0200, Lars-Peter Clausen wrote: > This patch adds a MFD driver for the JZ4740 ADC unit. The driver is used to > demultiplex IRQs and synchronize access to shared registers between the battery, > hwmon and (future) touchscreen driver. The driver looks pretty clean. I only have a couple nitpicks: > +static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc) > +{ > + struct jz4740_adc *adc = get_irq_desc_data(desc); > + uint8_t status; > + unsigned int i; > + > + status = readb(adc->base + JZ_REG_ADC_STATUS); > + > + for (i = 0; i < 5; ++i) { > + if (status & BIT(i)) > + generic_handle_irq(adc->irq_base + i); for_each_set_bit() could nicely replace your loop here. > +static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) > +{ > + unsigned long flags; > + > + spin_lock_irqsave(&adc->lock, flags); > + if (adc->clk_ref++ == 0) > + clk_enable(adc->clk); > + spin_unlock_irqrestore(&adc->lock, flags); > +} I'm not familiar with your platform clock framework, but shouldn't the refcounting be handled there instead of spread over all your drivers ? > +static int __devinit jz4740_adc_probe(struct platform_device *pdev) > +{ > + int ret; > + struct jz4740_adc *adc; > + struct resource *mem_base; > + int irq; > + > + adc = kmalloc(sizeof(*adc), GFP_KERNEL); > + > + adc->irq = platform_get_irq(pdev, 0); > + if (adc->irq < 0) { > + ret = adc->irq; > + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); > + goto err_free; > + } > + > + adc->irq_base = platform_get_irq(pdev, 1); > + if (adc->irq_base < 0) { > + ret = adc->irq_base; > + dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret); > + goto err_free; > + } > + > + mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!mem_base) { > + ret = -ENOENT; > + dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); > + goto err_free; > + } > + > + /* Only request the shared registers for the MFD driver */ > + adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, > + pdev->name); > + if (!adc->mem) { > + ret = -EBUSY; > + dev_err(&pdev->dev, "Failed to request mmio memory region\n"); > + goto err_free; > + } > + > + adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); > + if (!adc->base) { > + ret = -EBUSY; > + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); > + goto err_release_mem_region; > + } > + > + adc->clk = clk_get(&pdev->dev, "adc"); > + if (IS_ERR(adc->clk)) { > + ret = PTR_ERR(adc->clk); > + dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); > + goto err_iounmap; > + } > + > + spin_lock_init(&adc->lock); > + > + adc->clk_ref = 0; > + > + platform_set_drvdata(pdev, adc); > + > + for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) { > + set_irq_chip_data(irq, adc); > + set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip, > + handle_level_irq); > + } > + > + set_irq_data(adc->irq, adc); > + set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux); > + > + writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); > + writeb(0xff, adc->base + JZ_REG_ADC_CTRL); > + > + mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, > + ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base); > + > + return 0; Please return the mfd_add_devices return value. Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ From lars@metafoo.de Mon Jul 5 17:44:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 17:44:09 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:53953 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491853Ab0GEPoF (ORCPT ); Mon, 5 Jul 2010 17:44:05 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 8AFBB4DD; Mon, 5 Jul 2010 17:43:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id xdG8MmsN1ui2; Mon, 5 Jul 2010 17:43:58 +0200 (CEST) Received: from [172.31.16.228] (d060066.adsl.hansenet.de [80.171.60.66]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id C10A04DC; Mon, 5 Jul 2010 17:43:50 +0200 (CEST) Message-ID: <4C31FDA3.3040708@metafoo.de> Date: Mon, 05 Jul 2010 17:43:31 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Samuel Ortiz CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 22/26] MFD: Add JZ4740 ADC driver References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-23-git-send-email-lars@metafoo.de> <20100705145306.GA3850@sortiz-mobl> In-Reply-To: <20100705145306.GA3850@sortiz-mobl> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27325 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Hi Samuel Ortiz wrote: > Hi Lars, > > Sorry for the review delay. This one got lost in my inbox :-/ > > On Sat, Jun 19, 2010 at 07:08:27AM +0200, Lars-Peter Clausen wrote: >> This patch adds a MFD driver for the JZ4740 ADC unit. The driver is used to >> demultiplex IRQs and synchronize access to shared registers between the battery, >> hwmon and (future) touchscreen driver. > The driver looks pretty clean. I only have a couple nitpicks: > >> +static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc) >> +{ >> + struct jz4740_adc *adc = get_irq_desc_data(desc); >> + uint8_t status; >> + unsigned int i; >> + >> + status = readb(adc->base + JZ_REG_ADC_STATUS); >> + >> + for (i = 0; i < 5; ++i) { >> + if (status & BIT(i)) >> + generic_handle_irq(adc->irq_base + i); > for_each_set_bit() could nicely replace your loop here. I wonder if it would make sense to optimize for_each_set_bit for small builtin constants. Using it in it's current form for this loop would likely add some overhead. > >> +static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) >> +{ >> + unsigned long flags; >> + >> + spin_lock_irqsave(&adc->lock, flags); >> + if (adc->clk_ref++ == 0) >> + clk_enable(adc->clk); >> + spin_unlock_irqrestore(&adc->lock, flags); >> +} > I'm not familiar with your platform clock framework, but shouldn't the > refcounting be handled there instead of spread over all your drivers ? The ADC clock is the only clock on this platform which is shared between multiple devices so I refrained from adding the refcounting to the core for now. But to be strictly complaint with the clock API as defined in linux/clk.h the implementation should do refcounting. I'm still a bit uncertain what would be done best here. > >> +static int __devinit jz4740_adc_probe(struct platform_device *pdev) >> +{ >> + int ret; >> + struct jz4740_adc *adc; >> + struct resource *mem_base; >> + int irq; >> + >> + adc = kmalloc(sizeof(*adc), GFP_KERNEL); >> + >> + adc->irq = platform_get_irq(pdev, 0); >> + if (adc->irq < 0) { >> + ret = adc->irq; >> + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); >> + goto err_free; >> + } >> + >> + adc->irq_base = platform_get_irq(pdev, 1); >> + if (adc->irq_base < 0) { >> + ret = adc->irq_base; >> + dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret); >> + goto err_free; >> + } >> + >> + mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (!mem_base) { >> + ret = -ENOENT; >> + dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); >> + goto err_free; >> + } >> + >> + /* Only request the shared registers for the MFD driver */ >> + adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, >> + pdev->name); >> + if (!adc->mem) { >> + ret = -EBUSY; >> + dev_err(&pdev->dev, "Failed to request mmio memory region\n"); >> + goto err_free; >> + } >> + >> + adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); >> + if (!adc->base) { >> + ret = -EBUSY; >> + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); >> + goto err_release_mem_region; >> + } >> + >> + adc->clk = clk_get(&pdev->dev, "adc"); >> + if (IS_ERR(adc->clk)) { >> + ret = PTR_ERR(adc->clk); >> + dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); >> + goto err_iounmap; >> + } >> + >> + spin_lock_init(&adc->lock); >> + >> + adc->clk_ref = 0; >> + >> + platform_set_drvdata(pdev, adc); >> + >> + for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) { >> + set_irq_chip_data(irq, adc); >> + set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip, >> + handle_level_irq); >> + } >> + >> + set_irq_data(adc->irq, adc); >> + set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux); >> + >> + writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); >> + writeb(0xff, adc->base + JZ_REG_ADC_CTRL); >> + >> + mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, >> + ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base); >> + >> + return 0; > Please return the mfd_add_devices return value. > > Cheers, > Samuel. > Thanks for reviewing the patch - Lars From sameo@linux.intel.com Mon Jul 5 17:53:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 17:53:52 +0200 (CEST) Received: from mga01.intel.com ([192.55.52.88]:11740 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491837Ab0GEPxr (ORCPT ); Mon, 5 Jul 2010 17:53:47 +0200 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 05 Jul 2010 08:52:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.53,540,1272870000"; d="scan'208";a="815011527" Received: from unknown (HELO sortiz-mobl) ([10.255.17.75]) by fmsmga001.fm.intel.com with ESMTP; 05 Jul 2010 08:53:21 -0700 Date: Mon, 5 Jul 2010 17:53:27 +0200 From: Samuel Ortiz To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 22/26] MFD: Add JZ4740 ADC driver Message-ID: <20100705155326.GC3850@sortiz-mobl> References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-23-git-send-email-lars@metafoo.de> <20100705145306.GA3850@sortiz-mobl> <4C31FDA3.3040708@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C31FDA3.3040708@metafoo.de> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27326 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sameo@linux.intel.com Precedence: bulk X-list: linux-mips On Mon, Jul 05, 2010 at 05:43:31PM +0200, Lars-Peter Clausen wrote: > >> +static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) > >> +{ > >> + unsigned long flags; > >> + > >> + spin_lock_irqsave(&adc->lock, flags); > >> + if (adc->clk_ref++ == 0) > >> + clk_enable(adc->clk); > >> + spin_unlock_irqrestore(&adc->lock, flags); > >> +} > > I'm not familiar with your platform clock framework, but shouldn't the > > refcounting be handled there instead of spread over all your drivers ? > > The ADC clock is the only clock on this platform which is shared between multiple > devices so I refrained from adding the refcounting to the core for now. But to be > strictly complaint with the clock API as defined in linux/clk.h the implementation > should do refcounting. I'm still a bit uncertain what would be done best here. > I can't see what leaving the refcount handling to drivers could bring compared to a centralized implementation. But that's your platform, either way is fine with me as far as this MFD driver is concerned. Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ From alex@digriz.org.uk Mon Jul 5 22:11:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jul 2010 22:11:31 +0200 (CEST) Received: from chipmunk.wormnet.eu ([195.195.131.226]:48274 "EHLO chipmunk.wormnet.eu" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491096Ab0GEUL1 (ORCPT ); Mon, 5 Jul 2010 22:11:27 +0200 Received: by chipmunk.wormnet.eu (Postfix, from userid 1000) id 0DE9287BA8; Mon, 5 Jul 2010 21:11:26 +0100 (BST) Date: Mon, 5 Jul 2010 21:11:26 +0100 From: Alexander Clouter To: linux-mips@linux-mips.org Cc: florian@openwrt.org Subject: [PATCH] MIPS: AR7: rewrite of cpmac_get_mac() Message-ID: <20100705201125.GL24655@chipmunk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Organization: diGriz X-URL: http://www.digriz.org.uk/ X-JabberID: alex@digriz.org.uk User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27327 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Shamelessly stealing wisdom from pasemi_mac.c, I found char2hex() could be replaced with a single call to sscanf(), looks cleaner to me at least. The result is 100 bytes trimmed off the size of a compiled cpmac_get_mac() and as an extra bonus it grumbles and gracefully fails over to using random_ether_addr() when an attempt to parse an invalid MAC address is made. Signed-off-by: Alexander Clouter --- arch/mips/ar7/platform.c | 42 +++++++++++++++--------------------------- 1 files changed, 15 insertions(+), 27 deletions(-) diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 8f31d1d..0da5b2b 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -292,40 +292,28 @@ static struct platform_device cpmac_high = { .num_resources = ARRAY_SIZE(cpmac_high_res), }; -static inline unsigned char char2hex(char h) +static void __init cpmac_get_mac(int instance, unsigned char *dev_addr) { - switch (h) { - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - return h - '0'; - case 'A': case 'B': case 'C': case 'D': case 'E': case 'F': - return h - 'A' + 10; - case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': - return h - 'a' + 10; - default: - return 0; - } -} - -static void cpmac_get_mac(int instance, unsigned char *dev_addr) -{ - int i; - char name[5], default_mac[ETH_ALEN], *mac; + char name[5], *mac; - mac = NULL; sprintf(name, "mac%c", 'a' + instance); mac = prom_getenv(name); - if (!mac) { + if (!mac && instance) { sprintf(name, "mac%c", 'a'); mac = prom_getenv(name); } - if (!mac) { - random_ether_addr(default_mac); - mac = default_mac; - } - for (i = 0; i < 6; i++) - dev_addr[i] = (char2hex(mac[i * 3]) << 4) + - char2hex(mac[i * 3 + 1]); + + if (mac) { + if (sscanf(mac, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &dev_addr[0], &dev_addr[1], + &dev_addr[2], &dev_addr[3], + &dev_addr[4], &dev_addr[5]) != 6) { + pr_warning("cannot parse mac address, " + "using random address\n"); + random_ether_addr(dev_addr); + } + } else + random_ether_addr(dev_addr); } /***************************************************************************** -- 1.7.1 From ralf@linux-mips.org Tue Jul 6 03:22:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 03:22:58 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45776 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491199Ab0GFBWx (ORCPT ); Tue, 6 Jul 2010 03:22:53 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o661MmHW019043; Tue, 6 Jul 2010 02:22:49 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o661MmrO019041; Tue, 6 Jul 2010 02:22:48 +0100 Date: Tue, 6 Jul 2010 02:22:48 +0100 From: Ralf Baechle To: Shinya Kuribayashi Cc: David VomLehn , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required Message-ID: <20100706012247.GA15859@linux-mips.org> References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> <4C2F49D0.60200@pobox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C2F49D0.60200@pobox.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27328 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Jul 03, 2010 at 11:31:44PM +0900, Shinya Kuribayashi wrote: > On 07/03/2010 06:32 AM, David VomLehn wrote: > > Usually it's better to control things on a feature-by-feature basis rather > > than rely on things like CPU model. This allows you to easily handle case > > where, for example, you have a different CPU that normally doesn't have > > a feature but a particular variant does have it. IIRC, the MIPS family has > > examples of this. So, I think it's better to go with the: > > __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz > > used in fls(). > > Ok, now I've come to the same conclusion. Revised patch will be like > this. Malta is a development platform supporting various types of > MIPS32/MIPS64 cores, hence use cpu_has_clo_clz directly. The same goes > to MIPSSim. > > Another concern is that, I'm not really sure whether cpu_has_clo_clz is > acceptable or not for Malta (and MIPSSim). Hopefully Ralf will help us > make things in the right direction. My grief with this patch at this moment is: o The suggestion of using __builtin_ffs or similar is nice but these functions appear to have introduced in GCC 3.4 but we unfortunately support GCC >= 3.2. o no Signed-off-by: line. So can you sen me one? Thanks Ralf From ralf@linux-mips.org Tue Jul 6 03:31:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 03:31:13 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53946 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491199Ab0GFBbJ (ORCPT ); Tue, 6 Jul 2010 03:31:09 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o661V6nu019982; Tue, 6 Jul 2010 02:31:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o661V6kJ019980; Tue, 6 Jul 2010 02:31:06 +0100 Date: Tue, 6 Jul 2010 02:31:06 +0100 From: Ralf Baechle To: David VomLehn Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Configuration changes to go along with simplified command line manipulation Message-ID: <20100706013106.GA19923@linux-mips.org> References: <20100701203751.GA870@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100701203751.GA870@dvomlehn-lnx2.corp.sa.net> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27329 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jul 01, 2010 at 01:37:52PM -0700, David VomLehn wrote: > Additional changes to Youichi Yuasa's command line simplication code > > The PowerTV platform uses a non-standard way to get the kernel command > line--we insert a built-in command line into arcs_cmdline and to > get additional command line information from the bootloader via a > pointer in the a1 register. It is necessary to insert a space between > to the two strings or the last argument from arcs_cmdline and the first > argument from the bootloader may be inadvertantly combined. > > It is also necessary to set CONFIG_CMDLINE_BOOL to "y" and to set the > default command line to an empty string to get the simplified code to > work properly in the PowerTV environment. Queued for 2.6.36 - but if absolutely necessary, should CONFIG_CMDLINE_BOOL not be selected? Ralf From davem@davemloft.net Tue Jul 6 03:55:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 03:55:59 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:52892 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492003Ab0GFBzy (ORCPT ); Tue, 6 Jul 2010 03:55:54 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 7B81724C113; Mon, 5 Jul 2010 18:56:06 -0700 (PDT) Date: Mon, 05 Jul 2010 18:56:06 -0700 (PDT) Message-Id: <20100705.185606.115922440.davem@davemloft.net> To: ralf@linux-mips.org Cc: segooon@gmail.com, kernel-janitors@vger.kernel.org, jpirko@redhat.com, eric.dumazet@gmail.com, kaber@trash.net, adobriyan@gmail.com, linux-mips@linux-mips.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [NET] ioc3-eth: Use the instance of net_device_stats from net_device. From: David Miller In-Reply-To: <20100705125938.GB28849@linux-mips.org> References: <20100705125938.GB28849@linux-mips.org> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27330 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Ralf Baechle Date: Mon, 5 Jul 2010 13:59:38 +0100 > Since net_device has an instance of net_device_stats, we can remove the > instance of this from the adapter structure. > > Based on original patch by Kulikov Vasiliy. > > Signed-off-by: Ralf Baechle > Signed-off-by: Kulikov Vasiliy Applied. From miloody@gmail.com Tue Jul 6 08:24:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 08:24:26 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:39672 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491054Ab0GFGYW (ORCPT ); Tue, 6 Jul 2010 08:24:22 +0200 Received: by gwaa18 with SMTP id a18so1076331gwa.36 for ; Mon, 05 Jul 2010 23:24:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=zQ9U6FGa2Ir5q9NZ/ZYSa8vk8aBV1oqmBRUwzizLEXE=; b=hfhDFuamDUx5a3R454ScoTA6/HFBzYt7vx+oblpMVBHPLHaL9AfdgkHMj24GMF/25X wFBo1k+qwJe9XaJVOavAwghFSGtpJkHe5YNn4k2X4zV7+n31v5rN4Sm0NrASW95ytlO4 HS4/ofEVTmuyx4yts5sgfTO5d8KNDIpZyLyAw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=kGjvXXcQELPopZuvTm849bpgwd2yM2x5DElLAdmNri2GAuIEth86CJaVTYa2p4VuyN +P9iR4Ffe3ZJNAgnCQrtuOd1cm+blAwBromem+IDsUlqwjnmUdrEfn46Q/wCXG+CwEIX OUZwjm8GqK0PyCR1k0HpZRgoEWfR35tBfIlR8= MIME-Version: 1.0 Received: by 10.90.63.13 with SMTP id l13mr4407323aga.57.1278397455534; Mon, 05 Jul 2010 23:24:15 -0700 (PDT) Received: by 10.90.56.11 with HTTP; Mon, 5 Jul 2010 23:24:15 -0700 (PDT) Date: Tue, 6 Jul 2010 14:24:15 +0800 Message-ID: Subject: why I receive tlb exception in kernel mode? From: loody To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27331 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Dear all: If I remember correctly, the copy_from_user will translate the user mode address by tlb. But why my usb kernel driver will get user mode address as 0x00000070? below is the kernel dump happen on my machine. ehci ehci.0: irq status c028 Async Periodic IAA FLR ehci ehci.0: itd_submit 1 urb 87f20c00 ep1in len 98304, 32 pkts 1 uframes [87b48280] ehci ehci.0: schedule devp 1 ep1in-iso period 1 start 46.0 ehci ehci.0: itd_submit 1 urb 87f20800 ep1in len 98304, 32 pkts 1 uframes [87b48280] ehci ehci.0: irq status c009 Async Periodic FLR INT CPU 0 Unable to handle kernel paging request at virtual address 00000070, epc == c045e8ac, ra == c045e610 Oops[#1]: Cpu 0 $ 0 : 00000000 00000001 00000000 00000007 $ 4 : a7b430bc 00000000 00000000 00000000 $ 8 : 00000008 00000002 8c005400 0000000f $12 : ffffffff 00000008 70000000 ffffffee $16 : 00000000 00000001 a7b45100 40000000 $20 : 20000000 00000000 87387ec0 87387e00 $24 : ffffffb1 ffffffc1 $28 : 87268000 872697a0 87b460bc c045e610 Hi : 00000178 Lo : 00000000 epc : c045e8ac ehci_work+0x640/0xcb4 [ehci_hcd] Not tainted ra : c045e610 ehci_work+0x3a4/0xcb4 [ehci_hcd] Status: 11000002 KERNEL EXL Cause : 40801408 BadVA : 00000070 PrId : 00019655 (MIPS 24Kc) Modules linked in: uvcvideo ehci_hcd usbcore Process a.out (pid: 823, threadinfo=87268000, task=8726a530, tls=00000000) Stack : 87387ec0 00000050 35303830 61376234 00000000 00000000 00000178 0000003a 000000bc 87387efc 000001d6 0000002f 00000800 a7b430bc 00000000 00000004 87387ed0 0000c009 87387ec0 87387e00 00000000 00000002 ffffffff 00000001 00010039 c0465474 81102200 c0466e7c 87893300 87269818 20717269 74617473 63207375 20393030 6e797341 65502063 646f6972 46206369 4920524c 0000544e ... Call Trace: [] ehci_work+0x640/0xcb4 [ehci_hcd] [] ehci_irq+0x108/0x524 [ehci_hcd] [] usb_hcd_irq+0x50/0xfc [usbcore] [<801687cc>] handle_IRQ_event+0x90/0x188 [<8016a7a0>] handle_percpu_irq+0x54/0xbc [<80109f90>] irq_dispatch+0x40/0x6c [<8010040c>] ret_from_irq+0x0/0x4 [<8013b88c>] __do_softirq+0x7c/0x164 [<8013b9f0>] do_softirq+0x7c/0x84 [<80109f98>] irq_dispatch+0x48/0x6c [<8010040c>] ret_from_irq+0x0/0x4 [<80135d38>] vprintk+0x31c/0x458 [<8010555c>] printk+0x24/0x30 [] ehci_urb_enqueue+0x5dc/0x13d8 [ehci_hcd] [] usb_hcd_submit_urb+0x110/0xc5c [usbcore] [] uvc_init_video+0x258/0x494 [uvcvideo] [] uvc_v4l2_do_ioctl+0x8f0/0x12c0 [uvcvideo] [<802e5908>] video_usercopy+0x240/0x424 [<801b2d9c>] vfs_ioctl+0xbc/0xcc [<801b2e40>] do_vfs_ioctl+0x94/0x7a0 [<801b3594>] sys_ioctl+0x48/0xc0 [<80102150>] stack_done+0x20/0x3c Code: 00061100 00e21021 24c30007 <8c440070> 00031900 00e31821 7ca24c00 00822023 ac640004 Disabling lock debugging due to kernel taint Kernel panic - not syncing: Fatal exception in interrupt appreciate your help, miloody From geert.uytterhoeven@gmail.com Tue Jul 6 09:03:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 09:03:28 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:39086 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491055Ab0GFHDY convert rfc822-to-8bit (ORCPT ); Tue, 6 Jul 2010 09:03:24 +0200 Received: by pwj5 with SMTP id 5so2839215pwj.36 for ; Tue, 06 Jul 2010 00:03:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type:content-transfer-encoding; bh=qRty7QUsP42pB43eScq4ySEzkHU6eaySXlJ08L00miU=; b=Wsj+oVgoN23FFK3QxwQKJadAWZUpptuVHqZR7OHw89NsFuiFg8eFLQAy0ezavJsRkB OI/rftYZaxTQNFgRytChExN89xalNaKQZbHphEtsG26W2MDtvivJbNPRrm8JSEy4Bd1h 0YwQ0unhlBHj3tjaJ43n3rxX9yBVIwiFhw2Io= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=qBGmf5OuJIwO0LL7msWEXqpdvCltiIESWuYVyKH12mT4HTehIg1Cb2qmURet0DhvfA Ah4m9rUtzgj87WZwXEUcjVz+CkpVvrWM9yKzb4NC0vve9JmBfvq5uBVQpkc4BxwwmVop szkXlkauBocW13XsowJqLv+EhRNIwGQ49OmR8= MIME-Version: 1.0 Received: by 10.142.132.12 with SMTP id f12mr4865274wfd.223.1278399794295; Tue, 06 Jul 2010 00:03:14 -0700 (PDT) Received: by 10.143.155.15 with HTTP; Tue, 6 Jul 2010 00:03:14 -0700 (PDT) In-Reply-To: References: Date: Tue, 6 Jul 2010 09:03:14 +0200 X-Google-Sender-Auth: 3kwB-1jsL218XIoefNYkxOrnloE Message-ID: Subject: Re: why I receive tlb exception in kernel mode? From: Geert Uytterhoeven To: loody Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27332 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Tue, Jul 6, 2010 at 08:24, loody wrote: > If I remember correctly, the copy_from_user will translate the user > mode address by tlb. Indeed... > But why my usb kernel driver will get user mode address as 0x00000070? > > below is the kernel dump happen on my machine. > > ehci ehci.0: irq status c028 Async Periodic IAA FLR > ehci ehci.0: itd_submit 1 urb 87f20c00 ep1in len 98304, 32 pkts 1 > uframes [87b48280] > ehci ehci.0: schedule devp 1 ep1in-iso period 1 start 46.0 > ehci ehci.0: itd_submit 1 urb 87f20800 ep1in len 98304, 32 pkts 1 > uframes [87b48280] > ehci ehci.0: irq status c009 Async Periodic FLR INT > CPU 0 Unable to handle kernel paging request at virtual address ^^^^^^ ... but this one is about a bad kernel address. > 00000070, epc == c045e8ac, ra == c045e610 Looks like an offset in a struct pointed to by a NULL pointer. > Oops[#1]: > Cpu 0 > $ 0   : 00000000 00000001 00000000 00000007 > $ 4   : a7b430bc 00000000 00000000 00000000 > $ 8   : 00000008 00000002 8c005400 0000000f > $12   : ffffffff 00000008 70000000 ffffffee > $16   : 00000000 00000001 a7b45100 40000000 > $20   : 20000000 00000000 87387ec0 87387e00 > $24   : ffffffb1 ffffffc1 > $28   : 87268000 872697a0 87b460bc c045e610 > Hi    : 00000178 > Lo    : 00000000 > epc   : c045e8ac ehci_work+0x640/0xcb4 [ehci_hcd] >    Not tainted > ra    : c045e610 ehci_work+0x3a4/0xcb4 [ehci_hcd] > Status: 11000002    KERNEL EXL > Cause : 40801408 > BadVA : 00000070 > PrId  : 00019655 (MIPS 24Kc) > Modules linked in: uvcvideo ehci_hcd usbcore > Process a.out (pid: 823, threadinfo=87268000, task=8726a530, tls=00000000) > Stack : 87387ec0 00000050 35303830 61376234 00000000 00000000 00000178 0000003a >        000000bc 87387efc 000001d6 0000002f 00000800 a7b430bc 00000000 00000004 >        87387ed0 0000c009 87387ec0 87387e00 00000000 00000002 ffffffff 00000001 >        00010039 c0465474 81102200 c0466e7c 87893300 87269818 20717269 74617473 >        63207375 20393030 6e797341 65502063 646f6972 46206369 4920524c 0000544e >        ... > Call Trace: > [] ehci_work+0x640/0xcb4 [ehci_hcd] > [] ehci_irq+0x108/0x524 [ehci_hcd] > [] usb_hcd_irq+0x50/0xfc [usbcore] > [<801687cc>] handle_IRQ_event+0x90/0x188 > [<8016a7a0>] handle_percpu_irq+0x54/0xbc > [<80109f90>] irq_dispatch+0x40/0x6c > [<8010040c>] ret_from_irq+0x0/0x4 > [<8013b88c>] __do_softirq+0x7c/0x164 > [<8013b9f0>] do_softirq+0x7c/0x84 > [<80109f98>] irq_dispatch+0x48/0x6c > [<8010040c>] ret_from_irq+0x0/0x4 > [<80135d38>] vprintk+0x31c/0x458 > [<8010555c>] printk+0x24/0x30 > [] ehci_urb_enqueue+0x5dc/0x13d8 [ehci_hcd] > [] usb_hcd_submit_urb+0x110/0xc5c [usbcore] > [] uvc_init_video+0x258/0x494 [uvcvideo] > [] uvc_v4l2_do_ioctl+0x8f0/0x12c0 [uvcvideo] > [<802e5908>] video_usercopy+0x240/0x424 > [<801b2d9c>] vfs_ioctl+0xbc/0xcc > [<801b2e40>] do_vfs_ioctl+0x94/0x7a0 > [<801b3594>] sys_ioctl+0x48/0xc0 > [<80102150>] stack_done+0x20/0x3c > > > Code: 00061100  00e21021  24c30007 <8c440070> 00031900  00e31821 > 7ca24c00  00822023  ac640004 > Disabling lock debugging due to kernel taint > Kernel panic - not syncing: Fatal exception in interrupt Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From ralf@linux-mips.org Tue Jul 6 11:39:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 11:39:32 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45805 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491054Ab0GFJj3 (ORCPT ); Tue, 6 Jul 2010 11:39:29 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o669dN1H006580; Tue, 6 Jul 2010 10:39:24 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o669dMh6006578; Tue, 6 Jul 2010 10:39:22 +0100 Date: Tue, 6 Jul 2010 10:39:21 +0100 From: Ralf Baechle To: Alexander Clouter Cc: linux-mips@linux-mips.org, florian@openwrt.org Subject: Re: [PATCH] MIPS: AR7: rewrite of cpmac_get_mac() Message-ID: <20100706093921.GA841@linux-mips.org> References: <20100705201125.GL24655@chipmunk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100705201125.GL24655@chipmunk> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27333 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.36. Ralf From ralf@linux-mips.org Tue Jul 6 12:23:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 12:23:33 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54741 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491126Ab0GFKXa (ORCPT ); Tue, 6 Jul 2010 12:23:30 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66ANSXR010112 for ; Tue, 6 Jul 2010 11:23:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66ANSNn010111 for linux-mips@linux-mips.org; Tue, 6 Jul 2010 11:23:28 +0100 Date: Tue, 6 Jul 2010 11:23:27 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: New stable kernels Message-ID: <20100706102327.GA10064@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27334 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips It's an unusually large number of -stable releases so I contrary to my usual practice I'm announcing the available of Linux 2.6.27.47 Linux 2.6.27.48 Linux 2.6.31.14 Linux 2.6.32.16 Linux 2.6.33.6 Linux 2.6.34.1 on linux-mips.org. Cheers, Ralf From shinya.kuribayashi.px@renesas.com Tue Jul 6 13:18:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 13:18:11 +0200 (CEST) Received: from TYO201.gate.nec.co.jp ([202.32.8.193]:41988 "EHLO tyo201.gate.nec.co.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491791Ab0GFLSH (ORCPT ); Tue, 6 Jul 2010 13:18:07 +0200 Received: from mailgate3.nec.co.jp ([10.7.69.195]) by tyo201.gate.nec.co.jp (8.13.8/8.13.4) with ESMTP id o66BI0if011071; Tue, 6 Jul 2010 20:18:00 +0900 (JST) Received: (from root@localhost) by mailgate3.nec.co.jp (8.11.7/3.7W-MAILGATE-NEC) id o66BI0t17158; Tue, 6 Jul 2010 20:18:00 +0900 (JST) Received: from relay51.aps.necel.com ([10.29.19.60]) by vgate01.nec.co.jp (8.11.7/3.7W-MAILSV-NEC) with ESMTP id o66BHx414172; Tue, 6 Jul 2010 20:17:59 +0900 (JST) Received: from realmbox31.aps.necel.com ([10.29.19.36] [10.29.19.36]) by relay51.aps.necel.com with ESMTP; Tue, 6 Jul 2010 20:17:59 +0900 Received: from [10.114.180.181] ([10.114.180.181] [10.114.180.181]) by mbox02.aps.necel.com with ESMTP; Tue, 6 Jul 2010 20:17:59 +0900 Message-ID: <4C3310CD.2090309@renesas.com> Date: Tue, 06 Jul 2010 20:17:33 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.4) Gecko/20100608 Lightning/1.0b2 Thunderbird/3.1 MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Shinya Kuribayashi , David VomLehn , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> <20100702213219.GA390@dvomlehn-lnx2.corp.sa.net> <4C2F49D0.60200@pobox.com> <4C312860.3020005@renesas.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27335 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shinya.kuribayashi.px@renesas.com Precedence: bulk X-list: linux-mips On 7/5/2010 10:35 PM, Maciej W. Rozycki wrote: > Well, seems to be getting this > right. MIPS IV options are not included as quite rare compared to > MIPS32/64 ones and run-time determined defaults apply. For MIPS32/64 > configurations compile-time optimisations work as usually. Good catch, I missed that point. Then CONFIG_CPU_32/64 used at irq_ffs() can be replaced with cpu_has_clo_clz without problems. (eell-designed, anyway) >>> It might be simpler just to use __builtin_ffs() for this variant though. >>> Inline assembly is better avoided unless absolutely required. Not even >>> mentioning readability. >> >> Hm. It might be simpler, but it's not the purpose of irq_ffs(), IMHO. > > My point is whenever cpu_has_clo_clz is hardcoded to 1 GCC will expand > __builtin_ffs() to CLZ as expected and may potentially be able to optimise > it further. For the fallback path I agree you do not want to use > __builtin_ffs() as you want to save processing time of the unneeded bits Got it. I was too lazy, thanks for kind clarification. As for __builtin_ffs(), in addition to Ralf's comments on GCC versions, I was thinkg about two things: 1) Can we really get irq_ffs() optimized using __builtin_ffs/fls()? __builtin_ffs/fls() will emit CLZ if available, that's fine. But we don't want ffs/fls itself here. First, contrary to its name, current irq_ffs() implementation is very similar to __fls(). It's like a super-subset of __fls() only menat for CP0.Status check. And ffs is basically achieved by fls(word & -word). So __builtin_ffs/fls() could never be smaller than current irq_ffs(). irq_ffs() < __fls() < __fls(w & -w) == __ffs() # Consequently we can't obtain smaller irq_ffs() using __builtin_ffs/fls(). IIUC, current form of irq_ffs() will be useful in the future. 2) How cpu_has_clo_clz should be handled in the kernel This is not limited to cpu_has_clo_clz, but more general issue. Using __builtin_foo features allow us to get a variety of GCC services, optimizations. But also means that, it increases dependency on the GCC, strictly speaking, dependency on processor specifiers (-march=). For instance, when cpu_has_clo_clz is specified, we'd like to make it to the assembler CLZ, even if it's not supported. Or we should not do that? This is already pointed out from Maciej in the previous comment: > ".set mips32" looks dodgy here. For pre-MIPS32/64 platforms this > code should never make it to the assembler and if it did, then a > build-time error is better than a run-time problem. I know there's not always one answer, everything should be handled on a case by case basis. I'm just wondering about such things for a while (no need to reply) > -- there's no 8-bit FFS intrinsic let alone a 4-bit one (I'm assuming > there is a reason this piece of code does not check lower 4 interrupt > inputs). Failed to understand what you say (sorry!), but as far as I examined irq_ffs(), it returns from 7 to 0. Perhaps the following "bits 12..15" could be replaced with "bits 8..15"? Or am I missing something? > /* > * Version of ffs that only looks at bits 12..15. > */ Once things become clear (for me), I'll make a patchset incorporating cpu-feature-overrieds.h against PowerTV (with David's SOB of course). -- Shinya Kuribayashi Renesas Electronics From ralf@linux-mips.org Tue Jul 6 15:02:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 15:02:29 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41371 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491849Ab0GFNCZ (ORCPT ); Tue, 6 Jul 2010 15:02:25 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66D21Fm028815; Tue, 6 Jul 2010 14:02:01 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66D1xq1028814; Tue, 6 Jul 2010 14:01:59 +0100 Date: Tue, 6 Jul 2010 14:01:59 +0100 From: Ralf Baechle To: Manuel Lauss Cc: FUJITA Tomonori , linux-mips@linux-mips.org, manuel.lauss@gmail.com Subject: Re: [PATCH] MIPS: Alchemy: fix deprecated compile warnings Message-ID: <20100706130159.GA6613@linux-mips.org> References: <20100624012415L.fujita.tomonori@lab.ntt.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27336 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 23, 2010 at 06:31:18PM +0200, Manuel Lauss wrote: > > replace deprecated DMA_32BIT_MASK with DMA_BIT_MASK. > > > > cc1: warnings being treated as errors > > arch/mips/alchemy/devboards/db1200/platform.c:219: error: 'DMA_nnBIT_MASK' is deprecated > > arch/mips/alchemy/devboards/db1200/platform.c:226: error: 'DMA_nnBIT_MASK' is deprecated > > arch/mips/alchemy/devboards/db1200/platform.c:388: error: 'DMA_nnBIT_MASK' is deprecated > > arch/mips/alchemy/devboards/db1200/platform.c:393: error: 'DMA_nnBIT_MASK' is deprecated > > > > Signed-off-by: FUJITA Tomonori > > --- > >  arch/mips/alchemy/devboards/db1200/platform.c |    8 ++++---- > >  1 files changed, 4 insertions(+), 4 deletions(-) > > Acked-by: Manuel Lauss Thanks, Fujita-San. Patch applied. This one became necessary due to the migration to the new MIPS platform makefiles which also enable -Werror for all platforms and arch/mips/alchemy/devboards/db1200/ was previously one of the few subdirs still getting built without -Werror. Ralf From ralf@linux-mips.org Tue Jul 6 15:57:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 15:57:12 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58908 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491810Ab0GFN5H (ORCPT ); Tue, 6 Jul 2010 15:57:07 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66Dv4cg000335; Tue, 6 Jul 2010 14:57:04 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66Dv3rn000333; Tue, 6 Jul 2010 14:57:03 +0100 Date: Tue, 6 Jul 2010 14:57:03 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: Create and use asm/arch_hweight.h Message-ID: <20100706135703.GA329@linux-mips.org> References: <1277509568-28927-1-git-send-email-ddaney@caviumnetworks.com> <1277509568-28927-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1277509568-28927-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27337 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.36. Ralf From ralf@linux-mips.org Tue Jul 6 15:57:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 15:57:38 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58913 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491926Ab0GFN5W (ORCPT ); Tue, 6 Jul 2010 15:57:22 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66DvK06000341; Tue, 6 Jul 2010 14:57:20 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66DvKWq000340; Tue, 6 Jul 2010 14:57:20 +0100 Date: Tue, 6 Jul 2010 14:57:20 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] MIPS: Octeon: Define ARCH_HAS_USABLE_BUILTIN_POPCOUNT for OCTEON. Message-ID: <20100706135720.GB329@linux-mips.org> References: <1277509568-28927-1-git-send-email-ddaney@caviumnetworks.com> <1277509568-28927-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1277509568-28927-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27338 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.36. Ralf From ralf@linux-mips.org Tue Jul 6 16:18:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 16:18:09 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35973 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492172Ab0GFOSD (ORCPT ); Tue, 6 Jul 2010 16:18:03 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66EHwgJ008530; Tue, 6 Jul 2010 15:18:00 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66EHvdr008528; Tue, 6 Jul 2010 15:17:57 +0100 Date: Tue, 6 Jul 2010 15:17:57 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: Get rid of useless 'init_vdso successfully' message. Message-ID: <20100706141756.GA8313@linux-mips.org> References: <1276725628-8572-1-git-send-email-ddaney@caviumnetworks.com> <1276725628-8572-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276725628-8572-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27339 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks! Ralf From ralf@linux-mips.org Tue Jul 6 16:27:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 16:27:03 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:34694 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491810Ab0GFO07 (ORCPT ); Tue, 6 Jul 2010 16:26:59 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66EQuPo014124; Tue, 6 Jul 2010 15:26:56 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66EQtfk014113; Tue, 6 Jul 2010 15:26:55 +0100 Date: Tue, 6 Jul 2010 15:26:54 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, Jiri Slaby Subject: Re: [PATCH 2/2] MIPS: Make init_vdso a subsys_initcall. Message-ID: <20100706142654.GB8313@linux-mips.org> References: <1276725628-8572-1-git-send-email-ddaney@caviumnetworks.com> <1276725628-8572-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1276725628-8572-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27340 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, applied. Ralf From ralf@linux-mips.org Tue Jul 6 16:37:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 16:38:01 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45287 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492117Ab0GFOh6 (ORCPT ); Tue, 6 Jul 2010 16:37:58 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66EbvGk014348; Tue, 6 Jul 2010 15:37:57 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66Ebtj3014346; Tue, 6 Jul 2010 15:37:55 +0100 Date: Tue, 6 Jul 2010 15:37:55 +0100 From: Ralf Baechle To: Shinya Kuribayashi Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/4] MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE Message-ID: <20100706143755.GC8313@linux-mips.org> References: <4C1A0801.60405@renesas.com> <4C1A089E.4050703@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C1A089E.4050703@renesas.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27341 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.36. Thanks, Shinya-San! Ralf From ralf@linux-mips.org Tue Jul 6 16:38:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 16:38:27 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57403 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492173Ab0GFOiK (ORCPT ); Tue, 6 Jul 2010 16:38:10 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66Ec9Vk014355; Tue, 6 Jul 2010 15:38:09 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66Ec9dJ014354; Tue, 6 Jul 2010 15:38:09 +0100 Date: Tue, 6 Jul 2010 15:38:09 +0100 From: Ralf Baechle To: Shinya Kuribayashi Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE Message-ID: <20100706143809.GD8313@linux-mips.org> References: <4C1A0801.60405@renesas.com> <4C1A08AD.7060708@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C1A08AD.7060708@renesas.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27342 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.36. Thanks, Shinya-San! Ralf From ralf@linux-mips.org Tue Jul 6 16:38:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 16:38:54 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57410 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491916Ab0GFOiT (ORCPT ); Tue, 6 Jul 2010 16:38:19 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66EcI5k014361; Tue, 6 Jul 2010 15:38:18 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66EcIHM014360; Tue, 6 Jul 2010 15:38:18 +0100 Date: Tue, 6 Jul 2010 15:38:18 +0100 From: Ralf Baechle To: Shinya Kuribayashi Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/4] MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n) Message-ID: <20100706143818.GE8313@linux-mips.org> References: <4C1A0801.60405@renesas.com> <4C1A08C0.9070400@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C1A08C0.9070400@renesas.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27343 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.36. Thanks, Shinya-San! Ralf From ralf@linux-mips.org Tue Jul 6 16:39:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 16:39:19 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57415 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492179Ab0GFOi3 (ORCPT ); Tue, 6 Jul 2010 16:38:29 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66EcSEU014367; Tue, 6 Jul 2010 15:38:28 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66EcSPW014366; Tue, 6 Jul 2010 15:38:28 +0100 Date: Tue, 6 Jul 2010 15:38:28 +0100 From: Ralf Baechle To: Shinya Kuribayashi Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 4/4] MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n) Message-ID: <20100706143828.GF8313@linux-mips.org> References: <4C1A0801.60405@renesas.com> <4C1A08E9.9030808@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C1A08E9.9030808@renesas.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27344 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Queued for 2.6.36. Thanks, Shinya-San! Ralf From ralf@linux-mips.org Tue Jul 6 17:18:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jul 2010 17:18:20 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48051 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492048Ab0GFPSR (ORCPT ); Tue, 6 Jul 2010 17:18:17 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o66FIChP004878; Tue, 6 Jul 2010 16:18:12 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o66FIB74004876; Tue, 6 Jul 2010 16:18:11 +0100 Date: Tue, 6 Jul 2010 16:18:11 +0100 From: Ralf Baechle To: "David S. Miller" , netdev@vger.kernel.org Cc: linux-mips@linux-mips.org, "Maciej W. Rozycki" Subject: NET: SB1250: Initialize .owner Message-ID: <20100706151811.GA4829@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27345 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Ralf Baechle drivers/net/sb1250-mac.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c index 1f3acc3..79eee30 100644 --- a/drivers/net/sb1250-mac.c +++ b/drivers/net/sb1250-mac.c @@ -2671,6 +2671,7 @@ static struct platform_driver sbmac_driver = { .remove = __exit_p(sbmac_remove), .driver = { .name = sbmac_string, + .owner = THIS_MODULE, }, }; From davem@davemloft.net Thu Jul 8 00:00:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 00:00:58 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:45696 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491852Ab0GGWAx (ORCPT ); Thu, 8 Jul 2010 00:00:53 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id D67C624C090; Wed, 7 Jul 2010 15:01:05 -0700 (PDT) Date: Wed, 07 Jul 2010 15:01:05 -0700 (PDT) Message-Id: <20100707.150105.85406304.davem@davemloft.net> To: ralf@linux-mips.org Cc: netdev@vger.kernel.org, linux-mips@linux-mips.org, macro@linux-mips.org Subject: Re: NET: SB1250: Initialize .owner From: David Miller In-Reply-To: <20100706151811.GA4829@linux-mips.org> References: <20100706151811.GA4829@linux-mips.org> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27346 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Ralf Baechle Date: Tue, 6 Jul 2010 16:18:11 +0100 > Signed-off-by: Ralf Baechle Applied, thanks Ralf. From akpm@linux-foundation.org Thu Jul 8 01:42:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 01:42:30 +0200 (CEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:43689 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492033Ab0GGXm0 (ORCPT ); Thu, 8 Jul 2010 01:42:26 +0200 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id o67Nfp9P008810 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 7 Jul 2010 16:41:52 -0700 Received: from akpm.mtv.corp.google.com (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id o67NfmZl001200; Wed, 7 Jul 2010 16:41:49 -0700 Date: Wed, 7 Jul 2010 16:41:48 -0700 From: Andrew Morton To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle , linux-fbdev@vger.kernel.org Subject: Re: [PATCH v2 16/26] fbdev: Add JZ4740 framebuffer driver Message-Id: <20100707164148.d2a1f8c4.akpm@linux-foundation.org> In-Reply-To: <4C310ACD.6040604@metafoo.de> References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-17-git-send-email-lars@metafoo.de> <4C310ACD.6040604@metafoo.de> X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.9; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27347 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Mon, 05 Jul 2010 00:27:25 +0200 Lars-Peter Clausen wrote: > Hi Andrew > > v2 of this patch has been around for two weeks without any comments. I've fixed all > the issues you had with v1. If you this version is ok, an Acked-By would be nice :) I don't do acks - I already have enough to be blamed for. I'd merge it if asked to though. Although I might whine about inappropriate use of ENOENT, which means "No such file or directory". From dedekind1@gmail.com Thu Jul 8 08:10:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 08:11:01 +0200 (CEST) Received: from smtp.nokia.com ([192.100.122.233]:48833 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490994Ab0GHGKz (ORCPT ); Thu, 8 Jul 2010 08:10:55 +0200 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o686AmXG028985; Thu, 8 Jul 2010 09:10:49 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 8 Jul 2010 09:10:47 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 8 Jul 2010 09:10:47 +0300 Received: from [172.21.41.123] (esdhcp041123.research.nokia.com [172.21.41.123]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o686AjKn010287; Thu, 8 Jul 2010 09:10:46 +0300 Subject: Re: [PATCH v2 17/26] MTD: Nand: Add JZ4740 NAND driver From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, David Woodhouse , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org In-Reply-To: <1276924111-11158-18-git-send-email-lars@metafoo.de> References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-18-git-send-email-lars@metafoo.de> Content-Type: text/plain; charset="UTF-8" Date: Thu, 08 Jul 2010 09:06:54 +0300 Message-ID: <1278569214.12733.38.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.30.2 (2.30.2-1.fc13) Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 08 Jul 2010 06:10:47.0729 (UTC) FILETIME=[4EC50A10:01CB1E64] X-Nokia-AV: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27348 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Sat, 2010-06-19 at 07:08 +0200, Lars-Peter Clausen wrote: > diff --git a/include/linux/mtd/jz4740_nand.h b/include/linux/mtd/jz4740_nand.h > new file mode 100644 > index 0000000..379f9b6 > --- /dev/null > +++ b/include/linux/mtd/jz4740_nand.h > @@ -0,0 +1,34 @@ > +/* > + * Copyright (C) 2009-2010, Lars-Peter Clausen > + * JZ4740 SoC NAND controller driver > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > + > +#ifndef __JZ_NAND_H__ > +#define __JZ_NAND_H__ > + > +#include > +#include > + > +struct jz_nand_platform_data { > + int num_partitions; > + struct mtd_partition *partitions; > + > + struct nand_ecclayout *ecc_layout; > + > + unsigned int busy_gpio; > + > + void (*ident_callback)(struct platform_device *, struct nand_chip *, > + struct mtd_partition **, int *num_partitions); > +}; > + > +#endif Do you really have to add your platform data strucutre to "inlculde/mtd" ? That is quite global namespace, and ideally only things like user-space interface and "public" interface of the MTD subsystem should live there. Can you keep this somewhere in mips architecture directory? -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From lars@metafoo.de Thu Jul 8 15:20:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 15:20:45 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:59242 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491091Ab0GHNUi (ORCPT ); Thu, 8 Jul 2010 15:20:38 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 9D468542; Thu, 8 Jul 2010 15:20:31 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 936RspPOJi+4; Thu, 8 Jul 2010 15:20:31 +0200 (CEST) Received: from [172.31.16.228] (d078161.adsl.hansenet.de [80.171.78.161]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id C061853A; Thu, 8 Jul 2010 15:20:22 +0200 (CEST) Message-ID: <4C35D084.7050605@metafoo.de> Date: Thu, 08 Jul 2010 15:20:04 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: dedekind1@gmail.com CC: Ralf Baechle , linux-mips@linux-mips.org, David Woodhouse , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH v2 17/26] MTD: Nand: Add JZ4740 NAND driver References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-18-git-send-email-lars@metafoo.de> <1278569214.12733.38.camel@localhost> In-Reply-To: <1278569214.12733.38.camel@localhost> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27349 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Artem Bityutskiy wrote: > On Sat, 2010-06-19 at 07:08 +0200, Lars-Peter Clausen wrote: >> diff --git a/include/linux/mtd/jz4740_nand.h b/include/linux/mtd/jz4740_nand.h >> new file mode 100644 >> index 0000000..379f9b6 >> --- /dev/null >> +++ b/include/linux/mtd/jz4740_nand.h >> @@ -0,0 +1,34 @@ >> +/* >> + * Copyright (C) 2009-2010, Lars-Peter Clausen >> + * JZ4740 SoC NAND controller driver >> + * >> + * This program is free software; you can redistribute it and/or modify it >> + * under the terms of the GNU General Public License as published by the >> + * Free Software Foundation; either version 2 of the License, or (at your >> + * option) any later version. >> + * >> + * You should have received a copy of the GNU General Public License along >> + * with this program; if not, write to the Free Software Foundation, Inc., >> + * 675 Mass Ave, Cambridge, MA 02139, USA. >> + * >> + */ >> + >> +#ifndef __JZ_NAND_H__ >> +#define __JZ_NAND_H__ >> + >> +#include >> +#include >> + >> +struct jz_nand_platform_data { >> + int num_partitions; >> + struct mtd_partition *partitions; >> + >> + struct nand_ecclayout *ecc_layout; >> + >> + unsigned int busy_gpio; >> + >> + void (*ident_callback)(struct platform_device *, struct nand_chip *, >> + struct mtd_partition **, int *num_partitions); >> +}; >> + >> +#endif > > Do you really have to add your platform data strucutre to > "inlculde/mtd" ? That is quite global namespace, and ideally only things > like user-space interface and "public" interface of the MTD subsystem > should live there. > > Can you keep this somewhere in mips architecture directory? Hi Hm, ok, I see. I'll move it to arch/mips/include/asm/mach-jz4740/ then. But I guess I should move the headers for all the other jz4740 driver to the same directory as well. On the other hand I'm wondering where on would put headers for non platform specific drivers? - Lars From dedekind1@gmail.com Thu Jul 8 15:23:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 15:23:55 +0200 (CEST) Received: from smtp.nokia.com ([192.100.105.134]:38898 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491782Ab0GHNXr (ORCPT ); Thu, 8 Jul 2010 15:23:47 +0200 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o68DNDnh015684; Thu, 8 Jul 2010 08:23:35 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 8 Jul 2010 16:22:58 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 8 Jul 2010 16:22:57 +0300 Received: from [172.21.41.123] (esdhcp041123.research.nokia.com [172.21.41.123]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o68DMujn018098; Thu, 8 Jul 2010 16:22:56 +0300 Subject: Re: [PATCH v2 17/26] MTD: Nand: Add JZ4740 NAND driver From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, David Woodhouse , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org In-Reply-To: <4C35D084.7050605@metafoo.de> References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-18-git-send-email-lars@metafoo.de> <1278569214.12733.38.camel@localhost> <4C35D084.7050605@metafoo.de> Content-Type: text/plain; charset="UTF-8" Date: Thu, 08 Jul 2010 16:19:02 +0300 Message-ID: <1278595142.20321.26.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.30.2 (2.30.2-1.fc13) Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 08 Jul 2010 13:22:58.0219 (UTC) FILETIME=[AE8BCFB0:01CB1EA0] X-Nokia-AV: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27350 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Thu, 2010-07-08 at 15:20 +0200, Lars-Peter Clausen wrote: > On the other hand I'm wondering where on would put headers for non platform specific > drivers? If we are talking about MTD, then drivers/mtd ? -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From lars@metafoo.de Thu Jul 8 15:28:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 15:28:38 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:60051 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491962Ab0GHN2e (ORCPT ); Thu, 8 Jul 2010 15:28:34 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id A32205B1; Thu, 8 Jul 2010 15:28:28 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 413-mdlEhrjU; Thu, 8 Jul 2010 15:28:28 +0200 (CEST) Received: from [172.31.16.228] (d078161.adsl.hansenet.de [80.171.78.161]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id EB05C5B0; Thu, 8 Jul 2010 15:28:22 +0200 (CEST) Message-ID: <4C35D264.7080809@metafoo.de> Date: Thu, 08 Jul 2010 15:28:04 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Andrew Morton CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle , linux-fbdev@vger.kernel.org Subject: Re: [PATCH v2 16/26] fbdev: Add JZ4740 framebuffer driver References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-17-git-send-email-lars@metafoo.de> <4C310ACD.6040604@metafoo.de> <20100707164148.d2a1f8c4.akpm@linux-foundation.org> In-Reply-To: <20100707164148.d2a1f8c4.akpm@linux-foundation.org> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27351 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Andrew Morton wrote: > On Mon, 05 Jul 2010 00:27:25 +0200 > Lars-Peter Clausen wrote: > >> Hi Andrew >> >> v2 of this patch has been around for two weeks without any comments. I've fixed all >> the issues you had with v1. If you this version is ok, an Acked-By would be nice :) > > I don't do acks - I already have enough to be blamed for. Hm, ok. > Although I might whine about inappropriate use of > ENOENT, which means "No such file or directory". > That is due to to many bad examples, I guess. Would using ENXIO instead keep you from whining? - Lars From lars@metafoo.de Thu Jul 8 16:02:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 16:02:50 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:62683 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492278Ab0GHOCq (ORCPT ); Thu, 8 Jul 2010 16:02:46 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id AB7207BC; Thu, 8 Jul 2010 16:02:39 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id iZEVjPZkbeqm; Thu, 8 Jul 2010 16:02:39 +0200 (CEST) Received: from [172.31.16.228] (d078161.adsl.hansenet.de [80.171.78.161]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id D94C47BB; Thu, 8 Jul 2010 16:02:38 +0200 (CEST) Message-ID: <4C35DA6C.2060405@metafoo.de> Date: Thu, 08 Jul 2010 16:02:20 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: dedekind1@gmail.com CC: Ralf Baechle , linux-mips@linux-mips.org, David Woodhouse , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH v2 17/26] MTD: Nand: Add JZ4740 NAND driver References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-18-git-send-email-lars@metafoo.de> <1278569214.12733.38.camel@localhost> <4C35D084.7050605@metafoo.de> <1278595142.20321.26.camel@localhost> In-Reply-To: <1278595142.20321.26.camel@localhost> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27352 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Artem Bityutskiy wrote: > On Thu, 2010-07-08 at 15:20 +0200, Lars-Peter Clausen wrote: >> On the other hand I'm wondering where on would put headers for non platform specific >> drivers? > > If we are talking about MTD, then drivers/mtd ? > No, what I meant was header defining platform data structs and such. And what I wanted to get at is an answer to why driver header files are put in different directories while the driver files themselves are all keep in the same directory. (drivers of the same subsystem that is) - Lars From dedekind1@gmail.com Thu Jul 8 16:19:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 16:19:14 +0200 (CEST) Received: from smtp.nokia.com ([192.100.105.134]:43222 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491114Ab0GHOTK (ORCPT ); Thu, 8 Jul 2010 16:19:10 +0200 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o68EI5qc030036; Thu, 8 Jul 2010 09:19:05 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 8 Jul 2010 17:18:52 +0300 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Thu, 8 Jul 2010 17:18:52 +0300 Received: from [172.21.41.123] (esdhcp041123.research.nokia.com [172.21.41.123]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o68EIpFN016387; Thu, 8 Jul 2010 17:18:51 +0300 Subject: Re: [PATCH v2 17/26] MTD: Nand: Add JZ4740 NAND driver From: Artem Bityutskiy Reply-To: dedekind1@gmail.com To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, David Woodhouse , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org In-Reply-To: <4C35DA6C.2060405@metafoo.de> References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-18-git-send-email-lars@metafoo.de> <1278569214.12733.38.camel@localhost> <4C35D084.7050605@metafoo.de> <1278595142.20321.26.camel@localhost> <4C35DA6C.2060405@metafoo.de> Content-Type: text/plain; charset="UTF-8" Date: Thu, 08 Jul 2010 17:14:57 +0300 Message-ID: <1278598497.20321.29.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.30.2 (2.30.2-1.fc13) Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 08 Jul 2010 14:18:52.0419 (UTC) FILETIME=[7DCE1D30:01CB1EA8] X-Nokia-AV: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27353 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dedekind1@gmail.com Precedence: bulk X-list: linux-mips On Thu, 2010-07-08 at 16:02 +0200, Lars-Peter Clausen wrote: > Artem Bityutskiy wrote: > > On Thu, 2010-07-08 at 15:20 +0200, Lars-Peter Clausen wrote: > >> On the other hand I'm wondering where on would put headers for non platform specific > >> drivers? > > > > If we are talking about MTD, then drivers/mtd ? > > > No, what I meant was header defining platform data structs and such. > And what I wanted to get at is an answer to why driver header files are put in > different directories while the driver files themselves are all keep in the same > directory. (drivers of the same subsystem that is) To be frank I do not know, I did not look at the whole picture, just at the MTD part :-) -- Best Regards, Artem Bityutskiy (Ðртём Битюцкий) From akpm@linux-foundation.org Thu Jul 8 18:47:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 18:47:10 +0200 (CEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:49571 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491797Ab0GHQrH (ORCPT ); Thu, 8 Jul 2010 18:47:07 +0200 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id o68Gku90005691 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jul 2010 09:46:57 -0700 Received: from localhost (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id o68GksDN014560; Thu, 8 Jul 2010 09:46:55 -0700 Date: Thu, 8 Jul 2010 09:46:54 -0700 From: Andrew Morton To: Lars-Peter Clausen Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle , linux-fbdev@vger.kernel.org Subject: Re: [PATCH v2 16/26] fbdev: Add JZ4740 framebuffer driver Message-Id: <20100708094654.6fbeefe8.akpm@linux-foundation.org> In-Reply-To: <4C35D264.7080809@metafoo.de> References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-17-git-send-email-lars@metafoo.de> <4C310ACD.6040604@metafoo.de> <20100707164148.d2a1f8c4.akpm@linux-foundation.org> <4C35D264.7080809@metafoo.de> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.18.9; x86_64-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27354 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Thu, 08 Jul 2010 15:28:04 +0200 Lars-Peter Clausen wrote: > > Although I might whine about inappropriate use of > > ENOENT, which means "No such file or directory". > > > > That is due to to many bad examples, I guess. Would using ENXIO instead keep > you from whining? Sounds a bit better. It's hardly a huge issue though. From mattst88@gmail.com Thu Jul 8 22:46:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 22:46:37 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:63231 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492123Ab0GHUq3 (ORCPT ); Thu, 8 Jul 2010 22:46:29 +0200 Received: by gwj21 with SMTP id 21so269618gwj.36 for ; Thu, 08 Jul 2010 13:46:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=8VkSdYJQjkFfwQFJtFzbCnxxxZZHe0LlRV9FAEZc+IM=; b=iowxsxdhV7gA0C/77py6eKkBR6R1XBjvMVlVRRj8SNnUn7cmdBpoHsPUMikULHYCts 8P+ssQbu0yhAcIRv28fU4vZ/BzhUJ2Jl0mKFeZ/qgPWBq/Abl60LXv1TQcXC+bUb3wDQ rT1SPiVMDm/y7s6Dw1TpXfyYapk7UhHFS0270= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=bNs3wmRTPOe8E3HfXIXoO0mIvP92iP34YAQSainfONX2wswW0oWRl5KEV9gpBIQlpg XJTCAdnBhuiGaYiy5s/K9dNykgB0yc4FS73C3/7Ti5C8CXEVcVm0bfOBSyVMESp9xniO nD5j99hWCAhWTphWRNeatxMrEPSFSLfuR75Go= MIME-Version: 1.0 Received: by 10.224.112.209 with SMTP id x17mr4946900qap.304.1278621981184; Thu, 08 Jul 2010 13:46:21 -0700 (PDT) Received: by 10.229.37.77 with HTTP; Thu, 8 Jul 2010 13:46:21 -0700 (PDT) Date: Thu, 8 Jul 2010 16:46:21 -0400 Message-ID: Subject: Questions about BCM91250A From: Matt Turner To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27355 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mattst88@gmail.com Precedence: bulk X-list: linux-mips Hi, I'm trying to figure out how to access a Compact Flash card via a PCMCIA->CF adapter on my BCM91250A. I've added --- PCCard (PCMCIA/CardBus) support <*> 16-bit PCMCIA support [*] Load CIS updates from userspace (EXPERIMENTAL) [*] 32-bit CardBus support *** PC-card bridges *** <*> CardBus yenta-compatible bridge support [*] Special initialization for O2Micro bridges [*] Special initialization for Ricoh bridges [*] Special initialization for TI and EnE bridges [*] Auto-tune EnE bridges for CB cards [*] Special initialization for Toshiba ToPIC bridges <*> Cirrus PD6729 compatible bridge support <*> i82092 compatible bridge support and --- Serial ATA and Parallel ATA drivers <*> PCMCIA PATA support <*> Generic platform device PATA support But I see nothing in dmesg about this. Also, I can't get access to the rtc. I've tried a lot of different drivers. Any clues which is the right one? Thanks! Matt From guenter.roeck@ericsson.com Thu Jul 8 23:00:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jul 2010 23:00:15 +0200 (CEST) Received: from imr1.ericy.com ([198.24.6.9]:33605 "EHLO imr1.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491765Ab0GHVAI (ORCPT ); Thu, 8 Jul 2010 23:00:08 +0200 Received: from eusaamw0707.eamcs.ericsson.se ([147.117.20.32]) by imr1.ericy.com (8.13.1/8.13.1) with ESMTP id o68L852e031620; Thu, 8 Jul 2010 16:08:12 -0500 Received: from [155.53.128.111] (147.117.20.213) by eusaamw0707.eamcs.ericsson.se (147.117.20.92) with Microsoft SMTP Server id 8.2.234.1; Thu, 8 Jul 2010 16:59:54 -0400 Subject: Re: Questions about BCM91250A From: Guenter Roeck Reply-To: guenter.roeck@ericsson.com To: Matt Turner CC: "linux-mips@linux-mips.org" In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: Ericsson Date: Thu, 8 Jul 2010 13:59:53 -0700 Message-ID: <1278622793.11618.54.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27356 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips On Thu, 2010-07-08 at 16:46 -0400, Matt Turner wrote: > Hi, > I'm trying to figure out how to access a Compact Flash card via a > PCMCIA->CF adapter on my BCM91250A. > I suspect it is not supported. If you search for PCMCIA_CS, you'll notice that it is defined but never used. Maybe that code was not ported from 2.4. Guenter > I've added > --- PCCard (PCMCIA/CardBus) support > <*> 16-bit PCMCIA support > [*] Load CIS updates from userspace (EXPERIMENTAL) > [*] 32-bit CardBus support > *** PC-card bridges *** > <*> CardBus yenta-compatible bridge support > [*] Special initialization for O2Micro bridges > [*] Special initialization for Ricoh bridges > [*] Special initialization for TI and EnE bridges > [*] Auto-tune EnE bridges for CB cards > [*] Special initialization for Toshiba ToPIC bridges > <*> Cirrus PD6729 compatible bridge support > <*> i82092 compatible bridge support > > and > > --- Serial ATA and Parallel ATA drivers > <*> PCMCIA PATA support > <*> Generic platform device PATA support > > But I see nothing in dmesg about this. > > Also, I can't get access to the rtc. I've tried a lot of different > drivers. Any clues which is the right one? > > Thanks! > Matt > From jayakumar.lkml@gmail.com Fri Jul 9 03:26:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jul 2010 03:26:48 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:39456 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492130Ab0GIB0k convert rfc822-to-8bit (ORCPT ); Fri, 9 Jul 2010 03:26:40 +0200 Received: by iwn40 with SMTP id 40so1819204iwn.36 for ; Thu, 08 Jul 2010 18:26:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=IYSfeyTEohEhStk/lxk6xWqlOnIxS96XIuF72z6J6t8=; b=CfCRlnuq2fVPmTka1cYYY3v48cje285y+Opa1oHxcZjzQphAp17ktDC61FidJ61ojW XliZU342g/ze1bbk1bWkvCKSwHFDs1b5Vvk5ba9AdgutFJ5iF3n90zk21aGln8c87UJf 1Wo3/N7gzLPZdTm4fr+MnwBAa106Dmn4nCeXY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=YOwnsMjQEotqxtiNNaKYZkc4tdGB1Z1wayhtMn/1zXZAHr8L2fyyufbQC726CbW6iZ UC3c5SZ33l6PI14ft02x/OrTMM47LYhX/ZRqAPT6u/2nxqfdjgcFWNxCQRsYor+BUr7B tCQT8uDSM/Bdn4na2j07CNJ+R/XUU4dKAMWlo= MIME-Version: 1.0 Received: by 10.231.148.73 with SMTP id o9mr9400619ibv.21.1278638799057; Thu, 08 Jul 2010 18:26:39 -0700 (PDT) Received: by 10.231.41.28 with HTTP; Thu, 8 Jul 2010 18:26:38 -0700 (PDT) In-Reply-To: <4C310ACD.6040604@metafoo.de> References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-17-git-send-email-lars@metafoo.de> <4C310ACD.6040604@metafoo.de> Date: Fri, 9 Jul 2010 09:26:38 +0800 Message-ID: Subject: Re: [PATCH v2 16/26] fbdev: Add JZ4740 framebuffer driver From: Jaya Kumar To: Lars-Peter Clausen Cc: Andrew Morton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle , linux-fbdev@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27357 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jayakumar.lkml@gmail.com Precedence: bulk X-list: linux-mips On Mon, Jul 5, 2010 at 6:27 AM, Lars-Peter Clausen wrote: > Hi Andrew > > v2 of this patch has been around for two weeks without any comments. I've fixed all > the issues you had with v1. If you this version is ok, an Acked-By would be nice :) > > Thanks > - Lars > > Lars-Peter Clausen wrote: >> This patch adds support for the LCD controller on JZ4740 SoCs. Hi Lars, Andrew, I think this driver looks okay but I had some quick questions: >> +config FB_JZ4740 >> +     tristate "JZ4740 LCD framebuffer support" >> +     depends on FB >> +     select FB_SYS_FILLRECT >> +     select FB_SYS_COPYAREA >> +     select FB_SYS_IMAGEBLIT Out of curiosity, why FB_SYS and not FB_CFB? The users of FB_SYS are drivers that use virtual memory for their framebuffer. I didn't see any vmalloc in this driver. >> +     help >> +       Framebuffer support for the JZ4740 SoC. >> + >>  source "drivers/video/omap/Kconfig" >>  source "drivers/video/omap2/Kconfig" >> >> diff --git a/drivers/video/Makefile b/drivers/video/Makefile >> index 3c3bf86..fd2df57 100644 >> --- a/drivers/video/Makefile >> +++ b/drivers/video/Makefile >> @@ -132,6 +132,7 @@ obj-$(CONFIG_FB_CARMINE)          += carminefb.o >>  obj-$(CONFIG_FB_MB862XX)       += mb862xx/ >>  obj-$(CONFIG_FB_MSM)              += msm/ >>  obj-$(CONFIG_FB_NUC900)           += nuc900fb.o >> +obj-$(CONFIG_FB_JZ4740)                += jz4740_fb.o Just a minor nit, the typical naming in fbdev appears to be controllerfb.c as opposed to controller_fb.c . >> >>  # Platform or fallback drivers go here >>  obj-$(CONFIG_FB_UVESA)            += uvesafb.o >> diff --git a/drivers/video/jz4740_fb.c b/drivers/video/jz4740_fb.c >> new file mode 100644 >> index 0000000..8d03181 >> --- /dev/null >> +++ b/drivers/video/jz4740_fb.c >> @@ -0,0 +1,817 @@ >> +/* >> + *  Copyright (C) 2009-2010, Lars-Peter Clausen >> + *   JZ4740 SoC LCD framebuffer driver >> + * >> + *  This program is free software; you can redistribute it and/or modify it >> + *  under  the terms of  the GNU General Public License as published by the >> + *  Free Software Foundation;  either version 2 of the License, or (at your >> + *  option) any later version. >> + * >> + *  You should have received a copy of the GNU General Public License along >> + *  with this program; if not, write to the Free Software Foundation, Inc., >> + *  675 Mass Ave, Cambridge, MA 02139, USA. >> + * >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> +#include >> + >> +#include >> +#include >> + >> +#include >> + >> +#include I see a lot of register defines below. Is there any reason why they shouldn't go in above j*fb.h? Also, I'm not sure if linux/j*.h is the best place. I think most fbdev drivers place their headers in drivers/video itself unless they need to share something driver specific with userspace which is rare. Is there a specific reason why you put it in include/linux? >> +#include >> + >> +#define JZ_REG_LCD_CFG               0x00 >> +#define JZ_REG_LCD_VSYNC     0x04 >> +#define JZ_REG_LCD_HSYNC     0x08 >> +#define JZ_REG_LCD_VAT               0x0C >> +#define JZ_REG_LCD_DAH               0x10 >> +#define JZ_REG_LCD_DAV               0x14 >> +#define JZ_REG_LCD_PS                0x18 >> +#define JZ_REG_LCD_CLS               0x1C >> +#define JZ_REG_LCD_SPL               0x20 >> +#define JZ_REG_LCD_REV               0x24 >> +#define JZ_REG_LCD_CTRL              0x30 >> +#define JZ_REG_LCD_STATE     0x34 >> +#define JZ_REG_LCD_IID               0x38 >> +#define JZ_REG_LCD_DA0               0x40 >> +#define JZ_REG_LCD_SA0               0x44 >> +#define JZ_REG_LCD_FID0              0x48 >> +#define JZ_REG_LCD_CMD0              0x4C >> +#define JZ_REG_LCD_DA1               0x50 >> +#define JZ_REG_LCD_SA1               0x54 >> +#define JZ_REG_LCD_FID1              0x58 >> +#define JZ_REG_LCD_CMD1              0x5C >> + >> +#define JZ_LCD_CFG_SLCD                      BIT(31) >> +#define JZ_LCD_CFG_PS_DISABLE                BIT(23) >> +#define JZ_LCD_CFG_CLS_DISABLE               BIT(22) >> +#define JZ_LCD_CFG_SPL_DISABLE               BIT(21) >> +#define JZ_LCD_CFG_REV_DISABLE               BIT(20) >> +#define JZ_LCD_CFG_HSYNCM            BIT(19) >> +#define JZ_LCD_CFG_PCLKM             BIT(18) >> +#define JZ_LCD_CFG_INV                       BIT(17) >> +#define JZ_LCD_CFG_SYNC_DIR          BIT(16) >> +#define JZ_LCD_CFG_PS_POLARITY               BIT(15) >> +#define JZ_LCD_CFG_CLS_POLARITY              BIT(14) >> +#define JZ_LCD_CFG_SPL_POLARITY              BIT(13) >> +#define JZ_LCD_CFG_REV_POLARITY              BIT(12) >> +#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW  BIT(11) >> +#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) >> +#define JZ_LCD_CFG_DE_ACTIVE_LOW     BIT(9) >> +#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW  BIT(8) >> +#define JZ_LCD_CFG_18_BIT            BIT(7) >> +#define JZ_LCD_CFG_PDW                       (BIT(5) | BIT(4)) >> +#define JZ_LCD_CFG_MODE_MASK 0xf >> + >> +#define JZ_LCD_CTRL_BURST_4          (0x0 << 28) >> +#define JZ_LCD_CTRL_BURST_8          (0x1 << 28) >> +#define JZ_LCD_CTRL_BURST_16         (0x2 << 28) >> +#define JZ_LCD_CTRL_RGB555           BIT(27) >> +#define JZ_LCD_CTRL_OFUP             BIT(26) >> +#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) >> +#define JZ_LCD_CTRL_FRC_GRAYSCALE_4  (0x1 << 24) >> +#define JZ_LCD_CTRL_FRC_GRAYSCALE_2  (0x2 << 24) >> +#define JZ_LCD_CTRL_PDD_MASK         (0xff << 16) >> +#define JZ_LCD_CTRL_EOF_IRQ          BIT(13) >> +#define JZ_LCD_CTRL_SOF_IRQ          BIT(12) >> +#define JZ_LCD_CTRL_OFU_IRQ          BIT(11) >> +#define JZ_LCD_CTRL_IFU0_IRQ         BIT(10) >> +#define JZ_LCD_CTRL_IFU1_IRQ         BIT(9) >> +#define JZ_LCD_CTRL_DD_IRQ           BIT(8) >> +#define JZ_LCD_CTRL_QDD_IRQ          BIT(7) >> +#define JZ_LCD_CTRL_REVERSE_ENDIAN   BIT(6) >> +#define JZ_LCD_CTRL_LSB_FISRT                BIT(5) >> +#define JZ_LCD_CTRL_DISABLE          BIT(4) >> +#define JZ_LCD_CTRL_ENABLE           BIT(3) >> +#define JZ_LCD_CTRL_BPP_1            0x0 >> +#define JZ_LCD_CTRL_BPP_2            0x1 >> +#define JZ_LCD_CTRL_BPP_4            0x2 >> +#define JZ_LCD_CTRL_BPP_8            0x3 >> +#define JZ_LCD_CTRL_BPP_15_16                0x4 >> +#define JZ_LCD_CTRL_BPP_18_24                0x5 >> + >> +#define JZ_LCD_CMD_SOF_IRQ BIT(15) >> +#define JZ_LCD_CMD_EOF_IRQ BIT(16) >> +#define JZ_LCD_CMD_ENABLE_PAL BIT(12) >> + >> +#define JZ_LCD_SYNC_MASK 0x3ff >> + >> +#define JZ_LCD_STATE_DISABLED BIT(0) >> + >> +struct jzfb_framedesc { >> +     uint32_t next; >> +     uint32_t addr; >> +     uint32_t id; >> +     uint32_t cmd; >> +} __packed; >> + >> +struct jzfb { >> +     struct fb_info *fb; >> +     struct platform_device *pdev; >> +     void __iomem *base; >> +     struct resource *mem; >> +     struct jz4740_fb_platform_data *pdata; >> + >> +     size_t vidmem_size; >> +     void *vidmem; >> +     dma_addr_t vidmem_phys; >> +     struct jzfb_framedesc *framedesc; >> +     dma_addr_t framedesc_phys; >> + >> +     struct clk *ldclk; >> +     struct clk *lpclk; >> + >> +     unsigned is_enabled:1; Out of curiosity, why the bitfield? >> +     struct mutex lock; >> + >> +     uint32_t pseudo_palette[16]; >> +}; >> + >> +static const struct fb_fix_screeninfo jzfb_fix __devinitdata = { >> +     .id             = "JZ4740 FB", >> +     .type           = FB_TYPE_PACKED_PIXELS, >> +     .visual         = FB_VISUAL_TRUECOLOR, >> +     .xpanstep       = 0, >> +     .ypanstep       = 0, >> +     .ywrapstep      = 0, >> +     .accel          = FB_ACCEL_NONE, >> +}; >> + >> +static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = { >> +     JZ_GPIO_BULK_PIN(LCD_PCLK), >> +     JZ_GPIO_BULK_PIN(LCD_HSYNC), >> +     JZ_GPIO_BULK_PIN(LCD_VSYNC), >> +     JZ_GPIO_BULK_PIN(LCD_DE), >> +     JZ_GPIO_BULK_PIN(LCD_PS), >> +     JZ_GPIO_BULK_PIN(LCD_REV), >> +}; >> + >> +static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = { >> +     JZ_GPIO_BULK_PIN(LCD_DATA0), >> +     JZ_GPIO_BULK_PIN(LCD_DATA1), >> +     JZ_GPIO_BULK_PIN(LCD_DATA2), >> +     JZ_GPIO_BULK_PIN(LCD_DATA3), >> +     JZ_GPIO_BULK_PIN(LCD_DATA4), >> +     JZ_GPIO_BULK_PIN(LCD_DATA5), >> +     JZ_GPIO_BULK_PIN(LCD_DATA6), >> +     JZ_GPIO_BULK_PIN(LCD_DATA7), >> +     JZ_GPIO_BULK_PIN(LCD_DATA8), >> +     JZ_GPIO_BULK_PIN(LCD_DATA9), >> +     JZ_GPIO_BULK_PIN(LCD_DATA10), >> +     JZ_GPIO_BULK_PIN(LCD_DATA11), >> +     JZ_GPIO_BULK_PIN(LCD_DATA12), >> +     JZ_GPIO_BULK_PIN(LCD_DATA13), >> +     JZ_GPIO_BULK_PIN(LCD_DATA14), >> +     JZ_GPIO_BULK_PIN(LCD_DATA15), >> +     JZ_GPIO_BULK_PIN(LCD_DATA16), >> +     JZ_GPIO_BULK_PIN(LCD_DATA17), >> +}; >> + >> +static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb) >> +{ >> +     unsigned int num; >> + >> +     switch (jzfb->pdata->lcd_type) { >> +     case JZ_LCD_TYPE_GENERIC_16_BIT: >> +             num = 4; >> +             break; >> +     case JZ_LCD_TYPE_GENERIC_18_BIT: >> +             num = 4; >> +             break; >> +     case JZ_LCD_TYPE_8BIT_SERIAL: >> +             num = 3; >> +             break; The lcd type serial looks interesting to me. It'd be nice to have some descriptive comments so that we know what its used with. >> +     default: >> +             num = 0; >> +             break; >> +     } >> +     return num; >> +} >> + >> +static unsigned int jzfb_num_data_pins(struct jzfb *jzfb) >> +{ >> +     unsigned int num; >> + >> +     switch (jzfb->pdata->lcd_type) { >> +     case JZ_LCD_TYPE_GENERIC_16_BIT: >> +             num = 16; >> +             break; >> +     case JZ_LCD_TYPE_GENERIC_18_BIT: >> +             num = 18; >> +             break; >> +     case JZ_LCD_TYPE_8BIT_SERIAL: >> +             num = 8; >> +             break; >> +     default: >> +             num = 0; >> +             break; >> +     } >> +     return num; >> +} >> + >> +/* Based on CNVT_TOHW macro from skeletonfb.c */ >> +static inline uint32_t jzfb_convert_color_to_hw(unsigned val, >> +     struct fb_bitfield *bf) >> +{ >> +     return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset; >> +} >> + >> +static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, >> +                     unsigned blue, unsigned transp, struct fb_info *fb) >> +{ >> +     uint32_t color; >> + >> +     if (regno >= 16) >> +             return -EINVAL; >> + >> +     color = jzfb_convert_color_to_hw(red, &fb->var.red); >> +     color |= jzfb_convert_color_to_hw(green, &fb->var.green); >> +     color |= jzfb_convert_color_to_hw(blue, &fb->var.blue); >> +     color |= jzfb_convert_color_to_hw(transp, &fb->var.transp); >> + >> +     ((uint32_t *)(fb->pseudo_palette))[regno] = color; >> + >> +     return 0; >> +} >> + >> +static int jzfb_get_controller_bpp(struct jzfb *jzfb) >> +{ >> +     switch (jzfb->pdata->bpp) { >> +     case 18: >> +     case 24: >> +             return 32; >> +     case 15: >> +             return 16; >> +     default: >> +             return jzfb->pdata->bpp; >> +     } >> +} >> + >> +static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb, >> +     struct fb_var_screeninfo *var) >> +{ >> +     size_t i; >> +     struct fb_videomode *mode = jzfb->pdata->modes; >> + >> +     for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) { >> +             if (mode->xres == var->xres && mode->yres == var->yres) >> +                     return mode; >> +     } >> + >> +     return NULL; >> +} >> + >> +static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb) >> +{ >> +     struct jzfb *jzfb = fb->par; >> +     struct fb_videomode *mode; >> + >> +     if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) && >> +             var->bits_per_pixel != jzfb->pdata->bpp) >> +             return -EINVAL; >> + >> +     mode = jzfb_get_mode(jzfb, var); >> +     if (mode == NULL) >> +             return -EINVAL; >> + >> +     fb_videomode_to_var(var, mode); >> + >> +     switch (jzfb->pdata->bpp) { >> +     case 8: >> +             break; >> +     case 15: >> +             var->red.offset = 10; >> +             var->red.length = 5; >> +             var->green.offset = 6; >> +             var->green.length = 5; >> +             var->blue.offset = 0; >> +             var->blue.length = 5; >> +             break; >> +     case 16: >> +             var->red.offset = 11; >> +             var->red.length = 5; >> +             var->green.offset = 5; >> +             var->green.length = 6; >> +             var->blue.offset = 0; >> +             var->blue.length = 5; >> +             break; >> +     case 18: >> +             var->red.offset = 16; >> +             var->red.length = 6; >> +             var->green.offset = 8; >> +             var->green.length = 6; >> +             var->blue.offset = 0; >> +             var->blue.length = 6; >> +             var->bits_per_pixel = 32; >> +             break; >> +     case 32: >> +     case 24: >> +             var->transp.offset = 24; >> +             var->transp.length = 8; >> +             var->red.offset = 16; >> +             var->red.length = 8; >> +             var->green.offset = 8; >> +             var->green.length = 8; >> +             var->blue.offset = 0; >> +             var->blue.length = 8; >> +             var->bits_per_pixel = 32; >> +             break; >> +     default: >> +             break; >> +     } >> + >> +     return 0; >> +} >> + >> +static int jzfb_set_par(struct fb_info *info) >> +{ >> +     struct jzfb *jzfb = info->par; >> +     struct fb_var_screeninfo *var = &info->var; >> +     struct fb_videomode *mode; >> +     uint16_t hds, vds; >> +     uint16_t hde, vde; >> +     uint16_t ht, vt; >> +     uint32_t ctrl; >> +     uint32_t cfg; >> +     unsigned long rate; >> + >> +     mode = jzfb_get_mode(jzfb, var); >> +     if (mode == NULL) >> +             return -EINVAL; >> + >> +     if (mode == info->mode) >> +             return 0; >> + >> +     info->mode = mode; >> + >> +     hds = mode->hsync_len + mode->left_margin; >> +     hde = hds + mode->xres; >> +     ht = hde + mode->right_margin; >> + >> +     vds = mode->vsync_len + mode->upper_margin; >> +     vde = vds + mode->yres; >> +     vt = vde + mode->lower_margin; >> + >> +     ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16; >> + >> +     switch (jzfb->pdata->bpp) { >> +     case 1: >> +             ctrl |= JZ_LCD_CTRL_BPP_1; >> +             break; >> +     case 2: >> +             ctrl |= JZ_LCD_CTRL_BPP_2; >> +             break; >> +     case 4: >> +             ctrl |= JZ_LCD_CTRL_BPP_4; >> +             break; >> +     case 8: >> +             ctrl |= JZ_LCD_CTRL_BPP_8; >> +     break; >> +     case 15: >> +             ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */ >> +     case 16: >> +             ctrl |= JZ_LCD_CTRL_BPP_15_16; >> +             break; >> +     case 18: >> +     case 24: >> +     case 32: >> +             ctrl |= JZ_LCD_CTRL_BPP_18_24; >> +             break; >> +     default: >> +             break; >> +     } >> + >> +     cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE | >> +             JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; >> + >> +     if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) >> +             cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; >> + >> +     if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) >> +             cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; >> + >> +     if (jzfb->pdata->pixclk_falling_edge) >> +             cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; >> + >> +     if (jzfb->pdata->date_enable_active_low) >> +             cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; >> + >> +     if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT) >> +             cfg |= JZ_LCD_CFG_18_BIT; >> + >> +     cfg |= jzfb->pdata->lcd_type & 0xf; >> + >> +     if (mode->pixclock) { >> +             rate = PICOS2KHZ(mode->pixclock) * 1000; >> +             mode->refresh = rate / vt / ht; >> +     } else { >> +             if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) >> +                     rate = mode->refresh * (vt + 2 * mode->xres) * ht; >> +             else >> +                     rate = mode->refresh * vt * ht; >> + >> +             mode->pixclock = KHZ2PICOS(rate / 1000); >> +     } >> + >> +     mutex_lock(&jzfb->lock); >> +     if (!jzfb->is_enabled) >> +             clk_enable(jzfb->ldclk); >> +     else >> +             ctrl |= JZ_LCD_CTRL_ENABLE; >> + >> +     writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC); >> +     writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC); >> + >> +     writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT); >> + >> +     writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH); >> +     writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV); >> + >> +     writel(cfg, jzfb->base + JZ_REG_LCD_CFG); >> + >> +     writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); >> + >> +     if (!jzfb->is_enabled) >> +             clk_disable(jzfb->ldclk); >> + >> +     mutex_unlock(&jzfb->lock); >> + >> +     clk_set_rate(jzfb->lpclk, rate); >> +     clk_set_rate(jzfb->ldclk, rate * 3); >> + >> +     return 0; >> +} >> + >> +static void jzfb_enable(struct jzfb *jzfb) >> +{ >> +     uint32_t ctrl; >> + >> +     clk_enable(jzfb->ldclk); >> + >> +     jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); >> +     jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); >> + >> +     writel(0, jzfb->base + JZ_REG_LCD_STATE); >> + >> +     writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); >> + >> +     ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); >> +     ctrl |= JZ_LCD_CTRL_ENABLE; >> +     ctrl &= ~JZ_LCD_CTRL_DISABLE; >> +     writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); >> +} >> + >> +static void jzfb_disable(struct jzfb *jzfb) >> +{ >> +     uint32_t ctrl; >> + >> +     ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); >> +     ctrl |= JZ_LCD_CTRL_DISABLE; >> +     writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); >> +     do { >> +             ctrl = readl(jzfb->base + JZ_REG_LCD_STATE); >> +     } while (!(ctrl & JZ_LCD_STATE_DISABLED)); >> + >> +     jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); >> +     jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); >> + >> +     clk_disable(jzfb->ldclk); >> +} >> + >> +static int jzfb_blank(int blank_mode, struct fb_info *info) >> +{ >> +     struct jzfb *jzfb = info->par; >> + >> +     switch (blank_mode) { >> +     case FB_BLANK_UNBLANK: >> +             mutex_lock(&jzfb->lock); >> +             if (jzfb->is_enabled) { >> +                     mutex_unlock(&jzfb->lock); >> +                     return 0; >> +             } >> + >> +             jzfb_enable(jzfb); >> +             jzfb->is_enabled = 1; >> + >> +             mutex_unlock(&jzfb->lock); >> +             break; >> +     default: >> +             mutex_lock(&jzfb->lock); >> +             if (!jzfb->is_enabled) { >> +                     mutex_unlock(&jzfb->lock); >> +                     return 0; >> +             } >> + >> +             jzfb_disable(jzfb); >> +             jzfb->is_enabled = 0; >> + >> +             mutex_unlock(&jzfb->lock); >> +             break; >> +     } >> + >> +     return 0; >> +} >> + >> +static int jzfb_alloc_devmem(struct jzfb *jzfb) >> +{ >> +     int max_videosize = 0; >> +     struct fb_videomode *mode = jzfb->pdata->modes; >> +     void *page; >> +     int i; >> + >> +     for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) { >> +             if (max_videosize < mode->xres * mode->yres) >> +                     max_videosize = mode->xres * mode->yres; >> +     } >> + >> +     max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3; >> + >> +     jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev, >> +                                     sizeof(*jzfb->framedesc), >> +                                     &jzfb->framedesc_phys, GFP_KERNEL); >> + >> +     if (!jzfb->framedesc) >> +             return -ENOMEM; >> + >> +     jzfb->vidmem_size = PAGE_ALIGN(max_videosize); >> +     jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev, >> +                                     jzfb->vidmem_size, >> +                                     &jzfb->vidmem_phys, GFP_KERNEL); >> + >> +     if (!jzfb->vidmem) >> +             goto err_free_framedesc; >> + >> +     for (page = jzfb->vidmem; >> +              page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size); >> +              page += PAGE_SIZE) { >> +             SetPageReserved(virt_to_page(page)); >> +     } It'd be nice to know the reasoning for the SetPageReserved. Thanks, jaya From chris@notav8.com Fri Jul 9 09:43:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jul 2010 09:43:34 +0200 (CEST) Received: from qmta08.emeryville.ca.mail.comcast.net ([76.96.30.80]:36397 "EHLO qmta08.emeryville.ca.mail.comcast.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491920Ab0GIHna (ORCPT ); Fri, 9 Jul 2010 09:43:30 +0200 Received: from omta19.emeryville.ca.mail.comcast.net ([76.96.30.76]) by qmta08.emeryville.ca.mail.comcast.net with comcast id fjiy1e0061eYJf8A8jjNh5; Fri, 09 Jul 2010 07:43:22 +0000 Received: from [10.0.0.109] ([98.248.135.54]) by omta19.emeryville.ca.mail.comcast.net with comcast id fjjM1e0031AbZWA01jjMNd; Fri, 09 Jul 2010 07:43:22 +0000 Message-ID: <4C36D31A.5000500@notav8.com> Date: Fri, 09 Jul 2010 00:43:22 -0700 From: Chris Rhodin User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: IP22 Debian Install Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27358 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chris@notav8.com Precedence: bulk X-list: linux-mips Hi, How much memory is required to install Debian (3.1 and 5) on an Indigo2? I have 128MB and get this when I attempt to install: tip22: IP22 Linux tftpboot loader 0.3.8.6 Loading program segment 2 at 0x88002000, size = 0x218000 Zeroing memory at 0x8821a000, size = 0x365b0 Starting kernel; entry point = 0x881e0040 Copied initrd from 0x88aab190 to 0x88251000 (0x1d5ce2 bytes) Exception: Status register: 0x30044803 Cause register: 0x30008010 Exception PC: 0x88124c74, Exception RA: 0x881f61b0 Read address error exception, bad address: 0x2a Local I/O interrupt register 1: 0x80 Local I/O interrupt register 2: 0xc8 Saved user regs in hex (&gpda 0xa8740e48, &_regs 0xa8741048): arg: a8740000 881dffe0 882505ac 88000000 tmp: a8740000 2 887fe378 887fe4cc 0 8 887fe7d4 881e0040 sve: a8740000 3 400000 8000000 16 3f80 0 c000000 t8 a8740000 t9 fffff7ff at bfefff7f v0 ffbff5ef v1 fff71fbf k1 500 gp a8740000 fp fefbfeff sp fffdffff ra feeffff7 PANIC: Unexpected exception It looks like the kernel is loading at 0x88002000 which is more than 128MB away from the beginning of kseg0. Thanks, Chris Rhodin From lars@metafoo.de Fri Jul 9 17:32:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jul 2010 17:32:35 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:50743 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491064Ab0GIPc2 (ORCPT ); Fri, 9 Jul 2010 17:32:28 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 20EB8DA4; Fri, 9 Jul 2010 17:32:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id XsKC3DNf0j+T; Fri, 9 Jul 2010 17:32:20 +0200 (CEST) Received: from [192.168.37.30] (port-8961.pppoe.wtnet.de [84.46.35.36]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 1A155D9C; Fri, 9 Jul 2010 17:32:05 +0200 (CEST) Message-ID: <4C3740E5.5080200@metafoo.de> Date: Fri, 09 Jul 2010 17:31:49 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Jaya Kumar CC: Andrew Morton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle , linux-fbdev@vger.kernel.org Subject: Re: [PATCH v2 16/26] fbdev: Add JZ4740 framebuffer driver References: <1276924111-11158-1-git-send-email-lars@metafoo.de> <1276924111-11158-17-git-send-email-lars@metafoo.de> <4C310ACD.6040604@metafoo.de> In-Reply-To: X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27359 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Jaya Kumar wrote: > On Mon, Jul 5, 2010 at 6:27 AM, Lars-Peter Clausen wrote: >> Hi Andrew >> >> v2 of this patch has been around for two weeks without any comments. I've fixed all >> the issues you had with v1. If you this version is ok, an Acked-By would be nice :) >> >> Thanks >> - Lars >> >> Lars-Peter Clausen wrote: >>> This patch adds support for the LCD controller on JZ4740 SoCs. > > Hi Lars, Andrew, > > I think this driver looks okay but I had some quick questions: > >>> +config FB_JZ4740 >>> + tristate "JZ4740 LCD framebuffer support" >>> + depends on FB >>> + select FB_SYS_FILLRECT >>> + select FB_SYS_COPYAREA >>> + select FB_SYS_IMAGEBLIT > > Out of curiosity, why FB_SYS and not FB_CFB? The users of FB_SYS are > drivers that use virtual memory for their framebuffer. I didn't see > any vmalloc in this driver. The framebuffer is allocated with dma_alloc_coherent and thus lives in system memory. > >>> + help >>> + Framebuffer support for the JZ4740 SoC. >>> + >>> source "drivers/video/omap/Kconfig" >>> source "drivers/video/omap2/Kconfig" >>> >>> diff --git a/drivers/video/Makefile b/drivers/video/Makefile >>> index 3c3bf86..fd2df57 100644 >>> --- a/drivers/video/Makefile >>> +++ b/drivers/video/Makefile >>> @@ -132,6 +132,7 @@ obj-$(CONFIG_FB_CARMINE) += carminefb.o >>> obj-$(CONFIG_FB_MB862XX) += mb862xx/ >>> obj-$(CONFIG_FB_MSM) += msm/ >>> obj-$(CONFIG_FB_NUC900) += nuc900fb.o >>> +obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o > > Just a minor nit, the typical naming in fbdev appears to be > controllerfb.c as opposed to controller_fb.c . > >>> # Platform or fallback drivers go here >>> obj-$(CONFIG_FB_UVESA) += uvesafb.o >>> diff --git a/drivers/video/jz4740_fb.c b/drivers/video/jz4740_fb.c >>> new file mode 100644 >>> index 0000000..8d03181 >>> --- /dev/null >>> +++ b/drivers/video/jz4740_fb.c >>> @@ -0,0 +1,817 @@ >>> +/* >>> + * Copyright (C) 2009-2010, Lars-Peter Clausen >>> + * JZ4740 SoC LCD framebuffer driver >>> + * >>> + * This program is free software; you can redistribute it and/or modify it >>> + * under the terms of the GNU General Public License as published by the >>> + * Free Software Foundation; either version 2 of the License, or (at your >>> + * option) any later version. >>> + * >>> + * You should have received a copy of the GNU General Public License along >>> + * with this program; if not, write to the Free Software Foundation, Inc., >>> + * 675 Mass Ave, Cambridge, MA 02139, USA. >>> + * >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include >>> +#include >>> + >>> +#include >>> +#include >>> + >>> +#include >>> + >>> +#include > > I see a lot of register defines below. Is there any reason why they > shouldn't go in above j*fb.h? Also, I'm not sure if linux/j*.h is the > best place. I think most fbdev drivers place their headers in > drivers/video itself unless they need to share something driver > specific with userspace which is rare. Is there a specific reason why > you put it in include/linux? > > The register definitions are only used by the driver, so there is no reason why they should be in a different file. The header file defines the platform data struct for this driver. But I guess the better location for it is include/video. >>> +#include >>> + >>> +#define JZ_REG_LCD_CFG 0x00 >>> +#define JZ_REG_LCD_VSYNC 0x04 >>> +#define JZ_REG_LCD_HSYNC 0x08 >>> +#define JZ_REG_LCD_VAT 0x0C >>> +#define JZ_REG_LCD_DAH 0x10 >>> +#define JZ_REG_LCD_DAV 0x14 >>> +#define JZ_REG_LCD_PS 0x18 >>> +#define JZ_REG_LCD_CLS 0x1C >>> +#define JZ_REG_LCD_SPL 0x20 >>> +#define JZ_REG_LCD_REV 0x24 >>> +#define JZ_REG_LCD_CTRL 0x30 >>> +#define JZ_REG_LCD_STATE 0x34 >>> +#define JZ_REG_LCD_IID 0x38 >>> +#define JZ_REG_LCD_DA0 0x40 >>> +#define JZ_REG_LCD_SA0 0x44 >>> +#define JZ_REG_LCD_FID0 0x48 >>> +#define JZ_REG_LCD_CMD0 0x4C >>> +#define JZ_REG_LCD_DA1 0x50 >>> +#define JZ_REG_LCD_SA1 0x54 >>> +#define JZ_REG_LCD_FID1 0x58 >>> +#define JZ_REG_LCD_CMD1 0x5C >>> + >>> +#define JZ_LCD_CFG_SLCD BIT(31) >>> +#define JZ_LCD_CFG_PS_DISABLE BIT(23) >>> +#define JZ_LCD_CFG_CLS_DISABLE BIT(22) >>> +#define JZ_LCD_CFG_SPL_DISABLE BIT(21) >>> +#define JZ_LCD_CFG_REV_DISABLE BIT(20) >>> +#define JZ_LCD_CFG_HSYNCM BIT(19) >>> +#define JZ_LCD_CFG_PCLKM BIT(18) >>> +#define JZ_LCD_CFG_INV BIT(17) >>> +#define JZ_LCD_CFG_SYNC_DIR BIT(16) >>> +#define JZ_LCD_CFG_PS_POLARITY BIT(15) >>> +#define JZ_LCD_CFG_CLS_POLARITY BIT(14) >>> +#define JZ_LCD_CFG_SPL_POLARITY BIT(13) >>> +#define JZ_LCD_CFG_REV_POLARITY BIT(12) >>> +#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) >>> +#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) >>> +#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) >>> +#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) >>> +#define JZ_LCD_CFG_18_BIT BIT(7) >>> +#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) >>> +#define JZ_LCD_CFG_MODE_MASK 0xf >>> + >>> +#define JZ_LCD_CTRL_BURST_4 (0x0 << 28) >>> +#define JZ_LCD_CTRL_BURST_8 (0x1 << 28) >>> +#define JZ_LCD_CTRL_BURST_16 (0x2 << 28) >>> +#define JZ_LCD_CTRL_RGB555 BIT(27) >>> +#define JZ_LCD_CTRL_OFUP BIT(26) >>> +#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) >>> +#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) >>> +#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) >>> +#define JZ_LCD_CTRL_PDD_MASK (0xff << 16) >>> +#define JZ_LCD_CTRL_EOF_IRQ BIT(13) >>> +#define JZ_LCD_CTRL_SOF_IRQ BIT(12) >>> +#define JZ_LCD_CTRL_OFU_IRQ BIT(11) >>> +#define JZ_LCD_CTRL_IFU0_IRQ BIT(10) >>> +#define JZ_LCD_CTRL_IFU1_IRQ BIT(9) >>> +#define JZ_LCD_CTRL_DD_IRQ BIT(8) >>> +#define JZ_LCD_CTRL_QDD_IRQ BIT(7) >>> +#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) >>> +#define JZ_LCD_CTRL_LSB_FISRT BIT(5) >>> +#define JZ_LCD_CTRL_DISABLE BIT(4) >>> +#define JZ_LCD_CTRL_ENABLE BIT(3) >>> +#define JZ_LCD_CTRL_BPP_1 0x0 >>> +#define JZ_LCD_CTRL_BPP_2 0x1 >>> +#define JZ_LCD_CTRL_BPP_4 0x2 >>> +#define JZ_LCD_CTRL_BPP_8 0x3 >>> +#define JZ_LCD_CTRL_BPP_15_16 0x4 >>> +#define JZ_LCD_CTRL_BPP_18_24 0x5 >>> + >>> +#define JZ_LCD_CMD_SOF_IRQ BIT(15) >>> +#define JZ_LCD_CMD_EOF_IRQ BIT(16) >>> +#define JZ_LCD_CMD_ENABLE_PAL BIT(12) >>> + >>> +#define JZ_LCD_SYNC_MASK 0x3ff >>> + >>> +#define JZ_LCD_STATE_DISABLED BIT(0) >>> + >>> +struct jzfb_framedesc { >>> + uint32_t next; >>> + uint32_t addr; >>> + uint32_t id; >>> + uint32_t cmd; >>> +} __packed; >>> + >>> +struct jzfb { >>> + struct fb_info *fb; >>> + struct platform_device *pdev; >>> + void __iomem *base; >>> + struct resource *mem; >>> + struct jz4740_fb_platform_data *pdata; >>> + >>> + size_t vidmem_size; >>> + void *vidmem; >>> + dma_addr_t vidmem_phys; >>> + struct jzfb_framedesc *framedesc; >>> + dma_addr_t framedesc_phys; >>> + >>> + struct clk *ldclk; >>> + struct clk *lpclk; >>> + >>> + unsigned is_enabled:1; > > Out of curiosity, why the bitfield? > >>> + struct mutex lock; >>> + >>> + uint32_t pseudo_palette[16]; >>> +}; >>> + >>> +static const struct fb_fix_screeninfo jzfb_fix __devinitdata = { >>> + .id = "JZ4740 FB", >>> + .type = FB_TYPE_PACKED_PIXELS, >>> + .visual = FB_VISUAL_TRUECOLOR, >>> + .xpanstep = 0, >>> + .ypanstep = 0, >>> + .ywrapstep = 0, >>> + .accel = FB_ACCEL_NONE, >>> +}; >>> + >>> +static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = { >>> + JZ_GPIO_BULK_PIN(LCD_PCLK), >>> + JZ_GPIO_BULK_PIN(LCD_HSYNC), >>> + JZ_GPIO_BULK_PIN(LCD_VSYNC), >>> + JZ_GPIO_BULK_PIN(LCD_DE), >>> + JZ_GPIO_BULK_PIN(LCD_PS), >>> + JZ_GPIO_BULK_PIN(LCD_REV), >>> +}; >>> + >>> +static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = { >>> + JZ_GPIO_BULK_PIN(LCD_DATA0), >>> + JZ_GPIO_BULK_PIN(LCD_DATA1), >>> + JZ_GPIO_BULK_PIN(LCD_DATA2), >>> + JZ_GPIO_BULK_PIN(LCD_DATA3), >>> + JZ_GPIO_BULK_PIN(LCD_DATA4), >>> + JZ_GPIO_BULK_PIN(LCD_DATA5), >>> + JZ_GPIO_BULK_PIN(LCD_DATA6), >>> + JZ_GPIO_BULK_PIN(LCD_DATA7), >>> + JZ_GPIO_BULK_PIN(LCD_DATA8), >>> + JZ_GPIO_BULK_PIN(LCD_DATA9), >>> + JZ_GPIO_BULK_PIN(LCD_DATA10), f>>> + JZ_GPIO_BULK_PIN(LCD_DATA11), >>> + JZ_GPIO_BULK_PIN(LCD_DATA12), >>> + JZ_GPIO_BULK_PIN(LCD_DATA13), >>> + JZ_GPIO_BULK_PIN(LCD_DATA14), >>> + JZ_GPIO_BULK_PIN(LCD_DATA15), >>> + JZ_GPIO_BULK_PIN(LCD_DATA16), >>> + JZ_GPIO_BULK_PIN(LCD_DATA17), >>> +}; >>> + >>> +static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb) >>> +{ >>> + unsigned int num; >>> + >>> + switch (jzfb->pdata->lcd_type) { >>> + case JZ_LCD_TYPE_GENERIC_16_BIT: >>> + num = 4; >>> + break; >>> + case JZ_LCD_TYPE_GENERIC_18_BIT: >>> + num = 4; >>> + break; >>> + case JZ_LCD_TYPE_8BIT_SERIAL: >>> + num = 3; >>> + break; > > The lcd type serial looks interesting to me. It'd be nice to have some > descriptive comments so that we know what its used with. > Uhm, its a standard 8bit serial connection. 3 channels (R,G,B) and 8 bits per channel. And the channels are send one after another over the wire. >>> + default: >>> + num = 0; >>> + break; >>> + } >>> + return num; >>> +} >>> + >>> +static unsigned int jzfb_num_data_pins(struct jzfb *jzfb) >>> +{ >>> + unsigned int num; >>> + >>> + switch (jzfb->pdata->lcd_type) { >>> + case JZ_LCD_TYPE_GENERIC_16_BIT: >>> + num = 16; >>> + break; >>> + case JZ_LCD_TYPE_GENERIC_18_BIT: >>> + num = 18; >>> + break; >>> + case JZ_LCD_TYPE_8BIT_SERIAL: >>> + num = 8; >>> + break; >>> + default: >>> + num = 0; >>> + break; >>> + } >>> + return num; >>> +} >>> + >>> +/* Based on CNVT_TOHW macro from skeletonfb.c */ >>> +static inline uint32_t jzfb_convert_color_to_hw(unsigned val, >>> + struct fb_bitfield *bf) >>> +{ >>> + return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset; >>> +} >>> + >>> +static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, >>> + unsigned blue, unsigned transp, struct fb_info *fb) >>> +{ >>> + uint32_t color; >>> + >>> + if (regno >= 16) >>> + return -EINVAL; >>> + >>> + color = jzfb_convert_color_to_hw(red, &fb->var.red); >>> + color |= jzfb_convert_color_to_hw(green, &fb->var.green); >>> + color |= jzfb_convert_color_to_hw(blue, &fb->var.blue); >>> + color |= jzfb_convert_color_to_hw(transp, &fb->var.transp); >>> + >>> + ((uint32_t *)(fb->pseudo_palette))[regno] = color; >>> + >>> + return 0; >>> +} >>> + >>> +static int jzfb_get_controller_bpp(struct jzfb *jzfb) >>> +{ >>> + switch (jzfb->pdata->bpp) { >>> + case 18: >>> + case 24: >>> + return 32; >>> + case 15: >>> + return 16; >>> + default: >>> + return jzfb->pdata->bpp; >>> + } >>> +} >>> + >>> +static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb, >>> + struct fb_var_screeninfo *var) >>> +{ >>> + size_t i; >>> + struct fb_videomode *mode = jzfb->pdata->modes; >>> + >>> + for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) { >>> + if (mode->xres == var->xres && mode->yres == var->yres) >>> + return mode; >>> + } >>> + >>> + return NULL; >>> +} >>> + >>> +static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb) >>> +{ >>> + struct jzfb *jzfb = fb->par; >>> + struct fb_videomode *mode; >>> + >>> + if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) && >>> + var->bits_per_pixel != jzfb->pdata->bpp) >>> + return -EINVAL; >>> + >>> + mode = jzfb_get_mode(jzfb, var); >>> + if (mode == NULL) >>> + return -EINVAL; >>> + >>> + fb_videomode_to_var(var, mode); >>> + >>> + switch (jzfb->pdata->bpp) { >>> + case 8: >>> + break; >>> + case 15: >>> + var->red.offset = 10; >>> + var->red.length = 5; >>> + var->green.offset = 6; >>> + var->green.length = 5; >>> + var->blue.offset = 0; >>> + var->blue.length = 5; >>> + break; >>> + case 16: >>> + var->red.offset = 11; >>> + var->red.length = 5; >>> + var->green.offset = 5; >>> + var->green.length = 6; >>> + var->blue.offset = 0; >>> + var->blue.length = 5; >>> + break; >>> + case 18: >>> + var->red.offset = 16; >>> + var->red.length = 6; >>> + var->green.offset = 8; >>> + var->green.length = 6; >>> + var->blue.offset = 0; >>> + var->blue.length = 6; >>> + var->bits_per_pixel = 32; >>> + break; >>> + case 32: >>> + case 24: >>> + var->transp.offset = 24; >>> + var->transp.length = 8; >>> + var->red.offset = 16; >>> + var->red.length = 8; >>> + var->green.offset = 8; >>> + var->green.length = 8; >>> + var->blue.offset = 0; >>> + var->blue.length = 8; >>> + var->bits_per_pixel = 32; >>> + break; >>> + default: >>> + break; >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +static int jzfb_set_par(struct fb_info *info) >>> +{ >>> + struct jzfb *jzfb = info->par; >>> + struct fb_var_screeninfo *var = &info->var; >>> + struct fb_videomode *mode; >>> + uint16_t hds, vds; >>> + uint16_t hde, vde; >>> + uint16_t ht, vt; >>> + uint32_t ctrl; >>> + uint32_t cfg; >>> + unsigned long rate; >>> + >>> + mode = jzfb_get_mode(jzfb, var); >>> + if (mode == NULL) >>> + return -EINVAL; >>> + >>> + if (mode == info->mode) >>> + return 0; >>> + >>> + info->mode = mode; >>> + >>> + hds = mode->hsync_len + mode->left_margin; >>> + hde = hds + mode->xres; >>> + ht = hde + mode->right_margin; >>> + >>> + vds = mode->vsync_len + mode->upper_margin; >>> + vde = vds + mode->yres; >>> + vt = vde + mode->lower_margin; >>> + >>> + ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16; >>> + >>> + switch (jzfb->pdata->bpp) { >>> + case 1: >>> + ctrl |= JZ_LCD_CTRL_BPP_1; >>> + break; >>> + case 2: >>> + ctrl |= JZ_LCD_CTRL_BPP_2; >>> + break; >>> + case 4: >>> + ctrl |= JZ_LCD_CTRL_BPP_4; >>> + break; >>> + case 8: >>> + ctrl |= JZ_LCD_CTRL_BPP_8; >>> + break; >>> + case 15: >>> + ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */ >>> + case 16: >>> + ctrl |= JZ_LCD_CTRL_BPP_15_16; >>> + break; >>> + case 18: >>> + case 24: >>> + case 32: >>> + ctrl |= JZ_LCD_CTRL_BPP_18_24; >>> + break; >>> + default: >>> + break; >>> + } >>> + >>> + cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE | >>> + JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; >>> + >>> + if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) >>> + cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; >>> + >>> + if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) >>> + cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; >>> + >>> + if (jzfb->pdata->pixclk_falling_edge) >>> + cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; >>> + >>> + if (jzfb->pdata->date_enable_active_low) >>> + cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; >>> + >>> + if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT) >>> + cfg |= JZ_LCD_CFG_18_BIT; >>> + >>> + cfg |= jzfb->pdata->lcd_type & 0xf; >>> + >>> + if (mode->pixclock) { >>> + rate = PICOS2KHZ(mode->pixclock) * 1000; >>> + mode->refresh = rate / vt / ht; >>> + } else { >>> + if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) >>> + rate = mode->refresh * (vt + 2 * mode->xres) * ht; >>> + else >>> + rate = mode->refresh * vt * ht; >>> + >>> + mode->pixclock = KHZ2PICOS(rate / 1000); >>> + } >>> + >>> + mutex_lock(&jzfb->lock); >>> + if (!jzfb->is_enabled) >>> + clk_enable(jzfb->ldclk); >>> + else >>> + ctrl |= JZ_LCD_CTRL_ENABLE; >>> + >>> + writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC); >>> + writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC); >>> + >>> + writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT); >>> + >>> + writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH); >>> + writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV); >>> + >>> + writel(cfg, jzfb->base + JZ_REG_LCD_CFG); >>> + >>> + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); >>> + >>> + if (!jzfb->is_enabled) >>> + clk_disable(jzfb->ldclk); >>> + >>> + mutex_unlock(&jzfb->lock); >>> + >>> + clk_set_rate(jzfb->lpclk, rate); >>> + clk_set_rate(jzfb->ldclk, rate * 3); >>> + >>> + return 0; >>> +} >>> + >>> +static void jzfb_enable(struct jzfb *jzfb) >>> +{ >>> + uint32_t ctrl; >>> + >>> + clk_enable(jzfb->ldclk); >>> + >>> + jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); >>> + jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); >>> + >>> + writel(0, jzfb->base + JZ_REG_LCD_STATE); >>> + >>> + writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); >>> + >>> + ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); >>> + ctrl |= JZ_LCD_CTRL_ENABLE; >>> + ctrl &= ~JZ_LCD_CTRL_DISABLE; >>> + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); >>> +} >>> + >>> +static void jzfb_disable(struct jzfb *jzfb) >>> +{ >>> + uint32_t ctrl; >>> + >>> + ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); >>> + ctrl |= JZ_LCD_CTRL_DISABLE; >>> + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); >>> + do { >>> + ctrl = readl(jzfb->base + JZ_REG_LCD_STATE); >>> + } while (!(ctrl & JZ_LCD_STATE_DISABLED)); >>> + >>> + jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); >>> + jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); >>> + >>> + clk_disable(jzfb->ldclk); >>> +} >>> + >>> +static int jzfb_blank(int blank_mode, struct fb_info *info) >>> +{ >>> + struct jzfb *jzfb = info->par; >>> + >>> + switch (blank_mode) { >>> + case FB_BLANK_UNBLANK: >>> + mutex_lock(&jzfb->lock); >>> + if (jzfb->is_enabled) { >>> + mutex_unlock(&jzfb->lock); >>> + return 0; >>> + } >>> + >>> + jzfb_enable(jzfb); >>> + jzfb->is_enabled = 1; >>> + >>> + mutex_unlock(&jzfb->lock); >>> + break; >>> + default: >>> + mutex_lock(&jzfb->lock); >>> + if (!jzfb->is_enabled) { >>> + mutex_unlock(&jzfb->lock); >>> + return 0; >>> + } >>> + >>> + jzfb_disable(jzfb); >>> + jzfb->is_enabled = 0; >>> + >>> + mutex_unlock(&jzfb->lock); >>> + break; >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +static int jzfb_alloc_devmem(struct jzfb *jzfb) >>> +{ >>> + int max_videosize = 0; >>> + struct fb_videomode *mode = jzfb->pdata->modes; >>> + void *page; >>> + int i; >>> + >>> + for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) { >>> + if (max_videosize < mode->xres * mode->yres) >>> + max_videosize = mode->xres * mode->yres; >>> + } >>> + >>> + max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3; >>> + >>> + jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev, >>> + sizeof(*jzfb->framedesc), >>> + &jzfb->framedesc_phys, GFP_KERNEL); >>> + >>> + if (!jzfb->framedesc) >>> + return -ENOMEM; >>> + >>> + jzfb->vidmem_size = PAGE_ALIGN(max_videosize); >>> + jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev, >>> + jzfb->vidmem_size, >>> + &jzfb->vidmem_phys, GFP_KERNEL); >>> + >>> + if (!jzfb->vidmem) >>> + goto err_free_framedesc; >>> + >>> + for (page = jzfb->vidmem; >>> + page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size); >>> + page += PAGE_SIZE) { >>> + SetPageReserved(virt_to_page(page)); >>> + } > > It'd be nice to know the reasoning for the SetPageReserved. > It's to make sure that the framebuffer memory is not swapped out. But actually I'm not sure if it's really needed, since I'm not that familar with how the swap management code choose pages to swap out. But there are similar drivers seem to do the same thing. > Thanks, > jaya > Thanks for reviewing, - - Lars -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkw3QN8ACgkQBX4mSR26RiNg3wCfeg7uauWGHNx5z9StBcbloOrj luYAnjjGFuYcD8O7zBKjlzOHOMD8PPuJ =qrO3 -----END PGP SIGNATURE----- From David.Daney@caviumnetworks.com Fri Jul 9 23:52:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jul 2010 23:52:48 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15340 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492013Ab0GIVwm (ORCPT ); Fri, 9 Jul 2010 23:52:42 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 09 Jul 2010 14:53:05 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 9 Jul 2010 14:52:39 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 9 Jul 2010 14:52:39 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.4/8.14.3) with ESMTP id o69LqU0o012087; Fri, 9 Jul 2010 14:52:33 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.4/8.14.4/Submit) id o69LqPhA012085; Fri, 9 Jul 2010 14:52:25 -0700 From: David Daney To: rostedt@goodmis.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, David Daney , Li Hong , Ingo Molnar , Matt Fleming , Ralf Baechle Subject: [PATCH] tracing: recordmcount.pl: Fix $mcount_regex for MIPS. Date: Fri, 9 Jul 2010 14:52:05 -0700 Message-Id: <1278712325-12050-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 X-OriginalArrivalTime: 09 Jul 2010 21:52:39.0815 (UTC) FILETIME=[0D02C970:01CB1FB1] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27360 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips I found this issue in a locally patched 2.6.32.x, current kernels have moved the offending code to an __init function which is skipped by recordmcount.pl, so the bug is not currently being exercised. However, I think the patch is still a good idea, to avoid future problems if _mcount were to ever have its address taken in normal code. This is what I originally saw: Although arch/mips/kernel/ftrace.c is built without -pg, and thus contains no calls to _mcount, it does use the address of _mcount in ftrace_make_nop(). This was causing relocations to be emitted for _mcount which recordmcount.pl erronously took to be _mcount call sites. The result was that the text of ftrace_make_nop() would be patched with garbage leading to a system crash. In non-module code, all _mcount call sites will have R_MIPS_26 relocations, so we restrict $mcount_regex to only match on these. Signed-off-by: David Daney Cc: Steven Rostedt Cc: Li Hong Cc: Ingo Molnar Cc: Matt Fleming Cc: Ralf Baechle --- scripts/recordmcount.pl | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl index f3c9c0a..0171060 100755 --- a/scripts/recordmcount.pl +++ b/scripts/recordmcount.pl @@ -326,7 +326,7 @@ if ($arch eq "x86_64") { # 14: R_MIPS_NONE *ABS* # 18: 00020021 nop if ($is_module eq "0") { - $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$"; + $mcount_regex = "^\\s*([0-9a-fA-F]+): R_MIPS_26\\s+_mcount\$"; } else { $mcount_regex = "^\\s*([0-9a-fA-F]+): R_MIPS_HI16\\s+_mcount\$"; } -- 1.6.6.1 From rostedt@goodmis.org Sat Jul 10 02:26:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Jul 2010 02:26:15 +0200 (CEST) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.124]:35828 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492348Ab0GJA0L (ORCPT ); Sat, 10 Jul 2010 02:26:11 +0200 X-Authority-Analysis: v=1.1 cv=eWk9bc5BAcy1KEyGm/gc5mmqTM7Cp/ADlcqpp9MTMWU= c=1 sm=0 a=FRz5Z-s_pikA:10 a=uEzv4HemXiYA:10 a=7U3hwN5JcxgA:10 a=Q9fys5e9bTEA:10 a=gMqfjgEr1zLu/65IO0LwxA==:17 a=enOvQawGAAAA:8 a=meVymXHHAAAA:8 a=pGLkceISAAAA:8 a=fLbG0_AyAAAA:8 a=WPyIoOwQAAAA:8 a=JthM5FLITNI90Auf7SkA:9 a=PdYW2Q_PvQN3CrIXJFoA:7 a=PcINbpXVotJABtRA0vZcE26HmBwA:4 a=PUjeQqilurYA:10 a=bkT6KWdcy0IA:10 a=jeBq3FmKZ4MA:10 a=MSl-tDqOz04A:10 a=CO1XcZHhRtcA:10 a=1DbiqZag68YA:10 a=NfQ4XEVMfFwRZDAQ:21 a=RlLd5cM5IF2OoY7G:21 a=gMqfjgEr1zLu/65IO0LwxA==:117 X-Cloudmark-Score: 0 X-Originating-IP: 74.67.89.75 Received: from [74.67.89.75] ([74.67.89.75:60417] helo=[192.168.23.10]) by hrndva-oedge04.mail.rr.com (envelope-from ) (ecelerity 2.2.2.39 r()) with ESMTP id 5E/8C-00342-B1EB73C4; Sat, 10 Jul 2010 00:26:04 +0000 Subject: Re: [PATCH] tracing: recordmcount.pl: Fix $mcount_regex for MIPS. From: Steven Rostedt Reply-To: rostedt@goodmis.org To: David Daney Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Li Hong , Ingo Molnar , Matt Fleming , Ralf Baechle , Wu Zhangjin In-Reply-To: <1278712325-12050-1-git-send-email-ddaney@caviumnetworks.com> References: <1278712325-12050-1-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset="ISO-8859-15" Organization: Kihon Technologies Inc. Date: Fri, 09 Jul 2010 20:26:02 -0400 Message-ID: <1278721562.1537.169.camel@gandalf.stny.rr.com> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27361 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk X-list: linux-mips On Fri, 2010-07-09 at 14:52 -0700, David Daney wrote: > I found this issue in a locally patched 2.6.32.x, current kernels have > moved the offending code to an __init function which is skipped by > recordmcount.pl, so the bug is not currently being exercised. > However, I think the patch is still a good idea, to avoid future > problems if _mcount were to ever have its address taken in normal > code. > > This is what I originally saw: > > Although arch/mips/kernel/ftrace.c is built without -pg, and thus > contains no calls to _mcount, it does use the address of _mcount > in ftrace_make_nop(). This was causing relocations to be emitted > for _mcount which recordmcount.pl erronously took to be _mcount > call sites. The result was that the text of ftrace_make_nop() > would be patched with garbage leading to a system crash. > > In non-module code, all _mcount call sites will have R_MIPS_26 > relocations, so we restrict $mcount_regex to only match on these. > I'd like to get an Acked-by from Ralf and Wu before pulling this. Thanks, -- Steve > Signed-off-by: David Daney > Cc: Steven Rostedt > Cc: Li Hong > Cc: Ingo Molnar > Cc: Matt Fleming > Cc: Ralf Baechle > --- > scripts/recordmcount.pl | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl > index f3c9c0a..0171060 100755 > --- a/scripts/recordmcount.pl > +++ b/scripts/recordmcount.pl > @@ -326,7 +326,7 @@ if ($arch eq "x86_64") { > # 14: R_MIPS_NONE *ABS* > # 18: 00020021 nop > if ($is_module eq "0") { > - $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$"; > + $mcount_regex = "^\\s*([0-9a-fA-F]+): R_MIPS_26\\s+_mcount\$"; > } else { > $mcount_regex = "^\\s*([0-9a-fA-F]+): R_MIPS_HI16\\s+_mcount\$"; > } From ralf@linux-mips.org Sat Jul 10 04:12:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Jul 2010 04:12:52 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42939 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491959Ab0GJCMt (ORCPT ); Sat, 10 Jul 2010 04:12:49 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o6A2CTQ8017421; Sat, 10 Jul 2010 03:12:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o6A2CSRB017418; Sat, 10 Jul 2010 03:12:28 +0100 Date: Sat, 10 Jul 2010 03:12:27 +0100 From: Ralf Baechle To: Steven Rostedt Cc: David Daney , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Li Hong , Ingo Molnar , Matt Fleming , Wu Zhangjin Subject: Re: [PATCH] tracing: recordmcount.pl: Fix $mcount_regex for MIPS. Message-ID: <20100710021227.GA16134@linux-mips.org> References: <1278712325-12050-1-git-send-email-ddaney@caviumnetworks.com> <1278721562.1537.169.camel@gandalf.stny.rr.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1278721562.1537.169.camel@gandalf.stny.rr.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27362 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jul 09, 2010 at 08:26:02PM -0400, Steven Rostedt wrote: > I'd like to get an Acked-by from Ralf and Wu before pulling this. I talked through this on irc with David and it is the right thing to do. Acked-by: Ralf Baechle Ralf From wuzhangjin@gmail.com Sat Jul 10 05:32:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Jul 2010 05:32:49 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:36973 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490955Ab0GJDcp (ORCPT ); Sat, 10 Jul 2010 05:32:45 +0200 Received: by pxi13 with SMTP id 13so1289545pxi.36 for ; Fri, 09 Jul 2010 20:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=x4k/qK+vUN55nxvyXM+jfQ6+eTRalmubPQf6B/40uMk=; b=TTSo47QHR4NXovQUojOAjeUs6K17Ywi199sG90O6C5KUq0u9eAUQF1pUCDNC/MqY8G 0+Z55P+OVIJaWrUA4HjXrs4X/rb0j/LSR8GCI7AYgBQf+WAMYJqmj310Pjcd3lDj4Ann VInuMgrcDdAAG2Tk7Vu7oCViYJRq0Kc5oXFhE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=WFAAVmMVr88wopmvT29kJUCIUqb0GT/qNIudE6EL/NSUOPolHrsUJ+n35PKzjMKseN WqD8C4P46ZQHjbfPokpEa6uiaao6ARBj0MyLWSPma5LWeZ32/wZOwc84eE9eD2UDS+zz n/N4eHMuPfeCxISPVx3X8dBhJ8IRbto9uPUHs= Received: by 10.142.148.2 with SMTP id v2mr7456717wfd.115.1278732756550; Fri, 09 Jul 2010 20:32:36 -0700 (PDT) Received: from [192.168.0.106] ([182.18.29.11]) by mx.google.com with ESMTPS id z1sm1842990wfd.15.2010.07.09.20.32.32 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 09 Jul 2010 20:32:35 -0700 (PDT) Subject: Re: [PATCH] tracing: recordmcount.pl: Fix $mcount_regex for MIPS. From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: rostedt@goodmis.org Cc: David Daney , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Li Hong , Ingo Molnar , Matt Fleming , Ralf Baechle In-Reply-To: <1278721562.1537.169.camel@gandalf.stny.rr.com> References: <1278712325-12050-1-git-send-email-ddaney@caviumnetworks.com> <1278721562.1537.169.camel@gandalf.stny.rr.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 10 Jul 2010 11:32:30 +0800 Message-ID: <1278732750.4750.4.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27363 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2010-07-09 at 20:26 -0400, Steven Rostedt wrote: > > I'd like to get an Acked-by from Ralf and Wu before pulling this. > It is ok for me ;) Acked-by: Wu Zhangjin Regards, Wu Zhangjin From skuribay@pobox.com Sun Jul 11 16:02:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Jul 2010 16:02:14 +0200 (CEST) Received: from b-pb-sasl-quonix.pobox.com ([208.72.237.35]:36309 "EHLO sasl.smtp.pobox.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491873Ab0GKOCK (ORCPT ); Sun, 11 Jul 2010 16:02:10 +0200 Received: from sasl.smtp.pobox.com (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 4336EB46AB; Sun, 11 Jul 2010 10:01:58 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=pobox.com; h=message-id :date:from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; s=sasl; bh=DsTEP7bFLMqN HzbGZfTHIg9PNfE=; b=Jn6sc9TDl0RYWUebPcDOBk6iC4TtbTj6m+5UGADr3Z7r 6hK2q791uovKDcqFT33ZqwfGsS5UWY6F0VYOIjirP+jU6GVJyd75hhmKMeTdi1NM gnxN96UAQ+lrZM/Wl/Pu/400kCBGWgQPi6fbwDFYR7m9k0D1aFzteeEBxZmDN84= DomainKey-Signature: a=rsa-sha1; c=nofws; d=pobox.com; h=message-id:date :from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; q=dns; s=sasl; b=pl7YBY niL+L63JCnz7hFEYS3BmJPhh6mkrI6BvmYrnWmwWrSp9fXnan9pUIFj0fe87QqcE QFb4wr+zb/0O3VCcUagvf0G1U/VOH9Hdn/5Vpwgt/btOBhRgWwUbM9Ob1yXs+ekn ZWdsSdfR26OsfoYt0yXDSzB+0BVMsb+QRWuXo= Received: from b-pb-sasl-quonix. (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 295BEB46AA; Sun, 11 Jul 2010 10:01:57 -0400 (EDT) Received: from [192.168.11.3] (unknown [114.162.174.29]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by b-sasl-quonix.pobox.com (Postfix) with ESMTPSA id 1B3BEB46A9; Sun, 11 Jul 2010 10:01:54 -0400 (EDT) Message-ID: <4C39CED0.40503@pobox.com> Date: Sun, 11 Jul 2010 23:01:52 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.10) Gecko/20100527 Thunderbird/3.0.5 MIME-Version: 1.0 To: David VomLehn CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: PowerTV: Use fls() carefully where static optimization is required References: <4C2755A3.3080600@pobox.com> <20100630220124.GA576@dvomlehn-lnx2.corp.sa.net> <4C2DF427.7080508@pobox.com> In-Reply-To: <4C2DF427.7080508@pobox.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Pobox-Relay-ID: DE23EA74-8CF4-11DF-A241-DA91016DD5F0-47602734!b-pb-sasl-quonix.pobox.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27364 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@pobox.com Precedence: bulk X-list: linux-mips Hi David, Before submitting irq_ffs() cleanup patchset, it seems I/we need to sort out PowerTV's IRQ code properly. Please find my comments below. On 07/02/2010 11:13 PM, Shinya Kuribayashi wrote: > On 07/01/2010 07:01 AM, David VomLehn wrote: >> Thanks! You are correct in your analysis and make a good point that >> clz should be used in interrupt handling. I think, though, that it's >> better to go ahead and supply a full-blown cpu-features-override.h >> rather than focusing on this one case. This way fls() will be optimized >> to use clz everywhere and any other optimizations that depend on constant >> cpu_has_* values will also be used. > > Your choice, either one will be fine :-) Double-checking the generated code, current PowerTV IRQ code is slightly different from what I expected: 1) PowerTV doesn't use mips_cpu_irq_init(), so IRQ #0-7 are not allocated for MIPS CPU IRQs, but used for its ASIC interrupts. All irq_desc[0.. 126] (NR_IRQS=127) are meant for ASIC interrupts, a bit surprising ;-) Presumably it intentionally skips primary CP0.Status decoding. Just check CP0.Status, and if it's flagged, then jump into ASIC dispatcher directly. 2) PowerTV's irq_ffs() behaves differently from Malta or MISPSim one. Without CLZ optimization, current PowerTV's irq_ffs() returns: PowerTV ------- status=0x 100 => 9 status=0x 300 => 10 status=0x 700 => 11 status=0x f00 => 12 status=0x1f00 => 13 status=0x3f00 => 14 status=0x7f00 => 15 status=0xff00 => 16 while Malta and MIPSSim would return: Malta, MIPSSim ------- status=0x 100 => 0 status=0x 300 => 1 status=0x 700 => 2 status=0x f00 => 3 status=0x1f00 => 4 status=0x3f00 => 5 status=0x7f00 => 6 status=0xff00 => 7 3) In addition to 2), the most questionable part is (irq == CAUSEF_IP3): > asmlinkage void plat_irq_dispatch(void) > { > unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; > int irq; > > irq = irq_ffs(pending); > > if (irq == CAUSEF_IP3) > asic_irqdispatch(); > else if (irq >= 0) > do_IRQ(irq); > else > spurious_interrupt(); > } CAUSEF_IP3 is 0x0800, while irq_ffs() returns (9..16). This implies that asic_irqdispatch() is not used here, and all interrupts are forwarded to 'else-if (irq >= 0) do_IRQ(irq);' path. Remember that all irq_desc[0..126] are meant for ASIC interrupts, and irq_ffs() returns (9..16). How do you handle rest of interrupts? I'm lost here. Taking a closer look, PowerTV has the code registering VI- or EIC- handlers. Asic_irqdispatch() might be directly strapped via VI- or EIC-mode, and plat_irq_dispatch() is not used completely, hmm. --- For example, the patch like this still works for PowerTV? I'd like to make sure whether PowerTV still require irq_ffs() or not, as it prevents irq_ffs() consolidation patch from being submitted. But no need to hurry, I can hold the patch for weeks, for months. Shinya diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c index 529c44a..2a8fd99 100644 --- a/arch/mips/powertv/asic/asic_int.c +++ b/arch/mips/powertv/asic/asic_int.c @@ -33,7 +33,6 @@ #include #include -#include #include #include @@ -68,40 +67,15 @@ static void asic_irqdispatch(void) do_IRQ(irq); } -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ - return fls(pending) - 1 + CAUSEB_IP; -} - /* * TODO: check how it works under EIC mode. */ asmlinkage void plat_irq_dispatch(void) { - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; int irq; - irq = irq_ffs(pending); - - if (irq == CAUSEF_IP3) - asic_irqdispatch(); - else if (irq >= 0) + irq = get_int(); + if (irq >= 0) do_IRQ(irq); else spurious_interrupt(); From randolf.bruno@googlemail.com Sun Jul 11 17:40:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Jul 2010 17:40:44 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:58024 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492163Ab0GKPkk (ORCPT ); Sun, 11 Jul 2010 17:40:40 +0200 Received: by pvf33 with SMTP id 33so1742568pvf.36 for ; Sun, 11 Jul 2010 08:40:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:subject:to:from:cc:date :message-id:user-agent:mime-version:content-type :content-transfer-encoding; bh=UcQOXypIkXuBJum6mqGxdkXnXXh8WXbs7xLGRIi3ZKM=; b=AnXyL9Fy5JYb/LOGGAru8+HvzGWgAZrb7RZFsC4ducFhEWvqBcFAFYgWTZLQ78BtNQ kAJ2IwGoUcYy+HoNkivVwiyOzQF2ICXpQHJng2YBGUePTPMsUhJiXwAndCXHdvnFjmue 02KVCQERXkFIfCNPriR4PbAGhvt3H/Kzr+n94= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=subject:to:from:cc:date:message-id:user-agent:mime-version :content-type:content-transfer-encoding; b=XEIILNeGD1AcyATcnQgMhUAcR9OyOlkKP9zuG0O/Tdc0StpCRzMaQpZbzuKFnSEEy9 An/x2MFRvOv8W3YsABEgejtxfxa2+B50vYQxBvGFSj+hjHNxLL7d26lf6Sjjs9R2Wa/E gsABV0+vueJOY63wzAdH6NH+1yVN7t3wGKZ7k= Received: by 10.142.127.9 with SMTP id z9mr14720293wfc.188.1278862833842; Sun, 11 Jul 2010 08:40:33 -0700 (PDT) Received: from [127.0.1.1] (zaq3d2e62b2.zaq.ne.jp [61.46.98.178]) by mx.google.com with ESMTPS id f20sm3393148rvb.8.2010.07.11.08.40.31 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 11 Jul 2010 08:40:32 -0700 (PDT) Subject: [PATCH 1/2] MIPS: MTX-1: fix PCI on the MeshCube and related boards To: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org From: Bruno Randolf Cc: florian@openwrt.org Date: Mon, 12 Jul 2010 00:40:28 +0900 Message-ID: <20100711154028.29863.74414.stgit@void> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27365 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: randolf.bruno@googlemail.com Precedence: bulk X-list: linux-mips This patch fixes a regression introduced by commit "MIPS: Alchemy: MTX-1: Use linux gpio api." (bb706b28bbd647c2fd7f22d6bf03a18b9552be05) which broke PCI bus operation. The problem is caused by alchemy_gpio2_enable() which resets the GPIO2 block. Two PCI signals (PCI_SERR and PCI_RST) are connected to GPIO2 and they obviously do not to like the reset. Since GPIO2 is correctly initialized by the boot monitor (YAMON) it is not necessary to call this function, so just remove it. Also replace gpio_set_value() with alchemy_gpio_set_value() to avoid problems in case gpiolib gets initialized after PCI. And since alchemy gpio_set_value() calls au_sync() we don't have to au_sync() again later. Cc: stable@kernel.org Signed-off-by: Bruno Randolf --- arch/mips/alchemy/mtx-1/board_setup.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index a9f0336..52d883d 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -67,8 +67,6 @@ static void mtx1_power_off(void) void __init board_setup(void) { - alchemy_gpio2_enable(); - #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) /* Enable USB power switch */ alchemy_gpio_direction_output(204, 0); @@ -117,11 +115,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert) if (assert && devsel != 0) /* Suppress signal to Cardbus */ - gpio_set_value(1, 0); /* set EXT_IO3 OFF */ + alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ else - gpio_set_value(1, 1); /* set EXT_IO3 ON */ + alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ - au_sync_udelay(1); + udelay(1); return 1; } From randolf.bruno@googlemail.com Sun Jul 11 17:41:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Jul 2010 17:41:09 +0200 (CEST) Received: from mail-px0-f177.google.com ([209.85.212.177]:59773 "EHLO mail-px0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491890Ab0GKPku (ORCPT ); Sun, 11 Jul 2010 17:40:50 +0200 Received: by pxi13 with SMTP id 13so1749268pxi.36 for ; Sun, 11 Jul 2010 08:40:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:subject:to:from:cc:date :message-id:in-reply-to:references:user-agent:mime-version :content-type:content-transfer-encoding; bh=63HqvPUXp11T8uBoZm8EFxXdUXoNXSIXnbTNUHyLuKw=; b=mKJgNMw7WwUVakE6orD63Veallnd9AHcRbIreD+lVkOEkhATa42Vj2MXYS56YyuHOn NeK2CXMBFqU5pAhLFxF1EFBDo69PsFQViqa+kgQ1urfsuYAZGkDTv9gPIFUaR5PmWk4j 9LHVlDu9nn+ypHDxhjLy93IvrpTgM2fvTS1+Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; b=lYEQ7onxft/sXo9kx4SIdLCvulFyNXdJ1kgzfnxTaBJ+neBRhvv01Tcp0RbcYjP/UX YEpfvTVuhXjJwLFaB4ts/r7If956xgZryrZZunRhTnCWz0jHzTW1eBbZOFjQ5UDsJLQi Sr24og7lbJSHfL7LkOCkANPOfDEQgFB6fVbG0= Received: by 10.142.127.9 with SMTP id z9mr14963588wfc.184.1278862842740; Sun, 11 Jul 2010 08:40:42 -0700 (PDT) Received: from [127.0.1.1] (zaq3d2e62b2.zaq.ne.jp [61.46.98.178]) by mx.google.com with ESMTPS id l29sm3393232rvb.7.2010.07.11.08.40.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 11 Jul 2010 08:40:41 -0700 (PDT) Subject: [PATCH 2/2] MIPS: MTX-1: cleanup and comments To: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org From: Bruno Randolf Cc: florian@openwrt.org Date: Mon, 12 Jul 2010 00:40:38 +0900 Message-ID: <20100711154038.29863.23111.stgit@void> In-Reply-To: <20100711154028.29863.74414.stgit@void> References: <20100711154028.29863.74414.stgit@void> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27366 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: randolf.bruno@googlemail.com Precedence: bulk X-list: linux-mips Add some comments about mtx1_pci_idsel() and remove a dead block of old code. Signed-off-by: Bruno Randolf --- arch/mips/alchemy/mtx-1/board_setup.c | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 52d883d..3cf2fa2 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -105,14 +105,10 @@ void __init board_setup(void) int mtx1_pci_idsel(unsigned int devsel, int assert) { -#define MTX_IDSEL_ONLY_0_AND_3 0 -#if MTX_IDSEL_ONLY_0_AND_3 - if (devsel != 0 && devsel != 3) { - printk(KERN_ERR "*** not 0 or 3\n"); - return 0; - } -#endif - + /* This function is only necessary to support a proprietary Cardbus + * adapter on the mtx-1 "singleboard" variant. It triggers a custom + * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. + */ if (assert && devsel != 0) /* Suppress signal to Cardbus */ alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ From f.fainelli@gmail.com Sun Jul 11 19:10:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Jul 2010 19:10:09 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:55508 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491135Ab0GKRKG convert rfc822-to-8bit (ORCPT ); Sun, 11 Jul 2010 19:10:06 +0200 Received: by wyf28 with SMTP id 28so2188447wyf.36 for ; Sun, 11 Jul 2010 10:10:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:reply-to:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=sbvh4uut5qdh0nuuG+tboh59vYQeK7UlSKwb56nGdMY=; b=bUZyg2ggBh8bheIN48+hfiKFjgSs/s0FJgf/azAoVj9isPDOZW/MNOReJ9bnq7O5cG n3xounQU37+8FQ7+mZLgd34LPF5rw4hbMtx0dWOlDvo0ZuxrkBprOdczTU2906Kfwnt+ Ldfx3cyX5LZwK+ko3ZFbpAC8vX8X0x0gfQvvA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:reply-to:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=QwOGdksN/Yt0vDrNKW5es8WbJqhaNfRD8BRuc23xu//Fb9gRhoI7km7S04/iAZHhaW BGcZcGdv+D8TtHkiqj0z7SR7mvZMcGlQCLsf/0bRqPt8xrtHQTXURALcCRbeC+4i5IIx IFrSOxYIgnD0ia1gQq9Txrxc3A8IrgLicPI0I= Received: by 10.216.29.1 with SMTP id h1mr7493530wea.20.1278868199931; Sun, 11 Jul 2010 10:09:59 -0700 (PDT) Received: from lenovo.localnet (147.199.66-86.rev.gaoland.net [86.66.199.147]) by mx.google.com with ESMTPS id m73sm1209119wej.36.2010.07.11.10.09.58 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 11 Jul 2010 10:09:59 -0700 (PDT) From: Florian Fainelli Reply-To: Florian Fainelli To: Bruno Randolf Subject: Re: [PATCH 1/2] MIPS: MTX-1: fix PCI on the MeshCube and related boards Date: Sun, 11 Jul 2010 19:10:20 +0200 User-Agent: KMail/1.13.3 (Linux/2.6.34-1-amd64; KDE/4.4.4; x86_64; ; ) Cc: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org References: <20100711154028.29863.74414.stgit@void> In-Reply-To: <20100711154028.29863.74414.stgit@void> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Message-Id: <201007111910.22303.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27367 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Sunday 11 July 2010 17:40:28, Bruno Randolf a écrit : > This patch fixes a regression introduced by commit "MIPS: Alchemy: MTX-1: > Use linux gpio api." (bb706b28bbd647c2fd7f22d6bf03a18b9552be05) which > broke PCI bus operation. The problem is caused by alchemy_gpio2_enable() > which resets the GPIO2 block. Two PCI signals (PCI_SERR and PCI_RST) are > connected to GPIO2 and they obviously do not to like the reset. Since > GPIO2 is correctly initialized by the boot monitor (YAMON) it is not > necessary to call this function, so just remove it. > > Also replace gpio_set_value() with alchemy_gpio_set_value() to avoid > problems in case gpiolib gets initialized after PCI. And since alchemy > gpio_set_value() calls au_sync() we don't have to au_sync() again later. > > Cc: stable@kernel.org > Signed-off-by: Bruno Randolf Tested-by: Florian Fainelli > --- > arch/mips/alchemy/mtx-1/board_setup.c | 8 +++----- > 1 files changed, 3 insertions(+), 5 deletions(-) > > diff --git a/arch/mips/alchemy/mtx-1/board_setup.c > b/arch/mips/alchemy/mtx-1/board_setup.c index a9f0336..52d883d 100644 > --- a/arch/mips/alchemy/mtx-1/board_setup.c > +++ b/arch/mips/alchemy/mtx-1/board_setup.c > @@ -67,8 +67,6 @@ static void mtx1_power_off(void) > > void __init board_setup(void) > { > - alchemy_gpio2_enable(); > - > #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) > /* Enable USB power switch */ > alchemy_gpio_direction_output(204, 0); > @@ -117,11 +115,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert) > > if (assert && devsel != 0) > /* Suppress signal to Cardbus */ > - gpio_set_value(1, 0); /* set EXT_IO3 OFF */ > + alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ > else > - gpio_set_value(1, 1); /* set EXT_IO3 ON */ > + alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ > > - au_sync_udelay(1); > + udelay(1); > return 1; > } From f.fainelli@gmail.com Sun Jul 11 19:10:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Jul 2010 19:10:49 +0200 (CEST) Received: from mail-ww0-f41.google.com ([74.125.82.41]:53056 "EHLO mail-ww0-f41.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492159Ab0GKRKp convert rfc822-to-8bit (ORCPT ); Sun, 11 Jul 2010 19:10:45 +0200 Received: by wwe15 with SMTP id 15so2413974wwe.0 for ; Sun, 11 Jul 2010 10:10:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:reply-to:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=Wcdtoqa6H9UmmcGKKgbPUhyDEFAcMAZEiRX7AHEFshs=; b=qnFXwx7KSqP/u2oMSlr9baof/o9Te7xZEKsFKfbCU/DJlFKP9G7oxtEBUc+joMZrsX M5eGtn+Y+7Rv/2N9qKvjUty9W0NyFmsyCuGelBpVa76wrjYAUWhzakuYgHazbk6n1uDp o3yleFXLPjC9CTbgxlXxm4DNPq/cx9xcS917c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:reply-to:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=o8qNe566WA5pKXeVhDAtXNigLahypb5iz3O3FP2ubfM94W+AXDTiBgv9DpJFJ2jJlS ijZNFda3whvlpEaRRylm1g8vy5Zdhv0t5xpltsU9ORPXw+HfbV+0aKoVng1MlxUXkxpS nfCHpfIe1idzWNeOA9PvHd7gZHthXKFiS0tzc= Received: by 10.216.236.146 with SMTP id w18mr2324377weq.19.1278868238874; Sun, 11 Jul 2010 10:10:38 -0700 (PDT) Received: from lenovo.localnet (147.199.66-86.rev.gaoland.net [86.66.199.147]) by mx.google.com with ESMTPS id o11sm1207862wej.45.2010.07.11.10.10.37 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 11 Jul 2010 10:10:38 -0700 (PDT) From: Florian Fainelli Reply-To: Florian Fainelli To: Bruno Randolf Subject: Re: [PATCH 2/2] MIPS: MTX-1: cleanup and comments Date: Sun, 11 Jul 2010 19:11:01 +0200 User-Agent: KMail/1.13.3 (Linux/2.6.34-1-amd64; KDE/4.4.4; x86_64; ; ) Cc: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org References: <20100711154028.29863.74414.stgit@void> <20100711154038.29863.23111.stgit@void> In-Reply-To: <20100711154038.29863.23111.stgit@void> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Message-Id: <201007111911.02200.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27368 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Sunday 11 July 2010 17:40:38, Bruno Randolf a écrit : > Add some comments about mtx1_pci_idsel() and remove a dead block of old > code. > > Signed-off-by: Bruno Randolf Acked-by: Florian Fainelli > --- > arch/mips/alchemy/mtx-1/board_setup.c | 12 ++++-------- > 1 files changed, 4 insertions(+), 8 deletions(-) > > diff --git a/arch/mips/alchemy/mtx-1/board_setup.c > b/arch/mips/alchemy/mtx-1/board_setup.c index 52d883d..3cf2fa2 100644 > --- a/arch/mips/alchemy/mtx-1/board_setup.c > +++ b/arch/mips/alchemy/mtx-1/board_setup.c > @@ -105,14 +105,10 @@ void __init board_setup(void) > int > mtx1_pci_idsel(unsigned int devsel, int assert) > { > -#define MTX_IDSEL_ONLY_0_AND_3 0 > -#if MTX_IDSEL_ONLY_0_AND_3 > - if (devsel != 0 && devsel != 3) { > - printk(KERN_ERR "*** not 0 or 3\n"); > - return 0; > - } > -#endif > - > + /* This function is only necessary to support a proprietary Cardbus > + * adapter on the mtx-1 "singleboard" variant. It triggers a custom > + * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. > + */ > if (assert && devsel != 0) > /* Suppress signal to Cardbus */ > alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ From ralf@linux-mips.org Mon Jul 12 00:26:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 00:26:04 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40775 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492199Ab0GKW0A (ORCPT ); Mon, 12 Jul 2010 00:26:00 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o6BMPwIs001352; Sun, 11 Jul 2010 23:25:58 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o6BMPv0c001350; Sun, 11 Jul 2010 23:25:57 +0100 Date: Sun, 11 Jul 2010 23:25:57 +0100 From: Ralf Baechle To: Bruno Randolf Cc: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, florian@openwrt.org Subject: Re: [PATCH 1/2] MIPS: MTX-1: fix PCI on the MeshCube and related boards Message-ID: <20100711222557.GA1157@linux-mips.org> References: <20100711154028.29863.74414.stgit@void> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100711154028.29863.74414.stgit@void> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27369 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jul 12, 2010 at 12:40:28AM +0900, Bruno Randolf wrote: > Cc: stable@kernel.org Thanks, applied - but stable wasn't on the Cc: list! Ralf From ralf@linux-mips.org Mon Jul 12 00:34:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 00:35:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35920 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492069Ab0GKWe6 (ORCPT ); Mon, 12 Jul 2010 00:34:58 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o6BMYtnR007421; Sun, 11 Jul 2010 23:34:55 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o6BMYtUo007419; Sun, 11 Jul 2010 23:34:55 +0100 Date: Sun, 11 Jul 2010 23:34:55 +0100 From: Ralf Baechle To: Bruno Randolf Cc: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, florian@openwrt.org Subject: Re: [PATCH 2/2] MIPS: MTX-1: cleanup and comments Message-ID: <20100711223455.GB1157@linux-mips.org> References: <20100711154028.29863.74414.stgit@void> <20100711154038.29863.23111.stgit@void> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100711154038.29863.23111.stgit@void> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27370 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.36. Ralf From ralf@linux-mips.org Mon Jul 12 01:08:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 01:09:00 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52672 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492058Ab0GKXIw (ORCPT ); Mon, 12 Jul 2010 01:08:52 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.4/8.14.3) with ESMTP id o6BN8pLX008235; Mon, 12 Jul 2010 00:08:52 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.4/8.14.4/Submit) id o6BN8p7v008233; Mon, 12 Jul 2010 00:08:51 +0100 Date: Mon, 12 Jul 2010 00:08:51 +0100 From: Ralf Baechle To: Chris Rhodin Cc: linux-mips@linux-mips.org Subject: Re: IP22 Debian Install Message-ID: <20100711230851.GA8181@linux-mips.org> References: <4C36D31A.5000500@notav8.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C36D31A.5000500@notav8.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27371 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jul 09, 2010 at 12:43:22AM -0700, Chris Rhodin wrote: > tip22: IP22 Linux tftpboot loader 0.3.8.6 > Loading program segment 2 at 0x88002000, size = 0x218000 > Zeroing memory at 0x8821a000, size = 0x365b0 > Starting kernel; entry point = 0x881e0040 > Copied initrd from 0x88aab190 to 0x88251000 (0x1d5ce2 bytes) > > Exception: > Status register: 0x30044803 > Cause register: 0x30008010 > Exception PC: 0x88124c74, Exception RA: 0x881f61b0 > Read address error exception, bad address: 0x2a > Local I/O interrupt register 1: 0x80 > Local I/O interrupt register 2: 0xc8 > Saved user regs in hex (&gpda 0xa8740e48, &_regs 0xa8741048): > arg: a8740000 881dffe0 882505ac 88000000 > tmp: a8740000 2 887fe378 887fe4cc 0 8 887fe7d4 881e0040 > sve: a8740000 3 400000 8000000 16 3f80 0 c000000 > t8 a8740000 t9 fffff7ff at bfefff7f v0 ffbff5ef v1 fff71fbf k1 500 > gp a8740000 fp fefbfeff sp fffdffff ra feeffff7 > > PANIC: Unexpected exception > > It looks like the kernel is loading at 0x88002000 which is more than > 128MB away from the beginning of kseg0. Yes and that's correct. Memory doesn't always start at address zero! Ralf From randolf.bruno@googlemail.com Mon Jul 12 02:05:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 02:05:17 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:49164 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492187Ab0GLAFK (ORCPT ); Mon, 12 Jul 2010 02:05:10 +0200 Received: by pwj7 with SMTP id 7so1837739pwj.36 for ; Sun, 11 Jul 2010 17:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:subject:to:from:cc:date :message-id:user-agent:mime-version:content-type :content-transfer-encoding; bh=k+61SQGnT+K3KBEdPAwmB4ftr4UCfyO2uLhoVcq4ygA=; b=tftE2Rrk6bKNJFBZOkSE0JQ+BoZSsKJH/qZhk1VIAx8hcbpDEbdF8f0fCiZYrGIVEu TyYT+6CC2MaS1GRZrQsVKWBK3jIlsosgcSqBq+XcWiDayi6vJBxop9zaO0loyVAcVO8w junHuf0g/dgw7dcNjzudTNmErGA/5RY8GHT7w= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=subject:to:from:cc:date:message-id:user-agent:mime-version :content-type:content-transfer-encoding; b=xXdsnUGD6/BAsDYQj8I+HvjBaJVsTYFaVZFK5pyqqnJmKd+IPjKty/rOnpFpYpddft uomaEigAMRTGAKkkFSh86linZYCNsflrHEkgxSEBc/gwJmQVFNbnRopzF8mZD+URGS7x z/7y/y+4EHFaXm+CBfVSlC4iaMDMLXcK76pDs= Received: by 10.114.159.14 with SMTP id h14mr15094245wae.113.1278893102790; Sun, 11 Jul 2010 17:05:02 -0700 (PDT) Received: from [127.0.1.1] (zaq3d2e62b2.zaq.ne.jp [61.46.98.178]) by mx.google.com with ESMTPS id d38sm58416358wam.8.2010.07.11.17.05.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 11 Jul 2010 17:05:01 -0700 (PDT) Subject: [PATCH] MIPS: MTX-1: fix PCI on the MeshCube and related boards To: linux-mips@linux-mips.org, manuel.lauss@googlemail.com, ralf@linux-mips.org From: Bruno Randolf Cc: stable@kernel.org Date: Mon, 12 Jul 2010 09:04:58 +0900 Message-ID: <20100712000425.31611.49721.stgit@void> User-Agent: StGit/0.15 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27372 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: randolf.bruno@googlemail.com Precedence: bulk X-list: linux-mips This patch fixes a regression introduced by commit "MIPS: Alchemy: MTX-1: Use linux gpio api." (bb706b28bbd647c2fd7f22d6bf03a18b9552be05) which broke PCI bus operation. The problem is caused by alchemy_gpio2_enable() which resets the GPIO2 block. Two PCI signals (PCI_SERR and PCI_RST) are connected to GPIO2 and they obviously do not to like the reset. Since GPIO2 is correctly initialized by the boot monitor (YAMON) it is not necessary to call this function, so just remove it. Also replace gpio_set_value() with alchemy_gpio_set_value() to avoid problems in case gpiolib gets initialized after PCI. And since alchemy gpio_set_value() calls au_sync() we don't have to au_sync() again later. Cc: stable@kernel.org Signed-off-by: Bruno Randolf --- sending again with stable on cc: --- arch/mips/alchemy/mtx-1/board_setup.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index a9f0336..52d883d 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -67,8 +67,6 @@ static void mtx1_power_off(void) void __init board_setup(void) { - alchemy_gpio2_enable(); - #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) /* Enable USB power switch */ alchemy_gpio_direction_output(204, 0); @@ -117,11 +115,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert) if (assert && devsel != 0) /* Suppress signal to Cardbus */ - gpio_set_value(1, 0); /* set EXT_IO3 OFF */ + alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ else - gpio_set_value(1, 1); /* set EXT_IO3 ON */ + alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */ - au_sync_udelay(1); + udelay(1); return 1; } From lars@metafoo.de Mon Jul 12 03:48:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 03:48:38 +0200 (CEST) Received: from smtp-out-215.synserver.de ([212.40.180.215]:1075 "HELO smtp-out-213.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1492107Ab0GLBsc (ORCPT ); Mon, 12 Jul 2010 03:48:32 +0200 Received: (qmail 22127 invoked by uid 0); 12 Jul 2010 01:48:27 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 22083 Received: from port-3658.pppoe.wtnet.de (HELO localhost.localdomain) [84.46.14.88] by 217.119.54.81 with SMTP; 12 Jul 2010 01:48:26 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen , Samuel Ortiz Subject: [PATCH v3] MFD: Add JZ4740 ADC driver Date: Mon, 12 Jul 2010 03:48:08 +0200 Message-Id: <1278899288-14921-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1276924111-11158-23-git-send-email-lars@metafoo.de> References: <1276924111-11158-23-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27373 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds a MFD driver for the JZ4740 ADC unit. The driver is used to demultiplex IRQs and synchronize access to shared registers between the battery, hwmon and (future) touchscreen driver. Signed-off-by: Lars-Peter Clausen Cc: Samuel Ortiz --- Changes since v2 - Use atmic_t for clock ref-counting. - Add a comment why ref-counting is done in the driver and not in the clock framework. - Return more appropriate error codes when resources are missing. - Return result of mfd_add_devices at the end of the drivers probe function. --- drivers/mfd/Kconfig | 8 + drivers/mfd/Makefile | 1 + drivers/mfd/jz4740-adc.c | 384 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/jz4740-adc.h | 32 ++++ 4 files changed, 425 insertions(+), 0 deletions(-) create mode 100644 drivers/mfd/jz4740-adc.c create mode 100644 include/linux/jz4740-adc.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3f65dd0..2cde665 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -524,6 +524,14 @@ config MFD_JANZ_CMODIO host many different types of MODULbus daughterboards, including CAN and GPIO controllers. +config MFD_JZ4740_ADC + tristate "Support for the JZ4740 SoC ADC core" + select MFD_CORE + depends on MACH_JZ4740 + help + Say yes here if you want support for the ADC unit in the JZ4740 SoC. + This driver is necessary for jz4740-battery and jz4740-hwmon driver. + endif # MFD_SUPPORT menu "Multimedia Capabilities Port drivers" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 130c5f0..8a751dd 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -73,3 +73,4 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o obj-$(CONFIG_LPC_SCH) += lpc_sch.o obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o +obj-$(CONFIG_MFD_JZ4740_ADC) += jz4740-adc.o diff --git a/drivers/mfd/jz4740-adc.c b/drivers/mfd/jz4740-adc.c new file mode 100644 index 0000000..7a844ae --- /dev/null +++ b/drivers/mfd/jz4740-adc.c @@ -0,0 +1,384 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 SoC ADC driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * This driver synchronizes access to the JZ4740 ADC core between the + * JZ4740 battery and hwmon drivers. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + + +#define JZ_REG_ADC_ENABLE 0x00 +#define JZ_REG_ADC_CFG 0x04 +#define JZ_REG_ADC_CTRL 0x08 +#define JZ_REG_ADC_STATUS 0x0c + +#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10 +#define JZ_REG_ADC_BATTERY_BASE 0x1c +#define JZ_REG_ADC_HWMON_BASE 0x20 + +#define JZ_ADC_ENABLE_TOUCH BIT(2) +#define JZ_ADC_ENABLE_BATTERY BIT(1) +#define JZ_ADC_ENABLE_ADCIN BIT(0) + +enum { + JZ_ADC_IRQ_ADCIN = 0, + JZ_ADC_IRQ_BATTERY, + JZ_ADC_IRQ_TOUCH, + JZ_ADC_IRQ_PENUP, + JZ_ADC_IRQ_PENDOWN, +}; + +struct jz4740_adc { + struct resource *mem; + void __iomem *base; + + int irq; + int irq_base; + + struct clk *clk; + atomic_t clk_ref; + + spinlock_t lock; +}; + +static inline void jz4740_adc_irq_set_masked(struct jz4740_adc *adc, int irq, + bool masked) +{ + unsigned long flags; + uint8_t val; + + irq -= adc->irq_base; + + spin_lock_irqsave(&adc->lock, flags); + + val = readb(adc->base + JZ_REG_ADC_CTRL); + if (masked) + val |= BIT(irq); + else + val &= ~BIT(irq); + writeb(val, adc->base + JZ_REG_ADC_CTRL); + + spin_unlock_irqrestore(&adc->lock, flags); +} + +static void jz4740_adc_irq_mask(unsigned int irq) +{ + struct jz4740_adc *adc = get_irq_chip_data(irq); + jz4740_adc_irq_set_masked(adc, irq, true); +} + +static void jz4740_adc_irq_unmask(unsigned int irq) +{ + struct jz4740_adc *adc = get_irq_chip_data(irq); + jz4740_adc_irq_set_masked(adc, irq, false); +} + +static void jz4740_adc_irq_ack(unsigned int irq) +{ + struct jz4740_adc *adc = get_irq_chip_data(irq); + + irq -= adc->irq_base; + writeb(BIT(irq), adc->base + JZ_REG_ADC_STATUS); +} + +static struct irq_chip jz4740_adc_irq_chip = { + .name = "jz4740-adc", + .mask = jz4740_adc_irq_mask, + .unmask = jz4740_adc_irq_unmask, + .ack = jz4740_adc_irq_ack, +}; + +static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + struct jz4740_adc *adc = get_irq_desc_data(desc); + uint8_t status; + unsigned int i; + + status = readb(adc->base + JZ_REG_ADC_STATUS); + + for (i = 0; i < 5; ++i) { + if (status & BIT(i)) + generic_handle_irq(adc->irq_base + i); + } +} + + +/* Refcounting for the ADC clock is done in here instead of in the clock + * framework, because it is the only clock which is shared between multiple + * devices and thus is the only clock which needs refcounting */ +static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) +{ + if (atomic_inc_return(&adc->clk_ref) == 1) + clk_enable(adc->clk); +} + +static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc) +{ + if (atomic_dec_return(&adc->clk_ref) == 0) + clk_disable(adc->clk); +} + +static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine, + bool enabled) +{ + unsigned long flags; + uint8_t val; + + spin_lock_irqsave(&adc->lock, flags); + + val = readb(adc->base + JZ_REG_ADC_ENABLE); + if (enabled) + val |= BIT(engine); + else + val &= BIT(engine); + writeb(val, adc->base + JZ_REG_ADC_ENABLE); + + spin_unlock_irqrestore(&adc->lock, flags); +} + +static int jz4740_adc_cell_enable(struct platform_device *pdev) +{ + struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); + + jz4740_adc_clk_enable(adc); + jz4740_adc_set_enabled(adc, pdev->id, true); + + return 0; +} + +static int jz4740_adc_cell_disable(struct platform_device *pdev) +{ + struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); + + jz4740_adc_set_enabled(adc, pdev->id, false); + jz4740_adc_clk_disable(adc); + + return 0; +} + +int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val) +{ + struct jz4740_adc *adc = dev_get_drvdata(dev); + unsigned long flags; + uint32_t cfg; + + if (!adc) + return -ENODEV; + + spin_lock_irqsave(&adc->lock, flags); + + cfg = readl(adc->base + JZ_REG_ADC_CFG); + + cfg &= ~mask; + cfg |= val; + + writel(cfg, adc->base + JZ_REG_ADC_CFG); + + spin_unlock_irqrestore(&adc->lock, flags); + + return 0; +} +EXPORT_SYMBOL_GPL(jz4740_adc_set_config); + +static struct resource jz4740_hwmon_resources[] = { + { + .start = JZ_ADC_IRQ_ADCIN, + .flags = IORESOURCE_IRQ, + }, + { + .start = JZ_REG_ADC_HWMON_BASE, + .end = JZ_REG_ADC_HWMON_BASE + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource jz4740_battery_resources[] = { + { + .start = JZ_ADC_IRQ_BATTERY, + .flags = IORESOURCE_IRQ, + }, + { + .start = JZ_REG_ADC_BATTERY_BASE, + .end = JZ_REG_ADC_BATTERY_BASE + 3, + .flags = IORESOURCE_MEM, + }, +}; + +const struct mfd_cell jz4740_adc_cells[] = { + { + .id = 0, + .name = "jz4740-hwmon", + .num_resources = ARRAY_SIZE(jz4740_hwmon_resources), + .resources = jz4740_hwmon_resources, + .platform_data = (void *)&jz4740_adc_cells[0], + .data_size = sizeof(struct mfd_cell), + + .enable = jz4740_adc_cell_enable, + .disable = jz4740_adc_cell_disable, + }, + { + .id = 1, + .name = "jz4740-battery", + .num_resources = ARRAY_SIZE(jz4740_battery_resources), + .resources = jz4740_battery_resources, + .platform_data = (void *)&jz4740_adc_cells[1], + .data_size = sizeof(struct mfd_cell), + + .enable = jz4740_adc_cell_enable, + .disable = jz4740_adc_cell_disable, + }, +}; + +static int __devinit jz4740_adc_probe(struct platform_device *pdev) +{ + int ret; + struct jz4740_adc *adc; + struct resource *mem_base; + int irq; + + adc = kmalloc(sizeof(*adc), GFP_KERNEL); + + adc->irq = platform_get_irq(pdev, 0); + if (adc->irq < 0) { + ret = adc->irq; + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); + goto err_free; + } + + adc->irq_base = platform_get_irq(pdev, 1); + if (adc->irq_base < 0) { + ret = adc->irq_base; + dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret); + goto err_free; + } + + mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem_base) { + ret = -ENOENT; + dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); + goto err_free; + } + + /* Only request the shared registers for the MFD driver */ + adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, + pdev->name); + if (!adc->mem) { + ret = -EBUSY; + dev_err(&pdev->dev, "Failed to request mmio memory region\n"); + goto err_free; + } + + adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); + if (!adc->base) { + ret = -EBUSY; + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); + goto err_release_mem_region; + } + + adc->clk = clk_get(&pdev->dev, "adc"); + if (IS_ERR(adc->clk)) { + ret = PTR_ERR(adc->clk); + dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); + goto err_iounmap; + } + + spin_lock_init(&adc->lock); + atomic_set(&adc->clk_ref, 0); + + platform_set_drvdata(pdev, adc); + + for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) { + set_irq_chip_data(irq, adc); + set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip, + handle_level_irq); + } + + set_irq_data(adc->irq, adc); + set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux); + + writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); + writeb(0xff, adc->base + JZ_REG_ADC_CTRL); + + return mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, + ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base); + +err_iounmap: + platform_set_drvdata(pdev, NULL); + iounmap(adc->base); +err_release_mem_region: + release_mem_region(adc->mem->start, resource_size(adc->mem)); +err_free: + kfree(adc); + + return ret; +} + +static int __devexit jz4740_adc_remove(struct platform_device *pdev) +{ + struct jz4740_adc *adc = platform_get_drvdata(pdev); + + mfd_remove_devices(&pdev->dev); + + set_irq_data(adc->irq, NULL); + set_irq_chained_handler(adc->irq, NULL); + + iounmap(adc->base); + release_mem_region(adc->mem->start, resource_size(adc->mem)); + + clk_put(adc->clk); + + platform_set_drvdata(pdev, NULL); + + kfree(adc); + + return 0; +} + +struct platform_driver jz4740_adc_driver = { + .probe = jz4740_adc_probe, + .remove = __devexit_p(jz4740_adc_remove), + .driver = { + .name = "jz4740-adc", + .owner = THIS_MODULE, + }, +}; + +static int __init jz4740_adc_init(void) +{ + return platform_driver_register(&jz4740_adc_driver); +} +module_init(jz4740_adc_init); + +static void __exit jz4740_adc_exit(void) +{ + platform_driver_unregister(&jz4740_adc_driver); +} +module_exit(jz4740_adc_exit); + +MODULE_DESCRIPTION("JZ4740 SoC ADC driver"); +MODULE_AUTHOR("Lars-Peter Clausen "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:jz4740-adc"); diff --git a/include/linux/jz4740-adc.h b/include/linux/jz4740-adc.h new file mode 100644 index 0000000..9053f95 --- /dev/null +++ b/include/linux/jz4740-adc.h @@ -0,0 +1,32 @@ + +#ifndef __LINUX_JZ4740_ADC +#define __LINUX_JZ4740_ADC + +#include + +/* + * jz4740_adc_set_config - Configure a JZ4740 adc device + * @dev: Pointer to a jz4740-adc device + * @mask: Mask for the config value to be set + * @val: Value to be set + * + * This function can be used by the JZ4740 ADC mfd cells to configure their + * options in the shared config register. +*/ +int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val); + +#define JZ_ADC_CONFIG_SPZZ BIT(31) +#define JZ_ADC_CONFIG_EX_IN BIT(30) +#define JZ_ADC_CONFIG_DNUM_MASK (0x7 << 16) +#define JZ_ADC_CONFIG_DMA_ENABLE BIT(15) +#define JZ_ADC_CONFIG_XYZ_MASK (0x2 << 13) +#define JZ_ADC_CONFIG_SAMPLE_NUM_MASK (0x7 << 10) +#define JZ_ADC_CONFIG_CLKDIV_MASK (0xf << 5) +#define JZ_ADC_CONFIG_BAT_MB BIT(4) + +#define JZ_ADC_CONFIG_DNUM(dnum) ((dnum) << 16) +#define JZ_ADC_CONFIG_XYZ_OFFSET(dnum) ((xyz) << 13) +#define JZ_ADC_CONFIG_SAMPLE_NUM(x) ((x) << 10) +#define JZ_ADC_CONFIG_CLKDIV(div) ((div) << 5) + +#endif -- 1.5.6.5 From skuribay@pobox.com Mon Jul 12 17:37:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 17:37:56 +0200 (CEST) Received: from b-pb-sasl-quonix.pobox.com ([208.72.237.35]:63156 "EHLO sasl.smtp.pobox.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491973Ab0GLPhv (ORCPT ); Mon, 12 Jul 2010 17:37:51 +0200 Received: from sasl.smtp.pobox.com (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 6AA70B6D57; Mon, 12 Jul 2010 11:37:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=pobox.com; h=message-id :date:from:mime-version:to:cc:subject:content-type :content-transfer-encoding; s=sasl; bh=XtTp5PFhirzBhJTFmpLVkDdkm Js=; b=CVa9y5AUgAaGy694EAfnnGoYeLE6oedYU1PvLj+R7mZQ9qs1Jkp5m/JWA Ap15xWlcOSI/wAHubpVP+s76e4iOnTUs6V3267aoGD5KY/EwhIi9oAsGLxhZBWLK Uy9g7C1/e4Mh8oPgp04jy1KOFg5rfbiBIUf5aoAaA2P/fMwui0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=pobox.com; h=message-id:date :from:mime-version:to:cc:subject:content-type :content-transfer-encoding; q=dns; s=sasl; b=mukK7TwpAT3952G/L97 /7eq3OGZ18ENab2yq7VmJINxYhZQTd5LN8oEDZzu9nkI8sLpVzyaMs/UaxykpkVY 0ZTDATpntChY8oiTJnX3LgF9JYF42KjG0uD9iVGarVgbd9npYnXEjfkSxUu3nlti ncsLmsEZOYKHWtdPNFxCsMPU= Received: from b-pb-sasl-quonix. (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 3B63AB6D55; Mon, 12 Jul 2010 11:37:33 -0400 (EDT) Received: from [192.168.11.3] (unknown [114.162.174.29]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by b-sasl-quonix.pobox.com (Postfix) with ESMTPSA id D2CFCB6D52; Mon, 12 Jul 2010 11:37:28 -0400 (EDT) Message-ID: <4C3B36B3.6010800@pobox.com> Date: Tue, 13 Jul 2010 00:37:23 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.10) Gecko/20100527 Thunderbird/3.0.5 MIME-Version: 1.0 To: David VomLehn , ralf@linux-mips.org, macro@linux-mips.org CC: linux-mips@linux-mips.org Subject: [PATCH 0/2] MIPS: cpu-feature-overrides patches Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Pobox-Relay-ID: 63886CA4-8DCB-11DF-81BE-DA91016DD5F0-47602734!b-pb-sasl-quonix.pobox.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27374 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@pobox.com Precedence: bulk X-list: linux-mips Hi, Here're CPU-feature-overrides patches for PowerTV, Malta and MIPSSim. Along with these patches, I was going to consolidate irq_ffs() used in platforms above, but it seems PowerTV's IRQ routines need some work, so drop the relevant patches for now. P.S. I don't feel a strong motivation to consolidate irq_ffs(), so you don't have to take care of my comments. If you have a chance, take a look at it, thanks. Shinya David VomLehn (1): MIPS: PowerTV: Provide cpu-feature-overrides.h Shinya Kuribayashi (1): MIPS: Enable cpu_has_clo_clz for MIPS Technologies' platforms .../include/asm/mach-malta/cpu-feature-overrides.h | 2 + .../asm/mach-mipssim/cpu-feature-overrides.h | 2 + .../asm/mach-powertv/cpu-feature-overrides.h | 59 ++++++++++++++++++++ 3 files changed, 63 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h From skuribay@pobox.com Mon Jul 12 17:41:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 17:41:29 +0200 (CEST) Received: from b-pb-sasl-quonix.pobox.com ([208.72.237.35]:37891 "EHLO sasl.smtp.pobox.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492372Ab0GLPlX (ORCPT ); Mon, 12 Jul 2010 17:41:23 +0200 Received: from sasl.smtp.pobox.com (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id C4384B6D81; Mon, 12 Jul 2010 11:41:22 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=pobox.com; h=message-id :date:from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; s=sasl; bh=GnigqYJcAhFL ytUIq2jd+/v0aps=; b=MQJDmgxvpVN0wpX7YxDpLRWCu763SziWZ/ehf6H83hUJ tVIjkejfLOq8udqv+M3ypkpkTTJ3MdLFAXe0SKYQn7qUdSZ8TooyxzTSamA3JUSY 9K7hyIWgQyXyxVAdGNy5YMYWjoP2TGig4z1c9n5ZmfaE4xk1N3bnLv1jpKl7eOU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=pobox.com; h=message-id:date :from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; q=dns; s=sasl; b=aS6SZe YN2HZBlaYHvZZq1qoRwTB/Z6/lQVUAonUAsJWhd41HmuzegYulIi2lWd4KPiqdyF gDWPzejLYjB8lhFVTmqP5GtWGPp0AIF7zc2nSf3HejfuSs57NgVjehPWsdgS/SyV NXFSSY70eimzynmIaYjteUx1kYdt9oX+BXVeI= Received: from b-pb-sasl-quonix. (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 940EDB6D80; Mon, 12 Jul 2010 11:41:19 -0400 (EDT) Received: from [192.168.11.3] (unknown [114.162.174.29]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by b-sasl-quonix.pobox.com (Postfix) with ESMTPSA id 24690B6D7F; Mon, 12 Jul 2010 11:41:14 -0400 (EDT) Message-ID: <4C3B3798.9010908@pobox.com> Date: Tue, 13 Jul 2010 00:41:12 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.10) Gecko/20100527 Thunderbird/3.0.5 MIME-Version: 1.0 To: David VomLehn , ralf@linux-mips.org, macro@linux-mips.org CC: linux-mips@linux-mips.org Subject: [PATCH 1/2] MIPS: PowerTV: Provide cpu-feature-overrides.h References: <4C3B36B3.6010800@pobox.com> In-Reply-To: <4C3B36B3.6010800@pobox.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Pobox-Relay-ID: EA74BC5E-8DCB-11DF-B04B-DA91016DD5F0-47602734!b-pb-sasl-quonix.pobox.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27375 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@pobox.com Precedence: bulk X-list: linux-mips From: David VomLehn This will optimize fls() and __fls() to use CLZ throughout the kernel, and any other optimizations that depend on constant cpu_has_* values will also be used. Signed-off-by: David VomLehn Signed-off-by: Shinya Kuribayashi --- .../asm/mach-powertv/cpu-feature-overrides.h | 59 ++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h new file mode 100644 index 0000000..f751e3e --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2010 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ +#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_vint 1 +#define cpu_has_veic 1 +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#endif -- 1.7.1.1 From skuribay@pobox.com Mon Jul 12 17:42:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 17:42:08 +0200 (CEST) Received: from b-pb-sasl-quonix.pobox.com ([208.72.237.35]:39087 "EHLO sasl.smtp.pobox.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491944Ab0GLPmB (ORCPT ); Mon, 12 Jul 2010 17:42:01 +0200 Received: from sasl.smtp.pobox.com (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id 02F60B6D91; Mon, 12 Jul 2010 11:42:01 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=pobox.com; h=message-id :date:from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; s=sasl; bh=263dQAKUE9N3 zni3Zp0h78S7vCw=; b=XJFRTK2729JEdasHBlRykadEfHO8BlqkYwxChxOqDSQj H/VX4Q660wo0+aXCr8G/5f9ED0ODe7KLfHl/YSR/0AQ9ze2MBic08yv/RAHt0j2b br1PfCFx8fgSD/nmbnR8f3H+nQLEtXUPrJwAAUeiU4AEP2X2SNIwnfGvovlNgqU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=pobox.com; h=message-id:date :from:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; q=dns; s=sasl; b=HfR17x iA3jTssbxXKwAuuM/XCa76jQCubwmxvCRDUMWuEdGgTz4s7purqp10p/hcmL5mne t7lxeKH+eQ+I1iUuwou51JTBEK0HowEfrMDMZ3z1Max2g6kMZGVkOhFgVrFV84Br Z5YCz6cCj77fXHYHKxy/aTb5GOjAeCRR5Gfyo= Received: from b-pb-sasl-quonix. (unknown [127.0.0.1]) by b-sasl-quonix.pobox.com (Postfix) with ESMTP id BED2EB6D8C; Mon, 12 Jul 2010 11:41:57 -0400 (EDT) Received: from [192.168.11.3] (unknown [114.162.174.29]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by b-sasl-quonix.pobox.com (Postfix) with ESMTPSA id 84958B6D8B; Mon, 12 Jul 2010 11:41:53 -0400 (EDT) Message-ID: <4C3B37BF.2090606@pobox.com> Date: Tue, 13 Jul 2010 00:41:51 +0900 From: Shinya Kuribayashi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.10) Gecko/20100527 Thunderbird/3.0.5 MIME-Version: 1.0 To: David VomLehn , ralf@linux-mips.org, macro@linux-mips.org CC: linux-mips@linux-mips.org Subject: [PATCH 2/2] MIPS: Enable cpu_has_clo_clz for MIPS Technologies' platforms References: <4C3B36B3.6010800@pobox.com> In-Reply-To: <4C3B36B3.6010800@pobox.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Pobox-Relay-ID: 0135DF2C-8DCC-11DF-B991-DA91016DD5F0-47602734!b-pb-sasl-quonix.pobox.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27376 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@pobox.com Precedence: bulk X-list: linux-mips Enable cpu_has_clo_clz only when CONFIG_CPU_MIPS32 or CONFIG_CPU_MIPS64 is selected. This will optimize fls() and __fls() to use CLZ insn, and eventually ffs() and __ffs() as well. Malta and MIPSSim are development platforms, and need to take care of various processor configurations, release rivisions and so on, even across different MIPS ISAs. For such platforms we have to be careful, for instance, with turning on cpu_has_mips{32,64}r[12] features. As for CLZ, all MIPS32/64 processors support it, regardless of release revisions. Signed-off-by: Shinya Kuribayashi --- .../include/asm/mach-malta/cpu-feature-overrides.h | 2 ++ .../asm/mach-mipssim/cpu-feature-overrides.h | 2 ++ 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h index 2848cea..37e3583 100644 --- a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h @@ -32,6 +32,7 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ @@ -58,6 +59,7 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ diff --git a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h index 779b022..27aaaa5 100644 --- a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h @@ -31,6 +31,7 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ @@ -56,6 +57,7 @@ /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_clo_clz 1 #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ -- 1.7.1.1 From lars@metafoo.de Mon Jul 12 23:33:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 23:34:05 +0200 (CEST) Received: from smtp-out-217.synserver.de ([212.40.180.217]:1059 "HELO smtp-out-217.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492392Ab0GLVd7 (ORCPT ); Mon, 12 Jul 2010 23:33:59 +0200 Received: (qmail 17269 invoked by uid 0); 12 Jul 2010 21:33:53 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 17199 Received: from d043121.adsl.hansenet.de (HELO localhost.localdomain) [80.171.43.121] by 217.119.54.81 with SMTP; 12 Jul 2010 21:33:52 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen , Andrew Morton , Matt Fleming , linux-mmc@vger.kernel.org Subject: [PATCH v4] MMC: Add JZ4740 mmc driver Date: Mon, 12 Jul 2010 23:33:32 +0200 Message-Id: <1278970413-21617-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1277688041-23522-1-git-send-email-lars@metafoo.de> References: <1277688041-23522-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27377 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for the mmc controller on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen Acked-by: Matt Fleming Cc: Andrew Morton Cc: Matt Fleming Cc: linux-mmc@vger.kernel.org --- Changes since v1 - Do not request IRQ with IRQF_DISABLED since it is a noop now - Use a generous slack for the timeout timer. It does not need to be accurate. Changes since v2 - Use sg_mapping_to iterate over sg elements in mmc read and write functions - Use bitops instead of a spinlock and a variable for testing whether a request has been finished. - Rework irq and timeout handling in order to get rid of locking in hot paths Changes since v3 - Drastically decrease IRQ poll timeout. Now when the poll timeout is reached the IRQ which was polled is enabled. A variable keeps track of what state the driver is in and what has to be done next when the IRQ handler is entered again. By doing so busy looping is reduced, but overall performance can be maintained. - Move header file from include/linux/mmc to arch/mips/include/asm/mach-jz4740 --- arch/mips/include/asm/mach-jz4740/jz4740_mmc.h | 15 + drivers/mmc/host/Kconfig | 8 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/jz4740_mmc.c | 1024 ++++++++++++++++++++++++ 4 files changed, 1048 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h create mode 100644 drivers/mmc/host/jz4740_mmc.c diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h new file mode 100644 index 0000000..8543f43 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h @@ -0,0 +1,15 @@ +#ifndef __LINUX_MMC_JZ4740_MMC +#define __LINUX_MMC_JZ4740_MMC + +struct jz4740_mmc_platform_data { + int gpio_power; + int gpio_card_detect; + int gpio_read_only; + unsigned card_detect_active_low:1; + unsigned read_only_active_low:1; + unsigned power_active_low:1; + + unsigned data_1bit:1; +}; + +#endif diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index f06d06e..546fc49 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -81,6 +81,14 @@ config MMC_RICOH_MMC If unsure, say Y. +config MMC_JZ4740 + tristate "JZ4740 SD/Multimedia Card Interface support" + depends on MACH_JZ4740 + help + This selects the Ingenic Z4740 SD/Multimedia card Interface. + If you have an ngenic platform with a Multimedia Card slot, + say Y or M here. + config MMC_SDHCI_OF tristate "SDHCI support on OpenFirmware platforms" depends on MMC_SDHCI && PPC_OF diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index e30c2ee..f4e53c9 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MMC_CB710) += cb710-mmc.o obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o +obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o sdhci-of-y := sdhci-of-core.o diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c new file mode 100644 index 0000000..82a449a --- /dev/null +++ b/drivers/mmc/host/jz4740_mmc.c @@ -0,0 +1,1024 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 SD/MMC controller driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#define JZ_REG_MMC_STRPCL 0x00 +#define JZ_REG_MMC_STATUS 0x04 +#define JZ_REG_MMC_CLKRT 0x08 +#define JZ_REG_MMC_CMDAT 0x0C +#define JZ_REG_MMC_RESTO 0x10 +#define JZ_REG_MMC_RDTO 0x14 +#define JZ_REG_MMC_BLKLEN 0x18 +#define JZ_REG_MMC_NOB 0x1C +#define JZ_REG_MMC_SNOB 0x20 +#define JZ_REG_MMC_IMASK 0x24 +#define JZ_REG_MMC_IREG 0x28 +#define JZ_REG_MMC_CMD 0x2C +#define JZ_REG_MMC_ARG 0x30 +#define JZ_REG_MMC_RESP_FIFO 0x34 +#define JZ_REG_MMC_RXFIFO 0x38 +#define JZ_REG_MMC_TXFIFO 0x3C + +#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) +#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) +#define JZ_MMC_STRPCL_START_READWAIT BIT(5) +#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) +#define JZ_MMC_STRPCL_RESET BIT(3) +#define JZ_MMC_STRPCL_START_OP BIT(2) +#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) +#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) +#define JZ_MMC_STRPCL_CLOCK_START BIT(1) + + +#define JZ_MMC_STATUS_IS_RESETTING BIT(15) +#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) +#define JZ_MMC_STATUS_PRG_DONE BIT(13) +#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) +#define JZ_MMC_STATUS_END_CMD_RES BIT(11) +#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) +#define JZ_MMC_STATUS_IS_READWAIT BIT(9) +#define JZ_MMC_STATUS_CLK_EN BIT(8) +#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) +#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) +#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) +#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) +#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) +#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) +#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) +#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) + +#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) +#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) + + +#define JZ_MMC_CMDAT_IO_ABORT BIT(11) +#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) +#define JZ_MMC_CMDAT_DMA_EN BIT(8) +#define JZ_MMC_CMDAT_INIT BIT(7) +#define JZ_MMC_CMDAT_BUSY BIT(6) +#define JZ_MMC_CMDAT_STREAM BIT(5) +#define JZ_MMC_CMDAT_WRITE BIT(4) +#define JZ_MMC_CMDAT_DATA_EN BIT(3) +#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) +#define JZ_MMC_CMDAT_RSP_R1 1 +#define JZ_MMC_CMDAT_RSP_R2 2 +#define JZ_MMC_CMDAT_RSP_R3 3 + +#define JZ_MMC_IRQ_SDIO BIT(7) +#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) +#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) +#define JZ_MMC_IRQ_END_CMD_RES BIT(2) +#define JZ_MMC_IRQ_PRG_DONE BIT(1) +#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) + + +#define JZ_MMC_CLK_RATE 24000000 + +enum jz4740_mmc_state { + JZ4740_MMC_STATE_READ_RESPONSE, + JZ4740_MMC_STATE_TRANSFER_DATA, + JZ4740_MMC_STATE_SEND_STOP, + JZ4740_MMC_STATE_DONE, +}; + +struct jz4740_mmc_host { + struct mmc_host *mmc; + struct platform_device *pdev; + struct jz4740_mmc_platform_data *pdata; + struct clk *clk; + + int irq; + int card_detect_irq; + + struct resource *mem; + void __iomem *base; + struct mmc_request *req; + struct mmc_command *cmd; + + unsigned long waiting; + + uint32_t cmdat; + + uint16_t irq_mask; + + spinlock_t lock; + + struct timer_list timeout_timer; + struct sg_mapping_iter miter; + enum jz4740_mmc_state state; +}; + +static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, + unsigned int irq, bool enabled) +{ + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + if (enabled) + host->irq_mask &= ~irq; + else + host->irq_mask |= irq; + spin_unlock_irqrestore(&host->lock, flags); + + writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK); +} + +static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, + bool start_transfer) +{ + uint16_t val = JZ_MMC_STRPCL_CLOCK_START; + + if (start_transfer) + val |= JZ_MMC_STRPCL_START_OP; + + writew(val, host->base + JZ_REG_MMC_STRPCL); +} + +static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) +{ + uint32_t status; + unsigned int timeout = 1000; + + writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); + do { + status = readl(host->base + JZ_REG_MMC_STATUS); + } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); +} + +static void jz4740_mmc_reset(struct jz4740_mmc_host *host) +{ + uint32_t status; + unsigned int timeout = 1000; + + writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); + udelay(10); + do { + status = readl(host->base + JZ_REG_MMC_STATUS); + } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); +} + +static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) +{ + struct mmc_request *req; + + req = host->req; + host->req = NULL; + + mmc_request_done(host->mmc, req); +} +static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, + unsigned int irq) +{ + unsigned int timeout = 1000; + uint16_t status; + + do { + status = readw(host->base + JZ_REG_MMC_IREG); + } while (!(status & irq) && --timeout); + + if (timeout == 0) { + set_bit(0, &host->waiting); + mod_timer(&host->timeout_timer, jiffies + 5*HZ); + jz4740_mmc_set_irq_enabled(host, irq, true); + return true; + } + + return false; +} + +static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + int status; + + status = readl(host->base + JZ_REG_MMC_STATUS); + if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { + if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { + host->req->cmd->error = -ETIMEDOUT; + data->error = -ETIMEDOUT; + } else { + host->req->cmd->error = -EIO; + data->error = -EIO; + } + } +} + +static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + struct sg_mapping_iter *miter = &host->miter; + uint32_t *buf; + bool timeout; + size_t i, j; + + while (sg_miter_next(miter)) { + buf = miter->addr; + i = miter->length / 4; + j = i / 8; + i = i & 0x7; + while (j) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + writel(buf[0], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[1], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[2], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[3], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[4], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[5], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[6], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[7], host->base + JZ_REG_MMC_TXFIFO); + buf += 8; + --j; + } + if (unlikely(i)) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + while (i) { + writel(*buf, host->base + JZ_REG_MMC_TXFIFO); + ++buf; + --i; + } + } + data->bytes_xfered += miter->length; + } + sg_miter_stop(miter); + + return false; + +poll_timeout: + miter->consumed = (void *)buf - miter->addr; + data->bytes_xfered += miter->consumed; + sg_miter_stop(miter); + + return true; +} + +static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + struct sg_mapping_iter *miter = &host->miter; + uint32_t *buf; + uint32_t d; + uint16_t status; + size_t i, j; + unsigned int timeout; + + while (sg_miter_next(miter)) { + buf = miter->addr; + i = miter->length; + j = i / 32; + i = i & 0x1f; + while (j) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + buf[0] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[1] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[2] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[3] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[4] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[5] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[6] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[7] = readl(host->base + JZ_REG_MMC_RXFIFO); + + buf += 8; + --j; + } + + if (unlikely(i)) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + while (i >= 4) { + *buf++ = readl(host->base + JZ_REG_MMC_RXFIFO); + i -= 4; + } + if (unlikely(i > 0)) { + d = readl(host->base + JZ_REG_MMC_RXFIFO); + memcpy(buf, &d, i); + } + } + data->bytes_xfered += miter->length; + + /* This can go away once MIPS implements + * flush_kernel_dcache_page */ + flush_dcache_page(miter->page); + } + sg_miter_stop(miter); + + /* For whatever reason there is sometime one word more in the fifo then + * requested */ + timeout = 1000; + status = readl(host->base + JZ_REG_MMC_STATUS); + while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { + d = readl(host->base + JZ_REG_MMC_RXFIFO); + status = readl(host->base + JZ_REG_MMC_STATUS); + } + + return false; + +poll_timeout: + miter->consumed = (void *)buf - miter->addr; + data->bytes_xfered += miter->consumed; + sg_miter_stop(miter); + + return true; +} + +static void jz4740_mmc_timeout(unsigned long data) +{ + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data; + + if (!test_and_clear_bit(0, &host->waiting)) + return; + + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); + + host->req->cmd->error = -ETIMEDOUT; + jz4740_mmc_request_done(host); +} + +static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, + struct mmc_command *cmd) +{ + int i; + uint16_t tmp; + + if (cmd->flags & MMC_RSP_136) { + tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO); + for (i = 0; i < 4; ++i) { + cmd->resp[i] = tmp << 24; + tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO); + cmd->resp[i] |= tmp << 8; + tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO); + cmd->resp[i] |= tmp >> 8; + } + } else { + cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24; + cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8; + cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff; + } +} + +static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, + struct mmc_command *cmd) +{ + uint32_t cmdat = host->cmdat; + + host->cmdat &= ~JZ_MMC_CMDAT_INIT; + jz4740_mmc_clock_disable(host); + + host->cmd = cmd; + + if (cmd->flags & MMC_RSP_BUSY) + cmdat |= JZ_MMC_CMDAT_BUSY; + + switch (mmc_resp_type(cmd)) { + case MMC_RSP_R1B: + case MMC_RSP_R1: + cmdat |= JZ_MMC_CMDAT_RSP_R1; + break; + case MMC_RSP_R2: + cmdat |= JZ_MMC_CMDAT_RSP_R2; + break; + case MMC_RSP_R3: + cmdat |= JZ_MMC_CMDAT_RSP_R3; + break; + default: + break; + } + + if (cmd->data) { + cmdat |= JZ_MMC_CMDAT_DATA_EN; + if (cmd->data->flags & MMC_DATA_WRITE) + cmdat |= JZ_MMC_CMDAT_WRITE; + if (cmd->data->flags & MMC_DATA_STREAM) + cmdat |= JZ_MMC_CMDAT_STREAM; + + writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); + writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); + } + + writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); + writel(cmd->arg, host->base + JZ_REG_MMC_ARG); + writel(cmdat, host->base + JZ_REG_MMC_CMDAT); + + jz4740_mmc_clock_enable(host, 1); +} + +static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) +{ + struct mmc_command *cmd = host->req->cmd; + struct mmc_data *data = cmd->data; + int direction; + + if (cmd->data->flags & MMC_DATA_READ) + direction = SG_MITER_TO_SG; + else + direction = SG_MITER_FROM_SG; + + sg_miter_start(&host->miter, data->sg, data->sg_len, direction); +} + + +static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) +{ + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; + struct mmc_command *cmd = host->req->cmd; + struct mmc_request *req = host->req; + bool timedout = false; + + if (cmd->error) + host->state = JZ4740_MMC_STATE_DONE; + + switch (host->state) { + case JZ4740_MMC_STATE_READ_RESPONSE: + if (cmd->flags & MMC_RSP_PRESENT) + jz4740_mmc_read_response(host, cmd); + + if (!cmd->data) + break; + + jz_mmc_prepare_data_transfer(host); + + case JZ4740_MMC_STATE_TRANSFER_DATA: + if (cmd->data->flags & MMC_DATA_READ) + timedout = jz4740_mmc_read_data(host, cmd->data); + else + timedout = jz4740_mmc_write_data(host, cmd->data); + + if (unlikely(timedout)) { + host->state = JZ4740_MMC_STATE_TRANSFER_DATA; + break; + } + + jz4740_mmc_transfer_check_state(host, cmd->data); + + timedout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); + if (unlikely(timedout)) { + host->state = JZ4740_MMC_STATE_SEND_STOP; + break; + } + writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG); + + case JZ4740_MMC_STATE_SEND_STOP: + if (!req->stop) + break; + + jz4740_mmc_send_command(host, req->stop); + + timedout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE); + if (timedout) { + host->state = JZ4740_MMC_STATE_DONE; + break; + } + case JZ4740_MMC_STATE_DONE: + break; + } + + if (!timedout) + jz4740_mmc_request_done(host); + + return IRQ_HANDLED; +} + +static irqreturn_t jz_mmc_irq(int irq, void *devid) +{ + struct jz4740_mmc_host *host = devid; + uint16_t irq_reg, status, tmp; + + irq_reg = readw(host->base + JZ_REG_MMC_IREG); + + tmp = irq_reg; + irq_reg &= ~host->irq_mask; + + tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | + JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); + + if (tmp != irq_reg) + writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG); + + if (irq_reg & JZ_MMC_IRQ_SDIO) { + writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG); + mmc_signal_sdio_irq(host->mmc); + irq_reg &= ~JZ_MMC_IRQ_SDIO; + } + + if (host->req && host->cmd && irq_reg) { + if (test_and_clear_bit(0, &host->waiting)) { + del_timer(&host->timeout_timer); + + status = readl(host->base + JZ_REG_MMC_STATUS); + + if (status & JZ_MMC_STATUS_TIMEOUT_RES) { + host->cmd->error = -ETIMEDOUT; + } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { + host->cmd->error = -EIO; + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | + JZ_MMC_STATUS_CRC_WRITE_ERROR)) { + host->cmd->data->error = -EIO; + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | + JZ_MMC_STATUS_CRC_WRITE_ERROR)) { + host->cmd->data->error = -EIO; + } + + jz4740_mmc_set_irq_enabled(host, irq_reg, false); + writew(irq_reg, host->base + JZ_REG_MMC_IREG); + + return IRQ_WAKE_THREAD; + } + } + + return IRQ_HANDLED; +} + +static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) +{ + int div = 0; + int real_rate; + + jz4740_mmc_clock_disable(host); + clk_set_rate(host->clk, JZ_MMC_CLK_RATE); + + real_rate = clk_get_rate(host->clk); + + while (real_rate > rate && div < 7) { + ++div; + real_rate >>= 1; + } + + writew(div, host->base + JZ_REG_MMC_CLKRT); + return real_rate; +} + +static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + + host->req = req; + + writew(0xffff, host->base + JZ_REG_MMC_IREG); + + writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG); + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); + + host->state = JZ4740_MMC_STATE_READ_RESPONSE; + set_bit(0, &host->waiting); + mod_timer(&host->timeout_timer, jiffies + 5*HZ); + jz4740_mmc_send_command(host, req->cmd); +} + +static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (ios->clock) + jz4740_mmc_set_clock_rate(host, ios->clock); + + switch (ios->power_mode) { + case MMC_POWER_UP: + jz4740_mmc_reset(host); + if (gpio_is_valid(host->pdata->gpio_power)) + gpio_set_value(host->pdata->gpio_power, + !host->pdata->power_active_low); + host->cmdat |= JZ_MMC_CMDAT_INIT; + clk_enable(host->clk); + break; + case MMC_POWER_ON: + break; + default: + if (gpio_is_valid(host->pdata->gpio_power)) + gpio_set_value(host->pdata->gpio_power, + host->pdata->power_active_low); + clk_disable(host->clk); + break; + } + + switch (ios->bus_width) { + case MMC_BUS_WIDTH_1: + host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT; + break; + case MMC_BUS_WIDTH_4: + host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; + break; + default: + break; + } +} + +static int jz4740_mmc_get_ro(struct mmc_host *mmc) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (!gpio_is_valid(host->pdata->gpio_read_only)) + return -ENOSYS; + + return gpio_get_value(host->pdata->gpio_read_only) ^ + host->pdata->read_only_active_low; +} + +static int jz4740_mmc_get_cd(struct mmc_host *mmc) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (!gpio_is_valid(host->pdata->gpio_card_detect)) + return -ENOSYS; + + return gpio_get_value(host->pdata->gpio_card_detect) ^ + host->pdata->card_detect_active_low; +} + +static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid) +{ + struct jz4740_mmc_host *host = devid; + + mmc_detect_change(host->mmc, HZ / 2); + + return IRQ_HANDLED; +} + +static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); +} + +static const struct mmc_host_ops jz4740_mmc_ops = { + .request = jz4740_mmc_request, + .set_ios = jz4740_mmc_set_ios, + .get_ro = jz4740_mmc_get_ro, + .get_cd = jz4740_mmc_get_cd, + .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, +}; + +static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = { + JZ_GPIO_BULK_PIN(MSC_CMD), + JZ_GPIO_BULK_PIN(MSC_CLK), + JZ_GPIO_BULK_PIN(MSC_DATA0), + JZ_GPIO_BULK_PIN(MSC_DATA1), + JZ_GPIO_BULK_PIN(MSC_DATA2), + JZ_GPIO_BULK_PIN(MSC_DATA3), +}; + +static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio, + const char *name, bool output, int value) +{ + int ret; + + if (!gpio_is_valid(gpio)) + return 0; + + ret = gpio_request(gpio, name); + if (ret) { + dev_err(dev, "Failed to request %s gpio: %d\n", name, ret); + return ret; + } + + if (output) + gpio_direction_output(gpio, value); + else + gpio_direction_input(gpio); + + return 0; +} + +static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev) +{ + int ret; + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (!pdata) + return 0; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect, + "MMC detect change", false, 0); + if (ret) + goto err; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only, + "MMC read only", false, 0); + if (ret) + goto err_free_gpio_card_detect; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power, + "MMC read only", true, pdata->power_active_low); + if (ret) + goto err_free_gpio_read_only; + + return 0; + +err_free_gpio_read_only: + if (gpio_is_valid(pdata->gpio_read_only)) + gpio_free(pdata->gpio_read_only); +err_free_gpio_card_detect: + if (gpio_is_valid(pdata->gpio_card_detect)) + gpio_free(pdata->gpio_card_detect); +err: + return ret; +} + +static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev, + struct jz4740_mmc_host *host) +{ + int ret; + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (gpio_is_valid(pdata->gpio_card_detect)) + return 0; + + host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect); + + if (host->card_detect_irq < 0) { + dev_warn(&pdev->dev, "Failed to get card detect irq\n"); + return 0; + } + return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "MMC card detect", host); + + + return ret; +} + +static void jz4740_mmc_free_gpios(struct platform_device *pdev) +{ + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (!pdata) + return; + + if (gpio_is_valid(pdata->gpio_power)) + gpio_free(pdata->gpio_power); + if (gpio_is_valid(pdata->gpio_read_only)) + gpio_free(pdata->gpio_read_only); + if (gpio_is_valid(pdata->gpio_card_detect)) + gpio_free(pdata->gpio_card_detect); +} + +static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host) +{ + size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins); + if (host->pdata && host->pdata->data_1bit) + num_pins -= 3; + + return num_pins; +} + +static int __devinit jz4740_mmc_probe(struct platform_device* pdev) +{ + int ret; + struct mmc_host *mmc; + struct jz4740_mmc_host *host; + struct jz4740_mmc_platform_data *pdata; + + pdata = pdev->dev.platform_data; + + mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); + if (!mmc) { + dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); + return -ENOMEM; + } + + host = mmc_priv(mmc); + host->pdata = pdata; + + host->irq = platform_get_irq(pdev, 0); + if (host->irq < 0) { + ret = host->irq; + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); + goto err_free_host; + } + + host->clk = clk_get(&pdev->dev, "mmc"); + if (!host->clk) { + ret = -ENOENT; + dev_err(&pdev->dev, "Failed to get mmc clock\n"); + goto err_free_host; + } + + host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!host->mem) { + ret = -ENOENT; + dev_err(&pdev->dev, "Failed to get base platform memory\n"); + goto err_clk_put; + } + + host->mem = request_mem_region(host->mem->start, + resource_size(host->mem), pdev->name); + if (!host->mem) { + ret = -EBUSY; + dev_err(&pdev->dev, "Failed to request base memory region\n"); + goto err_clk_put; + } + + host->base = ioremap_nocache(host->mem->start, resource_size(host->mem)); + if (!host->base) { + ret = -EBUSY; + dev_err(&pdev->dev, "Failed to ioremap base memory\n"); + goto err_release_mem_region; + } + + ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + if (ret) { + dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret); + goto err_iounmap; + } + + ret = jz4740_mmc_request_gpios(pdev); + if (ret) + goto err_gpio_bulk_free; + + mmc->ops = &jz4740_mmc_ops; + mmc->f_min = JZ_MMC_CLK_RATE / 128; + mmc->f_max = JZ_MMC_CLK_RATE; + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA; + mmc->caps |= MMC_CAP_SDIO_IRQ; + + mmc->max_blk_size = (1 << 10) - 1; + mmc->max_blk_count = (1 << 15) - 1; + mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; + + mmc->max_phys_segs = 128; + mmc->max_hw_segs = 128; + mmc->max_seg_size = mmc->max_req_size; + + host->mmc = mmc; + host->pdev = pdev; + spin_lock_init(&host->lock); + host->irq_mask = 0xffff; + + ret = jz4740_mmc_request_cd_irq(pdev, host); + if (ret) { + dev_err(&pdev->dev, "Failed to request card detect irq\n"); + goto err_free_gpios; + } + + ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, + dev_name(&pdev->dev), host); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); + goto err_free_card_detect_irq; + } + + jz4740_mmc_reset(host); + jz4740_mmc_clock_disable(host); + setup_timer(&host->timeout_timer, jz4740_mmc_timeout, + (unsigned long)host); + /* It is not important when it times out, it just needs to timeout. */ + set_timer_slack(&host->timeout_timer, HZ); + + platform_set_drvdata(pdev, host); + ret = mmc_add_host(mmc); + + if (ret) { + dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); + goto err_free_irq; + } + dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); + + return 0; + +err_free_irq: + free_irq(host->irq, host); +err_free_card_detect_irq: + if (host->card_detect_irq >= 0) + free_irq(host->card_detect_irq, host); +err_free_gpios: + jz4740_mmc_free_gpios(pdev); +err_gpio_bulk_free: + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); +err_iounmap: + iounmap(host->base); +err_release_mem_region: + release_mem_region(host->mem->start, resource_size(host->mem)); +err_clk_put: + clk_put(host->clk); +err_free_host: + platform_set_drvdata(pdev, NULL); + mmc_free_host(mmc); + + return ret; +} + +static int __devexit jz4740_mmc_remove(struct platform_device *pdev) +{ + struct jz4740_mmc_host *host = platform_get_drvdata(pdev); + + del_timer_sync(&host->timeout_timer); + jz4740_mmc_set_irq_enabled(host, 0xff, false); + jz4740_mmc_reset(host); + + mmc_remove_host(host->mmc); + + free_irq(host->irq, host); + if (host->card_detect_irq >= 0) + free_irq(host->card_detect_irq, host); + + jz4740_mmc_free_gpios(pdev); + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + iounmap(host->base); + release_mem_region(host->mem->start, resource_size(host->mem)); + + clk_put(host->clk); + + platform_set_drvdata(pdev, NULL); + mmc_free_host(host->mmc); + + return 0; +} + +#ifdef CONFIG_PM + +static int jz4740_mmc_suspend(struct device *dev) +{ + struct jz4740_mmc_host *host = dev_get_drvdata(dev); + + mmc_suspend_host(host->mmc); + + jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + return 0; +} + +static int jz4740_mmc_resume(struct device *dev) +{ + struct jz4740_mmc_host *host = dev_get_drvdata(dev); + + jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + mmc_resume_host(host->mmc); + + return 0; +} + +const struct dev_pm_ops jz4740_mmc_pm_ops = { + .suspend = jz4740_mmc_suspend, + .resume = jz4740_mmc_resume, + .poweroff = jz4740_mmc_suspend, + .restore = jz4740_mmc_resume, +}; + +#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) +#else +#define JZ4740_MMC_PM_OPS NULL +#endif + +static struct platform_driver jz4740_mmc_driver = { + .probe = jz4740_mmc_probe, + .remove = __devexit_p(jz4740_mmc_remove), + .driver = { + .name = "jz4740-mmc", + .owner = THIS_MODULE, + .pm = JZ4740_MMC_PM_OPS, + }, +}; + +static int __init jz4740_mmc_init(void) +{ + return platform_driver_register(&jz4740_mmc_driver); +} +module_init(jz4740_mmc_init); + +static void __exit jz4740_mmc_exit(void) +{ + platform_driver_unregister(&jz4740_mmc_driver); +} +module_exit(jz4740_mmc_exit); + +MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lars-Peter Clausen "); -- 1.5.6.5 From randy.dunlap@oracle.com Mon Jul 12 23:43:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jul 2010 23:43:24 +0200 (CEST) Received: from rcsinet10.oracle.com ([148.87.113.121]:56056 "EHLO rcsinet10.oracle.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492388Ab0GLVnS (ORCPT ); Mon, 12 Jul 2010 23:43:18 +0200 Received: from acsinet15.oracle.com (acsinet15.oracle.com [141.146.126.227]) by rcsinet10.oracle.com (Switch-3.4.2/Switch-3.4.2) with ESMTP id o6CLgx3K017122 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 12 Jul 2010 21:43:01 GMT Received: from acsmt353.oracle.com (acsmt353.oracle.com [141.146.40.153]) by acsinet15.oracle.com (Switch-3.4.2/Switch-3.4.1) with ESMTP id o6CJmH2U002572; Mon, 12 Jul 2010 21:42:58 GMT Received: from abhmt013.oracle.com by acsmt354.oracle.com with ESMTP id 399055571278970901; Mon, 12 Jul 2010 14:41:41 -0700 Received: from [192.168.5.251] (/64.134.136.20) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Mon, 12 Jul 2010 14:41:41 -0700 Message-ID: <4C3B8C13.3040009@oracle.com> Date: Mon, 12 Jul 2010 14:41:39 -0700 From: Randy Dunlap User-Agent: Thunderbird 2.0.0.19 (X11/20081227) MIME-Version: 1.0 To: Lars-Peter Clausen CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton , Matt Fleming , linux-mmc@vger.kernel.org Subject: Re: [PATCH v4] MMC: Add JZ4740 mmc driver References: <1277688041-23522-1-git-send-email-lars@metafoo.de> <1278970413-21617-1-git-send-email-lars@metafoo.de> In-Reply-To: <1278970413-21617-1-git-send-email-lars@metafoo.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Source-IP: acsmt353.oracle.com [141.146.40.153] X-Auth-Type: Internal IP X-CT-RefId: str=0001.0A090206.4C3B8C63.000C:SCFMA4539814,ss=1,fgs=0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27378 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: randy.dunlap@oracle.com Precedence: bulk X-list: linux-mips Lars-Peter Clausen wrote: > This patch adds support for the mmc controller on JZ4740 SoCs. > > Signed-off-by: Lars-Peter Clausen > Acked-by: Matt Fleming > Cc: Andrew Morton > Cc: Matt Fleming > Cc: linux-mmc@vger.kernel.org > > --- > arch/mips/include/asm/mach-jz4740/jz4740_mmc.h | 15 + > drivers/mmc/host/Kconfig | 8 + > drivers/mmc/host/Makefile | 1 + > drivers/mmc/host/jz4740_mmc.c | 1024 ++++++++++++++++++++++++ > 4 files changed, 1048 insertions(+), 0 deletions(-) > create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h > create mode 100644 drivers/mmc/host/jz4740_mmc.c > > diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h > new file mode 100644 > index 0000000..8543f43 > --- /dev/null > +++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h > @@ -0,0 +1,15 @@ > +#ifndef __LINUX_MMC_JZ4740_MMC > +#define __LINUX_MMC_JZ4740_MMC > + > +struct jz4740_mmc_platform_data { > + int gpio_power; > + int gpio_card_detect; > + int gpio_read_only; > + unsigned card_detect_active_low:1; > + unsigned read_only_active_low:1; > + unsigned power_active_low:1; > + > + unsigned data_1bit:1; > +}; > + > +#endif > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig > index f06d06e..546fc49 100644 > --- a/drivers/mmc/host/Kconfig > +++ b/drivers/mmc/host/Kconfig > @@ -81,6 +81,14 @@ config MMC_RICOH_MMC > > If unsure, say Y. > > +config MMC_JZ4740 > + tristate "JZ4740 SD/Multimedia Card Interface support" > + depends on MACH_JZ4740 What tree has the kconfig symbol MACH_JZ4740 in it? I can't seem to find it... Should the depends also say anything about GPIO? I only ask because the header file above mentions gpio. > + help > + This selects the Ingenic Z4740 SD/Multimedia card Interface. > + If you have an ngenic platform with a Multimedia Card slot, Ingenic ? > + say Y or M here. > + > config MMC_SDHCI_OF > tristate "SDHCI support on OpenFirmware platforms" > depends on MMC_SDHCI && PPC_OF From lars@metafoo.de Tue Jul 13 00:08:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jul 2010 00:08:36 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:35628 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492008Ab0GLWIc (ORCPT ); Tue, 13 Jul 2010 00:08:32 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id BE6F0467; Tue, 13 Jul 2010 00:08:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id LMZLN2TgkzIf; Tue, 13 Jul 2010 00:08:25 +0200 (CEST) Received: from [172.31.16.228] (d043121.adsl.hansenet.de [80.171.43.121]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id C3BCE465; Tue, 13 Jul 2010 00:08:14 +0200 (CEST) Message-ID: <4C3B923F.1090703@metafoo.de> Date: Tue, 13 Jul 2010 00:07:59 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Randy Dunlap CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton , Matt Fleming , linux-mmc@vger.kernel.org Subject: Re: [PATCH v4] MMC: Add JZ4740 mmc driver References: <1277688041-23522-1-git-send-email-lars@metafoo.de> <1278970413-21617-1-git-send-email-lars@metafoo.de> <4C3B8C13.3040009@oracle.com> In-Reply-To: <4C3B8C13.3040009@oracle.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27379 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Hi Randy Dunlap wrote: > Lars-Peter Clausen wrote: >> This patch adds support for the mmc controller on JZ4740 SoCs. >> >> Signed-off-by: Lars-Peter Clausen >> Acked-by: Matt Fleming >> Cc: Andrew Morton >> Cc: Matt Fleming >> Cc: linux-mmc@vger.kernel.org >> >> --- >> arch/mips/include/asm/mach-jz4740/jz4740_mmc.h | 15 + >> drivers/mmc/host/Kconfig | 8 + >> drivers/mmc/host/Makefile | 1 + >> drivers/mmc/host/jz4740_mmc.c | 1024 ++++++++++++++++++++++++ >> 4 files changed, 1048 insertions(+), 0 deletions(-) >> create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h >> create mode 100644 drivers/mmc/host/jz4740_mmc.c >> >> diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h >> new file mode 100644 >> index 0000000..8543f43 >> --- /dev/null >> +++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h >> @@ -0,0 +1,15 @@ >> +#ifndef __LINUX_MMC_JZ4740_MMC >> +#define __LINUX_MMC_JZ4740_MMC >> + >> +struct jz4740_mmc_platform_data { >> + int gpio_power; >> + int gpio_card_detect; >> + int gpio_read_only; >> + unsigned card_detect_active_low:1; >> + unsigned read_only_active_low:1; >> + unsigned power_active_low:1; >> + >> + unsigned data_1bit:1; >> +}; >> + >> +#endif >> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig >> index f06d06e..546fc49 100644 >> --- a/drivers/mmc/host/Kconfig >> +++ b/drivers/mmc/host/Kconfig >> @@ -81,6 +81,14 @@ config MMC_RICOH_MMC >> >> If unsure, say Y. >> >> +config MMC_JZ4740 >> + tristate "JZ4740 SD/Multimedia Card Interface support" >> + depends on MACH_JZ4740 > > What tree has the kconfig symbol MACH_JZ4740 in it? > I can't seem to find it... > > Should the depends also say anything about GPIO? > I only ask because the header file above mentions gpio. > None yet, mips hopefully soon. Version 1 of this patch was part of a series adding support for the JZ4740. Since the jz4740 platform code provides the gpio functions I don't think it is necessary to add an additional depends on GENERIC_GPIO. >> + help >> + This selects the Ingenic Z4740 SD/Multimedia card Interface. >> + If you have an ngenic platform with a Multimedia Card slot, > > Ingenic ? > Woops, yes. >> + say Y or M here. >> + >> config MMC_SDHCI_OF >> tristate "SDHCI support on OpenFirmware platforms" >> depends on MMC_SDHCI && PPC_OF > > Thanks for reviewing - Lars From lars@metafoo.de Tue Jul 13 00:21:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jul 2010 00:21:17 +0200 (CEST) Received: from smtp-out-217.synserver.de ([212.40.180.217]:1050 "HELO smtp-out-217.synserver.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492008Ab0GLWVL (ORCPT ); Tue, 13 Jul 2010 00:21:11 +0200 Received: (qmail 21216 invoked by uid 0); 12 Jul 2010 22:21:04 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 21052 Received: from d043121.adsl.hansenet.de (HELO localhost.localdomain) [80.171.43.121] by 217.119.54.77 with SMTP; 12 Jul 2010 22:21:03 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen , Andrew Morton , Matt Fleming , linux-mmc@vger.kernel.org Subject: [PATCH v5] MMC: Add JZ4740 mmc driver Date: Tue, 13 Jul 2010 00:20:45 +0200 Message-Id: <1278973245-25451-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1278970413-21617-1-git-send-email-lars@metafoo.de> References: <1278970413-21617-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27380 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for the mmc controller on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen Acked-by: Matt Fleming Cc: Andrew Morton Cc: Matt Fleming Cc: linux-mmc@vger.kernel.org --- Changes since v1 - Do not request IRQ with IRQF_DISABLED since it is a noop now - Use a generous slack for the timeout timer. It does not need to be accurate. Changes since v2 - Use sg_mapping_to iterate over sg elements in mmc read and write functions - Use bitops instead of a spinlock and a variable for testing whether a request has been finished. - Rework irq and timeout handling in order to get rid of locking in hot paths Changes since v3 - Drastically decrease IRQ poll timeout. Now when the poll timeout is reached the IRQ which was polled is enabled. A variable keeps track of what state the driver is in and what has to be done next when the IRQ handler is entered again. By doing so busy looping is reduced, but overall performance can be maintained. - Move header file from include/linux/mmc to arch/mips/include/asm/mach-jz4740 Changes since v4 - Rework Kconfig entry --- arch/mips/include/asm/mach-jz4740/jz4740_mmc.h | 15 + drivers/mmc/host/Kconfig | 9 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/jz4740_mmc.c | 1024 ++++++++++++++++++++++++ 4 files changed, 1049 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h create mode 100644 drivers/mmc/host/jz4740_mmc.c diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h new file mode 100644 index 0000000..8543f43 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h @@ -0,0 +1,15 @@ +#ifndef __LINUX_MMC_JZ4740_MMC +#define __LINUX_MMC_JZ4740_MMC + +struct jz4740_mmc_platform_data { + int gpio_power; + int gpio_card_detect; + int gpio_read_only; + unsigned card_detect_active_low:1; + unsigned read_only_active_low:1; + unsigned power_active_low:1; + + unsigned data_1bit:1; +}; + +#endif diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index f06d06e..d25e22c 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -432,3 +432,12 @@ config MMC_SH_MMCIF This selects the MMC Host Interface controler (MMCIF). This driver supports MMCIF in sh7724/sh7757/sh7372. + +config MMC_JZ4740 + tristate "JZ4740 SD/Multimedia Card Interface support" + depends on MACH_JZ4740 + help + This selects support for the SD/MMC controller on Ingenic JZ4740 + SoCs. + If you have a board based on such a SoC and with a SD/MMC slot, + say Y or M here. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index e30c2ee..f4e53c9 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MMC_CB710) += cb710-mmc.o obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o +obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o sdhci-of-y := sdhci-of-core.o diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c new file mode 100644 index 0000000..82a449a --- /dev/null +++ b/drivers/mmc/host/jz4740_mmc.c @@ -0,0 +1,1024 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 SD/MMC controller driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#define JZ_REG_MMC_STRPCL 0x00 +#define JZ_REG_MMC_STATUS 0x04 +#define JZ_REG_MMC_CLKRT 0x08 +#define JZ_REG_MMC_CMDAT 0x0C +#define JZ_REG_MMC_RESTO 0x10 +#define JZ_REG_MMC_RDTO 0x14 +#define JZ_REG_MMC_BLKLEN 0x18 +#define JZ_REG_MMC_NOB 0x1C +#define JZ_REG_MMC_SNOB 0x20 +#define JZ_REG_MMC_IMASK 0x24 +#define JZ_REG_MMC_IREG 0x28 +#define JZ_REG_MMC_CMD 0x2C +#define JZ_REG_MMC_ARG 0x30 +#define JZ_REG_MMC_RESP_FIFO 0x34 +#define JZ_REG_MMC_RXFIFO 0x38 +#define JZ_REG_MMC_TXFIFO 0x3C + +#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) +#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) +#define JZ_MMC_STRPCL_START_READWAIT BIT(5) +#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) +#define JZ_MMC_STRPCL_RESET BIT(3) +#define JZ_MMC_STRPCL_START_OP BIT(2) +#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) +#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) +#define JZ_MMC_STRPCL_CLOCK_START BIT(1) + + +#define JZ_MMC_STATUS_IS_RESETTING BIT(15) +#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) +#define JZ_MMC_STATUS_PRG_DONE BIT(13) +#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) +#define JZ_MMC_STATUS_END_CMD_RES BIT(11) +#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) +#define JZ_MMC_STATUS_IS_READWAIT BIT(9) +#define JZ_MMC_STATUS_CLK_EN BIT(8) +#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) +#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) +#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) +#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) +#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) +#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) +#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) +#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) + +#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) +#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) + + +#define JZ_MMC_CMDAT_IO_ABORT BIT(11) +#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) +#define JZ_MMC_CMDAT_DMA_EN BIT(8) +#define JZ_MMC_CMDAT_INIT BIT(7) +#define JZ_MMC_CMDAT_BUSY BIT(6) +#define JZ_MMC_CMDAT_STREAM BIT(5) +#define JZ_MMC_CMDAT_WRITE BIT(4) +#define JZ_MMC_CMDAT_DATA_EN BIT(3) +#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) +#define JZ_MMC_CMDAT_RSP_R1 1 +#define JZ_MMC_CMDAT_RSP_R2 2 +#define JZ_MMC_CMDAT_RSP_R3 3 + +#define JZ_MMC_IRQ_SDIO BIT(7) +#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) +#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) +#define JZ_MMC_IRQ_END_CMD_RES BIT(2) +#define JZ_MMC_IRQ_PRG_DONE BIT(1) +#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) + + +#define JZ_MMC_CLK_RATE 24000000 + +enum jz4740_mmc_state { + JZ4740_MMC_STATE_READ_RESPONSE, + JZ4740_MMC_STATE_TRANSFER_DATA, + JZ4740_MMC_STATE_SEND_STOP, + JZ4740_MMC_STATE_DONE, +}; + +struct jz4740_mmc_host { + struct mmc_host *mmc; + struct platform_device *pdev; + struct jz4740_mmc_platform_data *pdata; + struct clk *clk; + + int irq; + int card_detect_irq; + + struct resource *mem; + void __iomem *base; + struct mmc_request *req; + struct mmc_command *cmd; + + unsigned long waiting; + + uint32_t cmdat; + + uint16_t irq_mask; + + spinlock_t lock; + + struct timer_list timeout_timer; + struct sg_mapping_iter miter; + enum jz4740_mmc_state state; +}; + +static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, + unsigned int irq, bool enabled) +{ + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + if (enabled) + host->irq_mask &= ~irq; + else + host->irq_mask |= irq; + spin_unlock_irqrestore(&host->lock, flags); + + writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK); +} + +static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, + bool start_transfer) +{ + uint16_t val = JZ_MMC_STRPCL_CLOCK_START; + + if (start_transfer) + val |= JZ_MMC_STRPCL_START_OP; + + writew(val, host->base + JZ_REG_MMC_STRPCL); +} + +static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) +{ + uint32_t status; + unsigned int timeout = 1000; + + writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); + do { + status = readl(host->base + JZ_REG_MMC_STATUS); + } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); +} + +static void jz4740_mmc_reset(struct jz4740_mmc_host *host) +{ + uint32_t status; + unsigned int timeout = 1000; + + writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); + udelay(10); + do { + status = readl(host->base + JZ_REG_MMC_STATUS); + } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); +} + +static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) +{ + struct mmc_request *req; + + req = host->req; + host->req = NULL; + + mmc_request_done(host->mmc, req); +} +static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, + unsigned int irq) +{ + unsigned int timeout = 1000; + uint16_t status; + + do { + status = readw(host->base + JZ_REG_MMC_IREG); + } while (!(status & irq) && --timeout); + + if (timeout == 0) { + set_bit(0, &host->waiting); + mod_timer(&host->timeout_timer, jiffies + 5*HZ); + jz4740_mmc_set_irq_enabled(host, irq, true); + return true; + } + + return false; +} + +static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + int status; + + status = readl(host->base + JZ_REG_MMC_STATUS); + if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { + if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { + host->req->cmd->error = -ETIMEDOUT; + data->error = -ETIMEDOUT; + } else { + host->req->cmd->error = -EIO; + data->error = -EIO; + } + } +} + +static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + struct sg_mapping_iter *miter = &host->miter; + uint32_t *buf; + bool timeout; + size_t i, j; + + while (sg_miter_next(miter)) { + buf = miter->addr; + i = miter->length / 4; + j = i / 8; + i = i & 0x7; + while (j) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + writel(buf[0], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[1], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[2], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[3], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[4], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[5], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[6], host->base + JZ_REG_MMC_TXFIFO); + writel(buf[7], host->base + JZ_REG_MMC_TXFIFO); + buf += 8; + --j; + } + if (unlikely(i)) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + while (i) { + writel(*buf, host->base + JZ_REG_MMC_TXFIFO); + ++buf; + --i; + } + } + data->bytes_xfered += miter->length; + } + sg_miter_stop(miter); + + return false; + +poll_timeout: + miter->consumed = (void *)buf - miter->addr; + data->bytes_xfered += miter->consumed; + sg_miter_stop(miter); + + return true; +} + +static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + struct sg_mapping_iter *miter = &host->miter; + uint32_t *buf; + uint32_t d; + uint16_t status; + size_t i, j; + unsigned int timeout; + + while (sg_miter_next(miter)) { + buf = miter->addr; + i = miter->length; + j = i / 32; + i = i & 0x1f; + while (j) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + buf[0] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[1] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[2] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[3] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[4] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[5] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[6] = readl(host->base + JZ_REG_MMC_RXFIFO); + buf[7] = readl(host->base + JZ_REG_MMC_RXFIFO); + + buf += 8; + --j; + } + + if (unlikely(i)) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + while (i >= 4) { + *buf++ = readl(host->base + JZ_REG_MMC_RXFIFO); + i -= 4; + } + if (unlikely(i > 0)) { + d = readl(host->base + JZ_REG_MMC_RXFIFO); + memcpy(buf, &d, i); + } + } + data->bytes_xfered += miter->length; + + /* This can go away once MIPS implements + * flush_kernel_dcache_page */ + flush_dcache_page(miter->page); + } + sg_miter_stop(miter); + + /* For whatever reason there is sometime one word more in the fifo then + * requested */ + timeout = 1000; + status = readl(host->base + JZ_REG_MMC_STATUS); + while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { + d = readl(host->base + JZ_REG_MMC_RXFIFO); + status = readl(host->base + JZ_REG_MMC_STATUS); + } + + return false; + +poll_timeout: + miter->consumed = (void *)buf - miter->addr; + data->bytes_xfered += miter->consumed; + sg_miter_stop(miter); + + return true; +} + +static void jz4740_mmc_timeout(unsigned long data) +{ + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data; + + if (!test_and_clear_bit(0, &host->waiting)) + return; + + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); + + host->req->cmd->error = -ETIMEDOUT; + jz4740_mmc_request_done(host); +} + +static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, + struct mmc_command *cmd) +{ + int i; + uint16_t tmp; + + if (cmd->flags & MMC_RSP_136) { + tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO); + for (i = 0; i < 4; ++i) { + cmd->resp[i] = tmp << 24; + tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO); + cmd->resp[i] |= tmp << 8; + tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO); + cmd->resp[i] |= tmp >> 8; + } + } else { + cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24; + cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8; + cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff; + } +} + +static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, + struct mmc_command *cmd) +{ + uint32_t cmdat = host->cmdat; + + host->cmdat &= ~JZ_MMC_CMDAT_INIT; + jz4740_mmc_clock_disable(host); + + host->cmd = cmd; + + if (cmd->flags & MMC_RSP_BUSY) + cmdat |= JZ_MMC_CMDAT_BUSY; + + switch (mmc_resp_type(cmd)) { + case MMC_RSP_R1B: + case MMC_RSP_R1: + cmdat |= JZ_MMC_CMDAT_RSP_R1; + break; + case MMC_RSP_R2: + cmdat |= JZ_MMC_CMDAT_RSP_R2; + break; + case MMC_RSP_R3: + cmdat |= JZ_MMC_CMDAT_RSP_R3; + break; + default: + break; + } + + if (cmd->data) { + cmdat |= JZ_MMC_CMDAT_DATA_EN; + if (cmd->data->flags & MMC_DATA_WRITE) + cmdat |= JZ_MMC_CMDAT_WRITE; + if (cmd->data->flags & MMC_DATA_STREAM) + cmdat |= JZ_MMC_CMDAT_STREAM; + + writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); + writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); + } + + writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); + writel(cmd->arg, host->base + JZ_REG_MMC_ARG); + writel(cmdat, host->base + JZ_REG_MMC_CMDAT); + + jz4740_mmc_clock_enable(host, 1); +} + +static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) +{ + struct mmc_command *cmd = host->req->cmd; + struct mmc_data *data = cmd->data; + int direction; + + if (cmd->data->flags & MMC_DATA_READ) + direction = SG_MITER_TO_SG; + else + direction = SG_MITER_FROM_SG; + + sg_miter_start(&host->miter, data->sg, data->sg_len, direction); +} + + +static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) +{ + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; + struct mmc_command *cmd = host->req->cmd; + struct mmc_request *req = host->req; + bool timedout = false; + + if (cmd->error) + host->state = JZ4740_MMC_STATE_DONE; + + switch (host->state) { + case JZ4740_MMC_STATE_READ_RESPONSE: + if (cmd->flags & MMC_RSP_PRESENT) + jz4740_mmc_read_response(host, cmd); + + if (!cmd->data) + break; + + jz_mmc_prepare_data_transfer(host); + + case JZ4740_MMC_STATE_TRANSFER_DATA: + if (cmd->data->flags & MMC_DATA_READ) + timedout = jz4740_mmc_read_data(host, cmd->data); + else + timedout = jz4740_mmc_write_data(host, cmd->data); + + if (unlikely(timedout)) { + host->state = JZ4740_MMC_STATE_TRANSFER_DATA; + break; + } + + jz4740_mmc_transfer_check_state(host, cmd->data); + + timedout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); + if (unlikely(timedout)) { + host->state = JZ4740_MMC_STATE_SEND_STOP; + break; + } + writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG); + + case JZ4740_MMC_STATE_SEND_STOP: + if (!req->stop) + break; + + jz4740_mmc_send_command(host, req->stop); + + timedout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE); + if (timedout) { + host->state = JZ4740_MMC_STATE_DONE; + break; + } + case JZ4740_MMC_STATE_DONE: + break; + } + + if (!timedout) + jz4740_mmc_request_done(host); + + return IRQ_HANDLED; +} + +static irqreturn_t jz_mmc_irq(int irq, void *devid) +{ + struct jz4740_mmc_host *host = devid; + uint16_t irq_reg, status, tmp; + + irq_reg = readw(host->base + JZ_REG_MMC_IREG); + + tmp = irq_reg; + irq_reg &= ~host->irq_mask; + + tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | + JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); + + if (tmp != irq_reg) + writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG); + + if (irq_reg & JZ_MMC_IRQ_SDIO) { + writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG); + mmc_signal_sdio_irq(host->mmc); + irq_reg &= ~JZ_MMC_IRQ_SDIO; + } + + if (host->req && host->cmd && irq_reg) { + if (test_and_clear_bit(0, &host->waiting)) { + del_timer(&host->timeout_timer); + + status = readl(host->base + JZ_REG_MMC_STATUS); + + if (status & JZ_MMC_STATUS_TIMEOUT_RES) { + host->cmd->error = -ETIMEDOUT; + } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { + host->cmd->error = -EIO; + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | + JZ_MMC_STATUS_CRC_WRITE_ERROR)) { + host->cmd->data->error = -EIO; + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | + JZ_MMC_STATUS_CRC_WRITE_ERROR)) { + host->cmd->data->error = -EIO; + } + + jz4740_mmc_set_irq_enabled(host, irq_reg, false); + writew(irq_reg, host->base + JZ_REG_MMC_IREG); + + return IRQ_WAKE_THREAD; + } + } + + return IRQ_HANDLED; +} + +static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) +{ + int div = 0; + int real_rate; + + jz4740_mmc_clock_disable(host); + clk_set_rate(host->clk, JZ_MMC_CLK_RATE); + + real_rate = clk_get_rate(host->clk); + + while (real_rate > rate && div < 7) { + ++div; + real_rate >>= 1; + } + + writew(div, host->base + JZ_REG_MMC_CLKRT); + return real_rate; +} + +static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + + host->req = req; + + writew(0xffff, host->base + JZ_REG_MMC_IREG); + + writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG); + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); + + host->state = JZ4740_MMC_STATE_READ_RESPONSE; + set_bit(0, &host->waiting); + mod_timer(&host->timeout_timer, jiffies + 5*HZ); + jz4740_mmc_send_command(host, req->cmd); +} + +static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (ios->clock) + jz4740_mmc_set_clock_rate(host, ios->clock); + + switch (ios->power_mode) { + case MMC_POWER_UP: + jz4740_mmc_reset(host); + if (gpio_is_valid(host->pdata->gpio_power)) + gpio_set_value(host->pdata->gpio_power, + !host->pdata->power_active_low); + host->cmdat |= JZ_MMC_CMDAT_INIT; + clk_enable(host->clk); + break; + case MMC_POWER_ON: + break; + default: + if (gpio_is_valid(host->pdata->gpio_power)) + gpio_set_value(host->pdata->gpio_power, + host->pdata->power_active_low); + clk_disable(host->clk); + break; + } + + switch (ios->bus_width) { + case MMC_BUS_WIDTH_1: + host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT; + break; + case MMC_BUS_WIDTH_4: + host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; + break; + default: + break; + } +} + +static int jz4740_mmc_get_ro(struct mmc_host *mmc) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (!gpio_is_valid(host->pdata->gpio_read_only)) + return -ENOSYS; + + return gpio_get_value(host->pdata->gpio_read_only) ^ + host->pdata->read_only_active_low; +} + +static int jz4740_mmc_get_cd(struct mmc_host *mmc) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (!gpio_is_valid(host->pdata->gpio_card_detect)) + return -ENOSYS; + + return gpio_get_value(host->pdata->gpio_card_detect) ^ + host->pdata->card_detect_active_low; +} + +static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid) +{ + struct jz4740_mmc_host *host = devid; + + mmc_detect_change(host->mmc, HZ / 2); + + return IRQ_HANDLED; +} + +static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); +} + +static const struct mmc_host_ops jz4740_mmc_ops = { + .request = jz4740_mmc_request, + .set_ios = jz4740_mmc_set_ios, + .get_ro = jz4740_mmc_get_ro, + .get_cd = jz4740_mmc_get_cd, + .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, +}; + +static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = { + JZ_GPIO_BULK_PIN(MSC_CMD), + JZ_GPIO_BULK_PIN(MSC_CLK), + JZ_GPIO_BULK_PIN(MSC_DATA0), + JZ_GPIO_BULK_PIN(MSC_DATA1), + JZ_GPIO_BULK_PIN(MSC_DATA2), + JZ_GPIO_BULK_PIN(MSC_DATA3), +}; + +static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio, + const char *name, bool output, int value) +{ + int ret; + + if (!gpio_is_valid(gpio)) + return 0; + + ret = gpio_request(gpio, name); + if (ret) { + dev_err(dev, "Failed to request %s gpio: %d\n", name, ret); + return ret; + } + + if (output) + gpio_direction_output(gpio, value); + else + gpio_direction_input(gpio); + + return 0; +} + +static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev) +{ + int ret; + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (!pdata) + return 0; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect, + "MMC detect change", false, 0); + if (ret) + goto err; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only, + "MMC read only", false, 0); + if (ret) + goto err_free_gpio_card_detect; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power, + "MMC read only", true, pdata->power_active_low); + if (ret) + goto err_free_gpio_read_only; + + return 0; + +err_free_gpio_read_only: + if (gpio_is_valid(pdata->gpio_read_only)) + gpio_free(pdata->gpio_read_only); +err_free_gpio_card_detect: + if (gpio_is_valid(pdata->gpio_card_detect)) + gpio_free(pdata->gpio_card_detect); +err: + return ret; +} + +static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev, + struct jz4740_mmc_host *host) +{ + int ret; + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (gpio_is_valid(pdata->gpio_card_detect)) + return 0; + + host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect); + + if (host->card_detect_irq < 0) { + dev_warn(&pdev->dev, "Failed to get card detect irq\n"); + return 0; + } + return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "MMC card detect", host); + + + return ret; +} + +static void jz4740_mmc_free_gpios(struct platform_device *pdev) +{ + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (!pdata) + return; + + if (gpio_is_valid(pdata->gpio_power)) + gpio_free(pdata->gpio_power); + if (gpio_is_valid(pdata->gpio_read_only)) + gpio_free(pdata->gpio_read_only); + if (gpio_is_valid(pdata->gpio_card_detect)) + gpio_free(pdata->gpio_card_detect); +} + +static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host) +{ + size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins); + if (host->pdata && host->pdata->data_1bit) + num_pins -= 3; + + return num_pins; +} + +static int __devinit jz4740_mmc_probe(struct platform_device* pdev) +{ + int ret; + struct mmc_host *mmc; + struct jz4740_mmc_host *host; + struct jz4740_mmc_platform_data *pdata; + + pdata = pdev->dev.platform_data; + + mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); + if (!mmc) { + dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); + return -ENOMEM; + } + + host = mmc_priv(mmc); + host->pdata = pdata; + + host->irq = platform_get_irq(pdev, 0); + if (host->irq < 0) { + ret = host->irq; + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); + goto err_free_host; + } + + host->clk = clk_get(&pdev->dev, "mmc"); + if (!host->clk) { + ret = -ENOENT; + dev_err(&pdev->dev, "Failed to get mmc clock\n"); + goto err_free_host; + } + + host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!host->mem) { + ret = -ENOENT; + dev_err(&pdev->dev, "Failed to get base platform memory\n"); + goto err_clk_put; + } + + host->mem = request_mem_region(host->mem->start, + resource_size(host->mem), pdev->name); + if (!host->mem) { + ret = -EBUSY; + dev_err(&pdev->dev, "Failed to request base memory region\n"); + goto err_clk_put; + } + + host->base = ioremap_nocache(host->mem->start, resource_size(host->mem)); + if (!host->base) { + ret = -EBUSY; + dev_err(&pdev->dev, "Failed to ioremap base memory\n"); + goto err_release_mem_region; + } + + ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + if (ret) { + dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret); + goto err_iounmap; + } + + ret = jz4740_mmc_request_gpios(pdev); + if (ret) + goto err_gpio_bulk_free; + + mmc->ops = &jz4740_mmc_ops; + mmc->f_min = JZ_MMC_CLK_RATE / 128; + mmc->f_max = JZ_MMC_CLK_RATE; + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA; + mmc->caps |= MMC_CAP_SDIO_IRQ; + + mmc->max_blk_size = (1 << 10) - 1; + mmc->max_blk_count = (1 << 15) - 1; + mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; + + mmc->max_phys_segs = 128; + mmc->max_hw_segs = 128; + mmc->max_seg_size = mmc->max_req_size; + + host->mmc = mmc; + host->pdev = pdev; + spin_lock_init(&host->lock); + host->irq_mask = 0xffff; + + ret = jz4740_mmc_request_cd_irq(pdev, host); + if (ret) { + dev_err(&pdev->dev, "Failed to request card detect irq\n"); + goto err_free_gpios; + } + + ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, + dev_name(&pdev->dev), host); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); + goto err_free_card_detect_irq; + } + + jz4740_mmc_reset(host); + jz4740_mmc_clock_disable(host); + setup_timer(&host->timeout_timer, jz4740_mmc_timeout, + (unsigned long)host); + /* It is not important when it times out, it just needs to timeout. */ + set_timer_slack(&host->timeout_timer, HZ); + + platform_set_drvdata(pdev, host); + ret = mmc_add_host(mmc); + + if (ret) { + dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); + goto err_free_irq; + } + dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); + + return 0; + +err_free_irq: + free_irq(host->irq, host); +err_free_card_detect_irq: + if (host->card_detect_irq >= 0) + free_irq(host->card_detect_irq, host); +err_free_gpios: + jz4740_mmc_free_gpios(pdev); +err_gpio_bulk_free: + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); +err_iounmap: + iounmap(host->base); +err_release_mem_region: + release_mem_region(host->mem->start, resource_size(host->mem)); +err_clk_put: + clk_put(host->clk); +err_free_host: + platform_set_drvdata(pdev, NULL); + mmc_free_host(mmc); + + return ret; +} + +static int __devexit jz4740_mmc_remove(struct platform_device *pdev) +{ + struct jz4740_mmc_host *host = platform_get_drvdata(pdev); + + del_timer_sync(&host->timeout_timer); + jz4740_mmc_set_irq_enabled(host, 0xff, false); + jz4740_mmc_reset(host); + + mmc_remove_host(host->mmc); + + free_irq(host->irq, host); + if (host->card_detect_irq >= 0) + free_irq(host->card_detect_irq, host); + + jz4740_mmc_free_gpios(pdev); + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + iounmap(host->base); + release_mem_region(host->mem->start, resource_size(host->mem)); + + clk_put(host->clk); + + platform_set_drvdata(pdev, NULL); + mmc_free_host(host->mmc); + + return 0; +} + +#ifdef CONFIG_PM + +static int jz4740_mmc_suspend(struct device *dev) +{ + struct jz4740_mmc_host *host = dev_get_drvdata(dev); + + mmc_suspend_host(host->mmc); + + jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + return 0; +} + +static int jz4740_mmc_resume(struct device *dev) +{ + struct jz4740_mmc_host *host = dev_get_drvdata(dev); + + jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + mmc_resume_host(host->mmc); + + return 0; +} + +const struct dev_pm_ops jz4740_mmc_pm_ops = { + .suspend = jz4740_mmc_suspend, + .resume = jz4740_mmc_resume, + .poweroff = jz4740_mmc_suspend, + .restore = jz4740_mmc_resume, +}; + +#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) +#else +#define JZ4740_MMC_PM_OPS NULL +#endif + +static struct platform_driver jz4740_mmc_driver = { + .probe = jz4740_mmc_probe, + .remove = __devexit_p(jz4740_mmc_remove), + .driver = { + .name = "jz4740-mmc", + .owner = THIS_MODULE, + .pm = JZ4740_MMC_PM_OPS, + }, +}; + +static int __init jz4740_mmc_init(void) +{ + return platform_driver_register(&jz4740_mmc_driver); +} +module_init(jz4740_mmc_init); + +static void __exit jz4740_mmc_exit(void) +{ + platform_driver_unregister(&jz4740_mmc_driver); +} +module_exit(jz4740_mmc_exit); + +MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lars-Peter Clausen "); -- 1.5.6.5 From joe@perches.com Tue Jul 13 00:45:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jul 2010 00:45:23 +0200 (CEST) Received: from mail.perches.com ([173.55.12.10]:1846 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492382Ab0GLWpU (ORCPT ); Tue, 13 Jul 2010 00:45:20 +0200 Received: from [192.168.1.151] (Joe-Laptop.home [192.168.1.151]) by mail.perches.com (Postfix) with ESMTP id 8511424368; Mon, 12 Jul 2010 15:45:08 -0700 (PDT) Subject: Re: [PATCH v5] MMC: Add JZ4740 mmc driver From: Joe Perches To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton , Matt Fleming , linux-mmc@vger.kernel.org In-Reply-To: <1278973245-25451-1-git-send-email-lars@metafoo.de> References: <1278970413-21617-1-git-send-email-lars@metafoo.de> <1278973245-25451-1-git-send-email-lars@metafoo.de> Content-Type: text/plain; charset="UTF-8" Date: Mon, 12 Jul 2010 15:45:10 -0700 Message-ID: <1278974710.1501.317.camel@Joe-Laptop.home> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27381 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips On Tue, 2010-07-13 at 00:20 +0200, Lars-Peter Clausen wrote: > This patch adds support for the mmc controller on JZ4740 SoCs. > +static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, > + struct mmc_data *data) > +{ > + struct sg_mapping_iter *miter = &host->miter; > + uint32_t *buf; > + bool timeout; > + size_t i, j; > + > + while (sg_miter_next(miter)) { > + buf = miter->addr; > + i = miter->length / 4; > + j = i / 8; > + i = i & 0x7; > + while (j) { > + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); > + if (unlikely(timeout)) > + goto poll_timeout; > + > + writel(buf[0], host->base + JZ_REG_MMC_TXFIFO); Perhaps it'd be better to use a temporary for host->base + JZ_REG_MMC_TXFIFO > + writel(buf[1], host->base + JZ_REG_MMC_TXFIFO); > + writel(buf[2], host->base + JZ_REG_MMC_TXFIFO); > + writel(buf[3], host->base + JZ_REG_MMC_TXFIFO); > + writel(buf[4], host->base + JZ_REG_MMC_TXFIFO); > + writel(buf[5], host->base + JZ_REG_MMC_TXFIFO); > + writel(buf[6], host->base + JZ_REG_MMC_TXFIFO); > + writel(buf[7], host->base + JZ_REG_MMC_TXFIFO); > + buf += 8; > + --j; > + } > + if (unlikely(i)) { > + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); > + if (unlikely(timeout)) > + goto poll_timeout; > + > + while (i) { > + writel(*buf, host->base + JZ_REG_MMC_TXFIFO); > + ++buf; > + --i; > + } > + } > + data->bytes_xfered += miter->length; > + } From lars@metafoo.de Tue Jul 13 01:46:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jul 2010 01:46:10 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:39004 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492023Ab0GLXqH (ORCPT ); Tue, 13 Jul 2010 01:46:07 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 518145EB; Tue, 13 Jul 2010 01:46:00 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id baup628Yss45; Tue, 13 Jul 2010 01:45:59 +0200 (CEST) Received: from [172.31.16.228] (d043121.adsl.hansenet.de [80.171.43.121]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id A47EC5EA; Tue, 13 Jul 2010 01:45:58 +0200 (CEST) Message-ID: <4C3BA927.3040307@metafoo.de> Date: Tue, 13 Jul 2010 01:45:43 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Joe Perches CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton , Matt Fleming , linux-mmc@vger.kernel.org Subject: Re: [PATCH v5] MMC: Add JZ4740 mmc driver References: <1278970413-21617-1-git-send-email-lars@metafoo.de> <1278973245-25451-1-git-send-email-lars@metafoo.de> <1278974710.1501.317.camel@Joe-Laptop.home> In-Reply-To: <1278974710.1501.317.camel@Joe-Laptop.home> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27382 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips Hi Joe Perches wrote: > On Tue, 2010-07-13 at 00:20 +0200, Lars-Peter Clausen wrote: >> This patch adds support for the mmc controller on JZ4740 SoCs. >> +static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, >> + struct mmc_data *data) >> +{ >> + struct sg_mapping_iter *miter = &host->miter; >> + uint32_t *buf; >> + bool timeout; >> + size_t i, j; >> + >> + while (sg_miter_next(miter)) { >> + buf = miter->addr; >> + i = miter->length / 4; >> + j = i / 8; >> + i = i & 0x7; >> + while (j) { >> + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); >> + if (unlikely(timeout)) >> + goto poll_timeout; >> + >> + writel(buf[0], host->base + JZ_REG_MMC_TXFIFO); > > Perhaps it'd be better to use a temporary for > host->base + JZ_REG_MMC_TXFIFO Hm, indeed host->addr is reloaded before each write. > >> + writel(buf[1], host->base + JZ_REG_MMC_TXFIFO); >> + writel(buf[2], host->base + JZ_REG_MMC_TXFIFO); >> + writel(buf[3], host->base + JZ_REG_MMC_TXFIFO); >> + writel(buf[4], host->base + JZ_REG_MMC_TXFIFO); >> + writel(buf[5], host->base + JZ_REG_MMC_TXFIFO); >> + writel(buf[6], host->base + JZ_REG_MMC_TXFIFO); >> + writel(buf[7], host->base + JZ_REG_MMC_TXFIFO); >> + buf += 8; >> + --j; >> + } >> + if (unlikely(i)) { >> + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); >> + if (unlikely(timeout)) >> + goto poll_timeout; >> + >> + while (i) { >> + writel(*buf, host->base + JZ_REG_MMC_TXFIFO); >> + ++buf; >> + --i; >> + } >> + } >> + data->bytes_xfered += miter->length; >> + } > > Thanks for reviewing - Lars From sameo@linux.intel.com Wed Jul 14 11:19:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 11:19:58 +0200 (CEST) Received: from mga09.intel.com ([134.134.136.24]:65001 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491044Ab0GNJTs (ORCPT ); Wed, 14 Jul 2010 11:19:48 +0200 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 14 Jul 2010 02:18:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.55,201,1278313200"; d="scan'208";a="535382465" Received: from unknown (HELO sortiz-mobl) ([10.255.17.103]) by orsmga002.jf.intel.com with ESMTP; 14 Jul 2010 02:20:10 -0700 Date: Wed, 14 Jul 2010 11:19:35 +0200 From: Samuel Ortiz To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] MFD: Add JZ4740 ADC driver Message-ID: <20100714091934.GA2771@sortiz-mobl> References: <1276924111-11158-23-git-send-email-lars@metafoo.de> <1278899288-14921-1-git-send-email-lars@metafoo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1278899288-14921-1-git-send-email-lars@metafoo.de> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27383 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sameo@linux.intel.com Precedence: bulk X-list: linux-mips Hi Lars, On Mon, Jul 12, 2010 at 03:48:08AM +0200, Lars-Peter Clausen wrote: > This patch adds a MFD driver for the JZ4740 ADC unit. The driver is used to > demultiplex IRQs and synchronize access to shared registers between the battery, > hwmon and (future) touchscreen driver. > > Signed-off-by: Lars-Peter Clausen > Cc: Samuel Ortiz Patch applied, many thanks. Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ From wg@denx.de Wed Jul 14 11:59:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 11:59:15 +0200 (CEST) Received: from mail-out.m-online.net ([212.18.0.10]:38221 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492034Ab0GNJ7I (ORCPT ); Wed, 14 Jul 2010 11:59:08 +0200 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 39A6D1C00561 for ; Wed, 14 Jul 2010 11:59:07 +0200 (CEST) X-Auth-Info: wDyYiDjdh0qRmINI4RFLfRg5U8FOMLl+DbDatL76y2M= Received: from mail.denx.de (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id A36941C001AE for ; Wed, 14 Jul 2010 11:59:07 +0200 (CEST) Received: from pollux.denx.de (pollux [192.168.1.1]) by mail.denx.de (Postfix) with ESMTP id 83224410C03C for ; Wed, 14 Jul 2010 11:59:07 +0200 (CEST) Received: by pollux.denx.de (Postfix, from userid 504) id 1DE9E100C6DEF; Wed, 14 Jul 2010 11:59:07 +0200 (CEST) From: Wolfgang Grandegger To: linux-mips@linux-mips.org Cc: Wolfgang Grandegger Subject: [PATCH] mips/alchemy: add basic support for the GPR board Date: Wed, 14 Jul 2010 11:59:07 +0200 Message-Id: <1279101547-14498-1-git-send-email-wg@grandegger.com> X-Mailer: git-send-email 1.6.2.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27384 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips From: Wolfgang Grandegger This patch adds basic support for the General Purpose Router (GPR) board from Trapeze ITS. Signed-off-by: Wolfgang Grandegger --- arch/mips/Makefile | 6 + arch/mips/alchemy/Kconfig | 9 + arch/mips/alchemy/gpr/Makefile | 11 + arch/mips/alchemy/gpr/board_setup.c | 97 ++ arch/mips/alchemy/gpr/init.c | 63 + arch/mips/alchemy/gpr/platform.c | 185 +++ arch/mips/configs/gpr_defconfig | 2062 ++++++++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/au1000.h | 2 + 8 files changed, 2435 insertions(+), 0 deletions(-) create mode 100644 arch/mips/alchemy/gpr/Makefile create mode 100644 arch/mips/alchemy/gpr/board_setup.c create mode 100644 arch/mips/alchemy/gpr/init.c create mode 100644 arch/mips/alchemy/gpr/platform.c create mode 100644 arch/mips/configs/gpr_defconfig diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0b9c01a..6b81b9f 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -325,6 +325,12 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 +# +# Trapeze ITS GRP board +# +libs-$(CONFIG_MIPS_GPR) += arch/mips/alchemy/gpr/ +load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 + # must be last for Alchemy systems for GPIO to work properly cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index df3b1a7..c9830e0 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -128,6 +128,15 @@ config MIPS_XXS1500 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK +config MIPS_GPR + bool "Trapeze ITS GPR board" + select SOC_AU1550 + select HW_HAS_PCI + select DMA_NONCOHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + endchoice config SOC_AU1000 diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile new file mode 100644 index 0000000..d65c993 --- /dev/null +++ b/arch/mips/alchemy/gpr/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2003 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# +# Makefile for Trapeze ITS GPR board. +# + +lib-y := init.o board_setup.o +obj-y := platform.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c new file mode 100644 index 0000000..dc8c55d --- /dev/null +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -0,0 +1,97 @@ +/* + * Copyright 2010 Wolfgang Grandegger + * + * Copyright 2000-2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +char irq_tab_alchemy[][5] __initdata = { + [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, +}; + +static void gpr_reset(char *c) +{ + /* switch System-LED to orange (red# and green# on) */ + alchemy_gpio_direction_output(4, 0); + alchemy_gpio_direction_output(5, 0); + + /* trigger watchdog to reset board in 200ms */ + printk(KERN_EMERG "Triggering watchdog soft reset...\n"); + raw_local_irq_disable(); + alchemy_gpio_direction_output(1, 0); + udelay(1); + alchemy_gpio_set_value(1, 1); + while (1) + asm volatile (".set mips3 ; wait ; .set mips0"); +} + +static void gpr_power_off(void) +{ + printk(KERN_ALERT "It's now safe to remove power\n"); + while (1) + asm volatile (".set mips3 ; wait ; .set mips0"); +} + +void __init board_setup(void) +{ + printk(KERN_INFO "Tarpeze ITS GPR board\n"); + + pm_power_off = gpr_power_off; + _machine_halt = gpr_power_off; + _machine_restart = gpr_reset; + + /* Enable UART3 */ + au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ + au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + /* Enable UART1 */ + au_writel(0x01, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ + au_writel(0x03, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + + /* Take away Reset of UMTS-card */ + alchemy_gpio_direction_output(215, 1); + +#ifdef CONFIG_PCI +#if defined(__MIPSEB__) + au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); +#else + au_writel(0xf, Au1500_PCI_CFG); +#endif +#endif +} + +static int __init gpr_init_irq(void) +{ + return 0; +} +arch_initcall(gpr_init_irq); diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c new file mode 100644 index 0000000..f044f4c --- /dev/null +++ b/arch/mips/alchemy/gpr/init.c @@ -0,0 +1,63 @@ +/* + * Copyright 2010 Wolfgang Grandegger + * + * Copyright 2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include +#include + +#include + +const char *get_system_type(void) +{ + return "GPR"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(UART0_PHYS_ADDR, c); +} diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c new file mode 100644 index 0000000..3aed1dd --- /dev/null +++ b/arch/mips/alchemy/gpr/platform.c @@ -0,0 +1,185 @@ +/* + * GPR board platform device registration + * + * Copyright (C) 2010 Wolfgang Grandegger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Watchdog + */ +static struct resource gpr_wdt_resource[] = { + [0] = { + .start = 1, + .end = 1, + .name = "gpr-adm6320-wdt", + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device gpr_wdt_device = { + .name = "adm6320-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(gpr_wdt_resource), + .resource = gpr_wdt_resource, +}; + +/* + * FLASH + * + * 0x00000000-0x00200000 : "kernel" + * 0x00200000-0x00a00000 : "rootfs" + * 0x01d00000-0x01f00000 : "config" + * 0x01c00000-0x01d00000 : "yamon" + * 0x01d00000-0x01d40000 : "yamon env vars" + * 0x00000000-0x00a00000 : "kernel+rootfs" + */ +static struct mtd_partition gpr_mtd_partitions[] = { + { + .name = "kernel", + .size = 0x00200000, + .offset = 0, + }, + { + .name = "rootfs", + .size = 0x00800000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "config", + .size = 0x00200000, + .offset = 0x01d00000, + }, + { + .name = "yamon", + .size = 0x00100000, + .offset = 0x01c00000, + }, + { + .name = "yamon env vars", + .size = 0x00040000, + .offset = MTDPART_OFS_APPEND, + }, + { + .name = "kernel+rootfs", + .size = 0x00a00000, + .offset = 0, + }, +}; + +static struct physmap_flash_data gpr_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(gpr_mtd_partitions), + .parts = gpr_mtd_partitions, +}; + +static struct resource gpr_mtd_resource = { + .start = 0x1e000000, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gpr_mtd_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &gpr_flash_data, + }, + .num_resources = 1, + .resource = &gpr_mtd_resource, +}; + +/* + * LEDs + */ +static struct gpio_led gpr_gpio_leds[] = { + { /* green */ + .name = "green", + .gpio = 4, + .active_low = 1, + .default_trigger = "none", + }, + { /* red */ + .name = "red", + .gpio = 5, + .active_low = 1, + .default_trigger = "none", + } +}; + +static struct gpio_led_platform_data gpr_led_data = { + .num_leds = ARRAY_SIZE(gpr_gpio_leds), + .leds = gpr_gpio_leds, +}; + +static struct platform_device gpr_led_devices = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpr_led_data, + } +}; + +/* + * I2C + */ +static struct i2c_gpio_platform_data gpr_i2c_data = { + .sda_pin = 209, + .sda_is_open_drain = 1, + .scl_pin = 210, + .scl_is_open_drain = 1, + .udelay = 2, /* ~100 kHz */ + .timeout = HZ, + }; + +static struct platform_device gpr_i2c_device = { + .name = "i2c-gpio", + .id = -1, + .dev.platform_data = &gpr_i2c_data, +}; + +static struct i2c_board_info gpr_i2c_info[] __initdata = { + { + I2C_BOARD_INFO("lm83", 0x18), + .type = "lm83" + } +}; + +static struct platform_device *gpr_devices[] __initdata = { + &gpr_wdt_device, + &gpr_mtd_device, + &gpr_i2c_device, + &gpr_led_devices, +}; + +static int __init gpr_dev_init(void) +{ + i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); + + return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices)); +} +device_initcall(gpr_dev_init); diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig new file mode 100644 index 0000000..8f0c968 --- /dev/null +++ b/arch/mips/configs/gpr_defconfig @@ -0,0 +1,2062 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35-rc4 +# Wed Jul 14 11:09:25 2010 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_AR7 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_ALCHEMY_GPIOINT_AU1000=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_MIPS_GPR=y +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y +CONFIG_LOONGSON_UART_BASE=y +# CONFIG_LOONGSON_MC146818 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_LED is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +# CONFIG_BRIDGE_EBT_NFLOG is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_CCID3_RTO=100 +CONFIG_IP_DCCP_TFRC_LIB=y +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=y +CONFIG_ATM_CLIP=y +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +# CONFIG_AX25_DAMA_SLAVE is not set +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=m +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=m +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_IFB is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_SMSC_PHY=m +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_MIPS_AU1X00_ENET=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +CONFIG_ATH_COMMON=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH5K=y +CONFIG_ATH5K_DEBUG=y +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_AR9170_USB is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set +# CONFIG_ZD1211RW is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WAN=y +CONFIG_LANMEDIA=m +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_PCI200SYN=m +CONFIG_WANXL=m +# CONFIG_PC300TOO is not set +CONFIG_FARSYNC=m +CONFIG_DSCC4=m +CONFIG_DSCC4_PCISYNC=y +CONFIG_DSCC4_PCI_RST=y +CONFIG_DLCI=m +CONFIG_DLCI_MAX=8 +CONFIG_WAN_ROUTER_DRIVERS=m +CONFIG_CYCLADES_SYNC=m +CONFIG_CYCLOMX_X25=y +CONFIG_LAPBETHER=m +CONFIG_X25_ASY=m +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +CONFIG_ATM_FIRESTREAM=m +CONFIG_ATM_ZATM=m +# CONFIG_ATM_ZATM_DEBUG is not set +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_AMBASSADOR=m +# CONFIG_ATM_AMBASSADOR_DEBUG is not set +CONFIG_ATM_HORIZON=m +# CONFIG_ATM_HORIZON_DEBUG is not set +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +# CONFIG_ATM_FORE200E_USE_TASKLET is not set +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +# CONFIG_ATM_SOLOS is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOATM=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_NET_FC=y +CONFIG_NETCONSOLE=m +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_AU1550 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_SCH is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +CONFIG_SENSORS_LM83=y +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +# CONFIG_SSB_B43_PCI_BRIDGE is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +# CONFIG_SSB_DRIVER_MIPS is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=y +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ATM is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_LKDTM is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw ip=auto" +# CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index a697661..836f516 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -994,6 +994,8 @@ enum soc_au1200_ints { #ifdef CONFIG_SOC_AU1550 #define UART0_ADDR 0xB1100000 +#define UART1_ADDR 0xB1200000 +#define UART3_ADDR 0xB1400000 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ #define USB_OHCI_LEN 0x00060000 -- 1.6.2.5 From manuel.lauss@googlemail.com Wed Jul 14 12:12:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 12:12:36 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:46455 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491161Ab0GNKMc convert rfc822-to-8bit (ORCPT ); Wed, 14 Jul 2010 12:12:32 +0200 Received: by iwn40 with SMTP id 40so7875527iwn.36 for ; Wed, 14 Jul 2010 03:12:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=LvEsJMwqbSTcg/hnFK5oDwPF2gJXX9w+PijR5kBwJTU=; b=C7SVrSQXwEH5WRq/mmO6GLW0tRCZ9l3lFGASTSSkZ+HubpY39mLQ6oqcD6bff1zcZx 4N7M079WoPGyZIjscJTCAVDXrQvkFUWNucQfASykNOt4eRhfko4XOaPlJAIeBPyyDNmQ 48sGU4wOlQycOvVinOPJOei3TlwKHdYTHPFg8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=n1QTzl6g6pRtcJIX97+69PvVUNusfBuN5g2RD7eSwIVO8wOk8k4NAK+kaVA0+Q6aMX 3qqWUk/mlfXptSYUBZPtP+WlEt5f6fznHglhRaNOSRvGCynxNXyzj7FI9mGrcPyuyoQc SYKhvCnSi5TgPFhXpEKmV+HIppVSlZ1d+vPzc= MIME-Version: 1.0 Received: by 10.231.182.204 with SMTP id cd12mr5558026ibb.101.1279102351400; Wed, 14 Jul 2010 03:12:31 -0700 (PDT) Received: by 10.231.182.207 with HTTP; Wed, 14 Jul 2010 03:12:31 -0700 (PDT) In-Reply-To: <1279101547-14498-1-git-send-email-wg@grandegger.com> References: <1279101547-14498-1-git-send-email-wg@grandegger.com> Date: Wed, 14 Jul 2010 12:12:31 +0200 Message-ID: Subject: Re: [PATCH] mips/alchemy: add basic support for the GPR board From: Manuel Lauss To: Wolfgang Grandegger Cc: linux-mips@linux-mips.org, Wolfgang Grandegger Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27385 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Wed, Jul 14, 2010 at 11:59 AM, Wolfgang Grandegger wrote: > From: Wolfgang Grandegger > > This patch adds basic support for the General Purpose Router (GPR) > board from Trapeze ITS. > > Signed-off-by: Wolfgang Grandegger > --- >  arch/mips/Makefile                         |    6 + >  arch/mips/alchemy/Kconfig                  |    9 + >  arch/mips/alchemy/gpr/Makefile             |   11 + >  arch/mips/alchemy/gpr/board_setup.c        |   97 ++ >  arch/mips/alchemy/gpr/init.c               |   63 + >  arch/mips/alchemy/gpr/platform.c           |  185 +++ >  arch/mips/configs/gpr_defconfig            | 2062 ++++++++++++++++++++++++++++ >  arch/mips/include/asm/mach-au1x00/au1000.h |    2 + >  8 files changed, 2435 insertions(+), 0 deletions(-) >  create mode 100644 arch/mips/alchemy/gpr/Makefile >  create mode 100644 arch/mips/alchemy/gpr/board_setup.c >  create mode 100644 arch/mips/alchemy/gpr/init.c >  create mode 100644 arch/mips/alchemy/gpr/platform.c >  create mode 100644 arch/mips/configs/gpr_defconfig > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index 0b9c01a..6b81b9f 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -325,6 +325,12 @@ load-$(CONFIG_MIPS_MTX1)   += 0xffffffff80100000 >  libs-$(CONFIG_MIPS_XXS1500)    += arch/mips/alchemy/xxs1500/ >  load-$(CONFIG_MIPS_XXS1500)    += 0xffffffff80100000 > > +# > +# Trapeze ITS GRP board > +# > +libs-$(CONFIG_MIPS_GPR)                += arch/mips/alchemy/gpr/ > +load-$(CONFIG_MIPS_GPR)                += 0xffffffff80100000 > + Have a look at the current mips-queue tree: theres a new way to hook up boards with Platform files. > --- a/arch/mips/include/asm/mach-au1x00/au1000.h > +++ b/arch/mips/include/asm/mach-au1x00/au1000.h > @@ -994,6 +994,8 @@ enum soc_au1200_ints { > >  #ifdef CONFIG_SOC_AU1550 >  #define UART0_ADDR             0xB1100000 > +#define UART1_ADDR             0xB1200000 > +#define UART3_ADDR             0xB1400000 Please don't add those back, I'm trying to get rid of them. Use something like "KSEG1ADDR(UART1_PHYS_ADDR)" in the init code where you enable uarts 1 and 3. Thanks! Manuel Lauss From wg@denx.de Wed Jul 14 15:47:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 15:47:38 +0200 (CEST) Received: from mail-out.m-online.net ([212.18.0.9]:41617 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491869Ab0GNNra (ORCPT ); Wed, 14 Jul 2010 15:47:30 +0200 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 210461C158AA for ; Wed, 14 Jul 2010 15:47:24 +0200 (CEST) X-Auth-Info: TveFK1N5JmZ8o1UWRJnWb680JHm0Oh59USSsxkHM3T0= Received: from mail.denx.de (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 5634B1C001EA for ; Wed, 14 Jul 2010 15:47:24 +0200 (CEST) Received: from pollux.denx.de (pollux [192.168.1.1]) by mail.denx.de (Postfix) with ESMTP id 3D6AF410C03C for ; Wed, 14 Jul 2010 15:47:24 +0200 (CEST) Received: by pollux.denx.de (Postfix, from userid 504) id E03B0100C6DEF; Wed, 14 Jul 2010 15:47:23 +0200 (CEST) From: Wolfgang Grandegger To: linux-mips@linux-mips.org Cc: Wolfgang Grandegger Subject: [PATCH v2] mips/alchemy: add basic support for the GPR board Date: Wed, 14 Jul 2010 15:47:23 +0200 Message-Id: <1279115243-11586-1-git-send-email-wg@grandegger.com> X-Mailer: git-send-email 1.6.2.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27386 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips From: Wolfgang Grandegger This patch adds basic support for the General Purpose Router (GPR) board from Trapeze ITS. Signed-off-by: Wolfgang Grandegger --- arch/mips/alchemy/Kconfig | 9 + arch/mips/alchemy/Platform | 5 + arch/mips/alchemy/gpr/Makefile | 8 + arch/mips/alchemy/gpr/board_setup.c | 100 ++ arch/mips/alchemy/gpr/init.c | 63 ++ arch/mips/alchemy/gpr/platform.c | 185 ++++ arch/mips/configs/gpr_defconfig | 2062 +++++++++++++++++++++++++++++++++++ 7 files changed, 2432 insertions(+), 0 deletions(-) create mode 100644 arch/mips/alchemy/gpr/Makefile create mode 100644 arch/mips/alchemy/gpr/board_setup.c create mode 100644 arch/mips/alchemy/gpr/init.c create mode 100644 arch/mips/alchemy/gpr/platform.c create mode 100644 arch/mips/configs/gpr_defconfig diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index df3b1a7..c9830e0 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -128,6 +128,15 @@ config MIPS_XXS1500 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK +config MIPS_GPR + bool "Trapeze ITS GPR board" + select SOC_AU1550 + select HW_HAS_PCI + select DMA_NONCOHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + endchoice config SOC_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 495cc9a..c64e3b7 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -100,6 +100,11 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 +# +# Trapeze ITS GRP board +# +platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/ +load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 # boards can specify their own in one of their include dirs. # If they do, placing this line here at the end will make sure the diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile new file mode 100644 index 0000000..1a3f214 --- /dev/null +++ b/arch/mips/alchemy/gpr/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2003 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# +# Makefile for Trapeze ITS GPR board. +# + +obj-y += init.o board_setup.o platform.o diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c new file mode 100644 index 0000000..4e68d76 --- /dev/null +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -0,0 +1,100 @@ +/* + * Copyright 2010 Wolfgang Grandegger + * + * Copyright 2000-2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR) +#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR) + +char irq_tab_alchemy[][5] __initdata = { + [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, +}; + +static void gpr_reset(char *c) +{ + /* switch System-LED to orange (red# and green# on) */ + alchemy_gpio_direction_output(4, 0); + alchemy_gpio_direction_output(5, 0); + + /* trigger watchdog to reset board in 200ms */ + printk(KERN_EMERG "Triggering watchdog soft reset...\n"); + raw_local_irq_disable(); + alchemy_gpio_direction_output(1, 0); + udelay(1); + alchemy_gpio_set_value(1, 1); + while (1) + asm volatile (".set mips3 ; wait ; .set mips0"); +} + +static void gpr_power_off(void) +{ + printk(KERN_ALERT "It's now safe to remove power\n"); + while (1) + asm volatile (".set mips3 ; wait ; .set mips0"); +} + +void __init board_setup(void) +{ + printk(KERN_INFO "Tarpeze ITS GPR board\n"); + + pm_power_off = gpr_power_off; + _machine_halt = gpr_power_off; + _machine_restart = gpr_reset; + + /* Enable UART3 */ + au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */ + au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + /* Enable UART1 */ + au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ + au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + + /* Take away Reset of UMTS-card */ + alchemy_gpio_direction_output(215, 1); + +#ifdef CONFIG_PCI +#if defined(__MIPSEB__) + au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); +#else + au_writel(0xf, Au1500_PCI_CFG); +#endif +#endif +} + +static int __init gpr_init_irq(void) +{ + return 0; +} +arch_initcall(gpr_init_irq); diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c new file mode 100644 index 0000000..f044f4c --- /dev/null +++ b/arch/mips/alchemy/gpr/init.c @@ -0,0 +1,63 @@ +/* + * Copyright 2010 Wolfgang Grandegger + * + * Copyright 2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include +#include + +#include + +const char *get_system_type(void) +{ + return "GPR"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(UART0_PHYS_ADDR, c); +} diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c new file mode 100644 index 0000000..3aed1dd --- /dev/null +++ b/arch/mips/alchemy/gpr/platform.c @@ -0,0 +1,185 @@ +/* + * GPR board platform device registration + * + * Copyright (C) 2010 Wolfgang Grandegger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Watchdog + */ +static struct resource gpr_wdt_resource[] = { + [0] = { + .start = 1, + .end = 1, + .name = "gpr-adm6320-wdt", + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device gpr_wdt_device = { + .name = "adm6320-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(gpr_wdt_resource), + .resource = gpr_wdt_resource, +}; + +/* + * FLASH + * + * 0x00000000-0x00200000 : "kernel" + * 0x00200000-0x00a00000 : "rootfs" + * 0x01d00000-0x01f00000 : "config" + * 0x01c00000-0x01d00000 : "yamon" + * 0x01d00000-0x01d40000 : "yamon env vars" + * 0x00000000-0x00a00000 : "kernel+rootfs" + */ +static struct mtd_partition gpr_mtd_partitions[] = { + { + .name = "kernel", + .size = 0x00200000, + .offset = 0, + }, + { + .name = "rootfs", + .size = 0x00800000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "config", + .size = 0x00200000, + .offset = 0x01d00000, + }, + { + .name = "yamon", + .size = 0x00100000, + .offset = 0x01c00000, + }, + { + .name = "yamon env vars", + .size = 0x00040000, + .offset = MTDPART_OFS_APPEND, + }, + { + .name = "kernel+rootfs", + .size = 0x00a00000, + .offset = 0, + }, +}; + +static struct physmap_flash_data gpr_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(gpr_mtd_partitions), + .parts = gpr_mtd_partitions, +}; + +static struct resource gpr_mtd_resource = { + .start = 0x1e000000, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gpr_mtd_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &gpr_flash_data, + }, + .num_resources = 1, + .resource = &gpr_mtd_resource, +}; + +/* + * LEDs + */ +static struct gpio_led gpr_gpio_leds[] = { + { /* green */ + .name = "green", + .gpio = 4, + .active_low = 1, + .default_trigger = "none", + }, + { /* red */ + .name = "red", + .gpio = 5, + .active_low = 1, + .default_trigger = "none", + } +}; + +static struct gpio_led_platform_data gpr_led_data = { + .num_leds = ARRAY_SIZE(gpr_gpio_leds), + .leds = gpr_gpio_leds, +}; + +static struct platform_device gpr_led_devices = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpr_led_data, + } +}; + +/* + * I2C + */ +static struct i2c_gpio_platform_data gpr_i2c_data = { + .sda_pin = 209, + .sda_is_open_drain = 1, + .scl_pin = 210, + .scl_is_open_drain = 1, + .udelay = 2, /* ~100 kHz */ + .timeout = HZ, + }; + +static struct platform_device gpr_i2c_device = { + .name = "i2c-gpio", + .id = -1, + .dev.platform_data = &gpr_i2c_data, +}; + +static struct i2c_board_info gpr_i2c_info[] __initdata = { + { + I2C_BOARD_INFO("lm83", 0x18), + .type = "lm83" + } +}; + +static struct platform_device *gpr_devices[] __initdata = { + &gpr_wdt_device, + &gpr_mtd_device, + &gpr_i2c_device, + &gpr_led_devices, +}; + +static int __init gpr_dev_init(void) +{ + i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); + + return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices)); +} +device_initcall(gpr_dev_init); diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig new file mode 100644 index 0000000..8f0c968 --- /dev/null +++ b/arch/mips/configs/gpr_defconfig @@ -0,0 +1,2062 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35-rc4 +# Wed Jul 14 11:09:25 2010 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_AR7 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_ALCHEMY_GPIOINT_AU1000=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_MIPS_GPR=y +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y +CONFIG_LOONGSON_UART_BASE=y +# CONFIG_LOONGSON_MC146818 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_LED is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +# CONFIG_BRIDGE_EBT_NFLOG is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_CCID3_RTO=100 +CONFIG_IP_DCCP_TFRC_LIB=y +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=y +CONFIG_ATM_CLIP=y +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +# CONFIG_AX25_DAMA_SLAVE is not set +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=m +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=m +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_IFB is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_SMSC_PHY=m +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_MIPS_AU1X00_ENET=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +CONFIG_ATH_COMMON=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH5K=y +CONFIG_ATH5K_DEBUG=y +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_AR9170_USB is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set +# CONFIG_ZD1211RW is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WAN=y +CONFIG_LANMEDIA=m +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_PCI200SYN=m +CONFIG_WANXL=m +# CONFIG_PC300TOO is not set +CONFIG_FARSYNC=m +CONFIG_DSCC4=m +CONFIG_DSCC4_PCISYNC=y +CONFIG_DSCC4_PCI_RST=y +CONFIG_DLCI=m +CONFIG_DLCI_MAX=8 +CONFIG_WAN_ROUTER_DRIVERS=m +CONFIG_CYCLADES_SYNC=m +CONFIG_CYCLOMX_X25=y +CONFIG_LAPBETHER=m +CONFIG_X25_ASY=m +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +CONFIG_ATM_FIRESTREAM=m +CONFIG_ATM_ZATM=m +# CONFIG_ATM_ZATM_DEBUG is not set +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_AMBASSADOR=m +# CONFIG_ATM_AMBASSADOR_DEBUG is not set +CONFIG_ATM_HORIZON=m +# CONFIG_ATM_HORIZON_DEBUG is not set +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +# CONFIG_ATM_FORE200E_USE_TASKLET is not set +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +# CONFIG_ATM_SOLOS is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOATM=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_NET_FC=y +CONFIG_NETCONSOLE=m +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_AU1550 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_SCH is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +CONFIG_SENSORS_LM83=y +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +# CONFIG_SSB_B43_PCI_BRIDGE is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +# CONFIG_SSB_DRIVER_MIPS is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=y +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ATM is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_LKDTM is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw ip=auto" +# CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.2.5 From wg@grandegger.com Wed Jul 14 15:49:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 15:49:33 +0200 (CEST) Received: from mail-out.m-online.net ([212.18.0.9]:55347 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492015Ab0GNNt1 (ORCPT ); Wed, 14 Jul 2010 15:49:27 +0200 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 4BAD01C15B1B; Wed, 14 Jul 2010 15:49:22 +0200 (CEST) X-Auth-Info: AWuL4qZ4SbywjC6Q3Gd7Ew+k4h9yjeuDTIqLKyjxeOo= Received: from lancy.mylan.de (p4FF069FD.dip.t-dialin.net [79.240.105.253]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 245631C00244; Wed, 14 Jul 2010 15:49:22 +0200 (CEST) Message-ID: <4C3DC06D.10107@grandegger.com> Date: Wed, 14 Jul 2010 15:49:33 +0200 From: Wolfgang Grandegger User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Manuel Lauss CC: linux-mips@linux-mips.org, Wolfgang Grandegger Subject: Re: [PATCH] mips/alchemy: add basic support for the GPR board References: <1279101547-14498-1-git-send-email-wg@grandegger.com> In-Reply-To: X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27387 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips On 07/14/2010 12:12 PM, Manuel Lauss wrote: > On Wed, Jul 14, 2010 at 11:59 AM, Wolfgang Grandegger wrote: >> From: Wolfgang Grandegger >> >> This patch adds basic support for the General Purpose Router (GPR) >> board from Trapeze ITS. >> >> Signed-off-by: Wolfgang Grandegger >> --- >> arch/mips/Makefile | 6 + >> arch/mips/alchemy/Kconfig | 9 + >> arch/mips/alchemy/gpr/Makefile | 11 + >> arch/mips/alchemy/gpr/board_setup.c | 97 ++ >> arch/mips/alchemy/gpr/init.c | 63 + >> arch/mips/alchemy/gpr/platform.c | 185 +++ >> arch/mips/configs/gpr_defconfig | 2062 ++++++++++++++++++++++++++++ >> arch/mips/include/asm/mach-au1x00/au1000.h | 2 + >> 8 files changed, 2435 insertions(+), 0 deletions(-) >> create mode 100644 arch/mips/alchemy/gpr/Makefile >> create mode 100644 arch/mips/alchemy/gpr/board_setup.c >> create mode 100644 arch/mips/alchemy/gpr/init.c >> create mode 100644 arch/mips/alchemy/gpr/platform.c >> create mode 100644 arch/mips/configs/gpr_defconfig >> >> diff --git a/arch/mips/Makefile b/arch/mips/Makefile >> index 0b9c01a..6b81b9f 100644 >> --- a/arch/mips/Makefile >> +++ b/arch/mips/Makefile >> @@ -325,6 +325,12 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 >> libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/ >> load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 >> >> +# >> +# Trapeze ITS GRP board >> +# >> +libs-$(CONFIG_MIPS_GPR) += arch/mips/alchemy/gpr/ >> +load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 >> + > > Have a look at the current mips-queue tree: theres a new way to hook up > boards with Platform files. > > >> --- a/arch/mips/include/asm/mach-au1x00/au1000.h >> +++ b/arch/mips/include/asm/mach-au1x00/au1000.h >> @@ -994,6 +994,8 @@ enum soc_au1200_ints { >> >> #ifdef CONFIG_SOC_AU1550 >> #define UART0_ADDR 0xB1100000 >> +#define UART1_ADDR 0xB1200000 >> +#define UART3_ADDR 0xB1400000 > > Please don't add those back, I'm trying to get rid of them. Use something > like "KSEG1ADDR(UART1_PHYS_ADDR)" in the init code where you enable > uarts 1 and 3. I just re-sent v2 which is now based on the linux-queue git tree. Thanks, Wolfgang. From manuel.lauss@googlemail.com Wed Jul 14 16:51:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 16:51:28 +0200 (CEST) Received: from mail-iw0-f177.google.com ([209.85.214.177]:63999 "EHLO mail-iw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492277Ab0GNOvX convert rfc822-to-8bit (ORCPT ); Wed, 14 Jul 2010 16:51:23 +0200 Received: by iwn40 with SMTP id 40so8154892iwn.36 for ; Wed, 14 Jul 2010 07:51:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=pu+dsbSQ5v0oxZT9ATrYOwSHfziavA9IPn0ecEoRYzE=; b=CvVnKnb77YMmDy7zFqOfxD7FDfEioSbojzONmnxPWGmWAiwdToEiAA4jFm/3dbeywC 5FafCmL9/ldMkpmUxGQs/ahP76/9sIUGmu9tDvSfzpJNPBFiIFpqSxUOXkd6fVBMkQRf Aa6jxwizGEY4F0+9l7Uuxnhu99Wj1QJXFFGDU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=JAHR7qm/rxvybzhzh39YlIxEBOccaE7Y59IPs6GzhyV4ahFVRhd5K4YJlvlC8K7lO5 8Y63ljcXIKCKsiZXfhPYTCI7ENOBNY2lQlLTf8AZLt6P/Pz+JByDzwHssdLFglY7Aajp El0Nw+Yxvsrdxc6D0krWxsR7YrQEH15i8XyGs= MIME-Version: 1.0 Received: by 10.231.178.103 with SMTP id bl39mr16190985ibb.138.1279119078097; Wed, 14 Jul 2010 07:51:18 -0700 (PDT) Received: by 10.231.182.207 with HTTP; Wed, 14 Jul 2010 07:51:18 -0700 (PDT) In-Reply-To: <1279115243-11586-1-git-send-email-wg@grandegger.com> References: <1279115243-11586-1-git-send-email-wg@grandegger.com> Date: Wed, 14 Jul 2010 16:51:18 +0200 Message-ID: Subject: Re: [PATCH v2] mips/alchemy: add basic support for the GPR board From: Manuel Lauss To: Wolfgang Grandegger Cc: linux-mips@linux-mips.org, Wolfgang Grandegger Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27388 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Wed, Jul 14, 2010 at 3:47 PM, Wolfgang Grandegger wrote: > diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c > new file mode 100644 > index 0000000..4e68d76 > --- /dev/null > +++ b/arch/mips/alchemy/gpr/board_setup.c > +static int __init gpr_init_irq(void) > +{ > +       return 0; > +} > +arch_initcall(gpr_init_irq); Seems superfluous. Do you intend to add something here in the future? Otherwise looks ok to me. Thank you! Manuel Lauss From segooon@gmail.com Wed Jul 14 20:02:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 20:02:24 +0200 (CEST) Received: from mail-ew0-f49.google.com ([209.85.215.49]:52757 "EHLO mail-ew0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491064Ab0GNSCU (ORCPT ); Wed, 14 Jul 2010 20:02:20 +0200 Received: by ewy9 with SMTP id 9so8784ewy.36 for ; Wed, 14 Jul 2010 11:02:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=3F1T+FQHQ7AeDBBZadZ96Sc1sf4eSvcD9tZbSFHj628=; b=HzuKXdtTuJrmoxkywurqgG2Wcb+EIFHmUzPjUeOJz8QdazO4UdfZ8aaaPPHrikBYWP I13Dz8fPnfuCD3dEwe3qjJoe+ZzkLEt/5t2eIJRWL+N1AG4PLOunulsqFqpHa+H0zVSL axOWSJ1WAQxgtteg3ty2UtQbUvqJFFxp8v31Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=jwFtquRpwiwUVM5YBNRnEjSmP6FdYF/FCeFXHKl76umpaOFbjetWhNKoaBH902MxfA WRpgYieuk76hmqosZlw5gdMP1riAKQQJLLiGRrEBkUASEaPEBlJnUbkUhNCfRVTPn/IU 1qLE8iDD7wRkYCTxKbgwz5KLm4WOWD73+t0Yc= Received: by 10.213.5.5 with SMTP id 5mr12393647ebt.72.1279130539343; Wed, 14 Jul 2010 11:02:19 -0700 (PDT) Received: from localhost ([213.87.81.7]) by mx.google.com with ESMTPS id x54sm161885eeh.5.2010.07.14.11.02.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 14 Jul 2010 11:02:17 -0700 (PDT) From: Kulikov Vasiliy To: kernel-janitors@vger.kernel.org Cc: Ralf Baechle , Chris Dearman , "Robert P. J. Day" , Rusty Russell , =?UTF-8?q?Andr=C3=A9=20Goddard=20Rosa?= , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/11] arch/mips/kernel/smtc.c: formatting of pointers in printk() Date: Wed, 14 Jul 2010 22:01:42 +0400 Message-Id: <1279130502-10777-1-git-send-email-segooon@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27389 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: segooon@gmail.com Precedence: bulk X-list: linux-mips Use %p instead of %08x in printk(). Signed-off-by: Kulikov Vasiliy --- arch/mips/kernel/smtc.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index a95dea5..cfeb2c1 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -975,8 +975,7 @@ void ipi_decode(struct smtc_ipi *pipi) ipi_call_interrupt(); break; default: - printk("Impossible SMTC IPI Argument 0x%x\n", - (int)arg_copy); + printk("Impossible SMTC IPI Argument %p\n", arg_copy); break; } break; -- 1.7.0.4 From f.fainelli@gmail.com Wed Jul 14 20:40:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 20:40:38 +0200 (CEST) Received: from mail-wy0-f177.google.com ([74.125.82.177]:38124 "EHLO mail-wy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491076Ab0GNSkd (ORCPT ); Wed, 14 Jul 2010 20:40:33 +0200 Received: by wyb32 with SMTP id 32so138695wyb.36 for ; Wed, 14 Jul 2010 11:40:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; 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Wed, 14 Jul 2010 11:40:27 -0700 (PDT) In-Reply-To: <1279115243-11586-1-git-send-email-wg@grandegger.com> References: <1279115243-11586-1-git-send-email-wg@grandegger.com> Date: Wed, 14 Jul 2010 20:40:27 +0200 X-Google-Sender-Auth: 5BcDDdZEDmuGuBplLkNLstee3ic Message-ID: Subject: Re: [PATCH v2] mips/alchemy: add basic support for the GPR board From: Florian Fainelli To: Wolfgang Grandegger Cc: linux-mips@linux-mips.org, Wolfgang Grandegger Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: base64 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips SGkgV29sZmdhbmcsCgoyMDEwLzcvMTQgV29sZmdhbmcgR3JhbmRlZ2dlciA8d2dAZ3JhbmRlZ2dl ci5jb20+Ogo+IEZyb206IFdvbGZnYW5nIEdyYW5kZWdnZXIgPHdnQGRlbnguZGU+Cj4KPiBUaGlz IHBhdGNoIGFkZHMgYmFzaWMgc3VwcG9ydCBmb3IgdGhlIEdlbmVyYWwgUHVycG9zZSBSb3V0ZXIg KEdQUikKPiBib2FyZCBmcm9tIFRyYXBlemUgSVRTLgo+Cj4gU2lnbmVkLW9mZi1ieTogV29sZmdh bmcgR3JhbmRlZ2dlciA8d2dAZGVueC5kZT4KW3NuaXBdCgo+ICsKPiArLyoKPiArICogTEVEcwo+ ICsgKi8KPiArc3RhdGljIHN0cnVjdCBncGlvX2xlZCBncHJfZ3Bpb19sZWRzW10gPSB7Cj4gKyDC oCDCoCDCoCB7IMKgIMKgIMKgIC8qIGdyZWVuICovCj4gKyDCoCDCoCDCoCDCoCDCoCDCoCDCoCAu bmFtZSDCoCDCoCDCoCDCoCDCoCDCoCDCoCDCoCDCoCA9ICJncmVlbiIsCj4gKyDCoCDCoCDCoCDC oCDCoCDCoCDCoCAuZ3BpbyDCoCDCoCDCoCDCoCDCoCDCoCDCoCDCoCDCoCA9IDQsCj4gKyDCoCDC oCDCoCDCoCDCoCDCoCDCoCAuYWN0aXZlX2xvdyDCoCDCoCDCoCDCoCDCoCDCoCA9IDEsCj4gKyDC oCDCoCDCoCDCoCDCoCDCoCDCoCAuZGVmYXVsdF90cmlnZ2VyIMKgIMKgIMKgIMKgPSAibm9uZSIs Cj4gKyDCoCDCoCDCoCB9LAo+ICsgwqAgwqAgwqAgeyDCoCDCoCDCoCAvKiByZWQgKi8KPiArIMKg IMKgIMKgIMKgIMKgIMKgIMKgIC5uYW1lIMKgIMKgIMKgIMKgIMKgIMKgIMKgIMKgIMKgID0gInJl ZCIsCj4gKyDCoCDCoCDCoCDCoCDCoCDCoCDCoCAuZ3BpbyDCoCDCoCDCoCDCoCDCoCDCoCDCoCDC oCDCoCA9IDUsCj4gKyDCoCDCoCDCoCDCoCDCoCDCoCDCoCAuYWN0aXZlX2xvdyDCoCDCoCDCoCDC oCDCoCDCoCA9IDEsCj4gKyDCoCDCoCDCoCDCoCDCoCDCoCDCoCAuZGVmYXVsdF90cmlnZ2VyIMKg IMKgIMKgIMKgPSAibm9uZSIsCj4gKyDCoCDCoCDCoCB9Cj4gK307CgpTaG91bGQgYmUgImdwcjpn cmVlbiIgYW5kICJncHI6cmVkIiByZXNwZWN0aXZlbHkgdG8gZm9sbG93IHRoZSBMaW51eApMRURz IGNsYXNzIG5hbWluZyBjb252ZW50aW9ucy4gVGhlIGRlZmF1bHQgdHJpZ2dlciBpcyBzdXBlcmZs dW91cywKaG93ZXZlciBpdCB3b3VsZCBtYWtlIHNlbnNlIHRvIGhhdmUgdGhlIGdyZWVuIGxlZCBi ZSBhc3NvY2lhdGVkIHdpdGgKdGhlICJkZWZhdWx0LW9uIiB0cmlnZ2VyLiBPdGhlcndpc2UsIGl0 IGxvb2tzIHZlcnkgZ29vZC4KLS0KRmxvcmlhbgo= From wg@grandegger.com Wed Jul 14 21:26:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jul 2010 21:26:09 +0200 (CEST) Received: from mail-out.m-online.net ([212.18.0.9]:55908 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492002Ab0GNT0G (ORCPT ); Wed, 14 Jul 2010 21:26:06 +0200 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 5887A1C15B20; Wed, 14 Jul 2010 21:26:00 +0200 (CEST) X-Auth-Info: TWxwPfzDJLHCV84CA4oRT87ghk40FukjnNutfGZXCxw= Received: from lancy.mylan.de (p4FE641EC.dip.t-dialin.net [79.230.65.236]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 18D4B1C001B5; Wed, 14 Jul 2010 21:26:00 +0200 (CEST) Message-ID: <4C3E0F52.9090201@grandegger.com> Date: Wed, 14 Jul 2010 21:26:10 +0200 From: Wolfgang Grandegger User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Manuel Lauss CC: linux-mips@linux-mips.org, Wolfgang Grandegger Subject: Re: [PATCH v2] mips/alchemy: add basic support for the GPR board References: <1279115243-11586-1-git-send-email-wg@grandegger.com> In-Reply-To: X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips On 07/14/2010 04:51 PM, Manuel Lauss wrote: > On Wed, Jul 14, 2010 at 3:47 PM, Wolfgang Grandegger wrote: >> diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c >> new file mode 100644 >> index 0000000..4e68d76 >> --- /dev/null >> +++ b/arch/mips/alchemy/gpr/board_setup.c > >> +static int __init gpr_init_irq(void) >> +{ >> + return 0; >> +} >> +arch_initcall(gpr_init_irq); > > Seems superfluous. Do you intend to add something here in the future? Well, as PCMCIA is not supported on that board, it's actually not needed. I will remove and it for v3. Wolfgang. From mlistz@gmail.com Thu Jul 15 09:52:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 09:52:39 +0200 (CEST) Received: from mail-qw0-f49.google.com ([209.85.216.49]:42392 "EHLO mail-qw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492117Ab0GOHwe convert rfc822-to-8bit (ORCPT ); Thu, 15 Jul 2010 09:52:34 +0200 Received: by qwe4 with SMTP id 4so166441qwe.36 for ; Thu, 15 Jul 2010 00:52:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Nz4nClMTlrUAa9NyIWM6MAYjbTbTTFiLyU1+Mh7iUw0=; b=N1DuUZPWvAQNUMlYLrNRVVGkZVYcIvbQ6124pWW94LekdgDJUBpx6r/NsYvKq1FDZm u1tg1+TzJIwrqX2PGWhbazoiPSPWIDhQCB/P3E1DEWGVn0AI4PVRwY6+tEsoXRJlC+Uu qSpzytxfZBO+Hri7Cy8NGBwgPrHxnbS1ev4kc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=WUvoV4K9aec92q5DmgPbozoIRRsxyp8XiQVMQ6O4rWlzWyZMSLkO/jcjQ4iDNY9Wzo lydTo0cHeuG6a4OxfG/QgnDWlrOFtzhq8wJRSS05rqS8Kq7nK5hh4nBMD3xap6cNCZjY fPkb8Zxc4S8P9CoEgLyzO636TKStzheGYHTVM= MIME-Version: 1.0 Received: by 10.224.78.194 with SMTP id m2mr2352369qak.19.1279180346519; Thu, 15 Jul 2010 00:52:26 -0700 (PDT) Received: by 10.229.51.7 with HTTP; Thu, 15 Jul 2010 00:52:26 -0700 (PDT) In-Reply-To: References: Date: Thu, 15 Jul 2010 15:52:26 +0800 Message-ID: Subject: Re: [Kernel Oops] Cavium Octeon, linux 2.6.34 From: Zhuang Yuyao To: linux-mips@linux-mips.org Cc: David Daney Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlistz@gmail.com Precedence: bulk X-list: linux-mips Hi, I tried to find the cause of this bug, finally, I've found that it is introduced by a patch in linux-2.6.34-rc6. http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=6de9400250f95f82da432c28b9b43823f4154c58 commit 6de9400250f95f82da432c28b9b43823f4154c58 Author: Jörn Engel Date: Thu Apr 22 14:11:43 2010 +0200 Fix JFFS2 sync silent failure JFFS2 does not appear to set s_bdi anywhere. And as of 32a88aa1, __sync_filesystem() will return 0 if s_bdi is not set. As a result, sync_fs() is never called for jffs2 and whatever remains in the wbuf will not make it to the device. Fix that up by assigning the mtd bdi. Signed-off-by: Jörn Engel Acked-By: David Woodhouse Signed-off-by: Jens Axboe revert this patch, the problem disappeared. fix this problem is beyond my knowledge, but I think it may be caused by memory barrier implementation on cavium octeon cpu. On Tue, Jul 13, 2010 at 11:40 AM, Zhuang Yuyao wrote: > This bug still exists in linux kernel 2.6.34.1. > > / # reboot > CPU 1 Unable to handle kernel paging request at virtual address > 0000005781657c00, epc == ffffffff8115f2b0, ra == ffffffff8115f3a0 > Oops[#1]: > Cpu 1 > $ 0   : 0000000000000000 ffffffff81640008 002bffffffc0af58 015ffffffe057ac0 > $ 4   : ffffffe057afee00 0000000000000000 0000005781657c00 00000057ffffff80 > $ 8   : 0000000000000014 ffffffff815d0000 0000000000000001 0000000000008000 > $12   : a8000000cbb7ffe0 0000000000008c00 a8000000d0cc8000 0000000000000000 > $16   : ffffffff815ebfb8 ffffffff815ec0a0 ffffffff815d0000 ffffffff815ec100 > $20   : 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > $24   : 0000000000000000 0000000000000000 > $28   : a8000000cbb7c000 a8000000cbb7fdc0 0000000000000000 ffffffff8115f3a0 > Hi    : 000000000000000a > Lo    : 92f53dde60000000 > epc   : ffffffff8115f2b0 bit_waitqueue+0x30/0xd0 >    Not tainted > ra    : ffffffff8115f3a0 wake_up_bit+0x18/0x38 > Status: 10108ce3    KX SX UX KERNEL EXL IE > Cause : 00800008 > BadVA : 0000005781657c00 > PrId  : 000d0409 (Cavium Octeon+) > Modules linked in: > Process flush-mtd-unmap (pid: 1307, threadinfo=a8000000cbb7c000, > task=a8000000d0ca4040, tls=0000000000000000) > Stack : 0000000000000000 ffffffff815d0000 ffffffff815ebf90 ffffffff8119ce70 >        0000000000000000 a8000000d0ccbca0 ffffffff8119cde8 ffffffff815ec0a0 >        0000000000000000 ffffffff8115eee0 0000000000000000 0000000000000000 >        00000000dead4ead ffffffff00000000 ffffffffffffffff a8000000cbb7fe38 >        a8000000cbb7fe38 a8000000044d9200 0000000000000000 0000000000000000 >        0000000000000000 ffffffff81119368 a8000000044c9200 0000000000000000 >        0000000000000000 0000000000000000 0000000000000000 0000000000000000 >        a8000000d0ccbca0 ffffffff8115ee58 0000000000000000 0000000000000000 >        0000000000000000 0000000000000000 0000000000000000 0000000000000000 >        0000000000000000 0000000000000000 0000000000000000 0000000000000000 >        ... > Call Trace: > [] bit_waitqueue+0x30/0xd0 > [] wake_up_bit+0x18/0x38 > [] bdi_start_fn+0x88/0x108 > [] kthread+0x88/0x90 > [] kernel_thread_helper+0x10/0x18 > > > Code: 000219b8  00c7302d  000210f8 0062102f  2403fffc > 24070680  00c31824  00a42025 > Disabling lock debugging due to kernel taint > > On Thu, Jul 1, 2010 at 1:47 PM, Zhuang Yuyao wrote: >> Hi, >> >> While the 2.6.34 kernel works fine on loading and running, but it >> emits oops everytime while rebooting. >> >> / # /sbin/reboot >> CPU 2 Unable to handle kernel paging request at virtual address >> 0000005781657c00, epc == ffffffff8115f290, ra == ffffffff8115f380 >> Oops[#1]: >> Cpu 2 >> $ 0   : 0000000000000000 0000000000000018 002bffffffc0af58 015ffffffe057ac0 >> $ 4   : ffffffe057afee00 0000000000000000 0000005781657c00 00000057ffffff80 >> $ 8   : 000000182f2de56b 0000000000000000 0000000000000001 0000000000008000 >> $12   : 0000000000000000 ffffffff81105d44 0000000000000000 0000000000000000 >> $16   : ffffffff815ebfb8 ffffffff815ec0a0 ffffffff815d0000 ffffffff815ec100 >> $20   : 0000000000000000 0000000000000000 0000000000000000 0000000000000000 >> $24   : 0000000000000000 ffffffff811152b8 >> $28   : a8000000bd180000 a8000000bd183dc0 0000000000000000 ffffffff8115f380 >> Hi    : 0000000000000000 >> Lo    : 0000000000000000 >> epc   : ffffffff8115f290 bit_waitqueue+0x30/0xd0 >>    Not tainted >> ra    : ffffffff8115f380 wake_up_bit+0x18/0x38 >> Status: 10108ce3    KX SX UX KERNEL EXL IE >> Cause : 00800008 >> BadVA : 0000005781657c00 >> PrId  : 000d0409 (Cavium Octeon+) >> Modules linked in: >> Process flush-mtd-unmap (pid: 1357, threadinfo=a8000000bd180000, >> task=a8000000d0256040, tls=0000000000000000) >> Stack : 0000000000000000 ffffffff815d0000 ffffffff815ebf90 ffffffff8119ce18 >>        0000000000000000 a8000000d0cc7ca0 ffffffff8119cd90 ffffffff815ec0a0 >>        0000000000000000 ffffffff8115eec0 00000000beb2b997 0000000041b4b962 >>        00000000dead4ead ffffffffecbeaa23 ffffffffffffffff a8000000bd183e38 >>        a8000000bd183e38 a8000000044e9200 0000000000000000 0000000000000000 >>        0000000000000000 ffffffff81119348 a8000000044d9200 0000000000000000 >>        0000000000000000 0000000000000000 0000000000000000 0000000000000000 >>        a8000000d0cc7ca0 ffffffff8115ee38 0000000000000000 0000000000000000 >>        0000000000000000 0000000000000000 0000000000000000 0000000000000000 >>        0000000000000000 0000000000000000 0000000000000000 0000000000000000 >>        ... >> Call Trace: >> [] bit_waitqueue+0x30/0xd0 >> [] wake_up_bit+0x18/0x38 >> [] bdi_start_fn+0x88/0x108 >> [] kthread+0x88/0x90 >> [] kernel_thread_helper+0x10/0x18 >> >> >> Code: 000219b8  00c7302d  000210f8 0062102f  2403fffc >> 24070680  00c31824  00a42025 >> Disabling lock debugging due to kernel taint >> >> Is it a known and fixed bug? >> >> Best regards, >> >> Zhuang Yuyao >> > From wg@grandegger.com Thu Jul 15 11:04:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 11:04:35 +0200 (CEST) Received: from mail-out.m-online.net ([212.18.0.10]:53839 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492174Ab0GOJE3 (ORCPT ); Thu, 15 Jul 2010 11:04:29 +0200 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3BCB31C00233; Thu, 15 Jul 2010 11:04:28 +0200 (CEST) X-Auth-Info: EDmiIOdv0sE+80dVzqnMlUSaduXvHHmURZRLu6Nfsxw= Received: from lancy.mylan.de (p4FF05C95.dip.t-dialin.net [79.240.92.149]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 1C1AD1C0021E; Thu, 15 Jul 2010 11:04:28 +0200 (CEST) Message-ID: <4C3ECF27.4040306@grandegger.com> Date: Thu, 15 Jul 2010 11:04:39 +0200 From: Wolfgang Grandegger User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Florian Fainelli CC: linux-mips@linux-mips.org, Wolfgang Grandegger Subject: Re: [PATCH v2] mips/alchemy: add basic support for the GPR board References: <1279115243-11586-1-git-send-email-wg@grandegger.com> In-Reply-To: X-Enigmail-Version: 1.0.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips On 07/14/2010 08:40 PM, Florian Fainelli wrote: > Hi Wolfgang, > > 2010/7/14 Wolfgang Grandegger : >> From: Wolfgang Grandegger >> >> This patch adds basic support for the General Purpose Router (GPR) >> board from Trapeze ITS. >> >> Signed-off-by: Wolfgang Grandegger > [snip] > >> + >> +/* >> + * LEDs >> + */ >> +static struct gpio_led gpr_gpio_leds[] = { >> + { /* green */ >> + .name = "green", >> + .gpio = 4, >> + .active_low = 1, >> + .default_trigger = "none", >> + }, >> + { /* red */ >> + .name = "red", >> + .gpio = 5, >> + .active_low = 1, >> + .default_trigger = "none", >> + } >> +}; > > Should be "gpr:green" and "gpr:red" respectively to follow the Linux > LEDs class naming conventions. The default trigger is superfluous, Will be fixed. > however it would make sense to have the green led be associated with > the "default-on" trigger. Otherwise, it looks very good. I just played with various default triggers. None of them is needed and I will remove it. In the board setup code, the LEDs are toggled and therefore I do not want to define a "default-on". Thanks, Wolfgang. From wg@denx.de Thu Jul 15 11:16:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 11:17:05 +0200 (CEST) Received: from mail-out.m-online.net ([212.18.0.10]:37806 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492138Ab0GOJQ6 (ORCPT ); Thu, 15 Jul 2010 11:16:58 +0200 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 440E11C004B1 for ; Thu, 15 Jul 2010 11:16:58 +0200 (CEST) X-Auth-Info: wNBbrWMWkSUPWcrX9Eqbf+Pmf8RtmMEKQQjaCjwTqh8= Received: from mail.denx.de (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 10D6D1C00256 for ; Thu, 15 Jul 2010 11:16:58 +0200 (CEST) Received: from pollux.denx.de (pollux [192.168.1.1]) by mail.denx.de (Postfix) with ESMTP id EC38340B71C5 for ; Thu, 15 Jul 2010 11:16:57 +0200 (CEST) Received: by pollux.denx.de (Postfix, from userid 504) id A8789100E57B7; Thu, 15 Jul 2010 11:16:57 +0200 (CEST) From: Wolfgang Grandegger To: linux-mips@linux-mips.org Subject: Date: Thu, 15 Jul 2010 11:16:57 +0200 Message-Id: <1279185417-20883-1-git-send-email-wg@grandegger.com> X-Mailer: git-send-email 1.6.2.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips From dfa82efffd0d215d0e0a25b201b0ebc3a9bdc25e Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Wed, 14 Jul 2010 15:42:05 +0200 Subject: [PATCH v3] mips/alchemy: add basic support for the GPR board This patch adds basic support for the General Purpose Router (GPR) board from Trapeze ITS. Signed-off-by: Wolfgang Grandegger --- Changes since v1: - rebased against the linux-queue git tree. - use new way to hook up boards with the Platform file. - don't add UART[13]_ADDR to au1000.h Changes since v2: - remove superfluous gpr_init_irq() - fix LED platform code arch/mips/alchemy/Kconfig | 9 + arch/mips/alchemy/Platform | 5 + arch/mips/alchemy/gpr/Makefile | 8 + arch/mips/alchemy/gpr/board_setup.c | 94 ++ arch/mips/alchemy/gpr/init.c | 63 ++ arch/mips/alchemy/gpr/platform.c | 183 ++++ arch/mips/configs/gpr_defconfig | 2062 +++++++++++++++++++++++++++++++++++ 7 files changed, 2424 insertions(+), 0 deletions(-) create mode 100644 arch/mips/alchemy/gpr/Makefile create mode 100644 arch/mips/alchemy/gpr/board_setup.c create mode 100644 arch/mips/alchemy/gpr/init.c create mode 100644 arch/mips/alchemy/gpr/platform.c create mode 100644 arch/mips/configs/gpr_defconfig diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index df3b1a7..c9830e0 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -128,6 +128,15 @@ config MIPS_XXS1500 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK +config MIPS_GPR + bool "Trapeze ITS GPR board" + select SOC_AU1550 + select HW_HAS_PCI + select DMA_NONCOHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + endchoice config SOC_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 495cc9a..c64e3b7 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -100,6 +100,11 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 +# +# Trapeze ITS GRP board +# +platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/ +load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 # boards can specify their own in one of their include dirs. # If they do, placing this line here at the end will make sure the diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile new file mode 100644 index 0000000..1a3f214 --- /dev/null +++ b/arch/mips/alchemy/gpr/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2003 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# +# Makefile for Trapeze ITS GPR board. +# + +obj-y += init.o board_setup.o platform.o diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c new file mode 100644 index 0000000..31721f7 --- /dev/null +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -0,0 +1,94 @@ +/* + * Copyright 2010 Wolfgang Grandegger + * + * Copyright 2000-2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR) +#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR) + +char irq_tab_alchemy[][5] __initdata = { + [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, +}; + +static void gpr_reset(char *c) +{ + /* switch System-LED to orange (red# and green# on) */ + alchemy_gpio_direction_output(4, 0); + alchemy_gpio_direction_output(5, 0); + + /* trigger watchdog to reset board in 200ms */ + printk(KERN_EMERG "Triggering watchdog soft reset...\n"); + raw_local_irq_disable(); + alchemy_gpio_direction_output(1, 0); + udelay(1); + alchemy_gpio_set_value(1, 1); + while (1) + asm volatile (".set mips3 ; wait ; .set mips0"); +} + +static void gpr_power_off(void) +{ + printk(KERN_ALERT "It's now safe to remove power\n"); + while (1) + asm volatile (".set mips3 ; wait ; .set mips0"); +} + +void __init board_setup(void) +{ + printk(KERN_INFO "Tarpeze ITS GPR board\n"); + + pm_power_off = gpr_power_off; + _machine_halt = gpr_power_off; + _machine_restart = gpr_reset; + + /* Enable UART3 */ + au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */ + au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + /* Enable UART1 */ + au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ + au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + + /* Take away Reset of UMTS-card */ + alchemy_gpio_direction_output(215, 1); + +#ifdef CONFIG_PCI +#if defined(__MIPSEB__) + au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); +#else + au_writel(0xf, Au1500_PCI_CFG); +#endif +#endif +} diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c new file mode 100644 index 0000000..f044f4c --- /dev/null +++ b/arch/mips/alchemy/gpr/init.c @@ -0,0 +1,63 @@ +/* + * Copyright 2010 Wolfgang Grandegger + * + * Copyright 2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include +#include + +#include + +const char *get_system_type(void) +{ + return "GPR"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(UART0_PHYS_ADDR, c); +} diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c new file mode 100644 index 0000000..14b4662 --- /dev/null +++ b/arch/mips/alchemy/gpr/platform.c @@ -0,0 +1,183 @@ +/* + * GPR board platform device registration + * + * Copyright (C) 2010 Wolfgang Grandegger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Watchdog + */ +static struct resource gpr_wdt_resource[] = { + [0] = { + .start = 1, + .end = 1, + .name = "gpr-adm6320-wdt", + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device gpr_wdt_device = { + .name = "adm6320-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(gpr_wdt_resource), + .resource = gpr_wdt_resource, +}; + +/* + * FLASH + * + * 0x00000000-0x00200000 : "kernel" + * 0x00200000-0x00a00000 : "rootfs" + * 0x01d00000-0x01f00000 : "config" + * 0x01c00000-0x01d00000 : "yamon" + * 0x01d00000-0x01d40000 : "yamon env vars" + * 0x00000000-0x00a00000 : "kernel+rootfs" + */ +static struct mtd_partition gpr_mtd_partitions[] = { + { + .name = "kernel", + .size = 0x00200000, + .offset = 0, + }, + { + .name = "rootfs", + .size = 0x00800000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "config", + .size = 0x00200000, + .offset = 0x01d00000, + }, + { + .name = "yamon", + .size = 0x00100000, + .offset = 0x01c00000, + }, + { + .name = "yamon env vars", + .size = 0x00040000, + .offset = MTDPART_OFS_APPEND, + }, + { + .name = "kernel+rootfs", + .size = 0x00a00000, + .offset = 0, + }, +}; + +static struct physmap_flash_data gpr_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(gpr_mtd_partitions), + .parts = gpr_mtd_partitions, +}; + +static struct resource gpr_mtd_resource = { + .start = 0x1e000000, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gpr_mtd_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &gpr_flash_data, + }, + .num_resources = 1, + .resource = &gpr_mtd_resource, +}; + +/* + * LEDs + */ +static struct gpio_led gpr_gpio_leds[] = { + { /* green */ + .name = "gpr:green", + .gpio = 4, + .active_low = 1, + }, + { /* red */ + .name = "gpr:red", + .gpio = 5, + .active_low = 1, + } +}; + +static struct gpio_led_platform_data gpr_led_data = { + .num_leds = ARRAY_SIZE(gpr_gpio_leds), + .leds = gpr_gpio_leds, +}; + +static struct platform_device gpr_led_devices = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpr_led_data, + } +}; + +/* + * I2C + */ +static struct i2c_gpio_platform_data gpr_i2c_data = { + .sda_pin = 209, + .sda_is_open_drain = 1, + .scl_pin = 210, + .scl_is_open_drain = 1, + .udelay = 2, /* ~100 kHz */ + .timeout = HZ, + }; + +static struct platform_device gpr_i2c_device = { + .name = "i2c-gpio", + .id = -1, + .dev.platform_data = &gpr_i2c_data, +}; + +static struct i2c_board_info gpr_i2c_info[] __initdata = { + { + I2C_BOARD_INFO("lm83", 0x18), + .type = "lm83" + } +}; + +static struct platform_device *gpr_devices[] __initdata = { + &gpr_wdt_device, + &gpr_mtd_device, + &gpr_i2c_device, + &gpr_led_devices, +}; + +static int __init gpr_dev_init(void) +{ + i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); + + return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices)); +} +device_initcall(gpr_dev_init); diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig new file mode 100644 index 0000000..17d8052 --- /dev/null +++ b/arch/mips/configs/gpr_defconfig @@ -0,0 +1,2062 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35-rc4 +# Wed Jul 14 13:14:25 2010 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_AR7 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_ALCHEMY_GPIOINT_AU1000=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_MIPS_GPR=y +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y +CONFIG_LOONGSON_UART_BASE=y +# CONFIG_LOONGSON_MC146818 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_LED is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +# CONFIG_BRIDGE_EBT_NFLOG is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_CCID3_RTO=100 +CONFIG_IP_DCCP_TFRC_LIB=y +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=y +CONFIG_ATM_CLIP=y +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +# CONFIG_AX25_DAMA_SLAVE is not set +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=m +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=m +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_IFB is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_SMSC_PHY=m +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_MIPS_AU1X00_ENET=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +CONFIG_ATH_COMMON=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH5K=y +CONFIG_ATH5K_DEBUG=y +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_AR9170_USB is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set +# CONFIG_ZD1211RW is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WAN=y +CONFIG_LANMEDIA=m +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_PCI200SYN=m +CONFIG_WANXL=m +# CONFIG_PC300TOO is not set +CONFIG_FARSYNC=m +CONFIG_DSCC4=m +CONFIG_DSCC4_PCISYNC=y +CONFIG_DSCC4_PCI_RST=y +CONFIG_DLCI=m +CONFIG_DLCI_MAX=8 +CONFIG_WAN_ROUTER_DRIVERS=m +CONFIG_CYCLADES_SYNC=m +CONFIG_CYCLOMX_X25=y +CONFIG_LAPBETHER=m +CONFIG_X25_ASY=m +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +CONFIG_ATM_FIRESTREAM=m +CONFIG_ATM_ZATM=m +# CONFIG_ATM_ZATM_DEBUG is not set +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_AMBASSADOR=m +# CONFIG_ATM_AMBASSADOR_DEBUG is not set +CONFIG_ATM_HORIZON=m +# CONFIG_ATM_HORIZON_DEBUG is not set +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +# CONFIG_ATM_FORE200E_USE_TASKLET is not set +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +# CONFIG_ATM_SOLOS is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOATM=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_NET_FC=y +CONFIG_NETCONSOLE=m +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_AU1550 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_SCH is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +CONFIG_SENSORS_LM83=y +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +# CONFIG_SSB_B43_PCI_BRIDGE is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +# CONFIG_SSB_DRIVER_MIPS is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=y +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ATM is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_LKDTM is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw ip=auto" +# CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.2.5 From wg@denx.de Thu Jul 15 11:21:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 11:21:36 +0200 (CEST) Received: from mail-out.m-online.net ([212.18.0.9]:51372 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491929Ab0GOJV3 (ORCPT ); Thu, 15 Jul 2010 11:21:29 +0200 Received: from frontend1.mail.m-online.net (unknown [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 7EC9C1C15D42 for ; Thu, 15 Jul 2010 11:21:24 +0200 (CEST) X-Auth-Info: t6h1BBrFeGHBxFQ4b1pL/f9YvEY+BUQyR7IoSQmVXhQ= Received: from mail.denx.de (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 279D41C00088 for ; Thu, 15 Jul 2010 11:21:24 +0200 (CEST) Received: from pollux.denx.de (pollux [192.168.1.1]) by mail.denx.de (Postfix) with ESMTP id 056EE410C03C for ; Thu, 15 Jul 2010 11:21:23 +0200 (CEST) Received: by pollux.denx.de (Postfix, from userid 504) id D2C5B100E57B7; Thu, 15 Jul 2010 11:21:23 +0200 (CEST) From: Wolfgang Grandegger To: linux-mips@linux-mips.org Cc: Wolfgang Grandegger Subject: [PATCH v3] mips/alchemy: add basic support for the GPR board Date: Thu, 15 Jul 2010 11:21:23 +0200 Message-Id: <1279185683-21037-1-git-send-email-wg@grandegger.com> X-Mailer: git-send-email 1.6.2.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wg@grandegger.com Precedence: bulk X-list: linux-mips From: Wolfgang Grandegger This patch adds basic support for the General Purpose Router (GPR) board from Trapeze ITS. Signed-off-by: Wolfgang Grandegger --- Something went wrong with my previous "git send-email", please ignore. Changes since v1: - rebased against the linux-queue git tree. - use new way to hook up boards with the Platform file. - don't add UART[13]_ADDR to au1000.h Changes since v2: - remove superfluous gpr_init_irq() - fix LED platform code arch/mips/alchemy/Kconfig | 9 + arch/mips/alchemy/Platform | 5 + arch/mips/alchemy/gpr/Makefile | 8 + arch/mips/alchemy/gpr/board_setup.c | 94 ++ arch/mips/alchemy/gpr/init.c | 63 ++ arch/mips/alchemy/gpr/platform.c | 183 ++++ arch/mips/configs/gpr_defconfig | 2062 +++++++++++++++++++++++++++++++++++ 7 files changed, 2424 insertions(+), 0 deletions(-) create mode 100644 arch/mips/alchemy/gpr/Makefile create mode 100644 arch/mips/alchemy/gpr/board_setup.c create mode 100644 arch/mips/alchemy/gpr/init.c create mode 100644 arch/mips/alchemy/gpr/platform.c create mode 100644 arch/mips/configs/gpr_defconfig diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index df3b1a7..c9830e0 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -128,6 +128,15 @@ config MIPS_XXS1500 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK +config MIPS_GPR + bool "Trapeze ITS GPR board" + select SOC_AU1550 + select HW_HAS_PCI + select DMA_NONCOHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + endchoice config SOC_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 495cc9a..c64e3b7 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -100,6 +100,11 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 +# +# Trapeze ITS GRP board +# +platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/ +load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 # boards can specify their own in one of their include dirs. # If they do, placing this line here at the end will make sure the diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile new file mode 100644 index 0000000..1a3f214 --- /dev/null +++ b/arch/mips/alchemy/gpr/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2003 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# +# Makefile for Trapeze ITS GPR board. +# + +obj-y += init.o board_setup.o platform.o diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c new file mode 100644 index 0000000..31721f7 --- /dev/null +++ b/arch/mips/alchemy/gpr/board_setup.c @@ -0,0 +1,94 @@ +/* + * Copyright 2010 Wolfgang Grandegger + * + * Copyright 2000-2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR) +#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR) + +char irq_tab_alchemy[][5] __initdata = { + [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, +}; + +static void gpr_reset(char *c) +{ + /* switch System-LED to orange (red# and green# on) */ + alchemy_gpio_direction_output(4, 0); + alchemy_gpio_direction_output(5, 0); + + /* trigger watchdog to reset board in 200ms */ + printk(KERN_EMERG "Triggering watchdog soft reset...\n"); + raw_local_irq_disable(); + alchemy_gpio_direction_output(1, 0); + udelay(1); + alchemy_gpio_set_value(1, 1); + while (1) + asm volatile (".set mips3 ; wait ; .set mips0"); +} + +static void gpr_power_off(void) +{ + printk(KERN_ALERT "It's now safe to remove power\n"); + while (1) + asm volatile (".set mips3 ; wait ; .set mips0"); +} + +void __init board_setup(void) +{ + printk(KERN_INFO "Tarpeze ITS GPR board\n"); + + pm_power_off = gpr_power_off; + _machine_halt = gpr_power_off; + _machine_restart = gpr_reset; + + /* Enable UART3 */ + au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */ + au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + /* Enable UART1 */ + au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ + au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ + + /* Take away Reset of UMTS-card */ + alchemy_gpio_direction_output(215, 1); + +#ifdef CONFIG_PCI +#if defined(__MIPSEB__) + au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); +#else + au_writel(0xf, Au1500_PCI_CFG); +#endif +#endif +} diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c new file mode 100644 index 0000000..f044f4c --- /dev/null +++ b/arch/mips/alchemy/gpr/init.c @@ -0,0 +1,63 @@ +/* + * Copyright 2010 Wolfgang Grandegger + * + * Copyright 2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include +#include + +#include + +const char *get_system_type(void) +{ + return "GPR"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(UART0_PHYS_ADDR, c); +} diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c new file mode 100644 index 0000000..14b4662 --- /dev/null +++ b/arch/mips/alchemy/gpr/platform.c @@ -0,0 +1,183 @@ +/* + * GPR board platform device registration + * + * Copyright (C) 2010 Wolfgang Grandegger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Watchdog + */ +static struct resource gpr_wdt_resource[] = { + [0] = { + .start = 1, + .end = 1, + .name = "gpr-adm6320-wdt", + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device gpr_wdt_device = { + .name = "adm6320-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(gpr_wdt_resource), + .resource = gpr_wdt_resource, +}; + +/* + * FLASH + * + * 0x00000000-0x00200000 : "kernel" + * 0x00200000-0x00a00000 : "rootfs" + * 0x01d00000-0x01f00000 : "config" + * 0x01c00000-0x01d00000 : "yamon" + * 0x01d00000-0x01d40000 : "yamon env vars" + * 0x00000000-0x00a00000 : "kernel+rootfs" + */ +static struct mtd_partition gpr_mtd_partitions[] = { + { + .name = "kernel", + .size = 0x00200000, + .offset = 0, + }, + { + .name = "rootfs", + .size = 0x00800000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "config", + .size = 0x00200000, + .offset = 0x01d00000, + }, + { + .name = "yamon", + .size = 0x00100000, + .offset = 0x01c00000, + }, + { + .name = "yamon env vars", + .size = 0x00040000, + .offset = MTDPART_OFS_APPEND, + }, + { + .name = "kernel+rootfs", + .size = 0x00a00000, + .offset = 0, + }, +}; + +static struct physmap_flash_data gpr_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(gpr_mtd_partitions), + .parts = gpr_mtd_partitions, +}; + +static struct resource gpr_mtd_resource = { + .start = 0x1e000000, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gpr_mtd_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &gpr_flash_data, + }, + .num_resources = 1, + .resource = &gpr_mtd_resource, +}; + +/* + * LEDs + */ +static struct gpio_led gpr_gpio_leds[] = { + { /* green */ + .name = "gpr:green", + .gpio = 4, + .active_low = 1, + }, + { /* red */ + .name = "gpr:red", + .gpio = 5, + .active_low = 1, + } +}; + +static struct gpio_led_platform_data gpr_led_data = { + .num_leds = ARRAY_SIZE(gpr_gpio_leds), + .leds = gpr_gpio_leds, +}; + +static struct platform_device gpr_led_devices = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpr_led_data, + } +}; + +/* + * I2C + */ +static struct i2c_gpio_platform_data gpr_i2c_data = { + .sda_pin = 209, + .sda_is_open_drain = 1, + .scl_pin = 210, + .scl_is_open_drain = 1, + .udelay = 2, /* ~100 kHz */ + .timeout = HZ, + }; + +static struct platform_device gpr_i2c_device = { + .name = "i2c-gpio", + .id = -1, + .dev.platform_data = &gpr_i2c_data, +}; + +static struct i2c_board_info gpr_i2c_info[] __initdata = { + { + I2C_BOARD_INFO("lm83", 0x18), + .type = "lm83" + } +}; + +static struct platform_device *gpr_devices[] __initdata = { + &gpr_wdt_device, + &gpr_mtd_device, + &gpr_i2c_device, + &gpr_led_devices, +}; + +static int __init gpr_dev_init(void) +{ + i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); + + return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices)); +} +device_initcall(gpr_dev_init); diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig new file mode 100644 index 0000000..17d8052 --- /dev/null +++ b/arch/mips/configs/gpr_defconfig @@ -0,0 +1,2062 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35-rc4 +# Wed Jul 14 13:14:25 2010 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_AR7 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_ALCHEMY_GPIOINT_AU1000=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_MIPS_GPR=y +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y +CONFIG_LOONGSON_UART_BASE=y +# CONFIG_LOONGSON_MC146818 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_LED is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +# CONFIG_BRIDGE_EBT_NFLOG is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_CCID3_RTO=100 +CONFIG_IP_DCCP_TFRC_LIB=y +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +CONFIG_TIPC=m +# CONFIG_TIPC_ADVANCED is not set +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=y +CONFIG_ATM_CLIP=y +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +# CONFIG_AX25_DAMA_SLAVE is not set +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=m +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=m +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_IFB is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_SMSC_PHY=m +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_MIPS_AU1X00_ENET=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +CONFIG_ATH_COMMON=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH5K=y +CONFIG_ATH5K_DEBUG=y +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_AR9170_USB is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set +# CONFIG_ZD1211RW is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WAN=y +CONFIG_LANMEDIA=m +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_PCI200SYN=m +CONFIG_WANXL=m +# CONFIG_PC300TOO is not set +CONFIG_FARSYNC=m +CONFIG_DSCC4=m +CONFIG_DSCC4_PCISYNC=y +CONFIG_DSCC4_PCI_RST=y +CONFIG_DLCI=m +CONFIG_DLCI_MAX=8 +CONFIG_WAN_ROUTER_DRIVERS=m +CONFIG_CYCLADES_SYNC=m +CONFIG_CYCLOMX_X25=y +CONFIG_LAPBETHER=m +CONFIG_X25_ASY=m +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +CONFIG_ATM_FIRESTREAM=m +CONFIG_ATM_ZATM=m +# CONFIG_ATM_ZATM_DEBUG is not set +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_AMBASSADOR=m +# CONFIG_ATM_AMBASSADOR_DEBUG is not set +CONFIG_ATM_HORIZON=m +# CONFIG_ATM_HORIZON_DEBUG is not set +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +# CONFIG_ATM_FORE200E_USE_TASKLET is not set +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +# CONFIG_ATM_SOLOS is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOATM=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_NET_FC=y +CONFIG_NETCONSOLE=m +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_AU1550 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_SCH is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +CONFIG_SENSORS_LM83=y +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +# CONFIG_SSB_B43_PCI_BRIDGE is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +# CONFIG_SSB_DRIVER_MIPS is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=y +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ATM is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_LKDTM is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw ip=auto" +# CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_SPINLOCK_TEST is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.2.5 From manuel.lauss@googlemail.com Thu Jul 15 21:45:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 21:45:22 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:62513 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491837Ab0GOTpS (ORCPT ); Thu, 15 Jul 2010 21:45:18 +0200 Received: by bwz15 with SMTP id 15so902171bwz.36 for ; Thu, 15 Jul 2010 12:45:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=x6YUF3aeBHYAloSN/vEPVMm4qSMb0+FB7H3tXUU2ODk=; b=TeRErKrVCEZw+R4hq7UnC2IhiOMhkfX+qhvWuYhFp+tq5SfwkSsxzJYocODLA9tg8K UYQod0AX7VFEecBlKAm+867U2g8PAmMI7WdFFp85MlvE7iCkjSlRdNyunoEZWNyl13Xp 8DE2A7IhikXZj+Q5k7/duapGASE3rE/GYyHkY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=eWuzJ5Hwdm9DZ5sEOHIS5zJXPxp7jEklZGpM9iSdjZkCurVE2UY38pVE0/Gl2bgzNf abaIZWu206jPcqudkp21UIEprMngwCp/lboJq3YUk4v+A9665t2nhRKlguviBhPDv5OV 8g6cIcbPGKHqV/kxzfBB9Uw5HFZaKjevGm/P8= Received: by 10.204.101.72 with SMTP id b8mr78477bko.192.1279223117459; Thu, 15 Jul 2010 12:45:17 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id s17sm7274438bkx.18.2010.07.15.12.45.14 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Jul 2010 12:45:15 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH 1/2] MIPS: Alchemy: remove SOC_AU1X00 in favor of MIPS_ALCHEMY Date: Thu, 15 Jul 2010 21:45:04 +0200 Message-Id: <1279223105-23816-1-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.1.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips This patch removes the CONFIG_SOC_AU1X00 Kconfig symbol since its job can also be done by MACH_ALCHEMY, now renamed to MIPS_ALCHEMY. Signed-off-by: Manuel Lauss --- arch/mips/Kconfig | 11 ++++++++++- arch/mips/alchemy/Kconfig | 19 +------------------ arch/mips/alchemy/Platform | 4 ++-- arch/mips/boot/compressed/Makefile | 2 +- arch/mips/configs/db1000_defconfig | 3 +-- arch/mips/configs/db1100_defconfig | 3 +-- arch/mips/configs/db1200_defconfig | 3 +-- arch/mips/configs/db1500_defconfig | 3 +-- arch/mips/configs/db1550_defconfig | 3 +-- arch/mips/configs/mtx1_defconfig | 3 +-- arch/mips/configs/pb1100_defconfig | 3 +-- arch/mips/configs/pb1200_defconfig | 3 +-- arch/mips/configs/pb1500_defconfig | 3 +-- arch/mips/configs/pb1550_defconfig | 3 +-- arch/mips/include/asm/hazards.h | 4 ++-- drivers/net/Kconfig | 2 +- drivers/pcmcia/Kconfig | 4 ++-- drivers/rtc/Kconfig | 2 +- drivers/serial/Kconfig | 2 +- drivers/usb/Kconfig | 2 +- drivers/usb/host/ohci-hcd.c | 2 +- 21 files changed, 33 insertions(+), 51 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index cdaae94..b189555 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -23,8 +23,17 @@ choice prompt "System type" default SGI_IP22 -config MACH_ALCHEMY +config MIPS_ALCHEMY bool "Alchemy processor based machines" + select 64BIT_PHYS_ADDR + select CEVT_R4K_LIB + select CSRC_R4K_LIB + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_APM_EMULATION + select GENERIC_GPIO + select ARCH_WANT_OPTIONAL_GPIOLIB select SYS_SUPPORTS_ZBOOT config AR7 diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index df3b1a7..1179c4d 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -11,7 +11,7 @@ config ALCHEMY_GPIO_INDIRECT choice prompt "Machine type" - depends on MACH_ALCHEMY + depends on MIPS_ALCHEMY default MIPS_DB1000 config MIPS_MTX1 @@ -132,37 +132,20 @@ endchoice config SOC_AU1000 bool - select SOC_AU1X00 select ALCHEMY_GPIOINT_AU1000 config SOC_AU1100 bool - select SOC_AU1X00 select ALCHEMY_GPIOINT_AU1000 config SOC_AU1500 bool - select SOC_AU1X00 select ALCHEMY_GPIOINT_AU1000 config SOC_AU1550 bool - select SOC_AU1X00 select ALCHEMY_GPIOINT_AU1000 config SOC_AU1200 bool - select SOC_AU1X00 select ALCHEMY_GPIOINT_AU1000 - -config SOC_AU1X00 - bool - select 64BIT_PHYS_ADDR - select CEVT_R4K_LIB - select CSRC_R4K_LIB - select IRQ_CPU - select SYS_HAS_CPU_MIPS32_R1 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_APM_EMULATION - select GENERIC_GPIO - select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 495cc9a..0bf2b09 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -1,7 +1,7 @@ # # Core Alchemy code # -platform-$(CONFIG_MACH_ALCHEMY) += alchemy/common/ +platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/ # @@ -106,4 +106,4 @@ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 # compiler picks the board one. If they don't, it will make sure # the alchemy generic gpio header is picked up. -cflags-$(CONFIG_MACH_ALCHEMY) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 +cflags-$(CONFIG_MIPS_ALCHEMY) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index 74a52d7..edc48ad 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -40,7 +40,7 @@ vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o ifdef CONFIG_DEBUG_ZBOOT vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o -vmlinuzobjs-$(CONFIG_MACH_ALCHEMY) += $(obj)/uart-alchemy.o +vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o endif targets += vmlinux.bin diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index f66d406..3a9ec6c 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_DB1000=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1000=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index abb9a58..4589b84 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_DB1100=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1100=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 991c20a..9950f2a 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_DB1200=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1200=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 5424c91..346ae63 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_DB1500=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1500=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 949b6dc..10eafb9 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_DB1550=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1550=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index cff8f4c..10d20aa 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_MTX1=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1500=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 97382b6..778f726 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_PB1100=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1100=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig index e9ad773..0f908c6 100644 --- a/arch/mips/configs/pb1200_defconfig +++ b/arch/mips/configs/pb1200_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_PB1200=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1200=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 7497d33..1c5fe6f 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_MIPS_PB1500=y # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1500=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index aa526f5..49494b0 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -8,7 +8,7 @@ CONFIG_MIPS=y # # Machine selection # -CONFIG_MACH_ALCHEMY=y +CONFIG_MIPS_ALCHEMY=y # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set @@ -64,7 +64,6 @@ CONFIG_ALCHEMY_GPIOINT_AU1000=y CONFIG_MIPS_PB1550=y # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1550=y -CONFIG_SOC_AU1X00=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 0eaf77f..4e33216 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -87,7 +87,7 @@ do { \ : "=r" (tmp)); \ } while (0) -#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY) +#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY) /* * These are slightly complicated by the fact that we guarantee R1 kernels to @@ -138,7 +138,7 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ +#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ defined(CONFIG_CPU_R5500) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ce2fcdd..adead30 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -484,7 +484,7 @@ config XTENSA_XT2000_SONIC config MIPS_AU1X00_ENET tristate "MIPS AU1000 Ethernet support" - depends on SOC_AU1X00 + depends on MIPS_ALCHEMY select PHYLIB select CRC32 help diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index d0f5ad3..c988514 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -157,11 +157,11 @@ config PCMCIA_M8XX config PCMCIA_AU1X00 tristate "Au1x00 pcmcia support" - depends on SOC_AU1X00 && PCMCIA + depends on MIPS_ALCHEMY && PCMCIA config PCMCIA_ALCHEMY_DEVBOARD tristate "Alchemy Db/Pb1xxx PCMCIA socket services" - depends on SOC_AU1X00 && PCMCIA + depends on MIPS_ALCHEMY && PCMCIA select 64BIT_PHYS_ADDR help Enable this driver of you want PCMCIA support on your Alchemy diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 10ba12c..9d6952e 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -774,7 +774,7 @@ config RTC_DRV_AT91SAM9_GPBR config RTC_DRV_AU1XXX tristate "Au1xxx Counter0 RTC support" - depends on SOC_AU1X00 + depends on MIPS_ALCHEMY help This is a driver for the Au1xxx on-chip Counter0 (Time-Of-Year counter) to be used as a RTC. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b23165..1acc7b3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -260,7 +260,7 @@ config SERIAL_8250_ACORN config SERIAL_8250_AU1X00 bool "Au1x00 serial port support" - depends on SERIAL_8250 != n && SOC_AU1X00 + depends on SERIAL_8250 != n && MIPS_ALCHEMY help If you have an Au1x00 SOC based board and want to use the serial port, say Y to this option. The driver can handle up to 4 serial ports, diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 6a58cb1..c2ddab1 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -45,7 +45,7 @@ config USB_ARCH_HAS_OHCI default y if STB03xxx default y if PPC_MPC52xx # MIPS: - default y if SOC_AU1X00 + default y if MIPS_ALCHEMY # SH: default y if CPU_SUBTYPE_SH7720 default y if CPU_SUBTYPE_SH7721 diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index fc57655..ba6b0a5 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1031,7 +1031,7 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver #endif -#ifdef CONFIG_SOC_AU1X00 +#ifdef CONFIG_MIPS_ALCHEMY #include "ohci-au1xxx.c" #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver #endif -- 1.7.1.1 From manuel.lauss@googlemail.com Thu Jul 15 21:45:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 21:45:49 +0200 (CEST) Received: from mail-bw0-f49.google.com ([209.85.214.49]:62513 "EHLO mail-bw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492453Ab0GOTpT (ORCPT ); Thu, 15 Jul 2010 21:45:19 +0200 Received: by mail-bw0-f49.google.com with SMTP id 15so902171bwz.36 for ; Thu, 15 Jul 2010 12:45:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=UV1FdQ33aRnkv7ALXE9J02z4HysguoxJeQ9B2zZbyNM=; b=d9s36WNlnb++p5cSG1Cia8kuDjQPGXiJNWwZ0VBnq5cD10hTfmHrkcZ9AzL59BOr7G 0lg1a7n/tQOfF2HogxWht+0H556eDZ7pjqXgbEJCsgB13MUSU6fM+i43r1ClorrJs5cs eE1tn/dMtsRVgcJTaLUEVrr1X5qfc3AtMOx2g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=TvuutXuJNfgRCk/nGB/d7DEgpkS9DkX13r1tpV9/XtXeU7anEG+ecBMXU0B4YocZtR K+GK9xjAzE28wf/qQ3AD81YX3TgM+81BpGlVPZLku3DxK3WGu16Ph1QdSWUevjenjBOq RD1rmVYadiYQY6VLVMhtln+C8f73kaqLk86BM= Received: by 10.204.142.205 with SMTP id r13mr76302bku.207.1279223119501; Thu, 15 Jul 2010 12:45:19 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id s17sm7274438bkx.18.2010.07.15.12.45.17 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Jul 2010 12:45:18 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss , Linux-serial Subject: [PATCH 2/2] serial: 8250: remove SERIAL_8250_AU1X00 Date: Thu, 15 Jul 2010 21:45:05 +0200 Message-Id: <1279223105-23816-2-git-send-email-manuel.lauss@googlemail.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1279223105-23816-1-git-send-email-manuel.lauss@googlemail.com> References: <1279223105-23816-1-git-send-email-manuel.lauss@googlemail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Remove the SERIAL_8250_AU1X00 config symbol. Instead, use the MIPS_ALCHEMY one which is always defined when building an Au1x00-based platform. Cc: Linux-serial Signed-off-by: Manuel Lauss --- This one depends on a previous patch (which removes SOC_AU1X00 and changes MACH_ALCHEMY) to apply cleanly (and then actually work), so I'd love for this to go in via the mips tree. arch/mips/alchemy/common/platform.c | 2 -- drivers/serial/8250.c | 13 +++---------- drivers/serial/Kconfig | 8 -------- 3 files changed, 3 insertions(+), 20 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 70f4abd..7186a02 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -50,7 +50,6 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, } static struct plat_serial8250_port au1x00_uart_data[] = { -#if defined(CONFIG_SERIAL_8250_AU1X00) #if defined(CONFIG_SOC_AU1000) PORT(UART0_PHYS_ADDR, AU1000_UART0_INT), PORT(UART1_PHYS_ADDR, AU1000_UART1_INT), @@ -71,7 +70,6 @@ static struct plat_serial8250_port au1x00_uart_data[] = { PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), #endif -#endif /* CONFIG_SERIAL_8250_AU1X00 */ { }, }; diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index 2420bec..92f34b3 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -302,7 +302,7 @@ static const struct serial8250_config uart_config[] = { }, }; -#if defined (CONFIG_SERIAL_8250_AU1X00) +#if defined(CONFIG_MIPS_ALCHEMY) /* Au1x00 UART hardware has a weird register layout */ static const u8 au_io_in_map[] = { @@ -422,7 +422,6 @@ static unsigned int mem32_serial_in(struct uart_port *p, int offset) return readl(p->membase + offset); } -#ifdef CONFIG_SERIAL_8250_AU1X00 static unsigned int au_serial_in(struct uart_port *p, int offset) { offset = map_8250_in_reg(p, offset) << p->regshift; @@ -434,7 +433,6 @@ static void au_serial_out(struct uart_port *p, int offset, int value) offset = map_8250_out_reg(p, offset) << p->regshift; __raw_writel(value, p->membase + offset); } -#endif static unsigned int tsi_serial_in(struct uart_port *p, int offset) { @@ -503,12 +501,11 @@ static void set_io_from_upio(struct uart_port *p) p->serial_out = mem32_serial_out; break; -#ifdef CONFIG_SERIAL_8250_AU1X00 case UPIO_AU: p->serial_in = au_serial_in; p->serial_out = au_serial_out; break; -#endif + case UPIO_TSI: p->serial_in = tsi_serial_in; p->serial_out = tsi_serial_out; @@ -535,9 +532,7 @@ serial_out_sync(struct uart_8250_port *up, int offset, int value) switch (p->iotype) { case UPIO_MEM: case UPIO_MEM32: -#ifdef CONFIG_SERIAL_8250_AU1X00 case UPIO_AU: -#endif case UPIO_DWAPB: p->serial_out(p, offset, value); p->serial_in(p, UART_LCR); /* safe, no side-effects */ @@ -573,7 +568,7 @@ static inline void _serial_dl_write(struct uart_8250_port *up, int value) serial_outp(up, UART_DLM, value >> 8 & 0xff); } -#if defined(CONFIG_SERIAL_8250_AU1X00) +#if defined(CONFIG_MIPS_ALCHEMY) /* Au1x00 haven't got a standard divisor latch */ static int serial_dl_read(struct uart_8250_port *up) { @@ -2596,11 +2591,9 @@ static void serial8250_config_port(struct uart_port *port, int flags) if (flags & UART_CONFIG_TYPE) autoconfig(up, probeflags); -#ifdef CONFIG_SERIAL_8250_AU1X00 /* if access method is AU, it is a 16550 with a quirk */ if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU) up->bugs |= UART_BUG_NOMSR; -#endif if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) autoconfig_irq(up); diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1acc7b3..e437ce8 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -258,14 +258,6 @@ config SERIAL_8250_ACORN system, say Y to this option. The driver can handle 1, 2, or 3 port cards. If unsure, say N. -config SERIAL_8250_AU1X00 - bool "Au1x00 serial port support" - depends on SERIAL_8250 != n && MIPS_ALCHEMY - help - If you have an Au1x00 SOC based board and want to use the serial port, - say Y to this option. The driver can handle up to 4 serial ports, - depending on the SOC. If unsure, say N. - config SERIAL_8250_RM9K bool "Support for MIPS RM9xxx integrated serial port" depends on SERIAL_8250 != n && SERIAL_RM9000 -- 1.7.1.1 From lars@metafoo.de Thu Jul 15 23:06:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 23:06:55 +0200 (CEST) Received: from smtp-out-248.synserver.de ([212.40.180.248]:1053 "HELO smtp-out-247.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1492115Ab0GOVGi (ORCPT ); Thu, 15 Jul 2010 23:06:38 +0200 Received: (qmail 507 invoked by uid 0); 15 Jul 2010 21:06:31 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 32135 Received: from d077238.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.238] by 217.119.54.77 with SMTP; 15 Jul 2010 21:06:28 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen , Andrew Morton , Matt Fleming , linux-mmc@vger.kernel.org Subject: [PATCH v6] MMC: Add JZ4740 mmc driver Date: Thu, 15 Jul 2010 23:06:04 +0200 Message-Id: <1279227964-17801-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1278973245-25451-1-git-send-email-lars@metafoo.de> References: <1278973245-25451-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for the mmc controller on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen Acked-by: Matt Fleming Cc: Andrew Morton Cc: Matt Fleming Cc: linux-mmc@vger.kernel.org --- Changes since v1 - Do not request IRQ with IRQF_DISABLED since it is a noop now - Use a generous slack for the timeout timer. It does not need to be accurate. Changes since v2 - Use sg_mapping_to iterate over sg elements in mmc read and write functions - Use bitops instead of a spinlock and a variable for testing whether a request has been finished. - Rework irq and timeout handling in order to get rid of locking in hot paths Changes since v3 - Drastically decrease IRQ poll timeout. Now when the poll timeout is reached the IRQ which was polled is enabled. A variable keeps track of what state the driver is in and what has to be done next when the IRQ handler is entered again. By doing so busy looping is reduced, but overall performance can be maintained. - Move header file from include/linux/mmc to arch/mips/include/asm/mach-jz4740 Changes since v4 - Rework Kconfig entry Changes since v5 - Avoid reloading the fifo address before each read/write --- arch/mips/include/asm/mach-jz4740/jz4740_mmc.h | 15 + drivers/mmc/host/Kconfig | 9 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/jz4740_mmc.c | 1033 ++++++++++++++++++++++++ 4 files changed, 1058 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h create mode 100644 drivers/mmc/host/jz4740_mmc.c diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h new file mode 100644 index 0000000..8543f43 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h @@ -0,0 +1,15 @@ +#ifndef __LINUX_MMC_JZ4740_MMC +#define __LINUX_MMC_JZ4740_MMC + +struct jz4740_mmc_platform_data { + int gpio_power; + int gpio_card_detect; + int gpio_read_only; + unsigned card_detect_active_low:1; + unsigned read_only_active_low:1; + unsigned power_active_low:1; + + unsigned data_1bit:1; +}; + +#endif diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index f06d06e..d25e22c 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -432,3 +432,12 @@ config MMC_SH_MMCIF This selects the MMC Host Interface controler (MMCIF). This driver supports MMCIF in sh7724/sh7757/sh7372. + +config MMC_JZ4740 + tristate "JZ4740 SD/Multimedia Card Interface support" + depends on MACH_JZ4740 + help + This selects support for the SD/MMC controller on Ingenic JZ4740 + SoCs. + If you have a board based on such a SoC and with a SD/MMC slot, + say Y or M here. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index e30c2ee..f4e53c9 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MMC_CB710) += cb710-mmc.o obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o +obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o sdhci-of-y := sdhci-of-core.o diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c new file mode 100644 index 0000000..12efd9c --- /dev/null +++ b/drivers/mmc/host/jz4740_mmc.c @@ -0,0 +1,1033 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 SD/MMC controller driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#define JZ_REG_MMC_STRPCL 0x00 +#define JZ_REG_MMC_STATUS 0x04 +#define JZ_REG_MMC_CLKRT 0x08 +#define JZ_REG_MMC_CMDAT 0x0C +#define JZ_REG_MMC_RESTO 0x10 +#define JZ_REG_MMC_RDTO 0x14 +#define JZ_REG_MMC_BLKLEN 0x18 +#define JZ_REG_MMC_NOB 0x1C +#define JZ_REG_MMC_SNOB 0x20 +#define JZ_REG_MMC_IMASK 0x24 +#define JZ_REG_MMC_IREG 0x28 +#define JZ_REG_MMC_CMD 0x2C +#define JZ_REG_MMC_ARG 0x30 +#define JZ_REG_MMC_RESP_FIFO 0x34 +#define JZ_REG_MMC_RXFIFO 0x38 +#define JZ_REG_MMC_TXFIFO 0x3C + +#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) +#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) +#define JZ_MMC_STRPCL_START_READWAIT BIT(5) +#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) +#define JZ_MMC_STRPCL_RESET BIT(3) +#define JZ_MMC_STRPCL_START_OP BIT(2) +#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) +#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) +#define JZ_MMC_STRPCL_CLOCK_START BIT(1) + + +#define JZ_MMC_STATUS_IS_RESETTING BIT(15) +#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) +#define JZ_MMC_STATUS_PRG_DONE BIT(13) +#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) +#define JZ_MMC_STATUS_END_CMD_RES BIT(11) +#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) +#define JZ_MMC_STATUS_IS_READWAIT BIT(9) +#define JZ_MMC_STATUS_CLK_EN BIT(8) +#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) +#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) +#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) +#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) +#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) +#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) +#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) +#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) + +#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) +#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) + + +#define JZ_MMC_CMDAT_IO_ABORT BIT(11) +#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) +#define JZ_MMC_CMDAT_DMA_EN BIT(8) +#define JZ_MMC_CMDAT_INIT BIT(7) +#define JZ_MMC_CMDAT_BUSY BIT(6) +#define JZ_MMC_CMDAT_STREAM BIT(5) +#define JZ_MMC_CMDAT_WRITE BIT(4) +#define JZ_MMC_CMDAT_DATA_EN BIT(3) +#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) +#define JZ_MMC_CMDAT_RSP_R1 1 +#define JZ_MMC_CMDAT_RSP_R2 2 +#define JZ_MMC_CMDAT_RSP_R3 3 + +#define JZ_MMC_IRQ_SDIO BIT(7) +#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) +#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) +#define JZ_MMC_IRQ_END_CMD_RES BIT(2) +#define JZ_MMC_IRQ_PRG_DONE BIT(1) +#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) + + +#define JZ_MMC_CLK_RATE 24000000 + +enum jz4740_mmc_state { + JZ4740_MMC_STATE_READ_RESPONSE, + JZ4740_MMC_STATE_TRANSFER_DATA, + JZ4740_MMC_STATE_SEND_STOP, + JZ4740_MMC_STATE_DONE, +}; + +struct jz4740_mmc_host { + struct mmc_host *mmc; + struct platform_device *pdev; + struct jz4740_mmc_platform_data *pdata; + struct clk *clk; + + int irq; + int card_detect_irq; + + struct resource *mem; + void __iomem *base; + struct mmc_request *req; + struct mmc_command *cmd; + + unsigned long waiting; + + uint32_t cmdat; + + uint16_t irq_mask; + + spinlock_t lock; + + struct timer_list timeout_timer; + struct sg_mapping_iter miter; + enum jz4740_mmc_state state; +}; + +static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, + unsigned int irq, bool enabled) +{ + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + if (enabled) + host->irq_mask &= ~irq; + else + host->irq_mask |= irq; + spin_unlock_irqrestore(&host->lock, flags); + + writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK); +} + +static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, + bool start_transfer) +{ + uint16_t val = JZ_MMC_STRPCL_CLOCK_START; + + if (start_transfer) + val |= JZ_MMC_STRPCL_START_OP; + + writew(val, host->base + JZ_REG_MMC_STRPCL); +} + +static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) +{ + uint32_t status; + unsigned int timeout = 1000; + + writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); + do { + status = readl(host->base + JZ_REG_MMC_STATUS); + } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); +} + +static void jz4740_mmc_reset(struct jz4740_mmc_host *host) +{ + uint32_t status; + unsigned int timeout = 1000; + + writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); + udelay(10); + do { + status = readl(host->base + JZ_REG_MMC_STATUS); + } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); +} + +static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) +{ + struct mmc_request *req; + + req = host->req; + host->req = NULL; + + mmc_request_done(host->mmc, req); +} + +static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, + unsigned int irq) +{ + unsigned int timeout = 0x800; + uint16_t status; + + do { + status = readw(host->base + JZ_REG_MMC_IREG); + } while (!(status & irq) && --timeout); + + if (timeout == 0) { + set_bit(0, &host->waiting); + mod_timer(&host->timeout_timer, jiffies + 5*HZ); + jz4740_mmc_set_irq_enabled(host, irq, true); + return true; + } + + return false; +} + +static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + int status; + + status = readl(host->base + JZ_REG_MMC_STATUS); + if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { + if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { + host->req->cmd->error = -ETIMEDOUT; + data->error = -ETIMEDOUT; + } else { + host->req->cmd->error = -EIO; + data->error = -EIO; + } + } +} + +static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + struct sg_mapping_iter *miter = &host->miter; + void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; + uint32_t *buf; + bool timeout; + size_t i, j; + + while (sg_miter_next(miter)) { + buf = miter->addr; + i = miter->length / 4; + j = i / 8; + i = i & 0x7; + while (j) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + writel(buf[0], fifo_addr); + writel(buf[1], fifo_addr); + writel(buf[2], fifo_addr); + writel(buf[3], fifo_addr); + writel(buf[4], fifo_addr); + writel(buf[5], fifo_addr); + writel(buf[6], fifo_addr); + writel(buf[7], fifo_addr); + buf += 8; + --j; + } + if (unlikely(i)) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + while (i) { + writel(*buf, fifo_addr); + ++buf; + --i; + } + } + data->bytes_xfered += miter->length; + } + sg_miter_stop(miter); + + return false; + +poll_timeout: + miter->consumed = (void *)buf - miter->addr; + data->bytes_xfered += miter->consumed; + sg_miter_stop(miter); + + return true; +} + +static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, + struct mmc_data *data) +{ + struct sg_mapping_iter *miter = &host->miter; + void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; + uint32_t *buf; + uint32_t d; + uint16_t status; + size_t i, j; + unsigned int timeout; + + while (sg_miter_next(miter)) { + buf = miter->addr; + i = miter->length; + j = i / 32; + i = i & 0x1f; + while (j) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + buf[0] = readl(fifo_addr); + buf[1] = readl(fifo_addr); + buf[2] = readl(fifo_addr); + buf[3] = readl(fifo_addr); + buf[4] = readl(fifo_addr); + buf[5] = readl(fifo_addr); + buf[6] = readl(fifo_addr); + buf[7] = readl(fifo_addr); + + buf += 8; + --j; + } + + if (unlikely(i)) { + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); + if (unlikely(timeout)) + goto poll_timeout; + + while (i >= 4) { + *buf++ = readl(fifo_addr); + i -= 4; + } + if (unlikely(i > 0)) { + d = readl(fifo_addr); + memcpy(buf, &d, i); + } + } + data->bytes_xfered += miter->length; + + /* This can go away once MIPS implements + * flush_kernel_dcache_page */ + flush_dcache_page(miter->page); + } + sg_miter_stop(miter); + + /* For whatever reason there is sometime one word more in the fifo then + * requested */ + timeout = 1000; + status = readl(host->base + JZ_REG_MMC_STATUS); + while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { + d = readl(fifo_addr); + status = readl(host->base + JZ_REG_MMC_STATUS); + } + + return false; + +poll_timeout: + miter->consumed = (void *)buf - miter->addr; + data->bytes_xfered += miter->consumed; + sg_miter_stop(miter); + + return true; +} + +static void jz4740_mmc_timeout(unsigned long data) +{ + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data; + + if (!test_and_clear_bit(0, &host->waiting)) + return; + + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); + + host->req->cmd->error = -ETIMEDOUT; + jz4740_mmc_request_done(host); +} + +static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, + struct mmc_command *cmd) +{ + int i; + uint16_t tmp; + void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; + + if (cmd->flags & MMC_RSP_136) { + tmp = readw(fifo_addr); + for (i = 0; i < 4; ++i) { + cmd->resp[i] = tmp << 24; + tmp = readw(fifo_addr); + cmd->resp[i] |= tmp << 8; + tmp = readw(fifo_addr); + cmd->resp[i] |= tmp >> 8; + } + } else { + cmd->resp[0] = readw(fifo_addr) << 24; + cmd->resp[0] |= readw(fifo_addr) << 8; + cmd->resp[0] |= readw(fifo_addr) & 0xff; + } +} + +static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, + struct mmc_command *cmd) +{ + uint32_t cmdat = host->cmdat; + + host->cmdat &= ~JZ_MMC_CMDAT_INIT; + jz4740_mmc_clock_disable(host); + + host->cmd = cmd; + + if (cmd->flags & MMC_RSP_BUSY) + cmdat |= JZ_MMC_CMDAT_BUSY; + + switch (mmc_resp_type(cmd)) { + case MMC_RSP_R1B: + case MMC_RSP_R1: + cmdat |= JZ_MMC_CMDAT_RSP_R1; + break; + case MMC_RSP_R2: + cmdat |= JZ_MMC_CMDAT_RSP_R2; + break; + case MMC_RSP_R3: + cmdat |= JZ_MMC_CMDAT_RSP_R3; + break; + default: + break; + } + + if (cmd->data) { + cmdat |= JZ_MMC_CMDAT_DATA_EN; + if (cmd->data->flags & MMC_DATA_WRITE) + cmdat |= JZ_MMC_CMDAT_WRITE; + if (cmd->data->flags & MMC_DATA_STREAM) + cmdat |= JZ_MMC_CMDAT_STREAM; + + writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); + writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); + } + + writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); + writel(cmd->arg, host->base + JZ_REG_MMC_ARG); + writel(cmdat, host->base + JZ_REG_MMC_CMDAT); + + jz4740_mmc_clock_enable(host, 1); +} + +static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) +{ + struct mmc_command *cmd = host->req->cmd; + struct mmc_data *data = cmd->data; + int direction; + + if (data->flags & MMC_DATA_READ) + direction = SG_MITER_TO_SG; + else + direction = SG_MITER_FROM_SG; + + sg_miter_start(&host->miter, data->sg, data->sg_len, direction); +} + + +static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) +{ + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; + struct mmc_command *cmd = host->req->cmd; + struct mmc_request *req = host->req; + bool timeout = false; + + if (cmd->error) + host->state = JZ4740_MMC_STATE_DONE; + + switch (host->state) { + case JZ4740_MMC_STATE_READ_RESPONSE: + if (cmd->flags & MMC_RSP_PRESENT) + jz4740_mmc_read_response(host, cmd); + + if (!cmd->data) + break; + + jz_mmc_prepare_data_transfer(host); + + case JZ4740_MMC_STATE_TRANSFER_DATA: + if (cmd->data->flags & MMC_DATA_READ) + timeout = jz4740_mmc_read_data(host, cmd->data); + else + timeout = jz4740_mmc_write_data(host, cmd->data); + + if (unlikely(timeout)) { + host->state = JZ4740_MMC_STATE_TRANSFER_DATA; + break; + } + + jz4740_mmc_transfer_check_state(host, cmd->data); + + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); + if (unlikely(timeout)) { + host->state = JZ4740_MMC_STATE_SEND_STOP; + break; + } + writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG); + + case JZ4740_MMC_STATE_SEND_STOP: + if (!req->stop) + break; + + jz4740_mmc_send_command(host, req->stop); + + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE); + if (timeout) { + host->state = JZ4740_MMC_STATE_DONE; + break; + } + case JZ4740_MMC_STATE_DONE: + break; + } + + if (!timeout) + jz4740_mmc_request_done(host); + + return IRQ_HANDLED; +} + +static irqreturn_t jz_mmc_irq(int irq, void *devid) +{ + struct jz4740_mmc_host *host = devid; + struct mmc_command *cmd = host->cmd; + uint16_t irq_reg, status, tmp; + + irq_reg = readw(host->base + JZ_REG_MMC_IREG); + + tmp = irq_reg; + irq_reg &= ~host->irq_mask; + + tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | + JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); + + if (tmp != irq_reg) + writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG); + + if (irq_reg & JZ_MMC_IRQ_SDIO) { + writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG); + mmc_signal_sdio_irq(host->mmc); + irq_reg &= ~JZ_MMC_IRQ_SDIO; + } + + if (host->req && cmd && irq_reg) { + if (test_and_clear_bit(0, &host->waiting)) { + del_timer(&host->timeout_timer); + + status = readl(host->base + JZ_REG_MMC_STATUS); + + if (status & JZ_MMC_STATUS_TIMEOUT_RES) { + cmd->error = -ETIMEDOUT; + } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { + cmd->error = -EIO; + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | + JZ_MMC_STATUS_CRC_WRITE_ERROR)) { + if (cmd->data) + cmd->data->error = -EIO; + cmd->error = -EIO; + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | + JZ_MMC_STATUS_CRC_WRITE_ERROR)) { + if (cmd->data) + cmd->data->error = -EIO; + cmd->error = -EIO; + } + + jz4740_mmc_set_irq_enabled(host, irq_reg, false); + writew(irq_reg, host->base + JZ_REG_MMC_IREG); + + return IRQ_WAKE_THREAD; + } + } + + return IRQ_HANDLED; +} + +static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) +{ + int div = 0; + int real_rate; + + jz4740_mmc_clock_disable(host); + clk_set_rate(host->clk, JZ_MMC_CLK_RATE); + + real_rate = clk_get_rate(host->clk); + + while (real_rate > rate && div < 7) { + ++div; + real_rate >>= 1; + } + + writew(div, host->base + JZ_REG_MMC_CLKRT); + return real_rate; +} + +static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + + host->req = req; + + writew(0xffff, host->base + JZ_REG_MMC_IREG); + + writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG); + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); + + host->state = JZ4740_MMC_STATE_READ_RESPONSE; + set_bit(0, &host->waiting); + mod_timer(&host->timeout_timer, jiffies + 5*HZ); + jz4740_mmc_send_command(host, req->cmd); +} + +static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (ios->clock) + jz4740_mmc_set_clock_rate(host, ios->clock); + + switch (ios->power_mode) { + case MMC_POWER_UP: + jz4740_mmc_reset(host); + if (gpio_is_valid(host->pdata->gpio_power)) + gpio_set_value(host->pdata->gpio_power, + !host->pdata->power_active_low); + host->cmdat |= JZ_MMC_CMDAT_INIT; + clk_enable(host->clk); + break; + case MMC_POWER_ON: + break; + default: + if (gpio_is_valid(host->pdata->gpio_power)) + gpio_set_value(host->pdata->gpio_power, + host->pdata->power_active_low); + clk_disable(host->clk); + break; + } + + switch (ios->bus_width) { + case MMC_BUS_WIDTH_1: + host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT; + break; + case MMC_BUS_WIDTH_4: + host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; + break; + default: + break; + } +} + +static int jz4740_mmc_get_ro(struct mmc_host *mmc) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (!gpio_is_valid(host->pdata->gpio_read_only)) + return -ENOSYS; + + return gpio_get_value(host->pdata->gpio_read_only) ^ + host->pdata->read_only_active_low; +} + +static int jz4740_mmc_get_cd(struct mmc_host *mmc) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + if (!gpio_is_valid(host->pdata->gpio_card_detect)) + return -ENOSYS; + + return gpio_get_value(host->pdata->gpio_card_detect) ^ + host->pdata->card_detect_active_low; +} + +static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid) +{ + struct jz4740_mmc_host *host = devid; + + mmc_detect_change(host->mmc, HZ / 2); + + return IRQ_HANDLED; +} + +static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct jz4740_mmc_host *host = mmc_priv(mmc); + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); +} + +static const struct mmc_host_ops jz4740_mmc_ops = { + .request = jz4740_mmc_request, + .set_ios = jz4740_mmc_set_ios, + .get_ro = jz4740_mmc_get_ro, + .get_cd = jz4740_mmc_get_cd, + .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, +}; + +static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = { + JZ_GPIO_BULK_PIN(MSC_CMD), + JZ_GPIO_BULK_PIN(MSC_CLK), + JZ_GPIO_BULK_PIN(MSC_DATA0), + JZ_GPIO_BULK_PIN(MSC_DATA1), + JZ_GPIO_BULK_PIN(MSC_DATA2), + JZ_GPIO_BULK_PIN(MSC_DATA3), +}; + +static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio, + const char *name, bool output, int value) +{ + int ret; + + if (!gpio_is_valid(gpio)) + return 0; + + ret = gpio_request(gpio, name); + if (ret) { + dev_err(dev, "Failed to request %s gpio: %d\n", name, ret); + return ret; + } + + if (output) + gpio_direction_output(gpio, value); + else + gpio_direction_input(gpio); + + return 0; +} + +static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev) +{ + int ret; + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (!pdata) + return 0; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect, + "MMC detect change", false, 0); + if (ret) + goto err; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only, + "MMC read only", false, 0); + if (ret) + goto err_free_gpio_card_detect; + + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power, + "MMC read only", true, pdata->power_active_low); + if (ret) + goto err_free_gpio_read_only; + + return 0; + +err_free_gpio_read_only: + if (gpio_is_valid(pdata->gpio_read_only)) + gpio_free(pdata->gpio_read_only); +err_free_gpio_card_detect: + if (gpio_is_valid(pdata->gpio_card_detect)) + gpio_free(pdata->gpio_card_detect); +err: + return ret; +} + +static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev, + struct jz4740_mmc_host *host) +{ + int ret; + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (gpio_is_valid(pdata->gpio_card_detect)) + return 0; + + host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect); + + if (host->card_detect_irq < 0) { + dev_warn(&pdev->dev, "Failed to get card detect irq\n"); + return 0; + } + return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "MMC card detect", host); + + + return ret; +} + +static void jz4740_mmc_free_gpios(struct platform_device *pdev) +{ + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; + + if (!pdata) + return; + + if (gpio_is_valid(pdata->gpio_power)) + gpio_free(pdata->gpio_power); + if (gpio_is_valid(pdata->gpio_read_only)) + gpio_free(pdata->gpio_read_only); + if (gpio_is_valid(pdata->gpio_card_detect)) + gpio_free(pdata->gpio_card_detect); +} + +static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host) +{ + size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins); + if (host->pdata && host->pdata->data_1bit) + num_pins -= 3; + + return num_pins; +} + +static int __devinit jz4740_mmc_probe(struct platform_device* pdev) +{ + int ret; + struct mmc_host *mmc; + struct jz4740_mmc_host *host; + struct jz4740_mmc_platform_data *pdata; + + pdata = pdev->dev.platform_data; + + mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); + if (!mmc) { + dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); + return -ENOMEM; + } + + host = mmc_priv(mmc); + host->pdata = pdata; + + host->irq = platform_get_irq(pdev, 0); + if (host->irq < 0) { + ret = host->irq; + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); + goto err_free_host; + } + + host->clk = clk_get(&pdev->dev, "mmc"); + if (!host->clk) { + ret = -ENOENT; + dev_err(&pdev->dev, "Failed to get mmc clock\n"); + goto err_free_host; + } + + host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!host->mem) { + ret = -ENOENT; + dev_err(&pdev->dev, "Failed to get base platform memory\n"); + goto err_clk_put; + } + + host->mem = request_mem_region(host->mem->start, + resource_size(host->mem), pdev->name); + if (!host->mem) { + ret = -EBUSY; + dev_err(&pdev->dev, "Failed to request base memory region\n"); + goto err_clk_put; + } + + host->base = ioremap_nocache(host->mem->start, resource_size(host->mem)); + if (!host->base) { + ret = -EBUSY; + dev_err(&pdev->dev, "Failed to ioremap base memory\n"); + goto err_release_mem_region; + } + + ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + if (ret) { + dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret); + goto err_iounmap; + } + + ret = jz4740_mmc_request_gpios(pdev); + if (ret) + goto err_gpio_bulk_free; + + mmc->ops = &jz4740_mmc_ops; + mmc->f_min = JZ_MMC_CLK_RATE / 128; + mmc->f_max = JZ_MMC_CLK_RATE; + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA; + mmc->caps |= MMC_CAP_SDIO_IRQ; + + mmc->max_blk_size = (1 << 10) - 1; + mmc->max_blk_count = (1 << 15) - 1; + mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; + + mmc->max_phys_segs = 128; + mmc->max_hw_segs = 128; + mmc->max_seg_size = mmc->max_req_size; + + host->mmc = mmc; + host->pdev = pdev; + spin_lock_init(&host->lock); + host->irq_mask = 0xffff; + + ret = jz4740_mmc_request_cd_irq(pdev, host); + if (ret) { + dev_err(&pdev->dev, "Failed to request card detect irq\n"); + goto err_free_gpios; + } + + ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, + dev_name(&pdev->dev), host); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); + goto err_free_card_detect_irq; + } + + jz4740_mmc_reset(host); + jz4740_mmc_clock_disable(host); + setup_timer(&host->timeout_timer, jz4740_mmc_timeout, + (unsigned long)host); + /* It is not important when it times out, it just needs to timeout. */ + set_timer_slack(&host->timeout_timer, HZ); + + platform_set_drvdata(pdev, host); + ret = mmc_add_host(mmc); + + if (ret) { + dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); + goto err_free_irq; + } + dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); + + return 0; + +err_free_irq: + free_irq(host->irq, host); +err_free_card_detect_irq: + if (host->card_detect_irq >= 0) + free_irq(host->card_detect_irq, host); +err_free_gpios: + jz4740_mmc_free_gpios(pdev); +err_gpio_bulk_free: + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); +err_iounmap: + iounmap(host->base); +err_release_mem_region: + release_mem_region(host->mem->start, resource_size(host->mem)); +err_clk_put: + clk_put(host->clk); +err_free_host: + platform_set_drvdata(pdev, NULL); + mmc_free_host(mmc); + + return ret; +} + +static int __devexit jz4740_mmc_remove(struct platform_device *pdev) +{ + struct jz4740_mmc_host *host = platform_get_drvdata(pdev); + + del_timer_sync(&host->timeout_timer); + jz4740_mmc_set_irq_enabled(host, 0xff, false); + jz4740_mmc_reset(host); + + mmc_remove_host(host->mmc); + + free_irq(host->irq, host); + if (host->card_detect_irq >= 0) + free_irq(host->card_detect_irq, host); + + jz4740_mmc_free_gpios(pdev); + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + iounmap(host->base); + release_mem_region(host->mem->start, resource_size(host->mem)); + + clk_put(host->clk); + + platform_set_drvdata(pdev, NULL); + mmc_free_host(host->mmc); + + return 0; +} + +#ifdef CONFIG_PM + +static int jz4740_mmc_suspend(struct device *dev) +{ + struct jz4740_mmc_host *host = dev_get_drvdata(dev); + + mmc_suspend_host(host->mmc); + + jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + return 0; +} + +static int jz4740_mmc_resume(struct device *dev) +{ + struct jz4740_mmc_host *host = dev_get_drvdata(dev); + + jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); + + mmc_resume_host(host->mmc); + + return 0; +} + +const struct dev_pm_ops jz4740_mmc_pm_ops = { + .suspend = jz4740_mmc_suspend, + .resume = jz4740_mmc_resume, + .poweroff = jz4740_mmc_suspend, + .restore = jz4740_mmc_resume, +}; + +#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) +#else +#define JZ4740_MMC_PM_OPS NULL +#endif + +static struct platform_driver jz4740_mmc_driver = { + .probe = jz4740_mmc_probe, + .remove = __devexit_p(jz4740_mmc_remove), + .driver = { + .name = "jz4740-mmc", + .owner = THIS_MODULE, + .pm = JZ4740_MMC_PM_OPS, + }, +}; + +static int __init jz4740_mmc_init(void) +{ + return platform_driver_register(&jz4740_mmc_driver); +} +module_init(jz4740_mmc_init); + +static void __exit jz4740_mmc_exit(void) +{ + platform_driver_unregister(&jz4740_mmc_driver); +} +module_exit(jz4740_mmc_exit); + +MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lars-Peter Clausen "); -- 1.5.6.5 From akpm@linux-foundation.org Thu Jul 15 23:17:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 23:17:15 +0200 (CEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:47449 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492054Ab0GOVRI (ORCPT ); Thu, 15 Jul 2010 23:17:08 +0200 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id o6FLGsYR017228 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 15 Jul 2010 14:16:55 -0700 Received: from akpm.mtv.corp.google.com (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id o6FLGrZn019686; Thu, 15 Jul 2010 14:16:54 -0700 Date: Thu, 15 Jul 2010 14:16:53 -0700 From: Andrew Morton To: Lars-Peter Clausen Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Matt Fleming , linux-mmc@vger.kernel.org Subject: Re: [PATCH v6] MMC: Add JZ4740 mmc driver Message-Id: <20100715141653.1c0b6a8d.akpm@linux-foundation.org> In-Reply-To: <1279227964-17801-1-git-send-email-lars@metafoo.de> References: <1278973245-25451-1-git-send-email-lars@metafoo.de> <1279227964-17801-1-git-send-email-lars@metafoo.de> X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.9; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Thu, 15 Jul 2010 23:06:04 +0200 Lars-Peter Clausen wrote: > This patch adds support for the mmc controller on JZ4740 SoCs. > > > ... > > + if (gpio_is_valid(host->pdata->gpio_power)) > + gpio_set_value(host->pdata->gpio_power, > + !host->pdata->power_active_low); > > ... > Should this driver have a `depends on GPIOLIB' in Kconfig? From lars@metafoo.de Thu Jul 15 23:38:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jul 2010 23:38:28 +0200 (CEST) Received: from mailhost.informatik.uni-hamburg.de ([134.100.9.70]:65205 "EHLO mailhost.informatik.uni-hamburg.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492115Ab0GOViY (ORCPT ); Thu, 15 Jul 2010 23:38:24 +0200 Received: from localhost (localhost [127.0.0.1]) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTP id 56328A9B; Thu, 15 Jul 2010 23:38:17 +0200 (CEST) X-Virus-Scanned: amavisd-new at informatik.uni-hamburg.de Received: from mailhost.informatik.uni-hamburg.de ([127.0.0.1]) by localhost (mailhost.informatik.uni-hamburg.de [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 0+PLLWyyW+vi; Thu, 15 Jul 2010 23:38:16 +0200 (CEST) Received: from [172.31.16.213] (d077238.adsl.hansenet.de [80.171.77.238]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: 7clausen) by mailhost.informatik.uni-hamburg.de (Postfix) with ESMTPSA id 613BDA9A; Thu, 15 Jul 2010 23:38:05 +0200 (CEST) Message-ID: <4C3F7FAD.5010106@metafoo.de> Date: Thu, 15 Jul 2010 23:37:49 +0200 From: Lars-Peter Clausen User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) MIME-Version: 1.0 To: Andrew Morton CC: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Matt Fleming , linux-mmc@vger.kernel.org Subject: Re: [PATCH v6] MMC: Add JZ4740 mmc driver References: <1278973245-25451-1-git-send-email-lars@metafoo.de> <1279227964-17801-1-git-send-email-lars@metafoo.de> <20100715141653.1c0b6a8d.akpm@linux-foundation.org> In-Reply-To: <20100715141653.1c0b6a8d.akpm@linux-foundation.org> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Andrew Morton wrote: > On Thu, 15 Jul 2010 23:06:04 +0200 > Lars-Peter Clausen wrote: > >> This patch adds support for the mmc controller on JZ4740 SoCs. >> >> >> ... >> >> + if (gpio_is_valid(host->pdata->gpio_power)) >> + gpio_set_value(host->pdata->gpio_power, >> + !host->pdata->power_active_low); >> >> ... >> > > Should this driver have a `depends on GPIOLIB' in Kconfig? > The driver depends on MACH_JZ4740 which selects ARCH_REQUIRE_GPIOLIB, so there already is an implicit depends on GPIOLIB. - - Lars -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEUEARECAAYFAkw/f60ACgkQBX4mSR26RiNexQCfUXt0cqiMqEf17k+z+q6XVwRO ImEAmPKxeyX9ANVasUNL60f51GxKofg= =3NrE -----END PGP SIGNATURE----- From lars@metafoo.de Sat Jul 17 14:08:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:08:19 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1047 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491804Ab0GQMIN (ORCPT ); Sat, 17 Jul 2010 14:08:13 +0200 Received: (qmail 29037 invoked by uid 0); 17 Jul 2010 12:08:07 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 28959 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.77 with SMTP; 17 Jul 2010 12:08:07 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH v3] MIPS: Add base support for Ingenic JZ4740 System-on-a-Chip Date: Sat, 17 Jul 2010 14:07:51 +0200 Message-Id: <1279368471-20307-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds a new cpu type for the JZ4740 to the Linux MIPS architecture code. It also adds the iomem addresses for the different components found on a JZ4740 SoC. Signed-off-by: Lars-Peter Clausen -- Changes since v1 - Use physical addresses for base addresses Changes since v2 - Add cpu-feature-overrides.h --- arch/mips/include/asm/bootinfo.h | 6 ++ arch/mips/include/asm/cpu.h | 9 +++- arch/mips/include/asm/mach-jz4740/base.h | 26 ++++++++++ .../asm/mach-jz4740/cpu-feature-overrides.h | 51 ++++++++++++++++++++ arch/mips/include/asm/mach-jz4740/war.h | 25 ++++++++++ arch/mips/kernel/cpu-probe.c | 20 ++++++++ arch/mips/mm/tlbex.c | 5 ++ 7 files changed, 141 insertions(+), 1 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/base.h create mode 100644 arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-jz4740/war.h diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index 09eee09..15a8ef0 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -71,6 +71,12 @@ #define MACH_LEMOTE_LL2F 7 #define MACH_LOONGSON_END 8 +/* + * Valid machtype for group INGENIC + */ +#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */ +#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */ + extern char *system_type; const char *get_system_type(void); diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index a5acda4..b201a8f 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -34,7 +34,7 @@ #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 #define PRID_COMP_CAVIUM 0x0d0000 - +#define PRID_COMP_INGENIC 0xd00000 /* * Assigned values for the product ID register. In order to detect a @@ -133,6 +133,12 @@ #define PRID_IMP_CAVIUM_CN52XX 0x0700 /* + * These are the PRID's for when 23:16 == PRID_COMP_INGENIC + */ + +#define PRID_IMP_JZRISC 0x0200 + +/* * Definitions for 7:0 on legacy processors */ @@ -219,6 +225,7 @@ enum cpu_type_enum { CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358, + CPU_JZRISC, /* * MIPS64 class processors diff --git a/arch/mips/include/asm/mach-jz4740/base.h b/arch/mips/include/asm/mach-jz4740/base.h new file mode 100644 index 0000000..f373186 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/base.h @@ -0,0 +1,26 @@ +#ifndef __ASM_MACH_JZ4740_BASE_H__ +#define __ASM_MACH_JZ4740_BASE_H__ + +#define JZ4740_CPM_BASE_ADDR 0x10000000 +#define JZ4740_INTC_BASE_ADDR 0x10001000 +#define JZ4740_WDT_BASE_ADDR 0x10002000 +#define JZ4740_TCU_BASE_ADDR 0x10002010 +#define JZ4740_RTC_BASE_ADDR 0x10003000 +#define JZ4740_GPIO_BASE_ADDR 0x10010000 +#define JZ4740_AIC_BASE_ADDR 0x10020000 +#define JZ4740_MSC_BASE_ADDR 0x10021000 +#define JZ4740_UART0_BASE_ADDR 0x10030000 +#define JZ4740_UART1_BASE_ADDR 0x10031000 +#define JZ4740_I2C_BASE_ADDR 0x10042000 +#define JZ4740_SSI_BASE_ADDR 0x10043000 +#define JZ4740_SADC_BASE_ADDR 0x10070000 +#define JZ4740_EMC_BASE_ADDR 0x13010000 +#define JZ4740_DMAC_BASE_ADDR 0x13020000 +#define JZ4740_UHC_BASE_ADDR 0x13030000 +#define JZ4740_UDC_BASE_ADDR 0x13040000 +#define JZ4740_LCD_BASE_ADDR 0x13050000 +#define JZ4740_SLCD_BASE_ADDR 0x13050000 +#define JZ4740_CIM_BASE_ADDR 0x13060000 +#define JZ4740_IPU_BASE_ADDR 0x13080000 + +#endif diff --git a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h new file mode 100644 index 0000000..d12e5c6 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h @@ -0,0 +1,51 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 0 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define kernel_uses_llsc 1 +#define cpu_has_vtag_icache 1 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_pindexed_dcache 0 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h new file mode 100644 index 0000000..3a5bc17 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H +#define __ASM_MIPS_MACH_JZ4740_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 3562b85..9b66331 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -187,6 +187,7 @@ void __init check_wait(void) case CPU_BCM6358: case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: + case CPU_JZRISC: cpu_wait = r4k_wait; break; @@ -956,6 +957,22 @@ platform: } } +static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) +{ + decode_configs(c); + /* JZRISC does not implement the CP0 counter. */ + c->options &= ~MIPS_CPU_COUNTER; + switch (c->processor_id & 0xff00) { + case PRID_IMP_JZRISC: + c->cputype = CPU_JZRISC; + __cpu_name[cpu] = "Ingenic JZRISC"; + break; + default: + panic("Unknown Ingenic Processor ID!"); + break; + } +} + const char *__cpu_name[NR_CPUS]; const char *__elf_platform; @@ -994,6 +1011,9 @@ __cpuinit void cpu_probe(void) case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; + case PRID_COMP_INGENIC: + cpu_probe_ingenic(c, cpu); + break; } BUG_ON(!__cpu_name[cpu]); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 86f004d..4510e61 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, tlbw(p); break; + case CPU_JZRISC: + tlbw(p); + uasm_i_nop(p); + break; + default: panic("No TLB refill handler yet (CPU type: %d)", current_cpu_data.cputype); -- 1.5.6.5 From lars@metafoo.de Sat Jul 17 14:09:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:09:05 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1025 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491154Ab0GQMJA (ORCPT ); Sat, 17 Jul 2010 14:09:00 +0200 Received: (qmail 5444 invoked by uid 0); 17 Jul 2010 12:08:59 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 5366 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.81 with SMTP; 17 Jul 2010 12:08:59 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH v3] MIPS: jz4740: Add IRQ handler code Date: Sat, 17 Jul 2010 14:08:43 +0200 Message-Id: <1279368523-20427-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1276924111-11158-3-git-send-email-lars@metafoo.de> References: <1276924111-11158-3-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for IRQ handling on a JZ4740 SoC. Signed-off-by: Lars-Peter Clausen -- Changes since v1 - Reserve IRQ numbers for ADC IRQ demultiplexing Changes since v2 - Use __fls instead of ffs in the interrupt demuxer --- arch/mips/include/asm/mach-jz4740/irq.h | 57 +++++++++++ arch/mips/jz4740/irq.c | 167 +++++++++++++++++++++++++++++++ arch/mips/jz4740/irq.h | 21 ++++ 3 files changed, 245 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/irq.h create mode 100644 arch/mips/jz4740/irq.c create mode 100644 arch/mips/jz4740/irq.h diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h new file mode 100644 index 0000000..a865c98 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/irq.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 IRQ definitions + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __ASM_MACH_JZ4740_IRQ_H__ +#define __ASM_MACH_JZ4740_IRQ_H__ + +#define MIPS_CPU_IRQ_BASE 0 +#define JZ4740_IRQ_BASE 8 + +/* 1st-level interrupts */ +#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x)) +#define JZ4740_IRQ_I2C JZ4740_IRQ(1) +#define JZ4740_IRQ_UHC JZ4740_IRQ(3) +#define JZ4740_IRQ_UART1 JZ4740_IRQ(8) +#define JZ4740_IRQ_UART0 JZ4740_IRQ(9) +#define JZ4740_IRQ_SADC JZ4740_IRQ(12) +#define JZ4740_IRQ_MSC JZ4740_IRQ(14) +#define JZ4740_IRQ_RTC JZ4740_IRQ(15) +#define JZ4740_IRQ_SSI JZ4740_IRQ(16) +#define JZ4740_IRQ_CIM JZ4740_IRQ(17) +#define JZ4740_IRQ_AIC JZ4740_IRQ(18) +#define JZ4740_IRQ_ETH JZ4740_IRQ(19) +#define JZ4740_IRQ_DMAC JZ4740_IRQ(20) +#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21) +#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22) +#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23) +#define JZ4740_IRQ_UDC JZ4740_IRQ(24) +#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25) +#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26) +#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27) +#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28) +#define JZ4740_IRQ_IPU JZ4740_IRQ(29) +#define JZ4740_IRQ_LCD JZ4740_IRQ(30) + +/* 2nd-level interrupts */ +#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X)) + +#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x)) +#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x)) + +#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(176) + +#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6) + +#endif diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c new file mode 100644 index 0000000..7d33ff8 --- /dev/null +++ b/arch/mips/jz4740/irq.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 platform IRQ support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +static void __iomem *jz_intc_base; +static uint32_t jz_intc_wakeup; +static uint32_t jz_intc_saved; + +#define JZ_REG_INTC_STATUS 0x00 +#define JZ_REG_INTC_MASK 0x04 +#define JZ_REG_INTC_SET_MASK 0x08 +#define JZ_REG_INTC_CLEAR_MASK 0x0c +#define JZ_REG_INTC_PENDING 0x10 + +#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE) + +static void intc_irq_unmask(unsigned int irq) +{ + writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); +} + +static void intc_irq_mask(unsigned int irq) +{ + writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK); +} + +static int intc_irq_set_wake(unsigned int irq, unsigned int on) +{ + if (on) + jz_intc_wakeup |= IRQ_BIT(irq); + else + jz_intc_wakeup &= ~IRQ_BIT(irq); + + return 0; +} + +static struct irq_chip intc_irq_type = { + .name = "INTC", + .mask = intc_irq_mask, + .mask_ack = intc_irq_mask, + .unmask = intc_irq_unmask, + .set_wake = intc_irq_set_wake, +}; + +static irqreturn_t jz4740_cascade(int irq, void *data) +{ + uint32_t irq_reg; + + irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING); + + if (irq_reg) + generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE); + + return IRQ_HANDLED; +} + +static struct irqaction jz4740_cascade_action = { + .handler = jz4740_cascade, + .name = "JZ4740 cascade interrupt", +}; + +void __init arch_init_irq(void) +{ + int i; + mips_cpu_irq_init(); + + jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); + + for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { + intc_irq_mask(i); + set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); + } + + setup_irq(2, &jz4740_cascade_action); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + if (pending & STATUSF_IP2) + do_IRQ(2); + else if (pending & STATUSF_IP3) + do_IRQ(3); + else + spurious_interrupt(); +} + +void jz4740_intc_suspend(void) +{ + jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK); + writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK); + writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK); +} + +void jz4740_intc_resume(void) +{ + writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK); + writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK); +} + +#ifdef CONFIG_DEBUG_FS + +static inline void intc_seq_reg(struct seq_file *s, const char *name, + unsigned int reg) +{ + seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg)); +} + +static int intc_regs_show(struct seq_file *s, void *unused) +{ + intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS); + intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK); + intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING); + + return 0; +} + +static int intc_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, intc_regs_show, NULL); +} + +static const struct file_operations intc_regs_operations = { + .open = intc_regs_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init intc_debugfs_init(void) +{ + (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO, + NULL, NULL, &intc_regs_operations); + return 0; +} +subsys_initcall(intc_debugfs_init); + +#endif diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h new file mode 100644 index 0000000..56b5ead --- /dev/null +++ b/arch/mips/jz4740/irq.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __MIPS_JZ4740_IRQ_H__ +#define __MIPS_JZ4740_IRQ_H__ + +extern void jz4740_intc_suspend(void); +extern void jz4740_intc_resume(void); + +#endif -- 1.5.6.5 From lars@metafoo.de Sat Jul 17 14:10:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:10:23 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1068 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491917Ab0GQMKR (ORCPT ); Sat, 17 Jul 2010 14:10:17 +0200 Received: (qmail 8164 invoked by uid 0); 17 Jul 2010 12:10:16 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 7896 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.81 with SMTP; 17 Jul 2010 12:10:16 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH v4] MIPS: JZ4740: Add clock API support. Date: Sat, 17 Jul 2010 14:10:00 +0200 Message-Id: <1279368600-20575-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1277688263-28005-1-git-send-email-lars@metafoo.de> References: <1277688263-28005-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for managing the clocks found on JZ4740 SoC through the Linux clock API. Signed-off-by: Lars-Peter Clausen --- Changes since v2 - Fix setting of inital parents for spi and i2s clocks - In clk_set_parent(), preserve clock enabled/disabled state. - Set correct get_rate callback for the pll clock - Fix pll frequency rate formula Changes since v3 - Move clock initialization to arch_initcall --- arch/mips/include/asm/mach-jz4740/clock.h | 28 + arch/mips/jz4740/clock-debugfs.c | 109 ++++ arch/mips/jz4740/clock.c | 924 +++++++++++++++++++++++++++++ arch/mips/jz4740/clock.h | 76 +++ 4 files changed, 1137 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/clock.h create mode 100644 arch/mips/jz4740/clock-debugfs.c create mode 100644 arch/mips/jz4740/clock.c create mode 100644 arch/mips/jz4740/clock.h diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h new file mode 100644 index 0000000..1b7408d --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/clock.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __ASM_JZ4740_CLOCK_H__ +#define __ASM_JZ4740_CLOCK_H__ + +enum jz4740_wait_mode { + JZ4740_WAIT_MODE_IDLE, + JZ4740_WAIT_MODE_SLEEP, +}; + +void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode); + +void jz4740_clock_udc_enable_auto_suspend(void); +void jz4740_clock_udc_disable_auto_suspend(void); + +#endif diff --git a/arch/mips/jz4740/clock-debugfs.c b/arch/mips/jz4740/clock-debugfs.c new file mode 100644 index 0000000..330a0f2 --- /dev/null +++ b/arch/mips/jz4740/clock-debugfs.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen + * JZ4740 SoC clock support debugfs entries + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include "clock.h" + +static struct dentry *jz4740_clock_debugfs; + +static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value) +{ + struct clk *clk = data; + *value = clk_is_enabled(clk); + + return 0; +} + +static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value) +{ + struct clk *clk = data; + + if (value) + return clk_enable(clk); + else + clk_disable(clk); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled, + jz4740_clock_debugfs_show_enabled, + jz4740_clock_debugfs_set_enabled, + "%llu\n"); + +static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value) +{ + struct clk *clk = data; + *value = clk_get_rate(clk); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate, + jz4740_clock_debugfs_show_rate, + NULL, + "%llu\n"); + +void jz4740_clock_debugfs_add_clk(struct clk *clk) +{ + if (!jz4740_clock_debugfs) + return; + + clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs); + debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk, + &jz4740_clock_debugfs_ops_rate); + debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk, + &jz4740_clock_debugfs_ops_enabled); + + if (clk->parent) { + char parent_path[100]; + snprintf(parent_path, 100, "../%s", clk->parent->name); + clk->debugfs_parent_entry = debugfs_create_symlink("parent", + clk->debugfs_entry, + parent_path); + } +} + +/* TODO: Locking */ +void jz4740_clock_debugfs_update_parent(struct clk *clk) +{ + if (clk->debugfs_parent_entry) + debugfs_remove(clk->debugfs_parent_entry); + + if (clk->parent) { + char parent_path[100]; + snprintf(parent_path, 100, "../%s", clk->parent->name); + clk->debugfs_parent_entry = debugfs_create_symlink("parent", + clk->debugfs_entry, + parent_path); + } else { + clk->debugfs_parent_entry = NULL; + } +} + +void jz4740_clock_debugfs_init(void) +{ + jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL); + if (IS_ERR(jz4740_clock_debugfs)) + jz4740_clock_debugfs = NULL; +} diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c new file mode 100644 index 0000000..118a8a5 --- /dev/null +++ b/arch/mips/jz4740/clock.c @@ -0,0 +1,924 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen + * JZ4740 SoC clock support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "clock.h" + +#define JZ_REG_CLOCK_CTRL 0x00 +#define JZ_REG_CLOCK_LOW_POWER 0x04 +#define JZ_REG_CLOCK_PLL 0x10 +#define JZ_REG_CLOCK_GATE 0x20 +#define JZ_REG_CLOCK_SLEEP_CTRL 0x24 +#define JZ_REG_CLOCK_I2S 0x60 +#define JZ_REG_CLOCK_LCD 0x64 +#define JZ_REG_CLOCK_MMC 0x68 +#define JZ_REG_CLOCK_UHC 0x6C +#define JZ_REG_CLOCK_SPI 0x74 + +#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31) +#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30) +#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29) +#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000 +#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22) +#define JZ_CLOCK_CTRL_PLL_HALF BIT(21) +#define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000 +#define JZ_CLOCK_CTRL_UDIV_OFFSET 23 +#define JZ_CLOCK_CTRL_LDIV_OFFSET 16 +#define JZ_CLOCK_CTRL_MDIV_OFFSET 12 +#define JZ_CLOCK_CTRL_PDIV_OFFSET 8 +#define JZ_CLOCK_CTRL_HDIV_OFFSET 4 +#define JZ_CLOCK_CTRL_CDIV_OFFSET 0 + +#define JZ_CLOCK_GATE_UART0 BIT(0) +#define JZ_CLOCK_GATE_TCU BIT(1) +#define JZ_CLOCK_GATE_RTC BIT(2) +#define JZ_CLOCK_GATE_I2C BIT(3) +#define JZ_CLOCK_GATE_SPI BIT(4) +#define JZ_CLOCK_GATE_AIC BIT(5) +#define JZ_CLOCK_GATE_I2S BIT(6) +#define JZ_CLOCK_GATE_MMC BIT(7) +#define JZ_CLOCK_GATE_ADC BIT(8) +#define JZ_CLOCK_GATE_CIM BIT(9) +#define JZ_CLOCK_GATE_LCD BIT(10) +#define JZ_CLOCK_GATE_UDC BIT(11) +#define JZ_CLOCK_GATE_DMAC BIT(12) +#define JZ_CLOCK_GATE_IPU BIT(13) +#define JZ_CLOCK_GATE_UHC BIT(14) +#define JZ_CLOCK_GATE_UART1 BIT(15) + +#define JZ_CLOCK_I2S_DIV_MASK 0x01ff + +#define JZ_CLOCK_LCD_DIV_MASK 0x01ff + +#define JZ_CLOCK_MMC_DIV_MASK 0x001f + +#define JZ_CLOCK_UHC_DIV_MASK 0x000f + +#define JZ_CLOCK_SPI_SRC_PLL BIT(31) +#define JZ_CLOCK_SPI_DIV_MASK 0x000f + +#define JZ_CLOCK_PLL_M_MASK 0x01ff +#define JZ_CLOCK_PLL_N_MASK 0x001f +#define JZ_CLOCK_PLL_OD_MASK 0x0003 +#define JZ_CLOCK_PLL_STABLE BIT(10) +#define JZ_CLOCK_PLL_BYPASS BIT(9) +#define JZ_CLOCK_PLL_ENABLED BIT(8) +#define JZ_CLOCK_PLL_STABLIZE_MASK 0x000f +#define JZ_CLOCK_PLL_M_OFFSET 23 +#define JZ_CLOCK_PLL_N_OFFSET 18 +#define JZ_CLOCK_PLL_OD_OFFSET 16 + +#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2) +#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0) + +#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7) +#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6) + +static void __iomem *jz_clock_base; +static spinlock_t jz_clock_lock; +static LIST_HEAD(jz_clocks); + +struct main_clk { + struct clk clk; + uint32_t div_offset; +}; + +struct divided_clk { + struct clk clk; + uint32_t reg; + uint32_t mask; +}; + +struct static_clk { + struct clk clk; + unsigned long rate; +}; + +static uint32_t jz_clk_reg_read(int reg) +{ + return readl(jz_clock_base + reg); +} + +static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask) +{ + uint32_t val2; + + spin_lock(&jz_clock_lock); + val2 = readl(jz_clock_base + reg); + val2 &= ~mask; + val2 |= val; + writel(val2, jz_clock_base + reg); + spin_unlock(&jz_clock_lock); +} + +static void jz_clk_reg_set_bits(int reg, uint32_t mask) +{ + uint32_t val; + + spin_lock(&jz_clock_lock); + val = readl(jz_clock_base + reg); + val |= mask; + writel(val, jz_clock_base + reg); + spin_unlock(&jz_clock_lock); +} + +static void jz_clk_reg_clear_bits(int reg, uint32_t mask) +{ + uint32_t val; + + spin_lock(&jz_clock_lock); + val = readl(jz_clock_base + reg); + val &= ~mask; + writel(val, jz_clock_base + reg); + spin_unlock(&jz_clock_lock); +} + +static int jz_clk_enable_gating(struct clk *clk) +{ + if (clk->gate_bit == JZ4740_CLK_NOT_GATED) + return -EINVAL; + + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); + return 0; +} + +static int jz_clk_disable_gating(struct clk *clk) +{ + if (clk->gate_bit == JZ4740_CLK_NOT_GATED) + return -EINVAL; + + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); + return 0; +} + +static int jz_clk_is_enabled_gating(struct clk *clk) +{ + if (clk->gate_bit == JZ4740_CLK_NOT_GATED) + return 1; + + return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit); +} + +static unsigned long jz_clk_static_get_rate(struct clk *clk) +{ + return ((struct static_clk *)clk)->rate; +} + +static int jz_clk_ko_enable(struct clk *clk) +{ + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE); + return 0; +} + +static int jz_clk_ko_disable(struct clk *clk) +{ + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE); + return 0; +} + +static int jz_clk_ko_is_enabled(struct clk *clk) +{ + return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE); +} + +static const int pllno[] = {1, 2, 2, 4}; + +static unsigned long jz_clk_pll_get_rate(struct clk *clk) +{ + uint32_t val; + int m; + int n; + int od; + + val = jz_clk_reg_read(JZ_REG_CLOCK_PLL); + + if (val & JZ_CLOCK_PLL_BYPASS) + return clk_get_rate(clk->parent); + + m = ((val >> 23) & 0x1ff) + 2; + n = ((val >> 18) & 0x1f) + 2; + od = (val >> 16) & 0x3; + + return ((clk_get_rate(clk->parent) / n) * m) / pllno[od]; +} + +static unsigned long jz_clk_pll_half_get_rate(struct clk *clk) +{ + uint32_t reg; + + reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); + if (reg & JZ_CLOCK_CTRL_PLL_HALF) + return jz_clk_pll_get_rate(clk->parent); + return jz_clk_pll_get_rate(clk->parent) >> 1; +} + +static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + +static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); + int div; + + div = parent_rate / rate; + if (div > 32) + return parent_rate / 32; + else if (div < 1) + return parent_rate; + + div &= (0x3 << (ffs(div) - 1)); + + return parent_rate / div; +} + +static unsigned long jz_clk_main_get_rate(struct clk *clk) +{ + struct main_clk *mclk = (struct main_clk *)clk; + uint32_t div; + + div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); + + div >>= mclk->div_offset; + div &= 0xf; + + if (div >= ARRAY_SIZE(jz_clk_main_divs)) + div = ARRAY_SIZE(jz_clk_main_divs) - 1; + + return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div]; +} + +static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate) +{ + struct main_clk *mclk = (struct main_clk *)clk; + int i; + int div; + unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); + + rate = jz_clk_main_round_rate(clk, rate); + + div = parent_rate / rate; + + i = (ffs(div) - 1) << 1; + if (i > 0 && !(div & BIT(i-1))) + i -= 1; + + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset, + 0xf << mclk->div_offset); + + return 0; +} + +static struct clk_ops jz_clk_static_ops = { + .get_rate = jz_clk_static_get_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, +}; + +static struct static_clk jz_clk_ext = { + .clk = { + .name = "ext", + .gate_bit = JZ4740_CLK_NOT_GATED, + .ops = &jz_clk_static_ops, + }, +}; + +static struct clk_ops jz_clk_pll_ops = { + .get_rate = jz_clk_pll_get_rate, +}; + +static struct clk jz_clk_pll = { + .name = "pll", + .parent = &jz_clk_ext.clk, + .ops = &jz_clk_pll_ops, +}; + +static struct clk_ops jz_clk_pll_half_ops = { + .get_rate = jz_clk_pll_half_get_rate, +}; + +static struct clk jz_clk_pll_half = { + .name = "pll half", + .parent = &jz_clk_pll, + .ops = &jz_clk_pll_half_ops, +}; + +static const struct clk_ops jz_clk_main_ops = { + .get_rate = jz_clk_main_get_rate, + .set_rate = jz_clk_main_set_rate, + .round_rate = jz_clk_main_round_rate, +}; + +static struct main_clk jz_clk_cpu = { + .clk = { + .name = "cclk", + .parent = &jz_clk_pll, + .ops = &jz_clk_main_ops, + }, + .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET, +}; + +static struct main_clk jz_clk_memory = { + .clk = { + .name = "mclk", + .parent = &jz_clk_pll, + .ops = &jz_clk_main_ops, + }, + .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET, +}; + +static struct main_clk jz_clk_high_speed_peripheral = { + .clk = { + .name = "hclk", + .parent = &jz_clk_pll, + .ops = &jz_clk_main_ops, + }, + .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET, +}; + + +static struct main_clk jz_clk_low_speed_peripheral = { + .clk = { + .name = "pclk", + .parent = &jz_clk_pll, + .ops = &jz_clk_main_ops, + }, + .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET, +}; + +static const struct clk_ops jz_clk_ko_ops = { + .enable = jz_clk_ko_enable, + .disable = jz_clk_ko_disable, + .is_enabled = jz_clk_ko_is_enabled, +}; + +static struct clk jz_clk_ko = { + .name = "cko", + .parent = &jz_clk_memory.clk, + .ops = &jz_clk_ko_ops, +}; + +static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent) +{ + if (parent == &jz_clk_pll) + jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI); + else if (parent == &jz_clk_ext.clk) + jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI); + else + return -EINVAL; + + clk->parent = parent; + + return 0; +} + +static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent) +{ + if (parent == &jz_clk_pll_half) + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL); + else if (parent == &jz_clk_ext.clk) + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL); + else + return -EINVAL; + + clk->parent = parent; + + return 0; +} + +static int jz_clk_udc_enable(struct clk *clk) +{ + jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL, + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); + + return 0; +} + +static int jz_clk_udc_disable(struct clk *clk) +{ + jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL, + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); + + return 0; +} + +static int jz_clk_udc_is_enabled(struct clk *clk) +{ + return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) & + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); +} + +static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent) +{ + if (parent == &jz_clk_pll_half) + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL); + else if (parent == &jz_clk_ext.clk) + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL); + else + return -EINVAL; + + clk->parent = parent; + + return 0; +} + +static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate) +{ + int div; + + if (clk->parent == &jz_clk_ext.clk) + return -EINVAL; + + div = clk_get_rate(clk->parent) / rate - 1; + + if (div < 0) + div = 0; + else if (div > 63) + div = 63; + + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET, + JZ_CLOCK_CTRL_UDIV_MASK); + return 0; +} + +static unsigned long jz_clk_udc_get_rate(struct clk *clk) +{ + int div; + + if (clk->parent == &jz_clk_ext.clk) + return clk_get_rate(clk->parent); + + div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK); + div >>= JZ_CLOCK_CTRL_UDIV_OFFSET; + div += 1; + + return clk_get_rate(clk->parent) / div; +} + +static unsigned long jz_clk_divided_get_rate(struct clk *clk) +{ + struct divided_clk *dclk = (struct divided_clk *)clk; + int div; + + if (clk->parent == &jz_clk_ext.clk) + return clk_get_rate(clk->parent); + + div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate) +{ + struct divided_clk *dclk = (struct divided_clk *)clk; + int div; + + if (clk->parent == &jz_clk_ext.clk) + return -EINVAL; + + div = clk_get_rate(clk->parent) / rate - 1; + + if (div < 0) + div = 0; + else if (div > dclk->mask) + div = dclk->mask; + + jz_clk_reg_write_mask(dclk->reg, div, dclk->mask); + + return 0; +} + +static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate) +{ + int div; + unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent); + + if (rate > 150000000) + return 150000000; + + div = parent_rate / rate; + if (div < 1) + div = 1; + else if (div > 32) + div = 32; + + return parent_rate / div; +} + +static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate) +{ + int div; + + if (rate > 150000000) + return -EINVAL; + + div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1; + if (div < 0) + div = 0; + else if (div > 31) + div = 31; + + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET, + JZ_CLOCK_CTRL_LDIV_MASK); + + return 0; +} + +static unsigned long jz_clk_ldclk_get_rate(struct clk *clk) +{ + int div; + + div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK; + div >>= JZ_CLOCK_CTRL_LDIV_OFFSET; + + return jz_clk_pll_half_get_rate(clk->parent) / (div + 1); +} + +static const struct clk_ops jz_clk_ops_ld = { + .set_rate = jz_clk_ldclk_set_rate, + .get_rate = jz_clk_ldclk_get_rate, + .round_rate = jz_clk_ldclk_round_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, +}; + +static struct clk jz_clk_ld = { + .name = "lcd", + .gate_bit = JZ_CLOCK_GATE_LCD, + .parent = &jz_clk_pll_half, + .ops = &jz_clk_ops_ld, +}; + +static const struct clk_ops jz_clk_i2s_ops = { + .set_rate = jz_clk_divided_set_rate, + .get_rate = jz_clk_divided_get_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, + .set_parent = jz_clk_i2s_set_parent, +}; + +static const struct clk_ops jz_clk_spi_ops = { + .set_rate = jz_clk_divided_set_rate, + .get_rate = jz_clk_divided_get_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, + .set_parent = jz_clk_spi_set_parent, +}; + +static const struct clk_ops jz_clk_divided_ops = { + .set_rate = jz_clk_divided_set_rate, + .get_rate = jz_clk_divided_get_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, +}; + +static struct divided_clk jz4740_clock_divided_clks[] = { + [0] = { + .clk = { + .name = "i2s", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_I2S, + .ops = &jz_clk_i2s_ops, + }, + .reg = JZ_REG_CLOCK_I2S, + .mask = JZ_CLOCK_I2S_DIV_MASK, + }, + [1] = { + .clk = { + .name = "spi", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_SPI, + .ops = &jz_clk_spi_ops, + }, + .reg = JZ_REG_CLOCK_SPI, + .mask = JZ_CLOCK_SPI_DIV_MASK, + }, + [2] = { + .clk = { + .name = "lcd_pclk", + .parent = &jz_clk_pll_half, + .gate_bit = JZ4740_CLK_NOT_GATED, + .ops = &jz_clk_divided_ops, + }, + .reg = JZ_REG_CLOCK_LCD, + .mask = JZ_CLOCK_LCD_DIV_MASK, + }, + [3] = { + .clk = { + .name = "mmc", + .parent = &jz_clk_pll_half, + .gate_bit = JZ_CLOCK_GATE_MMC, + .ops = &jz_clk_divided_ops, + }, + .reg = JZ_REG_CLOCK_MMC, + .mask = JZ_CLOCK_MMC_DIV_MASK, + }, + [4] = { + .clk = { + .name = "uhc", + .parent = &jz_clk_pll_half, + .gate_bit = JZ_CLOCK_GATE_UHC, + .ops = &jz_clk_divided_ops, + }, + .reg = JZ_REG_CLOCK_UHC, + .mask = JZ_CLOCK_UHC_DIV_MASK, + }, +}; + +static const struct clk_ops jz_clk_udc_ops = { + .set_parent = jz_clk_udc_set_parent, + .set_rate = jz_clk_udc_set_rate, + .get_rate = jz_clk_udc_get_rate, + .enable = jz_clk_udc_enable, + .disable = jz_clk_udc_disable, + .is_enabled = jz_clk_udc_is_enabled, +}; + +static const struct clk_ops jz_clk_simple_ops = { + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, +}; + +static struct clk jz4740_clock_simple_clks[] = { + [0] = { + .name = "udc", + .parent = &jz_clk_ext.clk, + .ops = &jz_clk_udc_ops, + }, + [1] = { + .name = "uart0", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_UART0, + .ops = &jz_clk_simple_ops, + }, + [2] = { + .name = "uart1", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_UART1, + .ops = &jz_clk_simple_ops, + }, + [3] = { + .name = "dma", + .parent = &jz_clk_high_speed_peripheral.clk, + .gate_bit = JZ_CLOCK_GATE_UART0, + .ops = &jz_clk_simple_ops, + }, + [4] = { + .name = "ipu", + .parent = &jz_clk_high_speed_peripheral.clk, + .gate_bit = JZ_CLOCK_GATE_IPU, + .ops = &jz_clk_simple_ops, + }, + [5] = { + .name = "adc", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_ADC, + .ops = &jz_clk_simple_ops, + }, + [6] = { + .name = "i2c", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_I2C, + .ops = &jz_clk_simple_ops, + }, + [7] = { + .name = "aic", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_AIC, + .ops = &jz_clk_simple_ops, + }, +}; + +static struct static_clk jz_clk_rtc = { + .clk = { + .name = "rtc", + .gate_bit = JZ_CLOCK_GATE_RTC, + .ops = &jz_clk_static_ops, + }, + .rate = 32768, +}; + +int clk_enable(struct clk *clk) +{ + if (!clk->ops->enable) + return -EINVAL; + + return clk->ops->enable(clk); +} +EXPORT_SYMBOL_GPL(clk_enable); + +void clk_disable(struct clk *clk) +{ + if (clk->ops->disable) + clk->ops->disable(clk); +} +EXPORT_SYMBOL_GPL(clk_disable); + +int clk_is_enabled(struct clk *clk) +{ + if (clk->ops->is_enabled) + return clk->ops->is_enabled(clk); + + return 1; +} + +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk->ops->get_rate) + return clk->ops->get_rate(clk); + if (clk->parent) + return clk_get_rate(clk->parent); + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(clk_get_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (!clk->ops->set_rate) + return -EINVAL; + return clk->ops->set_rate(clk, rate); +} +EXPORT_SYMBOL_GPL(clk_set_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk->ops->round_rate) + return clk->ops->round_rate(clk, rate); + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(clk_round_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret; + int enabled; + + if (!clk->ops->set_parent) + return -EINVAL; + + enabled = clk_is_enabled(clk); + if (enabled) + clk_disable(clk); + ret = clk->ops->set_parent(clk, parent); + if (enabled) + clk_enable(clk); + + jz4740_clock_debugfs_update_parent(clk); + + return ret; +} +EXPORT_SYMBOL_GPL(clk_set_parent); + +struct clk *clk_get(struct device *dev, const char *name) +{ + struct clk *clk; + + list_for_each_entry(clk, &jz_clocks, list) { + if (strcmp(clk->name, name) == 0) + return clk; + } + return ERR_PTR(-ENXIO); +} +EXPORT_SYMBOL_GPL(clk_get); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL_GPL(clk_put); + +static inline void clk_add(struct clk *clk) +{ + list_add_tail(&clk->list, &jz_clocks); + + jz4740_clock_debugfs_add_clk(clk); +} + +static void clk_register_clks(void) +{ + size_t i; + + clk_add(&jz_clk_ext.clk); + clk_add(&jz_clk_pll); + clk_add(&jz_clk_pll_half); + clk_add(&jz_clk_cpu.clk); + clk_add(&jz_clk_high_speed_peripheral.clk); + clk_add(&jz_clk_low_speed_peripheral.clk); + clk_add(&jz_clk_ko); + clk_add(&jz_clk_ld); + clk_add(&jz_clk_rtc.clk); + + for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i) + clk_add(&jz4740_clock_divided_clks[i].clk); + + for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i) + clk_add(&jz4740_clock_simple_clks[i]); +} + +void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode) +{ + switch (mode) { + case JZ4740_WAIT_MODE_IDLE: + jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP); + break; + case JZ4740_WAIT_MODE_SLEEP: + jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP); + break; + } +} + +void jz4740_clock_udc_disable_auto_suspend(void) +{ + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend); + +void jz4740_clock_udc_enable_auto_suspend(void) +{ + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend); + +void jz4740_clock_suspend(void) +{ + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, + JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0); + + jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED); +} + +void jz4740_clock_resume(void) +{ + uint32_t pll; + + jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED); + + do { + pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL); + } while (!(pll & JZ_CLOCK_PLL_STABLE)); + + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, + JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0); +} + +static int jz4740_clock_init(void) +{ + uint32_t val; + + jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100); + if (!jz_clock_base) + return -EBUSY; + + spin_lock_init(&jz_clock_lock); + + jz_clk_ext.rate = jz4740_clock_bdata.ext_rate; + jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate; + + val = jz_clk_reg_read(JZ_REG_CLOCK_SPI); + + if (val & JZ_CLOCK_SPI_SRC_PLL) + jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half; + + val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); + + if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL) + jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half; + + if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL) + jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half; + + jz4740_clock_debugfs_init(); + + clk_register_clks(); + + return 0; +} +arch_initcall(jz4740_clock_init); diff --git a/arch/mips/jz4740/clock.h b/arch/mips/jz4740/clock.h new file mode 100644 index 0000000..5d07499 --- /dev/null +++ b/arch/mips/jz4740/clock.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen + * JZ4740 SoC clock support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __MIPS_JZ4740_CLOCK_H__ +#define __MIPS_JZ4740_CLOCK_H__ + +#include + +struct jz4740_clock_board_data { + unsigned long ext_rate; + unsigned long rtc_rate; +}; + +extern struct jz4740_clock_board_data jz4740_clock_bdata; + +void jz4740_clock_suspend(void); +void jz4740_clock_resume(void); + +struct clk; + +struct clk_ops { + unsigned long (*get_rate)(struct clk *clk); + unsigned long (*round_rate)(struct clk *clk, unsigned long rate); + int (*set_rate)(struct clk *clk, unsigned long rate); + int (*enable)(struct clk *clk); + int (*disable)(struct clk *clk); + int (*is_enabled)(struct clk *clk); + + int (*set_parent)(struct clk *clk, struct clk *parent); + +}; + +struct clk { + const char *name; + struct clk *parent; + + uint32_t gate_bit; + + const struct clk_ops *ops; + + struct list_head list; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_entry; + struct dentry *debugfs_parent_entry; +#endif + +}; + +#define JZ4740_CLK_NOT_GATED ((uint32_t)-1) + +int clk_is_enabled(struct clk *clk); + +#ifdef CONFIG_DEBUG_FS +void jz4740_clock_debugfs_init(void); +void jz4740_clock_debugfs_add_clk(struct clk *clk); +void jz4740_clock_debugfs_update_parent(struct clk *clk); +#else +static inline void jz4740_clock_debugfs_init(void) {}; +static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {}; +static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {}; +#endif + +#endif -- 1.5.6.5 From lars@metafoo.de Sat Jul 17 14:11:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:11:42 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1047 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491957Ab0GQMLh (ORCPT ); Sat, 17 Jul 2010 14:11:37 +0200 Received: (qmail 11031 invoked by uid 0); 17 Jul 2010 12:11:36 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 10827 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.81 with SMTP; 17 Jul 2010 12:11:35 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH v3] MIPS: JZ4740: Add gpio support Date: Sat, 17 Jul 2010 14:11:19 +0200 Message-Id: <1279368679-20740-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1276924111-11158-9-git-send-email-lars@metafoo.de> References: <1276924111-11158-9-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds gpiolib support for JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen --- Changes since v1 - Fix possible irq setup race Changes since v2 - Use __fls instead of ffs in the interupt demuxer - Fix LCD pins wrongly labeld as MEM pins --- arch/mips/include/asm/mach-jz4740/gpio.h | 398 ++++++++++++++++++++ arch/mips/jz4740/gpio.c | 604 ++++++++++++++++++++++++++++++ 2 files changed, 1002 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/gpio.h create mode 100644 arch/mips/jz4740/gpio.c diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h new file mode 100644 index 0000000..7b74703 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/gpio.h @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2009, Lars-Peter Clausen + * JZ4740 GPIO pin definitions + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef _JZ_GPIO_H +#define _JZ_GPIO_H + +#include + +enum jz_gpio_function { + JZ_GPIO_FUNC_NONE, + JZ_GPIO_FUNC1, + JZ_GPIO_FUNC2, + JZ_GPIO_FUNC3, +}; + + +/* + Usually a driver for a SoC component has to request several gpio pins and + configure them as funcion pins. + jz_gpio_bulk_request can be used to ease this process. + Usually one would do something like: + + const static struct jz_gpio_bulk_request i2c_pins[] = { + JZ_GPIO_BULK_PIN(I2C_SDA), + JZ_GPIO_BULK_PIN(I2C_SCK), + }; + + inside the probe function: + + ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins)); + if (ret) { + ... + + inside the remove function: + + jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins)); + + +*/ +struct jz_gpio_bulk_request { + int gpio; + const char *name; + enum jz_gpio_function function; +}; + +#define JZ_GPIO_BULK_PIN(pin) { \ + .gpio = JZ_GPIO_ ## pin, \ + .name = #pin, \ + .function = JZ_GPIO_FUNC_ ## pin \ +} + +int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num); +void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num); +void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num); +void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num); +void jz_gpio_enable_pullup(unsigned gpio); +void jz_gpio_disable_pullup(unsigned gpio); +int jz_gpio_set_function(int gpio, enum jz_gpio_function function); + +int jz_gpio_port_direction_input(int port, uint32_t mask); +int jz_gpio_port_direction_output(int port, uint32_t mask); +void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask); +uint32_t jz_gpio_port_get_value(int port, uint32_t mask); + +#include + +#define JZ_GPIO_PORTA(x) ((x) + 32 * 0) +#define JZ_GPIO_PORTB(x) ((x) + 32 * 1) +#define JZ_GPIO_PORTC(x) ((x) + 32 * 2) +#define JZ_GPIO_PORTD(x) ((x) + 32 * 3) + +/* Port A function pins */ +#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0) +#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1) +#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2) +#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3) +#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4) +#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5) +#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6) +#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7) +#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8) +#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9) +#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10) +#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11) +#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12) +#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13) +#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14) +#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15) +#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16) +#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17) +#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18) +#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19) +#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20) +#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21) +#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22) +#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23) +#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24) +#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25) +#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26) +#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27) +#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28) +#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29) +#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30) +#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31) + +#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1 + +/* Port B function pins */ +#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0) +#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1) +#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2) +#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3) +#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4) +#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5) +#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6) +#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7) +#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8) +#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9) +#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10) +#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11) +#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12) +#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13) +#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14) +#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15) +#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16) +#define JZ_GPIO_LCD_CLS JZ_GPIO_PORTB(17) +#define JZ_GPIO_LCD_SPL JZ_GPIO_PORTB(18) +#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19) +#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20) +#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21) +#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22) +#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23) +#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24) +#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25) +#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26) +#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27) +#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28) +#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29) +#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30) +#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31) + +#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1 + + +#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17) +#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18) + +#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2 + +/* Port C function pins */ +#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0) +#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1) +#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2) +#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3) +#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4) +#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5) +#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6) +#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7) +#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8) +#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9) +#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10) +#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11) +#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12) +#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13) +#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14) +#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15) +#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16) +#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17) +#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18) +#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19) +#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20) +#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21) +#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22) +#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23) +#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24) +#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25) +#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26) +#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27) +#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28) +#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29) + +#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1 + + +#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22) +#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23) + +#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2 + +/* Port D function pins */ +#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0) +#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1) +#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2) +#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3) +#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4) +#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5) +#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6) +#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7) +#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8) +#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9) +#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10) +#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11) +#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12) +#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13) +#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14) +#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15) +#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16) +#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17) +#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18) +#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19) +#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20) +#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21) +#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22) +#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23) +#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24) +#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25) +#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26) +#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27) +#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28) +#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30) +#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31) + +#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA +#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA +#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA +#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA +#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA +#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA +#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA +#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA +#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA +#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA +#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA +#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA +#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1 + +#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM +#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM +#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM +#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM +#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM +#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM +#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM +#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM + +#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18) +#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19) +#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20) +#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21) +#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22) +#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23) +#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24) +#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25) +#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26) +#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27) +#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28) +#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30) +#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31) + +#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2 +#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2 + +#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30) +#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31) + +#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3 +#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3 + +#endif diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c new file mode 100644 index 0000000..38f60f3 --- /dev/null +++ b/arch/mips/jz4740/gpio.c @@ -0,0 +1,604 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 platform GPIO support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define JZ4740_GPIO_BASE_A (32*0) +#define JZ4740_GPIO_BASE_B (32*1) +#define JZ4740_GPIO_BASE_C (32*2) +#define JZ4740_GPIO_BASE_D (32*3) + +#define JZ4740_GPIO_NUM_A 32 +#define JZ4740_GPIO_NUM_B 32 +#define JZ4740_GPIO_NUM_C 31 +#define JZ4740_GPIO_NUM_D 32 + +#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A) +#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B) +#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C) +#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D) + +#define JZ_REG_GPIO_PIN 0x00 +#define JZ_REG_GPIO_DATA 0x10 +#define JZ_REG_GPIO_DATA_SET 0x14 +#define JZ_REG_GPIO_DATA_CLEAR 0x18 +#define JZ_REG_GPIO_MASK 0x20 +#define JZ_REG_GPIO_MASK_SET 0x24 +#define JZ_REG_GPIO_MASK_CLEAR 0x28 +#define JZ_REG_GPIO_PULL 0x30 +#define JZ_REG_GPIO_PULL_SET 0x34 +#define JZ_REG_GPIO_PULL_CLEAR 0x38 +#define JZ_REG_GPIO_FUNC 0x40 +#define JZ_REG_GPIO_FUNC_SET 0x44 +#define JZ_REG_GPIO_FUNC_CLEAR 0x48 +#define JZ_REG_GPIO_SELECT 0x50 +#define JZ_REG_GPIO_SELECT_SET 0x54 +#define JZ_REG_GPIO_SELECT_CLEAR 0x58 +#define JZ_REG_GPIO_DIRECTION 0x60 +#define JZ_REG_GPIO_DIRECTION_SET 0x64 +#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68 +#define JZ_REG_GPIO_TRIGGER 0x70 +#define JZ_REG_GPIO_TRIGGER_SET 0x74 +#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78 +#define JZ_REG_GPIO_FLAG 0x80 +#define JZ_REG_GPIO_FLAG_CLEAR 0x14 + +#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f) +#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg)) +#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg)) + +struct jz_gpio_chip { + unsigned int irq; + unsigned int irq_base; + uint32_t wakeup; + uint32_t suspend_mask; + uint32_t edge_trigger_both; + + void __iomem *base; + + spinlock_t lock; + + struct gpio_chip gpio_chip; + struct irq_chip irq_chip; + struct sys_device sysdev; +}; + +static struct jz_gpio_chip jz4740_gpio_chips[]; + +static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio) +{ + return &jz4740_gpio_chips[gpio >> 5]; +} + +static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip) +{ + return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip); +} + +static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq) +{ + return get_irq_chip_data(irq); +} + +static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) +{ + writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg)); +} + +int jz_gpio_set_function(int gpio, enum jz_gpio_function function) +{ + if (function == JZ_GPIO_FUNC_NONE) { + jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR); + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); + } else { + jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET); + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); + switch (function) { + case JZ_GPIO_FUNC1: + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); + break; + case JZ_GPIO_FUNC3: + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET); + case JZ_GPIO_FUNC2: /* Falltrough */ + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET); + break; + default: + BUG(); + break; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(jz_gpio_set_function); + +int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num) +{ + size_t i; + int ret; + + for (i = 0; i < num; ++i, ++request) { + ret = gpio_request(request->gpio, request->name); + if (ret) + goto err; + jz_gpio_set_function(request->gpio, request->function); + } + + return 0; + +err: + for (--request; i > 0; --i, --request) { + gpio_free(request->gpio); + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); + } + + return ret; +} +EXPORT_SYMBOL_GPL(jz_gpio_bulk_request); + +void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num) +{ + size_t i; + + for (i = 0; i < num; ++i, ++request) { + gpio_free(request->gpio); + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); + } + +} +EXPORT_SYMBOL_GPL(jz_gpio_bulk_free); + +void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num) +{ + size_t i; + + for (i = 0; i < num; ++i, ++request) { + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); + jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET); + } +} +EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend); + +void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num) +{ + size_t i; + + for (i = 0; i < num; ++i, ++request) + jz_gpio_set_function(request->gpio, request->function); +} +EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume); + +void jz_gpio_enable_pullup(unsigned gpio) +{ + jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR); +} +EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup); + +void jz_gpio_disable_pullup(unsigned gpio) +{ + jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET); +} +EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup); + +static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio) +{ + return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio)); +} + +static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) +{ + uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET); + reg += !value; + writel(BIT(gpio), reg); +} + +static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, + int value) +{ + writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET)); + jz_gpio_set_value(chip, gpio, value); + + return 0; +} + +static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR)); + + return 0; +} + +int jz_gpio_port_direction_input(int port, uint32_t mask) +{ + writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR)); + + return 0; +} +EXPORT_SYMBOL(jz_gpio_port_direction_input); + +int jz_gpio_port_direction_output(int port, uint32_t mask) +{ + writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET)); + + return 0; +} +EXPORT_SYMBOL(jz_gpio_port_direction_output); + +void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask) +{ + writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR)); + writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET)); +} +EXPORT_SYMBOL(jz_gpio_port_set_value); + +uint32_t jz_gpio_port_get_value(int port, uint32_t mask) +{ + uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN)); + + return value & mask; +} +EXPORT_SYMBOL(jz_gpio_port_get_value); + +int gpio_to_irq(unsigned gpio) +{ + return JZ4740_IRQ_GPIO(0) + gpio; +} +EXPORT_SYMBOL_GPL(gpio_to_irq); + +int irq_to_gpio(unsigned irq) +{ + return irq - JZ4740_IRQ_GPIO(0); +} +EXPORT_SYMBOL_GPL(irq_to_gpio); + +#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f) + +static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq) +{ + uint32_t value; + void __iomem *reg; + uint32_t mask = IRQ_TO_BIT(irq); + + if (!(chip->edge_trigger_both & mask)) + return; + + reg = chip->base; + + value = readl(chip->base + JZ_REG_GPIO_PIN); + if (value & mask) + reg += JZ_REG_GPIO_DIRECTION_CLEAR; + else + reg += JZ_REG_GPIO_DIRECTION_SET; + + writel(mask, reg); +} + +static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc) +{ + uint32_t flag; + unsigned int gpio_irq; + unsigned int gpio_bank; + struct jz_gpio_chip *chip = get_irq_desc_data(desc); + + gpio_bank = JZ4740_IRQ_GPIO0 - irq; + + flag = readl(chip->base + JZ_REG_GPIO_FLAG); + + if (!flag) + return; + + gpio_irq = __fls(flag); + + jz_gpio_check_trigger_both(chip, irq); + + gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0); + + generic_handle_irq(gpio_irq); +}; + +static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg) +{ + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); + writel(IRQ_TO_BIT(irq), chip->base + reg); +} + +static void jz_gpio_irq_mask(unsigned int irq) +{ + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET); +}; + +static void jz_gpio_irq_unmask(unsigned int irq) +{ + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); + + jz_gpio_check_trigger_both(chip, irq); + + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR); +}; + +/* TODO: Check if function is gpio */ +static unsigned int jz_gpio_irq_startup(unsigned int irq) +{ + struct irq_desc *desc = irq_to_desc(irq); + + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET); + + desc->status &= ~IRQ_MASKED; + jz_gpio_irq_unmask(irq); + + return 0; +} + +static void jz_gpio_irq_shutdown(unsigned int irq) +{ + struct irq_desc *desc = irq_to_desc(irq); + + jz_gpio_irq_mask(irq); + desc->status |= IRQ_MASKED; + + /* Set direction to input */ + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR); +} + +static void jz_gpio_irq_ack(unsigned int irq) +{ + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR); +}; + +static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); + struct irq_desc *desc = irq_to_desc(irq); + + jz_gpio_irq_mask(irq); + + if (flow_type == IRQ_TYPE_EDGE_BOTH) { + uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); + if (value & IRQ_TO_BIT(irq)) + flow_type = IRQ_TYPE_EDGE_FALLING; + else + flow_type = IRQ_TYPE_EDGE_RISING; + chip->edge_trigger_both |= IRQ_TO_BIT(irq); + } else { + chip->edge_trigger_both &= ~IRQ_TO_BIT(irq); + } + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); + break; + case IRQ_TYPE_EDGE_FALLING: + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); + break; + case IRQ_TYPE_LEVEL_HIGH: + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); + break; + case IRQ_TYPE_LEVEL_LOW: + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); + break; + default: + return -EINVAL; + } + + if (!(desc->status & IRQ_MASKED)) + jz_gpio_irq_unmask(irq); + + return 0; +} + +static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on) +{ + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); + spin_lock(&chip->lock); + if (on) + chip->wakeup |= IRQ_TO_BIT(irq); + else + chip->wakeup &= ~IRQ_TO_BIT(irq); + spin_unlock(&chip->lock); + + set_irq_wake(chip->irq, on); + return 0; +} + +/* + * This lock class tells lockdep that GPIO irqs are in a different + * category than their parents, so it won't report false recursion. + */ +static struct lock_class_key gpio_lock_class; + +#define JZ4740_GPIO_CHIP(_bank) { \ + .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \ + .gpio_chip = { \ + .label = "Bank " # _bank, \ + .owner = THIS_MODULE, \ + .set = jz_gpio_set_value, \ + .get = jz_gpio_get_value, \ + .direction_output = jz_gpio_direction_output, \ + .direction_input = jz_gpio_direction_input, \ + .base = JZ4740_GPIO_BASE_ ## _bank, \ + .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ + }, \ + .irq_chip = { \ + .name = "GPIO Bank " # _bank, \ + .mask = jz_gpio_irq_mask, \ + .unmask = jz_gpio_irq_unmask, \ + .ack = jz_gpio_irq_ack, \ + .startup = jz_gpio_irq_startup, \ + .shutdown = jz_gpio_irq_shutdown, \ + .set_type = jz_gpio_irq_set_type, \ + .set_wake = jz_gpio_irq_set_wake, \ + }, \ +} + +static struct jz_gpio_chip jz4740_gpio_chips[] = { + JZ4740_GPIO_CHIP(A), + JZ4740_GPIO_CHIP(B), + JZ4740_GPIO_CHIP(C), + JZ4740_GPIO_CHIP(D), +}; + +static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev) +{ + return container_of(dev, struct jz_gpio_chip, sysdev); +} + +static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state) +{ + struct jz_gpio_chip *chip = sysdev_to_chip(dev); + + chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK); + writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET); + writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR); + + return 0; +} + +static int jz4740_gpio_resume(struct sys_device *dev) +{ + struct jz_gpio_chip *chip = sysdev_to_chip(dev); + uint32_t mask = chip->suspend_mask; + + writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR); + writel(mask, chip->base + JZ_REG_GPIO_MASK_SET); + + return 0; +} + +static struct sysdev_class jz4740_gpio_sysdev_class = { + .name = "gpio", + .suspend = jz4740_gpio_suspend, + .resume = jz4740_gpio_resume, +}; + +static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) +{ + int ret, irq; + + chip->sysdev.id = id; + chip->sysdev.cls = &jz4740_gpio_sysdev_class; + ret = sysdev_register(&chip->sysdev); + + if (ret) + return ret; + + spin_lock_init(&chip->lock); + + chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100); + + gpiochip_add(&chip->gpio_chip); + + chip->irq = JZ4740_IRQ_INTC_GPIO(id); + set_irq_data(chip->irq, chip); + set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); + + for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { + lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class); + set_irq_chip_data(irq, chip); + set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq); + } + + return 0; +} + +static int __init jz4740_gpio_init(void) +{ + unsigned int i; + int ret; + + ret = sysdev_class_register(&jz4740_gpio_sysdev_class); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i) + jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i); + + printk(KERN_INFO "JZ4740 GPIO initalized\n"); + + return 0; +} +arch_initcall(jz4740_gpio_init); + +#ifdef CONFIG_DEBUG_FS + +static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip, + const char *name, unsigned int reg) +{ + seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg)); +} + +static int gpio_regs_show(struct seq_file *s, void *unused) +{ + struct jz_gpio_chip *chip = jz4740_gpio_chips; + int i; + + for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) { + seq_printf(s, "==GPIO %d==\n", i); + gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN); + gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA); + gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK); + gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL); + gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC); + gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT); + gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION); + gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER); + gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG); + } + + return 0; +} + +static int gpio_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, gpio_regs_show, NULL); +} + +static const struct file_operations gpio_regs_operations = { + .open = gpio_regs_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init gpio_debugfs_init(void) +{ + (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO, + NULL, NULL, &gpio_regs_operations); + return 0; +} +subsys_initcall(gpio_debugfs_init); + +#endif -- 1.5.6.5 From lars@metafoo.de Sat Jul 17 14:12:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:12:43 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1038 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491923Ab0GQMMj (ORCPT ); Sat, 17 Jul 2010 14:12:39 +0200 Received: (qmail 30852 invoked by uid 0); 17 Jul 2010 12:12:36 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 30814 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.77 with SMTP; 17 Jul 2010 12:12:36 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH v4] MIPS: JZ4740: Add PWM support Date: Sat, 17 Jul 2010 14:12:20 +0200 Message-Id: <1279368740-20850-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1277688225-25728-1-git-send-email-lars@metafoo.de> References: <1277688225-25728-1-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for the PWM part of the timer unit on a JZ4740 SoC. Signed-off-by: Lars-Peter Clausen --- Changes since v2 - Fix handling if the pwm clock is not available Changes since v3 - Move pwm subsys_initcall to subsys_initcall --- arch/mips/jz4740/pwm.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 177 insertions(+), 0 deletions(-) create mode 100644 arch/mips/jz4740/pwm.c diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c new file mode 100644 index 0000000..a26a6fa --- /dev/null +++ b/arch/mips/jz4740/pwm.c @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen + * JZ4740 platform PWM support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include + +#include +#include +#include +#include + +#include +#include "timer.h" + +static struct clk *jz4740_pwm_clk; + +DEFINE_MUTEX(jz4740_pwm_mutex); + +struct pwm_device { + unsigned int id; + unsigned int gpio; + bool used; +}; + +static struct pwm_device jz4740_pwm_list[] = { + { 2, JZ_GPIO_PWM2, false }, + { 3, JZ_GPIO_PWM3, false }, + { 4, JZ_GPIO_PWM4, false }, + { 5, JZ_GPIO_PWM5, false }, + { 6, JZ_GPIO_PWM6, false }, + { 7, JZ_GPIO_PWM7, false }, +}; + +struct pwm_device *pwm_request(int id, const char *label) +{ + int ret = 0; + struct pwm_device *pwm; + + if (id < 2 || id > 7 || !jz4740_pwm_clk) + return ERR_PTR(-ENODEV); + + mutex_lock(&jz4740_pwm_mutex); + + pwm = &jz4740_pwm_list[id - 2]; + if (pwm->used) + ret = -EBUSY; + else + pwm->used = true; + + mutex_unlock(&jz4740_pwm_mutex); + + if (ret) + return ERR_PTR(ret); + + ret = gpio_request(pwm->gpio, label); + + if (ret) { + printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret); + pwm->used = false; + return ERR_PTR(ret); + } + + jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM); + + jz4740_timer_start(id); + + return pwm; +} + +void pwm_free(struct pwm_device *pwm) +{ + pwm_disable(pwm); + jz4740_timer_set_ctrl(pwm->id, 0); + + jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE); + gpio_free(pwm->gpio); + + jz4740_timer_stop(pwm->id); + + pwm->used = false; +} + +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + unsigned long long tmp; + unsigned long period, duty; + unsigned int prescaler = 0; + unsigned int id = pwm->id; + uint16_t ctrl; + bool is_enabled; + + if (duty_ns < 0 || duty_ns > period_ns) + return -EINVAL; + + tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns; + do_div(tmp, 1000000000); + period = tmp; + + while (period > 0xffff && prescaler < 6) { + period >>= 2; + ++prescaler; + } + + if (prescaler == 6) + return -EINVAL; + + tmp = (unsigned long long)period * duty_ns; + do_div(tmp, period_ns); + duty = period - tmp; + + if (duty >= period) + duty = period - 1; + + is_enabled = jz4740_timer_is_enabled(id); + if (is_enabled) + pwm_disable(pwm); + + jz4740_timer_set_count(id, 0); + jz4740_timer_set_duty(id, duty); + jz4740_timer_set_period(id, period); + + ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | + JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; + + jz4740_timer_set_ctrl(id, ctrl); + + if (is_enabled) + pwm_enable(pwm); + + return 0; +} + +int pwm_enable(struct pwm_device *pwm) +{ + uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); + + ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; + jz4740_timer_set_ctrl(pwm->id, ctrl); + jz4740_timer_enable(pwm->id); + + return 0; +} + +void pwm_disable(struct pwm_device *pwm) +{ + uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); + + ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; + jz4740_timer_disable(pwm->id); + jz4740_timer_set_ctrl(pwm->id, ctrl); +} + +static int __init jz4740_pwm_init(void) +{ + int ret = 0; + + jz4740_pwm_clk = clk_get(NULL, "ext"); + + if (IS_ERR(jz4740_pwm_clk)) { + ret = PTR_ERR(jz4740_pwm_clk); + jz4740_pwm_clk = NULL; + } + + return ret; +} +subsys_initcall(jz4740_pwm_init); -- 1.5.6.5 From lars@metafoo.de Sat Jul 17 14:13:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:13:49 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1074 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491154Ab0GQMNq (ORCPT ); Sat, 17 Jul 2010 14:13:46 +0200 Received: (qmail 31948 invoked by uid 0); 17 Jul 2010 12:13:45 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 31910 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.77 with SMTP; 17 Jul 2010 12:13:45 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH v3] MIPS: JZ4740: Add platform devices Date: Sat, 17 Jul 2010 14:13:29 +0200 Message-Id: <1279368809-21006-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1276924111-11158-14-git-send-email-lars@metafoo.de> References: <1276924111-11158-14-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27406 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds platform devices for all the JZ4740 platform drivers. Signed-off-by: Lars-Peter Clausen --- Changes since v1 - Add JZ4740 PCM device - Add ADC MFD device and remove battery device Changes since v2 - Add memory region for NAND bank --- arch/mips/include/asm/mach-jz4740/platform.h | 36 ++++ arch/mips/jz4740/platform.c | 291 ++++++++++++++++++++++++++ 2 files changed, 327 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/platform.h create mode 100644 arch/mips/jz4740/platform.c diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h new file mode 100644 index 0000000..8987a76 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/platform.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 platform device definitions + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + + +#ifndef __JZ4740_PLATFORM_H +#define __JZ4740_PLATFORM_H + +#include + +extern struct platform_device jz4740_usb_ohci_device; +extern struct platform_device jz4740_udc_device; +extern struct platform_device jz4740_mmc_device; +extern struct platform_device jz4740_rtc_device; +extern struct platform_device jz4740_i2c_device; +extern struct platform_device jz4740_nand_device; +extern struct platform_device jz4740_framebuffer_device; +extern struct platform_device jz4740_i2s_device; +extern struct platform_device jz4740_pcm_device; +extern struct platform_device jz4740_codec_device; +extern struct platform_device jz4740_adc_device; + +void jz4740_serial_device_register(void); + +#endif diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c new file mode 100644 index 0000000..95bc2b5 --- /dev/null +++ b/arch/mips/jz4740/platform.c @@ -0,0 +1,291 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 platform devices + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include "serial.h" +#include "clock.h" + +/* OHCI controller */ +static struct resource jz4740_usb_ohci_resources[] = { + { + .start = JZ4740_UHC_BASE_ADDR, + .end = JZ4740_UHC_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_UHC, + .end = JZ4740_IRQ_UHC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_usb_ohci_device = { + .name = "jz4740-ohci", + .id = -1, + .dev = { + .dma_mask = &jz4740_usb_ohci_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources), + .resource = jz4740_usb_ohci_resources, +}; + +/* UDC (USB gadget controller) */ +static struct resource jz4740_usb_gdt_resources[] = { + { + .start = JZ4740_UDC_BASE_ADDR, + .end = JZ4740_UDC_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_UDC, + .end = JZ4740_IRQ_UDC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_udc_device = { + .name = "jz-udc", + .id = -1, + .dev = { + .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources), + .resource = jz4740_usb_gdt_resources, +}; + +/* MMC/SD controller */ +static struct resource jz4740_mmc_resources[] = { + { + .start = JZ4740_MSC_BASE_ADDR, + .end = JZ4740_MSC_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_MSC, + .end = JZ4740_IRQ_MSC, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device jz4740_mmc_device = { + .name = "jz4740-mmc", + .id = 0, + .dev = { + .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(jz4740_mmc_resources), + .resource = jz4740_mmc_resources, +}; + +/* RTC controller */ +static struct resource jz4740_rtc_resources[] = { + { + .start = JZ4740_RTC_BASE_ADDR, + .end = JZ4740_RTC_BASE_ADDR + 0x38 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_RTC, + .end = JZ4740_IRQ_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_rtc_device = { + .name = "jz4740-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_rtc_resources), + .resource = jz4740_rtc_resources, +}; + +/* I2C controller */ +static struct resource jz4740_i2c_resources[] = { + { + .start = JZ4740_I2C_BASE_ADDR, + .end = JZ4740_I2C_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_I2C, + .end = JZ4740_IRQ_I2C, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device jz4740_i2c_device = { + .name = "jz4740-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(jz4740_i2c_resources), + .resource = jz4740_i2c_resources, +}; + +/* NAND controller */ +static struct resource jz4740_nand_resources[] = { + { + .name = "mmio", + .start = JZ4740_EMC_BASE_ADDR, + .end = JZ4740_EMC_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank", + .start = 0x18000000, + .end = 0x180C0000 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_nand_device = { + .name = "jz4740-nand", + .num_resources = ARRAY_SIZE(jz4740_nand_resources), + .resource = jz4740_nand_resources, +}; + +/* LCD controller */ +static struct resource jz4740_framebuffer_resources[] = { + { + .start = JZ4740_LCD_BASE_ADDR, + .end = JZ4740_LCD_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_framebuffer_device = { + .name = "jz4740-fb", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources), + .resource = jz4740_framebuffer_resources, + .dev = { + .dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +/* I2S controller */ +static struct resource jz4740_i2s_resources[] = { + { + .start = JZ4740_AIC_BASE_ADDR, + .end = JZ4740_AIC_BASE_ADDR + 0x38 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_i2s_device = { + .name = "jz4740-i2s", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_i2s_resources), + .resource = jz4740_i2s_resources, +}; + +/* PCM */ +struct platform_device jz4740_pcm_device = { + .name = "jz4740-pcm", + .id = -1, +}; + +/* Codec */ +static struct resource jz4740_codec_resources[] = { + { + .start = JZ4740_AIC_BASE_ADDR + 0x80, + .end = JZ4740_AIC_BASE_ADDR + 0x88 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_codec_device = { + .name = "jz4740-codec", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_codec_resources), + .resource = jz4740_codec_resources, +}; + +/* ADC controller */ +static struct resource jz4740_adc_resources[] = { + { + .start = JZ4740_SADC_BASE_ADDR, + .end = JZ4740_SADC_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_SADC, + .end = JZ4740_IRQ_SADC, + .flags = IORESOURCE_IRQ, + }, + { + .start = JZ4740_IRQ_ADC_BASE, + .end = JZ4740_IRQ_ADC_BASE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_adc_device = { + .name = "jz4740-adc", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_adc_resources), + .resource = jz4740_adc_resources, +}; + +/* Serial */ +#define JZ4740_UART_DATA(_id) \ + { \ + .flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \ + .iotype = UPIO_MEM, \ + .regshift = 2, \ + .serial_out = jz4740_serial_out, \ + .type = PORT_16550, \ + .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \ + .irq = JZ4740_IRQ_UART ## _id, \ + } + +static struct plat_serial8250_port jz4740_uart_data[] = { + JZ4740_UART_DATA(0), + JZ4740_UART_DATA(1), + {}, +}; + +static struct platform_device jz4740_uart_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = jz4740_uart_data, + }, +}; + +void jz4740_serial_device_register(void) +{ + struct plat_serial8250_port *p; + + for (p = jz4740_uart_data; p->flags != 0; ++p) + p->uartclk = jz4740_clock_bdata.ext_rate; + + platform_device_register(&jz4740_uart_device); +} -- 1.5.6.5 From lars@metafoo.de Sat Jul 17 14:14:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:15:01 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1054 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491763Ab0GQMO4 (ORCPT ); Sat, 17 Jul 2010 14:14:56 +0200 Received: (qmail 374 invoked by uid 0); 17 Jul 2010 12:14:51 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 331 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.77 with SMTP; 17 Jul 2010 12:14:50 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen , Andrew Morton , linux-fbdev@vger.kernel.org Subject: [PATCH v3] fbdev: Add JZ4740 framebuffer driver Date: Sat, 17 Jul 2010 14:14:34 +0200 Message-Id: <1279368874-21103-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1276924111-11158-17-git-send-email-lars@metafoo.de> References: <1276924111-11158-17-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27407 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for the LCD controller on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen Cc: Andrew Morton Cc: linux-fbdev@vger.kernel.org -- Changes since v1 - Use __packed instead of __attribute__((packed)) - Make jzfb_fix const - Only set mode in set_par if it has changed Changes since v2 - Add support for special tft type lcds - Move include file from include/linux to arch/mips/include/asm/mach-jz4740 --- arch/mips/include/asm/mach-jz4740/jz4740_fb.h | 67 ++ drivers/video/Kconfig | 9 + drivers/video/Makefile | 1 + drivers/video/jz4740_fb.c | 847 +++++++++++++++++++++++++ 4 files changed, 924 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_fb.h create mode 100644 drivers/video/jz4740_fb.c diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_fb.h b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h new file mode 100644 index 0000000..6a50e6f --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2009, Lars-Peter Clausen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__ +#define __ASM_MACH_JZ4740_JZ4740_FB_H__ + +#include + +enum jz4740_fb_lcd_type { + JZ_LCD_TYPE_GENERIC_16_BIT = 0, + JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4), + JZ_LCD_TYPE_SPECIAL_TFT_1 = 1, + JZ_LCD_TYPE_SPECIAL_TFT_2 = 2, + JZ_LCD_TYPE_SPECIAL_TFT_3 = 3, + JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5, + JZ_LCD_TYPE_INTERLACED_CCIR656 = 7, + JZ_LCD_TYPE_SINGLE_COLOR_STN = 8, + JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9, + JZ_LCD_TYPE_DUAL_COLOR_STN = 10, + JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11, + JZ_LCD_TYPE_8BIT_SERIAL = 12, +}; + +#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop)) + +/* +* width: width of the lcd display in mm +* height: height of the lcd display in mm +* num_modes: size of modes +* modes: list of valid video modes +* bpp: bits per pixel for the lcd +* lcd_type: lcd type +*/ + +struct jz4740_fb_platform_data { + unsigned int width; + unsigned int height; + + size_t num_modes; + struct fb_videomode *modes; + + unsigned int bpp; + enum jz4740_fb_lcd_type lcd_type; + + struct { + uint32_t spl; + uint32_t cls; + uint32_t ps; + uint32_t rev; + } special_tft_config; + + unsigned pixclk_falling_edge:1; + unsigned date_enable_active_low:1; +}; + +#endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index a9f9e5e..eae4c8a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2237,6 +2237,15 @@ config FB_BROADSHEET and could also have been called by other names when coupled with a bridge adapter. +config FB_JZ4740 + tristate "JZ4740 LCD framebuffer support" + depends on FB + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + help + Framebuffer support for the JZ4740 SoC. + source "drivers/video/omap/Kconfig" source "drivers/video/omap2/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 3c3bf86..fd2df57 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -132,6 +132,7 @@ obj-$(CONFIG_FB_CARMINE) += carminefb.o obj-$(CONFIG_FB_MB862XX) += mb862xx/ obj-$(CONFIG_FB_MSM) += msm/ obj-$(CONFIG_FB_NUC900) += nuc900fb.o +obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o # Platform or fallback drivers go here obj-$(CONFIG_FB_UVESA) += uvesafb.o diff --git a/drivers/video/jz4740_fb.c b/drivers/video/jz4740_fb.c new file mode 100644 index 0000000..670ecaa --- /dev/null +++ b/drivers/video/jz4740_fb.c @@ -0,0 +1,847 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 SoC LCD framebuffer driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include +#include + +#define JZ_REG_LCD_CFG 0x00 +#define JZ_REG_LCD_VSYNC 0x04 +#define JZ_REG_LCD_HSYNC 0x08 +#define JZ_REG_LCD_VAT 0x0C +#define JZ_REG_LCD_DAH 0x10 +#define JZ_REG_LCD_DAV 0x14 +#define JZ_REG_LCD_PS 0x18 +#define JZ_REG_LCD_CLS 0x1C +#define JZ_REG_LCD_SPL 0x20 +#define JZ_REG_LCD_REV 0x24 +#define JZ_REG_LCD_CTRL 0x30 +#define JZ_REG_LCD_STATE 0x34 +#define JZ_REG_LCD_IID 0x38 +#define JZ_REG_LCD_DA0 0x40 +#define JZ_REG_LCD_SA0 0x44 +#define JZ_REG_LCD_FID0 0x48 +#define JZ_REG_LCD_CMD0 0x4C +#define JZ_REG_LCD_DA1 0x50 +#define JZ_REG_LCD_SA1 0x54 +#define JZ_REG_LCD_FID1 0x58 +#define JZ_REG_LCD_CMD1 0x5C + +#define JZ_LCD_CFG_SLCD BIT(31) +#define JZ_LCD_CFG_PS_DISABLE BIT(23) +#define JZ_LCD_CFG_CLS_DISABLE BIT(22) +#define JZ_LCD_CFG_SPL_DISABLE BIT(21) +#define JZ_LCD_CFG_REV_DISABLE BIT(20) +#define JZ_LCD_CFG_HSYNCM BIT(19) +#define JZ_LCD_CFG_PCLKM BIT(18) +#define JZ_LCD_CFG_INV BIT(17) +#define JZ_LCD_CFG_SYNC_DIR BIT(16) +#define JZ_LCD_CFG_PS_POLARITY BIT(15) +#define JZ_LCD_CFG_CLS_POLARITY BIT(14) +#define JZ_LCD_CFG_SPL_POLARITY BIT(13) +#define JZ_LCD_CFG_REV_POLARITY BIT(12) +#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) +#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) +#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) +#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) +#define JZ_LCD_CFG_18_BIT BIT(7) +#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) +#define JZ_LCD_CFG_MODE_MASK 0xf + +#define JZ_LCD_CTRL_BURST_4 (0x0 << 28) +#define JZ_LCD_CTRL_BURST_8 (0x1 << 28) +#define JZ_LCD_CTRL_BURST_16 (0x2 << 28) +#define JZ_LCD_CTRL_RGB555 BIT(27) +#define JZ_LCD_CTRL_OFUP BIT(26) +#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) +#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) +#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) +#define JZ_LCD_CTRL_PDD_MASK (0xff << 16) +#define JZ_LCD_CTRL_EOF_IRQ BIT(13) +#define JZ_LCD_CTRL_SOF_IRQ BIT(12) +#define JZ_LCD_CTRL_OFU_IRQ BIT(11) +#define JZ_LCD_CTRL_IFU0_IRQ BIT(10) +#define JZ_LCD_CTRL_IFU1_IRQ BIT(9) +#define JZ_LCD_CTRL_DD_IRQ BIT(8) +#define JZ_LCD_CTRL_QDD_IRQ BIT(7) +#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) +#define JZ_LCD_CTRL_LSB_FISRT BIT(5) +#define JZ_LCD_CTRL_DISABLE BIT(4) +#define JZ_LCD_CTRL_ENABLE BIT(3) +#define JZ_LCD_CTRL_BPP_1 0x0 +#define JZ_LCD_CTRL_BPP_2 0x1 +#define JZ_LCD_CTRL_BPP_4 0x2 +#define JZ_LCD_CTRL_BPP_8 0x3 +#define JZ_LCD_CTRL_BPP_15_16 0x4 +#define JZ_LCD_CTRL_BPP_18_24 0x5 + +#define JZ_LCD_CMD_SOF_IRQ BIT(15) +#define JZ_LCD_CMD_EOF_IRQ BIT(16) +#define JZ_LCD_CMD_ENABLE_PAL BIT(12) + +#define JZ_LCD_SYNC_MASK 0x3ff + +#define JZ_LCD_STATE_DISABLED BIT(0) + +struct jzfb_framedesc { + uint32_t next; + uint32_t addr; + uint32_t id; + uint32_t cmd; +} __packed; + +struct jzfb { + struct fb_info *fb; + struct platform_device *pdev; + void __iomem *base; + struct resource *mem; + struct jz4740_fb_platform_data *pdata; + + size_t vidmem_size; + void *vidmem; + dma_addr_t vidmem_phys; + struct jzfb_framedesc *framedesc; + dma_addr_t framedesc_phys; + + struct clk *ldclk; + struct clk *lpclk; + + unsigned is_enabled:1; + struct mutex lock; + + uint32_t pseudo_palette[16]; +}; + +static const struct fb_fix_screeninfo jzfb_fix __devinitdata = { + .id = "JZ4740 FB", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_TRUECOLOR, + .xpanstep = 0, + .ypanstep = 0, + .ywrapstep = 0, + .accel = FB_ACCEL_NONE, +}; + +static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = { + JZ_GPIO_BULK_PIN(LCD_PCLK), + JZ_GPIO_BULK_PIN(LCD_HSYNC), + JZ_GPIO_BULK_PIN(LCD_VSYNC), + JZ_GPIO_BULK_PIN(LCD_DE), + JZ_GPIO_BULK_PIN(LCD_PS), + JZ_GPIO_BULK_PIN(LCD_REV), + JZ_GPIO_BULK_PIN(LCD_CLS), + JZ_GPIO_BULK_PIN(LCD_SPL), +}; + +static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = { + JZ_GPIO_BULK_PIN(LCD_DATA0), + JZ_GPIO_BULK_PIN(LCD_DATA1), + JZ_GPIO_BULK_PIN(LCD_DATA2), + JZ_GPIO_BULK_PIN(LCD_DATA3), + JZ_GPIO_BULK_PIN(LCD_DATA4), + JZ_GPIO_BULK_PIN(LCD_DATA5), + JZ_GPIO_BULK_PIN(LCD_DATA6), + JZ_GPIO_BULK_PIN(LCD_DATA7), + JZ_GPIO_BULK_PIN(LCD_DATA8), + JZ_GPIO_BULK_PIN(LCD_DATA9), + JZ_GPIO_BULK_PIN(LCD_DATA10), + JZ_GPIO_BULK_PIN(LCD_DATA11), + JZ_GPIO_BULK_PIN(LCD_DATA12), + JZ_GPIO_BULK_PIN(LCD_DATA13), + JZ_GPIO_BULK_PIN(LCD_DATA14), + JZ_GPIO_BULK_PIN(LCD_DATA15), + JZ_GPIO_BULK_PIN(LCD_DATA16), + JZ_GPIO_BULK_PIN(LCD_DATA17), +}; + +static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb) +{ + unsigned int num; + + switch (jzfb->pdata->lcd_type) { + case JZ_LCD_TYPE_GENERIC_16_BIT: + num = 4; + break; + case JZ_LCD_TYPE_GENERIC_18_BIT: + num = 4; + break; + case JZ_LCD_TYPE_8BIT_SERIAL: + num = 3; + break; + case JZ_LCD_TYPE_SPECIAL_TFT_1: + case JZ_LCD_TYPE_SPECIAL_TFT_2: + case JZ_LCD_TYPE_SPECIAL_TFT_3: + num = 8; + break; + default: + num = 0; + break; + } + return num; +} + +static unsigned int jzfb_num_data_pins(struct jzfb *jzfb) +{ + unsigned int num; + + switch (jzfb->pdata->lcd_type) { + case JZ_LCD_TYPE_GENERIC_16_BIT: + num = 16; + break; + case JZ_LCD_TYPE_GENERIC_18_BIT: + num = 18; + break; + case JZ_LCD_TYPE_8BIT_SERIAL: + num = 8; + break; + case JZ_LCD_TYPE_SPECIAL_TFT_1: + case JZ_LCD_TYPE_SPECIAL_TFT_2: + case JZ_LCD_TYPE_SPECIAL_TFT_3: + if (jzfb->pdata->bpp == 18) + num = 18; + else + num = 16; + break; + default: + num = 0; + break; + } + return num; +} + +/* Based on CNVT_TOHW macro from skeletonfb.c */ +static inline uint32_t jzfb_convert_color_to_hw(unsigned val, + struct fb_bitfield *bf) +{ + return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset; +} + +static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, struct fb_info *fb) +{ + uint32_t color; + + if (regno >= 16) + return -EINVAL; + + color = jzfb_convert_color_to_hw(red, &fb->var.red); + color |= jzfb_convert_color_to_hw(green, &fb->var.green); + color |= jzfb_convert_color_to_hw(blue, &fb->var.blue); + color |= jzfb_convert_color_to_hw(transp, &fb->var.transp); + + ((uint32_t *)(fb->pseudo_palette))[regno] = color; + + return 0; +} + +static int jzfb_get_controller_bpp(struct jzfb *jzfb) +{ + switch (jzfb->pdata->bpp) { + case 18: + case 24: + return 32; + case 15: + return 16; + default: + return jzfb->pdata->bpp; + } +} + +static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb, + struct fb_var_screeninfo *var) +{ + size_t i; + struct fb_videomode *mode = jzfb->pdata->modes; + + for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) { + if (mode->xres == var->xres && mode->yres == var->yres) + return mode; + } + + return NULL; +} + +static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb) +{ + struct jzfb *jzfb = fb->par; + struct fb_videomode *mode; + + if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) && + var->bits_per_pixel != jzfb->pdata->bpp) + return -EINVAL; + + mode = jzfb_get_mode(jzfb, var); + if (mode == NULL) + return -EINVAL; + + fb_videomode_to_var(var, mode); + + switch (jzfb->pdata->bpp) { + case 8: + break; + case 15: + var->red.offset = 10; + var->red.length = 5; + var->green.offset = 6; + var->green.length = 5; + var->blue.offset = 0; + var->blue.length = 5; + break; + case 16: + var->red.offset = 11; + var->red.length = 5; + var->green.offset = 5; + var->green.length = 6; + var->blue.offset = 0; + var->blue.length = 5; + break; + case 18: + var->red.offset = 16; + var->red.length = 6; + var->green.offset = 8; + var->green.length = 6; + var->blue.offset = 0; + var->blue.length = 6; + var->bits_per_pixel = 32; + break; + case 32: + case 24: + var->transp.offset = 24; + var->transp.length = 8; + var->red.offset = 16; + var->red.length = 8; + var->green.offset = 8; + var->green.length = 8; + var->blue.offset = 0; + var->blue.length = 8; + var->bits_per_pixel = 32; + break; + default: + break; + } + + return 0; +} + +static int jzfb_set_par(struct fb_info *info) +{ + struct jzfb *jzfb = info->par; + struct jz4740_fb_platform_data *pdata = jzfb->pdata; + struct fb_var_screeninfo *var = &info->var; + struct fb_videomode *mode; + uint16_t hds, vds; + uint16_t hde, vde; + uint16_t ht, vt; + uint32_t ctrl; + uint32_t cfg; + unsigned long rate; + + mode = jzfb_get_mode(jzfb, var); + if (mode == NULL) + return -EINVAL; + + if (mode == info->mode) + return 0; + + info->mode = mode; + + hds = mode->hsync_len + mode->left_margin; + hde = hds + mode->xres; + ht = hde + mode->right_margin; + + vds = mode->vsync_len + mode->upper_margin; + vde = vds + mode->yres; + vt = vde + mode->lower_margin; + + ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16; + + switch (pdata->bpp) { + case 1: + ctrl |= JZ_LCD_CTRL_BPP_1; + break; + case 2: + ctrl |= JZ_LCD_CTRL_BPP_2; + break; + case 4: + ctrl |= JZ_LCD_CTRL_BPP_4; + break; + case 8: + ctrl |= JZ_LCD_CTRL_BPP_8; + break; + case 15: + ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */ + case 16: + ctrl |= JZ_LCD_CTRL_BPP_15_16; + break; + case 18: + case 24: + case 32: + ctrl |= JZ_LCD_CTRL_BPP_18_24; + break; + default: + break; + } + + cfg = pdata->lcd_type & 0xf; + + if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) + cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; + + if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) + cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; + + if (pdata->pixclk_falling_edge) + cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; + + if (pdata->date_enable_active_low) + cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; + + if (pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT) + cfg |= JZ_LCD_CFG_18_BIT; + + if (mode->pixclock) { + rate = PICOS2KHZ(mode->pixclock) * 1000; + mode->refresh = rate / vt / ht; + } else { + if (pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) + rate = mode->refresh * (vt + 2 * mode->xres) * ht; + else + rate = mode->refresh * vt * ht; + + mode->pixclock = KHZ2PICOS(rate / 1000); + } + + mutex_lock(&jzfb->lock); + if (!jzfb->is_enabled) + clk_enable(jzfb->ldclk); + else + ctrl |= JZ_LCD_CTRL_ENABLE; + + switch (pdata->lcd_type) { + case JZ_LCD_TYPE_SPECIAL_TFT_1: + case JZ_LCD_TYPE_SPECIAL_TFT_2: + case JZ_LCD_TYPE_SPECIAL_TFT_3: + writel(pdata->special_tft_config.spl, jzfb->base + JZ_REG_LCD_SPL); + writel(pdata->special_tft_config.cls, jzfb->base + JZ_REG_LCD_CLS); + writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_PS); + writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_REV); + break; + default: + cfg |= JZ_LCD_CFG_PS_DISABLE; + cfg |= JZ_LCD_CFG_CLS_DISABLE; + cfg |= JZ_LCD_CFG_SPL_DISABLE; + cfg |= JZ_LCD_CFG_REV_DISABLE; + break; + } + + writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC); + writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC); + + writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT); + + writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH); + writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV); + + writel(cfg, jzfb->base + JZ_REG_LCD_CFG); + + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); + + if (!jzfb->is_enabled) + clk_disable(jzfb->ldclk); + + mutex_unlock(&jzfb->lock); + + clk_set_rate(jzfb->lpclk, rate); + clk_set_rate(jzfb->ldclk, rate * 3); + + return 0; +} + +static void jzfb_enable(struct jzfb *jzfb) +{ + uint32_t ctrl; + + clk_enable(jzfb->ldclk); + + jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); + jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); + + writel(0, jzfb->base + JZ_REG_LCD_STATE); + + writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); + + ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); + ctrl |= JZ_LCD_CTRL_ENABLE; + ctrl &= ~JZ_LCD_CTRL_DISABLE; + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); +} + +static void jzfb_disable(struct jzfb *jzfb) +{ + uint32_t ctrl; + + ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); + ctrl |= JZ_LCD_CTRL_DISABLE; + writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); + do { + ctrl = readl(jzfb->base + JZ_REG_LCD_STATE); + } while (!(ctrl & JZ_LCD_STATE_DISABLED)); + + jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); + jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); + + clk_disable(jzfb->ldclk); +} + +static int jzfb_blank(int blank_mode, struct fb_info *info) +{ + struct jzfb *jzfb = info->par; + + switch (blank_mode) { + case FB_BLANK_UNBLANK: + mutex_lock(&jzfb->lock); + if (jzfb->is_enabled) { + mutex_unlock(&jzfb->lock); + return 0; + } + + jzfb_enable(jzfb); + jzfb->is_enabled = 1; + + mutex_unlock(&jzfb->lock); + break; + default: + mutex_lock(&jzfb->lock); + if (!jzfb->is_enabled) { + mutex_unlock(&jzfb->lock); + return 0; + } + + jzfb_disable(jzfb); + jzfb->is_enabled = 0; + + mutex_unlock(&jzfb->lock); + break; + } + + return 0; +} + +static int jzfb_alloc_devmem(struct jzfb *jzfb) +{ + int max_videosize = 0; + struct fb_videomode *mode = jzfb->pdata->modes; + void *page; + int i; + + for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) { + if (max_videosize < mode->xres * mode->yres) + max_videosize = mode->xres * mode->yres; + } + + max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3; + + jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev, + sizeof(*jzfb->framedesc), + &jzfb->framedesc_phys, GFP_KERNEL); + + if (!jzfb->framedesc) + return -ENOMEM; + + jzfb->vidmem_size = PAGE_ALIGN(max_videosize); + jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev, + jzfb->vidmem_size, + &jzfb->vidmem_phys, GFP_KERNEL); + + if (!jzfb->vidmem) + goto err_free_framedesc; + + for (page = jzfb->vidmem; + page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size); + page += PAGE_SIZE) { + SetPageReserved(virt_to_page(page)); + } + + jzfb->framedesc->next = jzfb->framedesc_phys; + jzfb->framedesc->addr = jzfb->vidmem_phys; + jzfb->framedesc->id = 0xdeafbead; + jzfb->framedesc->cmd = 0; + jzfb->framedesc->cmd |= max_videosize / 4; + + return 0; + +err_free_framedesc: + dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), + jzfb->framedesc, jzfb->framedesc_phys); + return -ENOMEM; +} + +static void jzfb_free_devmem(struct jzfb *jzfb) +{ + dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size, + jzfb->vidmem, jzfb->vidmem_phys); + dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), + jzfb->framedesc, jzfb->framedesc_phys); +} + +static struct fb_ops jzfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = jzfb_check_var, + .fb_set_par = jzfb_set_par, + .fb_blank = jzfb_blank, + .fb_fillrect = sys_fillrect, + .fb_copyarea = sys_copyarea, + .fb_imageblit = sys_imageblit, + .fb_setcolreg = jzfb_setcolreg, +}; + +static int __devinit jzfb_probe(struct platform_device *pdev) +{ + int ret; + struct jzfb *jzfb; + struct fb_info *fb; + struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data; + struct resource *mem; + + if (!pdata) { + dev_err(&pdev->dev, "Missing platform data\n"); + return -ENXIO; + } + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "Failed to get register memory resource\n"); + return -ENXIO; + } + + mem = request_mem_region(mem->start, resource_size(mem), pdev->name); + if (!mem) { + dev_err(&pdev->dev, "Failed to request register memory region\n"); + return -EBUSY; + } + + fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev); + if (!fb) { + dev_err(&pdev->dev, "Failed to allocate framebuffer device\n"); + ret = -ENOMEM; + goto err_release_mem_region; + } + + fb->fbops = &jzfb_ops; + fb->flags = FBINFO_DEFAULT; + + jzfb = fb->par; + jzfb->pdev = pdev; + jzfb->pdata = pdata; + jzfb->mem = mem; + + jzfb->ldclk = clk_get(&pdev->dev, "lcd"); + if (IS_ERR(jzfb->ldclk)) { + ret = PTR_ERR(jzfb->ldclk); + dev_err(&pdev->dev, "Failed to get lcd clock: %d\n", ret); + goto err_framebuffer_release; + } + + jzfb->lpclk = clk_get(&pdev->dev, "lcd_pclk"); + if (IS_ERR(jzfb->lpclk)) { + ret = PTR_ERR(jzfb->lpclk); + dev_err(&pdev->dev, "Failed to get lcd pixel clock: %d\n", ret); + goto err_put_ldclk; + } + + jzfb->base = ioremap(mem->start, resource_size(mem)); + if (!jzfb->base) { + dev_err(&pdev->dev, "Failed to ioremap register memory region\n"); + ret = -EBUSY; + goto err_put_lpclk; + } + + platform_set_drvdata(pdev, jzfb); + + mutex_init(&jzfb->lock); + + fb_videomode_to_modelist(pdata->modes, pdata->num_modes, + &fb->modelist); + fb_videomode_to_var(&fb->var, pdata->modes); + fb->var.bits_per_pixel = pdata->bpp; + jzfb_check_var(&fb->var, fb); + + ret = jzfb_alloc_devmem(jzfb); + if (ret) { + dev_err(&pdev->dev, "Failed to allocate video memory\n"); + goto err_iounmap; + } + + fb->fix = jzfb_fix; + fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8; + fb->fix.mmio_start = mem->start; + fb->fix.mmio_len = resource_size(mem); + fb->fix.smem_start = jzfb->vidmem_phys; + fb->fix.smem_len = fb->fix.line_length * fb->var.yres; + fb->screen_base = jzfb->vidmem; + fb->pseudo_palette = jzfb->pseudo_palette; + + fb_alloc_cmap(&fb->cmap, 256, 0); + + clk_enable(jzfb->ldclk); + jzfb->is_enabled = 1; + + writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); + + fb->mode = NULL; + jzfb_set_par(fb); + + jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); + jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); + + ret = register_framebuffer(fb); + if (ret) { + dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret); + goto err_free_devmem; + } + + jzfb->fb = fb; + + return 0; + +err_free_devmem: + jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); + jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); + + fb_dealloc_cmap(&fb->cmap); + jzfb_free_devmem(jzfb); +err_iounmap: + iounmap(jzfb->base); +err_put_lpclk: + clk_put(jzfb->lpclk); +err_put_ldclk: + clk_put(jzfb->ldclk); +err_framebuffer_release: + framebuffer_release(fb); +err_release_mem_region: + release_mem_region(mem->start, resource_size(mem)); + return ret; +} + +static int __devexit jzfb_remove(struct platform_device *pdev) +{ + struct jzfb *jzfb = platform_get_drvdata(pdev); + + jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb); + + jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); + jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); + + iounmap(jzfb->base); + release_mem_region(jzfb->mem->start, resource_size(jzfb->mem)); + + fb_dealloc_cmap(&jzfb->fb->cmap); + jzfb_free_devmem(jzfb); + + platform_set_drvdata(pdev, NULL); + + clk_put(jzfb->lpclk); + clk_put(jzfb->ldclk); + + framebuffer_release(jzfb->fb); + + return 0; +} + +#ifdef CONFIG_PM + +static int jzfb_suspend(struct device *dev) +{ + struct jzfb *jzfb = dev_get_drvdata(dev); + + acquire_console_sem(); + fb_set_suspend(jzfb->fb, 1); + release_console_sem(); + + mutex_lock(&jzfb->lock); + if (jzfb->is_enabled) + jzfb_disable(jzfb); + mutex_unlock(&jzfb->lock); + + return 0; +} + +static int jzfb_resume(struct device *dev) +{ + struct jzfb *jzfb = dev_get_drvdata(dev); + clk_enable(jzfb->ldclk); + + mutex_lock(&jzfb->lock); + if (jzfb->is_enabled) + jzfb_enable(jzfb); + mutex_unlock(&jzfb->lock); + + acquire_console_sem(); + fb_set_suspend(jzfb->fb, 0); + release_console_sem(); + + return 0; +} + +static const struct dev_pm_ops jzfb_pm_ops = { + .suspend = jzfb_suspend, + .resume = jzfb_resume, + .poweroff = jzfb_suspend, + .restore = jzfb_resume, +}; + +#define JZFB_PM_OPS (&jzfb_pm_ops) + +#else +#define JZFB_PM_OPS NULL +#endif + +static struct platform_driver jzfb_driver = { + .probe = jzfb_probe, + .remove = __devexit_p(jzfb_remove), + .driver = { + .name = "jz4740-fb", + .pm = JZFB_PM_OPS, + }, +}; + +static int __init jzfb_init(void) +{ + return platform_driver_register(&jzfb_driver); +} +module_init(jzfb_init); + +static void __exit jzfb_exit(void) +{ + platform_driver_unregister(&jzfb_driver); +} +module_exit(jzfb_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lars-Peter Clausen "); +MODULE_DESCRIPTION("JZ4740 SoC LCD framebuffer driver"); +MODULE_ALIAS("platform:jz4740-fb"); -- 1.5.6.5 From lars@metafoo.de Sat Jul 17 14:15:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:15:55 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1043 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491799Ab0GQMPu (ORCPT ); Sat, 17 Jul 2010 14:15:50 +0200 Received: (qmail 19371 invoked by uid 0); 17 Jul 2010 12:15:47 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 19297 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.81 with SMTP; 17 Jul 2010 12:15:46 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen , David Woodhouse , linux-mtd@lists.infradead.org Subject: [PATCH v3] MTD: Nand: Add JZ4740 NAND driver Date: Sat, 17 Jul 2010 14:15:29 +0200 Message-Id: <1279368929-21193-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1276924111-11158-18-git-send-email-lars@metafoo.de> References: <1276924111-11158-18-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27408 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for the NAND controller on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen Cc: David Woodhouse Cc: linux-mtd@lists.infradead.org -- Changes since v1 - JZ4740: Remove debug macro - Fix platform driver remove callback - Add custom nand read/write callback since we need to support more then 64 ecc bytes Changes since v2 - Fix potential deadlock that can happen when the hardware is broken - Move include file from include/linux/mtd/ to arch/mips/include/asm/mach-jz4740/ - {Enable,Disable} NAND-chip in {probe,remove} - Supply memory bank address through platform resource --- arch/mips/include/asm/mach-jz4740/jz4740_nand.h | 34 ++ drivers/mtd/nand/Kconfig | 6 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/jz4740_nand.c | 516 +++++++++++++++++++++++ 4 files changed, 557 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_nand.h create mode 100644 drivers/mtd/nand/jz4740_nand.c diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h new file mode 100644 index 0000000..bb5b9a4 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 SoC NAND controller driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__ +#define __ASM_MACH_JZ4740_JZ4740_NAND_H__ + +#include +#include + +struct jz_nand_platform_data { + int num_partitions; + struct mtd_partition *partitions; + + struct nand_ecclayout *ecc_layout; + + unsigned int busy_gpio; + + void (*ident_callback)(struct platform_device *, struct nand_chip *, + struct mtd_partition **, int *num_partitions); +}; + +#endif diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index ffc3720..362d177 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -526,4 +526,10 @@ config MTD_NAND_NUC900 This enables the driver for the NAND Flash on evaluation board based on w90p910 / NUC9xx. +config MTD_NAND_JZ4740 + tristate "Support for JZ4740 SoC NAND controller" + depends on MACH_JZ4740 + help + Enables support for NAND Flash on JZ4740 SoC based boards. + endif # MTD_NAND diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index e8ab884..ac83dcd 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -46,5 +46,6 @@ obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o +obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o nand-objs := nand_base.o nand_bbt.o diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c new file mode 100644 index 0000000..67343fc --- /dev/null +++ b/drivers/mtd/nand/jz4740_nand.c @@ -0,0 +1,516 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen + * JZ4740 SoC NAND controller driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#define JZ_REG_NAND_CTRL 0x50 +#define JZ_REG_NAND_ECC_CTRL 0x100 +#define JZ_REG_NAND_DATA 0x104 +#define JZ_REG_NAND_PAR0 0x108 +#define JZ_REG_NAND_PAR1 0x10C +#define JZ_REG_NAND_PAR2 0x110 +#define JZ_REG_NAND_IRQ_STAT 0x114 +#define JZ_REG_NAND_IRQ_CTRL 0x118 +#define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2)) + +#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4) +#define JZ_NAND_ECC_CTRL_ENCODING BIT(3) +#define JZ_NAND_ECC_CTRL_RS BIT(2) +#define JZ_NAND_ECC_CTRL_RESET BIT(1) +#define JZ_NAND_ECC_CTRL_ENABLE BIT(0) + +#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29)) +#define JZ_NAND_STATUS_PAD_FINISH BIT(4) +#define JZ_NAND_STATUS_DEC_FINISH BIT(3) +#define JZ_NAND_STATUS_ENC_FINISH BIT(2) +#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1) +#define JZ_NAND_STATUS_ERROR BIT(0) + +#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1) +#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1) + +#define JZ_NAND_MEM_ADDR_OFFSET 0x10000 +#define JZ_NAND_MEM_CMD_OFFSET 0x08000 + +struct jz_nand { + struct mtd_info mtd; + struct nand_chip chip; + void __iomem *base; + struct resource *mem; + + void __iomem *bank_base; + struct resource *bank_mem; + + struct jz_nand_platform_data *pdata; + bool is_reading; +}; + +static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd) +{ + return container_of(mtd, struct jz_nand, mtd); +} + +static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) +{ + struct jz_nand *nand = mtd_to_jz_nand(mtd); + struct nand_chip *chip = mtd->priv; + uint32_t reg; + + if (ctrl & NAND_CTRL_CHANGE) { + BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE)); + if (ctrl & NAND_ALE) + chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET; + else if (ctrl & NAND_CLE) + chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET; + else + chip->IO_ADDR_W = nand->bank_base; + + reg = readl(nand->base + JZ_REG_NAND_CTRL); + if (ctrl & NAND_NCE) + reg |= JZ_NAND_CTRL_ASSERT_CHIP(0); + else + reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0); + writel(reg, nand->base + JZ_REG_NAND_CTRL); + } + if (dat != NAND_CMD_NONE) + writeb(dat, chip->IO_ADDR_W); +} + +static int jz_nand_dev_ready(struct mtd_info *mtd) +{ + struct jz_nand *nand = mtd_to_jz_nand(mtd); + return gpio_get_value_cansleep(nand->pdata->busy_gpio); +} + +static void jz_nand_hwctl(struct mtd_info *mtd, int mode) +{ + struct jz_nand *nand = mtd_to_jz_nand(mtd); + uint32_t reg; + + writel(0, nand->base + JZ_REG_NAND_IRQ_STAT); + reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); + + reg |= JZ_NAND_ECC_CTRL_RESET; + reg |= JZ_NAND_ECC_CTRL_ENABLE; + reg |= JZ_NAND_ECC_CTRL_RS; + + switch (mode) { + case NAND_ECC_READ: + reg &= ~JZ_NAND_ECC_CTRL_ENCODING; + nand->is_reading = true; + break; + case NAND_ECC_WRITE: + reg |= JZ_NAND_ECC_CTRL_ENCODING; + nand->is_reading = false; + break; + default: + break; + } + + writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); +} + +static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + struct jz_nand *nand = mtd_to_jz_nand(mtd); + uint32_t reg, status; + int i; + unsigned int timeout = 1000; + static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4, + 0x8b, 0xff, 0xb7, 0x6f}; + + if (nand->is_reading) + return 0; + + do { + status = readl(nand->base + JZ_REG_NAND_IRQ_STAT); + } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout); + + if (timeout == 0) + return -1; + + reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); + reg &= ~JZ_NAND_ECC_CTRL_ENABLE; + writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); + + for (i = 0; i < 9; ++i) + ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i); + + /* If the written data is completly 0xff, we also want to write 0xff as + * ecc, otherwise we will get in trouble when doing subpage writes. */ + if (memcmp(ecc_code, empty_block_ecc, 9) == 0) + memset(ecc_code, 0xff, 9); + + return 0; +} + +static void jz_nand_correct_data(uint8_t *dat, int index, int mask) +{ + int offset = index & 0x7; + uint16_t data; + + index += (index >> 3); + + data = dat[index]; + data |= dat[index+1] << 8; + + mask ^= (data >> offset) & 0x1ff; + data &= ~(0x1ff << offset); + data |= (mask << offset); + + dat[index] = data & 0xff; + dat[index+1] = (data >> 8) & 0xff; +} + +static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, uint8_t *calc_ecc) +{ + struct jz_nand *nand = mtd_to_jz_nand(mtd); + int i, error_count, index; + uint32_t reg, status, error; + uint32_t t; + unsigned int timeout = 1000; + + t = read_ecc[0]; + + if (t == 0xff) { + for (i = 1; i < 9; ++i) + t &= read_ecc[i]; + + t &= dat[0]; + t &= dat[nand->chip.ecc.size / 2]; + t &= dat[nand->chip.ecc.size - 1]; + + if (t == 0xff) { + for (i = 1; i < nand->chip.ecc.size - 1; ++i) + t &= dat[i]; + if (t == 0xff) + return 0; + } + } + + for (i = 0; i < 9; ++i) + writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i); + + reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); + reg |= JZ_NAND_ECC_CTRL_PAR_READY; + writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); + + do { + status = readl(nand->base + JZ_REG_NAND_IRQ_STAT); + } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout); + + if (timeout == 0) + return -1; + + reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); + reg &= ~JZ_NAND_ECC_CTRL_ENABLE; + writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); + + if (status & JZ_NAND_STATUS_ERROR) { + if (status & JZ_NAND_STATUS_UNCOR_ERROR) + return -1; + + error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29; + + for (i = 0; i < error_count; ++i) { + error = readl(nand->base + JZ_REG_NAND_ERR(i)); + index = ((error >> 16) & 0x1ff) - 1; + if (index >= 0 && index < 512) + jz_nand_correct_data(dat, index, error & 0x1ff); + } + + return error_count; + } + + return 0; +} + + +/* Copy paste of nand_read_page_hwecc_oob_first except for different eccpos + * handling. The ecc area is for 4k chips 72 bytes long and thus does not fit + * into the eccpos array. */ +static int jz_nand_read_page_hwecc_oob_first(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + unsigned int ecc_offset = chip->page_shift; + + /* Read the OOB area first */ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + + stat = chip->ecc.correct(mtd, p, &chip->oob_poi[i], NULL); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +/* Copy-and-paste of nand_write_page_hwecc with different eccpos handling. */ +static void jz_nand_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + const uint8_t *p = buf; + unsigned int ecc_offset = chip->page_shift; + + for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + chip->ecc.hwctl(mtd, NAND_ECC_WRITE); + chip->write_buf(mtd, p, eccsize); + chip->ecc.calculate(mtd, p, &chip->oob_poi[i]); + } + + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); +} + +#ifdef CONFIG_MTD_CMDLINE_PARTS +static const char *part_probes[] = {"cmdline", NULL}; +#endif + +static int jz_nand_ioremap_resource(struct platform_device *pdev, + const char *name, struct resource **res, void __iomem **base) +{ + int ret; + + *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); + if (!*res) { + dev_err(&pdev->dev, "Failed to get platform %s memory\n", name); + ret = -ENXIO; + goto err; + } + + *res = request_mem_region((*res)->start, resource_size(*res), + pdev->name); + if (!*res) { + dev_err(&pdev->dev, "Failed to request %s memory region\n", name); + ret = -EBUSY; + goto err; + } + + *base = ioremap((*res)->start, resource_size(*res)); + if (!*base) { + dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name); + ret = -EBUSY; + goto err_release_mem; + } + + return 0; + +err_release_mem: + release_mem_region((*res)->start, resource_size(*res)); +err: + *res = NULL; + *base = NULL; + return ret; +} + +static int __devinit jz_nand_probe(struct platform_device *pdev) +{ + int ret; + struct jz_nand *nand; + struct nand_chip *chip; + struct mtd_info *mtd; + struct jz_nand_platform_data *pdata = pdev->dev.platform_data; +#ifdef CONFIG_MTD_PARTITIONS + struct mtd_partition *partition_info; + int num_partitions = 0; +#endif + + nand = kzalloc(sizeof(*nand), GFP_KERNEL); + if (!nand) { + dev_err(&pdev->dev, "Failed to allocate device structure.\n"); + return -ENOMEM; + } + + ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base); + if (ret) + goto err_free; + ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem, + &nand->bank_base); + if (ret) + goto err_iounmap_mmio; + + if (pdata && gpio_is_valid(pdata->busy_gpio)) { + ret = gpio_request(pdata->busy_gpio, "NAND busy pin"); + if (ret) { + dev_err(&pdev->dev, + "Failed to request busy gpio %d: %d\n", + pdata->busy_gpio, ret); + goto err_iounmap_mem; + } + } + + mtd = &nand->mtd; + chip = &nand->chip; + mtd->priv = chip; + mtd->owner = THIS_MODULE; + mtd->name = "jz4740-nand"; + + chip->ecc.hwctl = jz_nand_hwctl; + chip->ecc.calculate = jz_nand_calculate_ecc_rs; + chip->ecc.correct = jz_nand_correct_ecc_rs; + chip->ecc.mode = NAND_ECC_HW_OOB_FIRST; + chip->ecc.size = 512; + chip->ecc.bytes = 9; + + chip->ecc.read_page = jz_nand_read_page_hwecc_oob_first; + chip->ecc.write_page = jz_nand_write_page_hwecc; + + if (pdata) + chip->ecc.layout = pdata->ecc_layout; + + chip->chip_delay = 50; + chip->cmd_ctrl = jz_nand_cmd_ctrl; + + if (pdata && gpio_is_valid(pdata->busy_gpio)) + chip->dev_ready = jz_nand_dev_ready; + + chip->IO_ADDR_R = nand->bank_base; + chip->IO_ADDR_W = nand->bank_base; + + nand->pdata = pdata; + platform_set_drvdata(pdev, nand); + + writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL); + + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) { + dev_err(&pdev->dev, "Failed to scan nand\n"); + goto err_gpio_free; + } + + if (pdata && pdata->ident_callback) { + pdata->ident_callback(pdev, chip, &pdata->partitions, + &pdata->num_partitions); + } + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(&pdev->dev, "Failed to scan nand\n"); + goto err_gpio_free; + } + +#ifdef CONFIG_MTD_PARTITIONS +#ifdef CONFIG_MTD_CMDLINE_PARTS + num_partitions = parse_mtd_partitions(mtd, part_probes, + &partition_info, 0); +#endif + if (num_partitions <= 0 && pdata) { + num_partitions = pdata->num_partitions; + partition_info = pdata->partitions; + } + + if (num_partitions > 0) + ret = add_mtd_partitions(mtd, partition_info, num_partitions); + else +#endif + ret = add_mtd_device(mtd); + + if (ret) { + dev_err(&pdev->dev, "Failed to add mtd device\n"); + goto err_nand_release; + } + + dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n"); + + return 0; + +err_nand_release: + nand_release(&nand->mtd); +err_gpio_free: + platform_set_drvdata(pdev, NULL); + gpio_free(pdata->busy_gpio); +err_iounmap_mem: + iounmap(nand->bank_base); +err_iounmap_mmio: + iounmap(nand->base); +err_free: + kfree(nand); + return ret; +} + +static int __devexit jz_nand_remove(struct platform_device *pdev) +{ + struct jz_nand *nand = platform_get_drvdata(pdev); + + nand_release(&nand->mtd); + + /* Deassert and disable all chips */ + writel(0, nand->base + JZ_REG_NAND_CTRL); + + iounmap(nand->bank_base); + release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem)); + iounmap(nand->base); + release_mem_region(nand->mem->start, resource_size(nand->mem)); + + platform_set_drvdata(pdev, NULL); + kfree(nand); + + return 0; +} + +struct platform_driver jz_nand_driver = { + .probe = jz_nand_probe, + .remove = __devexit_p(jz_nand_remove), + .driver = { + .name = "jz4740-nand", + .owner = THIS_MODULE, + }, +}; + +static int __init jz_nand_init(void) +{ + return platform_driver_register(&jz_nand_driver); +} +module_init(jz_nand_init); + +static void __exit jz_nand_exit(void) +{ + platform_driver_unregister(&jz_nand_driver); +} +module_exit(jz_nand_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lars-Peter Clausen "); +MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC"); +MODULE_ALIAS("platform:jz4740-nand"); -- 1.5.6.5 From lars@metafoo.de Sat Jul 17 14:16:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jul 2010 14:17:02 +0200 (CEST) Received: from smtp-out-005.synserver.de ([212.40.180.5]:1054 "HELO smtp-out-003.synserver.de" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with SMTP id S1491007Ab0GQMQ5 (ORCPT ); Sat, 17 Jul 2010 14:16:57 +0200 Received: (qmail 20374 invoked by uid 0); 17 Jul 2010 12:16:57 -0000 X-SynServer-TrustedSrc: 1 X-SynServer-AuthUser: lars@laprican.de X-SynServer-PPID: 20162 Received: from d077015.adsl.hansenet.de (HELO localhost.localdomain) [80.171.77.15] by 217.119.54.81 with SMTP; 17 Jul 2010 12:16:56 -0000 From: Lars-Peter Clausen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH v3] MIPS: JZ4740: Add qi_lb60 board support Date: Sat, 17 Jul 2010 14:16:29 +0200 Message-Id: <1279368989-21316-1-git-send-email-lars@metafoo.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1276924111-11158-26-git-send-email-lars@metafoo.de> References: <1276924111-11158-26-git-send-email-lars@metafoo.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 27409 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lars@metafoo.de Precedence: bulk X-list: linux-mips This patch adds support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device. Signed-off-by: Lars-Peter Clausen --- Changes since v1 - Register jz4740 pcm device - Battery device is now registered by the ADC MFD device Changes since v2 - Use the pwm-beeper instead of the pwm-leds driver for the piezo - Update include file locations --- arch/mips/jz4740/Kconfig | 4 + arch/mips/jz4740/Makefile | 2 + arch/mips/jz4740/board-qi_lb60.c | 471 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 477 insertions(+), 0 deletions(-) create mode 100644 arch/mips/jz4740/board-qi_lb60.c diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig index 8a5e850..3e7141f 100644 --- a/arch/mips/jz4740/Kconfig +++ b/arch/mips/jz4740/Kconfig @@ -1,6 +1,10 @@ choice prompt "Machine type" depends on MACH_JZ4740 + default JZ4740_QI_LB60 + +config JZ4740_QI_LB60 + bool "Qi Hardware Ben NanoNote" endchoice diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile index a803ccb..a604eae 100644 --- a/arch/mips/jz4740/Makefile +++ b/arch/mips/jz4740/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o # board specific support +obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o + # PM support obj-$(CONFIG_PM) += pm.o diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c new file mode 100644 index 0000000..5742bb4 --- /dev/null +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -0,0 +1,471 @@ +/* + * linux/arch/mips/jz4740/board-qi_lb60.c + * + * QI_LB60 board support + * + * Copyright (c) 2009 Qi Hardware inc., + * Author: Xiangfu Liu + * Copyright 2010, Lars-Petrer Clausen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or later + * as published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include + +#include + +#include "clock.h" + +static bool is_avt2; + +/* GPIOs */ +#define QI_LB60_GPIO_SD_CD JZ_GPIO_PORTD(0) +#define QI_LB60_GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2) + +#define QI_LB60_GPIO_KEYOUT(x) (JZ_GPIO_PORTC(10) + (x)) +#define QI_LB60_GPIO_KEYIN(x) (JZ_GPIO_PORT