From David.Daney@caviumnetworks.com Fri Apr 2 03:18:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Apr 2010 03:19:03 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10744 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492107Ab0DBBS6 (ORCPT ); Fri, 2 Apr 2010 03:18:58 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 01 Apr 2010 18:19:08 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Apr 2010 18:18:07 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Apr 2010 18:18:07 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o321I3tg012790; Thu, 1 Apr 2010 18:18:03 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o321I3rT012789; Thu, 1 Apr 2010 18:18:03 -0700 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: davem@davemloft.net, David Daney Subject: [PATCH 1/2] netdev: phy/mdio-octeon: Enable the hardware before using it. Date: Thu, 1 Apr 2010 18:17:54 -0700 Message-Id: <1270171075-12741-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1270171075-12741-1-git-send-email-ddaney@caviumnetworks.com> References: <1270171075-12741-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 02 Apr 2010 01:18:07.0584 (UTC) FILETIME=[5A09CE00:01CAD202] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26337 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips In some cases the mdio bus is not enabled at the time of probing. This prevents anything from working, so we will enable it before trying to use it, and disable it when the driver is removed. Signed-off-by: David Daney --- drivers/net/phy/mdio-octeon.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c index 61a4461..dfaaf30 100644 --- a/drivers/net/phy/mdio-octeon.c +++ b/drivers/net/phy/mdio-octeon.c @@ -87,6 +87,7 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, static int __init octeon_mdiobus_probe(struct platform_device *pdev) { struct octeon_mdiobus *bus; + union cvmx_smix_en smi_en; int i; int err = -ENOENT; @@ -102,6 +103,10 @@ static int __init octeon_mdiobus_probe(struct platform_device *pdev) if (!bus->mii_bus) goto err; + smi_en.u64 = 0; + smi_en.s.en = 1; + cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + /* * Standard Octeon evaluation boards don't support phy * interrupts, we need to poll. @@ -132,17 +137,22 @@ err_register: err: devm_kfree(&pdev->dev, bus); + smi_en.u64 = 0; + cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); return err; } static int __exit octeon_mdiobus_remove(struct platform_device *pdev) { struct octeon_mdiobus *bus; + union cvmx_smix_en smi_en; bus = dev_get_drvdata(&pdev->dev); mdiobus_unregister(bus->mii_bus); mdiobus_free(bus->mii_bus); + smi_en.u64 = 0; + cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); return 0; } -- 1.6.6.1 From David.Daney@caviumnetworks.com Fri Apr 2 03:19:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Apr 2010 03:19:30 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10746 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491108Ab0DBBS6 (ORCPT ); Fri, 2 Apr 2010 03:18:58 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 01 Apr 2010 18:19:08 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Apr 2010 18:18:07 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Apr 2010 18:18:07 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o321I3q3012794; Thu, 1 Apr 2010 18:18:03 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o321I3sH012793; Thu, 1 Apr 2010 18:18:03 -0700 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: davem@davemloft.net, David Daney Subject: [PATCH 2/2] staging: octeon-ethernet: Use proper phy addresses for Movidis hardware. Date: Thu, 1 Apr 2010 18:17:55 -0700 Message-Id: <1270171075-12741-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1270171075-12741-1-git-send-email-ddaney@caviumnetworks.com> References: <1270171075-12741-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 02 Apr 2010 01:18:07.0584 (UTC) FILETIME=[5A09CE00:01CAD202] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26338 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- drivers/staging/octeon/cvmx-helper-board.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/drivers/staging/octeon/cvmx-helper-board.c index 3085e38..00a555b 100644 --- a/drivers/staging/octeon/cvmx-helper-board.c +++ b/drivers/staging/octeon/cvmx-helper-board.c @@ -153,6 +153,14 @@ int cvmx_helper_board_get_mii_address(int ipd_port) * through switch. */ return -1; + + case CVMX_BOARD_TYPE_CUST_WSX16: + if (ipd_port >= 0 && ipd_port <= 3) + return ipd_port; + else if (ipd_port >= 16 && ipd_port <= 19) + return ipd_port - 16 + 4; + else + return -1; } /* Some unknown board. Somebody forgot to update this function... */ -- 1.6.6.1 From David.Daney@caviumnetworks.com Fri Apr 2 03:19:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Apr 2010 03:19:54 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10745 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492102Ab0DBBS6 (ORCPT ); Fri, 2 Apr 2010 03:18:58 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 01 Apr 2010 18:19:08 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Apr 2010 18:18:05 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Apr 2010 18:18:05 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o321I3Nt012786; Thu, 1 Apr 2010 18:18:03 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o321I16M012785; Thu, 1 Apr 2010 18:18:01 -0700 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: davem@davemloft.net, David Daney Subject: [PATCH 0/2] Fix ethernet driver for Octeon based Movidis hardware Date: Thu, 1 Apr 2010 18:17:53 -0700 Message-Id: <1270171075-12741-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 X-OriginalArrivalTime: 02 Apr 2010 01:18:05.0630 (UTC) FILETIME=[58DFA5E0:01CAD202] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26339 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The Movidis X16 bootloader doesn't enable the mdio bus. The first patch fixes this by enabling the mdio bus when the driver is initialized. Also the addresses of the PHYs was unknown for this device. The second patch adds the corresponding PHY addresses. With both patches applied I can successfully use all eight Ethernet ports. Please consider for 2.6.34. Since Octeon is an embedded MIPS SOC it is unlikely to break the kernel for any workstations. Any or all of these could be considered for merging via Ralf's linux-mips.org tree. Thanks, David Daney (2): netdev: phy/mdio-octeon: Enable the hardware before using it. staging: octeon-ethernet: Use proper phy addresses for Movidis hardware. drivers/net/phy/mdio-octeon.c | 10 ++++++++++ drivers/staging/octeon/cvmx-helper-board.c | 8 ++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) From davem@davemloft.net Fri Apr 2 03:20:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Apr 2010 03:20:50 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:45966 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492102Ab0DBBUq (ORCPT ); Fri, 2 Apr 2010 03:20:46 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 51A6024C020; Thu, 1 Apr 2010 18:20:46 -0700 (PDT) Date: Thu, 01 Apr 2010 18:20:45 -0700 (PDT) Message-Id: <20100401.182045.106908204.davem@davemloft.net> To: ddaney@caviumnetworks.com Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Subject: Re: [PATCH 0/2] Fix ethernet driver for Octeon based Movidis hardware From: David Miller In-Reply-To: <1270171075-12741-1-git-send-email-ddaney@caviumnetworks.com> References: <1270171075-12741-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: Mew version 6.3 on Emacs 23.1 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26340 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: David Daney Date: Thu, 1 Apr 2010 18:17:53 -0700 > The Movidis X16 bootloader doesn't enable the mdio bus. The first > patch fixes this by enabling the mdio bus when the driver is > initialized. > > Also the addresses of the PHYs was unknown for this device. The > second patch adds the corresponding PHY addresses. > > With both patches applied I can successfully use all eight Ethernet > ports. > > Please consider for 2.6.34. Since Octeon is an embedded MIPS SOC it > is unlikely to break the kernel for any workstations. Any or all of > these could be considered for merging via Ralf's linux-mips.org tree. Ralf please merge this via your MIPS tree, thanks: Acked-by: David S. Miller From aba@not.so.argh.org Fri Apr 2 15:32:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Apr 2010 15:32:38 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:42383 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491777Ab0DBNcd (ORCPT ); Fri, 2 Apr 2010 15:32:33 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1Nxgz8-0002h4-Ih; Fri, 02 Apr 2010 13:32:31 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1Nxgz2-0004y2-J4; Fri, 02 Apr 2010 15:32:24 +0200 Date: Fri, 2 Apr 2010 15:32:24 +0200 From: Andreas Barth To: David Daney Cc: Peter 'p2' De Schrijver , linux-mips@linux-mips.org Subject: Re: movidis x16 hard lockup using 2.6.33 Message-ID: <20100402133224.GR27216@mails.so.argh.org> References: <20100326184132.GU2437@apfelkorn> <4BAD03A5.9070701@caviumnetworks.com> <20100327230744.GG27216@mails.so.argh.org> <4BB0DB2A.9080405@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4BB0DB2A.9080405@caviumnetworks.com> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26341 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips * David Daney (ddaney@caviumnetworks.com) [100329 18:54]: > [...] I need to admit I'm sorry but I can't read enough from the log file. Serial console output is http://alius.ayous.org/~aba/screenlog.0 This kernel is with the NMI-handler but without the "don't reboot" patch: Linux version 2.6.34-rc2-dsa-octeon (aba@gabrielli) (gcc version 4.4.3 (Debian 4.4.3-3) ) #5 SMP Sat Mar 27 10:16:03 UTC 2010 and this one has NMI-handler plus the small loop: Linux version 2.6.34-rc2-dsa-octeon (aba@gabrielli) (gcc version 4.4.3 (Debian 4.4.3-3) ) #6 SMP Mon Mar 29 22:23:26 UTC 2010 Unfortunatly it looks like we get neither the information nor don't reboot, but adding the NMU handler changed behaviour from "machine freezes" to "machine reboots". Thanks for helping us so much. Andi From aba@not.so.argh.org Fri Apr 2 17:03:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Apr 2010 17:04:03 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:33636 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491892Ab0DBPD6 (ORCPT ); Fri, 2 Apr 2010 17:03:58 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NxiG8-0004JD-WA; Fri, 02 Apr 2010 14:54:11 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1NxiG1-00052Y-Fa; Fri, 02 Apr 2010 16:54:01 +0200 Date: Fri, 2 Apr 2010 16:54:01 +0200 From: Andreas Barth To: Wu Zhangjin Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH v3 1/3] Loongson-2F: Flush the branch target history such as BTB and RAS Message-ID: <20100402145401.GS27216@mails.so.argh.org> References: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26342 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips * Wu Zhangjin (wuzhangjin@gmail.com) [100313 05:45]: > This patch did clear BTB(branch target buffer), forbid RAS(return > address stack) via Loongson-2F's 64bit diagnostic register. Unfortunatly the Loongson 2F here still fails with this patch, compiled with the new binutils and both options enabled. Testcase: plain debian unstable chroot, build binutils in that chroot. More ideas, codes, whatever welcome. Andi From gregkh@suse.de Fri Apr 2 19:05:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Apr 2010 19:05:21 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:51761 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491978Ab0DBRFN (ORCPT ); Fri, 2 Apr 2010 19:05:13 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) by mx2.suse.de (Postfix) with ESMTP id 662CE86391; Fri, 2 Apr 2010 19:05:13 +0200 (CEST) Date: Fri, 2 Apr 2010 10:04:24 -0700 From: Greg KH To: David Miller Cc: ddaney@caviumnetworks.com, ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 0/2] Fix ethernet driver for Octeon based Movidis hardware Message-ID: <20100402170424.GC32293@suse.de> References: <1270171075-12741-1-git-send-email-ddaney@caviumnetworks.com> <20100401.182045.106908204.davem@davemloft.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100401.182045.106908204.davem@davemloft.net> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26343 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips On Thu, Apr 01, 2010 at 06:20:45PM -0700, David Miller wrote: > From: David Daney > Date: Thu, 1 Apr 2010 18:17:53 -0700 > > > The Movidis X16 bootloader doesn't enable the mdio bus. The first > > patch fixes this by enabling the mdio bus when the driver is > > initialized. > > > > Also the addresses of the PHYs was unknown for this device. The > > second patch adds the corresponding PHY addresses. > > > > With both patches applied I can successfully use all eight Ethernet > > ports. > > > > Please consider for 2.6.34. Since Octeon is an embedded MIPS SOC it > > is unlikely to break the kernel for any workstations. Any or all of > > these could be considered for merging via Ralf's linux-mips.org tree. > > Ralf please merge this via your MIPS tree, thanks: > > Acked-by: David S. Miller I agree, Ralf, please take these and you can add: Acked-by: Greg Kroah-Hartman to them. thanks, greg k-h From wuzhangjin@gmail.com Sat Apr 3 03:49:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Apr 2010 03:50:05 +0200 (CEST) Received: from mail-yw0-f189.google.com ([209.85.211.189]:60347 "EHLO mail-yw0-f189.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492194Ab0DCBt7 (ORCPT ); Sat, 3 Apr 2010 03:49:59 +0200 Received: by ywh27 with SMTP id 27so1659038ywh.22 for ; Fri, 02 Apr 2010 18:49:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=TqmLzh3tk62OgCfAHtx9d5B4mj7XQafF2uQTwtkvbAs=; b=C4P0ig7W81zYLeKumGD1pluL3RhLtS0hu+aW7l0BvL0M6NYxkgwS1A1msEPlo2YyG+ 4SN/Tr2MO9fYJyHIEJGpCxOwQneAG74q1JtkVAzhLNLFDra3sMnlisGXSe1DBj8C9BFO r4S1R+pn5/l1Ld9KYglTHgrtoqhPTB9SxnsSw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=jiYhPpX8zhIt+NIjBjrHx6tYZh4zZxmqj+GDVANFRdkPJ9kbDdUt0Nr42hcSkYgZTC CCuxQVyk9H9U04Bt1ORr5IJN8zHz35Fo123CALMlZF4vcVTtvEY13cr4k6XMi84y0inu AhV0XcKDUpQ0u66MnogmuAVqosOMk5Pz4h+P8= Received: by 10.101.142.37 with SMTP id u37mr6906396ann.79.1270259391431; Fri, 02 Apr 2010 18:49:51 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm426796iwn.12.2010.04.02.18.49.47 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 02 Apr 2010 18:49:49 -0700 (PDT) Subject: Re: [PATCH v3 1/3] Loongson-2F: Flush the branch target history such as BTB and RAS From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Andreas Barth Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <20100402145401.GS27216@mails.so.argh.org> References: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> <20100402145401.GS27216@mails.so.argh.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 03 Apr 2010 09:42:55 +0800 Message-ID: <1270258975.23702.18.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26344 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2010-04-02 at 16:54 +0200, Andreas Barth wrote: > * Wu Zhangjin (wuzhangjin@gmail.com) [100313 05:45]: > > This patch did clear BTB(branch target buffer), forbid RAS(return > > address stack) via Loongson-2F's 64bit diagnostic register. > > Unfortunatly the Loongson 2F here still fails with this patch, > compiled with the new binutils and both options enabled. > > Testcase: plain debian unstable chroot, build binutils in that chroot. > > More ideas, codes, whatever welcome. Hi, This patch is not enough, please use the kernel(>=2.6.32) from http://dev.lemote.com/code/rt4ls or http://dev.lemote.com/code/linux-loongson-community Regards, Wu Zhangjin From r0bertz@gentoo.org Sat Apr 3 03:53:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Apr 2010 03:54:03 +0200 (CEST) Received: from smtp.gentoo.org ([140.211.166.183]:56695 "EHLO smtp.gentoo.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492194Ab0DCBx7 (ORCPT ); Sat, 3 Apr 2010 03:53:59 +0200 Received: by smtp.gentoo.org (Postfix, from userid 2181) id 2469F1B41BB; Sat, 3 Apr 2010 01:53:52 +0000 (UTC) Date: Sat, 3 Apr 2010 01:53:52 +0000 From: Zhang Le To: Andreas Barth Cc: Wu Zhangjin , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH v3 1/3] Loongson-2F: Flush the branch target history such as BTB and RAS Message-ID: <20100403015352.GA26168@woodpecker.gentoo.org> Mail-Followup-To: Andreas Barth , Wu Zhangjin , Ralf Baechle , linux-mips@linux-mips.org References: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> <20100402145401.GS27216@mails.so.argh.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100402145401.GS27216@mails.so.argh.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26345 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: r0bertz@gentoo.org Precedence: bulk X-list: linux-mips On 16:54 Fri 02 Apr , Andreas Barth wrote: > * Wu Zhangjin (wuzhangjin@gmail.com) [100313 05:45]: > > This patch did clear BTB(branch target buffer), forbid RAS(return > > address stack) via Loongson-2F's 64bit diagnostic register. > > Unfortunatly the Loongson 2F here still fails with this patch, > compiled with the new binutils and both options enabled. Which version of binutils exactly? The patch is in cvs, but latest binutils-2.20.1 still didn't include it. You need to patch it. Zhang, Le From aba@not.so.argh.org Sat Apr 3 05:11:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Apr 2010 05:11:39 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:38446 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491078Ab0DCDLf (ORCPT ); Sat, 3 Apr 2010 05:11:35 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1Nxtlj-0000xh-RJ; Sat, 03 Apr 2010 03:11:31 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1Nxtle-0005hy-4P; Sat, 03 Apr 2010 05:11:26 +0200 Date: Sat, 3 Apr 2010 05:11:26 +0200 From: Andreas Barth To: Wu Zhangjin , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH v3 1/3] Loongson-2F: Flush the branch target history such as BTB and RAS Message-ID: <20100403031126.GT27216@mails.so.argh.org> References: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> <20100402145401.GS27216@mails.so.argh.org> <20100403015352.GA26168@woodpecker.gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100403015352.GA26168@woodpecker.gentoo.org> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26346 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips * Zhang Le (r0bertz@gentoo.org) [100403 04:20]: > On 16:54 Fri 02 Apr , Andreas Barth wrote: > > * Wu Zhangjin (wuzhangjin@gmail.com) [100313 05:45]: > > > This patch did clear BTB(branch target buffer), forbid RAS(return > > > address stack) via Loongson-2F's 64bit diagnostic register. > > > > Unfortunatly the Loongson 2F here still fails with this patch, > > compiled with the new binutils and both options enabled. > > Which version of binutils exactly? > The patch is in cvs, but latest binutils-2.20.1 still didn't include it. > You need to patch it. Yes, binutils are patched with http://sourceware.org/ml/binutils/2009-11/msg00387.html Andi From manuel.lauss@googlemail.com Sat Apr 3 17:07:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Apr 2010 17:07:09 +0200 (CEST) Received: from mail-bw0-f219.google.com ([209.85.218.219]:65078 "EHLO mail-bw0-f219.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492248Ab0DCPHD (ORCPT ); Sat, 3 Apr 2010 17:07:03 +0200 Received: by bwz19 with SMTP id 19so379803bwz.24 for ; Sat, 03 Apr 2010 08:06:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=LGPA32gkF6u7Ruil7jjWVOgNA6YA0IyP3Iybl3PGrFk=; b=PuW4LrpfZpwrGc61P2pPvgkGAAo6lAJnuTQSU7t3kEGtpXRQjUVqOxgrMgLF6gAx9D thJLCzxk9r0XbucVHcw9E0u8qciFo+ci+ogH+mRx7V3GXor644ViAGYvr3g+7yHZlzgz z+obs4J2CJyn+ARrLhP9Au1uvqtrNs8dtvXqw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=ZSEv+hrKYXBNJ7JlwfRlcO9gQQ6XoEGNq3x/rkI92oIcguldxh00VHKZgxSAFHvGgY D18c3SLlxL2gvxwokDYj+uON8lsApZbf8XvVMSIWvckSKlaf8Kzaai6ZjMnT3rk1eXUX RImax9VgqkBQHXuxGVn//zCRTNgONnC/8BQOg= Received: by 10.204.132.214 with SMTP id c22mr4566294bkt.60.1270307216168; Sat, 03 Apr 2010 08:06:56 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id 14sm4961538bwz.6.2010.04.03.08.06.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 03 Apr 2010 08:06:55 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: db1200: remove custom wait implementation Date: Sat, 3 Apr 2010 17:07:03 +0200 Message-Id: <1270307223-3825-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26347 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips While playing with the out-of-tree MAE driver module, the system would panic after a while in the db1200 custom wait code after wakeup due to a clobbered k0 register being used as target address of a store op. Remove the custom wait implementation and revert back to the Alchemy-recommended implementation already set as default. Signed-off-by: Manuel Lauss --- I've played a few hours worth of video from a SD card now without a hitch; usually the panic would occur after ~10 minutes. Please add this to the 2.6.34 queue, Thanks! arch/mips/alchemy/devboards/db1200/setup.c | 40 ---------------------------- 1 files changed, 0 insertions(+), 40 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index 379536e..be7e92e 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -60,43 +60,6 @@ void __init board_setup(void) wmb(); } -/* use the hexleds to count the number of times the cpu has entered - * wait, the dots to indicate whether the CPU is currently idle or - * active (dots off = sleeping, dots on = working) for cases where - * the number doesn't change for a long(er) period of time. - */ -static void db1200_wait(void) -{ - __asm__(" .set push \n" - " .set mips3 \n" - " .set noreorder \n" - " cache 0x14, 0(%0) \n" - " cache 0x14, 32(%0) \n" - " cache 0x14, 64(%0) \n" - /* dots off: we're about to call wait */ - " lui $26, 0xb980 \n" - " ori $27, $0, 3 \n" - " sb $27, 0x18($26) \n" - " sync \n" - " nop \n" - " wait \n" - " nop \n" - " nop \n" - " nop \n" - " nop \n" - " nop \n" - /* dots on: there's work to do, increment cntr */ - " lui $26, 0xb980 \n" - " sb $0, 0x18($26) \n" - " lui $26, 0xb9c0 \n" - " lb $27, 0($26) \n" - " addiu $27, $27, 1 \n" - " sb $27, 0($26) \n" - " sync \n" - " .set pop \n" - : : "r" (db1200_wait)); -} - static int __init db1200_arch_init(void) { /* GPIO7 is low-level triggered CPLD cascade */ @@ -110,9 +73,6 @@ static int __init db1200_arch_init(void) irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; - if (cpu_wait) - cpu_wait = db1200_wait; - return 0; } arch_initcall(db1200_arch_init); -- 1.7.0.4 From p2@psychaos.be Sat Apr 3 17:43:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 03 Apr 2010 17:43:22 +0200 (CEST) Received: from apfelkorn.psychaos.be ([195.144.77.38]:34397 "EHLO apfelkorn.psychaos.be" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492240Ab0DCPnR (ORCPT ); Sat, 3 Apr 2010 17:43:17 +0200 Received: from p2 by apfelkorn.psychaos.be with local (Exim 4.69) (envelope-from ) id 1Ny5VA-0003sJ-CL; Sat, 03 Apr 2010 18:43:12 +0300 Date: Sat, 3 Apr 2010 18:43:12 +0300 From: Peter 'p2' De Schrijver To: Andreas Barth Cc: David Daney , linux-mips@linux-mips.org Subject: Re: movidis x16 hard lockup using 2.6.33 Message-ID: <20100403154312.GY2437@apfelkorn> References: <20100326184132.GU2437@apfelkorn> <4BAD03A5.9070701@caviumnetworks.com> <20100327230744.GG27216@mails.so.argh.org> <4BB0DB2A.9080405@caviumnetworks.com> <20100402133224.GR27216@mails.so.argh.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100402133224.GR27216@mails.so.argh.org> X-Unexpected-Header: The spanish inquisition ! X-mate: Mate, mann gewohnt sich an alles X-Paddo: Munch, Munch User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26348 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: p2@debian.org Precedence: bulk X-list: linux-mips Hi, > * David Daney (ddaney@caviumnetworks.com) [100329 18:54]: > > [...] > > I need to admit I'm sorry but I can't read enough from the log file. > Serial console output is http://alius.ayous.org/~aba/screenlog.0 > > This kernel is with the NMI-handler but without the "don't reboot" > patch: > Linux version 2.6.34-rc2-dsa-octeon (aba@gabrielli) (gcc version 4.4.3 > (Debian 4.4.3-3) ) #5 SMP Sat Mar 27 10:16:03 UTC 2010 > > and this one has NMI-handler plus the small loop: > Linux version 2.6.34-rc2-dsa-octeon (aba@gabrielli) (gcc version 4.4.3 > (Debian 4.4.3-3) ) #6 SMP Mon Mar 29 22:23:26 UTC 2010 > > > Unfortunatly it looks like we get neither the information nor don't > reboot, but adding the NMU handler changed behaviour from "machine > freezes" to "machine reboots". > http://zobel.ftbfs.de/.x/lucatelli-nmi-watchdog-output.txt Dump of one of those hangs. Most cores seem to be stuck in wait (0xffffffff81100b80), except for core 1 which is in octeon_irq_ciu0_ack (octeon_irq_ciu0_ack). Any insight welcome. Thanks, Peter. From aba@not.so.argh.org Tue Apr 6 21:10:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Apr 2010 21:10:40 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:43795 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492448Ab0DFTKf (ORCPT ); Tue, 6 Apr 2010 21:10:35 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NzEAS-0004wR-M8; Tue, 06 Apr 2010 19:10:32 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1NzEAM-00058w-Nk; Tue, 06 Apr 2010 21:10:26 +0200 Date: Tue, 6 Apr 2010 21:10:26 +0200 From: Andreas Barth To: Wu Zhangjin Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH v3 1/3] Loongson-2F: Flush the branch target history such as BTB and RAS Message-ID: <20100406191026.GD27216@mails.so.argh.org> References: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> <20100402145401.GS27216@mails.so.argh.org> <1270258975.23702.18.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1270258975.23702.18.camel@falcon> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26349 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips * Wu Zhangjin (wuzhangjin@gmail.com) [100403 03:50]: > On Fri, 2010-04-02 at 16:54 +0200, Andreas Barth wrote: > > * Wu Zhangjin (wuzhangjin@gmail.com) [100313 05:45]: > > > This patch did clear BTB(branch target buffer), forbid RAS(return > > > address stack) via Loongson-2F's 64bit diagnostic register. > > > > Unfortunatly the Loongson 2F here still fails with this patch, > > compiled with the new binutils and both options enabled. > > > > Testcase: plain debian unstable chroot, build binutils in that chroot. > > > > More ideas, codes, whatever welcome. > This patch is not enough, please use the kernel(>=2.6.32) from > http://dev.lemote.com/code/rt4ls or > http://dev.lemote.com/code/linux-loongson-community The kernel vmlinuz-2.6.33-lemote2f-bfs inside of http://www.anheng.com.cn/loongson/install/loongson2_debian6_20100328.tar.lzma (linked via linux-loongson-community) fails at the same place: touch stamp-picdir if [ x"-fPIC" != x ]; then \ gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic -fPIC ../../libiberty/regex.c -o pic/regex.o; \ else true; fi gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic ../../libiberty/regex.c -o regex.o if [ x"-fPIC" != x ]; then \ gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic -fPIC ../../libiberty/cplus-dem.c -o pic/cplus-dem.o; \ else true; fi Any other kernel I should try? Andi From David.Daney@caviumnetworks.com Tue Apr 6 22:30:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Apr 2010 22:30:11 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17029 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492462Ab0DFUaG (ORCPT ); Tue, 6 Apr 2010 22:30:06 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 06 Apr 2010 13:30:14 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 6 Apr 2010 13:29:54 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 6 Apr 2010 13:29:54 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o36KTqjk012765; Tue, 6 Apr 2010 13:29:52 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o36KTpVv012764; Tue, 6 Apr 2010 13:29:51 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels Date: Tue, 6 Apr 2010 13:29:50 -0700 Message-Id: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 X-OriginalArrivalTime: 06 Apr 2010 20:29:54.0757 (UTC) FILETIME=[EAC68F50:01CAD5C7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26350 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The ebase is relative to CKSEG0 not CAC_BASE. On a 32-bit kernel they are the same thing, for a 64-bit kernel they are not. It happens to kind of work on a 64-bit kernel as they both reference the same physical memory. However since the CPU uses the CKSEG0 base, determining if a J instruction will reach always gives the wrong result unless we use the same number the CPU uses. Signed-off-by: David Daney --- arch/mips/kernel/traps.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 7ce84bb..b122f76 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1706,7 +1706,7 @@ void __init trap_init(void) ebase = (unsigned long) __alloc_bootmem(size, 1 << fls(size), 0); } else { - ebase = CAC_BASE; + ebase = CKSEG0; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); } -- 1.6.6.1 From maria.dickson@yandex.ru Tue Apr 6 22:54:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Apr 2010 22:54:41 +0200 (CEST) Received: from forward5.mail.yandex.net ([77.88.46.21]:47793 "EHLO forward5.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491982Ab0DFUyg (ORCPT ); Tue, 6 Apr 2010 22:54:36 +0200 Received: from web70.yandex.ru (web70.yandex.ru [77.88.46.30]) by forward5.mail.yandex.net (Yandex) with ESMTP id 46D83B6003C; Wed, 7 Apr 2010 00:54:29 +0400 (MSD) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1270587269; bh=cDiq5tvG08XuXt7Jp7+Hd9gyUXWI06yV1FvqNbvv3IM=; h=From:To:Subject:MIME-Version:Message-Id:Date:Content-Type; b=STLAWiTYI4nlQDUzWdzlQczQ2fOCLSIaqbwMhUysGnFXmihqTwZl8n2pBQNlDQHUS hRhbPjDU30LANuIkl+ChTcR4OpU07oh5ZLi8IoIFG90QQuUtVop9y/UI8FrexPJk9H QK2z7OJRA9df9dwLjv+6D7/u0o22hzMAoo0KanSs= Received: from localhost (localhost.localdomain [127.0.0.1]) by web70.yandex.ru (Yandex) with ESMTP id 3728851806D; Wed, 7 Apr 2010 00:54:29 +0400 (MSD) X-Yandex-Spam: 1 X-Yandex-Front: web70.yandex.ru X-Yandex-TimeMark: 1270587269 Received: from [41.214.67.252] ([41.214.67.252]) by mail.yandex.ru with HTTP; Wed, 07 Apr 2010 00:54:27 +0400 From: dickson Maria To: mariadickson24@yahoo.com Subject: Hello My New Friend; MIME-Version: 1.0 Message-Id: <2421270587268@web70.yandex.ru> Date: Wed, 07 Apr 2010 00:54:28 +0400 X-Mailer: Yamail [ http://yandex.ru ] 5.0 Content-Type: multipart/mixed; boundary="----==--bound.243.web70.yandex.ru" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26351 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maria.dickson@yandex.ru Precedence: bulk X-list: linux-mips ------==--bound.243.web70.yandex.ru Content-Transfer-Encoding: 7bit Content-Type: text/plain Hello , How are you doing today, I hope all is fine with you. My name is Maria, I am a widower. I like most types of music. classical, opera, pop, I think would like Gospel song etc. I also like to travel and have holidays and I like to read, I like to watch football, basket, and swiming. but I am not a fanatic, I also like to eat out and have a nice meal at home ( with some wine) I leave a lone, I'm looking for my life partner for longterm that we lead to marriage. I 'm not here to play games and i don't want to meet a man that is not here to play games. I 'm serouly looking for my search partner. I want you to send me mail and tell what you like in a woman. so that i can send you my pictures. Hope to read from sooner. Maria ------==--bound.243.web70.yandex.ru Content-Disposition: attachment; filename="maria(2).JPG" Content-Transfer-Encoding: base64 Content-Type: image/jpeg; name="maria(2).JPG" /9j/4AAQSkZJRgABAQEAYABgAAD/4QAWRXhpZgAASUkqAAgAAAAAAAAAAAD/2wBDAAEBAQEBAQEB AQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQH/ 2wBDAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEBAQEB AQEBAQEBAQEBAQH/wAARCAEsAZADASIAAhEBAxEB/8QAHwAAAQUBAQEBAQEAAAAAAAAAAAECAwQF BgcICQoL/8QAtRAAAgEDAwIEAwUFBAQAAAF9AQIDAAQRBRIhMUEGE1FhByJxFDKBkaEII0KxwRVS 0fAkM2JyggkKFhcYGRolJicoKSo0NTY3ODk6Q0RFRkdISUpTVFVWV1hZWmNkZWZnaGlqc3R1dnd4 eXqDhIWGh4iJipKTlJWWl5iZmqKjpKWmp6ipqrKztLW2t7i5usLDxMXGx8jJytLT1NXW19jZ2uHi 4+Tl5ufo6erx8vP09fb3+Pn6/8QAHwEAAwEBAQEBAQEBAQAAAAAAAAECAwQFBgcICQoL/8QAtREA AgECBAQDBAcFBAQAAQJ3AAECAxEEBSExBhJBUQdhcRMiMoEIFEKRobHBCSMzUvAVYnLRChYkNOEl 8RcYGRomJygpKjU2Nzg5OkNERUZHSElKU1RVVldYWVpjZGVmZ2hpanN0dXZ3eHl6goOEhYaHiImK kpOUlZaXmJmaoqOkpaanqKmqsrO0tba3uLm6wsPExcbHyMnK0tPU1dbX2Nna4uPk5ebn6Onq8vP0 9fb3+Pn6/9oADAMBAAIRAxEAPwD8Xv2ObzzbXxBpQ/5dbwXuOcen8+nSv0Bs9N6/ln/P58fietfl f+x1r3k+N9Pg/wCXfXtH/H/oPfn/AJ9q/YCGH97+P05BP6/oetfE5L/usl10069Oh+i8ZYb6tmkZ fZaVnfpZdG+jf3ejM+HTf3v1/Q/j69exrP8AFem+do3nnH+i3h7noO/Pb8OOma9Ahs/8/wA+f5H8 PajUtN87S9Qg54s/fnp0yAO3v07c16X1by/r/wACPk47r1X5nk/gmHydZ8gH/j6xY/QEHqP0+v1x XtENn/n+fP8AI/h7V4/o/wDoeqadPx/ol4o/Mjjp1Hrj2r6Ihs/8/wA+f5H8PaubC7v1/Q6q+y9F +UTH+x+3/j1WIYSZbfr6noO3fGfX+Xoa6CGz/wA/z5/kfw9qJofJi8/AH2Tj29BjjB+vbr3zXach x9nD5OqahBz/AKV/Zd7zx/k5wPT86NS03zrowf8AP3Z6nYjnBx7n1Hrxnnp0rqLyz8rWtPxn/SrP VLI+uOxP+fxPFGp2eZdPn/6ff8+mcY6dvTms8N0/r+Ycd16r8zz/AMSQm8/s++/5+tH0q9H0/sTg /wD1/wBOw7jwdD52jaeev2W8/P6e/Hv3HtWNrFl/xJtP/wCnX+1LIfUa1nsfb+VdT4Dh/wCJXqMG f+PW8+28fh1yO2e/cd+TRhun9fzHrR2XovyPQIbMmW3/APrj+f8Ank+nGjeWZ822PrZ8cZ4569fT 8T61fhs/8/z5/kfw9q2Lyz/dW/p/xNO/T/HBz9c47V2GBy/ke/6//WqxDZnzff2/zwPU55981sQ2 f+f58/yP4e1WIbP/AD/Pn+R/D2oA8/8Asf73rz+n0/Pv69813EUPnRW/kdfyHrg8f56iqE0Xk3Vx n/l1wPw49P5jn8TXX6bD/otsAfm/P/DqPpz64+YAz4YfN/z/APq5696sQ2f+f58/yP4e1bENmfN9 /b/PA9Tnn3zWhDZ/5/nz/I/h7UHnnH6xZ/6L/wBvn+fTPPfnP1Ar0D4M69/YOvf2Vfz/APEv1Tiz 9f7UGOMZxxj8Oax9Ss/9AuP1wP0//X+fWs/QfIs9Z0e+n/49ra90u9AH/wBf8fxx0qMThv8AP1/r 076Xs32Ybp/X8x9QeMNN+2aXc/uBc/X8R+v5dMjvXn2mw/2x4S8i3/5CGg3hvT6dx/8AW57+4r6B vIYNStT5GbnJx7qcjr0GfT8K8v0eyOj69b+fBm3ObLWOP+YX78ew4HTJPXgZx3XqvzNDuPB8P9mS +fcAfZ9esvX/AJinHrx09f8A9X8p/wDwXs0DXPG37aXwX8K2MH2a3uvgPpf2O8/5hn/I6ePv6Dt1 69TX9Z+j6aT/AKDz9m6/r2PYc4+p9a/BD/gsxr3gD4J/EH4X/E3xHB/aXijxR8N/FHhjSLT7H/aW T4F1rQNe0IZzjw/x45/5Gn00D2rsyyyzdSbSTStd2vseTmP+6w+f6H5//wDBK/8AZ71z4V/tBah4 j1XVba5/tT4b+KNGs9JtLPkf8TrQNeA9Mf8AEj+uPXiv6kNNs/8AiiLfPv05/wCg/nvx9fzr+S// AIJX/GDxj8VP22PtHiO/P9n3Xw38ef2P4etP+QZYf8TrQPfPXJI/H6f14aPZ+d4Nt/8AuF49f+Y/ z+Ht+NennX+9/wDbv+R5uF+z8v8A208/+x+3/j1eb/EjwH4q8YaNbWPhXxxc+Cbi1u/9Mu/7H/tH 7f8A9QXv+I6+1e4fY/b/AMeqx9j9v/Hq5/lfy7+XzOg+GIf2b/jhDYXE9vP8NfFtuBjA/tnw3qfH 0/4S4Z+v5da57WP2Y/GNn4cufEeufDnTftFrkXvh7wnrH9p+JgR/1A8ewHX1x1r9UNHs/JsLf+X+ Ryf6/StiGz/z/Pn+R/D2rjxOT5di1/tGEb5rapvR+7e6tppe2/5pedmOGWKcZNO97tWT00ul3el+ tu+p+C837PfhzxVf6PBrnxNtvhLqNref6GPib8KvGXhvTB1HOueH/Dfr0HP6YP0R+zF+wT4j8H/G 7w/448AfFv8AZ3+Mlx9j1XRT/wAI98YfBup89x/YfiD/AIRHnnpX7AWemwTYguIPtNt8vHrntz+G Dg59O9cxqXwH+EfiTnVfhz4SubnnF3/Y2jabqePX+3OhJ7e/pXk0eDMtw0vreGdndSavs7x6b3vp bX7hYdPCx/2Xsr+ul09Lrbo121Pofw38N/ippul+R4x+BFzrej9Lz+ycanjv14wcEcHofXHPy/8A tsfB/wDZys/hp4e8R6F8MtN+G/xIuviRpll/a114b0bTdT/ssaLr+vf2J/bg/wCKXzx+nPv3Hhv4 Mz+Dzn4c/Eb4tfDfr/onhPx5rP8AZnr/AMgPxAfF3hjp19TzjGa7Dxtpv7Sfirw5b+FZ/jFoni3T 7W8N7/xc34b6N4k1O/8Abt/U9gc4z9BHDRSS00SXT/5EazDFYZ20eyfezt+Xr1sl3+N/Afjfx/4P 8OafYQX1vc6fa2X+h/2To+je/wCPX8+Onfl9e1j/AISrWbi+1zw59puP+gtdnpjtyOTz75I+XHf6 As/hj8VNBuvPn+Ffw31L/n8u/hl4k1jwR+P9h+ID/wAIx19+pxmvm/48fDfxj4rurf8A4pX42fDf T/7H+xXh8PaPo+paYNU64/4p8+ufT6cU8RhrvTXmta39623Tt17fNrH4d2und2v7ul3brbzR4v4q +Nt98Dfs99Y+I7a5+1Xml2X9k6t/xMe/8zj88/hY+P37ZkHxs+Gnh/wr4H8K2vgDWBZmx1jVrW88 G/8AFXf9B3Wf+Kf+G3hDH8sZx2r5em/ZR+2a1cT/APCztN1LULq9Fl/ZPjc6zpupnt/bWPr2/EV6 DZ/s3+P/AA3pdvY6Voem+JLj/n70nWP7T0z+yz6+55/mK9KP1vC4Rcrvf3VZ92t0tEebh8Pl9fMl UipJq3dLm9166W/T8D2jwJpvwq8VXWnwa5Y+G7bT7vWNKsrzVtW8N/8ACSfYNM/5AP8AyAvD/hv/ AISf/kY+P+KT46eteD/EL4M/s5+PPGWsQaV8Jbm20f8A5k+7u9H/AOEb1Pxb/wAx/P8A1L5/4RzH ig/n1rQ+IXhv4i/Da/t7/StD8SaJ4euib77Xd2esY0/VdC/sDXv/AFI/TNeH/wBveOPDdro9xP8A Zv7P0u8+3aPaWn4HI5zzk/44rzo/XNO2nbb89j38S8U6clCULKLUPeT0StHS++qtv37HP69+wT8J NfFxPBY+LfDf+mCy/wBE/wCJj+R6cf5Ffph8DfgnofwZ8EeH/hlon/IO8Ln7D9s/5/8APXWj27cH r1r5++GPxO1zXvF3hiCD+29NuPtn228+yc/YPXrz19e36fbPgP8AtzUh59xY239n2o+xG7GB/aGB 7YH4cdTxyK9BYiVle9+v9cx8hgKWPo1ZLHy5oSm7JPXW1tvK/Xy6HYeG/Df9sa9YQeRn7VeY49c/ j9CTx7A5r9QNHhg03S9OsPI/49bPr68cg9z7H16etfF/wks4LLxHb308B+z2vXP5+ufbjjrxzX2B D4k0q8l8jz/yGT078evr1/n52I2+X/yR9EaE03+T/T+QAPqSe1c/efvuvb+vr+n9c11Hk+b+Hv8A 56Z9uv5Y80P+T/T+YIHqCO9YHQef3kPb6f8A6yf5DH171y+pWfv9M/1/Qcex969Qms/8/wAuf5n8 PauX1KzPm5/xP6jr/n04AP8AN3/Zu8S/2D4j8Hzz8/2V4kGi3g+pGgegxnn/ADzX9BGmweda28/Q fY+n/wBf+nXv2FfzPeD7z7HrOsWPb7Z/bX8vr7gn8Omcf0lfCXWIPEngPwvrmf8AkKaPpd739T05 x1B6df5/IZFK9XGJvVxXKr72cXZJeW9vmtT9i46wslhsHinF6cvN90N9eytrpvZnf2dn/n888/n+ hxWxDZ/5/nz/ACP4e1EMP/6/6/4n8BXm3xC8SX2mnT7Gxvvs1x/06f4npwP/AK9fR4j4Y/4V+aPz U8416b+x5dQ8iD7ULW8+xex/D8f8MZr1jwr8QrHU7W3/ALV+zW1xdWf/AB92h59Rnjk9Pb0FfH/i Sa+h1W5n8+5/0qzI6/8A68Z+nGfy7jwfMJtGtxg5tbz7F0/H69Pb8RXzmGxP+2d/69P+D69PV+rL 6mu6tr6NW/Fdv8z7YhvLExf6/vzwffGO3Xt07gjitCH7BeQ3EEE9tc4744POPbHX69B1r5fhvJ/+ e4P+Gef6Z4HXIFdBo+pT2cong/MYGfr64/rivT+s+f8AX/gJzfVvL+v/AAI+gNYi/wBF0e+H/Lte aX19+f6flS6xZ/8AEruJ+v2UC+x69eO9c9o+vf29oOoaVPP/AMTC0s/fHH5EdOe5z0716T5MF5Yd vs91ZZ498enH1+n4DfDtK13b+pHGefalZ/6BqEBx/ousfbR0yP8AiS479v8AiR96sfD2HN1qFjxm 6s+nTpjBzgAjHU5PIzWh5IltOBj7Vo+l3o9caFk49Of7c4yOw6Cq/gP9z4jt7f8A5+v7U/p+P0/L uK6sLs/T9Wege4WcPnWtvcenOSew9hjsKv3lmPstvP2F5357fz9eOf1qzpsOLUdTj/Qsdvx55PHP Tp3Nef8AxU+MHg74VaNp83iq+trb+1LzS7Ky+19uxx/X69q6m0t2l6tL8zgSk3aN7vtudxDD/wDr /r/ifwFWIbP/AD/Pn+R/D2r8x/BP/BUT4L+KvG+s+Dr6x1Lw39lvPsVnd3fP2/P+R/8AX5r6A8bf tmfB3wf4St/GM/irTtS0+6sj/Y/9k6x/x/6p/wBAX+3OP1rm+s/3fwl/l5r7zsWGxTteSV7fjbTd 99eyPpi8s/8AT/0/p0/Lt64HSuo0eHzrD3+nHf1J9B+WeO353/Af9urwd8Zte/sPVYLfw3rGvXv2 Hwfm8/tI69pXIzj/AJl/gZ4+hr9IdC8j7LceR/z+d/8APTGfb8cUsN19P1DEp4Xo7/rpbe+19bNW vqy/DD/+v+v+J/AVofY/b/x6rEMP/wCv+v8AifwFWIYf3X4fXg5/T9R1rrPKM+8h/wBFuP17fn/n PbtXLww//r/r/ifwFegcTWvfP+fp6e2PpXLww/8A6/6/4n8BQdCfVP5p/wCR9EfDHWP7S0b+yp7g f2hpfXnP/ErI/wDrcnsOtdBrMNlZy/bb6e2tra14/wBL5xz049/wr5vs/Phl8+Ce5trjr/ol4dM/ Dv8AQcgc+1aBs4Lybz7/AO03Nx/z96tef2lqefp79scds1yfVV3X4/5mn1nz/r/wE+gIviF4czBb 6V/xMtRP+hWf2TH9l8jP0A6Y4/Sv5h/+DhbXtVh8UfAfSp4NNurbxR4b1S9vLv7H/wATOw/4QXWv +QLof/Uuf8Vxgk46V/Qho9n/AMTTTz/0+fp/Lt64PTtX8+//AAcRWg/t/wDZHv8A/Rra3utH+Mn/ ALyL6H8u/BrowdBf2lgkm05WTfmlGz+V/wADkeIWJstGlvfSy9bb9v06/M//AARt0cWfxv8AD99p XxG8Falb6p4b8U/2x4I+xf2b45sNU/8Adg4/xr+xDQbP/iiLeb+Z7Y1/H19/w4Nfx/8A/BMbxJqu vftffB6GDSfBQ8H6X4D8U+GLPxvaeD9G8Nan4t1T/hCzr2u9v+En8QeuD+Q6j+yjQYRN4Dt+eo47 fT/PGM172Zf7yvVflE8483+x+3/j1WIbM+b7+3+eB6nPPvmtjyPf9f8A61bFnpv7309+f646/wBP pXmAdBZ2Zhit4OPfjsenbn/PA7aEMP8A+v8Ar/ifwFaEMP8A+v8Ar/ifwFWIYf8A9f8AX/E/gK6A LFnZ/wCfzzz+f6HFdhZ2f+fzzz+f6HFZ9nZ/5/PPP5/ocV2FnD2+v/1zn+Yx/SgDQs7OD/6/J47/ AM+4zn8q6iz03r+Wf8/nx+J61Xs4fOi6njt69D+fp+NdRZw9vr/9c5/mMf0oOcIdNg9+5/oe/wCX p71of2P/AJz/APZVsQw//r/r/ifwFbEMP/6/6/4n8BQTyx/lj9y/rovuPP8AUvAfh3XovI1zQ9E1 u3/6i1n/AGkfbt/ntXk+pfsofBbU5fPg8HW2iXHH+l+HrzWfDZ4x/wBC/wBD+v8AX6ohs/8AP8+f 5H8ParENn/n+fP8AI/h7V0/WHa2tu3T7uYf1eKd1ZPvpf7+U/P8A8Vfsf/2l/wAgP4qfEDTf+nTV ho3iTTO/T/hIPbt365HWvB9f/Yt8cf6R5/8Awq7xtb5/5i2jnw3qnTj/AKG7nj8Bmv2A+x+3/j1Z 82mds/j+XP8ATr9O9cxz+wl/O/8AwKX+Z+T/AMPf2J4NMu/7V1XQ9N8JC1/5hOlXn9pfb/8AuOY9 h17k9RXu83wTns4vIsf9GtrXn7Jnv6duwH4e1fcM2mds/j+XP9Ov071n/wBmf7X+fzo+s9n+P/2w Yehf4pPTW711tbz10X5+nzP4V+Hs+m2GZ8/aPwxz7dOvbsMcYwK2JvDc8Mpng68Aj0znj0/Ucdq9 4m0ztn8fy5/p1+neq82j9T/n0z/hz649KDpPJ7O8vrP8O3HTvnge44OO+a34dSgl6HH6/wCfX6H2 52b3QYMfj/P9efy9e9V/7H/zn/7KucCvNDB5X0/Drzzjj074rn7yz7/Qfyxz+WfxOK6j7H7f+PVX ms/8/wAuf5n8Pag6D/LGhxZ+KNPnGR/aln9i9O+P5/h+FfvT+xb4k/tj4Q6PY3H+v0G81TReP1PP 19fzr8F9em+xy6ffZ/49dY+29BjOewxg+uCMnnjAr9cP+Ce/iQzS+MPDc/X/AIletWZzj69eP+gG fUcV+XZLiZe3wTb3ir2Vr6RVn3111W/zZ/TPHOXKtkuKajbls4q69yzi9dHa1nZa6M/VCDv+P9K+ Z/Hem31n4juPtAxb3X+m2efyz6Y4/rX1BDD/APr/AK/4n8BXm/xO0GfUtPF9B9m/4ldnzwQP1J/H OK+1xPX+v5T8Bw1flSi9bJLW+lrd+2nztrbb4/8AGEP/ACD58ellj8z6fpWx8PZvOi1CAD3/AK9D xj9D35zSeKoPO0a4zj/RcXoHvjtxj2H6+h5jwHMIdet4B/y9WfX+Xb/H9BXzf/Mb/XY+lXvYLTX0 169bH0BB3/H+lbEHf8f6Vnwd/wAf6VsQd/x/pXoHjnYeD7z7J4k0/JP2fVB9ivP6ZHrnqfrXsHhv WJobr+w7/wBfsVld8n9fX8ep714PDN9jutPuP+fW8A7fT/OP/wBfT+MJf7N8R3E8Gfs91/pvBPuf w/DgjHtXQZ4n+v8AyU9Z8nyZbeDr/pnimy9Of+Q7/wC4P/OMVj6P/ofiPT5/+nz0/wA/zIHTkVX0 fxJBrH2mCf8A4+LW80u96D/sA67jPp/9buaTUv8AQ5TPjP2XgfXjGMA++fT9a9XCvrfovz0/TQ5s LfW/f8LaX/A+gNY8SaV4P0DxB4k1y+ttN0fQf9NvLsfj3HTnjHf9D/Kh/wAFCP2orj4qfGTWP+EA 8f8AiS58D3WjaXZXvhPxDZ/2bpmg6poXUaHn0/DrjjnH6Qf8FCP2zPCt54d8QfBbwPq2J8aUfHmr XdmP7MsP7Cxr39i+o8Rf8gP0r+df4qfELVfiF4juNcv7DTba4tbP7Ef7IwTz0x17fU89OtH+8YpL WKS00stEl2tfbTS1zow8fq7eJtdO6aetrteXp5X6aHD/ANparD9ovvt1z9ouv9N/4/OueO/4/wA+ laF5428R3ug2+h32ual/Y9refbf7JN5/xLPr6+g6n144rn55oIbS386Af6V649/5f0wOlV7LQdc1 6XyLGxufp1xg54+nv6YxxXoTdOEb1HGMet7LTTv8rfI6IRqVZJU4ynJ2aSTbd7Wsui0XR9LLt9If s3/Hi++A/jzT/GP9h23i7T9L/wCYTd5/TPb0/EGv6IP2Rf8AgrF4H+J3im48HfGLStE+G9x/Y/8A xJ/ERvB/wjN/qhP/ABPdFHYfngn6V/L/AAfDfxlzBBpOpe3tj8x2/wAeasTaD4j8Ny+ffaVqWmk9 R/zDP6egxnt7Djy3XwDly4WtBzbs488b30TVr9/nqei8tx8sLKWIoVNdYtwl1tvdJNapaN6N9Gf6 DOg6xpXiTRtP8R6HfW2t6Pqln9t0fVrT/l/0vofyBz1z+Qrfhh/e/j9OQT+v6HrX4X/8Ehf2rofF Xg24+BHirW7b/hIPC95ql74btLu8/wCZX5x/P2561+7EHf8AH+ld589icN9Vt0emi6t9PXbT9Ahh /wD1/wBf8T+Arjx/rrj/AD2NegQd/wAf6Vw837m6uIP+n3/Pb/8AXj8+g58Lu/X9GaFn2/4FWxB3 /H+lY9n2/wCBV0EHf8f6UEF7TP8Aj/0//r8P/oJr8Qf+C/Hw31zxtf8A7I9j4d0PUvEniDXbz4ya Lo+k6Tef8xT/AIoHXsfp2+nAr9x7L/XW/wD1+/1Ffnx/wV602+03wb8F/ippM/8ApHwl1jx5rV5a Y/4//C+u/wBgaB460X/wnP7cHX/oWPfCwrSzXAuX929/Snvfvt6nOfl//wAE2f2S/FPwx+Pvw38f +OPEdzqWseF9H1XRbPSbS8/4lmgHXtF1/wD4k2Pbnp7H0r+s/wAOf8k//wC33+gr8N/gb4w8Hab4 k+B9hpV9bXP/AAmWsap9ju/tn9pfb/8AiS6+PXt4c0P6/h1/cnwn/wAiEf8Ar8/pXo51/va/w/5H Phul/K9/+3d7mP5P73/Oev1x17/piuw02H0/H/65/Pp9R6Vx8Hf8f6V2Gmfxf59a88DqIYf/ANf9 f8T+AqxDD/8Ar/r/AIn8BRB3/H+laEHf8f6V0AbFn2/4FXYWcPb6/wD1zn+Yx/SuXs4e31/+uc/z GP6V2Fn2/wCBUAdBZw9vr/8AXOf5jH9K7Czh7fX/AOuc/wAxj+lc/Z9v+BV0Fn2/4FQB0EMP/wCv +v8AifwFbEHf8f6Vn2fb/gVbEHf8f6UAWK0IO/4/0qvDD/8Ar/r/AIn8BWhXOAeR7/r/APWqvVii ug5zPn7fh/Wq/ke/6/8A1q0Kr1zgV5of8n+n8wQPUEd6rzWf+f5c/wAz+HtWhRXQBz81n/n+XP8A M/h7VjzWf+f5c/zP4e1dhP2/D+tZ80P+T/T+YIHqCO9c4HLzQ/5P9P5ggeoI71jzQ/5P9P5ggeoI 712E0P8Ak/0/mCB6gjvWPND/AJP9P5ggeoI70Af5U+sG41i11Dzut1Z8Z6Z7fy+vf0z9ofsOeNf7 M+K3h/7RN/yNGkfYiD1HXXsf+UPHT8K+PvIPm3EH/Pr6YP6dR7Z/Pmuh+CfiT/hD/G/h/VfP/wBH 8L+MdLN7/wBgoa11Bxj6ce3vX4plWJXPC2jUortazit9Fv66n9pcUYH22AqUUn/tdOTSS+HSL1a2 fm0teup/URDN/wDq/p/iPxFaIgt5ovs8/Ju+Og/AdD269OD+FcdoN4L3S9Pmgzm6s/8AAc+nQ88/ lXYQzf8A6v6f4j8RX6xT1pwvreEfO+iP5MrwdGvVpvV05yTTWzvbp20/I+N/FWgmzuvEGh+v+hZz k855/L+ua+f9BvBZ6zYT8f8AH5/pgJxxn0P+1jjjHfrx9kfFTTILPXre+x/yFLP/AEz8eO/4/lzX xtrEP2LWdQgHH2W8xz1xz1HTuc9M59q+dzC31tWt8S2t/c7HvZbiLqz1TVnfb8W+9+h9Ywd/x/pW xB3/AB/pXL6PefbNL0++z/x9Wf4449Pbr9PwPUQd/wAf6V2R2XovyON3u779Se8/49R9D/I12Pir /TNK8L6sP+XuzNicgf1/D/Oc8uYTND5Hbt+Pvkfr2x65rp/ON54Dt/8An40vWDn3PXHGfTGMevSm I4D7ZPpt/wDuDn7Vo+qY568/TPYntzzXj/7cn7UWk/A3wHbTwC6/4Sjx5Z6p/wAIf/nj69MZ9q9Y 1LBl0+fP/L51/l/nn/H8J/8AgpBqWreJPjJbwf2qLnR/BvgPwvotnaXdngWGqf5+vtnpV4V2b11v +S/TQ1wvX0/U+D/HnxC8R+PNe1DVfEd9/aVxc3mqXtn9rs/+g9j1P69unSvP9Nhg83z5/s2B/pn+ cdPrx6UQy5+0Tzj7T19Oueo7H27frWNe+f5X7jHtnr7/AK/r04r6PD8qXNKySWsnZWXu31e3zMuV z92K5m9la+r8tTofCujz+MNZ/fwfabfPS0/D+mD/APXr9cPgD+z3pWsaNb/6CftHF91/l7e3vzXz P+xD8JbDxV4p0/7ffW2Lo/zz6Y9PX8q/pg+HvwU0rw3pdvPb/wCk/ZbP/j77Z/PP4Hrz2Oa/J/EX iSeF/wBkwMnzWWsb7u3Vf0z9o8N+GoTksxx0FKKSaU4q1vd1ab09F3Pgez+AMEP7iDSrUn/ryz6H +XTp+Wc8/wCKv2dbHWLXULGfSrb/AEqz6dvT1/Tp+GMfpxPrHgbTbowX19bW3pd/8w3j8j16+3Xk 4qzNoOlawP7Q0qe21K3P/L3aD055+o6jt39D+QYbE53hrY2VWpytqVnNx0vFp779/Va2Z+2YqlkW Lp/VPYU17nK2opatRSe3db+e6P5jvEng/wAVfsr/ABf8PeMfDk+pW1v/AGx/bWj3dpnj+wv+YLz0 xwMcehHNf2YfA3xh/wALC+Enw/8AGP8ApJ/t7w3pV7e/bLP+zNTsM9Qc+nfrntnv+F/7Znwx0rWf CVhPfWNt9n0HxJpmtXv2u8/s3/iV6Fn+3eg/TAAyfYH9yPgPeaHefCD4bzeHP+QP/wAIfpf2P9Px P069eM1/Q3BWbTzTLI18WnJrljHr0jrd3d9fX8j+VvEbKMNl2ZOhh7Wd2tdVqnZaWWm6S7HtEHf8 f6VxGp/8hS4+p/lXcQ/6kfQ/yrjte/c6pn/pz475Pf3x9Rg+np9mfn+F3fr+jCDv+P8ASugg7/j/ AErl7Pt/wKughm//AFf0/wAR+IoIOgg7/j/Svhf/AIK6QTnwv8B/I1a50S4uvHnijRftdpxzrvgr X/zz/YeM4+8QCc19wQzfuvw+nAz+n6npXxv/AMFYv33gj4Dnj7R/wvj7Fjp/zRf4u/05549smvOx DlHHYBxvpa9r6/w/Tpp966Btg79V39T8Z/2D9S13Qf2m/h/8OfFeuanqdx8OfEv9i+Dzd2XP/CBj wWf7Czxj9O4+lf18eFZv+KIuIP8Ap9PPfHH4dK/kP8H6aPB/x9+E/wAd9KsNS1vWPB2saXZeJPD/ AIezqep694XH/Id/sPQz/wAzF4Tz/wAJRk8/lgf1g/CXxVofjb4VW/jHwrq1trfh/X/+J1o+q2n/ ACDL/S/+JD7jp+HoSMCvfzCv7f6m7a7ST3932e9rqzaX9PTBJYhK2kU1t30Sf4Lt/nrwd/x/pXQW c3f6/wD1xj+Zz/SuX8/2/T/69aEM3/6v6f4j8RXCI9Ihm/8A1f0/xH4itiGb97+P15JP6/oOlcPD N+6/D6cDP6fqelbEN5/n+fH8h+PvXQc56Rps3p+P/wBcfn0+g9a7iz7f8Cry/Tbz2+uPz/x6+49q 7jTbz2+uPz/x6+49qAPQLPt/wKuos+3/AAKuX02b0/H/AOuPz6fQetdRZ9v+BVzgdBB3/H+lbEHf 8f6Vjwd/x/pWxB3/AB/pQBoQd/x/pWhB3/H+lZ9WK6ANCq9FFAFeiiiuc5woooroArzQ/wCT/T+Y IHqCO9Z80P8Ak/0/mCB6gjvWhVeucDPmh/yf6fzBA9QR3rHn7fh/Wtift+H9az5+34f1oA/yn5v+ Prvm6/8A1jv1zx09Tnk1y9nP9j16fj/j6s9LvTnp9Dznn8McYFdBDe/bLDT5+nr06559f6/SuX1j 91f6NPwcXn2LBGD0x6ZHtx6/SvwDLJcmNjhmtE1K762cd3e+vk33R/eOYwVbBKurO65YpK6TlbRJ aJar/Pa39MH7PfiqDxh8JfB+ufaObrR9L+2Yz3+ntz0PrivcJtSgs4ri4vp/stva/wDL5z/PPf6H Ffmf+xN8ToNN+Bmo2M/+kz+F9Y1Sys7TjAOu4170z11zr+ozXrGpeMdc8Sy/8TW+9/smP+JZn1z6 8djnPpX61hcxSwkYpX2jpra+n4WP5P4jy9UM8xtC3Lz3m1rZX5ZL01b+7seoeNvFUHiTWbeex/5B 9rZfYrPOBg4z+vHH9enzP48h8nXvP/5+rP6fn75zxxn88+kQzf8A6v6f4j8RXD/EiETWmj33/Pre fYvw/Dv0J6jr0615uId3fz/DWxyYWP1WSS6uy09NHf1Xy/H1D4b3n2zw5b/vzi1vBZfjnI5Pr7dB k/T1CGb/APV/T/EfiK+f/hLqWItYsRjJBvbPrn8enGM8CvcIZv8A9X9P8R+Irpw2I/2Tpe9rW16J bP8A4f8AFLE2WJja6X6vlt311/pHUw/6kfQ/yrf8N/6ZYeMNKnH/AE+/zwPw6ZzXHw3g8r29v88H 1GOffNdR4Vm/4qO3Ag/0fXtH4u/5dv8AqCZ/LtitjI4fWONLuJzyLX/Teo6YOM8evHHtg9a/G/8A 4KTeD/EdnLo/iOxsbb/hFvtv+mXef+Jnf6rjPPp1AHrzX7j6loMGpWBgsf8AkIE6nZXlpxx7df8A PpX54ft4fD6+8Sfs5eIL6e++zXHhez8L/EGztLvj7eNCH9gnRfx/tw8dOSKuFli4tL3U09nZq8Pz 7meG6f1/Mfzf+d5MtxBj/j0vM/ZPTP49vTHfvX3h/wAE8vhB4P8AjL8X9ZsPGNjpupad4Y8BaprX 2TVz/aWl/wBp/wBtaAecHGP+EdGt9c9PUAj5H8N+A/FXiq/1CDSrC5uf7L0fVNavLS0P/Ez/ALLB 9/5dh79frn9i281z4V+N7j4xT2OpXPw3tbTVNF+JFpZ5/tP/AIRfXc51rnOc8du34DuzWeJrZZi5 4VpSjG6tdP3VG+q8t356+f0nC9PDUs9wlXMVfAyajZ6rXlte+m7Wvrufqf8AD79l3S/hB8ffD8Pg /SrnTtH1S81S8vLS8JP9n6p0UH2wMcHgcDuK/ci8m/sHwlbwWOlfabj7H/U59z0x+favzm8N/Ejw 5428UeH73w5rlz4k+y/6b9ru/wC2f+Y7/wBjB/X2I9D+qXw9vNJ1/QbeC++zHULWzP8Ax98D2/xz 0yfTr/NWa4jF5jjmqj5XGXK3L+60nvq3fs1qz+osHhsHh8JF4FJQmvsq6UXZKyWr3t22+f5O/Ej4 tfFS817WPBuq+B9N0TR7Wy/tqz1e740y/wCc/wBi6H/1MXHt6/XuPDesT+D/AIc6hrkEFzbelpz3 OOB/LtX1T8VPB/hXR9Zt9V/0a5uP+fT8j9c5556dfWuf8baNpWseDbnSvP0S2FrybT+19G9ep+ud vtntkY82tia7cMI2nTVubkbd4rlb++1nv6ndRyujaWJ+tt1HFpR2bbUdNddHbWy6WurH53eD/FXg f4qePPA+q/25qWt3GveMPsVmLv8A5FnXh/zHdFzn/qOaH/d7fWv3Z8N+G9K8K6Xb6Hodjbabo9r/ AMednan3H8sHA/lX5P8Ag/4M+FdN1nwvrn2H/iX2viTS720tOn2D/idHjQ/88+uM1+vEM3/6v6f4 j8RX79wJVw6ytLDp3STaa3klHqlZ7et1938xeK1DEUM0wzqzTb7b6uHVb3Xc0K5jxJ/x9W//AF5f 0rp4Zv8A9X9P8R+Irl/FX+q0+fofTuen8/fP5cn9APy3D7/P9YmfDN/+r+n+I/EVsQzf/q/p/iPx FcvDN/8Aq/p/iPxFbEM3/wCr+n+I/EUG52EM37r8PpwM/p+p6V8cf8FUIbib4VfA+fz7m5+y/HjS z74HwX+Lp/mOeOua+t7Obv8AX/64x/M5/pXxv/wVoOq6l+yr4H1XwdOf+Eg0v42eA7yz/wBD/tL/ AJkvx8NdPXp/yHD7CuKtb65gL91+dLfytcD89/gPDB/wuT4b54/4rDSzzz/zGsd+vr647V+zGj6P 44/ZvsPFHjH4ZaHc+Lfgvr2sap4o+JHwy0r/AJGbwlqn/Eg/t7xp8K9D/wDU38Lf+EFX4QfsffEj SvHnjf4X65BPpn9oWvjzS9F1i0tLz/jw1Qa0uMeo9gfXNf1T+A4YJvCWsd/Tr/8AW+tduI5orqtL 9V3/AOB+B5+F+z8v/bTj/B/jDw5488OaP4x8Ha5pviXwtr1n9u0fVtJvP+JZf4x7dfy9Aea7CGb/ APV/T/EfiK+LvFXgPxj8E/Ees/FX4H6V/bfh/Xrz+2vip8EbT/kF69x/xPfGnwr5/wCKf+In/UrH nxpyB/xXnT6R+G/xI8HfFTwvp/ivwRqv9paPdf6F203U7DVQf+J7ouuaHx/wj/iLt/wi38+wdB7B Zzd/r/8AXGP5nP8AStiGb/8AV/T/ABH4iuPhm/8A1f0/xH4itiGb/wDV/T/EfiK6DnPQLObv9f8A 64x/M5/pXYabee31x+f+PX3HtXl9nef5/PPH5/oM11Gm3nt9cfn/AI9fce1AHuGj3nr/AJ+n68fp XoFnN3+v/wBcY/mc/wBK8f0e89f8/T9eP0r0jTZvT8f/AK4/Pp9B61zgegQd/wAf6VoQd/x/pXPw zf8A6v6f4j8RWxDN/wDq/p/iPxFAGx5/t+n/ANetCGb/APV/T/EfiKx4Zv8A9X9P8R+IrQhm/wD1 f0/xH4igDQqvVfz/AG/T/wCvVfz/AG/T/wCvQBYo8/2/T/69V/P9v0/+vVeab/J/p/IAH1JPag5z Q8/2/T/69Hn+36f/AF6rwzf/AKv6f4j8RR5/t+n/ANegAqvR5/t+n/16r+f7fp/9eugAn7fh/Wse ft+H9a0Jpv8AJ/p/IAH1JPas+ft+H9aAP8m/wTefbfDtuAPb39OD/UdOnWrHiT9/pdxz/pFr/pvJ /wAfc9eAOua4f4b3nkw6hYzn/Sf8/XP9cV6RMBNa3FuO3J5PHOPX+YPT+6Tn8BzaP1PO0knG/K3Z W1tFb2WumlkvRM/uLh3Gf2pw+5XTlBJp7t8ri3v10v2trufcH7Fuo/2xqnjjwPBcf6RqejaX4n0f nP8AyAc//Lz9SMV9nwzCEjzxm5tOff5uP85/Dmvy5/ZA8YDw18Wvh/PPP9m+1XmqeGbz0Gef0zzk +nSv2P8Aipo+k6Zf22uWM9sP7eP+mWnbPpgdMnk889Mivt8m/wB2s97q/V7an4Px3S9lnMcW46Y1 Rg+iWkVda2uu9urVzn7Obv8AX/64x/M5/pWP4wh+2eHNQJ6Wv+m/XHHT/PPU0Wd5/n888fn+gzWw f9LtbiDj/SrP7Ef/AK358kZ5+px0Yjf5/qz46O69V+Z5v8MdS8nxPbwf8/Vn9i/TH0Ocf/Xr6Yhm /e/j9eST+v6DpXxfoN5/Zms6fP3tdYP2z1A/zj8cV9kQd/x/pRlmz9WaZhsvX/5E6CGb/wDV/T/E fiK2LPXr7Tbrw/B/o39n6XrGPw4785+vp+Vc/B3/AB/pVe87/wDAa7ziPeNH1Kx03xvfwX3TVB/o d3yPTGPpjp1/Suf8eeD9L16w/sPXLG21LR7q88UeGNY0m7sx/wAgvXca9g9Ppknp3rlvEmsWOpXO nTwfaTc/2Ppf2z/Q/wDmKcep/HB5ApbPxt/x8aHfX32n/iceF72zvPtmdT/6AP8APrj9KuOIwsml yu7aWnV6eW13/VyI4fFLlk3FRVm+1lZ9Xbbzt8j5P+G/7HGh/Df406dqvg6D7No+qWeq6LeWf2PJ /wCwJ/2Lvrnr69aP2wPgPcfB/wCDev8AjHwPpX/Em1TR/wDhCvHmk2n9jf2ZYaZ/xP8A+wta4PA/ 4SPXOfX/AIpc16h8Zv2zPgR+z3r9vB4q8VW+peMNLvM/8In4e/4mep+39uYx/wAI/kdO3H4V+a/x 5/4KS2X7Tmn/APCA/YLfwT4WPiU61/Zd2G/tPX9oB0Ma3rvTIBG4DoMZHz5rpxNV0MDJKM3zrXRt 2kktXa2t1e/3dD2MppVsdjqCc4RhCUOWMpJfC4PRdNNVpZnuH7Luvf8ACNxeH76+/wCPe6s9KsfT 9Ppx2P8AX9ifCviT7ZYW89hObbuRjnHbv3z7/rX4TfCvUrHUtBGlef8AZtRtf+XT8vU9Bg4/P2r6 I8H/AB+8VfCq6/srxHBc6l4f/wCXPVh/y4Y/TH5cZr+es/y+dbGOeG5qbUm3o43u4vbTy2vZs/qD KcQqGApwi1NqMI6NNr3Vd2V/VX30P0Y8Sanqs3xB0+C+sbnUvC9rxeat/wA+GqfX0xjHfjAryf8A aE0Gw03QbnXND8f+GvEtx9s0uyvfCek/2zpup/8AE9/7GD19P616R8Pfid4O+IWg3N9oeuW32i5/ 4/LP7Z7/AIn2H5da+J/2rvHdh8FPhz4o8cG//trX7oix8N6V9sPGqHjJxz6ds9hyRl5JR9tKGFlg v9snJR5mm4tScU3fzbvvb8AzPF/U8FPGLGNKEW+VLqrOz2s9+ltNNTj/ABt+2ZY/Cr4ofBf4V332 a5tv+Ek8L3nxIzeYOg+FvTg4/wCpo6+tf0QQy+dF58H/AB73WevT8SPqQOc+lf54+peKtc8S69qH iPXL651LWNUvDfXd3edf7U65/hwO/Q4I61/YB/wTT/bN8KftFfBvw/4H1XVbW1+MHw50fS9F8SaT d3n/ABM9f0zQv+QF400L0x3B684Oa/oTI8n/ALGyuNLltOSUk4pacyjp+v566n8s8W5xic7xjrNp qD5byd7RVldaPS2t0r33P1Ihm/8A1f0/xH4isfxV/wAeFv8A9fg/rViGb/8AV/T/ABH4isjXv+QV cfQ/yFe3HZei/I+QOWhm/wD1f0/xH4iughm//V/T/EfiK4eGb/8AV/T/ABH4iugs5u/1/wDrjH8z n+lYHQdxZzd/r/8AXGP5nP8ASvh//gsxZ6V/wwBc6rP/AMe+hePPhfe9f+g6f7B68f8AQd6Yr7Is 5u/1/wDrjH8zn+lfH/8AwWAsv7Y/4Jp/EjyMf6LefBv/ANWd4B0D378Hn/E8WJlOOJwUo35uX3dL 3aVPl/H8b/KopNpO9r626Lq/X+tbn8s/7K/hXxH4b/al/Zn8R3407+x7r48fC+xzpP8Ay4f8VpoH 6eo71/oIfD2bPg3xB/jjnt+nTv8Ajmv4L/2VvjBY6v8AFr4H+HPEeh6bbeILX4wfBqxs9WtD/Zpv /wCwvidoHb/JH8v7wPht/wAij4i/4F/IVdCtj6039fXJTu+XZXSta3W2nRefVhiMPhYpfVlZ2vK7 6e69276vrZpfMz5+34f1r5f8efB/xHo/inUfi38CL7TfDfxIuv8AkcPD13n/AIQf4taXnP8AYnjg 5/4p/wARH/oafUV9MT9vw/rVevSOU4b4P/GbQ/ipYahBBY6l4S8YeF7z+xfHnw98Q/8AIzeEtT7/ ANuc8eHf+hI8U9fGle4wzf8A6v6f4j8RXyv8VPhLfeJNU0/4jfDnVbbwT8aPC9l9i0bxD9j/AOJX 4t0vr/whfjjQ/wDmP+Hc+n/Il557V1Hwf+Nlj8SP7Q8Oa5pVz4J+KHhfnxh8PdWvP+JnYc/8hrQ/ +hg8O85/4SnHJ4FAH0xDN/8Aq/p/iPxFdBZ3n+fzzx+f6DNcPDN/+r+n+I/EVoWd5/n888fn+gzQ B7ho956/5+n68fpXrGj3nr/n6frx+lfO+j3nr/n6frx+lesaDeDyu3445P8ATj3yMZoA9vs5gYu3 r6fQ4/yT9Qa2YZv/ANX9P8R+Irh9NvPb64/P/Hr7j2rqIZv/ANX9P8R+IoOc6CGb/wDV/T/EfiK0 IZv/ANX9P8R+Irn4Zv8A9X9P8R+IrQhm/wD1f0/xH4igDQ8/2/T/AOvVfz/b9P8A69V/P9v0/wDr 1X8/2/T/AOvQBoef7fp/9eq/n+36f/Xqv5/t+n/16r+f7fp/9egDYhm//V/T/EfiKPP9v0/+vVfz /b9P/r1X8/2/T/69Bzljz/b9P/r0VX8/2/T/AOvVfz/b9P8A69AFiab/ACf6fyAB9ST2rPmm/wAn +n8gAfUk9qJpv8n+n8gAfUk9qz5pv8n+n8gAfUk9qAP8l+9iOg/EvULHg292OTk9evvz19h6da9I m/cy3HkAcd+fXn09+d3Tv0FfO+vePL7X/Een6tPDm4tbz/j7zn29ufxzx+A9w/tLMVvOB26de3t6 fjgfr+ScZYOSxcMTFOUlZJpenXyuu9n1P688P8fh5YXG4RPRq0Lt2s0lZabv7tfS0HhXWJ/Dfiee /gP+kaXrGmazZ8jOc89M8c+oO4kDPIP6HQ/tdz69a6fP4x0PxKLi1s/sRu7Sz0b+zOPX6fXHUniv zI1Kbytct5xgi6tfsXXpkAZ/QZ+mMccfXHgmGDWPCWn3A5uD/oXbH16n0/yK0yfEO1Pu4R6dlFPp u2n531sfOcc5esZRUoqzwTildaO7ht5pWv01sz640f8AaE+GV5zPqtzpvb/ibaPrOm/X/POPft6x oPxa+HOp/Z/sPjjw1c+n/E40XjPbj6/gOmcCvz/m0ztn8fy5/p1+nes+bR9KP+vsbW5/znr6/wD6 +1fQfWH5/wBf9vH5fDLrOM1LVOMl8rNdT7A1/UrGHX9YFjcW11b/AGz7bZ/ZLz/JAOP0z9Prjwrr FvqWg6Pfefj7VZ/h/nHbGePz/I+zs4IYjbwQfZvYHt2/z/KrEN54js5f+JV4x8W6bwP+PTxJrP17 Y9PxH5Hmw2J+q/fbbr1ut/z/ACZtiML9YSi7aJfNJJK79P6s2j9oIbyDPfvxnj1PfqeMegAA9KsT TedET7Hr/Lv/AICvx/h+Knxp0f7P9h8f6lc/ZRzaatZ6NqXHtn0/PpjOc16Rpv7Tnxj03/j+g8Ja 3bj/AKg+s6bqfQH/AKGTj0x9e1elHE4R7q3z72303v8Acuu5439mYv8AqP8AwPX+np+jBvJ4fs8+ bY/asf8AL5kccD8Men+FfFHxJ8SfHf8AaK1nxB8Ov2c7f+zfD+l/8SXxh8TNWvP7M0y/1TBxovgk /MQdwH/FUY+Zdxyvy7s7R/jZ4x+J9h/wg+lWNzoniDVP7UsrzxDZ/wDMP0s/8xrQ8c9R06dfQY/U j9nXwHofwy8JafYWNjbW1va2f+h2mc/T06genr+PyOf8SrK5P6oouVrWlZ8rfKrvpe99+p+k8G8F TzN+3zJSWBdrJb/Zts9LX36+dz+a/wCM37BP7Sfwr0XUPFWueHP+Et0e1/03WNX8PXh1L+zyOPf8 MD6k9vhabTYJTuxhuOfp0568dB7V/dzeeI9Dntbi3nsLa5F1wefoT24z+PHc9K/mH/4KQfs3aV8K /Hf/AAs3wPp/9m+CPHd451nSrTcdN0HxMMEk4zhfFYUsxxhcktkAV6XBvHEM1xCy3MlTvOzg7WvL 3NE+utmummhpxjwRTyHD/wBo5U6iSXMkm9Nne2/T77N9b/EHw8+NnirwHd2sF9Pc6lp9qf8AQ/8A oJ6f19sD8fTNfpv4D+KmlfFTQPPsMalc2uTe2lpxqfOf+YF69ee/51+N8/b8P61oaDr2t+FdUt9V 0PVrnTdQtf8Al7tP/rE+/P8AkfS51wphcyvOheM7OUeVJXbslsrP8elvP5fh3jvMstmo4u8qalGM nJXf2NWuvXXtdH7EXkM8Gf8AhG57nTbi6Gf9FvB1wf6Y/D1yMc/+0Ho9xD8KtQn1W+uLm4tdH1UX l3d3g1Lrowx6fr69ssK8A+Hv7aQ863/4W14c/tLUB/x+eLPD5H9p33OR/bmh8cAcdQe/A4rn/wBo v9qjSvib4c/4Q7wPpOpW2n3V5/xONW1Yj/T9L5O3APBHYEYBr4XC8NZzgs3wdLll7OE1JzS3inFX vbokt2/O7P0nMeMskxvD+Nqcy9rUj8O6cmo7J2au/J+vU+JrPt/wKvUPhj8SfGPwl8b+H/H/AIH1 y50TxT4XvDe6Rq1mfoOePz78nknp5vDD5ERH4A/y6+nuO3OTViv22MfcjGWtopPzaX+aP52nJTlK Ufhk7r0bTX6H9pH7E/7eHw5/a08JW8Hn23hv4saXZf8AFY+CLu8/4/8Ap/xOtDPP/CQeHRjnI/QV 946l++0rUOn/AB5/h/8AXHP4/Sv8/bwV428R+A/FGj+KvB2ual4b8QaFefbtH1bSbw6bqdhqn49e 1f10f8E9/wBurSv2uvh9qHhvxV9m0340eDdHz4k0mzAz4s0v/odNDGM9uP681j9V8vw/+1DE7r1/ RH2hDN/+r+n+I/EVsQzf/q/p/iPxFcfDN/8Aq/p/iPxFbEM3/wCr+n+I/EV55B3FnN3+v/1xj+Zz /SvD/wDgpPDBef8ABPH4kQT339mW+PhePtX/AD4f8Xo8A9Mn+ff1NesWc3f6/wD1xj+Zz/SvD/8A go1Zz6l/wTn+P8GQP+KO0u9s/f8AsHxpoHv3+9wPX8ebEr95l/Ktprma6XlDf1vp8+iOrDdfX7tN /lufgh8Df2V9D0f4jfD/AOI3iTXPDdt/ZfjvwHrej/6H/Zv/ABNP7a0Dknw+e/pnrz0wB/ZP8MZv +KS8Qc8+5x+vQe+fp2r+Cj9kf4SeK/iZ4l8A+N7jxVpmieGPAPj3wxdm0W+1fVdSzoGuaBrh0VdF Qsugr1w/ipmQjBU7Tmv614f2xtc0Gw1ix8D+B7bUre7/AOYv4hvDk9c50M9Mfrj8avijPcqyt4KO InFWik1Fq692GrS6N99V+ffk3DGaZ1iW8vhLFq6SbTstYtrZLTt8rH3hNN/k/wBP5AA+pJ7VXr87 7P8AbM8Y2cv/ABUfgDTbm36f8Sm81rTfw/QjvX1R8Mfjx4A+J0fkaHqv2fWP+Xzw9q//ABLNT6Z6 8Hv+AHHrXj5dxNlWYzSw+PV7pOM2t/dSa1T336X9LPvzbhLO8lvLE5e+X7UlB2WierWz002X6e8V 4/8AFT4M6H8T/wCx9VgvtS8JeP8Awv8A6b4P+Jvh8/8AFTaCMHp/0MHh3AwPC3iznn1OK9Yg7/j/ AErQg7/j/SvpY+8lKPvRa0ktb9tV/WvQ+P2dno1unuvVHzv8N/jbrmj+KNP+Enx3sdN8N/EC648H +K9JP/FDfFv/ALAf/Qv+IvTwtz/KvrCGb/8AV/T/ABH4ivH/AB78PfCvxO8L6h4O8Y6V/aWj3R5/ 5hup2Gqcf2FrWh64cnw/4h47d/bNeT/D34keKvhX4p0b4LfHe+/tM6pefYvg/wDGO7/5BnxL/wCp L8cf9C/8ROMcnHjTnHOKYH3Bps3p+P8A9cfn0+g9a9g0G8Hldvxxyf6ce+RjNfP8M3/6v6f4j8RX rGg3g8rt+OOT/Tj3yMZoA9402b0/H/64/Pp9B613FnN3+v8A9cY/mc/0ryfR5vX8M/8A1vxGPqPS vQLObv8AX/64x/M5/pQc52EM3/6v6f4j8RViGb/j4/nj/wCv+XH1rHhm/dfh9OBn9P1PStCgCx5/ t+n/ANeq/n+36f8A16r1X8/2/T/69AFjz/b9P/r0Qzf/AKv6f4j8RWf5/t+n/wBeiGb/APV/T/Ef iKAOg8/2/T/69V/P9v0/+vVfz/b9P/r1X8/2/T/69AGh5/t+n/16rzTf5P8AT+QAPqSe1V/P9v0/ +vVeab/J/p/IAH1JPag5yx5/t+n/ANes+ab91+H14OP0/UdKPP8Ab9P/AK9Z8037r8Prwcfp+o6U Af5L+neD57yG3/tWD7NBa3n23/ROPt445Hft6V2F5DBDELeD/Sf9M/0O04/l1PQf1qxeXk837gnF uOxHrgfgPy/ljH87yvx9v89ce/T8/wAdzDOMTmsotwbimm7aPW3Zf8Mf2dkvD2EyK8lK7bik07pv Ttddnqt0QeJDmKwvuP8ARrzrz1yOOOvtyM9exr6P+DOpY0vWNK/59bz/AA7Y/D26+9fN95rEE0Wo WX2Hm5H2Ie/vnPBHI9Occ5zXpHwZvPJ8UfYZ8f6VZ46j8MDOD2OPyA5rpy+aocq0k4xstNbNJ29L 3b6dfI8TieEsRh8baLS923mo8l9F6Lu9dD6RvP8AWj6n+Rqt1/6ef0/zj8K2J7L/AJ4flj+Q/wA+ p9azvsc//PG5/Jf8a9k/JLW07afcL1/7ef8AP4fr0o86CHryP8nPv6Y7++KT+zdV83/Uc/59+n6Y 96s/2PPN+4zweQc+v/6u3piucDPm8iaI/L+XOAD68dOvbvRNef5/lx/Mfj71sQeFbiab/QftNz6E 9j25Pr/npzY/s7w5DL9n/wCRk1D1s7z/AIllj/3HPpjnGMe9BUFecV3lFfe0fTH7K+jwTXVxrk8H +kXV56/n+XXn17V+oGm6x+68jJ7f1HtnI7844Ir81/gZefY7HpbW1wLz/l0s/wDiWc8+v59O2PSv sCz8S/8AHv8Av/r/AC45/UV+GcSV8S8xxsLu0drttJ3jZL5fe++x/SnDeGVDIcFZK8oxdrX0ajuv L57dj3D7Z53PT9fx/H6e/evlf9pDwTofxI+H3iDwfrn/AB76pZj7Hd8f6Bqn8v69e+K9403UvOi5 z7cdz9ffr/Wvmf8Aad8ST6F4N1C+gz/ovrxjAx1HP456Ae9c+UzxUMbls8O5J3hdx0bs4t7Pbffo dOcQws8tqQxav7rSTSdm0l5JJ9O11rsfzP8AiTQb/wAK+I9Y8OarATqGg6xqmi3nsPw/x/kRWP5H v+v/ANavYP2hbyC8+LWsX0H2b7RdWel314epOqf2Lnnn8+Ow98+T1/X2V1qmIwWXVaiakopSXm1F e9Zd0fxtmlGFLNcfRpyThzS5GrWesXZa2626depX8j3/AF/+tR5Hv+v/ANatDyf3n+o5/wDrfT1/ X3qx5Hv+v/1q9SyvzWV1tK2qXr+v/BvzfV3bl15f5b6fdzWM+q9aE0P+T/T+YIHqCO9Z/wC9/wA7 qZx2fZ/d/XdfeFfTH7KPxs1z4DfHj4b/ABG0Kf7N/ZXiTS7LWbTtf+F9d/4kOu6L6/8AIuf49K+Z 4O/4/wBK+kf2S/g/q3xy+PHw/wDA+lWNzc251jS9a8SdvsGlaCeevH+fqaDc/s3hvYLz/ToP9Rdf 6ZZfr/h074zWxDN/+r+n+I/EVz5s4NH/AOJVBxb6XZ/YfXn6cdMZxzx64FaEM3/6v6f4j8RXnnOd hZzd/r/9cY/mc/0rP/aQ0LQ/G/7I3xA8HeIh/wAU/r3hs2WsYvP+YX/wmnT9M5Hp2os5u/1/+uMf zOf6V5x8cviQToOj/CvQp/8ASNUze+JOObDS/wC2snRT1+mfr92vm+JMy/sjK1iotKSd0nZPdWd1 52221Pd4by3EZrmqw1FN0+aKn1TV43Xm+2nU/M79mn9l3wP8PNUuPEelaULa41S9/wCJOdWs9G/t PQdLOtf2/wD2J16kA1+nGm+A7GGK3gH4Y/Pp0z+H1xXmHhuy+x/Z/wA/1zz/AI816vZ6lfcn8Pbp n+mMe2Oe/wDO+ZZpi87zB43FTapr4VzaJJRW17W07WP6nyLLMJkOFhRw0Yqs4xcml9q0bq/ql+uh na98MYJ7X9xB9Qeoz06f4g5ye1fNHiTwrf8AhvVLfVdKnudNubW8+22d3afXj6+hAP8AOvuiHWB9 k8ieDIA/mf8APfr+deP+NtBN5CZ/Iz0x/wDXOOnX2rKnCeDcMTg5ySUlKSjK3Mvdut+ltF0e3n6M 5U8epYPH04uMk4uTje9+Vbu1+v4H0x+zf8Zv+FneHDY65cf8VhoP/H5nn7dpfX+2xj/JHOOa+mIZ v/1f0/xH4ivxH0fXtc+FXjfT/Feh3H2f7Lef6baAH/T/AH49frxycV+wHgPxtpXjzw5p/iPSsG3u v+Py0/58NUHTPtjvwa/eODOJf7RwkcHLSSUU3J+8tu71srX23Z/MvHnCksmzOWLwumBm3azdru2t 72tv5HoFY/jDwT4W+JHhfUPB3jLSrbW/D+qD/TbS74yOvJx/yMXX9PQVoef7fp/9etCGb/8AV/T/ ABH4ivuT88PmfTfHnjj9mm5g8OfGLVdT8bfBe6vPsXhv43Xf/IT8JD/oC/HDnGR2+KWcf9D76194 eG9TgvIreexmtri3uv8ATbO7tMf8TDpz/k/pivP/ALHY6jaXFjfW9tqVtdWf2K8tLvH+n9+n4Z44 9e1fN/8AwhXjj9mqX+2/hJY6l42+C/2z7b4k+CP2z+0vE3gP/qN/A/p+Pwt5/wCpCoA/TjQbz3/T +v8AT8Mdq9Q02b0/H/64/Pp9B618n/Cb4p+FfiF4c0/xV4V1y21vw/qn/Hlq1p/y4ap/0Bdb6/8A CP8AiLuenfjPJ+kNNm9Px/8Arj8+n0HrXOc56BFN18/6Zz/P+XP5VoVz8M3/AOr+n+I/EVoef7fp /wDXroAsef7fp/8AXqv5/t+n/wBeq803+T/T+QAPqSe1Z/n+36f/AF6ANDz/AG/T/wCvViGb/wDV /T/EfiKx/P8Ab9P/AK9EM3/6v6f4j8RQB0Hn+36f/Xo8/wBv0/8Ar1n+f7fp/wDXooOcsef7fp/9 eq9FV/P9v0/+vQATTf5P9P5AA+pJ7Vn3k3/Hv/X8s/z4HufarE/b8P61nzTfvfx+nII/X9D0oA/y j5rzzov3GftHHp/nvz9R9KsRaPPLERP/AMS636f9RIj159+mV/LivQIdMsbL/jxgx/095zqZPT/9 f19KsTQ/5P8AT+YIHqCO9fzxLOLNfVYqzd3dWaXu3suj66/dbQ/vvDZPNq+Jk7rZXbV1ZtL0V13+ 5nH2mnWNnF5EMGcHr2/Xnrzz1yOc8g8N6lDoXjfRr7A+zi80s5I7/wBO315GeOdCaH97+P15JH6/ oOtcPr2YZbef0+uO/p0znP4nmuvLcTKWMTk202m7tvXmTdvW27PKz7CR+oTSirOMtbR10Vk7/Kx+ nE00HlfX8enHOOPTtisf9/Me5JP0JJP59f5+9c/4JvP7Y8L+H9V88XP2rRu2fy68Y7duM12F5qWl aP8AuL6e5/tD/oE2h/4mg/8AmfAJHGD+FfoUHeMX3in96R/N1a+HrVFfXnfnvptp/wAC5X/s2eWW 38iD7Tc3X/Lpa5B/LOQPXHt07495eWOmy3Nj5/8AaWsc/wDEp0k9T3/t3XMkdv59wa0JodV1iL/S Jxomj3eP+JRZ3n/Ezv8A/sO677dasf8AEq0eLyIIB6E9zzzzng5449OtYmRz5h1TWIvI1X/iW6f/ ANAnSf8AkGf/AIQdPy+hrYhht4Iv3EH/AB6/Q+/fH+elV4b399cdMetp3xnjH+yfr1PpxoQ/vpf3 EHPfp9T9c88fTuRgOqL5ZRl2kn9zuen/AAx1LyLq4t8fZv8ATPU84B68Z6+uc/ga+mdO1L09zj/9 X5Ekfh0r4/8AB959j1meDH/Ln1IyAPf+fqK+kNHvP3XqO/GP859+nrX4nxFhl/aWNdlq7p9L+70+ dnv9x/SvCddYjIsFHqrRb3srR/yte/X0v7xpuveTa/6R1A5wR7D15598nqT3Hxf+2v4wgs/g34wn M5trj7Gv2P8A7CgP8OeQR2x7cmvpD7Z/ovTj68fzx1/Wvy//AG9fEfleA7fSfO51TV9MItOnQZY+ 527vr69RXbwhgPrGbZfRcVJRnGTuuicNGrW6NdrdTk4uxH1bIMweiTjO0nv8K2dt0/Tr0Pyns7y+ vLq4vr6a5ubi6z/pd2fy4PPHPU459K2Ibw+b7+3+eR6jHHtiuYs5iJe/r6/Q4/yB9Cav1/VlKCp0 4U1ZKEIxtFWV0rX7fjon16fxzWk51Zzbu3Jtt929GnfW3fy7JncQ3kF59onn/wBF6ZNp2H4+/qR6 CtjydKz532626deP/wBXvjr/ACrzeGb/APV/T/EfiK0Ptnv/AOO1Zt9Z8/6/8BOovJrHH7if0z6d vf8Az+dc/efZ4R6fy7evX/6/FV5rz/P8uP5j8feufmvPPlMEGP8A9R9fT+n1IoF9YXl93/2vkvuN CaaeaXyLft15I9R19P5d+cV+5H/BFT4heB9B+JfjD4c+I9K0228YeKLL+2vB/iLP/EzvzoP/ACHd F6en6/8ACTnI5r8P7OGCHkkfaP8A6/Ge3cDpx716B4P8Ya54J8R6P4q8K6rc6J4g0G7OtaPq9peH +07DVB2xwSf/AK/OK5zkP7mPEn/Icuf89hWfZzd/r/8AXGP5nP8ASvze/Yz/AG9rH9pu1t/CnjGC 20T4s6Vo5+2fZMjTPFul4/5DWh+2Of8AhFu/HODX6I2d5BMB9Mj/AB7Z/PrzXM5RW7S9Wl+YbnQa lr1j4b0bUNc1Wc21hpdn9tvOo7n645+hPPpXxRoOpX3iTXtQ8Vatn+0NfvPtvr9g/TrnpyMYrr/2 kNenm0rw/wCFbGf/AI+tY0q91j0/5AviD5Tx/wBgMnjGD3zXL+G4fJtbfn09eMnJ69j1/wD11+Ge IuefWsR/ZtNrkWqabsmrNrT8Plex+7eGeSxw+HeZTVpS3V77OPpfbR9L/f7ho837n27/AOck/jxz 611EOvQWfGP58AcdcY6nA55xXk9nqXlfuJ+Scf5xj8PfnPPTz/xt4w+x2tx5E/Ht3z39O/8A9avy tXVkr6bfh9+yP2Ja2t1t+J9oaDrEF71nNz9PXJ6ccevr7jOK2NShg+y+v/1un+POB71+e/wB+Kk+ vXWoWM8/+kaXefYv54/xx26c8V9wQ6x51r/r/wDP4d/8+59PDXTa21220t2+78B4jD2V07Kys76q /m7tdHvd/l494w0eC8luIPI56j8O3px9B09DXoP7PfxCPgnxR/Yd9cf8U/r3+hXou/8Alw1PJGha 1z6DjvkZ6Dis/V7M+V5/cH0yT+nA9u/8vL9Sh8m6E/PTGCOfz6nP6cZ5zXblOZYrKsdDE4fmVNzj 7RJ20bjfR2Vurujw8+yXC53lE8PX1mo2hprdJdbWvo7vTpfc/YCDv+P9K0IZv/1f0/xH4ivD/wBm 7xt/wnng37DfXx/4SDwv/od59r/5f9LP/IC1o46/n2xX0R/Y8/8ApH+j/wBOn+ev51/SOU5lh8zw NPFULKpyrm/xcsb/AOf3213/AJRzXLK+U4yeExC/dOUuW99k18/n9++pZzd/r/8AXGP5nP8ASu40 2a3mGR7Yx9OP8T275riIbOeDuT+Y/Qjr0Oev58dPpo8mX/OMev8A+s571655B5v4q+CeuaPr2ofF T4EX2m+EviBqn/I4eE9W/wCSZ/FrHX+3M/8AIveIf+pp8J/hXtHwZ+OWleNptQ8OXGlal4S8f+F+ PGHwy8Rf8jNoP/Ua0Pt4g8Penirwn/8Aq7DR5/8Aj3yPr/kf4f41y/xO+DHhz4qWun6r9u1Lwl8R /C+L3wH8TfD3/Et8TeEtU/A/8VB4d7f8IsB680AfUFnqUF5F58E/Pb+g6jJzgdeenFWJrz/P8uP5 j8fevhjwT8ctc8N+KNP+GXxxsdN8E/FC6/0Lw34htP8Akmfxp9f+EH1zP/FP+Is/8yt1zX0/Dr0N 5Fx/o1yBj7IPT09cc9vfp3DnO4m1Pvj8Py4/r0+nes/+0/8AZ/z+VcfNqXbzvUEH+X+HPrVf+0/9 n/P5UAegfbPO56fr+P4/T371sWd5/n888fn+gzXm8Op98fh+fH9en17V0FnqXnc+/wCXp+GPTj1O KAO48/2/T/69Hn+36f8A16x4bz/P8+P5D8fetDz/AG/T/wCvQBYqvR5/t+n/ANeq/n+36f8A16Dn LHn+36f/AF6z/O/e/wCc9fpjr2/XFWKz6AP8veH7Pg+d+Pp19/6d8VXvJu/0/wD1EfyOfr3qx+58 r/8AXj/P/stZ83/PfP8Anj3/AM8YPev5dwqerintpbXqz/R9yjGPM5JR/mbVvv2Meft+H9a4/WIv Otfy/Xrjv/8ArHXnGjqWvQWf7mAG5HTr347HPrz0OD16Vx0M2q6lL/z7W/0+ufp+n+P1mX4Xl/2m S5NE+V6aLlskr3Wu1lp8kz4rO8wwtRPCwTfnFXSbaa2duqXX8j6o+DHivXJvC9xodjfW2m2+l3n/ AB92f/ITHvnP/wCr2r2izm/s2H9xY23T+X+enryOlfL/AMGbyDTdZ1iwnm/4+rP2/H2449K+kPtn nf6jnn8/b17/AMh1r7fCa4NdbrTr0VvU/n/PcN9XzVx1s9k1s2o2vfZqy7vTsbF5rF8f+fb156ZP HQ/5OKx4dS1UfvybfPT2zwOh/ln3o/df520Q2dxexHyD+nT19Pz/AMa3PNNCz1jzpf8Al19Pbp64 H/1+3rXYQzX3v9nuvTHPXH688fQHFY9no8EP+o/0nr/pZBye/wCPHpnGK6iGaeHJ88C36DqfXp+X f15745wOf/tKfTde0+f7Oba2/wCPL6fXOe3brxX0x4bm86K3uP55z+OfqOfbpXy/4qx/xJ54P+Pg ax79/wCn+e9fSHgnz/stv1x75/p74/WvzfivC/7VdK11dvZNJK2vrpsrX+R+68A4n/hI36P9PX+u 3X1D/ly/z61+Q/7bGj654kl/tWxAudP8GD/icWmc/wDIdz/xOgOBg8Z7gAH1r9eLyaCGwuMH2A/n /k18Tw2djr2vfEC3voLa5066/wBDvLS77dse38qvgJS/tSOIcWuR21V3ry6Xsktumy2sc3iNiksh dBO8nq7d3y+evTvufiPDN5X+f/189e1bHn+36f8A169Q+OXwfvfhL4ongg+03HhfUx9t8N3nIyck nRmwSDwcHAA46ZyT5PB3/H+lf0rhXHFparZq/S2ltdPy877H8rYq91dNO99fQsed5X4+3+euPfp+ Z5s3r+o/xqx5ME3Xgf5GPb1z29s0eR7/AK//AFqCDPm8+aX7PBBn8u3tj1x/Tjg6FnD5MRI689vT jGfx79/bpYhh/wD1/wBf8T+Aqx9j9v8Ax6gAhm//AFf0/wAR+IrQhm//AFf0/wAR+IqvRQtXZb/8 N/mgXxK2/T71+tjuPB/jzxH8PfF2j+KvB2q3OieINBvPttlq1pj/AED6/wD6uuc+tf04fsN/tCfF T9oTwbceKtc0PTbnwfoNmP7Y+IQz4a+wap/0Bf7D6+IPf/hEh/MGvxX/AOCeP7DXir9t74vf2H/x MtE+FHg3+y9a+Knje04/s/S/+gNoh/6GLxYemeOpPGBX9bPib4WeHfBfhnwh8Cfg94d07w94Y0K0 0yztNL0q03NZaaQSWJzyT3JPXnJ5z+TcdcZ4LLa/9m4WonmMt4xa0T5b3s3Z30tZvXXZJ/S5Zlvt 3fFKMVo1tb7NrK3/AA1vu+BvjBP9j/4Vf4j1Wb7MPFHjvx5opPT/AJgmgcf54H9v+/Oxps/k2tv6 n16fh2H9ffjB/wAFLNBsfh9o37L/AIVgn/4nFrefFDWrzBxj/kQCP16e4ryfwH42g17QNPn8/Nzz 9syeP7UPAx7/AK/SvxPFrG4tvGTe97tu7tK3W9+uiR+/8FxUcrjTj9lSUfT3Uv0R7BeXlv5Xr16c f4V83/FTWJ7O0uJ/tHGD3xwPr/Udfrz6RrHiWCH9x/x83H/PpadM4wQev49eM9civN9T+GPirx5L +/8As2iafdEf9RLU+Pf8P6460sI8JhuV4qzWjVteqkur3u9/kfb4ZPXTrp620/NfoeX/ALN/jCCz 8UeKYPP+y3H/ABKr3n05/Qe+MevXH6AWXxOsYYv+Pi5ubj/p0H9pZz09f146DHavDvh7+yt4V0C/ Gq+Rc6nqGD9su7u8I7/Trkfr619RWfgmDTbX7PBY232cdR39AP0+n04rDMMbh6uIhWwkZRUbK3fS N7r10Xd6brTqw+H/ANnbxMtea0V1a0ei3dtLX2Wr0sctP8SJpsCfSdbtrfHUZGecjPX+WBj1oGvW OpD/AF/+kHn7HeYzx6ZPc/T3ruIdBsZf3E8A9+n/AOvPf8/evP8AxJ4WgspRfQE2w7n0+vfJ9fqa ccTKTUUndtLp1atfTRJ+RP1dWvbS17eVv8R6D8LPiFqvw38WadrljPcW1v8A8eOsWlp0v9L6+vbp nH8jn9b9H8eT3lrbzwXFtc291Z/8fdp/y/8Atk/Qentivwn03WDeRfYZ8faLXPT9MY/T2+tffH7N /jwaloNx4Vvp/wDSNB/02z6c6Xz6/hz+g6V+r8B5sqGIjl1eStK3K7+67uO7ej02129GfhfiZkl6 McywsVzW1ik72XLe2j6u2+11ofojZ+I7K85voPs2P+nM49cfX9DjjOK6/TYbC74gn+055/0S8/tL /wCtx6f4V8z2epXHBt58kc+3GO3+PJ5Jr0DTtZ8nieD6/wAh/h7/AMv2T6uulvw/+RPwjtfRpa+v b79D6Y03Tf8AngPf/D+mPzHY11HkmGL/AI9/8+/T35OfbivF9B8VXEMX7i+4/wCnwdOnr069umT7 V3EPjb90YJ7cH0FpwPpzjP8ALmsAMf4heFfB3xD8Oah4U8caHpviTw/qmfttndg9OnAz759M549f kfWLz4p/s6xW89hB4k+NnwotTzn/AImXxe8B6Xkc/wDVQPDpz/2Og9SQa+wJtesLyLGLY3A5/wBL H9nH07d8f045zWReWfnHz/8AOfT1H49B2xXQBx3w++LXg74neHNP8VeB/Eem+JNHuh/x92l5699c 5x4fOOB29s13H9p/7P8An8q+P/iF+zrqtl4o1D4qfADXbbwB8ULr/kMWnXwN8S/+oJ440P3/AOhp 48a/TitD4Y/H6DxhrNx8OfHGh6l8LvjDpdn/AMTj4e+If+Yhpf8A0GvA+ucf8LA8O89OvrQB9cQ6 n3x+H58f16fXtXQWesdv8/X/AB49a8v8/wBv0/8Ar1oWd5/n888fn+gzXQc57hZ6l1/PH+fy4/Ed a6CHUv3v0/U/j6dO5rxez1jt/n6/48etdxZ6l1/PH+fy4/Eda5wPQPP9v0/+vR5/t+n/ANeufhvP N9v++f6/r0xzWh5/t+n/ANeg5zQ8791/nHT6Z6dv1zVfzv8Aj4/DH/1v1wPxNE03+T/T+QAPqSe1 cd428SQeD/BHinxVPB/o+g+G9U1oY7f2FouefwJz6Gg6D/MI1jxHY2kXy/8AHz/nnt/QZwfrkGHW 7y6t/t0NzpthqlqRu4/tI8/ezgN8x5Ax69DxWxoWnf2bLciA2ouM5/tW6sz/AGiOo6cnQPTJJJwe tdPDZwadF+46/rxn8Sfwz+GMfz0q+Cy20YR9pJ295q+ulkvJd22+tk9/7ihRzXOpqWIby7A6OybT a93To7dldXRx9nFPpsVxBY/8S37V/oV4Bj+07/TD1/4nn4dOPccVn/Y4If8AUZ/T1/Lrz19q6C8m 7/T/APUR/I5+veufmmuJupxz06e/fnr+FJYnF4pq94pNNPsnZp7dNPl1OieWYXDP9x780tXLW+1n rqrtLby7h4bvP7N8W6PPwftV59hx0/n16fzOa+uIf3vt1/T8/wCtfE8159jvLe/gH/HreHp155zw cdcE8GvtDQdSg1Kwt76D/SftVmenPHG36fw8dv5/fZLrhEut4p9dba7f8HX7j8c47wlsTHErrFJ2 W1mt/wAF6+RsWc3kxdDz39Og/P0/GughvOLeCf8A49/xGcZ/nXP1Yx18+f8AH8+CfzPPvXoHxC1S ff8AyT/U7CG8g/H/AJ9Py/pzx75HWk+2fbD/AKgfZ8e3+cY+p9qwIf3Xv1/X8v6V0EP/AD3z/nn3 /wA85PehaNPt/mn+gGfeQ+ddaPAel1q5PGc/4+59ugNfXHhvRhZ6WZwf8/kOv45x/DXy/wCFTBrH jy3sf+XfS7PF4B/0FM47/h+nTt9oazBfaboIMEOfpzz09fp9fTFfnHFNf6zi1FaJJLXTa3Ta+nS/ oft3BlCVDJE5Jpy12/mlG35bba+p5frGsT3n2iCAcduh75/xA7DpzkGvm/QZvJ1TxhOcD/icfmOO MZ7Y/Xr6e0eJNY/4RrQdQ1W+/Lnn9fTBwMn8eT4v4Vs54dL8++51DVLz+2rzHXGvc9/88AV7PCeE 5a6dtLK8lGy0Udeq69WnufNcd4xLDxwqfvaN63drre3ovTroV/G3hXRPHfhi/wDDutQm4sbrkYOP 7PPUHPbBGQe3JOa/Jf4kfD3XPhj4juNKvs3UHTR9W6fb9L4/A+mOTgdOlfsRND/k/wBP5ggeoI71 4v8AE7wFY+PNLuNKvrf7Tnmzu/8Anw1Q459MY/MeuMV+mZbiZYa0U300a80u9/l8+5+N5hhViIrl SVrPZWdrK9/lfroflfB3/H+laFWNe0HVfB2s6h4c1WD/AEnSrzoePTgen4+/Ss+Gb/8AV/T/ABH4 ivqYvmjGXdJ/ernzRoVYg7/j/Ss+Gb/9X9P8R+IqxTAsef7fp/8AXrsvhp8NfGPxi8eeEPhl8P8A Q7jxH4w8Y+ItL8MeG9ItOuo6rrrbcDGOSWGc9gSeBis7wP4I8V/EnxRoPg7wdomo+I/E/ibWNL0f w74e0q0/tLVNe1PK8AYIOTj1GWzwgLD+4n/glH/wS88OfsaaDbfFL4mwab4j/aG13RwdY1c/8TLT PhppmB/xRuiY7kZ/4TbxTztywXrlvz7jHjPBcO4OpFVIvMZQkqVOLvKTaSTaunZW1aXe3Vnq4XDP EuOm1t+lnf77f57b/T37Jf7Ivg79iH9nPw98JPDn2a51i1sxrXjzxYRj/hLfHmuAf27rWBgZJH/F EHA/4osknNeseEPCkGm3Vxqs/wDpOsap/pt5djj/ALAOi9cf0OcfT0DXtSuPFWqeRYm5udHtb36/ b/r7E+4711Gj+G4NN0vWNc1z/kH6DZ6pe3mev+R7H+mP5TxGMxGY42pmuLlOWPqTbim7/E0/tfel u7Lrv9dQpXnRpLVuVOGmt7tJvTTzf3+n82//AAUU1LXPjB+03qHhXw5Y/adG+F/hvS/DH9rf8wz+ 1Nd/4n2u568/8Tv/AIRf/uAGvN/hv8GNc02Lz77Vrn/Shn7JaH+zdM9v5Dv9eRX1R/YNxrGu6x4j 1X/kI69rOqa1rF3nn+1NdP8Ab3HTP+elegaPoMEPbjj1HXjv17cjrwc178cVinhFhnZtqLctm72v t5a/I/oPIMvwuX4Gm9byUG07btJ/JX328+p5v4b+GUEP/LD8OM9cd/x5/CvcNN8HwQxW48jngdPU ZxzyPX1/DitizvILPP8AnnP9Pp2qxN4j6/l/Uf8A1v1Paub6vLz/AB/+RPd+sJbWXy/+18l9xoQ6 bY2fTr17/j35Hb6/Sq801vwO+evXt298e+fTABz5/rHiow4/f9Of1/i/w4weOlcPefEODyuZzj8f 159eufw4rZRXSK7aJeWn5fh5EHtENnBNKfTnn8/8T9eOlUPEnhvzrXkH26c549enX/8AVXDeFfG1 veS5M/oD37e5P/1v0r2CbUvOtORyMdOf6Z+n06VphrXfr+n/AAxp9Z8/6/8AAT428S6bPo8lxPYc XH4DnHb9D+Xaup+Hvjy+8LX9v4jsYPtP2Xm8tLT/AJf8ep/z6da9I8VaDBqXn9Bjpxn8Tjr9OnIr x/TPDc+g3VzByIPp/nHI9Mcfn1ZZmbwWOjNp6STvrdtNaX+7yR5WeZXhsbgXFWk3H/t27ST06X0e 2jR9o/D39q74deJJrexvtVufDeof8+niGzOm+/Pv3J+vc19T6R4wsZobeeCe2uba6AH2u0vP7S9/ 84z/ADr8P/ElnPaapcQT2P2nTx6dcjHXHT8+/Q1X0zWNV0e/+3eDvEeteHLi1/6BN5/ZgHOOn+ee 1f0JlPECxWDhXve0Yq91dJ2WuttFono3f5H8s57w+8Nj3hkknKV1Z2Sd1bXy7d9Hc/oY03XvO/1E /fHb/PTA749OK6j+2PO/5b/j+uc8/wCT71+H3hv9qL4xeFZQNVOm+Nre1/5+/wDiWal09Ovv619U +D/2zfA97+48Vwal4SuMdNW/4mXrk47E4z+GRXu4bMsHez62/Hpfrv8Ah93gYjJsSr6pqPbyt5W2 bs+jSfr+jH9p/wCz/n8q0ItS8mUeRPc22Of9E4/Dv3PTH8q8H8N/Ejw54qi8/Q9c03Uuufsl6Py9 ePy6DpXcQax5xHIGPwwCR6c+/H5da9BYmL2af3dbW+15r71138fkmvsS/wDAX/kesw69NnGba5/L n2/xA9682+Kvwx8AfG3RrfSvFUGpW2oaXefbPDfizSbz+zPE3hLVP+g1oeuf8jP4f5/yasQ6lB5w xP3/AJ+/p/LvjvsQ6n3x+H58f16fXtTWHT2s/Sz/ACiT9Ya0b207fhzHzPZ/EL4m/s9zW+lfH6c+ P/hfa/6FZ/tCeEtH/wCJpoP/AGVTwOf+Rf7/APFU+E/+KL9ccV9caPrGh+JNL0/XND1XTdS0fVLP 7bZ6taXn9paZfjnnPb8fp2rHmmgmiHn4Nv8A9PfQ/XHHTjuOOeRmvlfWPg/4x+GGqah4x/Ze8R6b 4J1C6vPtviT4OeIR/wAWg8ef9wQ/8k/8Rc/8jT4Sx/2JGTxLoYqLX1Zpq6um+icbrfW67dNurKWJ wrt0bS0a7200fZn3BD58ORxnPrkjGPTPOPXr69a6jTbz2+uPz/x6+49q+N/hX+1d4c8bazceAPHH hXUvhd8YNLsze6x8PfEN5/ZuqX+l/wDQa8Da5x4Y+IHh7pn/AIRPPX8/rjTdY0q8l/cX1sP+vvOm /TJ44/r68VevXfr6/MhYdPZX0vt6f3fM9As7z/P554/P9Bmuohm//V/T/EfiK4ezhuP+fG5+z/8A P3af8TLTCOnpxnnn2611EM0GR+/45+uf8/4Z7UvrC8vw/wDkh/VvL8P/ALU2PO/e/wCc9fpjr2/X FeX/ABgm+2aD4f8ADlv18ZePPC+i3lpx/p2l/wBuf29469/+Rc0PXPfk9hXced+9/wA56/THXt+u K838STf2x8UfAGlD/j30HR/FHxB+mqZ/4QPQvzHjjXPTPoaYH+avFD18/wCuMfz/AJ8/nWgfP8q4 z/x7/wBP8+vfGe1Y9ljzR5/9enfP4dO+fatCab/J/p/IAH1JPav5n389rdfT/gH+h8nGMbysoxV9 dkvToY837r36fr+X9K5+ft+H9asalrNvZ/68/wBemeP6cj8+K8v1LWL7UsfZ8W2n/Tnnr/iO3H4j 6LLsuxWJs5NRirb6JJdr6/gfI5xnWEw79z3m1aPL0d15bJ7a2t5LXoNY1Oxgi8g/6RcfXj+QJ69P Xn2r0/4J6x5OqXGhz33/AB9Wf22zsz6YJP8AnPY8+vgHk+V+Pv8A5649+n5+gfDGG+vPFujz2MH/ AB63f+mXf/UL6Aj/AAz/AIV9tgMM8IkqGt7c10+tk9O3Z/5M/Jc8xaxSk8VZdIr4W01dLy01eqS0 PuiHvBB+eP65+o/nWhDDb8nvnp17d/fHtn1wAMn2PyePIzjt0z+PPT0xzjHvWhDDYw2vn+f/AKRn ofb/AOv/AF98egfAB5UPp+h/wroIYT5X2ie4+zW+Tyc5/Xp06Y/D+7n2cPnf8sOmOO//AOvPf86r +Mbz+zfDHiCf/l4Fl9hzjj+1PX9M+w9jXNJ2i5dk1f06X/Q7MFFzqwjFXbnHT/t6O/kZ/wAGbz7Z rOoa5P8A8xS8+2jr7dPfp3z3z1r7ovNYM2jdffjjvx364OfwJ46V8L/CvTTZ2FvP2/z6en/6q948 SeKv7H0a4nnuOnqffnOP/rc/hX5TmMXjMcopu6ly6Xu3dK6XXv8AK2x+/wCElHBZLGTtG0E7PRJW i9r2t+Cs9Tz/AMealP4q8Uaf4cgP2nT9LzrWsdc9uOnXr16cY6iib9179P1/L+lY/hWzuDa3GuT4 /tDXr03vXrpf/MC57H+WRXUeR7/r/wDWr9VyHCxw+Ejh2kpOKd7Xdmo+XktNz8H4izH+0sy9qpNQ jzJxUl9lJXStt07Gf5P3vP8A0H1yev5/ic1n3kPb6f8A6yf5DH171oTwz/8ALD6/Tr3zxj39uvev 53Xz4Pr/AF/r29Tmvoj5y67/ANf01958LftXeFbH7B4f8cQQf6R9s/sW846YBOhfgAPQ+vrXxR5s 3r+o/wAa/ZDxLoFj4q0bUND1aC2udPurL7F9k69e2OO/+TXxv4P/AGAv2p/iFdfZ/h/8Mbnxbp/2 z7FZ6taax4N03TL/AN/+Kg8ScAkkHn6+/fh8ywmEwreLk4w3bbty2tq3fok38noeFiMNfbXZ6dNV b89NO+lrW+P4RPx+/wDx447n8O3ucHjFfXH7K/7HPx+/bA8Y2/g/4L+B9S1om9x4j8WXf/Eu8DeE 9L/6DWu65nCj1wc/dO0Dcw/aL9i3/ghLe6vd23jH9sPxSdF8P2ufsfwz8EayP7Tvzgca3rWG+UPn P/CKE7x08bociv6jvhL8IPh18H/Bun/Dv4Z+D9E8BeANB5Ph/wAP2f8AZ32/uSTxnd349COpr8n4 08WssyuE8LkjWOzF3irNuEW0o83MnF+7Kzio6N3u2tH1YbLnieV2a1TS1XVd19/bS+x8Uf8ABPj/ AIJd/CT9i7RrbVLFbXx/8b9esvsPiT4sXdkB9h6/27ovws0Mc6B4eOT/AMVWefGg44GFr9H9Y+z3 n2nStKH2bT7U/YsZ6+/tn+gx2rYs7zyf7Qn63Bs8dSOR/Eenpx97selZ+mfxf59a/n2tmONznFf2 jmkpvGttxhKV4xWlkk21azttp3sfRU4rCcsUkrWirW627fK/Zu/Y0NH0eCzi/wBQf5c/5571ofEj /Q/gZ8WJ4MfaLrwH4855/wCgLn6c8Y9+c0ed+6/zjp9M9O365qv4qs5/Enw08ceHIM/ade8N+KNF s/8AuO6L/THp/jWNXEfvIbX5oR6X3t5/1frou3AyvmVKTa1qU2303h+B+F0N5BB2B/IfqT06DHT8 +F/tP/Z/z+VeXza7+6784/Tr+H8OcEfkax7zXu30x/X/APWfbFfX00/Zwf8Acj+S/wA0f0PRa9jS 1X8Knt/hS08r6HrF74kzF+P48flxz+Wcc4xy95r3k/8ALx2+nH1+vvXl954kzF/rz+vpz1J/Tv3x XH6x4qzF/r8/z/Hr+FbLDc2yv/X+I1Og8eeJPtmmXEEF/c232r/l86f0z/j054r5P8bfEj+wbX7P BP8AZre17fX+f9BV/wAbeMB5XE5/HB/xxkeuPTg4r5A8bal9s+0Tz3Ge49+5/LoDj8+te1luVqVk 1e72fTz19d9vxOfE4xYPCayTsrt37NPXyta36XPuD4J/Fr+0pbfyJ/7v4d+v8h06dc1+jHhDxtBe RW4/5ePx7d+OpHB/EV+C/wADbzXNNv7jVfsGpf2BdXn2Ky1c/wDIM/tQ5Gfb06dPrX6ceD/Ek0MV vPBP+fX1PT/PXFeZnOXPLcXF0NIvl5rapLS/e7tfbbTQMtzGGZ4aVZOPNGyaXSy30d1vr3P0Rm02 C9tfPP6fh+Gc464PU+9eXa9o/wDx8/y/Tn/Pr9KzvBPjwTS28E8/+j5x/wDWI9zjA9DnrjPrOpWc Gs2vnwfTPt/h0HcfqK5Hh/rKjLDWVleTWmrtfl8m9/l2PSw+IurNadne3dr0u9b6/p8n+MNMnFqb 6AH7Ra8fT2/DH4V5PNND/o/7j/J/D8/yNfWGp6P/AMfFvP8Ah/nH5/mK+d9S0waPfzwf8u/P2Ln1 6HjI6/54Ffc8HZm4yeDqNJrS0+rXKr262XXt8rflPHOROhif7ShHmjK1opbfDq7bLo/X1OPhnnmi /wBBn59/y9umeM/1qteWdxD+/uILa545xn39R7dfUmuphs4PKBg/5eiB1H4dx7f/AF6z9SggEP2G Cf7SOn2v9f5/zzivvz8rMezvL7R5re+0PXdS025/6c7z8Pw5r1DwR+0t8YvCl2YLfxFbeJLe1/5h Piyz5/8AB5zn27fWvH/7H8mLp6Z9ffPXpz9asTabi1zBAc8c9/f9fT0/GunDYp3s76d9vLz6duna 1p5IP7Ef/AV/kfoR4J/bq8K6l9ng8Y6HqWiXH/HleatpP/Ez02wPfPT19ME+gzX1h4V+NngfxXFb /wDCOeMdD1L7ST/of2w/2n+fTsc8e3Wvw/8AJ/df5x0+uenf9M1nzWdhNdf6/pkf9A3Ux9f5fjxx mvRoZzicOuV2kmlbXWyavr3trdau9m9Tz8RluEdkt/Trpr99kf0QQeMYOfP9B16/hkjnuR2zWx/b EE3+on/P/Ofr07jrjP8AP/o3xO+KvgmX/inPHGt3On2pGLTVv+JlpnQdP8eQPrkD2/w3+3Vqumy2 8Hj/AMHC5t+n9reHvy/5AQ/pjr27+nh87w+jafM2tG33i3u7310+5+Xl4nJFbTa11ouyfS/a3T77 n6YfGb4V+FfjBo1vY64Lm31DSr37b4b8WaTnTfE3hLVD01rQtcx/xT/X8PWvMPhj8fvEXwx8b6f8 Fvj9ruiXWoapZ/8AFt/jHd/8U3pnjzr/AMSXXOn/AAj/AMRPfB/4TT8K8w8H/tX/AAx8YDyNK8Y2 2m6hdAf8SnxDnTdSxxjnP8zj6da/G7/gsx4q8Rw+JP2d76x1wXOj6p/wnt6dJtD/AMxTQv8AhAf+ J36HnJ784r2XOGJV3JRT11aVtv8ANdr2Rw0MK0rNNevRWj87LSzv5Lez/sJ8N6jffZft1j9pt/8A PQ/1/wA47eHxJPN/x/fZrn/p779x9Rkeufzr+ef/AII/+JPjFoP7PGoT/FvXPEmm2+veJNUvfAnh 7xENZ/tP/hFx/wC677f0Jr9mNBGlQ2FvPpX2rRPW0s738vX26+nWsTjPoDTdSgmurjyDc/ZhnH2u 9/tLoD+H1HGcVx/hW8/tj4l/FDXM/uNB/wCEX+H3rn+wtF/4Tz/3eND6DgaB1rH0HV/Oi8/n/Srz /j75/wCJhpef+JF+HXjt2xWf8E9Sg1LwR/wkfT/hPPEninxp9r/5/tL13Wtf/sL8B4c/sPA7/lQB /nTxGCH9/P8A6Nbn8T/nnr7/AI1xGva95x+w6Vnz+me+evH55Pp/LOvLz7Z/y3Ftb9bLpxx689u4 6jjNWNN0fVde/wCPGD7Nb9Ly8vMf59uv0r8My3Jm5KVlKScdN7tW33fTZ7/gf2ZnfE8I4RpzjFqz tdLS0X3vr6W7I4eaHzpvPvpxc3Hv1656/QfhznrRDCfNP/Lzc9LK0tOOuMDv1P8AhzzX1RoPwk0r 7Bb30/2XU7j/AKe/XHOPX046j0zXqGj+CfCugxfbrHSra21j/n79Md+vP1GeB/u193Sy76tGPt9L pW5e3utKy2S66/PRn5ZW4ooYhtUE3NaPm1Tva717aNPolo9T5f8ADfwfvrz7PfeKvtOm25/5hP8A zE7/ABweOO46/wAhmvoDR9H0qzjt4NK0o6bb2v8Ay6WmM+/fseP8BxXX+TbzfaO3Hf8AX8B09unX FWYYbcReR9euPTH+QfT8+hdLfK34WPmcVisTimniH7t/dafa3Rdv067nUaPqUFnaiCeD7TbXX0z+ Hpj8PqK6j+zYPsvn/wDHzb4Pf+zfsHcDj/JOea4fTIPJ49R/n/P9MV2Fnjzf38/T/A8/5zwfzDNW tpstAMOJScC2tucDnHGRn9K8/wDiRN52l6NpVvz/AGprB/D+wun58+w9zXqAhE03kd+/4++R+nfP rmvNtSh/t74g29j0t9BsvsP/AHFO/Pp7ev0rz8yxP1TBrz0321f/AANfT0fu8N4T61mq91uN0ld9 nHV+Vmrfrseo+D9N+x6VbnP9fr+fv/SuX17/AIqrXrfQs/8AEvtf9N1j88/2KP8A9X+Fes6lNBo+ g3Fx/wBOY9vw6n3+vtXPeD9N+x6X59xBjWdV/wBMvPrwT2yOe569K+TyDL/reNljJL3eZyUWtmrP e2+ifRbn3nGOcRy3LXg4ySnJKEknrZqK167WsreSvYPJ8r8ff/PXHv0/PY0fTbG81SAX09z/AGf1 vPslnyc8cex/p64omhn83z5/9J+n6dscnnn9cmq8PMp/5drjjt1wP/1c/T8f0fC9fX9Gfh/Nze9/ Nr9+p2HhXTfBsMtz/wAJHpWpalcC80sWdpaax/Zv4/8AIt51/kfr0zXceMLz4VWf2ix0r4f/AGnU Psf2L/S7zWdN+wap/wBy/wDkP5V5P5U3p+g/womM/r9pHT1yeP8AP+AzXT9Z8/6/8BOX6tfqnfzl 5efkjP1Lx7BZxXEGleBvCWm/av8AQrz/AIlA1LU/b/kYOM+mOT04zke//sr/ABgvvB/jfR7GD/kD +Msf6Ja/8uGqfp+HOe30+SNY0G+vb7z7extrom8OR+mPx6//AFzXQQ3kGj/Zp9DvtSttY0u80v7E ev2D0xnj/wCueleVmlB5jgp4XRNRburXdklZtdfV6peqN1Q+rJP4k+W1vLl3v1Xyd09z+rD4b69D ef2ffX8//LmPseB+R555z+X6fRAvLeGIwfTrnn8un51+R/7Lvxg/4TDwbo9xNN9puPsZ+2cYyffr 2/8ArV+lPhvXvtlr/p3+k3FrZ/bbzPr7+vOPpX8pcTZJLB49yakpczs+u6dtr+qTtqmj0sNiUuiX mtPLr6dF8tmev/bPJiuM4/5hf6dR9D+v1zVeG8Pm+/t/nkeoxx7YrIvNYsPN/cQH7P8A2Ppd79P1 H4n1ziq3/CSQeVb/AGeA+nf8v5deMnj1riwt7a3+Hrvv+drBdd19/wDXdfedh9sn8nGe2M9/y9Mc /wBa2NH1mxs/+P6f7N6fa/b6Dt/nrxw8OsXF4bmDz/8Aj64P4E9+nf0B461nmaCaIT30Iufspx26 nsPz/TNNYZJp3WjT69H6mEcUoSU01eLUlbyd/wCY/Cf9orTf+ED+N3xI8Of8e2n/APCSape6Pj/o V9c/4n2henT09eCc1876l4k6jz/Yf/Xx/UV+lH/BTLwHBDo/gf4t6HB/x63n/CF+JLu0P/MK/wCQ 9oXP/g89OOa/FfUvEnk/8t+45HrjPPpxjn09cV+j5JhfreFWn2VfZ7KOj666O/TW25+48PZj/aOW YGs53cbRmla7so6t9Xprp5nrGpeJO3+e44z/AI+o968f8SePPJ+0cdent2+mD9TyO/fzfxJ42/df 6/8Az6e/B/zmvP8AR9N8Y/E7xHp/hXwdoepeJPEGqXn+h6TpNn+A/wAePX8a9qhlyjfnajtpJpb6 W1fo/uOzFZ3g8Jo2uru29Nul1rsvVk/irxsZxxwe2fyycEA8fTHXNdh8N/gzfeMJbfxH44gubbw/ /wAufh8cfb8e3QZxkjk17Do/7NX/AAr3Xrj/AITi/wBN8SeINL/4/NJ0m8/4lmg6pn/y4Menrk17 hDDPnz+f/r9cf59cc5r7bLssUcN9YtFNK9tNk4pJK33Py3V9PzDPOLHi74bBt2b1k3e2yt91tF6X 3Of17wrY3fhe50PSoLa2+y/6bo9paf8ALhqnfvjngEf/AK65/wCHvjDz4oLGfm4yLK9+uO/Tvgn+ Xp6h53kw/uIB6devfH6Z9O5PXPh/jzQZ/Dep/wDCY6V/yD7vnxJ9kx/xL/8AqNf5/XFedxFkn1rC /Wo/F0S1a0T1S26enc6eB+JPqGKlhMXK6qaJtp6tx2eqt5a7n1Bo+vfY5bb079T6Z574J/Lt0r6g 8BeOxNFbwT8c9fTrnH4+/UjjqR+e/hvxJBqWn97nnn1z7dSO3/1z19Q0fxJPaS2/5fqcd+4Gent1 6/mKTwctU3ytXWt9/wCvltpe/wCzwlGrFSg01L3lbW19VovvP0I160g1Kw+3QEfZz7Y7np0GPwPX 15r5+8SaP50Wf+XjHHrjH6j/ADnsPQfhj4wg1K1+w3w9unvjOOM9+nHQ9BWx4p0L7FL58H/Hvz+v 49euevv3z01G4Sp5lhW/dcXKGz05btW30S0dn6PQxrQhjcLLB4lJuSai5K9+ZK27/wCGXe58r3l5 Yw/6DBxcH/j8z9MngH1+pxmq8Gnf8t4IP885zkfy9j6tXcazo8EN1b6rjjn7YfoRx655HPI9fSs+ abzv9RP/AJB/HP8ASv1TI8xWY4WNRtOcIRXJf3tFHpvfW3XVNrU/AuJMnxeSYp0oxbpSk5c6WiTs 0r30srr0MfXpp9S+z/uLa2NrZmy/0TI9e3PPes+ys/3Xn30F0Ra+v/6/oR0I/GtDz/b9P/r10H2T Nh5//Htm8/8ArdO36/QV6p84cP5UHlf8e5+0dfx/w7etY/8AZsHm3An/AOPn6+gx/hxj8wa7ebTf Pl623J5+nv8Az/HnvnAmhnF1cfv/APRxzzz2z/h7Y/QA4/8Asf8Ae3H2ef8A0f3/AKD6cfkOuRXH 6lo88x59Oufp25+p6j17V7B5P2OLt0H8/fgdufqDxzWPQB8zeKvCs89qJ4LEWw5/yB3/AJjPT04/ R7zx/oOqafe2Oq/2lp+l3n22y0nxBZ6N4k0yw1T00PQ/EHUc19c3dnBN/r4P8n69Pb/Oc7+zLGGX yP7D025t7rj8v5555yAMcEmutYuotFKSXa78v73l/XWeWP8AKtrbLbTR99l9x6T4J/bf+KmmxeR4 q8D6J4kt7U4+16T/AMS3Uz7nj8fQfjz9UQ/8FCPB2m6Nbwf2VreiajdWZsrP7XnNhqnP9hfxEc/X 8hwPhf8A4QOCeXz9KnFt/wBOd5njvn15/wD1ccVYPhWCHP8Aa1hnP/TmR1GDn3Gef61usyxXqvTz XW3lb5vu7831fB9l93/BP2g8bftFeB/B/wAC/FGueHPGGifadB8B40e7/tj/AKgv/Eh45IOefT6c V9IfDzxVpWj+EvC+h6FNbXOj6Z4b0uy0e7tLz/mF/wBi88jnH+AwRmv519e8E6V4k0E+HJ/tP9n3 f/H5afbP59v89ScV6R8MfiT8W/hLbW9h4V8Y3GpeF9K/0Kz8PeLP+Jnpn9l4z/nv7+vpYbMk7fXI 6aWV/T/gaNadTznl2Fber+Sfl5f1f7/5n9H8N3E01vPPAbrr/omenv8A5yQT9K948N6PmHHU2mT9 kOeewOenHt681Y0fTbfTYv3EH2n+fb17+v8Ak12FnZQTf9Ox6D/H9eucYA4rzOXCYWP+yJ366NX0 V97/ACV/LofX1sXjMxxCxGInKMLJ8jb6KN1bRaXerS9bBDPPZ/6i3/0cf8vX449x+HX1IrYvNS+2 Sief/j26Dn+n0+nb1zRmeH7TB5H+jd/qPX+f6Yyar+TbzS/8+3+fftx6/wAga53iG97v1u/zkaKK WyS9EV4czS3E0H4g/lx/9buOK6CH/pv+OP1zj/PX2qxDpvkj9x2/P69vXuPfrWhDD+6/6eBn/wCv 6knv+mfRFJNtJLmu9I7822lvPb+tLENn5Xv/AN8/1/Xrnmp7OH975+MD/Hr09z/kmoPtlhDIIOk+ ePsdmPx9P6Z/Cse8+IVjDdXGleHNJubnULXP+l3f/IM/zj3H1xwW8Vg8JeUvK7b1tZa676fr5Hp4 bJM0xbUaGCcHKzu00/ecU92r9e+tz0DyYIYbi4vp7m2/5/LrvYH0P8+AMfrXn/weh/tKXUNcn66p efbeevHv/PGPpwKrww+KvEpuLHxHPc/8I/r9kbK8Ok9LD888nsevUCu40fwfqvw3tfsN/wDZv7Pu v9Ns7r/n/wDf8Of09a+dzrH4TF4eNPCvlk5QTW7adk9PTW6373PusgyfEZDWc8XGz5VK76KylpdW 2V316HUeJJodS1nT9DBH2e1/0287Dvzz04559eTxWhND/k/0/mCB6gjvVfw1pulTWFxquq86hqn+ m+1hyfx/w9PXoDDP5v7/AP0nIJx/9boB3+tevkeGWFwqb+KzV9Lu9raabpb666H57xLmP9p5q7Sb hCW2605V5dWtXovvtn2fnw/8sD64/wD1+/44rY/seC8/fZ4/5+/UfXP+fT06CHTYJovPx69M/j/W tC0hnhlt4DD6dB+PI9evfsfevV+tPs/w/wAjwvq68vw/+ROPh0a4s4sCfrgdfU9f549eKsQ2ZMXn gd+fbj9OR+PJ579x5P3vP/QfXJ6/n+JzWfDZm7m8j/l37cfr2z69fxrl+sPz/H/5IPq68vw/+ROH vIYJorjyM/8AX2fqMZ/D29TWfD4b8mLz54M5/Tse34/1xivYINBsbP8Afz/8fHYdOvH4j9MGq95p vncwf49Djp1x0/XrTWId1e9rq/pfX7QzY/Z7+IU/w38b6fY+f9m0fXrzS7K89P8AkNf0Nfvh8K/G FhrFhcTef/pF1o+q/wDp6wev0z+mfX+defQu4Huf19fwA/TvX0R8Gfjx4x+D+qaf/av2nW/D/wBs GLS7/wCQmdL6559u/XHc9a+N4q4cjmfLi8Lytq3MtLq+l7dHr/wzOc/eHTde+2WFxAP+PjS+f+4X g8dfy9PTvSQ695I/1/fuev459v69enxB8Pf2lfA/iS6t59K122trj/n0u86bqec59P8AHp16V9DW nirSryL9xcZt/p+R7cdfz61+a4jh+eFsnTlJvtG+q5dXpbtfp19cLvu/v/rsvuPcdN8Sdv8APYc4 /wAfQe9bB16D/SOn/wCr/wDXxn3zXzvNr0EMv+v/AP1d/wDA9ec8VkXnjDMWPt2Oee/6VP8AZv8A d/AR6f8AHLwf/wALg+C3jjwBbwW32rVNHzo/2v8A6Cg/4n2hY7f8jH36c8V/KP4lvPsctxBe/aba 4tbz7FeWf/PhjjP19D6HNf1AeGvGF9ZzC4sbj/tzu73Ix+pPOcjsenfPwP4k/ZK8HQ/tD+Ofibfe HLnxt/wmWsf8JP4P8JXln/xTOgaprv8AyHta13/oYP8Aio/7c/4pX/EV05dif7L+KVlzK77J9Oz2 /HfVH1eQ8QvLMHKClJc3wpvrbTRvv216H5//ALPf7E/jH48S2/ivxjPqPgr4b9bP/Q/+Km17Gf8A kB9/+5p54/HH60eKvDfwr/ZF+COoQfDnw5puiahqp+xaPd/8zNr/AIoz/wAhrXNcOf8AkU+T1/wr 6Ih0CfQdBt9V1yf7N9msxe3l5xpmmWHvz+Oe3uDX47/HL4wX3xa8ZXF9BPcjw/pY+w+G7S7/AOgX 1/ts+p4zzx1xivfyrD4/iDNacoqSwEHGUmkkrxcXe+zu03fzPFzHNsZjG/rDfK3dOLd7O1lp12/W /Tj7TUvOl/f3GB/y+f5575rY/tKDyrjyOvr+uf8APHGe1ebw3g8r29v88H1GOffNbFn581rccjtx n/8AXnt+Nfs0MGoQjBLSKSXy2+0eMdhD/wClX4emPp+uOenNaBhsfKngvvswt7qzzeWl2P8Aj/7j 9Mdz+pFcvZ3lx/qP+fX+fOfU9cfj3x00IZp5jbi459OvTk+446kdM/WuRxUlytXXbpt2XkVGThNS jJqUbNNaNOOq6+m346Hg/iTR7/4b6hcarpUFyPB91eZOemgk9P4TjGDxn+mPQNA8VQalFb3Hn8H/ AD7/AEzgn68V6BeTW/2W4gnt7a6tx/y6fhj2wffHucivnfXvDd94JurjXPDn2jUvD/8Ay+aR30Hn nrzyPTFfF57w0mnisKk11i9Vbrpfa+3Xax+q8GcaWccHmUmldKDk7fy2vL7+nzfT648E+Kvscv8A r8fX3/mP/rj3r7h8OeJLHxVo1vYz3H+kY9jn6c+/cgAd+a/Ibwr4w86Lz4Z8Z6Y69++e/b0P6fU/ gP4hfY5bfz5+nrj8+w/ya+CoUnhZezlHd25ZJreye/okvuXW/wCsRnHFpSpyTTSaatps7rX0e6bS +/6Z8VaDPD9og8j/AD39c/j29sY+d7yH+wdU+wz/APIPuv8Ajzu/+fD9PrxivrDTde0rxhpf+kT4 uT7DOAB29OOh+nSvJ/FWgw3sVxBPbj8h+OO319aunicXkuKjiMLKXs5OKcbNr3mr3Wisr77XOXM8 twueYOVDExXtYr3ZW95tbb62ut99Th4YoJh6ZyPbHr/n8xmrH+q/znOfy9Pbp+fwv8YPip44+Bvx V8HwT6qP+EH8UWeqWWsWl5j+zLD+wvzOO/vmvrHwf8SPCvjzS7e+0O+F19qs/tv2S7I03U7Dnse/ 4f41+rYPEvG4OOLVpSajpvuknvqt/wBT+fM1y7+y8bPCWsr2/LV9/RbPzOvmm87/AFHp39vbBzz+ Peq8Nn/n+fP8j+HtVkzQTTfYICLnveHrwQO4x+PofU8G/LB/yw/49vtPPr3698HuPXrnmulapPv/ AJJ/qeacveWc8378Z78/Tjn26+uR7Vn/AGP/AKYfZsfh79PfHqfXjv1Hk/e8/wDQfXJ6/n+JzR5U Pp+h/wAKAOP+xzzjMFwLngDqTn+WeO5/LkCoIbMQjP8Ax7fj36ZPHoSPXvwa7eazgz37c449B26n nPoASfWq/wBjnh4H+k9vfsc8H07fj7UHOV7P99n/AJef6fz/AE6c56mugim879wT/o56fa+nvk9/ f8R1zXPww+V/n/8AXx171sQTT/8ATt+nt/nnr37V0AaA0fSrwAf8g259uf8A6+cf09DWPd6DqsWP Intrm3tOO/5A+x+vOa2POg5E/wDx8fTpz29OBz7elH73/O6gD8FtNlns/wB/Bj3HT/P69CfXHUwz ed/r/Xt7Z7YOePw71n2fkwy+f5HX/PsP88elbA/1tvP09/8ADOP58ex69B9AaAhnhlHp/Pnkf4Z+ mK2IYfOl/wBR+f5Y6f19T7VXs5vPwZxznH4Z5x3/AMfQda6eGGD/AJYfavtGB/olpnp1Pf8A/Ufx rnOgghh8r/P/AOvjr3qveWc+m6z9hvtctf8ARf8ATcaSD4k1Sw5Gf+RfJ/x/Ouo/s2+026t576DT tSP/AECdW/5Bg9uDj14/LPbl/wCwb6GW4n0PXLbwlb/8vlp4e0cjU9QPpzz+PQe5yK87Mfrll9U7 K/3q976XPpeHqGVpc2KklNO6nLRJq2zfVPTd+aOXs/s+pf2xPfarqX+lf6Fo9nq3/IzX/Tn+w92f D/J57A+3FaHg/wAHz6Da3N9qv2XTf64H+R9cV0Gj+DreG6uL6x0m5Go3X/MW1e8z26Dn/Oe1bF54 JM0uLifUtS1C6xizH/MQOf8APA6GvNw+UYvELmxTeydrq9tL2+evpfvY+tq8SYPBqEMEljMXeMU1 pCKfKl5WVls9vNmhpHjfw5Pqh0PSrf8AtHUP+P28/wCof7n6jr78+1dRqWoz6lFb6HB9m1LTrof6 ZpN3ZnUtM5+vYjp/9euXs/B3/CB6hcWH2H/ioLr/AI/PtmP+Jfk/1x+nc8V6RoOg3GmxYwPtF1ze /Xk9uf8AOeTWGGySUcUsQn7sW0k3o7WSt0+9La7M+IeJIwyn6vXivr1SCWju4JpaX8k3a77aINH0 0WfE/wBODx19c9/16d66iz02D/XzzdMZx/T04zx+lWIYfOl/6ePwGc8HoM/jnIx7CpzZ3H+vnx37 f/X+gz+XevqlorLtb5af5H5C6HM3N6t6uXXXpfl89rizWcE/7+D/AI+P+fvj/PHAI/rVfzriH9xP /pJ/5+8e4/P/AOv6cVY88eZ5OP59Menrj/PatCzssxeeIP8ASP179cdevA6H060AFnpv2wf6/NuM 9h7e2Pfrj6YroPscEP7jycjqPb05zzjOf05758MHky/uJ/s1x746Z+nv+GeOuKsZuIZSZ/8Aj2/5 +/6enP4gfz5wD9x/qM/6R+n8/wDPXpWh9iuMfZ/68fX/AD9cVoWcMH/LD09+fw4684/LpjGhiD/l x5/6e8j1746fj6cUAZ/9jQ/88f1P+FV5tHt7z7RPP14wccn8vw44/Cuws4BDF+//AM+n/wCvHNaF nZ+fFcT+R9mt+D9f/rdPr0rnvLa/u9tf87fgc54xqXg+Dr/x7f8AXpx7+34dh2q/pviT4neG4rca H4x1K2t+f9Duz/aeOep9T+GPpXpB0z/Sriefp3Pf07e9WJtH8k8Qdv8AQ/8AP+eOemKy5qbSji6U dGraLVJqy0X9bKx5n1Vd1+P+Zz//AAub44abnz762uT/AMuVp9jOL/8ADj1/mO/GfefGb44TRfv5 rfTbjk4tNH/lz1+nNdxDpEAi/fwf6R78fmPYZ6e/aibR/JBGOvrzyAfX8sd/yrnWFwTd1gFa6eyd 1eOt/O/3t/I+rea/H/M4fR/2j/jvoMv/AB/W2pf9fej9Djrx/I8ZHevcPCv7aXir7Xb/APCR+FbY XFrj/S7Q8/Q9eOo7dc9TXn/9mwebm4gPI7cDpx/n/wCtVf7HDZ/8sLa6x16ZAI/PsPX056jCtkuW YpJSwKV2ru1v5W9Nr6aflYs2Pip+058TfiFpeseHPt/9m+F9UH+mWg/5Cd8Pr2Ht156V8zww/vfx +nIJ/X9D1r3C8s7G958j7Tb5Pp9OnT/6/t0zx4a0qb7QILf7N9MD1x68cdcenSvdy2hhMswqw2Ei oydm9LvVLql0+SsB5PCf3nkeR+P19O2M8HPpx79hZ2WIv17HjP4/T256V1EPhWDzv3EHfnr+X04z x6+2BsQw/Y/9H8i2uf5/p/8AX+ua9dbK+/X7l8t7nOeXwzTwy3PPB6+ncc+vfOPWtiGaCH7Rnn8+ ffP+T7ZHHcQ2cH+vuPstvbj/ABI7fTsAfeiazgmj5gFtzgdf8ep9uw+tAHl815feb588FyefX+fb /PpmrH2yeaH/AFByfw/r/wDq9+/YTWf/ACwtz6Z4/qf8+tZ83nwxf6m2Hfoc+/0/XB/CjTrt19Pn oNSlFqUHaS1i13WzXzPnfxJ4JvtHurjXPCsH/T5e+Hj/AO4L8P58VoeFfG3n/wDLf/SOl71/z9ef /re4fa/+mP6f/Wry/wAefD2DUpf+Ej8OfZtN8QZ7/wDIM17I6+uOuOgA6g9/nM64dwmKgsThrKTi 7x03929uq16Lrdtaaff8Kca4nL5LCZi3KEuVJvWydrK9+zV/LXsfSHw9+IQhFv5E/f8A/Xn0wfw6 9B1+oIbyDxJp/wBu8/8A0joPfnjHv35/XGK/H/QfGF9pt/8AYb6C503ULX/j8tLv8Rx+fI/M9a+w Ph78VP8Aj38if26fQ8YP+f8AvmvzurhXhnLC4tSs/hbV7a7N+e29ux+y4TGQxqhi8JJOMuVtRknp ZNu2zvpb5HoHxh+EvhX4neF9Q8K+K7H7Tb3RP2K7/wCYnYaoMf8AE7/Xk+/4V+H/AIr1j4t/sZ/E /wAjVZ7m5t8f8SfxDd/8TLTNe0vIzwCP+oHkV/QwdSsfEdtbzwf8fHbHsR/jxxg9M5r5v+P3we8K fGbwbqHg7xVYgfaSf7H1a0/5Ceg6pzjWtD/pk8d66uH8/wD7Jx0MHilJ4GcrQurtXcUren62PD4q 4YwmcYKWLwto5go3ttsldJd9NHrvfQ+b/gb+2x8MviTLb6Vqs9t4S8Yf8+n2z/iWX+qdce2OOfzr 7wh8/wAr7RPcW1zcf8vnbjH17ZxwO/AzzX47/Df/AIJv6HeeI9QsdV+O9yNY8L/2Ve3mkeHtGOm6 nYcjgeh7jP8ALiv2A8K6DB4V8OaP4csZ9R1K20Gz0vRbK71X/kJ34z15HX65+tfplephKkoSwjje UVJK99GotX0Vt9nrot1qfz9UWKwVSWExSbUZWTStdJrTWz3Wl+mxsQ3n+i+QYB2/4+/Xk8fic/8A 6qsGz86L/wDX19ffrxjHv61Y8j3/AF/+tR9j9v8Ax6sAMf8A5a/5/vUf8tf8/wB6tCaH/J/p/MED 1BHes+ft+H9a6ACazmOPI/0m369TzySOnb1/HJ7UfY/b/wAeo/fwnuCD9SCD+fX+XtVjzoJsweQP /r5H6n8P0xQBnwwz/wDPf8Pbnvn168+lJ5M5lt/s/f8An0wBjv8A1zzmrP8Aqv8AOc5/L09un52P O8799j9c+/r3x7elBzn4TwRf8t8/Qn8R/wDX5966ezsxMP3/APiOOvb0yPUfWqFnFBDFbTz/AGk8 nv7env68D3OK6CzmuLwnz/8ARv8Ap05zxz+PHXkficV0H0B0FnDBFF+4xc9OcH8fQfmO3Fdho832 OL9x/o1z/wA/f+SM89MHnvzXL2cPb6//AFzn+Yx/Suoh/c/6/wD0n68/4f8A1vxoOg0P+Wv+f71b EMP/AOv+v+J/AUabZwTRfv8AI/H37DOPX37E+uwNNnh/1/8Ax756cj+hHr+R9BXONSlHZtddG1r/ AEl/SCH/AKYfhj9M5/z196sQ/aLO+0/VbG4+zaxpd4b2z6f5znocjuO9WIR5w/cT8n19/wCnA4xz 9a2ITBD/ANfH5df8/wCHPFARxLi+ZXi073Wjuut7/iyxeT3+sX9xquuXH2nULrr09BjH0H9McVY8 mcxfuOuT9e+T/nOfXIo/1v8AnGMfn6+/X8tiGHyYv9ec9vw/njB4PPrXOLE4qWMtduTjaN27vZb3 63+/y6Z8Nn5Mo87+XT3+vY9PXnmtiaGeCK38+c/Zxz75P06+mMdfwo/s25vP399j7R+XbjnqP04z 16VoQzXsP7ieD7Tb+/PToeffPr0+lBzmPDDB53XOO+Ov58/zNaE37mLHOeoxj9Rn0/HPPHbfh02C b9/YzY7fZbv8P5dPqKg8nyJfIuIce2Pw6/jj6DPrQBjw/vv38B/yB+n16D0qxD58P7j5Rnj+WTnH 8s/l10IdN/defB259j27+/6fWtH7HN/zxH5H/GgDnoZriH7QYJzbfaubw+/c/wBOmenFbFpeev8A 5KD8u31oghsR/wBPNx37/wCf58dO1QTfaP8AlvnH/Ppn65Bx+uPyoOc6aG94t5xP9p6Z/wDr9OgP Q/kK0bO8vse36cA4GPb1x0/KuWs/Iz/z7XHX8e/ofb+g5NdDNqVxZ2v2GCD7Tcf1wcfjx/nNc4Gx Befvv+njpwevfnnrxx+QroIf3MVz/wAvNxdc3l337jnGOoPPueg4rhof3376C4/0jj7Z07+uD+A9 exrRs9Tn839/9ex/oMdc9hj1oA2P33m//qz/AJ/9mrQ/6+P+Bf5H49Px71Xn5h+3wZ6euceh79On p+dV4b23mziDH0OPTrjr/THPsAE03+T/AE/kAD6kntWPefZ4R6fy7evX/wCvxW/PDB/yw6cn+ffO D6YPt0xWBdw/88B9f/1fnkf/AFqDnMfzvJmHkf4+x+nIx6/yJ9s8nnr+n4/h9PftWh5Pk5wP9I6+ 3+P5evTFVvsdx6j8v/rV6ACwalP5Vxx/pH9Pz/z61Y8mCb9/78c/5z+vSs/yPf8AX/61aGm2fnH9 /ABb/wDpf0z35OfbP1roAsWZ/dfbp4DcW/8Ay6c9Ov8A9ccfyqv5/bPr/ol3/j+Y/wAgVfm8+a6t /T8/b8f8RntmsDUpv3vkQdevsccfgaDnLH2yx/0jH2nAx/8AXGP5dMDPA7580Pm/5/n7Zx361Ygg 6GD8yPw/wwSfXjoasQ6P+6/1/wDpHufp05/Kg5zn/Jhmi4yPtXT0/wA+mT9PfH8r7H+PPT07fh16 +3seo8nyZfIn9iLv6/8AxPbjoOar+Tb3n+v9enTt78Y9fy47AK11fyTfW39dNEef+MPAeh+MLD/T 7H+zdYGP7H8Q2hx9gH9fb+lfN32zxH8PdeOla3B/pJz9ju7TjS77v7Y6g9R+PWvuGGzgMXP4Z9B/ +v26815v8WtH0O88EeKNV1WDH9g6Pqniezuz1sP7C57ZHH+GOuR5uYZWsxjeMUmrPRK7dlbS2vTR 367n1nDfEeKyXGQjUnKWATirNt/y3vF9Fsld+hX8B/FryTb/AL8+3f3z2z6DpyD7V6R8SPjNb2ej W2leFbH+2/ih4ozZeD/D3OeeDrWudCfDpz7AjHXivzWh+JFjr/hy4n8AXFtqXje10fS9as/D13/x LRqGlYz2yB/wiZ44/lX0z+y74an8N3Vx4x8SX39t+OPFH/H54hvOPsGl9tE0P25HOR2znFfBYrJP qcniMfZSi26MfTl5bx63srW2XQ/YI51/asYPLvdU4pSbtbVK9m+l3p1WiPcPhv8ACW++G2l3F9qu q3Wt+P8AxRef214x8Qd7/U+OPbw717f0r3jQfElvefabG+/0bULXv7YHXnH/AOrPY0alB/aUVtPB P2I/If557Y9CDXLal4bnm/f/APLxuJ/r+Z+nQ14+GzjE5di1XxDbg5JJXVkny2+HTskn53OPMeF8 szLByo6PMrJ8zWt/dkne3f77q57D53/LD8dv64x/n6d6IZvK/wA//r569q8f0fxhPpt19h1v/j3/ AOgsO3XPXge3evUIZre8i/cz2tzb3YHfP5dP6ev0/SsuzfB5nBPDygpcq3eqbSvZPs2/8kz8ZzfI sflmKVDEqUqcWnzqL5Va1neyW72u9CxNN/k/0/kAD6kntWf1i/6eLr8MZ/n09vxqxNMZv3Fv/wAu vTr6d8+/bjHfmiDv+P8ASvVPNWytt0+5fPaxn+RPDFAf+Xjj+XHQYHf19DjoDM3/AD7/AMv8KsT9 vw/rVfz/AG/T/wCvQBWvP3PHnYuOf9D7+p+nr/KtCXyIYreC3/z0/I59xXMTTTzX/wC//wCXT6nO qdh0/X1PpRPefMDbz/ZuTjqMe/P+c9zjFBzn4zww/vTPn/SOgz+vGfb8OnPQ9RZ+nkep6/XPP+ex 9q5+y8/8OOvr/nr+NdhDZnyjPBP14ycD/Oeef6dfQPYNiH7RB/08k9ufbr+HT6jmuos4YOuOcf59 /wAuDjkA5rl7OG+84wXH6c9v8/pwetdhBZ/9e359+/PbjueOQOe3OdBv2cJhH7jHt9B7DHQYz/8A WzXU2fb/AIFXL2fb/gVdhaQ/89x9P/1flgf/AF65wLE2mnPnwf8AHx/9b8Af/rdhzSWc3k/uJz/p H5nuSen0z3rZs4Z5gPI9ycdT+H0/H2PUH2Pzv3Hkfj0/p+vOcZ560AHMMPuPw6/1/I5PY1YhNxDN 55g+0jPFpyP1H/1hxznNIdMNn1/0n1+1jr/kcj1HFbOm+RN9oME9t/16d/b+X0zQBoWd5PDFmx/0 bp1P0x7Dr+OehGKsQ3k8xME/f6+38/T1zgCq9nDPeXXkf6T9owecfN6/oD6HrwK2PsQh/cX2Pf7J 35OOvXHb0/mAV5rOCb/Uf5x+P4eoHWteGGfyseRxx/x99eSe3v26/wCNmHyIeIP9J9Bd89O3T37c 8enFWBeedF/+vr6H19849vSgCv5MEMXnwf6R149PxP59ulZ80Pnf8fE9ybjr+PXnJOfx+pxnbV+D z/NH2f7T19/f9P1x1qyYYPN/fwfZuhz6/wBOv4dMjjgOcz4YZjL/AMe/2n/Pr9fWi8h87/Xwe/8A ofP+eg45xjv32PJn/wCWH+k2/GO30/8A1Y/xqv5M80Vx5HNvz9su8f7PH9M5x/F1784GPDDPNdeR APb7Xj/jwA5wPT29Pp16CGz/AOWEH1/r3/A5/A1Xhh/5YQfTj9cn9OK6iGH7H/qMf6V0+h478c9P cYXr1AK8umweV5E8P2q56G74z1zyffP09+aIbPMX7/8A0m39eP7T5Pr/AD7nHatCH99/r/8ASsYz +P19e3rjvzVib977dP0/P+tBzmfDNPZ+9ufr3z6HPU9eB+FHkwTS+eB+/wDfqMcdeMYP5nHHHPQf 2bBNHbzzZwP09B+nvjP1JxpvP83/AEeD6YGPbPv2/LOQOAAaM0ME1rwcY9Ofrk4+ua5+XMMvkfzH 6/n+J74NWIYJ5ufPx0H2Qe36/h049+T7HPDLi+gH2fn/ADz9ePXJz0oAx5vP6/Z7nH6Ek9M+3X8a IfP4/D8v/wBf3q2LyHypcwT/AGa3B/0Mcjrxj0I+v5darw+RNKYP/JsA8Z6Y44x2GPwFdB0FeGHz ovPz/o+f+XTrn17+n41Y/wBI87/p3x+H+GP89a0MT3t1mCH7Nb+ueB175H+J6c1Xn8/TftEEHNxx m7OeuOvXgfqPWg5ytqc1j/qIIPs2c/oRgdvy71gQw/8A6/6/4n8BWh5P7q3nuP8A9QI6fgTU/k+d F5/bH/6s49unp0roOcWzs4PKn/5+Pp34H8+aJv3MX+v/ANI6f/r4H+RzitD7JP5XT/SPp26/zqvD pnnSiCc8c5yORj6YB/T0I70AV/sft/49Ve8h+2Re3bpjP6fT0roJoPJjNvjFv6dPr7+3fHfmseGH z/3+R6f3T3z055z/AEFBzhZ2c8OP9IHHT7X/AJ9vxwPSvL/jnpt9e/Bv4oWOlWP/ABONU8B+KLKz +yen9jdPx6fTPfmvYLOz86UQcdx/Lnr249vbitC8hg1LFj/y7c2WM9OvTtz39f0rpg0pRfRNPysm vkB/O/8As3+Kp9N8Uav4N/tW21v7KPsVn9kIxf6X/wBQPrn/ACO2a/TDwfear4cNudKuPtOj/wDP pn/jw/njv6Z/SvzX/aK/Zj+Lfwr+I2saromh+JNb8L2t59s8H+LPD1n/AGl9g0sZ/sHRNcxjHPfp 3we3cfB/9szXPCstvofxM0Ma3b2v+hf2taWROp2H/Yc9OvtzzXlcSZDicyisRhZxS5V7umllHZd7 66JafNn3fCfFmDweHjhsS+SSdlKV7v4bNPTl0Ss7eh+wGg+JNc80ef8A8e/0z3z+H4d+K+iNNvId T0//AD+XIB9R6+vIzXxf8N/i14A8bWFtqvg7Vba5t7vGLS8/5Cdh/wB9DoPfPcY4zX0voOpT+Vbz gH1//XznvjPQ5r8ixWVYzDNxxkZS1aV430urdPnfb52P0zC4+ji3HF4KrDmdvtJ3va+z0Wz6+hBr 2g/vbmf/ABz0+g54+nuc1x9nNfaP+/0q++zXHH+icfp7f1969wvIoNYiz/y8fh056/55rw/xVqVj o8VzPfT/AGb7L/x+C7yevbPH5dsgds14+F+v4bGcuB53eW0eZpax1ST9Vq35nsVFl+YYR0sxhBWV 5Tla7Vle3Mt1ZXV33M/xt+0hpXw30Ya54j8K6lc2/wBs0uyvP+Ee/wA/ifT9a2PB/wC0t8HfGF1b 2Nj4ptrbULq8+xWdrq3/ABLunGfxB7Z98V+U/wC058YIPG39oaH4VvtN/wCEX8L2f/CT6xqt3ef2 b/b3/E6/sHQv7DPXxB/yHPTgc46V8jzTeI5rXR77w5P/AMJL9q0f7beWlpZ6z/xIT/bX9g/jx/6f /QGv33hzKsXict+sZmpNtR5dHfXkS7a6+nyPwHimWW4XM/q+WvmwSerWt5Xi7O3XbZ208j+mibxL 4cmi8+DXNNuf+vS849v5j/8AV0rw6xY+VcT/AG61ube14zz2ODjB+vX39q/mv1H/AITHwra28/jH xHpvhL7UP+QT9s/tLxN/4IvD/Hh/p/zNn/CG+leseA/hj8ePiRdfYfB3hzW9Nt8/6Zq3izWDpv2D P/UD/wCZfx6eLBjPpmvW/seOFjztpXV9W725Y236dPzPk1mOGk3FRbbdk03fWyvvbdvpbbvp++Fn NPFEfPz9puz9tvOfT/Hp3z3rPvLPzuvr0444/l7dCM815v8ABnwf4j8B/D7w/wCFfGXir/hLdYtf +PzVv0/sXv25r1CbyP8AlhOMDPt+GPXv/kCvFOtapPv/AJJ/qfj/AGk3/Pc/T/8AX+WD/wDXrsNN 8/8A18E5+0ep9v8AOOcE81x+mwwck+5/rzj3GefrzwB2Gm/uf3EEH2r7VjAx/n35r0D2D0CzhgmI 8/7NbXF16c8H1+o7E9+fQ7MOmiz+0f8APxx/on9Cfb/Dvmues4YPN4nOfp+f49Pxx9DsQji3/wCf jP8Ax6c9Pb0P45/qAdBZ/vunb+vp1z3z+meK6iEeTDiD6d+f89c9veuP+2QeV5E/2n7Tgf8AHp1O B6DH1/Wup0eC4MXn33t/on5nqO4//XXOdB09nmaPz/P+zW/r3xn9fz9OlX572CHr/M8jGfp2Pr07 dsiY+d1nI6/5/wA/Xr1sQwfven+kf8+mP6H9D9cdjXOAQzQTTfvzdfT1z/n9fy6CzsvOl/48La2y Ov8Anke3GfXnmq8Nn58onnx/+o+np/T6g10H+p/1HHr+ufXPt19qDnK/2y+h/wCW/wBpt/8AP+H1 HX2qxD9omi8+DqefTn9dv4dOTntViibTf3vnZ+zXHGf+n/PT/E9/5UAEMI+1edyOrYwexGc9snPH Pf646jyfPx5/t+GPrkj/APUe1c/DL+9HnwfZuT7n1/z16fUV1FmIIYv3/fnOMfX8hjjjrQAWdnce b+/Bubfv/gf88/SrE1kbyYZ/lz7fT9cj17VzNPx9nuP5+nGR/Eeepzweua0NNhn1KLz54Tbaf3PX 7eM7j6/pjr1oAz5v30tv9hzbW9p/y9n/AJfx07Z7ev49RWhDDiI/uCc4+x2loP5fj168e1a9npsA /wCXgfZ7X/Pcc9TnPrzSzTTw58gdeeMD9OxPI9O2emQDP8mCH/Xz/wAv89euPTvR5P8Az2m9vsn5 9s/09T6VP5MH+v8A+Pq4+n1+p6HH4YPtZ8j3/X/61AFfyfJ/5eM59s9fy9KsQd/x/pRDZ/8ALCD6 /wBe/wCBz+Bqx5Hv+v8A9ag5yzN++it/P/5dbP0+vGfr9R79qTyfOl/A+p6dPw6d8deKrww3E3QY 569Pbtz1/CtDyTk+Qf8AR/16/wAv5e+eADPmh/yf6fzBA9QR3om8+GLj/SfzGf8APr69K0JoRN+4 9PbPPPP49O34daghPk/6QR9pP/Ln06fj2/rQBjQQzzYse46Wl3kY69OnT8PyqxDpsEMX2GDrg/6X 9cYPXHGM8457Eba2LPyIf3E2bn7Vjjj8f6nH8zxVeaGeKLz7Cfg4P2Tqe/4cjj6dMZoAS9ggs/8A UT/af+vQenTsf8frjjA8r7Z+HPT17fj16+3sLEM080pgnH2a4x3zx17e3B6546emhFCftXHXjr+P 5cE+/rwKAK8EJmhME/8Ay6En1z+ufbjnHTirOYIceRb+x9MZ3fz98+2Kv+R7/r/9aq/M0Pufx6f1 /M5Hc0HOHlTen6D/AAqwIYIZT1+0fz/UdPXrxjpiq80M/lc/abb7N69+uOmc9Mc9fzxX877HF+/z x3Ht19en05/A10AY+sfuZbe35+0Yx3Gceo/+vjv9bNnD+68/GT/h16ew/wAgVfhhhmi4z1Pp7due nT2/KtCHyIYrc/Zzj+XIHb9PfFAGfmDTbUeeSLi64wT+WOPbnH04qvAJ4P3/APy8Z5/zx1/+v0rP mnnmusj/AI9/Q+v4dP8AGs+bUbiE9+M57f5P+z+maDnOom1j/nvB9p+vUHGe/X9PXk8V8/8Axh/Z p+HPxg8OaxbwaVpnhvxRdWedH8Q2ln/Zup/2rgf8hz/oYPxP869Q+2wf8t+n8+T/AI4yR6j0qx50 E0J9f1HX8Prj0zmuzDSlreTtfq3Zaade9jyvqz7v8P8AM+H/AIV/Af4SePNCuND8SeDrbwl8WPhx /wAUX4ku/Cd5/wAI1qZ1TH/Ei1r/AIp4H659BjpxXrEPhv44fB8C+8OaqPi1oFpjOk+If+Jb4n9P +Q5j/ioOmAOntmsfxJo/jHQfjx4X8ceAILW5t9es/wCxfiRaXeP7M/svHOtfgOT1/wCRfNfZFnNB NFm+P0598jn/ADjrzipxGEwWKf8AtUfe2Vo33aS07bP1V+h2Zfm2PyuaeHqTklKOjl2avom97aaP zPjfWP8AgoR8HfCujZ8R6H4ktvGFr/oV54TNpjU7DVOep9Pf0/I/E/xD/aL1X9pyLxR/av2bwT4f tdH1TWvDfhP+2P7N/t/S9C0U69rp1zWz78Ef8zp1z6fpR8bP2XfhX8bLXyPFehgayf8Ajz8W6SDp viawIB49zxj/AAHT5Ps/+Ccvg6aK30rVfib4tudH0v8A487W00fRtN7Y6jsc4ODj9DXPl+RZRl2K WI9nGeqavFNK9r6NeXXqz3sfxnmmPwv1WL5G7XnFtNbJ3fn/AF5fnf42+IXwk8SZg8OeHNStre6/ su9svCfh7R/7M0yw1T+xToP/ACHPEHiTxd4n8Qf+Fhj9RXoHw3+D/wAfvi1a29hoeh3Phvw/nS/s erXf/MB0v/if8aH/AODz1zjjoAtfrB4D/ZF+C3wrl8/SvB1treof9BbxDe/2l69P+ZYOOM47de1e 8QXkEP7j/j2gwP8AQ+vv29+v/wCo17WJzjlioYOPLGNkla1krNadn1WlvK+nxbljZS5ptybd5Nu7 e1/M+L/gz+xP4H+G9/p/irxVff8ACSeKLX/Tftf2wf6Bjof7c6fQeEv+EOPNfYGj2djo+n+RZQW2 nW//AD52ln/Zp088dT09asXk3nf6D0GPbt/9bjPUjP1qvPL/AMsMfUfkf/rce1eLXxWKxNpYhuK0 Ss3orK1ter/Ra3PRw2Guk5JJ2T1Vuz/ytv06asnvPJ/2vy9eOmfrVf8Atib0/lWfeTd/p/8AqI/k c/XvXPzan3x+H5cf16fTvXKesfnPZ/uf9f8A6Tn1/H/PGMY79uw02Hzoj5H2U/8A1uD068g+g4/C uH0f/SM+bz16cdPX8v8ADFdPZf6JfWzw/K2Tk9c9PpX0B6B1Nn59nL/pAyMA/r06nnpjj8a6CG88 32/75/r+vTHNYr3Et1fjzm3f6YOcYPatO8/0SO3s7f8AdQeeZdq8HdyOvp3xjrXngb9nN5MvkQf6 TqHX7Z/z4e3tjHoP146iz/0PP2ee5ubi5+vYZ/pnt3965SzRYIk8sbfMGW9+a1Yf+Pv/AD71zgdc ZvJ+z/Zx/pH3ugHv+Iz+uO5NdRZzQQ/Z5/8Al4yP65Pf+XPqO/OWaDOPYn37/wA66OH/AJePwoA6 iz/fdYAPsvr6en16du35aHnQTdOB/k59vTHb2zWHExxb/wCe2T+eOf0xWjsHqf0/woA24fIhl/cZ GePf6/8A7XTp7VY/10vnz8j0/PHGe31/DaapxEjv3b9CB+o6/pitQf8ALD8f6UAEM3m/5/8A1cde 1WDZ/Yov3E/+j/8APpd++f6f5xVnT7eJCFVcDp19/wD636miC3iuPtXmLnZceavOMOO//wBag5yt ZwwaxL5E/wDo0H/L5aXfr0/Tuf8AI6+zE/8Az3xb445zx26g1yCEtMoPrj9M/r0+nFbul3k7WrIW G2MLtGOn60AdH+4hiH+kXH/1/X/I98is68hzn/n3x7Djr2x0PTpz07UxWJlOT/y5Z/T/AOvVyQC6 kuHm+ZgeMce1c4EEP+pH0P8AKtfyfK/H3/z1x79Pzz7Pt/wKn7z6D9f8aALsM3/6v6f4j8RRFD18 /wCuMfz/AJ8/nVaH/XD6n+daEJPmb/4v/wBZ/wA/rXQBZhsjDF/n/wDX9cdDnrjNE3+h/wDHx2/r j1z+vT8K2G+WFSP+Wlmu7k+3Tnj8K5e9/wBbA/8AFHjafTk0ALqU0Fnamf6+2OOO4PP09MZPFY1n eeTdeRPPa/aLr/jz4/Hnn6d/wNbFj/pA3S/M3r0PA/8Ar8+vesxUFr5xhyvmDLZ5Hbp/n60HOWx5 EMXkQf6TwBg9e2fbjuDzmrHneT+//wBG9Pp7+nGffnqDVma3hMZJjXIHp7kf0/U+2KensV1dLQcQ yQiFl7lDgHn1/T2xxXOdA8eRLF584+09Pw/DPPH1/PpXhzD/AKiccHn7Z7/lx+vfNb/iPTrfTYwl oZUU9QXz3HsPU1gJ82M989PbNdBzljzv+WH47f1xj/P071Yh8+aUfL+fOCB68dOvbtRB3/H+lVrr /RYW8n5fLI2556A9aAFvLz/j4/IHP+H9PYe1Y83+myjg4xnPPp79e/U5qxKB5Kf9NB835f54Oalt FG3f/Fx9PyrnAfDCIYsf8vHXsM/j6enpn1omxxBnP2rm8/z656nHbmtiH/l2/wCB0xLS3uYv3sYb 6cdvxroAwprOARf6OOf8OnYc9v8A9Zzy95pvT8s/5/Pn8D0rXS8nXUBbhh5WQNuPp3z/APrrU3n0 H6/40AeeTQ/9u3pnt64/rwfrgUQwziXyP+Pk9cH7o+nHPPr+Q79Nd2sLfMV545+uR6VYjtIGsLYl Tkn19z659aabTunZnOUdNht4Rge2MfTj/A9u2K0Jprfgd89evbt7498+mADnKlY5uOeoJ/IAj+dZ 94x8r8B+uSf5fzrs9q9NNttv8jH2Mf6v/mXJtSnh/wBRnp3H4fn2/oBVmHUoJpf38HHH154P4/hw OOOp477TL5uN36e+P5VqIxZS7ctz+lP20v6t/kc/sY/1f/M7WGa35HfPXp27++PfPrkEYz7yz8// AJYeufb/AAwPTH86z9M/i/z61bvbqf7BKfMb95btC/unTH5fh7VyYrdev6Ik5y0s77/SJ4J/+QoO hx/yCj+vtjp29qLz7d5uZ4P+PX/l76d/8fUcV1EP+t/7cf8AGseft+H9a5D0Djrz9/8A8e856A59 x/n/AD1rAmh86Uj3PX+ff/EV1Os28RmGV/zisCWRj9pBwRhj365+uaAP/9k= ------==--bound.243.web70.yandex.ru-- From wuzhangjin@gmail.com Wed Apr 7 09:38:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 09:38:06 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:38713 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491117Ab0DGHiB (ORCPT ); Wed, 7 Apr 2010 09:38:01 +0200 Received: by pvc30 with SMTP id 30so130142pvc.36 for ; Wed, 07 Apr 2010 00:37:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=ynjpFNLJ08qrQ4TdPqcIHJVIJHlGZztmAmBAdDDm7Qw=; b=GL81vD+k2x9Fiv2+hH/xcGp/OXrytbP7KWqb01l4dzu9AJuqx5jQJZFjv1RlZanv8s qGOZAi8O2sLMbTWyQS8/n+TS11jocVTReV1AXSIMkZ3UZFeD4zLydlYk1V05KeYGr8FF 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References: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> <20100402145401.GS27216@mails.so.argh.org> <1270258975.23702.18.camel@falcon> <20100406191026.GD27216@mails.so.argh.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 07 Apr 2010 15:30:55 +0800 Message-ID: <1270625455.17528.8.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26352 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2010-04-06 at 21:10 +0200, Andreas Barth wrote: [...] > > The kernel vmlinuz-2.6.33-lemote2f-bfs inside of > http://www.anheng.com.cn/loongson/install/loongson2_debian6_20100328.tar.lzma > (linked via linux-loongson-community) fails at the same place: > > touch stamp-picdir > if [ x"-fPIC" != x ]; then \ > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic -fPIC ../../libiberty/regex.c -o pic/regex.o; \ > else true; fi > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic ../../libiberty/regex.c -o regex.o > if [ x"-fPIC" != x ]; then \ > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic -fPIC ../../libiberty/cplus-dem.c -o pic/cplus-dem.o; \ > else true; fi > When & where did you get the above information? do you mean the kernel can not boot or there are some other problems after the kernel booting? I guess: the whole system crashed when you was compiling something? then please ensure the as & ld is ok via fixing the NOPS with the tool (fix-nop.c) from http://dev.lemote.com/code/linux-loongson-community : $ ./fix-nop `which as` $ ./fix-nop `which ld` > > Any other kernel I should try? > The kernel in the above link should boot, or you can compile one yourself. Regards, Wu Zhangjin From wuzhangjin@gmail.com Wed Apr 7 15:04:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 15:04:15 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:50442 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491181Ab0DGNEL (ORCPT ); Wed, 7 Apr 2010 15:04:11 +0200 Received: by pzk16 with SMTP id 16so871892pzk.22 for ; Wed, 07 Apr 2010 06:04:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=1XSstEOTL5ZwyO3JzhtBCUDx32Xs8wDMQ7JEBVH1HHc=; b=eeDiLrBEUMAkcw65df2vw5oiwJWt1XA4JeAfok/VEzlo7kknZfPKKl+ZvCYfsAmL5J rNOoU2w59SRMoV+Ls/jeaoXVBmwJnaQ+g0Nk4BYayhmmow5uXZo73qf+dxMKraJjM8bG nVIaTl0GLsqbJGPwd2L//VKGzJapUbtCetW+g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=cHQxmlViF1XjQN3y8kmkuBtvjkd+CAce9x/Y1CSrZQY8tZWTEOxO/CgdRqYQ9S0LV8 Y89BdxlGvgx0qJdeTFtV4RCnJaaEQqgvwrkm7SM7NpqdXQNLAN1MlvkOs0A+h5UZVKgv j5wP8L6lrv2H0RurrOB+4DyAjkUL5vaIpLw1o= Received: by 10.140.55.12 with SMTP id d12mr7188491rva.208.1270645443505; Wed, 07 Apr 2010 06:04:03 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm1373651pzk.9.2010.04.07.06.03.59 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 06:04:01 -0700 (PDT) Subject: Re: [PATCH v3 3/3] Loongson-2F: Fixup of problems introduced by -mfix-loongson2f-jump of binutils 2.20.1 From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, Shinya Kuribayashi In-Reply-To: <20100317150207.GB4554@linux-mips.org> References: <169f2daa3d623fe56c5b0be30feeda10bc79a478.1268453720.git.wuzhangjin@gmail.com> <20100317150207.GB4554@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 07 Apr 2010 20:57:03 +0800 Message-ID: <1270645023.22802.2.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26353 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2010-03-17 at 16:02 +0100, Ralf Baechle wrote: > On Sat, Mar 13, 2010 at 12:34:17PM +0800, Wu Zhangjin wrote: > > > - /* reboot via jumping to boot base address */ > > + /* reboot via jumping to boot base address > > + * > > + * ".set noat" and ".set at" are used to ensure the address not break > > + * by the -mfix-loongson2f-jump option provided by binutils 2.20.1 (or > > + * higher version) which try to change the jumping address to "addr & > > + * 0xcfffffff" via the at($1) register, this is totally wrong for > > + * 0xbfc00000 (LOONGSON_BOOT_BASE). > > + */ > > + __asm__ __volatile__(".set noat\n"); > > ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); > > + __asm__ __volatile__(".set at\n"); > > Ouch. This is fragile and totally puts the kernels fate at the mercy of > gcc and the ioremap_nocache() implementation. GCC might emit a .set noat > at any time. Something like > > void loongson_restart(char *command) > { > void (*func)(void); > > /* do preparation for reboot */ > mach_prepare_reboot(); > > /* reboot via jumping to boot base address */ > func = (void *) ioremap_nocache(LOONGSON_BOOT_BASE, 4); > > __asm__ __volatile__( > " .set noat \n" > " jr %[func] \n" > " .set at \n" > : /* No outputs */ > : [func] "r" (func)); > } > > should be safe against -mfix-loongson2f-jump I think. Thanks very much, will apply it in the revision of this patch. Regards, Wu Zhangjin From wuzhangjin@gmail.com Wed Apr 7 15:09:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 15:09:44 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:41020 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491195Ab0DGNJk (ORCPT ); Wed, 7 Apr 2010 15:09:40 +0200 Received: by pwj3 with SMTP id 3so904939pwj.36 for ; Wed, 07 Apr 2010 06:09:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=Cu18Q4/gYo4sQE0+/O4bPSe9E1gakvr0bT+nonnmhSI=; b=w4ADRzN1XimoDkYeT3CZZB99ubm2jYt2DtE6vVbkMe2LwjrADpe89c8ZHehiqV7Zco MQnj5+d7IAZaJMGkEdNE7GNHMbLdyzn2v7Xy1YmNjbHdLPIq297+VgG9l8Vxduz10VWO ZrTeKpdIVHF39uTVcgYRA6EUIyIZqQGdU2uWc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=h+hfCMs6S8VjmuM3L0w+1rmk+kHMAKqS9oxeiL+QidIMyoj+lCOt6jUP/nByAhmNA5 5OH82gFOcHJZy6IfohUgPHW5EV927+9Lj9TBJpe4P7KRM/+Jy4IpbPqUnUdIDgTqZxC3 zXa5c3hiNU5qooGaFr6ERpyKW8l84Ya+5fwr0= Received: by 10.141.23.16 with SMTP id a16mr7068670rvj.239.1270645771353; Wed, 07 Apr 2010 06:09:31 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 4sm3968641ywg.9.2010.04.07.06.09.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 06:09:30 -0700 (PDT) Subject: Re: [PATCH v3 2/3] Loongson-2F: Enable fixups of binutils 2.20.1 From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, Shinya Kuribayashi , Zhang Le In-Reply-To: <20100317135223.GA4554@linux-mips.org> References: <20100317135223.GA4554@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 07 Apr 2010 21:02:30 +0800 Message-ID: <1270645350.22802.7.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26354 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2010-03-17 at 14:52 +0100, Ralf Baechle wrote: > On Sat, Mar 13, 2010 at 12:34:16PM +0800, Wu Zhangjin wrote: > > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > > index 2f2eac2..5ae342e 100644 > > --- a/arch/mips/Makefile > > +++ b/arch/mips/Makefile > > @@ -135,7 +135,9 @@ cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap > > cflags-$(CONFIG_CPU_LOONGSON2E) += \ > > $(call cc-option,-march=loongson2e,-march=r4600) > > cflags-$(CONFIG_CPU_LOONGSON2F) += \ > > - $(call cc-option,-march=loongson2f,-march=r4600) > > + $(call cc-option,-march=loongson2f,-march=r4600) \ > > + $(call as-option,-Wa$(comma)-mfix-loongson2f-nop,) \ > > + $(call as-option,-Wa$(comma)-mfix-loongson2f-jump,) > > Shouldn't these options be used unconditionally? It seems a kernel build > should rather fail than a possibly unreliable kernel be built - possibly > even without the user noticing the problem. Thanks for your good suggestion! Just added a new kernel config option: CPU_LOONGSON2F_WORKAROUNDS to allow the users to enable the workarounds for the necessary loongson2f batches and it is enabled by default. And to force the users to use the right binutils with the workarounds, errors will be printed on the standard output with the following stuff: ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) $(error gcc does not support needed option -mfix-loongson2f-nop) else cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa $(comma)-mfix-loongson2f-nop endif Will resend the new patchset with your feedbacks asap. Regards, Wu Zhangjin From wuzhangjin@gmail.com Wed Apr 7 15:19:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 15:19:08 +0200 (CEST) Received: from mail-iw0-f179.google.com ([209.85.223.179]:38241 "EHLO mail-iw0-f179.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491195Ab0DGNTC (ORCPT ); Wed, 7 Apr 2010 15:19:02 +0200 Received: by iwn9 with SMTP id 9so511762iwn.0 for ; Wed, 07 Apr 2010 06:18:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=wW79bNVlvzikJLy0Hs7Y4YPojGmBm75idveX5lbr/FA=; b=YTrh92DR0BqgNKcorC8jxqBlQouDfa0Qsge6zOBSWGHVpKkQZwmOn9piLvTzBbU/MA LRxupBgzCCJoeeNzLRzPXn0ui4KNAWkz1Xk0K6+/g23BtNvP+VsDdZiga9OJbq6UKZN4 4jIXh6jKufcl0t3Xt09vOhTM+KZNr/W0TuNG0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=adI1UpQ4bG0pdXpG4TmO16l/gqMnEuFA0UOz/qIJn2g2rWp8t6rBT9E+ZjM+pcudOR VdoegXXcuEwBJTS/im4hMfYVExychNzWhH1yh1u4psyTbPRCJvjfft3s1UzxlssT8/VB T1N8AiOtQlqIwQv9E/ECeqwvlXon84i24qLIs= Received: by 10.142.59.5 with SMTP id h5mr3393024wfa.185.1270646334897; Wed, 07 Apr 2010 06:18:54 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm3753168pzk.15.2010.04.07.06.18.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 06:18:54 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH v4 0/4] Workaround the Out-of-order Issue of Loongson-2 Date: Wed, 7 Apr 2010 21:11:50 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26355 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin v3->v4: + Incorporated with the feedbacks from Ralf. o add a new kernel config option to allow the users to disable the workarounds for the new loongson2f batches(2F03 and newer). o enable the workarounds unconditionally for the related loongson2f(2F01/02). o use a safer method to fixup the reset issue introduced by the workaround. v2->v3: o Herein, RAS is short for Return Address Stack not Row Address Strobe, at the same time, the "model" in the translation of Chapter 15 should be "mode". (feedback from Shinya Kuribayashi) v1->v2: o Cleanup some comments and align some instructions. ---- As the Chapter 15: "Errata: Issue of Out-of-order in loongson"[1] shows, to workaround the Issue of Loongson-2F，We need to do: o When switching from user mode to kernel mode, you should flush the branch target history such as BTB and RAS. o Doing some tricks to the indirect branch target to make sure that the indirect branch target can not be in the I/O region. This patchset applied the above methods and for the binutils patch[3] have been merged into binutils 2.20.1, so, it's time to upstream this patchset now. without this patch, the machines will hang when the instruction sequence hit the Out-of-order Issue of Loongson-2F, therefore, this patchset is very urgent for both 2.6.33 and 2.6.34. [1] Chinese Version: http://www.loongson.cn/uploadfile/file/20080821113149.pdf [2] English Version of Chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source [3] http://sourceware.org/ml/binutils/2009-11/msg00387.html Wu Zhangjin (4): Loongson: Add CPU_LOONGSON2F_WORKAROUNDS Loongson-2F: Enable fixups of the latest binutils Loongson-2F: Flush the branch target history in BTB and RAS (cont.) Loongson-2F: Fixup of problems introduced by -mfix-loongson2f-jump arch/mips/Kconfig | 26 ++++++++++++++++++++++++++ arch/mips/Makefile | 13 +++++++++++++ arch/mips/include/asm/stackframe.h | 2 +- arch/mips/loongson/common/reset.c | 20 +++++++++++++++++++- 4 files changed, 59 insertions(+), 2 deletions(-) From wuzhangjin@gmail.com Wed Apr 7 15:19:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 15:19:57 +0200 (CEST) Received: from mail-pz0-f180.google.com ([209.85.222.180]:33542 "EHLO mail-pz0-f180.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491195Ab0DGNTx (ORCPT ); Wed, 7 Apr 2010 15:19:53 +0200 Received: by pzk10 with SMTP id 10so883406pzk.21 for ; Wed, 07 Apr 2010 06:19:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=BeZP6ErnTEdxAcr+23gDkE18bDfoDprD3+DXqpwkcNs=; b=F2XeFAhaK2lzQVBszCd7Boiv6W7/6CeaIHfSNwzvo305sG5yN5nuu7NqrF3ZFkB+Eh FB0cacDaAFeHSJqD9HTBNHNEWTvYe05HHoVTCIyjLury8R733qGWWVUczxIPuRe+fxzf QE+L5yreoXMQ8N6YavRbTKjy/5pojigWYTEhg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=UeFagZzk2vD3R96m+UXKL5qq3Ks06PN5V6hN9fluW+0yfWE8cgxjA1gAK1pIyPfl6d VgD3+K4qo9yffRheLS6FVD9fC/k5bwPwyW5pZvNMVGp9mdbJeUmCAXNeSUsreRzIxa7N O1LJ7nNVITIGjYhzeRMfKfO1dVfDnxqb5sSGw= Received: by 10.141.124.16 with SMTP id b16mr7128585rvn.91.1270646385367; Wed, 07 Apr 2010 06:19:45 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm3753168pzk.15.2010.04.07.06.19.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 06:19:45 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH v4 1/4] Loongson: Add CPU_LOONGSON2F_WORKAROUNDS Date: Wed, 7 Apr 2010 21:11:51 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26356 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin As the Loongson2F User Manual[2,3] shows, the old Loongson2F series(2F01/02) have the NOP & JUMP issues, need the related workarounds in the kernel and binutils, but the new Loongson2F series(2F03 and laters) have no such issues, so, none of the workarounds is needed. Currently, the workaround[1] with the -mfix-loongson2f-nop, -mfix-loongson2f-jump options have been added into the latest binutils(in the cvs repository), it's time to add the workarounds in the kernel. The workarounds have no big side effect on the system, but may decrease the performance, therefore, this patch adds a new CPU_LOONGSON2F_WORKAROUNDS config option to allow the users to only enable it for the necessary processor series. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] English Version of the above chapter 15 http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 29e8692..f2ead53 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1305,6 +1305,32 @@ config CPU_CAVIUM_OCTEON endchoice +if CPU_LOONGSON2F +config CPU_NOP_WORKAROUNDS + bool + +config CPU_JUMP_WORKAROUNDS + bool + +config CPU_LOONGSON2F_WORKAROUNDS + bool "Loongson 2F Workarounds" + default y + select CPU_NOP_WORKAROUNDS + select CPU_JUMP_WORKAROUNDS + help + The Loongson 2F01/02 processor has the NOP & JUMP issues, needs the + related workarounds, without workarounds, the system will hang + unexpectedly. to get more information about them, please refer to the + -mfix-loongson2f-nop and -mfix-loongson2f-jump options of gas. + + For Loongson 2F03 and the later batches have fixed the issues, none + of these workarounds needed for them. These workarounds have no big + side effect on them but may decrease the performance of the system, + therefore, it's better to disable this config for them. + + If unsure, please say Y. +endif # CPU_LOONGSON2F + config SYS_SUPPORTS_ZBOOT bool select HAVE_KERNEL_GZIP -- 1.7.0.1 From wuzhangjin@gmail.com Wed Apr 7 15:20:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 15:20:22 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:62138 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492116Ab0DGNT6 (ORCPT ); Wed, 7 Apr 2010 15:19:58 +0200 Received: by pvc30 with SMTP id 30so297049pvc.36 for ; Wed, 07 Apr 2010 06:19:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=ccLDHo8YL/CFeFz74yy3p7YGpPDZlJTgdHodFdiH4PE=; b=OmsIMh2AFStdJkng0GL0rKfZHP77SezpGNWzeDucKMPsLstx3iYIiQfdsvPNvCpBQD NzzjD+sgZ2zqkZi/6DdUY55CItAcoQYj40PRoNpt09VxxeZS61qMH1BWSUPfx/fqdp+C d/OqVvFqqgPd6H5UF7CcEImSHIIay7grdy0Io= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=HFop5Uf1eH8bXIByy+dYnf27TTunFq5lj+VNwWOiZNIFUjakyYTelEzbzQX0eVgUwl jeW9a5R0GcFtkHTd8U8kx+McQ8dzeUVr+KWHUN8dOFs70EAgi7J3kRe5HiavHstE/+ZZ HeQmXnIJAZKGbZg/Deg7ZD8BeEVV+pwe3CvUk= Received: by 10.115.66.26 with SMTP id t26mr8420776wak.210.1270646389464; Wed, 07 Apr 2010 06:19:49 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm3753168pzk.15.2010.04.07.06.19.46 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 06:19:49 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin , Zhang Le Subject: [PATCH v4 2/4] Loongson-2F: Enable fixups of the latest binutils Date: Wed, 7 Apr 2010 21:11:52 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26357 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes from old revision: o Incorporated with the feedbacks from Ralf and used the options introduced from "Loongson: Add CPU_LOONGSON2F_WORKAROUNDS". As the "Fixups of Loongson2F" patch[1] to binutils have been applied into binutils 2.20.1. It's time to enable the options provided by the patch to compile the kernel. Without these fixups, the system will hang unexpectedly for the bug of processor. To learn more about these fixups, please refer to the following references. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] English Version of the above chapter 15 http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Zhang Le Signed-off-by: Wu Zhangjin --- arch/mips/Makefile | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 2f2eac2..14f12bc 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -136,6 +136,19 @@ cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=r4600) cflags-$(CONFIG_CPU_LOONGSON2F) += \ $(call cc-option,-march=loongson2f,-march=r4600) +# enable the workarounds for loongson2f +ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) + $(error gcc does not support needed option -mfix-loongson2f-nop) + else + cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop + endif + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),) + $(error gcc does not support needed option -mfix-loongson2f-jump) + else + cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump + endif +endif cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap -- 1.7.0.1 From wuzhangjin@gmail.com Wed Apr 7 15:20:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 15:20:46 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:59958 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492121Ab0DGNUD (ORCPT ); Wed, 7 Apr 2010 15:20:03 +0200 Received: by pwj3 with SMTP id 3so917462pwj.36 for ; Wed, 07 Apr 2010 06:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=uZWwT2a0zCcz5+9PmRR/o5+evszG5Dxs04VVpLfjHKc=; b=M3LZdhPN0Iaxi8iYfFFCSXys2tTXOJcD/sZgR41VAndpvHypgegKUt0+SILaCWcDn+ PqMnD5RxKomXJF2Pt3kM1T3UdGYaiGRZNBByAswkIf0s4U6AYl/6FQ8r9Boy5oeEg29X Ew+NqRhNnqlCuxhnJMAtj3/x/0v5lmwUTPOs8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=K4rBBPuI01Zs9KjhpmvN/6olaph+7XUctZd4e5TjUkCVthDdzr2igLlsqUSLa8EByr axJoEa+CfJpDUbFhHIvDMaH9qu00sVIWoUewF8nkuvdksgRQ4cgxmoaw5Fi8UHG6tEJD VCLzVr2Wubr9MCoFfRRPkqtwqsRZlgHNn9vr4= Received: by 10.142.209.6 with SMTP id h6mr3286591wfg.11.1270646394142; Wed, 07 Apr 2010 06:19:54 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm3753168pzk.15.2010.04.07.06.19.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 06:19:53 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH v4 3/4] Loongson-2F: Flush the branch target history in BTB and RAS (cont.) Date: Wed, 7 Apr 2010 21:11:53 +0800 Message-Id: <2ec826149b079c1e088c7de5aee41b67d8fab026.1270645413.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26358 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch uses the new option CONFIG_CPU_JUMP_WORKAROUNDS introduced from "Loongson: Add CPU_LOONGSON2F_WORKAROUNDS" to enable the workarounds for the necessary loongson series(2F01/02). Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/stackframe.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index c841912..58730c5 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -121,7 +121,7 @@ .endm #else .macro get_saved_sp /* Uniprocessor variation */ -#ifdef CONFIG_CPU_LOONGSON2F +#ifdef CONFIG_CPU_JUMP_WORKAROUNDS /* * Clear BTB (branch target buffer), forbid RAS (return address * stack) to workaround the Out-of-order Issue in Loongson2F -- 1.7.0.1 From wuzhangjin@gmail.com Wed Apr 7 15:21:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 15:21:10 +0200 (CEST) Received: from mail-iw0-f179.google.com ([209.85.223.179]:53313 "EHLO mail-iw0-f179.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492147Ab0DGNUE (ORCPT ); Wed, 7 Apr 2010 15:20:04 +0200 Received: by iwn9 with SMTP id 9so512980iwn.0 for ; Wed, 07 Apr 2010 06:19:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=VYUmR+Y4s9bws+/rs2pv3MfiLu/dxIYtiWM+i75a2WU=; b=Lmci2zfECtcBBvcAzfUXbBGtFoFRIJFmrQAvFUumxjIuDRqmGzIJWtYfy74I7rYiw8 OFCixeGswaq+VLHsrEb7G/ciyLsOvuPzrydmBD0gPKmlVlfAVHNJ90sYHtUECXEOG4Id mpiiermnMqPe/uGzzlcH/CcHywrWwO/61bYWs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=F24jMXUTBWosYafi6wNfLzOtAMvi1PUOygwIrF3Ngbx45imzue2TBbe05BTn0vcwGB 18QzbWsoP45sq/eqp6GdplOzNhfzvG+3WT4kzu5LGlETA3CqUqXkZgX1cn3rJtpI7sjl uoe9J1ldAu7B67LuY+SHWvjeTbwHnqOdM4xXE= Received: by 10.142.119.20 with SMTP id r20mr3583447wfc.15.1270646398068; Wed, 07 Apr 2010 06:19:58 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm3753168pzk.15.2010.04.07.06.19.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 06:19:57 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH v4 4/4] Loongson-2F: Fixup of problems introduced by -mfix-loongson2f-jump Date: Wed, 7 Apr 2010 21:11:54 +0800 Message-Id: <6fe942386f96dd1ff085e77494100a38ea02b87c.1270645413.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26359 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes from old revisions: o Incorporated with the feedbacks from Ralf Baechle and used the option CONFIG_CPU_JUMP_WORKAROUNDS introduced by "Loongson: Add CPU_LOONGSON2F_WORKAROUNDS". The -mfix-loongson2f-jump option provided by the latest binutils(in the cvs repository) have fixed the Out-of-order Issue of Loongson-2F described in Chapter 15 of "Loongson2F User Manual"[1,2], but introduced some problems. The option changes all of the jumping target to "addr & 0xcfffffff" through the at($1) register, but for the REBOOT address of loongson-2F: 0xbfc00000, this is totally wrong, so, this patch try to avoid the problem via telling the assembler not to use at($1) register. [1] Loongson2F User Manual(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [2] English Version of Chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Reported-and-tested-by: Liu Shiwei Signed-off-by: Wu Zhangjin --- arch/mips/loongson/common/reset.c | 20 +++++++++++++++++++- 1 files changed, 19 insertions(+), 1 deletions(-) diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c index 4bd9c18..9e10d62 100644 --- a/arch/mips/loongson/common/reset.c +++ b/arch/mips/loongson/common/reset.c @@ -16,13 +16,31 @@ #include +static inline void loongson_reboot(void) +{ +#ifndef CONFIG_CPU_JUMP_WORKAROUNDS + ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); +#else + void (*func)(void); + + func = (void *)ioremap_nocache(LOONGSON_BOOT_BASE, 4); + + __asm__ __volatile__( + " .set noat \n" + " jr %[func] \n" + " .set at \n" + : /* No outputs */ + : [func] "r" (func)); +#endif +} + static void loongson_restart(char *command) { /* do preparation for reboot */ mach_prepare_reboot(); /* reboot via jumping to boot base address */ - ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); + loongson_reboot(); } static void loongson_poweroff(void) -- 1.7.0.1 From ralf@linux-mips.org Wed Apr 7 17:35:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 17:35:15 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:34431 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492357Ab0DGPfK (ORCPT ); Wed, 7 Apr 2010 17:35:10 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o37FZ07F024941; Wed, 7 Apr 2010 16:35:00 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o37FYuwt024936; Wed, 7 Apr 2010 16:34:56 +0100 Date: Wed, 7 Apr 2010 16:34:56 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH] MIPS: Alchemy: db1200: remove custom wait implementation Message-ID: <20100407153454.GA24682@linux-mips.org> References: <1270307223-3825-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1270307223-3825-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26360 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Apr 03, 2010 at 05:07:03PM +0200, Manuel Lauss wrote: > While playing with the out-of-tree MAE driver module, the system > would panic after a while in the db1200 custom wait code after > wakeup due to a clobbered k0 register being used as target address > of a store op. > > Remove the custom wait implementation and revert back to the > Alchemy-recommended implementation already set as default. > > Signed-off-by: Manuel Lauss > --- > I've played a few hours worth of video from a SD card now without > a hitch; usually the panic would occur after ~10 minutes. > > Please add this to the 2.6.34 queue, Thanks! Yes, this use of k0 was definately looking fishy - and I'm not talking about the kind of fish in a bouillabaisse ;-) Applied. Thanks! Ralf From ralf@linux-mips.org Wed Apr 7 17:39:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 17:39:54 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:37742 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492398Ab0DGPjv (ORCPT ); Wed, 7 Apr 2010 17:39:51 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o37FdgqY025150; Wed, 7 Apr 2010 16:39:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o37FddpJ025148; Wed, 7 Apr 2010 16:39:39 +0100 Date: Wed, 7 Apr 2010 16:39:39 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels Message-ID: <20100407153937.GA24982@linux-mips.org> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26361 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 06, 2010 at 01:29:50PM -0700, David Daney wrote: > The ebase is relative to CKSEG0 not CAC_BASE. On a 32-bit kernel they > are the same thing, for a 64-bit kernel they are not. > > It happens to kind of work on a 64-bit kernel as they both reference > the same physical memory. However since the CPU uses the CKSEG0 base, > determining if a J instruction will reach always gives the wrong > result unless we use the same number the CPU uses. Applied, thanks! Ralf From wuzhangjin@gmail.com Wed Apr 7 18:13:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 18:13:13 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:37664 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492436Ab0DGQNK (ORCPT ); Wed, 7 Apr 2010 18:13:10 +0200 Received: by pwj3 with SMTP id 3so1126871pwj.36 for ; Wed, 07 Apr 2010 09:13:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=krXE+U+Txk6R9agv/z1OzEWdSMlxtD/P40DwijTNFuQ=; b=ObIkbu/p0aEo8BGhX/Ovn2Gv+cvjHFcuEgyI7rFe/6OXEglRhocB9lhURUDihmyHBM dOCyjIhxfw2lqHzw5KmR64pRxI0Rmfdf+NAiMu31W7cGw74c5N5sq01BSrgB8e6IB0Rf A2wx6nSxtAcO8xYCn58DUowCiOywvl/k2O2hc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=JvXvteaJR/tkI0/LqsFLnDtqiaMDEjsyQB3BinAnjAqUNSK1cd7v2ByskX8KSVRirU 6il4havhjEff4ekhYY7zi4fBUFDv1fTpQsIkgAYFga0dqd+gkY4kLo/RxXd3xW/v+tNV uXyGllBtHsFbmleuZWxalERRSqkSK2wj4I8g4= Received: by 10.141.188.37 with SMTP id q37mr7596827rvp.212.1270656781576; Wed, 07 Apr 2010 09:13:01 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 6sm4027054ywd.8.2010.04.07.09.12.57 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 09:13:00 -0700 (PDT) From: Wu Zhangin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, David Daney , =?UTF-8?q?Ralf=20R=C3=B6sch?= Subject: [PATCH v2 1/3] MIPS: add a common mips_cyc2ns() Date: Thu, 8 Apr 2010 00:05:38 +0800 Message-Id: <9e1889ed5fa23dfaa1ad432ebb4b8f837f6668b4.1270655886.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26362 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes: v1 -> v2: o change the old mips_sched_clock() to mips_cyc2ns() and modify the arguments to support 32bit. o add 32bit support: use a smaller shift to avoid the quick overflow of 64bit arithmatic and balance the overhead of the 128bit arithmatic and the precision lost with the smaller shift. ---------------------- Because the high resolution sched_clock() for r4k has the same overflow problem and solution mentioned in "MIPS: Octeon: Use non-overflowing arithmetic in sched_clock". "With typical mult and shift values, the calculation for Octeon's sched_clock overflows when using 64-bit arithmetic. Use 128-bit calculations instead." To reduce the duplication, This patch abstracts the solution into an inline funciton mips_cyc2ns() into arch/mips/include/asm/time.h from arch/mips/cavium-octeon/csrc-octeon.c. Two patches for Cavium and R4K will be sent out respectively to use this common function. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/time.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 38 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index c7f1bfe..898f0e0 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -96,4 +96,42 @@ static inline void clockevent_set_clock(struct clock_event_device *cd, clockevents_calc_mult_shift(cd, clock, 4); } +static inline unsigned long long mips_cyc2ns(u64 cyc, u64 mult, u64 shift) +{ +#ifdef CONFIG_32BIT + /* + * To balance the overhead of 128bit-arithematic and the precision + * lost, we choose a smaller shift to avoid the quick overflow as the + * X86 & ARM does. please refer to arch/x86/kernel/tsc.c and + * arch/arm/plat-orion/time.c + */ + return (cyc * mult) >> shift; +#else /* CONFIG_64BIT */ + /* 64-bit arithmatic can overflow, so use 128-bit. */ +#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3)) + u64 t1, t2, t3; + unsigned long long rv; + + asm ( + "dmultu\t%[cyc],%[mult]\n\t" + "nor\t%[t1],$0,%[shift]\n\t" + "mfhi\t%[t2]\n\t" + "mflo\t%[t3]\n\t" + "dsll\t%[t2],%[t2],1\n\t" + "dsrlv\t%[rv],%[t3],%[shift]\n\t" + "dsllv\t%[t1],%[t2],%[t1]\n\t" + "or\t%[rv],%[t1],%[rv]\n\t" + : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) + : [cyc] "r" (cyc), [mult] "r" (mult), [shift] "r" (shift) + : "hi", "lo"); + return rv; +#else /* GCC > 4.3 do it the easy way. */ + unsigned int __attribute__((mode(TI))) t = cyc; + + t = (t * mult) >> shift; + return (unsigned long long)t; +#endif +#endif /* CONFIG_64BIT */ +} + #endif /* _ASM_TIME_H */ -- 1.7.0.1 From wuzhangjin@gmail.com Wed Apr 7 18:13:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 18:13:37 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:42063 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492447Ab0DGQNQ (ORCPT ); Wed, 7 Apr 2010 18:13:16 +0200 Received: by pzk16 with SMTP id 16so1089490pzk.22 for ; Wed, 07 Apr 2010 09:13:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=z4uyzgdlL9TTCF51xgAUkZwEaOz/3jZRn7rL994gcFo=; b=TSRqp/66VwlqaPiRyXN0xCG8DEgJYXtoO3EvPmoUwtUe54mplHBt4nSNDKzHKeDSoH Eh4GzmT8sS+xiihHItHkAK7T9CunQMJRTGEsXVPrL9czOIEpsRJ/sewp/ezIdzMPUFPR Cy7V2fE5H5G+m7jlpZz5rVaylkSv8Ep8LOsxM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=xnlOT6SWAfy0kH0yLGvDw4qh3UH5nC8HYFJWAeYmo2pkf76YYUQeTu0YsR+shFlNmd PaiUQzXqljGt69fVGART+NVzh3vrOWiNZY2Iwhry/vqUN4EOXa2O9eHEScTCsuTG80bm QCt/4NQNXkwmSkSU7b8DPCnLw3FbLN+1MvaYs= Received: by 10.114.189.14 with SMTP id m14mr8772645waf.12.1270656787212; Wed, 07 Apr 2010 09:13:07 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 6sm4027054ywd.8.2010.04.07.09.13.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 09:13:06 -0700 (PDT) From: Wu Zhangin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, David Daney , =?UTF-8?q?Ralf=20R=C3=B6sch?= Subject: [PATCH v2 2/3] MIPS: cavium-octeon: rewrite the sched_clock() based on mips_cyc2ns() Date: Thu, 8 Apr 2010 00:05:39 +0800 Message-Id: <503ec883993ca4be3a5680bf52091bf0fcf37357.1270655886.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26363 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes from v1: o use the new interface mips_cyc2ns() intead of the old mips_sched_clock(). The commit "MIPS: add a common mips_cyc2ns()" have abstracted the solution of the 64bit calculation's overflow problem into a common mips_cyc2ns() function in arch/mips/include/asm/time.h, This patch just rewrites the sched_clock() for cavium-octeon on it. Signed-off-by: Wu Zhangjin --- arch/mips/cavium-octeon/csrc-octeon.c | 29 ++--------------------------- 1 files changed, 2 insertions(+), 27 deletions(-) diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c index 0bf4bbe..bca0004 100644 --- a/arch/mips/cavium-octeon/csrc-octeon.c +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -52,34 +52,9 @@ static struct clocksource clocksource_mips = { unsigned long long notrace sched_clock(void) { - /* 64-bit arithmatic can overflow, so use 128-bit. */ -#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3)) - u64 t1, t2, t3; - unsigned long long rv; - u64 mult = clocksource_mips.mult; - u64 shift = clocksource_mips.shift; - u64 cnt = read_c0_cvmcount(); + u64 cyc = read_c0_cvmcount(); - asm ( - "dmultu\t%[cnt],%[mult]\n\t" - "nor\t%[t1],$0,%[shift]\n\t" - "mfhi\t%[t2]\n\t" - "mflo\t%[t3]\n\t" - "dsll\t%[t2],%[t2],1\n\t" - "dsrlv\t%[rv],%[t3],%[shift]\n\t" - "dsllv\t%[t1],%[t2],%[t1]\n\t" - "or\t%[rv],%[t1],%[rv]\n\t" - : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) - : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift) - : "hi", "lo"); - return rv; -#else - /* GCC > 4.3 do it the easy way. */ - unsigned int __attribute__((mode(TI))) t; - t = read_c0_cvmcount(); - t = t * clocksource_mips.mult; - return (unsigned long long)(t >> clocksource_mips.shift); -#endif + return mips_cyc2ns(cyc, clocksource_mips.mult, clocksource_mips.shift); } void __init plat_time_init(void) -- 1.7.0.1 From wuzhangjin@gmail.com Wed Apr 7 18:13:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 18:14:03 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:37664 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492450Ab0DGQNV (ORCPT ); Wed, 7 Apr 2010 18:13:21 +0200 Received: by mail-pw0-f49.google.com with SMTP id 3so1126871pwj.36 for ; Wed, 07 Apr 2010 09:13:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=im+l56aD7iHB6+xllaDIXDdvJ3yHV84D+1e2AxBVrQE=; b=gOrBev1gmQORW5KHiqxX7hXZPUT8lcvKhFtpJTLAa7OvaIpqb7Yr7JT0pPsLSRiI3d EIMgENmVgALJUpWLmptWqdEdlHGM9CVMXADUkENrebJr9W/L81b2DI3iPkZ4bI5f1goY TO7OVbPwUSPeu8L+5kJtKuPCNbXE+cGebpqmQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=BOeJ8QLo9npw6JQ7gQC344CYAIv46l/HLggOyb9L+jfZ+CJdi/AGoQkKnATwmA76n5 d4YF3G6Yvp9xhnxfgGXfVXkYczZJeY9jMKkTnGzrPI2EXuNITXHh1Sv+ZcwrshPGzK/k kPcDH0R8WcvgFIqOEd0Oy+geTKSSHiG1BWqRY= Received: by 10.140.251.8 with SMTP id y8mr177978rvh.231.1270656799691; Wed, 07 Apr 2010 09:13:19 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 6sm4027054ywd.8.2010.04.07.09.13.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 09:13:18 -0700 (PDT) From: Wu Zhangin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, David Daney , =?UTF-8?q?Ralf=20R=C3=B6sch?= Subject: [PATCH v2 3/3] MIPS: r4k: Add a high resolution sched_clock() Date: Thu, 8 Apr 2010 00:05:40 +0800 Message-Id: <17c790c41f4a2eba1accdd31d4bd7a5907493608.1270655886.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26364 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin (v9 -> v10: o use the new interface mips_cyc2ns() instead of the old mips_sched_clock() o adds 32bit support via using a smaller shift to balance the overhead of 128bit arithmatic and the precision lost. please refer to the method used in X86 & ARM platforms, arch/x86/kernel/tsc.c, arch/arm/plat-orion/time.c. v8 -> v9: O Make it depends on 64BIT for the current mips_cyc2ns() only support 64bit currently. v7 -> v8: O Make it works with the exisiting clocksource_mips.mult, clocksource_mips.shift and copes with the 64bit calculation's overflow problem with the method introduced by David Daney in "MIPS: Octeon: Use non-overflowing arithmetic in sched_clock". To reduce the duplication, I have abstracted an inline mips_cyc2ns() function to arch/mips/include/asm/time.h from arch/mips/cavium-octeon/csrc-octeon.c. v6 -> v7: O Make it depends on !CPU_FREQ and CPU_HAS_FIXED_C0_COUNT This sched_clock() is only available with the processor has fixed cp0 MIPS count register or even has dynamic cp0 MIPS count register but with CPU_FREQ disabled. NOTE: If your processor has fixed c0 count, please select CPU_HAS_FIXED_C0_COUNT for it and send a related patch to Ralf. v5 -> v6: o hard-codes the cycle2ns_scale_factor as 8 for 30(cs->shift) is too big. With 30, the return value of sched_clock() will also overflow quickly. o moves the sched_clock() back into csrc-r4k.c as David and Sergei recommended. o inits c0 count as zero for PRINTK_TIME=y. o drops the HR_SCHED_CLCOK option for the current sched_clock() is stable enough to replace the jiffies based one. ) This patch adds a cnt32_to_63() and MIPS c0 count based sched_clock(), which provides high resolution. Without it, the Ftrace for MIPS will give useless timestamp information. Because cnt32_to_63() needs to be called at least once per half period to work properly, Differ from the old version, this v2 revision set up a kernel timer to ensure the requirement of some MIPSs which have short c0 count period. And also, we init the c0 count as ZERO(just as jiffies does) in time_init() before plat_time_init(), without it, PRINTK_TIME=y will get wrong timestamp information. (NOTE: some platforms have initiazlied c0 count as zero, but some not, this may introduce some duplication, perhaps a new patch is needed to remove the initialized of c0 count in the platforms later?) This is originally from arch/arm/plat-orion/time.c This revision works well for function graph tracer now, and also, PRINTK_TIME=y will get normal timestamp informatin. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 12 +++++++ arch/mips/kernel/csrc-r4k.c | 75 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/time.c | 5 +++ 3 files changed, 92 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f2ead53..b302838 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1962,6 +1962,18 @@ config NR_CPUS source "kernel/time/Kconfig" # +# High Resolution sched_clock() support +# + +config CPU_HAS_FIXED_C0_COUNT + bool + +config CPU_SUPPORTS_HR_SCHED_CLOCK + bool + depends on CPU_HAS_FIXED_C0_COUNT || !CPU_FREQ + default y + +# # Timer Interrupt Frequency Configuration # diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index e95a3cd..fa4d763 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -6,7 +6,9 @@ * Copyright (C) 2007 by Ralf Baechle */ #include +#include #include +#include #include @@ -22,6 +24,77 @@ static struct clocksource clocksource_mips = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK +/* + * MIPS sched_clock implementation. + * + * Because the hardware timer period is quite short and because cnt32_to_63() + * needs to be called at least once per half period to work properly, a kernel + * timer is set up to ensure this requirement is always met. + * + * Please refer to include/linux/cnt32_to_63.h, arch/arm/plat-orion/time.c and + * arch/mips/include/asm/time.h (mips_cyc2ns) + */ + +#define CYC2NS_SHIFT 10 +static u64 mult __read_mostly; +static u64 shift __read_mostly; + +unsigned long long notrace sched_clock(void) +{ + u64 cyc = cnt32_to_63(read_c0_count()); + +#ifdef CONFIG_64BIT + /* For we have used 128bit arithmatic to cope with the overflow + * problem, the method to clear the top bit with an event value doesn't + * work now, therefore, clear it at run-time is needed. + */ + if (cyc & 0x8000000000000000) + cyc &= 0x7fffffffffffffff; +#endif + return mips_cyc2ns(cyc, mult, shift); +} + +static struct timer_list cnt32_to_63_keepwarm_timer; + +static void cnt32_to_63_keepwarm(unsigned long data) +{ + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); + sched_clock(); +} +#endif + +static inline void setup_hres_sched_clock(unsigned long clock) +{ +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK + unsigned long data; + +#ifdef CONFIG_32BIT + unsigned long long v; + v = NSEC_PER_SEC; + v <<= CYC2NS_SHIFT; + v += clock/2; + do_div(v, clock); + mult = v; + shift = CYC2NS_SHIFT; + /* + * We want an even value to automatically clear the top bit + * returned by cnt32_to_63() without an additional run time + * instruction. So if the LSB is 1 then round it up. + */ + if (mult & 1) + mult++; +#else + mult = clocksource_mips.mult; + shift = clocksource_mips.shift; +#endif + + data = 0x80000000UL / clock * HZ; + setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); +#endif +} + int __init init_r4k_clocksource(void) { if (!cpu_has_counter || !mips_hpt_frequency) @@ -32,6 +105,8 @@ int __init init_r4k_clocksource(void) clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); + setup_hres_sched_clock(mips_hpt_frequency); + clocksource_register(&clocksource_mips); return 0; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index fb74974..86cf18a 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -119,6 +119,11 @@ static __init int cpu_has_mfc0_count_bug(void) void __init time_init(void) { +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK + if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) + write_c0_count(0); +#endif + plat_time_init(); if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) -- 1.7.0.1 From wuzhangjin@gmail.com Wed Apr 7 18:14:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 18:14:28 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:42063 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492452Ab0DGQNV (ORCPT ); Wed, 7 Apr 2010 18:13:21 +0200 Received: by mail-pz0-f186.google.com with SMTP id 16so1089490pzk.22 for ; Wed, 07 Apr 2010 09:13:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=h1KPBpKQldIhEd5S6o5Iylbw2HMwVgqvDUCRB6cBU2g=; b=Gxf9i3S61C59q1Oo2vZhapwOFeZF51zEFhgT354PKHUraVvbVhkfk1IghmwwHW3sGu Aow+B7RG94jaSS/KS+F15XC8ufy7nbkdfJsvTtsa0ZBUG7h2YEECGAAXsqUZEd3cZdyl GSuAaXn594sx/qkpHGlgVeVcHh49QdC6Lgaew= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=fDZ1tP8cV8o2fLWMuFBh1IM7Enb38w8mMbm7jBBalnMJ3Q9olI9FEhGWIEvfTzaOcZ HSVFX/1goVcHQtalti2LYtQdkbKPaB+v4069nYJgvULeAzdWT2gMNuw1Hlbf1SdyoUcm ANUkUaS4G0oL6gg8EW1yhkE1SF3N7MzMPj2FM= Received: by 10.142.209.17 with SMTP id h17mr3404941wfg.303.1270656773949; Wed, 07 Apr 2010 09:12:53 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 6sm4027054ywd.8.2010.04.07.09.12.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 07 Apr 2010 09:12:52 -0700 (PDT) From: Wu Zhangin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, David Daney , =?UTF-8?q?Ralf=20R=C3=B6sch?= Subject: [PATCH v2 0/3] add high resolution sched_clock() for MIPS Date: Thu, 8 Apr 2010 00:05:37 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26365 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes from old revision: o Adds 32bit support, using a smaller scaling factor(shift) to avoid 128bit arithmatic, of course, it loses some precision. o Adds the testing results of the overhead of sched_clock() in 64bit kernel Clock func/overhead(us) Min Avg Max Jitter Std.Dev. ---------------------------------------------- sched_clock(cnt32_to_63) 105 116.2 236 131 9.5 getnstimeofday() 160 167.1 437 277 15 sched_clock(Accumulation method[1]) 193 200.9 243 50 2.9 ---------------------------------------------- As we can see, the cnt32_to_63() based sched_clock() have lower overhead than the other two. ---------------- This patchset adds a high resolution version of sched_clock() for the r4k MIPS. The generic sched_clock() is jiffies based and has very bad resolution(1ms with HZ set as 1000), this one is based on the r4k c0 count, the resolution reaches about several ns(2.5ns with 400M clock frequency). To cope with the overflow problem of the 32bit c0 count, based on the cnt32_to_63() method in include/linux/cnt32_to_63.h. we have converted the 32bit counter to a virtual 63bit counter. And to fix the overflow problem of the 64bit arithmatic(cycles * mult) in 64bit kernel, we use the 128bit arithmatic contributed by David, but for 32bit kernel, to balance the overhead of 128bit arithmatic and the precision lost, we choose the method used in X86(arch/x86/kernel/tsc.c) and ARM(arch/arm/plat-orion/time.c): just use a smaller scale factor and do 64bit arithmatic, of course, it will also overflow but not that quickly. [1] the algorithm looks like this: static inline unsigned long long notrace read_c0_clock(void) { static u64 clock; static u32 old_clock; u32 current_clock; raw_spin_lock(&clock_lock); current_clock = read_c0_count(); clock += ((current_clock - old_clock) & MASK); old_clock = current_clock; raw_spin_unlock(&clock_lock); return clock; } Regards, Wu Zhangjin Wu Zhangjin (3): MIPS: add a common mips_cyc2ns() MIPS: cavium-octeon: rewrite the sched_clock() based on mips_cyc2ns() MIPS: r4k: Add a high resolution sched_clock() arch/mips/Kconfig | 12 +++++ arch/mips/cavium-octeon/csrc-octeon.c | 28 +----------- arch/mips/include/asm/time.h | 38 +++++++++++++++++ arch/mips/kernel/csrc-r4k.c | 75 +++++++++++++++++++++++++++++++++ arch/mips/kernel/time.c | 5 ++ 5 files changed, 132 insertions(+), 26 deletions(-) From David.Daney@caviumnetworks.com Wed Apr 7 18:49:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 18:49:08 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16882 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492476Ab0DGQtE (ORCPT ); Wed, 7 Apr 2010 18:49:04 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 07 Apr 2010 09:49:15 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 7 Apr 2010 09:48:21 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 7 Apr 2010 09:48:21 -0700 Message-ID: <4BBCB750.3000002@caviumnetworks.com> Date: Wed, 07 Apr 2010 09:48:16 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Wu Zhangin CC: Ralf Baechle , linux-mips@linux-mips.org, =?ISO-8859-1?Q?Ralf_R=F6sch?= Subject: Re: [PATCH v2 1/3] MIPS: add a common mips_cyc2ns() References: <9e1889ed5fa23dfaa1ad432ebb4b8f837f6668b4.1270655886.git.wuzhangjin@gmail.com> In-Reply-To: <9e1889ed5fa23dfaa1ad432ebb4b8f837f6668b4.1270655886.git.wuzhangjin@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 07 Apr 2010 16:48:21.0693 (UTC) FILETIME=[21E7B6D0:01CAD672] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26366 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/07/2010 09:05 AM, Wu Zhangin wrote: > From: Wu Zhangjin > > Changes: > > v1 -> v2: > > o change the old mips_sched_clock() to mips_cyc2ns() and modify the > arguments to support 32bit. > o add 32bit support: use a smaller shift to avoid the quick overflow > of 64bit arithmatic and balance the overhead of the 128bit arithmatic > and the precision lost with the smaller shift. > > ---------------------- > > Because the high resolution sched_clock() for r4k has the same overflow > problem and solution mentioned in "MIPS: Octeon: Use non-overflowing > arithmetic in sched_clock". > > "With typical mult and shift values, the calculation for Octeon's > sched_clock overflows when using 64-bit arithmetic. Use 128-bit > calculations instead." > > To reduce the duplication, This patch abstracts the solution into an > inline funciton mips_cyc2ns() into arch/mips/include/asm/time.h from > arch/mips/cavium-octeon/csrc-octeon.c. > > Two patches for Cavium and R4K will be sent out respectively to use this > common function. > > Signed-off-by: Wu Zhangjin > --- > arch/mips/include/asm/time.h | 38 ++++++++++++++++++++++++++++++++++++++ > 1 files changed, 38 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h > index c7f1bfe..898f0e0 100644 > --- a/arch/mips/include/asm/time.h > +++ b/arch/mips/include/asm/time.h > @@ -96,4 +96,42 @@ static inline void clockevent_set_clock(struct clock_event_device *cd, > clockevents_calc_mult_shift(cd, clock, 4); > } > > +static inline unsigned long long mips_cyc2ns(u64 cyc, u64 mult, u64 shift) > +{ > +#ifdef CONFIG_32BIT > + /* > + * To balance the overhead of 128bit-arithematic and the precision > + * lost, we choose a smaller shift to avoid the quick overflow as the > + * X86& ARM does. please refer to arch/x86/kernel/tsc.c and > + * arch/arm/plat-orion/time.c > + */ > + return (cyc * mult)>> shift; > +#else /* CONFIG_64BIT */ > + /* 64-bit arithmatic can overflow, so use 128-bit. */ > +#if (__GNUC__< 4) || ((__GNUC__ == 4)&& (__GNUC_MINOR__<= 3)) > + u64 t1, t2, t3; > + unsigned long long rv; > + > + asm ( > + "dmultu\t%[cyc],%[mult]\n\t" > + "nor\t%[t1],$0,%[shift]\n\t" > + "mfhi\t%[t2]\n\t" > + "mflo\t%[t3]\n\t" > + "dsll\t%[t2],%[t2],1\n\t" > + "dsrlv\t%[rv],%[t3],%[shift]\n\t" > + "dsllv\t%[t1],%[t2],%[t1]\n\t" > + "or\t%[rv],%[t1],%[rv]\n\t" > + : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) > + : [cyc] "r" (cyc), [mult] "r" (mult), [shift] "r" (shift) > + : "hi", "lo"); > + return rv; > +#else /* GCC> 4.3 do it the easy way. */ > + unsigned int __attribute__((mode(TI))) t = cyc; > + > + t = (t * mult)>> shift; > + return (unsigned long long)t; > +#endif > +#endif /* CONFIG_64BIT */ > +} > + > #endif /* _ASM_TIME_H */ It turns out that all GCC versions can handle the inline asm way. It has also been noted that the default Debian compiler somehow has problems with the 'easy way'. Therefore, I would recommend gitting rid of the GCC version conditionals and just leave the inline asm. David Daney From David.Daney@caviumnetworks.com Wed Apr 7 18:51:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 18:51:06 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16912 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492476Ab0DGQvC (ORCPT ); Wed, 7 Apr 2010 18:51:02 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 07 Apr 2010 09:51:15 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 7 Apr 2010 09:50:52 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 7 Apr 2010 09:50:52 -0700 Message-ID: <4BBCB7EC.5020403@caviumnetworks.com> Date: Wed, 07 Apr 2010 09:50:52 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Wu Zhangin CC: Ralf Baechle , linux-mips@linux-mips.org, =?ISO-8859-1?Q?Ralf_R=F6sch?= Subject: Re: [PATCH v2 1/3] MIPS: add a common mips_cyc2ns() References: <9e1889ed5fa23dfaa1ad432ebb4b8f837f6668b4.1270655886.git.wuzhangjin@gmail.com> In-Reply-To: <9e1889ed5fa23dfaa1ad432ebb4b8f837f6668b4.1270655886.git.wuzhangjin@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 07 Apr 2010 16:50:52.0271 (UTC) FILETIME=[7BA817F0:01CAD672] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26367 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/07/2010 09:05 AM, Wu Zhangin wrote: > From: Wu Zhangjin > > Changes: > > v1 -> v2: > > o change the old mips_sched_clock() to mips_cyc2ns() and modify the > arguments to support 32bit. > o add 32bit support: use a smaller shift to avoid the quick overflow > of 64bit arithmatic and balance the overhead of the 128bit arithmatic > and the precision lost with the smaller shift. > > ---------------------- > > Because the high resolution sched_clock() for r4k has the same overflow > problem and solution mentioned in "MIPS: Octeon: Use non-overflowing > arithmetic in sched_clock". > > "With typical mult and shift values, the calculation for Octeon's > sched_clock overflows when using 64-bit arithmetic. Use 128-bit > calculations instead." > > To reduce the duplication, This patch abstracts the solution into an > inline funciton mips_cyc2ns() into arch/mips/include/asm/time.h from > arch/mips/cavium-octeon/csrc-octeon.c. > > Two patches for Cavium and R4K will be sent out respectively to use this > common function. > > Signed-off-by: Wu Zhangjin > --- > arch/mips/include/asm/time.h | 38 ++++++++++++++++++++++++++++++++++++++ > 1 files changed, 38 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h > index c7f1bfe..898f0e0 100644 > --- a/arch/mips/include/asm/time.h > +++ b/arch/mips/include/asm/time.h > @@ -96,4 +96,42 @@ static inline void clockevent_set_clock(struct clock_event_device *cd, > clockevents_calc_mult_shift(cd, clock, 4); > } > > +static inline unsigned long long mips_cyc2ns(u64 cyc, u64 mult, u64 shift) > +{ > +#ifdef CONFIG_32BIT > + /* > + * To balance the overhead of 128bit-arithematic and the precision > + * lost, we choose a smaller shift to avoid the quick overflow as the > + * X86& ARM does. please refer to arch/x86/kernel/tsc.c and > + * arch/arm/plat-orion/time.c > + */ > + return (cyc * mult)>> shift; Have you tested that on a 32-bit kernel? I think it may overflow for many cases. David Daney From ralf@linux-mips.org Wed Apr 7 19:05:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 19:05:06 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42252 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492489Ab0DGRFD (ORCPT ); Wed, 7 Apr 2010 19:05:03 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o37H4YQr027950; Wed, 7 Apr 2010 18:04:34 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o37H4Wee027927; Wed, 7 Apr 2010 18:04:32 +0100 Date: Wed, 7 Apr 2010 18:04:32 +0100 From: Ralf Baechle To: Julia Lawall Cc: peterz@infradead.org, mingo@elte.hu, tglx@linutronix.de, oleg@redhat.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: Re: [PATCH 4/7] arch/mips/kernel: Use set_cpus_allowed_ptr Message-ID: <20100407170432.GB26242@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26368 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Mar 26, 2010 at 11:03:07PM +0100, Julia Lawall wrote: > From: Julia Lawall > > Use set_cpus_allowed_ptr rather than set_cpus_allowed. Thanks Julia, queued for 2.6.35. Ralf From r0bertz@gentoo.org Wed Apr 7 19:16:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 07 Apr 2010 19:16:52 +0200 (CEST) Received: from smtp.gentoo.org ([140.211.166.183]:47240 "EHLO smtp.gentoo.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491984Ab0DGRQo (ORCPT ); Wed, 7 Apr 2010 19:16:44 +0200 Received: by smtp.gentoo.org (Postfix, from userid 2181) id A32DF1B4026; Wed, 7 Apr 2010 17:16:32 +0000 (UTC) Date: Wed, 7 Apr 2010 17:16:32 +0000 From: Zhang Le To: Wu Zhangjin Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH v4 2/4] Loongson-2F: Enable fixups of the latest binutils Message-ID: <20100407171632.GA1137@woodpecker.gentoo.org> Mail-Followup-To: Wu Zhangjin , Ralf Baechle , linux-mips@linux-mips.org References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26369 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: r0bertz@gentoo.org Precedence: bulk X-list: linux-mips On 21:11 Wed 07 Apr , Wu Zhangjin wrote: > From: Wu Zhangjin > > Changes from old revision: > > o Incorporated with the feedbacks from Ralf and used the options > introduced from "Loongson: Add CPU_LOONGSON2F_WORKAROUNDS". > > As the "Fixups of Loongson2F" patch[1] to binutils have been applied > into binutils 2.20.1. It's time to enable the options provided by the > patch to compile the kernel. > > Without these fixups, the system will hang unexpectedly for the bug of > processor. > > To learn more about these fixups, please refer to the following > references. > > [1] "Fixups of Loongson2F" patch for binutils(actually for gas) > http://sourceware.org/ml/binutils/2009-11/msg00387.html > [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) > http://www.loongson.cn/uploadfile/file/200808211 > [3] English Version of the above chapter 15 > http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source > > Signed-off-by: Zhang Le > Signed-off-by: Wu Zhangjin > --- > arch/mips/Makefile | 13 +++++++++++++ > 1 files changed, 13 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index 2f2eac2..14f12bc 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -136,6 +136,19 @@ cflags-$(CONFIG_CPU_LOONGSON2E) += \ > $(call cc-option,-march=loongson2e,-march=r4600) > cflags-$(CONFIG_CPU_LOONGSON2F) += \ > $(call cc-option,-march=loongson2f,-march=r4600) > +# enable the workarounds for loongson2f > +ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS > + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) > + $(error gcc does not support needed option -mfix-loongson2f-nop) Again, this is an as option. :) So this error msg is a little miss leading. Maybe we should tell user at least which version of binutils is needed. > + else > + cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop > + endif > + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),) > + $(error gcc does not support needed option -mfix-loongson2f-jump) Same here. Zhang, Le > + else > + cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump > + endif > +endif > > cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ > -Wa,-mips32 -Wa,--trap > -- > 1.7.0.1 > From wuzhangjin@gmail.com Thu Apr 8 10:54:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Apr 2010 10:54:58 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:37768 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492215Ab0DHIyz (ORCPT ); Thu, 8 Apr 2010 10:54:55 +0200 Received: by pzk16 with SMTP id 16so151821pzk.22 for ; Thu, 08 Apr 2010 01:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=m8ZBz3rGvtaXCR+EIxwKWDToOdMJvJ10zQr8mkP6W6c=; b=Sp/rVPZb48RwdPhe6Kg9p0JRLflPWvaOSzyLb3xhmUQvDbiFfI1xr15ZrmcMMIJl8S v+Os/zaXMaYWwFjpwscGpmKFFBGVX9d5cYor1wo+CjxbKH6xAemfX0F1AaiSl2IHXG/v Ihds5XNwpyXM52HCJFl3duhd55oz+e+yPaQ+0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=XFROc5WsOSfr9hMA5go82w2yy9mTlIapWo3eyxKnUWZX5YefOFt+XapYTrlrqVW6dX 2ty3NWCcYBBEGylTR+r+GwcmP2el+4uUr/cLuR1W/utaDyzNAY8YVRhnQFlKM7hbgZoG RU/3/cFAiWSAOtc96jsLlQu2jleTH452BNYrU= Received: by 10.140.58.18 with SMTP id g18mr8629607rva.46.1270716887004; Thu, 08 Apr 2010 01:54:47 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm4362589pzk.8.2010.04.08.01.54.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 08 Apr 2010 01:54:46 -0700 (PDT) Subject: Re: [PATCH v4 2/4] Loongson-2F: Enable fixups of the latest binutils From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Zhang Le Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <20100407171632.GA1137@woodpecker.gentoo.org> References: <20100407171632.GA1137@woodpecker.gentoo.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 08 Apr 2010 16:47:51 +0800 Message-ID: <1270716471.5709.3.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26370 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2010-04-07 at 17:16 +0000, Zhang Le wrote: [...] > > +# enable the workarounds for loongson2f > > +ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS > > + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) > > + $(error gcc does not support needed option -mfix-loongson2f-nop) > > Again, this is an as option. :) > So this error msg is a little miss leading. > Maybe we should tell user at least which version of binutils is needed. > hmm, yeah, it's better to tell the users the exact tool here although 'as' is part of the integrated gcc toolchain ;) Thanks & Regards, Wu Zhangjin From wuzhangjin@gmail.com Thu Apr 8 11:39:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Apr 2010 11:39:59 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:59718 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491843Ab0DHJj4 (ORCPT ); Thu, 8 Apr 2010 11:39:56 +0200 Received: by pwj3 with SMTP id 3so1789309pwj.36 for ; Thu, 08 Apr 2010 02:39:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=C7O2d7etTz1VU/R5peusrWABGHUf+r/U2rJPoDjqArg=; b=EqZ8pHTxtk5VITH2K5vBocev97KmACL2A13JpF8z9QrtfwQcTjebTX4r0QbsWUzP1W TO0E1/5uFVEMIeH/iuD7bVzrFg7PxFYiZ1EG5+gT1Fkz8HnTqK5dI9fYb8nYqNFuEF9B gXjChpyEA289rQw5v1txuna4MxIajMGD+7zug= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=kmD7UHCQVEgQ34FdeKRuM8c02AcoFNt3ZgOa2SsOdHfn+ZdhiOwWhfgW6Ac1VEU6fN 4y2jBjXHNwzK4wb8PsLQ/9Huy6vA41PwRV/q9FoAsNMxH9P/OZjdKSrARguSMwb1uKX4 NVmnJvJYjlYu6XCxAb/17kCC4FFk/svU5bqD8= Received: by 10.115.115.9 with SMTP id s9mr9955358wam.66.1270719586583; Thu, 08 Apr 2010 02:39:46 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm3231125pzk.12.2010.04.08.02.39.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 08 Apr 2010 02:39:45 -0700 (PDT) Subject: Re: [PATCH v2 1/3] MIPS: add a common mips_cyc2ns() From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: David Daney Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralf =?ISO-8859-1?Q?R=F6sch?= In-Reply-To: <4BBCB7EC.5020403@caviumnetworks.com> References: <9e1889ed5fa23dfaa1ad432ebb4b8f837f6668b4.1270655886.git.wuzhangjin@gmail.com> <4BBCB7EC.5020403@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 08 Apr 2010 17:32:51 +0800 Message-ID: <1270719171.5709.37.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26371 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2010-04-07 at 09:50 -0700, David Daney wrote: [...] > > +static inline unsigned long long mips_cyc2ns(u64 cyc, u64 mult, u64 shift) > > +{ > > +#ifdef CONFIG_32BIT > > + /* > > + * To balance the overhead of 128bit-arithematic and the precision > > + * lost, we choose a smaller shift to avoid the quick overflow as the > > + * X86& ARM does. please refer to arch/x86/kernel/tsc.c and > > + * arch/arm/plat-orion/time.c > > + */ > > + return (cyc * mult)>> shift; > > Have you tested that on a 32-bit kernel? I think it may overflow for > many cases. > Yes, I have done some basic testing ;) Since a c0 count with 400MHz clock frequency will overflow after about more than 1 hour with the scaling factor 10, I think it is enough for the generic debugging, such as Ftrace, If it is not enough, perhaps we can choose a smaller scaling factor, such as 8. The core idea here is to get a smaller mult to let (cyc * mult) not overflow that quickly but also not get a 'bad' precision, of course, we can try to implement the 128bit arithmatic in 32bit system, but that may increase the overhead(not tested it yet, perhaps will be worse than the original getnstimeofday()). Regards, Wu Zhangjin From wuzhangjin@gmail.com Thu Apr 8 11:43:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Apr 2010 11:43:23 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:35603 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492422Ab0DHJnT (ORCPT ); Thu, 8 Apr 2010 11:43:19 +0200 Received: by pzk16 with SMTP id 16so171297pzk.22 for ; Thu, 08 Apr 2010 02:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=RIK+drH56veJpQFVnSiTetOsCXz26Tb2tQTWCTM2I94=; b=VlEZWPEDZ8QouPQ7JFOf12DKvToCdwoSXrSJEiNNsO0/PgNbEky5FA+++XwUxt7rdB qORJknux2igKXzfSHWi6YXCdmLnR9WzG+OK8NDcl97lu5eZPwTsFiSnBLKjBdUuTbjpf X83hCVmncMCvx7OJUhOdeey5JzS7X8HBSC3Bc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=Utr+btiY9KtyaCsmSJYz+F3a8taLT+uyextUYf4EZCD6ImrOPrvlhb+U886Cc3/AC3 OFGoTI3WaLDxJYt1vip7GClsymULqRDGuzyhxlX/dCP3cnZ/sKhHlXvaGwVuk+tkjx5/ PtofeWAAUc9mTlmfg3frrYP3R3px7RmXnLCXw= Received: by 10.142.122.11 with SMTP id u11mr4214174wfc.227.1270719790973; Thu, 08 Apr 2010 02:43:10 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm2856495pzk.3.2010.04.08.02.43.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 08 Apr 2010 02:43:10 -0700 (PDT) Subject: Re: [PATCH v2 1/3] MIPS: add a common mips_cyc2ns() From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: David Daney Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralf =?ISO-8859-1?Q?R=F6sch?= In-Reply-To: <4BBCB750.3000002@caviumnetworks.com> References: <9e1889ed5fa23dfaa1ad432ebb4b8f837f6668b4.1270655886.git.wuzhangjin@gmail.com> <4BBCB750.3000002@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 08 Apr 2010 17:36:15 +0800 Message-ID: <1270719375.5709.39.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26372 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2010-04-07 at 09:48 -0700, David Daney wrote: [...] > > arch/mips/include/asm/time.h | 38 ++++++++++++++++++++++++++++++++++++++ > > 1 files changed, 38 insertions(+), 0 deletions(-) > > > > diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h > > index c7f1bfe..898f0e0 100644 > > --- a/arch/mips/include/asm/time.h > > +++ b/arch/mips/include/asm/time.h > > @@ -96,4 +96,42 @@ static inline void clockevent_set_clock(struct clock_event_device *cd, > > clockevents_calc_mult_shift(cd, clock, 4); > > } > > > > +static inline unsigned long long mips_cyc2ns(u64 cyc, u64 mult, u64 shift) > > +{ > > +#ifdef CONFIG_32BIT > > + /* > > + * To balance the overhead of 128bit-arithematic and the precision > > + * lost, we choose a smaller shift to avoid the quick overflow as the > > + * X86& ARM does. please refer to arch/x86/kernel/tsc.c and > > + * arch/arm/plat-orion/time.c > > + */ > > + return (cyc * mult)>> shift; > > +#else /* CONFIG_64BIT */ > > + /* 64-bit arithmatic can overflow, so use 128-bit. */ > > +#if (__GNUC__< 4) || ((__GNUC__ == 4)&& (__GNUC_MINOR__<= 3)) > > + u64 t1, t2, t3; > > + unsigned long long rv; > > + > > + asm ( > > + "dmultu\t%[cyc],%[mult]\n\t" > > + "nor\t%[t1],$0,%[shift]\n\t" > > + "mfhi\t%[t2]\n\t" > > + "mflo\t%[t3]\n\t" > > + "dsll\t%[t2],%[t2],1\n\t" > > + "dsrlv\t%[rv],%[t3],%[shift]\n\t" > > + "dsllv\t%[t1],%[t2],%[t1]\n\t" > > + "or\t%[rv],%[t1],%[rv]\n\t" > > + : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) > > + : [cyc] "r" (cyc), [mult] "r" (mult), [shift] "r" (shift) > > + : "hi", "lo"); > > + return rv; > > +#else /* GCC> 4.3 do it the easy way. */ > > + unsigned int __attribute__((mode(TI))) t = cyc; > > + > > + t = (t * mult)>> shift; > > + return (unsigned long long)t; > > +#endif > > +#endif /* CONFIG_64BIT */ > > +} > > + > > #endif /* _ASM_TIME_H */ > > It turns out that all GCC versions can handle the inline asm way. It > has also been noted that the default Debian compiler somehow has > problems with the 'easy way'. > > Therefore, I would recommend gitting rid of the GCC version conditionals > and just leave the inline asm. Ok, will only reserve the asm way in the next revision, thanks! Regards, Wu Zhangjin From geert.uytterhoeven@gmail.com Thu Apr 8 20:52:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Apr 2010 20:52:12 +0200 (CEST) Received: from mail-ww0-f49.google.com ([74.125.82.49]:57417 "EHLO mail-ww0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492185Ab0DHSwH (ORCPT ); Thu, 8 Apr 2010 20:52:07 +0200 Received: by wwg30 with SMTP id 30so214676wwg.36 for ; Thu, 08 Apr 2010 11:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:date :x-google-sender-auth:received:message-id:subject:from:to:cc :content-type; bh=WMOagt+mdMx2BoCLSUYAWpfCTmH/VaFZ0bw0bxBmtt4=; b=wPwzabRM7q/rNqijTFepyCugYGIDQo08KnqcDJysrykJKDfTLbtSo4iPZi+dRuzpbC HrK3X0ih40WNx3c80O0KBm+hIlDdclJKpaYicuDK0Z9YA1Zib232wypATJR7PUKktn7q RGhlErHR0pXFHwSGkBwveqcETi9mM53jIvxEc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type; b=i+6hZfCqQCvwCF3aI8R/HeTwq3Bzhk9N9pJ4ic9xWIMFP5F6PcDMSzSIPsMmVIbWIf 7tnmu0Bn33U7wIDz+DjQ+WSyY4CXxe1wUv4M1jz0IET9/ZbXIuK+xViK0jPKVumzm2pM kM9lRB1V7X9G7FGPLxdqVzFLRMdObeatpMBpQ= MIME-Version: 1.0 Received: by 10.216.28.11 with HTTP; Thu, 8 Apr 2010 11:52:00 -0700 (PDT) Date: Thu, 8 Apr 2010 20:52:00 +0200 X-Google-Sender-Auth: c7a6f56fc1d655d2 Received: by 10.216.91.12 with SMTP id g12mr258131wef.77.1270752720993; Thu, 08 Apr 2010 11:52:00 -0700 (PDT) Message-ID: Subject: [PATCH] mips/txx9: Add missing MODULE_ALIAS definitions for txx9 platform devices From: Geert Uytterhoeven To: Atsushi Nemoto , Ralf Baechle Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26373 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Hi Nemoto-san, Ralf-san, I need the patch below to enable autoloading of the TXx9 sound driver on my RBTX4927. It works very nice as a low-power MPD player. From 0902bacfe10db79472c7ecd35ac28f1c02f72101 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 8 Apr 2010 20:46:28 +0200 Subject: [PATCH] mips/txx9: Add missing MODULE_ALIAS definitions for txx9 platform devices This enables autoloading of the TXx9 sound driver on my RBTX4927. Signed-off-by: Geert Uytterhoeven --- drivers/dma/txx9dmac.c | 2 ++ sound/soc/txx9/txx9aclc-ac97.c | 1 + sound/soc/txx9/txx9aclc-generic.c | 1 + 3 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c index 3ebc610..75fcf1a 100644 --- a/drivers/dma/txx9dmac.c +++ b/drivers/dma/txx9dmac.c @@ -1359,3 +1359,5 @@ module_exit(txx9dmac_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("TXx9 DMA Controller driver"); MODULE_AUTHOR("Atsushi Nemoto "); +MODULE_ALIAS("platform:txx9dmac"); +MODULE_ALIAS("platform:txx9dmac-chan"); diff --git a/sound/soc/txx9/txx9aclc-ac97.c b/sound/soc/txx9/txx9aclc-ac97.c index 612e18b..0ec20b6 100644 --- a/sound/soc/txx9/txx9aclc-ac97.c +++ b/sound/soc/txx9/txx9aclc-ac97.c @@ -254,3 +254,4 @@ module_exit(txx9aclc_ac97_exit); MODULE_AUTHOR("Atsushi Nemoto "); MODULE_DESCRIPTION("TXx9 ACLC AC97 driver"); MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:txx9aclc-ac97"); diff --git a/sound/soc/txx9/txx9aclc-generic.c b/sound/soc/txx9/txx9aclc-generic.c index 3175de9..95b17f7 100644 --- a/sound/soc/txx9/txx9aclc-generic.c +++ b/sound/soc/txx9/txx9aclc-generic.c @@ -96,3 +96,4 @@ module_exit(txx9aclc_generic_exit); MODULE_AUTHOR("Atsushi Nemoto "); MODULE_DESCRIPTION("Generic TXx9 ACLC ALSA SoC audio driver"); MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:txx9aclc-generic"); -- 1.6.0.4 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From anemo@mba.ocn.ne.jp Fri Apr 9 16:27:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Apr 2010 16:27:46 +0200 (CEST) Received: from mv-drv-hcb003.ocn.ad.jp ([118.23.109.133]:38772 "EHLO mv-drv-hcb003.ocn.ad.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491968Ab0DIO1l (ORCPT ); Fri, 9 Apr 2010 16:27:41 +0200 Received: from vcmba.ocn.ne.jp (localhost.localdomain [127.0.0.1]) by mv-drv-hcb003.ocn.ad.jp (Postfix) with ESMTP id 4E1A956421D; Fri, 9 Apr 2010 23:27:35 +0900 (JST) Received: from localhost (softbank221040169135.bbtec.net [221.40.169.135]) by vcmba.ocn.ne.jp (Postfix) with ESMTP; Fri, 9 Apr 2010 23:27:35 +0900 (JST) Date: Fri, 09 Apr 2010 23:27:31 +0900 (JST) Message-Id: <20100409.232731.07635176.anemo@mba.ocn.ne.jp> To: geert@linux-m68k.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] mips/txx9: Add missing MODULE_ALIAS definitions for txx9 platform devices From: Atsushi Nemoto In-Reply-To: References: X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26374 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Thu, 8 Apr 2010 20:52:00 +0200, Geert Uytterhoeven wrote: > I need the patch below to enable autoloading of the TXx9 sound driver > on my RBTX4927. > It works very nice as a low-power MPD player. Thank you, good news. > Subject: [PATCH] mips/txx9: Add missing MODULE_ALIAS definitions for > txx9 platform devices > > This enables autoloading of the TXx9 sound driver on my RBTX4927. > > Signed-off-by: Geert Uytterhoeven Acked-by: Atsushi Nemoto From wuzhangjin@gmail.com Sat Apr 10 07:53:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 07:53:37 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:62637 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491198Ab0DJFxe (ORCPT ); Sat, 10 Apr 2010 07:53:34 +0200 Received: by pzk16 with SMTP id 16so1906936pzk.22 for ; Fri, 09 Apr 2010 22:53:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=/tdnyVjdB6pSd4hkQchcX8/5I9QTxb4uzrrN2Ac6+t0=; b=U/Upc57LVk28iBQX2m3egkmTCjZrjRKq6bAEQeIQ5owDVodVivlRbSJeXkdVodmL+a pgmPaxE2xNufN9vt10W4tITMb9UzmXqNVq8gI5d8IznewSQKaWkSo+CUTXBOqxce0wJb TFz2BZz1xxvmGEKzyNbAgcvCwrG32r7u+JHfc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=enIu3/xcpJviepLAN5r/Vle+yMedhi6QUxN+5qWWw3pJ/M3UqMqazkFSNxvw2hTky8 F5Ihml2IzJa2d0MnJMad8bSAgzA3juLmEl1qTj4nCs7A56FEwyzL1z89f+G5zNQSBOOW VQ82i2N44IgkmQtgOCy+aBQ6hjJ9Ij/jNhr6g= Received: by 10.114.186.40 with SMTP id j40mr1397300waf.93.1270878806187; Fri, 09 Apr 2010 22:53:26 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 23sm1599507pzk.2.2010.04.09.22.53.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 09 Apr 2010 22:53:24 -0700 (PDT) Subject: Re: [PATCH v2 1/3] MIPS: add a common mips_cyc2ns() From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: David Daney Cc: Ralf Baechle , linux-mips@linux-mips.org, Ralf =?ISO-8859-1?Q?R=F6sch?= In-Reply-To: <1270719171.5709.37.camel@falcon> References: <9e1889ed5fa23dfaa1ad432ebb4b8f837f6668b4.1270655886.git.wuzhangjin@gmail.com> <4BBCB7EC.5020403@caviumnetworks.com> <1270719171.5709.37.camel@falcon> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 10 Apr 2010 13:46:29 +0800 Message-ID: <1270878389.17333.39.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26375 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Thu, 2010-04-08 at 17:32 +0800, Wu Zhangjin wrote: > On Wed, 2010-04-07 at 09:50 -0700, David Daney wrote: > [...] > > > +static inline unsigned long long mips_cyc2ns(u64 cyc, u64 mult, u64 shift) > > > +{ > > > +#ifdef CONFIG_32BIT > > > + /* > > > + * To balance the overhead of 128bit-arithematic and the precision > > > + * lost, we choose a smaller shift to avoid the quick overflow as the > > > + * X86& ARM does. please refer to arch/x86/kernel/tsc.c and > > > + * arch/arm/plat-orion/time.c > > > + */ > > > + return (cyc * mult)>> shift; > > > > Have you tested that on a 32-bit kernel? I think it may overflow for > > many cases. > > > > Yes, I have done some basic testing ;) > > Since a c0 count with 400MHz clock frequency will overflow after about > more than 1 hour with the scaling factor 10, Exactly, with 10, it will overflow after counting 2^51, which means it will overflow at 3127 hours(about 130 days), which is enough. > I think it is enough for > the generic debugging, such as Ftrace, If it is not enough, perhaps we > can choose a smaller scaling factor, such as 8. With 8, it will overflow after 12510 hours(about 521 days). So, I will choose 8 in the next revision. PS: ... #include #define NSEC_PER_SEC 1000000000 /* 10^9 */ #define CLOCK_FREQ 400000000 /* 400 M*/ #define CYC2NS_SHIFT 8 int main(void) { unsigned long long mult, v; unsigned long long ullint_max = ~0; unsigned long long tmp = 2ULL<<53; double t_ns; int t_h, t_d; v = NSEC_PER_SEC; v <<= CYC2NS_SHIFT; v += CLOCK_FREQ/2; v = v / CLOCK_FREQ; mult = v; printf("sizeof(unsigned long long): %d\n", sizeof(unsigned long long)); printf("%lld (max of cycles)\n", ullint_max/mult); printf("%lld (2^53)\n", tmp); t_h = (double)tmp / CLOCK_FREQ / 3600; t_d = t_h / 24; printf("%d hours, %d days\n", t_h, t_d); return 0; } $ gcc -o clock clock.c $ $ ./clock sizeof(unsigned long long): 8 28823037615171174 (max of cycles) 18014398509481984 (2^53) 12509 hours, 521 days Regards, Wu Zhangjin From wuzhangjin@gmail.com Sat Apr 10 08:57:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 08:57:13 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:64099 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490984Ab0DJG5J (ORCPT ); Sat, 10 Apr 2010 08:57:09 +0200 Received: by pvc30 with SMTP id 30so2193336pvc.36 for ; Fri, 09 Apr 2010 23:57:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=h+1ydAdbF6itO3lddgYiG6ig8+jb7AYoSAft027qwQw=; b=aoJEmdmkBaMv8MzbxskrM+qtUgC/K97MlA5jIdod3xewTBIOhvM+Sb/a8ZqnOS1h24 EXvrRNzJ2oxhwkfEBcrLpUq9nrqxgj897VodTA2+yRFgRJZqQaCCb53NrN7irAfKGVRg 3uurQc9eoAeryubfPdCjANkLhBs7DnERt4SIg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=iPhQZ9ELyHzexh9WHFcztPHgzEDB+jYGNJlkFyPja8qzn5vrA1lV1PiK3Eqm7QrEY3 jMX7ZJ/JsweMiCAsO3VoChUVUcqzWSX4BCTJoLLTelOvmkME5hbbUYqjm0vwTVo8yfPe 3HadnDPa2aqmZtdsYvShtGBtxUQDb1WwoWahQ= Received: by 10.143.25.3 with SMTP id c3mr724269wfj.17.1270882622843; Fri, 09 Apr 2010 23:57:02 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm1642896pzk.8.2010.04.09.23.57.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 09 Apr 2010 23:57:02 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , David Daney , =?UTF-8?q?Ralf=20R=C3=B6sch?= , linux-mips@linux-mips.org Subject: [PATCH v3 0/3] add high resolution sched_clock() for MIPS Date: Sat, 10 Apr 2010 14:49:56 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26376 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Hi, Ralf, hi David. I have tested it again in the 32bit and 64bit kernel on a Yeeloong netbook, both of them work well. so, it should be applicable now. BTW: to David, if the first two patches are ok for you, could you give a "Acked-by:"? thanks! to Ralf Rösch, does this 32bit version work for you? If yes, welcome your tested-by:, thanks ;) ---------------- Changes: v2 -> v3: o remove the 'easy way' of 128bit arithmatic of mips_cyc2ns(). o use 32bit type instead of 64bit for the input arguments(mult and shift) as the 'struct clocksource' does. o use a smaller scaling factor: 8, with this factor, if the clock frequency is 400MHz, it will overflow after about 521 days. v1 -> v2: o Adds 32bit support, using a smaller scaling factor(shift) to avoid 128bit arithmatic, of course, it loses some precision. o Adds the testing results of the overhead of sched_clock() in 64bit kernel Clock func/overhead(ns) Min Avg Max Jitter Std.Dev. ---------------------------------------------- sched_clock(cnt32_to_63) 105 116.2 236 131 9.5 getnstimeofday() 160 167.1 437 277 15 ---------------------------------------------- As we can see, the cnt32_to_63() based sched_clock() have lower overhead. ---------------- This patchset adds a high resolution version of sched_clock() for the r4k MIPS. The generic sched_clock() is jiffies based and has very bad resolution(1ms with HZ set as 1000), this one is based on the r4k c0 count, the resolution reaches about several ns(2.5ns with 400M clock frequency). To cope with the overflow problem of the 32bit c0 count, based on the cnt32_to_63() method in include/linux/cnt32_to_63.h. we have converted the 32bit counter to a virtual 63bit counter. And to fix the overflow problem of the 64bit arithmatic(cycles * mult) in 64bit kernel, we use the 128bit arithmatic contributed by David, but for 32bit kernel, to balance the overhead of 128bit arithmatic and the precision lost, we choose the method used in X86(arch/x86/kernel/tsc.c) and ARM(arch/arm/plat-orion/time.c): just use a smaller scaling factor and do 64bit arithmatic, of course, it will also overflow but not that quickly. Regards, Wu Zhangjin Wu Zhangjin (3): MIPS: add a common mips_cyc2ns() MIPS: cavium-octeon: rewrite the sched_clock() based on mips_cyc2ns() MIPS: r4k: Add a high resolution sched_clock() arch/mips/Kconfig | 12 +++++ arch/mips/cavium-octeon/csrc-octeon.c | 29 +------------ arch/mips/include/asm/time.h | 34 +++++++++++++++ arch/mips/kernel/csrc-r4k.c | 76 +++++++++++++++++++++++++++++++++ arch/mips/kernel/time.c | 5 ++ 5 files changed, 129 insertions(+), 27 deletions(-) From wuzhangjin@gmail.com Sat Apr 10 08:57:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 08:57:37 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:46800 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491958Ab0DJG5O (ORCPT ); Sat, 10 Apr 2010 08:57:14 +0200 Received: by pwj3 with SMTP id 3so3553431pwj.36 for ; Fri, 09 Apr 2010 23:57:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=sUGNdKEpG7sGQVVJ3fXkT300NAgm2L1rK7C72sHBRXk=; b=Zs9hRiRuTAVOVfhpEu9bA4RuGQu39n62xoQj4VovOmPNrgeLNQNz8H9/zc4QRVQpKX fDq4nk9NgniPGhFJd1m/apMKMz/a1676WVuVOY2tRjOa9flk/fB6CccPOezHqwPO2ilo dv5MS8dV19PXs3SYIMXZ+3PI3DN74Iy8Z+LJw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=tGm6XNJ887GQFjxpdbXxet78vNjQcdio1EpW7VNYwt7whPDnD/mG/TOyjXxme0fBTX c29ZQNbu2llR435x2TuVUb5mUDJ+qYT2J2QCgoPlfVJrBycrVLaC9sq/hy+LeArpwbAn ybgANJnc22kJEa10eE//ARWbaCwaADWq+UkCI= Received: by 10.141.91.7 with SMTP id t7mr1329284rvl.83.1270882626592; Fri, 09 Apr 2010 23:57:06 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm1642896pzk.8.2010.04.09.23.57.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 09 Apr 2010 23:57:05 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , David Daney , =?UTF-8?q?Ralf=20R=C3=B6sch?= , linux-mips@linux-mips.org Subject: [PATCH v3 1/3] MIPS: add a common mips_cyc2ns() Date: Sat, 10 Apr 2010 14:49:57 +0800 Message-Id: <789d123bca6b687f82d43b94feb60066c2160228.1270881177.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26377 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes: v2 -> v3: o use 32bit instead of 64bit for mult and shift as the 'struct clocksource' does, which saves several instructions for the 32bit version of mips_cyc2ns(). o removes the 'easy way' of 128bit arithmatic for it not work with some compilers. (feedback from David) v1 -> v2: o change the old mips_sched_clock() to mips_cyc2ns() and modify the arguments to support 32bit. o add 32bit support: use a smaller shift to avoid the quick overflow of 64bit arithmatic and balance the overhead of the 128bit arithmatic and the precision lost with the smaller shift. ---------------------- Because the high resolution sched_clock() for r4k has the same overflow problem and solution mentioned in "MIPS: Octeon: Use non-overflowing arithmetic in sched_clock". "With typical mult and shift values, the calculation for Octeon's sched_clock overflows when using 64-bit arithmetic. Use 128-bit calculations instead." To reduce the duplication, This patch abstracts the solution into an inline funciton mips_cyc2ns() into arch/mips/include/asm/time.h from arch/mips/cavium-octeon/csrc-octeon.c. Two patches for Cavium and R4K will be sent out respectively to use this common function. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/time.h | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index c7f1bfe..f0ee643 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -96,4 +96,38 @@ static inline void clockevent_set_clock(struct clock_event_device *cd, clockevents_calc_mult_shift(cd, clock, 4); } +static inline unsigned long long mips_cyc2ns(u64 cyc, u32 __mult, u32 __shift) +{ +#ifdef CONFIG_32BIT + /* + * To balance the overhead of 128bit-arithematic and the precision + * lost, we choose a smaller shift to avoid the quick overflow as the + * X86 & ARM does. please refer to arch/x86/kernel/tsc.c and + * arch/arm/plat-orion/time.c + */ + return (cyc * __mult) >> __shift; +#else /* CONFIG_64BIT */ + /* 64-bit arithmatic can overflow, so use 128-bit */ + u64 t1, t2, t3; + unsigned long long rv; + u64 mult, shift; + mult = __mult; + shift = __shift; + + asm ( + "dmultu\t%[cyc],%[mult]\n\t" + "nor\t%[t1],$0,%[shift]\n\t" + "mfhi\t%[t2]\n\t" + "mflo\t%[t3]\n\t" + "dsll\t%[t2],%[t2],1\n\t" + "dsrlv\t%[rv],%[t3],%[shift]\n\t" + "dsllv\t%[t1],%[t2],%[t1]\n\t" + "or\t%[rv],%[t1],%[rv]\n\t" + : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) + : [cyc] "r" (cyc), [mult] "r" (mult), [shift] "r" (shift) + : "hi", "lo"); + return rv; +#endif +} + #endif /* _ASM_TIME_H */ -- 1.7.0.1 From wuzhangjin@gmail.com Sat Apr 10 08:57:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 08:58:02 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:64099 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491978Ab0DJG5Z (ORCPT ); Sat, 10 Apr 2010 08:57:25 +0200 Received: by mail-pv0-f177.google.com with SMTP id 30so2193336pvc.36 for ; Fri, 09 Apr 2010 23:57:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=z4uyzgdlL9TTCF51xgAUkZwEaOz/3jZRn7rL994gcFo=; b=Np3sLDCdrVdvIPP9Q4eXGuGJJuz8PQenU0Kbmlagydvpb0rnk4e4d3zvzdBGtn0WN5 RAmonOSokC/8TfIz/WjxpW8veNMDnQEPqPSug5JuOLG4unfRcT4ggoLhBFJRpLkbn2rq vdkf5KT1py9qMI5ktp5jB1DBD6h4pZcnOnbk8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=VANYhr8CP1qxRHGHKEaLurdVknleCmXw3kQS+xb8M+RrhaFZngUB5nshaLnHH6tG69 t9Rj/UEp9rHYO2Y/j60/o+HuU2VevuJfD6Sq7SFmXJhyGqJ+MJZtBxmWSv3KkSSGIUon dUFN9Ej9lQKs2yJNRoMUD5M4gNW208weLlrow= Received: by 10.140.179.8 with SMTP id b8mr1460572rvf.99.1270882644888; Fri, 09 Apr 2010 23:57:24 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm1642896pzk.8.2010.04.09.23.57.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 09 Apr 2010 23:57:24 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , David Daney , =?UTF-8?q?Ralf=20R=C3=B6sch?= , linux-mips@linux-mips.org Subject: [PATCH v3 2/3] MIPS: cavium-octeon: rewrite the sched_clock() based on mips_cyc2ns() Date: Sat, 10 Apr 2010 14:49:58 +0800 Message-Id: <4e8166375d6fb067115961f1dd28993c5a411d99.1270881177.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26378 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes from v1: o use the new interface mips_cyc2ns() intead of the old mips_sched_clock(). The commit "MIPS: add a common mips_cyc2ns()" have abstracted the solution of the 64bit calculation's overflow problem into a common mips_cyc2ns() function in arch/mips/include/asm/time.h, This patch just rewrites the sched_clock() for cavium-octeon on it. Signed-off-by: Wu Zhangjin --- arch/mips/cavium-octeon/csrc-octeon.c | 29 ++--------------------------- 1 files changed, 2 insertions(+), 27 deletions(-) diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c index 0bf4bbe..bca0004 100644 --- a/arch/mips/cavium-octeon/csrc-octeon.c +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -52,34 +52,9 @@ static struct clocksource clocksource_mips = { unsigned long long notrace sched_clock(void) { - /* 64-bit arithmatic can overflow, so use 128-bit. */ -#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3)) - u64 t1, t2, t3; - unsigned long long rv; - u64 mult = clocksource_mips.mult; - u64 shift = clocksource_mips.shift; - u64 cnt = read_c0_cvmcount(); + u64 cyc = read_c0_cvmcount(); - asm ( - "dmultu\t%[cnt],%[mult]\n\t" - "nor\t%[t1],$0,%[shift]\n\t" - "mfhi\t%[t2]\n\t" - "mflo\t%[t3]\n\t" - "dsll\t%[t2],%[t2],1\n\t" - "dsrlv\t%[rv],%[t3],%[shift]\n\t" - "dsllv\t%[t1],%[t2],%[t1]\n\t" - "or\t%[rv],%[t1],%[rv]\n\t" - : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) - : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift) - : "hi", "lo"); - return rv; -#else - /* GCC > 4.3 do it the easy way. */ - unsigned int __attribute__((mode(TI))) t; - t = read_c0_cvmcount(); - t = t * clocksource_mips.mult; - return (unsigned long long)(t >> clocksource_mips.shift); -#endif + return mips_cyc2ns(cyc, clocksource_mips.mult, clocksource_mips.shift); } void __init plat_time_init(void) -- 1.7.0.1 From wuzhangjin@gmail.com Sat Apr 10 08:58:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 08:58:28 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:46037 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491981Ab0DJG5i (ORCPT ); Sat, 10 Apr 2010 08:57:38 +0200 Received: by pzk16 with SMTP id 16so1923385pzk.22 for ; Fri, 09 Apr 2010 23:57:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=njKXGb5OKpfJfs6Ql5tFnWoJWijw7q+v+Q++a6twIRA=; b=p6rP88nkWbkKmd7Gye2iVWA3cBqDHaDoPLr7f8sdpH02zLd0iSna0Ooy/twvJ3F5B8 QlChVQGK/aQpSaea0ICwvBPPFMwdAM8KcNv/Nw+8ra+wJgMKWIcsUxNtx1oXm+f44Obr Z+vV5B3OysJvUWqjSN84Gr5sOwXGbon0l/lic= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=D+48ZE6RKzOZs9eP5xZrYkLkhbw6sknEPFnMMGXNDACEd3Gh2HszMT7yGFcvg/bxtq JhJP/7OzWnDEjLeOvK8mrjHUEgo9tFEpze/emPsSsZjOioSBSvdE02dpV9DUPUW+H7Pq KUjU6Vy31qXvvuZc/7bHnUdWcruL+HVmYP/os= Received: by 10.115.84.22 with SMTP id m22mr1449759wal.201.1270882650510; Fri, 09 Apr 2010 23:57:30 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm1642896pzk.8.2010.04.09.23.57.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 09 Apr 2010 23:57:29 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , David Daney , =?UTF-8?q?Ralf=20R=C3=B6sch?= , linux-mips@linux-mips.org Subject: [PATCH v3 3/3] MIPS: r4k: Add a high resolution sched_clock() Date: Sat, 10 Apr 2010 14:49:59 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26379 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin (v10 -> v11: o uses 32bit instead of 64bit for mult and shift for the new mips_cyc2ns(). o choose a smaller scaling factor: 8 to ensure it overflows slower. With 8, if the clock frequency is 400 MHz, it will overflow after 12509 hours(about 521 days) which is enough for generic debugging(i.e. Ftrace). o annotate the cnt32_to_63_keepwarm() with notrace. v9 -> v10: o use the new interface mips_cyc2ns() instead of the old mips_sched_clock() o adds 32bit support via using a smaller shift to balance the overhead of 128bit arithmatic and the precision lost. please refer to the method used in X86 & ARM platforms, arch/x86/kernel/tsc.c, arch/arm/plat-orion/time.c. v8 -> v9: O Make it depends on 64BIT for the current mips_cyc2ns() only support 64bit currently. v7 -> v8: O Make it works with the exisiting clocksource_mips.mult, clocksource_mips.shift and copes with the 64bit calculation's overflow problem with the method introduced by David Daney in "MIPS: Octeon: Use non-overflowing arithmetic in sched_clock". To reduce the duplication, I have abstracted an inline mips_cyc2ns() function to arch/mips/include/asm/time.h from arch/mips/cavium-octeon/csrc-octeon.c. v6 -> v7: O Make it depends on !CPU_FREQ and CPU_HAS_FIXED_C0_COUNT This sched_clock() is only available with the processor has fixed cp0 MIPS count register or even has dynamic cp0 MIPS count register but with CPU_FREQ disabled. NOTE: If your processor has fixed c0 count, please select CPU_HAS_FIXED_C0_COUNT for it and send a related patch to Ralf. v5 -> v6: o hard-codes the cycle2ns_scale_factor as 8 for 30(cs->shift) is too big. With 30, the return value of sched_clock() will also overflow quickly. o moves the sched_clock() back into csrc-r4k.c as David and Sergei recommended. o inits c0 count as zero for PRINTK_TIME=y. o drops the HR_SCHED_CLCOK option for the current sched_clock() is stable enough to replace the jiffies based one. ) This patch adds a cnt32_to_63() and MIPS c0 count based sched_clock(), which provides high resolution. Without it, the Ftrace for MIPS will give useless timestamp information. Because cnt32_to_63() needs to be called at least once per half period to work properly, Differ from the old version, this v2 revision set up a kernel timer to ensure the requirement of some MIPSs which have short c0 count period. And also, we init the c0 count as ZERO(just as jiffies does) in time_init() before plat_time_init(), without it, PRINTK_TIME=y will get wrong timestamp information. (NOTE: some platforms have initiazlied c0 count as zero, but some not, this may introduce some duplication, perhaps a new patch is needed to remove the initialized of c0 count in the platforms later?) This is originally from arch/arm/plat-orion/time.c This revision works well for function graph tracer now, and also, PRINTK_TIME=y will get normal timestamp informatin. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 12 +++++++ arch/mips/kernel/csrc-r4k.c | 76 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/time.c | 5 +++ 3 files changed, 93 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f2ead53..b302838 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1962,6 +1962,18 @@ config NR_CPUS source "kernel/time/Kconfig" # +# High Resolution sched_clock() support +# + +config CPU_HAS_FIXED_C0_COUNT + bool + +config CPU_SUPPORTS_HR_SCHED_CLOCK + bool + depends on CPU_HAS_FIXED_C0_COUNT || !CPU_FREQ + default y + +# # Timer Interrupt Frequency Configuration # diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index e95a3cd..92870cb 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -6,7 +6,9 @@ * Copyright (C) 2007 by Ralf Baechle */ #include +#include #include +#include #include @@ -22,6 +24,78 @@ static struct clocksource clocksource_mips = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK +/* + * MIPS sched_clock implementation. + * + * Because the hardware timer period is quite short and because cnt32_to_63() + * needs to be called at least once per half period to work properly, a kernel + * timer is set up to ensure this requirement is always met. + * + * Please refer to include/linux/cnt32_to_63.h, arch/arm/plat-orion/time.c and + * arch/mips/include/asm/time.h (mips_cyc2ns) + */ + +#define CYC2NS_SHIFT 8 +static u32 mult __read_mostly; +static u32 shift __read_mostly; + +unsigned long long notrace sched_clock(void) +{ + u64 cyc = cnt32_to_63(read_c0_count()); + +#ifdef CONFIG_64BIT + /* For we have used 128bit arithmatic to cope with the overflow + * problem, the method to clear the top bit with an event value doesn't + * work now, therefore, clear it at run-time is needed. + */ + if (cyc & 0x8000000000000000) + cyc &= 0x7fffffffffffffff; +#endif + return mips_cyc2ns(cyc, mult, shift); +} + +static struct timer_list cnt32_to_63_keepwarm_timer; + +static void notrace cnt32_to_63_keepwarm(unsigned long data) +{ + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); + sched_clock(); +} +#endif + +static inline void setup_hres_sched_clock(unsigned long clock) +{ +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK + unsigned long data; + +#ifdef CONFIG_32BIT + unsigned long long v; + + v = NSEC_PER_SEC; + v <<= CYC2NS_SHIFT; + v += clock/2; + do_div(v, clock); + mult = v; + shift = CYC2NS_SHIFT; + /* + * We want an even value to automatically clear the top bit + * returned by cnt32_to_63() without an additional run time + * instruction. So if the LSB is 1 then round it up. + */ + if (mult & 1) + mult++; +#else + mult = clocksource_mips.mult; + shift = clocksource_mips.shift; +#endif + + data = 0x80000000UL / clock * HZ; + setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); +#endif +} + int __init init_r4k_clocksource(void) { if (!cpu_has_counter || !mips_hpt_frequency) @@ -32,6 +106,8 @@ int __init init_r4k_clocksource(void) clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); + setup_hres_sched_clock(mips_hpt_frequency); + clocksource_register(&clocksource_mips); return 0; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index fb74974..86cf18a 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -119,6 +119,11 @@ static __init int cpu_has_mfc0_count_bug(void) void __init time_init(void) { +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK + if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) + write_c0_count(0); +#endif + plat_time_init(); if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) -- 1.7.0.1 From aba@not.so.argh.org Sat Apr 10 10:10:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 10:10:54 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:40934 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S2097170Ab0DJIKr (ORCPT ); Sat, 10 Apr 2010 10:10:47 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1O0Vm9-0005IS-Nt; Sat, 10 Apr 2010 08:10:45 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1O0Vm3-0003zU-UL; Sat, 10 Apr 2010 10:10:39 +0200 Date: Sat, 10 Apr 2010 10:10:39 +0200 From: Andreas Barth To: Wu Zhangjin Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH v3 1/3] Loongson-2F: Flush the branch target history such as BTB and RAS Message-ID: <20100410081039.GK27216@mails.so.argh.org> References: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> <20100402145401.GS27216@mails.so.argh.org> <1270258975.23702.18.camel@falcon> <20100406191026.GD27216@mails.so.argh.org> <1270625455.17528.8.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1270625455.17528.8.camel@falcon> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26380 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips * Wu Zhangjin (wuzhangjin@gmail.com) [100407 09:38]: > On Tue, 2010-04-06 at 21:10 +0200, Andreas Barth wrote: > [...] > > > > The kernel vmlinuz-2.6.33-lemote2f-bfs inside of > > http://www.anheng.com.cn/loongson/install/loongson2_debian6_20100328.tar.lzma > > (linked via linux-loongson-community) fails at the same place: > > > > touch stamp-picdir > > if [ x"-fPIC" != x ]; then \ > > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic -fPIC ../../libiberty/regex.c -o pic/regex.o; \ > > else true; fi > > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic ../../libiberty/regex.c -o regex.o > > if [ x"-fPIC" != x ]; then \ > > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic -fPIC ../../libiberty/cplus-dem.c -o pic/cplus-dem.o; \ > > else true; fi > > > > When & where did you get the above information? > > do you mean the kernel can not boot or there are some other problems > after the kernel booting? > > I guess: the whole system crashed when you was compiling something? then > please ensure the as & ld is ok via fixing the NOPS with the tool > (fix-nop.c) from http://dev.lemote.com/code/linux-loongson-community : The kernel does boot, but the whole machines crashes. I know the fixups (I have adjusted binutils), but I need an kernel that userland cannot crash (otherwise it gets a bit hard to run that as debian buildd). Andi From ralf@linux-mips.org Sat Apr 10 12:22:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 12:22:16 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:55699 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492466Ab0DJKWJ (ORCPT ); Sat, 10 Apr 2010 12:22:09 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3AALrPE018741; Sat, 10 Apr 2010 11:21:53 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3AALmoQ018723; Sat, 10 Apr 2010 11:21:48 +0100 Date: Sat, 10 Apr 2010 11:21:48 +0100 From: Ralf Baechle To: Geert Uytterhoeven Cc: Atsushi Nemoto , Linux MIPS Mailing List Subject: Re: [PATCH] mips/txx9: Add missing MODULE_ALIAS definitions for txx9 platform devices Message-ID: <20100410102148.GA23809@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26381 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Apr 08, 2010 at 08:52:00PM +0200, Geert Uytterhoeven wrote: > Hi Nemoto-san, Ralf-san, > > I need the patch below to enable autoloading of the TXx9 sound driver > on my RBTX4927. > It works very nice as a low-power MPD player. > > >From 0902bacfe10db79472c7ecd35ac28f1c02f72101 Mon Sep 17 00:00:00 2001 > From: Geert Uytterhoeven > Date: Thu, 8 Apr 2010 20:46:28 +0200 > Subject: [PATCH] mips/txx9: Add missing MODULE_ALIAS definitions for > txx9 platform devices > > This enables autoloading of the TXx9 sound driver on my RBTX4927. > > Signed-off-by: Geert Uytterhoeven > --- > drivers/dma/txx9dmac.c | 2 ++ > sound/soc/txx9/txx9aclc-ac97.c | 1 + > sound/soc/txx9/txx9aclc-generic.c | 1 + > 3 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c > index 3ebc610..75fcf1a 100644 > --- a/drivers/dma/txx9dmac.c > +++ b/drivers/dma/txx9dmac.c > @@ -1359,3 +1359,5 @@ module_exit(txx9dmac_exit); > MODULE_LICENSE("GPL"); > MODULE_DESCRIPTION("TXx9 DMA Controller driver"); > MODULE_AUTHOR("Atsushi Nemoto "); > +MODULE_ALIAS("platform:txx9dmac"); > +MODULE_ALIAS("platform:txx9dmac-chan"); > diff --git a/sound/soc/txx9/txx9aclc-ac97.c b/sound/soc/txx9/txx9aclc-ac97.c > index 612e18b..0ec20b6 100644 > --- a/sound/soc/txx9/txx9aclc-ac97.c > +++ b/sound/soc/txx9/txx9aclc-ac97.c > @@ -254,3 +254,4 @@ module_exit(txx9aclc_ac97_exit); > MODULE_AUTHOR("Atsushi Nemoto "); > MODULE_DESCRIPTION("TXx9 ACLC AC97 driver"); > MODULE_LICENSE("GPL"); > +MODULE_ALIAS("platform:txx9aclc-ac97"); > diff --git a/sound/soc/txx9/txx9aclc-generic.c > b/sound/soc/txx9/txx9aclc-generic.c > index 3175de9..95b17f7 100644 > --- a/sound/soc/txx9/txx9aclc-generic.c > +++ b/sound/soc/txx9/txx9aclc-generic.c > @@ -96,3 +96,4 @@ module_exit(txx9aclc_generic_exit); > MODULE_AUTHOR("Atsushi Nemoto "); > MODULE_DESCRIPTION("Generic TXx9 ACLC ALSA SoC audio driver"); > MODULE_LICENSE("GPL"); > +MODULE_ALIAS("platform:txx9aclc-generic"); Will apply. A while ago I noticed that all of the MIPS platform device drivers I looked at did not have MODULE_ALIAS(). Ralf From ralf.roesch@rw-gmbh.de Sat Apr 10 12:55:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 12:55:21 +0200 (CEST) Received: from rs1.rw-gmbh.net ([213.239.201.58]:38637 "EHLO rs1.rw-gmbh.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491800Ab0DJKzS (ORCPT ); Sat, 10 Apr 2010 12:55:18 +0200 Received: from pd95181a7.dip0.t-ipconnect.de ([217.81.129.167] helo=[192.168.178.24]) by rs1.rw-gmbh.net with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1O0YLG-0003SR-HI; Sat, 10 Apr 2010 12:55:15 +0200 Message-ID: <4BC0590D.5080305@rw-gmbh.de> Date: Sat, 10 Apr 2010 12:55:09 +0200 From: Ralf Roesch User-Agent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.1.9) Gecko/20100405 Lightning/1.0b1 Icedove/3.0.4 MIME-Version: 1.0 To: Wu Zhangjin CC: Ralf Baechle , David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH v3 0/3] add high resolution sched_clock() for MIPS References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26382 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf.roesch@rw-gmbh.de Precedence: bulk X-list: linux-mips I applied your patch set against tip/rt/2.6.33 (kernel.org) and it works fine on our TX4938 based Fieldbuscontroller which uses the r4k-based timer clocksource. Thanks! (32bit version) tested-by: Ralf Roesch On Sat Apr 10 2010 08:49:56 GMT+0200 (CET), Wu Zhangjin wrote: > From: Wu Zhangjin > > Hi, Ralf, hi David. > > I have tested it again in the 32bit and 64bit kernel on a Yeeloong netbook, > both of them work well. so, it should be applicable now. > > BTW: > > to David, if the first two patches are ok for you, could you give a > "Acked-by:"? thanks! > > to Ralf Rösch, does this 32bit version work for you? If yes, welcome your > tested-by:, thanks ;) > > ---------------- > > Changes: > > v2 -> v3: > > o remove the 'easy way' of 128bit arithmatic of mips_cyc2ns(). > o use 32bit type instead of 64bit for the input arguments(mult and shift) as > the 'struct clocksource' does. > o use a smaller scaling factor: 8, with this factor, if the clock frequency > is 400MHz, it will overflow after about 521 days. > > v1 -> v2: > > o Adds 32bit support, using a smaller scaling factor(shift) to avoid 128bit > arithmatic, of course, it loses some precision. > > o Adds the testing results of the overhead of sched_clock() in 64bit kernel > > Clock func/overhead(ns) Min Avg Max Jitter Std.Dev. > ---------------------------------------------- > sched_clock(cnt32_to_63) 105 116.2 236 131 9.5 > getnstimeofday() 160 167.1 437 277 15 > ---------------------------------------------- > > As we can see, the cnt32_to_63() based sched_clock() have lower overhead. > > ---------------- > > This patchset adds a high resolution version of sched_clock() for the r4k MIPS. > > The generic sched_clock() is jiffies based and has very bad resolution(1ms with > HZ set as 1000), this one is based on the r4k c0 count, the resolution reaches > about several ns(2.5ns with 400M clock frequency). > > To cope with the overflow problem of the 32bit c0 count, based on the > cnt32_to_63() method in include/linux/cnt32_to_63.h. we have converted the > 32bit counter to a virtual 63bit counter. > > And to fix the overflow problem of the 64bit arithmatic(cycles * mult) in 64bit > kernel, we use the 128bit arithmatic contributed by David, but for 32bit > kernel, to balance the overhead of 128bit arithmatic and the precision lost, we > choose the method used in X86(arch/x86/kernel/tsc.c) and > ARM(arch/arm/plat-orion/time.c): just use a smaller scaling factor and do 64bit > arithmatic, of course, it will also overflow but not that quickly. > > Regards, > Wu Zhangjin > > Wu Zhangjin (3): > MIPS: add a common mips_cyc2ns() > MIPS: cavium-octeon: rewrite the sched_clock() based on mips_cyc2ns() > MIPS: r4k: Add a high resolution sched_clock() > > arch/mips/Kconfig | 12 +++++ > arch/mips/cavium-octeon/csrc-octeon.c | 29 +------------ > arch/mips/include/asm/time.h | 34 +++++++++++++++ > arch/mips/kernel/csrc-r4k.c | 76 +++++++++++++++++++++++++++++++++ > arch/mips/kernel/time.c | 5 ++ > 5 files changed, 129 insertions(+), 27 deletions(-) > > From wuzhangjin@gmail.com Sat Apr 10 14:11:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 14:11:53 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:47363 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491997Ab0DJMLu (ORCPT ); Sat, 10 Apr 2010 14:11:50 +0200 Received: by pwj3 with SMTP id 3so3629502pwj.36 for ; Sat, 10 Apr 2010 05:11:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=BeZP6ErnTEdxAcr+23gDkE18bDfoDprD3+DXqpwkcNs=; b=V3xjfkg0id1ZE9YlGCK1ZBFhapFwwgY7YjgKqwey64zHQcYHqDnLxS+d7Mzp+7nEer aXv/BWNPs+rB/6QATwsJbdfB8vDX7ShJKQhflXs2NQJyoPBhiLQIvoTVzVkazn4hDuGL Zh3fXh/NneVCqP3RuQx1ejU+tKwHh4qITbn8M= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=CRpuGGhGuaC5B9VlPZYO5ktJgb1kP7bQLFJWesaPsdOMkKkuHwBz2K+RXTkWGRW+dG IVKFM3+V86ysrHTbE1zoQOsdUfSMX+CW1QWORWu4DQeQfnnWwP6pZ14ADoi1AND+Xm5b 4TBZcXCoBOe8ZwVPvfgg3e8Smq3JkPaajYxFg= Received: by 10.142.202.15 with SMTP id z15mr67167wff.5.1270901498268; Sat, 10 Apr 2010 05:11:38 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 23sm1917842pzk.10.2010.04.10.05.11.36 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 10 Apr 2010 05:11:37 -0700 (PDT) Subject: [PATCH v5 1/4] Loongson: Add CPU_LOONGSON2F_WORKAROUNDS From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips In-Reply-To: References: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 10 Apr 2010 20:04:42 +0800 Message-ID: <1270901082.14758.5.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26383 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin As the Loongson2F User Manual[2,3] shows, the old Loongson2F series(2F01/02) have the NOP & JUMP issues, need the related workarounds in the kernel and binutils, but the new Loongson2F series(2F03 and laters) have no such issues, so, none of the workarounds is needed. Currently, the workaround[1] with the -mfix-loongson2f-nop, -mfix-loongson2f-jump options have been added into the latest binutils(in the cvs repository), it's time to add the workarounds in the kernel. The workarounds have no big side effect on the system, but may decrease the performance, therefore, this patch adds a new CPU_LOONGSON2F_WORKAROUNDS config option to allow the users to only enable it for the necessary processor series. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] English Version of the above chapter 15 http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 29e8692..f2ead53 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1305,6 +1305,32 @@ config CPU_CAVIUM_OCTEON endchoice +if CPU_LOONGSON2F +config CPU_NOP_WORKAROUNDS + bool + +config CPU_JUMP_WORKAROUNDS + bool + +config CPU_LOONGSON2F_WORKAROUNDS + bool "Loongson 2F Workarounds" + default y + select CPU_NOP_WORKAROUNDS + select CPU_JUMP_WORKAROUNDS + help + The Loongson 2F01/02 processor has the NOP & JUMP issues, needs the + related workarounds, without workarounds, the system will hang + unexpectedly. to get more information about them, please refer to the + -mfix-loongson2f-nop and -mfix-loongson2f-jump options of gas. + + For Loongson 2F03 and the later batches have fixed the issues, none + of these workarounds needed for them. These workarounds have no big + side effect on them but may decrease the performance of the system, + therefore, it's better to disable this config for them. + + If unsure, please say Y. +endif # CPU_LOONGSON2F + config SYS_SUPPORTS_ZBOOT bool select HAVE_KERNEL_GZIP -- 1.7.0.1 From wuzhangjin@gmail.com Sat Apr 10 14:12:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 14:12:20 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:60848 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492477Ab0DJML6 (ORCPT ); Sat, 10 Apr 2010 14:11:58 +0200 Received: by mail-pz0-f186.google.com with SMTP id 16so2000855pzk.22 for ; Sat, 10 Apr 2010 05:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=39D3lx1KBDd3UluliAiQdprKo7n7w7ulj9Im38jDR2Q=; b=OgpifkOWRJuwCp82A3B0ggrnm4K8b73ORx+ks2zYP514vHROHLpT8zW9zxKCh91hti cyJsfDcg/EOVuTsxFTMmKeys4LKEiXAweFqxmlNwwxqgXL5I1PouINxVQgHj74TFalsv 3SzulRE64IgWmHmo2uKQdo5z55d0qgoRTMOtM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=XCeYbEHwuyFgduLaebz+2dQ4n3UGv5GR5U4WZdF6gBWv4NvNM8R3YBqCZaelraiW0c bzbVMNOPoLzUGzuu8R1WUmO2OQnHBl5rcK//MjTDfAIHqMAu4VZxronymt9ymSYYHqRT WwG3ON7Z4ViF/I5tHty57paJIKcm90xUnEzaE= Received: by 10.141.105.16 with SMTP id h16mr1439470rvm.274.1270901517364; Sat, 10 Apr 2010 05:11:57 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 23sm1925678pzk.6.2010.04.10.05.11.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 10 Apr 2010 05:11:56 -0700 (PDT) Subject: [PATCH v5 2/4] Loongson-2F: Enable fixups of the latest binutils From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Wu Zhangjin , Zhang Le , linux-mips In-Reply-To: References: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 10 Apr 2010 20:05:01 +0800 Message-ID: <1270901101.14758.6.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26384 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes from old revision: o Clear the errror information as suggesttion from Zhang Le. o Incorporated with the feedbacks from Ralf and used the options introduced from "Loongson: Add CPU_LOONGSON2F_WORKAROUNDS". As the "Fixups of Loongson2F" patch[1] to binutils have been applied into binutils 2.20.1. It's time to enable the options provided by the patch to compile the kernel. Without these fixups, the system will hang unexpectedly for the bug of processor. To learn more about these fixups, please refer to the following references. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] English Version of the above chapter 15 http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Zhang Le Signed-off-by: Wu Zhangjin --- arch/mips/Makefile | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 2f2eac2..0b9c01a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -136,6 +136,19 @@ cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=r4600) cflags-$(CONFIG_CPU_LOONGSON2F) += \ $(call cc-option,-march=loongson2f,-march=r4600) +# enable the workarounds for loongson2f +ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) + $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop) + else + cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop + endif + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),) + $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump) + else + cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump + endif +endif cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap -- 1.7.0.1 From wuzhangjin@gmail.com Sat Apr 10 14:12:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 14:12:44 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:60848 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491997Ab0DJMMQ (ORCPT ); Sat, 10 Apr 2010 14:12:16 +0200 Received: by mail-pz0-f186.google.com with SMTP id 16so2000855pzk.22 for ; Sat, 10 Apr 2010 05:12:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=BeZP6ErnTEdxAcr+23gDkE18bDfoDprD3+DXqpwkcNs=; b=L3Xbf1TUDQi8nUL6vu28ffNtiPu0vdGE/xS6Xu6THM3y6bedNjJSB/wOckq3Qvr+A2 G6o1ia6xnOkxeFQSKAYBQnuVkqHrbd1LPJVHQok8hh1yC9vepcHrApsgkU9OGmrhmt7/ 1Ndl4EZejFFulJ5qmYBwGN7cSZ/7WKknU4vUY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=IJFB6SZinccx3VDTunz715TnDowFGJGHADqLfRq2K7r2aEzn5KlIoZbIJ3FVwKKqCr +ajDCT1AdLYqL4lxn44PQnDjTcI9Jrs/2xNUvH0NISDOzQ+KAjapVvu5JesLUQCzhKZ0 yDBsu+7+JykdMh1K2/U/G4t8DEMcghwVj9XmE= Received: by 10.115.39.40 with SMTP id r40mr1474811waj.183.1270901535638; Sat, 10 Apr 2010 05:12:15 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 23sm1916989pzk.14.2010.04.10.05.12.13 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 10 Apr 2010 05:12:14 -0700 (PDT) Subject: [PATCH v5 1/4] Loongson: Add CPU_LOONGSON2F_WORKAROUNDS From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Wu Zhangjin , linux-mips In-Reply-To: References: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 10 Apr 2010 20:05:20 +0800 Message-ID: <1270901120.14758.7.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26385 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin As the Loongson2F User Manual[2,3] shows, the old Loongson2F series(2F01/02) have the NOP & JUMP issues, need the related workarounds in the kernel and binutils, but the new Loongson2F series(2F03 and laters) have no such issues, so, none of the workarounds is needed. Currently, the workaround[1] with the -mfix-loongson2f-nop, -mfix-loongson2f-jump options have been added into the latest binutils(in the cvs repository), it's time to add the workarounds in the kernel. The workarounds have no big side effect on the system, but may decrease the performance, therefore, this patch adds a new CPU_LOONGSON2F_WORKAROUNDS config option to allow the users to only enable it for the necessary processor series. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] English Version of the above chapter 15 http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 29e8692..f2ead53 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1305,6 +1305,32 @@ config CPU_CAVIUM_OCTEON endchoice +if CPU_LOONGSON2F +config CPU_NOP_WORKAROUNDS + bool + +config CPU_JUMP_WORKAROUNDS + bool + +config CPU_LOONGSON2F_WORKAROUNDS + bool "Loongson 2F Workarounds" + default y + select CPU_NOP_WORKAROUNDS + select CPU_JUMP_WORKAROUNDS + help + The Loongson 2F01/02 processor has the NOP & JUMP issues, needs the + related workarounds, without workarounds, the system will hang + unexpectedly. to get more information about them, please refer to the + -mfix-loongson2f-nop and -mfix-loongson2f-jump options of gas. + + For Loongson 2F03 and the later batches have fixed the issues, none + of these workarounds needed for them. These workarounds have no big + side effect on them but may decrease the performance of the system, + therefore, it's better to disable this config for them. + + If unsure, please say Y. +endif # CPU_LOONGSON2F + config SYS_SUPPORTS_ZBOOT bool select HAVE_KERNEL_GZIP -- 1.7.0.1 From wuzhangjin@gmail.com Sat Apr 10 14:14:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 14:14:08 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:44749 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491997Ab0DJMOE (ORCPT ); Sat, 10 Apr 2010 14:14:04 +0200 Received: by pvc30 with SMTP id 30so2248782pvc.36 for ; Sat, 10 Apr 2010 05:13:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=uZWwT2a0zCcz5+9PmRR/o5+evszG5Dxs04VVpLfjHKc=; b=b1tgRysBjl4VX8756cZfyA8y3g+CovFXMHcdWAqJo6mKNTNoOSUxuft46w92bkEvxe VjJpKBZ8aX6l0k/IgQfGgZzbIwgjisJR3boycOhsMCOKrp+guJ55mN7LgR2gvnD0ijqX ML714sibTsZbNad1IORe/ONcbQdtsiJFKJ2gk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=EDrpJLr1Bnq4/0uDo/0vTuxXp9ucwfL5mEkB4MLxnoemMdmXmcs7mD7P8yk1CBg2tL r1MPvwLXiUpj5uAaCbVc0hi0TiXfoRE3iMpx9QuPojeAq/NcrhFiMUWwcUvSPwk1pDou /tWpr7nUFvJ08aqEfy+VWZfaOKajp5R9QKLBA= Received: by 10.115.116.5 with SMTP id t5mr1607018wam.77.1270901637537; Sat, 10 Apr 2010 05:13:57 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm1922863pzk.9.2010.04.10.05.13.54 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 10 Apr 2010 05:13:56 -0700 (PDT) Subject: [PATCH v5 3/4] Loongson-2F: Flush the branch target history in BTB and RAS (cont.) From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Wu Zhangjin , linux-mips In-Reply-To: References: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 10 Apr 2010 20:07:01 +0800 Message-ID: <1270901221.14758.8.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26386 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch uses the new option CONFIG_CPU_JUMP_WORKAROUNDS introduced from "Loongson: Add CPU_LOONGSON2F_WORKAROUNDS" to enable the workarounds for the necessary loongson series(2F01/02). Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/stackframe.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index c841912..58730c5 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -121,7 +121,7 @@ .endm #else .macro get_saved_sp /* Uniprocessor variation */ -#ifdef CONFIG_CPU_LOONGSON2F +#ifdef CONFIG_CPU_JUMP_WORKAROUNDS /* * Clear BTB (branch target buffer), forbid RAS (return address * stack) to workaround the Out-of-order Issue in Loongson2F -- 1.7.0.1 From wuzhangjin@gmail.com Sat Apr 10 14:14:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Apr 2010 14:14:32 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:50328 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492579Ab0DJMOS (ORCPT ); Sat, 10 Apr 2010 14:14:18 +0200 Received: by pwj3 with SMTP id 3so3630144pwj.36 for ; Sat, 10 Apr 2010 05:14:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=VYUmR+Y4s9bws+/rs2pv3MfiLu/dxIYtiWM+i75a2WU=; b=CmrcKTBSwJ14H15wB1GfrdJzkh+KzaJYRHn3emNfMF4v4wgi9oU2IDOKHvxSVJk3Wx o6TH8TeAT+svRYTGMrGwybRNfAw0LiMJuSnSn4n4uqzhS7wAJaMA4/yKXrcN+YNydwox ofNQ+C8KmHey2aH2to1Sn4qVBd5cCNGl0Khkw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=qPqr4EqNAR03hInrKkK+J7KtOqrhqD/4vIPp2+vaeM+tareVUhvZXIlQmYTOA277RR 7FIYv4v9WOuqTiIvcxxn7+NWA4e7wC6ueQdC1OuWm/VynRJelDXgydbDUnQ9Y1P4QndK sXtJZUfibc0Lnh7bEkgulFTUxtskr/m4hATKI= Received: by 10.115.24.9 with SMTP id b9mr1434585waj.83.1270901649508; Sat, 10 Apr 2010 05:14:09 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm1923058pzk.9.2010.04.10.05.14.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 10 Apr 2010 05:14:09 -0700 (PDT) Subject: [PATCH v5 4/4] Loongson-2F: Fixup of problems introduced by -mfix-loongson2f-jump From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Wu Zhangjin , linux-mips In-Reply-To: References: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 10 Apr 2010 20:07:13 +0800 Message-ID: <1270901233.14758.9.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26387 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes from old revisions: o Incorporated with the feedbacks from Ralf Baechle and used the option CONFIG_CPU_JUMP_WORKAROUNDS introduced by "Loongson: Add CPU_LOONGSON2F_WORKAROUNDS". The -mfix-loongson2f-jump option provided by the latest binutils(in the cvs repository) have fixed the Out-of-order Issue of Loongson-2F described in Chapter 15 of "Loongson2F User Manual"[1,2], but introduced some problems. The option changes all of the jumping target to "addr & 0xcfffffff" through the at($1) register, but for the REBOOT address of loongson-2F: 0xbfc00000, this is totally wrong, so, this patch try to avoid the problem via telling the assembler not to use at($1) register. [1] Loongson2F User Manual(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [2] English Version of Chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Reported-and-tested-by: Liu Shiwei Signed-off-by: Wu Zhangjin --- arch/mips/loongson/common/reset.c | 20 +++++++++++++++++++- 1 files changed, 19 insertions(+), 1 deletions(-) diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c index 4bd9c18..9e10d62 100644 --- a/arch/mips/loongson/common/reset.c +++ b/arch/mips/loongson/common/reset.c @@ -16,13 +16,31 @@ #include +static inline void loongson_reboot(void) +{ +#ifndef CONFIG_CPU_JUMP_WORKAROUNDS + ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); +#else + void (*func)(void); + + func = (void *)ioremap_nocache(LOONGSON_BOOT_BASE, 4); + + __asm__ __volatile__( + " .set noat \n" + " jr %[func] \n" + " .set at \n" + : /* No outputs */ + : [func] "r" (func)); +#endif +} + static void loongson_restart(char *command) { /* do preparation for reboot */ mach_prepare_reboot(); /* reboot via jumping to boot base address */ - ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); + loongson_reboot(); } static void loongson_poweroff(void) -- 1.7.0.1 From wuzhangjin@gmail.com Mon Apr 12 05:35:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Apr 2010 05:35:07 +0200 (CEST) Received: from mail-yx0-f200.google.com ([209.85.210.200]:53604 "EHLO mail-yx0-f200.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491197Ab0DLDfD (ORCPT ); Mon, 12 Apr 2010 05:35:03 +0200 Received: by yxe38 with SMTP id 38so1871395yxe.22 for ; Sun, 11 Apr 2010 20:34:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=zh72fpVOCjDaNrxDkh4Dnio0mk1NNBZd53oS8Gk4UbI=; b=AF8IndCrw4oKDVutp68vldwlIAEa8eqd/kpKG1u8TE7zaIK5YHgKfEPh7uwqGjU2zj qkgRtLlLaLosNIlFsf1JmBGfZbGkTzXTEjAvmyOjZerx4N9/hIkzKvrlWMewrTgsKpJx U4JH8uTHi0H9BvWpKmLaebI/33+KnscMr5jvE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=FjDuh/JFlYyAYXcciKybqu7T2amlverhDx5sEjhz5dMsdJ+y6ZnohQaSl50PNGnWuL GhEOoVmJ7djNZxZOMOcvzzTYY/Wg2F9tSXW3KA0p0KjeYWm1pgnSoLZhTU6XfMKCjFWt twuTeqoRATwQEmujvwjDsVtmnv21vGqVlW24g= Received: by 10.100.88.10 with SMTP id l10mr5558083anb.184.1271043296063; Sun, 11 Apr 2010 20:34:56 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm3630818iwn.3.2010.04.11.20.34.52 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 11 Apr 2010 20:34:54 -0700 (PDT) Subject: Re: [PATCH v3 1/3] Loongson-2F: Flush the branch target history such as BTB and RAS From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Andreas Barth Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <20100410081039.GK27216@mails.so.argh.org> References: <05e2ba2596f23fa4dda64d63ce2480504b1be4ac.1268453720.git.wuzhangjin@gmail.com> <20100402145401.GS27216@mails.so.argh.org> <1270258975.23702.18.camel@falcon> <20100406191026.GD27216@mails.so.argh.org> <1270625455.17528.8.camel@falcon> <20100410081039.GK27216@mails.so.argh.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Mon, 12 Apr 2010 11:33:59 +0800 Message-ID: <1271043239.1917.11.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26388 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Sat, 2010-04-10 at 10:10 +0200, Andreas Barth wrote: > * Wu Zhangjin (wuzhangjin@gmail.com) [100407 09:38]: > > On Tue, 2010-04-06 at 21:10 +0200, Andreas Barth wrote: > > [...] > > > > > > The kernel vmlinuz-2.6.33-lemote2f-bfs inside of > > > http://www.anheng.com.cn/loongson/install/loongson2_debian6_20100328.tar.lzma > > > (linked via linux-loongson-community) fails at the same place: > > > > > > touch stamp-picdir > > > if [ x"-fPIC" != x ]; then \ > > > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic -fPIC ../../libiberty/regex.c -o pic/regex.o; \ > > > else true; fi > > > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic ../../libiberty/regex.c -o regex.o > > > if [ x"-fPIC" != x ]; then \ > > > gcc -c -DHAVE_CONFIG_H -g -O2 -I. -I../../libiberty/../include -W -Wall -Wwrite-strings -Wc++-compat -Wstrict-prototypes -pedantic -fPIC ../../libiberty/cplus-dem.c -o pic/cplus-dem.o; \ > > > else true; fi > > > > > > > When & where did you get the above information? > > > > do you mean the kernel can not boot or there are some other problems > > after the kernel booting? > > > > I guess: the whole system crashed when you was compiling something? then > > please ensure the as & ld is ok via fixing the NOPS with the tool > > (fix-nop.c) from http://dev.lemote.com/code/linux-loongson-community : > > The kernel does boot, but the whole machines crashes. > > I know the fixups (I have adjusted binutils), but I need an kernel > that userland cannot crash (otherwise it gets a bit hard to run that > as debian buildd). > > The userland canot be prevented from crash without user-space fixups, that's why we need the fix-nop.c to fix the NOPs in the binaries of user-land applications or using the -mfix-loongson-nop to compile the user-land applications. If you just need to rebuild debian, you just need to fix the NOPs in the as and ld with fix-nop.c as I have mentioned before: $ ./fix-nop $(which as) $ ./fix-nop $(which ld) Regards, Wu Zhangjin From wuzhangjin@gmail.com Tue Apr 13 06:59:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 06:59:14 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:56688 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491118Ab0DME7J (ORCPT ); Tue, 13 Apr 2010 06:59:09 +0200 Received: by gyb11 with SMTP id 11so3428674gyb.36 for ; Mon, 12 Apr 2010 21:59:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :content-type:organization:date:message-id:mime-version:x-mailer; bh=4gS7GDD/9POeqiat1zoOSfMguQjiM7NXQQm4hMi2wbg=; b=DJpnHkdMfYENDcYaM1sQJDY0PTYhveiuXQMYtDcLUzMCvt/if/h4uyyG6w1Ojvu8bN 7j/BOn7KwChVyzYlZsYnV/3mKQTq5Zh0OIormYGjJVM3KrsL5yA2xD+rXCMYFEZEdm92 GjXg6DUfNxcRXbKyeBXgxot1jcTjB85Jxv2Y0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:content-type:organization:date :message-id:mime-version:x-mailer; b=MnKBNuD8coSbO/iM37HhnaApcSAnk6V2IDmO6YjtzQShZegcTL+x2eBDmz/B0AQvBi 4yETfAInC3Nns76uDhNais1bXzcB+kktkPcaowK1PWzB/9VeKZDxscLit7aHZRXD7c4b IPnvGoRV0c9/AbJBtBmr+KTl3nfvXHU1WMquA= Received: by 10.91.39.4 with SMTP id r4mr2327601agj.107.1271134741915; Mon, 12 Apr 2010 21:59:01 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm4591294iwn.1.2010.04.12.21.58.59 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 12 Apr 2010 21:59:01 -0700 (PDT) Subject: About MIPS specific dma_mmap_coherent() From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle , Takashi Iwai Cc: linux-mips Content-Type: multipart/mixed; boundary="=-MOmtyQD51rQcYat/yaYI" Organization: DSLab, Lanzhou University, China Date: Tue, 13 Apr 2010 12:58:54 +0800 Message-ID: <1271134735.25797.35.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26389 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips --=-MOmtyQD51rQcYat/yaYI Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Hi, Ralf and Takashi Seems Takashi have sent the MIPS specific dma_mmap_coherent() at 18 Aug 2008: http://www.linux-mips.org/archives/linux-mips/2008-08/msg00178.html But that patch have not been accepted since it was not suitable to all of the MIPS variants. Without that patch, the ALSA output will be broken in some of the MIPS variants, can we make the implementation in the above url be weak, then the particular MIPS variants can override it with their own versions but the common MIPS variants can share it to fix the ALSA problem? I have attached a change of the above patch, which is applicable to the linux-2.6.33 and linux-2.6.34-rcX and I have tested it on my YeeLoong netbook, the following command function well with it. $ mplayer -ao alsa file.mp3 but without it, the ALSA output is broken. Regards, Wu Zhangjin --=-MOmtyQD51rQcYat/yaYI Content-Disposition: attachment; filename*0=0001-MIPS-Implement-dma_mmap_coherent-for-ALSA-audio-outp.pat; filename*1=ch Content-Type: text/x-patch; name="0001-MIPS-Implement-dma_mmap_coherent-for-ALSA-audio-outp.patch"; charset="UTF-8" Content-Transfer-Encoding: 7bit From a6ee304febbd609d2936dd5b33a16482ef224c97 Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Sun, 11 Apr 2010 03:58:13 +0800 Subject: [PATCH] MIPS: Implement dma_mmap_coherent() for ALSA audio output A lazy version of dma_mmap_coherent() implementation for MIPS. Without this patch, the ALSA sound output of MIPS is broken: $ mplayer -ao alsa file.mp3 (This patch was sent out by Takashi Iwai at '18 Aug 2008' but not have been applied yet for it is not suitable for all MIPS variants. If you need more info, please access: http://www.linux-mips.org/archives/linux-mips/2008-08/msg00178.html) Signed-off-by: Takashi Iwai --- arch/mips/include/asm/dma-mapping.h | 4 ++++ arch/mips/mm/dma-default.c | 13 +++++++++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 664ba53..c39bfdf 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -74,4 +74,8 @@ extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr); extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction); +#define ARCH_HAS_DMA_MMAP_COHERENT +extern int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, + void *cpu_addr, dma_addr_t handle, size_t size); + #endif /* _ASM_DMA_MAPPING_H */ diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 9547bc0..8388428 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -375,3 +375,16 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, } EXPORT_SYMBOL(dma_cache_sync); + +int __weak dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, + void *cpu_addr, dma_addr_t handle, size_t size) +{ + struct page *pg; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + cpu_addr = (void *)dma_addr_to_virt(dev, handle); + pg = virt_to_page(cpu_addr); + return remap_pfn_range(vma, vma->vm_start, + page_to_pfn(pg) + vma->vm_pgoff, + size, vma->vm_page_prot); +} +EXPORT_SYMBOL(dma_mmap_coherent); -- 1.7.0 --=-MOmtyQD51rQcYat/yaYI-- From wuzhangjin@gmail.com Tue Apr 13 07:04:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 07:04:17 +0200 (CEST) Received: from mail-yx0-f200.google.com ([209.85.210.200]:47813 "EHLO mail-yx0-f200.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491118Ab0DMFEJ (ORCPT ); Tue, 13 Apr 2010 07:04:09 +0200 Received: by yxe38 with SMTP id 38so2520735yxe.22 for ; Mon, 12 Apr 2010 22:04:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:x-priority:content-type:organization:date :message-id:mime-version:x-mailer:content-transfer-encoding; bh=VCIsg488Y94CsX4qRUs4W4d8c5HkkeO/d7gARqWJld0=; b=Rxh67ftAozcSC4uTfV98nEAHebGmyLZhjDM//IwEYr/AdV6tOGgyJOD2+8OZaNi7ju Lk0sF8voTTeLOEUgqhCk7ipphdbWU/j73EuyidmZosog3jRn6Sxmlwyn9arc1aLI9ACd psZAbriIgH6rOm5JHrV60puMG4Ec7d7IjcHI0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:x-priority :content-type:organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=aN+V5A//CUw80reeTqZyEcc4YLAiJ/Og58zSWDgZv97Zm8U+xoUCOYTmkYxVH9Xith 1p+Hrj611nSiH8l020RBPe3bgb1i7QS2YMHnXaF0tRpT8GfaDAD/Q5SdT1LLNVAlaRw+ n4SVmf/IcvPsQm4RAKbUScmCXi08gqueSZeT8= Received: by 10.150.103.12 with SMTP id a12mr4356880ybc.112.1271135041714; Mon, 12 Apr 2010 22:04:01 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm4595766iwn.4.2010.04.12.22.03.58 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 12 Apr 2010 22:04:00 -0700 (PDT) Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org In-Reply-To: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> X-Priority: 1 Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Tue, 13 Apr 2010 13:03:54 +0800 Message-ID: <1271135034.25797.41.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, David and Ralf This patch have broken the support to the MIPS variants whose cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different in these MIPSs. With the patch, the kernel will exit when booting(later after trap_init()). A potential patch to fix the above problem is: diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 1a4dd65..d8cb554 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1599,7 +1599,7 @@ void __init trap_init(void) ebase = (unsigned long) __alloc_bootmem(size, 1 << fls(size), 0); } else { - ebase = CKSEG0; + ebase = (cpu_has_mips_r2) ? CKSEG0 : CAC_BASE; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); } Regards, Wu Zhangjin On Tue, 2010-04-06 at 13:29 -0700, David Daney wrote: > The ebase is relative to CKSEG0 not CAC_BASE. On a 32-bit kernel they > are the same thing, for a 64-bit kernel they are not. > > It happens to kind of work on a 64-bit kernel as they both reference > the same physical memory. However since the CPU uses the CKSEG0 base, > determining if a J instruction will reach always gives the wrong > result unless we use the same number the CPU uses. > > Signed-off-by: David Daney > --- > arch/mips/kernel/traps.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index 7ce84bb..b122f76 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -1706,7 +1706,7 @@ void __init trap_init(void) > ebase = (unsigned long) > __alloc_bootmem(size, 1 << fls(size), 0); > } else { > - ebase = CAC_BASE; > + ebase = CKSEG0; > if (cpu_has_mips_r2) > ebase += (read_c0_ebase() & 0x3ffff000); > } From wuzhangjin@gmail.com Tue Apr 13 07:16:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 07:17:00 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:34883 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491118Ab0DMFQz (ORCPT ); Tue, 13 Apr 2010 07:16:55 +0200 Received: by pwj4 with SMTP id 4so1409453pwj.36 for ; Mon, 12 Apr 2010 22:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=rqsLiZC6AB6BNuGZ5mJsCMmlcAVD36zT8K7cQAcK6FY=; b=SuV3aHXGLaKELd33pdy3gt2zpIZRkT62Gv104KsQRmKOeaRCu+mVCoKD/8hHx25mIR o2MtTb+JkS0EeYYuJKzyMM6MVrvk/rlNFpxwVSE2rxS8XWZ6UEzCFRpKACVmTW83kYiZ GxolCWbR0/aY3Z5GyxvgDWA7zUKF/fLQ5Mczk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=yC7VtMg10/5z82MH2ve4Kc8lz5wJVBzB3RMIdc8IinzNcy2CixDwl8TR968ZJlvvWw J32nmwmpn2rufpbxHB0nb5le/HVOWgEhGB8di10+hbUfHPGXvbHRVDvJ7eCAXPgAL4mO lbY2I7EzbhqmqPP0x+HqMkR5xTddtjpPV2e+g= Received: by 10.142.1.41 with SMTP id 41mr2277724wfa.289.1271135806948; Mon, 12 Apr 2010 22:16:46 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm4619421iwn.7.2010.04.12.22.16.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 12 Apr 2010 22:16:46 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: Linux-MIPS , Wu Zhangjin Subject: [PATCH] Loongson: update cpu-feature-overrides.h Date: Tue, 13 Apr 2010 13:16:34 +0800 Message-Id: <1271135794-19762-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts (cpu_has_vint) and MIPSR2 external interrupt controller mode (cpu_has_veic) are 0. Signed-off-by: Wu Zhangjin --- .../asm/mach-loongson/cpu-feature-overrides.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 16210ce..675bd86 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -52,6 +52,8 @@ #define cpu_has_tx39_cache 0 #define cpu_has_userlocal 0 #define cpu_has_vce 0 +#define cpu_has_veic 0 +#define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 -- 1.7.0 From tsbogend@alpha.franken.de Tue Apr 13 09:35:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 09:35:04 +0200 (CEST) Received: from elvis.franken.de ([193.175.24.41]:33446 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491900Ab0DMHfA (ORCPT ); Tue, 13 Apr 2010 09:35:00 +0200 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1O1aeB-00077x-00; Tue, 13 Apr 2010 09:34:59 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 2694E1D2DE; Tue, 13 Apr 2010 09:34:38 +0200 (CEST) Date: Tue, 13 Apr 2010 09:34:38 +0200 From: Thomas Bogendoerfer To: Wu Zhangjin Cc: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels Message-ID: <20100413073435.GA6371@alpha.franken.de> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1271135034.25797.41.camel@falcon> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote: > This patch have broken the support to the MIPS variants whose > cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different > in these MIPSs. I've checked R4k and R10k manulas and the exception base is at CKSEG0, so about CPU we are talking ? And wouldn't it make for senso to have an extra define for the exception base then ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From tiwai@suse.de Tue Apr 13 18:49:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 18:49:27 +0200 (CEST) Received: from cantor.suse.de ([195.135.220.2]:44608 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491176Ab0DMQtX (ORCPT ); Tue, 13 Apr 2010 18:49:23 +0200 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 8D01F90975; Tue, 13 Apr 2010 18:49:22 +0200 (CEST) Date: Tue, 13 Apr 2010 18:49:20 +0200 Message-ID: From: Takashi Iwai To: wuzhangjin@gmail.com Cc: Ralf Baechle , linux-mips Subject: Re: About MIPS specific dma_mmap_coherent() In-Reply-To: <1271134735.25797.35.camel@falcon> References: <1271134735.25797.35.camel@falcon> User-Agent: Wanderlust/2.15.6 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.7 Emacs/23.1 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiwai@suse.de Precedence: bulk X-list: linux-mips At Tue, 13 Apr 2010 12:58:54 +0800, Wu Zhangjin wrote: > > Hi, Ralf and Takashi > > Seems Takashi have sent the MIPS specific dma_mmap_coherent() at 18 Aug > 2008: > > http://www.linux-mips.org/archives/linux-mips/2008-08/msg00178.html > > But that patch have not been accepted since it was not suitable to all > of the MIPS variants. > > Without that patch, the ALSA output will be broken in some of the MIPS > variants, can we make the implementation in the above url be weak, then > the particular MIPS variants can override it with their own versions but > the common MIPS variants can share it to fix the ALSA problem? > > I have attached a change of the above patch, which is applicable to the > linux-2.6.33 and linux-2.6.34-rcX and I have tested it on my YeeLoong > netbook, the following command function well with it. > > $ mplayer -ao alsa file.mp3 > > but without it, the ALSA output is broken. Hm, which driver/device are you using? Also, how is it broken? There is already a low-level hack in sound/core/pcm_native.c for MIPS, so I thought the kernel oops should have been avoided, at least. Maybe still pgprot_noncached() is missing, though. thanks, Takashi > > Regards, > Wu Zhangjin > [2 0001-MIPS-Implement-dma_mmap_coherent-for-ALSA-audio-outp.patch ] > >From a6ee304febbd609d2936dd5b33a16482ef224c97 Mon Sep 17 00:00:00 2001 > From: Wu Zhangjin > Date: Sun, 11 Apr 2010 03:58:13 +0800 > Subject: [PATCH] MIPS: Implement dma_mmap_coherent() for ALSA audio output > > A lazy version of dma_mmap_coherent() implementation for MIPS. > > Without this patch, the ALSA sound output of MIPS is broken: > > $ mplayer -ao alsa file.mp3 > > (This patch was sent out by Takashi Iwai at '18 Aug 2008' but not have > been applied yet for it is not suitable for all MIPS variants. If you > need more info, please access: > http://www.linux-mips.org/archives/linux-mips/2008-08/msg00178.html) > > Signed-off-by: Takashi Iwai > --- > arch/mips/include/asm/dma-mapping.h | 4 ++++ > arch/mips/mm/dma-default.c | 13 +++++++++++++ > 2 files changed, 17 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h > index 664ba53..c39bfdf 100644 > --- a/arch/mips/include/asm/dma-mapping.h > +++ b/arch/mips/include/asm/dma-mapping.h > @@ -74,4 +74,8 @@ extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr); > extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, > enum dma_data_direction direction); > > +#define ARCH_HAS_DMA_MMAP_COHERENT > +extern int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, > + void *cpu_addr, dma_addr_t handle, size_t size); > + > #endif /* _ASM_DMA_MAPPING_H */ > diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c > index 9547bc0..8388428 100644 > --- a/arch/mips/mm/dma-default.c > +++ b/arch/mips/mm/dma-default.c > @@ -375,3 +375,16 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, > } > > EXPORT_SYMBOL(dma_cache_sync); > + > +int __weak dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, > + void *cpu_addr, dma_addr_t handle, size_t size) > +{ > + struct page *pg; > + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); > + cpu_addr = (void *)dma_addr_to_virt(dev, handle); > + pg = virt_to_page(cpu_addr); > + return remap_pfn_range(vma, vma->vm_start, > + page_to_pfn(pg) + vma->vm_pgoff, > + size, vma->vm_page_prot); > +} > +EXPORT_SYMBOL(dma_mmap_coherent); > -- > 1.7.0 > From ralf@linux-mips.org Tue Apr 13 19:16:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 19:16:22 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54552 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492525Ab0DMRQT (ORCPT ); Tue, 13 Apr 2010 19:16:19 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3DHGBvA017726; Tue, 13 Apr 2010 18:16:11 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3DHGAKY017724; Tue, 13 Apr 2010 18:16:10 +0100 Date: Tue, 13 Apr 2010 18:16:10 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: Wu Zhangjin , David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels Message-ID: <20100413171610.GA16578@linux-mips.org> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100413073435.GA6371@alpha.franken.de> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote: > On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote: > > This patch have broken the support to the MIPS variants whose > > cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different > > in these MIPSs. > > I've checked R4k and R10k manulas and the exception base is at CKSEG0, so > about CPU we are talking ? And wouldn't it make for senso to have > an extra define for the exception base then ? C0_ebase's design was a short-sigthed only considering 32-bit processors. So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or older. So yes, there is a bug as I've verified by testing but the patch is unfortunately incorrect. Ralf From manuel.lauss@googlemail.com Tue Apr 13 20:10:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 20:10:07 +0200 (CEST) Received: from mail-ew0-f211.google.com ([209.85.219.211]:44881 "EHLO mail-ew0-f211.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492525Ab0DMSKC (ORCPT ); Tue, 13 Apr 2010 20:10:02 +0200 Received: by ewy3 with SMTP id 3so2550ewy.26 for ; Tue, 13 Apr 2010 11:09:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=s3pwaZjzIMr9U9GW4Pv8ouRoythi9cxKnbF/dIefJtI=; b=pbMhJi0vnYNQddYF9BG8Xuoxu1Rw62R1vfpBIO/tdZ61ZCtOZZWxGmiXbpgJzMWbJm Cc55EnkCixHof5o9QRkvbIPgKPI02jTG3GOtP+iQo7xS6z/TUrA2xE03ttN6TEvfGlDH t+I9NuLYdwlYBlmKFYDdFgvbLhcw89DUmwhRc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=sO2NZ5K/TYyQqhK+eOCsOm7OTyc+wE5VSc7qK6wUpSdmDArkoZEPi/ckgF3lr4zbv5 NytyZfruM1XlfwixzjLSSwbKnyhnoFXQS2W4S1Ng/YHxUJst/N3B7vMLW02my1DSGlqQ G3MBDmp/s76ShOeId8VenaaL0B2wSuQD6MU20= Received: by 10.87.53.22 with SMTP id f22mr5227784fgk.41.1271182196119; Tue, 13 Apr 2010 11:09:56 -0700 (PDT) Received: from localhost.localdomain (p5496D173.dip.t-dialin.net [84.150.209.115]) by mx.google.com with ESMTPS id 9sm11614748fks.26.2010.04.13.11.09.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 13 Apr 2010 11:09:55 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH v4] MIPS: Alchemy: add sysdev for IRQ PM. Date: Tue, 13 Apr 2010 20:09:40 +0200 Message-Id: <1271182180-8158-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Use a sysdev to implement PM methods for the Au1000 interrupt controllers. Signed-off-by: Manuel Lauss --- v4: need slab.h for kzalloc v3: fix odd formatting v2: register a sysdev for each of the 2 controllers (instead of a single one handling both). arch/mips/alchemy/common/irq.c | 197 ++++++++++++++++------------ arch/mips/alchemy/common/power.c | 5 - arch/mips/include/asm/mach-au1x00/au1000.h | 2 - 3 files changed, 113 insertions(+), 91 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index b2821ac..4792c89 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include #include @@ -216,90 +218,6 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { }; -#ifdef CONFIG_PM - -/* - * Save/restore the interrupt controller state. - * Called from the save/restore core registers as part of the - * au_sleep function in power.c.....maybe I should just pm_register() - * them instead? - */ -static unsigned int sleep_intctl_config0[2]; -static unsigned int sleep_intctl_config1[2]; -static unsigned int sleep_intctl_config2[2]; -static unsigned int sleep_intctl_src[2]; -static unsigned int sleep_intctl_assign[2]; -static unsigned int sleep_intctl_wake[2]; -static unsigned int sleep_intctl_mask[2]; - -void save_au1xxx_intctl(void) -{ - sleep_intctl_config0[0] = au_readl(IC0_CFG0RD); - sleep_intctl_config1[0] = au_readl(IC0_CFG1RD); - sleep_intctl_config2[0] = au_readl(IC0_CFG2RD); - sleep_intctl_src[0] = au_readl(IC0_SRCRD); - sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD); - sleep_intctl_wake[0] = au_readl(IC0_WAKERD); - sleep_intctl_mask[0] = au_readl(IC0_MASKRD); - - sleep_intctl_config0[1] = au_readl(IC1_CFG0RD); - sleep_intctl_config1[1] = au_readl(IC1_CFG1RD); - sleep_intctl_config2[1] = au_readl(IC1_CFG2RD); - sleep_intctl_src[1] = au_readl(IC1_SRCRD); - sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD); - sleep_intctl_wake[1] = au_readl(IC1_WAKERD); - sleep_intctl_mask[1] = au_readl(IC1_MASKRD); -} - -/* - * For most restore operations, we clear the entire register and - * then set the bits we found during the save. - */ -void restore_au1xxx_intctl(void) -{ - au_writel(0xffffffff, IC0_MASKCLR); au_sync(); - - au_writel(0xffffffff, IC0_CFG0CLR); au_sync(); - au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync(); - au_writel(0xffffffff, IC0_CFG1CLR); au_sync(); - au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync(); - au_writel(0xffffffff, IC0_CFG2CLR); au_sync(); - au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync(); - au_writel(0xffffffff, IC0_SRCCLR); au_sync(); - au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync(); - au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync(); - au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync(); - au_writel(0xffffffff, IC0_WAKECLR); au_sync(); - au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync(); - au_writel(0xffffffff, IC0_RISINGCLR); au_sync(); - au_writel(0xffffffff, IC0_FALLINGCLR); au_sync(); - au_writel(0x00000000, IC0_TESTBIT); au_sync(); - - au_writel(0xffffffff, IC1_MASKCLR); au_sync(); - - au_writel(0xffffffff, IC1_CFG0CLR); au_sync(); - au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync(); - au_writel(0xffffffff, IC1_CFG1CLR); au_sync(); - au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync(); - au_writel(0xffffffff, IC1_CFG2CLR); au_sync(); - au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync(); - au_writel(0xffffffff, IC1_SRCCLR); au_sync(); - au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync(); - au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync(); - au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync(); - au_writel(0xffffffff, IC1_WAKECLR); au_sync(); - au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync(); - au_writel(0xffffffff, IC1_RISINGCLR); au_sync(); - au_writel(0xffffffff, IC1_FALLINGCLR); au_sync(); - au_writel(0x00000000, IC1_TESTBIT); au_sync(); - - au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync(); - - au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync(); -} -#endif /* CONFIG_PM */ - - static void au1x_ic0_unmask(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -635,3 +553,114 @@ void __init arch_init_irq(void) break; } } + +struct alchemy_ic_sysdev { + struct sys_device sysdev; + unsigned long pmdata[7 * 2]; +}; + +static int alchemy_ic_suspend(struct sys_device *dev, pm_message_t state) +{ + struct alchemy_ic_sysdev *icdev = + container_of(dev, struct alchemy_ic_sysdev, sysdev); + + icdev->pmdata[0] = au_readl(IC0_CFG0RD); + icdev->pmdata[1] = au_readl(IC0_CFG1RD); + icdev->pmdata[2] = au_readl(IC0_CFG2RD); + icdev->pmdata[3] = au_readl(IC0_SRCRD); + icdev->pmdata[4] = au_readl(IC0_ASSIGNRD); + icdev->pmdata[5] = au_readl(IC0_WAKERD); + icdev->pmdata[6] = au_readl(IC0_MASKRD); + + icdev->pmdata[7] = au_readl(IC1_CFG0RD); + icdev->pmdata[8] = au_readl(IC1_CFG1RD); + icdev->pmdata[9] = au_readl(IC1_CFG2RD); + icdev->pmdata[10] = au_readl(IC1_SRCRD); + icdev->pmdata[11] = au_readl(IC1_ASSIGNRD); + icdev->pmdata[12] = au_readl(IC1_WAKERD); + icdev->pmdata[13] = au_readl(IC1_MASKRD); + + return 0; +} + +static int alchemy_ic_resume(struct sys_device *dev) +{ + struct alchemy_ic_sysdev *icdev = + container_of(dev, struct alchemy_ic_sysdev, sysdev); + + au_writel(0xffffffff, IC0_MASKCLR); + au_writel(0xffffffff, IC0_CFG0CLR); + au_writel(0xffffffff, IC0_CFG1CLR); + au_writel(0xffffffff, IC0_CFG2CLR); + au_writel(0xffffffff, IC0_SRCCLR); + au_writel(0xffffffff, IC0_ASSIGNCLR); + au_writel(0xffffffff, IC0_WAKECLR); + au_writel(0xffffffff, IC0_RISINGCLR); + au_writel(0xffffffff, IC0_FALLINGCLR); + au_writel(0x00000000, IC0_TESTBIT); + au_sync(); + au_writel(icdev->pmdata[0], IC0_CFG0SET); + au_writel(icdev->pmdata[1], IC0_CFG1SET); + au_writel(icdev->pmdata[2], IC0_CFG2SET); + au_writel(icdev->pmdata[3], IC0_SRCSET); + au_writel(icdev->pmdata[4], IC0_ASSIGNSET); + au_writel(icdev->pmdata[5], IC0_WAKESET); + au_sync(); + + au_writel(0xffffffff, IC1_MASKCLR); + au_writel(0xffffffff, IC1_CFG0CLR); + au_writel(0xffffffff, IC1_CFG1CLR); + au_writel(0xffffffff, IC1_CFG2CLR); + au_writel(0xffffffff, IC1_SRCCLR); + au_writel(0xffffffff, IC1_ASSIGNCLR); + au_writel(0xffffffff, IC1_WAKECLR); + au_writel(0xffffffff, IC1_RISINGCLR); + au_writel(0xffffffff, IC1_FALLINGCLR); + au_writel(0x00000000, IC1_TESTBIT); + au_sync(); + au_writel(icdev->pmdata[7], IC1_CFG0SET); + au_writel(icdev->pmdata[8], IC1_CFG1SET); + au_writel(icdev->pmdata[9], IC1_CFG2SET); + au_writel(icdev->pmdata[10], IC1_SRCSET); + au_writel(icdev->pmdata[11], IC1_ASSIGNSET); + au_writel(icdev->pmdata[12], IC1_WAKESET); + au_sync(); + + au_writel(icdev->pmdata[13], IC1_MASKSET); + au_sync(); + au_writel(icdev->pmdata[6], IC0_MASKSET); + au_sync(); + + return 0; +} + +static struct sysdev_class alchemy_ic_sysdev_class = { + .name = "ic", + .suspend = alchemy_ic_suspend, + .resume = alchemy_ic_resume, +}; + +static int __init alchemy_ic_sysdev_init(void) +{ + struct alchemy_ic_sysdev *icdev; + int err; + + icdev = kzalloc(sizeof(struct alchemy_ic_sysdev), GFP_KERNEL); + if (!icdev) + return -ENOMEM; + + err = sysdev_class_register(&alchemy_ic_sysdev_class); + if (err) { + kfree(icdev); + return err; + } + + icdev->sysdev.id = 0; + icdev->sysdev.cls = &alchemy_ic_sysdev_class; + err = sysdev_register(&icdev->sysdev); + if (err) + kfree(icdev); + + return err; +} +device_initcall(alchemy_ic_sysdev_init); diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index c07101c..e097094 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -106,9 +106,6 @@ static void save_core_regs(void) sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ #endif - /* Save interrupt controller state. */ - save_au1xxx_intctl(); - /* Clocks and PLLs. */ sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); @@ -200,8 +197,6 @@ static void restore_core_regs(void) au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); } - restore_au1xxx_intctl(); - #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) au1xxx_dbdma_resume(); #endif diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index cb91714..c84fcd6 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -191,8 +191,6 @@ extern unsigned long au1xxx_calc_clock(void); void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); void au_sleep(void); -void save_au1xxx_intctl(void); -void restore_au1xxx_intctl(void); /* SOC Interrupt numbers */ -- 1.7.0.3 From manuel.lauss@googlemail.com Tue Apr 13 20:12:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 20:12:46 +0200 (CEST) Received: from mail-bw0-f218.google.com ([209.85.218.218]:51226 "EHLO mail-bw0-f218.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492265Ab0DMSMm (ORCPT ); Tue, 13 Apr 2010 20:12:42 +0200 Received: by bwz10 with SMTP id 10so3642132bwz.24 for ; Tue, 13 Apr 2010 11:12:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:cc:content-type; bh=QXG1kfuCOHHPYRRRL8GxGxV66L4UVdI29+foR4pPO/g=; b=sztCXqijutPvQx451Kb+CN6J5TKnTMjQEXaqyDoeyXx+nJuMlXGRc+IxTwOksltYpo DI8eHh5bXBNDco0itRJ7l0gqkX2uhBTbe9mCu/D0i6Ad57gu03C2LbWv3Y30rQe8ue/w U9VUYE7qNlDZioQqCipkPYkkwcH+avSE3Z4RQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=hKn9kSzAErUGVYLYymQwVY850gHokDjDad6VvvmpcPSmrGjDd+ExOdfeW7fpMIn0k5 LLtFl65ZcztKOcoefTaLGnLEwI4hmdE8z6RU2zTfw+DG3zORxKAAWLANsyG6Y8LaZ6aJ AuLXoRFI6V6+c7fMUUVSlXGIQwFXW7u7m7pzk= MIME-Version: 1.0 Received: by 10.223.106.12 with HTTP; Tue, 13 Apr 2010 11:12:35 -0700 (PDT) In-Reply-To: <1271182180-8158-1-git-send-email-manuel.lauss@gmail.com> References: <1271182180-8158-1-git-send-email-manuel.lauss@gmail.com> Date: Tue, 13 Apr 2010 20:12:35 +0200 Received: by 10.223.143.20 with SMTP id s20mr3606506fau.38.1271182355760; Tue, 13 Apr 2010 11:12:35 -0700 (PDT) Message-ID: Subject: Re: [PATCH v4] MIPS: Alchemy: add sysdev for IRQ PM. From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Whoa, ignore this one, it's and old version (again). Manuel From tsbogend@alpha.franken.de Tue Apr 13 20:15:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 20:15:42 +0200 (CEST) Received: from elvis.franken.de ([193.175.24.41]:44606 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492265Ab0DMSPi (ORCPT ); Tue, 13 Apr 2010 20:15:38 +0200 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1O1ke9-0007Zz-00; Tue, 13 Apr 2010 20:15:37 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 2428D1D2E1; Tue, 13 Apr 2010 20:15:17 +0200 (CEST) Date: Tue, 13 Apr 2010 20:15:17 +0200 From: Thomas Bogendoerfer To: Ralf Baechle Cc: Wu Zhangjin , David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels Message-ID: <20100413181516.GA19223@alpha.franken.de> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> <20100413171610.GA16578@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100413171610.GA16578@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Tue, Apr 13, 2010 at 06:16:10PM +0100, Ralf Baechle wrote: > C0_ebase's design was a short-sigthed only considering 32-bit processors. > So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or > older. So yes, there is a bug as I've verified by testing but the patch > is unfortunately incorrect. well not quite every 64bit CPU, R8k is as always special. R8k has a trap vector register. But since support for R8k is still lacking no problem for now. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From manuel.lauss@googlemail.com Tue Apr 13 20:49:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 20:49:36 +0200 (CEST) Received: from mail-bw0-f218.google.com ([209.85.218.218]:38823 "EHLO mail-bw0-f218.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491908Ab0DMStc (ORCPT ); Tue, 13 Apr 2010 20:49:32 +0200 Received: by bwz10 with SMTP id 10so3681644bwz.24 for ; Tue, 13 Apr 2010 11:49:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=Fxthmo+2zfqQJEP6WTEYSMLp+A6vFarZyZ/2/CiCdTo=; b=N9RdEvWFD/ncYXWaWwgxs38sHjlBskBywY24KE+mQ9YZEz7ZX8uBZHzSVOyxuizUAj hIJdf1W0/BOi8gqDEGV2ty9laEZzUootS//JtZ/nmasd4OmqBturqcvJiH3CPMqRm8D2 260nqE1fgl0QlCROpwCk0xlmt5EUI+wS80Kb4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=aYB6Cxuga9HGoM0pOCUmyy/lt+qPvjq0FSOLKPa+o7wTQFkxlXOZ3AYTgeNhF7jk4I moBTqVW52O+Qe1vJ3wtTq+zYkJ1OX2buUuezM1mp18P1/aIbaA7PCuJ6fiqE/dDartgj NBFxo+qCJXBKrTKi1IM8TIkngVBZe6sBUQwb0= Received: by 10.223.62.207 with SMTP id y15mr3431553fah.92.1271184565693; Tue, 13 Apr 2010 11:49:25 -0700 (PDT) Received: from localhost.localdomain (p5496D173.dip.t-dialin.net [84.150.209.115]) by mx.google.com with ESMTPS id 21sm538563fks.23.2010.04.13.11.49.24 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 13 Apr 2010 11:49:24 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH v5] MIPS: Alchemy: add sysdev for IRQ PM. Date: Tue, 13 Apr 2010 20:49:14 +0200 Message-Id: <1271184554-28058-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Use a sysdev to implement PM methods for the Au1000 interrupt controllers. Signed-off-by: Manuel Lauss --- v5: an older patch slipped in for v4 v4: need slab.h for kzalloc v3: fix odd formatting v2: register a sysdev for each of the 2 controllers (instead of a single one handling both). arch/mips/alchemy/common/irq.c | 174 ++++++++++++++------------- arch/mips/alchemy/common/power.c | 5 - arch/mips/include/asm/mach-au1x00/au1000.h | 34 +++++- 3 files changed, 122 insertions(+), 91 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index b2821ac..9f78ada 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include #include @@ -216,90 +218,6 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { }; -#ifdef CONFIG_PM - -/* - * Save/restore the interrupt controller state. - * Called from the save/restore core registers as part of the - * au_sleep function in power.c.....maybe I should just pm_register() - * them instead? - */ -static unsigned int sleep_intctl_config0[2]; -static unsigned int sleep_intctl_config1[2]; -static unsigned int sleep_intctl_config2[2]; -static unsigned int sleep_intctl_src[2]; -static unsigned int sleep_intctl_assign[2]; -static unsigned int sleep_intctl_wake[2]; -static unsigned int sleep_intctl_mask[2]; - -void save_au1xxx_intctl(void) -{ - sleep_intctl_config0[0] = au_readl(IC0_CFG0RD); - sleep_intctl_config1[0] = au_readl(IC0_CFG1RD); - sleep_intctl_config2[0] = au_readl(IC0_CFG2RD); - sleep_intctl_src[0] = au_readl(IC0_SRCRD); - sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD); - sleep_intctl_wake[0] = au_readl(IC0_WAKERD); - sleep_intctl_mask[0] = au_readl(IC0_MASKRD); - - sleep_intctl_config0[1] = au_readl(IC1_CFG0RD); - sleep_intctl_config1[1] = au_readl(IC1_CFG1RD); - sleep_intctl_config2[1] = au_readl(IC1_CFG2RD); - sleep_intctl_src[1] = au_readl(IC1_SRCRD); - sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD); - sleep_intctl_wake[1] = au_readl(IC1_WAKERD); - sleep_intctl_mask[1] = au_readl(IC1_MASKRD); -} - -/* - * For most restore operations, we clear the entire register and - * then set the bits we found during the save. - */ -void restore_au1xxx_intctl(void) -{ - au_writel(0xffffffff, IC0_MASKCLR); au_sync(); - - au_writel(0xffffffff, IC0_CFG0CLR); au_sync(); - au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync(); - au_writel(0xffffffff, IC0_CFG1CLR); au_sync(); - au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync(); - au_writel(0xffffffff, IC0_CFG2CLR); au_sync(); - au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync(); - au_writel(0xffffffff, IC0_SRCCLR); au_sync(); - au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync(); - au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync(); - au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync(); - au_writel(0xffffffff, IC0_WAKECLR); au_sync(); - au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync(); - au_writel(0xffffffff, IC0_RISINGCLR); au_sync(); - au_writel(0xffffffff, IC0_FALLINGCLR); au_sync(); - au_writel(0x00000000, IC0_TESTBIT); au_sync(); - - au_writel(0xffffffff, IC1_MASKCLR); au_sync(); - - au_writel(0xffffffff, IC1_CFG0CLR); au_sync(); - au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync(); - au_writel(0xffffffff, IC1_CFG1CLR); au_sync(); - au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync(); - au_writel(0xffffffff, IC1_CFG2CLR); au_sync(); - au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync(); - au_writel(0xffffffff, IC1_SRCCLR); au_sync(); - au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync(); - au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync(); - au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync(); - au_writel(0xffffffff, IC1_WAKECLR); au_sync(); - au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync(); - au_writel(0xffffffff, IC1_RISINGCLR); au_sync(); - au_writel(0xffffffff, IC1_FALLINGCLR); au_sync(); - au_writel(0x00000000, IC1_TESTBIT); au_sync(); - - au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync(); - - au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync(); -} -#endif /* CONFIG_PM */ - - static void au1x_ic0_unmask(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -635,3 +553,91 @@ void __init arch_init_irq(void) break; } } + +struct alchemy_ic_sysdev { + struct sys_device sysdev; + void __iomem *base; + unsigned long pmdata[7]; +}; + +static int alchemy_ic_suspend(struct sys_device *dev, pm_message_t state) +{ + struct alchemy_ic_sysdev *icdev = + container_of(dev, struct alchemy_ic_sysdev, sysdev); + + icdev->pmdata[0] = __raw_readl(icdev->base + IC_CFG0RD); + icdev->pmdata[1] = __raw_readl(icdev->base + IC_CFG1RD); + icdev->pmdata[2] = __raw_readl(icdev->base + IC_CFG2RD); + icdev->pmdata[3] = __raw_readl(icdev->base + IC_SRCRD); + icdev->pmdata[4] = __raw_readl(icdev->base + IC_ASSIGNRD); + icdev->pmdata[5] = __raw_readl(icdev->base + IC_WAKERD); + icdev->pmdata[6] = __raw_readl(icdev->base + IC_MASKRD); + + return 0; +} + +static int alchemy_ic_resume(struct sys_device *dev) +{ + struct alchemy_ic_sysdev *icdev = + container_of(dev, struct alchemy_ic_sysdev, sysdev); + + __raw_writel(0xffffffff, icdev->base + IC_MASKCLR); + __raw_writel(0xffffffff, icdev->base + IC_CFG0CLR); + __raw_writel(0xffffffff, icdev->base + IC_CFG1CLR); + __raw_writel(0xffffffff, icdev->base + IC_CFG2CLR); + __raw_writel(0xffffffff, icdev->base + IC_SRCCLR); + __raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR); + __raw_writel(0xffffffff, icdev->base + IC_WAKECLR); + __raw_writel(0xffffffff, icdev->base + IC_RISINGCLR); + __raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR); + __raw_writel(0x00000000, icdev->base + IC_TESTBIT); + wmb(); + __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET); + __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET); + __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET); + __raw_writel(icdev->pmdata[3], icdev->base + IC_SRCSET); + __raw_writel(icdev->pmdata[4], icdev->base + IC_ASSIGNSET); + __raw_writel(icdev->pmdata[5], icdev->base + IC_WAKESET); + wmb(); + + __raw_writel(icdev->pmdata[6], icdev->base + IC_MASKSET); + wmb(); + + return 0; +} + +static struct sysdev_class alchemy_ic_sysdev_class = { + .name = "ic", + .suspend = alchemy_ic_suspend, + .resume = alchemy_ic_resume, +}; + +static int __init alchemy_ic_sysdev_init(void) +{ + struct alchemy_ic_sysdev *icdev; + unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR }; + int err, i; + + err = sysdev_class_register(&alchemy_ic_sysdev_class); + if (err) + return err; + + for (i = 0; i < 2; i++) { + icdev = kzalloc(sizeof(struct alchemy_ic_sysdev), GFP_KERNEL); + if (!icdev) + return -ENOMEM; + + icdev->base = ioremap(icbase[i], 0x1000); + + icdev->sysdev.id = i; + icdev->sysdev.cls = &alchemy_ic_sysdev_class; + err = sysdev_register(&icdev->sysdev); + if (err) { + kfree(icdev); + return err; + } + } + + return 0; +} +device_initcall(alchemy_ic_sysdev_init); diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index c07101c..e097094 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -106,9 +106,6 @@ static void save_core_regs(void) sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ #endif - /* Save interrupt controller state. */ - save_au1xxx_intctl(); - /* Clocks and PLLs. */ sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); @@ -200,8 +197,6 @@ static void restore_core_regs(void) au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); } - restore_au1xxx_intctl(); - #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) au1xxx_dbdma_resume(); #endif diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index cb91714..a697661 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -191,8 +191,6 @@ extern unsigned long au1xxx_calc_clock(void); void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); void au_sleep(void); -void save_au1xxx_intctl(void); -void restore_au1xxx_intctl(void); /* SOC Interrupt numbers */ @@ -836,6 +834,38 @@ enum soc_au1200_ints { #define MEM_STNAND_DATA 0x20 #endif + +/* Interrupt Controller register offsets */ +#define IC_CFG0RD 0x40 +#define IC_CFG0SET 0x40 +#define IC_CFG0CLR 0x44 +#define IC_CFG1RD 0x48 +#define IC_CFG1SET 0x48 +#define IC_CFG1CLR 0x4C +#define IC_CFG2RD 0x50 +#define IC_CFG2SET 0x50 +#define IC_CFG2CLR 0x54 +#define IC_REQ0INT 0x54 +#define IC_SRCRD 0x58 +#define IC_SRCSET 0x58 +#define IC_SRCCLR 0x5C +#define IC_REQ1INT 0x5C +#define IC_ASSIGNRD 0x60 +#define IC_ASSIGNSET 0x60 +#define IC_ASSIGNCLR 0x64 +#define IC_WAKERD 0x68 +#define IC_WAKESET 0x68 +#define IC_WAKECLR 0x6C +#define IC_MASKRD 0x70 +#define IC_MASKSET 0x70 +#define IC_MASKCLR 0x74 +#define IC_RISINGRD 0x78 +#define IC_RISINGCLR 0x78 +#define IC_FALLINGRD 0x7C +#define IC_FALLINGCLR 0x7C +#define IC_TESTBIT 0x80 + + /* Interrupt Controller 0 */ #define IC0_CFG0RD 0xB0400040 #define IC0_CFG0SET 0xB0400040 -- 1.7.0.4 From manuel.lauss@googlemail.com Tue Apr 13 21:32:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Apr 2010 21:32:22 +0200 (CEST) Received: from mail-bw0-f218.google.com ([209.85.218.218]:46513 "EHLO mail-bw0-f218.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491841Ab0DMTcQ (ORCPT ); Tue, 13 Apr 2010 21:32:16 +0200 Received: by bwz10 with SMTP id 10so3727108bwz.24 for ; Tue, 13 Apr 2010 12:32:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=BKHZ2GW30IwdUhuzkV1TKT6NPieHg7FKM24QmrEQLN8=; b=ribLWvd7ofZPQTQKZIVpSIgKoBoEag0K+gctQ3j6QXtnO3UZ41cZGlcy5M10gsBYVD CNNjVv1PLHjo7tRliyO6iEAmUEY9PEKMLYxK3Eh39XQH0cF/eqP/XnMhKZSd5PQeMhgE C3mYsCKiV5HCqIRs0jof16NKPmK2jjC587glc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=oR1ayBtFLQxVNDfokSNKhAbDxipk6WGksnSFklQwTBCan9SFXiVbAU8DHObpOKvlZ3 srNgxow3/4siMdjqyBKnW3jG8kxgEYafu1VuxB9wm6WY+X6cZZ8n05gXpeDUVT8fQR2k XSsfTHcy4TGPh461p/VA87vc6gPCPxg6g9GPc= Received: by 10.223.100.141 with SMTP id y13mr3745729fan.15.1271187130009; Tue, 13 Apr 2010 12:32:10 -0700 (PDT) Received: from localhost.localdomain (p5496D173.dip.t-dialin.net [84.150.209.115]) by mx.google.com with ESMTPS id 18sm11724573fkq.34.2010.04.13.12.32.09 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 13 Apr 2010 12:32:09 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [RFC PATCH] MIPS: Alchemy: sysdem for DBDMA PM Date: Tue, 13 Apr 2010 21:31:59 +0200 Message-Id: <1271187119-696-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Add a sysdev for DBDMA PM. Signed-off-by: Manuel Lauss --- Tested on DB1200 (STR while playing audio and SD card activity works fine). Will probably throw rejects in power.c, hence the RFC. arch/mips/alchemy/common/dbdma.c | 101 +++++++++++++++------ arch/mips/alchemy/common/power.c | 11 --- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 4 - 3 files changed, 72 insertions(+), 44 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 99ae84c..ca0506a 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -174,10 +175,6 @@ static dbdev_tab_t dbdev_tab[] = { #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) -#ifdef CONFIG_PM -static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][6]; -#endif - static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; @@ -960,29 +957,37 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) return nbytes; } -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void) + +struct alchemy_dbdma_sysdev { + struct sys_device sysdev; + u32 pm_regs[NUM_DBDMA_CHANS + 1][6]; +}; + +static int alchemy_dbdma_suspend(struct sys_device *dev, + pm_message_t state) { + struct alchemy_dbdma_sysdev *sdev = + container_of(dev, struct alchemy_dbdma_sysdev, sysdev); int i; u32 addr; addr = DDMA_GLOBAL_BASE; - au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00); - au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04); - au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08); - au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); + sdev->pm_regs[0][0] = au_readl(addr + 0x00); + sdev->pm_regs[0][1] = au_readl(addr + 0x04); + sdev->pm_regs[0][2] = au_readl(addr + 0x08); + sdev->pm_regs[0][3] = au_readl(addr + 0x0c); /* save channel configurations */ for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { - au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); - au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); - au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); - au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); - au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); - au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); + sdev->pm_regs[i][0] = au_readl(addr + 0x00); + sdev->pm_regs[i][1] = au_readl(addr + 0x04); + sdev->pm_regs[i][2] = au_readl(addr + 0x08); + sdev->pm_regs[i][3] = au_readl(addr + 0x0c); + sdev->pm_regs[i][4] = au_readl(addr + 0x10); + sdev->pm_regs[i][5] = au_readl(addr + 0x14); /* halt channel */ - au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); + au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00); au_sync(); while (!(au_readl(addr + 0x14) & 1)) au_sync(); @@ -992,32 +997,65 @@ void au1xxx_dbdma_suspend(void) /* disable channel interrupts */ au_writel(0, DDMA_GLOBAL_BASE + 0x0c); au_sync(); + + return 0; } -void au1xxx_dbdma_resume(void) +static int alchemy_dbdma_resume(struct sys_device *dev) { + struct alchemy_dbdma_sysdev *sdev = + container_of(dev, struct alchemy_dbdma_sysdev, sysdev); int i; u32 addr; addr = DDMA_GLOBAL_BASE; - au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00); - au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04); - au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08); - au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); + au_writel(sdev->pm_regs[0][0], addr + 0x00); + au_writel(sdev->pm_regs[0][1], addr + 0x04); + au_writel(sdev->pm_regs[0][2], addr + 0x08); + au_writel(sdev->pm_regs[0][3], addr + 0x0c); /* restore channel configurations */ for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { - au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); - au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); - au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); - au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); - au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); - au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); + au_writel(sdev->pm_regs[i][0], addr + 0x00); + au_writel(sdev->pm_regs[i][1], addr + 0x04); + au_writel(sdev->pm_regs[i][2], addr + 0x08); + au_writel(sdev->pm_regs[i][3], addr + 0x0c); + au_writel(sdev->pm_regs[i][4], addr + 0x10); + au_writel(sdev->pm_regs[i][5], addr + 0x14); au_sync(); addr += 0x100; /* next channel base */ } + + return 0; +} + +static struct sysdev_class alchemy_dbdma_sysdev_class = { + .name = "dbdma", + .suspend = alchemy_dbdma_suspend, + .resume = alchemy_dbdma_resume, +}; + +static int __init alchemy_dbdma_sysdev_init(void) +{ + struct alchemy_dbdma_sysdev *sdev; + int ret; + + ret = sysdev_class_register(&alchemy_dbdma_sysdev_class); + if (ret) + return ret; + + sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL); + if (!sdev) + return -ENOMEM; + + sdev->sysdev.id = -1; + sdev->sysdev.cls = &alchemy_dbdma_sysdev_class; + ret = sysdev_register(&sdev->sysdev); + if (ret) + kfree(sdev); + + return ret; } -#endif /* CONFIG_PM */ static int __init au1xxx_dbdma_init(void) { @@ -1046,6 +1084,11 @@ static int __init au1xxx_dbdma_init(void) else { dbdma_initialized = 1; printk(KERN_INFO "Alchemy DBDMA initialized\n"); + ret = alchemy_dbdma_sysdev_init(); + if (ret) { + printk(KERN_ERR "DBDMA PM init failed\n"); + ret = 0; + } } return ret; diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index cbc9eed..e5916a5 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -36,9 +36,6 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#include -#endif #ifdef CONFIG_PM @@ -108,10 +105,6 @@ static void save_core_regs(void) sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - au1xxx_dbdma_suspend(); -#endif } static void restore_core_regs(void) @@ -161,10 +154,6 @@ static void restore_core_regs(void) au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - au1xxx_dbdma_resume(); -#endif } void au_sleep(void) diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 8c6b110..c8a553a 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -358,10 +358,6 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); extern void au1xxx_ddma_del_device(u32 devid); void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void); -void au1xxx_dbdma_resume(void); -#endif /* * Flags for the put_source/put_dest functions. -- 1.7.0.4 From ralf@linux-mips.org Wed Apr 14 00:02:06 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 00:02:09 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60721 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492753Ab0DMWCG (ORCPT ); Wed, 14 Apr 2010 00:02:06 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3DM22te024650; Tue, 13 Apr 2010 23:02:02 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3DM21bs024649; Tue, 13 Apr 2010 23:02:01 +0100 Date: Tue, 13 Apr 2010 23:02:00 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS Subject: Re: [PATCH] Loongson: update cpu-feature-overrides.h Message-ID: <20100413220200.GA24077@linux-mips.org> References: <1271135794-19762-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1271135794-19762-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 13, 2010 at 01:16:34PM +0800, Wu Zhangjin wrote: > From: Wu Zhangjin > > Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts > (cpu_has_vint) and MIPSR2 external interrupt controller mode > (cpu_has_veic) are 0. > > Signed-off-by: Wu Zhangjin Thanks Wu, queued for 2.6.35! Ralf From ralf@linux-mips.org Wed Apr 14 00:45:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 00:45:13 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41927 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491164Ab0DMWpJ (ORCPT ); Wed, 14 Apr 2010 00:45:09 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3DMj4rV026035; Tue, 13 Apr 2010 23:45:05 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3DMj3Tt025997; Tue, 13 Apr 2010 23:45:03 +0100 Date: Tue, 13 Apr 2010 23:45:02 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH v2] MIPS: Alchemy: fix up residual devboard poweroff/reboot code. Message-ID: <20100413224501.GB24077@linux-mips.org> References: <1269554138-4620-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1269554138-4620-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Mar 25, 2010 at 10:55:38PM +0100, Manuel Lauss wrote: > Clean out stray unused board_reset() calls in pb1x boards, > the pb1000 is different from the rest and gets private methods. > > (Cleanup after 32fd6901a6d8d19f94e4de6be4e4b552ab078620) > > Signed-off-by: Manuel Lauss Thanks, queued for 2.6.35. Ralf From ralf@linux-mips.org Wed Apr 14 00:49:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 00:50:00 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44928 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492568Ab0DMWt5 (ORCPT ); Wed, 14 Apr 2010 00:49:57 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3DMnt3V026717; Tue, 13 Apr 2010 23:49:55 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3DMnt0O026715; Tue, 13 Apr 2010 23:49:55 +0100 Date: Tue, 13 Apr 2010 23:49:55 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH v5] MIPS: Alchemy: add sysdev for IRQ PM. Message-ID: <20100413224955.GC24077@linux-mips.org> References: <1271184554-28058-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1271184554-28058-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 13, 2010 at 08:49:14PM +0200, Manuel Lauss wrote: Queued for 2.6.35. There were some line offsets and fuzz when applying this patch but I hope that's ok. Thanks, Ralf From groeck@redback.com Wed Apr 14 03:28:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 03:28:41 +0200 (CEST) Received: from imr1.ericy.com ([198.24.6.9]:56952 "EHLO imr1.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492299Ab0DNB2f (ORCPT ); Wed, 14 Apr 2010 03:28:35 +0200 Received: from eusaamw0711.eamcs.ericsson.se ([147.117.20.178]) by imr1.ericy.com (8.13.1/8.13.1) with ESMTP id o3E1WfAQ005113; Tue, 13 Apr 2010 20:32:46 -0500 Received: from prattle.redback.com (147.117.20.212) by eusaamw0711.eamcs.ericsson.se (147.117.20.179) with Microsoft SMTP Server id 8.1.375.2; Tue, 13 Apr 2010 21:28:21 -0400 Received: from localhost (localhost [127.0.0.1]) by prattle.redback.com (Postfix) with ESMTP id 9858AFEFFFE; Tue, 13 Apr 2010 18:28:21 -0700 (PDT) Received: from prattle.redback.com ([127.0.0.1]) by localhost (prattle [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 01449-09; Tue, 13 Apr 2010 18:28:21 -0700 (PDT) Received: from localhost (rbos-pc-13.lab.redback.com [10.12.11.133]) by prattle.redback.com (Postfix) with ESMTP id 87263FEFFFC; Tue, 13 Apr 2010 18:28:20 -0700 (PDT) From: Guenter Roeck To: linux-mips@linux-mips.org, ralf@linux-mips.org CC: Guenter Roeck Subject: [PATCH] Fix sibyte watchdog initialization Date: Tue, 13 Apr 2010 18:28:16 -0700 Message-ID: <1271208496-30878-1-git-send-email-guenter.roeck@ericsson.com> X-Mailer: git-send-email 1.7.0.87.g0901d MIME-Version: 1.0 Content-Type: text/plain Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Watchdog configuration register and timer count register were interchanged, causing wrong values to be written into both registers. This caused watchdog triggered resets even if the watchdog was reset in time. Signed-off-by: Guenter Roeck --- drivers/watchdog/sb_wdog.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c index 9748eed..1407cfa 100644 --- a/drivers/watchdog/sb_wdog.c +++ b/drivers/watchdog/sb_wdog.c @@ -67,8 +67,8 @@ static DEFINE_SPINLOCK(sbwd_lock); void sbwdog_set(char __iomem *wdog, unsigned long t) { spin_lock(&sbwd_lock); - __raw_writeb(0, wdog - 0x10); - __raw_writeq(t & 0x7fffffUL, wdog); + __raw_writeb(0, wdog); + __raw_writeq(t & 0x7fffffUL, wdog - 0x10); spin_unlock(&sbwd_lock); } -- 1.7.0.87.g0901d From wuzhangjin@gmail.com Wed Apr 14 06:21:45 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 06:21:49 +0200 (CEST) Received: from mail-gx0-f228.google.com ([209.85.217.228]:48654 "EHLO mail-gx0-f228.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491017Ab0DNEVn (ORCPT ); Wed, 14 Apr 2010 06:21:43 +0200 Received: by gxk28 with SMTP id 28so1482238gxk.7 for ; Tue, 13 Apr 2010 21:21:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=aAafmdkQvRBXA1RQlKI/AL1MmLhY7OtCSuVwxOyboNc=; b=SiKkXpm1djjaxO73v+Oa/a8RqY1jPECA9+ewqcaXy/mu4EYl0RP3U7h67n/b9VnQQl sAfX/zLFHKwgn4YsNryDEAk8PXeCudhrLPoIrHQ3B1j3A6giQbNwAOlZn+TXe3/5HA9G WtpfqGHJcCDFXqT3h6q5hfE0MD5OR2G0rDV8c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=ajTgdwhJIV21pmSS3IubcYjIxH2ETsGCjA7KloClf0bF1SD1JFLfVpxFQG0gJZblqD 5M6T+z5ivjwqolSQP4ATXMNKCiZPUr9512tJ2CWuqTDtEmmbY/BhB5yJ6x7vTofedHdo DkYr4BJix85L+lRg8iNysdgGRQVfWlIkd/3PE= Received: by 10.101.11.17 with SMTP id o17mr11928338ani.111.1271218896145; Tue, 13 Apr 2010 21:21:36 -0700 (PDT) Received: from [192.168.2.243] ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm5419075iwn.8.2010.04.13.21.21.33 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 13 Apr 2010 21:21:34 -0700 (PDT) Subject: Re: About MIPS specific dma_mmap_coherent() From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Takashi Iwai Cc: Ralf Baechle , linux-mips In-Reply-To: References: <1271134735.25797.35.camel@falcon> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 14 Apr 2010 12:21:29 +0800 Message-ID: <1271218889.25872.27.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, > > $ mplayer -ao alsa file.mp3 > > > > but without it, the ALSA output is broken. > > Hm, which driver/device are you using? Also, how is it broken? I'm using the cs5535 audio in my Yeeloong laptop with the config "CONFIG_SND_CS5535AUDIO=m" the above 'broken' means there is audio output with ALSA, but the output is not normal for it has lots of noises: sha sha sha... > > There is already a low-level hack in sound/core/pcm_native.c for MIPS, > so I thought the kernel oops should have been avoided, at least. > Maybe still pgprot_noncached() is missing, though. You mean this part for MIPS: static inline struct page * snd_pcm_default_page_ops(struct snd_pcm_substream *substream, unsigned long ofs) { void *vaddr = substream->runtime->dma_area + ofs; #if defined(CONFIG_MIPS) && defined(CONFIG_DMA_NONCOHERENT) if (substream->dma_buffer.dev.type == SNDRV_DMA_TYPE_DEV) return virt_to_page(CAC_ADDR(vaddr)); #endif ... } Yes, it was already there from one of your patches to linux-2.6.33, but the pgprot_noncached() was missing as you mentioned above. And I have found you have added the ARM specific dma_mmap_coherent() to snd_pcm_default_mmap() to mmap the DMA buffer on RAM: /* * mmap the DMA buffer on RAM */ static int snd_pcm_default_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *area) { area->vm_flags |= VM_RESERVED; #ifdef ARCH_HAS_DMA_MMAP_COHERENT if (!substream->ops->page && substream->dma_buffer.dev.type == SNDRV_DMA_TYPE_DEV) return dma_mmap_coherent(substream->dma_buffer.dev.dev, area, substream->runtime->dma_area, substream->runtime->dma_addr, area->vm_end - area->vm_start); #endif /* ARCH_HAS_DMA_MMAP_COHERENT */ /* mmap with fault handler */ area->vm_ops = &snd_pcm_vm_ops_data_fault; return 0; } Before, we have added the low-level handling with pgprot_noncached() in snd_pcm_mmap() to fix it, but now, can we add MIPS specific dma_mmap_coherent() as ARM did? Regards, Wu Zhangjin > > [2 0001-MIPS-Implement-dma_mmap_coherent-for-ALSA-audio-outp.patch ] > > >From a6ee304febbd609d2936dd5b33a16482ef224c97 Mon Sep 17 00:00:00 2001 > > From: Wu Zhangjin > > Date: Sun, 11 Apr 2010 03:58:13 +0800 > > Subject: [PATCH] MIPS: Implement dma_mmap_coherent() for ALSA audio output > > > > A lazy version of dma_mmap_coherent() implementation for MIPS. > > > > Without this patch, the ALSA sound output of MIPS is broken: > > > > $ mplayer -ao alsa file.mp3 > > > > (This patch was sent out by Takashi Iwai at '18 Aug 2008' but not have > > been applied yet for it is not suitable for all MIPS variants. If you > > need more info, please access: > > http://www.linux-mips.org/archives/linux-mips/2008-08/msg00178.html) > > > > Signed-off-by: Takashi Iwai > > --- > > arch/mips/include/asm/dma-mapping.h | 4 ++++ > > arch/mips/mm/dma-default.c | 13 +++++++++++++ > > 2 files changed, 17 insertions(+), 0 deletions(-) > > > > diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h > > index 664ba53..c39bfdf 100644 > > --- a/arch/mips/include/asm/dma-mapping.h > > +++ b/arch/mips/include/asm/dma-mapping.h > > @@ -74,4 +74,8 @@ extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr); > > extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, > > enum dma_data_direction direction); > > > > +#define ARCH_HAS_DMA_MMAP_COHERENT > > +extern int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, > > + void *cpu_addr, dma_addr_t handle, size_t size); > > + > > #endif /* _ASM_DMA_MAPPING_H */ > > diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c > > index 9547bc0..8388428 100644 > > --- a/arch/mips/mm/dma-default.c > > +++ b/arch/mips/mm/dma-default.c > > @@ -375,3 +375,16 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, > > } > > > > EXPORT_SYMBOL(dma_cache_sync); > > + > > +int __weak dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, > > + void *cpu_addr, dma_addr_t handle, size_t size) > > +{ > > + struct page *pg; > > + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); > > + cpu_addr = (void *)dma_addr_to_virt(dev, handle); > > + pg = virt_to_page(cpu_addr); > > + return remap_pfn_range(vma, vma->vm_start, > > + page_to_pfn(pg) + vma->vm_pgoff, > > + size, vma->vm_page_prot); > > +} > > +EXPORT_SYMBOL(dma_mmap_coherent); > > -- > > 1.7.0 > > From manuel.lauss@googlemail.com Wed Apr 14 08:20:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 08:21:01 +0200 (CEST) Received: from mail-bw0-f218.google.com ([209.85.218.218]:40861 "EHLO mail-bw0-f218.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491008Ab0DNGUy convert rfc822-to-8bit (ORCPT ); Wed, 14 Apr 2010 08:20:54 +0200 Received: by bwz10 with SMTP id 10so4174642bwz.24 for ; Tue, 13 Apr 2010 23:20:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Xz2N/Q5EtsbQDXGrKec99DvrfW8IL4JgaIJp+qdLs2s=; b=SzLZ+Jzg9uATi31SqBBOfobOPdqr8gzhf6vHGCPmOCHk4wiJeK/QWXiAOfdHn2GFvL 6/9NqR3/JHkSql8vSOyW9DpegNzFXiRKqnR9UledSRJ3NedhUmmrcV/O32qyXwd3Rs0l gR+NXrFxWk2TicUgDdKWyRlu7ohCDrJaHiflE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=eQjpGdaEElmo7OEPTFQ6PYokn31Zk3VevAm57IM5iQCHq/7O21/384YoHe0rmCEzsM vDA/VIKtozC2ijRqHuoHQku19s0/G7cl/4MMOMyEq4o8LoLPf5lfTJ4ZncvKKqLB9XIW UT2c/TfzasZqyD8jWUCYaeFufnVThPvy8xDHk= MIME-Version: 1.0 Received: by 10.103.193.7 with HTTP; Tue, 13 Apr 2010 23:20:46 -0700 (PDT) In-Reply-To: <20100413224955.GC24077@linux-mips.org> References: <1271184554-28058-1-git-send-email-manuel.lauss@gmail.com> <20100413224955.GC24077@linux-mips.org> Date: Wed, 14 Apr 2010 08:20:46 +0200 Received: by 10.103.7.31 with SMTP id k31mr3771733mui.132.1271226046385; Tue, 13 Apr 2010 23:20:46 -0700 (PDT) Message-ID: Subject: Re: [PATCH v5] MIPS: Alchemy: add sysdev for IRQ PM. From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips > Queued for 2.6.35.  There were some line offsets and fuzz when applying > this patch but I hope that's ok. The version in queue is fine. Vielen Dank, Manuel Lauss From tiwai@suse.de Wed Apr 14 08:31:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 08:31:23 +0200 (CEST) Received: from cantor2.suse.de ([195.135.220.15]:53060 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491012Ab0DNGbT (ORCPT ); Wed, 14 Apr 2010 08:31:19 +0200 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) by mx2.suse.de (Postfix) with ESMTP id 34C5989783; Wed, 14 Apr 2010 08:31:19 +0200 (CEST) Date: Wed, 14 Apr 2010 08:31:17 +0200 Message-ID: From: Takashi Iwai To: wuzhangjin@gmail.com Cc: Ralf Baechle , linux-mips Subject: Re: About MIPS specific dma_mmap_coherent() In-Reply-To: <1271218889.25872.27.camel@falcon> References: <1271134735.25797.35.camel@falcon> <1271218889.25872.27.camel@falcon> User-Agent: Wanderlust/2.15.6 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.7 Emacs/23.1 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26406 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiwai@suse.de Precedence: bulk X-list: linux-mips At Wed, 14 Apr 2010 12:21:29 +0800, Wu Zhangjin wrote: > > Hi, > > > > $ mplayer -ao alsa file.mp3 > > > > > > but without it, the ALSA output is broken. > > > > Hm, which driver/device are you using? Also, how is it broken? > > I'm using the cs5535 audio in my Yeeloong laptop with the config > "CONFIG_SND_CS5535AUDIO=m" > > the above 'broken' means there is audio output with ALSA, but the output > is not normal for it has lots of noises: sha sha sha... > > > > > There is already a low-level hack in sound/core/pcm_native.c for MIPS, > > so I thought the kernel oops should have been avoided, at least. > > Maybe still pgprot_noncached() is missing, though. > > You mean this part for MIPS: > > static inline struct page * > snd_pcm_default_page_ops(struct snd_pcm_substream *substream, unsigned > long ofs) > { > void *vaddr = substream->runtime->dma_area + ofs; > #if defined(CONFIG_MIPS) && defined(CONFIG_DMA_NONCOHERENT) > if (substream->dma_buffer.dev.type == SNDRV_DMA_TYPE_DEV) > return virt_to_page(CAC_ADDR(vaddr)); > #endif > > ... > } > > Yes, it was already there from one of your patches to linux-2.6.33, but > the pgprot_noncached() was missing as you mentioned above. > > And I have found you have added the ARM specific dma_mmap_coherent() to > snd_pcm_default_mmap() to mmap the DMA buffer on RAM: > > /* > * mmap the DMA buffer on RAM > */ > static int snd_pcm_default_mmap(struct snd_pcm_substream *substream, > struct vm_area_struct *area) > { > area->vm_flags |= VM_RESERVED; > #ifdef ARCH_HAS_DMA_MMAP_COHERENT > if (!substream->ops->page && > substream->dma_buffer.dev.type == SNDRV_DMA_TYPE_DEV) > return dma_mmap_coherent(substream->dma_buffer.dev.dev, > area, > substream->runtime->dma_area, > substream->runtime->dma_addr, > area->vm_end - area->vm_start); > #endif /* ARCH_HAS_DMA_MMAP_COHERENT */ > /* mmap with fault handler */ > area->vm_ops = &snd_pcm_vm_ops_data_fault; > return 0; > } > > Before, we have added the low-level handling with pgprot_noncached() in > snd_pcm_mmap() to fix it, but now, can we add MIPS specific > dma_mmap_coherent() as ARM did? That would be a certainly fix, yes. I have no objection, of course ;) A quicky, less-intrusive one would be the patch below. thanks, Takashi --- diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index c22ebb0..fd6703e 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -3188,6 +3188,8 @@ static int snd_pcm_default_mmap(struct snd_pcm_substream *substream, substream->runtime->dma_area, substream->runtime->dma_addr, area->vm_end - area->vm_start); +#elif defined(CONFIG_MIPS) && defined(CONFIG_DMA_NONCOHERENT) + area->vm_page_prot = pgprot_noncached(area->vm_page_prot); #endif /* ARCH_HAS_DMA_MMAP_COHERENT */ /* mmap with fault handler */ area->vm_ops = &snd_pcm_vm_ops_data_fault; From wuzhangjin@gmail.com Wed Apr 14 10:03:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 10:03:23 +0200 (CEST) Received: from mail-pz0-f186.google.com ([209.85.222.186]:50103 "EHLO mail-pz0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491052Ab0DNIDT (ORCPT ); Wed, 14 Apr 2010 10:03:19 +0200 Received: by pzk16 with SMTP id 16so4634941pzk.22 for ; Wed, 14 Apr 2010 01:03:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=ZYqdjjD1QwNS65uWijunZJ5X8JnHzKGeeGCzCyFNGDY=; b=QJcbnuBRtFxGb6Obcf6/g5MKOUAx6YgEs1fOEwvYb43tRMZSPjh3a+DDJOFo2L+1oG 52cmgLgzBmROECT2pERyGHszsnW0XFG0X7YeK8SYlA8QyF1VP9CODchuhZtgYYPLaiDf WJ9IsLzsuPvwYUqUHUIsN+Z8bDZVFWXXgoFyw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=EyUypCb23RNIgUyoqNUEmvTVVHljkm5E/kas/9mLsXs2QXqAAm464gHypelxcQMsaP FZ9lHHwlWu8nX7a57HQgI3DN6YL/zcL/Z9x7tMNjrX1a54HptJ5Ccq6VE3sQwepKrjIL 94X4NG7hmsBW6PrrHsGWrZzD2bxhlkC4r+VDw= Received: by 10.115.102.36 with SMTP id e36mr6623024wam.126.1271232192080; Wed, 14 Apr 2010 01:03:12 -0700 (PDT) Received: from [192.168.2.243] ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm68533pzk.5.2010.04.14.01.03.09 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 14 Apr 2010 01:03:11 -0700 (PDT) Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Thomas Bogendoerfer , David Daney , linux-mips@linux-mips.org In-Reply-To: <20100413171610.GA16578@linux-mips.org> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> <20100413171610.GA16578@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 14 Apr 2010 16:03:05 +0800 Message-ID: <1271232185.25872.142.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26407 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2010-04-13 at 18:16 +0100, Ralf Baechle wrote: > On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote: > > > On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote: > > > This patch have broken the support to the MIPS variants whose > > > cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different > > > in these MIPSs. > > > > I've checked R4k and R10k manulas and the exception base is at CKSEG0, so > > about CPU we are talking ? And wouldn't it make for senso to have > > an extra define for the exception base then ? > > C0_ebase's design was a short-sigthed only considering 32-bit processors. > So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or > older. So yes, there is a bug as I've verified by testing but the patch > is unfortunately incorrect. Just debugged it via PMON: loaded the kernel and used "g console=tty root=/dev/hda5 init=/bin/bash" to start the kernel, there was a bad address exception. the kernel stopped at: Exception Cause=address error on store, SR=0x24000002, PC=0x8020526c ... BADVADDR=0x97ffffff80000100, ENTHI=0xfffffe000 ... ... __copy_user+0x48 ... sd t0,0(a0) # addr = 0x80000100 rt=0x401a8000 Seems the a0 argument of __copy_user is _bad_. And tried to set a break pointer to trap_init() and per_cpu_trap_init(), and then cpu_cache_init() ... r4k_cache_init() and at last found that set_uncached_handler(0x100, &except_vec2_generic, 0x80); /* * Install uncached CPU exception handler. * This is suitable only for the cache error exception which is the only * exception handler that is being run uncached. */ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { #ifdef CONFIG_32BIT unsigned long uncached_ebase = KSEG1ADDR(ebase); #endif #ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); #endif if (!addr) panic(panic_null_cerr); memcpy((void *)(uncached_ebase + offset), addr, size); } memcpy() called __copy_user... and the a0 is uncached_ebase + offset, and uncached_ebase is defined by TO_UNCAC: #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) #define UNCAC_BASE _AC(0x9000000000000000, UL) If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000, then we get the address: 0x97ffffff80000100, is this address ok? And before, we have used the CAC_BASE as the ebase, the CAC_BASE is defined as following: #ifndef CAC_BASE #ifdef CONFIG_DMA_NONCOHERENT #define CAC_BASE _AC(0x9800000000000000, UL) #else #define CAC_BASE _AC(0xa800000000000000, UL) #endif #endif So, before, the uncached_base is 0x9000000000000000. Regards, Wu Zhangjin From wuzhangjin@gmail.com Wed Apr 14 11:00:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 11:00:35 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:51223 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491139Ab0DNJAb (ORCPT ); Wed, 14 Apr 2010 11:00:31 +0200 Received: by pvc30 with SMTP id 30so4115335pvc.36 for ; Wed, 14 Apr 2010 02:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=MLY8Tkp5qhZQIgOucOlAlOZPYWUUTrW3bZpNADlYyE0=; b=G7xQPO/aTJZJ/NFf0ka0zrW9hib26obkEV39X5YwLJz1rIDCPKZiswV/4PMqPpSS5t PLASRvuuVVxSqoWKH+z0Qgiqr5Z5f8vDwHXxI3p4hob2RQOmia6ZKcR1L4cLMKJeTrqI cMFDC21rUzvCaH36Ovi0QlaHe3G0ePbOv2/7g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=hWdLNasXWBP16SyX+yfKed3wQ0bFxEFXHZoXOQ9NKkY4DCpjWcC9nN2iSLMQmUB9OA QXHqlxiL9TswLED842hVGHuy5It3WqkFrHwIZ/K6wVqSLqk79P4cR9HaSW7qh+9yZM1Z tQJHeTSq2TJk3RhXVOH3VnFPWyHKQ0YlS1m7M= Received: by 10.141.91.7 with SMTP id t7mr1063331rvl.83.1271235624797; Wed, 14 Apr 2010 02:00:24 -0700 (PDT) Received: from [192.168.2.243] ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm113661pzk.1.2010.04.14.02.00.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 14 Apr 2010 02:00:24 -0700 (PDT) Subject: Re: About MIPS specific dma_mmap_coherent() From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Takashi Iwai Cc: Ralf Baechle , linux-mips In-Reply-To: References: <1271134735.25797.35.camel@falcon> <1271218889.25872.27.camel@falcon> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 14 Apr 2010 17:00:19 +0800 Message-ID: <1271235619.25872.148.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26408 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2010-04-14 at 08:31 +0200, Takashi Iwai wrote: [...] > > > > Before, we have added the low-level handling with pgprot_noncached() in > > snd_pcm_mmap() to fix it, but now, can we add MIPS specific > > dma_mmap_coherent() as ARM did? > > That would be a certainly fix, yes. I have no objection, of course ;) > A quicky, less-intrusive one would be the patch below. The below patch works well, just tested it. > > > thanks, > > Takashi > > --- > diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c > index c22ebb0..fd6703e 100644 > --- a/sound/core/pcm_native.c > +++ b/sound/core/pcm_native.c > @@ -3188,6 +3188,8 @@ static int snd_pcm_default_mmap(struct snd_pcm_substream *substream, > substream->runtime->dma_area, > substream->runtime->dma_addr, > area->vm_end - area->vm_start); > +#elif defined(CONFIG_MIPS) && defined(CONFIG_DMA_NONCOHERENT) > + area->vm_page_prot = pgprot_noncached(area->vm_page_prot); > #endif /* ARCH_HAS_DMA_MMAP_COHERENT */ > /* mmap with fault handler */ > area->vm_ops = &snd_pcm_vm_ops_data_fault; From tsbogend@alpha.franken.de Wed Apr 14 13:25:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 13:25:11 +0200 (CEST) Received: from elvis.franken.de ([193.175.24.41]:57641 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491845Ab0DNLZH (ORCPT ); Wed, 14 Apr 2010 13:25:07 +0200 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1O20iQ-0004pT-00; Wed, 14 Apr 2010 13:25:06 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id C92411D2DE; Wed, 14 Apr 2010 13:24:58 +0200 (CEST) Date: Wed, 14 Apr 2010 13:24:58 +0200 From: Thomas Bogendoerfer To: Wu Zhangjin Cc: Ralf Baechle , David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels Message-ID: <20100414112458.GA8861@alpha.franken.de> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> <20100413171610.GA16578@linux-mips.org> <1271232185.25872.142.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1271232185.25872.142.camel@falcon> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26409 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Wed, Apr 14, 2010 at 04:03:05PM +0800, Wu Zhangjin wrote: > If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000, > then we get the address: 0x97ffffff80000100, is this address ok? the address is broken TO_UNCAC doesn't work properly for CKSEG0 addresses. And that's IMHO the real bug... I'm wondering whether this set_uncached_handler() stunt is even needed. Is there a machine where CKSEG0 and CKSEG1 address different memory ? If not, we could just use the normal set_handler() function and be done with it. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From tiwai@suse.de Wed Apr 14 17:46:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 17:46:20 +0200 (CEST) Received: from cantor.suse.de ([195.135.220.2]:57286 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492089Ab0DNPqQ (ORCPT ); Wed, 14 Apr 2010 17:46:16 +0200 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 94B5793717; Wed, 14 Apr 2010 17:46:15 +0200 (CEST) Date: Wed, 14 Apr 2010 17:46:13 +0200 Message-ID: From: Takashi Iwai To: wuzhangjin@gmail.com Cc: Ralf Baechle , linux-mips Subject: Re: About MIPS specific dma_mmap_coherent() In-Reply-To: <1271235619.25872.148.camel@falcon> References: <1271134735.25797.35.camel@falcon> <1271218889.25872.27.camel@falcon> <1271235619.25872.148.camel@falcon> User-Agent: Wanderlust/2.15.6 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.7 Emacs/23.1 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26410 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiwai@suse.de Precedence: bulk X-list: linux-mips At Wed, 14 Apr 2010 17:00:19 +0800, Wu Zhangjin wrote: > > On Wed, 2010-04-14 at 08:31 +0200, Takashi Iwai wrote: > [...] > > > > > > Before, we have added the low-level handling with pgprot_noncached() in > > > snd_pcm_mmap() to fix it, but now, can we add MIPS specific > > > dma_mmap_coherent() as ARM did? > > > > That would be a certainly fix, yes. I have no objection, of course ;) > > A quicky, less-intrusive one would be the patch below. > > The below patch works well, just tested it. Thanks. But, I remember vaguely that calling pgprot_noncached() unconditionally is dangerous. It should be checked somehow, e.g. via platform_device_is_coherent(). And, this found only in dma-coherence.h, and adding it to pcm_native.c would become messy like below... So, it'd be really better to add dma_mmap_coherent(), indeed. Takashi --- diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index c22ebb0..4c3edc1 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -36,6 +36,9 @@ #include #include #include +#if defined(CONFIG_MIPS) && defined(CONFIG_DMA_NONCOHERENT) +#include +#endif /* * Compatibility @@ -3188,6 +3191,10 @@ static int snd_pcm_default_mmap(struct snd_pcm_substream *substream, substream->runtime->dma_area, substream->runtime->dma_addr, area->vm_end - area->vm_start); +#elif defined(CONFIG_MIPS) && defined(CONFIG_DMA_NONCOHERENT) + if (substream->dma_buffer.dev.type == SNDRV_DMA_TYPE_DEV && + !plat_device_is_coherent(substream->dma_buffer.dev.dev)) + area->vm_page_prot = pgprot_noncached(area->vm_page_prot); #endif /* ARCH_HAS_DMA_MMAP_COHERENT */ /* mmap with fault handler */ area->vm_ops = &snd_pcm_vm_ops_data_fault; From manuel.lauss@googlemail.com Wed Apr 14 19:39:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 19:39:51 +0200 (CEST) Received: from mail-bw0-f226.google.com ([209.85.218.226]:38572 "EHLO mail-bw0-f226.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492766Ab0DNRjr convert rfc822-to-8bit (ORCPT ); Wed, 14 Apr 2010 19:39:47 +0200 Received: by bwz26 with SMTP id 26so433653bwz.27 for ; Wed, 14 Apr 2010 10:39:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=vJTNh/2wldGGuY1mFDyPusTZxcmy6ur5GbU/AaIBBW0=; b=MccHOVYj/LYbFt/K24HQ+a4NkXmsv8fOsOLvK03CUULz3PdxFu53bQqwLEGMZ6w8qV DM2zL1aRNjhoqiI14wHZoAHfXbl9kl0iPVGVNjdPUf225XLuWM71FajJGZi7vHe+wEVw vWkqf6PWnGI9bBb1QBAlvDgqGHTlZT9OydmHA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=an82oqCX2JTzM1pzrv1/DJd/bJsL2psOn6iNf56YRMNzsJmMVExD0uMhZ1bwTN/tlM ies9dpw9KLBBClrdOypm/C9jlpuSPRlDdHr34wq4T0jz6GGegrroGlvBLLQq76bMdytQ n3LuEuXBAeBslc5iTOOL7rcVyfEx4tuL9pI8Q= MIME-Version: 1.0 Received: by 10.103.193.7 with HTTP; Wed, 14 Apr 2010 10:39:41 -0700 (PDT) In-Reply-To: <1269450986-3714-1-git-send-email-manuel.lauss@gmail.com> References: <1269450986-3714-1-git-send-email-manuel.lauss@gmail.com> Date: Wed, 14 Apr 2010 19:39:41 +0200 Received: by 10.102.17.2 with SMTP id 2mr4331976muq.130.1271266782183; Wed, 14 Apr 2010 10:39:42 -0700 (PDT) Message-ID: Subject: Re: [RFC PATCH 0/2] serial 8250 platform PM hooks From: Manuel Lauss To: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org, Manuel Lauss Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26411 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Ping? Noone interested? On Wed, Mar 24, 2010 at 7:16 PM, Manuel Lauss wrote: > The following 2 patches implement a PM hook for platform 8250 > UARTs and a sample PM implementation for a MIPS SoC. > > Patch #1 hooks a new .pm callback in struct plat_serial8250_port to > the rest of serial_core's PM infrastructure, > > Patch #2 implements uart power gating for Alchemy line of mips socs > using the new hook. > > With these 2 patches serial console on my test system survives > suspend/resume cycles without having to resort to platform-specific > hacks in the PM code. > > Thanks, >     Manuel Lauss > > Manuel Lauss (2): >  8250: allow platform uarts to install PM callback. >  Alchemy: UART PM through serial framework. > >  arch/mips/alchemy/common/platform.c |   17 +++++++++++++++++ >  arch/mips/alchemy/common/power.c    |   32 -------------------------------- >  drivers/serial/8250.c               |   31 ++++++++++++++++++++++++++++--- >  include/linux/serial_8250.h         |    6 ++++++ >  4 files changed, 51 insertions(+), 35 deletions(-) > > From manuel.lauss@googlemail.com Wed Apr 14 20:33:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Apr 2010 20:33:59 +0200 (CEST) Received: from mail-bw0-f226.google.com ([209.85.218.226]:62406 "EHLO mail-bw0-f226.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492775Ab0DNSdy (ORCPT ); Wed, 14 Apr 2010 20:33:54 +0200 Received: by bwz26 with SMTP id 26so498708bwz.27 for ; Wed, 14 Apr 2010 11:33:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=K07UjI/AZ6pJ7ZvtfSqByXzOmAq8W/Z935qBVz+Nwvs=; b=NUVlldRhQ7QsXSIFUAXEvsq6gV76Pq5mLUlik9noSCmj8Sl2GCJSiXvj8MueTKoFCv g3mXWj2iSWRYcu39snJPkxRsyPToOVRKcQXw6Uv9Ljr0OFBTetyW3zgHk8PQ2qFhQefO aEec/d5Ry+eLMjJM0TY/i6Z+GPjxEQYnuXphg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=CG6oOJ0TK7p+8I3MGn5h5meONekUJFZroYJIPJAVmIUajaVMBNmMBPzP/nsLJu8j5f cZ7jOYMCIn6s27D1eUQ6kvdOHnh6PVBIa5po3ACuUTSR65HRdNxMFVMeMV4Y81UVSw3t uDJUBSOjAFu8giYcSUql8Dzyk8YsH7t5Y7Nno= Received: by 10.204.22.79 with SMTP id m15mr285385bkb.80.1271270027192; Wed, 14 Apr 2010 11:33:47 -0700 (PDT) Received: from localhost.localdomain (p5496CD44.dip.t-dialin.net [84.150.205.68]) by mx.google.com with ESMTPS id 14sm642696bwz.2.2010.04.14.11.33.45 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 14 Apr 2010 11:33:46 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: add sysdev for DBDMA PM. Date: Wed, 14 Apr 2010 20:33:44 +0200 Message-Id: <1271270024-26684-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26412 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Add a sysdev for DBDMA PM. Signed-off-by: Manuel Lauss --- Tested on DB1200; no changes since yesterday. It works as intended and per-channel sysdevs seem like overdoing it. arch/mips/alchemy/common/dbdma.c | 101 +++++++++++++++------ arch/mips/alchemy/common/power.c | 11 --- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 4 - 3 files changed, 72 insertions(+), 44 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 99ae84c..ca0506a 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -174,10 +175,6 @@ static dbdev_tab_t dbdev_tab[] = { #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) -#ifdef CONFIG_PM -static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][6]; -#endif - static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; @@ -960,29 +957,37 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) return nbytes; } -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void) + +struct alchemy_dbdma_sysdev { + struct sys_device sysdev; + u32 pm_regs[NUM_DBDMA_CHANS + 1][6]; +}; + +static int alchemy_dbdma_suspend(struct sys_device *dev, + pm_message_t state) { + struct alchemy_dbdma_sysdev *sdev = + container_of(dev, struct alchemy_dbdma_sysdev, sysdev); int i; u32 addr; addr = DDMA_GLOBAL_BASE; - au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00); - au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04); - au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08); - au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); + sdev->pm_regs[0][0] = au_readl(addr + 0x00); + sdev->pm_regs[0][1] = au_readl(addr + 0x04); + sdev->pm_regs[0][2] = au_readl(addr + 0x08); + sdev->pm_regs[0][3] = au_readl(addr + 0x0c); /* save channel configurations */ for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { - au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); - au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); - au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); - au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); - au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); - au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); + sdev->pm_regs[i][0] = au_readl(addr + 0x00); + sdev->pm_regs[i][1] = au_readl(addr + 0x04); + sdev->pm_regs[i][2] = au_readl(addr + 0x08); + sdev->pm_regs[i][3] = au_readl(addr + 0x0c); + sdev->pm_regs[i][4] = au_readl(addr + 0x10); + sdev->pm_regs[i][5] = au_readl(addr + 0x14); /* halt channel */ - au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); + au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00); au_sync(); while (!(au_readl(addr + 0x14) & 1)) au_sync(); @@ -992,32 +997,65 @@ void au1xxx_dbdma_suspend(void) /* disable channel interrupts */ au_writel(0, DDMA_GLOBAL_BASE + 0x0c); au_sync(); + + return 0; } -void au1xxx_dbdma_resume(void) +static int alchemy_dbdma_resume(struct sys_device *dev) { + struct alchemy_dbdma_sysdev *sdev = + container_of(dev, struct alchemy_dbdma_sysdev, sysdev); int i; u32 addr; addr = DDMA_GLOBAL_BASE; - au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00); - au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04); - au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08); - au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); + au_writel(sdev->pm_regs[0][0], addr + 0x00); + au_writel(sdev->pm_regs[0][1], addr + 0x04); + au_writel(sdev->pm_regs[0][2], addr + 0x08); + au_writel(sdev->pm_regs[0][3], addr + 0x0c); /* restore channel configurations */ for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { - au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); - au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); - au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); - au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); - au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); - au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); + au_writel(sdev->pm_regs[i][0], addr + 0x00); + au_writel(sdev->pm_regs[i][1], addr + 0x04); + au_writel(sdev->pm_regs[i][2], addr + 0x08); + au_writel(sdev->pm_regs[i][3], addr + 0x0c); + au_writel(sdev->pm_regs[i][4], addr + 0x10); + au_writel(sdev->pm_regs[i][5], addr + 0x14); au_sync(); addr += 0x100; /* next channel base */ } + + return 0; +} + +static struct sysdev_class alchemy_dbdma_sysdev_class = { + .name = "dbdma", + .suspend = alchemy_dbdma_suspend, + .resume = alchemy_dbdma_resume, +}; + +static int __init alchemy_dbdma_sysdev_init(void) +{ + struct alchemy_dbdma_sysdev *sdev; + int ret; + + ret = sysdev_class_register(&alchemy_dbdma_sysdev_class); + if (ret) + return ret; + + sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL); + if (!sdev) + return -ENOMEM; + + sdev->sysdev.id = -1; + sdev->sysdev.cls = &alchemy_dbdma_sysdev_class; + ret = sysdev_register(&sdev->sysdev); + if (ret) + kfree(sdev); + + return ret; } -#endif /* CONFIG_PM */ static int __init au1xxx_dbdma_init(void) { @@ -1046,6 +1084,11 @@ static int __init au1xxx_dbdma_init(void) else { dbdma_initialized = 1; printk(KERN_INFO "Alchemy DBDMA initialized\n"); + ret = alchemy_dbdma_sysdev_init(); + if (ret) { + printk(KERN_ERR "DBDMA PM init failed\n"); + ret = 0; + } } return ret; diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index e097094..5ef06a1 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -36,9 +36,6 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#include -#endif #ifdef CONFIG_PM @@ -129,10 +126,6 @@ static void save_core_regs(void) sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - au1xxx_dbdma_suspend(); -#endif } static void restore_core_regs(void) @@ -196,10 +189,6 @@ static void restore_core_regs(void) au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); } - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - au1xxx_dbdma_resume(); -#endif } void au_sleep(void) diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 8c6b110..c8a553a 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -358,10 +358,6 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); extern void au1xxx_ddma_del_device(u32 devid); void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void); -void au1xxx_dbdma_resume(void); -#endif /* * Flags for the put_source/put_dest functions. -- 1.7.0.4 From ralf@linux-mips.org Thu Apr 15 12:46:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Apr 2010 12:46:17 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51646 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492631Ab0DOKqN (ORCPT ); Thu, 15 Apr 2010 12:46:13 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3FAkBaB012940; Thu, 15 Apr 2010 11:46:12 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3FAkB9J012938; Thu, 15 Apr 2010 11:46:11 +0100 Date: Thu, 15 Apr 2010 11:46:10 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH] MIPS: Alchemy: add sysdev for DBDMA PM. Message-ID: <20100415104610.GA8123@linux-mips.org> References: <1271270024-26684-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1271270024-26684-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26413 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 14, 2010 at 08:33:44PM +0200, Manuel Lauss wrote: > Add a sysdev for DBDMA PM. > > Signed-off-by: Manuel Lauss > --- > Tested on DB1200; no changes since yesterday. It works as intended > and per-channel sysdevs seem like overdoing it. Agreed. Thanks, queued for 2.6.35. Ralf From dengcheng.zhu@gmail.com Thu Apr 15 18:38:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Apr 2010 18:39:11 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:50034 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492419Ab0DOQit (ORCPT ); Thu, 15 Apr 2010 18:38:49 +0200 Received: by pwj4 with SMTP id 4so1289591pwj.36 for ; Thu, 15 Apr 2010 09:38:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=kcPhAHKifHLEL21oLKW+xVV1+jJD9XfNr9XBV8GrIb0=; b=k603VkG9MLZjTzKBzF5d7L7IrOSq2E4CCUy8ub7ZTeoVv4AFgsogeJdZII636oE3UM o8T28pzUftHSHjHT9tAoxtWDKxmnasGjjmGbMQUUZ0zmFFbE669uOtZvrC4sVjDGkfn7 Yg3+rKIt/b8At8ptmeSZTv9yvgEuouKLl1Ivs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=meqL2bArF7Ot4NPBQr/2LbjlZQEpNPbJTKbuzEA0fSyETk/4TSx0KP0SUJ9y5wuRMO 09lcrO6nUfaWjkjp8vexdn5IP1MB6mvumpQkPl6/oKa/o3HR47UrK7MXgwGwdgMQBOM8 qd/YvnaYr8x7umnrB2SVDS9Sl4nXXnbautkVI= Received: by 10.142.1.35 with SMTP id 35mr296375wfa.26.1271349520527; Thu, 15 Apr 2010 09:38:40 -0700 (PDT) Received: from [192.168.1.101] ([114.84.94.52]) by mx.google.com with ESMTPS id 21sm456994yxe.39.2010.04.15.09.38.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Apr 2010 09:38:40 -0700 (PDT) Subject: [PATCH 0/3] MIPS performance event support initial version From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 16 Apr 2010 00:38:31 +0800 Message-ID: <1271349511.7467.419.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26414 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips This patch series implemented the low-level logic for the Linux performance counter subsystem on MIPS, which enables the collection of all sorts of HW/SW performance events based on per-CPU or per-task. An overview of this implementation is as follows: - Using generic atomic64 operations from lib. - SMVP/UP kernels are supported (not for SMTC). - 24K/34K/74K cores are implemented. - Currently working when Oprofile is _not_ available. - Minimal software perf events are supported. Tests were carried on the Malta-R board. The mentioned cores and kernel flavors were tested. For more information, please refer to the particular patches. Deng-Cheng Zhu (3): - MIPS: use the generic atomic64 operations for perf counter support - MIPS: adding support for software perf events - MIPS: implement hardware perf event support From dengcheng.zhu@gmail.com Thu Apr 15 18:39:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Apr 2010 18:39:34 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:41780 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492434Ab0DOQjC (ORCPT ); Thu, 15 Apr 2010 18:39:02 +0200 Received: by pvc30 with SMTP id 30so1011890pvc.36 for ; Thu, 15 Apr 2010 09:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=+6pjBhVj0k+jbHNxNp8wm1b8CJ+sAE16vGcSvqQkzoU=; b=YUnsuk3Lx44aSF0MzwSIV5uuwENjhRVBcWGFyw2RT6rYFr8+iBRB9oZSR/Dy7Q5TqE 9lBKqTbmqxOP9JVCjcLh4UEXYU004Qu15cXTZjIVWExudlfhBAdblTamPC73Yu/BN16G pTAIrXzxuBaXMhmek15lC8tT+2AwF2Jg/loFc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=JqKQyTwyXV/zF2t5EmkRMYtfNWGvixyJGcAv7vc8yGR1YISNiG2TE6PytpBiDj5KOt /BkNrrQ7v1JwQte9zhHuILbOlVfWIXQE1UgPdknZR5eZfCdH9TnZZI2jx/2DcsVRkMWy v+02Ua78H02Cw4YPHFeUPyWQAr/VgizQS6RaA= Received: by 10.143.21.32 with SMTP id y32mr289921wfi.60.1271349534123; Thu, 15 Apr 2010 09:38:54 -0700 (PDT) Received: from [192.168.1.101] ([114.84.94.52]) by mx.google.com with ESMTPS id 20sm491399ywh.48.2010.04.15.09.38.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Apr 2010 09:38:53 -0700 (PDT) Subject: [PATCH 1/3] MIPS: use the generic atomic64 operations for perf counter support From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 16 Apr 2010 00:38:45 +0800 Message-ID: <1271349525.7467.420.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26415 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Currently we take the generic spinlock'ed atomic64 implementation from the lib. The atomic64 types and related functions are needed for the Linux performance counter subsystem. Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 1 + arch/mips/include/asm/atomic.h | 4 ++++ 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 29e8692..7161751 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,7 @@ config MIPS select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE select HAVE_OPROFILE + select GENERIC_ATOMIC64 select HAVE_ARCH_KGDB select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACE_MCOUNT_TEST diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 519197e..b0a932e 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -21,6 +21,10 @@ #include #include +#ifdef CONFIG_GENERIC_ATOMIC64 +#include +#endif + #define ATOMIC_INIT(i) { (i) } /* -- 1.7.0.4 From dengcheng.zhu@gmail.com Thu Apr 15 18:39:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Apr 2010 18:40:00 +0200 (CEST) Received: from mail-qy0-f193.google.com ([209.85.221.193]:64437 "EHLO mail-qy0-f193.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492451Ab0DOQjR (ORCPT ); Thu, 15 Apr 2010 18:39:17 +0200 Received: by qyk31 with SMTP id 31so1605991qyk.20 for ; Thu, 15 Apr 2010 09:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=igA0X9v1WXPupNGpA7+1h5LTmrdMaeVdBLpiAFHNN5g=; b=vsLX5NCd65Y/dOUYu2UYD9yLxRrwWYOkpJuXImZii9W8vkhLDRIdnle/4YGmtm44vB f5yx+gS+B5X5NQXkmSMUpCD+U4dEEcXX2s0PT8WLS1Ysnq1jbUN41xrOYFUHVFqwBL45 mcHylXV71iXaAbLVfChbeTc9fo4Sk+xiC20LM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=TK3pPJF8B3omEIaCNo/9XoCSx6J/w35rtUKZCytfPXMD4G0FpsLHsefsBSfS2j2534 40K7kOt888mxkl/D6sb4KdzAG950Y6YBclKZo8if02jz+GAYIEJ5ls3NXm2iqREV384t Ndl5Qobe3Kcq0VYZ8Ky6nMUiQ1o8h+UYm1aX8= Received: by 10.229.227.5 with SMTP id iy5mr268342qcb.29.1271349549355; Thu, 15 Apr 2010 09:39:09 -0700 (PDT) Received: from [192.168.1.101] ([114.84.94.52]) by mx.google.com with ESMTPS id w30sm1892903qce.4.2010.04.15.09.39.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Apr 2010 09:39:08 -0700 (PDT) Subject: [PATCH 2/3] MIPS: adding support for software perf events From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 16 Apr 2010 00:39:00 +0800 Message-ID: <1271349540.7467.423.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26416 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips This is the minimal support for the SW perf events, required as a part of the measurable stuff by the Linux performance counter subsystem. Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 2 ++ arch/mips/include/asm/perf_event.h | 28 ++++++++++++++++++++++++++++ arch/mips/mm/fault.c | 11 +++++++++-- 3 files changed, 39 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/perf_event.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7161751..cf33418 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,8 @@ config MIPS select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE select HAVE_OPROFILE + select HAVE_PERF_EVENTS + select PERF_USE_VMALLOC select GENERIC_ATOMIC64 select HAVE_ARCH_KGDB select HAVE_FUNCTION_TRACER diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h new file mode 100644 index 0000000..bcf54bc --- /dev/null +++ b/arch/mips/include/asm/perf_event.h @@ -0,0 +1,28 @@ +/* + * linux/arch/mips/include/asm/perf_event.h + * + * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __MIPS_PERF_EVENT_H__ +#define __MIPS_PERF_EVENT_H__ + +extern int (*perf_irq)(void); + +/* + * MIPS performance counters do not raise NMI upon overflow, a regular + * interrupt will be signaled. Hence we can do the pending perf event + * work at the tail of the irq handler. + */ +static inline void +set_perf_event_pending(void) +{ +} + +#endif /* __MIPS_PERF_EVENT_H__ */ + diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index b78f7d9..5987d2b 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -18,6 +18,7 @@ #include #include /* For unblank_screen() */ #include +#include #include #include @@ -132,6 +133,7 @@ good_area: * the fault. */ fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -139,10 +141,15 @@ good_area: goto do_sigbus; BUG(); } - if (fault & VM_FAULT_MAJOR) + if (fault & VM_FAULT_MAJOR) { + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, + 1, 0, regs, address); tsk->maj_flt++; - else + } else { + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, + 1, 0, regs, address); tsk->min_flt++; + } up_read(&mm->mmap_sem); return; -- 1.7.0.4 From dengcheng.zhu@gmail.com Thu Apr 15 18:40:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Apr 2010 18:40:28 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:40917 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492453Ab0DOQjq (ORCPT ); Thu, 15 Apr 2010 18:39:46 +0200 Received: by pwj4 with SMTP id 4so1290781pwj.36 for ; Thu, 15 Apr 2010 09:39:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=u7ELsplkqggH0rLmaDu9xo/gFkw5NJY3QwZgcqz0h0Q=; b=MOtyw/TEyrXFZdYjaX18CpyEUz6GTiXce6sTnnlECeOWsyDCIveMbbzz5cB/hhyadc An9wEq1u6P5m6RjkMEtqgodgDDUL8zSKdkad+MRur8fdKJvTo1ddtdwuHKzbbYFgU31D QalUb3kS8/S7wSy6pEB6Zex3IDLhI/Mwlb6tw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=rcej/2mMbfFiEx6YRGTfVEEKDJW/tho3IWfODGO8Qj9dug36/yzcJPO8LefKoAUgri wCYWwQY0xZz9e6P+VekhOTZ8LuRxkpq5fuK1X9HgdUrwQussg9h4qQeQUfmw9vn5Bjty iwYwW5/Y/BlzbJswgsaFmQOCMHbjO38+0ZjJ4= Received: by 10.141.124.2 with SMTP id b2mr616807rvn.23.1271349576664; Thu, 15 Apr 2010 09:39:36 -0700 (PDT) Received: from [192.168.1.101] ([114.84.94.52]) by mx.google.com with ESMTPS id 5sm452806yxd.53.2010.04.15.09.39.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Apr 2010 09:39:27 -0700 (PDT) Subject: [PATCH 3/3] MIPS: implement hardware perf event support From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 16 Apr 2010 00:39:17 +0800 Message-ID: <1271349557.7467.424.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26417 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips This patch is the HW perf event support. To enable this feature, we can not choose the SMTC kernel; Oprofile should be disabled; kernel performance events be selected. Then we can enable it in the Kernel type menu. Oprofile for MIPS platforms initializes irq at arch init time. Currently we do not change this logic to allow PMU reservation. If a platform has EIC, we can use the irq base and perf counter irq offset defines for the interrupt controller in mipspmu_get_irq(). Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 8 + arch/mips/kernel/Makefile | 2 + arch/mips/kernel/perf_event.c | 1468 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1478 insertions(+), 0 deletions(-) create mode 100644 arch/mips/kernel/perf_event.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index cf33418..9aac9b5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1857,6 +1857,14 @@ config NODES_SHIFT default "6" depends on NEED_MULTIPLE_NODES +config HW_PERF_EVENTS + bool "Enable hardware performance counter support for perf events" + depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n + default y + help + Enable hardware performance counter support for perf events. If + disabled, perf events will use software events only. + source "mm/Kconfig" config SMP diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 7a6ac50..c934ab7 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -101,6 +101,8 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/ +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o + EXTRA_CFLAGS += -Werror CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c new file mode 100644 index 0000000..49d101e --- /dev/null +++ b/arch/mips/kernel/perf_event.c @@ -0,0 +1,1468 @@ +/* + * Linux performance counter support for MIPS. + * + * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu + * + * This code is based on the implementation for ARM, which is in turn + * based on the sparc64 perf event code and the x86 code. Performance + * counter access is based on the MIPS Oprofile code. And the callchain + * support references the code of MIPS traps.c. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +#define MAX_PERIOD ((1ULL << 32) - 1) + +/* + * FIXME: For VSMP, originally Oprofile defines vpe_id() like this: + * #define vpe_id() (cpu_has_mipsmt_pertccounters ? \ + * 0 : cpu_data[smp_processor_id()].vpe_id) + * + * It is now redefined lower, because cpu_data[cpuid].vpe_id reports 0 + * for _both_ CPUs. + * + * Copied from Oprofile -- BEGIN + */ +#define M_CONFIG1_PC (1 << 4) +#define M_PERFCTL_EXL (1UL << 0) +#define M_PERFCTL_KERNEL (1UL << 1) +#define M_PERFCTL_SUPERVISOR (1UL << 2) +#define M_PERFCTL_USER (1UL << 3) +#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) +#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) +#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) +#define M_PERFCTL_MT_EN(filter) ((filter) << 20) +#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) +#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) +#define M_TC_EN_TC M_PERFCTL_MT_EN(2) +#define M_PERFCTL_TCID(tcid) ((tcid) << 22) +#define M_PERFCTL_WIDE (1UL << 30) +#define M_PERFCTL_MORE (1UL << 31) + +#define M_COUNTER_OVERFLOW (1UL << 31) + +static int (*save_perf_irq)(void); + +#ifdef CONFIG_MIPS_MT_SMP +static int cpu_has_mipsmt_pertccounters; +#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ + 0 : smp_processor_id()) + +/* + * The number of bits to shift to convert between counters per core and + * counters per VPE. There is no reasonable interface atm to obtain the + * number of VPEs used by Linux and in the 34K this number is fixed to two + * anyways so we hardcore a few things here for the moment. The way it's + * done here will ensure that oprofile VSMP kernel will run right on a lesser + * core like a 24K also or with maxcpus=1. + */ +static inline unsigned int vpe_shift(void) +{ + if (num_possible_cpus() > 1) + return 1; + + return 0; +} + +#else + +#define vpe_id() 0 + +static inline unsigned int vpe_shift(void) +{ + return 0; +} + +#endif + +static inline unsigned int +counters_total_to_per_cpu(unsigned int counters) +{ + return counters >> vpe_shift(); +} + +static inline unsigned int +counters_per_cpu_to_total(unsigned int counters) +{ + return counters << vpe_shift(); +} + +#define __define_perf_accessors(r, n, np) \ + \ +static inline unsigned int r_c0_ ## r ## n(void) \ +{ \ + unsigned int cpu = vpe_id(); \ + \ + switch (cpu) { \ + case 0: \ + return read_c0_ ## r ## n(); \ + case 1: \ + return read_c0_ ## r ## np(); \ + default: \ + BUG(); \ + } \ + return 0; \ +} \ + \ +static inline void w_c0_ ## r ## n(unsigned int value) \ +{ \ + unsigned int cpu = vpe_id(); \ + \ + switch (cpu) { \ + case 0: \ + write_c0_ ## r ## n(value); \ + return; \ + case 1: \ + write_c0_ ## r ## np(value); \ + return; \ + default: \ + BUG(); \ + } \ + return; \ +} \ + +__define_perf_accessors(perfcntr, 0, 2) +__define_perf_accessors(perfcntr, 1, 3) +__define_perf_accessors(perfcntr, 2, 0) +__define_perf_accessors(perfcntr, 3, 1) + +__define_perf_accessors(perfctrl, 0, 2) +__define_perf_accessors(perfctrl, 1, 3) +__define_perf_accessors(perfctrl, 2, 0) +__define_perf_accessors(perfctrl, 3, 1) + +static inline int __n_counters(void) +{ + if (!(read_c0_config1() & M_CONFIG1_PC)) + return 0; + if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) + return 1; + if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) + return 2; + if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) + return 3; + + return 4; +} + +static inline int n_counters(void) +{ + int counters; + + switch (current_cpu_type()) { + case CPU_R10000: + counters = 2; + break; + + case CPU_R12000: + case CPU_R14000: + counters = 4; + break; + + default: + counters = __n_counters(); + } + + return counters; +} + +static void reset_counters(void *arg) +{ + int counters = (int)(long)arg; + switch (counters) { + case 4: + w_c0_perfctrl3(0); + w_c0_perfcntr3(0); + case 3: + w_c0_perfctrl2(0); + w_c0_perfcntr2(0); + case 2: + w_c0_perfctrl1(0); + w_c0_perfcntr1(0); + case 1: + w_c0_perfctrl0(0); + w_c0_perfcntr0(0); + } +} +/* Copied from Oprofile -- END */ + +static inline unsigned int +mips_pmu_read_counter(unsigned int idx) +{ + switch (idx) { + case 0: + return r_c0_perfcntr0(); + case 1: + return r_c0_perfcntr1(); + case 2: + return r_c0_perfcntr2(); + case 3: + return r_c0_perfcntr3(); + default: + WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); + return 0; + } +} + +static inline void +mips_pmu_write_counter(unsigned int idx, unsigned int val) +{ + switch (idx) { + case 0: + w_c0_perfcntr0(val); + return; + case 1: + w_c0_perfcntr1(val); + return; + case 2: + w_c0_perfcntr2(val); + return; + case 3: + w_c0_perfcntr3(val); + return; + } +} + +static inline unsigned int +mips_pmu_read_control(unsigned int idx) +{ + switch (idx) { + case 0: + return r_c0_perfctrl0(); + case 1: + return r_c0_perfctrl1(); + case 2: + return r_c0_perfctrl2(); + case 3: + return r_c0_perfctrl3(); + default: + WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); + return 0; + } +} + +static inline void +mips_pmu_write_control(unsigned int idx, unsigned int val) +{ + switch (idx) { + case 0: + w_c0_perfctrl0(val); + return; + case 1: + w_c0_perfctrl1(val); + return; + case 2: + w_c0_perfctrl2(val); + return; + case 3: + w_c0_perfctrl3(val); + return; + } +} + +#define M_PERFCTL_COUNT_EVENT_WHENEVER \ + (M_PERFCTL_EXL | M_PERFCTL_KERNEL | \ + M_PERFCTL_USER | M_PERFCTL_SUPERVISOR | \ + M_PERFCTL_INTERRUPT_ENABLE) + +#ifdef CONFIG_MIPS_MT_SMP +#define M_PERFCTL_CONFIG_MASK 0x3fff801f +#else +#define M_PERFCTL_CONFIG_MASK 0x1f +#endif +#define M_PERFCTL_EVENT_MASK 0xfe0 + +#define MIPS_MAX_HWEVENTS 4 + +struct cpu_hw_events { + /* Array of events on this cpu. */ + struct perf_event *events[MIPS_MAX_HWEVENTS]; + + /* + * Set the bit (indexed by the counter number) when the counter + * is used for an event. + */ + unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; + + /* + * The borrowed MSB for the performance counter. A MIPS performance + * counter uses its bit 31 as a factor of determining whether a counter + * overflow should be signaled. So here we use a separate MSB for each + * counter to make things easy. + */ + unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; + + /* + * Software copy of the control register for each performance counter. + */ + unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; +}; +DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { + .saved_ctrl = {0}, +}; + +/* The description of MIPS performance events. */ +struct mips_perf_event { + u32 event_id; + u32 cntr_mask; + #define CNTR_EVEN 0x55555555 + #define CNTR_ODD 0xaaaaaaaa +#ifdef CONFIG_MIPS_MT_SMP + enum { + T = 0, + V = 1, + P = 2, + } range; +#else + #define T + #define V + #define P +#endif +}; + +#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff +#define C(x) PERF_COUNT_HW_CACHE_##x + +struct mips_pmu { + const char *name; + irqreturn_t (*handle_irq)(int irq, void *dev); + int (*handle_shared_irq)(void); + void (*start)(void); + void (*stop)(void); + int (*alloc_counter)(struct cpu_hw_events *cpuc, + struct hw_perf_event *hwc); + unsigned int (*read_counter)(unsigned int idx); + void (*write_counter)(unsigned int idx, unsigned int val); + void (*enable_event)(struct hw_perf_event *evt, int idx); + void (*disable_event)(int idx); + const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; + const struct mips_perf_event (*cache_event_map) + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + u32 num_counters; +}; + +static const struct mips_pmu *mipspmu; + +#ifdef CONFIG_MIPS_MT_SMP +static DEFINE_RWLOCK(pmuint_rwlock); +#endif + +/* 24K/34K/1004K cores can share the same event map. */ +static const struct mips_perf_event mipscore_event_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, + [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, + [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, + [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, + [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, +}; + +/* 74K core has different branch event code. */ +static const struct mips_perf_event mips74Kcore_event_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, + [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, + [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, + [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, + [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, +}; + +/* 24K/34K/1004K cores can share the same cache event map. */ +static const struct mips_perf_event mipscore_cache_map + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { +[C(L1D)] = { + /* + * Like some other architectures (e.g. ARM), the performance + * counters don't differentiate between read and write + * accesses/misses, so this isn't strictly correct, but it's the + * best we can do. Writes and reads get combined. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, + /* + * Note that MIPS has only "hit" events countable for + * the prefetch operation. + */ + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(DTLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(BPU)] = { + /* Using the same code for *HW_BRANCH* */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +}; + +/* 74K core has completely different cache event map. */ +static const struct mips_perf_event mips74Kcore_cache_map + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { +[C(L1D)] = { + /* + * Like some other architectures (e.g. ARM), the performance + * counters don't differentiate between read and write + * accesses/misses, so this isn't strictly correct, but it's the + * best we can do. Writes and reads get combined. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, + [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, + [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T}, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, + /* + * Note that MIPS has only "hit" events countable for + * the prefetch operation. + */ + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(DTLB)] = { + /* 74K core does not have specific DTLB events. */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(BPU)] = { + /* Using the same code for *HW_BRANCH* */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +}; + +static int +mipspmu_event_set_period(struct perf_event *event, + struct hw_perf_event *hwc, + int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + s64 left = atomic64_read(&hwc->period_left); + s64 period = hwc->sample_period; + int ret = 0; + unsigned long flags, uleft; + + if (unlikely(left <= -period)) { + left = period; + atomic64_set(&hwc->period_left, left); + hwc->last_period = period; + ret = 1; + } + + if (unlikely(left <= 0)) { + left += period; + atomic64_set(&hwc->period_left, left); + hwc->last_period = period; + ret = 1; + } + + if (left > (s64)MAX_PERIOD) + left = MAX_PERIOD; + + atomic64_set(&hwc->prev_count, (u64)-left); + + local_irq_save(flags); + uleft = (u64)(-left) & 0xffffffff; + test_bit(31, &uleft) ? + set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs); + mipspmu->write_counter(idx, (u64)(-left) & 0x7fffffff); + local_irq_restore(flags); + + perf_event_update_userpage(event); + + return ret; +} + +static int mipspmu_enable(struct perf_event *event) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct hw_perf_event *hwc = &event->hw; + int idx; + int err = 0; + + /* To look for a free counter for this event. */ + idx = mipspmu->alloc_counter(cpuc, hwc); + if (idx < 0) { + err = idx; + goto out; + } + + /* + * If there is an event in the counter we are going to use then + * make sure it is disabled. + */ + event->hw.idx = idx; + mipspmu->disable_event(idx); + cpuc->events[idx] = event; + + /* Set the period for the event. */ + mipspmu_event_set_period(event, hwc, idx); + + /* Enable the event. */ + mipspmu->enable_event(hwc, idx); + + /* Propagate our changes to the userspace mapping. */ + perf_event_update_userpage(event); + +out: + return err; +} + +static void mipspmu_event_update(struct perf_event *event, + struct hw_perf_event *hwc, + int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + int shift = 64 - 32; + s64 prev_raw_count, new_raw_count; + s64 delta; + +again: + prev_raw_count = atomic64_read(&hwc->prev_count); + local_irq_save(flags); + /* Make the counter value be a "real" one. */ + new_raw_count = mipspmu->read_counter(idx); + if (new_raw_count & (test_bit(idx, cpuc->msbs) << 31)) { + new_raw_count &= 0x7fffffff; + clear_bit(idx, cpuc->msbs); + } else + new_raw_count |= (test_bit(idx, cpuc->msbs) << 31); + local_irq_restore(flags); + + if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, + new_raw_count) != prev_raw_count) + goto again; + + delta = (new_raw_count << shift) - (prev_raw_count << shift); + delta >>= shift; + + atomic64_add(delta, &event->count); + atomic64_sub(delta, &hwc->period_left); + + return; +} + +static void mipspmu_disable(struct perf_event *event) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + /* We are working on a local event. */ + mipspmu->disable_event(idx); + + barrier(); + + mipspmu_event_update(event, hwc, idx); + cpuc->events[idx] = NULL; + clear_bit(idx, cpuc->used_mask); + + perf_event_update_userpage(event); +} + +static void mipspmu_unthrottle(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + + mipspmu->enable_event(hwc, hwc->idx); +} + +static void mipspmu_read(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + + /* Don't read disabled counters! */ + if (hwc->idx < 0) + return; + + mipspmu_event_update(event, hwc, hwc->idx); +} + +static struct pmu pmu = { + .enable = mipspmu_enable, + .disable = mipspmu_disable, + .unthrottle = mipspmu_unthrottle, + .read = mipspmu_read, +}; + +static atomic_t active_events = ATOMIC_INIT(0); +static DEFINE_MUTEX(pmu_reserve_mutex); +static int mips_pmu_irq = -1; + +static int mipspmu_get_irq(void) +{ + int err; + + if (cpu_has_veic) { + /* + * Using platform specific interrupt controller defines. + */ +#ifdef MSC01E_INT_BASE + mips_pmu_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; +#endif + } else if (cp0_perfcount_irq >= 0) { + /* + * Some CPUs have explicitly defined their perfcount irq. + */ +#if defined(CONFIG_CPU_RM9000) + mips_pmu_irq = rm9000_perfcount_irq; +#elif defined(CONFIG_CPU_LOONGSON2) + mips_pmu_irq = LOONGSON2_PERFCNT_IRQ; +#else + mips_pmu_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; +#endif + } + + if (mips_pmu_irq >= 0) { + /* Request my own irq handler. */ + err = request_irq(mips_pmu_irq, mipspmu->handle_irq, + IRQF_DISABLED | IRQF_NOBALANCING, + "mips_perf_pmu", NULL); + if (err) { + pr_warning("Unable to request IRQ%d for MIPS " + "performance counters!\n", mips_pmu_irq); + } + } else if (cp0_perfcount_irq < 0) { + /* + * We are sharing the irq number with the timer interrupt. + */ + save_perf_irq = perf_irq; + perf_irq = mipspmu->handle_shared_irq; + err = 0; + } else { + pr_warning("The platform hasn't properly defined its " + "interrupt controller.\n"); + err = -ENOENT; + } + + return err; +} + +static void mipspmu_free_irq(void) +{ + if (mips_pmu_irq >= 0) + free_irq(mips_pmu_irq, NULL); + else if (cp0_perfcount_irq < 0) + perf_irq = save_perf_irq; + + mips_pmu_irq = -1; +} + +static void hw_perf_event_destroy(struct perf_event *event) +{ + if (atomic_dec_and_mutex_lock(&active_events, + &pmu_reserve_mutex)) { + /* + * We must not call the destroy function with interrupts + * disabled. + */ + on_each_cpu(reset_counters, + (void *)(long)mipspmu->num_counters, 1); + mipspmu_free_irq(); + mutex_unlock(&pmu_reserve_mutex); + } +} + +#ifdef CONFIG_MIPS_MT_SMP +static int +calc_and_check_range(struct perf_event *event, + const struct mips_perf_event *pev) +{ + struct hw_perf_event *hwc = &event->hw; + + if (event->cpu >= 0) { + if (pev->range > V) { + /* + * The user selected an event that is processor + * wide, while expecting it to be VPE wide. + */ + hwc->config_base |= M_TC_EN_ALL; + } else { + /* + * FIXME: cpu_data[event->cpu].vpe_id reports 0 + * for both CPUs. + */ + hwc->config_base |= M_PERFCTL_VPEID(event->cpu); + hwc->config_base |= M_TC_EN_VPE; + } + } else + hwc->config_base |= M_TC_EN_ALL; + + return 0; +} +#else +static int +calc_and_check_range(struct perf_event *event, + const struct mips_perf_event *pev) +{ + return 0; +} +#endif + +static inline u32 perf_event_encode(const struct mips_perf_event *pev) +{ +/* + * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for + * event_id. + */ +#ifdef CONFIG_MIPS_MT_SMP + return ((u32) pev->range << 24) | + (pev->cntr_mask & 0xffff00) | + (pev->event_id & 0xff); +#else + return (pev->cntr_mask & 0xffff00) | + (pev->event_id & 0xff); +#endif +} + +static int validate_event(struct cpu_hw_events *cpuc, + struct perf_event *event) +{ + struct hw_perf_event fake_hwc = event->hw; + + if (event->pmu && event->pmu != &pmu) + return 0; + + return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; +} + +static int validate_group(struct perf_event *event) +{ + struct perf_event *sibling, *leader = event->group_leader; + struct cpu_hw_events fake_cpuc; + + memset(&fake_cpuc, 0, sizeof(fake_cpuc)); + + if (!validate_event(&fake_cpuc, leader)) + return -ENOSPC; + + list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + if (!validate_event(&fake_cpuc, sibling)) + return -ENOSPC; + } + + if (!validate_event(&fake_cpuc, event)) + return -ENOSPC; + + return 0; +} + +static const struct mips_perf_event * +mips_pmu_map_general_event(int idx) +{ + const struct mips_perf_event *pev; + + pev = ((*mipspmu->general_event_map)[idx].event_id == + UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) : + &(*mipspmu->general_event_map)[idx]); + + return pev; +} + +static const struct mips_perf_event * +mips_pmu_map_cache_event(u64 config) +{ + unsigned int cache_type, cache_op, cache_result; + const struct mips_perf_event *pev; + + cache_type = (config >> 0) & 0xff; + if (cache_type >= PERF_COUNT_HW_CACHE_MAX) + return ERR_PTR(-EINVAL); + + cache_op = (config >> 8) & 0xff; + if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) + return ERR_PTR(-EINVAL); + + cache_result = (config >> 16) & 0xff; + if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) + return ERR_PTR(-EINVAL); + + pev = &((*mipspmu->cache_event_map) + [cache_type] + [cache_op] + [cache_result]); + + if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID) + return ERR_PTR(-EOPNOTSUPP); + + return pev; + +} + +static int __hw_perf_event_init(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + struct hw_perf_event *hwc = &event->hw; + const struct mips_perf_event *pev; + int err; + + /* Returning MIPS event descriptor for generic perf event. */ + if (PERF_TYPE_HARDWARE == event->attr.type) { + if (event->attr.config >= PERF_COUNT_HW_MAX) + return -EINVAL; + pev = mips_pmu_map_general_event(event->attr.config); + } else if (PERF_TYPE_HW_CACHE == event->attr.type) { + pev = mips_pmu_map_cache_event(event->attr.config); + } else { + return -EOPNOTSUPP; + } + + if (IS_ERR(pev)) + return PTR_ERR(pev); + + /* + * We allow max flexibility on how each individual counter shared + * by the single CPU operates (the mode exclusion and the range). + */ + hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE; + + /* Calculate range bits and validate it. */ + err = calc_and_check_range(event, pev); + if (err < 0) + return err; + + if (!attr->exclude_user) + hwc->config_base |= M_PERFCTL_USER; + if (!attr->exclude_kernel) { + hwc->config_base |= M_PERFCTL_KERNEL; + /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */ + hwc->config_base |= M_PERFCTL_EXL; + } + if (!attr->exclude_hv) + hwc->config_base |= M_PERFCTL_SUPERVISOR; + + hwc->config_base &= M_PERFCTL_CONFIG_MASK; + hwc->event_base = perf_event_encode(pev); + /* + * The event can belong to another cpu. We do not assign a local + * counter for it for now. + */ + hwc->idx = -1; + hwc->config = 0; + + if (!hwc->sample_period) { + hwc->sample_period = MAX_PERIOD; + hwc->last_period = hwc->sample_period; + atomic64_set(&hwc->period_left, hwc->sample_period); + } + + err = 0; + if (event->group_leader != event) { + err = validate_group(event); + if (err) + return -EINVAL; + } + + event->destroy = hw_perf_event_destroy; + + return err; +} + +const struct pmu *hw_perf_event_init(struct perf_event *event) +{ + int err = 0; + + if (!mipspmu || event->cpu >= nr_cpumask_bits || + (event->cpu >= 0 && !cpu_online(event->cpu))) + return ERR_PTR(-ENODEV); + + if (!atomic_inc_not_zero(&active_events)) { + if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) { + atomic_dec(&active_events); + return ERR_PTR(-ENOSPC); + } + + mutex_lock(&pmu_reserve_mutex); + if (atomic_read(&active_events) == 0) + err = mipspmu_get_irq(); + + if (!err) + atomic_inc(&active_events); + mutex_unlock(&pmu_reserve_mutex); + } + + if (err) + return ERR_PTR(err); + + err = __hw_perf_event_init(event); + if (err) + hw_perf_event_destroy(event); + + return err ? ERR_PTR(err) : &pmu; +} + +void hw_perf_enable(void) +{ + if (mipspmu) + mipspmu->start(); +} + +void hw_perf_disable(void) +{ + if (mipspmu) + mipspmu->stop(); +} + +static void +handle_associated_event(struct cpu_hw_events *cpuc, + int idx, struct perf_sample_data *data, struct pt_regs *regs) +{ + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc = &event->hw; + + mipspmu_event_update(event, hwc, idx); + data->period = event->hw.last_period; + if (!mipspmu_event_set_period(event, hwc, idx)) + return; + + if (perf_event_overflow(event, 0, data, regs)) + mipspmu->disable_event(idx); +} + +static void pause_local_counters(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + int counters = mipspmu->num_counters; + unsigned long flags; + + local_irq_save(flags); + switch (counters) { + case 4: + cpuc->saved_ctrl[3] = r_c0_perfctrl3(); + w_c0_perfctrl3(cpuc->saved_ctrl[3] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + case 3: + cpuc->saved_ctrl[2] = r_c0_perfctrl2(); + w_c0_perfctrl2(cpuc->saved_ctrl[2] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + case 2: + cpuc->saved_ctrl[1] = r_c0_perfctrl1(); + w_c0_perfctrl1(cpuc->saved_ctrl[1] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + case 1: + cpuc->saved_ctrl[0] = r_c0_perfctrl0(); + w_c0_perfctrl0(cpuc->saved_ctrl[0] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + } + local_irq_restore(flags); +} + +static void resume_local_counters(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + int counters = mipspmu->num_counters; + unsigned long flags; + + local_irq_save(flags); + switch (counters) { + case 4: + w_c0_perfctrl3(cpuc->saved_ctrl[3]); + case 3: + w_c0_perfctrl2(cpuc->saved_ctrl[2]); + case 2: + w_c0_perfctrl1(cpuc->saved_ctrl[1]); + case 1: + w_c0_perfctrl0(cpuc->saved_ctrl[0]); + } + local_irq_restore(flags); +} + +static int mips_pmu_handle_shared_irq(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct perf_sample_data data; + unsigned int counters = mipspmu->num_counters; + unsigned int counter; + int handled = IRQ_NONE; + struct pt_regs *regs; + + if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) + return handled; + + /* + * First we pause the local counters, so that when we are locked + * here, the counters are all paused. When it gets locked due to + * perf_disable(), the timer interrupt handler will be delayed. + * + * See also mips_pmu_start(). + */ + pause_local_counters(); +#ifdef CONFIG_MIPS_MT_SMP + read_lock(&pmuint_rwlock); +#endif + + regs = get_irq_regs(); + + perf_sample_data_init(&data, 0); + + switch (counters) { +#define HANDLE_COUNTER(n) \ + case n + 1: \ + if (test_bit(n, cpuc->used_mask)) { \ + counter = r_c0_perfcntr ## n(); \ + if (counter & M_COUNTER_OVERFLOW) { \ + w_c0_perfcntr ## n(counter & \ + 0x7fffffff); \ + if (test_and_change_bit(n, cpuc->msbs)) \ + handle_associated_event(cpuc, \ + n, &data, regs); \ + handled = IRQ_HANDLED; \ + } \ + } + HANDLE_COUNTER(3) + HANDLE_COUNTER(2) + HANDLE_COUNTER(1) + HANDLE_COUNTER(0) + } + + /* + * Do all the work for the pending perf events. We can do this + * in here because the performance counter interrupt is a regular + * interrupt, not NMI. + */ + if (handled == IRQ_HANDLED) + perf_event_do_pending(); + +#ifdef CONFIG_MIPS_MT_SMP + read_unlock(&pmuint_rwlock); +#endif + resume_local_counters(); + return handled; +} + +static irqreturn_t +mips_pmu_handle_irq(int irq, void *dev) +{ + return mips_pmu_handle_shared_irq(); +} + +static void mips_pmu_start(void) +{ +#ifdef CONFIG_MIPS_MT_SMP + write_unlock(&pmuint_rwlock); +#endif + resume_local_counters(); +} + +/* + * MIPS performance counters can be per-TC. The control registers can + * not be directly accessed accross CPUs. Hence if we want to do global + * control, we need cross CPU calls. on_each_cpu() can help us, but we + * can not make sure this function is called with interrupts enabled. So + * here we pause local counters and then grab a rwlock and leave the + * counters on other CPUs alone. If any counter interrupt raises while + * we own the write lock, simply pause local counters on that CPU and + * spin in the handler. Also we know we won't be switched to another + * CPU after pausing local counters and before grabbing the lock. + */ +static void mips_pmu_stop(void) +{ + pause_local_counters(); +#ifdef CONFIG_MIPS_MT_SMP + write_lock(&pmuint_rwlock); +#endif +} + +static int +mips_pmu_alloc_counter(struct cpu_hw_events *cpuc, + struct hw_perf_event *hwc) +{ + int i; + + /* + * We only need to care the counter mask. The range has been + * checked definitely. + */ + unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; + + for (i = mipspmu->num_counters - 1; i >= 0; i--) { + /* + * Note that some MIPS perf events can be counted by both + * even and odd counters, wheresas many other are only by + * even _or_ odd counters. This introduces an issue that + * when the former kind of event takes the counter the + * latter kind of event wants to use, then the "counter + * allocation" for the latter event will fail. In fact if + * they can be dynamically swapped, they both feel happy. + * But here we leave this issue alone for now. + */ + if (test_bit(i, &cntr_mask) && + !test_and_set_bit(i, cpuc->used_mask)) + return i; + } + + return -EAGAIN; +} + +static void +mips_pmu_enable_event(struct hw_perf_event *evt, int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + local_irq_save(flags); + cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | + (evt->config_base & M_PERFCTL_CONFIG_MASK) | + /* Make sure interrupt enabled. */ + M_PERFCTL_INTERRUPT_ENABLE; + /* + * We do not actually let the counter run. Leave it until start(). + */ + local_irq_restore(flags); +} + +static void +mips_pmu_disable_event(int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + local_irq_save(flags); + cpuc->saved_ctrl[idx] = mips_pmu_read_control(idx) & + ~M_PERFCTL_COUNT_EVENT_WHENEVER; + mips_pmu_write_control(idx, cpuc->saved_ctrl[idx]); + local_irq_restore(flags); +} + +static struct mips_pmu mipscore_pmu = { + .handle_irq = mips_pmu_handle_irq, + .handle_shared_irq = mips_pmu_handle_shared_irq, + .start = mips_pmu_start, + .stop = mips_pmu_stop, + .alloc_counter = mips_pmu_alloc_counter, + .read_counter = mips_pmu_read_counter, + .write_counter = mips_pmu_write_counter, + .enable_event = mips_pmu_enable_event, + .disable_event = mips_pmu_disable_event, + .general_event_map = &mipscore_event_map, + .cache_event_map = &mipscore_cache_map, +}; + +static struct mips_pmu mips74Kcore_pmu = { + .handle_irq = mips_pmu_handle_irq, + .handle_shared_irq = mips_pmu_handle_shared_irq, + .start = mips_pmu_start, + .stop = mips_pmu_stop, + .alloc_counter = mips_pmu_alloc_counter, + .read_counter = mips_pmu_read_counter, + .write_counter = mips_pmu_write_counter, + .enable_event = mips_pmu_enable_event, + .disable_event = mips_pmu_disable_event, + .general_event_map = &mips74Kcore_event_map, + .cache_event_map = &mips74Kcore_cache_map, +}; + +static int __init +init_hw_perf_events(void) +{ + int counters; + + pr_info("Performance counters: "); + + counters = n_counters(); + if (counters == 0) { + pr_cont("No available PMU.\n"); + return -ENODEV; + } + +#ifdef CONFIG_MIPS_MT_SMP + cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19); + if (!cpu_has_mipsmt_pertccounters) + counters = counters_total_to_per_cpu(counters); +#endif + + on_each_cpu(reset_counters, (void *)(long)counters, 1); + + switch (current_cpu_type()) { + case CPU_24K: + mipscore_pmu.name = "mips/24K"; + mipscore_pmu.num_counters = counters; + mipspmu = &mipscore_pmu; + break; + case CPU_34K: + mipscore_pmu.name = "mips/34K"; + mipscore_pmu.num_counters = counters; + mipspmu = &mipscore_pmu; + break; + case CPU_74K: + mips74Kcore_pmu.name = "mips/74K"; + mips74Kcore_pmu.num_counters = counters; + mipspmu = &mips74Kcore_pmu; + break; + default: + pr_cont("Either hardware does not support performance " + "counters, or not yet implemented.\n"); + return -ENODEV; + } + + if (mipspmu) + pr_cont("%s PMU enabled, %d counters available to each " + "CPU\n", mipspmu->name, mipspmu->num_counters); + + return 0; +} +arch_initcall(init_hw_perf_events); + +/* + * Callchain handling code. + */ +static inline void +callchain_store(struct perf_callchain_entry *entry, + u64 ip) +{ + if (entry->nr < PERF_MAX_STACK_DEPTH) + entry->ip[entry->nr++] = ip; +} + +static void +perf_callchain_user(struct pt_regs *regs, + struct perf_callchain_entry *entry) +{ + unsigned long *sp; + unsigned long addr; + + callchain_store(entry, PERF_CONTEXT_USER); + + if (!user_mode(regs)) + regs = task_pt_regs(current); + + sp = (unsigned long *)(regs->regs[29] & ~3); + + while (!kstack_end(sp)) { + unsigned long __user *p = + (unsigned long __user *)(unsigned long)sp++; + if (__get_user(addr, p)) { + pr_warning("Performance counter callchain " + "suppport: Bad stack address.\n"); + break; + } + callchain_store(entry, addr); + } +} + +static void +perf_callchain_kernel(struct pt_regs *regs, + struct perf_callchain_entry *entry) +{ + unsigned long sp = regs->regs[29]; + unsigned long ra = regs->regs[31]; + unsigned long pc = regs->cp0_epc; + + if (unlikely(!__kernel_text_address(pc))) { + pr_warning("Performance counter callchain support " + "error.\n"); + return; + } + + callchain_store(entry, PERF_CONTEXT_KERNEL); + + do { + callchain_store(entry, pc); + pc = unwind_stack(current, &sp, pc, &ra); + } while (pc); +} + +static void +perf_do_callchain(struct pt_regs *regs, + struct perf_callchain_entry *entry) +{ + int is_user; + + if (!regs) + return; + + is_user = user_mode(regs); + + if (!current || !current->pid) + return; + + if (is_user && current->state != TASK_RUNNING) + return; + + if (!is_user) + perf_callchain_kernel(regs, entry); + + if (current->mm) + perf_callchain_user(regs, entry); +} + +static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); + +struct perf_callchain_entry * +perf_callchain(struct pt_regs *regs) +{ + struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry); + + entry->nr = 0; + perf_do_callchain(regs, entry); + return entry; +} + -- 1.7.0.4 From wuzhangjin@gmail.com Thu Apr 15 19:47:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Apr 2010 19:47:36 +0200 (CEST) Received: from mail-yx0-f183.google.com ([209.85.210.183]:37240 "EHLO mail-yx0-f183.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492068Ab0DORrd (ORCPT ); Thu, 15 Apr 2010 19:47:33 +0200 Received: by yxe13 with SMTP id 13so1032851yxe.0 for ; Thu, 15 Apr 2010 10:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=8oBco9Fc+/M5GnPTsgjek1RSvdpr5yWQ09oomFVSXdM=; b=u2PTJNlrUqVBNQwMVKwJDFw1gEQOI5OijIxIEm/bX2Q7n6XMt3B6S+1KBHDwHMNJmj hM0+RaeRe2HFT3vM+HhZMZKtFY4FrZV3D/39P7xxF1Y+Ij6zYQ9nR6myYnQO+68VAK+g NYoSBezMzzYbsv4jDNhs06+PyJPeGH1EWFv+w= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=ttj11XkB7PH4NqrocZxjLreb3G6v3521t3QrVnFe2u9RerizV2RhBVy9rO5j9TZ9pz NK20+DlqfpY+zzZCzy1GGFL8yGDMaaRVg5OhH0XgQ/ZEtzqeXAlK0DrTzgstQCisCHkw 65vl6kvOWHQDWj8hpmcy7/jaamA1sbjKq5RvU= Received: by 10.101.136.38 with SMTP id o38mr847413ann.146.1271353645427; Thu, 15 Apr 2010 10:47:25 -0700 (PDT) Received: from [192.168.2.212] ([202.201.14.140]) by mx.google.com with ESMTPS id b10sm3412201ana.16.2010.04.15.10.47.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Apr 2010 10:47:24 -0700 (PDT) Subject: Re: [PATCH 3/3] MIPS: implement hardware perf event support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Deng-Cheng Zhu Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com In-Reply-To: <1271349557.7467.424.camel@fun-lab> References: <1271349557.7467.424.camel@fun-lab> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Fri, 16 Apr 2010 01:47:16 +0800 Message-ID: <1271353636.20625.99.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26418 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, Deng-Cheng Thanks very much for your Perf support of MIPS. On Fri, 2010-04-16 at 00:39 +0800, Deng-Cheng Zhu wrote: > This patch is the HW perf event support. To enable this feature, we can not > choose the SMTC kernel; Oprofile should be disabled; kernel performance > events be selected. Then we can enable it in the Kernel type menu. > > Oprofile for MIPS platforms initializes irq at arch init time. Currently we > do not change this logic to allow PMU reservation. > > If a platform has EIC, we can use the irq base and perf counter irq > offset defines for the interrupt controller in mipspmu_get_irq(). > > Signed-off-by: Deng-Cheng Zhu > --- > arch/mips/Kconfig | 8 + > arch/mips/kernel/Makefile | 2 + > arch/mips/kernel/perf_event.c | 1468 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 1478 insertions(+), 0 deletions(-) > create mode 100644 arch/mips/kernel/perf_event.c [...] > + * Copied from Oprofile -- BEGIN > + */ [...] > +/* Copied from Oprofile -- END */ > + Seems you only copied the contents from arch/mips/oprofile/op_model_mipsxx.c and handle the mipsxx, what about rm9000(arch/mips/oprofile/op_model_rm9000.c) and loongson2(arch/mips/oprofile/op_model_loongson2.c)? I think it will not work on rm9000 and loongson2 for their performance counters are different from mipsxx. so suggest you only enable this for mipsxxx(refer to arch/mips/oprofile/Makefile) via #ifdef and renaming the current perf_event.c to perf_event_mipsxx.c. And to reduce the source code duplication, perhaps we need a solution to share the source code between Oprofile and Perf, and also among mipsxx, rm9000 and loongson2. Thanks & Regards, Wu Zhangjin From aba@not.so.argh.org Thu Apr 15 20:43:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Apr 2010 20:43:33 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:41072 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492138Ab0DOSn1 (ORCPT ); Thu, 15 Apr 2010 20:43:27 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1O2U22-000347-CI; Thu, 15 Apr 2010 18:43:18 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1O2U1w-0008Ae-Ot; Thu, 15 Apr 2010 20:43:12 +0200 Date: Thu, 15 Apr 2010 20:43:12 +0200 From: Andreas Barth To: David Daney , linux-mips@linux-mips.org Subject: irqbalance on movidis crashes the machine (was: movidis x16 hard lockup using 2.6.33) Message-ID: <20100415184312.GK2942@mails.so.argh.org> References: <20100326184132.GU2437@apfelkorn> <4BAD03A5.9070701@caviumnetworks.com> <20100327230744.GG27216@mails.so.argh.org> <4BB0DB2A.9080405@caviumnetworks.com> <20100402133224.GR27216@mails.so.argh.org> <20100403154312.GY2437@apfelkorn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100403154312.GY2437@apfelkorn> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26419 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips * Peter 'p2' De Schrijver (p2@debian.org) [100403 17:43]: > http://zobel.ftbfs.de/.x/lucatelli-nmi-watchdog-output.txt > Dump of one of those hangs. Most cores seem to be stuck in wait > (0xffffffff81100b80), except for core 1 which is in octeon_irq_ciu0_ack > (octeon_irq_ciu0_ack). On further investigation we found out that this happens when irqbalance is started. The version of irqbalance being run is 0.55. We removed this program from the affected machine, but of course this still should be fixed (and we still get a few reboots on another machine without irqbalance). Andi From aba@not.so.argh.org Thu Apr 15 22:35:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Apr 2010 22:36:03 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:41213 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492813Ab0DOUf6 (ORCPT ); Thu, 15 Apr 2010 22:35:58 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1O2Vn2-0005rc-U8; Thu, 15 Apr 2010 20:35:57 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1O2Vmw-0008VQ-SM; Thu, 15 Apr 2010 22:35:50 +0200 Date: Thu, 15 Apr 2010 22:35:50 +0200 From: Andreas Barth To: David Daney , linux-mips@linux-mips.org Subject: Re: irqbalance on movidis crashes the machine (was: movidis x16 hard lockup using 2.6.33) Message-ID: <20100415203550.GA32686@mails.so.argh.org> References: <20100326184132.GU2437@apfelkorn> <4BAD03A5.9070701@caviumnetworks.com> <20100327230744.GG27216@mails.so.argh.org> <4BB0DB2A.9080405@caviumnetworks.com> <20100402133224.GR27216@mails.so.argh.org> <20100403154312.GY2437@apfelkorn> <20100415184312.GK2942@mails.so.argh.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100415184312.GK2942@mails.so.argh.org> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26420 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips * Andreas Barth (aba@not.so.argh.org) [100415 20:43]: > * Peter 'p2' De Schrijver (p2@debian.org) [100403 17:43]: > > http://zobel.ftbfs.de/.x/lucatelli-nmi-watchdog-output.txt > > Dump of one of those hangs. Most cores seem to be stuck in wait > > (0xffffffff81100b80), except for core 1 which is in octeon_irq_ciu0_ack > > (octeon_irq_ciu0_ack). > > On further investigation we found out that this happens when > irqbalance is started. The version of irqbalance being run is 0.55. > > We removed this program from the affected machine, but of course this > still should be fixed (and we still get a few reboots on another > machine without irqbalance). Clarification: Running irqbalance itself doesn't crash the machine, but increases the probability of crashes dramatically. Usually the next few (< 10) commands crash the machine. The crashs however look similar to the ones we have without irqbalance - just way less often then with irqbalance. This seems like irqbalance exposes the crash way better than we do without. Andi From arnaud.patard@mandriva.com Fri Apr 16 11:19:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Apr 2010 11:19:47 +0200 (CEST) Received: from mx1.moondrake.net ([212.85.150.166]:51682 "EHLO mx1.mandriva.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492058Ab0DPJTl (ORCPT ); Fri, 16 Apr 2010 11:19:41 +0200 Received: by mx1.mandriva.com (Postfix, from userid 501) id D54FA274029; Fri, 16 Apr 2010 11:19:37 +0200 (CEST) Received: from office-abk.mandriva.com (unknown [195.7.104.248]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.mandriva.com (Postfix) with ESMTP id 8190C274014; Fri, 16 Apr 2010 11:19:36 +0200 (CEST) Received: from anduin.mandriva.com (fw2.mandriva.com [192.168.2.3]) by office-abk.mandriva.com (Postfix) with ESMTP id 301F884EF4; Fri, 16 Apr 2010 11:36:40 +0200 (CEST) Received: from anduin.mandriva.com (localhost [127.0.0.1]) by anduin.mandriva.com (Postfix) with ESMTP id 54117FF855; Fri, 16 Apr 2010 11:19:52 +0200 (CEST) From: Arnaud Patard To: linux-mips@linux-mips.org, rtc-linux@googlegroups.com Cc: david-b@pacbell.net, a.zummo@towertech.it, ralf@linux-mips.org Subject: [PATCH] rtc-cmos: Fix binary mode support Organization: Mandriva Date: Fri, 16 Apr 2010 11:19:51 +0200 Message-ID: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-=-=" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26421 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: apatard@mandriva.com Precedence: bulk X-list: linux-mips --=-=-= As a follow-up to the thread about rtc support for some loongson 2e/2f boards, this patch tries to address the "REVISIT"/"FIXME" comments about rtc binary mode handling and allow rtc to work with rtc in binary mode. I've also raised the message about 24-h mode not supported to warning otherwise, one may end up with no rtc without any message in the kernel log. Signed-off-by: Arnaud Patard --=-=-= Content-Type: text/x-patch Content-Disposition: inline; filename=rtc_cmos_binary_mode_fix.patch diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index e9aa814..9d99408 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -238,31 +238,32 @@ static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) rtc_control = CMOS_READ(RTC_CONTROL); spin_unlock_irq(&rtc_lock); - /* REVISIT this assumes PC style usage: always BCD */ - - if (((unsigned)t->time.tm_sec) < 0x60) - t->time.tm_sec = bcd2bin(t->time.tm_sec); - else - t->time.tm_sec = -1; - if (((unsigned)t->time.tm_min) < 0x60) - t->time.tm_min = bcd2bin(t->time.tm_min); - else - t->time.tm_min = -1; - if (((unsigned)t->time.tm_hour) < 0x24) - t->time.tm_hour = bcd2bin(t->time.tm_hour); - else - t->time.tm_hour = -1; - - if (cmos->day_alrm) { - if (((unsigned)t->time.tm_mday) <= 0x31) - t->time.tm_mday = bcd2bin(t->time.tm_mday); + if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { + if (((unsigned)t->time.tm_sec) < 0x60) + t->time.tm_sec = bcd2bin(t->time.tm_sec); else - t->time.tm_mday = -1; - if (cmos->mon_alrm) { - if (((unsigned)t->time.tm_mon) <= 0x12) - t->time.tm_mon = bcd2bin(t->time.tm_mon) - 1; + t->time.tm_sec = -1; + if (((unsigned)t->time.tm_min) < 0x60) + t->time.tm_min = bcd2bin(t->time.tm_min); + else + t->time.tm_min = -1; + if (((unsigned)t->time.tm_hour) < 0x24) + t->time.tm_hour = bcd2bin(t->time.tm_hour); + else + t->time.tm_hour = -1; + + if (cmos->day_alrm) { + if (((unsigned)t->time.tm_mday) <= 0x31) + t->time.tm_mday = bcd2bin(t->time.tm_mday); else - t->time.tm_mon = -1; + t->time.tm_mday = -1; + + if (cmos->mon_alrm) { + if (((unsigned)t->time.tm_mon) <= 0x12) + t->time.tm_mon = bcd2bin(t->time.tm_mon)-1; + else + t->time.tm_mon = -1; + } } } t->time.tm_year = -1; @@ -322,29 +323,26 @@ static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) { struct cmos_rtc *cmos = dev_get_drvdata(dev); - unsigned char mon, mday, hrs, min, sec; + unsigned char mon, mday, hrs, min, sec, rtc_control; if (!is_valid_irq(cmos->irq)) return -EIO; - /* REVISIT this assumes PC style usage: always BCD */ - - /* Writing 0xff means "don't care" or "match all". */ - mon = t->time.tm_mon + 1; - mon = (mon <= 12) ? bin2bcd(mon) : 0xff; - mday = t->time.tm_mday; - mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff; - hrs = t->time.tm_hour; - hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff; - min = t->time.tm_min; - min = (min < 60) ? bin2bcd(min) : 0xff; - sec = t->time.tm_sec; - sec = (sec < 60) ? bin2bcd(sec) : 0xff; + + rtc_control = CMOS_READ(RTC_CONTROL); + if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { + /* Writing 0xff means "don't care" or "match all". */ + mon = (mon <= 12) ? bin2bcd(mon) : 0xff; + mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff; + hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff; + min = (min < 60) ? bin2bcd(min) : 0xff; + sec = (sec < 60) ? bin2bcd(sec) : 0xff; + } spin_lock_irq(&rtc_lock); @@ -478,7 +476,7 @@ static int cmos_procfs(struct device *dev, struct seq_file *seq) "update_IRQ\t: %s\n" "HPET_emulated\t: %s\n" // "square_wave\t: %s\n" - // "BCD\t\t: %s\n" + "BCD\t\t: %s\n" "DST_enable\t: %s\n" "periodic_freq\t: %d\n" "batt_status\t: %s\n", @@ -486,7 +484,7 @@ static int cmos_procfs(struct device *dev, struct seq_file *seq) (rtc_control & RTC_UIE) ? "yes" : "no", is_hpet_enabled() ? "yes" : "no", // (rtc_control & RTC_SQWE) ? "yes" : "no", - // (rtc_control & RTC_DM_BINARY) ? "no" : "yes", + (rtc_control & RTC_DM_BINARY) ? "no" : "yes", (rtc_control & RTC_DST_EN) ? "yes" : "no", cmos->rtc->irq_freq, (valid & RTC_VRT) ? "okay" : "dead"); @@ -749,12 +747,11 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) spin_unlock_irq(&rtc_lock); - /* FIXME teach the alarm code how to handle binary mode; + /* FIXME: * doesn't know 12-hour mode either. */ - if (is_valid_irq(rtc_irq) && - (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY)))) { - dev_dbg(dev, "only 24-hr BCD mode supported\n"); + if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { + dev_warn(dev, "only 24-hr supported\n") retval = -ENXIO; goto cleanup1; } --=-=-=-- From manuel.lauss@googlemail.com Fri Apr 16 19:04:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Apr 2010 19:04:31 +0200 (CEST) Received: from mail-bw0-f226.google.com ([209.85.218.226]:36136 "EHLO mail-bw0-f226.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492183Ab0DPRE2 (ORCPT ); Fri, 16 Apr 2010 19:04:28 +0200 Received: by bwz26 with SMTP id 26so2890980bwz.27 for ; Fri, 16 Apr 2010 10:04:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=dr8TB6u6fIdLe3vQLBuuDw2g6rpcOfXRlc7Qta4vdlw=; b=Ytfx09RDlkY+/Jsg8+WopJJ39rT7S6/Dv1ctuZ6uykdi6R6fykWKDTp8mUD02rzhzW qNd3EipziTTcewR26FmkW2ChA1Cn/9/KcdZiXgVlxpiOmS0TOdhzrsbX7UyeN2gp+RGA 4YEEg+xKc7G4PDjSj5Q+744wzQtEcgbQR34PU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=wFoOoQyzPXrs9JZE3VTLp4UtKrUw3iEzfo5oNpTosmVFfYH/p0REJbXW73jyD5egMh x80V2PKnC0y1YvTFYwxX5bxii595nqloJq7Jltxbnm0HvuMpALqq7pnpDYtXEr6ZhIQc +O8JOU2rOopebdmVvV7hcqsvpM7SRV+0u/Qk8= Received: by 10.204.146.148 with SMTP id h20mr1899972bkv.185.1271437462665; Fri, 16 Apr 2010 10:04:22 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id 15sm1955345bwz.0.2010.04.16.10.04.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 16 Apr 2010 10:04:21 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: db1200: PCMCIA carddetects must not be auto-enabled. Date: Fri, 16 Apr 2010 19:04:17 +0200 Message-Id: <1271437457-26716-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26422 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Same issues as SD carddetects: One of both is always screaming, and the handlers take care to shut one up and enable the other. To avoid messages about "unbalanced interrupt enable/disable" they must not be automatically enabled when initally requested. Signed-off-by: Manuel Lauss --- The error it fixes doesn't show with the defconfig but I believe this is just because of fortunate timings. Please apply to 2.6.34-rc if still possible! arch/mips/alchemy/devboards/db1200/setup.c | 10 +++++++--- 1 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index be7e92e..8876195 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -66,12 +66,16 @@ static int __init db1200_arch_init(void) set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); - /* do not autoenable these: CPLD has broken edge int handling, - * and the CD handler setup requires manual enabling to work - * around that. + /* insert/eject pairs: one of both is always screaming. To avoid + * issues they must not be automatically enabled when initially + * requested. */ irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN; return 0; } -- 1.7.0.4 From dengcheng.zhu@gmail.com Sat Apr 17 03:49:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Apr 2010 03:49:51 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:60665 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492503Ab0DQBts (ORCPT ); Sat, 17 Apr 2010 03:49:48 +0200 Received: by gwaa12 with SMTP id a12so57334gwa.36 for ; Fri, 16 Apr 2010 18:49:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:cc:content-type; bh=CejXxCE5xrL4YK178BOov5KeV0oJeNG9GFF14a810hI=; b=no3n3WfAqD3wTxY3+Jjvpi6zHTFIiavyNPY6hkAbLR6i0J+m8oAFvgSpTlG2HpKrxk VIcqUZS1FuHT0tpsMmgpKKFHCyztbmzK28OqKcDqSYe0hOphlTQANbCHv37ksfzV2FUf i1NvbS5lOdTnsHcOJ0BE/QXAnOdVp+lt+QtJ0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=DYRs/B+3eRnF6nJoEdsTuHV6E2zUsHYpkCLQk9gFn0BRAWufGhYGuxCI1Ab7YSzr0h ZMpEa9GZyJajBuFunTdFrx10f48K4x/fHYMTjAv08sD0DuWf01rVuI3afiBjWCC92hZ1 qTd+VhM8Q7cG/uGUlArOzsorouFF11YVBSHSM= MIME-Version: 1.0 Received: by 10.151.42.5 with HTTP; Fri, 16 Apr 2010 18:49:40 -0700 (PDT) In-Reply-To: <1271353636.20625.99.camel@falcon> References: <1271349557.7467.424.camel@fun-lab> <1271353636.20625.99.camel@falcon> Date: Sat, 17 Apr 2010 09:49:40 +0800 Received: by 10.150.117.17 with SMTP id p17mr2354882ybc.305.1271468980290; Fri, 16 Apr 2010 18:49:40 -0700 (PDT) Message-ID: Subject: Re: [PATCH 3/3] MIPS: implement hardware perf event support From: "dengcheng.zhu" To: wuzhangjin@gmail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26423 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Hi, Zhangjin Thanks for your feedback! 2010/4/16 Wu Zhangjin : > Seems you only copied the contents from > arch/mips/oprofile/op_model_mipsxx.c and handle the mipsxx, what about > rm9000(arch/mips/oprofile/op_model_rm9000.c) and > loongson2(arch/mips/oprofile/op_model_loongson2.c)? > > I think it will not work on rm9000 and loongson2 for their performance > counters are different from mipsxx. so suggest you only enable this for > mipsxxx(refer to arch/mips/oprofile/Makefile) via #ifdef and renaming > the current perf_event.c to perf_event_mipsxx.c. OK, I'll try to move the control/count help functions/defines and the specific mips_pmu stuff into a file called perf_event_mipsxx.c, and leave the common things in perf_event.c, so that when we implement Perf for loongson2 or rm9000, we can simply add new files like perf_event_loongson2.c. > And to reduce the source code duplication, perhaps we need a solution to > share the source code between Oprofile and Perf, and also among mipsxx, > rm9000 and loongson2. I think there is almost nothing for the count/control things which can be shared among mipsxx/rm9000/loongson2. As for sharing between Oprofile and Perf, how about moving mipsxx/rm9000/loongson2 count/control things into a new file asm/pmu.h, where we use #ifdef's. Deng-Cheng From wuzhangjin@gmail.com Sat Apr 17 07:04:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Apr 2010 07:04:38 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:56067 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490977Ab0DQFEf (ORCPT ); Sat, 17 Apr 2010 07:04:35 +0200 Received: by pvc30 with SMTP id 30so2241701pvc.36 for ; Fri, 16 Apr 2010 22:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=6E/y1khOdL382TV8UDb67NDew8WYJGgp2hHBeZak2rQ=; b=QAIEgqaFacMkr6l98WkN3OJluAweBx+pNz1KIVLvmjXnE5G9AoZ7KbrKsyNkpuKw08 4YPK6jpFATsYiF0FOo627EE8r4loMdMvqddbFpcYhyt0nZxGNORTHZ4m5O9tMm20/65c dUNBRnljmNv9ulaXObmbqW9yY6H33Nfm5LPY4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=DoVkXSXXJ61KEq/KHfoDtNESxj0ShptoEdHs48wHwAbxBB5uMcc7F/cEu6mhcQaSJi YGerOPpHjXox70/1+47DvcgYgi56asVNRkUdZnHnnTh4ZZo1mT1fQhw3yFk9BviSYQVN za3lGYXkQSmQlxK51lkJ2YTYUPMYw08Pj5iOg= Received: by 10.114.188.4 with SMTP id l4mr2510638waf.19.1271480667723; Fri, 16 Apr 2010 22:04:27 -0700 (PDT) Received: from [192.168.2.243] ([202.201.14.140]) by mx.google.com with ESMTPS id 23sm2877812pzk.10.2010.04.16.22.04.24 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 16 Apr 2010 22:04:26 -0700 (PDT) Subject: Re: [PATCH 3/3] MIPS: implement hardware perf event support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: "dengcheng.zhu" Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com In-Reply-To: References: <1271349557.7467.424.camel@fun-lab> <1271353636.20625.99.camel@falcon> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 17 Apr 2010 13:04:21 +0800 Message-ID: <1271480661.1860.36.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26424 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Sat, 2010-04-17 at 09:49 +0800, dengcheng.zhu wrote: [...] > > > > I think it will not work on rm9000 and loongson2 for their performance > > counters are different from mipsxx. so suggest you only enable this for > > mipsxxx(refer to arch/mips/oprofile/Makefile) via #ifdef and renaming > > the current perf_event.c to perf_event_mipsxx.c. > OK, I'll try to move the control/count help functions/defines and the > specific mips_pmu stuff into a file called perf_event_mipsxx.c, and leave > the common things in perf_event.c, so that when we implement Perf for > loongson2 or rm9000, we can simply add new files like > perf_event_loongson2.c. > > > And to reduce the source code duplication, perhaps we need a solution to > > share the source code between Oprofile and Perf, and also among mipsxx, > > rm9000 and loongson2. > I think there is almost nothing for the count/control things which can be > shared among mipsxx/rm9000/loongson2. As for sharing between Oprofile and > Perf, how about moving mipsxx/rm9000/loongson2 count/control things into a > new file asm/pmu.h, where we use #ifdef's. > It looks good, based on your work, I will try to add the loongson2 specific perf support, then we can get more details about the common parts. Regards, Wu Zhangjin From manuel.lauss@googlemail.com Sat Apr 17 20:17:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Apr 2010 20:17:48 +0200 (CEST) Received: from fg-out-1718.google.com ([72.14.220.152]:48911 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491984Ab0DQSRo (ORCPT ); Sat, 17 Apr 2010 20:17:44 +0200 Received: by fg-out-1718.google.com with SMTP id 19so1670103fgg.6 for ; Sat, 17 Apr 2010 11:17:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=N+vfASzRkSWbdsQ/HN/1Fa6EgsWc2Jz5ZD+EmHq+5wI=; b=OKU6P7WyFPS4B9oJWvZM+ojDi+kCI/w2OlcVoaJO5bwxfKU6/2UpiA2bHrLXkzeVdN gh56kJlNf7SBtAxaZtmlmaJudSal26hXB9JcKNMHWHImLpge9iZuK2vvbXwh1XLh1oaq Ws0Mx0rnJqUBIRXuwHNBO0cwY4zhE06C83uLk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=dAAFwI+czV0jW5vNEO/0qxYU5E2Tq8thNcA9o0VLOsH7F+vuxz/EL5UMloat3kRwBL gunqFbcbLoflNREOjWTA2XCHdcQsGHDPqff4F5Dn+SL5v3NUPnPQRlEFrUwM1WxSrUVP gt5N9HAeDqoxDNrKMt679Bms2/S7litzBCceo= Received: by 10.223.60.206 with SMTP id q14mr1499670fah.93.1271528264317; Sat, 17 Apr 2010 11:17:44 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id 21sm6694202fks.23.2010.04.17.11.17.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 17 Apr 2010 11:17:43 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH v2] MIPS: Alchemy: db1200: PCMCIA carddetects must not be auto-enabled. Date: Sat, 17 Apr 2010 20:17:40 +0200 Message-Id: <1271528260-13749-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26425 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Same issues as SD carddetects: One of both is always screaming, and the handlers take care to shut one up and enable the other. To avoid messages about "unbalanced interrupt enable/disable" they must not be automatically enabled when initally requested. Signed-off-by: Manuel Lauss --- v2: remove the now unnecessary locks in the socket driver irq setup code. The error it fixes doesn't show with the defconfig but I believe this is just because of fortunate timings: build without networking chip support and its there. Please apply to 2.6.34-rc if still possible! arch/mips/alchemy/devboards/db1200/setup.c | 10 +++++++--- drivers/pcmcia/db1xxx_ss.c | 12 +++--------- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index be7e92e..8876195 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -66,12 +66,16 @@ static int __init db1200_arch_init(void) set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); - /* do not autoenable these: CPLD has broken edge int handling, - * and the CD handler setup requires manual enabling to work - * around that. + /* insert/eject pairs: one of both is always screaming. To avoid + * issues they must not be automatically enabled when initially + * requested. */ irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN; return 0; } diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c index 6206408..0f4cc3f 100644 --- a/drivers/pcmcia/db1xxx_ss.c +++ b/drivers/pcmcia/db1xxx_ss.c @@ -146,7 +146,6 @@ static irqreturn_t db1200_pcmcia_cdirq(int irq, void *data) static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) { int ret; - unsigned long flags; if (sock->stschg_irq != -1) { ret = request_irq(sock->stschg_irq, db1000_pcmcia_stschgirq, @@ -162,8 +161,6 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) * active one disabled. */ if (sock->board_type == BOARD_TYPE_DB1200) { - local_irq_save(flags); - ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq, IRQF_DISABLED, "pcmcia_insert", sock); if (ret) @@ -173,17 +170,14 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) IRQF_DISABLED, "pcmcia_eject", sock); if (ret) { free_irq(sock->insert_irq, sock); - local_irq_restore(flags); goto out1; } - /* disable the currently active one */ + /* enable the currently silent one */ if (db1200_card_inserted(sock)) - disable_irq_nosync(sock->insert_irq); + enable_irq(sock->eject_irq); else - disable_irq_nosync(sock->eject_irq); - - local_irq_restore(flags); + enable_irq(sock->insert_irq); } else { /* all other (older) Db1x00 boards use a GPIO to show * card detection status: use both-edge triggers. -- 1.7.0.4 From wuzhangjin@gmail.com Sat Apr 17 22:52:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Apr 2010 22:52:23 +0200 (CEST) Received: from mail-pz0-f194.google.com ([209.85.222.194]:55905 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492686Ab0DQUwO (ORCPT ); Sat, 17 Apr 2010 22:52:14 +0200 Received: by pzk32 with SMTP id 32so2030157pzk.21 for ; Sat, 17 Apr 2010 13:52:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=aCCUHjVnW9P6d2tw6jDLzN6nZawLJ7K1wMKWntuSjrM=; b=HCHK0gmPsU2/qXFzx9vBWorAZ+7QL12ibVfiNL0QnU+DIu2xNpGbszsarl6cOI5AsO IVrNwJ2jph0+35EtyRZaLqHuFeDpjfJ0qDWflA1kH7vrdfWQqZ/8qQN1YOqUOz+m8ERS Xhf8icifKs2Tv78Ku3zDz77fakHTCAahtkqHQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=UYsouBzR2VjZefYcIIb7Qtl5za3ofKrSZ2Y6eAvahjNrYpbElFkhUWLdkXvG8+584Z fMoEPctwzD2qQdGxiCb1yG+rSaAq17zxb9iPhpWlCrpfW+zlEGiNHKtKgOIOvJCIqvDD c69zhrBNTCVGkogJdDAKYqvmsB6+YZ8Ivofmk= Received: by 10.141.100.15 with SMTP id c15mr2986287rvm.221.1271537526607; Sat, 17 Apr 2010 13:52:06 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm3632343pzk.3.2010.04.17.13.52.02 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 17 Apr 2010 13:52:05 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Steven Rostedt , Wu Zhangjin Subject: [PATCH -v5] MIPS: tracing: Optimize the implementation Date: Sun, 18 Apr 2010 04:51:54 +0800 Message-Id: <1271537514-19584-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26426 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Hi, Ralf This patch not only fixes the function graph tracing support of 32bit kernel and module compiled with/without mmcount-ra-address, but also speeds up the dynamic function tracer and function graph tracer. Just tested it with the latest gcc 4.5 and added necessary changes to make the kernel and module support work well with mmcount-ra-address. I think it is applicable now. Regards, Wu Zhangjin -------------- Changes: v4 -> v5: * All of the these changes have been tested in 32bit & 64bit kernel compiled with gcc 4.4 & 4.5, including kernel & module Ftrace support. + Fixup of the module support broken by the change of v1->v2. As the source code(and also the objdump result of the kernel image) of -mmcount-ra-address shows, the change of v1->v2 is wrong and has broken the module support: For 64bit kernel with -mmcount-ra-address, the return address saving operation is put in the delay slot of the jump instruction(calling site of _mcount), so, the offset of "b 1f" is the same to the -mno-mcount-ra-address: 16. but for 32bit kernel, since there is already an instruction put in the delay slot, the return address operation must be put before the jump instruciton, so, the offset is bigger than the one with -mno-mcount-ra-address: 16+4=20. + Fixup of the 32bit support with gcc 4.5 As the doc[1] of gcc-4.5 shows, the -mmcount-ra-address uses the $12 to transfer the stack offset of the return address to the _mcount function. in 64bit kernel, $12 is t0, but in 32bit kernel, it is t4, so, we need to use $12 instead of t0 here to cover the 64bit and 32bit support. [1] Gcc doc: MIPS Options http://gcc.gnu.org/onlinedocs/gcc/MIPS-Options.html + Cleanup of mcount.S o merges two continuous "#ifdef CONFIG_64BIT". o removes the instruction "move a0, t0" via using a0 directly. o share the common "PTR_LA a0, PT_R1(sp)" v3 -> v4: + Fixup of 'undefined ftrace_graph_caller' ftrace_graph_caller variable is only needed by CONFIG_FUNCTION_GRAPH_TRACER, so, wrap it with #ifdef. v2 -> v3: + Fixes the buidling error of the changes from v2. v1 -> v2: + Fixes the support of -mmcount-ra-address The offset of "b 1f" instruction should be 20 for leaf-function and 24 for non-leaf function when -mmcount-ra-address is enabled. This patch adds a new get_insn_b_1f() function to get the different "b 1f" instruction. (only test without -mmcount-ra-address.) v1: + Reduce the runtime overhead o Uses macros instead of variables for the fixed instructions to reduce memory access o Moves the Initilization of the instructions which will be fixed after linking from ftrace_make_nop/ftrace_make_call to ftrace_dyn_arch_init() and encodes the instructions through uasm(arch/mips/include/asm/uasm.h). o A common macro in_module() is defined to determine which space the instruction pointer stays in and several related conditional statements are converted to conditional operator(? :) statement. + Cleanup the whole stuff Lots of comments/macros have been cleaned up to let it look better. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/ftrace.h | 12 ++- arch/mips/kernel/ftrace.c | 217 +++++++++++++++++++++++----------------- arch/mips/kernel/mcount.S | 20 ++-- 3 files changed, 141 insertions(+), 108 deletions(-) diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h index ce35c9a..29d71c0 100644 --- a/arch/mips/include/asm/ftrace.h +++ b/arch/mips/include/asm/ftrace.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive for * more details. * - * Copyright (C) 2009 DSLab, Lanzhou University, China + * Copyright (C) 2009, 2010 DSLab, Lanzhou University, China * Author: Wu Zhangjin */ @@ -19,6 +19,14 @@ extern void _mcount(void); #define mcount _mcount +/* + * If the Instruction Pointer is in module space (0xc0000000), return true; + * otherwise, it is in kernel space (0x80000000), return false. + * + * FIXME: This may not work in some cases. + */ +#define in_module(ip) (unlikely((ip) & 0x40000000)) + #define safe_load(load, src, dst, error) \ do { \ asm volatile ( \ @@ -83,8 +91,8 @@ static inline unsigned long ftrace_call_adjust(unsigned long addr) struct dyn_arch_ftrace { }; - #endif /* CONFIG_DYNAMIC_FTRACE */ + #endif /* __ASSEMBLY__ */ #endif /* CONFIG_FUNCTION_TRACER */ #endif /* _ASM_MIPS_FTRACE_H */ diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index e9e64e0..d01ab52 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -2,7 +2,7 @@ * Code for replacing ftrace calls with jumps. * * Copyright (C) 2007-2008 Steven Rostedt - * Copyright (C) 2009 DSLab, Lanzhou University, China + * Copyright (C) 2009, 2010 DSLab, Lanzhou University, China * Author: Wu Zhangjin * * Thanks goes to Steven Rostedt for writing the original x86 version. @@ -15,15 +15,51 @@ #include #include #include +#include + +#define INSN_S_R_SP 0xafb00000 /* s{d,w} R, offset(sp) */ #ifdef CONFIG_DYNAMIC_FTRACE -#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */ -#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ -#define jump_insn_encode(op_code, addr) \ - ((unsigned int)((op_code) | (((addr) >> 2) & ADDR_MASK))) +/* Before linking, the following instructions are fixed. */ +#ifdef CONFIG_CPU_LOONGSON2F +#define INSN_NOP 0x00200825 /* or at, at, zero */ +#else +#define INSN_NOP 0x00000000 /* nop */ +#endif +#define INSN_B_1F_16 0x10000004 /* b 1f; offset = (16 >> 2) */ +#define INSN_B_1F_20 0x10000005 /* b 1f; offset = (20 >> 2) */ + +/* After linking, the following instructions are fixed. */ +static unsigned int insn_jal_ftrace_caller __read_mostly; +static unsigned int insn_lui_v1_hi16_mcount __read_mostly; +static unsigned int insn_j_ftrace_graph_caller __maybe_unused __read_mostly; + +/* The following instructions are encoded in the run-time */ +/* insn: jal func; op_code|addr : 31...26|25 ....0 */ +#define INSN_JAL(addr) \ + ((unsigned int)(0x0c000000 | (((addr) >> 2) & 0x03ffffff))) + +static inline void ftrace_dyn_arch_init_insns(void) +{ + u32 *buf; + unsigned int v1; -static unsigned int ftrace_nop = 0x00000000; + /* lui v1, hi16_mcount */ + v1 = 3; + buf = (u32 *)&insn_lui_v1_hi16_mcount; + UASM_i_LA_mostly(&buf, v1, MCOUNT_ADDR); + + /* jal (ftrace_caller + 8), jump over the first two instruction */ + buf = (u32 *)&insn_jal_ftrace_caller; + uasm_i_jal(&buf, (FTRACE_ADDR + 8)); + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + /* j ftrace_graph_caller */ + buf = (u32 *)&insn_j_ftrace_graph_caller; + uasm_i_j(&buf, (unsigned long)ftrace_graph_caller); +#endif +} static int ftrace_modify_code(unsigned long ip, unsigned int new_code) { @@ -31,7 +67,6 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) /* *(unsigned int *)ip = new_code; */ safe_store_code(new_code, ip, faulted); - if (unlikely(faulted)) return -EFAULT; @@ -40,84 +75,82 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) return 0; } -static int lui_v1; -static int jal_mcount; - int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, unsigned long addr) { unsigned int new; - int faulted; unsigned long ip = rec->ip; - /* We have compiled module with -mlong-calls, but compiled the kernel - * without it, we need to cope with them respectively. */ - if (ip & 0x40000000) { - /* record it for ftrace_make_call */ - if (lui_v1 == 0) { - /* lui_v1 = *(unsigned int *)ip; */ - safe_load_code(lui_v1, ip, faulted); - - if (unlikely(faulted)) - return -EFAULT; - } - - /* lui v1, hi_16bit_of_mcount --> b 1f (0x10000004) - * addiu v1, v1, low_16bit_of_mcount - * move at, ra - * jalr v1 - * nop - * 1f: (ip + 12) - */ - new = 0x10000004; - } else { - /* record/calculate it for ftrace_make_call */ - if (jal_mcount == 0) { - /* We can record it directly like this: - * jal_mcount = *(unsigned int *)ip; - * Herein, jump over the first two nop instructions */ - jal_mcount = jump_insn_encode(JAL, (MCOUNT_ADDR + 8)); - } - - /* move at, ra - * jalr v1 --> nop - */ - new = ftrace_nop; + /* + * We have compiled modules with -mlong-calls, but compiled kernel + * without it, therefore, need to cope with them respectively. + * + * For module: + * + * lui v1, hi16_mcount --> b 1f + * addiu v1, v1, lo16_mcount + * move at, ra + * jalr v1 + * nop + * 1f: (ip + 16) + * For kernel: + * + * move at, ra + * jal _mcount --> nop + * + * And with the -mmcount-ra-address option, the offset may be 20 for + * leaf fuction and 24 for non-leaf function. + */ + + if (!in_module(ip)) + new = INSN_NOP; + else { +#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT) + new = INSN_B_1F_20; +#else + new = INSN_B_1F_16; +#endif } + return ftrace_modify_code(ip, new); } -static int modified; /* initialized as 0 by default */ - int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) { unsigned int new; unsigned long ip = rec->ip; - /* We just need to remove the "b ftrace_stub" at the fist time! */ - if (modified == 0) { - modified = 1; - ftrace_modify_code(addr, ftrace_nop); - } - /* ip, module: 0xc0000000, kernel: 0x80000000 */ - new = (ip & 0x40000000) ? lui_v1 : jal_mcount; + new = in_module(ip) ? insn_lui_v1_hi16_mcount : insn_jal_ftrace_caller; return ftrace_modify_code(ip, new); } -#define FTRACE_CALL_IP ((unsigned long)(&ftrace_call)) - int ftrace_update_ftrace_func(ftrace_func_t func) { unsigned int new; - new = jump_insn_encode(JAL, (unsigned long)func); + new = INSN_JAL((unsigned long)func); - return ftrace_modify_code(FTRACE_CALL_IP, new); + return ftrace_modify_code((unsigned long)(&ftrace_call), new); } int __init ftrace_dyn_arch_init(void *data) { + ftrace_dyn_arch_init_insns(); + + /* + * We are safe to remove the "b ftrace_stub" for the current + * ftrace_caller() is almost empty (only the stack operations), and + * most importantly, the calling to mcount will be disabled later in + * ftrace_init(), then there is no 'big' overhead. And in the future, + * we are hoping the function_trace_stop is initialized as 1 then we + * can eventually remove that 'useless' "b ftrace_stub" and the + * following nop. Currently, although we can call ftrace_stop() to set + * function_trace_stop as 1, but it will change the behavior of the + * Function Tracer. + */ + ftrace_modify_code(MCOUNT_ADDR, INSN_NOP); + /* The return code is retured via data */ *(unsigned long *)data = 0; @@ -128,30 +161,24 @@ int __init ftrace_dyn_arch_init(void *data) #ifdef CONFIG_FUNCTION_GRAPH_TRACER #ifdef CONFIG_DYNAMIC_FTRACE - extern void ftrace_graph_call(void); -#define JMP 0x08000000 /* jump to target directly */ -#define CALL_FTRACE_GRAPH_CALLER \ - jump_insn_encode(JMP, (unsigned long)(&ftrace_graph_caller)) #define FTRACE_GRAPH_CALL_IP ((unsigned long)(&ftrace_graph_call)) int ftrace_enable_ftrace_graph_caller(void) { return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, - CALL_FTRACE_GRAPH_CALLER); + insn_j_ftrace_graph_caller); } int ftrace_disable_ftrace_graph_caller(void) { - return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, ftrace_nop); + return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, INSN_NOP); } - #endif /* !CONFIG_DYNAMIC_FTRACE */ #ifndef KBUILD_MCOUNT_RA_ADDRESS -#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */ -#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */ -#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ +#define INSN_S_RA_SP 0xafbf0000 /* s{d,w} ra, offset(sp) */ +#define STACK_OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ unsigned long ftrace_get_parent_addr(unsigned long self_addr, unsigned long parent, @@ -162,35 +189,35 @@ unsigned long ftrace_get_parent_addr(unsigned long self_addr, unsigned int code; int faulted; - /* in module or kernel? */ - if (self_addr & 0x40000000) { - /* module: move to the instruction "lui v1, HI_16BIT_OF_MCOUNT" */ - ip = self_addr - 20; - } else { - /* kernel: move to the instruction "move ra, at" */ - ip = self_addr - 12; - } + /* + * For module, move the ip from calling site of mcount to the + * instruction "lui v1, hi_16bit_of_mcount"(offset is 20), but for + * kernel, move to the instruction "move ra, at"(offset is 12) + */ + ip = self_addr - (in_module(self_addr) ? 20 : 12); - /* search the text until finding the non-store instruction or "s{d,w} - * ra, offset(sp)" instruction */ + /* + * search the text until finding the non-store instruction or "s{d,w} + * ra, offset(sp)" instruction + */ do { ip -= 4; /* get the code at "ip": code = *(unsigned int *)ip; */ safe_load_code(code, ip, faulted); - if (unlikely(faulted)) return 0; - /* If we hit the non-store instruction before finding where the + /* + * If we hit the non-store instruction before finding where the * ra is stored, then this is a leaf function and it does not - * store the ra on the stack. */ - if ((code & S_R_SP) != S_R_SP) + * store the ra on the stack. + */ + if ((code & INSN_S_R_SP) != INSN_S_R_SP) return parent_addr; + } while (((code & INSN_S_RA_SP) != INSN_S_RA_SP)); - } while (((code & S_RA_SP) != S_RA_SP)); - - sp = fp + (code & OFFSET_MASK); + sp = fp + (code & STACK_OFFSET_MASK); /* ra = *(unsigned long *)sp; */ safe_load_stack(ra, sp, faulted); @@ -201,8 +228,7 @@ unsigned long ftrace_get_parent_addr(unsigned long self_addr, return sp; return 0; } - -#endif +#endif /* !KBUILD_MCOUNT_RA_ADDRESS */ /* * Hook the return address and push it in the stack of return addrs @@ -211,16 +237,17 @@ unsigned long ftrace_get_parent_addr(unsigned long self_addr, void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, unsigned long fp) { + int faulted; unsigned long old; struct ftrace_graph_ent trace; unsigned long return_hooker = (unsigned long) &return_to_handler; - int faulted; if (unlikely(atomic_read(¤t->tracing_graph_pause))) return; - /* "parent" is the stack address saved the return address of the caller + /* + * "parent" is the stack address saved the return address of the caller * of _mcount. * * if the gcc < 4.5, a leaf function does not save the return address @@ -241,12 +268,14 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, if (unlikely(faulted)) goto out; #ifndef KBUILD_MCOUNT_RA_ADDRESS - parent = (unsigned long *)ftrace_get_parent_addr(self_addr, old, - (unsigned long)parent, - fp); - /* If fails when getting the stack address of the non-leaf function's - * ra, stop function graph tracer and return */ - if (parent == 0) + parent = (unsigned long *)ftrace_get_parent_addr( + self_addr, old, (unsigned long)parent, fp); + + /* + * If fails on getting the stack address of the non-leaf function's ra, + * stop function graph tracer and return + */ + if (unlikely(parent == 0)) goto out; #endif /* *parent = return_hooker; */ diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S index 6851fc9..f95714c 100644 --- a/arch/mips/kernel/mcount.S +++ b/arch/mips/kernel/mcount.S @@ -6,6 +6,7 @@ * more details. * * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China + * Copyright (C) 2010 DSLab, Lanzhou University, China * Author: Wu Zhangjin */ @@ -45,8 +46,6 @@ PTR_L a5, PT_R9(sp) PTR_L a6, PT_R10(sp) PTR_L a7, PT_R11(sp) -#endif -#ifdef CONFIG_64BIT PTR_ADDIU sp, PT_SIZE #else PTR_ADDIU sp, (PT_SIZE + 8) @@ -71,7 +70,7 @@ _mcount: MCOUNT_SAVE_REGS #ifdef KBUILD_MCOUNT_RA_ADDRESS - PTR_S t0, PT_R12(sp) /* t0 saved the location of the return address(at) by -mmcount-ra-address */ + PTR_S $12, PT_R12(sp) /* $12 saved the location of the return address(at) */ #endif move a0, ra /* arg1: next ip, selfaddr */ @@ -137,25 +136,22 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra) #ifdef CONFIG_DYNAMIC_FTRACE PTR_L a1, PT_R31(sp) /* load the original ra from the stack */ #ifdef KBUILD_MCOUNT_RA_ADDRESS - PTR_L t0, PT_R12(sp) /* load the original t0 from the stack */ + PTR_L a0, PT_R12(sp) /* arg1: the location of the return address */ #endif -#else +#else /* ! CONFIG_DYNAMIC_FTRACE */ MCOUNT_SAVE_REGS move a1, ra /* arg2: next ip, selfaddr */ #endif #ifdef KBUILD_MCOUNT_RA_ADDRESS - bnez t0, 1f /* non-leaf func: t0 saved the location of the return address */ + bnez a0, 1f /* non-leaf func: get the location of the return address from saved $12 */ nop - PTR_LA t0, PT_R1(sp) /* leaf func: get the location of at(old ra) from our own stack */ -1: move a0, t0 /* arg1: the location of the return address */ -#else - PTR_LA a0, PT_R1(sp) /* arg1: &AT -> a0 */ #endif - jal prepare_ftrace_return + PTR_LA a0, PT_R1(sp) /* leaf func: get the location of at(old ra) from our own stack */ +1: jal prepare_ftrace_return #ifdef CONFIG_FRAME_POINTER move a2, fp /* arg3: frame pointer */ -#else +#else /* ! CONFIG_FRAME_POINTER */ #ifdef CONFIG_64BIT PTR_LA a2, PT_SIZE(sp) #else -- 1.7.0 From sebastian@breakpoint.cc Sun Apr 18 15:26:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 18 Apr 2010 15:26:44 +0200 (CEST) Received: from Chamillionaire.breakpoint.cc ([85.10.199.196]:55453 "EHLO Chamillionaire.breakpoint.cc" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491923Ab0DRN0k (ORCPT ); Sun, 18 Apr 2010 15:26:40 +0200 Received: id: bigeasy by Chamillionaire.breakpoint.cc with local (easymta 1.00 BETA 1) id 1O3UWC-0008Q1-LX; Sun, 18 Apr 2010 15:26:36 +0200 Date: Sun, 18 Apr 2010 15:26:36 +0200 From: Sebastian Andrzej Siewior To: Ralf Baechle Cc: tbm@cyrius.com, linux-mips@linux-mips.org Subject: mips: enable PATA platform on SWARM and LITTLESUR Message-ID: <20100418132636.GA32350@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline X-Key-Id: FE3F4706 X-Key-Fingerprint: FFDA BBBB 3563 1B27 75C9 925B 98D5 5C1C FE3F 4706 User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26427 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sebastian@breakpoint.cc Precedence: bulk X-list: linux-mips according to include/asm/sibyte/swarm.h both systems provide a platform device for the ide controler. Until now the IDE subsystem was used which is deprecated by now. The same structure can be used with the PATA driver. This was tested on SWARM. Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/Kconfig | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 29e8692..98628ec 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -509,6 +509,7 @@ config SIBYTE_SWARM bool "Sibyte BCM91250A-SWARM" select BOOT_ELF32 select DMA_COHERENT + select HAVE_PATA_PLATFORM select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE @@ -523,6 +524,7 @@ config SIBYTE_LITTLESUR depends on EXPERIMENTAL select BOOT_ELF32 select DMA_COHERENT + select HAVE_PATA_PLATFORM select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE -- 1.6.6.1 From wuzhangjin@gmail.com Mon Apr 19 11:36:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Apr 2010 11:37:04 +0200 (CEST) Received: from [74.125.83.177] ([74.125.83.177]:61895 "EHLO mail-pv0-f177.google.com" rhost-flags-FAIL-FAIL-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491152Ab0DSJg5 (ORCPT ); Mon, 19 Apr 2010 11:36:57 +0200 Received: by pvc30 with SMTP id 30so2933971pvc.36 for ; Mon, 19 Apr 2010 02:36:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=1EsG24hSXypweamtSNrpI8xu8WF8EFzuzl9yZiN1B+w=; b=Nwi+qgSEYEXJX67Yp7qbY+nb6lDNh9zDebl5ycCQYUPLk4fOSkFBiimg1Kh2vyg4zu SttefsANpf9klP0CKUZFD6KZu3xFVS3LNWUlHXo8MsIoVyHIbUHEyguVZNkahP3URkm3 2XfLFiU5tD6bqm9YFzgNU2ezK1Devbd2C8TrM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=tJ05P+aIRE/mFJ+XQBCVsnv2b1N7UHQxMxlVVT1jrvVq4FwbyT1RvEoLLPY2pNdlKm mWnayPXFgr5cZqDP5r8WJTWfvLDSi3Q7RfI/mdbzNHv6hNCc0dlNSBPYw3ycObWdQ3VS yQP1BK+ky9bXUs480x51FEl7oEXLKzo24/bW4= Received: by 10.141.107.19 with SMTP id j19mr3776218rvm.90.1271669775037; Mon, 19 Apr 2010 02:36:15 -0700 (PDT) Received: from [192.168.2.243] ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm5363134pzk.3.2010.04.19.02.36.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 19 Apr 2010 02:36:13 -0700 (PDT) Subject: Re: [PATCH -v5] MIPS: tracing: Optimize the implementation From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, Steven Rostedt In-Reply-To: <1271537514-19584-1-git-send-email-wuzhangjin@gmail.com> References: <1271537514-19584-1-git-send-email-wuzhangjin@gmail.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Mon, 19 Apr 2010 17:36:08 +0800 Message-ID: <1271669768.25163.2.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26428 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Sun, 2010-04-18 at 04:51 +0800, Wu Zhangjin wrote: [...] > diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S [...] > > @@ -45,8 +46,6 @@ > PTR_L a5, PT_R9(sp) > PTR_L a6, PT_R10(sp) > PTR_L a7, PT_R11(sp) > -#endif > -#ifdef CONFIG_64BIT > PTR_ADDIU sp, PT_SIZE > #else > PTR_ADDIU sp, (PT_SIZE + 8) > @@ -71,7 +70,7 @@ _mcount: > > MCOUNT_SAVE_REGS > #ifdef KBUILD_MCOUNT_RA_ADDRESS > - PTR_S t0, PT_R12(sp) /* t0 saved the location of the return address(at) by -mmcount-ra-address */ > + PTR_S $12, PT_R12(sp) /* $12 saved the location of the return address(at) */ > #endif > > move a0, ra /* arg1: next ip, selfaddr */ > @@ -137,25 +136,22 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra) > #ifdef CONFIG_DYNAMIC_FTRACE > PTR_L a1, PT_R31(sp) /* load the original ra from the stack */ > #ifdef KBUILD_MCOUNT_RA_ADDRESS > - PTR_L t0, PT_R12(sp) /* load the original t0 from the stack */ > + PTR_L a0, PT_R12(sp) /* arg1: the location of the return address */ > #endif > -#else > +#else /* ! CONFIG_DYNAMIC_FTRACE */ > MCOUNT_SAVE_REGS > move a1, ra /* arg2: next ip, selfaddr */ > #endif > > #ifdef KBUILD_MCOUNT_RA_ADDRESS > - bnez t0, 1f /* non-leaf func: t0 saved the location of the return address */ > + bnez a0, 1f /* non-leaf func: get the location of the return address from saved $12 */ > nop > - PTR_LA t0, PT_R1(sp) /* leaf func: get the location of at(old ra) from our own stack */ > -1: move a0, t0 /* arg1: the location of the return address */ > -#else > - PTR_LA a0, PT_R1(sp) /* arg1: &AT -> a0 */ > #endif > - jal prepare_ftrace_return The above change has broken the static function graph tracer with -mmcount-ra-address for it did not consider the argument 1 for static function graph tracer, a new revision of this patch will be sent out as "MIPS: tracing: adds misc cleanups and fixups". Regards, Wu Zhangjin From wuzhangjin@gmail.com Mon Apr 19 12:16:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Apr 2010 12:16:07 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:51302 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491166Ab0DSKQA (ORCPT ); Mon, 19 Apr 2010 12:16:00 +0200 Received: by pvc30 with SMTP id 30so2947493pvc.36 for ; Mon, 19 Apr 2010 03:15:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=5Ak2sHhCfigDK1FTCrIaTmkDBitnR4QY6dpHbeeFefc=; b=frZSg3Jb4aCxzqT3OgLAR9De5tfmoM9LG+EjT8DSrA3w6ewT1fMKiCBbQ0J7UUVQRu sfu6k33Tcy4i6+9lm/h/f96RemCkmZpNVlT/Hmuhgiq9WAEjV+EbS/C3d0+cD9JxRhpu T42Gx3TNd6K7F9F0yHESXisPKeYYTT79Pg2gU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=RYTzuANfF+pXOeSZbdRwXaQkPw+suciYmKPpIlpbtVVqbUs4SfwZvZVLOxqARGCKnH Bd30nfy2k3ckStc6vZW/DT99QQLx7UY6oevIzhSICLYqSQO+GAJQprU2/EIuEl8sEgkJ 2C/oyxXycW9Tyw6RONZ0EsiCHTNtPqDPJfRUY= Received: by 10.115.132.40 with SMTP id j40mr3695498wan.21.1271671676364; Mon, 19 Apr 2010 03:07:56 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm5379819pzk.15.2010.04.19.03.07.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 19 Apr 2010 03:07:55 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: Steven Rostedt , linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH v6] MIPS: tracing: adds misc cleanups and fixups Date: Mon, 19 Apr 2010 18:07:46 +0800 Message-Id: <89d59a54efbe4fb9e75e16638d5acec162624a40.1271671588.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26429 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Changes: v5 -> v6: + Fixup of the static function graph tracer with -mmcount-ra-address The last patch have broken the static function graph tracer with -mmcount-ra-address via passing a wrong argument (a0), this patch fixes it. + Cleanup of comments in mcount.S. v4 -> v5: * All of the these changes have been tested in 32bit & 64bit kernel with gcc 4.4 & 4.5, including kernel & module Ftrace support. + Fixup of the module support broken by the change of v1->v2. As the source code(and also the objdump result of the kernel image) of -mmcount-ra-address shows, the change of v1->v2 is wrong and has broken the module support: For 64bit kernel with -mmcount-ra-address, the return address saving operation is put in the delay slot of the jump instruction(calling site of _mcount), so, the offset of "b 1f" is the same to the -mno-mcount-ra-address: 16. but for 32bit kernel, since there is already an instruction put in the delay slot, the return address operation must be put before the jump instruciton, so, the offset is bigger than the one with -mno-mcount-ra-address: 16+4=20. + Fixup of the 32bit support with gcc 4.5 As the doc[1] of gcc-4.5 shows, the -mmcount-ra-address uses the $12 to transfer the stack offset of the return address to the _mcount function. in 64bit kernel, $12 is t0, but in 32bit kernel, it is t4, so, we need to use $12 instead of t0 here to cover the 64bit and 32bit support. [1] Gcc doc: MIPS Options http://gcc.gnu.org/onlinedocs/gcc/MIPS-Options.html + Cleanup of mcount.S o merges two continuous "#ifdef CONFIG_64BIT". o removes the instruction "move a0, t0" via using a0 directly. o share the common "PTR_LA a0, PT_R1(sp)" v3 -> v4: + Fixup of 'undefined ftrace_graph_caller' ftrace_graph_caller variable is only needed by CONFIG_FUNCTION_GRAPH_TRACER, so, wrap it with #ifdef. v2 -> v3: + Fixes the buidling error of the changes from v2. v1 -> v2: + Fixes the support of -mmcount-ra-address The offset of "b 1f" instruction should be 20 for leaf-function and 24 for non-leaf function when -mmcount-ra-address is enabled. This patch adds a new get_insn_b_1f() function to get the different "b 1f" instruction. (only test without -mmcount-ra-address.) v1: + Reduce the runtime overhead o Uses macros instead of variables for the fixed instructions to reduce memory access o Moves the Initilization of the instructions which will be fixed after linking from ftrace_make_nop/ftrace_make_call to ftrace_dyn_arch_init() and encodes the instructions through uasm(arch/mips/include/asm/uasm.h). o A common macro in_module() is defined to determine which space the instruction pointer stays in and several related conditional statements are converted to conditional operator(? :) statement. + Cleanup the whole stuff Lots of comments/macros have been cleaned up to let it look better. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/ftrace.h | 12 ++- arch/mips/kernel/ftrace.c | 217 +++++++++++++++++++++++----------------- arch/mips/kernel/mcount.S | 47 +++++---- 3 files changed, 160 insertions(+), 116 deletions(-) diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h index ce35c9a..29d71c0 100644 --- a/arch/mips/include/asm/ftrace.h +++ b/arch/mips/include/asm/ftrace.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive for * more details. * - * Copyright (C) 2009 DSLab, Lanzhou University, China + * Copyright (C) 2009, 2010 DSLab, Lanzhou University, China * Author: Wu Zhangjin */ @@ -19,6 +19,14 @@ extern void _mcount(void); #define mcount _mcount +/* + * If the Instruction Pointer is in module space (0xc0000000), return true; + * otherwise, it is in kernel space (0x80000000), return false. + * + * FIXME: This may not work in some cases. + */ +#define in_module(ip) (unlikely((ip) & 0x40000000)) + #define safe_load(load, src, dst, error) \ do { \ asm volatile ( \ @@ -83,8 +91,8 @@ static inline unsigned long ftrace_call_adjust(unsigned long addr) struct dyn_arch_ftrace { }; - #endif /* CONFIG_DYNAMIC_FTRACE */ + #endif /* __ASSEMBLY__ */ #endif /* CONFIG_FUNCTION_TRACER */ #endif /* _ASM_MIPS_FTRACE_H */ diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index e9e64e0..d01ab52 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -2,7 +2,7 @@ * Code for replacing ftrace calls with jumps. * * Copyright (C) 2007-2008 Steven Rostedt - * Copyright (C) 2009 DSLab, Lanzhou University, China + * Copyright (C) 2009, 2010 DSLab, Lanzhou University, China * Author: Wu Zhangjin * * Thanks goes to Steven Rostedt for writing the original x86 version. @@ -15,15 +15,51 @@ #include #include #include +#include + +#define INSN_S_R_SP 0xafb00000 /* s{d,w} R, offset(sp) */ #ifdef CONFIG_DYNAMIC_FTRACE -#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */ -#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ -#define jump_insn_encode(op_code, addr) \ - ((unsigned int)((op_code) | (((addr) >> 2) & ADDR_MASK))) +/* Before linking, the following instructions are fixed. */ +#ifdef CONFIG_CPU_LOONGSON2F +#define INSN_NOP 0x00200825 /* or at, at, zero */ +#else +#define INSN_NOP 0x00000000 /* nop */ +#endif +#define INSN_B_1F_16 0x10000004 /* b 1f; offset = (16 >> 2) */ +#define INSN_B_1F_20 0x10000005 /* b 1f; offset = (20 >> 2) */ + +/* After linking, the following instructions are fixed. */ +static unsigned int insn_jal_ftrace_caller __read_mostly; +static unsigned int insn_lui_v1_hi16_mcount __read_mostly; +static unsigned int insn_j_ftrace_graph_caller __maybe_unused __read_mostly; + +/* The following instructions are encoded in the run-time */ +/* insn: jal func; op_code|addr : 31...26|25 ....0 */ +#define INSN_JAL(addr) \ + ((unsigned int)(0x0c000000 | (((addr) >> 2) & 0x03ffffff))) + +static inline void ftrace_dyn_arch_init_insns(void) +{ + u32 *buf; + unsigned int v1; -static unsigned int ftrace_nop = 0x00000000; + /* lui v1, hi16_mcount */ + v1 = 3; + buf = (u32 *)&insn_lui_v1_hi16_mcount; + UASM_i_LA_mostly(&buf, v1, MCOUNT_ADDR); + + /* jal (ftrace_caller + 8), jump over the first two instruction */ + buf = (u32 *)&insn_jal_ftrace_caller; + uasm_i_jal(&buf, (FTRACE_ADDR + 8)); + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + /* j ftrace_graph_caller */ + buf = (u32 *)&insn_j_ftrace_graph_caller; + uasm_i_j(&buf, (unsigned long)ftrace_graph_caller); +#endif +} static int ftrace_modify_code(unsigned long ip, unsigned int new_code) { @@ -31,7 +67,6 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) /* *(unsigned int *)ip = new_code; */ safe_store_code(new_code, ip, faulted); - if (unlikely(faulted)) return -EFAULT; @@ -40,84 +75,82 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) return 0; } -static int lui_v1; -static int jal_mcount; - int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, unsigned long addr) { unsigned int new; - int faulted; unsigned long ip = rec->ip; - /* We have compiled module with -mlong-calls, but compiled the kernel - * without it, we need to cope with them respectively. */ - if (ip & 0x40000000) { - /* record it for ftrace_make_call */ - if (lui_v1 == 0) { - /* lui_v1 = *(unsigned int *)ip; */ - safe_load_code(lui_v1, ip, faulted); - - if (unlikely(faulted)) - return -EFAULT; - } - - /* lui v1, hi_16bit_of_mcount --> b 1f (0x10000004) - * addiu v1, v1, low_16bit_of_mcount - * move at, ra - * jalr v1 - * nop - * 1f: (ip + 12) - */ - new = 0x10000004; - } else { - /* record/calculate it for ftrace_make_call */ - if (jal_mcount == 0) { - /* We can record it directly like this: - * jal_mcount = *(unsigned int *)ip; - * Herein, jump over the first two nop instructions */ - jal_mcount = jump_insn_encode(JAL, (MCOUNT_ADDR + 8)); - } - - /* move at, ra - * jalr v1 --> nop - */ - new = ftrace_nop; + /* + * We have compiled modules with -mlong-calls, but compiled kernel + * without it, therefore, need to cope with them respectively. + * + * For module: + * + * lui v1, hi16_mcount --> b 1f + * addiu v1, v1, lo16_mcount + * move at, ra + * jalr v1 + * nop + * 1f: (ip + 16) + * For kernel: + * + * move at, ra + * jal _mcount --> nop + * + * And with the -mmcount-ra-address option, the offset may be 20 for + * leaf fuction and 24 for non-leaf function. + */ + + if (!in_module(ip)) + new = INSN_NOP; + else { +#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT) + new = INSN_B_1F_20; +#else + new = INSN_B_1F_16; +#endif } + return ftrace_modify_code(ip, new); } -static int modified; /* initialized as 0 by default */ - int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) { unsigned int new; unsigned long ip = rec->ip; - /* We just need to remove the "b ftrace_stub" at the fist time! */ - if (modified == 0) { - modified = 1; - ftrace_modify_code(addr, ftrace_nop); - } - /* ip, module: 0xc0000000, kernel: 0x80000000 */ - new = (ip & 0x40000000) ? lui_v1 : jal_mcount; + new = in_module(ip) ? insn_lui_v1_hi16_mcount : insn_jal_ftrace_caller; return ftrace_modify_code(ip, new); } -#define FTRACE_CALL_IP ((unsigned long)(&ftrace_call)) - int ftrace_update_ftrace_func(ftrace_func_t func) { unsigned int new; - new = jump_insn_encode(JAL, (unsigned long)func); + new = INSN_JAL((unsigned long)func); - return ftrace_modify_code(FTRACE_CALL_IP, new); + return ftrace_modify_code((unsigned long)(&ftrace_call), new); } int __init ftrace_dyn_arch_init(void *data) { + ftrace_dyn_arch_init_insns(); + + /* + * We are safe to remove the "b ftrace_stub" for the current + * ftrace_caller() is almost empty (only the stack operations), and + * most importantly, the calling to mcount will be disabled later in + * ftrace_init(), then there is no 'big' overhead. And in the future, + * we are hoping the function_trace_stop is initialized as 1 then we + * can eventually remove that 'useless' "b ftrace_stub" and the + * following nop. Currently, although we can call ftrace_stop() to set + * function_trace_stop as 1, but it will change the behavior of the + * Function Tracer. + */ + ftrace_modify_code(MCOUNT_ADDR, INSN_NOP); + /* The return code is retured via data */ *(unsigned long *)data = 0; @@ -128,30 +161,24 @@ int __init ftrace_dyn_arch_init(void *data) #ifdef CONFIG_FUNCTION_GRAPH_TRACER #ifdef CONFIG_DYNAMIC_FTRACE - extern void ftrace_graph_call(void); -#define JMP 0x08000000 /* jump to target directly */ -#define CALL_FTRACE_GRAPH_CALLER \ - jump_insn_encode(JMP, (unsigned long)(&ftrace_graph_caller)) #define FTRACE_GRAPH_CALL_IP ((unsigned long)(&ftrace_graph_call)) int ftrace_enable_ftrace_graph_caller(void) { return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, - CALL_FTRACE_GRAPH_CALLER); + insn_j_ftrace_graph_caller); } int ftrace_disable_ftrace_graph_caller(void) { - return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, ftrace_nop); + return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, INSN_NOP); } - #endif /* !CONFIG_DYNAMIC_FTRACE */ #ifndef KBUILD_MCOUNT_RA_ADDRESS -#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */ -#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */ -#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ +#define INSN_S_RA_SP 0xafbf0000 /* s{d,w} ra, offset(sp) */ +#define STACK_OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ unsigned long ftrace_get_parent_addr(unsigned long self_addr, unsigned long parent, @@ -162,35 +189,35 @@ unsigned long ftrace_get_parent_addr(unsigned long self_addr, unsigned int code; int faulted; - /* in module or kernel? */ - if (self_addr & 0x40000000) { - /* module: move to the instruction "lui v1, HI_16BIT_OF_MCOUNT" */ - ip = self_addr - 20; - } else { - /* kernel: move to the instruction "move ra, at" */ - ip = self_addr - 12; - } + /* + * For module, move the ip from calling site of mcount to the + * instruction "lui v1, hi_16bit_of_mcount"(offset is 20), but for + * kernel, move to the instruction "move ra, at"(offset is 12) + */ + ip = self_addr - (in_module(self_addr) ? 20 : 12); - /* search the text until finding the non-store instruction or "s{d,w} - * ra, offset(sp)" instruction */ + /* + * search the text until finding the non-store instruction or "s{d,w} + * ra, offset(sp)" instruction + */ do { ip -= 4; /* get the code at "ip": code = *(unsigned int *)ip; */ safe_load_code(code, ip, faulted); - if (unlikely(faulted)) return 0; - /* If we hit the non-store instruction before finding where the + /* + * If we hit the non-store instruction before finding where the * ra is stored, then this is a leaf function and it does not - * store the ra on the stack. */ - if ((code & S_R_SP) != S_R_SP) + * store the ra on the stack. + */ + if ((code & INSN_S_R_SP) != INSN_S_R_SP) return parent_addr; + } while (((code & INSN_S_RA_SP) != INSN_S_RA_SP)); - } while (((code & S_RA_SP) != S_RA_SP)); - - sp = fp + (code & OFFSET_MASK); + sp = fp + (code & STACK_OFFSET_MASK); /* ra = *(unsigned long *)sp; */ safe_load_stack(ra, sp, faulted); @@ -201,8 +228,7 @@ unsigned long ftrace_get_parent_addr(unsigned long self_addr, return sp; return 0; } - -#endif +#endif /* !KBUILD_MCOUNT_RA_ADDRESS */ /* * Hook the return address and push it in the stack of return addrs @@ -211,16 +237,17 @@ unsigned long ftrace_get_parent_addr(unsigned long self_addr, void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, unsigned long fp) { + int faulted; unsigned long old; struct ftrace_graph_ent trace; unsigned long return_hooker = (unsigned long) &return_to_handler; - int faulted; if (unlikely(atomic_read(¤t->tracing_graph_pause))) return; - /* "parent" is the stack address saved the return address of the caller + /* + * "parent" is the stack address saved the return address of the caller * of _mcount. * * if the gcc < 4.5, a leaf function does not save the return address @@ -241,12 +268,14 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, if (unlikely(faulted)) goto out; #ifndef KBUILD_MCOUNT_RA_ADDRESS - parent = (unsigned long *)ftrace_get_parent_addr(self_addr, old, - (unsigned long)parent, - fp); - /* If fails when getting the stack address of the non-leaf function's - * ra, stop function graph tracer and return */ - if (parent == 0) + parent = (unsigned long *)ftrace_get_parent_addr( + self_addr, old, (unsigned long)parent, fp); + + /* + * If fails on getting the stack address of the non-leaf function's ra, + * stop function graph tracer and return + */ + if (unlikely(parent == 0)) goto out; #endif /* *parent = return_hooker; */ diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S index 6851fc9..9ba0374 100644 --- a/arch/mips/kernel/mcount.S +++ b/arch/mips/kernel/mcount.S @@ -6,6 +6,7 @@ * more details. * * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China + * Copyright (C) 2010 DSLab, Lanzhou University, China * Author: Wu Zhangjin */ @@ -45,8 +46,6 @@ PTR_L a5, PT_R9(sp) PTR_L a6, PT_R10(sp) PTR_L a7, PT_R11(sp) -#endif -#ifdef CONFIG_64BIT PTR_ADDIU sp, PT_SIZE #else PTR_ADDIU sp, (PT_SIZE + 8) @@ -71,14 +70,14 @@ _mcount: MCOUNT_SAVE_REGS #ifdef KBUILD_MCOUNT_RA_ADDRESS - PTR_S t0, PT_R12(sp) /* t0 saved the location of the return address(at) by -mmcount-ra-address */ + PTR_S $12, PT_R12(sp) /* save location of parent's return address */ #endif - move a0, ra /* arg1: next ip, selfaddr */ + move a0, ra /* arg1: self return address */ .globl ftrace_call ftrace_call: nop /* a placeholder for the call to a real tracing function */ - move a1, AT /* arg2: the caller's next ip, parent */ + move a1, AT /* arg2: parent's return address */ #ifdef CONFIG_FUNCTION_GRAPH_TRACER .globl ftrace_graph_call @@ -119,9 +118,9 @@ NESTED(_mcount, PT_SIZE, ra) static_trace: MCOUNT_SAVE_REGS - move a0, ra /* arg1: next ip, selfaddr */ + move a0, ra /* arg1: self return address */ jalr t2 /* (1) call *ftrace_trace_function */ - move a1, AT /* arg2: the caller's next ip, parent */ + move a1, AT /* arg2: parent's return address */ MCOUNT_RESTORE_REGS .globl ftrace_stub @@ -134,28 +133,36 @@ ftrace_stub: #ifdef CONFIG_FUNCTION_GRAPH_TRACER NESTED(ftrace_graph_caller, PT_SIZE, ra) -#ifdef CONFIG_DYNAMIC_FTRACE - PTR_L a1, PT_R31(sp) /* load the original ra from the stack */ -#ifdef KBUILD_MCOUNT_RA_ADDRESS - PTR_L t0, PT_R12(sp) /* load the original t0 from the stack */ -#endif -#else +#ifndef CONFIG_DYNAMIC_FTRACE MCOUNT_SAVE_REGS - move a1, ra /* arg2: next ip, selfaddr */ #endif + /* arg1: Get the location of the parent's return address */ #ifdef KBUILD_MCOUNT_RA_ADDRESS - bnez t0, 1f /* non-leaf func: t0 saved the location of the return address */ +#ifdef CONFIG_DYNAMIC_FTRACE + PTR_L a0, PT_R12(sp) +#else + move a0, $12 +#endif + bnez a0, 1f /* arg1: non-leaf func: stored in $12 */ nop - PTR_LA t0, PT_R1(sp) /* leaf func: get the location of at(old ra) from our own stack */ -1: move a0, t0 /* arg1: the location of the return address */ +#endif + PTR_LA a0, PT_R1(sp) /* leaf func: the location in current stack */ + +1: + /* arg2: Get self return address */ +#ifdef CONFIG_DYNAMIC_FTRACE + PTR_L a1, PT_R31(sp) #else - PTR_LA a0, PT_R1(sp) /* arg1: &AT -> a0 */ + move a1, ra #endif + jal prepare_ftrace_return + + /* arg3: Get frame pointer of current stack */ #ifdef CONFIG_FRAME_POINTER - move a2, fp /* arg3: frame pointer */ -#else + move a2, fp +#else /* ! CONFIG_FRAME_POINTER */ #ifdef CONFIG_64BIT PTR_LA a2, PT_SIZE(sp) #else -- 1.7.0 From David.Daney@caviumnetworks.com Mon Apr 19 20:43:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Apr 2010 20:43:55 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12817 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492152Ab0DSSns (ORCPT ); Mon, 19 Apr 2010 20:43:48 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 19 Apr 2010 11:43:54 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 11:43:15 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 11:43:15 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3JIhCUj017834; Mon, 19 Apr 2010 11:43:12 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3JIhBeB017833; Mon, 19 Apr 2010 11:43:11 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Don't vmap things at address zero. Date: Mon, 19 Apr 2010 11:43:10 -0700 Message-Id: <1271702590-17799-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 X-OriginalArrivalTime: 19 Apr 2010 18:43:15.0180 (UTC) FILETIME=[2BB35AC0:01CADFF0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26430 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips In the 64-bit kernel we use swapper_pg_dir for three different things. 1) xuseg mappings for kernel threads. 2) vmap mappings for all kernel-space accesses in xkseg. 3) vmap mappings for kernel modules in ksseg (kseg2). Due to how the TLB refill handlers work, any mapping established in xkseg or ksseg will also establish a xuseg mapping that should never be used by the kernel. In order to be able to use exceptions to trap NULL pointer dereferences, we need to ensure that nothing is mapped at address zero. Since vmap mappings in xkseg are reflected in xuseg, this means we need to ensure that there are no vmap mappings established at the start of xkseg. So we move back VMALLOC_START to avoid establishing vmap mappings at the start of xkseg. Signed-off-by: David Daney --- arch/mips/include/asm/pgtable-64.h | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index adc2093..91db014 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -120,9 +120,14 @@ #endif #define FIRST_USER_ADDRESS 0UL -#define VMALLOC_START MAP_BASE +/* + * TLB refill handlers also map the vmalloc area into xuseg. Avoid + * the first couple of pages so NULL pointer dereferences will still + * reliably trap. + */ +#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE)) #define VMALLOC_END \ - (VMALLOC_START + \ + (MAP_BASE + \ min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ (1UL << cpu_vmbits)) - (1UL << 32)) -- 1.6.6.1 From ralf@linux-mips.org Mon Apr 19 23:41:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Apr 2010 23:41:05 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49563 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492600Ab0DSVlC (ORCPT ); Mon, 19 Apr 2010 23:41:02 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3JLexZY028764; Mon, 19 Apr 2010 22:40:59 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3JLevBG028759; Mon, 19 Apr 2010 22:40:57 +0100 Date: Mon, 19 Apr 2010 22:40:57 +0100 From: Ralf Baechle To: wu zhangjin , linux-mips@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] ftrace porting of linux-2.6.29 for mips Message-ID: <20100419214057.GG18697@linux-mips.org> References: <20090403113315.GC6629@adriano.hkcable.com.hk> <20090403141158.GA27751@adriano.hkcable.com.hk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090403141158.GA27751@adriano.hkcable.com.hk> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26431 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Apr 03, 2009 at 10:11:59PM +0800, Zhang Le wrote: > BTW, it seems linux-mips@vger.kernel.org is not an alias of > linux-mips@linux-mips.org, since I haven't seen our previous emails appear in > linux-mips ML's archive. So I have added linux-mips@linux-mips.org to CC list. No, as far as I can say that list is dead. It's years that the list last came to my attention and actually I thought it had been deleted as duplicate lists for essentially the same purpose are causing confusing and postings going down the drain unnoticed. Any of you subscribed there, is there activity? Ralf From David.Daney@caviumnetworks.com Tue Apr 20 02:20:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 02:20:33 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19797 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492647Ab0DTAU3 (ORCPT ); Tue, 20 Apr 2010 02:20:29 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 19 Apr 2010 17:20:40 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:20:08 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:20:07 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3K0K5Cx027938; Mon, 19 Apr 2010 17:20:05 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3K0K5wa027937; Mon, 19 Apr 2010 17:20:05 -0700 From: David Daney To: ltt-dev@lists.casi.polymtl.ca Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH 1/3] lttng: MIPS: Fix syscall entry tracing. Date: Mon, 19 Apr 2010 17:19:49 -0700 Message-Id: <1271722791-27885-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> References: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 20 Apr 2010 00:20:07.0969 (UTC) FILETIME=[3B763110:01CAE01F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26432 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips For the 32-bit kernel and all three ABIs of the 64-bit kernel, we need to test the _TIF_KERNEL_TRACE flag on syscall entry. Otherwise, no syscall entry tracing for you! Signed-off-by: David Daney --- arch/mips/kernel/scall32-o32.S | 2 +- arch/mips/kernel/scall64-64.S | 2 +- arch/mips/kernel/scall64-n32.S | 2 +- arch/mips/kernel/scall64-o32.S | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index fd2a9bb..28f262d 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -52,7 +52,7 @@ NESTED(handle_sys, PT_SIZE, sp) stack_done: lw t0, TI_FLAGS($28) # syscall tracing enabled? - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_KERNEL_TRACE and t0, t1 bnez t0, syscall_trace_entry # -> yes diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 18bf7f3..38c0c95 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -54,7 +54,7 @@ NESTED(handle_sys64, PT_SIZE, sp) sd a3, PT_R26(sp) # save a3 for syscall restarting - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_KERNEL_TRACE LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? and t0, t1, t0 bnez t0, syscall_trace_entry diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 3541fd3..fbecc01 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -53,7 +53,7 @@ NESTED(handle_sysn32, PT_SIZE, sp) sd a3, PT_R26(sp) # save a3 for syscall restarting - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_KERNEL_TRACE LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? and t0, t1, t0 bnez t0, n32_syscall_trace_entry diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 14dde4c..0db5589 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -81,7 +81,7 @@ NESTED(handle_sys, PT_SIZE, sp) PTR 4b, bad_stack .previous - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT + li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_KERNEL_TRACE LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? and t0, t1, t0 bnez t0, trace_a_syscall -- 1.6.6.1 From David.Daney@caviumnetworks.com Tue Apr 20 02:20:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 02:20:58 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19792 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492646Ab0DTAU3 (ORCPT ); Tue, 20 Apr 2010 02:20:29 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 19 Apr 2010 17:20:40 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:20:08 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:20:07 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3K0K5vt027942; Mon, 19 Apr 2010 17:20:05 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3K0K5Nn027941; Mon, 19 Apr 2010 17:20:05 -0700 From: David Daney To: ltt-dev@lists.casi.polymtl.ca Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH 2/3] lttng: MIPS: Dump MIPS system call tables. Date: Mon, 19 Apr 2010 17:19:50 -0700 Message-Id: <1271722791-27885-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> References: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 20 Apr 2010 00:20:07.0969 (UTC) FILETIME=[3B763110:01CAE01F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26433 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The 64-bit kernel may support all three ABIs, so we iterate the sys_call_tables of all of enabled ABIs. Signed-off-by: David Daney --- arch/mips/Kconfig | 1 + arch/mips/kernel/scall64-64.S | 3 +- arch/mips/kernel/scall64-n32.S | 2 + arch/mips/kernel/scall64-o32.S | 8 +++--- arch/mips/kernel/syscall.c | 58 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 67 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5e1133f..a690e9b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -8,6 +8,7 @@ config MIPS # Horrible source of confusion. Die, die, die ... select EMBEDDED select RTC_LIB if !LEMOTE_FULOONG2E + select HAVE_LTT_DUMP_TABLES mainmenu "Linux/MIPS Kernel Configuration" diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 38c0c95..f437a01 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -125,7 +125,8 @@ illegal_syscall: END(handle_sys64) .align 3 -sys_call_table: + .type sys_call_table,@object +EXPORT(sys_call_table) PTR sys_read /* 5000 */ PTR sys_write PTR sys_open diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index fbecc01..49ab15a 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -119,6 +119,8 @@ not_n32_scall: END(handle_sysn32) + .align 3 + .type sysn32_call_table,@object EXPORT(sysn32_call_table) PTR sys_read /* 6000 */ PTR sys_write diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 0db5589..01500cb 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -53,7 +53,7 @@ NESTED(handle_sys, PT_SIZE, sp) sll a3, a3, 0 dsll t0, v0, 3 # offset into table - ld t2, (sys_call_table - (__NR_O32_Linux * 8))(t0) + ld t2, (syso32_call_table - (__NR_O32_Linux * 8))(t0) sd a3, PT_R26(sp) # save a3 for syscall restarting @@ -179,7 +179,7 @@ LEAF(sys32_syscall) beqz t0, einval # do not recurse dsll t1, t0, 3 beqz v0, einval - ld t2, sys_call_table(t1) # syscall routine + ld t2, syso32_call_table(t1) # syscall routine move a0, a1 # shift argument registers move a1, a2 @@ -201,8 +201,8 @@ einval: li v0, -ENOSYS END(sys32_syscall) .align 3 - .type sys_call_table,@object -sys_call_table: + .type syso32_call_table,@object +EXPORT(syso32_call_table) PTR sys32_syscall /* 4000 */ PTR sys_exit PTR sys_fork diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 1452e2f..996ef29 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -560,3 +561,60 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[]) return -__v0; } + +void ltt_dump_sys_call_table(void *call_data) +{ + int i; + char namebuf[KSYM_NAME_LEN]; + +#ifdef CONFIG_32BIT + extern struct { + unsigned long ptr; + long j; + } sys_call_table[]; + for (i = 0; i < __NR_O32_Linux_syscalls; i++) { + sprint_symbol(namebuf, sys_call_table[i].ptr); + __trace_mark(0, syscall_state, sys_call_table, call_data, + "id %d address %p symbol %s", + i + __NR_O32_Linux, (void*)sys_call_table[i].ptr, namebuf); + } +#endif +#ifdef CONFIG_64BIT +# ifdef CONFIG_MIPS32_O32 + for (i = 0; i < __NR_O32_Linux_syscalls; i++) { + extern unsigned long syso32_call_table[]; + sprint_symbol(namebuf, syso32_call_table[i]); + __trace_mark(0, syscall_state, sys_call_table, call_data, + "id %d address %p symbol %s", + i + __NR_O32_Linux, (void*)syso32_call_table[i], namebuf); + } +# endif + + for (i = 0; i < __NR_64_Linux_syscalls; i++) { + extern unsigned long sys_call_table[]; + sprint_symbol(namebuf, sys_call_table[i]); + __trace_mark(0, syscall_state, sys_call_table, call_data, + "id %d address %p symbol %s", + i + __NR_64_Linux, (void*)sys_call_table[i], namebuf); + } + +# ifdef CONFIG_MIPS32_N32 + for (i = 0; i < __NR_N32_Linux_syscalls; i++) { + extern unsigned long sysn32_call_table[]; + sprint_symbol(namebuf, sysn32_call_table[i]); + __trace_mark(0, syscall_state, sys_call_table, call_data, + "id %d address %p symbol %s", + i + __NR_N32_Linux, (void*)sysn32_call_table[i], namebuf); + } +# endif +#endif + +} +EXPORT_SYMBOL_GPL(ltt_dump_sys_call_table); + +void ltt_dump_idt_table(void *call_data) +{ + /* No IDT information yet. */ + return; +} +EXPORT_SYMBOL_GPL(ltt_dump_idt_table); -- 1.6.6.1 From David.Daney@caviumnetworks.com Tue Apr 20 02:21:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 02:21:24 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19791 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492639Ab0DTAU3 (ORCPT ); Tue, 20 Apr 2010 02:20:29 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 19 Apr 2010 17:20:40 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:20:08 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:20:07 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3K0K1BZ027934; Mon, 19 Apr 2010 17:20:01 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3K0JtMl027931; Mon, 19 Apr 2010 17:19:55 -0700 From: David Daney To: ltt-dev@lists.casi.polymtl.ca Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH 0/3] LTTng patches for MIPS CPUs. Date: Mon, 19 Apr 2010 17:19:48 -0700 Message-Id: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 X-OriginalArrivalTime: 20 Apr 2010 00:20:07.0969 (UTC) FILETIME=[3B763110:01CAE01F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26434 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips After speaking with Mathieu at the Linux Collaboration Summit, I worked up these patches. Thanks Mathieu, for helping me with this. They should be fairly straight forward, the first one enables syscall entry tracing, the second gives us system call names in lttv, and the third fixes up the trace clock to work better on Octeon CPUs. The base of the patch set is the patch-2.6.32.9-lttng-0.198.tar.gz bundle from the download page on the web site. The patches are really only tested on a 64-bit kernel running on a 12 CPU Octeon SOC. I think the 32-bit code will compile and is correct, but I have not tested it. David Daney (3): lttng: MIPS: Fix syscall entry tracing. lttng: MIPS: Dump MIPS system call tables. lttng: MIPS: Use 64 bit counter for trace clock on Octeon CPUs. arch/mips/Kconfig | 5 ++- arch/mips/include/asm/trace-clock.h | 39 +++++++++++++++++++++++- arch/mips/kernel/scall32-o32.S | 2 +- arch/mips/kernel/scall64-64.S | 5 ++- arch/mips/kernel/scall64-n32.S | 4 ++- arch/mips/kernel/scall64-o32.S | 10 +++--- arch/mips/kernel/smp.c | 2 + arch/mips/kernel/syscall.c | 58 +++++++++++++++++++++++++++++++++++ 8 files changed, 113 insertions(+), 12 deletions(-) From David.Daney@caviumnetworks.com Tue Apr 20 02:21:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 02:21:50 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19806 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492648Ab0DTAUa (ORCPT ); Tue, 20 Apr 2010 02:20:30 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 19 Apr 2010 17:20:40 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:20:08 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 17:20:07 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3K0K5Rw027946; Mon, 19 Apr 2010 17:20:05 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3K0K5Vj027945; Mon, 19 Apr 2010 17:20:05 -0700 From: David Daney To: ltt-dev@lists.casi.polymtl.ca Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH 3/3] lttng: MIPS: Use 64 bit counter for trace clock on Octeon CPUs. Date: Mon, 19 Apr 2010 17:19:51 -0700 Message-Id: <1271722791-27885-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> References: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 20 Apr 2010 00:20:07.0969 (UTC) FILETIME=[3B763110:01CAE01F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26435 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Cavium Octeon CPUs have a 64-bit cycle counter that is synchronized when the CPUs are brought on-line. So for this case we don't need any fancy stuff. Signed-off-by: David Daney --- arch/mips/Kconfig | 4 +- arch/mips/include/asm/trace-clock.h | 39 ++++++++++++++++++++++++++++++++++- arch/mips/kernel/smp.c | 2 + 3 files changed, 42 insertions(+), 3 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a690e9b..9e91e8c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1782,8 +1782,8 @@ config HAVE_GET_CYCLES_32 def_bool y depends on !CPU_R4400_WORKAROUNDS select HAVE_TRACE_CLOCK - select HAVE_TRACE_CLOCK_32_TO_64 - select HAVE_UNSYNCHRONIZED_TSC + select HAVE_TRACE_CLOCK_32_TO_64 if (!CPU_CAVIUM_OCTEON) + select HAVE_UNSYNCHRONIZED_TSC if (!CPU_CAVIUM_OCTEON) # # Use the generic interrupt handling code in kernel/irq/: diff --git a/arch/mips/include/asm/trace-clock.h b/arch/mips/include/asm/trace-clock.h index 3d8cb0f..a052f42 100644 --- a/arch/mips/include/asm/trace-clock.h +++ b/arch/mips/include/asm/trace-clock.h @@ -12,6 +12,43 @@ #define TRACE_CLOCK_MIN_PROBE_DURATION 200 +#ifdef CONFIG_CPU_CAVIUM_OCTEON + +#include + +#define TC_HW_BITS 64 + +static inline u32 trace_clock_read32(void) +{ + return (u32)read_c0_cvmcount(); /* only need the 32 LSB */ +} + +static inline u64 trace_clock_read64(void) +{ + return read_c0_cvmcount(); +} + +static inline u64 trace_clock_frequency(void) +{ + return octeon_get_clock_rate(); +} + +static inline u32 trace_clock_freq_scale(void) +{ + return 1; +} + +static inline void get_trace_clock(void) +{ + return; +} + +static inline void put_trace_clock(void) +{ + return; +} + +#else /* !CONFIG_CPU_CAVIUM_OCTEON */ /* * Number of hardware clock bits. The higher order bits are expected to be 0. * If the hardware clock source has more than 32 bits, the bits higher than the @@ -65,7 +102,7 @@ static inline void put_trace_clock(void) { put_synthetic_tsc(); } - +#endif /* CONFIG_CPU_CAVIUM_OCTEON */ static inline void set_trace_clock_is_sync(int state) { } diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index f8c50d1..42083eb 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -159,7 +159,9 @@ void __init smp_cpus_done(unsigned int max_cpus) { mp_ops->cpus_done(); synchronise_count_master(); +#ifdef CONFIG_HAVE_UNSYNCHRONIZED_TSC test_tsc_synchronization(); +#endif } /* called from main before smp_init() */ -- 1.6.6.1 From ralf@linux-mips.org Tue Apr 20 02:28:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 02:28:41 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35313 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492656Ab0DTA2i (ORCPT ); Tue, 20 Apr 2010 02:28:38 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3K0SZ0k032478; Tue, 20 Apr 2010 01:28:35 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3K0SZ0l032469; Tue, 20 Apr 2010 01:28:35 +0100 Date: Tue, 20 Apr 2010 01:28:35 +0100 From: Ralf Baechle To: wu zhangjin , linux-mips@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] ftrace porting of linux-2.6.29 for mips Message-ID: <20100420002835.GH18697@linux-mips.org> References: <20090403113315.GC6629@adriano.hkcable.com.hk> <20090403141158.GA27751@adriano.hkcable.com.hk> <20100419214057.GG18697@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100419214057.GG18697@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26436 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 19, 2010 at 10:40:57PM +0100, Ralf Baechle wrote: > > BTW, it seems linux-mips@vger.kernel.org is not an alias of > > linux-mips@linux-mips.org, since I haven't seen our previous emails appear in > > linux-mips ML's archive. So I have added linux-mips@linux-mips.org to CC list. > > No, as far as I can say that list is dead. It's years that the list last > came to my attention and actually I thought it had been deleted as duplicate > lists for essentially the same purpose are causing confusing and postings > going down the drain unnoticed. > > Any of you subscribed there, is there activity? According to the postmaster of vger there is primarily spam on the list and he agreed to remove the list. So this posting cc'ed to it should hopefully bounce or at least be the laster one :-) Ralf From ralf@linux-mips.org Tue Apr 20 03:02:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 03:02:21 +0200 (CEST) Received: from [81.2.74.5] ([81.2.74.5]:40977 "EHLO h5.dl5rb.org.uk" rhost-flags-FAIL-FAIL-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492698Ab0DTBCF (ORCPT ); Tue, 20 Apr 2010 03:02:05 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3K11Wrq000819; Tue, 20 Apr 2010 02:01:32 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3K11VTn000818; Tue, 20 Apr 2010 02:01:31 +0100 Date: Tue, 20 Apr 2010 02:01:30 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Don't vmap things at address zero. Message-ID: <20100420010130.GA663@linux-mips.org> References: <1271702590-17799-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1271702590-17799-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26437 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 19, 2010 at 11:43:10AM -0700, David Daney wrote: Thanks, applied. Ralf From compudj@krystal.dyndns.org Tue Apr 20 15:56:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 15:56:15 +0200 (CEST) Received: from tomts13.bellnexxia.net ([209.226.175.34]:33416 "EHLO tomts13-srv.bellnexxia.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492772Ab0DTN4L (ORCPT ); Tue, 20 Apr 2010 15:56:11 +0200 Received: from toip4.srvr.bell.ca ([209.226.175.87]) by tomts13-srv.bellnexxia.net (InterMail vM.5.01.06.13 201-253-122-130-113-20050324) with ESMTP id <20100420135552.TXEF12176.tomts13-srv.bellnexxia.net@toip4.srvr.bell.ca> for ; Tue, 20 Apr 2010 09:55:52 -0400 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAKVOzUtGGNqG/2dsb2JhbACcAXK9S4UPBIZP Received: from bas6-montreal19-1176033926.dsl.bell.ca (HELO krystal.dyndns.org) ([70.24.218.134]) by toip4.srvr.bell.ca with ESMTP; 20 Apr 2010 10:10:28 -0400 Received: from localhost (localhost [127.0.0.1]) (uid 1000) by krystal.dyndns.org with local; Tue, 20 Apr 2010 09:55:48 -0400 id 001B6594.4BCDB264.00007205 Date: Tue, 20 Apr 2010 09:55:48 -0400 From: Mathieu Desnoyers To: David Daney Cc: ltt-dev@lists.casi.polymtl.ca, linux-mips@linux-mips.org Subject: Re: [ltt-dev] [PATCH 1/3] lttng: MIPS: Fix syscall entry tracing. Message-ID: <20100420135548.GA25175@Krystal> References: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> <1271722791-27885-2-git-send-email-ddaney@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Disposition: inline In-Reply-To: <1271722791-27885-2-git-send-email-ddaney@caviumnetworks.com> X-Editor: vi X-Info: http://krystal.dyndns.org:8080 X-Operating-System: Linux/2.6.27.31-grsec (i686) X-Uptime: 09:55:31 up 12 days, 23:49, 3 users, load average: 0.37, 0.26, 0.20 User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26438 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: compudj@krystal.dyndns.org Precedence: bulk X-list: linux-mips * David Daney (ddaney@caviumnetworks.com) wrote: > For the 32-bit kernel and all three ABIs of the 64-bit kernel, we need > to test the _TIF_KERNEL_TRACE flag on syscall entry. Otherwise, no > syscall entry tracing for you! Merged into the LTTng tree, thanks ! Mathieu > > Signed-off-by: David Daney > --- > arch/mips/kernel/scall32-o32.S | 2 +- > arch/mips/kernel/scall64-64.S | 2 +- > arch/mips/kernel/scall64-n32.S | 2 +- > arch/mips/kernel/scall64-o32.S | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S > index fd2a9bb..28f262d 100644 > --- a/arch/mips/kernel/scall32-o32.S > +++ b/arch/mips/kernel/scall32-o32.S > @@ -52,7 +52,7 @@ NESTED(handle_sys, PT_SIZE, sp) > > stack_done: > lw t0, TI_FLAGS($28) # syscall tracing enabled? > - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT > + li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_KERNEL_TRACE > and t0, t1 > bnez t0, syscall_trace_entry # -> yes > > diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S > index 18bf7f3..38c0c95 100644 > --- a/arch/mips/kernel/scall64-64.S > +++ b/arch/mips/kernel/scall64-64.S > @@ -54,7 +54,7 @@ NESTED(handle_sys64, PT_SIZE, sp) > > sd a3, PT_R26(sp) # save a3 for syscall restarting > > - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT > + li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_KERNEL_TRACE > LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? > and t0, t1, t0 > bnez t0, syscall_trace_entry > diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S > index 3541fd3..fbecc01 100644 > --- a/arch/mips/kernel/scall64-n32.S > +++ b/arch/mips/kernel/scall64-n32.S > @@ -53,7 +53,7 @@ NESTED(handle_sysn32, PT_SIZE, sp) > > sd a3, PT_R26(sp) # save a3 for syscall restarting > > - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT > + li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_KERNEL_TRACE > LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? > and t0, t1, t0 > bnez t0, n32_syscall_trace_entry > diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S > index 14dde4c..0db5589 100644 > --- a/arch/mips/kernel/scall64-o32.S > +++ b/arch/mips/kernel/scall64-o32.S > @@ -81,7 +81,7 @@ NESTED(handle_sys, PT_SIZE, sp) > PTR 4b, bad_stack > .previous > > - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT > + li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_KERNEL_TRACE > LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? > and t0, t1, t0 > bnez t0, trace_a_syscall > -- > 1.6.6.1 > > > _______________________________________________ > ltt-dev mailing list > ltt-dev@lists.casi.polymtl.ca > http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev > -- Mathieu Desnoyers Operating System Efficiency R&D Consultant EfficiOS Inc. http://www.efficios.com From compudj@krystal.dyndns.org Tue Apr 20 15:56:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 15:56:43 +0200 (CEST) Received: from tomts10.bellnexxia.net ([209.226.175.54]:33211 "EHLO tomts10-srv.bellnexxia.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492772Ab0DTN4i (ORCPT ); Tue, 20 Apr 2010 15:56:38 +0200 Received: from toip4.srvr.bell.ca ([209.226.175.87]) by tomts10-srv.bellnexxia.net (InterMail vM.5.01.06.13 201-253-122-130-113-20050324) with ESMTP id <20100420135610.SPKJ307.tomts10-srv.bellnexxia.net@toip4.srvr.bell.ca> for ; Tue, 20 Apr 2010 09:56:10 -0400 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAKVOzUtGGNqG/2dsb2JhbACcAXK9S4UPBIZP Received: from bas6-montreal19-1176033926.dsl.bell.ca (HELO krystal.dyndns.org) ([70.24.218.134]) by toip4.srvr.bell.ca with ESMTP; 20 Apr 2010 10:10:47 -0400 Received: from localhost (localhost [127.0.0.1]) (uid 1000) by krystal.dyndns.org with local; Tue, 20 Apr 2010 09:56:08 -0400 id 001B6594.4BCDB278.0000723C Date: Tue, 20 Apr 2010 09:56:08 -0400 From: Mathieu Desnoyers To: David Daney Cc: ltt-dev@lists.casi.polymtl.ca, linux-mips@linux-mips.org Subject: Re: [ltt-dev] [PATCH 2/3] lttng: MIPS: Dump MIPS system call tables. Message-ID: <20100420135608.GB25175@Krystal> References: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> <1271722791-27885-3-git-send-email-ddaney@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Disposition: inline In-Reply-To: <1271722791-27885-3-git-send-email-ddaney@caviumnetworks.com> X-Editor: vi X-Info: http://krystal.dyndns.org:8080 X-Operating-System: Linux/2.6.27.31-grsec (i686) X-Uptime: 09:55:51 up 12 days, 23:49, 3 users, load average: 0.37, 0.27, 0.20 User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26439 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: compudj@krystal.dyndns.org Precedence: bulk X-list: linux-mips * David Daney (ddaney@caviumnetworks.com) wrote: > The 64-bit kernel may support all three ABIs, so we iterate the > sys_call_tables of all of enabled ABIs. Merged into the LTTng tree, with some coding style cleanups. Thanks! Mathieu > > Signed-off-by: David Daney > --- > arch/mips/Kconfig | 1 + > arch/mips/kernel/scall64-64.S | 3 +- > arch/mips/kernel/scall64-n32.S | 2 + > arch/mips/kernel/scall64-o32.S | 8 +++--- > arch/mips/kernel/syscall.c | 58 ++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 67 insertions(+), 5 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 5e1133f..a690e9b 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -8,6 +8,7 @@ config MIPS > # Horrible source of confusion. Die, die, die ... > select EMBEDDED > select RTC_LIB if !LEMOTE_FULOONG2E > + select HAVE_LTT_DUMP_TABLES > > mainmenu "Linux/MIPS Kernel Configuration" > > diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S > index 38c0c95..f437a01 100644 > --- a/arch/mips/kernel/scall64-64.S > +++ b/arch/mips/kernel/scall64-64.S > @@ -125,7 +125,8 @@ illegal_syscall: > END(handle_sys64) > > .align 3 > -sys_call_table: > + .type sys_call_table,@object > +EXPORT(sys_call_table) > PTR sys_read /* 5000 */ > PTR sys_write > PTR sys_open > diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S > index fbecc01..49ab15a 100644 > --- a/arch/mips/kernel/scall64-n32.S > +++ b/arch/mips/kernel/scall64-n32.S > @@ -119,6 +119,8 @@ not_n32_scall: > > END(handle_sysn32) > > + .align 3 > + .type sysn32_call_table,@object > EXPORT(sysn32_call_table) > PTR sys_read /* 6000 */ > PTR sys_write > diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S > index 0db5589..01500cb 100644 > --- a/arch/mips/kernel/scall64-o32.S > +++ b/arch/mips/kernel/scall64-o32.S > @@ -53,7 +53,7 @@ NESTED(handle_sys, PT_SIZE, sp) > sll a3, a3, 0 > > dsll t0, v0, 3 # offset into table > - ld t2, (sys_call_table - (__NR_O32_Linux * 8))(t0) > + ld t2, (syso32_call_table - (__NR_O32_Linux * 8))(t0) > > sd a3, PT_R26(sp) # save a3 for syscall restarting > > @@ -179,7 +179,7 @@ LEAF(sys32_syscall) > beqz t0, einval # do not recurse > dsll t1, t0, 3 > beqz v0, einval > - ld t2, sys_call_table(t1) # syscall routine > + ld t2, syso32_call_table(t1) # syscall routine > > move a0, a1 # shift argument registers > move a1, a2 > @@ -201,8 +201,8 @@ einval: li v0, -ENOSYS > END(sys32_syscall) > > .align 3 > - .type sys_call_table,@object > -sys_call_table: > + .type syso32_call_table,@object > +EXPORT(syso32_call_table) > PTR sys32_syscall /* 4000 */ > PTR sys_exit > PTR sys_fork > diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c > index 1452e2f..996ef29 100644 > --- a/arch/mips/kernel/syscall.c > +++ b/arch/mips/kernel/syscall.c > @@ -29,6 +29,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -560,3 +561,60 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[]) > > return -__v0; > } > + > +void ltt_dump_sys_call_table(void *call_data) > +{ > + int i; > + char namebuf[KSYM_NAME_LEN]; > + > +#ifdef CONFIG_32BIT > + extern struct { > + unsigned long ptr; > + long j; > + } sys_call_table[]; > + for (i = 0; i < __NR_O32_Linux_syscalls; i++) { > + sprint_symbol(namebuf, sys_call_table[i].ptr); > + __trace_mark(0, syscall_state, sys_call_table, call_data, > + "id %d address %p symbol %s", > + i + __NR_O32_Linux, (void*)sys_call_table[i].ptr, namebuf); > + } > +#endif > +#ifdef CONFIG_64BIT > +# ifdef CONFIG_MIPS32_O32 > + for (i = 0; i < __NR_O32_Linux_syscalls; i++) { > + extern unsigned long syso32_call_table[]; > + sprint_symbol(namebuf, syso32_call_table[i]); > + __trace_mark(0, syscall_state, sys_call_table, call_data, > + "id %d address %p symbol %s", > + i + __NR_O32_Linux, (void*)syso32_call_table[i], namebuf); > + } > +# endif > + > + for (i = 0; i < __NR_64_Linux_syscalls; i++) { > + extern unsigned long sys_call_table[]; > + sprint_symbol(namebuf, sys_call_table[i]); > + __trace_mark(0, syscall_state, sys_call_table, call_data, > + "id %d address %p symbol %s", > + i + __NR_64_Linux, (void*)sys_call_table[i], namebuf); > + } > + > +# ifdef CONFIG_MIPS32_N32 > + for (i = 0; i < __NR_N32_Linux_syscalls; i++) { > + extern unsigned long sysn32_call_table[]; > + sprint_symbol(namebuf, sysn32_call_table[i]); > + __trace_mark(0, syscall_state, sys_call_table, call_data, > + "id %d address %p symbol %s", > + i + __NR_N32_Linux, (void*)sysn32_call_table[i], namebuf); > + } > +# endif > +#endif > + > +} > +EXPORT_SYMBOL_GPL(ltt_dump_sys_call_table); > + > +void ltt_dump_idt_table(void *call_data) > +{ > + /* No IDT information yet. */ > + return; > +} > +EXPORT_SYMBOL_GPL(ltt_dump_idt_table); > -- > 1.6.6.1 > > > _______________________________________________ > ltt-dev mailing list > ltt-dev@lists.casi.polymtl.ca > http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev > -- Mathieu Desnoyers Operating System Efficiency R&D Consultant EfficiOS Inc. http://www.efficios.com From compudj@krystal.dyndns.org Tue Apr 20 15:57:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 15:57:17 +0200 (CEST) Received: from tomts20.bellnexxia.net ([209.226.175.74]:43257 "EHLO tomts20-srv.bellnexxia.net" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492772Ab0DTN5J (ORCPT ); Tue, 20 Apr 2010 15:57:09 +0200 Received: from toip4.srvr.bell.ca ([209.226.175.87]) by tomts20-srv.bellnexxia.net (InterMail vM.5.01.06.13 201-253-122-130-113-20050324) with ESMTP id <20100420135704.HYQQ3465.tomts20-srv.bellnexxia.net@toip4.srvr.bell.ca> for ; Tue, 20 Apr 2010 09:57:04 -0400 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAKVOzUtGGNqG/2dsb2JhbACcAXK9S4UPBIZP Received: from bas6-montreal19-1176033926.dsl.bell.ca (HELO krystal.dyndns.org) ([70.24.218.134]) by toip4.srvr.bell.ca with ESMTP; 20 Apr 2010 10:11:40 -0400 Received: from localhost (localhost [127.0.0.1]) (uid 1000) by krystal.dyndns.org with local; Tue, 20 Apr 2010 09:56:59 -0400 id 001B6594.4BCDB2AB.0000727D Date: Tue, 20 Apr 2010 09:56:59 -0400 From: Mathieu Desnoyers To: David Daney Cc: ltt-dev@lists.casi.polymtl.ca, linux-mips@linux-mips.org Subject: Re: [ltt-dev] [PATCH 3/3] lttng: MIPS: Use 64 bit counter for trace clock on Octeon CPUs. Message-ID: <20100420135659.GC25175@Krystal> References: <1271722791-27885-1-git-send-email-ddaney@caviumnetworks.com> <1271722791-27885-4-git-send-email-ddaney@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Disposition: inline In-Reply-To: <1271722791-27885-4-git-send-email-ddaney@caviumnetworks.com> X-Editor: vi X-Info: http://krystal.dyndns.org:8080 X-Operating-System: Linux/2.6.27.31-grsec (i686) X-Uptime: 09:56:10 up 12 days, 23:49, 3 users, load average: 0.33, 0.27, 0.20 User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26440 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: compudj@krystal.dyndns.org Precedence: bulk X-list: linux-mips * David Daney (ddaney@caviumnetworks.com) wrote: > Cavium Octeon CPUs have a 64-bit cycle counter that is synchronized > when the CPUs are brought on-line. So for this case we don't need any > fancy stuff. Merged into the LTTng tree, with refactoring of the Octeon-specific header file code into a new arch/mips/include/asm/octeon/trace-clock.h file. Thanks! Mathieu > > Signed-off-by: David Daney > --- > arch/mips/Kconfig | 4 +- > arch/mips/include/asm/trace-clock.h | 39 ++++++++++++++++++++++++++++++++++- > arch/mips/kernel/smp.c | 2 + > 3 files changed, 42 insertions(+), 3 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index a690e9b..9e91e8c 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1782,8 +1782,8 @@ config HAVE_GET_CYCLES_32 > def_bool y > depends on !CPU_R4400_WORKAROUNDS > select HAVE_TRACE_CLOCK > - select HAVE_TRACE_CLOCK_32_TO_64 > - select HAVE_UNSYNCHRONIZED_TSC > + select HAVE_TRACE_CLOCK_32_TO_64 if (!CPU_CAVIUM_OCTEON) > + select HAVE_UNSYNCHRONIZED_TSC if (!CPU_CAVIUM_OCTEON) > > # > # Use the generic interrupt handling code in kernel/irq/: > diff --git a/arch/mips/include/asm/trace-clock.h b/arch/mips/include/asm/trace-clock.h > index 3d8cb0f..a052f42 100644 > --- a/arch/mips/include/asm/trace-clock.h > +++ b/arch/mips/include/asm/trace-clock.h > @@ -12,6 +12,43 @@ > > #define TRACE_CLOCK_MIN_PROBE_DURATION 200 > > +#ifdef CONFIG_CPU_CAVIUM_OCTEON > + > +#include > + > +#define TC_HW_BITS 64 > + > +static inline u32 trace_clock_read32(void) > +{ > + return (u32)read_c0_cvmcount(); /* only need the 32 LSB */ > +} > + > +static inline u64 trace_clock_read64(void) > +{ > + return read_c0_cvmcount(); > +} > + > +static inline u64 trace_clock_frequency(void) > +{ > + return octeon_get_clock_rate(); > +} > + > +static inline u32 trace_clock_freq_scale(void) > +{ > + return 1; > +} > + > +static inline void get_trace_clock(void) > +{ > + return; > +} > + > +static inline void put_trace_clock(void) > +{ > + return; > +} > + > +#else /* !CONFIG_CPU_CAVIUM_OCTEON */ > /* > * Number of hardware clock bits. The higher order bits are expected to be 0. > * If the hardware clock source has more than 32 bits, the bits higher than the > @@ -65,7 +102,7 @@ static inline void put_trace_clock(void) > { > put_synthetic_tsc(); > } > - > +#endif /* CONFIG_CPU_CAVIUM_OCTEON */ > static inline void set_trace_clock_is_sync(int state) > { > } > diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c > index f8c50d1..42083eb 100644 > --- a/arch/mips/kernel/smp.c > +++ b/arch/mips/kernel/smp.c > @@ -159,7 +159,9 @@ void __init smp_cpus_done(unsigned int max_cpus) > { > mp_ops->cpus_done(); > synchronise_count_master(); > +#ifdef CONFIG_HAVE_UNSYNCHRONIZED_TSC > test_tsc_synchronization(); > +#endif > } > > /* called from main before smp_init() */ > -- > 1.6.6.1 > > > _______________________________________________ > ltt-dev mailing list > ltt-dev@lists.casi.polymtl.ca > http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev > -- Mathieu Desnoyers Operating System Efficiency R&D Consultant EfficiOS Inc. http://www.efficios.com From David.Daney@caviumnetworks.com Tue Apr 20 18:26:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Apr 2010 18:26:27 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15451 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492407Ab0DTQ0X (ORCPT ); Tue, 20 Apr 2010 18:26:23 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 20 Apr 2010 09:26:33 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 20 Apr 2010 09:25:56 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 20 Apr 2010 09:25:56 -0700 Message-ID: <4BCDD58F.7020201@caviumnetworks.com> Date: Tue, 20 Apr 2010 09:25:51 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Deng-Cheng Zhu CC: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Subject: Re: [PATCH 1/3] MIPS: use the generic atomic64 operations for perf counter support References: <1271349525.7467.420.camel@fun-lab> In-Reply-To: <1271349525.7467.420.camel@fun-lab> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 20 Apr 2010 16:25:56.0828 (UTC) FILETIME=[27AC59C0:01CAE0A6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26441 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/15/2010 09:38 AM, Deng-Cheng Zhu wrote: > Currently we take the generic spinlock'ed atomic64 implementation from the > lib. The atomic64 types and related functions are needed for the Linux > performance counter subsystem. > > Signed-off-by: Deng-Cheng Zhu NAK. > --- > arch/mips/Kconfig | 1 + > arch/mips/include/asm/atomic.h | 4 ++++ > 2 files changed, 5 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 29e8692..7161751 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -4,6 +4,7 @@ config MIPS > select HAVE_GENERIC_DMA_COHERENT > select HAVE_IDE > select HAVE_OPROFILE > + select GENERIC_ATOMIC64 > select HAVE_ARCH_KGDB > select HAVE_FUNCTION_TRACER > select HAVE_FUNCTION_TRACE_MCOUNT_TEST > diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h > index 519197e..b0a932e 100644 > --- a/arch/mips/include/asm/atomic.h > +++ b/arch/mips/include/asm/atomic.h > @@ -21,6 +21,10 @@ > #include > #include > > +#ifdef CONFIG_GENERIC_ATOMIC64 > +#include > +#endif > + > #define ATOMIC_INIT(i) { (i) } > > /* This is incorrect. For 64-bit kernels, we already have all the 64-bit atomics implemented. This will break 64-bit kernels. David Daney From manuel.lauss@googlemail.com Wed Apr 21 17:42:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Apr 2010 17:42:14 +0200 (CEST) Received: from mail-ew0-f211.google.com ([209.85.219.211]:39489 "EHLO mail-ew0-f211.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492149Ab0DUPmJ (ORCPT ); Wed, 21 Apr 2010 17:42:09 +0200 Received: by ewy3 with SMTP id 3so83071ewy.26 for ; Wed, 21 Apr 2010 08:42:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=nz1H8OAAWSk+gU3jL+IfKrtjoc/gxEumUZSKB7EdA+k=; b=opoqPYU+5PPoBMFi6Pj8qPNmGQ5Dwls9MNqcnkliESXX3hjCVb/hFn3xEaFv/EIu6o 3hsDn03LVA4q3qoenOBnlVjt1Mm+ETCxB447LSoNZ66phwCxRZPyilh0awWSMnfg0TrF fTOiiA159QwAdXwLpugtYcEbWP/C7PDEwhsYg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=lDeTfAUChBW5v3Ii1uOp9cIOwa9jVZ4TltrU1u69tl+tiXCDOk7tbImGDBEO0fO6L1 9kLxmj/Baj7Gfa0iBuO6i+AaqgvPrsc4wSUaPZRX+i78rZI3oXgoAxj4X6bm/5ne+GM6 Eqa3KN+p2fE93SiBd+84K5KsgyXSZarjEczbA= Received: by 10.103.81.39 with SMTP id i39mr1466116mul.28.1271864523699; Wed, 21 Apr 2010 08:42:03 -0700 (PDT) Received: from localhost.localdomain (p5496D614.dip.t-dialin.net [84.150.214.20]) by mx.google.com with ESMTPS id j10sm3341751mue.18.2010.04.21.08.42.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 21 Apr 2010 08:42:02 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH v3] MIPS: Alchemy: db1200: PCMCIA carddetects must not be auto-enabled. Date: Wed, 21 Apr 2010 17:41:59 +0200 Message-Id: <1271864519-4516-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26442 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Same issues as SD carddetects: One of both is always triggering and the handlers take care to shut it up and enable the other. To avoid messages about "unbalanced interrupt enable/disable" they must not be automatically enabled when initally requested. This was not an issue with the db1200_defconfig due to fortunate timings; on a build without network chip support the warnings appear. Signed-off-by: Manuel Lauss --- v3: rebase on top of latest linus git (db1xxx_ss.c changed). v2: remove the now unnecessary locks in the socket driver irq setup code. Please apply to 2.6.34-rc if still possible! arch/mips/alchemy/devboards/db1200/setup.c | 10 +++++++--- drivers/pcmcia/db1xxx_ss.c | 16 ++++------------ 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index be7e92e..8876195 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -66,12 +66,16 @@ static int __init db1200_arch_init(void) set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); - /* do not autoenable these: CPLD has broken edge int handling, - * and the CD handler setup requires manual enabling to work - * around that. + /* insert/eject pairs: one of both is always screaming. To avoid + * issues they must not be automatically enabled when initially + * requested. */ irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN; return 0; } diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c index 2d48196..0f4cc3f 100644 --- a/drivers/pcmcia/db1xxx_ss.c +++ b/drivers/pcmcia/db1xxx_ss.c @@ -146,7 +146,6 @@ static irqreturn_t db1200_pcmcia_cdirq(int irq, void *data) static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) { int ret; - unsigned long flags; if (sock->stschg_irq != -1) { ret = request_irq(sock->stschg_irq, db1000_pcmcia_stschgirq, @@ -162,30 +161,23 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) * active one disabled. */ if (sock->board_type == BOARD_TYPE_DB1200) { - local_irq_save(flags); - ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq, IRQF_DISABLED, "pcmcia_insert", sock); - if (ret) { - local_irq_restore(flags); + if (ret) goto out1; - } ret = request_irq(sock->eject_irq, db1200_pcmcia_cdirq, IRQF_DISABLED, "pcmcia_eject", sock); if (ret) { free_irq(sock->insert_irq, sock); - local_irq_restore(flags); goto out1; } - /* disable the currently active one */ + /* enable the currently silent one */ if (db1200_card_inserted(sock)) - disable_irq_nosync(sock->insert_irq); + enable_irq(sock->eject_irq); else - disable_irq_nosync(sock->eject_irq); - - local_irq_restore(flags); + enable_irq(sock->insert_irq); } else { /* all other (older) Db1x00 boards use a GPIO to show * card detection status: use both-edge triggers. -- 1.7.0.4 From groeck@ericsson.com Wed Apr 21 19:10:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Apr 2010 19:10:52 +0200 (CEST) Received: from imr1.ericy.com ([198.24.6.9]:46475 "EHLO imr1.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492176Ab0DURKs (ORCPT ); Wed, 21 Apr 2010 19:10:48 +0200 Received: from eusaamw0707.eamcs.ericsson.se ([147.117.20.32]) by imr1.ericy.com (8.13.1/8.13.1) with ESMTP id o3LHFHai012575 for ; Wed, 21 Apr 2010 12:15:21 -0500 Received: from localhost (147.117.20.212) by eusaamw0707.eamcs.ericsson.se (147.117.20.92) with Microsoft SMTP Server id 8.1.375.2; Wed, 21 Apr 2010 13:10:36 -0400 Date: Wed, 21 Apr 2010 10:12:34 -0700 From: Guenter Roeck To: linux-mips@linux-mips.org Subject: PCMCIA/IDE driver for sibyte chips in 2.6 Message-ID: <20100421171234.GA11658@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26443 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Hi all, does anyone know if there is a PCMCIA/IDE driver for sibyte chips in the 2.6 kernel ? I did find drivers for 2.4, but not for 2.6. Thanks, Guenter From ralf@linux-mips.org Wed Apr 21 19:19:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Apr 2010 19:19:43 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41507 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S32854Ab0DURTh (ORCPT ); Wed, 21 Apr 2010 19:19:37 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3LHJJMC029499; Wed, 21 Apr 2010 18:19:19 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3LHJGMm029491; Wed, 21 Apr 2010 18:19:16 +0100 Date: Wed, 21 Apr 2010 18:19:15 +0100 From: Ralf Baechle To: David Daney Cc: Deng-Cheng Zhu , linux-mips@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Subject: Re: [PATCH 1/3] MIPS: use the generic atomic64 operations for perf counter support Message-ID: <20100421171915.GA29010@linux-mips.org> References: <1271349525.7467.420.camel@fun-lab> <4BCDD58F.7020201@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4BCDD58F.7020201@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26444 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 20, 2010 at 09:25:51AM -0700, David Daney wrote: > >Signed-off-by: Deng-Cheng Zhu > > NAK. > >+#ifdef CONFIG_GENERIC_ATOMIC64 > >+#include > >+#endif > >+ > > #define ATOMIC_INIT(i) { (i) } > > > > /* > > This is incorrect. For 64-bit kernels, we already have all the > 64-bit atomics implemented. This will break 64-bit kernels. Here's an alternative patch. Much larger but should take make the atomic64 functions fully usable on 32-bit kernels. Some additional optimizations for 64-bit hardware running 32-bit kernels would be possible but why bother. Ralf MIPS: Make atomic64 functions usable on 32-bit kernels. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 519197e..5f00bbc 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -15,11 +15,13 @@ #define _ASM_ATOMIC_H #include +#include #include #include +#include #include +#include #include -#include #define ATOMIC_INIT(i) { (i) } @@ -401,7 +403,9 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) */ #define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0) -#ifdef CONFIG_64BIT +typedef struct { + long long counter; +} atomic64_t; #define ATOMIC64_INIT(i) { (i) } @@ -410,14 +414,44 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * @v: pointer of type atomic64_t * */ -#define atomic64_read(v) ((v)->counter) +static long long __inline__ atomic64_read(const atomic64_t *v) +{ + unsigned long flags; + raw_spinlock_t *lock; + long long val; + + if (cpu_has_64bit_gp_regs) /* 64-bit regs imply 64-bit ld / sd */ + return v->counter; + + lock = atomic_lock_addr(v); + raw_spin_lock_irqsave(lock, flags); + val = v->counter; + raw_spin_unlock_irqrestore(lock, flags); + + return val; +} /* * atomic64_set - set atomic variable * @v: pointer of type atomic64_t * @i: required value */ -#define atomic64_set(v, i) ((v)->counter = (i)) +static void __inline__ atomic64_set(atomic64_t *v, long long i) +{ + unsigned long flags; + raw_spinlock_t *lock; + + if (cpu_has_64bit_gp_regs) { /* 64-bit regs imply 64-bit ld / sd */ + v->counter = i; + + return; + } + + lock = atomic_lock_addr(v); + raw_spin_lock_irqsave(lock, flags); + v->counter = i; + raw_spin_unlock_irqrestore(lock, flags); +} /* * atomic64_add - add integer to atomic variable @@ -428,7 +462,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) */ static __inline__ void atomic64_add(long i, atomic64_t * v) { - if (kernel_uses_llsc && R10000_LLSC_WAR) { + if (kernel_uses_llsc && cpu_has_64bit_gp_regs && R10000_LLSC_WAR) { long temp; __asm__ __volatile__( @@ -440,7 +474,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); - } else if (kernel_uses_llsc) { + } else if (kernel_uses_llsc && cpu_has_64bit_gp_regs) { long temp; __asm__ __volatile__( @@ -456,11 +490,12 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { + raw_spinlock_t *lock = atomic_lock_addr(v); unsigned long flags; - raw_local_irq_save(flags); + raw_spin_lock_irqsave(lock, flags); v->counter += i; - raw_local_irq_restore(flags); + raw_spin_unlock_irqrestore(lock, flags); } } @@ -473,7 +508,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) */ static __inline__ void atomic64_sub(long i, atomic64_t * v) { - if (kernel_uses_llsc && R10000_LLSC_WAR) { + if (kernel_uses_llsc && cpu_has_64bit_gp_regs && R10000_LLSC_WAR) { long temp; __asm__ __volatile__( @@ -485,7 +520,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); - } else if (kernel_uses_llsc) { + } else if (kernel_uses_llsc && cpu_has_64bit_gp_regs) { long temp; __asm__ __volatile__( @@ -501,11 +536,12 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { + raw_spinlock_t *lock = atomic_lock_addr(v); unsigned long flags; - raw_local_irq_save(flags); + raw_spin_lock_irqsave(lock, flags); v->counter -= i; - raw_local_irq_restore(flags); + raw_spin_unlock_irqrestore(lock, flags); } } @@ -518,7 +554,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) smp_mb__before_llsc(); - if (kernel_uses_llsc && R10000_LLSC_WAR) { + if (kernel_uses_llsc && cpu_has_64bit_gp_regs && R10000_LLSC_WAR) { long temp; __asm__ __volatile__( @@ -532,7 +568,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); - } else if (kernel_uses_llsc) { + } else if (kernel_uses_llsc && cpu_has_64bit_gp_regs) { long temp; __asm__ __volatile__( @@ -550,13 +586,14 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else { + raw_spinlock_t *lock = atomic_lock_addr(v); unsigned long flags; - raw_local_irq_save(flags); + raw_spin_lock_irqsave(lock, flags); result = v->counter; result += i; v->counter = result; - raw_local_irq_restore(flags); + raw_spin_unlock_irqrestore(lock, flags); } smp_llsc_mb(); @@ -570,7 +607,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) smp_mb__before_llsc(); - if (kernel_uses_llsc && R10000_LLSC_WAR) { + if (kernel_uses_llsc && cpu_has_64bit_gp_regs && R10000_LLSC_WAR) { long temp; __asm__ __volatile__( @@ -584,7 +621,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); - } else if (kernel_uses_llsc) { + } else if (kernel_uses_llsc && cpu_has_64bit_gp_regs) { long temp; __asm__ __volatile__( @@ -602,13 +639,14 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else { + raw_spinlock_t *lock = atomic_lock_addr(v); unsigned long flags; - raw_local_irq_save(flags); + raw_spin_lock_irqsave(lock, flags); result = v->counter; result -= i; v->counter = result; - raw_local_irq_restore(flags); + raw_spin_unlock_irqrestore(lock, flags); } smp_llsc_mb(); @@ -630,7 +668,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) smp_mb__before_llsc(); - if (kernel_uses_llsc && R10000_LLSC_WAR) { + if (kernel_uses_llsc && cpu_has_64bit_gp_regs && R10000_LLSC_WAR) { long temp; __asm__ __volatile__( @@ -648,7 +686,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); - } else if (kernel_uses_llsc) { + } else if (kernel_uses_llsc && cpu_has_64bit_gp_regs) { long temp; __asm__ __volatile__( @@ -670,14 +708,15 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else { + raw_spinlock_t *lock = atomic_lock_addr(v); unsigned long flags; - raw_local_irq_save(flags); + raw_spin_lock_irqsave(lock, flags); result = v->counter; result -= i; if (result >= 0) v->counter = result; - raw_local_irq_restore(flags); + raw_spin_unlock_irqrestore(lock, flags); } smp_llsc_mb(); @@ -782,8 +821,6 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) */ #define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0) -#endif /* CONFIG_64BIT */ - /* * atomic*_return operations are serializing but not the non-*_return * versions. diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index 2d28017..7ed77bd 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -9,6 +9,8 @@ #define __ASM_CMPXCHG_H #include +#include +#include #define __HAVE_ARCH_CMPXCHG 1 @@ -53,16 +55,8 @@ : "=&r" (__ret), "=R" (*m) \ : "R" (*m), "Jr" (old), "Jr" (new) \ : "memory"); \ - } else { \ - unsigned long __flags; \ - \ - raw_local_irq_save(__flags); \ - __ret = *m; \ - if (__ret == old) \ - *m = new; \ - raw_local_irq_restore(__flags); \ - } \ - \ + } else \ + BUG(); \ __ret; \ }) @@ -78,19 +72,42 @@ extern void __cmpxchg_called_with_bad_pointer(void); __typeof__(*(ptr)) __old = (old); \ __typeof__(*(ptr)) __new = (new); \ __typeof__(*(ptr)) __res = 0; \ + unsigned long __flags; \ + raw_spinlock_t *lock; \ \ pre_barrier; \ \ switch (sizeof(*(__ptr))) { \ case 4: \ - __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \ + if (kernel_uses_llsc) { \ + __res = __cmpxchg_asm("ll", "sc", __ptr, __old, \ + __new); \ + break; \ + } \ + \ + lock = atomic_lock_addr(__ptr); \ + raw_spin_lock_irqsave(lock, __flags); \ + __res = *__ptr; \ + if (__res == __old) \ + *__ptr = __new; \ + raw_spin_unlock_irqrestore(lock, __flags); \ break; \ + \ case 8: \ - if (sizeof(long) == 8) { \ + if (kernel_uses_llsc && cpu_has_64bit_gp_regs) { \ __res = __cmpxchg_asm("lld", "scd", __ptr, \ - __old, __new); \ + __old, __new); \ break; \ } \ + \ + lock = atomic_lock_addr(__ptr); \ + raw_spin_lock_irqsave(lock, __flags); \ + __res = *__ptr; \ + if (__res == __old) \ + *__ptr = __new; \ + raw_spin_unlock_irqrestore(lock, __flags); \ + break; \ + \ default: \ __cmpxchg_called_with_bad_pointer(); \ break; \ @@ -110,15 +127,10 @@ extern void __cmpxchg_called_with_bad_pointer(void); cmpxchg((ptr), (o), (n)); \ }) -#ifdef CONFIG_64BIT #define cmpxchg64_local(ptr, o, n) \ ({ \ BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ cmpxchg_local((ptr), (o), (n)); \ }) -#else -#include -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) -#endif #endif /* __ASM_CMPXCHG_H */ diff --git a/arch/mips/include/asm/hashed-locks.h b/arch/mips/include/asm/hashed-locks.h new file mode 100644 index 0000000..6d6321c --- /dev/null +++ b/arch/mips/include/asm/hashed-locks.h @@ -0,0 +1,38 @@ +/* + * Hashed locks for when we cannot or do not want to use LL/SC for the + * implementation of atomic operations in atomic.h, cmpxchg.h etc. + */ +#ifndef __ASM_HASHED_LOCKS_H +#define __ASM_HASHED_LOCKS_H + +#include +#include + +/* + * We use a hashed array of spinlocks to provide exclusive access + * to each atomic64_t variable. Since this is expected to used on + * systems with small numbers of CPUs (<= 4 or so), we use a + * relatively small array of 16 spinlocks to avoid wasting too much + * memory on the spinlock array. + */ +#define NR_LOCKS 16 + +/* + * Ensure each lock is in a separate cacheline. + */ +extern union atomic64_lock_union { + raw_spinlock_t lock; + char pad[L1_CACHE_BYTES]; +} __atomic_lock_array[NR_LOCKS]; + +static inline raw_spinlock_t *atomic_lock_addr(volatile const void *v) +{ + unsigned long addr = (unsigned long) v; + + addr >>= L1_CACHE_SHIFT; + addr ^= (addr >> 8) ^ (addr >> 16); + + return &__atomic_lock_array[addr & (NR_LOCKS - 1)].lock; +} + +#endif /* __ASM_HASHED_LOCKS_H */ diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 2adead5..c138aad 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -2,8 +2,8 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \ - strlen_user.o strncpy_user.o strnlen_user.o uncached.o +lib-y += csum_partial.o delay.o hashed-locks.o memcpy.o memcpy-inatomic.o \ + memset.o strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o diff --git a/arch/mips/lib/hashed-locks.c b/arch/mips/lib/hashed-locks.c new file mode 100644 index 0000000..2fbb68a --- /dev/null +++ b/arch/mips/lib/hashed-locks.c @@ -0,0 +1,9 @@ +#include +#include +#include + +union atomic64_lock_union __atomic_lock_array[NR_LOCKS] = { + [0 ... NR_LOCKS - 1] .lock = __ARCH_SPIN_LOCK_UNLOCKED, +} __cacheline_aligned_in_smp; + +EXPORT_SYMBOL(__atomic_lock_array); From David.Daney@caviumnetworks.com Wed Apr 21 19:45:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Apr 2010 19:45:45 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5981 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492207Ab0DURpm (ORCPT ); Wed, 21 Apr 2010 19:45:42 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 21 Apr 2010 10:45:51 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 21 Apr 2010 10:45:17 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 21 Apr 2010 10:45:17 -0700 Message-ID: <4BCF39A7.3020708@caviumnetworks.com> Date: Wed, 21 Apr 2010 10:45:11 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Ralf Baechle CC: Deng-Cheng Zhu , linux-mips@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Subject: Re: [PATCH 1/3] MIPS: use the generic atomic64 operations for perf counter support References: <1271349525.7467.420.camel@fun-lab> <4BCDD58F.7020201@caviumnetworks.com> <20100421171915.GA29010@linux-mips.org> In-Reply-To: <20100421171915.GA29010@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 21 Apr 2010 17:45:17.0614 (UTC) FILETIME=[67BC64E0:01CAE17A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26445 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/21/2010 10:19 AM, Ralf Baechle wrote: [...] > > -#ifdef CONFIG_64BIT > +typedef struct { > + long long counter; > +} atomic64_t; > How does this not conflict with the definition in linux/types.h for a 64-bit kernel? > #define ATOMIC64_INIT(i) { (i) } > > @@ -410,14 +414,44 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) > * @v: pointer of type atomic64_t > * > */ > -#define atomic64_read(v) ((v)->counter) > +static long long __inline__ atomic64_read(const atomic64_t *v) > +{ > + unsigned long flags; > + raw_spinlock_t *lock; > + long long val; > + > + if (cpu_has_64bit_gp_regs) /* 64-bit regs imply 64-bit ld / sd */ > + return v->counter; > + How is this atomic for the o32 ABI? counter is now not volatile, in o32, u64 values are often split between two registers. There is nothing to guarantee that the compiler will use LD. David Daney From sebastian@breakpoint.cc Wed Apr 21 20:55:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Apr 2010 20:55:54 +0200 (CEST) Received: from Chamillionaire.breakpoint.cc ([85.10.199.196]:37800 "EHLO Chamillionaire.breakpoint.cc" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491891Ab0DUSzv (ORCPT ); Wed, 21 Apr 2010 20:55:51 +0200 Received: id: bigeasy by Chamillionaire.breakpoint.cc with local (easymta 1.00 BETA 1) id 1O4f5P-00020f-Ax; Wed, 21 Apr 2010 20:55:47 +0200 Date: Wed, 21 Apr 2010 20:55:47 +0200 From: Sebastian Andrzej Siewior To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [RFC] mips/swarm: fixup screen_info struct Message-ID: <20100421185547.GA7708@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline X-Key-Id: FE3F4706 X-Key-Fingerprint: FFDA BBBB 3563 1B27 75C9 925B 98D5 5C1C FE3F 4706 User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26446 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sebastian@breakpoint.cc Precedence: bulk X-list: linux-mips |arch/mips/sibyte/swarm/setup.c:153: | warning: large integer implicitly truncated to unsigned type The field was changed in d9b26352 aka ("x86, setup: Store the boot cursor state"). This patch changes the values back they way they were before this extra field got introduced. I have no idea who needs it anyway. Signed-off-by: Sebastian Andrzej Siewior --- Using C99 initializer might be better arch/mips/sibyte/swarm/setup.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 5277aac..128b699 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -150,7 +150,7 @@ void __init plat_mem_setup(void) 52, /* orig_video_page */ 3, /* orig_video_mode */ 80, /* orig_video_cols */ - 4626, 3, 9, /* unused, ega_bx, unused */ + 12, 12, 3, 9, /* flags, unused, ega_bx, unused */ 25, /* orig_video_lines */ 0x22, /* orig_video_isVGA */ 16 /* orig_video_points */ -- 1.6.6.1 From sebastian@breakpoint.cc Wed Apr 21 20:57:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Apr 2010 20:57:13 +0200 (CEST) Received: from Chamillionaire.breakpoint.cc ([85.10.199.196]:34120 "EHLO Chamillionaire.breakpoint.cc" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491891Ab0DUS5J (ORCPT ); Wed, 21 Apr 2010 20:57:09 +0200 Received: id: bigeasy by Chamillionaire.breakpoint.cc with local (easymta 1.00 BETA 1) id 1O4f6i-00020o-Jq; Wed, 21 Apr 2010 20:57:08 +0200 Date: Wed, 21 Apr 2010 20:57:08 +0200 From: Sebastian Andrzej Siewior To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [PATCH] mips/sb1250: include correct header, remove a warning Message-ID: <20100421185708.GB7708@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline X-Key-Id: FE3F4706 X-Key-Fingerprint: FFDA BBBB 3563 1B27 75C9 925B 98D5 5C1C FE3F 4706 User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26447 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sebastian@breakpoint.cc Precedence: bulk X-list: linux-mips | arch/mips/pci/pci-sb1250.c: In function sb1250_pcibios_init: | arch/mips/pci/pci-sb1250.c:257: warning: assignment makes integer from pointer without a cast | arch/mips/pci/pci-sb1250.c:285: error: MAX_NR_CONSOLES undeclared (first use in this function) | arch/mips/pci/pci-sb1250.c:285: error: (Each undeclared identifier is reported only once | arch/mips/pci/pci-sb1250.c:285: error: for each function it appears in.) Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/pci/pci-sb1250.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index ada24e6..1711e8e 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -37,6 +37,7 @@ #include #include #include +#include #include @@ -254,7 +255,7 @@ static int __init sb1250_pcibios_init(void) * XXX ehs: Should this happen in PCI Device mode? */ io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024); - sb1250_controller.io_map_base = io_map_base; + sb1250_controller.io_map_base = (unsigned long)io_map_base; set_io_port_base((unsigned long)io_map_base); #ifdef CONFIG_SIBYTE_HAS_LDT -- 1.6.6.1 From sebastian@breakpoint.cc Wed Apr 21 22:36:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Apr 2010 22:36:52 +0200 (CEST) Received: from Chamillionaire.breakpoint.cc ([85.10.199.196]:56218 "EHLO Chamillionaire.breakpoint.cc" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492964Ab0DUUgt (ORCPT ); Wed, 21 Apr 2010 22:36:49 +0200 Received: id: bigeasy by Chamillionaire.breakpoint.cc with local (easymta 1.00 BETA 1) id 1O4gfA-0002DC-0B; Wed, 21 Apr 2010 22:36:48 +0200 Date: Wed, 21 Apr 2010 22:36:47 +0200 From: Sebastian Andrzej Siewior To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [PATCH v2] mips/swarm: fixup screen_info struct Message-ID: <20100421203647.GC7708@Chamillionaire.breakpoint.cc> References: <20100421185547.GA7708@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <20100421185547.GA7708@Chamillionaire.breakpoint.cc> X-Key-Id: FE3F4706 X-Key-Fingerprint: FFDA BBBB 3563 1B27 75C9 925B 98D5 5C1C FE3F 4706 User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26448 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sebastian@breakpoint.cc Precedence: bulk X-list: linux-mips |arch/mips/sibyte/swarm/setup.c:153: | warning: large integer implicitly truncated to unsigned type The field was changed in d9b26352 aka ("x86, setup: Store the boot cursor state"). This patch changes the values back they way they were before this extra field got introduced. While here, the other two boards are also converted to C99 initializer. Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/jazz/setup.c | 12 +++--------- arch/mips/loongson/common/setup.c | 14 +++++--------- arch/mips/sibyte/swarm/setup.c | 19 ++++++++++--------- 3 files changed, 18 insertions(+), 27 deletions(-) diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index 7043f6b..c492563 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -76,15 +76,9 @@ void __init plat_mem_setup(void) #ifdef CONFIG_VT screen_info = (struct screen_info) { - 0, 0, /* orig-x, orig-y */ - 0, /* unused */ - 0, /* orig_video_page */ - 0, /* orig_video_mode */ - 160, /* orig_video_cols */ - 0, 0, 0, /* unused, ega_bx, unused */ - 64, /* orig_video_lines */ - 0, /* orig_video_isVGA */ - 16 /* orig_video_points */ + .orig_video_cols = 160, + .orig_video_lines = 64, + .orig_video_points = 16, }; #endif diff --git a/arch/mips/loongson/common/setup.c b/arch/mips/loongson/common/setup.c index 4cd2aa9..c2e1410 100644 --- a/arch/mips/loongson/common/setup.c +++ b/arch/mips/loongson/common/setup.c @@ -41,15 +41,11 @@ void __init plat_mem_setup(void) conswitchp = &vga_con; screen_info = (struct screen_info) { - 0, 25, /* orig-x, orig-y */ - 0, /* unused */ - 0, /* orig-video-page */ - 0, /* orig-video-mode */ - 80, /* orig-video-cols */ - 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ - 25, /* orig-video-lines */ - VIDEO_TYPE_VGAC, /* orig-video-isVGA */ - 16 /* orig-video-points */ + .orig_y = 25, + .orig_video_cols = 80, + .orig_video_lines = 25, + .orig_video_isVGA = VIDEO_TYPE_VGAC, + .orig_video_points = 16, }; #elif defined(CONFIG_DUMMY_CONSOLE) conswitchp = &dummy_con; diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 5277aac..a3573f3 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -145,15 +145,16 @@ void __init plat_mem_setup(void) #ifdef CONFIG_VT screen_info = (struct screen_info) { - 0, 0, /* orig-x, orig-y */ - 0, /* unused */ - 52, /* orig_video_page */ - 3, /* orig_video_mode */ - 80, /* orig_video_cols */ - 4626, 3, 9, /* unused, ega_bx, unused */ - 25, /* orig_video_lines */ - 0x22, /* orig_video_isVGA */ - 16 /* orig_video_points */ + .orig_video_page = 52, + .orig_video_mode = 3, + .orig_video_cols = 80, + .flags = 12, + .unused2 = 12, + .orig_video_ega_bx = 3, + .unused3 = 9, + .orig_video_lines = 25, + .orig_video_isVGA = 0x22, + .orig_video_points = 16, }; /* XXXKW for CFE, get lines/cols from environment */ #endif -- 1.6.6.1 From dominicwj@gmail.com Thu Apr 22 17:31:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Apr 2010 17:31:51 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:43610 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492338Ab0DVPbo (ORCPT ); Thu, 22 Apr 2010 17:31:44 +0200 Received: by vws3 with SMTP id 3so1913486vws.36 for ; Thu, 22 Apr 2010 08:31:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:content-type; bh=eD7mGdvVc72lOOdPdhssbBSkj92pV6qXDjegyIz6mVA=; b=WyA58wRn1z7ZC3DrqRbn/cb+39kPzwehWORTiT72SgOZUpB3fPnoJqnxX2DH7xGE/E eprMzjxZagUnY0TPbiH0BRJtFgck+aW9r3zrYoxD9DPQ4ZiXhd+EqePFpr/PF2Q/MOkQ GCz82kBILW2C8zXYNc4Qy/b4cCarJcOFxpbbg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type; b=JbMQygmfIUDHJzR32WW52QSCGOf7kSGnf9B1yZjFYdO0Yi/7jrqfxzcGdLu/p463bT wy4Cwu/LAmFxS2JB1HYSNRomoinnZxSNp195AdgEHw3DvwB0BBKatapzLNhW1ZzDFw9R ztTKn907fzClbBoJtVTTGvK/92Ab6LcO1xjaU= MIME-Version: 1.0 Received: by 10.220.17.141 with HTTP; Thu, 22 Apr 2010 08:31:34 -0700 (PDT) In-Reply-To: References: Date: Thu, 22 Apr 2010 23:31:34 +0800 Received: by 10.220.123.74 with SMTP id o10mr6940117vcr.44.1271950296318; Thu, 22 Apr 2010 08:31:36 -0700 (PDT) Message-ID: Subject: Re: Ask help:why my 64-bit ELF file could not run at the 64-bit mips cpu From: Jian Wang To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26449 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dominicwj@gmail.com Precedence: bulk X-list: linux-mips Hi, I have a 64-bit mips cpu, and compiled a 64-bit application, but this application could not run. (the target is running Linux) The details is: 1)if I compile the application with -mabi=n64, this program could not run, when I run it in the shell, it prompts "command not found" 2)but if I compile the application with -mabi=n32, it runs well and gives the correct result. I am wondering why with "-mabi=n64", this program could not run? I checked the CP0(status register), Bit px=0b0, KX=0b1, SX=0b1, UX=0b1, it seems that in User Mode, it accepts 64-bit operation. Anybody could give me some help? Any comments is much appreciated!! BR/Dominic From dominicwj@gmail.com Thu Apr 22 18:01:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Apr 2010 18:01:23 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:57758 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492501Ab0DVQBS (ORCPT ); Thu, 22 Apr 2010 18:01:18 +0200 Received: by vws3 with SMTP id 3so1945697vws.36 for ; Thu, 22 Apr 2010 09:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:content-type; bh=eD7mGdvVc72lOOdPdhssbBSkj92pV6qXDjegyIz6mVA=; b=ALM4cFRkWG9X3UMQHhTubLBkJQPxfAhdZK1D6SXftGn1bXymoPbhfJVSoDDdwdBCq8 wGVJoQkC5BIw8jzbsapLRwTZIt8olngRwHlcsOu/XHzjnE9bGcpOmt75B71/fV5T9a3x jbSlbbC/QvQNXcDYRDAwtZNB5C2ifydCieZ5A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type; b=pLV4gxRNiZJYyRwnNEQVju0j460odoBxTSVGUWETzaHBtVPVtT9kItoe28qrZp8ntx hSQxxVqf38TlMnSlFa2L+u+XZHDp9WGES2eQiDqcu5eU/pquLcNS7kddPXME9rZuiu8k /EMJJIyTte3GoEaW8RDb+erAxKVII88btR9jc= MIME-Version: 1.0 Received: by 10.220.17.141 with HTTP; Thu, 22 Apr 2010 09:01:09 -0700 (PDT) In-Reply-To: References: Date: Fri, 23 Apr 2010 00:01:09 +0800 Received: by 10.220.126.151 with SMTP id c23mr1943335vcs.4.1271952071115; Thu, 22 Apr 2010 09:01:11 -0700 (PDT) Message-ID: Subject: Ask help:why my 64-bit ELF file could not run at the 64-bit mips cpu From: Jian Wang To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26450 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dominicwj@gmail.com Precedence: bulk X-list: linux-mips Hi, I have a 64-bit mips cpu, and compiled a 64-bit application, but this application could not run. (the target is running Linux) The details is: 1)if I compile the application with -mabi=n64, this program could not run, when I run it in the shell, it prompts "command not found" 2)but if I compile the application with -mabi=n32, it runs well and gives the correct result. I am wondering why with "-mabi=n64", this program could not run? I checked the CP0(status register), Bit px=0b0, KX=0b1, SX=0b1, UX=0b1, it seems that in User Mode, it accepts 64-bit operation. Anybody could give me some help? Any comments is much appreciated!! BR/Dominic From janr@adax.com Thu Apr 22 19:10:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Apr 2010 19:11:02 +0200 (CEST) Received: from mail1.adax.com ([208.201.231.104]:7354 "EHLO mail1.adax.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492732Ab0DVRK7 (ORCPT ); Thu, 22 Apr 2010 19:10:59 +0200 Received: from static-151-204-189-187.pskn.east.verizon.net (static-151-204-189-187.pskn.east.verizon.net [151.204.189.187]) by mail1.adax.com (Postfix) with ESMTP id E7890120E71; Thu, 22 Apr 2010 10:10:49 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by static-151-204-189-187.pskn.east.verizon.net (Postfix) with ESMTP id 0AA91400582; Thu, 22 Apr 2010 13:10:49 -0400 (EDT) X-Virus-Scanned: amavisd-new at pskn.east.verizon.net Received: from static-151-204-189-187.pskn.east.verizon.net ([127.0.0.1]) by localhost (static-151-204-189-187.pskn.east.verizon.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mCHZaBnXtf1W; Thu, 22 Apr 2010 13:10:47 -0400 (EDT) Received: from [192.168.1.76] (jr001327.mtl-nj.adax [192.168.1.76]) by static-151-204-189-187.pskn.east.verizon.net (Postfix) with ESMTP id 5B27E400431; Thu, 22 Apr 2010 13:10:47 -0400 (EDT) Message-ID: <4BD08329.80804@adax.com> Date: Thu, 22 Apr 2010 13:11:05 -0400 From: Jan Rovins User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 To: Jian Wang CC: linux-mips@linux-mips.org Subject: Re: Ask help:why my 64-bit ELF file could not run at the 64-bit mips cpu References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26451 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: janr@adax.com Precedence: bulk X-list: linux-mips Jian Wang wrote: > Hi, > > I have a 64-bit mips cpu, and compiled a 64-bit application, but this > application could not run. (the target is running Linux) > The details is: > 1)if I compile the application with -mabi=n64, this program could not > run, when I run it in the shell, it prompts "command not found" > 2)but if I compile the application with -mabi=n32, it runs well and > gives the correct result. > > I am wondering why with "-mabi=n64", this program could not run? I > checked the CP0(status register), Bit px=0b0, KX=0b1, SX=0b1, UX=0b1, > it seems that in User Mode, it accepts 64-bit operation. > > Anybody could give me some help? Any comments is much appreciated!! > > BR/Dominic > > Perhaps you do not have the "n64" system libraries set up correctly in userspace. I have seen the "command not found" error when some fundamental libraries or the loader was missing. Do you have a /lib64 & /user/lib64? Run the file command on some of those libraries & see if they are n64 or n32 libs. double check your ld.so.conf to make sure it points to every thing you need. re run ldconfig if you change something. Jan From David.Daney@caviumnetworks.com Thu Apr 22 19:12:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Apr 2010 19:12:55 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:12370 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492900Ab0DVRMv (ORCPT ); Thu, 22 Apr 2010 19:12:51 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 22 Apr 2010 10:13:03 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 22 Apr 2010 10:11:58 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 22 Apr 2010 10:11:58 -0700 Message-ID: <4BD0835E.4000209@caviumnetworks.com> Date: Thu, 22 Apr 2010 10:11:58 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Sangeerth yen a pa CC: mlistz@gmail.com, linux-mips@linux-mips.org Subject: Re: Need help on CN56XX References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 22 Apr 2010 17:11:58.0198 (UTC) FILETIME=[EA677960:01CAE23E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26452 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/22/2010 01:58 AM, Sangeerth yen a pa wrote: > Hi, > > I'm currently working on CN56XX evaluation board ( CN5600-EVB-MB12 ). i > need the *Software Development Kit [OS, Tools, Libraries, Drivers, APIs].* > ** I believe this board is also known as EBH5600. The current Linux kernel from linux-mips.org will run on that board. You should be able to interact with the U-Boot boot monitor on the bottom plug of j15 at 115200n81. > Where can i download this ? > > Could you please send me that ? > If you need more help than that, I would suggest contacting the sales/support organization of the manufacturer. See: http://www.caviumnetworks.com/ David Daney From ralf@linux-mips.org Fri Apr 23 01:01:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 01:01:20 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:38704 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491819Ab0DVXBR (ORCPT ); Fri, 23 Apr 2010 01:01:17 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3MN0uve020296; Fri, 23 Apr 2010 00:00:58 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3MN0qxG020284; Fri, 23 Apr 2010 00:00:52 +0100 Date: Fri, 23 Apr 2010 00:00:50 +0100 From: Ralf Baechle To: Sebastian Andrzej Siewior Cc: linux-mips@linux-mips.org Subject: Re: [PATCH v2] mips/swarm: fixup screen_info struct Message-ID: <20100422230048.GA9837@linux-mips.org> References: <20100421185547.GA7708@Chamillionaire.breakpoint.cc> <20100421203647.GC7708@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100421203647.GC7708@Chamillionaire.breakpoint.cc> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26453 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 21, 2010 at 10:36:47PM +0200, Sebastian Andrzej Siewior wrote: Applied with minor cosmetic changes. Thanks! Ralf From ralf@linux-mips.org Fri Apr 23 02:30:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 02:30:07 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44393 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493004Ab0DWAaE (ORCPT ); Fri, 23 Apr 2010 02:30:04 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3N0ToCF023653; Fri, 23 Apr 2010 01:29:51 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3N0TlBd023642; Fri, 23 Apr 2010 01:29:47 +0100 Date: Fri, 23 Apr 2010 01:29:46 +0100 From: Ralf Baechle To: Sebastian Andrzej Siewior Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] mips/sb1250: include correct header, remove a warning Message-ID: <20100423002946.GB9105@linux-mips.org> References: <20100421185708.GB7708@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100421185708.GB7708@Chamillionaire.breakpoint.cc> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26454 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 21, 2010 at 08:57:08PM +0200, Sebastian Andrzej Siewior wrote: Thanks, applied. Ralf From ralf@linux-mips.org Fri Apr 23 04:31:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 04:31:19 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59509 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490967Ab0DWCbP (ORCPT ); Fri, 23 Apr 2010 04:31:15 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3N2VE6g028955; Fri, 23 Apr 2010 03:31:14 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3N2VE9l028939; Fri, 23 Apr 2010 03:31:14 +0100 Date: Fri, 23 Apr 2010 03:31:14 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH v3] MIPS: Alchemy: db1200: PCMCIA carddetects must not be auto-enabled. Message-ID: <20100423023114.GA28017@linux-mips.org> References: <1271864519-4516-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1271864519-4516-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26455 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 21, 2010 at 05:41:59PM +0200, Manuel Lauss wrote: > Please apply to 2.6.34-rc if still possible! Done. Is this also required for -stable kernels? Ralf From Gurumurthy.Gowdar@gmobis.com Fri Apr 23 07:38:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 07:38:46 +0200 (CEST) Received: from anti.mobis.co.kr ([211.217.52.67]:34087 "HELO sniper.mobis.co.kr" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491036Ab0DWFin convert rfc822-to-8bit (ORCPT ); Fri, 23 Apr 2010 07:38:43 +0200 Received: (snipe 23445 invoked by uid 0); 23 Apr 2010 14:38:30 +0900 Received: from gurumurthy.gowdar@gmobis.com with Spamsniper 2.94.22 (Processed in 0.007517 secs); Received: from unknown (HELO msmobiweb.mobis.co.kr) (10.240.100.165) by unknown with SMTP; 23 Apr 2010 14:38:30 +0900 X-RCPTTO: linux-mips@linux-mips.org Received: from mkegmal01.global.mobis.co.kr ([10.240.200.82]) by msmobiweb.mobis.co.kr with Microsoft SMTPSVC(6.0.3790.3959); Fri, 23 Apr 2010 14:38:31 +0900 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: Porting U-boot on MIPS (Au1350) Date: Fri, 23 Apr 2010 14:38:30 +0900 Message-ID: <5858DE952C53A441BDA3408A0524130104CCE08F@mkegmal01> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Porting U-boot on MIPS (Au1350) Thread-Index: AcripzT9Ib2Hu3WASN2X0K8+q1Wp6g== From: =?iso-8859-1?Q?=A0Gurumurthy_G_M?= To: X-OriginalArrivalTime: 23 Apr 2010 05:38:31.0148 (UTC) FILETIME=[35153AC0:01CAE2A7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26456 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Gurumurthy.Gowdar@gmobis.com Precedence: bulk X-list: linux-mips Hi All, we are porting U-boot 1.2.0 to MIPS32 Au1350 Processor. i am using ELDK 4.1 for MIPS32. Thanks wolfgang now am able to compile toolchain for mips after using ELDK for MIPS. Now while porting U-boot to Au1350 MIPS32 we are facing following problems mentioned below. We have a MIPS CPU which has reset address 0xBFC00000 , this is mapped to NOR flash with XIP in place. The boot block ( ie 0xBFC00000) is in the top block of the NOR flash and its of 16KB. U-Boot shall be put from address 0xBFC00000 in the NOR flash for CPU boot up , since it is the last block (16KB only) we cannot put complete U-Boot , some part of the U-Boot should go to lower blocks . To do this u-boot need to be divided into blocks and we shall provide a jump from the top block to other blocks of NOR flash. We have BDI3000 debugger for flashing the NOR flash and bdiGDB for MIPS. Is there any NOR flash drivers available which can support the below chip? NOR Flash chip : M29W160ET --> AM29BX16 NOR Flash chip size is 0x00200000 --> 2MB MIPS CPU Clock is 660MHz System Bus is 330MHz SDRAM bus clock is 165MHz please let me know if am going wrong anywhere or missing out something. With Regards, Gurumurthy Gowdar KPIT Cummins Infosystems Ltd From graham.gower@gmail.com Fri Apr 23 07:54:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 07:54:47 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:47757 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491165Ab0DWFyn convert rfc822-to-8bit (ORCPT ); Fri, 23 Apr 2010 07:54:43 +0200 Received: by gyb11 with SMTP id 11so5075456gyb.36 for ; Thu, 22 Apr 2010 22:54:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=rInIZiTCB/eKMDQm4ZIdQvB59DDSdsZ/yNTRnnitrNQ=; b=OgFHVlARrRO0Sc57l4GQutacU9OO4q6Wa26NMZmVOtCKzd7vaUdUCth9JI2dUJFQLF WFfgyI4/BP9JGnusCr6YpViHoBPtdhXjr/ZPxAEOVeb3/YDBkWa7J0RnUhbXmE7wnwLT IWInSGUouOJBBUculoR/mSTFxl0Vr7RlPTgTU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=QEmTpAQA23fq+w3KSszjfzcR2CrRNUq7YXLa498OtTNxbH0x9KYrbuS/9jG8eNXCyC o10cEyBb/VwRkg5HVGtyGVJHI7jRb/p0HloCIiFrxJHfHUdKNvE+7ZyBXdWRufUI4U10 6hkuUzkK/FMuqSEk2DCqGv0EVGvcLAMhgOtnw= MIME-Version: 1.0 Received: by 10.231.154.8 with HTTP; Thu, 22 Apr 2010 22:54:36 -0700 (PDT) In-Reply-To: <5858DE952C53A441BDA3408A0524130104CCE08F@mkegmal01> References: <5858DE952C53A441BDA3408A0524130104CCE08F@mkegmal01> Date: Fri, 23 Apr 2010 15:24:36 +0930 Received: by 10.101.149.17 with SMTP id b17mr27004430ano.80.1272002076539; Thu, 22 Apr 2010 22:54:36 -0700 (PDT) Message-ID: Subject: Re: Porting U-boot on MIPS (Au1350) From: Graham Gower To: Gurumurthy G M Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26457 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: graham.gower@gmail.com Precedence: bulk X-list: linux-mips On 23 April 2010 15:08, Gurumurthy G M wrote: > > > Hi All, >       we are porting U-boot 1.2.0 to MIPS32 Au1350 Processor. i am using ELDK 4.1 for MIPS32. > > Thanks wolfgang now am able to compile toolchain for mips after using ELDK for MIPS. > > Now while porting U-boot to Au1350 MIPS32 we are facing following problems mentioned below. > > We have a MIPS CPU which has reset address 0xBFC00000 , this is mapped to NOR flash with XIP in place. The boot block  ( ie 0xBFC00000) is in the top block of the NOR flash and its of 16KB. U-Boot shall be put from address 0xBFC00000 in the NOR flash for CPU boot up , since it is the last block (16KB only) we cannot put complete U-Boot , some part of the U-Boot should go to lower blocks . To do this u-boot need to be divided into blocks and we shall provide a jump from the top block to other blocks of NOR flash. We have BDI3000 debugger for flashing the NOR flash and bdiGDB for MIPS. So, your NOR is mapped at: 0xbfc00000 + 16*1024 - 0x00200000 = 0xbfa04000 ? Wouldn't it be simpler to get your hardware engineer(s) to map the NOR flash to a saner address? e.g. 0xbfc00000. > > Is there any NOR flash drivers available which can support the below chip? > > NOR Flash chip : M29W160ET --> AM29BX16 > NOR Flash chip size is 0x00200000 --> 2MB You'll probably have to add an entry for the chip in linux/drivers/mtd/chips/jedec_probe.c and create a mapping driver (plenty of really simple examples in linux/drivers/mtd/maps/). > > MIPS CPU Clock is 660MHz > System Bus is 330MHz > SDRAM bus clock is 165MHz > > > please let me know if am going wrong anywhere or missing out something. > > With Regards, > Gurumurthy Gowdar > KPIT Cummins Infosystems Ltd > > -Graham From manuel.lauss@googlemail.com Fri Apr 23 07:58:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 07:59:12 +0200 (CEST) Received: from mail-bw0-f226.google.com ([209.85.218.226]:42424 "EHLO mail-bw0-f226.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491190Ab0DWF65 convert rfc822-to-8bit (ORCPT ); Fri, 23 Apr 2010 07:58:57 +0200 Received: by bwz26 with SMTP id 26so9268673bwz.27 for ; Thu, 22 Apr 2010 22:58:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=5BIZ2B/mUmw9WPikzDppICX00EpYQ9eZ/U3B32KHZeQ=; b=WmAL92zUibfQeMF3WevHdDCOPgCPUxxm6VqqDvKmGEP0MJXP6tXNrJfyMldyIkj8l/ uZQKZt9+M/EgwEvZRmWzrmfEe97eoRcCutYWsqVrz+jZ1DllcHCC8iyQmHX+qI+ZK05W rcUrDt2MSz4iFQW5G8vjLZ7cZNagwTc//IpAs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=q7FoU+uPCG3nFy1uJVcZpdv/LeaBg7I2tXBZ1H2dkY9laOqaFYY8QhUzBdnkGiu9Dc EPKrKX/cNVudND1B1xdMmlOKetCjbZpxpE2fLp6CQpK9hDUQHPPEv/kdxPHZ3vNh7Qih YkXZfkimWTNJ2yK5Nve5sdK75akjRvig9nV6w= MIME-Version: 1.0 Received: by 10.223.106.12 with HTTP; Thu, 22 Apr 2010 22:58:51 -0700 (PDT) In-Reply-To: <5858DE952C53A441BDA3408A0524130104CCE08F@mkegmal01> References: <5858DE952C53A441BDA3408A0524130104CCE08F@mkegmal01> Date: Fri, 23 Apr 2010 07:58:51 +0200 Received: by 10.103.82.17 with SMTP id j17mr2795819mul.101.1272002331954; Thu, 22 Apr 2010 22:58:51 -0700 (PDT) Message-ID: Subject: Re: Porting U-boot on MIPS (Au1350) From: Manuel Lauss To: Gurumurthy G M Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26458 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips >       we are porting U-boot 1.2.0 to MIPS32 Au1350 Processor. i am using ELDK 4.1 for MIPS32. > > We have a MIPS CPU which has reset address 0xBFC00000 , this is mapped to NOR flash with XIP in place. The boot block  ( ie 0xBFC00000) is in the top block of the NOR flash and its of 16KB. U-Boot shall be put from address 0xBFC00000 in the NOR flash for CPU boot up , since it is the last block (16KB only) we cannot put complete U-Boot , some part of the U-Boot should go to lower blocks . To do this u-boot need to be divided into blocks and we shall provide a jump from the top block to other blocks of NOR flash. We have BDI3000 debugger for flashing the NOR flash and bdiGDB for MIPS. > > Is there any NOR flash drivers available which can support the below chip? > > NOR Flash chip : M29W160ET --> AM29BX16 > NOR Flash chip size is 0x00200000 --> 2MB I believe you need to change CS0# decoded range (staddr0 reg) very early to enable access to the whole chip. Put init code at bfc00000, and let it load the main bootloader binary from a predefined ROM address to a predefined RAM address and execute. Manuel From ralf@linux-mips.org Fri Apr 23 09:31:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 09:31:43 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58065 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491909Ab0DWHbf (ORCPT ); Fri, 23 Apr 2010 09:31:35 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3N7VP1m006598; Fri, 23 Apr 2010 08:31:26 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3N7VOlq006587; Fri, 23 Apr 2010 08:31:24 +0100 Date: Fri, 23 Apr 2010 08:31:23 +0100 From: Ralf Baechle To: Sebastian Andrzej Siewior Cc: tbm@cyrius.com, linux-mips@linux-mips.org Subject: Re: mips: enable PATA platform on SWARM and LITTLESUR Message-ID: <20100423073123.GA6052@linux-mips.org> References: <20100418132636.GA32350@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100418132636.GA32350@Chamillionaire.breakpoint.cc> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26459 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Apr 18, 2010 at 03:26:36PM +0200, Sebastian Andrzej Siewior wrote: > according to include/asm/sibyte/swarm.h both systems provide a > platform device for the ide controler. Until now the IDE subsystem was > used which is deprecated by now. The same structure can be used with the > PATA driver. > This was tested on SWARM. Thanks, applied. Ralf From dominicwj@gmail.com Fri Apr 23 10:42:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 10:42:36 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:36468 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491789Ab0DWImd convert rfc822-to-8bit (ORCPT ); Fri, 23 Apr 2010 10:42:33 +0200 Received: by vws3 with SMTP id 3so2520826vws.36 for ; Fri, 23 Apr 2010 01:42:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:received:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=cwDs8pWyFY8KS2MrengUkITzIHs9dMYf3DhN2CMUlC4=; b=hw7cb85/phUKHH4PaPQnCICDsUMMRcn0lOuJxlCZ3CsJHxSBUwC6q7dd68jz64AFFP n/iK6tm80EZmADoG4l5VA2ZuXMNSrm3dY23pj2PurbCGic3XpmBIoLn9bjiswg0q84Ck 6f79ZSOFtwBYGVZbcqEQ/xdXmUHVXWzOXMzhs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=oHllwcoLpypBiTMM88E3HF4p2p4+uNFkePAxx9wmNkwlriZ/tALmaF2jSBHm+LUUzu UkMDRltfNF64NBeJCRiLX3IGTIKD2QvGqfN7kmCZaH3kzdrX25W4kmf1w0gB/8P+JaDJ DzTJB5QJayfwSayNwaE3QfmN/lmfHYVDnuvJs= MIME-Version: 1.0 Received: by 10.220.17.141 with HTTP; Fri, 23 Apr 2010 01:42:26 -0700 (PDT) In-Reply-To: <4BD08329.80804@adax.com> References: <4BD08329.80804@adax.com> Date: Fri, 23 Apr 2010 16:42:26 +0800 Received: by 10.220.157.206 with SMTP id c14mr7627121vcx.110.1272012146792; Fri, 23 Apr 2010 01:42:26 -0700 (PDT) Message-ID: Subject: Re: Ask help:why my 64-bit ELF file could not run at the 64-bit mips cpu From: Dominic To: Jan Rovins Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26460 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dominicwj@gmail.com Precedence: bulk X-list: linux-mips Hi Jan, Thanks a lot for your precious reply! I try to use -static to compile the program, then the 64-bit program can run, so it should be the library related other than 64-bit instruction or addressing related. Then I stored the 64-bit libraries in nfs, and mount it on the target board, after adding the path to ld.so.conf and 'ldconfig', the program compiled without -static still does not run. Shall I miss something? Thanks! BR/Dominic On Fri, Apr 23, 2010 at 1:11 AM, Jan Rovins wrote: > Jian Wang wrote: >> >> Hi, >> >>  I have a 64-bit mips cpu, and compiled a 64-bit application, but this >>  application could not run. (the target is running Linux) >>  The details is: >>  1)if I compile the application with -mabi=n64, this program could not >>  run, when I run it in the shell, it prompts "command not found" >>  2)but if I compile the application with -mabi=n32, it runs well and >>  gives the correct result. >> >>  I am wondering why with "-mabi=n64", this program could not run? I >>  checked the CP0(status register), Bit px=0b0, KX=0b1, SX=0b1, UX=0b1, >>  it seems that in User Mode, it accepts 64-bit operation. >> >>  Anybody could give me some help? Any comments is much appreciated!! >> >>  BR/Dominic >> >> > > Perhaps you do not have the "n64" system libraries set up correctly in > userspace. > I have seen the "command not found" error when some fundamental libraries or > the loader was missing. > > Do you have a /lib64 & /user/lib64? > Run the file command on some of those libraries & see if they are n64 or n32 > libs. > > double check your ld.so.conf to make sure it points to every thing you need. > re run ldconfig if you change something. > > > Jan > > From geert.uytterhoeven@gmail.com Fri Apr 23 11:26:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 11:26:59 +0200 (CEST) Received: from mail-ww0-f49.google.com ([74.125.82.49]:35585 "EHLO mail-ww0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492105Ab0DWJ0q convert rfc822-to-8bit (ORCPT ); Fri, 23 Apr 2010 11:26:46 +0200 Received: by wwi17 with SMTP id 17so411229wwi.36 for ; Fri, 23 Apr 2010 02:26:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:received:message-id:subject :from:to:cc:content-type:content-transfer-encoding; bh=ZHWrNV372VMAqhZiorBMkTihnlglZDMPYQ7PdcT+4lo=; b=LDb3WtM7CTRvEepmkMqhXhblCRA+NQrD1drnZVH/IZzGhtWjMtDVBrB8rC2qBL47lA y1pUka/3Bla43JexNYA9Tujse0hVPqHCKYfnXxeJkDHavYD2COuc4br6cTomWlBVvRAj KPhYSSAww4jv7uwwKv+RzKhCN1GEtkyuI+LBQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=hG+SoWKwJrSXgFDpPlAzXurhrNNvsk0W7oeBzG4D7qyUU5seC5o/ghh46rtww+q5AJ e8V8mgzE7BrAuo9Wp3S4mHNFuBEugyzPU4ZWcFwPMqBWsnrU/Ib51/w753iLy09ftmO9 9TswlL8chc8a4aGbDDz47dSgPXgsbtcLeIddY= MIME-Version: 1.0 Received: by 10.216.93.131 with HTTP; Fri, 23 Apr 2010 02:26:40 -0700 (PDT) In-Reply-To: References: <4BD08329.80804@adax.com> Date: Fri, 23 Apr 2010 11:26:40 +0200 X-Google-Sender-Auth: d151287b40416e9c Received: by 10.216.155.213 with SMTP id j63mr2055852wek.47.1272014800573; Fri, 23 Apr 2010 02:26:40 -0700 (PDT) Message-ID: Subject: Re: Ask help:why my 64-bit ELF file could not run at the 64-bit mips cpu From: Geert Uytterhoeven To: Dominic Cc: Jan Rovins , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26461 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Fri, Apr 23, 2010 at 10:42, Dominic wrote: > Thanks a lot for your precious reply! I try to use -static to compile > the program, then the 64-bit program can run, so it should be the > library related other than 64-bit instruction or addressing related. > Then I stored the 64-bit libraries in nfs, and mount it on the target > board, after adding the path to ld.so.conf and 'ldconfig', the program > compiled without -static still does not run. Shall I miss something? `ldd ' may tell you... > On Fri, Apr 23, 2010 at 1:11 AM, Jan Rovins wrote: >> Jian Wang wrote: >>> >>> Hi, >>> >>>  I have a 64-bit mips cpu, and compiled a 64-bit application, but this >>>  application could not run. (the target is running Linux) >>>  The details is: >>>  1)if I compile the application with -mabi=n64, this program could not >>>  run, when I run it in the shell, it prompts "command not found" >>>  2)but if I compile the application with -mabi=n32, it runs well and >>>  gives the correct result. >>> >>>  I am wondering why with "-mabi=n64", this program could not run? I >>>  checked the CP0(status register), Bit px=0b0, KX=0b1, SX=0b1, UX=0b1, >>>  it seems that in User Mode, it accepts 64-bit operation. >>> >>>  Anybody could give me some help? Any comments is much appreciated!! >>> >>>  BR/Dominic >>> >>> >> >> Perhaps you do not have the "n64" system libraries set up correctly in >> userspace. >> I have seen the "command not found" error when some fundamental libraries or >> the loader was missing. >> >> Do you have a /lib64 & /user/lib64? >> Run the file command on some of those libraries & see if they are n64 or n32 >> libs. >> >> double check your ld.so.conf to make sure it points to every thing you need. >> re run ldconfig if you change something. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From sgi-linux-mips@m.gmane.org Fri Apr 23 12:08:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 12:08:27 +0200 (CEST) Received: from lo.gmane.org ([80.91.229.12]:44514 "EHLO lo.gmane.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492321Ab0DWKIX (ORCPT ); Fri, 23 Apr 2010 12:08:23 +0200 Received: from list by lo.gmane.org with local (Exim 4.69) (envelope-from ) id 1O5Fo0-0004Ms-7u for linux-mips@linux-mips.org; Fri, 23 Apr 2010 12:08:16 +0200 Received: from chipmunk.wormnet.eu ([195.195.131.226]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Fri, 23 Apr 2010 12:08:16 +0200 Received: from alex by chipmunk.wormnet.eu with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Fri, 23 Apr 2010 12:08:16 +0200 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org connect(): No such file or directory From: Alexander Clouter Subject: Re: Ask help:why my 64-bit ELF file could not run at the 64-bit mips cpu Date: Fri, 23 Apr 2010 10:34:23 +0100 Lines: 35 Message-ID: References: <4BD08329.80804@adax.com> X-Complaints-To: usenet@dough.gmane.org X-Gmane-NNTP-Posting-Host: chipmunk.wormnet.eu User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.26-2-sparc64-smp (sparc64)) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26462 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Dominic wrote: > > Thanks a lot for your precious reply! I try to use -static to compile > the program, then the 64-bit program can run, so it should be the > library related other than 64-bit instruction or addressing related. > Then I stored the 64-bit libraries in nfs, and mount it on the target > board, after adding the path to ld.so.conf and 'ldconfig', the program > compiled without -static still does not run. Shall I miss something? > On your host, you can type something like: ---- alex@berk:/usr/src/wag54g$ readelf -d buildroot/output/target/usr/sbin/ip6tables-multi | grep Shared 0x00000001 (NEEDED) Shared library: [libip6tc.so.0] 0x00000001 (NEEDED) Shared library: [libxtables.so.4] 0x00000001 (NEEDED) Shared library: [libdl.so.0] 0x00000001 (NEEDED) Shared library: [libm.so.0] 0x00000001 (NEEDED) Shared library: [libc.so.0] ---- This will list all the libraries that you need installed[1], I'm guessin you have missed one. You can look at the output of 'readelf -a' to try to see what might be missing. Cheers [1] in addition to the interpreter required (for example 'ld-uClibc') and the main C library being used: readelf -l buildroot/output/target/usr/sbin/ip6tables-multi -- Alexander Clouter .sigmonster says: "Ninety percent of baseball is half mental." -- Yogi Berra From dengcheng.zhu@gmail.com Fri Apr 23 12:36:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 12:36:13 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:60581 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492343Ab0DWKgJ (ORCPT ); Fri, 23 Apr 2010 12:36:09 +0200 Received: by pvc30 with SMTP id 30so250363pvc.36 for ; Fri, 23 Apr 2010 03:36:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=7rbd21VQnY9ohB/NLMCUdjEUa+W5GgndX/99m4WB6dQ=; b=MilS0Vr32rU4p0/Fl9kAJcQ3bWsS3H3TS/NW0m/QLjrnInInNwR4sPLe2bVEXzUtp5 AElW9hoSN5VEU1ewSzyf1y1AvsOppT83HrnQ/Ci2j4Zyw4Lx/Sqd/SUODo419wFoK44k 8Z9EIeAW2sP09rj0D7h2CJsMo0/o0HM1i9U+Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=deQSzKvskW0Pk3jgRpzvokcnQmt0JrpfMJf5pdztJ4qYfuVuDv8iwhRAYxdNBiAN24 Dk3etXNc9rnZgXqBXXh5ebvUAeqxEDxHz5WTu5En1FziFyCrz2rVMMrBDcf+cn5Etpj/ ofLMe3422DyRq33UoVjuDoaJvESzV5iXHeBAE= Received: by 10.115.148.18 with SMTP id a18mr1877431wao.229.1272018961327; Fri, 23 Apr 2010 03:36:01 -0700 (PDT) Received: from [192.168.1.100] ([114.84.71.49]) by mx.google.com with ESMTPS id v13sm4146088wav.2.2010.04.23.03.35.56 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 23 Apr 2010 03:36:00 -0700 (PDT) Subject: [PATCH v2 0/4] MIPS performance event support v2 From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 23 Apr 2010 18:35:52 +0800 Message-ID: <1272018952.4662.88.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26463 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips v2 - v1: - Adjusting code structure as suggested by Wu Zhangjin. With this change, hardware performance event support for loongson2 and rm9000 can be conveniently implemented by adding and including new files like perf_event_loongson2.c; Oprofile and Perf for MIPS are now sharing pmu.h; Naming changes were made to some functions. - Fixing the generic atomic64 issue reported by David Daney. Currently, 32bit kernel is using the generic version from lib. When Ralf Baechle's common atomic64 version is ready, this may change. - Adding raw event support. For more details, please refer to the code comments for mipsxx_pmu_map_raw_event(). - Adding new software events - PERF_COUNT_SW_ALIGNMENT_FAULTS and PERF_COUNT_SW_EMULATION_FAULTS. - Fixing some small bugs. - Adding new comments for the code. - Making some code style changes. Deng-Cheng Zhu (4): - MIPS/Oprofile: extracting PMU defines/helper functions for sharing - MIPS: in non-64bit kernel, using the generic atomic64 operations for perf counter support - MIPS: adding support for software performance events - MIPS: implementing hardware performance event support v1: This patch series implemented the low-level logic for the Linux performance counter subsystem on MIPS, which enables the collection of all sorts of HW/SW performance events based on per-CPU or per-task. An overview of this implementation is as follows: - Using generic atomic64 operations from lib. - SMVP/UP kernels are supported (not for SMTC). - 24K/34K/74K cores are implemented. - Currently working when Oprofile is _not_ available. - Minimal software perf events are supported. Tests were carried on the Malta-R board. The mentioned cores and kernel flavors were tested. For more information, please refer to the particular patches. Deng-Cheng Zhu (3): - MIPS: use the generic atomic64 operations for perf counter support - MIPS: adding support for software perf events - MIPS: implement hardware perf event support From dengcheng.zhu@gmail.com Fri Apr 23 12:36:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 12:36:40 +0200 (CEST) Received: from mail-pv0-f177.google.com ([74.125.83.177]:60581 "EHLO mail-pv0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492348Ab0DWKgX (ORCPT ); Fri, 23 Apr 2010 12:36:23 +0200 Received: by mail-pv0-f177.google.com with SMTP id 30so250363pvc.36 for ; Fri, 23 Apr 2010 03:36:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=/oUFljwA/4724fzY2RfcutEmulSObGpx9Meck0k2QaI=; b=e0J5EYDwwykUS8aBt3giT9apGZEPpSc3lLfBuyRP8iPoQXuhjgmqzfY3DFVnQFBiJ/ O5DdxcPPqU98I0Zx2ZsicMuuTnZifrzNUuo1oLmq/w5hX5nZAtDkKQ1zOivKHt7b/Fpk +Mdys6VvqOkNugYUbLMKZY9i1LQCPFmxiYFeM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=bFjkpapzZnakZxoF5TbDiX8YitrDaG0Pc5HL2ytxqbVmmXf6mDd8g7oKrCMJrdZT4s hPCCzuJa5/f46r4IQphfOAyM1qC55Xk4nzMtkgjf4HEU12cahltBGJJNE4AdT1gIxNqA jSAJz2TvkroCd2pzbo6ZFYW9Y0dMqAb96tWnk= Received: by 10.114.18.19 with SMTP id 19mr2974668war.174.1272018982080; Fri, 23 Apr 2010 03:36:22 -0700 (PDT) Received: from [192.168.1.100] ([114.84.71.49]) by mx.google.com with ESMTPS id l8sm4140897wad.4.2010.04.23.03.36.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 23 Apr 2010 03:36:21 -0700 (PDT) Subject: [PATCH v2 1/4] MIPS/Oprofile: extracting PMU defines/helper functions for sharing From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 23 Apr 2010 18:36:10 +0800 Message-ID: <1272018970.4662.93.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26464 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Moving performance counter/control defines/helper functions into a single header file, so that software using the MIPS PMU can share the code. Signed-off-by: Deng-Cheng Zhu --- arch/mips/include/asm/pmu.h | 244 +++++++++++++++++++++++++++++++ arch/mips/oprofile/op_model_loongson2.c | 23 +--- arch/mips/oprofile/op_model_mipsxx.c | 164 +--------------------- arch/mips/oprofile/op_model_rm9000.c | 16 +-- 4 files changed, 247 insertions(+), 200 deletions(-) create mode 100644 arch/mips/include/asm/pmu.h diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h new file mode 100644 index 0000000..6da943c --- /dev/null +++ b/arch/mips/include/asm/pmu.h @@ -0,0 +1,244 @@ +/* + * linux/arch/mips/include/asm/pmu.h + * + * Copyright (C) 2004, 05, 06 by Ralf Baechle + * Copyright (C) 2005 by MIPS Technologies, Inc. + * Copyright (C) 2009 Lemote Inc. + * Author: Yanhua + * Author: Wu Zhangjin + * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu + * + * This file is shared by Oprofile and Perf. It is also shared across the + * Oprofile implementation for different MIPS CPUs. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MIPS_PMU_H__ +#define __MIPS_PMU_H__ + +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \ + defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1) + +#define M_CONFIG1_PC (1 << 4) + +#define M_PERFCTL_EXL (1UL << 0) +#define M_PERFCTL_KERNEL (1UL << 1) +#define M_PERFCTL_SUPERVISOR (1UL << 2) +#define M_PERFCTL_USER (1UL << 3) +#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) +#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) +#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) +#define M_PERFCTL_MT_EN(filter) ((filter) << 20) +#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) +#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) +#define M_TC_EN_TC M_PERFCTL_MT_EN(2) +#define M_PERFCTL_TCID(tcid) ((tcid) << 22) +#define M_PERFCTL_WIDE (1UL << 30) +#define M_PERFCTL_MORE (1UL << 31) + +#define M_COUNTER_OVERFLOW (1UL << 31) + +static int (*save_perf_irq)(void); + +#ifdef CONFIG_MIPS_MT_SMP +static int cpu_has_mipsmt_pertccounters; +#define WHAT (M_TC_EN_VPE | \ + M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id)) +/* + * FIXME: For VSMP, vpe_id() is redefined for Perf, because + * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. WHAT is not + * redefined because Perf does not use it. + */ +#if defined(CONFIG_HW_PERF_EVENTS) +#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ + 0 : smp_processor_id()) +#else +#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ + 0 : cpu_data[smp_processor_id()].vpe_id) +#endif +/* + * The number of bits to shift to convert between counters per core and + * counters per VPE. There is no reasonable interface atm to obtain the + * number of VPEs used by Linux and in the 34K this number is fixed to two + * anyways so we hardcore a few things here for the moment. The way it's + * done here will ensure that oprofile VSMP kernel will run right on a lesser + * core like a 24K also or with maxcpus=1. + */ +static inline unsigned int vpe_shift(void) +{ + if (num_possible_cpus() > 1) + return 1; + + return 0; +} +#else +#define WHAT 0 +#define vpe_id() 0 +static inline unsigned int vpe_shift(void) +{ + return 0; +} +#endif + +static inline unsigned int +counters_total_to_per_cpu(unsigned int counters) +{ + return counters >> vpe_shift(); +} + +static inline unsigned int +counters_per_cpu_to_total(unsigned int counters) +{ + return counters << vpe_shift(); +} + +#define __define_perf_accessors(r, n, np) \ + \ +static inline unsigned int r_c0_ ## r ## n(void) \ +{ \ + unsigned int cpu = vpe_id(); \ + \ + switch (cpu) { \ + case 0: \ + return read_c0_ ## r ## n(); \ + case 1: \ + return read_c0_ ## r ## np(); \ + default: \ + BUG(); \ + } \ + return 0; \ +} \ + \ +static inline void w_c0_ ## r ## n(unsigned int value) \ +{ \ + unsigned int cpu = vpe_id(); \ + \ + switch (cpu) { \ + case 0: \ + write_c0_ ## r ## n(value); \ + return; \ + case 1: \ + write_c0_ ## r ## np(value); \ + return; \ + default: \ + BUG(); \ + } \ + return; \ +} \ + +__define_perf_accessors(perfcntr, 0, 2) +__define_perf_accessors(perfcntr, 1, 3) +__define_perf_accessors(perfcntr, 2, 0) +__define_perf_accessors(perfcntr, 3, 1) + +__define_perf_accessors(perfctrl, 0, 2) +__define_perf_accessors(perfctrl, 1, 3) +__define_perf_accessors(perfctrl, 2, 0) +__define_perf_accessors(perfctrl, 3, 1) + +static inline int __n_counters(void) +{ + if (!(read_c0_config1() & M_CONFIG1_PC)) + return 0; + if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) + return 1; + if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) + return 2; + if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) + return 3; + + return 4; +} + +static inline int n_counters(void) +{ + int counters; + + switch (current_cpu_type()) { + case CPU_R10000: + counters = 2; + break; + + case CPU_R12000: + case CPU_R14000: + counters = 4; + break; + + default: + counters = __n_counters(); + } + + return counters; +} + +static void reset_counters(void *arg) +{ + int counters = (int)(long)arg; + switch (counters) { + case 4: + w_c0_perfctrl3(0); + w_c0_perfcntr3(0); + case 3: + w_c0_perfctrl2(0); + w_c0_perfcntr2(0); + case 2: + w_c0_perfctrl1(0); + w_c0_perfcntr1(0); + case 1: + w_c0_perfctrl0(0); + w_c0_perfcntr0(0); + } +} + +/* Used by Perf */ +#define MIPS_MAX_HWEVENTS 4 + +#elif defined(CONFIG_CPU_RM9000) + +#define RM9K_COUNTER1_EVENT(event) ((event) << 0) +#define RM9K_COUNTER1_SUPERVISOR (1ULL << 7) +#define RM9K_COUNTER1_KERNEL (1ULL << 8) +#define RM9K_COUNTER1_USER (1ULL << 9) +#define RM9K_COUNTER1_ENABLE (1ULL << 10) +#define RM9K_COUNTER1_OVERFLOW (1ULL << 15) + +#define RM9K_COUNTER2_EVENT(event) ((event) << 16) +#define RM9K_COUNTER2_SUPERVISOR (1ULL << 23) +#define RM9K_COUNTER2_KERNEL (1ULL << 24) +#define RM9K_COUNTER2_USER (1ULL << 25) +#define RM9K_COUNTER2_ENABLE (1ULL << 26) +#define RM9K_COUNTER2_OVERFLOW (1ULL << 31) + +extern unsigned int rm9000_perfcount_irq; + +#elif defined(CONFIG_CPU_LOONGSON2) + +/* + * a patch should be sent to oprofile with the loongson-specific support. + * otherwise, the oprofile tool will not recognize this and complain about + * "cpu_type 'unset' is not valid". + */ +#define LOONGSON2_CPU_TYPE "mips/loongson2" + +#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) +#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) + +#define LOONGSON2_PERFCNT_EXL (1UL << 0) +#define LOONGSON2_PERFCNT_KERNEL (1UL << 1) +#define LOONGSON2_PERFCNT_SUPERVISOR (1UL << 2) +#define LOONGSON2_PERFCNT_USER (1UL << 3) +#define LOONGSON2_PERFCNT_INT_EN (1UL << 4) +#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31) + +/* Loongson2 performance counter register */ +#define read_c0_perfctrl() __read_64bit_c0_register($24, 0) +#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val) +#define read_c0_perfcnt() __read_64bit_c0_register($25, 0) +#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val) + +#endif /* CONFIG_CPU_* */ + +#endif /* __MIPS_PMU_H__ */ diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index 29e2326..59b4c93 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -13,32 +13,11 @@ #include #include #include +#include #include /* LOONGSON2_PERFCNT_IRQ */ #include "op_impl.h" -/* - * a patch should be sent to oprofile with the loongson-specific support. - * otherwise, the oprofile tool will not recognize this and complain about - * "cpu_type 'unset' is not valid". - */ -#define LOONGSON2_CPU_TYPE "mips/loongson2" - -#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) -#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) - -#define LOONGSON2_PERFCNT_EXL (1UL << 0) -#define LOONGSON2_PERFCNT_KERNEL (1UL << 1) -#define LOONGSON2_PERFCNT_SUPERVISOR (1UL << 2) -#define LOONGSON2_PERFCNT_USER (1UL << 3) -#define LOONGSON2_PERFCNT_INT_EN (1UL << 4) -#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31) - -/* Loongson2 performance counter register */ -#define read_c0_perfctrl() __read_64bit_c0_register($24, 0) -#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val) -#define read_c0_perfcnt() __read_64bit_c0_register($25, 0) -#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val) static struct loongson2_register_config { unsigned int ctrl; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 54759f1..48461f7 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -11,116 +11,10 @@ #include #include #include +#include #include "op_impl.h" -#define M_PERFCTL_EXL (1UL << 0) -#define M_PERFCTL_KERNEL (1UL << 1) -#define M_PERFCTL_SUPERVISOR (1UL << 2) -#define M_PERFCTL_USER (1UL << 3) -#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) -#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) -#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) -#define M_PERFCTL_MT_EN(filter) ((filter) << 20) -#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) -#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) -#define M_TC_EN_TC M_PERFCTL_MT_EN(2) -#define M_PERFCTL_TCID(tcid) ((tcid) << 22) -#define M_PERFCTL_WIDE (1UL << 30) -#define M_PERFCTL_MORE (1UL << 31) - -#define M_COUNTER_OVERFLOW (1UL << 31) - -static int (*save_perf_irq)(void); - -#ifdef CONFIG_MIPS_MT_SMP -static int cpu_has_mipsmt_pertccounters; -#define WHAT (M_TC_EN_VPE | \ - M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id)) -#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ - 0 : cpu_data[smp_processor_id()].vpe_id) - -/* - * The number of bits to shift to convert between counters per core and - * counters per VPE. There is no reasonable interface atm to obtain the - * number of VPEs used by Linux and in the 34K this number is fixed to two - * anyways so we hardcore a few things here for the moment. The way it's - * done here will ensure that oprofile VSMP kernel will run right on a lesser - * core like a 24K also or with maxcpus=1. - */ -static inline unsigned int vpe_shift(void) -{ - if (num_possible_cpus() > 1) - return 1; - - return 0; -} - -#else - -#define WHAT 0 -#define vpe_id() 0 - -static inline unsigned int vpe_shift(void) -{ - return 0; -} - -#endif - -static inline unsigned int counters_total_to_per_cpu(unsigned int counters) -{ - return counters >> vpe_shift(); -} - -static inline unsigned int counters_per_cpu_to_total(unsigned int counters) -{ - return counters << vpe_shift(); -} - -#define __define_perf_accessors(r, n, np) \ - \ -static inline unsigned int r_c0_ ## r ## n(void) \ -{ \ - unsigned int cpu = vpe_id(); \ - \ - switch (cpu) { \ - case 0: \ - return read_c0_ ## r ## n(); \ - case 1: \ - return read_c0_ ## r ## np(); \ - default: \ - BUG(); \ - } \ - return 0; \ -} \ - \ -static inline void w_c0_ ## r ## n(unsigned int value) \ -{ \ - unsigned int cpu = vpe_id(); \ - \ - switch (cpu) { \ - case 0: \ - write_c0_ ## r ## n(value); \ - return; \ - case 1: \ - write_c0_ ## r ## np(value); \ - return; \ - default: \ - BUG(); \ - } \ - return; \ -} \ - -__define_perf_accessors(perfcntr, 0, 2) -__define_perf_accessors(perfcntr, 1, 3) -__define_perf_accessors(perfcntr, 2, 0) -__define_perf_accessors(perfcntr, 3, 1) - -__define_perf_accessors(perfctrl, 0, 2) -__define_perf_accessors(perfctrl, 1, 3) -__define_perf_accessors(perfctrl, 2, 0) -__define_perf_accessors(perfctrl, 3, 1) struct op_mips_model op_model_mipsxx_ops; @@ -242,62 +136,6 @@ static int mipsxx_perfcount_handler(void) return handled; } -#define M_CONFIG1_PC (1 << 4) - -static inline int __n_counters(void) -{ - if (!(read_c0_config1() & M_CONFIG1_PC)) - return 0; - if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) - return 1; - if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) - return 2; - if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) - return 3; - - return 4; -} - -static inline int n_counters(void) -{ - int counters; - - switch (current_cpu_type()) { - case CPU_R10000: - counters = 2; - break; - - case CPU_R12000: - case CPU_R14000: - counters = 4; - break; - - default: - counters = __n_counters(); - } - - return counters; -} - -static void reset_counters(void *arg) -{ - int counters = (int)(long)arg; - switch (counters) { - case 4: - w_c0_perfctrl3(0); - w_c0_perfcntr3(0); - case 3: - w_c0_perfctrl2(0); - w_c0_perfcntr2(0); - case 2: - w_c0_perfctrl1(0); - w_c0_perfcntr1(0); - case 1: - w_c0_perfctrl0(0); - w_c0_perfcntr0(0); - } -} - static int __init mipsxx_init(void) { int counters; diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c index 3aa8138..48e7487 100644 --- a/arch/mips/oprofile/op_model_rm9000.c +++ b/arch/mips/oprofile/op_model_rm9000.c @@ -9,24 +9,10 @@ #include #include #include +#include #include "op_impl.h" -#define RM9K_COUNTER1_EVENT(event) ((event) << 0) -#define RM9K_COUNTER1_SUPERVISOR (1ULL << 7) -#define RM9K_COUNTER1_KERNEL (1ULL << 8) -#define RM9K_COUNTER1_USER (1ULL << 9) -#define RM9K_COUNTER1_ENABLE (1ULL << 10) -#define RM9K_COUNTER1_OVERFLOW (1ULL << 15) - -#define RM9K_COUNTER2_EVENT(event) ((event) << 16) -#define RM9K_COUNTER2_SUPERVISOR (1ULL << 23) -#define RM9K_COUNTER2_KERNEL (1ULL << 24) -#define RM9K_COUNTER2_USER (1ULL << 25) -#define RM9K_COUNTER2_ENABLE (1ULL << 26) -#define RM9K_COUNTER2_OVERFLOW (1ULL << 31) - -extern unsigned int rm9000_perfcount_irq; static struct rm9k_register_config { unsigned int control; -- 1.7.0.4 From dengcheng.zhu@gmail.com Fri Apr 23 12:36:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 12:37:07 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:39598 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492343Ab0DWKgs (ORCPT ); Fri, 23 Apr 2010 12:36:48 +0200 Received: by pwj3 with SMTP id 3so1853372pwj.36 for ; Fri, 23 Apr 2010 03:36:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=wBhOSAG2XhK5HzeZdDGBf0rIJkrZZB3WL35wC8EjAlM=; b=FnZJXl/fQPOVuxUuZEP4DsG8PS22X2xH83kZqqnMX/3F/kk5P7SfKTT+VoSObP6/Xh 5tWJJKbYgCzeQeUnUe/tTooGQQIi2LVwW73BUenjagRmZo893JJRSZo7urdelBPBwudB WvVRCOpiBkxCg9WkcdIf/nRX0BT7xXrdVSn7o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=dvW5cW6V6G8SJMLAF0Adt1RFfk6Dk2pICGRV5Yy5bPHLtOpVPI7d8qgCtRdAxS3D1t IAgR00N4I55oY6spwqV4gg/HTMgYjSj+aXikB+TH1tyztWFgQBIk4QjKtDDESuYMOXVv nuqh6LEm707hAgD9IdiXimkQ/TogvKwWTtpg0= Received: by 10.115.38.23 with SMTP id q23mr1498207waj.212.1272019000492; Fri, 23 Apr 2010 03:36:40 -0700 (PDT) Received: from [192.168.1.100] ([114.84.71.49]) by mx.google.com with ESMTPS id 33sm4122680wad.17.2010.04.23.03.36.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 23 Apr 2010 03:36:40 -0700 (PDT) Subject: [PATCH v2 2/4] MIPS: in non-64bit kernel, using the generic atomic64 operations for perf counter support From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 23 Apr 2010 18:36:28 +0800 Message-ID: <1272018988.4662.94.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26465 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips 64bit kernel has already had its atomic64 functions. Except for that, we use the generic spinlocked version. The atomic64 types and related functions are needed for the Linux performance counter subsystem. Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 1 + arch/mips/include/asm/atomic.h | 4 ++++ 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 29e8692..469176c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,7 @@ config MIPS select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE select HAVE_OPROFILE + select GENERIC_ATOMIC64 if !64BIT select HAVE_ARCH_KGDB select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACE_MCOUNT_TEST diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 519197e..887a881 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -782,6 +782,10 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) */ #define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0) +#else /* CONFIG_64BIT */ + +#include + #endif /* CONFIG_64BIT */ /* -- 1.7.0.4 From dengcheng.zhu@gmail.com Fri Apr 23 12:37:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 12:37:34 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:39598 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492381Ab0DWKg7 (ORCPT ); Fri, 23 Apr 2010 12:36:59 +0200 Received: by mail-pw0-f49.google.com with SMTP id 3so1853372pwj.36 for ; Fri, 23 Apr 2010 03:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=BjTnXpdhf3gq4SVNF0VHKwAAKSE0hSUd7Z7hxsRGNQE=; b=qcHrgWic0xSv6ADQy2IojhiZGYPNPsi7pfrXh2kdlYOE11qbLq4S/lOp7TnLELHjfZ Z5FsJc2pjvkHvq1y/1wXVol18FxNmSGnRVwiH1iU0Nx1nP/1cNfRmtD4ga9fRi3bZj9P dVVN8ACS3n8BStpnycxLlPZNjvrU3Uf3fMvbs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=KvwBpqwOTFQf7gCoyrPZhz3Hog+8ZAqgQWNqrVdkU9Y3P4jqb3LLWryFa4IAQJalo1 /z1B0JFjXu5VDSZHvGGHTlkVKLw0QwmrM1CCqjHxVzi+nvxkN0LwXSZzegXXaDc24IEm MGAZGS5UaeV4+KTrJfWAVr/yr5GHTpnr0wi04= Received: by 10.115.114.37 with SMTP id r37mr3241934wam.97.1272019018494; Fri, 23 Apr 2010 03:36:58 -0700 (PDT) Received: from [192.168.1.100] ([114.84.71.49]) by mx.google.com with ESMTPS id 20sm945604pzk.15.2010.04.23.03.36.52 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 23 Apr 2010 03:36:57 -0700 (PDT) Subject: [PATCH v2 3/4] MIPS: adding support for software performance events From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 23 Apr 2010 18:36:46 +0800 Message-ID: <1272019006.4662.95.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26466 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips Software events are required as a part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 2 ++ arch/mips/kernel/traps.c | 18 +++++++++++++++--- arch/mips/kernel/unaligned.c | 5 +++++ arch/mips/math-emu/cp1emu.c | 3 +++ arch/mips/mm/fault.c | 11 +++++++++-- 5 files changed, 34 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 469176c..ebf2c79 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,8 @@ config MIPS select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE select HAVE_OPROFILE + select HAVE_PERF_EVENTS + select PERF_USE_VMALLOC select GENERIC_ATOMIC64 if !64BIT select HAVE_ARCH_KGDB select HAVE_FUNCTION_TRACER diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 1a4dd65..851705b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -557,10 +558,16 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) */ static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) { - if ((opcode & OPCODE) == LL) + if ((opcode & OPCODE) == LL) { + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, 0, regs, 0); return simulate_ll(regs, opcode); - if ((opcode & OPCODE) == SC) + } + if ((opcode & OPCODE) == SC) { + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, 0, regs, 0); return simulate_sc(regs, opcode); + } return -1; /* Must be something else ... */ } @@ -576,6 +583,8 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { int rd = (opcode & RD) >> 11; int rt = (opcode & RT) >> 16; + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, 0, regs, 0); switch (rd) { case 0: /* CPU number */ regs->regs[rt] = smp_processor_id(); @@ -611,8 +620,11 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) static int simulate_sync(struct pt_regs *regs, unsigned int opcode) { - if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) + if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, 0, regs, 0); return 0; + } return -1; /* Must be something else ... */ } diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 69b039c..a319c7a 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -78,6 +78,7 @@ #include #include #include +#include #include #include #include @@ -109,6 +110,8 @@ static void emulate_load_store_insn(struct pt_regs *regs, unsigned long value; unsigned int res; + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, 0, regs, 0); regs->regs[0] = 0; /* @@ -513,6 +516,8 @@ asmlinkage void do_ade(struct pt_regs *regs) unsigned int __user *pc; mm_segment_t seg; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, + 1, 0, regs, regs->cp0_badvaddr); /* * Did we catch a fault trying to load an instruction? * Or are we running in MIPS16 mode? diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 8f2f8e9..b3fa153 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -256,6 +257,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) } emul: + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, + 1, 0, xcp, 0); MIPS_FPU_EMU_INC_STATS(emulated); switch (MIPSInst_OPCODE(ir)) { case ldc1_op:{ diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index b78f7d9..5987d2b 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -18,6 +18,7 @@ #include #include /* For unblank_screen() */ #include +#include #include #include @@ -132,6 +133,7 @@ good_area: * the fault. */ fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -139,10 +141,15 @@ good_area: goto do_sigbus; BUG(); } - if (fault & VM_FAULT_MAJOR) + if (fault & VM_FAULT_MAJOR) { + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, + 1, 0, regs, address); tsk->maj_flt++; - else + } else { + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, + 1, 0, regs, address); tsk->min_flt++; + } up_read(&mm->mmap_sem); return; -- 1.7.0.4 From dengcheng.zhu@gmail.com Fri Apr 23 12:37:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Apr 2010 12:38:00 +0200 (CEST) Received: from mail-pw0-f49.google.com ([209.85.160.49]:39598 "EHLO mail-pw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492343Ab0DWKha (ORCPT ); Fri, 23 Apr 2010 12:37:30 +0200 Received: by mail-pw0-f49.google.com with SMTP id 3so1853372pwj.36 for ; Fri, 23 Apr 2010 03:37:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=1hiSMir+pxRv1UWzk0peHCw+WUrxi4sAuH30UUbw4E4=; b=glQG8nJPlI5Doe510SRBSg37ypd7NGrLwAw64rMd9V9t7Z39mUrSf040hKahlXH1/V 4kHiGCmMoFTwPgHvCior56tJPprnhJiNJaq6xIOUTv7ytzLG74c0ljY+9YDRNqeQT5zg masZcqKlZkO2nfgirNEVjDfYCupq3cDQYsC8s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=Hacsjo8FTwN6f4dMLLSVhwUfAxUtUrqYHn1UeJ+lbKg3XxcNdFj+07nS3V7dxfVqQ9 LNSZZ/RIxVzv9lzMo6S4Mr1WqMfrsn8ngiF0wRV5lSlFvlZ8LRmKIJ7QQhQZZMFiWWfU C6l6XD3vVN+vGDTxxCgwfzXpFt+jR+PEnxNi4= Received: by 10.115.39.17 with SMTP id r17mr235720waj.40.1272019049350; Fri, 23 Apr 2010 03:37:29 -0700 (PDT) Received: from [192.168.1.100] ([114.84.71.49]) by mx.google.com with ESMTPS id b4sm4121434wao.20.2010.04.23.03.37.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 23 Apr 2010 03:37:28 -0700 (PDT) Subject: [PATCH v2 4/4] MIPS: implementing hardware performance event support From: Deng-Cheng Zhu To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com Content-Type: text/plain; charset="UTF-8" Date: Fri, 23 Apr 2010 18:37:15 +0800 Message-ID: <1272019035.4662.97.camel@fun-lab> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26467 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips This patch is the HW perf event support. To enable this feature, we can not choose the SMTC kernel; Oprofile should be disabled; kernel performance events be selected. Then we can enable it in Kernel type menu. Oprofile for MIPS platforms initializes irq at arch init time. Currently we do not change this logic to allow PMU reservation. If a platform has EIC, we can use the irq base and perf counter irq offset defines for the interrupt controller in mipspmu_get_irq(). Besides generic hardware events and cache events, raw events are also supported by this patch. Please refer to processor core software user's manual and the comments for mipsxx_pmu_map_raw_event() for more details. Signed-off-by: Deng-Cheng Zhu --- arch/mips/Kconfig | 8 + arch/mips/include/asm/perf_event.h | 28 ++ arch/mips/kernel/Makefile | 2 + arch/mips/kernel/perf_event.c | 557 ++++++++++++++++++++++ arch/mips/kernel/perf_event_mipsxx.c | 871 ++++++++++++++++++++++++++++++++++ 5 files changed, 1466 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/perf_event.h create mode 100644 arch/mips/kernel/perf_event.c create mode 100644 arch/mips/kernel/perf_event_mipsxx.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ebf2c79..ff1bb5d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1857,6 +1857,14 @@ config NODES_SHIFT default "6" depends on NEED_MULTIPLE_NODES +config HW_PERF_EVENTS + bool "Enable hardware performance counter support for perf events" + depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32 + default y + help + Enable hardware performance counter support for perf events. If + disabled, perf events will use software events only. + source "mm/Kconfig" config SMP diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h new file mode 100644 index 0000000..bcf54bc --- /dev/null +++ b/arch/mips/include/asm/perf_event.h @@ -0,0 +1,28 @@ +/* + * linux/arch/mips/include/asm/perf_event.h + * + * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __MIPS_PERF_EVENT_H__ +#define __MIPS_PERF_EVENT_H__ + +extern int (*perf_irq)(void); + +/* + * MIPS performance counters do not raise NMI upon overflow, a regular + * interrupt will be signaled. Hence we can do the pending perf event + * work at the tail of the irq handler. + */ +static inline void +set_perf_event_pending(void) +{ +} + +#endif /* __MIPS_PERF_EVENT_H__ */ + diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 7a6ac50..c934ab7 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -101,6 +101,8 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/ +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o + EXTRA_CFLAGS += -Werror CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c new file mode 100644 index 0000000..a17dc64 --- /dev/null +++ b/arch/mips/kernel/perf_event.c @@ -0,0 +1,557 @@ +/* + * Linux performance counter support for MIPS. + * + * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu + * + * This code is based on the implementation for ARM, which is in turn + * based on the sparc64 perf event code and the x86 code. Performance + * counter access is based on the MIPS Oprofile code. And the callchain + * support references the code of MIPS traps.c. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +#define MAX_PERIOD ((1ULL << 32) - 1) + +struct cpu_hw_events { + /* Array of events on this cpu. */ + struct perf_event *events[MIPS_MAX_HWEVENTS]; + + /* + * Set the bit (indexed by the counter number) when the counter + * is used for an event. + */ + unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; + + /* + * The borrowed MSB for the performance counter. A MIPS performance + * counter uses its bit 31 as a factor of determining whether a counter + * overflow should be signaled. So here we use a separate MSB for each + * counter to make things easy. + */ + unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; + + /* + * Software copy of the control register for each performance counter. + * MIPS CPUs vary in performance counters. They use this differently, + * and even may not use it. + */ + unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; +}; +DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { + .saved_ctrl = {0}, +}; + +/* The description of MIPS performance events. */ +struct mips_perf_event { + unsigned int event_id; + unsigned int cntr_mask; + #define CNTR_EVEN 0x55555555 + #define CNTR_ODD 0xaaaaaaaa +#ifdef CONFIG_MIPS_MT_SMP + enum { + T = 0, + V = 1, + P = 2, + } range; +#else + #define T + #define V + #define P +#endif +}; + +static struct mips_perf_event raw_event; +static DEFINE_MUTEX(raw_event_mutex); + +#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff +#define C(x) PERF_COUNT_HW_CACHE_##x + +struct mips_pmu { + const char *name; + irqreturn_t (*handle_irq)(int irq, void *dev); + int (*handle_shared_irq)(void); + void (*start)(void); + void (*stop)(void); + int (*alloc_counter)(struct cpu_hw_events *cpuc, + struct hw_perf_event *hwc); + unsigned int (*read_counter)(unsigned int idx); + void (*write_counter)(unsigned int idx, unsigned int val); + void (*enable_event)(struct hw_perf_event *evt, int idx); + void (*disable_event)(int idx); + const struct mips_perf_event *(*map_raw_event)(u64 config); + const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; + const struct mips_perf_event (*cache_event_map) + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + unsigned int num_counters; +}; + +static const struct mips_pmu *mipspmu; + +static int +mipspmu_event_set_period(struct perf_event *event, + struct hw_perf_event *hwc, + int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + s64 left = atomic64_read(&hwc->period_left); + s64 period = hwc->sample_period; + int ret = 0; + unsigned long flags, uleft; + + if (unlikely(left <= -period)) { + left = period; + atomic64_set(&hwc->period_left, left); + hwc->last_period = period; + ret = 1; + } + + if (unlikely(left <= 0)) { + left += period; + atomic64_set(&hwc->period_left, left); + hwc->last_period = period; + ret = 1; + } + + if (left > (s64)MAX_PERIOD) + left = MAX_PERIOD; + + atomic64_set(&hwc->prev_count, (u64)-left); + + local_irq_save(flags); + uleft = (u64)(-left) & 0xffffffff; + test_bit(31, &uleft) ? + set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs); + mipspmu->write_counter(idx, (u64)(-left) & 0x7fffffff); + local_irq_restore(flags); + + perf_event_update_userpage(event); + + return ret; +} + +static int mipspmu_enable(struct perf_event *event) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct hw_perf_event *hwc = &event->hw; + int idx; + int err = 0; + + /* To look for a free counter for this event. */ + idx = mipspmu->alloc_counter(cpuc, hwc); + if (idx < 0) { + err = idx; + goto out; + } + + /* + * If there is an event in the counter we are going to use then + * make sure it is disabled. + */ + event->hw.idx = idx; + mipspmu->disable_event(idx); + cpuc->events[idx] = event; + + /* Set the period for the event. */ + mipspmu_event_set_period(event, hwc, idx); + + /* Enable the event. */ + mipspmu->enable_event(hwc, idx); + + /* Propagate our changes to the userspace mapping. */ + perf_event_update_userpage(event); + +out: + return err; +} + +static void mipspmu_event_update(struct perf_event *event, + struct hw_perf_event *hwc, + int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + int shift = 64 - 32; + s64 prev_raw_count, new_raw_count; + s64 delta; + +again: + prev_raw_count = atomic64_read(&hwc->prev_count); + local_irq_save(flags); + /* Make the counter value be a "real" one. */ + new_raw_count = mipspmu->read_counter(idx); + if (new_raw_count & (test_bit(idx, cpuc->msbs) << 31)) { + new_raw_count &= 0x7fffffff; + clear_bit(idx, cpuc->msbs); + } else + new_raw_count |= (test_bit(idx, cpuc->msbs) << 31); + local_irq_restore(flags); + + if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, + new_raw_count) != prev_raw_count) + goto again; + + delta = (new_raw_count << shift) - (prev_raw_count << shift); + delta >>= shift; + + atomic64_add(delta, &event->count); + atomic64_sub(delta, &hwc->period_left); + + return; +} + +static void mipspmu_disable(struct perf_event *event) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + /* We are working on a local event. */ + mipspmu->disable_event(idx); + + barrier(); + + mipspmu_event_update(event, hwc, idx); + cpuc->events[idx] = NULL; + clear_bit(idx, cpuc->used_mask); + + perf_event_update_userpage(event); +} + +static void mipspmu_unthrottle(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + + mipspmu->enable_event(hwc, hwc->idx); +} + +static void mipspmu_read(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + + /* Don't read disabled counters! */ + if (hwc->idx < 0) + return; + + mipspmu_event_update(event, hwc, hwc->idx); +} + +static struct pmu pmu = { + .enable = mipspmu_enable, + .disable = mipspmu_disable, + .unthrottle = mipspmu_unthrottle, + .read = mipspmu_read, +}; + +static atomic_t active_events = ATOMIC_INIT(0); +static DEFINE_MUTEX(pmu_reserve_mutex); +static int mips_pmu_irq = -1; + +static int mipspmu_get_irq(void) +{ + int err; + + if (cpu_has_veic) { + /* + * Using platform specific interrupt controller defines. + */ +#ifdef MSC01E_INT_BASE + mips_pmu_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; +#endif + } else if (cp0_perfcount_irq >= 0) { + /* + * Some CPUs have explicitly defined their perfcount irq. + */ +#if defined(CONFIG_CPU_RM9000) + mips_pmu_irq = rm9000_perfcount_irq; +#elif defined(CONFIG_CPU_LOONGSON2) + mips_pmu_irq = LOONGSON2_PERFCNT_IRQ; +#else + mips_pmu_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; +#endif + } + + if (mips_pmu_irq >= 0) { + /* Request my own irq handler. */ + err = request_irq(mips_pmu_irq, mipspmu->handle_irq, + IRQF_DISABLED | IRQF_NOBALANCING, + "mips_perf_pmu", NULL); + if (err) { + pr_warning("Unable to request IRQ%d for MIPS " + "performance counters!\n", mips_pmu_irq); + } + } else if (cp0_perfcount_irq < 0) { + /* + * We are sharing the irq number with the timer interrupt. + */ + save_perf_irq = perf_irq; + perf_irq = mipspmu->handle_shared_irq; + err = 0; + } else { + pr_warning("The platform hasn't properly defined its " + "interrupt controller.\n"); + err = -ENOENT; + } + + return err; +} + +static void mipspmu_free_irq(void) +{ + if (mips_pmu_irq >= 0) + free_irq(mips_pmu_irq, NULL); + else if (cp0_perfcount_irq < 0) + perf_irq = save_perf_irq; + + mips_pmu_irq = -1; +} + +static inline unsigned int +mipspmu_perf_event_encode(const struct mips_perf_event *pev) +{ +/* + * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for + * event_id. + */ +#ifdef CONFIG_MIPS_MT_SMP + return ((unsigned int)pev->range << 24) | + (pev->cntr_mask & 0xffff00) | + (pev->event_id & 0xff); +#else + return (pev->cntr_mask & 0xffff00) | + (pev->event_id & 0xff); +#endif +} + +static const struct mips_perf_event * +mipspmu_map_general_event(int idx) +{ + const struct mips_perf_event *pev; + + pev = ((*mipspmu->general_event_map)[idx].event_id == + UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) : + &(*mipspmu->general_event_map)[idx]); + + return pev; +} + +static const struct mips_perf_event * +mipspmu_map_cache_event(u64 config) +{ + unsigned int cache_type, cache_op, cache_result; + const struct mips_perf_event *pev; + + cache_type = (config >> 0) & 0xff; + if (cache_type >= PERF_COUNT_HW_CACHE_MAX) + return ERR_PTR(-EINVAL); + + cache_op = (config >> 8) & 0xff; + if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) + return ERR_PTR(-EINVAL); + + cache_result = (config >> 16) & 0xff; + if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) + return ERR_PTR(-EINVAL); + + pev = &((*mipspmu->cache_event_map) + [cache_type] + [cache_op] + [cache_result]); + + if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID) + return ERR_PTR(-EOPNOTSUPP); + + return pev; + +} + +static int validate_event(struct cpu_hw_events *cpuc, + struct perf_event *event) +{ + struct hw_perf_event fake_hwc = event->hw; + + if (event->pmu && event->pmu != &pmu) + return 0; + + return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0; +} + +static int validate_group(struct perf_event *event) +{ + struct perf_event *sibling, *leader = event->group_leader; + struct cpu_hw_events fake_cpuc; + + memset(&fake_cpuc, 0, sizeof(fake_cpuc)); + + if (!validate_event(&fake_cpuc, leader)) + return -ENOSPC; + + list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + if (!validate_event(&fake_cpuc, sibling)) + return -ENOSPC; + } + + if (!validate_event(&fake_cpuc, event)) + return -ENOSPC; + + return 0; +} + +/* + * mipsxx/rm9000/loongson2 have different performance counters, they have + * specific low-level init routines. + */ +static int __hw_perf_event_init(struct perf_event *event); + +static void hw_perf_event_destroy(struct perf_event *event); + +const struct pmu *hw_perf_event_init(struct perf_event *event) +{ + int err = 0; + + if (!mipspmu || event->cpu >= nr_cpumask_bits || + (event->cpu >= 0 && !cpu_online(event->cpu))) + return ERR_PTR(-ENODEV); + + if (!atomic_inc_not_zero(&active_events)) { + if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) { + atomic_dec(&active_events); + return ERR_PTR(-ENOSPC); + } + + mutex_lock(&pmu_reserve_mutex); + if (atomic_read(&active_events) == 0) + err = mipspmu_get_irq(); + + if (!err) + atomic_inc(&active_events); + mutex_unlock(&pmu_reserve_mutex); + } + + if (err) + return ERR_PTR(err); + + err = __hw_perf_event_init(event); + if (err) + hw_perf_event_destroy(event); + + return err ? ERR_PTR(err) : &pmu; +} + +#include "perf_event_mipsxx.c" + +/* + * Callchain handling code. + */ +static inline void +callchain_store(struct perf_callchain_entry *entry, + u64 ip) +{ + if (entry->nr < PERF_MAX_STACK_DEPTH) + entry->ip[entry->nr++] = ip; +} + +static void +perf_callchain_user(struct pt_regs *regs, + struct perf_callchain_entry *entry) +{ + unsigned long *sp; + unsigned long addr; + + callchain_store(entry, PERF_CONTEXT_USER); + + if (!user_mode(regs)) + regs = task_pt_regs(current); + + sp = (unsigned long *)(regs->regs[29] & ~3); + + while (!kstack_end(sp)) { + unsigned long __user *p = + (unsigned long __user *)(unsigned long)sp++; + if (__get_user(addr, p)) { + pr_warning("Performance counter callchain " + "suppport: Bad stack address.\n"); + break; + } + callchain_store(entry, addr); + } +} + +static void +perf_callchain_kernel(struct pt_regs *regs, + struct perf_callchain_entry *entry) +{ + unsigned long sp = regs->regs[29]; + unsigned long ra = regs->regs[31]; + unsigned long pc = regs->cp0_epc; + + if (unlikely(!__kernel_text_address(pc))) { + pr_warning("Performance counter callchain support " + "error.\n"); + return; + } + + callchain_store(entry, PERF_CONTEXT_KERNEL); + + do { + callchain_store(entry, pc); + pc = unwind_stack(current, &sp, pc, &ra); + } while (pc); +} + +static void +perf_do_callchain(struct pt_regs *regs, + struct perf_callchain_entry *entry) +{ + int is_user; + + if (!regs) + return; + + is_user = user_mode(regs); + + if (!current || !current->pid) + return; + + if (is_user && current->state != TASK_RUNNING) + return; + + if (!is_user) + perf_callchain_kernel(regs, entry); + + if (current->mm) + perf_callchain_user(regs, entry); +} + +static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); + +struct perf_callchain_entry * +perf_callchain(struct pt_regs *regs) +{ + struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry); + + entry->nr = 0; + perf_do_callchain(regs, entry); + return entry; +} + diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c new file mode 100644 index 0000000..750efb4 --- /dev/null +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -0,0 +1,871 @@ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \ + defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1) + +#define M_PERFCTL_COUNT_EVENT_WHENEVER \ + (M_PERFCTL_EXL | M_PERFCTL_KERNEL | \ + M_PERFCTL_USER | M_PERFCTL_SUPERVISOR | \ + M_PERFCTL_INTERRUPT_ENABLE) + +#ifdef CONFIG_MIPS_MT_SMP +#define M_PERFCTL_CONFIG_MASK 0x3fff801f +#else +#define M_PERFCTL_CONFIG_MASK 0x1f +#endif +#define M_PERFCTL_EVENT_MASK 0xfe0 + +static inline unsigned int +mipsxx_pmu_read_counter(unsigned int idx) +{ + switch (idx) { + case 0: + return r_c0_perfcntr0(); + case 1: + return r_c0_perfcntr1(); + case 2: + return r_c0_perfcntr2(); + case 3: + return r_c0_perfcntr3(); + default: + WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); + return 0; + } +} + +static inline void +mipsxx_pmu_write_counter(unsigned int idx, unsigned int val) +{ + switch (idx) { + case 0: + w_c0_perfcntr0(val); + return; + case 1: + w_c0_perfcntr1(val); + return; + case 2: + w_c0_perfcntr2(val); + return; + case 3: + w_c0_perfcntr3(val); + return; + } +} + +static inline unsigned int +mipsxx_pmu_read_control(unsigned int idx) +{ + switch (idx) { + case 0: + return r_c0_perfctrl0(); + case 1: + return r_c0_perfctrl1(); + case 2: + return r_c0_perfctrl2(); + case 3: + return r_c0_perfctrl3(); + default: + WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); + return 0; + } +} + +static inline void +mipsxx_pmu_write_control(unsigned int idx, unsigned int val) +{ + switch (idx) { + case 0: + w_c0_perfctrl0(val); + return; + case 1: + w_c0_perfctrl1(val); + return; + case 2: + w_c0_perfctrl2(val); + return; + case 3: + w_c0_perfctrl3(val); + return; + } +} + +#ifdef CONFIG_MIPS_MT_SMP +static DEFINE_RWLOCK(pmuint_rwlock); +#endif + +/* 24K/34K/1004K cores can share the same event map. */ +static const struct mips_perf_event mipsxxcore_event_map + [PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, + [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, + [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, + [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, + [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, +}; + +/* 74K core has different branch event code. */ +static const struct mips_perf_event mipsxx74Kcore_event_map + [PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, + [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, + [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, + [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, + [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, +}; + +/* 24K/34K/1004K cores can share the same cache event map. */ +static const struct mips_perf_event mipsxxcore_cache_map + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { +[C(L1D)] = { + /* + * Like some other architectures (e.g. ARM), the performance + * counters don't differentiate between read and write + * accesses/misses, so this isn't strictly correct, but it's the + * best we can do. Writes and reads get combined. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, + /* + * Note that MIPS has only "hit" events countable for + * the prefetch operation. + */ + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(DTLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(BPU)] = { + /* Using the same code for *HW_BRANCH* */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +}; + +/* 74K core has completely different cache event map. */ +static const struct mips_perf_event mipsxx74Kcore_cache_map + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { +[C(L1D)] = { + /* + * Like some other architectures (e.g. ARM), the performance + * counters don't differentiate between read and write + * accesses/misses, so this isn't strictly correct, but it's the + * best we can do. Writes and reads get combined. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, + [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, + [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, + /* + * Note that MIPS has only "hit" events countable for + * the prefetch operation. + */ + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, + [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(DTLB)] = { + /* 74K core does not have specific DTLB events. */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(BPU)] = { + /* Using the same code for *HW_BRANCH* */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, + [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +}; + +#ifdef CONFIG_MIPS_MT_SMP +static void +check_and_calc_range(struct perf_event *event, + const struct mips_perf_event *pev) +{ + struct hw_perf_event *hwc = &event->hw; + + if (event->cpu >= 0) { + if (pev->range > V) { + /* + * The user selected an event that is processor + * wide, while expecting it to be VPE wide. + */ + hwc->config_base |= M_TC_EN_ALL; + } else { + /* + * FIXME: cpu_data[event->cpu].vpe_id reports 0 + * for both CPUs. + */ + hwc->config_base |= M_PERFCTL_VPEID(event->cpu); + hwc->config_base |= M_TC_EN_VPE; + } + } else + hwc->config_base |= M_TC_EN_ALL; +} +#else +static void +check_and_calc_range(struct perf_event *event, + const struct mips_perf_event *pev) +{ +} +#endif + +static void hw_perf_event_destroy(struct perf_event *event) +{ + if (atomic_dec_and_mutex_lock(&active_events, + &pmu_reserve_mutex)) { + /* + * We must not call the destroy function with interrupts + * disabled. + */ + on_each_cpu(reset_counters, + (void *)(long)mipspmu->num_counters, 1); + mipspmu_free_irq(); + mutex_unlock(&pmu_reserve_mutex); + } +} + +static int __hw_perf_event_init(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + struct hw_perf_event *hwc = &event->hw; + const struct mips_perf_event *pev; + int err; + + /* Returning MIPS event descriptor for generic perf event. */ + if (PERF_TYPE_HARDWARE == event->attr.type) { + if (event->attr.config >= PERF_COUNT_HW_MAX) + return -EINVAL; + pev = mipspmu_map_general_event(event->attr.config); + } else if (PERF_TYPE_HW_CACHE == event->attr.type) { + pev = mipspmu_map_cache_event(event->attr.config); + } else if (PERF_TYPE_RAW == event->attr.type) { + /* We are working on the global raw event. */ + mutex_lock(&raw_event_mutex); + pev = mipspmu->map_raw_event(event->attr.config); + } else { + /* The event type is not (yet) supported. */ + return -EOPNOTSUPP; + } + + if (IS_ERR(pev)) { + if (PERF_TYPE_RAW == event->attr.type) + mutex_unlock(&raw_event_mutex); + return PTR_ERR(pev); + } + + /* + * We allow max flexibility on how each individual counter shared + * by the single CPU operates (the mode exclusion and the range). + */ + hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE; + + /* Calculate range bits and validate it. */ + if (num_possible_cpus() > 1) + check_and_calc_range(event, pev); + + hwc->event_base = mipspmu_perf_event_encode(pev); + if (PERF_TYPE_RAW == event->attr.type) + mutex_unlock(&raw_event_mutex); + + if (!attr->exclude_user) + hwc->config_base |= M_PERFCTL_USER; + if (!attr->exclude_kernel) { + hwc->config_base |= M_PERFCTL_KERNEL; + /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */ + hwc->config_base |= M_PERFCTL_EXL; + } + if (!attr->exclude_hv) + hwc->config_base |= M_PERFCTL_SUPERVISOR; + + hwc->config_base &= M_PERFCTL_CONFIG_MASK; + /* + * The event can belong to another cpu. We do not assign a local + * counter for it for now. + */ + hwc->idx = -1; + hwc->config = 0; + + if (!hwc->sample_period) { + hwc->sample_period = MAX_PERIOD; + hwc->last_period = hwc->sample_period; + atomic64_set(&hwc->period_left, hwc->sample_period); + } + + err = 0; + if (event->group_leader != event) { + err = validate_group(event); + if (err) + return -EINVAL; + } + + event->destroy = hw_perf_event_destroy; + + return err; +} + +void hw_perf_enable(void) +{ + if (mipspmu) + mipspmu->start(); +} + +void hw_perf_disable(void) +{ + if (mipspmu) + mipspmu->stop(); +} + +static void +handle_associated_event(struct cpu_hw_events *cpuc, + int idx, struct perf_sample_data *data, struct pt_regs *regs) +{ + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc = &event->hw; + + mipspmu_event_update(event, hwc, idx); + data->period = event->hw.last_period; + if (!mipspmu_event_set_period(event, hwc, idx)) + return; + + if (perf_event_overflow(event, 0, data, regs)) + mipspmu->disable_event(idx); +} + +static void pause_local_counters(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + int counters = mipspmu->num_counters; + unsigned long flags; + + local_irq_save(flags); + switch (counters) { + case 4: + cpuc->saved_ctrl[3] = r_c0_perfctrl3(); + w_c0_perfctrl3(cpuc->saved_ctrl[3] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + case 3: + cpuc->saved_ctrl[2] = r_c0_perfctrl2(); + w_c0_perfctrl2(cpuc->saved_ctrl[2] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + case 2: + cpuc->saved_ctrl[1] = r_c0_perfctrl1(); + w_c0_perfctrl1(cpuc->saved_ctrl[1] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + case 1: + cpuc->saved_ctrl[0] = r_c0_perfctrl0(); + w_c0_perfctrl0(cpuc->saved_ctrl[0] & + ~M_PERFCTL_COUNT_EVENT_WHENEVER); + } + local_irq_restore(flags); +} + +static void resume_local_counters(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + int counters = mipspmu->num_counters; + unsigned long flags; + + local_irq_save(flags); + switch (counters) { + case 4: + w_c0_perfctrl3(cpuc->saved_ctrl[3]); + case 3: + w_c0_perfctrl2(cpuc->saved_ctrl[2]); + case 2: + w_c0_perfctrl1(cpuc->saved_ctrl[1]); + case 1: + w_c0_perfctrl0(cpuc->saved_ctrl[0]); + } + local_irq_restore(flags); +} + +static int mipsxx_pmu_handle_shared_irq(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct perf_sample_data data; + unsigned int counters = mipspmu->num_counters; + unsigned int counter; + int handled = IRQ_NONE; + struct pt_regs *regs; + + if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) + return handled; + + /* + * First we pause the local counters, so that when we are locked + * here, the counters are all paused. When it gets locked due to + * perf_disable(), the timer interrupt handler will be delayed. + * + * See also mipsxx_pmu_start(). + */ + pause_local_counters(); +#ifdef CONFIG_MIPS_MT_SMP + read_lock(&pmuint_rwlock); +#endif + + regs = get_irq_regs(); + + perf_sample_data_init(&data, 0); + + switch (counters) { +#define HANDLE_COUNTER(n) \ + case n + 1: \ + if (test_bit(n, cpuc->used_mask)) { \ + counter = r_c0_perfcntr ## n(); \ + if (counter & M_COUNTER_OVERFLOW) { \ + w_c0_perfcntr ## n(counter & \ + 0x7fffffff); \ + if (test_and_change_bit(n, cpuc->msbs)) \ + handle_associated_event(cpuc, \ + n, &data, regs); \ + handled = IRQ_HANDLED; \ + } \ + } + HANDLE_COUNTER(3) + HANDLE_COUNTER(2) + HANDLE_COUNTER(1) + HANDLE_COUNTER(0) + } + + /* + * Do all the work for the pending perf events. We can do this + * in here because the performance counter interrupt is a regular + * interrupt, not NMI. + */ + if (handled == IRQ_HANDLED) + perf_event_do_pending(); + +#ifdef CONFIG_MIPS_MT_SMP + read_unlock(&pmuint_rwlock); +#endif + resume_local_counters(); + return handled; +} + +static irqreturn_t +mipsxx_pmu_handle_irq(int irq, void *dev) +{ + return mipsxx_pmu_handle_shared_irq(); +} + +static void mipsxx_pmu_start(void) +{ +#ifdef CONFIG_MIPS_MT_SMP + write_unlock(&pmuint_rwlock); +#endif + resume_local_counters(); +} + +/* + * MIPS performance counters can be per-TC. The control registers can + * not be directly accessed accross CPUs. Hence if we want to do global + * control, we need cross CPU calls. on_each_cpu() can help us, but we + * can not make sure this function is called with interrupts enabled. So + * here we pause local counters and then grab a rwlock and leave the + * counters on other CPUs alone. If any counter interrupt raises while + * we own the write lock, simply pause local counters on that CPU and + * spin in the handler. Also we know we won't be switched to another + * CPU after pausing local counters and before grabbing the lock. + */ +static void mipsxx_pmu_stop(void) +{ + pause_local_counters(); +#ifdef CONFIG_MIPS_MT_SMP + write_lock(&pmuint_rwlock); +#endif +} + +static int +mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, + struct hw_perf_event *hwc) +{ + int i; + + /* + * We only need to care the counter mask. The range has been + * checked definitely. + */ + unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; + + for (i = mipspmu->num_counters - 1; i >= 0; i--) { + /* + * Note that some MIPS perf events can be counted by both + * even and odd counters, wheresas many other are only by + * even _or_ odd counters. This introduces an issue that + * when the former kind of event takes the counter the + * latter kind of event wants to use, then the "counter + * allocation" for the latter event will fail. In fact if + * they can be dynamically swapped, they both feel happy. + * But here we leave this issue alone for now. + */ + if (test_bit(i, &cntr_mask) && + !test_and_set_bit(i, cpuc->used_mask)) + return i; + } + + return -EAGAIN; +} + +static void +mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + local_irq_save(flags); + cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | + (evt->config_base & M_PERFCTL_CONFIG_MASK) | + /* Make sure interrupt enabled. */ + M_PERFCTL_INTERRUPT_ENABLE; + /* + * We do not actually let the counter run. Leave it until start(). + */ + local_irq_restore(flags); +} + +static void +mipsxx_pmu_disable_event(int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + local_irq_save(flags); + cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & + ~M_PERFCTL_COUNT_EVENT_WHENEVER; + mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); + local_irq_restore(flags); +} + +#define IS_UNSUPPORTED_24K_EVENT(r, b) \ + ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \ + (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \ + (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \ + (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \ + ((b) >= 68 && (b) <= 127)) +#define IS_BOTH_COUNTERS_24K_EVENT(b) \ + ((b) == 0 || (b) == 1 || (b) == 11) + +#define IS_UNSUPPORTED_34K_EVENT(r, b) \ + ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \ + (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \ + ((b) >= 68 && (b) <= 127)) +#define IS_BOTH_COUNTERS_34K_EVENT(b) \ + ((b) == 0 || (b) == 1 || (b) == 11) +#ifdef CONFIG_MIPS_MT_SMP +#define IS_RANGE_P_34K_EVENT(r, b) \ + ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ + (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \ + (r) == 176 || ((b) >= 50 && (b) <= 55) || \ + ((b) >= 64 && (b) <= 67)) +#define IS_RANGE_V_34K_EVENT(r) \ + ((r) == 47) +#endif + +#define IS_UNSUPPORTED_74K_EVENT(r, b) \ + ((r) == 5 || ((r) >= 135 && (r) <= 137) || \ + ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \ + (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \ + (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \ + (b) == 61 || (r) == 62 || (r) == 191 || \ + ((b) >= 64 && (b) <= 127)) +#define IS_BOTH_COUNTERS_74K_EVENT(b) \ + ((b) == 0 || (b) == 1) + +/* + * User can use 0-255 raw events, where 0-127 for the events of even + * counters, and 128-255 for odd counters. Note that bit 7 is used to + * indicate the parity. So, for example, when user wants to take the + * Event Num of 15 for odd counters (by referring to the user manual), + * then 128 needs to be added to 15 as the input for the event config, + * i.e., 143 (0x8F) to be used. + */ +static const struct mips_perf_event * +mipsxx_pmu_map_raw_event(u64 config) +{ + unsigned int raw_id = config & 0xff; + unsigned int base_id = raw_id & 0x7f; + + switch (current_cpu_type()) { + case CPU_24K: + if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id)) + return ERR_PTR(-EOPNOTSUPP); + raw_event.event_id = base_id; + if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) + raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; + else + raw_event.cntr_mask = + raw_id > 127 ? CNTR_ODD : CNTR_EVEN; +#ifdef CONFIG_MIPS_MT_SMP + /* + * This is actually doing nothing. Non-multithreading + * CPUs will not check and calculate the range. + */ + raw_event.range = P; +#endif + break; + case CPU_34K: + if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id)) + return ERR_PTR(-EOPNOTSUPP); + raw_event.event_id = base_id; + if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) + raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; + else + raw_event.cntr_mask = + raw_id > 127 ? CNTR_ODD : CNTR_EVEN; +#ifdef CONFIG_MIPS_MT_SMP + if (IS_RANGE_P_34K_EVENT(raw_id, base_id)) + raw_event.range = P; + else if (IS_RANGE_V_34K_EVENT(raw_id)) + raw_event.range = V; + else + raw_event.range = T; +#endif + break; + case CPU_74K: + if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id)) + return ERR_PTR(-EOPNOTSUPP); + raw_event.event_id = base_id; + if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) + raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; + else + raw_event.cntr_mask = + raw_id > 127 ? CNTR_ODD : CNTR_EVEN; +#ifdef CONFIG_MIPS_MT_SMP + raw_event.range = P; +#endif + break; + } + + return &raw_event; +} + +static struct mips_pmu mipsxxcore_pmu = { + .handle_irq = mipsxx_pmu_handle_irq, + .handle_shared_irq = mipsxx_pmu_handle_shared_irq, + .start = mipsxx_pmu_start, + .stop = mipsxx_pmu_stop, + .alloc_counter = mipsxx_pmu_alloc_counter, + .read_counter = mipsxx_pmu_read_counter, + .write_counter = mipsxx_pmu_write_counter, + .enable_event = mipsxx_pmu_enable_event, + .disable_event = mipsxx_pmu_disable_event, + .map_raw_event = mipsxx_pmu_map_raw_event, + .general_event_map = &mipsxxcore_event_map, + .cache_event_map = &mipsxxcore_cache_map, +}; + +static struct mips_pmu mipsxx74Kcore_pmu = { + .handle_irq = mipsxx_pmu_handle_irq, + .handle_shared_irq = mipsxx_pmu_handle_shared_irq, + .start = mipsxx_pmu_start, + .stop = mipsxx_pmu_stop, + .alloc_counter = mipsxx_pmu_alloc_counter, + .read_counter = mipsxx_pmu_read_counter, + .write_counter = mipsxx_pmu_write_counter, + .enable_event = mipsxx_pmu_enable_event, + .disable_event = mipsxx_pmu_disable_event, + .map_raw_event = mipsxx_pmu_map_raw_event, + .general_event_map = &mipsxx74Kcore_event_map, + .cache_event_map = &mipsxx74Kcore_cache_map, +}; + +static int __init +init_hw_perf_events(void) +{ + int counters; + + pr_info("Performance counters: "); + + counters = n_counters(); + if (counters == 0) { + pr_cont("No available PMU.\n"); + return -ENODEV; + } + +#ifdef CONFIG_MIPS_MT_SMP + cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19); + if (!cpu_has_mipsmt_pertccounters) + counters = counters_total_to_per_cpu(counters); +#endif + + on_each_cpu(reset_counters, (void *)(long)counters, 1); + + switch (current_cpu_type()) { + case CPU_24K: + mipsxxcore_pmu.name = "mips/24K"; + mipsxxcore_pmu.num_counters = counters; + mipspmu = &mipsxxcore_pmu; + break; + case CPU_34K: + mipsxxcore_pmu.name = "mips/34K"; + mipsxxcore_pmu.num_counters = counters; + mipspmu = &mipsxxcore_pmu; + break; + case CPU_74K: + mipsxx74Kcore_pmu.name = "mips/74K"; + mipsxx74Kcore_pmu.num_counters = counters; + mipspmu = &mipsxx74Kcore_pmu; + break; + default: + pr_cont("Either hardware does not support performance " + "counters, or not yet implemented.\n"); + return -ENODEV; + } + + if (mipspmu) + pr_cont("%s PMU enabled, %d counters available to each " + "CPU\n", mipspmu->name, mipspmu->num_counters); + + return 0; +} +arch_initcall(init_hw_perf_events); + +#endif -- 1.7.0.4 From aba@not.so.argh.org Sun Apr 25 15:54:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Apr 2010 15:55:04 +0200 (CEST) Received: from alius.ayous.org ([78.46.213.165]:53517 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491970Ab0DYNy6 (ORCPT ); Sun, 25 Apr 2010 15:54:58 +0200 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1O62IQ-0007SJ-2V; Sun, 25 Apr 2010 13:54:54 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1O62IK-0000gY-3o; Sun, 25 Apr 2010 15:54:48 +0200 Date: Sun, 25 Apr 2010 15:54:48 +0200 From: Andreas Barth To: David Daney , linux-mips@linux-mips.org Subject: Re: irqbalance on movidis crashes the machine (was: movidis x16 hard lockup using 2.6.33) Message-ID: <20100425135448.GA2631@mails.so.argh.org> References: <20100326184132.GU2437@apfelkorn> <4BAD03A5.9070701@caviumnetworks.com> <20100327230744.GG27216@mails.so.argh.org> <4BB0DB2A.9080405@caviumnetworks.com> <20100402133224.GR27216@mails.so.argh.org> <20100403154312.GY2437@apfelkorn> <20100415184312.GK2942@mails.so.argh.org> <20100415203550.GA32686@mails.so.argh.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100415203550.GA32686@mails.so.argh.org> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26468 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips * Andreas Barth (aba@not.so.argh.org) [100415 22:35]: > * Andreas Barth (aba@not.so.argh.org) [100415 20:43]: > > * Peter 'p2' De Schrijver (p2@debian.org) [100403 17:43]: > > > http://zobel.ftbfs.de/.x/lucatelli-nmi-watchdog-output.txt > > > Dump of one of those hangs. Most cores seem to be stuck in wait > > > (0xffffffff81100b80), except for core 1 which is in octeon_irq_ciu0_ack > > > (octeon_irq_ciu0_ack). > > > > On further investigation we found out that this happens when > > irqbalance is started. The version of irqbalance being run is 0.55. > > > > We removed this program from the affected machine, but of course this > > still should be fixed (and we still get a few reboots on another > > machine without irqbalance). > > Clarification: > > Running irqbalance itself doesn't crash the machine, but increases the > probability of crashes dramatically. Usually the next few (< 10) > commands crash the machine. > > The crashs however look similar to the ones we have without irqbalance > - just way less often then with irqbalance. This seems like irqbalance > exposes the crash way better than we do without. Any ideas what we could do to reduce the number of crashes we experience? Andi From ypolyans@princeton.edu Mon Apr 26 06:53:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 06:53:42 +0200 (CEST) Received: from ppa04.Princeton.EDU ([128.112.128.215]:37523 "EHLO ppa04.Princeton.EDU" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491057Ab0DZExh (ORCPT ); Mon, 26 Apr 2010 06:53:37 +0200 Received: from smtpserver1.Princeton.EDU (smtpserver1.Princeton.EDU [128.112.129.65]) by ppa04.Princeton.EDU (8.14.3/8.14.3) with ESMTP id o3Q4rZ5r006375; Mon, 26 Apr 2010 00:53:35 -0400 Received: from tetra.ee.Princeton.EDU (tetra.ee.Princeton.EDU [128.112.49.188]) (authenticated bits=0) by smtpserver1.Princeton.EDU (8.12.9/8.12.9) with ESMTP id o3Q4rXiZ008485 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NOT); Mon, 26 Apr 2010 00:53:34 -0400 (EDT) Received: from penta.localdomain (nat04-resnet-ext.rutgers.edu [192.12.88.4]) (authenticated bits=0) by tetra.ee.Princeton.EDU (8.14.3/8.14.3/Debian-9) with ESMTP id o3Q4rUaM025426 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 26 Apr 2010 00:53:32 -0400 Received: from penta.localdomain (tcp@localhost.localdomain [127.0.0.1]) by penta.localdomain (8.14.3/8.14.3/Debian-9.1) with ESMTP id o3Q4rErJ003215; Mon, 26 Apr 2010 00:53:25 -0400 Date: Mon, 26 Apr 2010 00:53:10 -0400 From: Yury Polyanskiy To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH] die() does not call die notifier chain Message-ID: <20100426005310.0786273f@penta.localdomain> X-Mailer: Claws Mail 3.7.5 (GTK+ 2.18.6; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/QOxfIid8d50t3C+JA2D/=kE"; protocol="application/pgp-signature" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26469 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ypolyans@princeton.edu Precedence: bulk X-list: linux-mips --Sig_/QOxfIid8d50t3C+JA2D/=kE Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Dear Ralf, I think that the arch/mips implementation of die() forgets to call the notify_die() and thus notifiers registered via register_die_notifier() are not called. For example this results in kgdb not being activated on exceptions. The patch is very simple and attached: the only subtlety is that main notify_die declares regs argument w/o const, so I needed to remove const=20 from mips die() as well. Best wishes, Yury. PS. Please CC me: I am not on the list. diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index ce47118..cdc6a46 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -142,9 +142,9 @@ extern int ptrace_set_watch_regs(struct task_struct *ch= ild, =20 extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexi= t); =20 -extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NO= RET; +extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET; =20 -static inline void die_if_kernel(const char *str, const struct pt_regs *re= gs) +static inline void die_if_kernel(const char *str, struct pt_regs *regs) { if (unlikely(!user_mode(regs))) die(str, regs); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 4e00f9b..fdc6773 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -352,9 +352,10 @@ void show_registers(const struct pt_regs *regs) =20 static DEFINE_SPINLOCK(die_lock); =20 -void __noreturn die(const char * str, const struct pt_regs * regs) +void __noreturn die(const char * str, struct pt_regs * regs) { static int die_counter; + int sig =3D SIGSEGV; #ifdef CONFIG_MIPS_MT_SMTC unsigned long dvpret =3D dvpe(); #endif /* CONFIG_MIPS_MT_SMTC */ @@ -365,6 +366,10 @@ void __noreturn die(const char * str, const struct pt_= regs * regs) #ifdef CONFIG_MIPS_MT_SMTC mips_mt_regdump(dvpret); #endif /* CONFIG_MIPS_MT_SMTC */ + + if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_no, SIGSEGV) = =3D=3D NOTIFY_STOP) + sig =3D 0; + printk("%s[#%d]:\n", str, ++die_counter); show_registers(regs); add_taint(TAINT_DIE); @@ -379,7 +384,7 @@ void __noreturn die(const char * str, const struct pt_r= egs * regs) panic("Fatal exception"); } =20 - do_exit(SIGSEGV); + do_exit(sig); } =20 extern struct exception_table_entry __start___dbe_table[]; --Sig_/QOxfIid8d50t3C+JA2D/=kE Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEARECAAYFAkvVHDYACgkQemuRe3zuqOS1/ACeIZoaRsF8Jo2KFZFhTL8dUDB3 Zj8AniZXj9R2r967yFqJWe9PAdacxzyC =ng0i -----END PGP SIGNATURE----- --Sig_/QOxfIid8d50t3C+JA2D/=kE-- From dominicwj@gmail.com Mon Apr 26 14:01:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 14:01:06 +0200 (CEST) Received: from mail-vw0-f49.google.com ([209.85.212.49]:61200 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492475Ab0DZMBD convert rfc822-to-8bit (ORCPT ); Mon, 26 Apr 2010 14:01:03 +0200 Received: by vws16 with SMTP id 16so186958vws.36 for ; Mon, 26 Apr 2010 05:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=OprkUIdpGXVj/LWoT8hEHruiI5xdaQRCUUAutyscCEA=; b=BiPTgTRHxOo1grIje5He7qWKosCfTKECb8gcSExcZXPRbnFBOV22a+6bQX6l3DR4gR Ht9NwDKN4stsart3l/Ytcq5chgZViKyOzwBFJod4oRK7vPmsAT4nMHWkcT4VeDJ7k9Hi vJfS98bg6s9FZ3ts8GDdBBSZO+/lrtw5/uvSM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Q9CnTF5g3n+X5NLUGTUjIGaHbyICy1RVLRT1kcK97QwFe4yygFZqnLGk6SGOLGiiyh 4JR9bSt2SZhtR7XIKc3sEIiNil11f3S9U6y48lUdU4K9Zu5mJoQGMHOfsLDwJTD4WZQm UbuJL83danQCPHou11mAGWz7XAXKwaiEydZFI= MIME-Version: 1.0 Received: by 10.220.124.210 with SMTP id v18mr2693094vcr.106.1272283255638; Mon, 26 Apr 2010 05:00:55 -0700 (PDT) Received: by 10.220.17.141 with HTTP; Mon, 26 Apr 2010 05:00:51 -0700 (PDT) In-Reply-To: References: <4BD08329.80804@adax.com> Date: Mon, 26 Apr 2010 20:00:51 +0800 Message-ID: Subject: Re: Ask help:why my 64-bit ELF file could not run at the 64-bit mips cpu From: Dominic To: Alexander Clouter , Jan Rovins , geert@linux-m68k.org Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26470 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dominicwj@gmail.com Precedence: bulk X-list: linux-mips Hi Alexander, Jan & Greet Much thanks for your advice, I have solve this problem, thanks a lot! BR/Dominic On Fri, Apr 23, 2010 at 5:34 PM, Alexander Clouter wrote: > Dominic wrote: >> >> Thanks a lot for your precious reply! I try to use -static to compile >> the program, then the 64-bit program can run, so it should be the >> library related other than 64-bit instruction or addressing related. >> Then I stored the 64-bit libraries in nfs, and mount it on the target >> board, after adding the path to ld.so.conf and 'ldconfig', the program >> compiled without -static still does not run. Shall I miss something? >> > On your host, you can type something like: > ---- > alex@berk:/usr/src/wag54g$ readelf -d buildroot/output/target/usr/sbin/ip6tables-multi  | grep Shared >  0x00000001 (NEEDED)                     Shared library: [libip6tc.so.0] >  0x00000001 (NEEDED)                     Shared library: [libxtables.so.4] >  0x00000001 (NEEDED)                     Shared library: [libdl.so.0] >  0x00000001 (NEEDED)                     Shared library: [libm.so.0] >  0x00000001 (NEEDED)                     Shared library: [libc.so.0] > ---- > > This will list all the libraries that you need installed[1], I'm guessin > you have missed one. > > You can look at the output of 'readelf -a' to try to see what might be > missing. > > Cheers > > [1] in addition to the interpreter required (for example 'ld-uClibc') >        and the main C library being used: >        readelf -l buildroot/output/target/usr/sbin/ip6tables-multi > > -- > Alexander Clouter > .sigmonster says: "Ninety percent of baseball is half mental." >                                -- Yogi Berra > > > From wuzhangjin@gmail.com Mon Apr 26 14:02:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 14:02:39 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:54963 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492498Ab0DZMCg (ORCPT ); Mon, 26 Apr 2010 14:02:36 +0200 Received: by gwb1 with SMTP id 1so262039gwb.36 for ; Mon, 26 Apr 2010 05:02:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=Nl39hrGq5vgdjyZdFaMehAWaos7T0sRl3ua+mi67nTo=; b=j7ZxkMyvmJgsnmjTQWqzRbJVC4YS24tIbDSVSbvpZOnWx5+PpxMovHXFClXsSiRq9k 2vbsMR1h6Z7oEUiJe1hEVR3UN4zIDLmOfwU+xgT8dRu6wsmR2NeDEgl4YhGfqaXIAtvK jD1cB1S2w8gfXbAgv3NozDbifEcSvtu74GzDg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=heos3bZDEmt1eHSJVslWPKFDz0S/3owRr6xPNs3vdplqoVHBrZLi1PyoTf6ARdDeFy F2zCkmwTjEOgXXa4FjnyBiQ5gIpFz1KPMtKTHrMlGsqBUb8A5n4EfO5gAsb7JRpVZKTF hhn+IdVN/uC7eYT4PE9dGFcViwYw/6j7VrCDU= Received: by 10.150.128.3 with SMTP id a3mr3909433ybd.280.1272283341540; Mon, 26 Apr 2010 05:02:21 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 15sm1856832gxk.10.2010.04.26.05.02.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 26 Apr 2010 05:02:21 -0700 (PDT) From: Wu Zhangjin To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH] Loongson: Oprofile: Enable it when CONFIG_OPROFILE=m Date: Mon, 26 Apr 2010 20:01:54 +0800 Message-Id: X-Mailer: git-send-email 1.7.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26471 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin When the oprofile is compiled as a module, the do_IRQ() is not called in arch/mips/loongson/lemote-2f/irq.c for the wrong #ifdef there. This patch fixes it via calling do_IRQ() whenever oprofile is compiled as a module(CONFIG_OPROFILE_MODULE is defined) or compiled into the kernel(CONFIG_OPROFILE is defined). Signed-off-by: Wu Zhangjin --- arch/mips/loongson/lemote-2f/irq.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c index 882dfcd..1d8b4d2 100644 --- a/arch/mips/loongson/lemote-2f/irq.c +++ b/arch/mips/loongson/lemote-2f/irq.c @@ -79,7 +79,7 @@ void mach_irq_dispatch(unsigned int pending) if (pending & CAUSEF_IP7) do_IRQ(LOONGSON_TIMER_IRQ); else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */ -#ifdef CONFIG_OPROFILE +#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE) do_IRQ(LOONGSON2_PERFCNT_IRQ); #endif bonito_irqdispatch(); -- 1.7.0 From wuzhangjin@gmail.com Mon Apr 26 14:14:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 14:14:15 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:60313 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492511Ab0DZMOL (ORCPT ); Mon, 26 Apr 2010 14:14:11 +0200 Received: by gwb1 with SMTP id 1so266670gwb.36 for ; Mon, 26 Apr 2010 05:14:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=LWJ03z8zRf70fhkm1yYLfVLdgcf9mrEI05CXl6H0c7M=; b=li+PyiRBkiJtJYiwO/06awog1ZTLWRA+I4uY52IvroZhXE9oUhvVY1EbFYOapekdk+ 9ULUvqBa1UsIoMrCaAM5nbi5i5erozqQeWE3kDHtP0VCTQr2Zlp+PO9h7g9Is9GBudTq tBOdhZy8/0OYqXZf7Jbzc0NiQHIq1xdOVJbtY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=UZ3wKOFgtlwihzfEzaTN91NKxvR6FPt4MVo3aA/B+JffsFmDCOjffcW76KAbhvGZjA 78bm4+Nwve4tVxCVrJeO1u0QoybBCJiegsjfnr60TsYW4F3yOfJtR6Q7K61aa4wmVCHv cVo4hlxrDS25THCd4zptvs4z7lE+ExRKiVLu0= Received: by 10.101.171.15 with SMTP id y15mr5035971ano.4.1272284045517; Mon, 26 Apr 2010 05:14:05 -0700 (PDT) Received: from [192.168.2.213] ([202.201.14.140]) by mx.google.com with ESMTPS id r21sm43246782anp.7.2010.04.26.05.14.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 26 Apr 2010 05:14:02 -0700 (PDT) Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Thomas Bogendoerfer Cc: Ralf Baechle , David Daney , linux-mips@linux-mips.org In-Reply-To: <20100414112458.GA8861@alpha.franken.de> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> <20100413171610.GA16578@linux-mips.org> <1271232185.25872.142.camel@falcon> <20100414112458.GA8861@alpha.franken.de> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Mon, 26 Apr 2010 20:13:55 +0800 Message-ID: <1272284035.11865.8.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26472 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2010-04-14 at 13:24 +0200, Thomas Bogendoerfer wrote: > On Wed, Apr 14, 2010 at 04:03:05PM +0800, Wu Zhangjin wrote: > > If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000, > > then we get the address: 0x97ffffff80000100, is this address ok? > > the address is broken TO_UNCAC doesn't work properly for CKSEG0 addresses. > And that's IMHO the real bug... I'm wondering whether this > set_uncached_handler() stunt is even needed. Is there a machine > where CKSEG0 and CKSEG1 address different memory ? If not, we could > just use the normal set_handler() function and be done with it. > Hi, all I'm not familiar with this part, is there any fixup/workaround for this bug? otherwise, we will get a broken support for the r4k machines(at least the loongson machines). Regards, Wu Zhangjin From rampxxxx@gmail.com Mon Apr 26 15:41:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 15:41:18 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.148]:14679 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491062Ab0DZNlN convert rfc822-to-8bit (ORCPT ); Mon, 26 Apr 2010 15:41:13 +0200 Received: by ey-out-1920.google.com with SMTP id 3so825659eyh.52 for ; Mon, 26 Apr 2010 06:41:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:from:date :message-id:subject:to:content-type:content-transfer-encoding; bh=mGUFQVYWfJK4Q24pWPGaEp/RtnD4yvdMq2GbQhDZs1E=; b=ngO9Ov/zvKdz/utW4Ddjca6XP8VgIRSg36Kwn7XrLAbOYvXtANgLfSGNJ+1QkzROp1 qM8/kVgkFRL+WAw0nufD2ia2baEUvOcAJ1zKtBScBXImXQ1cZ7/skknCY/TCMes6Q36R 6U4YO7rpUqOJRfSmZ/BjBsLuRmi8Ehx/4Unls= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type :content-transfer-encoding; b=sil/WBWL7inDtgzqDTCXFq+DiR1AfJuKQvC2Z/Uez8h32dhO808kW2eoMmth26OugZ W3GPDADReyReUVqmRP7tcucWM9irUNdFOVLhTPZqMUWmaRDGYgbWJ7GTvjiCFx8q388A fuCtXFvMlPm9Wwf519V1CFai7vTV8SBQ+GZdk= Received: by 10.103.7.26 with SMTP id k26mr2312886mui.15.1272289272186; Mon, 26 Apr 2010 06:41:12 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.177.13 with HTTP; Mon, 26 Apr 2010 06:40:52 -0700 (PDT) From: "Giant Sand Fan's" Date: Mon, 26 Apr 2010 15:40:52 +0200 Message-ID: Subject: Cavium mips64 perf counters To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26473 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rampxxxx@gmail.com Precedence: bulk X-list: linux-mips Hi, I'm trying to calculate de CPU load by access the performance counters in mips and I haved reading in the cp0 but my problem is that I cannot find documentation about the real meaning of these counters : 1.-LOG_PERF_CNT_NISSUE : ¿means cycle with no issue? 2.-LOG_PERF_CNT_SISSUE : ¿means cycle with issue? 3.-LOG_PERF_CNT_DISSUE: ¿means cycle with double issue? so CPU load will be == 2*100/(1+2) , in the period of time. any clue... thanks -- Please avoid sending me Word or PowerPoint attachments. See http://www.gnu.org/philosophy/no-word-attachments.html From David.Daney@caviumnetworks.com Mon Apr 26 19:06:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 19:06:56 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11686 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492649Ab0DZRGs (ORCPT ); Mon, 26 Apr 2010 19:06:48 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 26 Apr 2010 10:06:59 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 10:06:05 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 10:06:05 -0700 Message-ID: <4BD5C7F8.6050406@caviumnetworks.com> Date: Mon, 26 Apr 2010 10:06:00 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Giant Sand Fan's CC: linux-mips@linux-mips.org Subject: Re: Cavium mips64 perf counters References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 26 Apr 2010 17:06:05.0573 (UTC) FILETIME=[C1E02B50:01CAE562] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26474 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/26/2010 06:40 AM, Giant Sand Fan's wrote: > Hi, > > I'm trying to calculate de CPU load by access the performance counters > in mips and I haved reading in the cp0 but my problem is that I cannot > find documentation about the real meaning of these counters : > > 1.-LOG_PERF_CNT_NISSUE : ¿means cycle with no issue? > > 2.-LOG_PERF_CNT_SISSUE : ¿means cycle with issue? Single issue. > > 3.-LOG_PERF_CNT_DISSUE: ¿means cycle with double issue? > That's right. And PERF_CNT_CLK is the number of cycles. David Daney From David.Daney@caviumnetworks.com Mon Apr 26 19:19:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 19:19:50 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11973 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492654Ab0DZRTr (ORCPT ); Mon, 26 Apr 2010 19:19:47 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 26 Apr 2010 10:20:00 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 10:19:10 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 10:19:09 -0700 Message-ID: <4BD5CB08.7010907@caviumnetworks.com> Date: Mon, 26 Apr 2010 10:19:04 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: wuzhangjin@gmail.com CC: Ralf Baechle , Thomas Bogendoerfer , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> <20100413171610.GA16578@linux-mips.org> <1271232185.25872.142.camel@falcon> In-Reply-To: <1271232185.25872.142.camel@falcon> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 26 Apr 2010 17:19:09.0995 (UTC) FILETIME=[956D77B0:01CAE564] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26475 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/14/2010 01:03 AM, Wu Zhangjin wrote: > On Tue, 2010-04-13 at 18:16 +0100, Ralf Baechle wrote: >> On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote: >> >>> On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote: >>>> This patch have broken the support to the MIPS variants whose >>>> cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different >>>> in these MIPSs. >>> >>> I've checked R4k and R10k manulas and the exception base is at CKSEG0, so >>> about CPU we are talking ? And wouldn't it make for senso to have >>> an extra define for the exception base then ? >> >> C0_ebase's design was a short-sigthed only considering 32-bit processors. >> So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or >> older. So yes, there is a bug as I've verified by testing but the patch >> is unfortunately incorrect. > > Just debugged it via PMON: > > loaded the kernel and used "g console=tty root=/dev/hda5 init=/bin/bash" > to start the kernel, there was a bad address exception. > > the kernel stopped at: > > Exception Cause=address error on store, SR=0x24000002, PC=0x8020526c > ... > BADVADDR=0x97ffffff80000100, ENTHI=0xfffffe000 > ... > ... > __copy_user+0x48 ... sd t0,0(a0) # addr = 0x80000100 rt=0x401a8000 > > Seems the a0 argument of __copy_user is _bad_. > > And tried to set a break pointer to trap_init() and per_cpu_trap_init(), > and then cpu_cache_init() ... r4k_cache_init() and at last found that > set_uncached_handler(0x100,&except_vec2_generic, 0x80); > > /* > * Install uncached CPU exception handler. > * This is suitable only for the cache error exception which is the only > * exception handler that is being run uncached. > */ > void __cpuinit set_uncached_handler(unsigned long offset, void *addr, > unsigned long size) > { > #ifdef CONFIG_32BIT > unsigned long uncached_ebase = KSEG1ADDR(ebase); > #endif > #ifdef CONFIG_64BIT > unsigned long uncached_ebase = TO_UNCAC(ebase); > #endif > > if (!addr) > panic(panic_null_cerr); > > memcpy((void *)(uncached_ebase + offset), addr, size); > } > > memcpy() called __copy_user... and the a0 is uncached_ebase + offset, > and uncached_ebase is defined by TO_UNCAC: > > #define TO_UNCAC(x) (UNCAC_BASE | ((x)& TO_PHYS_MASK)) > #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) > #define UNCAC_BASE _AC(0x9000000000000000, UL) > > If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000, > then we get the address: 0x97ffffff80000100, is this address ok? I don't think so. We should fix TO_UNCAC() so that it works with CKSEG0 addresses. It should be at physical address 0. So TO_UNCAC(0xffffffff80000000), should yield 0x9000000000000000 #define TO_UNCAC(x) ({ \ u64 a = (u64)(x); \ if (a & 0xffffffffc000000 == 0xffffffff80000000) \ a = UNCAC_BASE | (a & 0x30000000); \ else \ a = UNCAC_BASE | (a & TO_PHYS_MASK) \ a; \ }) David Daney > > And before, we have used the CAC_BASE as the ebase, the CAC_BASE is > defined as following: > > #ifndef CAC_BASE > #ifdef CONFIG_DMA_NONCOHERENT > #define CAC_BASE _AC(0x9800000000000000, UL) > #else > #define CAC_BASE _AC(0xa800000000000000, UL) > #endif > #endif > > So, before, the uncached_base is 0x9000000000000000. > > Regards, > Wu Zhangjin > > From sebastian@breakpoint.cc Mon Apr 26 21:52:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 21:52:35 +0200 (CEST) Received: from Chamillionaire.breakpoint.cc ([85.10.199.196]:47087 "EHLO Chamillionaire.breakpoint.cc" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492005Ab0DZTwa (ORCPT ); Mon, 26 Apr 2010 21:52:30 +0200 Received: id: bigeasy by Chamillionaire.breakpoint.cc with local (easymta 1.00 BETA 1) id 1O6UM1-00062N-Ho; Mon, 26 Apr 2010 21:52:29 +0200 Date: Mon, 26 Apr 2010 21:52:29 +0200 From: Sebastian Andrzej Siewior To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [RFC] net/sb1250: setup the pdevice within the soc code Message-ID: <20100426195229.GB22245@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline X-Key-Id: FE3F4706 X-Key-Fingerprint: FFDA BBBB 3563 1B27 75C9 925B 98D5 5C1C FE3F 4706 User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26476 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sebastian@breakpoint.cc Precedence: bulk X-list: linux-mips doing it within the driver does not look good. Signed-off-by: Sebastian Andrzej Siewior --- Ralf, if you fine with then I'm gonna to post it at netdev. arch/mips/sibyte/sb1250/setup.c | 55 ++++++++++++++++++ drivers/net/sb1250-mac.c | 120 +-------------------------------------- 2 files changed, 56 insertions(+), 119 deletions(-) diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index 92da315..915d698 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -245,3 +246,57 @@ void __init sb1250_setup(void) machine_restart(NULL); } } + +#define sb1250_dev_struct(num) \ + static struct resource sb1250_res##num = { \ + .name = "SB1250 MAC " __stringify(num), \ + .flags = IORESOURCE_MEM, \ + .start = A_MAC_CHANNEL_BASE(num), \ + .end = A_MAC_CHANNEL_BASE(num + 1) -1, \ + };\ + static struct platform_device sb1250_dev##num = { \ + .name = "sb1250-mac", \ + .id = num, \ + .resource = &sb1250_res##num, \ + .num_resources = 1, \ + } + +sb1250_dev_struct(0); +sb1250_dev_struct(1); +sb1250_dev_struct(2); +sb1250_dev_struct(3); + +static struct platform_device *sb1250_devs[] __initdata = { + &sb1250_dev0, + &sb1250_dev1, + &sb1250_dev2, + &sb1250_dev3, +}; + +static int __init sb1250_device_init(void) +{ + int ret; + + /* Set the number of available units based on the SOC type. */ + switch (soc_type) { + case K_SYS_SOC_TYPE_BCM1250: + case K_SYS_SOC_TYPE_BCM1250_ALT: + ret = platform_add_devices(sb1250_devs, 3); + break; + case K_SYS_SOC_TYPE_BCM1120: + case K_SYS_SOC_TYPE_BCM1125: + case K_SYS_SOC_TYPE_BCM1125H: + case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ + ret = platform_add_devices(sb1250_devs, 2); + break; + case K_SYS_SOC_TYPE_BCM1x55: + case K_SYS_SOC_TYPE_BCM1x80: + ret = platform_add_devices(sb1250_devs, 4); + break; + default: + ret = -ENODEV; + break; + } + return ret; +} +device_initcall(sb1250_device_init); diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c index fc503a1..459bc59 100644 --- a/drivers/net/sb1250-mac.c +++ b/drivers/net/sb1250-mac.c @@ -332,7 +332,6 @@ static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, ********************************************************************* */ static char sbmac_string[] = "sb1250-mac"; -static char sbmac_pretty[] = "SB1250 MAC"; static char sbmac_mdio_string[] = "sb1250-mac-mdio"; @@ -2668,114 +2667,6 @@ static int __exit sbmac_remove(struct platform_device *pldev) return 0; } - -static struct platform_device **sbmac_pldev; -static int sbmac_max_units; - -static int __init sbmac_platform_probe_one(int idx) -{ - struct platform_device *pldev; - struct { - struct resource r; - char name[strlen(sbmac_pretty) + 4]; - } *res; - int err; - - res = kzalloc(sizeof(*res), GFP_KERNEL); - if (!res) { - printk(KERN_ERR "%s.%d: unable to allocate memory\n", - sbmac_string, idx); - err = -ENOMEM; - goto out_err; - } - - /* - * This is the base address of the MAC. - */ - snprintf(res->name, sizeof(res->name), "%s %d", sbmac_pretty, idx); - res->r.name = res->name; - res->r.flags = IORESOURCE_MEM; - res->r.start = A_MAC_CHANNEL_BASE(idx); - res->r.end = A_MAC_CHANNEL_BASE(idx + 1) - 1; - - pldev = platform_device_register_simple(sbmac_string, idx, &res->r, 1); - if (IS_ERR(pldev)) { - printk(KERN_ERR "%s.%d: unable to register platform device\n", - sbmac_string, idx); - err = PTR_ERR(pldev); - goto out_kfree; - } - - if (!pldev->dev.driver) { - err = 0; /* No hardware at this address. */ - goto out_unregister; - } - - sbmac_pldev[idx] = pldev; - return 0; - -out_unregister: - platform_device_unregister(pldev); - -out_kfree: - kfree(res); - -out_err: - return err; -} - -static void __init sbmac_platform_probe(void) -{ - int i; - - /* Set the number of available units based on the SOC type. */ - switch (soc_type) { - case K_SYS_SOC_TYPE_BCM1250: - case K_SYS_SOC_TYPE_BCM1250_ALT: - sbmac_max_units = 3; - break; - case K_SYS_SOC_TYPE_BCM1120: - case K_SYS_SOC_TYPE_BCM1125: - case K_SYS_SOC_TYPE_BCM1125H: - case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ - sbmac_max_units = 2; - break; - case K_SYS_SOC_TYPE_BCM1x55: - case K_SYS_SOC_TYPE_BCM1x80: - sbmac_max_units = 4; - break; - default: - return; /* none */ - } - - sbmac_pldev = kcalloc(sbmac_max_units, sizeof(*sbmac_pldev), - GFP_KERNEL); - if (!sbmac_pldev) { - printk(KERN_ERR "%s: unable to allocate memory\n", - sbmac_string); - return; - } - - /* - * Walk through the Ethernet controllers and find - * those who have their MAC addresses set. - */ - for (i = 0; i < sbmac_max_units; i++) - if (sbmac_platform_probe_one(i)) - break; -} - - -static void __exit sbmac_platform_cleanup(void) -{ - int i; - - for (i = 0; i < sbmac_max_units; i++) - platform_device_unregister(sbmac_pldev[i]); - kfree(sbmac_pldev); -} - - static struct platform_driver sbmac_driver = { .probe = sbmac_probe, .remove = __exit_p(sbmac_remove), @@ -2786,20 +2677,11 @@ static struct platform_driver sbmac_driver = { static int __init sbmac_init_module(void) { - int err; - - err = platform_driver_register(&sbmac_driver); - if (err) - return err; - - sbmac_platform_probe(); - - return err; + return platform_driver_register(&sbmac_driver); } static void __exit sbmac_cleanup_module(void) { - sbmac_platform_cleanup(); platform_driver_unregister(&sbmac_driver); } -- 1.6.6.1 From ralf@linux-mips.org Mon Apr 26 22:25:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 22:25:11 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44031 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491823Ab0DZUZI (ORCPT ); Mon, 26 Apr 2010 22:25:08 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3QKP0qY027704; Mon, 26 Apr 2010 21:25:00 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3QKOxeV027702; Mon, 26 Apr 2010 21:24:59 +0100 Date: Mon, 26 Apr 2010 21:24:59 +0100 From: Ralf Baechle To: Sebastian Andrzej Siewior Cc: linux-mips@linux-mips.org Subject: Re: [RFC] net/sb1250: setup the pdevice within the soc code Message-ID: <20100426202459.GD27656@linux-mips.org> References: <20100426195229.GB22245@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100426195229.GB22245@Chamillionaire.breakpoint.cc> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26477 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 26, 2010 at 09:52:29PM +0200, Sebastian Andrzej Siewior wrote: > doing it within the driver does not look good. > > Signed-off-by: Sebastian Andrzej Siewior > --- > Ralf, if you fine with then I'm gonna to post it at netdev. > > arch/mips/sibyte/sb1250/setup.c | 55 ++++++++++++++++++ > drivers/net/sb1250-mac.c | 120 +-------------------------------------- Almost. The idea is right but the driver is also being used by the BCM1480-based platforms. So either arch/mips/sibyte/bcm1480/setup.c needs the same changes or - and better - you change arch/mips/sibyte/swarm/platform.c instead. Despite the swarm in the path name that file is being used also for all other currently supported Sibyte platforms. Ralf From sebastian@breakpoint.cc Mon Apr 26 22:41:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 22:41:30 +0200 (CEST) Received: from Chamillionaire.breakpoint.cc ([85.10.199.196]:41817 "EHLO Chamillionaire.breakpoint.cc" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491203Ab0DZUlY (ORCPT ); Mon, 26 Apr 2010 22:41:24 +0200 Received: id: bigeasy by Chamillionaire.breakpoint.cc with local (easymta 1.00 BETA 1) id 1O6V7K-0006AW-Qr; Mon, 26 Apr 2010 22:41:22 +0200 Date: Mon, 26 Apr 2010 22:41:22 +0200 From: Sebastian Andrzej Siewior To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: [RFC] net/sb1250: setup the pdevice within the soc code Message-ID: <20100426204122.GA23697@Chamillionaire.breakpoint.cc> References: <20100426195229.GB22245@Chamillionaire.breakpoint.cc> <20100426202459.GD27656@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <20100426202459.GD27656@linux-mips.org> X-Key-Id: FE3F4706 X-Key-Fingerprint: FFDA BBBB 3563 1B27 75C9 925B 98D5 5C1C FE3F 4706 User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26478 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sebastian@breakpoint.cc Precedence: bulk X-list: linux-mips doing it within the driver does not look good. Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/sibyte/swarm/platform.c | 54 +++++++++++++++++ drivers/net/sb1250-mac.c | 120 +------------------------------------ 2 files changed, 55 insertions(+), 119 deletions(-) diff --git a/arch/mips/sibyte/swarm/platform.c b/arch/mips/sibyte/swarm/platform.c index 54847fe..0973352 100644 --- a/arch/mips/sibyte/swarm/platform.c +++ b/arch/mips/sibyte/swarm/platform.c @@ -83,3 +83,57 @@ static int __init swarm_pata_init(void) device_initcall(swarm_pata_init); #endif /* defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_LITTLESUR) */ + +#define sb1250_dev_struct(num) \ + static struct resource sb1250_res##num = { \ + .name = "SB1250 MAC " __stringify(num), \ + .flags = IORESOURCE_MEM, \ + .start = A_MAC_CHANNEL_BASE(num), \ + .end = A_MAC_CHANNEL_BASE(num + 1) -1, \ + };\ + static struct platform_device sb1250_dev##num = { \ + .name = "sb1250-mac", \ + .id = num, \ + .resource = &sb1250_res##num, \ + .num_resources = 1, \ + } + +sb1250_dev_struct(0); +sb1250_dev_struct(1); +sb1250_dev_struct(2); +sb1250_dev_struct(3); + +static struct platform_device *sb1250_devs[] __initdata = { + &sb1250_dev0, + &sb1250_dev1, + &sb1250_dev2, + &sb1250_dev3, +}; + +static int __init sb1250_device_init(void) +{ + int ret; + + /* Set the number of available units based on the SOC type. */ + switch (soc_type) { + case K_SYS_SOC_TYPE_BCM1250: + case K_SYS_SOC_TYPE_BCM1250_ALT: + ret = platform_add_devices(sb1250_devs, 3); + break; + case K_SYS_SOC_TYPE_BCM1120: + case K_SYS_SOC_TYPE_BCM1125: + case K_SYS_SOC_TYPE_BCM1125H: + case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ + ret = platform_add_devices(sb1250_devs, 2); + break; + case K_SYS_SOC_TYPE_BCM1x55: + case K_SYS_SOC_TYPE_BCM1x80: + ret = platform_add_devices(sb1250_devs, 4); + break; + default: + ret = -ENODEV; + break; + } + return ret; +} +device_initcall(sb1250_device_init); diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c index fc503a1..459bc59 100644 --- a/drivers/net/sb1250-mac.c +++ b/drivers/net/sb1250-mac.c @@ -332,7 +332,6 @@ static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, ********************************************************************* */ static char sbmac_string[] = "sb1250-mac"; -static char sbmac_pretty[] = "SB1250 MAC"; static char sbmac_mdio_string[] = "sb1250-mac-mdio"; @@ -2668,114 +2667,6 @@ static int __exit sbmac_remove(struct platform_device *pldev) return 0; } - -static struct platform_device **sbmac_pldev; -static int sbmac_max_units; - -static int __init sbmac_platform_probe_one(int idx) -{ - struct platform_device *pldev; - struct { - struct resource r; - char name[strlen(sbmac_pretty) + 4]; - } *res; - int err; - - res = kzalloc(sizeof(*res), GFP_KERNEL); - if (!res) { - printk(KERN_ERR "%s.%d: unable to allocate memory\n", - sbmac_string, idx); - err = -ENOMEM; - goto out_err; - } - - /* - * This is the base address of the MAC. - */ - snprintf(res->name, sizeof(res->name), "%s %d", sbmac_pretty, idx); - res->r.name = res->name; - res->r.flags = IORESOURCE_MEM; - res->r.start = A_MAC_CHANNEL_BASE(idx); - res->r.end = A_MAC_CHANNEL_BASE(idx + 1) - 1; - - pldev = platform_device_register_simple(sbmac_string, idx, &res->r, 1); - if (IS_ERR(pldev)) { - printk(KERN_ERR "%s.%d: unable to register platform device\n", - sbmac_string, idx); - err = PTR_ERR(pldev); - goto out_kfree; - } - - if (!pldev->dev.driver) { - err = 0; /* No hardware at this address. */ - goto out_unregister; - } - - sbmac_pldev[idx] = pldev; - return 0; - -out_unregister: - platform_device_unregister(pldev); - -out_kfree: - kfree(res); - -out_err: - return err; -} - -static void __init sbmac_platform_probe(void) -{ - int i; - - /* Set the number of available units based on the SOC type. */ - switch (soc_type) { - case K_SYS_SOC_TYPE_BCM1250: - case K_SYS_SOC_TYPE_BCM1250_ALT: - sbmac_max_units = 3; - break; - case K_SYS_SOC_TYPE_BCM1120: - case K_SYS_SOC_TYPE_BCM1125: - case K_SYS_SOC_TYPE_BCM1125H: - case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ - sbmac_max_units = 2; - break; - case K_SYS_SOC_TYPE_BCM1x55: - case K_SYS_SOC_TYPE_BCM1x80: - sbmac_max_units = 4; - break; - default: - return; /* none */ - } - - sbmac_pldev = kcalloc(sbmac_max_units, sizeof(*sbmac_pldev), - GFP_KERNEL); - if (!sbmac_pldev) { - printk(KERN_ERR "%s: unable to allocate memory\n", - sbmac_string); - return; - } - - /* - * Walk through the Ethernet controllers and find - * those who have their MAC addresses set. - */ - for (i = 0; i < sbmac_max_units; i++) - if (sbmac_platform_probe_one(i)) - break; -} - - -static void __exit sbmac_platform_cleanup(void) -{ - int i; - - for (i = 0; i < sbmac_max_units; i++) - platform_device_unregister(sbmac_pldev[i]); - kfree(sbmac_pldev); -} - - static struct platform_driver sbmac_driver = { .probe = sbmac_probe, .remove = __exit_p(sbmac_remove), @@ -2786,20 +2677,11 @@ static struct platform_driver sbmac_driver = { static int __init sbmac_init_module(void) { - int err; - - err = platform_driver_register(&sbmac_driver); - if (err) - return err; - - sbmac_platform_probe(); - - return err; + return platform_driver_register(&sbmac_driver); } static void __exit sbmac_cleanup_module(void) { - sbmac_platform_cleanup(); platform_driver_unregister(&sbmac_driver); } -- 1.6.6.1 From ralf@linux-mips.org Mon Apr 26 23:00:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Apr 2010 23:00:35 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57149 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492275Ab0DZVAc (ORCPT ); Mon, 26 Apr 2010 23:00:32 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3QL0N6q028582; Mon, 26 Apr 2010 22:00:23 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3QL0NKh028580; Mon, 26 Apr 2010 22:00:23 +0100 Date: Mon, 26 Apr 2010 22:00:23 +0100 From: Ralf Baechle To: Sebastian Andrzej Siewior Cc: linux-mips@linux-mips.org Subject: Re: [RFC] net/sb1250: setup the pdevice within the soc code Message-ID: <20100426210022.GE27656@linux-mips.org> References: <20100426195229.GB22245@Chamillionaire.breakpoint.cc> <20100426202459.GD27656@linux-mips.org> <20100426204122.GA23697@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100426204122.GA23697@Chamillionaire.breakpoint.cc> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26479 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 26, 2010 at 10:41:22PM +0200, Sebastian Andrzej Siewior wrote: > doing it within the driver does not look good. And surely isn't how platform devices were meat to be used. > Signed-off-by: Sebastian Andrzej Siewior Go ahead: Acked-by: Ralf Baechle Thanks! Ralf From David.Daney@caviumnetworks.com Tue Apr 27 02:22:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 02:22:58 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1910 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492694Ab0D0AWy (ORCPT ); Tue, 27 Apr 2010 02:22:54 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 26 Apr 2010 17:23:03 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 17:22:17 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Apr 2010 17:22:16 -0700 Message-ID: <4BD62E38.10707@caviumnetworks.com> Date: Mon, 26 Apr 2010 17:22:16 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: post@pfrst.de, Ralf Baechle CC: linux-mips Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 27 Apr 2010 00:22:16.0932 (UTC) FILETIME=[B138A240:01CAE59F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26480 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/26/2010 06:25 PM, post@pfrst.de wrote: > > > Hi David, > > please excuse me, i just couldn't resist to comment on this :-) > > Some time ago we needed to handle multiple (virtual) address-spaces > (in TO_CAC/TO_UNCAC as well as in virt_to_phys and the like) for > SGI's Indigo2/R10k and Octane (neither could run a 32bit kernel). > So in addrspace.h we provided > #ifdef CONFIG_64BIT > static inline unsigned long kernel_physaddr(unsigned long kva) > { > if((kva&0xffffffff80000000UL)==0xffffffff80000000UL) > return CPHYSADDR(kva); > return XPHYSADDR(kva); > } > #else > #define kernel_physaddr CPHYSADDR > #endif > while mach-ipXX/spaces.h defined > #define TO_PHYS(x) ( kernel_physaddr(x)) > #define TO_CAC(x) (CAC_BASE | kernel_physaddr(x)) > #define TO_UNCAC(x) (UNCAC_BASE | kernel_physaddr(x)) > which did the job. > But at that time these defines didn't meet much acceptance for general > use in 64bit kernels. Now, to my amusement, some modern processor > (and/or system) seems to urge this kind of address-handling again ;-) > > FWIW, that seems cleaner than what I did (actually I didn't try my code). That should be the default definition for 64-bit kernels I think. David Daney > Good luck! > > > > On Mon, 26 Apr 2010, David Daney wrote: > >> Date: Mon, 26 Apr 2010 10:19:04 -0700 >> From: David Daney >> To: wuzhangjin@gmail.com >> Cc: Ralf Baechle, >> Thomas Bogendoerfer, >> linux-mips@linux-mips.org >> Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels >> >> ... >> I don't think so. We should fix TO_UNCAC() so that it works with CKSEG0 >> addresses. It should be at physical address 0. So >> TO_UNCAC(0xffffffff80000000), should yield 0x9000000000000000 >> >> >> #define TO_UNCAC(x) ({ \ >> u64 a = (u64)(x); \ >> if (a& 0xffffffffc000000 == 0xffffffff80000000) \ >> a = UNCAC_BASE | (a& 0x30000000); \ >> else \ >> a = UNCAC_BASE | (a& TO_PHYS_MASK) \ >> a; \ >> }) >> >> David Daney >> >> ... > From wuzhangjin@gmail.com Tue Apr 27 04:53:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 04:53:52 +0200 (CEST) Received: from mail-yw0-f187.google.com ([209.85.211.187]:58754 "EHLO mail-yw0-f187.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491094Ab0D0Cxr (ORCPT ); Tue, 27 Apr 2010 04:53:47 +0200 Received: by ywh17 with SMTP id 17so153701ywh.22 for ; Mon, 26 Apr 2010 19:53:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=K/1MhlxztOUHbPJuS5yDkiQz5GhdehP5sOdbc6DXteU=; b=q5c20buFjg3rDfQXJqxFGmeDzLlt0FokfZDGTs9RQTtV89zxaBPCUaLIM4ShO4PWX/ eEMVy6EnX98tzFSMW71zCalga6KjtZVB+AuDNp31PlyrDfhcgsyYO4Rq/lPXWV2HBUgg BuqPQmAWJl9pJC6sOsmX1k7QgfsN600XzWHjI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=U9KWT8grzNoxV4UdT69+Gnf1jA0A6Zz6rg5oLty7mzoC7kDxAPRHosxj5Xv+WoLFcN 6Qp/9iCzOpYCX+S2j4Vxy1ybldtlVuFPGjUcOD5QcU5o6+UwxyvnUqREbTlo+VTUQEnq 32i3dsJq5IYK0Ar9Gx2nQp9ppSp1WvDmVuNfc= Received: by 10.150.165.3 with SMTP id n3mr4646115ybe.47.1272336819552; Mon, 26 Apr 2010 19:53:39 -0700 (PDT) Received: from [192.168.2.213] ([202.201.14.140]) by mx.google.com with ESMTPS id 16sm1720038gxk.5.2010.04.26.19.53.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 26 Apr 2010 19:53:38 -0700 (PDT) Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: David Daney Cc: Ralf Baechle , Thomas Bogendoerfer , linux-mips@linux-mips.org In-Reply-To: <4BD5CB08.7010907@caviumnetworks.com> References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> <20100413171610.GA16578@linux-mips.org> <1271232185.25872.142.camel@falcon> <4BD5CB08.7010907@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Tue, 27 Apr 2010 10:53:30 +0800 Message-ID: <1272336811.21095.7.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26481 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Mon, 2010-04-26 at 10:19 -0700, David Daney wrote: > On 04/14/2010 01:03 AM, Wu Zhangjin wrote: > > On Tue, 2010-04-13 at 18:16 +0100, Ralf Baechle wrote: > >> On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote: > >> > >>> On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote: > >>>> This patch have broken the support to the MIPS variants whose > >>>> cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different > >>>> in these MIPSs. > >>> > >>> I've checked R4k and R10k manulas and the exception base is at CKSEG0, so > >>> about CPU we are talking ? And wouldn't it make for senso to have > >>> an extra define for the exception base then ? > >> > >> C0_ebase's design was a short-sigthed only considering 32-bit processors. > >> So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or > >> older. So yes, there is a bug as I've verified by testing but the patch > >> is unfortunately incorrect. > > > > Just debugged it via PMON: > > > > loaded the kernel and used "g console=tty root=/dev/hda5 init=/bin/bash" > > to start the kernel, there was a bad address exception. > > > > the kernel stopped at: > > > > Exception Cause=address error on store, SR=0x24000002, PC=0x8020526c > > ... > > BADVADDR=0x97ffffff80000100, ENTHI=0xfffffe000 > > ... > > ... > > __copy_user+0x48 ... sd t0,0(a0) # addr = 0x80000100 rt=0x401a8000 > > > > Seems the a0 argument of __copy_user is _bad_. > > > > And tried to set a break pointer to trap_init() and per_cpu_trap_init(), > > and then cpu_cache_init() ... r4k_cache_init() and at last found that > > set_uncached_handler(0x100,&except_vec2_generic, 0x80); > > > > /* > > * Install uncached CPU exception handler. > > * This is suitable only for the cache error exception which is the only > > * exception handler that is being run uncached. > > */ > > void __cpuinit set_uncached_handler(unsigned long offset, void *addr, > > unsigned long size) > > { > > #ifdef CONFIG_32BIT > > unsigned long uncached_ebase = KSEG1ADDR(ebase); > > #endif > > #ifdef CONFIG_64BIT > > unsigned long uncached_ebase = TO_UNCAC(ebase); > > #endif > > > > if (!addr) > > panic(panic_null_cerr); > > > > memcpy((void *)(uncached_ebase + offset), addr, size); > > } > > > > memcpy() called __copy_user... and the a0 is uncached_ebase + offset, > > and uncached_ebase is defined by TO_UNCAC: > > > > #define TO_UNCAC(x) (UNCAC_BASE | ((x)& TO_PHYS_MASK)) > > #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) > > #define UNCAC_BASE _AC(0x9000000000000000, UL) > > > > If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000, > > then we get the address: 0x97ffffff80000100, is this address ok? > > I don't think so. We should fix TO_UNCAC() so that it works with CKSEG0 > addresses. It should be at physical address 0. So > TO_UNCAC(0xffffffff80000000), should yield 0x9000000000000000 > > > #define TO_UNCAC(x) ({ \ > u64 a = (u64)(x); \ > if (a & 0xffffffffc000000 == 0xffffffff80000000) \ > a = UNCAC_BASE | (a & 0x30000000); \ > else \ > a = UNCAC_BASE | (a & TO_PHYS_MASK) \ > a; \ > }) Thanks, This works with few of changes: > diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h > index c9fa4b1..b49f381 100644 > --- a/arch/mips/include/asm/mach-generic/spaces.h > +++ b/arch/mips/include/asm/mach-generic/spaces.h > @@ -71,7 +71,14 @@ > > #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) > #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) > -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) > +#define TO_UNCAC(x) ({ \ > + u64 a = (u64)(x); \ > + if ((a & 0xffffffffc0000000UL) == 0xffffffff80000000UL) \ > + a = UNCAC_BASE | (a & 0x30000000); \ > + else \ > + a = UNCAC_BASE | (a & TO_PHYS_MASK); \ > + a; \ > +}) > > #endif /* CONFIG_64BIT */ I will send it out later. Regards, Wu Zhangjin > > David Daney > > > > > > And before, we have used the CAC_BASE as the ebase, the CAC_BASE is > > defined as following: > > > > #ifndef CAC_BASE > > #ifdef CONFIG_DMA_NONCOHERENT > > #define CAC_BASE _AC(0x9800000000000000, UL) > > #else > > #define CAC_BASE _AC(0xa800000000000000, UL) > > #endif > > #endif > > > > So, before, the uncached_base is 0x9000000000000000. > > > > Regards, > > Wu Zhangjin > > > > > From wuzhangjin@gmail.com Tue Apr 27 06:05:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 06:05:56 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:63316 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490995Ab0D0EFw (ORCPT ); Tue, 27 Apr 2010 06:05:52 +0200 Received: by gwb1 with SMTP id 1so596178gwb.36 for ; Mon, 26 Apr 2010 21:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=oXgufPCcdKjwF9iEZBIQTx/2ZVdoHposGJFaZSS4hF0=; b=wcDTumKD0iH1jI3KFoa2upTsmqFMBCLOLfW/y8a0myfr+rb6m82ESTpuF8pTFcXqqE EmzdEslgu6Gc1VibVQ1PX63Uy1JQkcdQaslFntFVYzxJZ7A0NnDf424Hh4eEWvPB58vX uGwERyp2IV3Xo41i+ZN4dcACTknWFOEoVqc1A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=CqqqtlmsCozKzhZTWJMWylTRmuyySNY2edbnxDBIZHkaoWHUDdt7ccJbWZEZaSGnbQ JKRtZIosxUXj2SuZLyaNnblHOsfiFdg7gWE4p9qv7KER5tCy0V515txuwtHGO5rT8WE3 stHTSj9Fz5cjuyruOaoiBe5uCJLlqxx3qbDpk= Received: by 10.150.159.15 with SMTP id h15mr4701827ybe.27.1272341144572; Mon, 26 Apr 2010 21:05:44 -0700 (PDT) Received: from [192.168.2.213] ([202.201.14.140]) by mx.google.com with ESMTPS id 16sm1745522gxk.13.2010.04.26.21.05.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 26 Apr 2010 21:05:43 -0700 (PDT) Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: David Daney Cc: post@pfrst.de, Ralf Baechle , linux-mips In-Reply-To: <4BD62E38.10707@caviumnetworks.com> References: <4BD62E38.10707@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Tue, 27 Apr 2010 12:05:37 +0800 Message-ID: <1272341137.21095.55.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26482 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Mon, 2010-04-26 at 17:22 -0700, David Daney wrote: [...] > > Some time ago we needed to handle multiple (virtual) address-spaces > > (in TO_CAC/TO_UNCAC as well as in virt_to_phys and the like) for > > SGI's Indigo2/R10k and Octane (neither could run a 32bit kernel). > > So in addrspace.h we provided > > #ifdef CONFIG_64BIT > > static inline unsigned long kernel_physaddr(unsigned long kva) > > { > > if((kva&0xffffffff80000000UL)==0xffffffff80000000UL) > > return CPHYSADDR(kva); > > return XPHYSADDR(kva); > > } > > #else > > #define kernel_physaddr CPHYSADDR > > #endif > > while mach-ipXX/spaces.h defined > > #define TO_PHYS(x) ( kernel_physaddr(x)) > > #define TO_CAC(x) (CAC_BASE | kernel_physaddr(x)) > > #define TO_UNCAC(x) (UNCAC_BASE | kernel_physaddr(x)) > > which did the job. > > But at that time these defines didn't meet much acceptance for general > > use in 64bit kernels. Now, to my amusement, some modern processor > > (and/or system) seems to urge this kind of address-handling again ;-) > > > > > > FWIW, that seems cleaner than what I did (actually I didn't try my > code). That should be the default definition for 64-bit kernels I think. Should we let this stuff be a common implementation? then we can also provide the TO_CAC(), TO_PHYS(), TO_UNCAC() to the 32bit kernel and remove some #ifdef from the kernel, for example: > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index 1a4dd65..fb8cd40 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -1557,12 +1557,7 @@ static char panic_null_cerr[] __cpuinitdata = > void __cpuinit set_uncached_handler(unsigned long offset, void *addr, > unsigned long size) > { > -#ifdef CONFIG_32BIT > - unsigned long uncached_ebase = KSEG1ADDR(ebase); > -#endif > -#ifdef CONFIG_64BIT > unsigned long uncached_ebase = TO_UNCAC(ebase); > -#endif > And I have found lots of places have used KSEG1ADDR() in the kernel source code, If the TO_UNCAC() for 32bit is provided, then we can also replace it by TO_UNCAC(). I will try to make a patch for it. Regards, Wu Zhangjin From wuzhangjin@gmail.com Tue Apr 27 07:46:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 07:46:14 +0200 (CEST) Received: from mail-gx0-f228.google.com ([209.85.217.228]:52371 "EHLO mail-gx0-f228.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491176Ab0D0FqL (ORCPT ); Tue, 27 Apr 2010 07:46:11 +0200 Received: by gxk28 with SMTP id 28so7819954gxk.7 for ; Mon, 26 Apr 2010 22:46:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=KpdDFgJZHuT+9XPcFIof5moO7LpcWYDsXXLWVVxTetM=; b=V3BF/G2t7tzVhlFHY9LYd3PqU/yeZkixvQswdldyspzpDIM8pZbfmxhACv7EUcP/4Z VX0umvpZrTjHWavBsRSzq2c4tyFm4THBSx+OCZP7zUDGptXPGMUg/RdeDP/NMNx7LCQT QPH/xSLmZJ7jwOpC3z6GZXAoQH67YR0nfnD3g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=nR4CL8PkcALC+399ap9rrYE0Brm3AlHvW11s1lpZX7d2w/YzMLGSOL7qpdAnvVC0im BvsVuQHIb52vOTlid0OLgjzS2dCjAovLvo9irNq+i7E/psQ3VLhuXU0D2gcHF42++Qxb Q8BcwP6/K8Nv8Ax0R3l5Qsd/hDVfV6bO87fQ8= Received: by 10.150.120.9 with SMTP id s9mr5111522ybc.299.1272347164743; Mon, 26 Apr 2010 22:46:04 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 16sm1784921gxk.9.2010.04.26.22.46.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 26 Apr 2010 22:46:04 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: David Daney , Thomas Bogendoerfer , post@pfrst.de, linux-mips , Wu Zhangjin Subject: [PATCH 1/2] MIPS: Fixup and cleanup of TO_PHYS(), TO_CAC(), TO_UNCAC() Date: Tue, 27 Apr 2010 13:45:46 +0800 Message-Id: <1272347147-15071-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26483 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch fixes the TO_UNCAC() interface of 64bit kernel, the TO_UNCAC(0xffffffff80000000) should yield 0x9000000000000000, but the old TO_UNCAC() yield 0x97ffffff80000100 and make the kernel stop booting with a bad address exception. BTW, to share the same interface and remove the awful #ifdef, this patch also provide the TO_PHYS(), TO_CAC(), TO_UNCAC() interfaces for the 32bit kernel, then we can substitue TO_UNCAC() for lots of old KSEG1ADDR(). Thanks very much to Ralf, David, Thomas Bogendoerfer and post@pfrst.de for their feedbacks of the following bug report: http://www.linux-mips.org/archives/linux-mips/2010-04/msg00055.html This patch is almost based on their feedbacks. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/addrspace.h | 13 +++++++++++++ arch/mips/include/asm/mach-generic/spaces.h | 8 ++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 569f80a..58c3fe7 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -136,6 +136,19 @@ */ #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ +#ifdef CONFIG_64BIT +#define kernel_physaddr(x) ({ \ + u64 a = (u64)(x); \ + if ((a & CKSEG0) == CKSEG0) \ + a = CPHYSADDR(a); \ + else \ + a &= TO_PHYS_MASK; \ + a; \ +}) +#else +#define kernel_physaddr CPHYSADDR +#endif + #ifndef CONFIG_CPU_R8000 /* diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index c9fa4b1..710f160 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -69,12 +69,12 @@ #define HIGHMEM_START (_AC(1, UL) << _AC(59, UL)) #endif -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) - #endif /* CONFIG_64BIT */ +#define TO_PHYS(x) kernel_physaddr(x) +#define TO_CAC(x) (CAC_BASE | kernel_physaddr(x)) +#define TO_UNCAC(x) (UNCAC_BASE | kernel_physaddr(x)) + /* * This handles the memory map. */ -- 1.7.0 From wuzhangjin@gmail.com Tue Apr 27 07:46:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 07:46:39 +0200 (CEST) Received: from mail-gx0-f228.google.com ([209.85.217.228]:52371 "EHLO mail-gx0-f228.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491192Ab0D0FqL (ORCPT ); Tue, 27 Apr 2010 07:46:11 +0200 Received: by mail-gx0-f228.google.com with SMTP id 28so7819954gxk.7 for ; Mon, 26 Apr 2010 22:46:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=ICTLGVzI7eslsRMqcC3oJOexzS0ayJ4kaaH8zvTT4Cs=; b=YK+rVZyS4lbvBxS11uletaQxR9IQa5iZnvC4eQBT6qBxJu70ucbKWY/v1SrZ+cBhil Q2xe9Wdj30TAG4Xy2PbhzQcmjDCvavHpeMwlOhBh7kSTD95TnAAM8duQl5G7dWIXrNA+ ROFMfyvlSpif3UYN9q04+LzISsQ5ZJiBqFTgU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=nJl4a63SqYpqShQCB6v4o0waqLGt0P29bRRy9ChQKkGCWkaeheaUoogRqTh/zn4Fr6 HAfCM6wqOnc8UnvYmL6bjcKTXhlUbeOJmlIaN7lNd5XhbMMzcScD7+d88XVrBmSvyLUN B5pBQPnnCVrFk/gPabj4vPpcfElsncjr1tqDg= Received: by 10.101.137.35 with SMTP id p35mr778617ann.204.1272347171274; Mon, 26 Apr 2010 22:46:11 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 16sm1784921gxk.9.2010.04.26.22.46.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 26 Apr 2010 22:46:10 -0700 (PDT) From: Wu Zhangjin To: Ralf Baechle Cc: David Daney , Thomas Bogendoerfer , post@pfrst.de, linux-mips , Wu Zhangjin Subject: [PATCH 2/2] MIPS: Cleanup of set_uncached_handler() Date: Tue, 27 Apr 2010 13:45:47 +0800 Message-Id: <1272347147-15071-2-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1272347147-15071-1-git-send-email-wuzhangjin@gmail.com> References: <1272347147-15071-1-git-send-email-wuzhangjin@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26484 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin The commit "MIPS: Fixup and cleanup of TO_PHYS(), TO_CAC(), TO_UNCAC()" has provided a TO_UNCAC() for 32bit kernel, so, we can share the same code between 32bit and 64bit kernel in set_uncached_handler(). Signed-off-by: Wu Zhangjin --- arch/mips/kernel/traps.c | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 1a4dd65..fb8cd40 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1557,12 +1557,7 @@ static char panic_null_cerr[] __cpuinitdata = void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { -#ifdef CONFIG_32BIT - unsigned long uncached_ebase = KSEG1ADDR(ebase); -#endif -#ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); -#endif if (!addr) panic(panic_null_cerr); -- 1.7.0 From rampxxxx@gmail.com Tue Apr 27 10:24:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 10:24:35 +0200 (CEST) Received: from mail-bw0-f218.google.com ([209.85.218.218]:64724 "EHLO mail-bw0-f218.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491831Ab0D0IYc convert rfc822-to-8bit (ORCPT ); Tue, 27 Apr 2010 10:24:32 +0200 Received: by bwz10 with SMTP id 10so12181921bwz.24 for ; Tue, 27 Apr 2010 01:24:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:mime-version:received:in-reply-to :references:from:date:message-id:subject:to:cc:content-type :content-transfer-encoding; bh=RUgwB2LQ8e3mjguEKqHW5dw3TfqVTjuaFx1p4Bv4xKo=; b=hQfVD03lNUY07caH2W1crykz4kwYbNn9L6IXj+OaMDBqEBGNLduPg4l9tRrIsWMm/B H9nT74yjoa5IAG+sVJEdyaLffs5gBRLcDSjVSA/qEMmD3otzG4tV3q44Kv9jfSFqQ6iv 6zTfFA62gI4O+7YkAHVG1jajOCZXUd966sXbU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:content-transfer-encoding; b=xkHxf1Pyw3AQWdaXiRLB6ZF6pxdg/vHOza56gvQ/tEvCc+/bx7GofcakSktukqEOnH AQ5F0QYDZNPnjkYAN/BGrRuSNpKMLrGEMhefS1SLsEOzcc/vdLrWz7gn6ZPfUxT0boEr CxEgiATUuStwNZPt4HlKICOLhZ0SrjX3vTUdY= Received: by 10.102.15.22 with SMTP id 22mr2993040muo.7.1272356665100; Tue, 27 Apr 2010 01:24:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.177.13 with HTTP; Tue, 27 Apr 2010 01:24:05 -0700 (PDT) In-Reply-To: <4BD5C7F8.6050406@caviumnetworks.com> References: <4BD5C7F8.6050406@caviumnetworks.com> From: "Giant Sand Fan's" Date: Tue, 27 Apr 2010 10:24:05 +0200 Message-ID: Subject: Re: Cavium mips64 perf counters To: David Daney Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26485 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rampxxxx@gmail.com Precedence: bulk X-list: linux-mips 0h, thank you David. So can I do something like : A.-) %CPU == (LOG_PERF_CNT_SISSUE)+(LOG_PERF_CNT_DISSUE*2)*100/CVMX_LOG_PERF_CNT_CLK or B.-) %CPU == (CVMX_LOG_PERF_CNT_ISSUE*100)/CVMX_LOG_PERF_CNT_CLK I setup and read perf counters with : mtc0 %0, $25, 0 dmfc0 %0, $25, 1 but I think that I can only read two counters so I can only use "B". ... or I'm totally wrong 2010/4/26 David Daney : > On 04/26/2010 06:40 AM, Giant Sand Fan's wrote: >> >> Hi, >> >> I'm trying to calculate de CPU load by access the performance counters >> in mips and I haved reading in the cp0 but my problem is that I cannot >> find documentation about the real meaning of these counters : >> >> 1.-LOG_PERF_CNT_NISSUE : żmeans cycle with no issue? >> >> 2.-LOG_PERF_CNT_SISSUE : żmeans cycle with     issue? > > Single issue. > >> >> 3.-LOG_PERF_CNT_DISSUE: żmeans cycle with double issue? >> > > That's right.  And PERF_CNT_CLK is the number of cycles. > > David Daney > -- Please avoid sending me Word or PowerPoint attachments. See http://www.gnu.org/philosophy/no-word-attachments.html From manuel.lauss@googlemail.com Tue Apr 27 14:14:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 14:14:36 +0200 (CEST) Received: from fg-out-1718.google.com ([72.14.220.155]:34620 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491092Ab0D0MOd (ORCPT ); Tue, 27 Apr 2010 14:14:33 +0200 Received: by fg-out-1718.google.com with SMTP id e12so1270920fga.6 for ; Tue, 27 Apr 2010 05:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=jFSdP2eKxW2WctFyaOKBOQDDYlcJ/rdfHayiC4xnCL0=; b=TYeLiXJPapCkUE1t2gRxVlwcAFsxQrnWHZCkodNMwIOfHCcTqNyf5PPdbWSgFKrpPV 6VT6U4FmtMl+rA9hMQRynUuKmMz5vV4Gk/5qUnNRiC4QD294DZ3ZreL/oYIXJiMQ+3GN zhhOg9jIQU9Atp+zD9PySkUiKCfvQHGKHa4t8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=WH08/WiMIL5/DWb7jF3YeHaTKR+VKCqxUhxMtHXc8V+1UsHther/kJeBWptqMX92vn qAsDYfhK1MS9zmuD4plQS/gAuiFMX0t+vk+d3ns/S2DYvbIC3UsTQxsbAgTN38ekdh+w uaOyVsPqV+2Tok35sy083VaALIp9pk+Rp1UUs= MIME-Version: 1.0 Received: by 10.86.124.35 with SMTP id w35mr4724010fgc.49.1272370472872; Tue, 27 Apr 2010 05:14:32 -0700 (PDT) Received: by 10.223.106.12 with HTTP; Tue, 27 Apr 2010 05:14:32 -0700 (PDT) Date: Tue, 27 Apr 2010 14:14:32 +0200 Message-ID: Subject: use bootmem in platform code on MIPS From: Manuel Lauss To: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26486 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Hello, I'd like to use bootmem to reserve large chunks of RAM (at a particular physical address; for Au1200 MAE, CIM and framebuffer, and later Au1300 OpenGL block) but it seems that it can't be done: Doing __alloc_bootmem() in plat_mem_setup() is too early, while an arch_initcall() is too late because by then the slab allocator is already up and handing out random addresses and/or refusing allocations larger than a few MBytes. Is there another callback I could use which would allow me to use bootmem (short of abusing plat_smp_setup)? Would a separate callback like this be an acceptable solution? --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -487,6 +487,10 @@ static void __init arch_mem_init(char **cmdline_p) } bootmem_init(); + + if (plat_bootmem_init) + plat_bootmem_init(); + sparse_init(); paging_init(); } Thanks, Manuel Lauss From dmo.lists@gmail.com Tue Apr 27 18:11:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 18:11:10 +0200 (CEST) Received: from mail-wy0-f176.google.com ([74.125.82.176]:43242 "EHLO mail-wy0-f176.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492147Ab0D0QLH (ORCPT ); Tue, 27 Apr 2010 18:11:07 +0200 Received: by wyb40 with SMTP id 40so3094315wyb.35 for ; Tue, 27 Apr 2010 09:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=By19QUSI7ibvzTJxgBGh5y38gORZ9V2ObRyy7k38nWk=; b=N6V6KVNs8t91I3Tc3pjCWpMiugr5bywoc6GOf8vr1IZTIQN+N/SMmQB/8j3StuKLIP D+Ar/1wtUbfi5foaJURewAK0+3NcCADQ1HGyrUTFlwDyHfUq0VgCXnZDT7i4zRJfG8zS irXeEysFEKrutVbMMzC6TJEWBoAvZ2OSEAhMQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=Di7CjJyRmh+fU2yFXHYSvmuxBfl5ATYDhZKDPL69SU6pP5hRV/i6Npymw/FpFD/im3 yXWD5pjAuySuqnKKOdCEgKJXklp3zJ7denlBrtv0567nXZvvSJKcLodU8WAxpOWliiYU tycNb/msalXDXJ0iaRKwfwK+XgJ38V852RQ+8= MIME-Version: 1.0 Received: by 10.216.87.80 with SMTP id x58mr8406657wee.96.1272384660733; Tue, 27 Apr 2010 09:11:00 -0700 (PDT) Received: by 10.216.166.12 with HTTP; Tue, 27 Apr 2010 09:11:00 -0700 (PDT) Date: Tue, 27 Apr 2010 09:11:00 -0700 Message-ID: Subject: issue with gdb load_symbol_file command when loading symbols for MIPS kernel modules From: David Olien To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26487 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmo.lists@gmail.com Precedence: bulk X-list: linux-mips I am using gdb version 6.8-1, running on an x86-64 platform with kernel version 2.6.26-2-686 (it's a Debian distrubtion) to debug a remote MIPS kernel, 2.6.22. I have built the gdb on the x86 machine, using the configuration parameter --target=mipsel-unknown-linux-gnu. After loading the kernel modules on the remote mips machine, I get the module load addresses from /proc/modules on the remote machine, and try to add them to the gdb's symbol table on the local machine, using the command: add-symbol-file {path to local copy of the remote machine's .ko file} {module load address retreived from remote machine's /proc/modules} After I do this, I can see that .text symbols are translated correctly to their memory address on the remote machine. But sumbols from the .bss and .data sections are NOT translated properly. In fact, the translate to addresses that are not even in the range of addresses valid for the kernel. Since then, I tried calculating which sections are loaded from the .ko, and where each section gets loaded into kernel memory (I put print statements in the remote kernel's kernel/modules.c source file). If I then give add-symbol-file the address of every loaded section, then I get properly translated symbols for .data and .bss. I have noticed that the address caluclation code in gdb's symfile.c is similar to but different from that in the kernel's module.c file. I am suspecting that the MIPS compiler tools are producing .ko files that are different enough in some way to confuse gdb's code in symbfile.c. Has anyone else encountered this, or have any suggestions? As a work around, I'm planning to write a utility with code stolen from kernel/modules.c that will calculate for me the section addresses based on the module loading address. But it would be nice if gdb did that calculation for me, as I suspect it would for an x86 system. Any suggestions? Thanks! Dave From sebastian@breakpoint.cc Tue Apr 27 22:53:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Apr 2010 22:53:38 +0200 (CEST) Received: from Chamillionaire.breakpoint.cc ([85.10.199.196]:42979 "EHLO Chamillionaire.breakpoint.cc" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492537Ab0D0Uxe (ORCPT ); Tue, 27 Apr 2010 22:53:34 +0200 Received: id: bigeasy by Chamillionaire.breakpoint.cc with local (easymta 1.00 BETA 1) id 1O6rmc-0000Mk-F1; Tue, 27 Apr 2010 22:53:30 +0200 Date: Tue, 27 Apr 2010 22:53:30 +0200 From: Sebastian Andrzej Siewior To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [PATCH] mips/traps: use CKSEG1ADDR for uncache handler Message-ID: <20100427205330.GA1390@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline X-Key-Id: FE3F4706 X-Key-Fingerprint: FFDA BBBB 3563 1B27 75C9 925B 98D5 5C1C FE3F 4706 User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26488 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sebastian@breakpoint.cc Precedence: bulk X-list: linux-mips since "MIPS: Calculate proper ebase value for 64-bit kernels" my mips toy did not boot anymore. Before that commit we always touched xkphys/shared as ebase and computed xphsys/unchached for that area. After that commit ebase become 32bit compat address and convert does not work anymore. So I guess now want to touch the 32bit compat unmapped & uncached area for this. CKSEG1ADDR does just in 32bit and 64bit. Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/kernel/traps.c | 7 +------ 1 files changed, 1 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 4e00f9b..1b57f18 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1557,12 +1557,7 @@ static char panic_null_cerr[] __cpuinitdata = void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { -#ifdef CONFIG_32BIT - unsigned long uncached_ebase = KSEG1ADDR(ebase); -#endif -#ifdef CONFIG_64BIT - unsigned long uncached_ebase = TO_UNCAC(ebase); -#endif + unsigned long uncached_ebase = CKSEG1ADDR(ebase); if (!addr) panic(panic_null_cerr); -- 1.6.6.1 From macro@linux-mips.org Wed Apr 28 01:06:00 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 01:06:04 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:57574 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492697Ab0D0XGA (ORCPT ); Wed, 28 Apr 2010 01:06:00 +0200 Date: Wed, 28 Apr 2010 00:06:00 +0100 (BST) From: "Maciej W. Rozycki" To: David Daney cc: wuzhangjin@gmail.com, Ralf Baechle , Thomas Bogendoerfer , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels In-Reply-To: <4BD5CB08.7010907@caviumnetworks.com> Message-ID: References: <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> <20100413171610.GA16578@linux-mips.org> <1271232185.25872.142.camel@falcon> <4BD5CB08.7010907@caviumnetworks.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26489 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 26 Apr 2010, David Daney wrote: > > If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000, > > then we get the address: 0x97ffffff80000100, is this address ok? > > I don't think so. We should fix TO_UNCAC() so that it works with CKSEG0 > addresses. It should be at physical address 0. So > TO_UNCAC(0xffffffff80000000), should yield 0x9000000000000000 A 0xffffffff80000000 -> 0xffffffffa0000000 translation would make more sense IMHO. Of course the use of XKPHYS addresses rather than CKSEG ones is preferable for 64-bit kernels in the first place, but then if the compatibility address space has been chosen for some reason (perhaps a virtual address stored in a structure defined by a peripheral is limited to 32 bits; I've seen such cases in DMA descriptor rings for example (not that code doing such things couldn't be converted to use cookies of some sort)), then I think it'll be safer to stick to the space. Maciej From macro@linux-mips.org Wed Apr 28 03:26:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 03:26:32 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:40473 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492732Ab0D1B02 (ORCPT ); Wed, 28 Apr 2010 03:26:28 +0200 Date: Wed, 28 Apr 2010 02:26:28 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Sebastian Andrzej Siewior , linux-mips@linux-mips.org Subject: Re: [RFC] net/sb1250: setup the pdevice within the soc code In-Reply-To: <20100426210022.GE27656@linux-mips.org> Message-ID: References: <20100426195229.GB22245@Chamillionaire.breakpoint.cc> <20100426202459.GD27656@linux-mips.org> <20100426204122.GA23697@Chamillionaire.breakpoint.cc> <20100426210022.GE27656@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26490 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 26 Apr 2010, Ralf Baechle wrote: > > doing it within the driver does not look good. > > And surely isn't how platform devices were meat to be used. > > > Signed-off-by: Sebastian Andrzej Siewior > > Go ahead: > > Acked-by: Ralf Baechle That was the long-term plan back when the driver was updated to its current form. Thanks for pushing this forward. Acked-by: Maciej W. Rozycki Maciej From wilbur512@gmail.com Wed Apr 28 03:29:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 03:29:38 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:44882 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492705Ab0D1B3f (ORCPT ); Wed, 28 Apr 2010 03:29:35 +0200 Received: by gyb11 with SMTP id 11so7153194gyb.36 for ; Tue, 27 Apr 2010 18:29:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=BHcZ0m0MMKlI3wImDAJ1o8XGrfwa8NKaSq4K3Kgo3Hs=; b=dJ+IpibCbZTJ4a+03npewFm+gbVtKLTTYkHh8Amords43bxPfbByMSawn3GvMoE5gX Jpn3B9CCgjPhTdy3sNQFsqhRGMGdBx8GHqJNUC/AArWenMoVy6QUEQl1oZ6ChNvQ+jyD bFioqLzt87ZHLr0cWEYFXfzXa8KIlbLKQwIps= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=wSH/pOjmvVmSQTm2YMCkp82Mx2Oa6OBDyCL8WlHj+BI2oESYIgGX/D+WlLfxaKbR/j a3MMr2v5rgPvIkQbVuwBEs6C0CEC75lhbKpEU7LrxaYYWlFCGZ2FgMginWf5f2IrXM+i 32luE08oRMhYG6eYTioqZrXm5eutdD8n7MerU= MIME-Version: 1.0 Received: by 10.91.190.11 with SMTP id s11mr3634008agp.50.1272418167789; Tue, 27 Apr 2010 18:29:27 -0700 (PDT) Received: by 10.90.99.14 with HTTP; Tue, 27 Apr 2010 18:29:27 -0700 (PDT) Date: Wed, 28 Apr 2010 09:29:27 +0800 Message-ID: Subject: [octeon]segment without execution priviledge,causing system down. From: "wilbur.chan" To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26491 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips I'm using a modified kernel version derived from 2.6.21.7,and the cpu is octeon cn5860. Strangely I found that , when executing some instruction in un-executable segment, the system will hang on, together with console down, and could not response to ping command. cn5860 has 16 CPUs, in our system , each non-zero cpu is running a real-time user-mode process with 99 priority(network business) , causing non-zero cpus to 100% cpu-usage. while cpu 0 ,is in charge of coordinating the whole system ,almost to 5~6% cpu-usage. That is , the following code ,will cause a problem , which hang the cpu 0, and then hang the whole system: #include #include char stack[8*1024] = {0}; // in un-executable segment void (*func)(void); int main() { func = (void (*)(void))stack; //convert to function pointer func(); //cpu will hang return 0; } In my opinion, the code above should generate a page_fault exception , and caused SIGSEGV error, however in my system , it hang on directly. Any one knows why this happened? Thanks regards, wilbur From david.s.daney@gmail.com Wed Apr 28 07:02:03 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 07:02:12 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:51569 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491005Ab0D1FCD (ORCPT ); Wed, 28 Apr 2010 07:02:03 +0200 Received: by gwb1 with SMTP id 1so1014006gwb.36 for ; Tue, 27 Apr 2010 22:01:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; bh=KsMUWqvDEVSpD35NIUGctgctuZgn6OUUQKo28uCysCg=; b=Oux1vyGkXuDvI+EOc91tuLdVv2zxzfhzCpyOWbuBPfDTQf/J3ghrBZlC0Hkxme9kZ4 aWsSN3XUtAIVVnlxXCZY7Cml1aM3ILVEQOP8Y1PrQMx3OmU0dQCm6zcze/XVV22NaBsR XBgCkf+mZ/WSWSUPpyY+zvkKzufO8Pkk+r/9w= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=F1zdR1G0yFRQdKaVde45n6QwTOL8FnNTkVC/pNZ0ws03RDToDdhE8XfnmEbmGyQBuL IRlEkdFZTEesfVyWr/bu9XaXGiHQ6sgouGfXB2Fso+FfiHEgxxY6UPY7vmDCUbgXh0U5 SFYW16TykYvjQ4w2jIR6pwRpNkwljCcZRf7y0= Received: by 10.101.175.37 with SMTP id c37mr2172785anp.56.1272430913191; Tue, 27 Apr 2010 22:01:53 -0700 (PDT) Received: from dd_xps.caveonetworks.com (adsl-67-127-190-169.dsl.pltn13.pacbell.net [67.127.190.169]) by mx.google.com with ESMTPS id 26sm61326763anx.13.2010.04.27.22.01.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 27 Apr 2010 22:01:52 -0700 (PDT) Message-ID: <4BD7C13D.6060609@gmail.com> Date: Tue, 27 Apr 2010 22:01:49 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc11 Thunderbird/3.0.4 MIME-Version: 1.0 To: "wilbur.chan" CC: Linux MIPS Mailing List , David Daney Subject: Re: [octeon]segment without execution priviledge,causing system down. References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26492 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.s.daney@gmail.com Precedence: bulk X-list: linux-mips On 04/27/2010 06:29 PM, wilbur.chan wrote: > I'm using a modified kernel version derived from 2.6.21.7,and the cpu > is octeon cn5860. Strangely I found that , when executing > > some instruction in un-executable segment, the system will hang on, > together with console down, and could not response to ping > > command. > [...] > Any one knows why this happened? Thanks > I think I know. There is a bug in your kernel. Since execute inhibit support was not added to the upstream kernel until very recently, we must assume you got your kernel from some vendor. You could either ask the vendor for a fix, or back port it yourself from: http://www.linux-mips.org/git?p=linux.git;a=commitdiff;h=6dd9344cfc41bcc60a01cdc828cb278be7a10e01 David Daney From dengcheng.zhu@gmail.com Wed Apr 28 13:54:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 13:54:59 +0200 (CEST) Received: from mail-pz0-f194.google.com ([209.85.222.194]:37436 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492032Ab0D1Lyy (ORCPT ); Wed, 28 Apr 2010 13:54:54 +0200 Received: by pzk32 with SMTP id 32so9736328pzk.21 for ; Wed, 28 Apr 2010 04:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=Urea0C5OwSG0P5XgXUturR/rpPSN7yPgqkcsQnmH6+c=; b=YNTa7UhHuR+ey+My0bXGHllb8FsdzeY487Zl/HTyTjj6Xd3IgGDqm/7vbohLiXVmDe R6ythEXItxsZFRHAEBaRz2KhyjNED76mRpjpDLTSCEG8q/XV4pIoY8sVSamaCk8LJ+EB lQpYEUtGEtwTjaaluB6RBY4yNOwJnXxNVfRNE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=xjL9guklraw6kTxfciqA3HLWe1EiN541IAMRnWoACHrCJCN69dkum3DmURUadhzDmr Y96kVVDNN+J3SFAQ6lNnwoDfwrGN/xZUcMR8fEtf6izuLjeGR641SgME7Ip5t9WU443M tlGSpDZ5LPdOvARHWvJKL9D87o3JWigGlvOZ8= Received: by 10.140.57.16 with SMTP id f16mr1221532rva.15.1272455685694; Wed, 28 Apr 2010 04:54:45 -0700 (PDT) Received: from localhost.localdomain ([114.84.90.248]) by mx.google.com with ESMTPS id 23sm1923736ywh.12.2010.04.28.04.54.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 28 Apr 2010 04:54:45 -0700 (PDT) From: Deng-Cheng Zhu To: ralf@linux-mips.org, ddaney@caviumnetworks.com, linux-mips@linux-mips.org Cc: dengcheng.zhu@gmail.com Subject: [PATCH] Perf-tool/MIPS: support cross compiling of tools/perf for MIPS Date: Wed, 28 Apr 2010 19:54:34 +0800 Message-Id: <1272455674-4725-1-git-send-email-dengcheng.zhu@gmail.com> X-Mailer: git-send-email 1.6.3.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26493 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips With the kernel facility of Linux performance counters, we want the user level tool tools/perf to be cross compiled for MIPS platform. To do this, we need to include unistd.h, add rmb() and cpu_relax() in perf.h. Your review comments are especially required for the definition of rmb(): In perf.h, we need to have a proper rmb() for _all_ MIPS platforms. And we don't have CONFIG_* things for use in here. Looking at barrier.h, rmb() goes into barrier() and __sync() for CAVIUM OCTEON and other CPUs, respectively. What's more, __sync() has different versions as well. Referring to BARRIER() in dump_tlb.c, I propose the "common" definition for perf tool rmb() in this patch. Do you have any comments? In addition, for testing the kernel part code I sent several days ago, I was using the "particular" rmb() version for 24K/34K/74K cores: #define rmb() asm volatile( \ ".set push\n\t" \ ".set noreorder\n\t" \ ".set mips2\n\t" \ "sync\n\t" \ ".set pop" \ : /* no output */ \ : /* no input */ \ : "memory") This is the definition of __sync() for CONFIG_CPU_HAS_SYNC. Thanks, Deng-Cheng Signed-off-by: Deng-Cheng Zhu --- tools/perf/perf.h | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/tools/perf/perf.h b/tools/perf/perf.h index 6fb379b..cd05284 100644 --- a/tools/perf/perf.h +++ b/tools/perf/perf.h @@ -69,6 +69,18 @@ #define cpu_relax() asm volatile("":::"memory") #endif +#ifdef __mips__ +#include "../../arch/mips/include/asm/unistd.h" +#define rmb() asm volatile( \ + ".set noreorder\n\t" \ + "nop;nop;nop;nop;nop;nop;nop\n\t" \ + ".set reorder" \ + : /* no output */ \ + : /* no input */ \ + : "memory") +#define cpu_relax() asm volatile("" ::: "memory") +#endif + #include #include #include -- 1.7.0.4 From Gurumurthy.Gowdar@gmobis.com Wed Apr 28 14:47:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 14:47:37 +0200 (CEST) Received: from anti.mobis.co.kr ([211.217.52.67]:35305 "HELO sniper.mobis.co.kr" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492148Ab0D1Mrc convert rfc822-to-8bit (ORCPT ); Wed, 28 Apr 2010 14:47:32 +0200 Received: (snipe 26345 invoked by uid 0); 28 Apr 2010 21:47:19 +0900 Received: from gurumurthy.gowdar@gmobis.com with Spamsniper 2.94.22 (Processed in 0.069998 secs); Received: from unknown (HELO msmobiweb.mobis.co.kr) (10.240.100.165) by unknown with SMTP; 28 Apr 2010 21:47:19 +0900 X-RCPTTO: linux-mips@linux-mips.org Received: from mkegmal01.global.mobis.co.kr ([10.240.200.82]) by msmobiweb.mobis.co.kr with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 21:47:20 +0900 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: MIPS ROM Exception Handler Error Date: Wed, 28 Apr 2010 21:47:20 +0900 Message-ID: <5858DE952C53A441BDA3408A0524130104CCE09C@mkegmal01> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: MIPS ROM Exception Handler Error Thread-Index: Acrm0PD7TjuMeXpsSp+LA6xj2BvWfg== From: =?iso-8859-1?Q?=A0Gurumurthy_G_M?= To: X-OriginalArrivalTime: 28 Apr 2010 12:47:20.0855 (UTC) FILETIME=[F13FB270:01CAE6D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26494 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Gurumurthy.Gowdar@gmobis.com Precedence: bulk X-list: linux-mips Hi all, I am porting U-boot-2010.03 on MIPS32 Architecture ( au1350 processor). u-boot is compiled for little endian and downloaded the u-boot.bin file to NOR Flash.After reset followed by go command , I observe that cpu hangs at 0xbfc00570 (ROM Exception Handler). we are using BDI3000 debugger and bdiGDB for programming. please let me know where is the problem? whether I am missing something. Regards, Gurumurthy From wuzhangjin@gmail.com Wed Apr 28 15:14:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 15:14:28 +0200 (CEST) Received: from mail-ww0-f49.google.com ([74.125.82.49]:63037 "EHLO mail-ww0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492325Ab0D1NOY (ORCPT ); Wed, 28 Apr 2010 15:14:24 +0200 Received: by wwb24 with SMTP id 24so27053wwb.36 for ; Wed, 28 Apr 2010 06:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=SUJ88Z7gp0zd/VIcutveMhORY/8mdk5b6LvxZIksp2o=; b=gcKXN35BhhlyBWYu1svVdbB/Mudpnx7JwOrajF/sX4l7qepq6UYGATxJRDOwx8wmUr hqifwI4Zhj9l7/nivKqSbOZmfehl5OBgxBysFjTiy6Y3LIilUjRjpEfQRRPK/vPkih6b DsQuGs04GMnql04SIao1tCTGk+Ws4WUmL8s8M= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=waGszlmrJuLxx0IZY3lGJtBosfI/U5avlr1Y/97eDsFK4hOCpBXuGky4ChLqSFngNb vHKOy4aHwjnqTdiLnoEq6ih8MnhjxH2/Uyk0q0jodkskzj6Fz0rxlFmHICa/79EFsKz0 219rdjt21bCL66eKqNhVA/2V0WRZmRrh81buQ= Received: by 10.216.87.205 with SMTP id y55mr1042875wee.88.1272460457747; Wed, 28 Apr 2010 06:14:17 -0700 (PDT) Received: from [192.168.2.210] ([202.201.14.140]) by mx.google.com with ESMTPS id z34sm13813813wbv.20.2010.04.28.06.14.12 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 28 Apr 2010 06:14:16 -0700 (PDT) Subject: Re: [PATCH] Perf-tool/MIPS: support cross compiling of tools/perf for MIPS From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Deng-Cheng Zhu Cc: ralf@linux-mips.org, ddaney@caviumnetworks.com, linux-mips@linux-mips.org In-Reply-To: <1272455674-4725-1-git-send-email-dengcheng.zhu@gmail.com> References: <1272455674-4725-1-git-send-email-dengcheng.zhu@gmail.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 28 Apr 2010 21:14:07 +0800 Message-ID: <1272460447.21867.31.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26495 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2010-04-28 at 19:54 +0800, Deng-Cheng Zhu wrote: > With the kernel facility of Linux performance counters, we want the user > level tool tools/perf to be cross compiled for MIPS platform. To do this, > we need to include unistd.h, add rmb() and cpu_relax() in perf.h. > Just found local-compiling also need rmb(). BTW: for local-compiling in a debian linux on MIPS machines, we need to copy linux-source-code/{tools/perf, include, lib} to the machine and install libdw-dev and libelf-dev, so the basic procedure for making perf work on a debian/MIPS: 0. prepare For tools/perf copy the directory {tools/perf, include, lib} of linux $ apt-get install libdw-dev libelf-dev For the kernel support apply deng-cheng's latest patch and ensure CONFIG_HW_PERF_EVENTS=y then boot into the new kernel. 1. compile tools/perf $ ls include lib tools $ ls tools/ perf $ cd tools/perf $ make 2. usage $ ./perf list For a non-raw event $ ./perf stat -e cycles ls -l For a raw event $ ./perf stat -e r120 ls -l Regard, > Your review comments are especially required for the definition of rmb(): > In perf.h, we need to have a proper rmb() for _all_ MIPS platforms. And > we don't have CONFIG_* things for use in here. Looking at barrier.h, > rmb() goes into barrier() and __sync() for CAVIUM OCTEON and other CPUs, > respectively. What's more, __sync() has different versions as well. > Referring to BARRIER() in dump_tlb.c, I propose the "common" definition > for perf tool rmb() in this patch. Do you have any comments? > > In addition, for testing the kernel part code I sent several days > ago, I was using the "particular" rmb() version for 24K/34K/74K cores: > > #define rmb() asm volatile( \ > ".set push\n\t" \ > ".set noreorder\n\t" \ > ".set mips2\n\t" \ > "sync\n\t" \ > ".set pop" \ > : /* no output */ \ > : /* no input */ \ > : "memory") > > This is the definition of __sync() for CONFIG_CPU_HAS_SYNC. > > > Thanks, > > Deng-Cheng > > Signed-off-by: Deng-Cheng Zhu > --- > tools/perf/perf.h | 12 ++++++++++++ > 1 files changed, 12 insertions(+), 0 deletions(-) > > diff --git a/tools/perf/perf.h b/tools/perf/perf.h > index 6fb379b..cd05284 100644 > --- a/tools/perf/perf.h > +++ b/tools/perf/perf.h > @@ -69,6 +69,18 @@ > #define cpu_relax() asm volatile("":::"memory") > #endif > > +#ifdef __mips__ > +#include "../../arch/mips/include/asm/unistd.h" > +#define rmb() asm volatile( \ > + ".set noreorder\n\t" \ > + "nop;nop;nop;nop;nop;nop;nop\n\t" \ > + ".set reorder" \ > + : /* no output */ \ > + : /* no input */ \ > + : "memory") > +#define cpu_relax() asm volatile("" ::: "memory") > +#endif > + > #include > #include > #include From wuzhangjin@gmail.com Wed Apr 28 17:21:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 17:21:42 +0200 (CEST) Received: from fg-out-1718.google.com ([72.14.220.159]:25421 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492020Ab0D1PVf (ORCPT ); Wed, 28 Apr 2010 17:21:35 +0200 Received: by fg-out-1718.google.com with SMTP id e12so1900060fga.6 for ; Wed, 28 Apr 2010 08:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=cTC3NyiSDi1LgRwZHikNYTMrwVXfaOyeTmj6KdTqVRA=; b=iPiFqeZSRIcbUMOH0DyYEOUI9vAiLK1urEeIbkcqZ1bS9u6aQPLPcDDsTUO0wVjGEb cCU/x6A42jAm5Roqpq/zz92SOnhhggl6F9ST82Ftxfna9olve5+oOP9wYH3yyNpBVCrU UZvSBNor+xEiaACYDfta19ACfdLxK86IC/eDI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=WDIdXh1LvWRlohR+pxMc82CFle5eS+9oOBmQbIzn2SfT9kaVrtcsr+EHghlgt+SU8u hTGU3wUQr93YJC4kOzaO3MhrG9zBlnKKPfxMle9D/r9rwMowh3uFqIg/SidDmyfomC4j 7AuQ35Ib8XZG38WZ9iADs3nagVhmqm9j3dT3s= Received: by 10.87.31.36 with SMTP id i36mr5063209fgj.56.1272468093649; Wed, 28 Apr 2010 08:21:33 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 3sm6669052fge.15.2010.04.28.08.21.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 28 Apr 2010 08:21:31 -0700 (PDT) From: Wu Zhangjin To: loongson-dev , linux-mips@linux-mips.org Cc: Deng-Cheng Zhu , ralf@linux-mips.org, Zhang Le , yajin , Wu Zhangjin Subject: [PATCH] Loongson2: add a primary perf support (not applicable) Date: Wed, 28 Apr 2010 23:21:17 +0800 Message-Id: <1272468077-12292-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.7.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26496 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin "perf - Performance analysis tools for Linux [...] Performance counters for Linux are a new kernel-based subsystem that provide a framework for all things performance analysis. It covers hardware level (CPU/PMU, Performance Monitoring Unit) features and software features (software counters, tracepoints) as well." -- tools/perf/Documentation/perf.txt Based on Deng-cheng's perf support for MIPS[1], this patch adds a primary perf support for loongson2. it is far from the full support. To make the basic perf support work on loongson2, you need to use the kernel 2.6.34-rc from [2] and apply Deng-cheng's patches[1] at first, then apply this patch and at last compile it with CONFIG_HW_PERF_EVENTS=y (and please ensure OPROFILE=n). And then you need to compile the user-space tools/perf with the following steps if want to local-compile it: 1. copy the {include, lib, tools/perf} directories of linux source code to the target machines and ensure it looks like this: $ ls include lib tools $ ls tools perf 2. install the basic -dev libs (use debian as an example) $ sudo apt-get install libdw-dev libelf-dev (If not enough, please refer to the error report when compiling, search the header files with the help of "apt-cache search ...") 3. Apply deng-cheng's another patch[3] for tools/perf 4. compile it $ cd tools/perf $ make 5. usage: refer to tools/perf/Documentation/examples.txt $ ./perf list For a non-raw event $ ./perf stat -e cycles ls -l For a raw event $ ./perf stat -e r0 ls -l Currently, seems "./perf record" and lots of software events not work, anybody have interest in playing with it can refer to {tools/perf/Documentation, arch/mips/kernel/perf_event*, arch/mips/include/asm/pmu.h, arch/x86/kernel/cpu/perf_event*, arch/arm/kernel/perf_event* ...}. That's all! Thanks~ [1] http://patchwork.linux-mips.org/project/linux-mips/list/?=Deng-Cheng+Zhu&submitter=168&state= [v2,4/4] MIPS: implementing hardware performance event support [v2,3/4] MIPS: adding support for software performance events [v2,2/4] MIPS: in non-64bit kernel, using the generic atomic64 operations for perf counter support [v2,1/4] MIPS/Oprofile: extracting PMU defines/helper functions for sharing [2] http://dev.lemote.com/code/linux-loongson-community [3] http://patchwork.linux-mips.org/patch/1150/ Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 2 +- arch/mips/include/asm/pmu.h | 19 +- arch/mips/kernel/perf_event.c | 1 + arch/mips/kernel/perf_event_loongson2.c | 470 +++++++++++++++++++++++++++++++ arch/mips/loongson/lemote-2f/irq.c | 3 +- 5 files changed, 484 insertions(+), 11 deletions(-) create mode 100644 arch/mips/kernel/perf_event_loongson2.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5b485a4..51bc385 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1859,7 +1859,7 @@ config NODES_SHIFT config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32 + depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n default y help Enable hardware performance counter support for perf events. If diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h index 6da943c..df409c7 100644 --- a/arch/mips/include/asm/pmu.h +++ b/arch/mips/include/asm/pmu.h @@ -19,6 +19,8 @@ #ifndef __MIPS_PMU_H__ #define __MIPS_PMU_H__ +static int (*save_perf_irq)(void); + #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \ defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1) @@ -41,8 +43,6 @@ #define M_COUNTER_OVERFLOW (1UL << 31) -static int (*save_perf_irq)(void); - #ifdef CONFIG_MIPS_MT_SMP static int cpu_has_mipsmt_pertccounters; #define WHAT (M_TC_EN_VPE | \ @@ -216,15 +216,16 @@ extern unsigned int rm9000_perfcount_irq; #elif defined(CONFIG_CPU_LOONGSON2) -/* - * a patch should be sent to oprofile with the loongson-specific support. - * otherwise, the oprofile tool will not recognize this and complain about - * "cpu_type 'unset' is not valid". - */ +#include + #define LOONGSON2_CPU_TYPE "mips/loongson2" -#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) -#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) +#define MIPS_MAX_HWEVENTS 2 + +#define LOONGSON2_COUNTER1_EVENT(event) (((event) & 0x0f) << 5) +#define LOONGSON2_COUNTER2_EVENT(event) (((event) & 0x0f) << 9) +#define LOONGSON2_PERFCNT_EVENT(event, idx) \ + (((event) & 0x0f) << ((idx) ? 9 : 5)) #define LOONGSON2_PERFCNT_EXL (1UL << 0) #define LOONGSON2_PERFCNT_KERNEL (1UL << 1) diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c index a17dc64..cbcaf43 100644 --- a/arch/mips/kernel/perf_event.c +++ b/arch/mips/kernel/perf_event.c @@ -459,6 +459,7 @@ const struct pmu *hw_perf_event_init(struct perf_event *event) } #include "perf_event_mipsxx.c" +#include "perf_event_loongson2.c" /* * Callchain handling code. diff --git a/arch/mips/kernel/perf_event_loongson2.c b/arch/mips/kernel/perf_event_loongson2.c new file mode 100644 index 0000000..d97bf4a --- /dev/null +++ b/arch/mips/kernel/perf_event_loongson2.c @@ -0,0 +1,470 @@ +#ifdef CONFIG_CPU_LOONGSON2 + +#define LOONGSON2_PERFCNT_COUNT_EVENT_WHENEVER \ + (LOONGSON2_PERFCNT_EXL | LOONGSON2_PERFCNT_KERNEL | \ + LOONGSON2_PERFCNT_USER | LOONGSON2_PERFCNT_SUPERVISOR | \ + LOONGSON2_PERFCNT_INT_EN) + +#define LOONGSON2_PERFCNT_CONFIG_MASK 0x1f + +static inline unsigned int +loongson2_pmu_read_counter(unsigned int idx) +{ + uint64_t counter = read_c0_perfcnt(); + + switch (idx) { + case 0: + return counter & 0xffffffff; + case 1: + return counter >> 32; + default: + WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); + return 0; + } +} + +static inline void +loongson2_pmu_write_counter(unsigned int idx, unsigned int val) +{ + uint64_t counter = read_c0_perfcnt(); + + switch (idx) { + case 0: + write_c0_perfcnt(val | counter); + return; + case 1: + write_c0_perfcnt(((uint64_t)val << 32) | counter); + return; + } +} + +static inline unsigned int +loongson2_pmu_read_control(unsigned int idx) +{ + return read_c0_perfctrl(); +} + +static inline void +loongson2_pmu_write_control(unsigned int idx, unsigned int val) +{ + write_c0_perfctrl(val); + return; +} + +static const struct mips_perf_event loongson2_event_map + [PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN }, + [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD }, + [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN }, + [PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD }, + [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, +}; + +static const struct mips_perf_event loongson2_cache_map + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { +[C(L1D)] = { + /* + * Like some other architectures (e.g. ARM), the performance + * counters don't differentiate between read and write + * accesses/misses, so this isn't strictly correct, but it's the + * best we can do. Writes and reads get combined. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x04, CNTR_ODD }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x04, CNTR_ODD }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x04, CNTR_EVEN }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x04, CNTR_EVEN }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + /* + * Note that MIPS has only "hit" events countable for + * the prefetch operation. + */ + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(DTLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x0d, CNTR_EVEN }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x0d, CNTR_EVEN }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +[C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x0c, CNTR_ODD }, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { 0x0c, CNTR_ODD }, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, + [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, + }, +}, +}; + +static void hw_perf_event_destroy(struct perf_event *event) +{ + if (atomic_dec_and_mutex_lock(&active_events, + &pmu_reserve_mutex)) { + /* + * We must not call the destroy function with interrupts + * disabled. + */ + write_c0_perfctrl(0); + mipspmu_free_irq(); + mutex_unlock(&pmu_reserve_mutex); + } +} + +static int __hw_perf_event_init(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + struct hw_perf_event *hwc = &event->hw; + const struct mips_perf_event *pev; + int err; + + /* Returning MIPS event descriptor for generic perf event. */ + if (PERF_TYPE_HARDWARE == event->attr.type) { + if (event->attr.config >= PERF_COUNT_HW_MAX) + return -EINVAL; + pev = mipspmu_map_general_event(event->attr.config); + } else if (PERF_TYPE_HW_CACHE == event->attr.type) { + pev = mipspmu_map_cache_event(event->attr.config); + } else if (PERF_TYPE_RAW == event->attr.type) { + /* We are working on the global raw event. */ + mutex_lock(&raw_event_mutex); + pev = mipspmu->map_raw_event(event->attr.config); + } else { + /* The event type is not (yet) supported. */ + return -EOPNOTSUPP; + } + + if (IS_ERR(pev)) { + if (PERF_TYPE_RAW == event->attr.type) + mutex_unlock(&raw_event_mutex); + return PTR_ERR(pev); + } + + /* + * We allow max flexibility on how each individual counter shared + * by the single CPU operates (the mode exclusion and the range). + */ + hwc->config_base = LOONGSON2_PERFCNT_INT_EN; + + hwc->event_base = mipspmu_perf_event_encode(pev); + if (PERF_TYPE_RAW == event->attr.type) + mutex_unlock(&raw_event_mutex); + + if (!attr->exclude_user) + hwc->config_base |= LOONGSON2_PERFCNT_USER; + if (!attr->exclude_kernel) { + hwc->config_base |= LOONGSON2_PERFCNT_KERNEL; + /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */ + hwc->config_base |= LOONGSON2_PERFCNT_EXL; + } + if (!attr->exclude_hv) + hwc->config_base |= LOONGSON2_PERFCNT_SUPERVISOR; + + hwc->config_base &= LOONGSON2_PERFCNT_CONFIG_MASK; + /* + * The event can belong to another cpu. We do not assign a local + * counter for it for now. + */ + hwc->idx = -1; + hwc->config = 0; + + if (!hwc->sample_period) { + hwc->sample_period = MAX_PERIOD; + hwc->last_period = hwc->sample_period; + atomic64_set(&hwc->period_left, hwc->sample_period); + } + + err = 0; + if (event->group_leader != event) { + err = validate_group(event); + if (err) + return -EINVAL; + } + + event->destroy = hw_perf_event_destroy; + + return err; +} + +void hw_perf_enable(void) +{ + if (mipspmu) + mipspmu->start(); +} + +void hw_perf_disable(void) +{ + if (mipspmu) + mipspmu->stop(); +} + +static void +handle_associated_event(struct cpu_hw_events *cpuc, + int idx, struct perf_sample_data *data, struct pt_regs *regs) +{ + struct perf_event *event = cpuc->events[idx]; + struct hw_perf_event *hwc = &event->hw; + + mipspmu_event_update(event, hwc, idx); + data->period = event->hw.last_period; + if (!mipspmu_event_set_period(event, hwc, idx)) + return; + + if (perf_event_overflow(event, 0, data, regs)) + mipspmu->disable_event(idx); +} + +static void pause_local_counters(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + local_irq_save(flags); + cpuc->saved_ctrl[0] = read_c0_perfctrl(); + write_c0_perfctrl(cpuc->saved_ctrl[0] & + ~LOONGSON2_PERFCNT_COUNT_EVENT_WHENEVER); + local_irq_restore(flags); +} + +static void resume_local_counters(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + local_irq_save(flags); + write_c0_perfctrl(cpuc->saved_ctrl[0]); + local_irq_restore(flags); +} + +static int loongson2_pmu_handle_shared_irq(void) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct perf_sample_data data; + unsigned int counters = mipspmu->num_counters; + unsigned int counter; + int handled = IRQ_NONE; + struct pt_regs *regs; + + /* Check whether the irq belongs to me */ + if (!(read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN)) + return IRQ_NONE; + + /* + * First we pause the local counters, so that when we are locked + * here, the counters are all paused. When it gets locked due to + * perf_disable(), the timer interrupt handler will be delayed. + * + * See also loongson2_pmu_start(). + */ + pause_local_counters(); + + regs = get_irq_regs(); + + perf_sample_data_init(&data, 0); + + switch (counters) { +#define HANDLE_COUNTER(n) \ + case n + 1: \ + if (test_bit(n, cpuc->used_mask)) { \ + counter = loongson2_pmu_read_counter(n); \ + if (counter & LOONGSON2_PERFCNT_OVERFLOW) { \ + loongson2_pmu_write_counter(n, counter &\ + 0x7fffffff); \ + if (test_and_change_bit(n, cpuc->msbs)) \ + handle_associated_event(cpuc, \ + n, &data, regs); \ + handled = IRQ_HANDLED; \ + } \ + } + HANDLE_COUNTER(1) + HANDLE_COUNTER(0) + } + + /* + * Do all the work for the pending perf events. We can do this + * in here because the performance counter interrupt is a regular + * interrupt, not NMI. + */ + if (handled == IRQ_HANDLED) + perf_event_do_pending(); + + resume_local_counters(); + return handled; +} + +static irqreturn_t +loongson2_pmu_handle_irq(int irq, void *dev) +{ + return loongson2_pmu_handle_shared_irq(); +} + +static void loongson2_pmu_start(void) +{ + resume_local_counters(); +} + +static void loongson2_pmu_stop(void) +{ + pause_local_counters(); +} + +static int +loongson2_pmu_alloc_counter(struct cpu_hw_events *cpuc, + struct hw_perf_event *hwc) +{ + int i; + + /* + * We only need to care the counter mask. The range has been + * checked definitely. + */ + unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; + + for (i = mipspmu->num_counters - 1; i >= 0; i--) { + /* + * Note that some MIPS perf events can be counted by both + * even and odd counters, wheresas many other are only by + * even _or_ odd counters. This introduces an issue that + * when the former kind of event takes the counter the + * latter kind of event wants to use, then the "counter + * allocation" for the latter event will fail. In fact if + * they can be dynamically swapped, they both feel happy. + * But here we leave this issue alone for now. + */ + if (test_bit(i, &cntr_mask) && + !test_and_set_bit(i, cpuc->used_mask)) + return i; + } + + return -EAGAIN; +} + +static void +loongson2_pmu_enable_event(struct hw_perf_event *evt, int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + local_irq_save(flags); + + cpuc->saved_ctrl[idx] = + LOONGSON2_PERFCNT_EVENT(evt->event_base & 0xff, idx) | + (evt->config_base & LOONGSON2_PERFCNT_CONFIG_MASK) | + /* Make sure interrupt enabled. */ + LOONGSON2_PERFCNT_INT_EN; + /* + * We do not actually let the counter run. Leave it until start(). + */ + local_irq_restore(flags); +} + +static void +loongson2_pmu_disable_event(int idx) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + unsigned long flags; + + WARN_ON(idx < 0 || idx >= mipspmu->num_counters); + + local_irq_save(flags); + cpuc->saved_ctrl[idx] = loongson2_pmu_read_control(idx) & + ~LOONGSON2_PERFCNT_COUNT_EVENT_WHENEVER; + loongson2_pmu_write_control(idx, cpuc->saved_ctrl[idx]); + local_irq_restore(flags); +} + +/* + * User can use 0-255 raw events, where 0-127 for the events of even + * counters, and 128-255 for odd counters. Note that bit 7 is used to + * indicate the parity. So, for example, when user wants to take the + * Event Num of 15 for odd counters (by referring to the user manual), + * then 128 needs to be added to 15 as the input for the event config, + * i.e., 143 (0x8F) to be used. + */ +static const struct mips_perf_event * +loongson2_pmu_map_raw_event(u64 config) +{ + unsigned int raw_id = config & 0xff; + unsigned int base_id = raw_id & 0x7f; + + raw_event.event_id = base_id; + raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN; + + return &raw_event; +} + +static struct mips_pmu loongson2_pmu = { + .handle_irq = loongson2_pmu_handle_irq, + .handle_shared_irq = loongson2_pmu_handle_shared_irq, + .start = loongson2_pmu_start, + .stop = loongson2_pmu_stop, + .alloc_counter = loongson2_pmu_alloc_counter, + .read_counter = loongson2_pmu_read_counter, + .write_counter = loongson2_pmu_write_counter, + .enable_event = loongson2_pmu_enable_event, + .disable_event = loongson2_pmu_disable_event, + .map_raw_event = loongson2_pmu_map_raw_event, + .general_event_map = &loongson2_event_map, + .cache_event_map = &loongson2_cache_map, +}; + +static int __init +init_hw_perf_events(void) +{ + pr_info("Performance counters: "); + + /* Reset counters */ + write_c0_perfctrl(0); + + loongson2_pmu.name = LOONGSON2_CPU_TYPE; + loongson2_pmu.num_counters = 2; + mipspmu = &loongson2_pmu; + + if (mipspmu) + pr_cont("%s PMU enabled, %d counters available to each " + "CPU\n", mipspmu->name, mipspmu->num_counters); + + return 0; +} +arch_initcall(init_hw_perf_events); + +#endif diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c index 1d8b4d2..d5e7220 100644 --- a/arch/mips/loongson/lemote-2f/irq.c +++ b/arch/mips/loongson/lemote-2f/irq.c @@ -79,7 +79,8 @@ void mach_irq_dispatch(unsigned int pending) if (pending & CAUSEF_IP7) do_IRQ(LOONGSON_TIMER_IRQ); else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */ -#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE) +#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE) \ + || defined(CONFIG_HW_PERF_EVENTS) do_IRQ(LOONGSON2_PERFCNT_IRQ); #endif bonito_irqdispatch(); -- 1.7.0 From wuzhangjin@gmail.com Wed Apr 28 17:45:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 17:45:40 +0200 (CEST) Received: from fg-out-1718.google.com ([72.14.220.154]:29497 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492549Ab0D1Ppe (ORCPT ); Wed, 28 Apr 2010 17:45:34 +0200 Received: by fg-out-1718.google.com with SMTP id e12so1910453fga.6 for ; Wed, 28 Apr 2010 08:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=paUDiRkyc4+40o5+sTvZGgbdonxLHpJHcpfJGKC/uAI=; b=neqzIQIXw+QiL/cOYfwmz07bPMev9DxwWD/jcaFsYmhGBFTXz8TvkX3a2SlgeiaAPj KfIlb6DUA7/zxIFyEBFte6qKm+dnmT+gbYDYdwt+C4Fhp3/T29YTWjli1qBQbPYAvgUH KmN9Xgo9yWjuVQu0llq63wLuw+YJ7Vp6CtyLU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=vnPkgZNgHV8D6ztTteIN9xJ6cBc0JQsQKsR6V6nZmT0Zemmz/+QKcZ5RRoK0upBk0y HrB6BURA6k0YrlGwqwfW45kk2LKfNkcedezXyOvh6Bx7gNXzGrx1HKKhEDTWK3JbB53f +9duJVM9PyiRYBEl5A4vLakpGpHGwu8AGviG8= Received: by 10.87.74.15 with SMTP id b15mr8228554fgl.11.1272469532577; Wed, 28 Apr 2010 08:45:32 -0700 (PDT) Received: from [192.168.2.210] ([202.201.14.140]) by mx.google.com with ESMTPS id e11sm8933135fga.18.2010.04.28.08.45.28 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 28 Apr 2010 08:45:30 -0700 (PDT) Subject: Re: [PATCH] mips/traps: use CKSEG1ADDR for uncache handler From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Sebastian Andrzej Siewior Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <20100427205330.GA1390@Chamillionaire.breakpoint.cc> References: <20100427205330.GA1390@Chamillionaire.breakpoint.cc> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 28 Apr 2010 23:45:22 +0800 Message-ID: <1272469522.26380.15.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26497 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2010-04-27 at 22:53 +0200, Sebastian Andrzej Siewior wrote: > since "MIPS: Calculate proper ebase value for 64-bit kernels" my mips > toy did not boot anymore. > Before that commit we always touched xkphys/shared as ebase and computed > xphsys/unchached for that area. After that commit ebase become 32bit > compat address and convert does not work anymore. So I guess now want to > touch the 32bit compat unmapped & uncached area for this. CKSEG1ADDR > does just in 32bit and 64bit. > Just tested it in 32bit and 64bit kernel on my YeeLoong netbook, both of them work well. BTW: there is another patch[1] sent to this mailing list Yesterday, differ from your method, it tries to provide a TO_UNCAC() for 32bit kernel, but seems yours is lighter. [1] http://patchwork.linux-mips.org/project/linux-mips/list/ [1/2] MIPS: Fixup and cleanup of TO_PHYS(), TO_CAC(), TO_UNCAC() http://patchwork.linux-mips.org/patch/1146/ [2/2] MIPS: Cleanup of set_uncached_handler() http://patchwork.linux-mips.org/patch/1147/ Regards, Wu Zhangjin > Signed-off-by: Sebastian Andrzej Siewior > --- > arch/mips/kernel/traps.c | 7 +------ > 1 files changed, 1 insertions(+), 6 deletions(-) > > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index 4e00f9b..1b57f18 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -1557,12 +1557,7 @@ static char panic_null_cerr[] __cpuinitdata = > void __cpuinit set_uncached_handler(unsigned long offset, void *addr, > unsigned long size) > { > -#ifdef CONFIG_32BIT > - unsigned long uncached_ebase = KSEG1ADDR(ebase); > -#endif > -#ifdef CONFIG_64BIT > - unsigned long uncached_ebase = TO_UNCAC(ebase); > -#endif > + unsigned long uncached_ebase = CKSEG1ADDR(ebase); > > if (!addr) > panic(panic_null_cerr); From ralf@linux-mips.org Wed Apr 28 17:54:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 17:54:46 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44049 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492572Ab0D1Pyl (ORCPT ); Wed, 28 Apr 2010 17:54:41 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3SFseCF022601; Wed, 28 Apr 2010 16:54:40 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3SFsdoA022599; Wed, 28 Apr 2010 16:54:39 +0100 Date: Wed, 28 Apr 2010 16:54:39 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS Subject: Re: use bootmem in platform code on MIPS Message-ID: <20100428155439.GA19468@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26498 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 27, 2010 at 02:14:32PM +0200, Manuel Lauss wrote: > I'd like to use bootmem to reserve large chunks of RAM (at a particular physical > address; for Au1200 MAE, CIM and framebuffer, and later Au1300 OpenGL block) > but it seems that it can't be done: Doing __alloc_bootmem() in > plat_mem_setup() is > too early, while an arch_initcall() is too late because by then the > slab allocator is > already up and handing out random addresses and/or refusing allocations larger > than a few MBytes. The maximum is actually configurable. CONFIG_FORCE_MAX_ZONEORDER defaults to 11 which means with 4kB pages you get 8MB maximum allocation - more for larger pages. CONFIG_FORCE_MAX_ZONEORDER is a tradeoff though. A smaller value will give slightly better performance and safe a bit of memory but I can't really quantify these numbers - I assume it's a small difference. It may actually be preferable to never tell the bootmem allocator about the memory you need for these devices that is bypass the mm code entirely. > Is there another callback I could use which would allow me to use bootmem (short > of abusing plat_smp_setup)? > > Would a separate callback like this be an acceptable solution? Certainly better than using plat_smp_setup which would require enabling SMP support for no good reason at all. I know we will eventually have to add another platform hooks to run after bootmem_init. The name of plat_mem_setup() already shows what this hook originally was meant for but it ended up as the everything-and-the-kitchen- sink hook for platform-specific early initialization. I just dislike conditional hooks. Let's add a call to a new hook function and fix whatever breaks or think about what other hooks needs there should be. Ralf From manuel.lauss@googlemail.com Wed Apr 28 18:28:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 18:28:55 +0200 (CEST) Received: from mail-fx0-f49.google.com ([209.85.161.49]:57800 "EHLO mail-fx0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492052Ab0D1Q2w convert rfc822-to-8bit (ORCPT ); Wed, 28 Apr 2010 18:28:52 +0200 Received: by fxm17 with SMTP id 17so583762fxm.36 for ; Wed, 28 Apr 2010 09:28:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Ouys47hPXaT1rhuQPbyKaHeT4L/3PPgWchffNiYzp0M=; b=dzpNiov7b0pgdqmsCb6J2TOv3a7HyZikOkzTL8jSHPO0PhA0cVs7OqylCwN0n7vRWh zdzRRbvzCi8p/ZdYkkL4i/+sobhZpQLc/w0mvpfMvYyXreXPUqKGzDEgATRysXPcDCzu 41vRIm7bRYPh1HXDh6SA2PcYpslLr9vc52yJo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=uXTCinJoNHK5nd/U9K6cnuWRRCsXL6r3sdQDZB1fDFrK5P3q/TMPyMaHgTT0UWhaKF d9okCHaggWUxhWoYXGOFpXyjurTVlTh0hWxuWdfv6Wx2RkqNpM2eIj7h7vZ//PhL3zWx TpgcMtE434yqiM6nqMCFVVzArOyNJEGK7fVAk= MIME-Version: 1.0 Received: by 10.223.99.78 with SMTP id t14mr420292fan.85.1272472125755; Wed, 28 Apr 2010 09:28:45 -0700 (PDT) Received: by 10.223.106.12 with HTTP; Wed, 28 Apr 2010 09:28:45 -0700 (PDT) In-Reply-To: <20100428155439.GA19468@linux-mips.org> References: <20100428155439.GA19468@linux-mips.org> Date: Wed, 28 Apr 2010 18:28:45 +0200 Message-ID: Subject: Re: use bootmem in platform code on MIPS From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26499 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Wed, Apr 28, 2010 at 5:54 PM, Ralf Baechle wrote: > On Tue, Apr 27, 2010 at 02:14:32PM +0200, Manuel Lauss wrote: > >> I'd like to use bootmem to reserve large chunks of RAM (at a particular physical >> address; for Au1200 MAE, CIM and framebuffer, and later Au1300 OpenGL block) >> but it seems that it can't be done:  Doing __alloc_bootmem() in >> plat_mem_setup() is >> too early, while an arch_initcall() is too late because by then the >> slab allocator is >> already up and handing out random addresses and/or refusing allocations larger >> than a few MBytes. > > The maximum is actually configurable.  CONFIG_FORCE_MAX_ZONEORDER defaults > to 11 which means with 4kB pages you get 8MB maximum allocation - more for > larger pages. I already had to modify it for large display resolutions. > CONFIG_FORCE_MAX_ZONEORDER is a tradeoff though.  A smaller value will give > slightly better performance and safe a bit of memory but I can't really > quantify these numbers - I assume it's a small difference. > > It may actually be preferable to never tell the bootmem allocator about the > memory you need for these devices that is bypass the mm code entirely. Do you mean by not adding the whole RAM area with add_memory_region()? Can I give the memory back later (if it's not required)? Right now I think with bootmem that is actually possible. >> Is there another callback I could use which would allow me to use bootmem (short >> of abusing plat_smp_setup)? >> >> Would a separate callback like this be an acceptable solution? > > Certainly better than using plat_smp_setup which would require enabling > SMP support for no good reason at all. > > I know we will eventually have to add another platform hooks to run after > bootmem_init.  The name of plat_mem_setup() already shows what this hook > originally was meant for but it ended up as the everything-and-the-kitchen- > sink hook for platform-specific early initialization.  I just dislike The comment above arch_mem_init() too mentions a separate function. > conditional hooks.  Let's add a call to a new hook function and fix whatever > breaks or think about what other hooks needs there should be. Okay, I'll cook something up. Thank you, Manuel Lauss From ralf@linux-mips.org Wed Apr 28 20:31:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 20:31:49 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40399 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492160Ab0D1Sbq (ORCPT ); Wed, 28 Apr 2010 20:31:46 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3SIVjkw006340; Wed, 28 Apr 2010 19:31:45 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3SIViYS006335; Wed, 28 Apr 2010 19:31:44 +0100 Date: Wed, 28 Apr 2010 19:31:43 +0100 From: Ralf Baechle To: Yury Polyanskiy Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] die() does not call die notifier chain Message-ID: <20100428183143.GA5623@linux-mips.org> References: <20100426005310.0786273f@penta.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100426005310.0786273f@penta.localdomain> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26500 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 26, 2010 at 12:53:10AM -0400, Yury Polyanskiy wrote: Yuri, > I think that the arch/mips implementation of die() forgets to call the > notify_die() and thus notifiers registered via register_die_notifier() > are not called. > > For example this results in kgdb not being activated on exceptions. > > The patch is very simple and attached: the only subtlety is that main > notify_die declares regs argument w/o const, so I needed to remove const > from mips die() as well. I'd have prefered to make all users of the reg pointer const in the hope gcc can use that for optimization and to avoid stupid assignments via that pointer but that turns out a significant problem on its own so I'm applying your patch as is. Please include a Signed-off-by: line (see Documentation/SubmittingPatches) in future patches. If your patch was any more complex than this I'd not have considered it without one. Thanks! Ralf From David.Daney@caviumnetworks.com Wed Apr 28 20:59:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 20:59:31 +0200 (CEST) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:10786 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492160Ab0D1S71 (ORCPT ); Wed, 28 Apr 2010 20:59:27 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by smtp2.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 28 Apr 2010 14:58:21 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 11:59:06 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 11:59:06 -0700 Message-ID: <4BD88575.1030505@caviumnetworks.com> Date: Wed, 28 Apr 2010 11:59:01 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100330 Fedora/3.0.4-1.fc12 Thunderbird/3.0.4 MIME-Version: 1.0 To: Manuel Lauss CC: Ralf Baechle , Linux-MIPS Subject: Re: use bootmem in platform code on MIPS References: <20100428155439.GA19468@linux-mips.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 28 Apr 2010 18:59:06.0619 (UTC) FILETIME=[E0852CB0:01CAE704] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26501 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 04/28/2010 09:28 AM, Manuel Lauss wrote: > On Wed, Apr 28, 2010 at 5:54 PM, Ralf Baechle wrote: >> On Tue, Apr 27, 2010 at 02:14:32PM +0200, Manuel Lauss wrote: >> >>> I'd like to use bootmem to reserve large chunks of RAM (at a particular physical >>> address; for Au1200 MAE, CIM and framebuffer, and later Au1300 OpenGL block) >>> but it seems that it can't be done: Doing __alloc_bootmem() in >>> plat_mem_setup() is >>> too early, while an arch_initcall() is too late because by then the >>> slab allocator is >>> already up and handing out random addresses and/or refusing allocations larger >>> than a few MBytes. >> >> The maximum is actually configurable. CONFIG_FORCE_MAX_ZONEORDER defaults >> to 11 which means with 4kB pages you get 8MB maximum allocation - more for >> larger pages. > > I already had to modify it for large display resolutions. You also have to modify it for huge pages combined with larger pages. I have: config FORCE_MAX_ZONEORDER int "Maximum zone order" range 13 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB default "13" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB range 12 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB default "12" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB range 11 64 default "11" help The kernel memory allocator divides physically contiguous memory blocks into "zones", where each zone is a power of two number of pages. This option selects the largest power of two that the kernel keeps in the memory allocator. If you need to allocate very large blocks of physically contiguous memory, then you may need to increase this value. This config option is actually maximum order plus one. For example, a value of 11 means that the largest free memory block is 2^10 pages. The page size is not necessarily 4KB. Keep this in mind when choosing a value for this option. > > >> CONFIG_FORCE_MAX_ZONEORDER is a tradeoff though. A smaller value will give >> slightly better performance and safe a bit of memory but I can't really >> quantify these numbers - I assume it's a small difference. >> >> It may actually be preferable to never tell the bootmem allocator about the >> memory you need for these devices that is bypass the mm code entirely. > > Do you mean by not adding the whole RAM area with add_memory_region()? > Can I give the memory back later (if it's not required)? Right now I think with > bootmem that is actually possible. > > >>> Is there another callback I could use which would allow me to use bootmem (short >>> of abusing plat_smp_setup)? >>> >>> Would a separate callback like this be an acceptable solution? >> >> Certainly better than using plat_smp_setup which would require enabling >> SMP support for no good reason at all. >> >> I know we will eventually have to add another platform hooks to run after >> bootmem_init. The name of plat_mem_setup() already shows what this hook >> originally was meant for but it ended up as the everything-and-the-kitchen- >> sink hook for platform-specific early initialization. I just dislike > > The comment above arch_mem_init() too mentions a separate function. > > >> conditional hooks. Let's add a call to a new hook function and fix whatever >> breaks or think about what other hooks needs there should be. > > Okay, I'll cook something up. > > Thank you, > Manuel Lauss > > From David.Daney@caviumnetworks.com Wed Apr 28 21:17:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 21:17:27 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9083 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492609Ab0D1TRR (ORCPT ); Wed, 28 Apr 2010 21:17:17 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 28 Apr 2010 12:17:29 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 12:16:27 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 12:16:27 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3SJGNUX004767; Wed, 28 Apr 2010 12:16:23 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3SJGNA3004766; Wed, 28 Apr 2010 12:16:23 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 3/3] MIPS: Check for accesses beyond the end of the PGD. Date: Wed, 28 Apr 2010 12:16:18 -0700 Message-Id: <1272482178-4712-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> References: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 28 Apr 2010 19:16:27.0635 (UTC) FILETIME=[4D039C30:01CAE707] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26502 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips For some combinations of PAGE_SIZE and vmbits, it is possible to have userspace access that are beyond what is covered by the PGD, but within vmbits. Such an access would cause the TLB refill handler to load garbage values for PMD and PTE potentially giving userspace access to parts of the physical address space to which it is not entitled. In the TLB refill hot path, we add a single dsrl instruction so we can check if any bits outside of the range covered by the PGD are set. In the vmalloc side we then separate the bad case from the normal vmalloc case and call tlb_do_page_fault_0 if warranted. This slows us down a bit, but has the benefit of yielding deterministic behavior. Signed-off-by: David Daney --- arch/mips/mm/tlbex.c | 99 +++++++++++++++++++++++++++++++++++++++++++------- 1 files changed, 85 insertions(+), 14 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 61374b2..8c8c6dd 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -31,6 +31,16 @@ #include #include +/* + * TLB load/store/modify handlers. + * + * Only the fastpath gets synthesized at runtime, the slowpath for + * do_page_fault remains normal asm. + */ +extern void tlb_do_page_fault_0(void); +extern void tlb_do_page_fault_1(void); + + static inline int r45k_bvahwbug(void) { /* XXX: We should probe for the presence of this bug, but we don't. */ @@ -83,6 +93,7 @@ enum label_id { label_nopage_tlbm, label_smp_pgtable_change, label_r3000_write_probe_fail, + label_large_segbits_fault, #ifdef CONFIG_HUGETLB_PAGE label_tlb_huge_update, #endif @@ -101,6 +112,7 @@ UASM_L_LA(_nopage_tlbs) UASM_L_LA(_nopage_tlbm) UASM_L_LA(_smp_pgtable_change) UASM_L_LA(_r3000_write_probe_fail) +UASM_L_LA(_large_segbits_fault) #ifdef CONFIG_HUGETLB_PAGE UASM_L_LA(_tlb_huge_update) #endif @@ -157,6 +169,8 @@ static u32 tlb_handler[128] __cpuinitdata; static struct uasm_label labels[128] __cpuinitdata; static struct uasm_reloc relocs[128] __cpuinitdata; +static int check_for_high_segbits __cpuinitdata; + #ifndef CONFIG_MIPS_PGD_C0_CONTEXT /* * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, @@ -532,7 +546,24 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, * The vmalloc handling is not in the hotpath. */ uasm_i_dmfc0(p, tmp, C0_BADVADDR); - uasm_il_bltz(p, r, tmp, label_vmalloc); + + if (check_for_high_segbits) { + /* + * The kernel currently implicitely assumes that the + * MIPS SEGBITS parameter for the processor is + * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never + * allocate virtual addresses outside the maximum + * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But + * that doesn't prevent user code from accessing the + * higher xuseg addresses. Here, we make sure that + * everything but the lower xuseg addresses goes down + * the module_alloc/vmalloc path. + */ + uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); + uasm_il_bnez(p, r, ptr, label_vmalloc); + } else { + uasm_il_bltz(p, r, tmp, label_vmalloc); + } /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ #ifdef CONFIG_MIPS_PGD_C0_CONTEXT @@ -583,28 +614,64 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, #endif } +enum vmalloc64_mode {not_refill, refill}; /* * BVADDR is the faulting address, PTR is scratch. * PTR will hold the pgd for vmalloc. */ static void __cpuinit build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, - unsigned int bvaddr, unsigned int ptr) + unsigned int bvaddr, unsigned int ptr, + enum vmalloc64_mode mode) { long swpd = (long)swapper_pg_dir; + int single_insn_swpd; + int did_vmalloc_branch = 0; + + single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); uasm_l_vmalloc(l, *p); - if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { - uasm_il_b(p, r, label_vmalloc_done); - uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); - } else { - UASM_i_LA_mostly(p, ptr, swpd); - uasm_il_b(p, r, label_vmalloc_done); - if (uasm_in_compat_space_p(swpd)) - uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); - else - uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); + if (mode == refill && check_for_high_segbits) { + if (single_insn_swpd) { + uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); + uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); + did_vmalloc_branch = 1; + /* fall through */ + } else { + uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); + } + } + if (!did_vmalloc_branch) { + if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { + uasm_il_b(p, r, label_vmalloc_done); + uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); + } else { + UASM_i_LA_mostly(p, ptr, swpd); + uasm_il_b(p, r, label_vmalloc_done); + if (uasm_in_compat_space_p(swpd)) + uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); + else + uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); + } + } + if (mode == refill && check_for_high_segbits) { + uasm_l_large_segbits_fault(l, *p); + /* + * We get here if we are an xsseg address, or if we are + * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. + * + * Ignoring xsseg (assume disabled so would generate + * (address errors?), the only remaining possibility + * is the upper xuseg addresses. On processors with + * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these + * addresses would have taken an address error. We try + * to mimic that here by taking a load/istream page + * fault. + */ + UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); + uasm_i_jr(p, ptr); + uasm_i_nop(p); } } @@ -823,7 +890,7 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) #endif #ifdef CONFIG_64BIT - build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); + build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, refill); #endif /* @@ -1300,7 +1367,7 @@ build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, uasm_i_eret(p); /* return from trap */ #ifdef CONFIG_64BIT - build_get_pgd_vmalloc64(p, l, r, tmp, ptr); + build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); #endif } @@ -1524,6 +1591,10 @@ void __cpuinit build_tlb_refill_handler(void) */ static int run_once = 0; +#ifdef CONFIG_64BIT + check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); +#endif + switch (current_cpu_type()) { case CPU_R2000: case CPU_R3000: -- 1.6.6.1 From David.Daney@caviumnetworks.com Wed Apr 28 21:17:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 21:17:52 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9082 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492610Ab0D1TRR (ORCPT ); Wed, 28 Apr 2010 21:17:17 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 28 Apr 2010 12:17:29 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 12:16:27 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 12:16:27 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3SJGMMj004755; Wed, 28 Apr 2010 12:16:23 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3SJGLfc004749; Wed, 28 Apr 2010 12:16:21 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 0/3] Check for accesses beyond end of PGD Date: Wed, 28 Apr 2010 12:16:15 -0700 Message-Id: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 X-OriginalArrivalTime: 28 Apr 2010 19:16:27.0635 (UTC) FILETIME=[4D039C30:01CAE707] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26503 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips In 64-bit kernels a user space access might cause us to try to access PGD elements beyound the end of the PGD, we must check for this and trap it. David Daney (3): MIPS: Add uasm_i_dsrl_safe() and uasm_i_dsll_safe() to uasm. MIPS: Use uasm_i_ds{r,l}l_safe() instead of uasm_i_ds{r,l}l() in tlbex.c MIPS: Check for accesses beyond the end of the PGD. arch/mips/include/asm/uasm.h | 18 ++++++ arch/mips/mm/tlbex.c | 129 ++++++++++++++++++++++++++++++++---------- 2 files changed, 117 insertions(+), 30 deletions(-) From David.Daney@caviumnetworks.com Wed Apr 28 21:18:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 21:18:18 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9084 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492612Ab0D1TRR (ORCPT ); Wed, 28 Apr 2010 21:17:17 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 28 Apr 2010 12:17:29 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 12:16:27 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 12:16:27 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3SJGNZ3004759; Wed, 28 Apr 2010 12:16:23 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3SJGNkI004758; Wed, 28 Apr 2010 12:16:23 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/3] MIPS: Add uasm_i_dsrl_safe() and uasm_i_dsll_safe() to uasm. Date: Wed, 28 Apr 2010 12:16:16 -0700 Message-Id: <1272482178-4712-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> References: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 28 Apr 2010 19:16:27.0635 (UTC) FILETIME=[4D039C30:01CAE707] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26504 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This allows us to clean up the code by not having to explicitly code checks for shift amounts greater than 32. Signed-off-by: David Daney --- arch/mips/include/asm/uasm.h | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 11a8b52..697e40c 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -167,6 +167,24 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ #define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1) #define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3) +static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1, + unsigned int a2, unsigned int a3) +{ + if (a3 < 32) + uasm_i_dsrl(p, a1, a2, a3); + else + uasm_i_dsrl32(p, a1, a2, a3 - 32); +} + +static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, + unsigned int a2, unsigned int a3) +{ + if (a3 < 32) + uasm_i_dsll(p, a1, a2, a3); + else + uasm_i_dsll32(p, a1, a2, a3 - 32); +} + /* Handle relocations. */ struct uasm_reloc { u32 *addr; -- 1.6.6.1 From David.Daney@caviumnetworks.com Wed Apr 28 21:18:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 21:18:42 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9086 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492614Ab0D1TRT (ORCPT ); Wed, 28 Apr 2010 21:17:19 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 28 Apr 2010 12:17:29 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 12:16:27 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 12:16:27 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3SJGNs4004763; Wed, 28 Apr 2010 12:16:23 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3SJGNJB004762; Wed, 28 Apr 2010 12:16:23 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/3] MIPS: Use uasm_i_ds{r,l}l_safe() instead of uasm_i_ds{r,l}l() in tlbex.c Date: Wed, 28 Apr 2010 12:16:17 -0700 Message-Id: <1272482178-4712-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> References: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 28 Apr 2010 19:16:27.0635 (UTC) FILETIME=[4D039C30:01CAE707] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26505 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This makes the code somewhat cleaner while reducing the risk of shift amount overflows when various page table related options are changed. Signed-off-by: David Daney --- arch/mips/mm/tlbex.c | 30 ++++++++++++++---------------- 1 files changed, 14 insertions(+), 16 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index d1f68aa..61374b2 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -408,7 +408,7 @@ static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); } else { #ifdef CONFIG_64BIT_PHYS_ADDR - uasm_i_dsrl(p, reg, reg, ilog2(_PAGE_GLOBAL)); + uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); #else UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); #endif @@ -549,14 +549,14 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, * SMTC uses TCBind value as "CPU" index */ uasm_i_mfc0(p, ptr, C0_TCBIND); - uasm_i_dsrl(p, ptr, ptr, 19); + uasm_i_dsrl_safe(p, ptr, ptr, 19); # else /* * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 * stored in CONTEXT. */ uasm_i_dmfc0(p, ptr, C0_CONTEXT); - uasm_i_dsrl(p, ptr, ptr, 23); + uasm_i_dsrl_safe(p, ptr, ptr, 23); # endif UASM_i_LA_mostly(p, tmp, pgdc); uasm_i_daddu(p, ptr, ptr, tmp); @@ -569,17 +569,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_l_vmalloc_done(l, *p); - if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */ - uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); - else - uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32); + /* get pgd offset in bytes */ + uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ #ifndef __PAGETABLE_PMD_FOLDED uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ - uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ + uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ #endif @@ -720,9 +718,9 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); } else { - uasm_i_dsrl(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ + uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ - uasm_i_dsrl(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ + uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ } UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } else { @@ -793,9 +791,9 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) uasm_i_dmfc0(&p, K0, C0_BADVADDR); uasm_i_dmfc0(&p, K1, C0_ENTRYHI); uasm_i_xor(&p, K0, K0, K1); - uasm_i_dsrl32(&p, K1, K0, 62 - 32); - uasm_i_dsrl(&p, K0, K0, 12 + 1); - uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32); + uasm_i_dsrl_safe(&p, K1, K0, 62); + uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); + uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); uasm_i_or(&p, K0, K0, K1); uasm_il_bnez(&p, &r, K0, label_leave); /* No need for uasm_i_nop */ @@ -1322,9 +1320,9 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_i_dmfc0(&p, K0, C0_BADVADDR); uasm_i_dmfc0(&p, K1, C0_ENTRYHI); uasm_i_xor(&p, K0, K0, K1); - uasm_i_dsrl32(&p, K1, K0, 62 - 32); - uasm_i_dsrl(&p, K0, K0, 12 + 1); - uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32); + uasm_i_dsrl_safe(&p, K1, K0, 62); + uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); + uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); uasm_i_or(&p, K0, K0, K1); uasm_il_bnez(&p, &r, K0, label_leave); /* No need for uasm_i_nop */ -- 1.6.6.1 From Gurumurthy.Gowdar@gmobis.com Wed Apr 28 21:55:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 21:56:00 +0200 (CEST) Received: from anti.mobis.co.kr ([211.217.52.67]:58244 "HELO sniper.mobis.co.kr" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1492218Ab0D1Tzx convert rfc822-to-8bit (ORCPT ); Wed, 28 Apr 2010 21:55:53 +0200 Received: (snipe 21412 invoked by uid 0); 29 Apr 2010 04:55:39 +0900 Received: from gurumurthy.gowdar@gmobis.com with Spamsniper 2.94.22 (Processed in 0.007224 secs); Received: from unknown (HELO msmobiweb.mobis.co.kr) (10.240.100.165) by unknown with SMTP; 29 Apr 2010 04:55:39 +0900 X-RCPTTO: linux-mips@linux-mips.org Received: from mkegmal01.global.mobis.co.kr ([10.240.200.82]) by msmobiweb.mobis.co.kr with Microsoft SMTPSVC(6.0.3790.3959); Thu, 29 Apr 2010 04:55:39 +0900 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: Facing problems U-boot Porting on MIPS32 Au1350 Date: Thu, 29 Apr 2010 04:55:39 +0900 Message-ID: <5858DE952C53A441BDA3408A0524130104CCE0A1@mkegmal01> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Facing problems U-boot Porting on MIPS32 Au1350 Thread-Index: AcrnDMaslQ9rCmqHSRm4/mM5M2aSmw== From: =?iso-8859-1?Q?=A0Gurumurthy_G_M?= To: X-OriginalArrivalTime: 28 Apr 2010 19:55:39.0784 (UTC) FILETIME=[C7011080:01CAE70C] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26506 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Gurumurthy.Gowdar@gmobis.com Precedence: bulk X-list: linux-mips Hi, i have one doubt regarding the configuring and working on serial port. In Free scale processors I used to #define the console write to smc or scc ( mpc8280 uart ports) . But here i don't think console write or console debug messages are configured to UART2 ( Debug Port) of Au1350. If not then how console port UART2 is taken though serial_init will initialize UART2. my concern is how output of printf or puts or debug messages is displayed on MIPS au1350 console( uart2 is debug port). If am right by defining configs/dbau1x00.h it will just initialize the serial port and baud rate. need help if am missing something regarding debug console. Regards, Gurumurthy From manuel.lauss@googlemail.com Wed Apr 28 22:09:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 22:09:23 +0200 (CEST) Received: from mail-bw0-f218.google.com ([209.85.218.218]:47116 "EHLO mail-bw0-f218.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492615Ab0D1UJQ (ORCPT ); Wed, 28 Apr 2010 22:09:16 +0200 Received: by bwz10 with SMTP id 10so13973906bwz.24 for ; Wed, 28 Apr 2010 13:09:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=arDgLzC0SPkfhiB5VOp5jYIsZ1iC9UWxD1qdmHw7sik=; b=Qx0f9Rg3agTHpMd/L/Pv2zFQWGVi0yXuMUieTROXa9KI0GingB1bhgr3cpjdTtCT9D Pv6nGtWec0zUQIdK0Asd+aBWoFkL7jH5jnKK4wZb2wwv7iEQWaj0p+tLS2vpIsDnuESO eZlydrI5PoHZAXYKEu/QBhE2bCjsZ66Ur5Jts= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=VnOVG+sn2nM/qnTTomDz9uF66DSZlX0b4zXOhQr2K1QzS4fSHtNnC9ghhO3sSr0eI1 aRoUhl1E+SE5PzzAnzsPtJPUPS9ylRGSLO2hTJkQNYuimiTExtdKSLkGf7YPPCh+BSql chxUA+QlOuUJdIonpy7uvsIs+a+qCISRl0Ob0= Received: by 10.102.166.8 with SMTP id o8mr4495463mue.13.1272485350000; Wed, 28 Apr 2010 13:09:10 -0700 (PDT) Received: from localhost.localdomain (p5496B2BC.dip.t-dialin.net [84.150.178.188]) by mx.google.com with ESMTPS id j10sm722509muh.58.2010.04.28.13.09.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 28 Apr 2010 13:09:07 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] MIPS: Alchemy: basic Au1300 SoC support Date: Wed, 28 Apr 2010 22:08:47 +0200 Message-Id: <1272485327-7858-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26507 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Add support for the Au1300 SoC: - CPU core detection - New GPIO/Interrupt controller code, - enable DBDMA, video and PSCs for new subtype. Signed-off-by: Manuel Lauss --- I'm submitting this in the hopes of some feedback. The code here adds just interrupt controller support which should be enough to get a new board started. I'm still working on DB1300 support; unfortunately the FPGA's irq multiplexer is extremely problematic: it generates mostly spurious interrupts or refuses to generate any more when poked the wrong way. I've tried to contact Kevin Hickey and other people inside RMI for assistance but got no response in the last 3 months. Please have a look, Thanks! Manuel Lauss arch/mips/alchemy/Kconfig | 9 + arch/mips/alchemy/common/Makefile | 2 + arch/mips/alchemy/common/dbdma.c | 48 ++- arch/mips/alchemy/common/gpioint.c | 462 ++++++++++++++++++++++ arch/mips/alchemy/common/gpiolib-au1300.c | 54 +++ arch/mips/alchemy/common/platform.c | 9 + arch/mips/alchemy/common/power.c | 9 +- arch/mips/alchemy/common/time.c | 1 + arch/mips/include/asm/cpu.h | 8 + arch/mips/include/asm/mach-au1x00/au1000.h | 197 +++++++++- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 ++ arch/mips/include/asm/mach-au1x00/gpio-au1300.h | 215 ++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 4 + arch/mips/kernel/cpu-probe.c | 18 + drivers/i2c/busses/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/video/Kconfig | 17 +- 17 files changed, 1071 insertions(+), 19 deletions(-) create mode 100644 arch/mips/alchemy/common/gpioint.c create mode 100644 arch/mips/alchemy/common/gpiolib-au1300.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1300.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index df3b1a7..0789c55 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -2,6 +2,10 @@ config ALCHEMY_GPIOINT_AU1000 bool +# au1300-style GPIO/INT controller +config ALCHEMY_GPIOINT_AU1300 + bool + # select this in your board config if you don't want to use the gpio # namespace as documented in the manuals. In this case however you need # to create the necessary gpio_* functions in your board code/headers! @@ -155,6 +159,11 @@ config SOC_AU1200 select SOC_AU1X00 select ALCHEMY_GPIOINT_AU1000 +config SOC_AU1300 + bool + select SOC_AU1X00 + select ALCHEMY_GPIOINT_AU1300 + config SOC_AU1X00 bool select 64BIT_PHYS_ADDR diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 06c0e65..b3b7c92 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -9,11 +9,13 @@ obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ sleeper.o dma.o dbdma.o obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o +obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpioint.o # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) ifeq ($(CONFIG_GPIOLIB),y) obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o + obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpiolib-au1300.o endif endif diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index ca0506a..aedb7e5 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -40,8 +40,6 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - /* * The Descriptor Based DMA supports up to 16 channels. * @@ -151,6 +149,47 @@ static dbdev_tab_t dbdev_tab[] = { #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU1300 + { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 }, + { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 }, + { DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 }, + { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, +#endif /* CONFIG_SOC_AU1300 */ + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, @@ -1073,6 +1112,9 @@ static int __init au1xxx_dbdma_init(void) case ALCHEMY_CPU_AU1200: irq_nr = AU1200_DDMA_INT; break; + case ALCHEMY_CPU_AU1300: + irq_nr = AU1300_DDMA_INT; + break; default: return -ENODEV; } @@ -1094,5 +1136,3 @@ static int __init au1xxx_dbdma_init(void) return ret; } subsys_initcall(au1xxx_dbdma_init); - -#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ diff --git a/arch/mips/alchemy/common/gpioint.c b/arch/mips/alchemy/common/gpioint.c new file mode 100644 index 0000000..873b5d7 --- /dev/null +++ b/arch/mips/alchemy/common/gpioint.c @@ -0,0 +1,462 @@ +/* + * gpioint.c - Au1300 GPIO+Interrupt controller support. + * + * Copyright (c) 2009-2010 Manuel Lauss + * + * licensed under the GPLv2. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#if 0 +#define DBG(x...) printk(KERN_INFO "GPIC " x) +#else +#define DBG(x...) +#endif + +static int au1300_gpic_settype(unsigned int irq, unsigned int type); + +/* setup for known onchip sources */ +struct gpic_devint_data { + int irq; /* linux IRQ number */ + int type; /* IRQ_TYPE_ */ + int prio; /* irq priority, 0 highest, 3 lowest */ + int internal; /* internal-only source (no ext. pin)? */ +}; + +struct gpic_devint_data au1300_devints[] __initdata = { + /* multifunction: gpio/device */ + { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + /* au1300 internal-only ints */ + { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, }, + { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { -1, }, /* terminator */ +}; + +struct alchemy_gpic_sysdev { + struct sys_device sysdev; + void __iomem *base; + unsigned long icr[6]; + unsigned long pincfg[128]; +}; + + +/* + * au1300_gpic_modcfg - change PIN configuration. + * @gpio: pin to change (0-based GPIO number from datasheet). + * @clr: clear all bits set in 'clr'. + * @set: set these bits. + * + * modifies a pins' configuration register, bits set in @clr will + * be cleared in the register, bits in @set will be set. + * NOTE: according to the datasheet, this should only be called + * for disabled interrupts! + */ +static inline void au1300_gpic_modcfg(int gpio, unsigned long clr, + unsigned long set) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long l; + + r += gpio * 4; /* offset into pin config array */ + l = __raw_readl(r + AU1300_GPIC_PINCFG); + l &= ~clr; + l |= set; + __raw_writel(l, r + AU1300_GPIC_PINCFG); + wmb(); + + DBG("MODCFG(%03d) %08lx %08lx -> %08lx\n", gpio, clr, set, l); +} + +/* + * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl). + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to the GPIO controller, so its level can either + * be read or set through the generic GPIO functions. + * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1). + * REVISIT: is this function really necessary? + */ +void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio) +{ + au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE); + + DBG("PIN2GPIN(%03d)\n", (int)gpio); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio); + +/* + * au1300_pinfunc_to_dev - assign a pin to the device function. + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to its associated device function; the pin will be + * driven by the device and not through GPIO functions. + */ +void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + r += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, r + AU1300_GPIC_DEVSEL); + wmb(); + + DBG("PIN2DEV(%03d)\n", (int)gpio); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev); + +/* + * au1300_set_irq_priority - set internal priority of IRQ. + * @irq: irq to set priority (linux irq number). + * @p: priority (0 = highest, 3 = lowest). + */ +void au1300_set_irq_priority(unsigned int irq, int p) +{ + irq -= ALCHEMY_GPIC_INT_BASE; + au1300_gpic_modcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p)); +} +EXPORT_SYMBOL_GPL(au1300_set_irq_priority); + +/* + * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers. + * @dchan: dbdma trigger select (0, 1). + * @gpio: pin to assign as trigger. + * + * DBDMA controller has 2 external trigger sources; this function + * assigns a GPIO to the selected trigger. + */ +void au1300_set_dbdma_gpio(int dchan, unsigned int gpio) +{ + unsigned long r; + + if ((dchan >= 0) && (dchan <= 1)) { + r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + r &= ~(0xff << (8 * dchan)); + r |= (gpio & 0x7f) << (8 * dchan); + __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + wmb(); + } +} + +/**********************************************************************/ + +static void gpic_pin_set_idlewake(int gpio, int allow) +{ + au1300_gpic_modcfg(gpio, GPIC_CFG_IDLEWAKE, + allow ? GPIC_CFG_IDLEWAKE : 0); + + DBG("SETIDLEWAKE(%03d) %d\n", gpio, allow); +} + +static void au1300_gpic_mask(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IDIS); + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_unmask(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= ALCHEMY_GPIC_INT_BASE; + + gpic_pin_set_idlewake(irq, 1); + + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IEN); + wmb(); +} + +static void au1300_gpic_maskack(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */ + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_ack(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + wmb(); +} + +static struct irq_chip au1300_gpic = { + .name = "Au1300-GPIOINT", + .ack = au1300_gpic_ack, + .mask = au1300_gpic_mask, + .mask_ack = au1300_gpic_maskack, + .unmask = au1300_gpic_unmask, + .set_type = au1300_gpic_settype, +}; + +#define SICHN(i, h, n) \ + set_irq_chip_and_handler_name(i, &au1300_gpic, h, n) + +static int au1300_gpic_settype(unsigned int irq, unsigned int type) +{ + unsigned long s; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + s = GPIC_CFG_IC_LEVEL_HIGH; + SICHN(irq, handle_level_irq, "highlevel"); + break; + case IRQ_TYPE_LEVEL_LOW: + s = GPIC_CFG_IC_LEVEL_LOW; + SICHN(irq, handle_level_irq, "lowlevel"); + break; + case IRQ_TYPE_EDGE_RISING: + s = GPIC_CFG_IC_EDGE_RISE; + SICHN(irq, handle_edge_irq, "riseedge"); + break; + case IRQ_TYPE_EDGE_FALLING: + s = GPIC_CFG_IC_EDGE_FALL; + SICHN(irq, handle_edge_irq, "falledge"); + break; + case IRQ_TYPE_EDGE_BOTH: + s = GPIC_CFG_IC_EDGE_BOTH; + SICHN(irq, handle_edge_irq, "bothedge"); + break; + case IRQ_TYPE_NONE: + s = GPIC_CFG_IC_OFF; + SICHN(irq, handle_level_irq, "disabled"); + break; + default: + return -EINVAL; + } + + au1300_gpic_modcfg(irq - ALCHEMY_GPIC_INT_BASE, + GPIC_CFG_IC_MASK, s); + + return 0; +} + +static void __init alchemy_gpic_init_irq(struct gpic_devint_data *dints) +{ + int i; + void __iomem *bank_base; + + mips_cpu_irq_init(); + + /* disable & ack all possible on-chip sources */ + for (i = 0; i < 4; i++) { + bank_base = AU1300_GPIC_ADDR + (i * 4); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS); + wmb(); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND); + wmb(); + } + + /* register all possible irq sources, with 2nd highest priority */ + bank_base = AU1300_GPIC_ADDR + AU1300_GPIC_PINCFG; + for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) { + au1300_set_irq_priority(i, 1); + au1300_gpic_settype(i, IRQ_TYPE_NONE); + } + + /* setup known on-chip sources */ + while ((i = dints->irq) != -1) { + au1300_gpic_settype(i, dints->type); + au1300_set_irq_priority(i, dints->prio); + + if (dints->internal) + au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE); + + dints++; + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); +} + +static int alchemy_gpic_suspend(struct sys_device *dev, pm_message_t state) +{ + struct alchemy_gpic_sysdev *icdev = + container_of(dev, struct alchemy_gpic_sysdev, sysdev); + void __iomem *addy; + int i; + + /* save pin configuration */ + addy = icdev->base + AU1300_GPIC_PINCFG; + for (i = 0; i < 128; i++) + icdev->pincfg[i] = __raw_readl(addy + (i << 2)); + + /* save interrupt mask status */ + icdev->icr[0] = __raw_readl(icdev->base + AU1300_GPIC_IEN + 0x0); + icdev->icr[1] = __raw_readl(icdev->base + AU1300_GPIC_IEN + 0x4); + icdev->icr[2] = __raw_readl(icdev->base + AU1300_GPIC_IEN + 0x8); + icdev->icr[3] = __raw_readl(icdev->base + AU1300_GPIC_IEN + 0xc); + + /* misc */ + icdev->icr[4] = __raw_readl(icdev->base + AU1300_GPIC_DMASEL); + wmb(); + + return 0; +} + +static int alchemy_gpic_resume(struct sys_device *dev) +{ + struct alchemy_gpic_sysdev *icdev = + container_of(dev, struct alchemy_gpic_sysdev, sysdev); + void __iomem *addy; + int i; + + /* mask all off first */ + __raw_writel(-1, icdev->base + AU1300_GPIC_IDIS + 0x0); + __raw_writel(-1, icdev->base + AU1300_GPIC_IDIS + 0x4); + __raw_writel(-1, icdev->base + AU1300_GPIC_IDIS + 0x8); + __raw_writel(-1, icdev->base + AU1300_GPIC_IDIS + 0xc); + wmb(); + + /* restore pin configurations */ + addy = icdev->base + AU1300_GPIC_PINCFG; + for (i = 0; i < 128; i++) + __raw_writel(icdev->pincfg[i], addy + (i << 2)); + wmb(); + + __raw_writel(icdev->icr[4], icdev->base + AU1300_GPIC_DMASEL); + wmb(); + + /* restore masks */ + addy = icdev->base + AU1300_GPIC_IEN; + __raw_writel(icdev->icr[0], addy + 0x0); + wmb(); + __raw_writel(icdev->icr[1], addy + 0x4); + wmb(); + __raw_writel(icdev->icr[2], addy + 0x8); + wmb(); + __raw_writel(icdev->icr[3], addy + 0xc); + wmb(); + + return 0; +} + +static struct sysdev_class alchemy_gpic_sysdev_class = { + .name = "gpic", + .suspend = alchemy_gpic_suspend, + .resume = alchemy_gpic_resume, +}; + +static int __init alchemy_gpic_sysdev_init(void) +{ + struct alchemy_gpic_sysdev *icdev; + int err; + + err = sysdev_class_register(&alchemy_gpic_sysdev_class); + if (err) + return err; + + icdev = kzalloc(sizeof(struct alchemy_gpic_sysdev), GFP_KERNEL); + if (!icdev) + return -ENOMEM; + + icdev->base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + + icdev->sysdev.id = -1; + icdev->sysdev.cls = &alchemy_gpic_sysdev_class; + err = sysdev_register(&icdev->sysdev); + if (err) + kfree(icdev); + + return err; +} +device_initcall(alchemy_gpic_sysdev_init); + +/**********************************************************************/ + +void __init arch_init_irq(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + alchemy_gpic_init_irq(&au1300_devints[0]); + break; + default: + panic("Alchemy GPIC: unsupported CPU!\n"); + } +} + +void plat_irq_dispatch(void) +{ + unsigned long c = read_c0_cause(), s = read_c0_status(); + int i; + + DBG("M %08lx S %08lx\n", c, s); + c &= s; + + if (c & CAUSEF_IP7) /* c0 timer */ + i = MIPS_CPU_IRQ_BASE + 7 - ALCHEMY_GPIC_INT_BASE; + else if (c & (CAUSEF_IP2 | CAUSEF_IP3 | CAUSEF_IP4 | CAUSEF_IP5)) { + i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC); + DBG("I %d\n", i); + if (unlikely(i == 127)) + goto spurious; + } else + goto spurious; + + do_IRQ(i + ALCHEMY_GPIC_INT_BASE); + return; +spurious: + spurious_interrupt(); +} diff --git a/arch/mips/alchemy/common/gpiolib-au1300.c b/arch/mips/alchemy/common/gpiolib-au1300.c new file mode 100644 index 0000000..661cc6f --- /dev/null +++ b/arch/mips/alchemy/common/gpiolib-au1300.c @@ -0,0 +1,54 @@ +/* + * Au1300-style GPIO/INT Controller GPIOLIB support + */ + +#include +#include +#include +#include +#include + +#include + +static int _gpic_get(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_get_value(off + AU1300_GPIO_BASE); +} + +static void _gpic_set(struct gpio_chip *chip, unsigned int off, int v) +{ + au1300_gpio_set_value(off + AU1300_GPIO_BASE, v); +} + +static int _gpic_direction_input(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_direction_input(off + AU1300_GPIO_BASE); +} + +static int _gpic_direction_output(struct gpio_chip *chip, unsigned int off, + int v) +{ + return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v); +} + +static int _gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_to_irq(off + AU1300_GPIO_BASE); +} + +static struct gpio_chip au1300_gpiochip = { + .label = "au1300", + .direction_input = _gpic_direction_input, + .direction_output = _gpic_direction_output, + .get = _gpic_get, + .set = _gpic_set, + .to_irq = _gpic_gpio_to_irq, + .base = AU1300_GPIO_BASE, + .ngpio = AU1300_GPIO_NUM, +}; + +static int __init au1300_gpiochip_init(void) +{ + return gpiochip_add(&au1300_gpiochip); +} +arch_initcall(au1300_gpiochip_init); diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 2580e77..6539ca3 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -53,6 +53,11 @@ static struct plat_serial8250_port au1x00_uart_data[] = { #elif defined(CONFIG_SOC_AU1200) PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), +#elif defined(CONFIG_SOC_AU1300) + PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT), + PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT), + PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT), + PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT), #endif #endif /* CONFIG_SERIAL_8250_AU1X00 */ { }, @@ -66,6 +71,7 @@ static struct platform_device au1xx0_uart_device = { }, }; +#ifdef FOR_PLATFORM_C_USB_HOST_INT /* OHCI (USB full speed host controller) */ static struct resource au1xxx_usb_ohci_resources[] = { [0] = { @@ -93,6 +99,7 @@ static struct platform_device au1xxx_usb_ohci_device = { .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), .resource = au1xxx_usb_ohci_resources, }; +#endif /*** AU1100 LCD controller ***/ @@ -412,7 +419,9 @@ void __init au1xxx_override_eth_cfg(unsigned int port, static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, +#ifdef FOR_PLATFORM_C_USB_HOST_INT &au1xxx_usb_ohci_device, +#endif #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 5ef06a1..af249d1 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -54,7 +54,9 @@ static unsigned int sleep_uart0_fifoctl; static unsigned int sleep_uart0_linectl; static unsigned int sleep_uart0_clkdiv; static unsigned int sleep_uart0_enable; +#ifndef CONFIG_SOC_AU1300 static unsigned int sleep_usb[2]; +#endif static unsigned int sleep_sys_clocks[5]; static unsigned int sleep_sys_pinfunc; static unsigned int sleep_static_memctlr[4][3]; @@ -79,7 +81,8 @@ static void save_core_regs(void) au_sync(); #ifndef CONFIG_SOC_AU1200 - /* Shutdown USB host/device. */ +#ifndef CONFIG_SOC_AU1300 /* doesn't apply to Au1300 USB */ +/* Shutdown USB host/device. */ sleep_usb[0] = au_readl(USB_HOST_CONFIG); /* There appears to be some undocumented reset register.... */ @@ -91,7 +94,7 @@ static void save_core_regs(void) sleep_usb[1] = au_readl(USBD_ENABLE); au_writel(0, USBD_ENABLE); au_sync(); - +#endif /* au1300 */ #else /* AU1200 */ /* enable access to OTG mmio so we can save OTG CAP/MUX. @@ -147,9 +150,11 @@ static void restore_core_regs(void) au_sync(); #ifndef CONFIG_SOC_AU1200 +#ifndef CONFIG_SOC_AU1300 /* doesn't apply to Au1300 either */ au_writel(sleep_usb[0], USB_HOST_CONFIG); au_writel(sleep_usb[1], USBD_ENABLE); au_sync(); +#endif #else /* enable accces to OTG memory */ au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 2aecb2f..db82325 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -179,6 +179,7 @@ static int alchemy_m2inttab[] __initdata = { AU1100_RTC_MATCH2_INT, AU1550_RTC_MATCH2_INT, AU1200_RTC_MATCH2_INT, + AU1300_RTC_MATCH2_INT, }; void __init plat_time_init(void) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index a5acda4..acb12f0 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 @@ -121,6 +122,13 @@ #define PRID_REV_BCM6368 0x0030 /* + * These are the PRID's for when 23:16 == PRID_COMP_RMI + */ + +#define PRID_IMP_AU13XX 0x8000 + + +/* * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index a697661..f826db2 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void) #define ALCHEMY_CPU_AU1100 2 #define ALCHEMY_CPU_AU1550 3 #define ALCHEMY_CPU_AU1200 4 +#define ALCHEMY_CPU_AU1300 5 static inline int alchemy_get_cputype(void) { @@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void) case 0x05030000: return ALCHEMY_CPU_AU1200; break; + case 0x800c0000: + return ALCHEMY_CPU_AU1300; + break; } return ALCHEMY_CPU_UNKNOWN; @@ -180,6 +184,68 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) wmb(); } +/* Multifunction pins: Each of these pins can either be assigned to the + * GPIO controller or a on-chip peripheral. + * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to + * assign one of these to either the GPIO controller or the device. + */ +enum au1300_multifunc_pins { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, + AU1300_PIN_WAKE3, + /* external clock sources for PSCs: 4-5 */ + AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* aux clk input for freqgen 3: 10 */ + AU1300_PIN_FG3AUX, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 29-31 */ + AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, +}; + +/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */ +extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio); +extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio); +extern void au1300_set_irq_priority(unsigned int irq, int p); +extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); @@ -194,13 +260,17 @@ void au_sleep(void); /* SOC Interrupt numbers */ - +/* Au1000-style (IC0/1): 2 controllers with 32 sources each */ #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST +/* Au1300-style (GPIC): 1 controller with up to 128 sources */ +#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) +#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + 127) + enum soc_au1000_ints { AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, AU1000_UART0_INT = AU1000_FIRST_INT, @@ -521,6 +591,43 @@ enum soc_au1200_ints { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ +/* Au1300 peripheral interrupt numbers */ +#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) +#define AU1300_UART1_INT (AU1300_FIRST_INT + 17) +#define AU1300_UART2_INT (AU1300_FIRST_INT + 25) +#define AU1300_UART3_INT (AU1300_FIRST_INT + 27) +#define AU1300_SD1_INT (AU1300_FIRST_INT + 32) +#define AU1300_SD2_INT (AU1300_FIRST_INT + 38) +#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) +#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) +#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) +#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) +#define AU1300_NAND_INT (AU1300_FIRST_INT + 62) +#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) +#define AU1300_MMU_INT (AU1300_FIRST_INT + 76) +#define AU1300_MPU_INT (AU1300_FIRST_INT + 77) +#define AU1300_GPU_INT (AU1300_FIRST_INT + 78) +#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) +#define AU1300_TOY_INT (AU1300_FIRST_INT + 80) +#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) +#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) +#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) +#define AU1300_RTC_INT (AU1300_FIRST_INT + 84) +#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) +#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) +#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) +#define AU1300_UART0_INT (AU1300_FIRST_INT + 88) +#define AU1300_SD0_INT (AU1300_FIRST_INT + 89) +#define AU1300_USB_INT (AU1300_FIRST_INT + 90) +#define AU1300_LCD_INT (AU1300_FIRST_INT + 91) +#define AU1300_BSA_INT (AU1300_FIRST_INT + 92) +#define AU1300_MPE_INT (AU1300_FIRST_INT + 93) +#define AU1300_ITE_INT (AU1300_FIRST_INT + 94) +#define AU1300_AES_INT (AU1300_FIRST_INT + 95) +#define AU1300_CIM_INT (AU1300_FIRST_INT + 96) + +/**********************************************************************/ + /* * SDRAM register offsets */ @@ -808,6 +915,46 @@ enum soc_au1200_ints { #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif +/**********************************************************************/ + +#define AU1300_ROM_PHYS_ADDR 0x10000000 +#define AU1300_OTP_PHYS_ADDR 0x10002000 +#define AU1300_UART0_PHYS_ADDR 0x10100000 +#define AU1300_UART1_PHYS_ADDR 0x10101000 +#define AU1300_UART2_PHYS_ADDR 0x10102000 +#define AU1300_UART3_PHYS_ADDR 0x10103000 +#define AU1300_GPIC_PHYS_ADDR 0x10200000 +#define AU1300_AES_PHYS_ADDR 0x10300000 +#define AU1300_GPU_PHYS_ADDR 0x10500000 +#define AU1300_SD0_PHYS_ADDR 0x10600000 +#define AU1300_SD1_PHYS_ADDR 0x10601000 +#define AU1300_SD2_PHYS_ADDR 0x10602000 +#define AU1300_SYS_PHYS_ADDR 0x10900000 +#define AU1300_PSC0_PHYS_ADDR 0x10A00000 +#define AU1300_PSC1_PHYS_ADDR 0x10A01000 +#define AU1300_PSC2_PHYS_ADDR 0x10A02000 +#define AU1300_PSC3_PHYS_ADDR 0x10A03000 +#define AU1300_VSS_PHYS_ADDR 0x11003000 + +#define AU1300_MEM_PHYS_ADDR 0x14000000 +#define AU1300_STATIC_PHYS_ADDR 0x14001000 +#define AU1300_UDMA_PHYS_ADDR 0x14001800 +#define AU1300_DDMA_PHYS_ADDR 0x14002000 +#define AU1300_CIM_PHYS_ADDR 0x14004000 +#define AU1300_MAEITE_PHYS_ADDR 0x14010000 +#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 +#define AU1300_USB_PHYS_ADDR 0x14020000 +#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 +#define AU1300_LCD_PHYS_ADDR 0x15000000 + +#ifdef CONFIG_SOC_AU1300 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL +#endif + +/**********************************************************************/ + /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 @@ -825,14 +972,12 @@ enum soc_au1200_ints { #define MEM_STTIME3 0xB4001034 #define MEM_STADDR3 0xB4001038 -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) #define MEM_STNDCTL 0xB4001100 #define MEM_STSTAT 0xB4001104 #define MEM_STNAND_CMD 0x0 #define MEM_STNAND_ADDR 0x4 #define MEM_STNAND_DATA 0x20 -#endif /* Interrupt Controller register offsets */ @@ -942,6 +1087,52 @@ enum soc_au1200_ints { #define IC1_TESTBIT 0xB1800080 +/* + * Au1300 GPIO+INT controller (GPIC) register offsets and bits + * Registers are 128bits (0x10 bytes), divided into 4 "banks". + */ +#define AU1300_GPIC_PINVAL 0x0000 +#define AU1300_GPIC_PINVALCLR 0x0010 +#define AU1300_GPIC_IPEND 0x0020 +#define AU1300_GPIC_PRIENC 0x0030 +#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ +#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ +#define AU1300_GPIC_DMASEL 0x0060 +#define AU1300_GPIC_DEVSEL 0x0080 +#define AU1300_GPIC_DEVCLR 0x0090 +#define AU1300_GPIC_RSTVAL 0x00a0 +/* pin configuration space. one 32bit register for up to 128 IRQs */ +#define AU1300_GPIC_PINCFG 0x1000 + +#define GPIC_GPIO_TO_BIT(gpio) \ + (1 << ((gpio) & 0x1f)) + +#define GPIC_GPIO_BANKOFF(gpio) \ + (((gpio) >> 5) * 4) + +/* Pin Control bits: who owns the pin, what does it do */ +#define GPIC_CFG_PC_GPIN 0 +#define GPIC_CFG_PC_DEV 1 +#define GPIC_CFG_PC_GPOLOW 2 +#define GPIC_CFG_PC_GPOHIGH 3 +#define GPIC_CFG_PC_MASK 3 + +/* assign pin to MIPS IRQ line */ +#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) +#define GPIC_CFG_IL_MASK (3 << 2) + +/* pin interrupt type setup */ +#define GPIC_CFG_IC_OFF (0 << 4) +#define GPIC_CFG_IC_LEVEL_LOW (1 << 4) +#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) +#define GPIC_CFG_IC_EDGE_FALL (5 << 4) +#define GPIC_CFG_IC_EDGE_RISE (6 << 4) +#define GPIC_CFG_IC_EDGE_BOTH (7 << 4) +#define GPIC_CFG_IC_MASK (7 << 4) + +/* allow interrupt to wake cpu from 'wait' */ +#define GPIC_CFG_IDLEWAKE (1 << 7) + /* Au1000 */ #ifdef CONFIG_SOC_AU1000 diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index c8a553a..17101e1 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -195,6 +195,39 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CIM_SYNC 26 #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU1300 +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_UART2_TX 4 +#define DSCR_CMD0_UART2_RX 5 +#define DSCR_CMD0_UART3_TX 6 +#define DSCR_CMD0_UART3_RX 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 12 +#define DSCR_CMD0_AES_RX 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_SDMS_TX2 24 +#define DSCR_CMD0_SDMS_RX2 25 +#define DSCR_CMD0_CIM_SYNC 26 +#define DSCR_CMD0_UDMA 27 +#define DSCR_CMD0_DMA_REQ0 28 +#define DSCR_CMD0_DMA_REQ1 29 +#endif /* CONFIG_SOC_AU1300 */ + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h new file mode 100644 index 0000000..afdc4d1 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -0,0 +1,215 @@ +/* + * gpio-au1300.h -- GPIO control for Au1300 and compatibles. + * + * Copyright (c) 2009-2010 Manuel Lauss + */ + +#ifndef _GPIO_AU1300_H_ +#define _GPIO_AU1300_H_ + +#include +#include +#include + +#define AU1300_GPIO_BASE 0 +#define AU1300_GPIO_NUM 75 +#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) + +#define AU1300_GPIC_ADDR \ + (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) + +static inline int au1300_gpio_get_value(int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + int bit; + + gpio -= AU1300_GPIO_BASE; + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; +} + +static inline int au1300_gpio_direction_input(int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); + wmb(); + + return 0; +} + +static inline int au1300_gpio_set_value(int gpio, int v) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL + : AU1300_GPIC_PINVALCLR)); + wmb(); + + return 0; +} + +static inline int au1300_gpio_direction_output(int gpio, int v) +{ + /* hw switches to output automatically */ + return au1300_gpio_set_value(gpio, v); +} + +static inline int au1300_gpio_to_irq(int gpio) +{ + return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); +} + +static inline int au1300_irq_to_gpio(int irq) +{ + return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; +} + +static inline int au1300_gpio_is_valid(int gpio) +{ + return ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); +} + +static inline int au1300_gpio_cansleep(int gpio) +{ + return 0; +} + +static inline void alchemy_gpio1_input_enable(void) +{ + __raw_writel(0, (void __iomem *)KSEG1ADDR(AU1300_SYS_PHYS_ADDR) + 0x110); + wmb(); +} + +/* hardware remembers gpio 0-63 levels on powerup */ +static inline int au1300_gpio_getinitlvl(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long v; + + if (unlikely(gpio > 63)) + return 0; + else if (gpio > 31) { + gpio -= 32; + roff += 4; + } + + v = __raw_readl(roff + AU1300_GPIC_RSTVAL); + return (v >> gpio) & 1; +} + +/**********************************************************************/ + +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifndef CONFIG_GPIOLIB + + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(int gpio) +{ + return au1300_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(int gpio, int v) +{ + return au1300_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(int gpio) +{ + return au1300_gpio_get_value(gpio); +} + +static inline void gpio_set_value(int gpio, int v) +{ + au1300_gpio_set_value(gpio, v); +} + +static inline int gpio_is_valid(int gpio) +{ + return au1300_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(int gpio) +{ + return au1300_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(int gpio) +{ + return au1300_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(int irq) +{ + return au1300_irq_to_gpio(irq); +} + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#else /* CONFIG GPIOLIB */ + + +/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */ +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */ + +/* get everything through gpiolib */ +#define gpio_to_irq __gpio_to_irq +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define irq_to_gpio au1300_irq_to_gpio + +#include + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#endif /* !CONFIG_GPIOLIB */ + +#endif /* _GPIO_AU1300_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index c3f60cd..4d6edea 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -5,6 +5,10 @@ #include +#elif defined(CONFIG_ALCHEMY_GPIOINT_AU1300) + +#include + #endif #endif /* _ALCHEMY_GPIO_H_ */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index be5bb16..432eef7 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -826,6 +826,21 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_rmi(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_AU13XX: + c->cputype = CPU_ALCHEMY; + __cpu_name[cpu] = "Au13xx"; + break; + default: + panic("Unknown RMI core!\n"); + break; + } +} + static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); @@ -967,6 +982,9 @@ __cpuinit void cpu_probe(void) case PRID_COMP_NXP: cpu_probe_nxp(c, cpu); break; + case PRID_COMP_RMI: + cpu_probe_rmi(c, cpu); + break; case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 9c6170c..3207d6d 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -297,7 +297,7 @@ config I2C_AT91 config I2C_AU1550 tristate "Au1550/Au1200 SMBus interface" - depends on SOC_AU1550 || SOC_AU1200 + depends on SOC_AU1550 || SOC_AU1200 || SOC_AU1300 help If you say yes to this option, support will be included for the Au1550 and Au1200 SMBus interface. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a191fa2..1d88767 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -68,7 +68,7 @@ config SPI_BFIN config SPI_AU1550 tristate "Au1550/Au12x0 SPI Controller" - depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL + depends on (SOC_AU1550 || SOC_AU1200 || SOC_AU1300) && EXPERIMENTAL select SPI_BITBANG help If you say yes to this option, support will be included for the diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6e16244..5ac6939 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1694,15 +1694,16 @@ config FB_AU1100 au1100fb:panel=. config FB_AU1200 - bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT + bool "Au1200/Au1300 LCD Driver" + depends on (FB = y) && (SOC_AU1200 || SOC_AU1300) + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS help - This is the framebuffer driver for the AMD Au1200 SOC. It can drive - various panels and CRTs by passing in kernel cmd line option - au1200fb:panel=. + This is the framebuffer driver for the AMD Au1200/Au1300 SOCs. + It can drive various panels and CRTs by passing in kernel + cmdline option au1200fb:panel=. source "drivers/video/geode/Kconfig" -- 1.7.0.4 From sebastian@breakpoint.cc Wed Apr 28 22:31:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Apr 2010 22:31:32 +0200 (CEST) Received: from Chamillionaire.breakpoint.cc ([85.10.199.196]:55854 "EHLO Chamillionaire.breakpoint.cc" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S2097167Ab0D1Ub0 (ORCPT ); Wed, 28 Apr 2010 22:31:26 +0200 Received: id: bigeasy by Chamillionaire.breakpoint.cc with local (easymta 1.00 BETA 1) id 1O7Dun-0001GY-SM; Wed, 28 Apr 2010 22:31:25 +0200 Date: Wed, 28 Apr 2010 22:31:25 +0200 From: Sebastian Andrzej Siewior To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [PATCH] mips/swarm: update defconfig Message-ID: <20100428203125.GB4578@Chamillionaire.breakpoint.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline X-Key-Id: FE3F4706 X-Key-Fingerprint: FFDA BBBB 3563 1B27 75C9 925B 98D5 5C1C FE3F 4706 User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26508 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sebastian@breakpoint.cc Precedence: bulk X-list: linux-mips the defconfig is updated from .25: - it no longer contains the platform driver for the IDE controler. It moves now to the PATA layer because it is not deprecated like IDE and works here. - everything not really required is deactivated. This includes IPsec, SCTP, Wireless, ... Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/configs/sb1250-swarm_defconfig | 785 +++++++++++++++++------------- 1 files changed, 439 insertions(+), 346 deletions(-) diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 7f07bf0..d7c82f5 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25 -# Sat May 3 00:38:11 2008 +# Linux kernel version: 2.6.34-rc5 +# Wed Apr 28 22:24:45 2010 # CONFIG_MIPS=y @@ -9,20 +9,25 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_AR7 is not set # CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set -# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set @@ -36,10 +41,13 @@ CONFIG_SIBYTE_SWARM=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set CONFIG_SIBYTE_SB1250=y CONFIG_SIBYTE_SB1xxx_SOC=y # CONFIG_CPU_SB1_PASS_1 is not set @@ -50,14 +58,13 @@ CONFIG_CPU_SB1_PASS_2_2=y # CONFIG_CPU_SB1_PASS_3 is not set CONFIG_SIBYTE_HAS_LDT=y CONFIG_SIBYTE_ENABLE_LDT_IF_PCI=y -# CONFIG_SIMULATION is not set # CONFIG_SB1_CEX_ALWAYS_FATAL is not set # CONFIG_SB1_CERR_STALL is not set -CONFIG_SIBYTE_CFE=y # CONFIG_SIBYTE_CFE_CONSOLE is not set # CONFIG_SIBYTE_BUS_WATCHER is not set # CONFIG_SIBYTE_TBPROF is not set CONFIG_SIBYTE_HAS_ZBUS_PROFILING=y +CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set @@ -68,15 +75,13 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_CEVT_SB1250=y CONFIG_CSRC_SB1250=y CONFIG_CFE=y CONFIG_DMA_COHERENT=y -CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y -# CONFIG_HOTPLUG_CPU is not set # CONFIG_NO_IOPORT is not set CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set @@ -90,7 +95,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -103,6 +109,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -110,6 +117,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set CONFIG_CPU_SB1=y +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_SB1=y CONFIG_WEAK_ORDERING=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y @@ -125,6 +133,7 @@ CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set # CONFIG_SIBYTE_DMA_PAGEOPS is not set CONFIG_CPU_HAS_PREFETCH=y @@ -132,6 +141,7 @@ CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_SB1_PASS_2_WORKAROUNDS=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y @@ -146,12 +156,13 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_SMP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS_DEFAULT_2=y @@ -163,12 +174,12 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set +CONFIG_HZ_250=y # CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y +# CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 +CONFIG_HZ=250 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -177,6 +188,7 @@ CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -193,31 +205,46 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=64 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=15 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set # CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set CONFIG_CPUSETS=y -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set +# CONFIG_PROC_PID_CPUSET is not set CONFIG_CGROUP_CPUACCT=y # CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_PROC_PID_CPUSET is not set CONFIG_RELAY=y CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_IPC_NS is not set # CONFIG_USER_NS is not set # CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y @@ -226,54 +253,91 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -# CONFIG_COMPAT_BRK is not set +# CONFIG_PCSPKR_PLATFORM is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +# CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_SYSCALL_WRAPPERS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y -# CONFIG_BLK_DEV_IO_TRACE is not set CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y +# CONFIG_CFQ_GROUP_IOSCHED is not set # CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_CLASSIC_RCU=y +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -282,7 +346,8 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCI_LEGACY is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set CONFIG_MMU=y CONFIG_ZONE_DMA32=y # CONFIG_PCCARD is not set @@ -292,6 +357,8 @@ CONFIG_ZONE_DMA32=y # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y @@ -304,27 +371,16 @@ CONFIG_BINFMT_ELF32=y # Power management options # CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set - -# -# Networking -# +# CONFIG_PM_RUNTIME is not set CONFIG_NET=y # # Networking options # CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -342,29 +398,26 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_LRO=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -374,8 +427,10 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set -CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set # # Network testing @@ -386,39 +441,9 @@ CONFIG_NET_SCH_FIFO=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -CONFIG_CFG80211=m -CONFIG_NL80211=y -CONFIG_WIRELESS_EXT=y -CONFIG_MAC80211=m - -# -# Rate control algorithm selection -# -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_NONE is not set - -# -# Selecting 'y' for an algorithm will -# - -# -# build the algorithm into mac80211. -# -CONFIG_MAC80211_RC_DEFAULT="pid" -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_MESH is not set -# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set -# CONFIG_MAC80211_DEBUG is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_RFKILL=m +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # @@ -429,9 +454,12 @@ CONFIG_RFKILL=m # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m # CONFIG_MTD is not set @@ -443,6 +471,7 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set @@ -450,96 +479,151 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=9220 # CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set CONFIG_ATA_OVER_ETH=m +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set CONFIG_SGI_IOC4=m # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set -CONFIG_HAVE_IDE=y -CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set # -# Please see Documentation/ide/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -CONFIG_BLK_DEV_IDECD=y -CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y -CONFIG_BLK_DEV_IDETAPE=y -CONFIG_BLK_DEV_IDEFLOPPY=y -# CONFIG_IDE_TASK_IOCTL is not set -CONFIG_IDE_PROC_FS=y +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set # -# IDE chipset support/bugfixes +# SCSI device support # -# CONFIG_IDE_GENERIC is not set -# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y # -# PCI IDE chipsets support -# -# CONFIG_BLK_DEV_GENERIC is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_JMICRON is not set -# CONFIG_BLK_DEV_SC1200 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT8213 is not set -# CONFIG_BLK_DEV_IT821X is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_BLK_DEV_TC86C001 is not set -CONFIG_BLK_DEV_IDE_SWARM=y -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_BLK_DEV_HD_ONLY is not set -# CONFIG_BLK_DEV_HD is not set +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m # -# SCSI device support -# -CONFIG_RAID_ATTRS=m -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_PATA_PLATFORM=y +# CONFIG_PATA_SCH is not set # CONFIG_MD is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -CONFIG_NETDEVICES_MULTIQUEUE=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set -CONFIG_MACVLAN=m +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set @@ -559,32 +643,20 @@ CONFIG_PHYLIB=y CONFIG_BROADCOM_PHY=y # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_NET_PCI is not set -# CONFIG_B44 is not set +# CONFIG_NET_ETHERNET is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set # CONFIG_E1000E is not set -# CONFIG_E1000E_ENABLED is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set +# CONFIG_IGBVF is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -596,49 +668,19 @@ CONFIG_SB1250_MAC=y # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set +# CONFIG_CNIC is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set -CONFIG_NETDEV_10000=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_IXGBE is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_NIU is not set -# CONFIG_MLX4_CORE is not set -# CONFIG_TEHUTI is not set -# CONFIG_BNX2X is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set +# CONFIG_WLAN is not set # -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -# CONFIG_IPW2100 is not set -# CONFIG_IPW2200 is not set -# CONFIG_LIBERTAS is not set -# CONFIG_HERMES is not set -# CONFIG_ATMEL is not set -# CONFIG_PRISM54 is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set -# CONFIG_RTL8180 is not set -# CONFIG_RTL8187 is not set -# CONFIG_ADM8211 is not set -# CONFIG_P54_COMMON is not set -# CONFIG_ATH5K is not set -# CONFIG_IWLCORE is not set -# CONFIG_IWLWIFI_LEDS is not set -# CONFIG_IWL4965 is not set -# CONFIG_IWL3945 is not set -# CONFIG_HOSTAP is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -# CONFIG_ZD1211RW is not set -# CONFIG_RT2X00 is not set +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # # USB Network Adapters @@ -648,37 +690,61 @@ CONFIG_WLAN_80211=y # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_NET_FC is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set # # Input device support # -# CONFIG_INPUT is not set +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Hardware I/O ports # -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m +# CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set # # Character devices # -# CONFIG_VT is not set +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set @@ -695,51 +761,51 @@ CONFIG_SERIAL_SB1250_DUART_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set +# CONFIG_SPI is not set # -# SPI support +# PPS support # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +# CONFIG_PPS is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_DAB is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_LPC_SCH is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support # +# CONFIG_VGA_ARB is not set # CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set @@ -752,9 +818,12 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_DISPLAY_SUPPORT is not set # -# Sound +# Console display driver support # +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -769,15 +838,23 @@ CONFIG_USB=y CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_PERSIST is not set # CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set # CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set @@ -785,27 +862,32 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # -# may also be needed; see USB_STORAGE Help for more information +# also be needed; see USB_STORAGE Help for more info # +# CONFIG_USB_STORAGE is not set # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set -CONFIG_USB_MON=y +# CONFIG_USB_MICROTEK is not set # # USB port drivers @@ -818,15 +900,13 @@ CONFIG_USB_MON=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set @@ -834,29 +914,45 @@ CONFIG_USB_MON=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set # -# Userspace I/O +# TI VLYNQ # -# CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # -CONFIG_EXT2_FS=y +CONFIG_EXT2_FS=m CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set @@ -864,16 +960,25 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m +# CONFIG_FUSE_FS is not set CONFIG_GENERIC_ACL=y # +# Caches +# +# CONFIG_FSCACHE is not set + +# # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set @@ -892,47 +997,28 @@ CONFIG_GENERIC_ACL=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -943,99 +1029,106 @@ CONFIG_SUNRPC=y # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_NLS is not set -CONFIG_DLM=m -# CONFIG_DLM_DEBUG is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set +CONFIG_PRINTK_TIME=y CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 # CONFIG_MAGIC_SYSRQ is not set +CONFIG_STRIP_ASM_SYMS=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y # CONFIG_CMDLINE_BOOL is not set # CONFIG_SB1XXX_CORELIS is not set # # Security options # -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_KEYS is not set # CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_BLKCIPHER=m -CONFIG_CRYPTO_SEQIV=m -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_LZO=m -# CONFIG_CRYPTO_HW is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # -CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set -CONFIG_CRC16=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y +# CONFIG_CRC32 is not set # CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_LZO_COMPRESS=m -CONFIG_LZO_DECOMPRESS=m -CONFIG_PLIST=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.6.1 From ralf@linux-mips.org Thu Apr 29 02:52:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 29 Apr 2010 02:52:50 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35677 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491037Ab0D2Awq (ORCPT ); Thu, 29 Apr 2010 02:52:46 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3T0qdj9002362; Thu, 29 Apr 2010 01:52:39 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3T0qbDk002360; Thu, 29 Apr 2010 01:52:37 +0100 Date: Thu, 29 Apr 2010 01:52:36 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] MIPS: Add uasm_i_dsrl_safe() and uasm_i_dsll_safe() to uasm. Message-ID: <20100429005234.GA1704@linux-mips.org> References: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> <1272482178-4712-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1272482178-4712-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26509 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 28, 2010 at 12:16:16PM -0700, David Daney wrote: > This allows us to clean up the code by not having to explicitly code > checks for shift amounts greater than 32. Thanks, applied. Ralf From ralf@linux-mips.org Thu Apr 29 03:13:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 29 Apr 2010 03:13:31 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60888 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491037Ab0D2BN2 (ORCPT ); Thu, 29 Apr 2010 03:13:28 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3T1DLmK002973; Thu, 29 Apr 2010 02:13:21 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3T1DITe002971; Thu, 29 Apr 2010 02:13:18 +0100 Date: Thu, 29 Apr 2010 02:13:17 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/3] MIPS: Use uasm_i_ds{r,l}l_safe() instead of uasm_i_ds{r,l}l() in tlbex.c Message-ID: <20100429011317.GB1704@linux-mips.org> References: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> <1272482178-4712-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1272482178-4712-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26510 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 28, 2010 at 12:16:17PM -0700, David Daney wrote: > This makes the code somewhat cleaner while reducing the risk of shift > amount overflows when various page table related options are changed. Applied. Thanks! Ralf From ralf@linux-mips.org Thu Apr 29 03:24:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 29 Apr 2010 03:24:21 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56565 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492731Ab0D2BYR (ORCPT ); Thu, 29 Apr 2010 03:24:17 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3T1OFE4003312; Thu, 29 Apr 2010 02:24:15 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3T1OEdF003310; Thu, 29 Apr 2010 02:24:14 +0100 Date: Thu, 29 Apr 2010 02:24:13 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/3] MIPS: Check for accesses beyond the end of the PGD. Message-ID: <20100429012413.GA3151@linux-mips.org> References: <1272482178-4712-1-git-send-email-ddaney@caviumnetworks.com> <1272482178-4712-4-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1272482178-4712-4-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26511 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 28, 2010 at 12:16:18PM -0700, David Daney wrote: Thanks, applied as well. Ralf From David.Daney@caviumnetworks.com Thu Apr 29 03:52:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 29 Apr 2010 03:52:14 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15661 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491166Ab0D2BwK (ORCPT ); Thu, 29 Apr 2010 03:52:10 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 28 Apr 2010 18:52:22 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 18:52:06 -0700 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Apr 2010 18:52:06 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.3) with ESMTP id o3T1q2rl001969; Wed, 28 Apr 2010 18:52:02 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o3T1q1RV001968; Wed, 28 Apr 2010 18:52:01 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Remove leftover declarations. Date: Wed, 28 Apr 2010 18:51:59 -0700 Message-Id: <1272505919-1932-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 X-OriginalArrivalTime: 29 Apr 2010 01:52:06.0650 (UTC) FILETIME=[9291D5A0:01CAE73E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26512 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/mm/tlbex.c | 9 --------- 1 files changed, 0 insertions(+), 9 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 5121a5b..e981277 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1003,15 +1003,6 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) } /* - * TLB load/store/modify handlers. - * - * Only the fastpath gets synthesized at runtime, the slowpath for - * do_page_fault remains normal asm. - */ -extern void tlb_do_page_fault_0(void); -extern void tlb_do_page_fault_1(void); - -/* * 128 instructions for the fastpath handler is generous and should * never be exceeded. */ -- 1.6.6.1 From ralf@linux-mips.org Thu Apr 29 04:13:37 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 29 Apr 2010 04:13:41 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46132 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490966Ab0D2CNg (ORCPT ); Thu, 29 Apr 2010 04:13:36 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o3T2DSNq004657; Thu, 29 Apr 2010 03:13:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o3T2DQUl004655; Thu, 29 Apr 2010 03:13:26 +0100 Date: Thu, 29 Apr 2010 03:13:25 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Remove leftover declarations. Message-ID: <20100429021323.GA32586@linux-mips.org> References: <1272505919-1932-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1272505919-1932-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26513 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 28, 2010 at 06:51:59PM -0700, David Daney wrote: Thanks, applied. Ralf From dengcheng.zhu@gmail.com Thu Apr 29 05:30:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 29 Apr 2010 05:30:11 +0200 (CEST) Received: from mail-gy0-f177.google.com ([209.85.160.177]:41476 "EHLO mail-gy0-f177.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490969Ab0D2DaH convert rfc822-to-8bit (ORCPT ); Thu, 29 Apr 2010 05:30:07 +0200 Received: by gyb11 with SMTP id 11so7823196gyb.36 for ; Wed, 28 Apr 2010 20:30:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=5sVHpaFvDyDd6bGSYtOV5jdKHIf8gWA3MmPCnC6b4jQ=; b=xsaZ7RzHGYWEp7p0qrsrRIDnDz08qtDQEIcNwUmmnTDmxXfsS90efaRRV6ZVkXwYx5 nF104g8CyyTc0Rb2jgmi8sJONNEp+O7Kkiz4y6Ct5OaOvBlj7f8gNbzmPQUivJ8gvNpG jBoJURSiyeY4NnhaSGVbmCv2MKwlkfOEVVy08= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=jVMlM/5yLNMNR4PqIj6X52ozgK7zWyiMkDrvXqV67kV/t4a/jeu7tU96nnymIBRQr0 TUVLeDlCTyFAl3hJOTP8ysdaetk/ZuyGoAnGIVpHA1+DyBF7KDAxNUAS8VUd9i38yuXU TBGhJsW1G3pAes1AqaXWJ7VIKY+bWEbHDdZVA= MIME-Version: 1.0 Received: by 10.150.118.14 with SMTP id q14mr995843ybc.291.1272511800013; Wed, 28 Apr 2010 20:30:00 -0700 (PDT) Received: by 10.150.122.11 with HTTP; Wed, 28 Apr 2010 20:29:59 -0700 (PDT) In-Reply-To: <1272468077-12292-1-git-send-email-wuzhangjin@gmail.com> References: <1272468077-12292-1-git-send-email-wuzhangjin@gmail.com> Date: Thu, 29 Apr 2010 11:29:59 +0800 Message-ID: Subject: Re: [PATCH] Loongson2: add a primary perf support (not applicable) From: Deng-Cheng Zhu To: Wu Zhangjin Cc: loongson-dev , linux-mips@linux-mips.org, ralf@linux-mips.org, Zhang Le , yajin Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26514 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dengcheng.zhu@gmail.com Precedence: bulk X-list: linux-mips > And then you need to compile the user-space tools/perf with the following steps > if want to local-compile it: And if you want to cross compile it, besides changing tools/perf/perf.h, tools/perf/Makefile also needs to have proper CFLAGS/LDFLAGS for headers and libs. Then it's OK to fire "make CROSS_COMPILE=$toolchain_prefix". > Currently, seems "./perf record" and lots of software events not work, anybody > have interest in playing with it can refer to {tools/perf/Documentation, > arch/mips/kernel/perf_event*, arch/mips/include/asm/pmu.h, > arch/x86/kernel/cpu/perf_event*, arch/arm/kernel/perf_event* ...}. "perf record" works fine on 24K/34K/74K cores. In addition, If you are seeing the message "Couldn't record kernel reference relocation symbol", and your kernel symbols only have _stext (without _text), then search "_text" in builtin-record.c and replace with "_stext". Here is the link: http://lkml.org/lkml/2010/1/18/177 For software events, it should be able to work without specific changes for loongson, I suppose. Because changes have been done to common MIPS code to support software events. >  config HW_PERF_EVENTS >        bool "Enable hardware performance counter support for perf events" > -       depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32 > +       depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n >        default y >        help >          Enable hardware performance counter support for perf events. If How about adding CPU_LOONGSON2* instead of deleting CPU_MIPS32? Because we want the perf functionality to be available when we are able to choose it.. From wuzhangjin@gmail.com Thu Apr 29 06:10:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 29 Apr 2010 06:10:32 +0200 (CEST) Received: from mail-gw0-f49.google.com ([74.125.83.49]:62789 "EHLO mail-gw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491070Ab0D2EK3 (ORCPT ); Thu, 29 Apr 2010 06:10:29 +0200 Received: by gwb1 with SMTP id 1so1617817gwb.36 for ; Wed, 28 Apr 2010 21:10:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=IhCsiiKJ05RN0cDEMZaohgaG3HpfFJOruHf+MvGA/T4=; b=FrGZ8CJ1M72/eS3jNpM10inuv7ldKJxG7e1edLbzJq8nHIbqlHK7/sQb43zrMM0teR ezo7/Csz2Wn4bZ6WmThcDZNRiWnRv4Fua8wBz5TGHF+Sx8fRPd4yfr1qS7frX/wGxSf3 fA1x7ey6l41Gk/gn77VSl/lywDPmbt8eGGWOM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=mqN54XRC6BF/bPGB+SOuYIuYsOG5MaIauHDdKp29PyrvfSy/pLcxlesawYvKY24ftF ozr4Q9yAM10zz+Rf5N0eCaAcx82L7IZt9OOotB65sZ+DI98TGSfJzXYkcorbw6RBwed2 zOLVWsJc/DewBNpMVbVhRQI3h12orD/zK6bu0= Received: by 10.150.159.11 with SMTP id h11mr118241ybe.62.1272514222989; Wed, 28 Apr 2010 21:10:22 -0700 (PDT) Received: from [192.168.2.218] ([202.201.14.140]) by mx.google.com with ESMTPS id 16sm298603gxk.5.2010.04.28.21.10.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 28 Apr 2010 21:10:21 -0700 (PDT) Subject: Re: [PATCH] Loongson2: add a primary perf support (not applicable) From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Deng-Cheng Zhu Cc: loongson-dev , linux-mips@linux-mips.org, ralf@linux-mips.org, Zhang Le , yajin In-Reply-To: References: <1272468077-12292-1-git-send-email-wuzhangjin@gmail.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 29 Apr 2010 12:10:12 +0800 Message-ID: <1272514212.24709.18.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 26515 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-o